Tatsuya Hiruma
gg
Dependencies: mbed MPU6050 RateLimiter test Math
X_NUCLEO_IHM07M1/x_nucleo_ihm07m1_targets.h@8:7efca5258efb, 2020-03-06 (annotated)
- Committer:
- 18fmr36
- Date:
- Fri Mar 06 05:58:45 2020 +0000
- Revision:
- 8:7efca5258efb
gg
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| 18fmr36 | 8:7efca5258efb | 1 | /* mbed Microcontroller Library |
| 18fmr36 | 8:7efca5258efb | 2 | * Copyright (c) 2006-2016 ARM Limited |
| 18fmr36 | 8:7efca5258efb | 3 | * |
| 18fmr36 | 8:7efca5258efb | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 18fmr36 | 8:7efca5258efb | 5 | * you may not use this file except in compliance with the License. |
| 18fmr36 | 8:7efca5258efb | 6 | * You may obtain a copy of the License at |
| 18fmr36 | 8:7efca5258efb | 7 | * |
| 18fmr36 | 8:7efca5258efb | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 18fmr36 | 8:7efca5258efb | 9 | * |
| 18fmr36 | 8:7efca5258efb | 10 | * Unless required by applicable law or agreed to in writing, software |
| 18fmr36 | 8:7efca5258efb | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 18fmr36 | 8:7efca5258efb | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 18fmr36 | 8:7efca5258efb | 13 | * See the License for the specific language governing permissions and |
| 18fmr36 | 8:7efca5258efb | 14 | * limitations under the License. |
| 18fmr36 | 8:7efca5258efb | 15 | */ |
| 18fmr36 | 8:7efca5258efb | 16 | |
| 18fmr36 | 8:7efca5258efb | 17 | /** |
| 18fmr36 | 8:7efca5258efb | 18 | ****************************************************************************** |
| 18fmr36 | 8:7efca5258efb | 19 | * @file x_nucleo_ihm07m1_targets.h |
| 18fmr36 | 8:7efca5258efb | 20 | * @author STMicroelectronics |
| 18fmr36 | 8:7efca5258efb | 21 | * @brief Header file with pin definitions for X-NUCLEO-IHM07M1 board |
| 18fmr36 | 8:7efca5258efb | 22 | ****************************************************************************** |
| 18fmr36 | 8:7efca5258efb | 23 | * @copy |
| 18fmr36 | 8:7efca5258efb | 24 | * |
| 18fmr36 | 8:7efca5258efb | 25 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
| 18fmr36 | 8:7efca5258efb | 26 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE |
| 18fmr36 | 8:7efca5258efb | 27 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY |
| 18fmr36 | 8:7efca5258efb | 28 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING |
| 18fmr36 | 8:7efca5258efb | 29 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE |
| 18fmr36 | 8:7efca5258efb | 30 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
| 18fmr36 | 8:7efca5258efb | 31 | * |
| 18fmr36 | 8:7efca5258efb | 32 | * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> |
| 18fmr36 | 8:7efca5258efb | 33 | */ |
| 18fmr36 | 8:7efca5258efb | 34 | |
| 18fmr36 | 8:7efca5258efb | 35 | /* Define to prevent from recursive inclusion --------------------------------*/ |
| 18fmr36 | 8:7efca5258efb | 36 | #ifndef __X_NUCLEO_IHM07M1_TARGETS_H_ |
| 18fmr36 | 8:7efca5258efb | 37 | #define __X_NUCLEO_IHM07M1_TARGETS_H_ |
| 18fmr36 | 8:7efca5258efb | 38 | |
| 18fmr36 | 8:7efca5258efb | 39 | // Default pin configuration for X-NUCLEO-IHM07M1 with STM32 Nucleo-64 boards |
| 18fmr36 | 8:7efca5258efb | 40 | |
| 18fmr36 | 8:7efca5258efb | 41 | // Logic input pins |
| 18fmr36 | 8:7efca5258efb | 42 | #define P_IN1 PA_8 |
| 18fmr36 | 8:7efca5258efb | 43 | #define P_IN2 PA_9 |
| 18fmr36 | 8:7efca5258efb | 44 | #define P_IN3 PA_10 |
| 18fmr36 | 8:7efca5258efb | 45 | |
| 18fmr36 | 8:7efca5258efb | 46 | // Enable channel pins |
| 18fmr36 | 8:7efca5258efb | 47 | //#define P_EN1 PC_10 //IHM07 |
| 18fmr36 | 8:7efca5258efb | 48 | //#define P_EN2 PC_11 |
| 18fmr36 | 8:7efca5258efb | 49 | //#define P_EN3 PC_12 |
| 18fmr36 | 8:7efca5258efb | 50 | |
| 18fmr36 | 8:7efca5258efb | 51 | #define P_EN1 PA_7 //IHM08 |
| 18fmr36 | 8:7efca5258efb | 52 | #define P_EN2 PB_0 |
| 18fmr36 | 8:7efca5258efb | 53 | #define P_EN3 PB_1 |
| 18fmr36 | 8:7efca5258efb | 54 | |
| 18fmr36 | 8:7efca5258efb | 55 | // Hall sensors pins |
| 18fmr36 | 8:7efca5258efb | 56 | #define P_HALL1 PA_15 |
| 18fmr36 | 8:7efca5258efb | 57 | #define P_HALL2 PB_3 |
| 18fmr36 | 8:7efca5258efb | 58 | #define P_HALL3 PB_10 |
| 18fmr36 | 8:7efca5258efb | 59 | |
| 18fmr36 | 8:7efca5258efb | 60 | // Temperature pin |
| 18fmr36 | 8:7efca5258efb | 61 | #define P_TEMP PC_2 |
| 18fmr36 | 8:7efca5258efb | 62 | |
| 18fmr36 | 8:7efca5258efb | 63 | // Fault LED |
| 18fmr36 | 8:7efca5258efb | 64 | #define P_FAULT PB_2 |
| 18fmr36 | 8:7efca5258efb | 65 | |
| 18fmr36 | 8:7efca5258efb | 66 | // Speed potentiometer |
| 18fmr36 | 8:7efca5258efb | 67 | //#define P_SPEED PB_1 //IHM07 |
| 18fmr36 | 8:7efca5258efb | 68 | #define P_SPEED PA_4 //IHM |
| 18fmr36 | 8:7efca5258efb | 69 | |
| 18fmr36 | 8:7efca5258efb | 70 | // Back EMF pins |
| 18fmr36 | 8:7efca5258efb | 71 | //#define P_BEMF1 PC_3 //IHM07 |
| 18fmr36 | 8:7efca5258efb | 72 | //#define P_BEMF2 PB_0 |
| 18fmr36 | 8:7efca5258efb | 73 | //#define P_BEMF3 PA_7 |
| 18fmr36 | 8:7efca5258efb | 74 | |
| 18fmr36 | 8:7efca5258efb | 75 | #define P_BEMF1 PC_3 //IHM08 |
| 18fmr36 | 8:7efca5258efb | 76 | #define P_BEMF2 PC_4 |
| 18fmr36 | 8:7efca5258efb | 77 | #define P_BEMF3 PC_5 |
| 18fmr36 | 8:7efca5258efb | 78 | |
| 18fmr36 | 8:7efca5258efb | 79 | // Current pins |
| 18fmr36 | 8:7efca5258efb | 80 | #define P_CURR1 PA_0 |
| 18fmr36 | 8:7efca5258efb | 81 | #define P_CURR2 PC_1 |
| 18fmr36 | 8:7efca5258efb | 82 | #define P_CURR3 PC_0 |
| 18fmr36 | 8:7efca5258efb | 83 | |
| 18fmr36 | 8:7efca5258efb | 84 | // Voltage bus pin |
| 18fmr36 | 8:7efca5258efb | 85 | #define P_VBUS PA_1 |
| 18fmr36 | 8:7efca5258efb | 86 | |
| 18fmr36 | 8:7efca5258efb | 87 | #endif // __X_NUCLEO_IHM07M1_TARGETS_H_ |