Projet
Dependents: DISCO-F746NG_Scope_copy
Fork of BSP_DISCO_F746NG by
n25q128a.h@1:ee089790cdbb, 2016-01-04 (annotated)
- Committer:
- bcostm
- Date:
- Mon Jan 04 15:19:15 2016 +0000
- Revision:
- 1:ee089790cdbb
Add missing files
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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bcostm | 1:ee089790cdbb | 1 | /** |
bcostm | 1:ee089790cdbb | 2 | ****************************************************************************** |
bcostm | 1:ee089790cdbb | 3 | * @file n25q128a.h |
bcostm | 1:ee089790cdbb | 4 | * @author MCD Application Team |
bcostm | 1:ee089790cdbb | 5 | * @version V1.0.0 |
bcostm | 1:ee089790cdbb | 6 | * @date 29-May-2015 |
bcostm | 1:ee089790cdbb | 7 | * @brief This file contains all the description of the N25Q128A QSPI memory. |
bcostm | 1:ee089790cdbb | 8 | ****************************************************************************** |
bcostm | 1:ee089790cdbb | 9 | * @attention |
bcostm | 1:ee089790cdbb | 10 | * |
bcostm | 1:ee089790cdbb | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
bcostm | 1:ee089790cdbb | 12 | * |
bcostm | 1:ee089790cdbb | 13 | * Redistribution and use in source and binary forms, with or without modification, |
bcostm | 1:ee089790cdbb | 14 | * are permitted provided that the following conditions are met: |
bcostm | 1:ee089790cdbb | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
bcostm | 1:ee089790cdbb | 16 | * this list of conditions and the following disclaimer. |
bcostm | 1:ee089790cdbb | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
bcostm | 1:ee089790cdbb | 18 | * this list of conditions and the following disclaimer in the documentation |
bcostm | 1:ee089790cdbb | 19 | * and/or other materials provided with the distribution. |
bcostm | 1:ee089790cdbb | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
bcostm | 1:ee089790cdbb | 21 | * may be used to endorse or promote products derived from this software |
bcostm | 1:ee089790cdbb | 22 | * without specific prior written permission. |
bcostm | 1:ee089790cdbb | 23 | * |
bcostm | 1:ee089790cdbb | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
bcostm | 1:ee089790cdbb | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
bcostm | 1:ee089790cdbb | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
bcostm | 1:ee089790cdbb | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
bcostm | 1:ee089790cdbb | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
bcostm | 1:ee089790cdbb | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
bcostm | 1:ee089790cdbb | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
bcostm | 1:ee089790cdbb | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
bcostm | 1:ee089790cdbb | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
bcostm | 1:ee089790cdbb | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
bcostm | 1:ee089790cdbb | 34 | * |
bcostm | 1:ee089790cdbb | 35 | ****************************************************************************** |
bcostm | 1:ee089790cdbb | 36 | */ |
bcostm | 1:ee089790cdbb | 37 | |
bcostm | 1:ee089790cdbb | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
bcostm | 1:ee089790cdbb | 39 | #ifndef __N25Q128A_H |
bcostm | 1:ee089790cdbb | 40 | #define __N25Q128A_H |
bcostm | 1:ee089790cdbb | 41 | |
bcostm | 1:ee089790cdbb | 42 | #ifdef __cplusplus |
bcostm | 1:ee089790cdbb | 43 | extern "C" { |
bcostm | 1:ee089790cdbb | 44 | #endif |
bcostm | 1:ee089790cdbb | 45 | |
bcostm | 1:ee089790cdbb | 46 | /* Includes ------------------------------------------------------------------*/ |
bcostm | 1:ee089790cdbb | 47 | |
bcostm | 1:ee089790cdbb | 48 | /** @addtogroup BSP |
bcostm | 1:ee089790cdbb | 49 | * @{ |
bcostm | 1:ee089790cdbb | 50 | */ |
bcostm | 1:ee089790cdbb | 51 | |
bcostm | 1:ee089790cdbb | 52 | /** @addtogroup Components |
bcostm | 1:ee089790cdbb | 53 | * @{ |
bcostm | 1:ee089790cdbb | 54 | */ |
bcostm | 1:ee089790cdbb | 55 | |
bcostm | 1:ee089790cdbb | 56 | /** @addtogroup n25q128a |
bcostm | 1:ee089790cdbb | 57 | * @{ |
bcostm | 1:ee089790cdbb | 58 | */ |
bcostm | 1:ee089790cdbb | 59 | |
bcostm | 1:ee089790cdbb | 60 | /** @defgroup N25Q128A_Exported_Types |
bcostm | 1:ee089790cdbb | 61 | * @{ |
bcostm | 1:ee089790cdbb | 62 | */ |
bcostm | 1:ee089790cdbb | 63 | |
bcostm | 1:ee089790cdbb | 64 | /** |
bcostm | 1:ee089790cdbb | 65 | * @} |
bcostm | 1:ee089790cdbb | 66 | */ |
bcostm | 1:ee089790cdbb | 67 | |
bcostm | 1:ee089790cdbb | 68 | /** @defgroup N25Q128A_Exported_Constants |
bcostm | 1:ee089790cdbb | 69 | * @{ |
bcostm | 1:ee089790cdbb | 70 | */ |
bcostm | 1:ee089790cdbb | 71 | |
bcostm | 1:ee089790cdbb | 72 | /** |
bcostm | 1:ee089790cdbb | 73 | * @brief N25Q128A Configuration |
bcostm | 1:ee089790cdbb | 74 | */ |
bcostm | 1:ee089790cdbb | 75 | #define N25Q128A_FLASH_SIZE 0x1000000 /* 128 MBits => 16MBytes */ |
bcostm | 1:ee089790cdbb | 76 | #define N25Q128A_SECTOR_SIZE 0x10000 /* 256 sectors of 64KBytes */ |
bcostm | 1:ee089790cdbb | 77 | #define N25Q128A_SUBSECTOR_SIZE 0x1000 /* 4096 subsectors of 4kBytes */ |
bcostm | 1:ee089790cdbb | 78 | #define N25Q128A_PAGE_SIZE 0x100 /* 65536 pages of 256 bytes */ |
bcostm | 1:ee089790cdbb | 79 | |
bcostm | 1:ee089790cdbb | 80 | #define N25Q128A_DUMMY_CYCLES_READ 8 |
bcostm | 1:ee089790cdbb | 81 | #define N25Q128A_DUMMY_CYCLES_READ_QUAD 10 |
bcostm | 1:ee089790cdbb | 82 | |
bcostm | 1:ee089790cdbb | 83 | #define N25Q128A_BULK_ERASE_MAX_TIME 250000 |
bcostm | 1:ee089790cdbb | 84 | #define N25Q128A_SECTOR_ERASE_MAX_TIME 3000 |
bcostm | 1:ee089790cdbb | 85 | #define N25Q128A_SUBSECTOR_ERASE_MAX_TIME 800 |
bcostm | 1:ee089790cdbb | 86 | |
bcostm | 1:ee089790cdbb | 87 | /** |
bcostm | 1:ee089790cdbb | 88 | * @brief N25Q128A Commands |
bcostm | 1:ee089790cdbb | 89 | */ |
bcostm | 1:ee089790cdbb | 90 | /* Reset Operations */ |
bcostm | 1:ee089790cdbb | 91 | #define RESET_ENABLE_CMD 0x66 |
bcostm | 1:ee089790cdbb | 92 | #define RESET_MEMORY_CMD 0x99 |
bcostm | 1:ee089790cdbb | 93 | |
bcostm | 1:ee089790cdbb | 94 | /* Identification Operations */ |
bcostm | 1:ee089790cdbb | 95 | #define READ_ID_CMD 0x9E |
bcostm | 1:ee089790cdbb | 96 | #define READ_ID_CMD2 0x9F |
bcostm | 1:ee089790cdbb | 97 | #define MULTIPLE_IO_READ_ID_CMD 0xAF |
bcostm | 1:ee089790cdbb | 98 | #define READ_SERIAL_FLASH_DISCO_PARAM_CMD 0x5A |
bcostm | 1:ee089790cdbb | 99 | |
bcostm | 1:ee089790cdbb | 100 | /* Read Operations */ |
bcostm | 1:ee089790cdbb | 101 | #define READ_CMD 0x03 |
bcostm | 1:ee089790cdbb | 102 | #define FAST_READ_CMD 0x0B |
bcostm | 1:ee089790cdbb | 103 | #define DUAL_OUT_FAST_READ_CMD 0x3B |
bcostm | 1:ee089790cdbb | 104 | #define DUAL_INOUT_FAST_READ_CMD 0xBB |
bcostm | 1:ee089790cdbb | 105 | #define QUAD_OUT_FAST_READ_CMD 0x6B |
bcostm | 1:ee089790cdbb | 106 | #define QUAD_INOUT_FAST_READ_CMD 0xEB |
bcostm | 1:ee089790cdbb | 107 | |
bcostm | 1:ee089790cdbb | 108 | /* Write Operations */ |
bcostm | 1:ee089790cdbb | 109 | #define WRITE_ENABLE_CMD 0x06 |
bcostm | 1:ee089790cdbb | 110 | #define WRITE_DISABLE_CMD 0x04 |
bcostm | 1:ee089790cdbb | 111 | |
bcostm | 1:ee089790cdbb | 112 | /* Register Operations */ |
bcostm | 1:ee089790cdbb | 113 | #define READ_STATUS_REG_CMD 0x05 |
bcostm | 1:ee089790cdbb | 114 | #define WRITE_STATUS_REG_CMD 0x01 |
bcostm | 1:ee089790cdbb | 115 | |
bcostm | 1:ee089790cdbb | 116 | #define READ_LOCK_REG_CMD 0xE8 |
bcostm | 1:ee089790cdbb | 117 | #define WRITE_LOCK_REG_CMD 0xE5 |
bcostm | 1:ee089790cdbb | 118 | |
bcostm | 1:ee089790cdbb | 119 | #define READ_FLAG_STATUS_REG_CMD 0x70 |
bcostm | 1:ee089790cdbb | 120 | #define CLEAR_FLAG_STATUS_REG_CMD 0x50 |
bcostm | 1:ee089790cdbb | 121 | |
bcostm | 1:ee089790cdbb | 122 | #define READ_NONVOL_CFG_REG_CMD 0xB5 |
bcostm | 1:ee089790cdbb | 123 | #define WRITE_NONVOL_CFG_REG_CMD 0xB1 |
bcostm | 1:ee089790cdbb | 124 | |
bcostm | 1:ee089790cdbb | 125 | #define READ_VOL_CFG_REG_CMD 0x85 |
bcostm | 1:ee089790cdbb | 126 | #define WRITE_VOL_CFG_REG_CMD 0x81 |
bcostm | 1:ee089790cdbb | 127 | |
bcostm | 1:ee089790cdbb | 128 | #define READ_ENHANCED_VOL_CFG_REG_CMD 0x65 |
bcostm | 1:ee089790cdbb | 129 | #define WRITE_ENHANCED_VOL_CFG_REG_CMD 0x61 |
bcostm | 1:ee089790cdbb | 130 | |
bcostm | 1:ee089790cdbb | 131 | /* Program Operations */ |
bcostm | 1:ee089790cdbb | 132 | #define PAGE_PROG_CMD 0x02 |
bcostm | 1:ee089790cdbb | 133 | #define DUAL_IN_FAST_PROG_CMD 0xA2 |
bcostm | 1:ee089790cdbb | 134 | #define EXT_DUAL_IN_FAST_PROG_CMD 0xD2 |
bcostm | 1:ee089790cdbb | 135 | #define QUAD_IN_FAST_PROG_CMD 0x32 |
bcostm | 1:ee089790cdbb | 136 | #define EXT_QUAD_IN_FAST_PROG_CMD 0x12 |
bcostm | 1:ee089790cdbb | 137 | |
bcostm | 1:ee089790cdbb | 138 | /* Erase Operations */ |
bcostm | 1:ee089790cdbb | 139 | #define SUBSECTOR_ERASE_CMD 0x20 |
bcostm | 1:ee089790cdbb | 140 | #define SECTOR_ERASE_CMD 0xD8 |
bcostm | 1:ee089790cdbb | 141 | #define BULK_ERASE_CMD 0xC7 |
bcostm | 1:ee089790cdbb | 142 | |
bcostm | 1:ee089790cdbb | 143 | #define PROG_ERASE_RESUME_CMD 0x7A |
bcostm | 1:ee089790cdbb | 144 | #define PROG_ERASE_SUSPEND_CMD 0x75 |
bcostm | 1:ee089790cdbb | 145 | |
bcostm | 1:ee089790cdbb | 146 | /* One-Time Programmable Operations */ |
bcostm | 1:ee089790cdbb | 147 | #define READ_OTP_ARRAY_CMD 0x4B |
bcostm | 1:ee089790cdbb | 148 | #define PROG_OTP_ARRAY_CMD 0x42 |
bcostm | 1:ee089790cdbb | 149 | |
bcostm | 1:ee089790cdbb | 150 | /** |
bcostm | 1:ee089790cdbb | 151 | * @brief N25Q128A Registers |
bcostm | 1:ee089790cdbb | 152 | */ |
bcostm | 1:ee089790cdbb | 153 | /* Status Register */ |
bcostm | 1:ee089790cdbb | 154 | #define N25Q128A_SR_WIP ((uint8_t)0x01) /*!< Write in progress */ |
bcostm | 1:ee089790cdbb | 155 | #define N25Q128A_SR_WREN ((uint8_t)0x02) /*!< Write enable latch */ |
bcostm | 1:ee089790cdbb | 156 | #define N25Q128A_SR_BLOCKPR ((uint8_t)0x5C) /*!< Block protected against program and erase operations */ |
bcostm | 1:ee089790cdbb | 157 | #define N25Q128A_SR_PRBOTTOM ((uint8_t)0x20) /*!< Protected memory area defined by BLOCKPR starts from top or bottom */ |
bcostm | 1:ee089790cdbb | 158 | #define N25Q128A_SR_SRWREN ((uint8_t)0x80) /*!< Status register write enable/disable */ |
bcostm | 1:ee089790cdbb | 159 | |
bcostm | 1:ee089790cdbb | 160 | /* Nonvolatile Configuration Register */ |
bcostm | 1:ee089790cdbb | 161 | #define N25Q128A_NVCR_LOCK ((uint16_t)0x0001) /*!< Lock nonvolatile configuration register */ |
bcostm | 1:ee089790cdbb | 162 | #define N25Q128A_NVCR_DUAL ((uint16_t)0x0004) /*!< Dual I/O protocol */ |
bcostm | 1:ee089790cdbb | 163 | #define N25Q128A_NVCR_QUAB ((uint16_t)0x0008) /*!< Quad I/O protocol */ |
bcostm | 1:ee089790cdbb | 164 | #define N25Q128A_NVCR_RH ((uint16_t)0x0010) /*!< Reset/hold */ |
bcostm | 1:ee089790cdbb | 165 | #define N25Q128A_NVCR_ODS ((uint16_t)0x01C0) /*!< Output driver strength */ |
bcostm | 1:ee089790cdbb | 166 | #define N25Q128A_NVCR_XIP ((uint16_t)0x0E00) /*!< XIP mode at power-on reset */ |
bcostm | 1:ee089790cdbb | 167 | #define N25Q128A_NVCR_NB_DUMMY ((uint16_t)0xF000) /*!< Number of dummy clock cycles */ |
bcostm | 1:ee089790cdbb | 168 | |
bcostm | 1:ee089790cdbb | 169 | /* Volatile Configuration Register */ |
bcostm | 1:ee089790cdbb | 170 | #define N25Q128A_VCR_WRAP ((uint8_t)0x03) /*!< Wrap */ |
bcostm | 1:ee089790cdbb | 171 | #define N25Q128A_VCR_XIP ((uint8_t)0x08) /*!< XIP */ |
bcostm | 1:ee089790cdbb | 172 | #define N25Q128A_VCR_NB_DUMMY ((uint8_t)0xF0) /*!< Number of dummy clock cycles */ |
bcostm | 1:ee089790cdbb | 173 | |
bcostm | 1:ee089790cdbb | 174 | /* Enhanced Volatile Configuration Register */ |
bcostm | 1:ee089790cdbb | 175 | #define N25Q128A_EVCR_ODS ((uint8_t)0x07) /*!< Output driver strength */ |
bcostm | 1:ee089790cdbb | 176 | #define N25Q128A_EVCR_VPPA ((uint8_t)0x08) /*!< Vpp accelerator */ |
bcostm | 1:ee089790cdbb | 177 | #define N25Q128A_EVCR_RH ((uint8_t)0x10) /*!< Reset/hold */ |
bcostm | 1:ee089790cdbb | 178 | #define N25Q128A_EVCR_DUAL ((uint8_t)0x40) /*!< Dual I/O protocol */ |
bcostm | 1:ee089790cdbb | 179 | #define N25Q128A_EVCR_QUAD ((uint8_t)0x80) /*!< Quad I/O protocol */ |
bcostm | 1:ee089790cdbb | 180 | |
bcostm | 1:ee089790cdbb | 181 | /* Flag Status Register */ |
bcostm | 1:ee089790cdbb | 182 | #define N25Q128A_FSR_PRERR ((uint8_t)0x02) /*!< Protection error */ |
bcostm | 1:ee089790cdbb | 183 | #define N25Q128A_FSR_PGSUS ((uint8_t)0x04) /*!< Program operation suspended */ |
bcostm | 1:ee089790cdbb | 184 | #define N25Q128A_FSR_VPPERR ((uint8_t)0x08) /*!< Invalid voltage during program or erase */ |
bcostm | 1:ee089790cdbb | 185 | #define N25Q128A_FSR_PGERR ((uint8_t)0x10) /*!< Program error */ |
bcostm | 1:ee089790cdbb | 186 | #define N25Q128A_FSR_ERERR ((uint8_t)0x20) /*!< Erase error */ |
bcostm | 1:ee089790cdbb | 187 | #define N25Q128A_FSR_ERSUS ((uint8_t)0x40) /*!< Erase operation suspended */ |
bcostm | 1:ee089790cdbb | 188 | #define N25Q128A_FSR_READY ((uint8_t)0x80) /*!< Ready or command in progress */ |
bcostm | 1:ee089790cdbb | 189 | |
bcostm | 1:ee089790cdbb | 190 | /** |
bcostm | 1:ee089790cdbb | 191 | * @} |
bcostm | 1:ee089790cdbb | 192 | */ |
bcostm | 1:ee089790cdbb | 193 | |
bcostm | 1:ee089790cdbb | 194 | /** @defgroup N25Q128A_Exported_Functions |
bcostm | 1:ee089790cdbb | 195 | * @{ |
bcostm | 1:ee089790cdbb | 196 | */ |
bcostm | 1:ee089790cdbb | 197 | /** |
bcostm | 1:ee089790cdbb | 198 | * @} |
bcostm | 1:ee089790cdbb | 199 | */ |
bcostm | 1:ee089790cdbb | 200 | |
bcostm | 1:ee089790cdbb | 201 | /** |
bcostm | 1:ee089790cdbb | 202 | * @} |
bcostm | 1:ee089790cdbb | 203 | */ |
bcostm | 1:ee089790cdbb | 204 | |
bcostm | 1:ee089790cdbb | 205 | /** |
bcostm | 1:ee089790cdbb | 206 | * @} |
bcostm | 1:ee089790cdbb | 207 | */ |
bcostm | 1:ee089790cdbb | 208 | |
bcostm | 1:ee089790cdbb | 209 | /** |
bcostm | 1:ee089790cdbb | 210 | * @} |
bcostm | 1:ee089790cdbb | 211 | */ |
bcostm | 1:ee089790cdbb | 212 | |
bcostm | 1:ee089790cdbb | 213 | #ifdef __cplusplus |
bcostm | 1:ee089790cdbb | 214 | } |
bcostm | 1:ee089790cdbb | 215 | #endif |
bcostm | 1:ee089790cdbb | 216 | |
bcostm | 1:ee089790cdbb | 217 | #endif /* __N25Q128A_H */ |
bcostm | 1:ee089790cdbb | 218 | |
bcostm | 1:ee089790cdbb | 219 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |