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wm8994.c@1:ee089790cdbb, 2016-01-04 (annotated)

Committer:
bcostm
Date:
Mon Jan 04 15:19:15 2016 +0000
Revision:
1:ee089790cdbb
Add missing files

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bcostm 1:ee089790cdbb 1 /**
bcostm 1:ee089790cdbb 2 ******************************************************************************
bcostm 1:ee089790cdbb 3 * @file wm8994.c
bcostm 1:ee089790cdbb 4 * @author MCD Application Team
bcostm 1:ee089790cdbb 5 * @version V2.0.0
bcostm 1:ee089790cdbb 6 * @date 24-June-2015
bcostm 1:ee089790cdbb 7 * @brief This file provides the WM8994 Audio Codec driver.
bcostm 1:ee089790cdbb 8 ******************************************************************************
bcostm 1:ee089790cdbb 9 * @attention
bcostm 1:ee089790cdbb 10 *
bcostm 1:ee089790cdbb 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bcostm 1:ee089790cdbb 12 *
bcostm 1:ee089790cdbb 13 * Redistribution and use in source and binary forms, with or without modification,
bcostm 1:ee089790cdbb 14 * are permitted provided that the following conditions are met:
bcostm 1:ee089790cdbb 15 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 1:ee089790cdbb 16 * this list of conditions and the following disclaimer.
bcostm 1:ee089790cdbb 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 1:ee089790cdbb 18 * this list of conditions and the following disclaimer in the documentation
bcostm 1:ee089790cdbb 19 * and/or other materials provided with the distribution.
bcostm 1:ee089790cdbb 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 1:ee089790cdbb 21 * may be used to endorse or promote products derived from this software
bcostm 1:ee089790cdbb 22 * without specific prior written permission.
bcostm 1:ee089790cdbb 23 *
bcostm 1:ee089790cdbb 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 1:ee089790cdbb 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 1:ee089790cdbb 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 1:ee089790cdbb 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 1:ee089790cdbb 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 1:ee089790cdbb 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 1:ee089790cdbb 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 1:ee089790cdbb 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 1:ee089790cdbb 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 1:ee089790cdbb 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 1:ee089790cdbb 34 *
bcostm 1:ee089790cdbb 35 ******************************************************************************
bcostm 1:ee089790cdbb 36 */
bcostm 1:ee089790cdbb 37
bcostm 1:ee089790cdbb 38 /* Includes ------------------------------------------------------------------*/
bcostm 1:ee089790cdbb 39 #include "wm8994.h"
bcostm 1:ee089790cdbb 40
bcostm 1:ee089790cdbb 41 /** @addtogroup BSP
bcostm 1:ee089790cdbb 42 * @{
bcostm 1:ee089790cdbb 43 */
bcostm 1:ee089790cdbb 44
bcostm 1:ee089790cdbb 45 /** @addtogroup Components
bcostm 1:ee089790cdbb 46 * @{
bcostm 1:ee089790cdbb 47 */
bcostm 1:ee089790cdbb 48
bcostm 1:ee089790cdbb 49 /** @addtogroup wm8994
bcostm 1:ee089790cdbb 50 * @brief This file provides a set of functions needed to drive the
bcostm 1:ee089790cdbb 51 * WM8994 audio codec.
bcostm 1:ee089790cdbb 52 * @{
bcostm 1:ee089790cdbb 53 */
bcostm 1:ee089790cdbb 54
bcostm 1:ee089790cdbb 55 /** @defgroup WM8994_Private_Types
bcostm 1:ee089790cdbb 56 * @{
bcostm 1:ee089790cdbb 57 */
bcostm 1:ee089790cdbb 58
bcostm 1:ee089790cdbb 59 /**
bcostm 1:ee089790cdbb 60 * @}
bcostm 1:ee089790cdbb 61 */
bcostm 1:ee089790cdbb 62
bcostm 1:ee089790cdbb 63 /** @defgroup WM8994_Private_Defines
bcostm 1:ee089790cdbb 64 * @{
bcostm 1:ee089790cdbb 65 */
bcostm 1:ee089790cdbb 66 /* Uncomment this line to enable verifying data sent to codec after each write
bcostm 1:ee089790cdbb 67 operation (for debug purpose) */
bcostm 1:ee089790cdbb 68 #if !defined (VERIFY_WRITTENDATA)
bcostm 1:ee089790cdbb 69 /* #define VERIFY_WRITTENDATA */
bcostm 1:ee089790cdbb 70 #endif /* VERIFY_WRITTENDATA */
bcostm 1:ee089790cdbb 71 /**
bcostm 1:ee089790cdbb 72 * @}
bcostm 1:ee089790cdbb 73 */
bcostm 1:ee089790cdbb 74
bcostm 1:ee089790cdbb 75 /** @defgroup WM8994_Private_Macros
bcostm 1:ee089790cdbb 76 * @{
bcostm 1:ee089790cdbb 77 */
bcostm 1:ee089790cdbb 78
bcostm 1:ee089790cdbb 79 /**
bcostm 1:ee089790cdbb 80 * @}
bcostm 1:ee089790cdbb 81 */
bcostm 1:ee089790cdbb 82
bcostm 1:ee089790cdbb 83 /** @defgroup WM8994_Private_Variables
bcostm 1:ee089790cdbb 84 * @{
bcostm 1:ee089790cdbb 85 */
bcostm 1:ee089790cdbb 86
bcostm 1:ee089790cdbb 87 /* Audio codec driver structure initialization */
bcostm 1:ee089790cdbb 88 AUDIO_DrvTypeDef wm8994_drv =
bcostm 1:ee089790cdbb 89 {
bcostm 1:ee089790cdbb 90 wm8994_Init,
bcostm 1:ee089790cdbb 91 wm8994_DeInit,
bcostm 1:ee089790cdbb 92 wm8994_ReadID,
bcostm 1:ee089790cdbb 93
bcostm 1:ee089790cdbb 94 wm8994_Play,
bcostm 1:ee089790cdbb 95 wm8994_Pause,
bcostm 1:ee089790cdbb 96 wm8994_Resume,
bcostm 1:ee089790cdbb 97 wm8994_Stop,
bcostm 1:ee089790cdbb 98
bcostm 1:ee089790cdbb 99 wm8994_SetFrequency,
bcostm 1:ee089790cdbb 100 wm8994_SetVolume,
bcostm 1:ee089790cdbb 101 wm8994_SetMute,
bcostm 1:ee089790cdbb 102 wm8994_SetOutputMode,
bcostm 1:ee089790cdbb 103
bcostm 1:ee089790cdbb 104 wm8994_Reset
bcostm 1:ee089790cdbb 105 };
bcostm 1:ee089790cdbb 106
bcostm 1:ee089790cdbb 107 static uint32_t outputEnabled = 0;
bcostm 1:ee089790cdbb 108 static uint32_t inputEnabled = 0;
bcostm 1:ee089790cdbb 109 /**
bcostm 1:ee089790cdbb 110 * @}
bcostm 1:ee089790cdbb 111 */
bcostm 1:ee089790cdbb 112
bcostm 1:ee089790cdbb 113 /** @defgroup WM8994_Function_Prototypes
bcostm 1:ee089790cdbb 114 * @{
bcostm 1:ee089790cdbb 115 */
bcostm 1:ee089790cdbb 116 static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value);
bcostm 1:ee089790cdbb 117 /**
bcostm 1:ee089790cdbb 118 * @}
bcostm 1:ee089790cdbb 119 */
bcostm 1:ee089790cdbb 120
bcostm 1:ee089790cdbb 121 /** @defgroup WM8994_Private_Functions
bcostm 1:ee089790cdbb 122 * @{
bcostm 1:ee089790cdbb 123 */
bcostm 1:ee089790cdbb 124
bcostm 1:ee089790cdbb 125 /**
bcostm 1:ee089790cdbb 126 * @brief Initializes the audio codec and the control interface.
bcostm 1:ee089790cdbb 127 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 128 * @param OutputInputDevice: can be OUTPUT_DEVICE_SPEAKER, OUTPUT_DEVICE_HEADPHONE,
bcostm 1:ee089790cdbb 129 * OUTPUT_DEVICE_BOTH, OUTPUT_DEVICE_AUTO, INPUT_DEVICE_DIGITAL_MICROPHONE_1,
bcostm 1:ee089790cdbb 130 * INPUT_DEVICE_DIGITAL_MICROPHONE_2, INPUT_DEVICE_INPUT_LINE_1 or INPUT_DEVICE_INPUT_LINE_2.
bcostm 1:ee089790cdbb 131 * @param Volume: Initial volume level (from 0 (Mute) to 100 (Max))
bcostm 1:ee089790cdbb 132 * @param AudioFreq: Audio Frequency
bcostm 1:ee089790cdbb 133 * @retval 0 if correct communication, else wrong communication
bcostm 1:ee089790cdbb 134 */
bcostm 1:ee089790cdbb 135 uint32_t wm8994_Init(uint16_t DeviceAddr, uint16_t OutputInputDevice, uint8_t Volume, uint32_t AudioFreq)
bcostm 1:ee089790cdbb 136 {
bcostm 1:ee089790cdbb 137 uint32_t counter = 0;
bcostm 1:ee089790cdbb 138 uint16_t output_device = OutputInputDevice & 0xFF;
bcostm 1:ee089790cdbb 139 uint16_t input_device = OutputInputDevice & 0xFF00;
bcostm 1:ee089790cdbb 140 uint16_t power_mgnt_reg_1 = 0;
bcostm 1:ee089790cdbb 141
bcostm 1:ee089790cdbb 142 /* Initialize the Control interface of the Audio Codec */
bcostm 1:ee089790cdbb 143 AUDIO_IO_Init();
bcostm 1:ee089790cdbb 144 /* wm8994 Errata Work-Arounds */
bcostm 1:ee089790cdbb 145 counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0003);
bcostm 1:ee089790cdbb 146 counter += CODEC_IO_Write(DeviceAddr, 0x817, 0x0000);
bcostm 1:ee089790cdbb 147 counter += CODEC_IO_Write(DeviceAddr, 0x102, 0x0000);
bcostm 1:ee089790cdbb 148
bcostm 1:ee089790cdbb 149 /* Enable VMID soft start (fast), Start-up Bias Current Enabled */
bcostm 1:ee089790cdbb 150 counter += CODEC_IO_Write(DeviceAddr, 0x39, 0x006C);
bcostm 1:ee089790cdbb 151
bcostm 1:ee089790cdbb 152 /* Enable bias generator, Enable VMID */
bcostm 1:ee089790cdbb 153 counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x0003);
bcostm 1:ee089790cdbb 154
bcostm 1:ee089790cdbb 155 /* Add Delay */
bcostm 1:ee089790cdbb 156 AUDIO_IO_Delay(50);
bcostm 1:ee089790cdbb 157
bcostm 1:ee089790cdbb 158 /* Path Configurations for output */
bcostm 1:ee089790cdbb 159 if (output_device > 0)
bcostm 1:ee089790cdbb 160 {
bcostm 1:ee089790cdbb 161 outputEnabled = 1;
bcostm 1:ee089790cdbb 162 switch (output_device)
bcostm 1:ee089790cdbb 163 {
bcostm 1:ee089790cdbb 164 case OUTPUT_DEVICE_SPEAKER:
bcostm 1:ee089790cdbb 165 /* Enable DAC1 (Left), Enable DAC1 (Right),
bcostm 1:ee089790cdbb 166 Disable DAC2 (Left), Disable DAC2 (Right)*/
bcostm 1:ee089790cdbb 167 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C);
bcostm 1:ee089790cdbb 168
bcostm 1:ee089790cdbb 169 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 1:ee089790cdbb 170 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000);
bcostm 1:ee089790cdbb 171
bcostm 1:ee089790cdbb 172 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 1:ee089790cdbb 173 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000);
bcostm 1:ee089790cdbb 174
bcostm 1:ee089790cdbb 175 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 1:ee089790cdbb 176 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
bcostm 1:ee089790cdbb 177
bcostm 1:ee089790cdbb 178 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 1:ee089790cdbb 179 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
bcostm 1:ee089790cdbb 180 break;
bcostm 1:ee089790cdbb 181
bcostm 1:ee089790cdbb 182 case OUTPUT_DEVICE_HEADPHONE:
bcostm 1:ee089790cdbb 183 /* Disable DAC1 (Left), Disable DAC1 (Right),
bcostm 1:ee089790cdbb 184 Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 1:ee089790cdbb 185 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
bcostm 1:ee089790cdbb 186
bcostm 1:ee089790cdbb 187 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 1:ee089790cdbb 188 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 1:ee089790cdbb 189
bcostm 1:ee089790cdbb 190 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 1:ee089790cdbb 191 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 1:ee089790cdbb 192
bcostm 1:ee089790cdbb 193 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 1:ee089790cdbb 194 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
bcostm 1:ee089790cdbb 195
bcostm 1:ee089790cdbb 196 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 1:ee089790cdbb 197 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
bcostm 1:ee089790cdbb 198 break;
bcostm 1:ee089790cdbb 199
bcostm 1:ee089790cdbb 200 case OUTPUT_DEVICE_BOTH:
bcostm 1:ee089790cdbb 201 /* Enable DAC1 (Left), Enable DAC1 (Right),
bcostm 1:ee089790cdbb 202 also Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 1:ee089790cdbb 203 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
bcostm 1:ee089790cdbb 204
bcostm 1:ee089790cdbb 205 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 1:ee089790cdbb 206 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 1:ee089790cdbb 207
bcostm 1:ee089790cdbb 208 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 1:ee089790cdbb 209 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 1:ee089790cdbb 210
bcostm 1:ee089790cdbb 211 /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 1:ee089790cdbb 212 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
bcostm 1:ee089790cdbb 213
bcostm 1:ee089790cdbb 214 /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 1:ee089790cdbb 215 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
bcostm 1:ee089790cdbb 216 break;
bcostm 1:ee089790cdbb 217
bcostm 1:ee089790cdbb 218 case OUTPUT_DEVICE_AUTO :
bcostm 1:ee089790cdbb 219 default:
bcostm 1:ee089790cdbb 220 /* Disable DAC1 (Left), Disable DAC1 (Right),
bcostm 1:ee089790cdbb 221 Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 1:ee089790cdbb 222 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
bcostm 1:ee089790cdbb 223
bcostm 1:ee089790cdbb 224 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 1:ee089790cdbb 225 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 1:ee089790cdbb 226
bcostm 1:ee089790cdbb 227 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 1:ee089790cdbb 228 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 1:ee089790cdbb 229
bcostm 1:ee089790cdbb 230 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 1:ee089790cdbb 231 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
bcostm 1:ee089790cdbb 232
bcostm 1:ee089790cdbb 233 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 1:ee089790cdbb 234 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
bcostm 1:ee089790cdbb 235 break;
bcostm 1:ee089790cdbb 236 }
bcostm 1:ee089790cdbb 237 }
bcostm 1:ee089790cdbb 238 else
bcostm 1:ee089790cdbb 239 {
bcostm 1:ee089790cdbb 240 outputEnabled = 0;
bcostm 1:ee089790cdbb 241 }
bcostm 1:ee089790cdbb 242
bcostm 1:ee089790cdbb 243 /* Path Configurations for input */
bcostm 1:ee089790cdbb 244 if (input_device > 0)
bcostm 1:ee089790cdbb 245 {
bcostm 1:ee089790cdbb 246 inputEnabled = 1;
bcostm 1:ee089790cdbb 247 switch (input_device)
bcostm 1:ee089790cdbb 248 {
bcostm 1:ee089790cdbb 249 case INPUT_DEVICE_DIGITAL_MICROPHONE_2 :
bcostm 1:ee089790cdbb 250 /* Enable AIF1ADC2 (Left), Enable AIF1ADC2 (Right)
bcostm 1:ee089790cdbb 251 * Enable DMICDAT2 (Left), Enable DMICDAT2 (Right)
bcostm 1:ee089790cdbb 252 * Enable Left ADC, Enable Right ADC */
bcostm 1:ee089790cdbb 253 counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0C30);
bcostm 1:ee089790cdbb 254
bcostm 1:ee089790cdbb 255 /* Enable AIF1 DRC2 Signal Detect & DRC in AIF1ADC2 Left/Right Timeslot 1 */
bcostm 1:ee089790cdbb 256 counter += CODEC_IO_Write(DeviceAddr, 0x450, 0x00DB);
bcostm 1:ee089790cdbb 257
bcostm 1:ee089790cdbb 258 /* Disable IN1L, IN1R, IN2L, IN2R, Enable Thermal sensor & shutdown */
bcostm 1:ee089790cdbb 259 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6000);
bcostm 1:ee089790cdbb 260
bcostm 1:ee089790cdbb 261 /* Enable the DMIC2(Left) to AIF1 Timeslot 1 (Left) mixer path */
bcostm 1:ee089790cdbb 262 counter += CODEC_IO_Write(DeviceAddr, 0x608, 0x0002);
bcostm 1:ee089790cdbb 263
bcostm 1:ee089790cdbb 264 /* Enable the DMIC2(Right) to AIF1 Timeslot 1 (Right) mixer path */
bcostm 1:ee089790cdbb 265 counter += CODEC_IO_Write(DeviceAddr, 0x609, 0x0002);
bcostm 1:ee089790cdbb 266
bcostm 1:ee089790cdbb 267 /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC2 signal detect */
bcostm 1:ee089790cdbb 268 counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000E);
bcostm 1:ee089790cdbb 269 break;
bcostm 1:ee089790cdbb 270
bcostm 1:ee089790cdbb 271 case INPUT_DEVICE_INPUT_LINE_1 :
bcostm 1:ee089790cdbb 272 /* Enable AIF1ADC1 (Left), Enable AIF1ADC1 (Right)
bcostm 1:ee089790cdbb 273 * Enable Left ADC, Enable Right ADC */
bcostm 1:ee089790cdbb 274 counter += CODEC_IO_Write(DeviceAddr, 0x04, 0x0303);
bcostm 1:ee089790cdbb 275
bcostm 1:ee089790cdbb 276 /* Enable AIF1 DRC1 Signal Detect & DRC in AIF1ADC1 Left/Right Timeslot 0 */
bcostm 1:ee089790cdbb 277 counter += CODEC_IO_Write(DeviceAddr, 0x440, 0x00DB);
bcostm 1:ee089790cdbb 278
bcostm 1:ee089790cdbb 279 /* Enable IN1L and IN1R, Disable IN2L and IN2R, Enable Thermal sensor & shutdown */
bcostm 1:ee089790cdbb 280 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x6350);
bcostm 1:ee089790cdbb 281
bcostm 1:ee089790cdbb 282 /* Enable the ADCL(Left) to AIF1 Timeslot 0 (Left) mixer path */
bcostm 1:ee089790cdbb 283 counter += CODEC_IO_Write(DeviceAddr, 0x606, 0x0002);
bcostm 1:ee089790cdbb 284
bcostm 1:ee089790cdbb 285 /* Enable the ADCR(Right) to AIF1 Timeslot 0 (Right) mixer path */
bcostm 1:ee089790cdbb 286 counter += CODEC_IO_Write(DeviceAddr, 0x607, 0x0002);
bcostm 1:ee089790cdbb 287
bcostm 1:ee089790cdbb 288 /* GPIO1 pin configuration GP1_DIR = output, GP1_FN = AIF1 DRC1 signal detect */
bcostm 1:ee089790cdbb 289 counter += CODEC_IO_Write(DeviceAddr, 0x700, 0x000D);
bcostm 1:ee089790cdbb 290 break;
bcostm 1:ee089790cdbb 291
bcostm 1:ee089790cdbb 292 case INPUT_DEVICE_DIGITAL_MICROPHONE_1 :
bcostm 1:ee089790cdbb 293 case INPUT_DEVICE_INPUT_LINE_2 :
bcostm 1:ee089790cdbb 294 default:
bcostm 1:ee089790cdbb 295 /* Actually, no other input devices supported */
bcostm 1:ee089790cdbb 296 counter++;
bcostm 1:ee089790cdbb 297 break;
bcostm 1:ee089790cdbb 298 }
bcostm 1:ee089790cdbb 299 }
bcostm 1:ee089790cdbb 300 else
bcostm 1:ee089790cdbb 301 {
bcostm 1:ee089790cdbb 302 inputEnabled = 0;
bcostm 1:ee089790cdbb 303 }
bcostm 1:ee089790cdbb 304
bcostm 1:ee089790cdbb 305 /* Clock Configurations */
bcostm 1:ee089790cdbb 306 switch (AudioFreq)
bcostm 1:ee089790cdbb 307 {
bcostm 1:ee089790cdbb 308 case AUDIO_FREQUENCY_8K:
bcostm 1:ee089790cdbb 309 /* AIF1 Sample Rate = 8 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 310 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003);
bcostm 1:ee089790cdbb 311 break;
bcostm 1:ee089790cdbb 312
bcostm 1:ee089790cdbb 313 case AUDIO_FREQUENCY_16K:
bcostm 1:ee089790cdbb 314 /* AIF1 Sample Rate = 16 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 315 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033);
bcostm 1:ee089790cdbb 316 break;
bcostm 1:ee089790cdbb 317
bcostm 1:ee089790cdbb 318 case AUDIO_FREQUENCY_48K:
bcostm 1:ee089790cdbb 319 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 320 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
bcostm 1:ee089790cdbb 321 break;
bcostm 1:ee089790cdbb 322
bcostm 1:ee089790cdbb 323 case AUDIO_FREQUENCY_96K:
bcostm 1:ee089790cdbb 324 /* AIF1 Sample Rate = 96 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 325 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3);
bcostm 1:ee089790cdbb 326 break;
bcostm 1:ee089790cdbb 327
bcostm 1:ee089790cdbb 328 case AUDIO_FREQUENCY_11K:
bcostm 1:ee089790cdbb 329 /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 330 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013);
bcostm 1:ee089790cdbb 331 break;
bcostm 1:ee089790cdbb 332
bcostm 1:ee089790cdbb 333 case AUDIO_FREQUENCY_22K:
bcostm 1:ee089790cdbb 334 /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 335 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043);
bcostm 1:ee089790cdbb 336 break;
bcostm 1:ee089790cdbb 337
bcostm 1:ee089790cdbb 338 case AUDIO_FREQUENCY_44K:
bcostm 1:ee089790cdbb 339 /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 340 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073);
bcostm 1:ee089790cdbb 341 break;
bcostm 1:ee089790cdbb 342
bcostm 1:ee089790cdbb 343 default:
bcostm 1:ee089790cdbb 344 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 345 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
bcostm 1:ee089790cdbb 346 break;
bcostm 1:ee089790cdbb 347 }
bcostm 1:ee089790cdbb 348 /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */
bcostm 1:ee089790cdbb 349 counter += CODEC_IO_Write(DeviceAddr, 0x300, 0x4010);
bcostm 1:ee089790cdbb 350
bcostm 1:ee089790cdbb 351 /* slave mode */
bcostm 1:ee089790cdbb 352 counter += CODEC_IO_Write(DeviceAddr, 0x302, 0x0000);
bcostm 1:ee089790cdbb 353
bcostm 1:ee089790cdbb 354 /* Enable the DSP processing clock for AIF1, Enable the core clock */
bcostm 1:ee089790cdbb 355 counter += CODEC_IO_Write(DeviceAddr, 0x208, 0x000A);
bcostm 1:ee089790cdbb 356
bcostm 1:ee089790cdbb 357 /* Enable AIF1 Clock, AIF1 Clock Source = MCLK1 pin */
bcostm 1:ee089790cdbb 358 counter += CODEC_IO_Write(DeviceAddr, 0x200, 0x0001);
bcostm 1:ee089790cdbb 359
bcostm 1:ee089790cdbb 360 if (output_device > 0) /* Audio output selected */
bcostm 1:ee089790cdbb 361 {
bcostm 1:ee089790cdbb 362 /* Analog Output Configuration */
bcostm 1:ee089790cdbb 363
bcostm 1:ee089790cdbb 364 /* Enable SPKRVOL PGA, Enable SPKMIXR, Enable SPKLVOL PGA, Enable SPKMIXL */
bcostm 1:ee089790cdbb 365 counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0300);
bcostm 1:ee089790cdbb 366
bcostm 1:ee089790cdbb 367 /* Left Speaker Mixer Volume = 0dB */
bcostm 1:ee089790cdbb 368 counter += CODEC_IO_Write(DeviceAddr, 0x22, 0x0000);
bcostm 1:ee089790cdbb 369
bcostm 1:ee089790cdbb 370 /* Speaker output mode = Class D, Right Speaker Mixer Volume = 0dB ((0x23, 0x0100) = class AB)*/
bcostm 1:ee089790cdbb 371 counter += CODEC_IO_Write(DeviceAddr, 0x23, 0x0000);
bcostm 1:ee089790cdbb 372
bcostm 1:ee089790cdbb 373 /* Unmute DAC2 (Left) to Left Speaker Mixer (SPKMIXL) path,
bcostm 1:ee089790cdbb 374 Unmute DAC2 (Right) to Right Speaker Mixer (SPKMIXR) path */
bcostm 1:ee089790cdbb 375 counter += CODEC_IO_Write(DeviceAddr, 0x36, 0x0300);
bcostm 1:ee089790cdbb 376
bcostm 1:ee089790cdbb 377 /* Enable bias generator, Enable VMID, Enable SPKOUTL, Enable SPKOUTR */
bcostm 1:ee089790cdbb 378 counter += CODEC_IO_Write(DeviceAddr, 0x01, 0x3003);
bcostm 1:ee089790cdbb 379
bcostm 1:ee089790cdbb 380 /* Headphone/Speaker Enable */
bcostm 1:ee089790cdbb 381
bcostm 1:ee089790cdbb 382 /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */
bcostm 1:ee089790cdbb 383 counter += CODEC_IO_Write(DeviceAddr, 0x51, 0x0005);
bcostm 1:ee089790cdbb 384
bcostm 1:ee089790cdbb 385 /* Enable bias generator, Enable VMID, Enable HPOUT1 (Left) and Enable HPOUT1 (Right) input stages */
bcostm 1:ee089790cdbb 386 /* idem for Speaker */
bcostm 1:ee089790cdbb 387 power_mgnt_reg_1 |= 0x0303 | 0x3003;
bcostm 1:ee089790cdbb 388 counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
bcostm 1:ee089790cdbb 389
bcostm 1:ee089790cdbb 390 /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate stages */
bcostm 1:ee089790cdbb 391 counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x0022);
bcostm 1:ee089790cdbb 392
bcostm 1:ee089790cdbb 393 /* Enable Charge Pump */
bcostm 1:ee089790cdbb 394 counter += CODEC_IO_Write(DeviceAddr, 0x4C, 0x9F25);
bcostm 1:ee089790cdbb 395
bcostm 1:ee089790cdbb 396 /* Add Delay */
bcostm 1:ee089790cdbb 397 AUDIO_IO_Delay(15);
bcostm 1:ee089790cdbb 398
bcostm 1:ee089790cdbb 399 /* Select DAC1 (Left) to Left Headphone Output PGA (HPOUT1LVOL) path */
bcostm 1:ee089790cdbb 400 counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0001);
bcostm 1:ee089790cdbb 401
bcostm 1:ee089790cdbb 402 /* Select DAC1 (Right) to Right Headphone Output PGA (HPOUT1RVOL) path */
bcostm 1:ee089790cdbb 403 counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0001);
bcostm 1:ee089790cdbb 404
bcostm 1:ee089790cdbb 405 /* Enable Left Output Mixer (MIXOUTL), Enable Right Output Mixer (MIXOUTR) */
bcostm 1:ee089790cdbb 406 /* idem for SPKOUTL and SPKOUTR */
bcostm 1:ee089790cdbb 407 counter += CODEC_IO_Write(DeviceAddr, 0x03, 0x0030 | 0x0300);
bcostm 1:ee089790cdbb 408
bcostm 1:ee089790cdbb 409 /* Enable DC Servo and trigger start-up mode on left and right channels */
bcostm 1:ee089790cdbb 410 counter += CODEC_IO_Write(DeviceAddr, 0x54, 0x0033);
bcostm 1:ee089790cdbb 411
bcostm 1:ee089790cdbb 412 /* Add Delay */
bcostm 1:ee089790cdbb 413 AUDIO_IO_Delay(250);
bcostm 1:ee089790cdbb 414
bcostm 1:ee089790cdbb 415 /* Enable HPOUT1 (Left) and HPOUT1 (Right) intermediate and output stages. Remove clamps */
bcostm 1:ee089790cdbb 416 counter += CODEC_IO_Write(DeviceAddr, 0x60, 0x00EE);
bcostm 1:ee089790cdbb 417
bcostm 1:ee089790cdbb 418 /* Unmutes */
bcostm 1:ee089790cdbb 419
bcostm 1:ee089790cdbb 420 /* Unmute DAC 1 (Left) */
bcostm 1:ee089790cdbb 421 counter += CODEC_IO_Write(DeviceAddr, 0x610, 0x00C0);
bcostm 1:ee089790cdbb 422
bcostm 1:ee089790cdbb 423 /* Unmute DAC 1 (Right) */
bcostm 1:ee089790cdbb 424 counter += CODEC_IO_Write(DeviceAddr, 0x611, 0x00C0);
bcostm 1:ee089790cdbb 425
bcostm 1:ee089790cdbb 426 /* Unmute the AIF1 Timeslot 0 DAC path */
bcostm 1:ee089790cdbb 427 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000);
bcostm 1:ee089790cdbb 428
bcostm 1:ee089790cdbb 429 /* Unmute DAC 2 (Left) */
bcostm 1:ee089790cdbb 430 counter += CODEC_IO_Write(DeviceAddr, 0x612, 0x00C0);
bcostm 1:ee089790cdbb 431
bcostm 1:ee089790cdbb 432 /* Unmute DAC 2 (Right) */
bcostm 1:ee089790cdbb 433 counter += CODEC_IO_Write(DeviceAddr, 0x613, 0x00C0);
bcostm 1:ee089790cdbb 434
bcostm 1:ee089790cdbb 435 /* Unmute the AIF1 Timeslot 1 DAC2 path */
bcostm 1:ee089790cdbb 436 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000);
bcostm 1:ee089790cdbb 437
bcostm 1:ee089790cdbb 438 /* Volume Control */
bcostm 1:ee089790cdbb 439 wm8994_SetVolume(DeviceAddr, Volume);
bcostm 1:ee089790cdbb 440 }
bcostm 1:ee089790cdbb 441
bcostm 1:ee089790cdbb 442 if (input_device > 0) /* Audio input selected */
bcostm 1:ee089790cdbb 443 {
bcostm 1:ee089790cdbb 444 if ((input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_1) || (input_device == INPUT_DEVICE_DIGITAL_MICROPHONE_2))
bcostm 1:ee089790cdbb 445 {
bcostm 1:ee089790cdbb 446 /* Enable Microphone bias 1 generator, Enable VMID */
bcostm 1:ee089790cdbb 447 power_mgnt_reg_1 |= 0x0013;
bcostm 1:ee089790cdbb 448 counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
bcostm 1:ee089790cdbb 449
bcostm 1:ee089790cdbb 450 /* ADC oversample enable */
bcostm 1:ee089790cdbb 451 counter += CODEC_IO_Write(DeviceAddr, 0x620, 0x0002);
bcostm 1:ee089790cdbb 452
bcostm 1:ee089790cdbb 453 /* AIF ADC2 HPF enable, HPF cut = voice mode 1 fc=127Hz at fs=8kHz */
bcostm 1:ee089790cdbb 454 counter += CODEC_IO_Write(DeviceAddr, 0x411, 0x3800);
bcostm 1:ee089790cdbb 455 }
bcostm 1:ee089790cdbb 456 else if ((input_device == INPUT_DEVICE_INPUT_LINE_1) || (input_device == INPUT_DEVICE_INPUT_LINE_2))
bcostm 1:ee089790cdbb 457 {
bcostm 1:ee089790cdbb 458 /* Enable normal bias generator, Enable VMID */
bcostm 1:ee089790cdbb 459 power_mgnt_reg_1 |= 0x0003;
bcostm 1:ee089790cdbb 460 counter += CODEC_IO_Write(DeviceAddr, 0x01, power_mgnt_reg_1);
bcostm 1:ee089790cdbb 461
bcostm 1:ee089790cdbb 462 /* Disable mute on IN1L, IN1L Volume = +0dB */
bcostm 1:ee089790cdbb 463 counter += CODEC_IO_Write(DeviceAddr, 0x18, 0x000B);
bcostm 1:ee089790cdbb 464
bcostm 1:ee089790cdbb 465 /* Disable mute on IN1R, IN1R Volume = +0dB */
bcostm 1:ee089790cdbb 466 counter += CODEC_IO_Write(DeviceAddr, 0x1A, 0x000B);
bcostm 1:ee089790cdbb 467
bcostm 1:ee089790cdbb 468 /* Disable mute on IN1L_TO_MIXINL, Gain = +0dB */
bcostm 1:ee089790cdbb 469 counter += CODEC_IO_Write(DeviceAddr, 0x29, 0x0025);
bcostm 1:ee089790cdbb 470
bcostm 1:ee089790cdbb 471 /* Disable mute on IN1R_TO_MIXINL, Gain = +0dB */
bcostm 1:ee089790cdbb 472 counter += CODEC_IO_Write(DeviceAddr, 0x2A, 0x0025);
bcostm 1:ee089790cdbb 473
bcostm 1:ee089790cdbb 474 /* IN1LN_TO_IN1L, IN1LP_TO_VMID, IN1RN_TO_IN1R, IN1RP_TO_VMID */
bcostm 1:ee089790cdbb 475 counter += CODEC_IO_Write(DeviceAddr, 0x28, 0x0011);
bcostm 1:ee089790cdbb 476
bcostm 1:ee089790cdbb 477 /* AIF ADC1 HPF enable, HPF cut = hifi mode fc=4Hz at fs=48kHz */
bcostm 1:ee089790cdbb 478 counter += CODEC_IO_Write(DeviceAddr, 0x410, 0x1800);
bcostm 1:ee089790cdbb 479 }
bcostm 1:ee089790cdbb 480 /* Volume Control */
bcostm 1:ee089790cdbb 481 wm8994_SetVolume(DeviceAddr, Volume);
bcostm 1:ee089790cdbb 482 }
bcostm 1:ee089790cdbb 483 /* Return communication control value */
bcostm 1:ee089790cdbb 484 return counter;
bcostm 1:ee089790cdbb 485 }
bcostm 1:ee089790cdbb 486
bcostm 1:ee089790cdbb 487 /**
bcostm 1:ee089790cdbb 488 * @brief Deinitializes the audio codec.
bcostm 1:ee089790cdbb 489 * @param None
bcostm 1:ee089790cdbb 490 * @retval None
bcostm 1:ee089790cdbb 491 */
bcostm 1:ee089790cdbb 492 void wm8994_DeInit(void)
bcostm 1:ee089790cdbb 493 {
bcostm 1:ee089790cdbb 494 /* Deinitialize Audio Codec interface */
bcostm 1:ee089790cdbb 495 AUDIO_IO_DeInit();
bcostm 1:ee089790cdbb 496 }
bcostm 1:ee089790cdbb 497
bcostm 1:ee089790cdbb 498 /**
bcostm 1:ee089790cdbb 499 * @brief Get the WM8994 ID.
bcostm 1:ee089790cdbb 500 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 501 * @retval The WM8994 ID
bcostm 1:ee089790cdbb 502 */
bcostm 1:ee089790cdbb 503 uint32_t wm8994_ReadID(uint16_t DeviceAddr)
bcostm 1:ee089790cdbb 504 {
bcostm 1:ee089790cdbb 505 /* Initialize the Control interface of the Audio Codec */
bcostm 1:ee089790cdbb 506 AUDIO_IO_Init();
bcostm 1:ee089790cdbb 507
bcostm 1:ee089790cdbb 508 return ((uint32_t)AUDIO_IO_Read(DeviceAddr, WM8994_CHIPID_ADDR));
bcostm 1:ee089790cdbb 509 }
bcostm 1:ee089790cdbb 510
bcostm 1:ee089790cdbb 511 /**
bcostm 1:ee089790cdbb 512 * @brief Start the audio Codec play feature.
bcostm 1:ee089790cdbb 513 * @note For this codec no Play options are required.
bcostm 1:ee089790cdbb 514 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 515 * @retval 0 if correct communication, else wrong communication
bcostm 1:ee089790cdbb 516 */
bcostm 1:ee089790cdbb 517 uint32_t wm8994_Play(uint16_t DeviceAddr, uint16_t* pBuffer, uint16_t Size)
bcostm 1:ee089790cdbb 518 {
bcostm 1:ee089790cdbb 519 uint32_t counter = 0;
bcostm 1:ee089790cdbb 520
bcostm 1:ee089790cdbb 521 /* Resumes the audio file playing */
bcostm 1:ee089790cdbb 522 /* Unmute the output first */
bcostm 1:ee089790cdbb 523 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
bcostm 1:ee089790cdbb 524
bcostm 1:ee089790cdbb 525 return counter;
bcostm 1:ee089790cdbb 526 }
bcostm 1:ee089790cdbb 527
bcostm 1:ee089790cdbb 528 /**
bcostm 1:ee089790cdbb 529 * @brief Pauses playing on the audio codec.
bcostm 1:ee089790cdbb 530 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 531 * @retval 0 if correct communication, else wrong communication
bcostm 1:ee089790cdbb 532 */
bcostm 1:ee089790cdbb 533 uint32_t wm8994_Pause(uint16_t DeviceAddr)
bcostm 1:ee089790cdbb 534 {
bcostm 1:ee089790cdbb 535 uint32_t counter = 0;
bcostm 1:ee089790cdbb 536
bcostm 1:ee089790cdbb 537 /* Pause the audio file playing */
bcostm 1:ee089790cdbb 538 /* Mute the output first */
bcostm 1:ee089790cdbb 539 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
bcostm 1:ee089790cdbb 540
bcostm 1:ee089790cdbb 541 /* Put the Codec in Power save mode */
bcostm 1:ee089790cdbb 542 counter += CODEC_IO_Write(DeviceAddr, 0x02, 0x01);
bcostm 1:ee089790cdbb 543
bcostm 1:ee089790cdbb 544 return counter;
bcostm 1:ee089790cdbb 545 }
bcostm 1:ee089790cdbb 546
bcostm 1:ee089790cdbb 547 /**
bcostm 1:ee089790cdbb 548 * @brief Resumes playing on the audio codec.
bcostm 1:ee089790cdbb 549 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 550 * @retval 0 if correct communication, else wrong communication
bcostm 1:ee089790cdbb 551 */
bcostm 1:ee089790cdbb 552 uint32_t wm8994_Resume(uint16_t DeviceAddr)
bcostm 1:ee089790cdbb 553 {
bcostm 1:ee089790cdbb 554 uint32_t counter = 0;
bcostm 1:ee089790cdbb 555
bcostm 1:ee089790cdbb 556 /* Resumes the audio file playing */
bcostm 1:ee089790cdbb 557 /* Unmute the output first */
bcostm 1:ee089790cdbb 558 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
bcostm 1:ee089790cdbb 559
bcostm 1:ee089790cdbb 560 return counter;
bcostm 1:ee089790cdbb 561 }
bcostm 1:ee089790cdbb 562
bcostm 1:ee089790cdbb 563 /**
bcostm 1:ee089790cdbb 564 * @brief Stops audio Codec playing. It powers down the codec.
bcostm 1:ee089790cdbb 565 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 566 * @param CodecPdwnMode: selects the power down mode.
bcostm 1:ee089790cdbb 567 * - CODEC_PDWN_SW: only mutes the audio codec. When resuming from this
bcostm 1:ee089790cdbb 568 * mode the codec keeps the previous initialization
bcostm 1:ee089790cdbb 569 * (no need to re-Initialize the codec registers).
bcostm 1:ee089790cdbb 570 * - CODEC_PDWN_HW: Physically power down the codec. When resuming from this
bcostm 1:ee089790cdbb 571 * mode, the codec is set to default configuration
bcostm 1:ee089790cdbb 572 * (user should re-Initialize the codec in order to
bcostm 1:ee089790cdbb 573 * play again the audio stream).
bcostm 1:ee089790cdbb 574 * @retval 0 if correct communication, else wrong communication
bcostm 1:ee089790cdbb 575 */
bcostm 1:ee089790cdbb 576 uint32_t wm8994_Stop(uint16_t DeviceAddr, uint32_t CodecPdwnMode)
bcostm 1:ee089790cdbb 577 {
bcostm 1:ee089790cdbb 578 uint32_t counter = 0;
bcostm 1:ee089790cdbb 579
bcostm 1:ee089790cdbb 580 if (outputEnabled != 0)
bcostm 1:ee089790cdbb 581 {
bcostm 1:ee089790cdbb 582 /* Mute the output first */
bcostm 1:ee089790cdbb 583 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
bcostm 1:ee089790cdbb 584
bcostm 1:ee089790cdbb 585 if (CodecPdwnMode == CODEC_PDWN_SW)
bcostm 1:ee089790cdbb 586 {
bcostm 1:ee089790cdbb 587 /* Only output mute required*/
bcostm 1:ee089790cdbb 588 }
bcostm 1:ee089790cdbb 589 else /* CODEC_PDWN_HW */
bcostm 1:ee089790cdbb 590 {
bcostm 1:ee089790cdbb 591 /* Mute the AIF1 Timeslot 0 DAC1 path */
bcostm 1:ee089790cdbb 592 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200);
bcostm 1:ee089790cdbb 593
bcostm 1:ee089790cdbb 594 /* Mute the AIF1 Timeslot 1 DAC2 path */
bcostm 1:ee089790cdbb 595 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200);
bcostm 1:ee089790cdbb 596
bcostm 1:ee089790cdbb 597 /* Disable DAC1L_TO_HPOUT1L */
bcostm 1:ee089790cdbb 598 counter += CODEC_IO_Write(DeviceAddr, 0x2D, 0x0000);
bcostm 1:ee089790cdbb 599
bcostm 1:ee089790cdbb 600 /* Disable DAC1R_TO_HPOUT1R */
bcostm 1:ee089790cdbb 601 counter += CODEC_IO_Write(DeviceAddr, 0x2E, 0x0000);
bcostm 1:ee089790cdbb 602
bcostm 1:ee089790cdbb 603 /* Disable DAC1 and DAC2 */
bcostm 1:ee089790cdbb 604 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0000);
bcostm 1:ee089790cdbb 605
bcostm 1:ee089790cdbb 606 /* Reset Codec by writing in 0x0000 address register */
bcostm 1:ee089790cdbb 607 counter += CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000);
bcostm 1:ee089790cdbb 608
bcostm 1:ee089790cdbb 609 outputEnabled = 0;
bcostm 1:ee089790cdbb 610 }
bcostm 1:ee089790cdbb 611 }
bcostm 1:ee089790cdbb 612 return counter;
bcostm 1:ee089790cdbb 613 }
bcostm 1:ee089790cdbb 614
bcostm 1:ee089790cdbb 615 /**
bcostm 1:ee089790cdbb 616 * @brief Sets higher or lower the codec volume level.
bcostm 1:ee089790cdbb 617 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 618 * @param Volume: a byte value from 0 to 255 (refer to codec registers
bcostm 1:ee089790cdbb 619 * description for more details).
bcostm 1:ee089790cdbb 620 * @retval 0 if correct communication, else wrong communication
bcostm 1:ee089790cdbb 621 */
bcostm 1:ee089790cdbb 622 uint32_t wm8994_SetVolume(uint16_t DeviceAddr, uint8_t Volume)
bcostm 1:ee089790cdbb 623 {
bcostm 1:ee089790cdbb 624 uint32_t counter = 0;
bcostm 1:ee089790cdbb 625 uint8_t convertedvol = VOLUME_CONVERT(Volume);
bcostm 1:ee089790cdbb 626
bcostm 1:ee089790cdbb 627 /* Output volume */
bcostm 1:ee089790cdbb 628 if (outputEnabled != 0)
bcostm 1:ee089790cdbb 629 {
bcostm 1:ee089790cdbb 630 if(convertedvol > 0x3E)
bcostm 1:ee089790cdbb 631 {
bcostm 1:ee089790cdbb 632 /* Unmute audio codec */
bcostm 1:ee089790cdbb 633 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
bcostm 1:ee089790cdbb 634
bcostm 1:ee089790cdbb 635 /* Left Headphone Volume */
bcostm 1:ee089790cdbb 636 counter += CODEC_IO_Write(DeviceAddr, 0x1C, 0x3F | 0x140);
bcostm 1:ee089790cdbb 637
bcostm 1:ee089790cdbb 638 /* Right Headphone Volume */
bcostm 1:ee089790cdbb 639 counter += CODEC_IO_Write(DeviceAddr, 0x1D, 0x3F | 0x140);
bcostm 1:ee089790cdbb 640
bcostm 1:ee089790cdbb 641 /* Left Speaker Volume */
bcostm 1:ee089790cdbb 642 counter += CODEC_IO_Write(DeviceAddr, 0x26, 0x3F | 0x140);
bcostm 1:ee089790cdbb 643
bcostm 1:ee089790cdbb 644 /* Right Speaker Volume */
bcostm 1:ee089790cdbb 645 counter += CODEC_IO_Write(DeviceAddr, 0x27, 0x3F | 0x140);
bcostm 1:ee089790cdbb 646 }
bcostm 1:ee089790cdbb 647 else if (Volume == 0)
bcostm 1:ee089790cdbb 648 {
bcostm 1:ee089790cdbb 649 /* Mute audio codec */
bcostm 1:ee089790cdbb 650 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_ON);
bcostm 1:ee089790cdbb 651 }
bcostm 1:ee089790cdbb 652 else
bcostm 1:ee089790cdbb 653 {
bcostm 1:ee089790cdbb 654 /* Unmute audio codec */
bcostm 1:ee089790cdbb 655 counter += wm8994_SetMute(DeviceAddr, AUDIO_MUTE_OFF);
bcostm 1:ee089790cdbb 656
bcostm 1:ee089790cdbb 657 /* Left Headphone Volume */
bcostm 1:ee089790cdbb 658 counter += CODEC_IO_Write(DeviceAddr, 0x1C, convertedvol | 0x140);
bcostm 1:ee089790cdbb 659
bcostm 1:ee089790cdbb 660 /* Right Headphone Volume */
bcostm 1:ee089790cdbb 661 counter += CODEC_IO_Write(DeviceAddr, 0x1D, convertedvol | 0x140);
bcostm 1:ee089790cdbb 662
bcostm 1:ee089790cdbb 663 /* Left Speaker Volume */
bcostm 1:ee089790cdbb 664 counter += CODEC_IO_Write(DeviceAddr, 0x26, convertedvol | 0x140);
bcostm 1:ee089790cdbb 665
bcostm 1:ee089790cdbb 666 /* Right Speaker Volume */
bcostm 1:ee089790cdbb 667 counter += CODEC_IO_Write(DeviceAddr, 0x27, convertedvol | 0x140);
bcostm 1:ee089790cdbb 668 }
bcostm 1:ee089790cdbb 669 }
bcostm 1:ee089790cdbb 670
bcostm 1:ee089790cdbb 671 /* Input volume */
bcostm 1:ee089790cdbb 672 if (inputEnabled != 0)
bcostm 1:ee089790cdbb 673 {
bcostm 1:ee089790cdbb 674 convertedvol = VOLUME_IN_CONVERT(Volume);
bcostm 1:ee089790cdbb 675
bcostm 1:ee089790cdbb 676 /* Left AIF1 ADC1 volume */
bcostm 1:ee089790cdbb 677 counter += CODEC_IO_Write(DeviceAddr, 0x400, convertedvol | 0x100);
bcostm 1:ee089790cdbb 678
bcostm 1:ee089790cdbb 679 /* Right AIF1 ADC1 volume */
bcostm 1:ee089790cdbb 680 counter += CODEC_IO_Write(DeviceAddr, 0x401, convertedvol | 0x100);
bcostm 1:ee089790cdbb 681
bcostm 1:ee089790cdbb 682 /* Left AIF1 ADC2 volume */
bcostm 1:ee089790cdbb 683 counter += CODEC_IO_Write(DeviceAddr, 0x404, convertedvol | 0x100);
bcostm 1:ee089790cdbb 684
bcostm 1:ee089790cdbb 685 /* Right AIF1 ADC2 volume */
bcostm 1:ee089790cdbb 686 counter += CODEC_IO_Write(DeviceAddr, 0x405, convertedvol | 0x100);
bcostm 1:ee089790cdbb 687 }
bcostm 1:ee089790cdbb 688 return counter;
bcostm 1:ee089790cdbb 689 }
bcostm 1:ee089790cdbb 690
bcostm 1:ee089790cdbb 691 /**
bcostm 1:ee089790cdbb 692 * @brief Enables or disables the mute feature on the audio codec.
bcostm 1:ee089790cdbb 693 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 694 * @param Cmd: AUDIO_MUTE_ON to enable the mute or AUDIO_MUTE_OFF to disable the
bcostm 1:ee089790cdbb 695 * mute mode.
bcostm 1:ee089790cdbb 696 * @retval 0 if correct communication, else wrong communication
bcostm 1:ee089790cdbb 697 */
bcostm 1:ee089790cdbb 698 uint32_t wm8994_SetMute(uint16_t DeviceAddr, uint32_t Cmd)
bcostm 1:ee089790cdbb 699 {
bcostm 1:ee089790cdbb 700 uint32_t counter = 0;
bcostm 1:ee089790cdbb 701
bcostm 1:ee089790cdbb 702 if (outputEnabled != 0)
bcostm 1:ee089790cdbb 703 {
bcostm 1:ee089790cdbb 704 /* Set the Mute mode */
bcostm 1:ee089790cdbb 705 if(Cmd == AUDIO_MUTE_ON)
bcostm 1:ee089790cdbb 706 {
bcostm 1:ee089790cdbb 707 /* Soft Mute the AIF1 Timeslot 0 DAC1 path L&R */
bcostm 1:ee089790cdbb 708 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0200);
bcostm 1:ee089790cdbb 709
bcostm 1:ee089790cdbb 710 /* Soft Mute the AIF1 Timeslot 1 DAC2 path L&R */
bcostm 1:ee089790cdbb 711 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0200);
bcostm 1:ee089790cdbb 712 }
bcostm 1:ee089790cdbb 713 else /* AUDIO_MUTE_OFF Disable the Mute */
bcostm 1:ee089790cdbb 714 {
bcostm 1:ee089790cdbb 715 /* Unmute the AIF1 Timeslot 0 DAC1 path L&R */
bcostm 1:ee089790cdbb 716 counter += CODEC_IO_Write(DeviceAddr, 0x420, 0x0000);
bcostm 1:ee089790cdbb 717
bcostm 1:ee089790cdbb 718 /* Unmute the AIF1 Timeslot 1 DAC2 path L&R */
bcostm 1:ee089790cdbb 719 counter += CODEC_IO_Write(DeviceAddr, 0x422, 0x0000);
bcostm 1:ee089790cdbb 720 }
bcostm 1:ee089790cdbb 721 }
bcostm 1:ee089790cdbb 722 return counter;
bcostm 1:ee089790cdbb 723 }
bcostm 1:ee089790cdbb 724
bcostm 1:ee089790cdbb 725 /**
bcostm 1:ee089790cdbb 726 * @brief Switch dynamically (while audio file is played) the output target
bcostm 1:ee089790cdbb 727 * (speaker or headphone).
bcostm 1:ee089790cdbb 728 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 729 * @param Output: specifies the audio output target: OUTPUT_DEVICE_SPEAKER,
bcostm 1:ee089790cdbb 730 * OUTPUT_DEVICE_HEADPHONE, OUTPUT_DEVICE_BOTH or OUTPUT_DEVICE_AUTO
bcostm 1:ee089790cdbb 731 * @retval 0 if correct communication, else wrong communication
bcostm 1:ee089790cdbb 732 */
bcostm 1:ee089790cdbb 733 uint32_t wm8994_SetOutputMode(uint16_t DeviceAddr, uint8_t Output)
bcostm 1:ee089790cdbb 734 {
bcostm 1:ee089790cdbb 735 uint32_t counter = 0;
bcostm 1:ee089790cdbb 736
bcostm 1:ee089790cdbb 737 switch (Output)
bcostm 1:ee089790cdbb 738 {
bcostm 1:ee089790cdbb 739 case OUTPUT_DEVICE_SPEAKER:
bcostm 1:ee089790cdbb 740 /* Enable DAC1 (Left), Enable DAC1 (Right),
bcostm 1:ee089790cdbb 741 Disable DAC2 (Left), Disable DAC2 (Right)*/
bcostm 1:ee089790cdbb 742 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0C0C);
bcostm 1:ee089790cdbb 743
bcostm 1:ee089790cdbb 744 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 1:ee089790cdbb 745 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0000);
bcostm 1:ee089790cdbb 746
bcostm 1:ee089790cdbb 747 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 1:ee089790cdbb 748 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0000);
bcostm 1:ee089790cdbb 749
bcostm 1:ee089790cdbb 750 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 1:ee089790cdbb 751 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
bcostm 1:ee089790cdbb 752
bcostm 1:ee089790cdbb 753 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 1:ee089790cdbb 754 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
bcostm 1:ee089790cdbb 755 break;
bcostm 1:ee089790cdbb 756
bcostm 1:ee089790cdbb 757 case OUTPUT_DEVICE_HEADPHONE:
bcostm 1:ee089790cdbb 758 /* Disable DAC1 (Left), Disable DAC1 (Right),
bcostm 1:ee089790cdbb 759 Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 1:ee089790cdbb 760 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
bcostm 1:ee089790cdbb 761
bcostm 1:ee089790cdbb 762 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 1:ee089790cdbb 763 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 1:ee089790cdbb 764
bcostm 1:ee089790cdbb 765 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 1:ee089790cdbb 766 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 1:ee089790cdbb 767
bcostm 1:ee089790cdbb 768 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 1:ee089790cdbb 769 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
bcostm 1:ee089790cdbb 770
bcostm 1:ee089790cdbb 771 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 1:ee089790cdbb 772 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
bcostm 1:ee089790cdbb 773 break;
bcostm 1:ee089790cdbb 774
bcostm 1:ee089790cdbb 775 case OUTPUT_DEVICE_BOTH:
bcostm 1:ee089790cdbb 776 /* Enable DAC1 (Left), Enable DAC1 (Right),
bcostm 1:ee089790cdbb 777 also Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 1:ee089790cdbb 778 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303 | 0x0C0C);
bcostm 1:ee089790cdbb 779
bcostm 1:ee089790cdbb 780 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 1:ee089790cdbb 781 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 1:ee089790cdbb 782
bcostm 1:ee089790cdbb 783 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 1:ee089790cdbb 784 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 1:ee089790cdbb 785
bcostm 1:ee089790cdbb 786 /* Enable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 1:ee089790cdbb 787 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0002);
bcostm 1:ee089790cdbb 788
bcostm 1:ee089790cdbb 789 /* Enable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 1:ee089790cdbb 790 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0002);
bcostm 1:ee089790cdbb 791 break;
bcostm 1:ee089790cdbb 792
bcostm 1:ee089790cdbb 793 default:
bcostm 1:ee089790cdbb 794 /* Disable DAC1 (Left), Disable DAC1 (Right),
bcostm 1:ee089790cdbb 795 Enable DAC2 (Left), Enable DAC2 (Right)*/
bcostm 1:ee089790cdbb 796 counter += CODEC_IO_Write(DeviceAddr, 0x05, 0x0303);
bcostm 1:ee089790cdbb 797
bcostm 1:ee089790cdbb 798 /* Enable the AIF1 Timeslot 0 (Left) to DAC 1 (Left) mixer path */
bcostm 1:ee089790cdbb 799 counter += CODEC_IO_Write(DeviceAddr, 0x601, 0x0001);
bcostm 1:ee089790cdbb 800
bcostm 1:ee089790cdbb 801 /* Enable the AIF1 Timeslot 0 (Right) to DAC 1 (Right) mixer path */
bcostm 1:ee089790cdbb 802 counter += CODEC_IO_Write(DeviceAddr, 0x602, 0x0001);
bcostm 1:ee089790cdbb 803
bcostm 1:ee089790cdbb 804 /* Disable the AIF1 Timeslot 1 (Left) to DAC 2 (Left) mixer path */
bcostm 1:ee089790cdbb 805 counter += CODEC_IO_Write(DeviceAddr, 0x604, 0x0000);
bcostm 1:ee089790cdbb 806
bcostm 1:ee089790cdbb 807 /* Disable the AIF1 Timeslot 1 (Right) to DAC 2 (Right) mixer path */
bcostm 1:ee089790cdbb 808 counter += CODEC_IO_Write(DeviceAddr, 0x605, 0x0000);
bcostm 1:ee089790cdbb 809 break;
bcostm 1:ee089790cdbb 810 }
bcostm 1:ee089790cdbb 811 return counter;
bcostm 1:ee089790cdbb 812 }
bcostm 1:ee089790cdbb 813
bcostm 1:ee089790cdbb 814 /**
bcostm 1:ee089790cdbb 815 * @brief Sets new frequency.
bcostm 1:ee089790cdbb 816 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 817 * @param AudioFreq: Audio frequency used to play the audio stream.
bcostm 1:ee089790cdbb 818 * @retval 0 if correct communication, else wrong communication
bcostm 1:ee089790cdbb 819 */
bcostm 1:ee089790cdbb 820 uint32_t wm8994_SetFrequency(uint16_t DeviceAddr, uint32_t AudioFreq)
bcostm 1:ee089790cdbb 821 {
bcostm 1:ee089790cdbb 822 uint32_t counter = 0;
bcostm 1:ee089790cdbb 823
bcostm 1:ee089790cdbb 824 /* Clock Configurations */
bcostm 1:ee089790cdbb 825 switch (AudioFreq)
bcostm 1:ee089790cdbb 826 {
bcostm 1:ee089790cdbb 827 case AUDIO_FREQUENCY_8K:
bcostm 1:ee089790cdbb 828 /* AIF1 Sample Rate = 8 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 829 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0003);
bcostm 1:ee089790cdbb 830 break;
bcostm 1:ee089790cdbb 831
bcostm 1:ee089790cdbb 832 case AUDIO_FREQUENCY_16K:
bcostm 1:ee089790cdbb 833 /* AIF1 Sample Rate = 16 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 834 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0033);
bcostm 1:ee089790cdbb 835 break;
bcostm 1:ee089790cdbb 836
bcostm 1:ee089790cdbb 837 case AUDIO_FREQUENCY_48K:
bcostm 1:ee089790cdbb 838 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 839 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
bcostm 1:ee089790cdbb 840 break;
bcostm 1:ee089790cdbb 841
bcostm 1:ee089790cdbb 842 case AUDIO_FREQUENCY_96K:
bcostm 1:ee089790cdbb 843 /* AIF1 Sample Rate = 96 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 844 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x00A3);
bcostm 1:ee089790cdbb 845 break;
bcostm 1:ee089790cdbb 846
bcostm 1:ee089790cdbb 847 case AUDIO_FREQUENCY_11K:
bcostm 1:ee089790cdbb 848 /* AIF1 Sample Rate = 11.025 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 849 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0013);
bcostm 1:ee089790cdbb 850 break;
bcostm 1:ee089790cdbb 851
bcostm 1:ee089790cdbb 852 case AUDIO_FREQUENCY_22K:
bcostm 1:ee089790cdbb 853 /* AIF1 Sample Rate = 22.050 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 854 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0043);
bcostm 1:ee089790cdbb 855 break;
bcostm 1:ee089790cdbb 856
bcostm 1:ee089790cdbb 857 case AUDIO_FREQUENCY_44K:
bcostm 1:ee089790cdbb 858 /* AIF1 Sample Rate = 44.1 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 859 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0073);
bcostm 1:ee089790cdbb 860 break;
bcostm 1:ee089790cdbb 861
bcostm 1:ee089790cdbb 862 default:
bcostm 1:ee089790cdbb 863 /* AIF1 Sample Rate = 48 (KHz), ratio=256 */
bcostm 1:ee089790cdbb 864 counter += CODEC_IO_Write(DeviceAddr, 0x210, 0x0083);
bcostm 1:ee089790cdbb 865 break;
bcostm 1:ee089790cdbb 866 }
bcostm 1:ee089790cdbb 867 return counter;
bcostm 1:ee089790cdbb 868 }
bcostm 1:ee089790cdbb 869
bcostm 1:ee089790cdbb 870 /**
bcostm 1:ee089790cdbb 871 * @brief Resets wm8994 registers.
bcostm 1:ee089790cdbb 872 * @param DeviceAddr: Device address on communication Bus.
bcostm 1:ee089790cdbb 873 * @retval 0 if correct communication, else wrong communication
bcostm 1:ee089790cdbb 874 */
bcostm 1:ee089790cdbb 875 uint32_t wm8994_Reset(uint16_t DeviceAddr)
bcostm 1:ee089790cdbb 876 {
bcostm 1:ee089790cdbb 877 uint32_t counter = 0;
bcostm 1:ee089790cdbb 878
bcostm 1:ee089790cdbb 879 /* Reset Codec by writing in 0x0000 address register */
bcostm 1:ee089790cdbb 880 counter = CODEC_IO_Write(DeviceAddr, 0x0000, 0x0000);
bcostm 1:ee089790cdbb 881 outputEnabled = 0;
bcostm 1:ee089790cdbb 882 inputEnabled=0;
bcostm 1:ee089790cdbb 883
bcostm 1:ee089790cdbb 884 return counter;
bcostm 1:ee089790cdbb 885 }
bcostm 1:ee089790cdbb 886
bcostm 1:ee089790cdbb 887 /**
bcostm 1:ee089790cdbb 888 * @brief Writes/Read a single data.
bcostm 1:ee089790cdbb 889 * @param Addr: I2C address
bcostm 1:ee089790cdbb 890 * @param Reg: Reg address
bcostm 1:ee089790cdbb 891 * @param Value: Data to be written
bcostm 1:ee089790cdbb 892 * @retval None
bcostm 1:ee089790cdbb 893 */
bcostm 1:ee089790cdbb 894 static uint8_t CODEC_IO_Write(uint8_t Addr, uint16_t Reg, uint16_t Value)
bcostm 1:ee089790cdbb 895 {
bcostm 1:ee089790cdbb 896 uint32_t result = 0;
bcostm 1:ee089790cdbb 897
bcostm 1:ee089790cdbb 898 AUDIO_IO_Write(Addr, Reg, Value);
bcostm 1:ee089790cdbb 899
bcostm 1:ee089790cdbb 900 #ifdef VERIFY_WRITTENDATA
bcostm 1:ee089790cdbb 901 /* Verify that the data has been correctly written */
bcostm 1:ee089790cdbb 902 result = (AUDIO_IO_Read(Addr, Reg) == Value)? 0:1;
bcostm 1:ee089790cdbb 903 #endif /* VERIFY_WRITTENDATA */
bcostm 1:ee089790cdbb 904
bcostm 1:ee089790cdbb 905 return result;
bcostm 1:ee089790cdbb 906 }
bcostm 1:ee089790cdbb 907
bcostm 1:ee089790cdbb 908 /**
bcostm 1:ee089790cdbb 909 * @}
bcostm 1:ee089790cdbb 910 */
bcostm 1:ee089790cdbb 911
bcostm 1:ee089790cdbb 912 /**
bcostm 1:ee089790cdbb 913 * @}
bcostm 1:ee089790cdbb 914 */
bcostm 1:ee089790cdbb 915
bcostm 1:ee089790cdbb 916 /**
bcostm 1:ee089790cdbb 917 * @}
bcostm 1:ee089790cdbb 918 */
bcostm 1:ee089790cdbb 919
bcostm 1:ee089790cdbb 920 /**
bcostm 1:ee089790cdbb 921 * @}
bcostm 1:ee089790cdbb 922 */
bcostm 1:ee089790cdbb 923
bcostm 1:ee089790cdbb 924 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/