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stm32746g_discovery_sdram.c@5:5a395e126678, 2016-11-09 (annotated)

Committer:
bcostm
Date:
Wed Nov 09 18:26:13 2016 +0100
Revision:
5:5a395e126678
Parent:
0:c9112f0c67e3 
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bcostm 0:c9112f0c67e3 1 /**
bcostm 0:c9112f0c67e3 2 ******************************************************************************
bcostm 0:c9112f0c67e3 3 * @file stm32746g_discovery_sdram.c
bcostm 0:c9112f0c67e3 4 * @author MCD Application Team
bcostm 0:c9112f0c67e3 5 * @version V1.0.0
bcostm 0:c9112f0c67e3 6 * @date 25-June-2015
bcostm 0:c9112f0c67e3 7 * @brief This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
bcostm 0:c9112f0c67e3 8 * device mounted on STM32746G-Discovery board.
bcostm 0:c9112f0c67e3 9 @verbatim
bcostm 0:c9112f0c67e3 10 1. How To use this driver:
bcostm 0:c9112f0c67e3 11 --------------------------
bcostm 0:c9112f0c67e3 12 - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
bcostm 0:c9112f0c67e3 13 on STM32746G-Discovery board.
bcostm 0:c9112f0c67e3 14 - This driver does not need a specific component driver for the SDRAM device
bcostm 0:c9112f0c67e3 15 to be included with.
bcostm 0:c9112f0c67e3 16
bcostm 0:c9112f0c67e3 17 2. Driver description:
bcostm 0:c9112f0c67e3 18 ---------------------
bcostm 0:c9112f0c67e3 19 + Initialization steps:
bcostm 0:c9112f0c67e3 20 o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
bcostm 0:c9112f0c67e3 21 function includes the MSP layer hardware resources initialization and the
bcostm 0:c9112f0c67e3 22 FMC controller configuration to interface with the external SDRAM memory.
bcostm 0:c9112f0c67e3 23 o It contains the SDRAM initialization sequence to program the SDRAM external
bcostm 0:c9112f0c67e3 24 device using the function BSP_SDRAM_Initialization_sequence(). Note that this
bcostm 0:c9112f0c67e3 25 sequence is standard for all SDRAM devices, but can include some differences
bcostm 0:c9112f0c67e3 26 from a device to another. If it is the case, the right sequence should be
bcostm 0:c9112f0c67e3 27 implemented separately.
bcostm 0:c9112f0c67e3 28
bcostm 0:c9112f0c67e3 29 + SDRAM read/write operations
bcostm 0:c9112f0c67e3 30 o SDRAM external memory can be accessed with read/write operations once it is
bcostm 0:c9112f0c67e3 31 initialized.
bcostm 0:c9112f0c67e3 32 Read/write operation can be performed with AHB access using the functions
bcostm 0:c9112f0c67e3 33 BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
bcostm 0:c9112f0c67e3 34 BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
bcostm 0:c9112f0c67e3 35 o The AHB access is performed with 32-bit width transaction, the DMA transfer
bcostm 0:c9112f0c67e3 36 configuration is fixed at single (no burst) word transfer (see the
bcostm 0:c9112f0c67e3 37 SDRAM_MspInit() static function).
bcostm 0:c9112f0c67e3 38 o User can implement his own functions for read/write access with his desired
bcostm 0:c9112f0c67e3 39 configurations.
bcostm 0:c9112f0c67e3 40 o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
bcostm 0:c9112f0c67e3 41 is called in IRQ handler file, to serve the generated interrupt once the DMA
bcostm 0:c9112f0c67e3 42 transfer is complete.
bcostm 0:c9112f0c67e3 43 o You can send a command to the SDRAM device in runtime using the function
bcostm 0:c9112f0c67e3 44 BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
bcostm 0:c9112f0c67e3 45 the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
bcostm 0:c9112f0c67e3 46
bcostm 0:c9112f0c67e3 47 @endverbatim
bcostm 0:c9112f0c67e3 48 ******************************************************************************
bcostm 0:c9112f0c67e3 49 * @attention
bcostm 0:c9112f0c67e3 50 *
bcostm 0:c9112f0c67e3 51 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bcostm 0:c9112f0c67e3 52 *
bcostm 0:c9112f0c67e3 53 * Redistribution and use in source and binary forms, with or without modification,
bcostm 0:c9112f0c67e3 54 * are permitted provided that the following conditions are met:
bcostm 0:c9112f0c67e3 55 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 0:c9112f0c67e3 56 * this list of conditions and the following disclaimer.
bcostm 0:c9112f0c67e3 57 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 0:c9112f0c67e3 58 * this list of conditions and the following disclaimer in the documentation
bcostm 0:c9112f0c67e3 59 * and/or other materials provided with the distribution.
bcostm 0:c9112f0c67e3 60 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 0:c9112f0c67e3 61 * may be used to endorse or promote products derived from this software
bcostm 0:c9112f0c67e3 62 * without specific prior written permission.
bcostm 0:c9112f0c67e3 63 *
bcostm 0:c9112f0c67e3 64 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 0:c9112f0c67e3 65 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 0:c9112f0c67e3 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 0:c9112f0c67e3 67 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 0:c9112f0c67e3 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 0:c9112f0c67e3 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 0:c9112f0c67e3 70 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 0:c9112f0c67e3 71 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 0:c9112f0c67e3 72 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 0:c9112f0c67e3 73 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 0:c9112f0c67e3 74 *
bcostm 0:c9112f0c67e3 75 ******************************************************************************
bcostm 0:c9112f0c67e3 76 */
bcostm 0:c9112f0c67e3 77
bcostm 0:c9112f0c67e3 78 /* Includes ------------------------------------------------------------------*/
bcostm 0:c9112f0c67e3 79 #include "stm32746g_discovery_sdram.h"
bcostm 0:c9112f0c67e3 80
bcostm 5:5a395e126678 81 void wait_ms(int ms); // MBED to replace HAL_Delay function
bcostm 0:c9112f0c67e3 82
bcostm 0:c9112f0c67e3 83 /** @addtogroup BSP
bcostm 0:c9112f0c67e3 84 * @{
bcostm 0:c9112f0c67e3 85 */
bcostm 0:c9112f0c67e3 86
bcostm 0:c9112f0c67e3 87 /** @addtogroup STM32746G_DISCOVERY
bcostm 0:c9112f0c67e3 88 * @{
bcostm 0:c9112f0c67e3 89 */
bcostm 0:c9112f0c67e3 90
bcostm 0:c9112f0c67e3 91 /** @defgroup STM32746G_DISCOVERY_SDRAM STM32746G_DISCOVERY_SDRAM
bcostm 0:c9112f0c67e3 92 * @{
bcostm 0:c9112f0c67e3 93 */
bcostm 0:c9112f0c67e3 94
bcostm 0:c9112f0c67e3 95 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Types_Definitions STM32746G_DISCOVERY_SDRAM Private Types Definitions
bcostm 0:c9112f0c67e3 96 * @{
bcostm 0:c9112f0c67e3 97 */
bcostm 0:c9112f0c67e3 98 /**
bcostm 0:c9112f0c67e3 99 * @}
bcostm 0:c9112f0c67e3 100 */
bcostm 0:c9112f0c67e3 101
bcostm 0:c9112f0c67e3 102 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Defines STM32746G_DISCOVERY_SDRAM Private Defines
bcostm 0:c9112f0c67e3 103 * @{
bcostm 0:c9112f0c67e3 104 */
bcostm 0:c9112f0c67e3 105 /**
bcostm 0:c9112f0c67e3 106 * @}
bcostm 0:c9112f0c67e3 107 */
bcostm 0:c9112f0c67e3 108
bcostm 0:c9112f0c67e3 109 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Macros STM32746G_DISCOVERY_SDRAM Private Macros
bcostm 0:c9112f0c67e3 110 * @{
bcostm 0:c9112f0c67e3 111 */
bcostm 0:c9112f0c67e3 112 /**
bcostm 0:c9112f0c67e3 113 * @}
bcostm 0:c9112f0c67e3 114 */
bcostm 0:c9112f0c67e3 115
bcostm 0:c9112f0c67e3 116 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Variables STM32746G_DISCOVERY_SDRAM Private Variables
bcostm 0:c9112f0c67e3 117 * @{
bcostm 0:c9112f0c67e3 118 */
bcostm 0:c9112f0c67e3 119 static SDRAM_HandleTypeDef sdramHandle;
bcostm 0:c9112f0c67e3 120 static FMC_SDRAM_TimingTypeDef Timing;
bcostm 0:c9112f0c67e3 121 static FMC_SDRAM_CommandTypeDef Command;
bcostm 0:c9112f0c67e3 122 /**
bcostm 0:c9112f0c67e3 123 * @}
bcostm 0:c9112f0c67e3 124 */
bcostm 0:c9112f0c67e3 125
bcostm 0:c9112f0c67e3 126 /** @defgroup STM32746G_DISCOVERY_SDRAM_Private_Function_Prototypes STM32746G_DISCOVERY_SDRAM Private Function Prototypes
bcostm 0:c9112f0c67e3 127 * @{
bcostm 0:c9112f0c67e3 128 */
bcostm 0:c9112f0c67e3 129 /**
bcostm 0:c9112f0c67e3 130 * @}
bcostm 0:c9112f0c67e3 131 */
bcostm 0:c9112f0c67e3 132
bcostm 0:c9112f0c67e3 133 /** @defgroup STM32746G_DISCOVERY_SDRAM_Exported_Functions STM32746G_DISCOVERY_SDRAM Exported Functions
bcostm 0:c9112f0c67e3 134 * @{
bcostm 0:c9112f0c67e3 135 */
bcostm 0:c9112f0c67e3 136
bcostm 0:c9112f0c67e3 137 /**
bcostm 0:c9112f0c67e3 138 * @brief Initializes the SDRAM device.
bcostm 0:c9112f0c67e3 139 * @retval SDRAM status
bcostm 0:c9112f0c67e3 140 */
bcostm 0:c9112f0c67e3 141 uint8_t BSP_SDRAM_Init(void)
bcostm 0:c9112f0c67e3 142 {
bcostm 0:c9112f0c67e3 143 static uint8_t sdramstatus = SDRAM_ERROR;
bcostm 0:c9112f0c67e3 144 /* SDRAM device configuration */
bcostm 0:c9112f0c67e3 145 sdramHandle.Instance = FMC_SDRAM_DEVICE;
bcostm 0:c9112f0c67e3 146
bcostm 0:c9112f0c67e3 147 /* Timing configuration for 100Mhz as SD clock frequency (System clock is up to 200Mhz) */
bcostm 0:c9112f0c67e3 148 Timing.LoadToActiveDelay = 2;
bcostm 0:c9112f0c67e3 149 Timing.ExitSelfRefreshDelay = 7;
bcostm 0:c9112f0c67e3 150 Timing.SelfRefreshTime = 4;
bcostm 0:c9112f0c67e3 151 Timing.RowCycleDelay = 7;
bcostm 0:c9112f0c67e3 152 Timing.WriteRecoveryTime = 2;
bcostm 0:c9112f0c67e3 153 Timing.RPDelay = 2;
bcostm 0:c9112f0c67e3 154 Timing.RCDDelay = 2;
bcostm 0:c9112f0c67e3 155
bcostm 0:c9112f0c67e3 156 sdramHandle.Init.SDBank = FMC_SDRAM_BANK1;
bcostm 0:c9112f0c67e3 157 sdramHandle.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8;
bcostm 0:c9112f0c67e3 158 sdramHandle.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
bcostm 0:c9112f0c67e3 159 sdramHandle.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
bcostm 0:c9112f0c67e3 160 sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
bcostm 0:c9112f0c67e3 161 sdramHandle.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_2;
bcostm 0:c9112f0c67e3 162 sdramHandle.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
bcostm 0:c9112f0c67e3 163 sdramHandle.Init.SDClockPeriod = SDCLOCK_PERIOD;
bcostm 0:c9112f0c67e3 164 sdramHandle.Init.ReadBurst = FMC_SDRAM_RBURST_ENABLE;
bcostm 0:c9112f0c67e3 165 sdramHandle.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0;
bcostm 0:c9112f0c67e3 166
bcostm 0:c9112f0c67e3 167 /* SDRAM controller initialization */
bcostm 0:c9112f0c67e3 168
bcostm 0:c9112f0c67e3 169 BSP_SDRAM_MspInit(&sdramHandle, NULL); /* __weak function can be rewritten by the application */
bcostm 0:c9112f0c67e3 170
bcostm 0:c9112f0c67e3 171 if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
bcostm 0:c9112f0c67e3 172 {
bcostm 0:c9112f0c67e3 173 sdramstatus = SDRAM_ERROR;
bcostm 0:c9112f0c67e3 174 }
bcostm 0:c9112f0c67e3 175 else
bcostm 0:c9112f0c67e3 176 {
bcostm 0:c9112f0c67e3 177 sdramstatus = SDRAM_OK;
bcostm 0:c9112f0c67e3 178 }
bcostm 0:c9112f0c67e3 179
bcostm 0:c9112f0c67e3 180 /* SDRAM initialization sequence */
bcostm 0:c9112f0c67e3 181 BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
bcostm 0:c9112f0c67e3 182
bcostm 0:c9112f0c67e3 183 return sdramstatus;
bcostm 0:c9112f0c67e3 184 }
bcostm 0:c9112f0c67e3 185
bcostm 0:c9112f0c67e3 186 /**
bcostm 0:c9112f0c67e3 187 * @brief DeInitializes the SDRAM device.
bcostm 0:c9112f0c67e3 188 * @retval SDRAM status
bcostm 0:c9112f0c67e3 189 */
bcostm 0:c9112f0c67e3 190 uint8_t BSP_SDRAM_DeInit(void)
bcostm 0:c9112f0c67e3 191 {
bcostm 0:c9112f0c67e3 192 static uint8_t sdramstatus = SDRAM_ERROR;
bcostm 0:c9112f0c67e3 193 /* SDRAM device de-initialization */
bcostm 0:c9112f0c67e3 194 sdramHandle.Instance = FMC_SDRAM_DEVICE;
bcostm 0:c9112f0c67e3 195
bcostm 0:c9112f0c67e3 196 if(HAL_SDRAM_DeInit(&sdramHandle) != HAL_OK)
bcostm 0:c9112f0c67e3 197 {
bcostm 0:c9112f0c67e3 198 sdramstatus = SDRAM_ERROR;
bcostm 0:c9112f0c67e3 199 }
bcostm 0:c9112f0c67e3 200 else
bcostm 0:c9112f0c67e3 201 {
bcostm 0:c9112f0c67e3 202 sdramstatus = SDRAM_OK;
bcostm 0:c9112f0c67e3 203 }
bcostm 0:c9112f0c67e3 204
bcostm 0:c9112f0c67e3 205 /* SDRAM controller de-initialization */
bcostm 0:c9112f0c67e3 206 BSP_SDRAM_MspDeInit(&sdramHandle, NULL);
bcostm 0:c9112f0c67e3 207
bcostm 0:c9112f0c67e3 208 return sdramstatus;
bcostm 0:c9112f0c67e3 209 }
bcostm 0:c9112f0c67e3 210
bcostm 0:c9112f0c67e3 211 /**
bcostm 0:c9112f0c67e3 212 * @brief Programs the SDRAM device.
bcostm 0:c9112f0c67e3 213 * @param RefreshCount: SDRAM refresh counter value
bcostm 0:c9112f0c67e3 214 * @retval None
bcostm 0:c9112f0c67e3 215 */
bcostm 0:c9112f0c67e3 216 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
bcostm 0:c9112f0c67e3 217 {
bcostm 0:c9112f0c67e3 218 __IO uint32_t tmpmrd = 0;
bcostm 0:c9112f0c67e3 219
bcostm 0:c9112f0c67e3 220 /* Step 1: Configure a clock configuration enable command */
bcostm 0:c9112f0c67e3 221 Command.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
bcostm 0:c9112f0c67e3 222 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
bcostm 0:c9112f0c67e3 223 Command.AutoRefreshNumber = 1;
bcostm 0:c9112f0c67e3 224 Command.ModeRegisterDefinition = 0;
bcostm 0:c9112f0c67e3 225
bcostm 0:c9112f0c67e3 226 /* Send the command */
bcostm 0:c9112f0c67e3 227 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
bcostm 0:c9112f0c67e3 228
bcostm 0:c9112f0c67e3 229 /* Step 2: Insert 100 us minimum delay */
bcostm 0:c9112f0c67e3 230 /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
bcostm 5:5a395e126678 231 //HAL_Delay(1); // MBED
bcostm 5:5a395e126678 232 wait_ms(1); // MBED
bcostm 0:c9112f0c67e3 233
bcostm 0:c9112f0c67e3 234 /* Step 3: Configure a PALL (precharge all) command */
bcostm 0:c9112f0c67e3 235 Command.CommandMode = FMC_SDRAM_CMD_PALL;
bcostm 0:c9112f0c67e3 236 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
bcostm 0:c9112f0c67e3 237 Command.AutoRefreshNumber = 1;
bcostm 0:c9112f0c67e3 238 Command.ModeRegisterDefinition = 0;
bcostm 0:c9112f0c67e3 239
bcostm 0:c9112f0c67e3 240 /* Send the command */
bcostm 0:c9112f0c67e3 241 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
bcostm 0:c9112f0c67e3 242
bcostm 0:c9112f0c67e3 243 /* Step 4: Configure an Auto Refresh command */
bcostm 0:c9112f0c67e3 244 Command.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
bcostm 0:c9112f0c67e3 245 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
bcostm 0:c9112f0c67e3 246 Command.AutoRefreshNumber = 8;
bcostm 0:c9112f0c67e3 247 Command.ModeRegisterDefinition = 0;
bcostm 0:c9112f0c67e3 248
bcostm 0:c9112f0c67e3 249 /* Send the command */
bcostm 0:c9112f0c67e3 250 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
bcostm 0:c9112f0c67e3 251
bcostm 0:c9112f0c67e3 252 /* Step 5: Program the external memory mode register */
bcostm 0:c9112f0c67e3 253 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 |\
bcostm 0:c9112f0c67e3 254 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
bcostm 0:c9112f0c67e3 255 SDRAM_MODEREG_CAS_LATENCY_2 |\
bcostm 0:c9112f0c67e3 256 SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
bcostm 0:c9112f0c67e3 257 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
bcostm 0:c9112f0c67e3 258
bcostm 0:c9112f0c67e3 259 Command.CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
bcostm 0:c9112f0c67e3 260 Command.CommandTarget = FMC_SDRAM_CMD_TARGET_BANK1;
bcostm 0:c9112f0c67e3 261 Command.AutoRefreshNumber = 1;
bcostm 0:c9112f0c67e3 262 Command.ModeRegisterDefinition = tmpmrd;
bcostm 0:c9112f0c67e3 263
bcostm 0:c9112f0c67e3 264 /* Send the command */
bcostm 0:c9112f0c67e3 265 HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
bcostm 0:c9112f0c67e3 266
bcostm 0:c9112f0c67e3 267 /* Step 6: Set the refresh rate counter */
bcostm 0:c9112f0c67e3 268 /* Set the device refresh rate */
bcostm 0:c9112f0c67e3 269 HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
bcostm 0:c9112f0c67e3 270 }
bcostm 0:c9112f0c67e3 271
bcostm 0:c9112f0c67e3 272 /**
bcostm 0:c9112f0c67e3 273 * @brief Reads an amount of data from the SDRAM memory in polling mode.
bcostm 0:c9112f0c67e3 274 * @param uwStartAddress: Read start address
bcostm 0:c9112f0c67e3 275 * @param pData: Pointer to data to be read
bcostm 0:c9112f0c67e3 276 * @param uwDataSize: Size of read data from the memory
bcostm 0:c9112f0c67e3 277 * @retval SDRAM status
bcostm 0:c9112f0c67e3 278 */
bcostm 0:c9112f0c67e3 279 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
bcostm 0:c9112f0c67e3 280 {
bcostm 0:c9112f0c67e3 281 if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 0:c9112f0c67e3 282 {
bcostm 0:c9112f0c67e3 283 return SDRAM_ERROR;
bcostm 0:c9112f0c67e3 284 }
bcostm 0:c9112f0c67e3 285 else
bcostm 0:c9112f0c67e3 286 {
bcostm 0:c9112f0c67e3 287 return SDRAM_OK;
bcostm 0:c9112f0c67e3 288 }
bcostm 0:c9112f0c67e3 289 }
bcostm 0:c9112f0c67e3 290
bcostm 0:c9112f0c67e3 291 /**
bcostm 0:c9112f0c67e3 292 * @brief Reads an amount of data from the SDRAM memory in DMA mode.
bcostm 0:c9112f0c67e3 293 * @param uwStartAddress: Read start address
bcostm 0:c9112f0c67e3 294 * @param pData: Pointer to data to be read
bcostm 0:c9112f0c67e3 295 * @param uwDataSize: Size of read data from the memory
bcostm 0:c9112f0c67e3 296 * @retval SDRAM status
bcostm 0:c9112f0c67e3 297 */
bcostm 0:c9112f0c67e3 298 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
bcostm 0:c9112f0c67e3 299 {
bcostm 0:c9112f0c67e3 300 if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 0:c9112f0c67e3 301 {
bcostm 0:c9112f0c67e3 302 return SDRAM_ERROR;
bcostm 0:c9112f0c67e3 303 }
bcostm 0:c9112f0c67e3 304 else
bcostm 0:c9112f0c67e3 305 {
bcostm 0:c9112f0c67e3 306 return SDRAM_OK;
bcostm 0:c9112f0c67e3 307 }
bcostm 0:c9112f0c67e3 308 }
bcostm 0:c9112f0c67e3 309
bcostm 0:c9112f0c67e3 310 /**
bcostm 0:c9112f0c67e3 311 * @brief Writes an amount of data to the SDRAM memory in polling mode.
bcostm 0:c9112f0c67e3 312 * @param uwStartAddress: Write start address
bcostm 0:c9112f0c67e3 313 * @param pData: Pointer to data to be written
bcostm 0:c9112f0c67e3 314 * @param uwDataSize: Size of written data from the memory
bcostm 0:c9112f0c67e3 315 * @retval SDRAM status
bcostm 0:c9112f0c67e3 316 */
bcostm 0:c9112f0c67e3 317 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
bcostm 0:c9112f0c67e3 318 {
bcostm 0:c9112f0c67e3 319 if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 0:c9112f0c67e3 320 {
bcostm 0:c9112f0c67e3 321 return SDRAM_ERROR;
bcostm 0:c9112f0c67e3 322 }
bcostm 0:c9112f0c67e3 323 else
bcostm 0:c9112f0c67e3 324 {
bcostm 0:c9112f0c67e3 325 return SDRAM_OK;
bcostm 0:c9112f0c67e3 326 }
bcostm 0:c9112f0c67e3 327 }
bcostm 0:c9112f0c67e3 328
bcostm 0:c9112f0c67e3 329 /**
bcostm 0:c9112f0c67e3 330 * @brief Writes an amount of data to the SDRAM memory in DMA mode.
bcostm 0:c9112f0c67e3 331 * @param uwStartAddress: Write start address
bcostm 0:c9112f0c67e3 332 * @param pData: Pointer to data to be written
bcostm 0:c9112f0c67e3 333 * @param uwDataSize: Size of written data from the memory
bcostm 0:c9112f0c67e3 334 * @retval SDRAM status
bcostm 0:c9112f0c67e3 335 */
bcostm 0:c9112f0c67e3 336 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
bcostm 0:c9112f0c67e3 337 {
bcostm 0:c9112f0c67e3 338 if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
bcostm 0:c9112f0c67e3 339 {
bcostm 0:c9112f0c67e3 340 return SDRAM_ERROR;
bcostm 0:c9112f0c67e3 341 }
bcostm 0:c9112f0c67e3 342 else
bcostm 0:c9112f0c67e3 343 {
bcostm 0:c9112f0c67e3 344 return SDRAM_OK;
bcostm 0:c9112f0c67e3 345 }
bcostm 0:c9112f0c67e3 346 }
bcostm 0:c9112f0c67e3 347
bcostm 0:c9112f0c67e3 348 /**
bcostm 0:c9112f0c67e3 349 * @brief Sends command to the SDRAM bank.
bcostm 0:c9112f0c67e3 350 * @param SdramCmd: Pointer to SDRAM command structure
bcostm 0:c9112f0c67e3 351 * @retval SDRAM status
bcostm 0:c9112f0c67e3 352 */
bcostm 0:c9112f0c67e3 353 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
bcostm 0:c9112f0c67e3 354 {
bcostm 0:c9112f0c67e3 355 if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
bcostm 0:c9112f0c67e3 356 {
bcostm 0:c9112f0c67e3 357 return SDRAM_ERROR;
bcostm 0:c9112f0c67e3 358 }
bcostm 0:c9112f0c67e3 359 else
bcostm 0:c9112f0c67e3 360 {
bcostm 0:c9112f0c67e3 361 return SDRAM_OK;
bcostm 0:c9112f0c67e3 362 }
bcostm 0:c9112f0c67e3 363 }
bcostm 0:c9112f0c67e3 364
bcostm 0:c9112f0c67e3 365 /**
bcostm 0:c9112f0c67e3 366 * @brief Handles SDRAM DMA transfer interrupt request.
bcostm 0:c9112f0c67e3 367 * @retval None
bcostm 0:c9112f0c67e3 368 */
bcostm 0:c9112f0c67e3 369 void BSP_SDRAM_DMA_IRQHandler(void)
bcostm 0:c9112f0c67e3 370 {
bcostm 0:c9112f0c67e3 371 HAL_DMA_IRQHandler(sdramHandle.hdma);
bcostm 0:c9112f0c67e3 372 }
bcostm 0:c9112f0c67e3 373
bcostm 0:c9112f0c67e3 374 /**
bcostm 0:c9112f0c67e3 375 * @brief Initializes SDRAM MSP.
bcostm 0:c9112f0c67e3 376 * @param hsdram: SDRAM handle
bcostm 0:c9112f0c67e3 377 * @param Params
bcostm 0:c9112f0c67e3 378 * @retval None
bcostm 0:c9112f0c67e3 379 */
bcostm 0:c9112f0c67e3 380 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram, void *Params)
bcostm 0:c9112f0c67e3 381 {
bcostm 0:c9112f0c67e3 382 static DMA_HandleTypeDef dma_handle;
bcostm 0:c9112f0c67e3 383 GPIO_InitTypeDef gpio_init_structure;
bcostm 0:c9112f0c67e3 384
bcostm 0:c9112f0c67e3 385 /* Enable FMC clock */
bcostm 0:c9112f0c67e3 386 __HAL_RCC_FMC_CLK_ENABLE();
bcostm 0:c9112f0c67e3 387
bcostm 0:c9112f0c67e3 388 /* Enable chosen DMAx clock */
bcostm 0:c9112f0c67e3 389 __DMAx_CLK_ENABLE();
bcostm 0:c9112f0c67e3 390
bcostm 0:c9112f0c67e3 391 /* Enable GPIOs clock */
bcostm 0:c9112f0c67e3 392 __HAL_RCC_GPIOC_CLK_ENABLE();
bcostm 0:c9112f0c67e3 393 __HAL_RCC_GPIOD_CLK_ENABLE();
bcostm 0:c9112f0c67e3 394 __HAL_RCC_GPIOE_CLK_ENABLE();
bcostm 0:c9112f0c67e3 395 __HAL_RCC_GPIOF_CLK_ENABLE();
bcostm 0:c9112f0c67e3 396 __HAL_RCC_GPIOG_CLK_ENABLE();
bcostm 0:c9112f0c67e3 397 __HAL_RCC_GPIOH_CLK_ENABLE();
bcostm 0:c9112f0c67e3 398
bcostm 0:c9112f0c67e3 399 /* Common GPIO configuration */
bcostm 0:c9112f0c67e3 400 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
bcostm 0:c9112f0c67e3 401 gpio_init_structure.Pull = GPIO_PULLUP;
bcostm 0:c9112f0c67e3 402 gpio_init_structure.Speed = GPIO_SPEED_FAST;
bcostm 0:c9112f0c67e3 403 gpio_init_structure.Alternate = GPIO_AF12_FMC;
bcostm 0:c9112f0c67e3 404
bcostm 0:c9112f0c67e3 405 /* GPIOC configuration */
bcostm 0:c9112f0c67e3 406 gpio_init_structure.Pin = GPIO_PIN_3;
bcostm 0:c9112f0c67e3 407 HAL_GPIO_Init(GPIOC, &gpio_init_structure);
bcostm 0:c9112f0c67e3 408
bcostm 0:c9112f0c67e3 409 /* GPIOD configuration */
bcostm 0:c9112f0c67e3 410 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 |
bcostm 0:c9112f0c67e3 411 GPIO_PIN_10 | GPIO_PIN_14 | GPIO_PIN_15;
bcostm 0:c9112f0c67e3 412 HAL_GPIO_Init(GPIOD, &gpio_init_structure);
bcostm 0:c9112f0c67e3 413
bcostm 0:c9112f0c67e3 414 /* GPIOE configuration */
bcostm 0:c9112f0c67e3 415 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
bcostm 0:c9112f0c67e3 416 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
bcostm 0:c9112f0c67e3 417 GPIO_PIN_15;
bcostm 0:c9112f0c67e3 418 HAL_GPIO_Init(GPIOE, &gpio_init_structure);
bcostm 0:c9112f0c67e3 419
bcostm 0:c9112f0c67e3 420 /* GPIOF configuration */
bcostm 0:c9112f0c67e3 421 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
bcostm 0:c9112f0c67e3 422 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
bcostm 0:c9112f0c67e3 423 GPIO_PIN_15;
bcostm 0:c9112f0c67e3 424 HAL_GPIO_Init(GPIOF, &gpio_init_structure);
bcostm 0:c9112f0c67e3 425
bcostm 0:c9112f0c67e3 426 /* GPIOG configuration */
bcostm 0:c9112f0c67e3 427 gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
bcostm 0:c9112f0c67e3 428 GPIO_PIN_15;
bcostm 0:c9112f0c67e3 429 HAL_GPIO_Init(GPIOG, &gpio_init_structure);
bcostm 0:c9112f0c67e3 430
bcostm 0:c9112f0c67e3 431 /* GPIOH configuration */
bcostm 0:c9112f0c67e3 432 gpio_init_structure.Pin = GPIO_PIN_3 | GPIO_PIN_5;
bcostm 0:c9112f0c67e3 433 HAL_GPIO_Init(GPIOH, &gpio_init_structure);
bcostm 0:c9112f0c67e3 434
bcostm 0:c9112f0c67e3 435 /* Configure common DMA parameters */
bcostm 0:c9112f0c67e3 436 dma_handle.Init.Channel = SDRAM_DMAx_CHANNEL;
bcostm 0:c9112f0c67e3 437 dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
bcostm 0:c9112f0c67e3 438 dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
bcostm 0:c9112f0c67e3 439 dma_handle.Init.MemInc = DMA_MINC_ENABLE;
bcostm 0:c9112f0c67e3 440 dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
bcostm 0:c9112f0c67e3 441 dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
bcostm 0:c9112f0c67e3 442 dma_handle.Init.Mode = DMA_NORMAL;
bcostm 0:c9112f0c67e3 443 dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
bcostm 0:c9112f0c67e3 444 dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
bcostm 0:c9112f0c67e3 445 dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
bcostm 0:c9112f0c67e3 446 dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
bcostm 0:c9112f0c67e3 447 dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
bcostm 0:c9112f0c67e3 448
bcostm 0:c9112f0c67e3 449 dma_handle.Instance = SDRAM_DMAx_STREAM;
bcostm 0:c9112f0c67e3 450
bcostm 0:c9112f0c67e3 451 /* Associate the DMA handle */
bcostm 0:c9112f0c67e3 452 __HAL_LINKDMA(hsdram, hdma, dma_handle);
bcostm 0:c9112f0c67e3 453
bcostm 0:c9112f0c67e3 454 /* Deinitialize the stream for new transfer */
bcostm 0:c9112f0c67e3 455 HAL_DMA_DeInit(&dma_handle);
bcostm 0:c9112f0c67e3 456
bcostm 0:c9112f0c67e3 457 /* Configure the DMA stream */
bcostm 0:c9112f0c67e3 458 HAL_DMA_Init(&dma_handle);
bcostm 0:c9112f0c67e3 459
bcostm 0:c9112f0c67e3 460 /* NVIC configuration for DMA transfer complete interrupt */
bcostm 0:c9112f0c67e3 461 HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
bcostm 0:c9112f0c67e3 462 HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
bcostm 0:c9112f0c67e3 463 }
bcostm 0:c9112f0c67e3 464
bcostm 0:c9112f0c67e3 465 /**
bcostm 0:c9112f0c67e3 466 * @brief DeInitializes SDRAM MSP.
bcostm 0:c9112f0c67e3 467 * @param hsdram: SDRAM handle
bcostm 0:c9112f0c67e3 468 * @param Params
bcostm 0:c9112f0c67e3 469 * @retval None
bcostm 0:c9112f0c67e3 470 */
bcostm 0:c9112f0c67e3 471 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram, void *Params)
bcostm 0:c9112f0c67e3 472 {
bcostm 0:c9112f0c67e3 473 static DMA_HandleTypeDef dma_handle;
bcostm 0:c9112f0c67e3 474
bcostm 0:c9112f0c67e3 475 /* Disable NVIC configuration for DMA interrupt */
bcostm 0:c9112f0c67e3 476 HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
bcostm 0:c9112f0c67e3 477
bcostm 0:c9112f0c67e3 478 /* Deinitialize the stream for new transfer */
bcostm 0:c9112f0c67e3 479 dma_handle.Instance = SDRAM_DMAx_STREAM;
bcostm 0:c9112f0c67e3 480 HAL_DMA_DeInit(&dma_handle);
bcostm 0:c9112f0c67e3 481
bcostm 0:c9112f0c67e3 482 /* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications
bcostm 0:c9112f0c67e3 483 by surcharging this __weak function */
bcostm 0:c9112f0c67e3 484 }
bcostm 0:c9112f0c67e3 485
bcostm 0:c9112f0c67e3 486 /**
bcostm 0:c9112f0c67e3 487 * @}
bcostm 0:c9112f0c67e3 488 */
bcostm 0:c9112f0c67e3 489
bcostm 0:c9112f0c67e3 490 /**
bcostm 0:c9112f0c67e3 491 * @}
bcostm 0:c9112f0c67e3 492 */
bcostm 0:c9112f0c67e3 493
bcostm 0:c9112f0c67e3 494 /**
bcostm 0:c9112f0c67e3 495 * @}
bcostm 0:c9112f0c67e3 496 */
bcostm 0:c9112f0c67e3 497
bcostm 0:c9112f0c67e3 498 /**
bcostm 0:c9112f0c67e3 499 * @}
bcostm 0:c9112f0c67e3 500 */
bcostm 0:c9112f0c67e3 501
bcostm 0:c9112f0c67e3 502 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/