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iNEMO inertial module: 3D accelerometer and 3D gyroscope.
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Dependents: X_NUCLEO_IKS01A3 X_NUCLEO_IKS01A3
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lsm6dso_reg.h
00001 /* 00002 ****************************************************************************** 00003 * @file lsm6dso_reg.h 00004 * @author Sensors Software Solution Team 00005 * @brief This file contains all the functions prototypes for the 00006 * lsm6dso_reg.c driver. 00007 ****************************************************************************** 00008 * @attention 00009 * 00010 * <h2><center>© Copyright (c) 2020 STMicroelectronics. 00011 * All rights reserved.</center></h2> 00012 * 00013 * This software component is licensed by ST under BSD 3-Clause license, 00014 * the "License"; You may not use this file except in compliance with the 00015 * License. You may obtain a copy of the License at: 00016 * opensource.org/licenses/BSD-3-Clause 00017 * 00018 ****************************************************************************** 00019 */ 00020 00021 /* Define to prevent recursive inclusion -------------------------------------*/ 00022 #ifndef LSM6DSO_REGS_H 00023 #define LSM6DSO_REGS_H 00024 00025 #ifdef __cplusplus 00026 extern "C" { 00027 #endif 00028 00029 /* Includes ------------------------------------------------------------------*/ 00030 #include <stdint.h> 00031 #include <stddef.h> 00032 #include <math.h> 00033 00034 /** @addtogroup LSM6DSO 00035 * @{ 00036 * 00037 */ 00038 00039 /** @defgroup STMicroelectronics sensors common types 00040 * @{ 00041 * 00042 */ 00043 00044 #ifndef MEMS_SHARED_TYPES 00045 #define MEMS_SHARED_TYPES 00046 00047 /** 00048 * @defgroup axisXbitXX_t 00049 * @brief These unions are useful to represent different sensors data type. 00050 * These unions are not need by the driver. 00051 * 00052 * REMOVING the unions you are compliant with: 00053 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 00054 * 00055 * @{ 00056 * 00057 */ 00058 00059 typedef union { 00060 int16_t i16bit[3]; 00061 uint8_t u8bit[6]; 00062 } axis3bit16_t; 00063 00064 typedef union { 00065 int16_t i16bit; 00066 uint8_t u8bit[2]; 00067 } axis1bit16_t; 00068 00069 typedef union { 00070 int32_t i32bit[3]; 00071 uint8_t u8bit[12]; 00072 } axis3bit32_t; 00073 00074 typedef union { 00075 int32_t i32bit; 00076 uint8_t u8bit[4]; 00077 } axis1bit32_t; 00078 00079 /** 00080 * @} 00081 * 00082 */ 00083 00084 typedef struct { 00085 uint8_t bit0 : 1; 00086 uint8_t bit1 : 1; 00087 uint8_t bit2 : 1; 00088 uint8_t bit3 : 1; 00089 uint8_t bit4 : 1; 00090 uint8_t bit5 : 1; 00091 uint8_t bit6 : 1; 00092 uint8_t bit7 : 1; 00093 } bitwise_t; 00094 00095 #define PROPERTY_DISABLE (0U) 00096 #define PROPERTY_ENABLE (1U) 00097 00098 #endif /* MEMS_SHARED_TYPES */ 00099 00100 #ifndef MEMS_UCF_SHARED_TYPES 00101 #define MEMS_UCF_SHARED_TYPES 00102 00103 /** @defgroup Generic address-data structure definition 00104 * @brief This structure is useful to load a predefined configuration 00105 * of a sensor. 00106 * You can create a sensor configuration by your own or using 00107 * Unico / Unicleo tools available on STMicroelectronics 00108 * web site. 00109 * 00110 * @{ 00111 * 00112 */ 00113 00114 typedef struct { 00115 uint8_t address; 00116 uint8_t data; 00117 } ucf_line_t; 00118 00119 /** 00120 * @} 00121 * 00122 */ 00123 00124 #endif /* MEMS_UCF_SHARED_TYPES */ 00125 00126 /** 00127 * @} 00128 * 00129 */ 00130 00131 /** @addtogroup LSM6DSO_Interfaces_Functions 00132 * @brief This section provide a set of functions used to read and 00133 * write a generic register of the device. 00134 * MANDATORY: return 0 -> no Error. 00135 * @{ 00136 * 00137 */ 00138 00139 typedef int32_t (*lsm6dso_write_ptr)(void *, uint8_t, uint8_t *, uint16_t); 00140 typedef int32_t (*lsm6dso_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 00141 00142 typedef struct { 00143 /** Component mandatory fields **/ 00144 lsm6dso_write_ptr write_reg; 00145 lsm6dso_read_ptr read_reg; 00146 /** Customizable optional pointer **/ 00147 void *handle; 00148 } lsm6dso_ctx_t; 00149 00150 /** 00151 * @} 00152 * 00153 */ 00154 00155 /** @defgroup LSM6DSO_Infos 00156 * @{ 00157 * 00158 */ 00159 00160 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 00161 #define LSM6DSO_I2C_ADD_L 0xD5 00162 #define LSM6DSO_I2C_ADD_H 0xD7 00163 00164 /** Device Identification (Who am I) **/ 00165 #define LSM6DSO_ID 0x6C 00166 00167 /** 00168 * @} 00169 * 00170 */ 00171 00172 #define LSM6DSO_FUNC_CFG_ACCESS 0x01U 00173 typedef struct { 00174 uint8_t not_used_01 : 6; 00175 uint8_t reg_access : 2; /* shub_reg_access + func_cfg_access */ 00176 } lsm6dso_func_cfg_access_t; 00177 00178 #define LSM6DSO_PIN_CTRL 0x02U 00179 typedef struct { 00180 uint8_t not_used_01 : 6; 00181 uint8_t sdo_pu_en : 1; 00182 uint8_t ois_pu_dis : 1; 00183 } lsm6dso_pin_ctrl_t; 00184 00185 #define LSM6DSO_FIFO_CTRL1 0x07U 00186 typedef struct { 00187 uint8_t wtm : 8; 00188 } lsm6dso_fifo_ctrl1_t; 00189 00190 #define LSM6DSO_FIFO_CTRL2 0x08U 00191 typedef struct { 00192 uint8_t wtm : 1; 00193 uint8_t uncoptr_rate : 2; 00194 uint8_t not_used_01 : 1; 00195 uint8_t odrchg_en : 1; 00196 uint8_t not_used_02 : 1; 00197 uint8_t fifo_compr_rt_en : 1; 00198 uint8_t stop_on_wtm : 1; 00199 } lsm6dso_fifo_ctrl2_t; 00200 00201 #define LSM6DSO_FIFO_CTRL3 0x09U 00202 typedef struct { 00203 uint8_t bdr_xl : 4; 00204 uint8_t bdr_gy : 4; 00205 } lsm6dso_fifo_ctrl3_t; 00206 00207 #define LSM6DSO_FIFO_CTRL4 0x0AU 00208 typedef struct { 00209 uint8_t fifo_mode : 3; 00210 uint8_t not_used_01 : 1; 00211 uint8_t odr_t_batch : 2; 00212 uint8_t odr_ts_batch : 2; 00213 } lsm6dso_fifo_ctrl4_t; 00214 00215 #define LSM6DSO_COUNTER_BDR_REG1 0x0BU 00216 typedef struct { 00217 uint8_t cnt_bdr_th : 3; 00218 uint8_t not_used_01 : 2; 00219 uint8_t trig_counter_bdr : 1; 00220 uint8_t rst_counter_bdr : 1; 00221 uint8_t dataready_pulsed : 1; 00222 } lsm6dso_counter_bdr_reg1_t; 00223 00224 #define LSM6DSO_COUNTER_BDR_REG2 0x0CU 00225 typedef struct { 00226 uint8_t cnt_bdr_th : 8; 00227 } lsm6dso_counter_bdr_reg2_t; 00228 00229 #define LSM6DSO_INT1_CTRL 0x0D 00230 typedef struct { 00231 uint8_t int1_drdy_xl : 1; 00232 uint8_t int1_drdy_g : 1; 00233 uint8_t int1_boot : 1; 00234 uint8_t int1_fifo_th : 1; 00235 uint8_t int1_fifo_ovr : 1; 00236 uint8_t int1_fifo_full : 1; 00237 uint8_t int1_cnt_bdr : 1; 00238 uint8_t den_drdy_flag : 1; 00239 } lsm6dso_int1_ctrl_t; 00240 00241 #define LSM6DSO_INT2_CTRL 0x0EU 00242 typedef struct { 00243 uint8_t int2_drdy_xl : 1; 00244 uint8_t int2_drdy_g : 1; 00245 uint8_t int2_drdy_temp : 1; 00246 uint8_t int2_fifo_th : 1; 00247 uint8_t int2_fifo_ovr : 1; 00248 uint8_t int2_fifo_full : 1; 00249 uint8_t int2_cnt_bdr : 1; 00250 uint8_t not_used_01 : 1; 00251 } lsm6dso_int2_ctrl_t; 00252 00253 #define LSM6DSO_WHO_AM_I 0x0FU 00254 #define LSM6DSO_CTRL1_XL 0x10U 00255 typedef struct { 00256 uint8_t not_used_01 : 1; 00257 uint8_t lpf2_xl_en : 1; 00258 uint8_t fs_xl : 2; 00259 uint8_t odr_xl : 4; 00260 } lsm6dso_ctrl1_xl_t; 00261 00262 #define LSM6DSO_CTRL2_G 0x11U 00263 typedef struct { 00264 uint8_t not_used_01 : 1; 00265 uint8_t fs_g : 3; /* fs_125 + fs_g */ 00266 uint8_t odr_g : 4; 00267 } lsm6dso_ctrl2_g_t; 00268 00269 #define LSM6DSO_CTRL3_C 0x12U 00270 typedef struct { 00271 uint8_t sw_reset : 1; 00272 uint8_t not_used_01 : 1; 00273 uint8_t if_inc : 1; 00274 uint8_t sim : 1; 00275 uint8_t pp_od : 1; 00276 uint8_t h_lactive : 1; 00277 uint8_t bdu : 1; 00278 uint8_t boot : 1; 00279 } lsm6dso_ctrl3_c_t; 00280 00281 #define LSM6DSO_CTRL4_C 0x13U 00282 typedef struct { 00283 uint8_t not_used_01 : 1; 00284 uint8_t lpf1_sel_g : 1; 00285 uint8_t i2c_disable : 1; 00286 uint8_t drdy_mask : 1; 00287 uint8_t not_used_02 : 1; 00288 uint8_t int2_on_int1 : 1; 00289 uint8_t sleep_g : 1; 00290 uint8_t not_used_03 : 1; 00291 } lsm6dso_ctrl4_c_t; 00292 00293 #define LSM6DSO_CTRL5_C 0x14U 00294 typedef struct { 00295 uint8_t st_xl : 2; 00296 uint8_t st_g : 2; 00297 uint8_t not_used_01 : 1; 00298 uint8_t rounding : 2; 00299 uint8_t xl_ulp_en : 1; 00300 } lsm6dso_ctrl5_c_t; 00301 00302 #define LSM6DSO_CTRL6_C 0x15U 00303 typedef struct { 00304 uint8_t ftype : 3; 00305 uint8_t usr_off_w : 1; 00306 uint8_t xl_hm_mode : 1; 00307 uint8_t den_mode : 3; /* trig_en + lvl1_en + lvl2_en */ 00308 } lsm6dso_ctrl6_c_t; 00309 00310 #define LSM6DSO_CTRL7_G 0x16U 00311 typedef struct { 00312 uint8_t ois_on : 1; 00313 uint8_t usr_off_on_out : 1; 00314 uint8_t ois_on_en : 1; 00315 uint8_t not_used_01 : 1; 00316 uint8_t hpm_g : 2; 00317 uint8_t hp_en_g : 1; 00318 uint8_t g_hm_mode : 1; 00319 } lsm6dso_ctrl7_g_t; 00320 00321 #define LSM6DSO_CTRL8_XL 0x17U 00322 typedef struct { 00323 uint8_t low_pass_on_6d : 1; 00324 uint8_t xl_fs_mode : 1; 00325 uint8_t hp_slope_xl_en : 1; 00326 uint8_t fastsettl_mode_xl : 1; 00327 uint8_t hp_ref_mode_xl : 1; 00328 uint8_t hpcf_xl : 3; 00329 } lsm6dso_ctrl8_xl_t; 00330 00331 #define LSM6DSO_CTRL9_XL 0x18U 00332 typedef struct { 00333 uint8_t not_used_01 : 1; 00334 uint8_t i3c_disable : 1; 00335 uint8_t den_lh : 1; 00336 uint8_t den_xl_g : 2; /* den_xl_en + den_xl_g */ 00337 uint8_t den_z : 1; 00338 uint8_t den_y : 1; 00339 uint8_t den_x : 1; 00340 } lsm6dso_ctrl9_xl_t; 00341 00342 #define LSM6DSO_CTRL10_C 0x19U 00343 typedef struct { 00344 uint8_t not_used_01 : 5; 00345 uint8_t timestamp_en : 1; 00346 uint8_t not_used_02 : 2; 00347 } lsm6dso_ctrl10_c_t; 00348 00349 #define LSM6DSO_ALL_INT_SRC 0x1AU 00350 typedef struct { 00351 uint8_t ff_ia : 1; 00352 uint8_t wu_ia : 1; 00353 uint8_t single_tap : 1; 00354 uint8_t double_tap : 1; 00355 uint8_t d6d_ia : 1; 00356 uint8_t sleep_change_ia : 1; 00357 uint8_t not_used_01 : 1; 00358 uint8_t timestamp_endcount : 1; 00359 } lsm6dso_all_int_src_t; 00360 00361 #define LSM6DSO_WAKE_UP_SRC 0x1BU 00362 typedef struct { 00363 uint8_t z_wu : 1; 00364 uint8_t y_wu : 1; 00365 uint8_t x_wu : 1; 00366 uint8_t wu_ia : 1; 00367 uint8_t sleep_state : 1; 00368 uint8_t ff_ia : 1; 00369 uint8_t sleep_change_ia : 1; 00370 uint8_t not_used_01 : 1; 00371 } lsm6dso_wake_up_src_t; 00372 00373 #define LSM6DSO_TAP_SRC 0x1CU 00374 typedef struct { 00375 uint8_t z_tap : 1; 00376 uint8_t y_tap : 1; 00377 uint8_t x_tap : 1; 00378 uint8_t tap_sign : 1; 00379 uint8_t double_tap : 1; 00380 uint8_t single_tap : 1; 00381 uint8_t tap_ia : 1; 00382 uint8_t not_used_02 : 1; 00383 } lsm6dso_tap_src_t; 00384 00385 #define LSM6DSO_D6D_SRC 0x1DU 00386 typedef struct { 00387 uint8_t xl : 1; 00388 uint8_t xh : 1; 00389 uint8_t yl : 1; 00390 uint8_t yh : 1; 00391 uint8_t zl : 1; 00392 uint8_t zh : 1; 00393 uint8_t d6d_ia : 1; 00394 uint8_t den_drdy : 1; 00395 } lsm6dso_d6d_src_t; 00396 00397 #define LSM6DSO_STATUS_REG 0x1EU 00398 typedef struct { 00399 uint8_t xlda : 1; 00400 uint8_t gda : 1; 00401 uint8_t tda : 1; 00402 uint8_t not_used_01 : 5; 00403 } lsm6dso_status_reg_t; 00404 00405 #define LSM6DSO_STATUS_SPIAUX 0x1EU 00406 typedef struct { 00407 uint8_t xlda : 1; 00408 uint8_t gda : 1; 00409 uint8_t gyro_settling : 1; 00410 uint8_t not_used_01 : 5; 00411 } lsm6dso_status_spiaux_t; 00412 00413 #define LSM6DSO_OUT_TEMP_L 0x20U 00414 #define LSM6DSO_OUT_TEMP_H 0x21U 00415 #define LSM6DSO_OUTX_L_G 0x22U 00416 #define LSM6DSO_OUTX_H_G 0x23U 00417 #define LSM6DSO_OUTY_L_G 0x24U 00418 #define LSM6DSO_OUTY_H_G 0x25U 00419 #define LSM6DSO_OUTZ_L_G 0x26U 00420 #define LSM6DSO_OUTZ_H_G 0x27U 00421 #define LSM6DSO_OUTX_L_A 0x28U 00422 #define LSM6DSO_OUTX_H_A 0x29U 00423 #define LSM6DSO_OUTY_L_A 0x2AU 00424 #define LSM6DSO_OUTY_H_A 0x2BU 00425 #define LSM6DSO_OUTZ_L_A 0x2CU 00426 #define LSM6DSO_OUTZ_H_A 0x2DU 00427 #define LSM6DSO_EMB_FUNC_STATUS_MAINPAGE 0x35U 00428 typedef struct { 00429 uint8_t not_used_01 : 3; 00430 uint8_t is_step_det : 1; 00431 uint8_t is_tilt : 1; 00432 uint8_t is_sigmot : 1; 00433 uint8_t not_used_02 : 1; 00434 uint8_t is_fsm_lc : 1; 00435 } lsm6dso_emb_func_status_mainpage_t; 00436 00437 #define LSM6DSO_FSM_STATUS_A_MAINPAGE 0x36U 00438 typedef struct { 00439 uint8_t is_fsm1 : 1; 00440 uint8_t is_fsm2 : 1; 00441 uint8_t is_fsm3 : 1; 00442 uint8_t is_fsm4 : 1; 00443 uint8_t is_fsm5 : 1; 00444 uint8_t is_fsm6 : 1; 00445 uint8_t is_fsm7 : 1; 00446 uint8_t is_fsm8 : 1; 00447 } lsm6dso_fsm_status_a_mainpage_t; 00448 00449 #define LSM6DSO_FSM_STATUS_B_MAINPAGE 0x37U 00450 typedef struct { 00451 uint8_t is_fsm9 : 1; 00452 uint8_t is_fsm10 : 1; 00453 uint8_t is_fsm11 : 1; 00454 uint8_t is_fsm12 : 1; 00455 uint8_t is_fsm13 : 1; 00456 uint8_t is_fsm14 : 1; 00457 uint8_t is_fsm15 : 1; 00458 uint8_t is_fsm16 : 1; 00459 } lsm6dso_fsm_status_b_mainpage_t; 00460 00461 #define LSM6DSO_STATUS_MASTER_MAINPAGE 0x39U 00462 typedef struct { 00463 uint8_t sens_hub_endop : 1; 00464 uint8_t not_used_01 : 2; 00465 uint8_t slave0_nack : 1; 00466 uint8_t slave1_nack : 1; 00467 uint8_t slave2_nack : 1; 00468 uint8_t slave3_nack : 1; 00469 uint8_t wr_once_done : 1; 00470 } lsm6dso_status_master_mainpage_t; 00471 00472 #define LSM6DSO_FIFO_STATUS1 0x3AU 00473 typedef struct { 00474 uint8_t diff_fifo : 8; 00475 } lsm6dso_fifo_status1_t; 00476 00477 #define LSM6DSO_FIFO_STATUS2 0x3B 00478 typedef struct { 00479 uint8_t diff_fifo : 2; 00480 uint8_t not_used_01 : 1; 00481 uint8_t over_run_latched : 1; 00482 uint8_t counter_bdr_ia : 1; 00483 uint8_t fifo_full_ia : 1; 00484 uint8_t fifo_ovr_ia : 1; 00485 uint8_t fifo_wtm_ia : 1; 00486 } lsm6dso_fifo_status2_t; 00487 00488 #define LSM6DSO_TIMESTAMP0 0x40U 00489 #define LSM6DSO_TIMESTAMP1 0x41U 00490 #define LSM6DSO_TIMESTAMP2 0x42U 00491 #define LSM6DSO_TIMESTAMP3 0x43U 00492 #define LSM6DSO_TAP_CFG0 0x56U 00493 typedef struct { 00494 uint8_t lir : 1; 00495 uint8_t tap_z_en : 1; 00496 uint8_t tap_y_en : 1; 00497 uint8_t tap_x_en : 1; 00498 uint8_t slope_fds : 1; 00499 uint8_t sleep_status_on_int : 1; 00500 uint8_t int_clr_on_read : 1; 00501 uint8_t not_used_01 : 1; 00502 } lsm6dso_tap_cfg0_t; 00503 00504 #define LSM6DSO_TAP_CFG1 0x57U 00505 typedef struct { 00506 uint8_t tap_ths_x : 5; 00507 uint8_t tap_priority : 3; 00508 } lsm6dso_tap_cfg1_t; 00509 00510 #define LSM6DSO_TAP_CFG2 0x58U 00511 typedef struct { 00512 uint8_t tap_ths_y : 5; 00513 uint8_t inact_en : 2; 00514 uint8_t interrupts_enable : 1; 00515 } lsm6dso_tap_cfg2_t; 00516 00517 #define LSM6DSO_TAP_THS_6D 0x59U 00518 typedef struct { 00519 uint8_t tap_ths_z : 5; 00520 uint8_t sixd_ths : 2; 00521 uint8_t d4d_en : 1; 00522 } lsm6dso_tap_ths_6d_t; 00523 00524 #define LSM6DSO_INT_DUR2 0x5AU 00525 typedef struct { 00526 uint8_t shock : 2; 00527 uint8_t quiet : 2; 00528 uint8_t dur : 4; 00529 } lsm6dso_int_dur2_t; 00530 00531 #define LSM6DSO_WAKE_UP_THS 0x5BU 00532 typedef struct { 00533 uint8_t wk_ths : 6; 00534 uint8_t usr_off_on_wu : 1; 00535 uint8_t single_double_tap : 1; 00536 } lsm6dso_wake_up_ths_t; 00537 00538 #define LSM6DSO_WAKE_UP_DUR 0x5CU 00539 typedef struct { 00540 uint8_t sleep_dur : 4; 00541 uint8_t wake_ths_w : 1; 00542 uint8_t wake_dur : 2; 00543 uint8_t ff_dur : 1; 00544 } lsm6dso_wake_up_dur_t; 00545 00546 #define LSM6DSO_FREE_FALL 0x5DU 00547 typedef struct { 00548 uint8_t ff_ths : 3; 00549 uint8_t ff_dur : 5; 00550 } lsm6dso_free_fall_t; 00551 00552 #define LSM6DSO_MD1_CFG 0x5EU 00553 typedef struct { 00554 uint8_t int1_shub : 1; 00555 uint8_t int1_emb_func : 1; 00556 uint8_t int1_6d : 1; 00557 uint8_t int1_double_tap : 1; 00558 uint8_t int1_ff : 1; 00559 uint8_t int1_wu : 1; 00560 uint8_t int1_single_tap : 1; 00561 uint8_t int1_sleep_change : 1; 00562 } lsm6dso_md1_cfg_t; 00563 00564 #define LSM6DSO_MD2_CFG 0x5FU 00565 typedef struct { 00566 uint8_t int2_timestamp : 1; 00567 uint8_t int2_emb_func : 1; 00568 uint8_t int2_6d : 1; 00569 uint8_t int2_double_tap : 1; 00570 uint8_t int2_ff : 1; 00571 uint8_t int2_wu : 1; 00572 uint8_t int2_single_tap : 1; 00573 uint8_t int2_sleep_change : 1; 00574 } lsm6dso_md2_cfg_t; 00575 00576 #define LSM6DSO_I3C_BUS_AVB 0x62U 00577 typedef struct { 00578 uint8_t pd_dis_int1 : 1; 00579 uint8_t not_used_01 : 2; 00580 uint8_t i3c_bus_avb_sel : 2; 00581 uint8_t not_used_02 : 3; 00582 } lsm6dso_i3c_bus_avb_t; 00583 00584 #define LSM6DSO_INTERNAL_FREQ_FINE 0x63U 00585 typedef struct { 00586 uint8_t freq_fine : 8; 00587 } lsm6dso_internal_freq_fine_t; 00588 00589 #define LSM6DSO_INT_OIS 0x6FU 00590 typedef struct { 00591 uint8_t st_xl_ois : 2; 00592 uint8_t not_used_01 : 3; 00593 uint8_t den_lh_ois : 1; 00594 uint8_t lvl2_ois : 1; 00595 uint8_t int2_drdy_ois : 1; 00596 } lsm6dso_int_ois_t; 00597 00598 #define LSM6DSO_CTRL1_OIS 0x70U 00599 typedef struct { 00600 uint8_t ois_en_spi2 : 1; 00601 uint8_t fs_g_ois : 3; /* fs_125_ois + fs[1:0]_g_ois */ 00602 uint8_t mode4_en : 1; 00603 uint8_t sim_ois : 1; 00604 uint8_t lvl1_ois : 1; 00605 uint8_t not_used_01 : 1; 00606 } lsm6dso_ctrl1_ois_t; 00607 00608 #define LSM6DSO_CTRL2_OIS 0x71U 00609 typedef struct { 00610 uint8_t hp_en_ois : 1; 00611 uint8_t ftype_ois : 2; 00612 uint8_t not_used_01 : 1; 00613 uint8_t hpm_ois : 2; 00614 uint8_t not_used_02 : 2; 00615 } lsm6dso_ctrl2_ois_t; 00616 00617 #define LSM6DSO_CTRL3_OIS 0x72U 00618 typedef struct { 00619 uint8_t st_ois_clampdis : 1; 00620 uint8_t st_ois : 2; 00621 uint8_t filter_xl_conf_ois : 3; 00622 uint8_t fs_xl_ois : 2; 00623 } lsm6dso_ctrl3_ois_t; 00624 00625 #define LSM6DSO_X_OFS_USR 0x73U 00626 #define LSM6DSO_Y_OFS_USR 0x74U 00627 #define LSM6DSO_Z_OFS_USR 0x75U 00628 #define LSM6DSO_FIFO_DATA_OUT_TAG 0x78U 00629 typedef struct { 00630 uint8_t tag_parity : 1; 00631 uint8_t tag_cnt : 2; 00632 uint8_t tag_sensor : 5; 00633 } lsm6dso_fifo_data_out_tag_t; 00634 00635 #define LSM6DSO_FIFO_DATA_OUT_X_L 0x79U 00636 #define LSM6DSO_FIFO_DATA_OUT_X_H 0x7AU 00637 #define LSM6DSO_FIFO_DATA_OUT_Y_L 0x7BU 00638 #define LSM6DSO_FIFO_DATA_OUT_Y_H 0x7CU 00639 #define LSM6DSO_FIFO_DATA_OUT_Z_L 0x7DU 00640 #define LSM6DSO_FIFO_DATA_OUT_Z_H 0x7EU 00641 #define LSM6DSO_PAGE_SEL 0x02U 00642 typedef struct { 00643 uint8_t not_used_01 : 4; 00644 uint8_t page_sel : 4; 00645 } lsm6dso_page_sel_t; 00646 00647 #define LSM6DSO_EMB_FUNC_EN_A 0x04U 00648 typedef struct { 00649 uint8_t not_used_01 : 3; 00650 uint8_t pedo_en : 1; 00651 uint8_t tilt_en : 1; 00652 uint8_t sign_motion_en : 1; 00653 uint8_t not_used_02 : 2; 00654 } lsm6dso_emb_func_en_a_t; 00655 00656 #define LSM6DSO_EMB_FUNC_EN_B 0x05U 00657 typedef struct { 00658 uint8_t fsm_en : 1; 00659 uint8_t not_used_01 : 2; 00660 uint8_t fifo_compr_en : 1; 00661 uint8_t pedo_adv_en : 1; 00662 uint8_t not_used_02 : 3; 00663 } lsm6dso_emb_func_en_b_t; 00664 00665 #define LSM6DSO_PAGE_ADDRESS 0x08U 00666 typedef struct { 00667 uint8_t page_addr : 8; 00668 } lsm6dso_page_address_t; 00669 00670 #define LSM6DSO_PAGE_VALUE 0x09U 00671 typedef struct { 00672 uint8_t page_value : 8; 00673 } lsm6dso_page_value_t; 00674 00675 #define LSM6DSO_EMB_FUNC_INT1 0x0AU 00676 typedef struct { 00677 uint8_t not_used_01 : 3; 00678 uint8_t int1_step_detector : 1; 00679 uint8_t int1_tilt : 1; 00680 uint8_t int1_sig_mot : 1; 00681 uint8_t not_used_02 : 1; 00682 uint8_t int1_fsm_lc : 1; 00683 } lsm6dso_emb_func_int1_t; 00684 00685 #define LSM6DSO_FSM_INT1_A 0x0BU 00686 typedef struct { 00687 uint8_t int1_fsm1 : 1; 00688 uint8_t int1_fsm2 : 1; 00689 uint8_t int1_fsm3 : 1; 00690 uint8_t int1_fsm4 : 1; 00691 uint8_t int1_fsm5 : 1; 00692 uint8_t int1_fsm6 : 1; 00693 uint8_t int1_fsm7 : 1; 00694 uint8_t int1_fsm8 : 1; 00695 } lsm6dso_fsm_int1_a_t; 00696 00697 #define LSM6DSO_FSM_INT1_B 0x0CU 00698 typedef struct { 00699 uint8_t int1_fsm9 : 1; 00700 uint8_t int1_fsm10 : 1; 00701 uint8_t int1_fsm11 : 1; 00702 uint8_t int1_fsm12 : 1; 00703 uint8_t int1_fsm13 : 1; 00704 uint8_t int1_fsm14 : 1; 00705 uint8_t int1_fsm15 : 1; 00706 uint8_t int1_fsm16 : 1; 00707 } lsm6dso_fsm_int1_b_t; 00708 00709 #define LSM6DSO_EMB_FUNC_INT2 0x0EU 00710 typedef struct { 00711 uint8_t not_used_01 : 3; 00712 uint8_t int2_step_detector : 1; 00713 uint8_t int2_tilt : 1; 00714 uint8_t int2_sig_mot : 1; 00715 uint8_t not_used_02 : 1; 00716 uint8_t int2_fsm_lc : 1; 00717 } lsm6dso_emb_func_int2_t; 00718 00719 #define LSM6DSO_FSM_INT2_A 0x0FU 00720 typedef struct { 00721 uint8_t int2_fsm1 : 1; 00722 uint8_t int2_fsm2 : 1; 00723 uint8_t int2_fsm3 : 1; 00724 uint8_t int2_fsm4 : 1; 00725 uint8_t int2_fsm5 : 1; 00726 uint8_t int2_fsm6 : 1; 00727 uint8_t int2_fsm7 : 1; 00728 uint8_t int2_fsm8 : 1; 00729 } lsm6dso_fsm_int2_a_t; 00730 00731 #define LSM6DSO_FSM_INT2_B 0x10U 00732 typedef struct { 00733 uint8_t int2_fsm9 : 1; 00734 uint8_t int2_fsm10 : 1; 00735 uint8_t int2_fsm11 : 1; 00736 uint8_t int2_fsm12 : 1; 00737 uint8_t int2_fsm13 : 1; 00738 uint8_t int2_fsm14 : 1; 00739 uint8_t int2_fsm15 : 1; 00740 uint8_t int2_fsm16 : 1; 00741 } lsm6dso_fsm_int2_b_t; 00742 00743 #define LSM6DSO_EMB_FUNC_STATUS 0x12U 00744 typedef struct { 00745 uint8_t not_used_01 : 3; 00746 uint8_t is_step_det : 1; 00747 uint8_t is_tilt : 1; 00748 uint8_t is_sigmot : 1; 00749 uint8_t not_used_02 : 1; 00750 uint8_t is_fsm_lc : 1; 00751 } lsm6dso_emb_func_status_t; 00752 00753 #define LSM6DSO_FSM_STATUS_A 0x13U 00754 typedef struct { 00755 uint8_t is_fsm1 : 1; 00756 uint8_t is_fsm2 : 1; 00757 uint8_t is_fsm3 : 1; 00758 uint8_t is_fsm4 : 1; 00759 uint8_t is_fsm5 : 1; 00760 uint8_t is_fsm6 : 1; 00761 uint8_t is_fsm7 : 1; 00762 uint8_t is_fsm8 : 1; 00763 } lsm6dso_fsm_status_a_t; 00764 00765 #define LSM6DSO_FSM_STATUS_B 0x14U 00766 typedef struct { 00767 uint8_t is_fsm9 : 1; 00768 uint8_t is_fsm10 : 1; 00769 uint8_t is_fsm11 : 1; 00770 uint8_t is_fsm12 : 1; 00771 uint8_t is_fsm13 : 1; 00772 uint8_t is_fsm14 : 1; 00773 uint8_t is_fsm15 : 1; 00774 uint8_t is_fsm16 : 1; 00775 } lsm6dso_fsm_status_b_t; 00776 00777 #define LSM6DSO_PAGE_RW 0x17U 00778 typedef struct { 00779 uint8_t not_used_01 : 5; 00780 uint8_t page_rw : 2; /* page_write + page_read */ 00781 uint8_t emb_func_lir : 1; 00782 } lsm6dso_page_rw_t; 00783 00784 #define LSM6DSO_EMB_FUNC_FIFO_CFG 0x44U 00785 typedef struct { 00786 uint8_t not_used_00 : 6; 00787 uint8_t pedo_fifo_en : 1; 00788 uint8_t not_used_01 : 1; 00789 } lsm6dso_emb_func_fifo_cfg_t; 00790 00791 #define LSM6DSO_FSM_ENABLE_A 0x46U 00792 typedef struct { 00793 uint8_t fsm1_en : 1; 00794 uint8_t fsm2_en : 1; 00795 uint8_t fsm3_en : 1; 00796 uint8_t fsm4_en : 1; 00797 uint8_t fsm5_en : 1; 00798 uint8_t fsm6_en : 1; 00799 uint8_t fsm7_en : 1; 00800 uint8_t fsm8_en : 1; 00801 } lsm6dso_fsm_enable_a_t; 00802 00803 #define LSM6DSO_FSM_ENABLE_B 0x47U 00804 typedef struct { 00805 uint8_t fsm9_en : 1; 00806 uint8_t fsm10_en : 1; 00807 uint8_t fsm11_en : 1; 00808 uint8_t fsm12_en : 1; 00809 uint8_t fsm13_en : 1; 00810 uint8_t fsm14_en : 1; 00811 uint8_t fsm15_en : 1; 00812 uint8_t fsm16_en : 1; 00813 } lsm6dso_fsm_enable_b_t; 00814 00815 #define LSM6DSO_FSM_LONG_COUNTER_L 0x48U 00816 #define LSM6DSO_FSM_LONG_COUNTER_H 0x49U 00817 #define LSM6DSO_FSM_LONG_COUNTER_CLEAR 0x4AU 00818 typedef struct { 00819 uint8_t fsm_lc_clr : 2; /* fsm_lc_cleared + fsm_lc_clear */ 00820 uint8_t not_used_01 : 6; 00821 } lsm6dso_fsm_long_counter_clear_t; 00822 00823 #define LSM6DSO_FSM_OUTS1 0x4CU 00824 typedef struct { 00825 uint8_t n_v : 1; 00826 uint8_t p_v : 1; 00827 uint8_t n_z : 1; 00828 uint8_t p_z : 1; 00829 uint8_t n_y : 1; 00830 uint8_t p_y : 1; 00831 uint8_t n_x : 1; 00832 uint8_t p_x : 1; 00833 } lsm6dso_fsm_outs1_t; 00834 00835 #define LSM6DSO_FSM_OUTS2 0x4DU 00836 typedef struct { 00837 uint8_t n_v : 1; 00838 uint8_t p_v : 1; 00839 uint8_t n_z : 1; 00840 uint8_t p_z : 1; 00841 uint8_t n_y : 1; 00842 uint8_t p_y : 1; 00843 uint8_t n_x : 1; 00844 uint8_t p_x : 1; 00845 } lsm6dso_fsm_outs2_t; 00846 00847 #define LSM6DSO_FSM_OUTS3 0x4EU 00848 typedef struct { 00849 uint8_t n_v : 1; 00850 uint8_t p_v : 1; 00851 uint8_t n_z : 1; 00852 uint8_t p_z : 1; 00853 uint8_t n_y : 1; 00854 uint8_t p_y : 1; 00855 uint8_t n_x : 1; 00856 uint8_t p_x : 1; 00857 } lsm6dso_fsm_outs3_t; 00858 00859 #define LSM6DSO_FSM_OUTS4 0x4FU 00860 typedef struct { 00861 uint8_t n_v : 1; 00862 uint8_t p_v : 1; 00863 uint8_t n_z : 1; 00864 uint8_t p_z : 1; 00865 uint8_t n_y : 1; 00866 uint8_t p_y : 1; 00867 uint8_t n_x : 1; 00868 uint8_t p_x : 1; 00869 } lsm6dso_fsm_outs4_t; 00870 00871 #define LSM6DSO_FSM_OUTS5 0x50U 00872 typedef struct { 00873 uint8_t n_v : 1; 00874 uint8_t p_v : 1; 00875 uint8_t n_z : 1; 00876 uint8_t p_z : 1; 00877 uint8_t n_y : 1; 00878 uint8_t p_y : 1; 00879 uint8_t n_x : 1; 00880 uint8_t p_x : 1; 00881 } lsm6dso_fsm_outs5_t; 00882 00883 #define LSM6DSO_FSM_OUTS6 0x51U 00884 typedef struct { 00885 uint8_t n_v : 1; 00886 uint8_t p_v : 1; 00887 uint8_t n_z : 1; 00888 uint8_t p_z : 1; 00889 uint8_t n_y : 1; 00890 uint8_t p_y : 1; 00891 uint8_t n_x : 1; 00892 uint8_t p_x : 1; 00893 } lsm6dso_fsm_outs6_t; 00894 00895 #define LSM6DSO_FSM_OUTS7 0x52U 00896 typedef struct { 00897 uint8_t n_v : 1; 00898 uint8_t p_v : 1; 00899 uint8_t n_z : 1; 00900 uint8_t p_z : 1; 00901 uint8_t n_y : 1; 00902 uint8_t p_y : 1; 00903 uint8_t n_x : 1; 00904 uint8_t p_x : 1; 00905 } lsm6dso_fsm_outs7_t; 00906 00907 #define LSM6DSO_FSM_OUTS8 0x53U 00908 typedef struct { 00909 uint8_t n_v : 1; 00910 uint8_t p_v : 1; 00911 uint8_t n_z : 1; 00912 uint8_t p_z : 1; 00913 uint8_t n_y : 1; 00914 uint8_t p_y : 1; 00915 uint8_t n_x : 1; 00916 uint8_t p_x : 1; 00917 } lsm6dso_fsm_outs8_t; 00918 00919 #define LSM6DSO_FSM_OUTS9 0x54U 00920 typedef struct { 00921 uint8_t n_v : 1; 00922 uint8_t p_v : 1; 00923 uint8_t n_z : 1; 00924 uint8_t p_z : 1; 00925 uint8_t n_y : 1; 00926 uint8_t p_y : 1; 00927 uint8_t n_x : 1; 00928 uint8_t p_x : 1; 00929 } lsm6dso_fsm_outs9_t; 00930 00931 #define LSM6DSO_FSM_OUTS10 0x55U 00932 typedef struct { 00933 uint8_t n_v : 1; 00934 uint8_t p_v : 1; 00935 uint8_t n_z : 1; 00936 uint8_t p_z : 1; 00937 uint8_t n_y : 1; 00938 uint8_t p_y : 1; 00939 uint8_t n_x : 1; 00940 uint8_t p_x : 1; 00941 } lsm6dso_fsm_outs10_t; 00942 00943 #define LSM6DSO_FSM_OUTS11 0x56U 00944 typedef struct { 00945 uint8_t n_v : 1; 00946 uint8_t p_v : 1; 00947 uint8_t n_z : 1; 00948 uint8_t p_z : 1; 00949 uint8_t n_y : 1; 00950 uint8_t p_y : 1; 00951 uint8_t n_x : 1; 00952 uint8_t p_x : 1; 00953 } lsm6dso_fsm_outs11_t; 00954 00955 #define LSM6DSO_FSM_OUTS12 0x57U 00956 typedef struct { 00957 uint8_t n_v : 1; 00958 uint8_t p_v : 1; 00959 uint8_t n_z : 1; 00960 uint8_t p_z : 1; 00961 uint8_t n_y : 1; 00962 uint8_t p_y : 1; 00963 uint8_t n_x : 1; 00964 uint8_t p_x : 1; 00965 } lsm6dso_fsm_outs12_t; 00966 00967 #define LSM6DSO_FSM_OUTS13 0x58U 00968 typedef struct { 00969 uint8_t n_v : 1; 00970 uint8_t p_v : 1; 00971 uint8_t n_z : 1; 00972 uint8_t p_z : 1; 00973 uint8_t n_y : 1; 00974 uint8_t p_y : 1; 00975 uint8_t n_x : 1; 00976 uint8_t p_x : 1; 00977 } lsm6dso_fsm_outs13_t; 00978 00979 #define LSM6DSO_FSM_OUTS14 0x59U 00980 typedef struct { 00981 uint8_t n_v : 1; 00982 uint8_t p_v : 1; 00983 uint8_t n_z : 1; 00984 uint8_t p_z : 1; 00985 uint8_t n_y : 1; 00986 uint8_t p_y : 1; 00987 uint8_t n_x : 1; 00988 uint8_t p_x : 1; 00989 } lsm6dso_fsm_outs14_t; 00990 00991 #define LSM6DSO_FSM_OUTS15 0x5AU 00992 typedef struct { 00993 uint8_t n_v : 1; 00994 uint8_t p_v : 1; 00995 uint8_t n_z : 1; 00996 uint8_t p_z : 1; 00997 uint8_t n_y : 1; 00998 uint8_t p_y : 1; 00999 uint8_t n_x : 1; 01000 uint8_t p_x : 1; 01001 } lsm6dso_fsm_outs15_t; 01002 01003 #define LSM6DSO_FSM_OUTS16 0x5BU 01004 typedef struct { 01005 uint8_t n_v : 1; 01006 uint8_t p_v : 1; 01007 uint8_t n_z : 1; 01008 uint8_t p_z : 1; 01009 uint8_t n_y : 1; 01010 uint8_t p_y : 1; 01011 uint8_t n_x : 1; 01012 uint8_t p_x : 1; 01013 } lsm6dso_fsm_outs16_t; 01014 01015 #define LSM6DSO_EMB_FUNC_ODR_CFG_B 0x5FU 01016 typedef struct { 01017 uint8_t not_used_01 : 3; 01018 uint8_t fsm_odr : 2; 01019 uint8_t not_used_02 : 3; 01020 } lsm6dso_emb_func_odr_cfg_b_t; 01021 01022 #define LSM6DSO_STEP_COUNTER_L 0x62U 01023 #define LSM6DSO_STEP_COUNTER_H 0x63U 01024 #define LSM6DSO_EMB_FUNC_SRC 0x64U 01025 typedef struct { 01026 uint8_t not_used_01 : 2; 01027 uint8_t stepcounter_bit_set : 1; 01028 uint8_t step_overflow : 1; 01029 uint8_t step_count_delta_ia : 1; 01030 uint8_t step_detected : 1; 01031 uint8_t not_used_02 : 1; 01032 uint8_t pedo_rst_step : 1; 01033 } lsm6dso_emb_func_src_t; 01034 01035 #define LSM6DSO_EMB_FUNC_INIT_A 0x66U 01036 typedef struct { 01037 uint8_t not_used_01 : 3; 01038 uint8_t step_det_init : 1; 01039 uint8_t tilt_init : 1; 01040 uint8_t sig_mot_init : 1; 01041 uint8_t not_used_02 : 2; 01042 } lsm6dso_emb_func_init_a_t; 01043 01044 #define LSM6DSO_EMB_FUNC_INIT_B 0x67U 01045 typedef struct { 01046 uint8_t fsm_init : 1; 01047 uint8_t not_used_01 : 2; 01048 uint8_t fifo_compr_init : 1; 01049 uint8_t not_used_02 : 4; 01050 } lsm6dso_emb_func_init_b_t; 01051 01052 #define LSM6DSO_MAG_SENSITIVITY_L 0xBAU 01053 #define LSM6DSO_MAG_SENSITIVITY_H 0xBBU 01054 #define LSM6DSO_MAG_OFFX_L 0xC0U 01055 #define LSM6DSO_MAG_OFFX_H 0xC1U 01056 #define LSM6DSO_MAG_OFFY_L 0xC2U 01057 #define LSM6DSO_MAG_OFFY_H 0xC3U 01058 #define LSM6DSO_MAG_OFFZ_L 0xC4U 01059 #define LSM6DSO_MAG_OFFZ_H 0xC5U 01060 #define LSM6DSO_MAG_SI_XX_L 0xC6U 01061 #define LSM6DSO_MAG_SI_XX_H 0xC7U 01062 #define LSM6DSO_MAG_SI_XY_L 0xC8U 01063 #define LSM6DSO_MAG_SI_XY_H 0xC9U 01064 #define LSM6DSO_MAG_SI_XZ_L 0xCAU 01065 #define LSM6DSO_MAG_SI_XZ_H 0xCBU 01066 #define LSM6DSO_MAG_SI_YY_L 0xCCU 01067 #define LSM6DSO_MAG_SI_YY_H 0xCDU 01068 #define LSM6DSO_MAG_SI_YZ_L 0xCEU 01069 #define LSM6DSO_MAG_SI_YZ_H 0xCFU 01070 #define LSM6DSO_MAG_SI_ZZ_L 0xD0U 01071 #define LSM6DSO_MAG_SI_ZZ_H 0xD1U 01072 #define LSM6DSO_MAG_CFG_A 0xD4U 01073 typedef struct { 01074 uint8_t mag_z_axis : 3; 01075 uint8_t not_used_01 : 1; 01076 uint8_t mag_y_axis : 3; 01077 uint8_t not_used_02 : 1; 01078 } lsm6dso_mag_cfg_a_t; 01079 01080 #define LSM6DSO_MAG_CFG_B 0xD5U 01081 typedef struct { 01082 uint8_t mag_x_axis : 3; 01083 uint8_t not_used_01 : 5; 01084 } lsm6dso_mag_cfg_b_t; 01085 01086 #define LSM6DSO_FSM_LC_TIMEOUT_L 0x17AU 01087 #define LSM6DSO_FSM_LC_TIMEOUT_H 0x17BU 01088 #define LSM6DSO_FSM_PROGRAMS 0x17CU 01089 #define LSM6DSO_FSM_START_ADD_L 0x17EU 01090 #define LSM6DSO_FSM_START_ADD_H 0x17FU 01091 #define LSM6DSO_PEDO_CMD_REG 0x183U 01092 typedef struct { 01093 uint8_t ad_det_en : 1; 01094 uint8_t not_used_01 : 1; 01095 uint8_t fp_rejection_en : 1; 01096 uint8_t carry_count_en : 1; 01097 uint8_t not_used_02 : 4; 01098 } lsm6dso_pedo_cmd_reg_t; 01099 01100 #define LSM6DSO_PEDO_DEB_STEPS_CONF 0x184U 01101 #define LSM6DSO_PEDO_SC_DELTAT_L 0x1D0U 01102 #define LSM6DSO_PEDO_SC_DELTAT_H 0x1D1U 01103 #define LSM6DSO_SENSOR_HUB_1 0x02U 01104 typedef struct { 01105 uint8_t bit0 : 1; 01106 uint8_t bit1 : 1; 01107 uint8_t bit2 : 1; 01108 uint8_t bit3 : 1; 01109 uint8_t bit4 : 1; 01110 uint8_t bit5 : 1; 01111 uint8_t bit6 : 1; 01112 uint8_t bit7 : 1; 01113 } lsm6dso_sensor_hub_1_t; 01114 01115 #define LSM6DSO_SENSOR_HUB_2 0x03U 01116 typedef struct { 01117 uint8_t bit0 : 1; 01118 uint8_t bit1 : 1; 01119 uint8_t bit2 : 1; 01120 uint8_t bit3 : 1; 01121 uint8_t bit4 : 1; 01122 uint8_t bit5 : 1; 01123 uint8_t bit6 : 1; 01124 uint8_t bit7 : 1; 01125 } lsm6dso_sensor_hub_2_t; 01126 01127 #define LSM6DSO_SENSOR_HUB_3 0x04U 01128 typedef struct { 01129 uint8_t bit0 : 1; 01130 uint8_t bit1 : 1; 01131 uint8_t bit2 : 1; 01132 uint8_t bit3 : 1; 01133 uint8_t bit4 : 1; 01134 uint8_t bit5 : 1; 01135 uint8_t bit6 : 1; 01136 uint8_t bit7 : 1; 01137 } lsm6dso_sensor_hub_3_t; 01138 01139 #define LSM6DSO_SENSOR_HUB_4 0x05U 01140 typedef struct { 01141 uint8_t bit0 : 1; 01142 uint8_t bit1 : 1; 01143 uint8_t bit2 : 1; 01144 uint8_t bit3 : 1; 01145 uint8_t bit4 : 1; 01146 uint8_t bit5 : 1; 01147 uint8_t bit6 : 1; 01148 uint8_t bit7 : 1; 01149 } lsm6dso_sensor_hub_4_t; 01150 01151 #define LSM6DSO_SENSOR_HUB_5 0x06U 01152 typedef struct { 01153 uint8_t bit0 : 1; 01154 uint8_t bit1 : 1; 01155 uint8_t bit2 : 1; 01156 uint8_t bit3 : 1; 01157 uint8_t bit4 : 1; 01158 uint8_t bit5 : 1; 01159 uint8_t bit6 : 1; 01160 uint8_t bit7 : 1; 01161 } lsm6dso_sensor_hub_5_t; 01162 01163 #define LSM6DSO_SENSOR_HUB_6 0x07U 01164 typedef struct { 01165 uint8_t bit0 : 1; 01166 uint8_t bit1 : 1; 01167 uint8_t bit2 : 1; 01168 uint8_t bit3 : 1; 01169 uint8_t bit4 : 1; 01170 uint8_t bit5 : 1; 01171 uint8_t bit6 : 1; 01172 uint8_t bit7 : 1; 01173 } lsm6dso_sensor_hub_6_t; 01174 01175 #define LSM6DSO_SENSOR_HUB_7 0x08U 01176 typedef struct { 01177 uint8_t bit0 : 1; 01178 uint8_t bit1 : 1; 01179 uint8_t bit2 : 1; 01180 uint8_t bit3 : 1; 01181 uint8_t bit4 : 1; 01182 uint8_t bit5 : 1; 01183 uint8_t bit6 : 1; 01184 uint8_t bit7 : 1; 01185 } lsm6dso_sensor_hub_7_t; 01186 01187 #define LSM6DSO_SENSOR_HUB_8 0x09U 01188 typedef struct { 01189 uint8_t bit0 : 1; 01190 uint8_t bit1 : 1; 01191 uint8_t bit2 : 1; 01192 uint8_t bit3 : 1; 01193 uint8_t bit4 : 1; 01194 uint8_t bit5 : 1; 01195 uint8_t bit6 : 1; 01196 uint8_t bit7 : 1; 01197 } lsm6dso_sensor_hub_8_t; 01198 01199 #define LSM6DSO_SENSOR_HUB_9 0x0AU 01200 typedef struct { 01201 uint8_t bit0 : 1; 01202 uint8_t bit1 : 1; 01203 uint8_t bit2 : 1; 01204 uint8_t bit3 : 1; 01205 uint8_t bit4 : 1; 01206 uint8_t bit5 : 1; 01207 uint8_t bit6 : 1; 01208 uint8_t bit7 : 1; 01209 } lsm6dso_sensor_hub_9_t; 01210 01211 #define LSM6DSO_SENSOR_HUB_10 0x0BU 01212 typedef struct { 01213 uint8_t bit0 : 1; 01214 uint8_t bit1 : 1; 01215 uint8_t bit2 : 1; 01216 uint8_t bit3 : 1; 01217 uint8_t bit4 : 1; 01218 uint8_t bit5 : 1; 01219 uint8_t bit6 : 1; 01220 uint8_t bit7 : 1; 01221 } lsm6dso_sensor_hub_10_t; 01222 01223 #define LSM6DSO_SENSOR_HUB_11 0x0CU 01224 typedef struct { 01225 uint8_t bit0 : 1; 01226 uint8_t bit1 : 1; 01227 uint8_t bit2 : 1; 01228 uint8_t bit3 : 1; 01229 uint8_t bit4 : 1; 01230 uint8_t bit5 : 1; 01231 uint8_t bit6 : 1; 01232 uint8_t bit7 : 1; 01233 } lsm6dso_sensor_hub_11_t; 01234 01235 #define LSM6DSO_SENSOR_HUB_12 0x0DU 01236 typedef struct { 01237 uint8_t bit0 : 1; 01238 uint8_t bit1 : 1; 01239 uint8_t bit2 : 1; 01240 uint8_t bit3 : 1; 01241 uint8_t bit4 : 1; 01242 uint8_t bit5 : 1; 01243 uint8_t bit6 : 1; 01244 uint8_t bit7 : 1; 01245 } lsm6dso_sensor_hub_12_t; 01246 01247 #define LSM6DSO_SENSOR_HUB_13 0x0EU 01248 typedef struct { 01249 uint8_t bit0 : 1; 01250 uint8_t bit1 : 1; 01251 uint8_t bit2 : 1; 01252 uint8_t bit3 : 1; 01253 uint8_t bit4 : 1; 01254 uint8_t bit5 : 1; 01255 uint8_t bit6 : 1; 01256 uint8_t bit7 : 1; 01257 } lsm6dso_sensor_hub_13_t; 01258 01259 #define LSM6DSO_SENSOR_HUB_14 0x0FU 01260 typedef struct { 01261 uint8_t bit0 : 1; 01262 uint8_t bit1 : 1; 01263 uint8_t bit2 : 1; 01264 uint8_t bit3 : 1; 01265 uint8_t bit4 : 1; 01266 uint8_t bit5 : 1; 01267 uint8_t bit6 : 1; 01268 uint8_t bit7 : 1; 01269 } lsm6dso_sensor_hub_14_t; 01270 01271 #define LSM6DSO_SENSOR_HUB_15 0x10U 01272 typedef struct { 01273 uint8_t bit0 : 1; 01274 uint8_t bit1 : 1; 01275 uint8_t bit2 : 1; 01276 uint8_t bit3 : 1; 01277 uint8_t bit4 : 1; 01278 uint8_t bit5 : 1; 01279 uint8_t bit6 : 1; 01280 uint8_t bit7 : 1; 01281 } lsm6dso_sensor_hub_15_t; 01282 01283 #define LSM6DSO_SENSOR_HUB_16 0x11U 01284 typedef struct { 01285 uint8_t bit0 : 1; 01286 uint8_t bit1 : 1; 01287 uint8_t bit2 : 1; 01288 uint8_t bit3 : 1; 01289 uint8_t bit4 : 1; 01290 uint8_t bit5 : 1; 01291 uint8_t bit6 : 1; 01292 uint8_t bit7 : 1; 01293 } lsm6dso_sensor_hub_16_t; 01294 01295 #define LSM6DSO_SENSOR_HUB_17 0x12U 01296 typedef struct { 01297 uint8_t bit0 : 1; 01298 uint8_t bit1 : 1; 01299 uint8_t bit2 : 1; 01300 uint8_t bit3 : 1; 01301 uint8_t bit4 : 1; 01302 uint8_t bit5 : 1; 01303 uint8_t bit6 : 1; 01304 uint8_t bit7 : 1; 01305 } lsm6dso_sensor_hub_17_t; 01306 01307 #define LSM6DSO_SENSOR_HUB_18 0x13U 01308 typedef struct { 01309 uint8_t bit0 : 1; 01310 uint8_t bit1 : 1; 01311 uint8_t bit2 : 1; 01312 uint8_t bit3 : 1; 01313 uint8_t bit4 : 1; 01314 uint8_t bit5 : 1; 01315 uint8_t bit6 : 1; 01316 uint8_t bit7 : 1; 01317 } lsm6dso_sensor_hub_18_t; 01318 01319 #define LSM6DSO_MASTER_CONFIG 0x14U 01320 typedef struct { 01321 uint8_t aux_sens_on : 2; 01322 uint8_t master_on : 1; 01323 uint8_t shub_pu_en : 1; 01324 uint8_t pass_through_mode : 1; 01325 uint8_t start_config : 1; 01326 uint8_t write_once : 1; 01327 uint8_t rst_master_regs : 1; 01328 } lsm6dso_master_config_t; 01329 01330 #define LSM6DSO_SLV0_ADD 0x15U 01331 typedef struct { 01332 uint8_t rw_0 : 1; 01333 uint8_t slave0 : 7; 01334 } lsm6dso_slv0_add_t; 01335 01336 #define LSM6DSO_SLV0_SUBADD 0x16U 01337 typedef struct { 01338 uint8_t slave0_reg : 8; 01339 } lsm6dso_slv0_subadd_t; 01340 01341 #define LSM6DSO_SLV0_CONFIG 0x17U 01342 typedef struct { 01343 uint8_t slave0_numop : 3; 01344 uint8_t batch_ext_sens_0_en : 1; 01345 uint8_t not_used_01 : 2; 01346 uint8_t shub_odr : 2; 01347 } lsm6dso_slv0_config_t; 01348 01349 #define LSM6DSO_SLV1_ADD 0x18U 01350 typedef struct { 01351 uint8_t r_1 : 1; 01352 uint8_t slave1_add : 7; 01353 } lsm6dso_slv1_add_t; 01354 01355 #define LSM6DSO_SLV1_SUBADD 0x19U 01356 typedef struct { 01357 uint8_t slave1_reg : 8; 01358 } lsm6dso_slv1_subadd_t; 01359 01360 #define LSM6DSO_SLV1_CONFIG 0x1AU 01361 typedef struct { 01362 uint8_t slave1_numop : 3; 01363 uint8_t batch_ext_sens_1_en : 1; 01364 uint8_t not_used_01 : 4; 01365 } lsm6dso_slv1_config_t; 01366 01367 #define LSM6DSO_SLV2_ADD 0x1BU 01368 typedef struct { 01369 uint8_t r_2 : 1; 01370 uint8_t slave2_add : 7; 01371 } lsm6dso_slv2_add_t; 01372 01373 #define LSM6DSO_SLV2_SUBADD 0x1CU 01374 typedef struct { 01375 uint8_t slave2_reg : 8; 01376 } lsm6dso_slv2_subadd_t; 01377 01378 #define LSM6DSO_SLV2_CONFIG 0x1DU 01379 typedef struct { 01380 uint8_t slave2_numop : 3; 01381 uint8_t batch_ext_sens_2_en : 1; 01382 uint8_t not_used_01 : 4; 01383 } lsm6dso_slv2_config_t; 01384 01385 #define LSM6DSO_SLV3_ADD 0x1EU 01386 typedef struct { 01387 uint8_t r_3 : 1; 01388 uint8_t slave3_add : 7; 01389 } lsm6dso_slv3_add_t; 01390 01391 #define LSM6DSO_SLV3_SUBADD 0x1FU 01392 typedef struct { 01393 uint8_t slave3_reg : 8; 01394 } lsm6dso_slv3_subadd_t; 01395 01396 #define LSM6DSO_SLV3_CONFIG 0x20U 01397 typedef struct { 01398 uint8_t slave3_numop : 3; 01399 uint8_t batch_ext_sens_3_en : 1; 01400 uint8_t not_used_01 : 4; 01401 } lsm6dso_slv3_config_t; 01402 01403 #define LSM6DSO_DATAWRITE_SLV0 0x21U 01404 typedef struct { 01405 uint8_t slave0_dataw : 8; 01406 } lsm6dso_datawrite_src_mode_sub_slv0_t; 01407 01408 #define LSM6DSO_STATUS_MASTER 0x22U 01409 typedef struct { 01410 uint8_t sens_hub_endop : 1; 01411 uint8_t not_used_01 : 2; 01412 uint8_t slave0_nack : 1; 01413 uint8_t slave1_nack : 1; 01414 uint8_t slave2_nack : 1; 01415 uint8_t slave3_nack : 1; 01416 uint8_t wr_once_done : 1; 01417 } lsm6dso_status_master_t; 01418 01419 #define LSM6DSO_START_FSM_ADD 0x0400U 01420 01421 /** 01422 * @defgroup LSM6DSO_Register_Union 01423 * @brief This union group all the registers that has a bitfield 01424 * description. 01425 * This union is useful but not need by the driver. 01426 * 01427 * REMOVING this union you are compliant with: 01428 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 01429 * 01430 * @{ 01431 * 01432 */ 01433 typedef union{ 01434 lsm6dso_func_cfg_access_t func_cfg_access; 01435 lsm6dso_pin_ctrl_t pin_ctrl; 01436 lsm6dso_fifo_ctrl1_t fifo_ctrl1; 01437 lsm6dso_fifo_ctrl2_t fifo_ctrl2; 01438 lsm6dso_fifo_ctrl3_t fifo_ctrl3; 01439 lsm6dso_fifo_ctrl4_t fifo_ctrl4; 01440 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1; 01441 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2; 01442 lsm6dso_int1_ctrl_t int1_ctrl; 01443 lsm6dso_int2_ctrl_t int2_ctrl; 01444 lsm6dso_ctrl1_xl_t ctrl1_xl; 01445 lsm6dso_ctrl2_g_t ctrl2_g; 01446 lsm6dso_ctrl3_c_t ctrl3_c; 01447 lsm6dso_ctrl4_c_t ctrl4_c; 01448 lsm6dso_ctrl5_c_t ctrl5_c; 01449 lsm6dso_ctrl6_c_t ctrl6_c; 01450 lsm6dso_ctrl7_g_t ctrl7_g; 01451 lsm6dso_ctrl8_xl_t ctrl8_xl; 01452 lsm6dso_ctrl9_xl_t ctrl9_xl; 01453 lsm6dso_ctrl10_c_t ctrl10_c; 01454 lsm6dso_all_int_src_t all_int_src; 01455 lsm6dso_wake_up_src_t wake_up_src; 01456 lsm6dso_tap_src_t tap_src; 01457 lsm6dso_d6d_src_t d6d_src; 01458 lsm6dso_status_reg_t status_reg; 01459 lsm6dso_status_spiaux_t status_spiaux; 01460 lsm6dso_fifo_status1_t fifo_status1; 01461 lsm6dso_fifo_status2_t fifo_status2; 01462 lsm6dso_tap_cfg0_t tap_cfg0; 01463 lsm6dso_tap_cfg1_t tap_cfg1; 01464 lsm6dso_tap_cfg2_t tap_cfg2; 01465 lsm6dso_tap_ths_6d_t tap_ths_6d; 01466 lsm6dso_int_dur2_t int_dur2; 01467 lsm6dso_wake_up_ths_t wake_up_ths; 01468 lsm6dso_wake_up_dur_t wake_up_dur; 01469 lsm6dso_free_fall_t free_fall; 01470 lsm6dso_md1_cfg_t md1_cfg; 01471 lsm6dso_md2_cfg_t md2_cfg; 01472 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 01473 lsm6dso_internal_freq_fine_t internal_freq_fine; 01474 lsm6dso_int_ois_t int_ois; 01475 lsm6dso_ctrl1_ois_t ctrl1_ois; 01476 lsm6dso_ctrl2_ois_t ctrl2_ois; 01477 lsm6dso_ctrl3_ois_t ctrl3_ois; 01478 lsm6dso_fifo_data_out_tag_t fifo_data_out_tag; 01479 lsm6dso_page_sel_t page_sel; 01480 lsm6dso_emb_func_en_a_t emb_func_en_a; 01481 lsm6dso_emb_func_en_b_t emb_func_en_b; 01482 lsm6dso_page_address_t page_address; 01483 lsm6dso_page_value_t page_value; 01484 lsm6dso_emb_func_int1_t emb_func_int1; 01485 lsm6dso_fsm_int1_a_t fsm_int1_a; 01486 lsm6dso_fsm_int1_b_t fsm_int1_b; 01487 lsm6dso_emb_func_int2_t emb_func_int2; 01488 lsm6dso_fsm_int2_a_t fsm_int2_a; 01489 lsm6dso_fsm_int2_b_t fsm_int2_b; 01490 lsm6dso_emb_func_status_t emb_func_status; 01491 lsm6dso_fsm_status_a_t fsm_status_a; 01492 lsm6dso_fsm_status_b_t fsm_status_b; 01493 lsm6dso_page_rw_t page_rw; 01494 lsm6dso_emb_func_fifo_cfg_t emb_func_fifo_cfg; 01495 lsm6dso_fsm_enable_a_t fsm_enable_a; 01496 lsm6dso_fsm_enable_b_t fsm_enable_b; 01497 lsm6dso_fsm_long_counter_clear_t fsm_long_counter_clear; 01498 lsm6dso_fsm_outs1_t fsm_outs1; 01499 lsm6dso_fsm_outs2_t fsm_outs2; 01500 lsm6dso_fsm_outs3_t fsm_outs3; 01501 lsm6dso_fsm_outs4_t fsm_outs4; 01502 lsm6dso_fsm_outs5_t fsm_outs5; 01503 lsm6dso_fsm_outs6_t fsm_outs6; 01504 lsm6dso_fsm_outs7_t fsm_outs7; 01505 lsm6dso_fsm_outs8_t fsm_outs8; 01506 lsm6dso_fsm_outs9_t fsm_outs9; 01507 lsm6dso_fsm_outs10_t fsm_outs10; 01508 lsm6dso_fsm_outs11_t fsm_outs11; 01509 lsm6dso_fsm_outs12_t fsm_outs12; 01510 lsm6dso_fsm_outs13_t fsm_outs13; 01511 lsm6dso_fsm_outs14_t fsm_outs14; 01512 lsm6dso_fsm_outs15_t fsm_outs15; 01513 lsm6dso_fsm_outs16_t fsm_outs16; 01514 lsm6dso_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 01515 lsm6dso_emb_func_src_t emb_func_src; 01516 lsm6dso_emb_func_init_a_t emb_func_init_a; 01517 lsm6dso_emb_func_init_b_t emb_func_init_b; 01518 lsm6dso_mag_cfg_a_t mag_cfg_a; 01519 lsm6dso_mag_cfg_b_t mag_cfg_b; 01520 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg; 01521 lsm6dso_sensor_hub_1_t sensor_hub_1; 01522 lsm6dso_sensor_hub_2_t sensor_hub_2; 01523 lsm6dso_sensor_hub_3_t sensor_hub_3; 01524 lsm6dso_sensor_hub_4_t sensor_hub_4; 01525 lsm6dso_sensor_hub_5_t sensor_hub_5; 01526 lsm6dso_sensor_hub_6_t sensor_hub_6; 01527 lsm6dso_sensor_hub_7_t sensor_hub_7; 01528 lsm6dso_sensor_hub_8_t sensor_hub_8; 01529 lsm6dso_sensor_hub_9_t sensor_hub_9; 01530 lsm6dso_sensor_hub_10_t sensor_hub_10; 01531 lsm6dso_sensor_hub_11_t sensor_hub_11; 01532 lsm6dso_sensor_hub_12_t sensor_hub_12; 01533 lsm6dso_sensor_hub_13_t sensor_hub_13; 01534 lsm6dso_sensor_hub_14_t sensor_hub_14; 01535 lsm6dso_sensor_hub_15_t sensor_hub_15; 01536 lsm6dso_sensor_hub_16_t sensor_hub_16; 01537 lsm6dso_sensor_hub_17_t sensor_hub_17; 01538 lsm6dso_sensor_hub_18_t sensor_hub_18; 01539 lsm6dso_master_config_t master_config; 01540 lsm6dso_slv0_add_t slv0_add; 01541 lsm6dso_slv0_subadd_t slv0_subadd; 01542 lsm6dso_slv0_config_t slv0_config; 01543 lsm6dso_slv1_add_t slv1_add; 01544 lsm6dso_slv1_subadd_t slv1_subadd; 01545 lsm6dso_slv1_config_t slv1_config; 01546 lsm6dso_slv2_add_t slv2_add; 01547 lsm6dso_slv2_subadd_t slv2_subadd; 01548 lsm6dso_slv2_config_t slv2_config; 01549 lsm6dso_slv3_add_t slv3_add; 01550 lsm6dso_slv3_subadd_t slv3_subadd; 01551 lsm6dso_slv3_config_t slv3_config; 01552 lsm6dso_datawrite_src_mode_sub_slv0_t datawrite_src_mode_sub_slv0; 01553 lsm6dso_status_master_t status_master; 01554 bitwise_t bitwise; 01555 uint8_t byte; 01556 } lsm6dso_reg_t; 01557 01558 /** 01559 * @} 01560 * 01561 */ 01562 01563 int32_t lsm6dso_read_reg(lsm6dso_ctx_t *ctx, uint8_t reg, uint8_t* data, 01564 uint16_t len); 01565 int32_t lsm6dso_write_reg(lsm6dso_ctx_t *ctx, uint8_t reg, uint8_t* data, 01566 uint16_t len); 01567 01568 extern float_t lsm6dso_from_fs2_to_mg(int16_t lsb); 01569 extern float_t lsm6dso_from_fs4_to_mg(int16_t lsb); 01570 extern float_t lsm6dso_from_fs8_to_mg(int16_t lsb); 01571 extern float_t lsm6dso_from_fs16_to_mg(int16_t lsb); 01572 extern float_t lsm6dso_from_fs125_to_mdps(int16_t lsb); 01573 extern float_t lsm6dso_from_fs500_to_mdps(int16_t lsb); 01574 extern float_t lsm6dso_from_fs250_to_mdps(int16_t lsb); 01575 extern float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb); 01576 extern float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb); 01577 extern float_t lsm6dso_from_lsb_to_celsius(int16_t lsb); 01578 extern float_t lsm6dso_from_lsb_to_nsec(int16_t lsb); 01579 01580 typedef enum { 01581 LSM6DSO_2g = 0, 01582 LSM6DSO_16g = 1, /* if XL_FS_MODE = ‘1’ -> LSM6DSO_2g */ 01583 LSM6DSO_4g = 2, 01584 LSM6DSO_8g = 3, 01585 } lsm6dso_fs_xl_t; 01586 int32_t lsm6dso_xl_full_scale_set(lsm6dso_ctx_t *ctx, lsm6dso_fs_xl_t val); 01587 int32_t lsm6dso_xl_full_scale_get(lsm6dso_ctx_t *ctx, lsm6dso_fs_xl_t *val); 01588 01589 typedef enum { 01590 LSM6DSO_XL_ODR_OFF = 0, 01591 LSM6DSO_XL_ODR_12Hz5 = 1, 01592 LSM6DSO_XL_ODR_26Hz = 2, 01593 LSM6DSO_XL_ODR_52Hz = 3, 01594 LSM6DSO_XL_ODR_104Hz = 4, 01595 LSM6DSO_XL_ODR_208Hz = 5, 01596 LSM6DSO_XL_ODR_417Hz = 6, 01597 LSM6DSO_XL_ODR_833Hz = 7, 01598 LSM6DSO_XL_ODR_1667Hz = 8, 01599 LSM6DSO_XL_ODR_3333Hz = 9, 01600 LSM6DSO_XL_ODR_6667Hz = 10, 01601 LSM6DSO_XL_ODR_1Hz6 = 11, /* (low power only) */ 01602 } lsm6dso_odr_xl_t; 01603 int32_t lsm6dso_xl_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_xl_t val); 01604 int32_t lsm6dso_xl_data_rate_get(lsm6dso_ctx_t *ctx, lsm6dso_odr_xl_t *val); 01605 01606 typedef enum { 01607 LSM6DSO_250dps = 0, 01608 LSM6DSO_125dps = 1, 01609 LSM6DSO_500dps = 2, 01610 LSM6DSO_1000dps = 4, 01611 LSM6DSO_2000dps = 6, 01612 } lsm6dso_fs_g_t; 01613 int32_t lsm6dso_gy_full_scale_set(lsm6dso_ctx_t *ctx, lsm6dso_fs_g_t val); 01614 int32_t lsm6dso_gy_full_scale_get(lsm6dso_ctx_t *ctx, lsm6dso_fs_g_t *val); 01615 01616 typedef enum { 01617 LSM6DSO_GY_ODR_OFF = 0, 01618 LSM6DSO_GY_ODR_12Hz5 = 1, 01619 LSM6DSO_GY_ODR_26Hz = 2, 01620 LSM6DSO_GY_ODR_52Hz = 3, 01621 LSM6DSO_GY_ODR_104Hz = 4, 01622 LSM6DSO_GY_ODR_208Hz = 5, 01623 LSM6DSO_GY_ODR_417Hz = 6, 01624 LSM6DSO_GY_ODR_833Hz = 7, 01625 LSM6DSO_GY_ODR_1667Hz = 8, 01626 LSM6DSO_GY_ODR_3333Hz = 9, 01627 LSM6DSO_GY_ODR_6667Hz = 10, 01628 } lsm6dso_odr_g_t; 01629 int32_t lsm6dso_gy_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_g_t val); 01630 int32_t lsm6dso_gy_data_rate_get(lsm6dso_ctx_t *ctx, lsm6dso_odr_g_t *val); 01631 01632 int32_t lsm6dso_block_data_update_set(lsm6dso_ctx_t *ctx, uint8_t val); 01633 int32_t lsm6dso_block_data_update_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01634 01635 typedef enum { 01636 LSM6DSO_LSb_1mg = 0, 01637 LSM6DSO_LSb_16mg = 1, 01638 } lsm6dso_usr_off_w_t; 01639 int32_t lsm6dso_xl_offset_weight_set(lsm6dso_ctx_t *ctx, 01640 lsm6dso_usr_off_w_t val); 01641 int32_t lsm6dso_xl_offset_weight_get(lsm6dso_ctx_t *ctx, 01642 lsm6dso_usr_off_w_t *val); 01643 01644 typedef enum { 01645 LSM6DSO_HIGH_PERFORMANCE_MD = 0, 01646 LSM6DSO_LOW_NORMAL_POWER_MD = 1, 01647 LSM6DSO_ULTRA_LOW_POWER_MD = 2, 01648 } lsm6dso_xl_hm_mode_t; 01649 int32_t lsm6dso_xl_power_mode_set(lsm6dso_ctx_t *ctx, 01650 lsm6dso_xl_hm_mode_t val); 01651 int32_t lsm6dso_xl_power_mode_get(lsm6dso_ctx_t *ctx, 01652 lsm6dso_xl_hm_mode_t *val); 01653 01654 typedef enum { 01655 LSM6DSO_GY_HIGH_PERFORMANCE = 0, 01656 LSM6DSO_GY_NORMAL = 1, 01657 } lsm6dso_g_hm_mode_t; 01658 int32_t lsm6dso_gy_power_mode_set(lsm6dso_ctx_t *ctx, 01659 lsm6dso_g_hm_mode_t val); 01660 int32_t lsm6dso_gy_power_mode_get(lsm6dso_ctx_t *ctx, 01661 lsm6dso_g_hm_mode_t *val); 01662 01663 int32_t lsm6dso_status_reg_get(lsm6dso_ctx_t *ctx, 01664 lsm6dso_status_reg_t *val); 01665 01666 int32_t lsm6dso_xl_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01667 01668 int32_t lsm6dso_gy_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01669 01670 int32_t lsm6dso_temp_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01671 01672 int32_t lsm6dso_xl_usr_offset_x_set(lsm6dso_ctx_t *ctx, uint8_t *buff); 01673 int32_t lsm6dso_xl_usr_offset_x_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 01674 01675 int32_t lsm6dso_xl_usr_offset_y_set(lsm6dso_ctx_t *ctx, uint8_t *buff); 01676 int32_t lsm6dso_xl_usr_offset_y_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 01677 01678 int32_t lsm6dso_xl_usr_offset_z_set(lsm6dso_ctx_t *ctx, uint8_t *buff); 01679 int32_t lsm6dso_xl_usr_offset_z_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 01680 01681 int32_t lsm6dso_xl_usr_offset_set(lsm6dso_ctx_t *ctx, uint8_t val); 01682 int32_t lsm6dso_xl_usr_offset_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01683 01684 int32_t lsm6dso_timestamp_rst(lsm6dso_ctx_t *ctx); 01685 01686 int32_t lsm6dso_timestamp_set(lsm6dso_ctx_t *ctx, uint8_t val); 01687 int32_t lsm6dso_timestamp_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01688 01689 int32_t lsm6dso_timestamp_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 01690 01691 typedef enum { 01692 LSM6DSO_NO_ROUND = 0, 01693 LSM6DSO_ROUND_XL = 1, 01694 LSM6DSO_ROUND_GY = 2, 01695 LSM6DSO_ROUND_GY_XL = 3, 01696 } lsm6dso_rounding_t; 01697 int32_t lsm6dso_rounding_mode_set(lsm6dso_ctx_t *ctx, 01698 lsm6dso_rounding_t val); 01699 int32_t lsm6dso_rounding_mode_get(lsm6dso_ctx_t *ctx, 01700 lsm6dso_rounding_t *val); 01701 01702 int32_t lsm6dso_temperature_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 01703 01704 int32_t lsm6dso_angular_rate_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 01705 01706 int32_t lsm6dso_acceleration_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 01707 01708 int32_t lsm6dso_fifo_out_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 01709 01710 int32_t lsm6dso_number_of_steps_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 01711 01712 int32_t lsm6dso_steps_reset(lsm6dso_ctx_t *ctx); 01713 01714 int32_t lsm6dso_odr_cal_reg_set(lsm6dso_ctx_t *ctx, uint8_t val); 01715 int32_t lsm6dso_odr_cal_reg_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01716 01717 typedef enum { 01718 LSM6DSO_USER_BANK = 0, 01719 LSM6DSO_SENSOR_HUB_BANK = 1, 01720 LSM6DSO_EMBEDDED_FUNC_BANK = 2, 01721 } lsm6dso_reg_access_t; 01722 int32_t lsm6dso_mem_bank_set(lsm6dso_ctx_t *ctx, lsm6dso_reg_access_t val); 01723 int32_t lsm6dso_mem_bank_get(lsm6dso_ctx_t *ctx, lsm6dso_reg_access_t *val); 01724 01725 int32_t lsm6dso_ln_pg_write_byte(lsm6dso_ctx_t *ctx, uint16_t address, 01726 uint8_t *val); 01727 int32_t lsm6dso_ln_pg_read_byte(lsm6dso_ctx_t *ctx, uint16_t address, 01728 uint8_t *val); 01729 int32_t lsm6dso_ln_pg_write(lsm6dso_ctx_t *ctx, uint16_t address, 01730 uint8_t *buf, uint8_t len); 01731 int32_t lsm6dso_ln_pg_read(lsm6dso_ctx_t *ctx, uint16_t address, 01732 uint8_t *val); 01733 01734 typedef enum { 01735 LSM6DSO_DRDY_LATCHED = 0, 01736 LSM6DSO_DRDY_PULSED = 1, 01737 } lsm6dso_dataready_pulsed_t; 01738 int32_t lsm6dso_data_ready_mode_set(lsm6dso_ctx_t *ctx, 01739 lsm6dso_dataready_pulsed_t val); 01740 int32_t lsm6dso_data_ready_mode_get(lsm6dso_ctx_t *ctx, 01741 lsm6dso_dataready_pulsed_t *val); 01742 01743 int32_t lsm6dso_device_id_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 01744 01745 int32_t lsm6dso_reset_set(lsm6dso_ctx_t *ctx, uint8_t val); 01746 int32_t lsm6dso_reset_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01747 01748 int32_t lsm6dso_auto_increment_set(lsm6dso_ctx_t *ctx, uint8_t val); 01749 int32_t lsm6dso_auto_increment_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01750 01751 int32_t lsm6dso_boot_set(lsm6dso_ctx_t *ctx, uint8_t val); 01752 int32_t lsm6dso_boot_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01753 01754 typedef enum { 01755 LSM6DSO_XL_ST_DISABLE = 0, 01756 LSM6DSO_XL_ST_POSITIVE = 1, 01757 LSM6DSO_XL_ST_NEGATIVE = 2, 01758 } lsm6dso_st_xl_t; 01759 int32_t lsm6dso_xl_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_xl_t val); 01760 int32_t lsm6dso_xl_self_test_get(lsm6dso_ctx_t *ctx, lsm6dso_st_xl_t *val); 01761 01762 typedef enum { 01763 LSM6DSO_GY_ST_DISABLE = 0, 01764 LSM6DSO_GY_ST_POSITIVE = 1, 01765 LSM6DSO_GY_ST_NEGATIVE = 3, 01766 } lsm6dso_st_g_t; 01767 int32_t lsm6dso_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_g_t val); 01768 int32_t lsm6dso_gy_self_test_get(lsm6dso_ctx_t *ctx, lsm6dso_st_g_t *val); 01769 01770 int32_t lsm6dso_xl_filter_lp2_set(lsm6dso_ctx_t *ctx, uint8_t val); 01771 int32_t lsm6dso_xl_filter_lp2_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01772 01773 int32_t lsm6dso_gy_filter_lp1_set(lsm6dso_ctx_t *ctx, uint8_t val); 01774 int32_t lsm6dso_gy_filter_lp1_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01775 01776 int32_t lsm6dso_filter_settling_mask_set(lsm6dso_ctx_t *ctx, 01777 uint8_t val); 01778 int32_t lsm6dso_filter_settling_mask_get(lsm6dso_ctx_t *ctx, 01779 uint8_t *val); 01780 01781 typedef enum { 01782 LSM6DSO_ULTRA_LIGHT = 0, 01783 LSM6DSO_VERY_LIGHT = 1, 01784 LSM6DSO_LIGHT = 2, 01785 LSM6DSO_MEDIUM = 3, 01786 LSM6DSO_STRONG = 4, /* not available for data rate > 1k670Hz */ 01787 LSM6DSO_VERY_STRONG = 5, /* not available for data rate > 1k670Hz */ 01788 LSM6DSO_AGGRESSIVE = 6, /* not available for data rate > 1k670Hz */ 01789 LSM6DSO_XTREME = 7, /* not available for data rate > 1k670Hz */ 01790 } lsm6dso_ftype_t; 01791 int32_t lsm6dso_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx, 01792 lsm6dso_ftype_t val); 01793 int32_t lsm6dso_gy_lp1_bandwidth_get(lsm6dso_ctx_t *ctx, 01794 lsm6dso_ftype_t *val); 01795 01796 int32_t lsm6dso_xl_lp2_on_6d_set(lsm6dso_ctx_t *ctx, uint8_t val); 01797 int32_t lsm6dso_xl_lp2_on_6d_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01798 01799 typedef enum { 01800 LSM6DSO_HP_PATH_DISABLE_ON_OUT = 0x00, 01801 LSM6DSO_SLOPE_ODR_DIV_4 = 0x10, 01802 LSM6DSO_HP_ODR_DIV_10 = 0x11, 01803 LSM6DSO_HP_ODR_DIV_20 = 0x12, 01804 LSM6DSO_HP_ODR_DIV_45 = 0x13, 01805 LSM6DSO_HP_ODR_DIV_100 = 0x14, 01806 LSM6DSO_HP_ODR_DIV_200 = 0x15, 01807 LSM6DSO_HP_ODR_DIV_400 = 0x16, 01808 LSM6DSO_HP_ODR_DIV_800 = 0x17, 01809 LSM6DSO_HP_REF_MD_ODR_DIV_10 = 0x31, 01810 LSM6DSO_HP_REF_MD_ODR_DIV_20 = 0x32, 01811 LSM6DSO_HP_REF_MD_ODR_DIV_45 = 0x33, 01812 LSM6DSO_HP_REF_MD_ODR_DIV_100 = 0x34, 01813 LSM6DSO_HP_REF_MD_ODR_DIV_200 = 0x35, 01814 LSM6DSO_HP_REF_MD_ODR_DIV_400 = 0x36, 01815 LSM6DSO_HP_REF_MD_ODR_DIV_800 = 0x37, 01816 LSM6DSO_LP_ODR_DIV_10 = 0x01, 01817 LSM6DSO_LP_ODR_DIV_20 = 0x02, 01818 LSM6DSO_LP_ODR_DIV_45 = 0x03, 01819 LSM6DSO_LP_ODR_DIV_100 = 0x04, 01820 LSM6DSO_LP_ODR_DIV_200 = 0x05, 01821 LSM6DSO_LP_ODR_DIV_400 = 0x06, 01822 LSM6DSO_LP_ODR_DIV_800 = 0x07, 01823 } lsm6dso_hp_slope_xl_en_t; 01824 int32_t lsm6dso_xl_hp_path_on_out_set(lsm6dso_ctx_t *ctx, 01825 lsm6dso_hp_slope_xl_en_t val); 01826 int32_t lsm6dso_xl_hp_path_on_out_get(lsm6dso_ctx_t *ctx, 01827 lsm6dso_hp_slope_xl_en_t *val); 01828 01829 int32_t lsm6dso_xl_fast_settling_set(lsm6dso_ctx_t *ctx, uint8_t val); 01830 int32_t lsm6dso_xl_fast_settling_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01831 01832 typedef enum { 01833 LSM6DSO_USE_SLOPE = 0, 01834 LSM6DSO_USE_HPF = 1, 01835 } lsm6dso_slope_fds_t; 01836 int32_t lsm6dso_xl_hp_path_internal_set(lsm6dso_ctx_t *ctx, 01837 lsm6dso_slope_fds_t val); 01838 int32_t lsm6dso_xl_hp_path_internal_get(lsm6dso_ctx_t *ctx, 01839 lsm6dso_slope_fds_t *val); 01840 01841 typedef enum { 01842 LSM6DSO_HP_FILTER_NONE = 0x00, 01843 LSM6DSO_HP_FILTER_16mHz = 0x80, 01844 LSM6DSO_HP_FILTER_65mHz = 0x81, 01845 LSM6DSO_HP_FILTER_260mHz = 0x82, 01846 LSM6DSO_HP_FILTER_1Hz04 = 0x83, 01847 } lsm6dso_hpm_g_t; 01848 int32_t lsm6dso_gy_hp_path_internal_set(lsm6dso_ctx_t *ctx, 01849 lsm6dso_hpm_g_t val); 01850 int32_t lsm6dso_gy_hp_path_internal_get(lsm6dso_ctx_t *ctx, 01851 lsm6dso_hpm_g_t *val); 01852 01853 typedef enum { 01854 LSM6DSO_AUX_PULL_UP_DISC = 0, 01855 LSM6DSO_AUX_PULL_UP_CONNECT = 1, 01856 } lsm6dso_ois_pu_dis_t; 01857 int32_t lsm6dso_aux_sdo_ocs_mode_set(lsm6dso_ctx_t *ctx, 01858 lsm6dso_ois_pu_dis_t val); 01859 int32_t lsm6dso_aux_sdo_ocs_mode_get(lsm6dso_ctx_t *ctx, 01860 lsm6dso_ois_pu_dis_t *val); 01861 01862 typedef enum { 01863 LSM6DSO_AUX_ON = 1, 01864 LSM6DSO_AUX_ON_BY_AUX_INTERFACE = 0, 01865 } lsm6dso_ois_on_t; 01866 int32_t lsm6dso_aux_pw_on_ctrl_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_on_t val); 01867 int32_t lsm6dso_aux_pw_on_ctrl_get(lsm6dso_ctx_t *ctx, lsm6dso_ois_on_t *val); 01868 01869 typedef enum { 01870 LSM6DSO_USE_SAME_XL_FS = 0, 01871 LSM6DSO_USE_DIFFERENT_XL_FS = 1, 01872 } lsm6dso_xl_fs_mode_t; 01873 int32_t lsm6dso_aux_xl_fs_mode_set(lsm6dso_ctx_t *ctx, 01874 lsm6dso_xl_fs_mode_t val); 01875 int32_t lsm6dso_aux_xl_fs_mode_get(lsm6dso_ctx_t *ctx, 01876 lsm6dso_xl_fs_mode_t *val); 01877 01878 int32_t lsm6dso_aux_status_reg_get(lsm6dso_ctx_t *ctx, 01879 lsm6dso_status_spiaux_t *val); 01880 01881 int32_t lsm6dso_aux_xl_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01882 01883 int32_t lsm6dso_aux_gy_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01884 01885 int32_t lsm6dso_aux_gy_flag_settling_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01886 01887 typedef enum { 01888 LSM6DSO_AUX_XL_DISABLE = 0, 01889 LSM6DSO_AUX_XL_POS = 1, 01890 LSM6DSO_AUX_XL_NEG = 2, 01891 } lsm6dso_st_xl_ois_t; 01892 int32_t lsm6dso_aux_xl_self_test_set(lsm6dso_ctx_t *ctx, 01893 lsm6dso_st_xl_ois_t val); 01894 int32_t lsm6dso_aux_xl_self_test_get(lsm6dso_ctx_t *ctx, 01895 lsm6dso_st_xl_ois_t *val); 01896 01897 typedef enum { 01898 LSM6DSO_AUX_DEN_ACTIVE_LOW = 0, 01899 LSM6DSO_AUX_DEN_ACTIVE_HIGH = 1, 01900 } lsm6dso_den_lh_ois_t; 01901 int32_t lsm6dso_aux_den_polarity_set(lsm6dso_ctx_t *ctx, 01902 lsm6dso_den_lh_ois_t val); 01903 int32_t lsm6dso_aux_den_polarity_get(lsm6dso_ctx_t *ctx, 01904 lsm6dso_den_lh_ois_t *val); 01905 01906 typedef enum { 01907 LSM6DSO_AUX_DEN_DISABLE = 0, 01908 LSM6DSO_AUX_DEN_LEVEL_LATCH = 3, 01909 LSM6DSO_AUX_DEN_LEVEL_TRIG = 2, 01910 } lsm6dso_lvl2_ois_t; 01911 int32_t lsm6dso_aux_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_lvl2_ois_t val); 01912 int32_t lsm6dso_aux_den_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_lvl2_ois_t *val); 01913 01914 int32_t lsm6dso_aux_drdy_on_int2_set(lsm6dso_ctx_t *ctx, uint8_t val); 01915 int32_t lsm6dso_aux_drdy_on_int2_get(lsm6dso_ctx_t *ctx, uint8_t *val); 01916 01917 typedef enum { 01918 LSM6DSO_AUX_DISABLE = 0, 01919 LSM6DSO_MODE_3_GY = 1, 01920 LSM6DSO_MODE_4_GY_XL = 3, 01921 } lsm6dso_ois_en_spi2_t; 01922 int32_t lsm6dso_aux_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_en_spi2_t val); 01923 int32_t lsm6dso_aux_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_ois_en_spi2_t *val); 01924 01925 typedef enum { 01926 LSM6DSO_250dps_AUX = 0, 01927 LSM6DSO_125dps_AUX = 1, 01928 LSM6DSO_500dps_AUX = 2, 01929 LSM6DSO_1000dps_AUX = 4, 01930 LSM6DSO_2000dps_AUX = 6, 01931 } lsm6dso_fs_g_ois_t; 01932 int32_t lsm6dso_aux_gy_full_scale_set(lsm6dso_ctx_t *ctx, 01933 lsm6dso_fs_g_ois_t val); 01934 int32_t lsm6dso_aux_gy_full_scale_get(lsm6dso_ctx_t *ctx, 01935 lsm6dso_fs_g_ois_t *val); 01936 01937 typedef enum { 01938 LSM6DSO_AUX_SPI_4_WIRE = 0, 01939 LSM6DSO_AUX_SPI_3_WIRE = 1, 01940 } lsm6dso_sim_ois_t; 01941 int32_t lsm6dso_aux_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_ois_t val); 01942 int32_t lsm6dso_aux_spi_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_sim_ois_t *val); 01943 01944 typedef enum { 01945 LSM6DSO_351Hz39 = 0, 01946 LSM6DSO_236Hz63 = 1, 01947 LSM6DSO_172Hz70 = 2, 01948 LSM6DSO_937Hz91 = 3, 01949 } lsm6dso_ftype_ois_t; 01950 int32_t lsm6dso_aux_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx, 01951 lsm6dso_ftype_ois_t val); 01952 int32_t lsm6dso_aux_gy_lp1_bandwidth_get(lsm6dso_ctx_t *ctx, 01953 lsm6dso_ftype_ois_t *val); 01954 01955 typedef enum { 01956 LSM6DSO_AUX_HP_DISABLE = 0x00, 01957 LSM6DSO_AUX_HP_Hz016 = 0x10, 01958 LSM6DSO_AUX_HP_Hz065 = 0x11, 01959 LSM6DSO_AUX_HP_Hz260 = 0x12, 01960 LSM6DSO_AUX_HP_1Hz040 = 0x13, 01961 } lsm6dso_hpm_ois_t; 01962 int32_t lsm6dso_aux_gy_hp_bandwidth_set(lsm6dso_ctx_t *ctx, 01963 lsm6dso_hpm_ois_t val); 01964 int32_t lsm6dso_aux_gy_hp_bandwidth_get(lsm6dso_ctx_t *ctx, 01965 lsm6dso_hpm_ois_t *val); 01966 01967 typedef enum { 01968 LSM6DSO_ENABLE_CLAMP = 0, 01969 LSM6DSO_DISABLE_CLAMP = 1, 01970 } lsm6dso_st_ois_clampdis_t; 01971 int32_t lsm6dso_aux_gy_clamp_set(lsm6dso_ctx_t *ctx, 01972 lsm6dso_st_ois_clampdis_t val); 01973 int32_t lsm6dso_aux_gy_clamp_get(lsm6dso_ctx_t *ctx, 01974 lsm6dso_st_ois_clampdis_t *val); 01975 01976 typedef enum { 01977 LSM6DSO_AUX_GY_DISABLE = 0, 01978 LSM6DSO_AUX_GY_POS = 1, 01979 LSM6DSO_AUX_GY_NEG = 3, 01980 } lsm6dso_st_ois_t; 01981 int32_t lsm6dso_aux_gy_self_test_set(lsm6dso_ctx_t *ctx, 01982 lsm6dso_st_ois_t val); 01983 int32_t lsm6dso_aux_gy_self_test_get(lsm6dso_ctx_t *ctx, 01984 lsm6dso_st_ois_t *val); 01985 01986 typedef enum { 01987 LSM6DSO_289Hz = 0, 01988 LSM6DSO_258Hz = 1, 01989 LSM6DSO_120Hz = 2, 01990 LSM6DSO_65Hz2 = 3, 01991 LSM6DSO_33Hz2 = 4, 01992 LSM6DSO_16Hz6 = 5, 01993 LSM6DSO_8Hz30 = 6, 01994 LSM6DSO_4Hz15 = 7, 01995 } lsm6dso_filter_xl_conf_ois_t; 01996 int32_t lsm6dso_aux_xl_bandwidth_set(lsm6dso_ctx_t *ctx, 01997 lsm6dso_filter_xl_conf_ois_t val); 01998 int32_t lsm6dso_aux_xl_bandwidth_get(lsm6dso_ctx_t *ctx, 01999 lsm6dso_filter_xl_conf_ois_t *val); 02000 02001 typedef enum { 02002 LSM6DSO_AUX_2g = 0, 02003 LSM6DSO_AUX_16g = 1, 02004 LSM6DSO_AUX_4g = 2, 02005 LSM6DSO_AUX_8g = 3, 02006 } lsm6dso_fs_xl_ois_t; 02007 int32_t lsm6dso_aux_xl_full_scale_set(lsm6dso_ctx_t *ctx, 02008 lsm6dso_fs_xl_ois_t val); 02009 int32_t lsm6dso_aux_xl_full_scale_get(lsm6dso_ctx_t *ctx, 02010 lsm6dso_fs_xl_ois_t *val); 02011 02012 typedef enum { 02013 LSM6DSO_PULL_UP_DISC = 0, 02014 LSM6DSO_PULL_UP_CONNECT = 1, 02015 } lsm6dso_sdo_pu_en_t; 02016 int32_t lsm6dso_sdo_sa0_mode_set(lsm6dso_ctx_t *ctx, 02017 lsm6dso_sdo_pu_en_t val); 02018 int32_t lsm6dso_sdo_sa0_mode_get(lsm6dso_ctx_t *ctx, 02019 lsm6dso_sdo_pu_en_t *val); 02020 02021 typedef enum { 02022 LSM6DSO_SPI_4_WIRE = 0, 02023 LSM6DSO_SPI_3_WIRE = 1, 02024 } lsm6dso_sim_t; 02025 int32_t lsm6dso_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_t val); 02026 int32_t lsm6dso_spi_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_sim_t *val); 02027 02028 typedef enum { 02029 LSM6DSO_I2C_ENABLE = 0, 02030 LSM6DSO_I2C_DISABLE = 1, 02031 } lsm6dso_i2c_disable_t; 02032 int32_t lsm6dso_i2c_interface_set(lsm6dso_ctx_t *ctx, 02033 lsm6dso_i2c_disable_t val); 02034 int32_t lsm6dso_i2c_interface_get(lsm6dso_ctx_t *ctx, 02035 lsm6dso_i2c_disable_t *val); 02036 02037 typedef enum { 02038 LSM6DSO_I3C_DISABLE = 0x80, 02039 LSM6DSO_I3C_ENABLE_T_50us = 0x00, 02040 LSM6DSO_I3C_ENABLE_T_2us = 0x01, 02041 LSM6DSO_I3C_ENABLE_T_1ms = 0x02, 02042 LSM6DSO_I3C_ENABLE_T_25ms = 0x03, 02043 } lsm6dso_i3c_disable_t; 02044 int32_t lsm6dso_i3c_disable_set(lsm6dso_ctx_t *ctx, 02045 lsm6dso_i3c_disable_t val); 02046 int32_t lsm6dso_i3c_disable_get(lsm6dso_ctx_t *ctx, 02047 lsm6dso_i3c_disable_t *val); 02048 02049 typedef enum { 02050 LSM6DSO_PULL_DOWN_DISC = 0, 02051 LSM6DSO_PULL_DOWN_CONNECT = 1, 02052 } lsm6dso_int1_pd_en_t; 02053 int32_t lsm6dso_int1_mode_set(lsm6dso_ctx_t *ctx, 02054 lsm6dso_int1_pd_en_t val); 02055 int32_t lsm6dso_int1_mode_get(lsm6dso_ctx_t *ctx, 02056 lsm6dso_int1_pd_en_t *val); 02057 02058 typedef enum { 02059 LSM6DSO_PUSH_PULL = 0, 02060 LSM6DSO_OPEN_DRAIN = 1, 02061 } lsm6dso_pp_od_t; 02062 int32_t lsm6dso_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_pp_od_t val); 02063 int32_t lsm6dso_pin_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_pp_od_t *val); 02064 02065 typedef enum { 02066 LSM6DSO_ACTIVE_HIGH = 0, 02067 LSM6DSO_ACTIVE_LOW = 1, 02068 } lsm6dso_h_lactive_t; 02069 int32_t lsm6dso_pin_polarity_set(lsm6dso_ctx_t *ctx, 02070 lsm6dso_h_lactive_t val); 02071 int32_t lsm6dso_pin_polarity_get(lsm6dso_ctx_t *ctx, 02072 lsm6dso_h_lactive_t *val); 02073 02074 int32_t lsm6dso_all_on_int1_set(lsm6dso_ctx_t *ctx, uint8_t val); 02075 int32_t lsm6dso_all_on_int1_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02076 02077 typedef enum { 02078 LSM6DSO_ALL_INT_PULSED = 0, 02079 LSM6DSO_BASE_LATCHED_EMB_PULSED = 1, 02080 LSM6DSO_BASE_PULSED_EMB_LATCHED = 2, 02081 LSM6DSO_ALL_INT_LATCHED = 3, 02082 } lsm6dso_lir_t; 02083 int32_t lsm6dso_int_notification_set(lsm6dso_ctx_t *ctx, lsm6dso_lir_t val); 02084 int32_t lsm6dso_int_notification_get(lsm6dso_ctx_t *ctx, lsm6dso_lir_t *val); 02085 02086 typedef enum { 02087 LSM6DSO_LSb_FS_DIV_64 = 0, 02088 LSM6DSO_LSb_FS_DIV_256 = 1, 02089 } lsm6dso_wake_ths_w_t; 02090 int32_t lsm6dso_wkup_ths_weight_set(lsm6dso_ctx_t *ctx, 02091 lsm6dso_wake_ths_w_t val); 02092 int32_t lsm6dso_wkup_ths_weight_get(lsm6dso_ctx_t *ctx, 02093 lsm6dso_wake_ths_w_t *val); 02094 02095 int32_t lsm6dso_wkup_threshold_set(lsm6dso_ctx_t *ctx, uint8_t val); 02096 int32_t lsm6dso_wkup_threshold_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02097 02098 int32_t lsm6dso_xl_usr_offset_on_wkup_set(lsm6dso_ctx_t *ctx, uint8_t val); 02099 int32_t lsm6dso_xl_usr_offset_on_wkup_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02100 02101 int32_t lsm6dso_wkup_dur_set(lsm6dso_ctx_t *ctx, uint8_t val); 02102 int32_t lsm6dso_wkup_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02103 02104 int32_t lsm6dso_gy_sleep_mode_set(lsm6dso_ctx_t *ctx, uint8_t val); 02105 int32_t lsm6dso_gy_sleep_mode_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02106 02107 typedef enum { 02108 LSM6DSO_DRIVE_SLEEP_CHG_EVENT = 0, 02109 LSM6DSO_DRIVE_SLEEP_STATUS = 1, 02110 } lsm6dso_sleep_status_on_int_t; 02111 int32_t lsm6dso_act_pin_notification_set(lsm6dso_ctx_t *ctx, 02112 lsm6dso_sleep_status_on_int_t val); 02113 int32_t lsm6dso_act_pin_notification_get(lsm6dso_ctx_t *ctx, 02114 lsm6dso_sleep_status_on_int_t *val); 02115 02116 typedef enum { 02117 LSM6DSO_XL_AND_GY_NOT_AFFECTED = 0, 02118 LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED = 1, 02119 LSM6DSO_XL_12Hz5_GY_SLEEP = 2, 02120 LSM6DSO_XL_12Hz5_GY_PD = 3, 02121 } lsm6dso_inact_en_t; 02122 int32_t lsm6dso_act_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_inact_en_t val); 02123 int32_t lsm6dso_act_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_inact_en_t *val); 02124 02125 int32_t lsm6dso_act_sleep_dur_set(lsm6dso_ctx_t *ctx, uint8_t val); 02126 int32_t lsm6dso_act_sleep_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02127 02128 int32_t lsm6dso_tap_detection_on_z_set(lsm6dso_ctx_t *ctx, uint8_t val); 02129 int32_t lsm6dso_tap_detection_on_z_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02130 02131 int32_t lsm6dso_tap_detection_on_y_set(lsm6dso_ctx_t *ctx, uint8_t val); 02132 int32_t lsm6dso_tap_detection_on_y_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02133 02134 int32_t lsm6dso_tap_detection_on_x_set(lsm6dso_ctx_t *ctx, uint8_t val); 02135 int32_t lsm6dso_tap_detection_on_x_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02136 02137 int32_t lsm6dso_tap_threshold_x_set(lsm6dso_ctx_t *ctx, uint8_t val); 02138 int32_t lsm6dso_tap_threshold_x_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02139 02140 typedef enum { 02141 LSM6DSO_XYZ = 0, 02142 LSM6DSO_YXZ = 1, 02143 LSM6DSO_XZY = 2, 02144 LSM6DSO_ZYX = 3, 02145 LSM6DSO_YZX = 5, 02146 LSM6DSO_ZXY = 6, 02147 } lsm6dso_tap_priority_t; 02148 int32_t lsm6dso_tap_axis_priority_set(lsm6dso_ctx_t *ctx, 02149 lsm6dso_tap_priority_t val); 02150 int32_t lsm6dso_tap_axis_priority_get(lsm6dso_ctx_t *ctx, 02151 lsm6dso_tap_priority_t *val); 02152 02153 int32_t lsm6dso_tap_threshold_y_set(lsm6dso_ctx_t *ctx, uint8_t val); 02154 int32_t lsm6dso_tap_threshold_y_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02155 02156 int32_t lsm6dso_tap_threshold_z_set(lsm6dso_ctx_t *ctx, uint8_t val); 02157 int32_t lsm6dso_tap_threshold_z_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02158 02159 int32_t lsm6dso_tap_shock_set(lsm6dso_ctx_t *ctx, uint8_t val); 02160 int32_t lsm6dso_tap_shock_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02161 02162 int32_t lsm6dso_tap_quiet_set(lsm6dso_ctx_t *ctx, uint8_t val); 02163 int32_t lsm6dso_tap_quiet_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02164 02165 int32_t lsm6dso_tap_dur_set(lsm6dso_ctx_t *ctx, uint8_t val); 02166 int32_t lsm6dso_tap_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02167 02168 typedef enum { 02169 LSM6DSO_ONLY_SINGLE = 0, 02170 LSM6DSO_BOTH_SINGLE_DOUBLE = 1, 02171 } lsm6dso_single_double_tap_t; 02172 int32_t lsm6dso_tap_mode_set(lsm6dso_ctx_t *ctx, 02173 lsm6dso_single_double_tap_t val); 02174 int32_t lsm6dso_tap_mode_get(lsm6dso_ctx_t *ctx, 02175 lsm6dso_single_double_tap_t *val); 02176 02177 typedef enum { 02178 LSM6DSO_DEG_80 = 0, 02179 LSM6DSO_DEG_70 = 1, 02180 LSM6DSO_DEG_60 = 2, 02181 LSM6DSO_DEG_50 = 3, 02182 } lsm6dso_sixd_ths_t; 02183 int32_t lsm6dso_6d_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_sixd_ths_t val); 02184 int32_t lsm6dso_6d_threshold_get(lsm6dso_ctx_t *ctx, lsm6dso_sixd_ths_t *val); 02185 02186 int32_t lsm6dso_4d_mode_set(lsm6dso_ctx_t *ctx, uint8_t val); 02187 int32_t lsm6dso_4d_mode_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02188 02189 typedef enum { 02190 LSM6DSO_FF_TSH_156mg = 0, 02191 LSM6DSO_FF_TSH_219mg = 1, 02192 LSM6DSO_FF_TSH_250mg = 2, 02193 LSM6DSO_FF_TSH_312mg = 3, 02194 LSM6DSO_FF_TSH_344mg = 4, 02195 LSM6DSO_FF_TSH_406mg = 5, 02196 LSM6DSO_FF_TSH_469mg = 6, 02197 LSM6DSO_FF_TSH_500mg = 7, 02198 } lsm6dso_ff_ths_t; 02199 int32_t lsm6dso_ff_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_ff_ths_t val); 02200 int32_t lsm6dso_ff_threshold_get(lsm6dso_ctx_t *ctx, lsm6dso_ff_ths_t *val); 02201 02202 int32_t lsm6dso_ff_dur_set(lsm6dso_ctx_t *ctx, uint8_t val); 02203 int32_t lsm6dso_ff_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02204 02205 int32_t lsm6dso_fifo_watermark_set(lsm6dso_ctx_t *ctx, uint16_t val); 02206 int32_t lsm6dso_fifo_watermark_get(lsm6dso_ctx_t *ctx, uint16_t *val); 02207 02208 int32_t lsm6dso_compression_algo_init_set(lsm6dso_ctx_t *ctx, uint8_t val); 02209 int32_t lsm6dso_compression_algo_init_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02210 02211 typedef enum { 02212 LSM6DSO_CMP_DISABLE = 0x00, 02213 LSM6DSO_CMP_ALWAYS = 0x04, 02214 LSM6DSO_CMP_8_TO_1 = 0x05, 02215 LSM6DSO_CMP_16_TO_1 = 0x06, 02216 LSM6DSO_CMP_32_TO_1 = 0x07, 02217 } lsm6dso_uncoptr_rate_t; 02218 int32_t lsm6dso_compression_algo_set(lsm6dso_ctx_t *ctx, 02219 lsm6dso_uncoptr_rate_t val); 02220 int32_t lsm6dso_compression_algo_get(lsm6dso_ctx_t *ctx, 02221 lsm6dso_uncoptr_rate_t *val); 02222 02223 int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(lsm6dso_ctx_t *ctx, 02224 uint8_t val); 02225 int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(lsm6dso_ctx_t *ctx, 02226 uint8_t *val); 02227 02228 int32_t lsm6dso_compression_algo_real_time_set(lsm6dso_ctx_t *ctx, 02229 uint8_t val); 02230 int32_t lsm6dso_compression_algo_real_time_get(lsm6dso_ctx_t *ctx, 02231 uint8_t *val); 02232 02233 int32_t lsm6dso_fifo_stop_on_wtm_set(lsm6dso_ctx_t *ctx, uint8_t val); 02234 int32_t lsm6dso_fifo_stop_on_wtm_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02235 02236 typedef enum { 02237 LSM6DSO_XL_NOT_BATCHED = 0, 02238 LSM6DSO_XL_BATCHED_AT_12Hz5 = 1, 02239 LSM6DSO_XL_BATCHED_AT_26Hz = 2, 02240 LSM6DSO_XL_BATCHED_AT_52Hz = 3, 02241 LSM6DSO_XL_BATCHED_AT_104Hz = 4, 02242 LSM6DSO_XL_BATCHED_AT_208Hz = 5, 02243 LSM6DSO_XL_BATCHED_AT_417Hz = 6, 02244 LSM6DSO_XL_BATCHED_AT_833Hz = 7, 02245 LSM6DSO_XL_BATCHED_AT_1667Hz = 8, 02246 LSM6DSO_XL_BATCHED_AT_3333Hz = 9, 02247 LSM6DSO_XL_BATCHED_AT_6667Hz = 10, 02248 LSM6DSO_XL_BATCHED_AT_6Hz5 = 11, 02249 } lsm6dso_bdr_xl_t; 02250 int32_t lsm6dso_fifo_xl_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_xl_t val); 02251 int32_t lsm6dso_fifo_xl_batch_get(lsm6dso_ctx_t *ctx, lsm6dso_bdr_xl_t *val); 02252 02253 typedef enum { 02254 LSM6DSO_GY_NOT_BATCHED = 0, 02255 LSM6DSO_GY_BATCHED_AT_12Hz5 = 1, 02256 LSM6DSO_GY_BATCHED_AT_26Hz = 2, 02257 LSM6DSO_GY_BATCHED_AT_52Hz = 3, 02258 LSM6DSO_GY_BATCHED_AT_104Hz = 4, 02259 LSM6DSO_GY_BATCHED_AT_208Hz = 5, 02260 LSM6DSO_GY_BATCHED_AT_417Hz = 6, 02261 LSM6DSO_GY_BATCHED_AT_833Hz = 7, 02262 LSM6DSO_GY_BATCHED_AT_1667Hz = 8, 02263 LSM6DSO_GY_BATCHED_AT_3333Hz = 9, 02264 LSM6DSO_GY_BATCHED_AT_6667Hz = 10, 02265 LSM6DSO_GY_BATCHED_AT_6Hz5 = 11, 02266 } lsm6dso_bdr_gy_t; 02267 int32_t lsm6dso_fifo_gy_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_gy_t val); 02268 int32_t lsm6dso_fifo_gy_batch_get(lsm6dso_ctx_t *ctx, lsm6dso_bdr_gy_t *val); 02269 02270 typedef enum { 02271 LSM6DSO_BYPASS_MODE = 0, 02272 LSM6DSO_FIFO_MODE = 1, 02273 LSM6DSO_STREAM_TO_FIFO_MODE = 3, 02274 LSM6DSO_BYPASS_TO_STREAM_MODE = 4, 02275 LSM6DSO_STREAM_MODE = 6, 02276 LSM6DSO_BYPASS_TO_FIFO_MODE = 7, 02277 } lsm6dso_fifo_mode_t; 02278 int32_t lsm6dso_fifo_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_fifo_mode_t val); 02279 int32_t lsm6dso_fifo_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_fifo_mode_t *val); 02280 02281 typedef enum { 02282 LSM6DSO_TEMP_NOT_BATCHED = 0, 02283 LSM6DSO_TEMP_BATCHED_AT_1Hz6 = 1, 02284 LSM6DSO_TEMP_BATCHED_AT_12Hz5 = 2, 02285 LSM6DSO_TEMP_BATCHED_AT_52Hz = 3, 02286 } lsm6dso_odr_t_batch_t; 02287 int32_t lsm6dso_fifo_temp_batch_set(lsm6dso_ctx_t *ctx, 02288 lsm6dso_odr_t_batch_t val); 02289 int32_t lsm6dso_fifo_temp_batch_get(lsm6dso_ctx_t *ctx, 02290 lsm6dso_odr_t_batch_t *val); 02291 02292 typedef enum { 02293 LSM6DSO_NO_DECIMATION = 0, 02294 LSM6DSO_DEC_1 = 1, 02295 LSM6DSO_DEC_8 = 2, 02296 LSM6DSO_DEC_32 = 3, 02297 } lsm6dso_odr_ts_batch_t; 02298 int32_t lsm6dso_fifo_timestamp_decimation_set(lsm6dso_ctx_t *ctx, 02299 lsm6dso_odr_ts_batch_t val); 02300 int32_t lsm6dso_fifo_timestamp_decimation_get(lsm6dso_ctx_t *ctx, 02301 lsm6dso_odr_ts_batch_t *val); 02302 02303 typedef enum { 02304 LSM6DSO_XL_BATCH_EVENT = 0, 02305 LSM6DSO_GYRO_BATCH_EVENT = 1, 02306 } lsm6dso_trig_counter_bdr_t; 02307 02308 typedef enum { 02309 LSM6DSO_GYRO_NC_TAG = 1, 02310 LSM6DSO_XL_NC_TAG, 02311 LSM6DSO_TEMPERATURE_TAG, 02312 LSM6DSO_TIMESTAMP_TAG, 02313 LSM6DSO_CFG_CHANGE_TAG, 02314 LSM6DSO_XL_NC_T_2_TAG, 02315 LSM6DSO_XL_NC_T_1_TAG, 02316 LSM6DSO_XL_2XC_TAG, 02317 LSM6DSO_XL_3XC_TAG, 02318 LSM6DSO_GYRO_NC_T_2_TAG, 02319 LSM6DSO_GYRO_NC_T_1_TAG, 02320 LSM6DSO_GYRO_2XC_TAG, 02321 LSM6DSO_GYRO_3XC_TAG, 02322 LSM6DSO_SENSORHUB_SLAVE0_TAG, 02323 LSM6DSO_SENSORHUB_SLAVE1_TAG, 02324 LSM6DSO_SENSORHUB_SLAVE2_TAG, 02325 LSM6DSO_SENSORHUB_SLAVE3_TAG, 02326 LSM6DSO_STEP_CPUNTER_TAG, 02327 LSM6DSO_GAME_ROTATION_TAG, 02328 LSM6DSO_GEOMAG_ROTATION_TAG, 02329 LSM6DSO_ROTATION_TAG, 02330 LSM6DSO_SENSORHUB_NACK_TAG = 0x19, 02331 } lsm6dso_fifo_tag_t; 02332 int32_t lsm6dso_fifo_cnt_event_batch_set(lsm6dso_ctx_t *ctx, 02333 lsm6dso_trig_counter_bdr_t val); 02334 int32_t lsm6dso_fifo_cnt_event_batch_get(lsm6dso_ctx_t *ctx, 02335 lsm6dso_trig_counter_bdr_t *val); 02336 02337 int32_t lsm6dso_rst_batch_counter_set(lsm6dso_ctx_t *ctx, uint8_t val); 02338 int32_t lsm6dso_rst_batch_counter_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02339 02340 int32_t lsm6dso_batch_counter_threshold_set(lsm6dso_ctx_t *ctx, 02341 uint16_t val); 02342 int32_t lsm6dso_batch_counter_threshold_get(lsm6dso_ctx_t *ctx, 02343 uint16_t *val); 02344 02345 int32_t lsm6dso_fifo_data_level_get(lsm6dso_ctx_t *ctx, uint16_t *val); 02346 02347 int32_t lsm6dso_fifo_status_get(lsm6dso_ctx_t *ctx, 02348 lsm6dso_fifo_status2_t *val); 02349 02350 int32_t lsm6dso_fifo_full_flag_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02351 02352 int32_t lsm6dso_fifo_ovr_flag_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02353 02354 int32_t lsm6dso_fifo_wtm_flag_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02355 02356 int32_t lsm6dso_fifo_sensor_tag_get(lsm6dso_ctx_t *ctx, 02357 lsm6dso_fifo_tag_t *val); 02358 02359 int32_t lsm6dso_fifo_pedo_batch_set(lsm6dso_ctx_t *ctx, uint8_t val); 02360 int32_t lsm6dso_fifo_pedo_batch_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02361 02362 int32_t lsm6dso_sh_batch_slave_0_set(lsm6dso_ctx_t *ctx, uint8_t val); 02363 int32_t lsm6dso_sh_batch_slave_0_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02364 02365 int32_t lsm6dso_sh_batch_slave_1_set(lsm6dso_ctx_t *ctx, uint8_t val); 02366 int32_t lsm6dso_sh_batch_slave_1_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02367 02368 int32_t lsm6dso_sh_batch_slave_2_set(lsm6dso_ctx_t *ctx, uint8_t val); 02369 int32_t lsm6dso_sh_batch_slave_2_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02370 02371 int32_t lsm6dso_sh_batch_slave_3_set(lsm6dso_ctx_t *ctx, uint8_t val); 02372 int32_t lsm6dso_sh_batch_slave_3_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02373 02374 typedef enum { 02375 LSM6DSO_DEN_DISABLE = 0, 02376 LSM6DSO_LEVEL_FIFO = 6, 02377 LSM6DSO_LEVEL_LETCHED = 3, 02378 LSM6DSO_LEVEL_TRIGGER = 2, 02379 LSM6DSO_EDGE_TRIGGER = 4, 02380 } lsm6dso_den_mode_t; 02381 int32_t lsm6dso_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_den_mode_t val); 02382 int32_t lsm6dso_den_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_den_mode_t *val); 02383 02384 typedef enum { 02385 LSM6DSO_DEN_ACT_LOW = 0, 02386 LSM6DSO_DEN_ACT_HIGH = 1, 02387 } lsm6dso_den_lh_t; 02388 int32_t lsm6dso_den_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_den_lh_t val); 02389 int32_t lsm6dso_den_polarity_get(lsm6dso_ctx_t *ctx, lsm6dso_den_lh_t *val); 02390 02391 typedef enum { 02392 LSM6DSO_STAMP_IN_GY_DATA = 0, 02393 LSM6DSO_STAMP_IN_XL_DATA = 1, 02394 LSM6DSO_STAMP_IN_GY_XL_DATA = 2, 02395 } lsm6dso_den_xl_g_t; 02396 int32_t lsm6dso_den_enable_set(lsm6dso_ctx_t *ctx, lsm6dso_den_xl_g_t val); 02397 int32_t lsm6dso_den_enable_get(lsm6dso_ctx_t *ctx, lsm6dso_den_xl_g_t *val); 02398 02399 int32_t lsm6dso_den_mark_axis_x_set(lsm6dso_ctx_t *ctx, uint8_t val); 02400 int32_t lsm6dso_den_mark_axis_x_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02401 02402 int32_t lsm6dso_den_mark_axis_y_set(lsm6dso_ctx_t *ctx, uint8_t val); 02403 int32_t lsm6dso_den_mark_axis_y_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02404 02405 int32_t lsm6dso_den_mark_axis_z_set(lsm6dso_ctx_t *ctx, uint8_t val); 02406 int32_t lsm6dso_den_mark_axis_z_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02407 02408 typedef enum { 02409 LSM6DSO_PEDO_BASE_MODE = 0x00, 02410 LSM6DSO_FALSE_STEP_REJ = 0x10, 02411 LSM6DSO_FALSE_STEP_REJ_ADV_MODE = 0x30, 02412 } lsm6dso_pedo_md_t; 02413 int32_t lsm6dso_pedo_sens_set(lsm6dso_ctx_t *ctx, lsm6dso_pedo_md_t val); 02414 int32_t lsm6dso_pedo_sens_get(lsm6dso_ctx_t *ctx, lsm6dso_pedo_md_t *val); 02415 02416 int32_t lsm6dso_pedo_step_detect_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02417 02418 int32_t lsm6dso_pedo_debounce_steps_set(lsm6dso_ctx_t *ctx, 02419 uint8_t *buff); 02420 int32_t lsm6dso_pedo_debounce_steps_get(lsm6dso_ctx_t *ctx, 02421 uint8_t *buff); 02422 02423 int32_t lsm6dso_pedo_steps_period_set(lsm6dso_ctx_t *ctx, uint8_t *buff); 02424 int32_t lsm6dso_pedo_steps_period_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 02425 02426 typedef enum { 02427 LSM6DSO_EVERY_STEP = 0, 02428 LSM6DSO_COUNT_OVERFLOW = 1, 02429 } lsm6dso_carry_count_en_t; 02430 int32_t lsm6dso_pedo_int_mode_set(lsm6dso_ctx_t *ctx, 02431 lsm6dso_carry_count_en_t val); 02432 int32_t lsm6dso_pedo_int_mode_get(lsm6dso_ctx_t *ctx, 02433 lsm6dso_carry_count_en_t *val); 02434 02435 int32_t lsm6dso_motion_flag_data_ready_get(lsm6dso_ctx_t *ctx, 02436 uint8_t *val); 02437 02438 int32_t lsm6dso_tilt_flag_data_ready_get(lsm6dso_ctx_t *ctx, 02439 uint8_t *val); 02440 02441 int32_t lsm6dso_mag_sensitivity_set(lsm6dso_ctx_t *ctx, uint8_t *buff); 02442 int32_t lsm6dso_mag_sensitivity_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 02443 02444 int32_t lsm6dso_mag_offset_set(lsm6dso_ctx_t *ctx, uint8_t *buff); 02445 int32_t lsm6dso_mag_offset_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 02446 02447 int32_t lsm6dso_mag_soft_iron_set(lsm6dso_ctx_t *ctx, uint8_t *buff); 02448 int32_t lsm6dso_mag_soft_iron_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 02449 02450 typedef enum { 02451 LSM6DSO_Z_EQ_Y = 0, 02452 LSM6DSO_Z_EQ_MIN_Y = 1, 02453 LSM6DSO_Z_EQ_X = 2, 02454 LSM6DSO_Z_EQ_MIN_X = 3, 02455 LSM6DSO_Z_EQ_MIN_Z = 4, 02456 LSM6DSO_Z_EQ_Z = 5, 02457 } lsm6dso_mag_z_axis_t; 02458 int32_t lsm6dso_mag_z_orient_set(lsm6dso_ctx_t *ctx, 02459 lsm6dso_mag_z_axis_t val); 02460 int32_t lsm6dso_mag_z_orient_get(lsm6dso_ctx_t *ctx, 02461 lsm6dso_mag_z_axis_t *val); 02462 02463 typedef enum { 02464 LSM6DSO_Y_EQ_Y = 0, 02465 LSM6DSO_Y_EQ_MIN_Y = 1, 02466 LSM6DSO_Y_EQ_X = 2, 02467 LSM6DSO_Y_EQ_MIN_X = 3, 02468 LSM6DSO_Y_EQ_MIN_Z = 4, 02469 LSM6DSO_Y_EQ_Z = 5, 02470 } lsm6dso_mag_y_axis_t; 02471 int32_t lsm6dso_mag_y_orient_set(lsm6dso_ctx_t *ctx, 02472 lsm6dso_mag_y_axis_t val); 02473 int32_t lsm6dso_mag_y_orient_get(lsm6dso_ctx_t *ctx, 02474 lsm6dso_mag_y_axis_t *val); 02475 02476 typedef enum { 02477 LSM6DSO_X_EQ_Y = 0, 02478 LSM6DSO_X_EQ_MIN_Y = 1, 02479 LSM6DSO_X_EQ_X = 2, 02480 LSM6DSO_X_EQ_MIN_X = 3, 02481 LSM6DSO_X_EQ_MIN_Z = 4, 02482 LSM6DSO_X_EQ_Z = 5, 02483 } lsm6dso_mag_x_axis_t; 02484 int32_t lsm6dso_mag_x_orient_set(lsm6dso_ctx_t *ctx, 02485 lsm6dso_mag_x_axis_t val); 02486 int32_t lsm6dso_mag_x_orient_get(lsm6dso_ctx_t *ctx, 02487 lsm6dso_mag_x_axis_t *val); 02488 02489 int32_t lsm6dso_long_cnt_flag_data_ready_get(lsm6dso_ctx_t *ctx, 02490 uint8_t *val); 02491 02492 typedef struct { 02493 lsm6dso_fsm_enable_a_t fsm_enable_a; 02494 lsm6dso_fsm_enable_b_t fsm_enable_b; 02495 } lsm6dso_emb_fsm_enable_t; 02496 int32_t lsm6dso_fsm_enable_set(lsm6dso_ctx_t *ctx, 02497 lsm6dso_emb_fsm_enable_t *val); 02498 int32_t lsm6dso_fsm_enable_get(lsm6dso_ctx_t *ctx, 02499 lsm6dso_emb_fsm_enable_t *val); 02500 02501 int32_t lsm6dso_long_cnt_set(lsm6dso_ctx_t *ctx, uint8_t *buff); 02502 int32_t lsm6dso_long_cnt_get(lsm6dso_ctx_t *ctx, uint8_t *buff); 02503 02504 typedef enum { 02505 LSM6DSO_LC_NORMAL = 0, 02506 LSM6DSO_LC_CLEAR = 1, 02507 LSM6DSO_LC_CLEAR_DONE = 2, 02508 } lsm6dso_fsm_lc_clr_t; 02509 int32_t lsm6dso_long_clr_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val); 02510 int32_t lsm6dso_long_clr_get(lsm6dso_ctx_t *ctx, lsm6dso_fsm_lc_clr_t *val); 02511 02512 typedef struct { 02513 lsm6dso_fsm_outs1_t fsm_outs1; 02514 lsm6dso_fsm_outs2_t fsm_outs2; 02515 lsm6dso_fsm_outs3_t fsm_outs3; 02516 lsm6dso_fsm_outs4_t fsm_outs4; 02517 lsm6dso_fsm_outs5_t fsm_outs5; 02518 lsm6dso_fsm_outs6_t fsm_outs6; 02519 lsm6dso_fsm_outs7_t fsm_outs7; 02520 lsm6dso_fsm_outs8_t fsm_outs8; 02521 lsm6dso_fsm_outs9_t fsm_outs9; 02522 lsm6dso_fsm_outs10_t fsm_outs10; 02523 lsm6dso_fsm_outs11_t fsm_outs11; 02524 lsm6dso_fsm_outs12_t fsm_outs12; 02525 lsm6dso_fsm_outs13_t fsm_outs13; 02526 lsm6dso_fsm_outs14_t fsm_outs14; 02527 lsm6dso_fsm_outs15_t fsm_outs15; 02528 lsm6dso_fsm_outs16_t fsm_outs16; 02529 } lsm6dso_fsm_out_t; 02530 int32_t lsm6dso_fsm_out_get(lsm6dso_ctx_t *ctx, lsm6dso_fsm_out_t *val); 02531 02532 typedef enum { 02533 LSM6DSO_ODR_FSM_12Hz5 = 0, 02534 LSM6DSO_ODR_FSM_26Hz = 1, 02535 LSM6DSO_ODR_FSM_52Hz = 2, 02536 LSM6DSO_ODR_FSM_104Hz = 3, 02537 } lsm6dso_fsm_odr_t; 02538 int32_t lsm6dso_fsm_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_odr_t val); 02539 int32_t lsm6dso_fsm_data_rate_get(lsm6dso_ctx_t *ctx, lsm6dso_fsm_odr_t *val); 02540 02541 int32_t lsm6dso_fsm_init_set(lsm6dso_ctx_t *ctx, uint8_t val); 02542 int32_t lsm6dso_fsm_init_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02543 02544 int32_t lsm6dso_long_cnt_int_value_set(lsm6dso_ctx_t *ctx, uint16_t val); 02545 int32_t lsm6dso_long_cnt_int_value_get(lsm6dso_ctx_t *ctx, uint16_t *val); 02546 02547 int32_t lsm6dso_fsm_number_of_programs_set(lsm6dso_ctx_t *ctx, uint8_t val); 02548 int32_t lsm6dso_fsm_number_of_programs_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02549 02550 int32_t lsm6dso_fsm_start_address_set(lsm6dso_ctx_t *ctx, uint16_t val); 02551 int32_t lsm6dso_fsm_start_address_get(lsm6dso_ctx_t *ctx, uint16_t *val); 02552 02553 int32_t lsm6dso_sh_read_data_raw_get(lsm6dso_ctx_t *ctx, uint8_t *val, 02554 uint8_t len); 02555 02556 typedef enum { 02557 LSM6DSO_SLV_0 = 0, 02558 LSM6DSO_SLV_0_1 = 1, 02559 LSM6DSO_SLV_0_1_2 = 2, 02560 LSM6DSO_SLV_0_1_2_3 = 3, 02561 } lsm6dso_aux_sens_on_t; 02562 int32_t lsm6dso_sh_slave_connected_set(lsm6dso_ctx_t *ctx, 02563 lsm6dso_aux_sens_on_t val); 02564 int32_t lsm6dso_sh_slave_connected_get(lsm6dso_ctx_t *ctx, 02565 lsm6dso_aux_sens_on_t *val); 02566 02567 int32_t lsm6dso_sh_master_set(lsm6dso_ctx_t *ctx, uint8_t val); 02568 int32_t lsm6dso_sh_master_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02569 02570 typedef enum { 02571 LSM6DSO_EXT_PULL_UP = 0, 02572 LSM6DSO_INTERNAL_PULL_UP = 1, 02573 } lsm6dso_shub_pu_en_t; 02574 int32_t lsm6dso_sh_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_pu_en_t val); 02575 int32_t lsm6dso_sh_pin_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_shub_pu_en_t *val); 02576 02577 int32_t lsm6dso_sh_pass_through_set(lsm6dso_ctx_t *ctx, uint8_t val); 02578 int32_t lsm6dso_sh_pass_through_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02579 02580 typedef enum { 02581 LSM6DSO_EXT_ON_INT2_PIN = 0, 02582 LSM6DSO_XL_GY_DRDY = 1, 02583 } lsm6dso_start_config_t; 02584 int32_t lsm6dso_sh_syncro_mode_set(lsm6dso_ctx_t *ctx, 02585 lsm6dso_start_config_t val); 02586 int32_t lsm6dso_sh_syncro_mode_get(lsm6dso_ctx_t *ctx, 02587 lsm6dso_start_config_t *val); 02588 02589 typedef enum { 02590 LSM6DSO_EACH_SH_CYCLE = 0, 02591 LSM6DSO_ONLY_FIRST_CYCLE = 1, 02592 } lsm6dso_write_once_t; 02593 int32_t lsm6dso_sh_write_mode_set(lsm6dso_ctx_t *ctx, 02594 lsm6dso_write_once_t val); 02595 int32_t lsm6dso_sh_write_mode_get(lsm6dso_ctx_t *ctx, 02596 lsm6dso_write_once_t *val); 02597 02598 int32_t lsm6dso_sh_reset_set(lsm6dso_ctx_t *ctx); 02599 int32_t lsm6dso_sh_reset_get(lsm6dso_ctx_t *ctx, uint8_t *val); 02600 02601 typedef enum { 02602 LSM6DSO_SH_ODR_104Hz = 0, 02603 LSM6DSO_SH_ODR_52Hz = 1, 02604 LSM6DSO_SH_ODR_26Hz = 2, 02605 LSM6DSO_SH_ODR_13Hz = 3, 02606 } lsm6dso_shub_odr_t; 02607 int32_t lsm6dso_sh_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_odr_t val); 02608 int32_t lsm6dso_sh_data_rate_get(lsm6dso_ctx_t *ctx, lsm6dso_shub_odr_t *val); 02609 02610 typedef struct{ 02611 uint8_t slv0_add; 02612 uint8_t slv0_subadd; 02613 uint8_t slv0_data; 02614 } lsm6dso_sh_cfg_write_t; 02615 int32_t lsm6dso_sh_cfg_write(lsm6dso_ctx_t *ctx, lsm6dso_sh_cfg_write_t *val); 02616 02617 typedef struct{ 02618 uint8_t slv_add; 02619 uint8_t slv_subadd; 02620 uint8_t slv_len; 02621 } lsm6dso_sh_cfg_read_t; 02622 int32_t lsm6dso_sh_slv0_cfg_read(lsm6dso_ctx_t *ctx, 02623 lsm6dso_sh_cfg_read_t *val); 02624 int32_t lsm6dso_sh_slv1_cfg_read(lsm6dso_ctx_t *ctx, 02625 lsm6dso_sh_cfg_read_t *val); 02626 int32_t lsm6dso_sh_slv2_cfg_read(lsm6dso_ctx_t *ctx, 02627 lsm6dso_sh_cfg_read_t *val); 02628 int32_t lsm6dso_sh_slv3_cfg_read(lsm6dso_ctx_t *ctx, 02629 lsm6dso_sh_cfg_read_t *val); 02630 02631 int32_t lsm6dso_sh_status_get(lsm6dso_ctx_t *ctx, 02632 lsm6dso_status_master_t *val); 02633 02634 02635 typedef struct { 02636 uint8_t ui; 02637 uint8_t aux; 02638 } lsm6dso_id_t; 02639 int32_t lsm6dso_id_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 02640 lsm6dso_id_t *val); 02641 02642 typedef struct { 02643 enum { 02644 LSM6DSO_SEL_BY_HW = 0x00, /* bus mode select by HW (SPI 3W disable) */ 02645 LSM6DSO_SPI_4W = 0x06, /* Only SPI: SDO / SDI separated pins */ 02646 LSM6DSO_SPI_3W = 0x07, /* Only SPI: SDO / SDI share the same pin */ 02647 LSM6DSO_I2C = 0x04, /* Only I2C */ 02648 LSM6DSO_I3C_T_50us = 0x02, /* I3C: available time equal to 50 μs */ 02649 LSM6DSO_I3C_T_2us = 0x12, /* I3C: available time equal to 2 μs */ 02650 LSM6DSO_I3C_T_1ms = 0x22, /* I3C: available time equal to 1 ms */ 02651 LSM6DSO_I3C_T_25ms = 0x32, /* I3C: available time equal to 25 ms */ 02652 } ui_bus_md; 02653 enum { 02654 LSM6DSO_SPI_4W_AUX = 0x00, 02655 LSM6DSO_SPI_3W_AUX = 0x01, 02656 } aux_bus_md; 02657 } lsm6dso_bus_mode_t; 02658 int32_t lsm6dso_bus_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 02659 lsm6dso_bus_mode_t val); 02660 int32_t lsm6dso_bus_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 02661 lsm6dso_bus_mode_t *val); 02662 02663 typedef enum { 02664 LSM6DSO_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 02665 LSM6DSO_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 02666 LSM6DSO_RESET = 0x02, /* Reset configuration registers */ 02667 LSM6DSO_FIFO_COMP = 0x04, /* FIFO compression initialization request. */ 02668 LSM6DSO_FSM = 0x08, /* Finite State Machine initialization request */ 02669 LSM6DSO_PEDO = 0x20, /* Pedometer algo initialization request. */ 02670 LSM6DSO_TILT = 0x40, /* Tilt algo initialization request */ 02671 LSM6DSO_SMOTION = 0x80, /* Significant Motion initialization request */ 02672 } lsm6dso_init_t; 02673 int32_t lsm6dso_init_set(lsm6dso_ctx_t *ctx, lsm6dso_init_t val); 02674 02675 typedef struct { 02676 uint8_t sw_reset : 1; /* Restoring configuration registers */ 02677 uint8_t boot : 1; /* Restoring calibration parameters */ 02678 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 02679 uint8_t drdy_g : 1; /* Gyroscope data ready */ 02680 uint8_t drdy_temp : 1; /* Temperature data ready */ 02681 uint8_t ois_drdy_xl : 1; /* Accelerometer data ready on OIS */ 02682 uint8_t ois_drdy_g : 1; /* Gyroscope data ready on OIS */ 02683 uint8_t ois_gyro_settling : 1; /* Gyroscope is in the settling phase */ 02684 } lsm6dso_status_t; 02685 int32_t lsm6dso_status_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 02686 lsm6dso_status_t *val); 02687 02688 typedef struct { 02689 uint8_t sdo_sa0_pull_up : 1; /* 1 = pull-up on SDO/SA0 pin */ 02690 uint8_t aux_sdo_ocs_pull_up : 1; /* 1 = pull-up on OCS_Aux/SDO_Aux pins */ 02691 uint8_t int1_int2_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 02692 uint8_t int1_pull_down : 1; /* 1 = pull-down always disabled (0=auto) */ 02693 } lsm6dso_pin_conf_t; 02694 int32_t lsm6dso_pin_conf_set(lsm6dso_ctx_t *ctx, lsm6dso_pin_conf_t val); 02695 int32_t lsm6dso_pin_conf_get(lsm6dso_ctx_t *ctx, lsm6dso_pin_conf_t *val); 02696 02697 typedef struct { 02698 uint8_t active_low : 1; /* 1 = active low / 0 = active high */ 02699 uint8_t base_latched : 1; /* base functions are: FF, WU, 6D, Tap, Act/Inac */ 02700 uint8_t emb_latched : 1; /* emb functions are: Pedo, Tilt, SMot, Timestamp */ 02701 } lsm6dso_int_mode_t; 02702 int32_t lsm6dso_interrupt_mode_set(lsm6dso_ctx_t *ctx, 02703 lsm6dso_int_mode_t val); 02704 int32_t lsm6dso_interrupt_mode_get(lsm6dso_ctx_t *ctx, 02705 lsm6dso_int_mode_t *val); 02706 02707 typedef struct { 02708 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 02709 uint8_t drdy_g : 1; /* Gyroscope data ready */ 02710 uint8_t drdy_temp : 1; /* Temperature data ready (1 = int2 pin disable) */ 02711 uint8_t boot : 1; /* Restoring calibration parameters */ 02712 uint8_t fifo_th : 1; /* FIFO threshold reached */ 02713 uint8_t fifo_ovr : 1; /* FIFO overrun */ 02714 uint8_t fifo_full : 1; /* FIFO full */ 02715 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 02716 uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ 02717 uint8_t sh_endop : 1; /* sensor hub end operation */ 02718 uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ 02719 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 02720 uint8_t double_tap : 1; /* double-tap event */ 02721 uint8_t free_fall : 1; /* free fall event */ 02722 uint8_t wake_up : 1; /* wake up event */ 02723 uint8_t single_tap : 1; /* single-tap event */ 02724 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 02725 uint8_t step_detector : 1; /* Step detected */ 02726 uint8_t tilt : 1; /* Relative tilt event detected */ 02727 uint8_t sig_mot : 1; /* "significant motion" event detected */ 02728 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 02729 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 02730 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 02731 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 02732 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 02733 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 02734 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 02735 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 02736 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 02737 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 02738 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 02739 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 02740 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 02741 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 02742 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 02743 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 02744 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 02745 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 02746 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 02747 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 02748 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 02749 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 02750 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 02751 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 02752 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 02753 } lsm6dso_pin_int1_route_t; 02754 02755 int32_t lsm6dso_pin_int1_route_set(lsm6dso_ctx_t *ctx, 02756 lsm6dso_pin_int1_route_t val); 02757 int32_t lsm6dso_pin_int1_route_get(lsm6dso_ctx_t *ctx, 02758 lsm6dso_pin_int1_route_t *val); 02759 02760 typedef struct { 02761 uint8_t drdy_ois : 1; /* OIS chain data ready */ 02762 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 02763 uint8_t drdy_g : 1; /* Gyroscope data ready */ 02764 uint8_t drdy_temp : 1; /* Temperature data ready */ 02765 uint8_t fifo_th : 1; /* FIFO threshold reached */ 02766 uint8_t fifo_ovr : 1; /* FIFO overrun */ 02767 uint8_t fifo_full : 1; /* FIFO full */ 02768 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 02769 uint8_t timestamp : 1; /* timestamp overflow */ 02770 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 02771 uint8_t double_tap : 1; /* double-tap event */ 02772 uint8_t free_fall : 1; /* free fall event */ 02773 uint8_t wake_up : 1; /* wake up event */ 02774 uint8_t single_tap : 1; /* single-tap event */ 02775 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 02776 uint8_t step_detector : 1; /* Step detected */ 02777 uint8_t tilt : 1; /* Relative tilt event detected */ 02778 uint8_t sig_mot : 1; /* "significant motion" event detected */ 02779 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 02780 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 02781 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 02782 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 02783 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 02784 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 02785 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 02786 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 02787 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 02788 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 02789 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 02790 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 02791 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 02792 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 02793 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 02794 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 02795 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 02796 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 02797 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 02798 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 02799 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 02800 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 02801 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 02802 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 02803 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 02804 } lsm6dso_pin_int2_route_t; 02805 02806 int32_t lsm6dso_pin_int2_route_set(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 02807 lsm6dso_pin_int2_route_t val); 02808 int32_t lsm6dso_pin_int2_route_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 02809 lsm6dso_pin_int2_route_t *val); 02810 02811 typedef struct { 02812 uint8_t drdy_xl : 1; /* Accelerometer data ready */ 02813 uint8_t drdy_g : 1; /* Gyroscope data ready */ 02814 uint8_t drdy_temp : 1; /* Temperature data ready */ 02815 uint8_t den_flag : 1; /* external trigger level recognition (DEN) */ 02816 uint8_t timestamp : 1; /* timestamp overflow (1 = int2 pin disable) */ 02817 uint8_t free_fall : 1; /* free fall event */ 02818 uint8_t wake_up : 1; /* wake up event */ 02819 uint8_t wake_up_z : 1; /* wake up on Z axis event */ 02820 uint8_t wake_up_y : 1; /* wake up on Y axis event */ 02821 uint8_t wake_up_x : 1; /* wake up on X axis event */ 02822 uint8_t single_tap : 1; /* single-tap event */ 02823 uint8_t double_tap : 1; /* double-tap event */ 02824 uint8_t tap_z : 1; /* single-tap on Z axis event */ 02825 uint8_t tap_y : 1; /* single-tap on Y axis event */ 02826 uint8_t tap_x : 1; /* single-tap on X axis event */ 02827 uint8_t tap_sign : 1; /* sign of tap event (0-pos / 1-neg) */ 02828 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 02829 uint8_t six_d_xl : 1; /* X-axis low 6D/4D event (under threshold) */ 02830 uint8_t six_d_xh : 1; /* X-axis high 6D/4D event (over threshold) */ 02831 uint8_t six_d_yl : 1; /* Y-axis low 6D/4D event (under threshold) */ 02832 uint8_t six_d_yh : 1; /* Y-axis high 6D/4D event (over threshold) */ 02833 uint8_t six_d_zl : 1; /* Z-axis low 6D/4D event (under threshold) */ 02834 uint8_t six_d_zh : 1; /* Z-axis high 6D/4D event (over threshold) */ 02835 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 02836 uint8_t sleep_state : 1; /* Act/Inact status flag (0-Act / 1-Inact) */ 02837 uint8_t step_detector : 1; /* Step detected */ 02838 uint8_t tilt : 1; /* Relative tilt event detected */ 02839 uint8_t sig_mot : 1; /* "significant motion" event detected */ 02840 uint8_t fsm_lc : 1; /* fsm long counter timeout interrupt event */ 02841 uint8_t fsm1 : 1; /* fsm 1 interrupt event */ 02842 uint8_t fsm2 : 1; /* fsm 2 interrupt event */ 02843 uint8_t fsm3 : 1; /* fsm 3 interrupt event */ 02844 uint8_t fsm4 : 1; /* fsm 4 interrupt event */ 02845 uint8_t fsm5 : 1; /* fsm 5 interrupt event */ 02846 uint8_t fsm6 : 1; /* fsm 6 interrupt event */ 02847 uint8_t fsm7 : 1; /* fsm 7 interrupt event */ 02848 uint8_t fsm8 : 1; /* fsm 8 interrupt event */ 02849 uint8_t fsm9 : 1; /* fsm 9 interrupt event */ 02850 uint8_t fsm10 : 1; /* fsm 10 interrupt event */ 02851 uint8_t fsm11 : 1; /* fsm 11 interrupt event */ 02852 uint8_t fsm12 : 1; /* fsm 12 interrupt event */ 02853 uint8_t fsm13 : 1; /* fsm 13 interrupt event */ 02854 uint8_t fsm14 : 1; /* fsm 14 interrupt event */ 02855 uint8_t fsm15 : 1; /* fsm 15 interrupt event */ 02856 uint8_t fsm16 : 1; /* fsm 16 interrupt event */ 02857 uint8_t mlc1 : 1; /* mlc 1 interrupt event */ 02858 uint8_t mlc2 : 1; /* mlc 2 interrupt event */ 02859 uint8_t mlc3 : 1; /* mlc 3 interrupt event */ 02860 uint8_t mlc4 : 1; /* mlc 4 interrupt event */ 02861 uint8_t mlc5 : 1; /* mlc 5 interrupt event */ 02862 uint8_t mlc6 : 1; /* mlc 6 interrupt event */ 02863 uint8_t mlc7 : 1; /* mlc 7 interrupt event */ 02864 uint8_t mlc8 : 1; /* mlc 8 interrupt event */ 02865 uint8_t sh_endop : 1; /* sensor hub end operation */ 02866 uint8_t sh_slave0_nack : 1; /* Not acknowledge on sensor hub slave 0 */ 02867 uint8_t sh_slave1_nack : 1; /* Not acknowledge on sensor hub slave 1 */ 02868 uint8_t sh_slave2_nack : 1; /* Not acknowledge on sensor hub slave 2 */ 02869 uint8_t sh_slave3_nack : 1; /* Not acknowledge on sensor hub slave 3 */ 02870 uint8_t sh_wr_once : 1; /* "WRITE_ONCE" end on sensor hub slave 0 */ 02871 uint16_t fifo_diff : 10; /* Number of unread sensor data in FIFO*/ 02872 uint8_t fifo_ovr_latched : 1; /* Latched FIFO overrun status */ 02873 uint8_t fifo_bdr : 1; /* FIFO Batch counter threshold reached */ 02874 uint8_t fifo_full : 1; /* FIFO full */ 02875 uint8_t fifo_ovr : 1; /* FIFO overrun */ 02876 uint8_t fifo_th : 1; /* FIFO threshold reached */ 02877 } lsm6dso_all_sources_t; 02878 int32_t lsm6dso_all_sources_get(lsm6dso_ctx_t *ctx, 02879 lsm6dso_all_sources_t *val); 02880 02881 typedef struct{ 02882 uint8_t odr_fine_tune; 02883 } lsm6dso_dev_cal_t; 02884 int32_t lsm6dso_calibration_get(lsm6dso_ctx_t *ctx, lsm6dso_dev_cal_t *val); 02885 02886 typedef struct { 02887 struct { 02888 struct { 02889 enum { 02890 LSM6DSO_XL_UI_OFF = 0x00, /* in power down */ 02891 LSM6DSO_XL_UI_1Hz6_LP = 0x1B, /* @1Hz6 (low power) */ 02892 LSM6DSO_XL_UI_1Hz6_ULP = 0x2B, /* @1Hz6 (ultra low/Gy, OIS imu off) */ 02893 LSM6DSO_XL_UI_12Hz5_HP = 0x01, /* @12Hz5 (high performance) */ 02894 LSM6DSO_XL_UI_12Hz5_LP = 0x11, /* @12Hz5 (low power) */ 02895 LSM6DSO_XL_UI_12Hz5_ULP = 0x21, /* @12Hz5 (ultra low/Gy, OIS imu off) */ 02896 LSM6DSO_XL_UI_26Hz_HP = 0x02, /* @26Hz (high performance) */ 02897 LSM6DSO_XL_UI_26Hz_LP = 0x12, /* @26Hz (low power) */ 02898 LSM6DSO_XL_UI_26Hz_ULP = 0x22, /* @26Hz (ultra low/Gy, OIS imu off) */ 02899 LSM6DSO_XL_UI_52Hz_HP = 0x03, /* @52Hz (high performance) */ 02900 LSM6DSO_XL_UI_52Hz_LP = 0x13, /* @52Hz (low power) */ 02901 LSM6DSO_XL_UI_52Hz_ULP = 0x23, /* @52Hz (ultra low/Gy, OIS imu off) */ 02902 LSM6DSO_XL_UI_104Hz_HP = 0x04, /* @104Hz (high performance) */ 02903 LSM6DSO_XL_UI_104Hz_NM = 0x14, /* @104Hz (normal mode) */ 02904 LSM6DSO_XL_UI_104Hz_ULP = 0x24, /* @104Hz (ultra low/Gy, OIS imu off) */ 02905 LSM6DSO_XL_UI_208Hz_HP = 0x05, /* @208Hz (high performance) */ 02906 LSM6DSO_XL_UI_208Hz_NM = 0x15, /* @208Hz (normal mode) */ 02907 LSM6DSO_XL_UI_208Hz_ULP = 0x25, /* @208Hz (ultra low/Gy, OIS imu off) */ 02908 LSM6DSO_XL_UI_416Hz_HP = 0x06, /* @416Hz (high performance) */ 02909 LSM6DSO_XL_UI_833Hz_HP = 0x07, /* @833Hz (high performance) */ 02910 LSM6DSO_XL_UI_1667Hz_HP = 0x08, /* @1kHz66 (high performance) */ 02911 LSM6DSO_XL_UI_3333Hz_HP = 0x09, /* @3kHz33 (high performance) */ 02912 LSM6DSO_XL_UI_6667Hz_HP = 0x0A, /* @6kHz66 (high performance) */ 02913 } odr; 02914 enum { 02915 LSM6DSO_XL_UI_2g = 0, 02916 LSM6DSO_XL_UI_4g = 2, 02917 LSM6DSO_XL_UI_8g = 3, 02918 LSM6DSO_XL_UI_16g = 1, /* OIS full scale is also forced to be 16g */ 02919 } fs; 02920 } xl; 02921 struct { 02922 enum { 02923 LSM6DSO_GY_UI_OFF = 0x00, /* gy in power down */ 02924 LSM6DSO_GY_UI_12Hz5_LP = 0x11, /* gy @12Hz5 (low power) */ 02925 LSM6DSO_GY_UI_12Hz5_HP = 0x01, /* gy @12Hz5 (high performance) */ 02926 LSM6DSO_GY_UI_26Hz_LP = 0x12, /* gy @26Hz (low power) */ 02927 LSM6DSO_GY_UI_26Hz_HP = 0x02, /* gy @26Hz (high performance) */ 02928 LSM6DSO_GY_UI_52Hz_LP = 0x13, /* gy @52Hz (low power) */ 02929 LSM6DSO_GY_UI_52Hz_HP = 0x03, /* gy @52Hz (high performance) */ 02930 LSM6DSO_GY_UI_104Hz_NM = 0x14, /* gy @104Hz (low power) */ 02931 LSM6DSO_GY_UI_104Hz_HP = 0x04, /* gy @104Hz (high performance) */ 02932 LSM6DSO_GY_UI_208Hz_NM = 0x15, /* gy @208Hz (low power) */ 02933 LSM6DSO_GY_UI_208Hz_HP = 0x05, /* gy @208Hz (high performance) */ 02934 LSM6DSO_GY_UI_416Hz_HP = 0x06, /* gy @416Hz (high performance) */ 02935 LSM6DSO_GY_UI_833Hz_HP = 0x07, /* gy @833Hz (high performance) */ 02936 LSM6DSO_GY_UI_1667Hz_HP = 0x08, /* gy @1kHz66 (high performance) */ 02937 LSM6DSO_GY_UI_3333Hz_HP = 0x09, /* gy @3kHz33 (high performance) */ 02938 LSM6DSO_GY_UI_6667Hz_HP = 0x0A, /* gy @6kHz66 (high performance) */ 02939 } odr; 02940 enum { 02941 LSM6DSO_GY_UI_250dps = 0, 02942 LSM6DSO_GY_UI_125dps = 1, 02943 LSM6DSO_GY_UI_500dps = 2, 02944 LSM6DSO_GY_UI_1000dps = 4, 02945 LSM6DSO_GY_UI_2000dps = 6, 02946 } fs; 02947 }gy; 02948 } ui; 02949 struct { 02950 enum { 02951 LSM6DSO_OIS_ONLY_AUX = 0x00, /* Auxiliary SPI full control */ 02952 LSM6DSO_OIS_MIXED = 0x01, /* Enabling by UI / read-config by AUX */ 02953 } ctrl_md; 02954 struct { 02955 enum { 02956 LSM6DSO_XL_OIS_OFF = 0x00, /* in power down */ 02957 LSM6DSO_XL_OIS_6667Hz_HP = 0x01, /* @6kHz OIS imu active/NO ULP on UI */ 02958 } odr; 02959 enum { 02960 LSM6DSO_XL_OIS_2g = 0, 02961 LSM6DSO_XL_OIS_4g = 2, 02962 LSM6DSO_XL_OIS_8g = 3, 02963 LSM6DSO_XL_OIS_16g = 1, /* UI full scale is also forced to be 16g */ 02964 } fs; 02965 } xl; 02966 struct { 02967 enum { 02968 LSM6DSO_GY_OIS_OFF = 0x00, /* in power down */ 02969 LSM6DSO_GY_OIS_6667Hz_HP = 0x01, /* @6kHz No Ultra Low Power*/ 02970 } odr; 02971 enum { 02972 LSM6DSO_GY_OIS_250dps = 0, 02973 LSM6DSO_GY_OIS_125dps = 1, 02974 LSM6DSO_GY_OIS_500dps = 2, 02975 LSM6DSO_GY_OIS_1000dps = 4, 02976 LSM6DSO_GY_OIS_2000dps = 6, 02977 } fs; 02978 } gy; 02979 } ois; 02980 struct { 02981 enum { 02982 LSM6DSO_FSM_DISABLE = 0x00, 02983 LSM6DSO_FSM_XL = 0x01, 02984 LSM6DSO_FSM_GY = 0x02, 02985 LSM6DSO_FSM_XL_GY = 0x03, 02986 } sens; 02987 enum { 02988 LSM6DSO_FSM_12Hz5 = 0x00, 02989 LSM6DSO_FSM_26Hz = 0x01, 02990 LSM6DSO_FSM_52Hz = 0x02, 02991 LSM6DSO_FSM_104Hz = 0x03, 02992 } odr; 02993 } fsm; 02994 } lsm6dso_md_t; 02995 int32_t lsm6dso_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 02996 lsm6dso_md_t *val); 02997 int32_t lsm6dso_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 02998 lsm6dso_md_t *val); 02999 typedef struct { 03000 struct { 03001 struct { 03002 float mg[3]; 03003 int16_t raw[3]; 03004 }xl; 03005 struct { 03006 float mdps[3]; 03007 int16_t raw[3]; 03008 }gy; 03009 struct { 03010 float deg_c; 03011 int16_t raw; 03012 }heat; 03013 } ui; 03014 struct { 03015 struct { 03016 float mg[3]; 03017 int16_t raw[3]; 03018 }xl; 03019 struct { 03020 float mdps[3]; 03021 int16_t raw[3]; 03022 }gy; 03023 } ois; 03024 } lsm6dso_data_t; 03025 int32_t lsm6dso_data_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 03026 lsm6dso_md_t *md, lsm6dso_data_t *data); 03027 03028 typedef struct { 03029 uint8_t sig_mot : 1; /* significant motion */ 03030 uint8_t tilt : 1; /* tilt detection */ 03031 uint8_t step : 1; /* step counter/detector */ 03032 uint8_t step_adv : 1; /* step counter advanced mode */ 03033 uint8_t fsm : 1; /* finite state machine */ 03034 uint8_t fifo_compr : 1; /* FIFO compression */ 03035 } lsm6dso_emb_sens_t; 03036 int32_t lsm6dso_embedded_sens_set(lsm6dso_ctx_t *ctx, 03037 lsm6dso_emb_sens_t *emb_sens); 03038 int32_t lsm6dso_embedded_sens_get(lsm6dso_ctx_t *ctx, 03039 lsm6dso_emb_sens_t *emb_sens); 03040 int32_t lsm6dso_embedded_sens_off(lsm6dso_ctx_t *ctx); 03041 03042 /** 03043 * @} 03044 * 03045 */ 03046 03047 #ifdef __cplusplus 03048 } 03049 #endif 03050 03051 #endif /*LSM6DSO_DRIVER_H */ 03052 03053 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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