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iNEMO inertial module: 3D accelerometer and 3D gyroscope.
Dependencies: X_NUCLEO_COMMON ST_INTERFACES
Dependents: X_NUCLEO_IKS01A3 X_NUCLEO_IKS01A3
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lsm6dso_reg.c
00001 /* 00002 ****************************************************************************** 00003 * @file lsm6dso_reg.c 00004 * @author Sensors Software Solution Team 00005 * @brief LSM6DSO driver file 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 #include "lsm6dso_reg.h" 00021 00022 /** 00023 * @defgroup LSM6DSO 00024 * @brief This file provides a set of functions needed to drive the 00025 * lsm6dso enhanced inertial module. 00026 * @{ 00027 * 00028 */ 00029 00030 /** 00031 * @defgroup LSM6DSO_Interfaces_Functions 00032 * @brief This section provide a set of functions used to read and 00033 * write a generic register of the device. 00034 * MANDATORY: return 0 -> no Error. 00035 * @{ 00036 * 00037 */ 00038 00039 /** 00040 * @brief Read generic device register 00041 * 00042 * @param ctx read / write interface definitions(ptr) 00043 * @param reg register to read 00044 * @param data pointer to buffer that store the data read(ptr) 00045 * @param len number of consecutive register to read 00046 * @retval interface status (MANDATORY: return 0 -> no Error) 00047 * 00048 */ 00049 int32_t lsm6dso_read_reg(lsm6dso_ctx_t* ctx, uint8_t reg, uint8_t* data, 00050 uint16_t len) 00051 { 00052 int32_t ret; 00053 ret = ctx->read_reg(ctx->handle, reg, data, len); 00054 return ret; 00055 } 00056 00057 /** 00058 * @brief Write generic device register 00059 * 00060 * @param ctx read / write interface definitions(ptr) 00061 * @param reg register to write 00062 * @param data pointer to data to write in register reg(ptr) 00063 * @param len number of consecutive register to write 00064 * @retval interface status (MANDATORY: return 0 -> no Error) 00065 * 00066 */ 00067 int32_t lsm6dso_write_reg(lsm6dso_ctx_t* ctx, uint8_t reg, uint8_t* data, 00068 uint16_t len) 00069 { 00070 int32_t ret; 00071 ret = ctx->write_reg(ctx->handle, reg, data, len); 00072 return ret; 00073 } 00074 00075 /** 00076 * @} 00077 * 00078 */ 00079 00080 /** 00081 * @defgroup LSM6DSOX_Private_functions 00082 * @brief Section collect all the utility functions needed by APIs. 00083 * @{ 00084 * 00085 */ 00086 00087 static void bytecpy(uint8_t *target, uint8_t *source) 00088 { 00089 if ( (target != NULL) && (source != NULL) ) { 00090 *target = *source; 00091 } 00092 } 00093 00094 /** 00095 * @defgroup LSM6DSO_Sensitivity 00096 * @brief These functions convert raw-data into engineering units. 00097 * @{ 00098 * 00099 */ 00100 float_t lsm6dso_from_fs2_to_mg(int16_t lsb) 00101 { 00102 return ((float_t)lsb) * 0.061f; 00103 } 00104 00105 float_t lsm6dso_from_fs4_to_mg(int16_t lsb) 00106 { 00107 return ((float_t)lsb) * 0.122f; 00108 } 00109 00110 float_t lsm6dso_from_fs8_to_mg(int16_t lsb) 00111 { 00112 return ((float_t)lsb) * 0.244f; 00113 } 00114 00115 float_t lsm6dso_from_fs16_to_mg(int16_t lsb) 00116 { 00117 return ((float_t)lsb) *0.488f; 00118 } 00119 00120 float_t lsm6dso_from_fs125_to_mdps(int16_t lsb) 00121 { 00122 return ((float_t)lsb) *4.375f; 00123 } 00124 00125 float_t lsm6dso_from_fs500_to_mdps(int16_t lsb) 00126 { 00127 return ((float_t)lsb) *17.50f; 00128 } 00129 00130 float_t lsm6dso_from_fs250_to_mdps(int16_t lsb) 00131 { 00132 return ((float_t)lsb) *8.750f; 00133 } 00134 00135 float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb) 00136 { 00137 return ((float_t)lsb) *35.0f; 00138 } 00139 00140 float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb) 00141 { 00142 return ((float_t)lsb) *70.0f; 00143 } 00144 00145 float_t lsm6dso_from_lsb_to_celsius(int16_t lsb) 00146 { 00147 return (((float_t)lsb / 256.0f) + 25.0f); 00148 } 00149 00150 float_t lsm6dso_from_lsb_to_nsec(int16_t lsb) 00151 { 00152 return ((float_t)lsb * 25000.0f); 00153 } 00154 00155 /** 00156 * @} 00157 * 00158 */ 00159 00160 /** 00161 * @defgroup LSM6DSO_Data_Generation 00162 * @brief This section groups all the functions concerning 00163 * data generation. 00164 * 00165 */ 00166 00167 /** 00168 * @brief Accelerometer full-scale selection.[set] 00169 * 00170 * @param ctx read / write interface definitions 00171 * @param val change the values of fs_xl in reg CTRL1_XL 00172 * 00173 */ 00174 int32_t lsm6dso_xl_full_scale_set(lsm6dso_ctx_t *ctx, 00175 lsm6dso_fs_xl_t val) 00176 { 00177 lsm6dso_ctrl1_xl_t reg; 00178 int32_t ret; 00179 00180 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1); 00181 if (ret == 0) { 00182 reg.fs_xl = (uint8_t) val; 00183 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1); 00184 } 00185 return ret; 00186 } 00187 00188 /** 00189 * @brief Accelerometer full-scale selection.[get] 00190 * 00191 * @param ctx read / write interface definitions 00192 * @param val Get the values of fs_xl in reg CTRL1_XL 00193 * 00194 */ 00195 int32_t lsm6dso_xl_full_scale_get(lsm6dso_ctx_t *ctx, lsm6dso_fs_xl_t *val) 00196 { 00197 lsm6dso_ctrl1_xl_t reg; 00198 int32_t ret; 00199 00200 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1); 00201 switch (reg.fs_xl) { 00202 case LSM6DSO_2g: 00203 *val = LSM6DSO_2g; 00204 break; 00205 case LSM6DSO_16g: 00206 *val = LSM6DSO_16g; 00207 break; 00208 case LSM6DSO_4g: 00209 *val = LSM6DSO_4g; 00210 break; 00211 case LSM6DSO_8g: 00212 *val = LSM6DSO_8g; 00213 break; 00214 default: 00215 *val = LSM6DSO_2g; 00216 break; 00217 } 00218 00219 return ret; 00220 } 00221 00222 /** 00223 * @brief Accelerometer UI data rate selection.[set] 00224 * 00225 * @param ctx read / write interface definitions 00226 * @param val change the values of odr_xl in reg CTRL1_XL 00227 * 00228 */ 00229 int32_t lsm6dso_xl_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_xl_t val) 00230 { 00231 lsm6dso_odr_xl_t odr_xl = val; 00232 lsm6dso_emb_fsm_enable_t fsm_enable; 00233 lsm6dso_fsm_odr_t fsm_odr; 00234 lsm6dso_ctrl1_xl_t reg; 00235 int32_t ret; 00236 00237 /* Check the Finite State Machine data rate constraints */ 00238 ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable); 00239 if (ret == 0) { 00240 if ( (fsm_enable.fsm_enable_a.fsm1_en | 00241 fsm_enable.fsm_enable_a.fsm2_en | 00242 fsm_enable.fsm_enable_a.fsm3_en | 00243 fsm_enable.fsm_enable_a.fsm4_en | 00244 fsm_enable.fsm_enable_a.fsm5_en | 00245 fsm_enable.fsm_enable_a.fsm6_en | 00246 fsm_enable.fsm_enable_a.fsm7_en | 00247 fsm_enable.fsm_enable_a.fsm8_en | 00248 fsm_enable.fsm_enable_b.fsm9_en | 00249 fsm_enable.fsm_enable_b.fsm10_en | 00250 fsm_enable.fsm_enable_b.fsm11_en | 00251 fsm_enable.fsm_enable_b.fsm12_en | 00252 fsm_enable.fsm_enable_b.fsm13_en | 00253 fsm_enable.fsm_enable_b.fsm14_en | 00254 fsm_enable.fsm_enable_b.fsm15_en | 00255 fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){ 00256 00257 ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr); 00258 if (ret == 0) { 00259 switch (fsm_odr) { 00260 case LSM6DSO_ODR_FSM_12Hz5: 00261 00262 if (val == LSM6DSO_XL_ODR_OFF){ 00263 odr_xl = LSM6DSO_XL_ODR_12Hz5; 00264 00265 } else { 00266 odr_xl = val; 00267 } 00268 break; 00269 case LSM6DSO_ODR_FSM_26Hz: 00270 00271 if (val == LSM6DSO_XL_ODR_OFF){ 00272 odr_xl = LSM6DSO_XL_ODR_26Hz; 00273 00274 } else if (val == LSM6DSO_XL_ODR_12Hz5){ 00275 odr_xl = LSM6DSO_XL_ODR_26Hz; 00276 00277 } else { 00278 odr_xl = val; 00279 } 00280 break; 00281 case LSM6DSO_ODR_FSM_52Hz: 00282 00283 if (val == LSM6DSO_XL_ODR_OFF){ 00284 odr_xl = LSM6DSO_XL_ODR_52Hz; 00285 00286 } else if (val == LSM6DSO_XL_ODR_12Hz5){ 00287 odr_xl = LSM6DSO_XL_ODR_52Hz; 00288 00289 } else if (val == LSM6DSO_XL_ODR_26Hz){ 00290 odr_xl = LSM6DSO_XL_ODR_52Hz; 00291 00292 } else { 00293 odr_xl = val; 00294 } 00295 break; 00296 case LSM6DSO_ODR_FSM_104Hz: 00297 00298 if (val == LSM6DSO_XL_ODR_OFF){ 00299 odr_xl = LSM6DSO_XL_ODR_104Hz; 00300 00301 } else if (val == LSM6DSO_XL_ODR_12Hz5){ 00302 odr_xl = LSM6DSO_XL_ODR_104Hz; 00303 00304 } else if (val == LSM6DSO_XL_ODR_26Hz){ 00305 odr_xl = LSM6DSO_XL_ODR_104Hz; 00306 00307 } else if (val == LSM6DSO_XL_ODR_52Hz){ 00308 odr_xl = LSM6DSO_XL_ODR_104Hz; 00309 00310 } else { 00311 odr_xl = val; 00312 } 00313 break; 00314 default: 00315 odr_xl = val; 00316 break; 00317 } 00318 } 00319 } 00320 } 00321 if (ret == 0) { 00322 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1); 00323 } 00324 if (ret == 0) { 00325 reg.odr_xl = (uint8_t) odr_xl; 00326 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1); 00327 } 00328 return ret; 00329 } 00330 00331 /** 00332 * @brief Accelerometer UI data rate selection.[get] 00333 * 00334 * @param ctx read / write interface definitions 00335 * @param val Get the values of odr_xl in reg CTRL1_XL 00336 * 00337 */ 00338 int32_t lsm6dso_xl_data_rate_get(lsm6dso_ctx_t *ctx, lsm6dso_odr_xl_t *val) 00339 { 00340 lsm6dso_ctrl1_xl_t reg; 00341 int32_t ret; 00342 00343 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1); 00344 00345 switch (reg.odr_xl) { 00346 case LSM6DSO_XL_ODR_OFF: 00347 *val = LSM6DSO_XL_ODR_OFF; 00348 break; 00349 case LSM6DSO_XL_ODR_12Hz5: 00350 *val = LSM6DSO_XL_ODR_12Hz5; 00351 break; 00352 case LSM6DSO_XL_ODR_26Hz: 00353 *val = LSM6DSO_XL_ODR_26Hz; 00354 break; 00355 case LSM6DSO_XL_ODR_52Hz: 00356 *val = LSM6DSO_XL_ODR_52Hz; 00357 break; 00358 case LSM6DSO_XL_ODR_104Hz: 00359 *val = LSM6DSO_XL_ODR_104Hz; 00360 break; 00361 case LSM6DSO_XL_ODR_208Hz: 00362 *val = LSM6DSO_XL_ODR_208Hz; 00363 break; 00364 case LSM6DSO_XL_ODR_417Hz: 00365 *val = LSM6DSO_XL_ODR_417Hz; 00366 break; 00367 case LSM6DSO_XL_ODR_833Hz: 00368 *val = LSM6DSO_XL_ODR_833Hz; 00369 break; 00370 case LSM6DSO_XL_ODR_1667Hz: 00371 *val = LSM6DSO_XL_ODR_1667Hz; 00372 break; 00373 case LSM6DSO_XL_ODR_3333Hz: 00374 *val = LSM6DSO_XL_ODR_3333Hz; 00375 break; 00376 case LSM6DSO_XL_ODR_6667Hz: 00377 *val = LSM6DSO_XL_ODR_6667Hz; 00378 break; 00379 case LSM6DSO_XL_ODR_1Hz6: 00380 *val = LSM6DSO_XL_ODR_1Hz6; 00381 break; 00382 default: 00383 *val = LSM6DSO_XL_ODR_OFF; 00384 break; 00385 } 00386 return ret; 00387 } 00388 00389 /** 00390 * @brief Gyroscope UI chain full-scale selection.[set] 00391 * 00392 * @param ctx read / write interface definitions 00393 * @param val change the values of fs_g in reg CTRL2_G 00394 * 00395 */ 00396 int32_t lsm6dso_gy_full_scale_set(lsm6dso_ctx_t *ctx, lsm6dso_fs_g_t val) 00397 { 00398 lsm6dso_ctrl2_g_t reg; 00399 int32_t ret; 00400 00401 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1); 00402 if (ret == 0) { 00403 reg.fs_g = (uint8_t) val; 00404 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1); 00405 } 00406 00407 return ret; 00408 } 00409 00410 /** 00411 * @brief Gyroscope UI chain full-scale selection.[get] 00412 * 00413 * @param ctx read / write interface definitions 00414 * @param val Get the values of fs_g in reg CTRL2_G 00415 * 00416 */ 00417 int32_t lsm6dso_gy_full_scale_get(lsm6dso_ctx_t *ctx, lsm6dso_fs_g_t *val) 00418 { 00419 lsm6dso_ctrl2_g_t reg; 00420 int32_t ret; 00421 00422 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1); 00423 switch (reg.fs_g) { 00424 case LSM6DSO_250dps: 00425 *val = LSM6DSO_250dps; 00426 break; 00427 case LSM6DSO_125dps: 00428 *val = LSM6DSO_125dps; 00429 break; 00430 case LSM6DSO_500dps: 00431 *val = LSM6DSO_500dps; 00432 break; 00433 case LSM6DSO_1000dps: 00434 *val = LSM6DSO_1000dps; 00435 break; 00436 case LSM6DSO_2000dps: 00437 *val = LSM6DSO_2000dps; 00438 break; 00439 default: 00440 *val = LSM6DSO_250dps; 00441 break; 00442 } 00443 00444 return ret; 00445 } 00446 00447 /** 00448 * @brief Gyroscope UI data rate selection.[set] 00449 * 00450 * @param ctx read / write interface definitions 00451 * @param val change the values of odr_g in reg CTRL2_G 00452 * 00453 */ 00454 int32_t lsm6dso_gy_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_odr_g_t val) 00455 { 00456 lsm6dso_odr_g_t odr_gy = val; 00457 lsm6dso_emb_fsm_enable_t fsm_enable; 00458 lsm6dso_fsm_odr_t fsm_odr; 00459 lsm6dso_ctrl2_g_t reg; 00460 int32_t ret; 00461 00462 /* Check the Finite State Machine data rate constraints */ 00463 ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable); 00464 if (ret == 0) { 00465 if ( (fsm_enable.fsm_enable_a.fsm1_en | 00466 fsm_enable.fsm_enable_a.fsm2_en | 00467 fsm_enable.fsm_enable_a.fsm3_en | 00468 fsm_enable.fsm_enable_a.fsm4_en | 00469 fsm_enable.fsm_enable_a.fsm5_en | 00470 fsm_enable.fsm_enable_a.fsm6_en | 00471 fsm_enable.fsm_enable_a.fsm7_en | 00472 fsm_enable.fsm_enable_a.fsm8_en | 00473 fsm_enable.fsm_enable_b.fsm9_en | 00474 fsm_enable.fsm_enable_b.fsm10_en | 00475 fsm_enable.fsm_enable_b.fsm11_en | 00476 fsm_enable.fsm_enable_b.fsm12_en | 00477 fsm_enable.fsm_enable_b.fsm13_en | 00478 fsm_enable.fsm_enable_b.fsm14_en | 00479 fsm_enable.fsm_enable_b.fsm15_en | 00480 fsm_enable.fsm_enable_b.fsm16_en ) == PROPERTY_ENABLE ){ 00481 00482 ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr); 00483 if (ret == 0) { 00484 switch (fsm_odr) { 00485 case LSM6DSO_ODR_FSM_12Hz5: 00486 00487 if (val == LSM6DSO_GY_ODR_OFF){ 00488 odr_gy = LSM6DSO_GY_ODR_12Hz5; 00489 00490 } else { 00491 odr_gy = val; 00492 } 00493 break; 00494 case LSM6DSO_ODR_FSM_26Hz: 00495 00496 if (val == LSM6DSO_GY_ODR_OFF){ 00497 odr_gy = LSM6DSO_GY_ODR_26Hz; 00498 00499 } else if (val == LSM6DSO_GY_ODR_12Hz5){ 00500 odr_gy = LSM6DSO_GY_ODR_26Hz; 00501 00502 } else { 00503 odr_gy = val; 00504 } 00505 break; 00506 case LSM6DSO_ODR_FSM_52Hz: 00507 00508 if (val == LSM6DSO_GY_ODR_OFF){ 00509 odr_gy = LSM6DSO_GY_ODR_52Hz; 00510 00511 } else if (val == LSM6DSO_GY_ODR_12Hz5){ 00512 odr_gy = LSM6DSO_GY_ODR_52Hz; 00513 00514 } else if (val == LSM6DSO_GY_ODR_26Hz){ 00515 odr_gy = LSM6DSO_GY_ODR_52Hz; 00516 00517 } else { 00518 odr_gy = val; 00519 } 00520 break; 00521 case LSM6DSO_ODR_FSM_104Hz: 00522 00523 if (val == LSM6DSO_GY_ODR_OFF){ 00524 odr_gy = LSM6DSO_GY_ODR_104Hz; 00525 00526 } else if (val == LSM6DSO_GY_ODR_12Hz5){ 00527 odr_gy = LSM6DSO_GY_ODR_104Hz; 00528 00529 } else if (val == LSM6DSO_GY_ODR_26Hz){ 00530 odr_gy = LSM6DSO_GY_ODR_104Hz; 00531 00532 } else if (val == LSM6DSO_GY_ODR_52Hz){ 00533 odr_gy = LSM6DSO_GY_ODR_104Hz; 00534 00535 } else { 00536 odr_gy = val; 00537 } 00538 break; 00539 default: 00540 odr_gy = val; 00541 break; 00542 } 00543 } 00544 } 00545 } 00546 00547 if (ret == 0) { 00548 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1); 00549 } 00550 if (ret == 0) { 00551 reg.odr_g = (uint8_t) odr_gy; 00552 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1); 00553 } 00554 00555 return ret; 00556 } 00557 00558 /** 00559 * @brief Gyroscope UI data rate selection.[get] 00560 * 00561 * @param ctx read / write interface definitions 00562 * @param val Get the values of odr_g in reg CTRL2_G 00563 * 00564 */ 00565 int32_t lsm6dso_gy_data_rate_get(lsm6dso_ctx_t *ctx, lsm6dso_odr_g_t *val) 00566 { 00567 lsm6dso_ctrl2_g_t reg; 00568 int32_t ret; 00569 00570 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t*)®, 1); 00571 switch (reg.odr_g) { 00572 case LSM6DSO_GY_ODR_OFF: 00573 *val = LSM6DSO_GY_ODR_OFF; 00574 break; 00575 case LSM6DSO_GY_ODR_12Hz5: 00576 *val = LSM6DSO_GY_ODR_12Hz5; 00577 break; 00578 case LSM6DSO_GY_ODR_26Hz: 00579 *val = LSM6DSO_GY_ODR_26Hz; 00580 break; 00581 case LSM6DSO_GY_ODR_52Hz: 00582 *val = LSM6DSO_GY_ODR_52Hz; 00583 break; 00584 case LSM6DSO_GY_ODR_104Hz: 00585 *val = LSM6DSO_GY_ODR_104Hz; 00586 break; 00587 case LSM6DSO_GY_ODR_208Hz: 00588 *val = LSM6DSO_GY_ODR_208Hz; 00589 break; 00590 case LSM6DSO_GY_ODR_417Hz: 00591 *val = LSM6DSO_GY_ODR_417Hz; 00592 break; 00593 case LSM6DSO_GY_ODR_833Hz: 00594 *val = LSM6DSO_GY_ODR_833Hz; 00595 break; 00596 case LSM6DSO_GY_ODR_1667Hz: 00597 *val = LSM6DSO_GY_ODR_1667Hz; 00598 break; 00599 case LSM6DSO_GY_ODR_3333Hz: 00600 *val = LSM6DSO_GY_ODR_3333Hz; 00601 break; 00602 case LSM6DSO_GY_ODR_6667Hz: 00603 *val = LSM6DSO_GY_ODR_6667Hz; 00604 break; 00605 default: 00606 *val = LSM6DSO_GY_ODR_OFF; 00607 break; 00608 } 00609 return ret; 00610 } 00611 00612 /** 00613 * @brief Block data update.[set] 00614 * 00615 * @param ctx read / write interface definitions 00616 * @param val change the values of bdu in reg CTRL3_C 00617 * 00618 */ 00619 int32_t lsm6dso_block_data_update_set(lsm6dso_ctx_t *ctx, uint8_t val) 00620 { 00621 lsm6dso_ctrl3_c_t reg; 00622 int32_t ret; 00623 00624 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 00625 if (ret == 0) { 00626 reg.bdu = val; 00627 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 00628 } 00629 return ret; 00630 } 00631 00632 /** 00633 * @brief Block data update.[get] 00634 * 00635 * @param ctx read / write interface definitions 00636 * @param val change the values of bdu in reg CTRL3_C 00637 * 00638 */ 00639 int32_t lsm6dso_block_data_update_get(lsm6dso_ctx_t *ctx, uint8_t *val) 00640 { 00641 lsm6dso_ctrl3_c_t reg; 00642 int32_t ret; 00643 00644 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 00645 *val = reg.bdu; 00646 00647 return ret; 00648 } 00649 00650 /** 00651 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), 00652 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set] 00653 * 00654 * @param ctx read / write interface definitions 00655 * @param val change the values of usr_off_w in reg CTRL6_C 00656 * 00657 */ 00658 int32_t lsm6dso_xl_offset_weight_set(lsm6dso_ctx_t *ctx, 00659 lsm6dso_usr_off_w_t val) 00660 { 00661 lsm6dso_ctrl6_c_t reg; 00662 int32_t ret; 00663 00664 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1); 00665 if (ret == 0) { 00666 reg.usr_off_w = (uint8_t)val; 00667 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1); 00668 } 00669 return ret; 00670 } 00671 00672 /** 00673 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h), 00674 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get] 00675 * 00676 * @param ctx read / write interface definitions 00677 * @param val Get the values of usr_off_w in reg CTRL6_C 00678 * 00679 */ 00680 int32_t lsm6dso_xl_offset_weight_get(lsm6dso_ctx_t *ctx, 00681 lsm6dso_usr_off_w_t *val) 00682 { 00683 lsm6dso_ctrl6_c_t reg; 00684 int32_t ret; 00685 00686 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1); 00687 00688 switch (reg.usr_off_w) { 00689 case LSM6DSO_LSb_1mg: 00690 *val = LSM6DSO_LSb_1mg; 00691 break; 00692 case LSM6DSO_LSb_16mg: 00693 *val = LSM6DSO_LSb_16mg; 00694 break; 00695 default: 00696 *val = LSM6DSO_LSb_1mg; 00697 break; 00698 } 00699 return ret; 00700 } 00701 00702 /** 00703 * @brief Accelerometer power mode.[set] 00704 * 00705 * @param ctx read / write interface definitions 00706 * @param val change the values of xl_hm_mode in 00707 * reg CTRL6_C 00708 * 00709 */ 00710 int32_t lsm6dso_xl_power_mode_set(lsm6dso_ctx_t *ctx, 00711 lsm6dso_xl_hm_mode_t val) 00712 { 00713 lsm6dso_ctrl5_c_t ctrl5_c; 00714 lsm6dso_ctrl6_c_t ctrl6_c; 00715 int32_t ret; 00716 00717 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1); 00718 if (ret == 0) { 00719 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1; 00720 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1); 00721 } 00722 if (ret == 0) { 00723 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1); 00724 } 00725 if (ret == 0) { 00726 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U; 00727 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1); 00728 } 00729 return ret; 00730 } 00731 00732 /** 00733 * @brief Accelerometer power mode.[get] 00734 * 00735 * @param ctx read / write interface definitions 00736 * @param val Get the values of xl_hm_mode in reg CTRL6_C 00737 * 00738 */ 00739 int32_t lsm6dso_xl_power_mode_get(lsm6dso_ctx_t *ctx, 00740 lsm6dso_xl_hm_mode_t *val) 00741 { 00742 lsm6dso_ctrl5_c_t ctrl5_c; 00743 lsm6dso_ctrl6_c_t ctrl6_c; 00744 int32_t ret; 00745 00746 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*) &ctrl5_c, 1); 00747 if (ret == 0) { 00748 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*) &ctrl6_c, 1); 00749 switch ( (ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode) { 00750 case LSM6DSO_HIGH_PERFORMANCE_MD: 00751 *val = LSM6DSO_HIGH_PERFORMANCE_MD; 00752 break; 00753 case LSM6DSO_LOW_NORMAL_POWER_MD: 00754 *val = LSM6DSO_LOW_NORMAL_POWER_MD; 00755 break; 00756 case LSM6DSO_ULTRA_LOW_POWER_MD: 00757 *val = LSM6DSO_ULTRA_LOW_POWER_MD; 00758 break; 00759 default: 00760 *val = LSM6DSO_HIGH_PERFORMANCE_MD; 00761 break; 00762 } 00763 } 00764 return ret; 00765 } 00766 00767 /** 00768 * @brief Operating mode for gyroscope.[set] 00769 * 00770 * @param ctx read / write interface definitions 00771 * @param val change the values of g_hm_mode in reg CTRL7_G 00772 * 00773 */ 00774 int32_t lsm6dso_gy_power_mode_set(lsm6dso_ctx_t *ctx, 00775 lsm6dso_g_hm_mode_t val) 00776 { 00777 lsm6dso_ctrl7_g_t reg; 00778 int32_t ret; 00779 00780 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 00781 if (ret == 0) { 00782 reg.g_hm_mode = (uint8_t)val; 00783 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 00784 } 00785 return ret; 00786 } 00787 00788 /** 00789 * @brief Operating mode for gyroscope.[get] 00790 * 00791 * @param ctx read / write interface definitions 00792 * @param val Get the values of g_hm_mode in reg CTRL7_G 00793 * 00794 */ 00795 int32_t lsm6dso_gy_power_mode_get(lsm6dso_ctx_t *ctx, 00796 lsm6dso_g_hm_mode_t *val) 00797 { 00798 lsm6dso_ctrl7_g_t reg; 00799 int32_t ret; 00800 00801 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 00802 switch (reg.g_hm_mode) { 00803 case LSM6DSO_GY_HIGH_PERFORMANCE: 00804 *val = LSM6DSO_GY_HIGH_PERFORMANCE; 00805 break; 00806 case LSM6DSO_GY_NORMAL: 00807 *val = LSM6DSO_GY_NORMAL; 00808 break; 00809 default: 00810 *val = LSM6DSO_GY_HIGH_PERFORMANCE; 00811 break; 00812 } 00813 return ret; 00814 } 00815 00816 /** 00817 * @brief The STATUS_REG register is read by the primary interface.[get] 00818 * 00819 * @param ctx read / write interface definitions 00820 * @param val register STATUS_REG 00821 * 00822 */ 00823 int32_t lsm6dso_status_reg_get(lsm6dso_ctx_t *ctx, lsm6dso_status_reg_t *val) 00824 { 00825 int32_t ret; 00826 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*) val, 1); 00827 return ret; 00828 } 00829 00830 /** 00831 * @brief Accelerometer new data available.[get] 00832 * 00833 * @param ctx read / write interface definitions 00834 * @param val change the values of xlda in reg STATUS_REG 00835 * 00836 */ 00837 int32_t lsm6dso_xl_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 00838 { 00839 lsm6dso_status_reg_t reg; 00840 int32_t ret; 00841 00842 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)®, 1); 00843 *val = reg.xlda; 00844 00845 return ret; 00846 } 00847 00848 /** 00849 * @brief Gyroscope new data available.[get] 00850 * 00851 * @param ctx read / write interface definitions 00852 * @param val change the values of gda in reg STATUS_REG 00853 * 00854 */ 00855 int32_t lsm6dso_gy_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 00856 { 00857 lsm6dso_status_reg_t reg; 00858 int32_t ret; 00859 00860 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)®, 1); 00861 *val = reg.gda; 00862 00863 return ret; 00864 } 00865 00866 /** 00867 * @brief Temperature new data available.[get] 00868 * 00869 * @param ctx read / write interface definitions 00870 * @param val change the values of tda in reg STATUS_REG 00871 * 00872 */ 00873 int32_t lsm6dso_temp_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 00874 { 00875 lsm6dso_status_reg_t reg; 00876 int32_t ret; 00877 00878 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t*)®, 1); 00879 *val = reg.tda; 00880 00881 return ret; 00882 } 00883 00884 /** 00885 * @brief Accelerometer X-axis user offset correction expressed in 00886 * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00887 * The value must be in the range [-127 127].[set] 00888 * 00889 * @param ctx read / write interface definitions 00890 * @param buff buffer that contains data to write 00891 * 00892 */ 00893 int32_t lsm6dso_xl_usr_offset_x_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 00894 { 00895 int32_t ret; 00896 ret = lsm6dso_write_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1); 00897 return ret; 00898 } 00899 00900 /** 00901 * @brief Accelerometer X-axis user offset correction expressed in two’s 00902 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00903 * The value must be in the range [-127 127].[get] 00904 * 00905 * @param ctx read / write interface definitions 00906 * @param buff buffer that stores data read 00907 * 00908 */ 00909 int32_t lsm6dso_xl_usr_offset_x_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 00910 { 00911 int32_t ret; 00912 ret = lsm6dso_read_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1); 00913 return ret; 00914 } 00915 00916 /** 00917 * @brief Accelerometer Y-axis user offset correction expressed in two’s 00918 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00919 * The value must be in the range [-127 127].[set] 00920 * 00921 * @param ctx read / write interface definitions 00922 * @param buff buffer that contains data to write 00923 * 00924 */ 00925 int32_t lsm6dso_xl_usr_offset_y_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 00926 { 00927 int32_t ret; 00928 ret = lsm6dso_write_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1); 00929 return ret; 00930 } 00931 00932 /** 00933 * @brief Accelerometer Y-axis user offset correction expressed in two’s 00934 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00935 * The value must be in the range [-127 127].[get] 00936 * 00937 * @param ctx read / write interface definitions 00938 * @param buff buffer that stores data read 00939 * 00940 */ 00941 int32_t lsm6dso_xl_usr_offset_y_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 00942 { 00943 int32_t ret; 00944 ret = lsm6dso_read_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1); 00945 return ret; 00946 } 00947 00948 /** 00949 * @brief Accelerometer Z-axis user offset correction expressed in two’s 00950 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00951 * The value must be in the range [-127 127].[set] 00952 * 00953 * @param ctx read / write interface definitions 00954 * @param buff buffer that contains data to write 00955 * 00956 */ 00957 int32_t lsm6dso_xl_usr_offset_z_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 00958 { 00959 int32_t ret; 00960 ret = lsm6dso_write_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1); 00961 return ret; 00962 } 00963 00964 /** 00965 * @brief Accelerometer Z-axis user offset correction expressed in two’s 00966 * complement, weight depends on USR_OFF_W in CTRL6_C (15h). 00967 * The value must be in the range [-127 127].[get] 00968 * 00969 * @param ctx read / write interface definitions 00970 * @param buff buffer that stores data read 00971 * 00972 */ 00973 int32_t lsm6dso_xl_usr_offset_z_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 00974 { 00975 int32_t ret; 00976 ret = lsm6dso_read_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1); 00977 return ret; 00978 } 00979 00980 /** 00981 * @brief Enables user offset on out.[set] 00982 * 00983 * @param ctx read / write interface definitions 00984 * @param val change the values of usr_off_on_out in reg CTRL7_G 00985 * 00986 */ 00987 int32_t lsm6dso_xl_usr_offset_set(lsm6dso_ctx_t *ctx, uint8_t val) 00988 { 00989 lsm6dso_ctrl7_g_t reg; 00990 int32_t ret; 00991 00992 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 00993 if (ret == 0) { 00994 reg.usr_off_on_out = val; 00995 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 00996 } 00997 return ret; 00998 } 00999 01000 /** 01001 * @brief User offset on out flag.[get] 01002 * 01003 * @param ctx read / write interface definitions 01004 * @param val values of usr_off_on_out in reg CTRL7_G 01005 * 01006 */ 01007 int32_t lsm6dso_xl_usr_offset_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01008 { 01009 lsm6dso_ctrl7_g_t reg; 01010 int32_t ret; 01011 01012 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 01013 *val = reg.usr_off_on_out; 01014 01015 return ret; 01016 } 01017 01018 /** 01019 * @} 01020 * 01021 */ 01022 01023 /** 01024 * @defgroup LSM6DSO_Timestamp 01025 * @brief This section groups all the functions that manage the 01026 * timestamp generation. 01027 * @{ 01028 * 01029 */ 01030 01031 /** 01032 * @brief Reset timestamp counter.[set] 01033 * 01034 * @param ctx Read / write interface definitions.(ptr) 01035 * @retval Interface status (MANDATORY: return 0 -> no Error). 01036 * 01037 */ 01038 int32_t lsm6dso_timestamp_rst(lsm6dso_ctx_t *ctx) 01039 { 01040 uint8_t rst_val = 0xAA; 01041 01042 return lsm6dso_write_reg(ctx, LSM6DSO_TIMESTAMP2, &rst_val, 1); 01043 } 01044 01045 /** 01046 * @brief Enables timestamp counter.[set] 01047 * 01048 * @param ctx read / write interface definitions 01049 * @param val change the values of timestamp_en in reg CTRL10_C 01050 * 01051 */ 01052 int32_t lsm6dso_timestamp_set(lsm6dso_ctx_t *ctx, uint8_t val) 01053 { 01054 lsm6dso_ctrl10_c_t reg; 01055 int32_t ret; 01056 01057 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)®, 1); 01058 if (ret == 0) { 01059 reg.timestamp_en = val; 01060 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)®, 1); 01061 } 01062 return ret; 01063 } 01064 01065 /** 01066 * @brief Enables timestamp counter.[get] 01067 * 01068 * @param ctx read / write interface definitions 01069 * @param val change the values of timestamp_en in reg CTRL10_C 01070 * 01071 */ 01072 int32_t lsm6dso_timestamp_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01073 { 01074 lsm6dso_ctrl10_c_t reg; 01075 int32_t ret; 01076 01077 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t*)®, 1); 01078 *val = reg.timestamp_en; 01079 01080 return ret; 01081 } 01082 01083 /** 01084 * @brief Timestamp first data output register (r). 01085 * The value is expressed as a 32-bit word and the bit 01086 * resolution is 25 μs.[get] 01087 * 01088 * @param ctx read / write interface definitions 01089 * @param buff buffer that stores data read 01090 * 01091 */ 01092 int32_t lsm6dso_timestamp_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01093 { 01094 int32_t ret; 01095 ret = lsm6dso_read_reg(ctx, LSM6DSO_TIMESTAMP0, buff, 4); 01096 return ret; 01097 } 01098 01099 /** 01100 * @} 01101 * 01102 */ 01103 01104 /** 01105 * @defgroup LSM6DSO_Data output 01106 * @brief This section groups all the data output functions. 01107 * @{ 01108 * 01109 */ 01110 01111 /** 01112 * @brief Circular burst-mode (rounding) read of the output 01113 * registers.[set] 01114 * 01115 * @param ctx read / write interface definitions 01116 * @param val change the values of rounding in reg CTRL5_C 01117 * 01118 */ 01119 int32_t lsm6dso_rounding_mode_set(lsm6dso_ctx_t *ctx, 01120 lsm6dso_rounding_t val) 01121 { 01122 lsm6dso_ctrl5_c_t reg; 01123 int32_t ret; 01124 01125 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1); 01126 if (ret == 0) { 01127 reg.rounding = (uint8_t)val; 01128 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1); 01129 } 01130 return ret; 01131 } 01132 01133 /** 01134 * @brief Gyroscope UI chain full-scale selection.[get] 01135 * 01136 * @param ctx read / write interface definitions 01137 * @param val Get the values of rounding in reg CTRL5_C 01138 * 01139 */ 01140 int32_t lsm6dso_rounding_mode_get(lsm6dso_ctx_t *ctx, 01141 lsm6dso_rounding_t *val) 01142 { 01143 lsm6dso_ctrl5_c_t reg; 01144 int32_t ret; 01145 01146 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1); 01147 switch (reg.rounding) { 01148 case LSM6DSO_NO_ROUND: 01149 *val = LSM6DSO_NO_ROUND; 01150 break; 01151 case LSM6DSO_ROUND_XL: 01152 *val = LSM6DSO_ROUND_XL; 01153 break; 01154 case LSM6DSO_ROUND_GY: 01155 *val = LSM6DSO_ROUND_GY; 01156 break; 01157 case LSM6DSO_ROUND_GY_XL: 01158 *val = LSM6DSO_ROUND_GY_XL; 01159 break; 01160 default: 01161 *val = LSM6DSO_NO_ROUND; 01162 break; 01163 } 01164 return ret; 01165 } 01166 01167 /** 01168 * @brief Temperature data output register (r). 01169 * L and H registers together express a 16-bit word in two’s 01170 * complement.[get] 01171 * 01172 * @param ctx read / write interface definitions 01173 * @param buff buffer that stores data read 01174 * 01175 */ 01176 int32_t lsm6dso_temperature_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01177 { 01178 int32_t ret; 01179 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 2); 01180 return ret; 01181 } 01182 01183 /** 01184 * @brief Angular rate sensor. The value is expressed as a 16-bit 01185 * word in two’s complement.[get] 01186 * 01187 * @param ctx read / write interface definitions 01188 * @param buff buffer that stores data read 01189 * 01190 */ 01191 int32_t lsm6dso_angular_rate_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01192 { 01193 int32_t ret; 01194 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_G, buff, 6); 01195 return ret; 01196 } 01197 01198 /** 01199 * @brief Linear acceleration output register. 01200 * The value is expressed as a 16-bit word in two’s complement.[get] 01201 * 01202 * @param ctx read / write interface definitions 01203 * @param buff buffer that stores data read 01204 * 01205 */ 01206 int32_t lsm6dso_acceleration_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01207 { 01208 int32_t ret; 01209 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_A, buff, 6); 01210 return ret; 01211 } 01212 01213 /** 01214 * @brief FIFO data output [get] 01215 * 01216 * @param ctx read / write interface definitions 01217 * @param buff buffer that stores data read 01218 * 01219 */ 01220 int32_t lsm6dso_fifo_out_raw_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01221 { 01222 int32_t ret; 01223 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_X_L, buff, 6); 01224 return ret; 01225 } 01226 01227 /** 01228 * @brief Step counter output register.[get] 01229 * 01230 * @param ctx read / write interface definitions 01231 * @param buff buffer that stores data read 01232 * 01233 */ 01234 int32_t lsm6dso_number_of_steps_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01235 { 01236 int32_t ret; 01237 01238 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 01239 if (ret == 0) { 01240 ret = lsm6dso_read_reg(ctx, LSM6DSO_STEP_COUNTER_L, buff, 2); 01241 } 01242 if (ret == 0) { 01243 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 01244 } 01245 return ret; 01246 } 01247 01248 /** 01249 * @brief Reset step counter register.[get] 01250 * 01251 * @param ctx read / write interface definitions 01252 * 01253 */ 01254 int32_t lsm6dso_steps_reset(lsm6dso_ctx_t *ctx) 01255 { 01256 lsm6dso_emb_func_src_t reg; 01257 int32_t ret; 01258 01259 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 01260 if (ret == 0) { 01261 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t*)®, 1); 01262 } 01263 if (ret == 0) { 01264 reg.pedo_rst_step = PROPERTY_ENABLE; 01265 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t*)®, 1); 01266 } 01267 if (ret == 0) { 01268 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 01269 } 01270 return ret; 01271 } 01272 01273 /** 01274 * @} 01275 * 01276 */ 01277 01278 /** 01279 * @defgroup LSM6DSO_common 01280 * @brief This section groups common usefull functions. 01281 * @{ 01282 * 01283 */ 01284 01285 /** 01286 * @brief Difference in percentage of the effective ODR(and timestamp rate) 01287 * with respect to the typical. 01288 * Step: 0.15%. 8-bit format, 2's complement.[set] 01289 * 01290 * @param ctx read / write interface definitions 01291 * @param val change the values of freq_fine in reg 01292 * INTERNAL_FREQ_FINE 01293 * 01294 */ 01295 int32_t lsm6dso_odr_cal_reg_set(lsm6dso_ctx_t *ctx, uint8_t val) 01296 { 01297 lsm6dso_internal_freq_fine_t reg; 01298 int32_t ret; 01299 01300 ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t*)®, 1); 01301 if (ret == 0) { 01302 reg.freq_fine = val; 01303 ret = lsm6dso_write_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, 01304 (uint8_t*)®, 1); 01305 } 01306 return ret; 01307 } 01308 01309 /** 01310 * @brief Difference in percentage of the effective ODR(and timestamp rate) 01311 * with respect to the typical. 01312 * Step: 0.15%. 8-bit format, 2's complement.[get] 01313 * 01314 * @param ctx read / write interface definitions 01315 * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE 01316 * 01317 */ 01318 int32_t lsm6dso_odr_cal_reg_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01319 { 01320 lsm6dso_internal_freq_fine_t reg; 01321 int32_t ret; 01322 01323 ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE, (uint8_t*)®, 1); 01324 *val = reg.freq_fine; 01325 01326 return ret; 01327 } 01328 01329 01330 /** 01331 * @brief Enable access to the embedded functions/sensor 01332 * hub configuration registers.[set] 01333 * 01334 * @param ctx read / write interface definitions 01335 * @param val change the values of reg_access in 01336 * reg FUNC_CFG_ACCESS 01337 * 01338 */ 01339 int32_t lsm6dso_mem_bank_set(lsm6dso_ctx_t *ctx, lsm6dso_reg_access_t val) 01340 { 01341 lsm6dso_func_cfg_access_t reg; 01342 int32_t ret; 01343 01344 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)®, 1); 01345 if (ret == 0) { 01346 reg.reg_access = (uint8_t)val; 01347 ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)®, 1); 01348 } 01349 return ret; 01350 } 01351 01352 /** 01353 * @brief Enable access to the embedded functions/sensor 01354 * hub configuration registers.[get] 01355 * 01356 * @param ctx read / write interface definitions 01357 * @param val Get the values of reg_access in 01358 * reg FUNC_CFG_ACCESS 01359 * 01360 */ 01361 int32_t lsm6dso_mem_bank_get(lsm6dso_ctx_t *ctx, lsm6dso_reg_access_t *val) 01362 { 01363 lsm6dso_func_cfg_access_t reg; 01364 int32_t ret; 01365 01366 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t*)®, 1); 01367 switch (reg.reg_access) { 01368 case LSM6DSO_USER_BANK: 01369 *val = LSM6DSO_USER_BANK; 01370 break; 01371 case LSM6DSO_SENSOR_HUB_BANK: 01372 *val = LSM6DSO_SENSOR_HUB_BANK; 01373 break; 01374 case LSM6DSO_EMBEDDED_FUNC_BANK: 01375 *val = LSM6DSO_EMBEDDED_FUNC_BANK; 01376 break; 01377 default: 01378 *val = LSM6DSO_USER_BANK; 01379 break; 01380 } 01381 return ret; 01382 } 01383 01384 /** 01385 * @brief Write a line(byte) in a page.[set] 01386 * 01387 * @param ctx read / write interface definitions 01388 * @param uint8_t address: page line address 01389 * @param val value to write 01390 * 01391 */ 01392 int32_t lsm6dso_ln_pg_write_byte(lsm6dso_ctx_t *ctx, uint16_t address, 01393 uint8_t *val) 01394 { 01395 lsm6dso_page_rw_t page_rw; 01396 lsm6dso_page_sel_t page_sel; 01397 lsm6dso_page_address_t page_address; 01398 int32_t ret; 01399 01400 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 01401 01402 if (ret == 0) { 01403 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01404 } 01405 if (ret == 0) { 01406 page_rw.page_rw = 0x02; /* page_write enable */ 01407 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01408 } 01409 if (ret == 0) { 01410 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1); 01411 } 01412 01413 if (ret == 0) { 01414 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); 01415 page_sel.not_used_01 = 1; 01416 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1); 01417 } 01418 if (ret == 0) { 01419 page_address.page_addr = (uint8_t)address & 0xFFU; 01420 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS, 01421 (uint8_t*)&page_address, 1); 01422 } 01423 if (ret == 0) { 01424 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1); 01425 } 01426 if (ret == 0) { 01427 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01428 } 01429 if (ret == 0) { 01430 page_rw.page_rw = 0x00; /* page_write disable */ 01431 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01432 } 01433 if (ret == 0) { 01434 01435 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 01436 } 01437 return ret; 01438 } 01439 01440 /** 01441 * @brief Write buffer in a page.[set] 01442 * 01443 * @param ctx read / write interface definitions 01444 * @param uint8_t address: page line address 01445 * @param uint8_t *buf: buffer to write 01446 * @param uint8_t len: buffer len 01447 * 01448 */ 01449 int32_t lsm6dso_ln_pg_write(lsm6dso_ctx_t *ctx, uint16_t address, 01450 uint8_t *buf, uint8_t len) 01451 { 01452 lsm6dso_page_rw_t page_rw; 01453 lsm6dso_page_sel_t page_sel; 01454 lsm6dso_page_address_t page_address; 01455 uint16_t addr_pointed; 01456 int32_t ret; 01457 uint8_t i ; 01458 01459 addr_pointed = address; 01460 01461 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 01462 if (ret == 0) { 01463 01464 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01465 } 01466 if (ret == 0) { 01467 page_rw.page_rw = 0x02; /* page_write enable*/ 01468 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01469 } 01470 if (ret == 0) { 01471 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1); 01472 } 01473 if (ret == 0) { 01474 page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU); 01475 page_sel.not_used_01 = 1; 01476 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1); 01477 } 01478 if (ret == 0) { 01479 page_address.page_addr = (uint8_t)(addr_pointed & 0x00FFU); 01480 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS, 01481 (uint8_t*)&page_address, 1); 01482 } 01483 01484 if (ret == 0) { 01485 for (i = 0; ( (i < len) && (ret == 0) ); i++) { 01486 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1); 01487 addr_pointed++; 01488 /* Check if page wrap */ 01489 if ( ( (addr_pointed % 0x0100U) == 0x00U ) && (ret == 0) ) { 01490 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*)&page_sel, 1); 01491 if (ret == 0) { 01492 page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU); 01493 page_sel.not_used_01 = 1; 01494 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, 01495 (uint8_t*)&page_sel, 1); 01496 } 01497 } 01498 } 01499 page_sel.page_sel = 0; 01500 page_sel.not_used_01 = 1; 01501 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1); 01502 } 01503 if (ret == 0) { 01504 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01505 } 01506 if (ret == 0) { 01507 page_rw.page_rw = 0x00; /* page_write disable */ 01508 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01509 } 01510 if (ret == 0) { 01511 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 01512 } 01513 return ret; 01514 } 01515 01516 /** 01517 * @brief Read a line(byte) in a page.[get] 01518 * 01519 * @param ctx read / write interface definitions 01520 * @param uint8_t address: page line address 01521 * @param val read value 01522 * 01523 */ 01524 int32_t lsm6dso_ln_pg_read_byte(lsm6dso_ctx_t *ctx, uint16_t address, 01525 uint8_t *val) 01526 { 01527 lsm6dso_page_rw_t page_rw; 01528 lsm6dso_page_sel_t page_sel; 01529 lsm6dso_page_address_t page_address; 01530 int32_t ret; 01531 01532 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 01533 if (ret == 0) { 01534 01535 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01536 } 01537 if (ret == 0) { 01538 page_rw.page_rw = 0x01; /* page_read enable*/ 01539 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01540 } 01541 if (ret == 0) { 01542 01543 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1); 01544 } 01545 if (ret == 0) { 01546 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU); 01547 page_sel.not_used_01 = 1; 01548 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t*) &page_sel, 1); 01549 } 01550 if (ret == 0) { 01551 page_address.page_addr = (uint8_t)address & 0x00FFU; 01552 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS, 01553 (uint8_t*)&page_address, 1); 01554 } 01555 if (ret == 0) { 01556 01557 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1); 01558 } 01559 if (ret == 0) { 01560 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01561 } 01562 if (ret == 0) { 01563 page_rw.page_rw = 0x00; /* page_read disable */ 01564 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 01565 } 01566 if (ret == 0) { 01567 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 01568 } 01569 01570 return ret; 01571 } 01572 01573 /** 01574 * @brief Data-ready pulsed / letched mode.[set] 01575 * 01576 * @param ctx read / write interface definitions 01577 * @param val change the values of 01578 * dataready_pulsed in 01579 * reg COUNTER_BDR_REG1 01580 * 01581 */ 01582 int32_t lsm6dso_data_ready_mode_set(lsm6dso_ctx_t *ctx, 01583 lsm6dso_dataready_pulsed_t val) 01584 { 01585 lsm6dso_counter_bdr_reg1_t reg; 01586 int32_t ret; 01587 01588 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1); 01589 if (ret == 0) { 01590 reg.dataready_pulsed = (uint8_t)val; 01591 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1); 01592 } 01593 return ret; 01594 } 01595 01596 /** 01597 * @brief Data-ready pulsed / letched mode.[get] 01598 * 01599 * @param ctx read / write interface definitions 01600 * @param val Get the values of 01601 * dataready_pulsed in 01602 * reg COUNTER_BDR_REG1 01603 * 01604 */ 01605 int32_t lsm6dso_data_ready_mode_get(lsm6dso_ctx_t *ctx, 01606 lsm6dso_dataready_pulsed_t *val) 01607 { 01608 lsm6dso_counter_bdr_reg1_t reg; 01609 int32_t ret; 01610 01611 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1); 01612 switch (reg.dataready_pulsed) { 01613 case LSM6DSO_DRDY_LATCHED: 01614 *val = LSM6DSO_DRDY_LATCHED; 01615 break; 01616 case LSM6DSO_DRDY_PULSED: 01617 *val = LSM6DSO_DRDY_PULSED; 01618 break; 01619 default: 01620 *val = LSM6DSO_DRDY_LATCHED; 01621 break; 01622 } 01623 return ret; 01624 } 01625 01626 /** 01627 * @brief Device "Who am I".[get] 01628 * 01629 * @param ctx read / write interface definitions 01630 * @param buff buffer that stores data read 01631 * 01632 */ 01633 int32_t lsm6dso_device_id_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 01634 { 01635 int32_t ret; 01636 ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, buff, 1); 01637 return ret; 01638 } 01639 01640 /** 01641 * @brief Software reset. Restore the default values 01642 * in user registers[set] 01643 * 01644 * @param ctx read / write interface definitions 01645 * @param val change the values of sw_reset in reg CTRL3_C 01646 * 01647 */ 01648 int32_t lsm6dso_reset_set(lsm6dso_ctx_t *ctx, uint8_t val) 01649 { 01650 lsm6dso_ctrl3_c_t reg; 01651 int32_t ret; 01652 01653 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 01654 if (ret == 0) { 01655 reg.sw_reset = val; 01656 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 01657 } 01658 01659 return ret; 01660 } 01661 01662 /** 01663 * @brief Software reset. Restore the default values in user registers.[get] 01664 * 01665 * @param ctx read / write interface definitions 01666 * @param val change the values of sw_reset in reg CTRL3_C 01667 * 01668 */ 01669 int32_t lsm6dso_reset_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01670 { 01671 lsm6dso_ctrl3_c_t reg; 01672 int32_t ret; 01673 01674 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 01675 *val = reg.sw_reset; 01676 01677 return ret; 01678 } 01679 01680 /** 01681 * @brief Register address automatically incremented during a multiple byte 01682 * access with a serial interface.[set] 01683 * 01684 * @param ctx read / write interface definitions 01685 * @param val change the values of if_inc in reg CTRL3_C 01686 * 01687 */ 01688 int32_t lsm6dso_auto_increment_set(lsm6dso_ctx_t *ctx, uint8_t val) 01689 { 01690 lsm6dso_ctrl3_c_t reg; 01691 int32_t ret; 01692 01693 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 01694 if (ret == 0) { 01695 reg.if_inc = val; 01696 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 01697 } 01698 return ret; 01699 } 01700 01701 /** 01702 * @brief Register address automatically incremented during a multiple byte 01703 * access with a serial interface.[get] 01704 * 01705 * @param ctx read / write interface definitions 01706 * @param val change the values of if_inc in reg CTRL3_C 01707 * 01708 */ 01709 int32_t lsm6dso_auto_increment_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01710 { 01711 lsm6dso_ctrl3_c_t reg; 01712 int32_t ret; 01713 01714 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 01715 *val = reg.if_inc; 01716 01717 return ret; 01718 } 01719 01720 /** 01721 * @brief Reboot memory content. Reload the calibration parameters.[set] 01722 * 01723 * @param ctx read / write interface definitions 01724 * @param val change the values of boot in reg CTRL3_C 01725 * 01726 */ 01727 int32_t lsm6dso_boot_set(lsm6dso_ctx_t *ctx, uint8_t val) 01728 { 01729 lsm6dso_ctrl3_c_t reg; 01730 int32_t ret; 01731 01732 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 01733 if (ret == 0) { 01734 reg.boot = val; 01735 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 01736 } 01737 return ret; 01738 } 01739 01740 /** 01741 * @brief Reboot memory content. Reload the calibration parameters.[get] 01742 * 01743 * @param ctx read / write interface definitions 01744 * @param val change the values of boot in reg CTRL3_C 01745 * 01746 */ 01747 int32_t lsm6dso_boot_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01748 { 01749 lsm6dso_ctrl3_c_t reg; 01750 int32_t ret; 01751 01752 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 01753 *val = reg.boot; 01754 01755 return ret; 01756 } 01757 01758 /** 01759 * @brief Linear acceleration sensor self-test enable.[set] 01760 * 01761 * @param ctx read / write interface definitions 01762 * @param val change the values of st_xl in reg CTRL5_C 01763 * 01764 */ 01765 int32_t lsm6dso_xl_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_xl_t val) 01766 { 01767 lsm6dso_ctrl5_c_t reg; 01768 int32_t ret; 01769 01770 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1); 01771 if (ret == 0) { 01772 reg.st_xl = (uint8_t)val; 01773 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1); 01774 } 01775 return ret; 01776 } 01777 01778 /** 01779 * @brief Linear acceleration sensor self-test enable.[get] 01780 * 01781 * @param ctx read / write interface definitions 01782 * @param val Get the values of st_xl in reg CTRL5_C 01783 * 01784 */ 01785 int32_t lsm6dso_xl_self_test_get(lsm6dso_ctx_t *ctx, lsm6dso_st_xl_t *val) 01786 { 01787 lsm6dso_ctrl5_c_t reg; 01788 int32_t ret; 01789 01790 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1); 01791 switch (reg.st_xl) { 01792 case LSM6DSO_XL_ST_DISABLE: 01793 *val = LSM6DSO_XL_ST_DISABLE; 01794 break; 01795 case LSM6DSO_XL_ST_POSITIVE: 01796 *val = LSM6DSO_XL_ST_POSITIVE; 01797 break; 01798 case LSM6DSO_XL_ST_NEGATIVE: 01799 *val = LSM6DSO_XL_ST_NEGATIVE; 01800 break; 01801 default: 01802 *val = LSM6DSO_XL_ST_DISABLE; 01803 break; 01804 } 01805 return ret; 01806 } 01807 01808 /** 01809 * @brief Angular rate sensor self-test enable.[set] 01810 * 01811 * @param ctx read / write interface definitions 01812 * @param val change the values of st_g in reg CTRL5_C 01813 * 01814 */ 01815 int32_t lsm6dso_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_g_t val) 01816 { 01817 lsm6dso_ctrl5_c_t reg; 01818 int32_t ret; 01819 01820 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1); 01821 if (ret == 0) { 01822 reg.st_g = (uint8_t)val; 01823 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1); 01824 } 01825 return ret; 01826 } 01827 01828 /** 01829 * @brief Angular rate sensor self-test enable.[get] 01830 * 01831 * @param ctx read / write interface definitions 01832 * @param val Get the values of st_g in reg CTRL5_C 01833 * 01834 */ 01835 int32_t lsm6dso_gy_self_test_get(lsm6dso_ctx_t *ctx, lsm6dso_st_g_t *val) 01836 { 01837 lsm6dso_ctrl5_c_t reg; 01838 int32_t ret; 01839 01840 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)®, 1); 01841 switch (reg.st_g) { 01842 case LSM6DSO_GY_ST_DISABLE: 01843 *val = LSM6DSO_GY_ST_DISABLE; 01844 break; 01845 case LSM6DSO_GY_ST_POSITIVE: 01846 *val = LSM6DSO_GY_ST_POSITIVE; 01847 break; 01848 case LSM6DSO_GY_ST_NEGATIVE: 01849 *val = LSM6DSO_GY_ST_NEGATIVE; 01850 break; 01851 default: 01852 *val = LSM6DSO_GY_ST_DISABLE; 01853 break; 01854 } 01855 return ret; 01856 } 01857 01858 /** 01859 * @} 01860 * 01861 */ 01862 01863 /** 01864 * @defgroup LSM6DSO_filters 01865 * @brief This section group all the functions concerning the 01866 * filters configuration 01867 * @{ 01868 * 01869 */ 01870 01871 /** 01872 * @brief Accelerometer output from LPF2 filtering stage selection.[set] 01873 * 01874 * @param ctx read / write interface definitions 01875 * @param val change the values of lpf2_xl_en in reg CTRL1_XL 01876 * 01877 */ 01878 int32_t lsm6dso_xl_filter_lp2_set(lsm6dso_ctx_t *ctx, uint8_t val) 01879 { 01880 lsm6dso_ctrl1_xl_t reg; 01881 int32_t ret; 01882 01883 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1); 01884 if (ret == 0) { 01885 reg.lpf2_xl_en = val; 01886 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1); 01887 } 01888 return ret; 01889 } 01890 01891 /** 01892 * @brief Accelerometer output from LPF2 filtering stage selection.[get] 01893 * 01894 * @param ctx read / write interface definitions 01895 * @param val change the values of lpf2_xl_en in reg CTRL1_XL 01896 * 01897 */ 01898 int32_t lsm6dso_xl_filter_lp2_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01899 { 01900 lsm6dso_ctrl1_xl_t reg; 01901 int32_t ret; 01902 01903 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 1); 01904 *val = reg.lpf2_xl_en; 01905 01906 return ret; 01907 } 01908 01909 /** 01910 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; 01911 * the bandwidth can be selected through FTYPE [2:0] 01912 * in CTRL6_C (15h).[set] 01913 * 01914 * @param ctx read / write interface definitions 01915 * @param val change the values of lpf1_sel_g in reg CTRL4_C 01916 * 01917 */ 01918 int32_t lsm6dso_gy_filter_lp1_set(lsm6dso_ctx_t *ctx, uint8_t val) 01919 { 01920 lsm6dso_ctrl4_c_t reg; 01921 int32_t ret; 01922 01923 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 01924 if (ret == 0) { 01925 reg.lpf1_sel_g = val; 01926 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 01927 } 01928 return ret; 01929 } 01930 01931 /** 01932 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled; 01933 * the bandwidth can be selected through FTYPE [2:0] 01934 * in CTRL6_C (15h).[get] 01935 * 01936 * @param ctx read / write interface definitions 01937 * @param val change the values of lpf1_sel_g in reg CTRL4_C 01938 * 01939 */ 01940 int32_t lsm6dso_gy_filter_lp1_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01941 { 01942 lsm6dso_ctrl4_c_t reg; 01943 int32_t ret; 01944 01945 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 01946 *val = reg.lpf1_sel_g; 01947 01948 return ret; 01949 } 01950 01951 /** 01952 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends 01953 * (XL and Gyro independently masked).[set] 01954 * 01955 * @param ctx read / write interface definitions 01956 * @param val change the values of drdy_mask in reg CTRL4_C 01957 * 01958 */ 01959 int32_t lsm6dso_filter_settling_mask_set(lsm6dso_ctx_t *ctx, uint8_t val) 01960 { 01961 lsm6dso_ctrl4_c_t reg; 01962 int32_t ret; 01963 01964 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 01965 if (ret == 0) { 01966 reg.drdy_mask = val; 01967 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 01968 } 01969 return ret; 01970 } 01971 01972 /** 01973 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends 01974 * (XL and Gyro independently masked).[get] 01975 * 01976 * @param ctx read / write interface definitions 01977 * @param val change the values of drdy_mask in reg CTRL4_C 01978 * 01979 */ 01980 int32_t lsm6dso_filter_settling_mask_get(lsm6dso_ctx_t *ctx, uint8_t *val) 01981 { 01982 lsm6dso_ctrl4_c_t reg; 01983 int32_t ret; 01984 01985 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 01986 *val = reg.drdy_mask; 01987 01988 return ret; 01989 } 01990 01991 /** 01992 * @brief Gyroscope lp1 bandwidth.[set] 01993 * 01994 * @param ctx read / write interface definitions 01995 * @param val change the values of ftype in reg CTRL6_C 01996 * 01997 */ 01998 int32_t lsm6dso_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx, lsm6dso_ftype_t val) 01999 { 02000 lsm6dso_ctrl6_c_t reg; 02001 int32_t ret; 02002 02003 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1); 02004 if (ret == 0) { 02005 reg.ftype = (uint8_t)val; 02006 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1); 02007 } 02008 return ret; 02009 } 02010 02011 /** 02012 * @brief Gyroscope lp1 bandwidth.[get] 02013 * 02014 * @param ctx read / write interface definitions 02015 * @param val Get the values of ftype in reg CTRL6_C 02016 * 02017 */ 02018 int32_t lsm6dso_gy_lp1_bandwidth_get(lsm6dso_ctx_t *ctx, lsm6dso_ftype_t *val) 02019 { 02020 lsm6dso_ctrl6_c_t reg; 02021 int32_t ret; 02022 02023 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1); 02024 switch (reg.ftype) { 02025 case LSM6DSO_ULTRA_LIGHT: 02026 *val = LSM6DSO_ULTRA_LIGHT; 02027 break; 02028 case LSM6DSO_VERY_LIGHT: 02029 *val = LSM6DSO_VERY_LIGHT; 02030 break; 02031 case LSM6DSO_LIGHT: 02032 *val = LSM6DSO_LIGHT; 02033 break; 02034 case LSM6DSO_MEDIUM: 02035 *val = LSM6DSO_MEDIUM; 02036 break; 02037 case LSM6DSO_STRONG: 02038 *val = LSM6DSO_STRONG; 02039 break; 02040 case LSM6DSO_VERY_STRONG: 02041 *val = LSM6DSO_VERY_STRONG; 02042 break; 02043 case LSM6DSO_AGGRESSIVE: 02044 *val = LSM6DSO_AGGRESSIVE; 02045 break; 02046 case LSM6DSO_XTREME: 02047 *val = LSM6DSO_XTREME; 02048 break; 02049 default: 02050 *val = LSM6DSO_ULTRA_LIGHT; 02051 break; 02052 } 02053 return ret; 02054 } 02055 02056 /** 02057 * @brief Low pass filter 2 on 6D function selection.[set] 02058 * 02059 * @param ctx read / write interface definitions 02060 * @param val change the values of low_pass_on_6d in reg CTRL8_XL 02061 * 02062 */ 02063 int32_t lsm6dso_xl_lp2_on_6d_set(lsm6dso_ctx_t *ctx, uint8_t val) 02064 { 02065 lsm6dso_ctrl8_xl_t reg; 02066 int32_t ret; 02067 02068 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02069 if (ret == 0) { 02070 reg.low_pass_on_6d = val; 02071 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02072 } 02073 return ret; 02074 } 02075 02076 /** 02077 * @brief Low pass filter 2 on 6D function selection.[get] 02078 * 02079 * @param ctx read / write interface definitions 02080 * @param val change the values of low_pass_on_6d in reg CTRL8_XL 02081 * 02082 */ 02083 int32_t lsm6dso_xl_lp2_on_6d_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02084 { 02085 lsm6dso_ctrl8_xl_t reg; 02086 int32_t ret; 02087 02088 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02089 *val = reg.low_pass_on_6d; 02090 02091 return ret; 02092 } 02093 02094 /** 02095 * @brief Accelerometer slope filter / high-pass filter selection 02096 * on output.[set] 02097 * 02098 * @param ctx read / write interface definitions 02099 * @param val change the values of hp_slope_xl_en 02100 * in reg CTRL8_XL 02101 * 02102 */ 02103 int32_t lsm6dso_xl_hp_path_on_out_set(lsm6dso_ctx_t *ctx, 02104 lsm6dso_hp_slope_xl_en_t val) 02105 { 02106 lsm6dso_ctrl8_xl_t reg; 02107 int32_t ret; 02108 02109 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02110 if (ret == 0) { 02111 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4; 02112 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5; 02113 reg.hpcf_xl = (uint8_t)val & 0x07U; 02114 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02115 } 02116 return ret; 02117 } 02118 02119 /** 02120 * @brief Accelerometer slope filter / high-pass filter selection 02121 * on output.[get] 02122 * 02123 * @param ctx read / write interface definitions 02124 * @param val Get the values of hp_slope_xl_en 02125 * in reg CTRL8_XL 02126 * 02127 */ 02128 int32_t lsm6dso_xl_hp_path_on_out_get(lsm6dso_ctx_t *ctx, 02129 lsm6dso_hp_slope_xl_en_t *val) 02130 { 02131 lsm6dso_ctrl8_xl_t reg; 02132 int32_t ret; 02133 02134 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02135 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) | 02136 reg.hpcf_xl) { 02137 case LSM6DSO_HP_PATH_DISABLE_ON_OUT: 02138 *val = LSM6DSO_HP_PATH_DISABLE_ON_OUT; 02139 break; 02140 case LSM6DSO_SLOPE_ODR_DIV_4: 02141 *val = LSM6DSO_SLOPE_ODR_DIV_4; 02142 break; 02143 case LSM6DSO_HP_ODR_DIV_10: 02144 *val = LSM6DSO_HP_ODR_DIV_10; 02145 break; 02146 case LSM6DSO_HP_ODR_DIV_20: 02147 *val = LSM6DSO_HP_ODR_DIV_20; 02148 break; 02149 case LSM6DSO_HP_ODR_DIV_45: 02150 *val = LSM6DSO_HP_ODR_DIV_45; 02151 break; 02152 case LSM6DSO_HP_ODR_DIV_100: 02153 *val = LSM6DSO_HP_ODR_DIV_100; 02154 break; 02155 case LSM6DSO_HP_ODR_DIV_200: 02156 *val = LSM6DSO_HP_ODR_DIV_200; 02157 break; 02158 case LSM6DSO_HP_ODR_DIV_400: 02159 *val = LSM6DSO_HP_ODR_DIV_400; 02160 break; 02161 case LSM6DSO_HP_ODR_DIV_800: 02162 *val = LSM6DSO_HP_ODR_DIV_800; 02163 break; 02164 case LSM6DSO_HP_REF_MD_ODR_DIV_10: 02165 *val = LSM6DSO_HP_REF_MD_ODR_DIV_10; 02166 break; 02167 case LSM6DSO_HP_REF_MD_ODR_DIV_20: 02168 *val = LSM6DSO_HP_REF_MD_ODR_DIV_20; 02169 break; 02170 case LSM6DSO_HP_REF_MD_ODR_DIV_45: 02171 *val = LSM6DSO_HP_REF_MD_ODR_DIV_45; 02172 break; 02173 case LSM6DSO_HP_REF_MD_ODR_DIV_100: 02174 *val = LSM6DSO_HP_REF_MD_ODR_DIV_100; 02175 break; 02176 case LSM6DSO_HP_REF_MD_ODR_DIV_200: 02177 *val = LSM6DSO_HP_REF_MD_ODR_DIV_200; 02178 break; 02179 case LSM6DSO_HP_REF_MD_ODR_DIV_400: 02180 *val = LSM6DSO_HP_REF_MD_ODR_DIV_400; 02181 break; 02182 case LSM6DSO_HP_REF_MD_ODR_DIV_800: 02183 *val = LSM6DSO_HP_REF_MD_ODR_DIV_800; 02184 break; 02185 case LSM6DSO_LP_ODR_DIV_10: 02186 *val = LSM6DSO_LP_ODR_DIV_10; 02187 break; 02188 case LSM6DSO_LP_ODR_DIV_20: 02189 *val = LSM6DSO_LP_ODR_DIV_20; 02190 break; 02191 case LSM6DSO_LP_ODR_DIV_45: 02192 *val = LSM6DSO_LP_ODR_DIV_45; 02193 break; 02194 case LSM6DSO_LP_ODR_DIV_100: 02195 *val = LSM6DSO_LP_ODR_DIV_100; 02196 break; 02197 case LSM6DSO_LP_ODR_DIV_200: 02198 *val = LSM6DSO_LP_ODR_DIV_200; 02199 break; 02200 case LSM6DSO_LP_ODR_DIV_400: 02201 *val = LSM6DSO_LP_ODR_DIV_400; 02202 break; 02203 case LSM6DSO_LP_ODR_DIV_800: 02204 *val = LSM6DSO_LP_ODR_DIV_800; 02205 break; 02206 default: 02207 *val = LSM6DSO_HP_PATH_DISABLE_ON_OUT; 02208 break; 02209 } 02210 02211 return ret; 02212 } 02213 02214 /** 02215 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. 02216 * The filter sets the second samples after writing this bit. 02217 * Active only during device exit from power-down mode.[set] 02218 * 02219 * @param ctx read / write interface definitions 02220 * @param val change the values of fastsettl_mode_xl in 02221 * reg CTRL8_XL 02222 * 02223 */ 02224 int32_t lsm6dso_xl_fast_settling_set(lsm6dso_ctx_t *ctx, uint8_t val) 02225 { 02226 lsm6dso_ctrl8_xl_t reg; 02227 int32_t ret; 02228 02229 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02230 if (ret == 0) { 02231 reg.fastsettl_mode_xl = val; 02232 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02233 } 02234 return ret; 02235 } 02236 02237 /** 02238 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. 02239 * The filter sets the second samples after writing this bit. 02240 * Active only during device exit from power-down mode.[get] 02241 * 02242 * @param ctx read / write interface definitions 02243 * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL 02244 * 02245 */ 02246 int32_t lsm6dso_xl_fast_settling_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02247 { 02248 lsm6dso_ctrl8_xl_t reg; 02249 int32_t ret; 02250 02251 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02252 *val = reg.fastsettl_mode_xl; 02253 02254 return ret; 02255 } 02256 02257 /** 02258 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity 02259 * functions.[set] 02260 * 02261 * @param ctx read / write interface definitions 02262 * @param val change the values of slope_fds in reg TAP_CFG0 02263 * 02264 */ 02265 int32_t lsm6dso_xl_hp_path_internal_set(lsm6dso_ctx_t *ctx, 02266 lsm6dso_slope_fds_t val) 02267 { 02268 lsm6dso_tap_cfg0_t reg; 02269 int32_t ret; 02270 02271 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 02272 if (ret == 0) { 02273 reg.slope_fds = (uint8_t)val; 02274 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 02275 } 02276 return ret; 02277 } 02278 02279 /** 02280 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity 02281 * functions.[get] 02282 * 02283 * @param ctx read / write interface definitions 02284 * @param val Get the values of slope_fds in reg TAP_CFG0 02285 * 02286 */ 02287 int32_t lsm6dso_xl_hp_path_internal_get(lsm6dso_ctx_t *ctx, 02288 lsm6dso_slope_fds_t *val) 02289 { 02290 lsm6dso_tap_cfg0_t reg; 02291 int32_t ret; 02292 02293 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 02294 switch (reg.slope_fds) { 02295 case LSM6DSO_USE_SLOPE: 02296 *val = LSM6DSO_USE_SLOPE; 02297 break; 02298 case LSM6DSO_USE_HPF: 02299 *val = LSM6DSO_USE_HPF; 02300 break; 02301 default: 02302 *val = LSM6DSO_USE_SLOPE; 02303 break; 02304 } 02305 return ret; 02306 } 02307 02308 /** 02309 * @brief Enables gyroscope digital high-pass filter. The filter is 02310 * enabled only if the gyro is in HP mode.[set] 02311 * 02312 * @param ctx read / write interface definitions 02313 * @param val Get the values of hp_en_g and hp_en_g 02314 * in reg CTRL7_G 02315 * 02316 */ 02317 int32_t lsm6dso_gy_hp_path_internal_set(lsm6dso_ctx_t *ctx, 02318 lsm6dso_hpm_g_t val) 02319 { 02320 lsm6dso_ctrl7_g_t reg; 02321 int32_t ret; 02322 02323 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 02324 if (ret == 0) { 02325 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7; 02326 reg.hpm_g = (uint8_t)val & 0x03U; 02327 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 02328 } 02329 return ret; 02330 } 02331 02332 /** 02333 * @brief Enables gyroscope digital high-pass filter. The filter is 02334 * enabled only if the gyro is in HP mode.[get] 02335 * 02336 * @param ctx read / write interface definitions 02337 * @param val Get the values of hp_en_g and hp_en_g 02338 * in reg CTRL7_G 02339 * 02340 */ 02341 int32_t lsm6dso_gy_hp_path_internal_get(lsm6dso_ctx_t *ctx, 02342 lsm6dso_hpm_g_t *val) 02343 { 02344 lsm6dso_ctrl7_g_t reg; 02345 int32_t ret; 02346 02347 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 02348 switch ((reg.hp_en_g << 7) + reg.hpm_g) { 02349 case LSM6DSO_HP_FILTER_NONE: 02350 *val = LSM6DSO_HP_FILTER_NONE; 02351 break; 02352 case LSM6DSO_HP_FILTER_16mHz: 02353 *val = LSM6DSO_HP_FILTER_16mHz; 02354 break; 02355 case LSM6DSO_HP_FILTER_65mHz: 02356 *val = LSM6DSO_HP_FILTER_65mHz; 02357 break; 02358 case LSM6DSO_HP_FILTER_260mHz: 02359 *val = LSM6DSO_HP_FILTER_260mHz; 02360 break; 02361 case LSM6DSO_HP_FILTER_1Hz04: 02362 *val = LSM6DSO_HP_FILTER_1Hz04; 02363 break; 02364 default: 02365 *val = LSM6DSO_HP_FILTER_NONE; 02366 break; 02367 } 02368 return ret; 02369 } 02370 02371 /** 02372 * @} 02373 * 02374 */ 02375 02376 /** 02377 * @defgroup LSM6DSO_ Auxiliary_interface 02378 * @brief This section groups all the functions concerning 02379 * auxiliary interface. 02380 * @{ 02381 * 02382 */ 02383 02384 /** 02385 * @brief aOn auxiliary interface connect/disconnect SDO and OCS 02386 * internal pull-up.[set] 02387 * 02388 * @param ctx read / write interface definitions 02389 * @param val change the values of ois_pu_dis in 02390 * reg PIN_CTRL 02391 * 02392 */ 02393 int32_t lsm6dso_aux_sdo_ocs_mode_set(lsm6dso_ctx_t *ctx, 02394 lsm6dso_ois_pu_dis_t val) 02395 { 02396 lsm6dso_pin_ctrl_t reg; 02397 int32_t ret; 02398 02399 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1); 02400 if (ret == 0) { 02401 reg.ois_pu_dis = (uint8_t)val; 02402 ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1); 02403 } 02404 return ret; 02405 } 02406 02407 /** 02408 * @brief On auxiliary interface connect/disconnect SDO and OCS 02409 * internal pull-up.[get] 02410 * 02411 * @param ctx read / write interface definitions 02412 * @param val Get the values of ois_pu_dis in reg PIN_CTRL 02413 * 02414 */ 02415 int32_t lsm6dso_aux_sdo_ocs_mode_get(lsm6dso_ctx_t *ctx, 02416 lsm6dso_ois_pu_dis_t *val) 02417 { 02418 lsm6dso_pin_ctrl_t reg; 02419 int32_t ret; 02420 02421 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1); 02422 switch (reg.ois_pu_dis) { 02423 case LSM6DSO_AUX_PULL_UP_DISC: 02424 *val = LSM6DSO_AUX_PULL_UP_DISC; 02425 break; 02426 case LSM6DSO_AUX_PULL_UP_CONNECT: 02427 *val = LSM6DSO_AUX_PULL_UP_CONNECT; 02428 break; 02429 default: 02430 *val = LSM6DSO_AUX_PULL_UP_DISC; 02431 break; 02432 } 02433 return ret; 02434 } 02435 02436 /** 02437 * @brief OIS chain on aux interface power on mode.[set] 02438 * 02439 * @param ctx read / write interface definitions 02440 * @param val change the values of ois_on in reg CTRL7_G 02441 * 02442 */ 02443 int32_t lsm6dso_aux_pw_on_ctrl_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_on_t val) 02444 { 02445 lsm6dso_ctrl7_g_t reg; 02446 int32_t ret; 02447 02448 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 02449 if (ret == 0) { 02450 reg.ois_on_en = (uint8_t)val & 0x01U; 02451 reg.ois_on = (uint8_t)val & 0x01U; 02452 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 02453 } 02454 return ret; 02455 } 02456 02457 /** 02458 * @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode 02459 * 02460 * @param ctx read / write interface definitions 02461 * @param val Get the values of ois_on in reg CTRL7_G 02462 * 02463 */ 02464 int32_t lsm6dso_aux_pw_on_ctrl_get(lsm6dso_ctx_t *ctx, lsm6dso_ois_on_t *val) 02465 { 02466 lsm6dso_ctrl7_g_t reg; 02467 int32_t ret; 02468 02469 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t*)®, 1); 02470 switch (reg.ois_on) { 02471 case LSM6DSO_AUX_ON: 02472 *val = LSM6DSO_AUX_ON; 02473 break; 02474 case LSM6DSO_AUX_ON_BY_AUX_INTERFACE: 02475 *val = LSM6DSO_AUX_ON_BY_AUX_INTERFACE; 02476 break; 02477 default: 02478 *val = LSM6DSO_AUX_ON; 02479 break; 02480 } 02481 02482 return ret; 02483 } 02484 02485 /** 02486 * @brief Accelerometer full-scale management between UI chain and 02487 * OIS chain. When XL UI is on, the full scale is the same 02488 * between UI/OIS and is chosen by the UI CTRL registers; 02489 * when XL UI is in PD, the OIS can choose the FS. 02490 * Full scales are independent between the UI/OIS chain 02491 * but both bound to 8 g.[set] 02492 * 02493 * @param ctx read / write interface definitions 02494 * @param val change the values of xl_fs_mode in 02495 * reg CTRL8_XL 02496 * 02497 */ 02498 int32_t lsm6dso_aux_xl_fs_mode_set(lsm6dso_ctx_t *ctx, 02499 lsm6dso_xl_fs_mode_t val) 02500 { 02501 lsm6dso_ctrl8_xl_t reg; 02502 int32_t ret; 02503 02504 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02505 if (ret == 0) { 02506 reg.xl_fs_mode = (uint8_t)val; 02507 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02508 } 02509 return ret; 02510 } 02511 02512 /** 02513 * @brief Accelerometer full-scale management between UI chain and 02514 * OIS chain. When XL UI is on, the full scale is the same 02515 * between UI/OIS and is chosen by the UI CTRL registers; 02516 * when XL UI is in PD, the OIS can choose the FS. 02517 * Full scales are independent between the UI/OIS chain 02518 * but both bound to 8 g.[get] 02519 * 02520 * @param ctx read / write interface definitions 02521 * @param val Get the values of xl_fs_mode in reg CTRL8_XL 02522 * 02523 */ 02524 int32_t lsm6dso_aux_xl_fs_mode_get(lsm6dso_ctx_t *ctx, 02525 lsm6dso_xl_fs_mode_t *val) 02526 { 02527 lsm6dso_ctrl8_xl_t reg; 02528 int32_t ret; 02529 02530 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t*)®, 1); 02531 switch (reg.xl_fs_mode) { 02532 case LSM6DSO_USE_SAME_XL_FS: 02533 *val = LSM6DSO_USE_SAME_XL_FS; 02534 break; 02535 case LSM6DSO_USE_DIFFERENT_XL_FS: 02536 *val = LSM6DSO_USE_DIFFERENT_XL_FS; 02537 break; 02538 default: 02539 *val = LSM6DSO_USE_SAME_XL_FS; 02540 break; 02541 } 02542 02543 return ret; 02544 } 02545 02546 /** 02547 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get] 02548 * 02549 * @param ctx read / write interface definitions 02550 * @param lsm6dso_status_spiaux_t: registers STATUS_SPIAUX 02551 * 02552 */ 02553 int32_t lsm6dso_aux_status_reg_get(lsm6dso_ctx_t *ctx, 02554 lsm6dso_status_spiaux_t *val) 02555 { 02556 int32_t ret; 02557 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*) val, 1); 02558 return ret; 02559 } 02560 02561 /** 02562 * @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available 02563 * 02564 * @param ctx read / write interface definitions 02565 * @param val change the values of xlda in reg STATUS_SPIAUX 02566 * 02567 */ 02568 int32_t lsm6dso_aux_xl_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02569 { 02570 lsm6dso_status_spiaux_t reg; 02571 int32_t ret; 02572 02573 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)®, 1); 02574 *val = reg.xlda; 02575 02576 return ret; 02577 } 02578 02579 /** 02580 * @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available. 02581 * 02582 * @param ctx read / write interface definitions 02583 * @param val change the values of gda in reg STATUS_SPIAUX 02584 * 02585 */ 02586 int32_t lsm6dso_aux_gy_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02587 { 02588 lsm6dso_status_spiaux_t reg; 02589 int32_t ret; 02590 02591 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)®, 1); 02592 *val = reg.gda; 02593 02594 return ret; 02595 } 02596 02597 /** 02598 * @brief High when the gyroscope output is in the settling phase.[get] 02599 * 02600 * @param ctx read / write interface definitions 02601 * @param val change the values of gyro_settling in reg STATUS_SPIAUX 02602 * 02603 */ 02604 int32_t lsm6dso_aux_gy_flag_settling_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02605 { 02606 lsm6dso_status_spiaux_t reg; 02607 int32_t ret; 02608 02609 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t*)®, 1); 02610 *val = reg.gyro_settling; 02611 02612 return ret; 02613 } 02614 02615 /** 02616 * @brief Selects accelerometer self-test. Effective only if XL OIS 02617 * chain is enabled.[set] 02618 * 02619 * @param ctx read / write interface definitions 02620 * @param val change the values of st_xl_ois in reg INT_OIS 02621 * 02622 */ 02623 int32_t lsm6dso_aux_xl_self_test_set(lsm6dso_ctx_t *ctx, 02624 lsm6dso_st_xl_ois_t val) 02625 { 02626 lsm6dso_int_ois_t reg; 02627 int32_t ret; 02628 02629 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1); 02630 if (ret == 0) { 02631 reg.st_xl_ois = (uint8_t)val; 02632 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1); 02633 } 02634 return ret; 02635 } 02636 02637 /** 02638 * @brief Selects accelerometer self-test. Effective only if XL OIS 02639 * chain is enabled.[get] 02640 * 02641 * @param ctx read / write interface definitions 02642 * @param val Get the values of st_xl_ois in reg INT_OIS 02643 * 02644 */ 02645 int32_t lsm6dso_aux_xl_self_test_get(lsm6dso_ctx_t *ctx, 02646 lsm6dso_st_xl_ois_t *val) 02647 { 02648 lsm6dso_int_ois_t reg; 02649 int32_t ret; 02650 02651 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1); 02652 switch (reg.st_xl_ois) { 02653 case LSM6DSO_AUX_XL_DISABLE: 02654 *val = LSM6DSO_AUX_XL_DISABLE; 02655 break; 02656 case LSM6DSO_AUX_XL_POS: 02657 *val = LSM6DSO_AUX_XL_POS; 02658 break; 02659 case LSM6DSO_AUX_XL_NEG: 02660 *val = LSM6DSO_AUX_XL_NEG; 02661 break; 02662 default: 02663 *val = LSM6DSO_AUX_XL_DISABLE; 02664 break; 02665 } 02666 return ret; 02667 } 02668 02669 /** 02670 * @brief Indicates polarity of DEN signal on OIS chain.[set] 02671 * 02672 * @param ctx read / write interface definitions 02673 * @param val change the values of den_lh_ois in 02674 * reg INT_OIS 02675 * 02676 */ 02677 int32_t lsm6dso_aux_den_polarity_set(lsm6dso_ctx_t *ctx, 02678 lsm6dso_den_lh_ois_t val) 02679 { 02680 lsm6dso_int_ois_t reg; 02681 int32_t ret; 02682 02683 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1); 02684 if (ret == 0) { 02685 reg.den_lh_ois = (uint8_t)val; 02686 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1); 02687 } 02688 return ret; 02689 } 02690 02691 /** 02692 * @brief Indicates polarity of DEN signal on OIS chain.[get] 02693 * 02694 * @param ctx read / write interface definitions 02695 * @param val Get the values of den_lh_ois in reg INT_OIS 02696 * 02697 */ 02698 int32_t lsm6dso_aux_den_polarity_get(lsm6dso_ctx_t *ctx, 02699 lsm6dso_den_lh_ois_t *val) 02700 { 02701 lsm6dso_int_ois_t reg; 02702 int32_t ret; 02703 02704 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1); 02705 switch (reg.den_lh_ois) { 02706 case LSM6DSO_AUX_DEN_ACTIVE_LOW: 02707 *val = LSM6DSO_AUX_DEN_ACTIVE_LOW; 02708 break; 02709 case LSM6DSO_AUX_DEN_ACTIVE_HIGH: 02710 *val = LSM6DSO_AUX_DEN_ACTIVE_HIGH; 02711 break; 02712 default: 02713 *val = LSM6DSO_AUX_DEN_ACTIVE_LOW; 02714 break; 02715 } 02716 return ret; 02717 } 02718 02719 /** 02720 * @brief Configure DEN mode on the OIS chain.[set] 02721 * 02722 * @param ctx read / write interface definitions 02723 * @param val change the values of lvl2_ois in reg INT_OIS 02724 * 02725 */ 02726 int32_t lsm6dso_aux_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_lvl2_ois_t val) 02727 { 02728 lsm6dso_ctrl1_ois_t ctrl1_ois; 02729 lsm6dso_int_ois_t int_ois; 02730 int32_t ret; 02731 02732 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1); 02733 if (ret == 0) { 02734 int_ois.lvl2_ois = (uint8_t)val & 0x01U; 02735 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1); 02736 } 02737 if (ret == 0) { 02738 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1); 02739 } 02740 if (ret == 0) { 02741 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1; 02742 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1); 02743 } 02744 return ret; 02745 } 02746 02747 /** 02748 * @brief Configure DEN mode on the OIS chain.[get] 02749 * 02750 * @param ctx read / write interface definitions 02751 * @param val Get the values of lvl2_ois in reg INT_OIS 02752 * 02753 */ 02754 int32_t lsm6dso_aux_den_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_lvl2_ois_t *val) 02755 { 02756 lsm6dso_ctrl1_ois_t ctrl1_ois; 02757 lsm6dso_int_ois_t int_ois; 02758 int32_t ret; 02759 02760 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*) &int_ois, 1); 02761 if (ret == 0) { 02762 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*) &ctrl1_ois, 1); 02763 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois) { 02764 case LSM6DSO_AUX_DEN_DISABLE: 02765 *val = LSM6DSO_AUX_DEN_DISABLE; 02766 break; 02767 case LSM6DSO_AUX_DEN_LEVEL_LATCH: 02768 *val = LSM6DSO_AUX_DEN_LEVEL_LATCH; 02769 break; 02770 case LSM6DSO_AUX_DEN_LEVEL_TRIG: 02771 *val = LSM6DSO_AUX_DEN_LEVEL_TRIG; 02772 break; 02773 default: 02774 *val = LSM6DSO_AUX_DEN_DISABLE; 02775 break; 02776 } 02777 } 02778 return ret; 02779 } 02780 02781 /** 02782 * @brief Enables/Disable OIS chain DRDY on INT2 pin. 02783 * This setting has priority over all other INT2 settings.[set] 02784 * 02785 * @param ctx read / write interface definitions 02786 * @param val change the values of int2_drdy_ois in reg INT_OIS 02787 * 02788 */ 02789 int32_t lsm6dso_aux_drdy_on_int2_set(lsm6dso_ctx_t *ctx, uint8_t val) 02790 { 02791 lsm6dso_int_ois_t reg; 02792 int32_t ret; 02793 02794 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1); 02795 if (ret == 0) { 02796 reg.int2_drdy_ois = val; 02797 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1); 02798 } 02799 return ret; 02800 } 02801 02802 /** 02803 * @brief Enables/Disable OIS chain DRDY on INT2 pin. 02804 * This setting has priority over all other INT2 settings.[get] 02805 * 02806 * @param ctx read / write interface definitions 02807 * @param val change the values of int2_drdy_ois in reg INT_OIS 02808 * 02809 */ 02810 int32_t lsm6dso_aux_drdy_on_int2_get(lsm6dso_ctx_t *ctx, uint8_t *val) 02811 { 02812 lsm6dso_int_ois_t reg; 02813 int32_t ret; 02814 02815 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t*)®, 1); 02816 *val = reg.int2_drdy_ois; 02817 02818 return ret; 02819 } 02820 02821 /** 02822 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4 02823 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1). 02824 * When the OIS chain is enabled, the OIS outputs are available 02825 * through the SPI2 in registers OUTX_L_G (22h) through 02826 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and 02827 * LPF1 is dedicated to this chain.[set] 02828 * 02829 * @param ctx read / write interface definitions 02830 * @param val change the values of ois_en_spi2 in 02831 * reg CTRL1_OIS 02832 * 02833 */ 02834 int32_t lsm6dso_aux_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ois_en_spi2_t val) 02835 { 02836 lsm6dso_ctrl1_ois_t reg; 02837 int32_t ret; 02838 02839 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1); 02840 if (ret == 0) { 02841 reg.ois_en_spi2 = (uint8_t)val & 0x01U; 02842 reg.mode4_en = ((uint8_t)val & 0x02U) >> 1; 02843 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1); 02844 } 02845 return ret; 02846 } 02847 02848 /** 02849 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4 02850 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1). 02851 * When the OIS chain is enabled, the OIS outputs are available 02852 * through the SPI2 in registers OUTX_L_G (22h) through 02853 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and 02854 * LPF1 is dedicated to this chain.[get] 02855 * 02856 * @param ctx read / write interface definitions 02857 * @param val Get the values of ois_en_spi2 in 02858 * reg CTRL1_OIS 02859 * 02860 */ 02861 int32_t lsm6dso_aux_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_ois_en_spi2_t *val) 02862 { 02863 lsm6dso_ctrl1_ois_t reg; 02864 int32_t ret; 02865 02866 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1); 02867 switch ((reg.mode4_en << 1) | reg.ois_en_spi2) { 02868 case LSM6DSO_AUX_DISABLE: 02869 *val = LSM6DSO_AUX_DISABLE; 02870 break; 02871 case LSM6DSO_MODE_3_GY: 02872 *val = LSM6DSO_MODE_3_GY; 02873 break; 02874 case LSM6DSO_MODE_4_GY_XL: 02875 *val = LSM6DSO_MODE_4_GY_XL; 02876 break; 02877 default: 02878 *val = LSM6DSO_AUX_DISABLE; 02879 break; 02880 } 02881 return ret; 02882 } 02883 02884 /** 02885 * @brief Selects gyroscope OIS chain full-scale.[set] 02886 * 02887 * @param ctx read / write interface definitions 02888 * @param val change the values of fs_g_ois in reg CTRL1_OIS 02889 * 02890 */ 02891 int32_t lsm6dso_aux_gy_full_scale_set(lsm6dso_ctx_t *ctx, 02892 lsm6dso_fs_g_ois_t val) 02893 { 02894 lsm6dso_ctrl1_ois_t reg; 02895 int32_t ret; 02896 02897 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1); 02898 if (ret == 0) { 02899 reg.fs_g_ois = (uint8_t)val; 02900 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1); 02901 } 02902 return ret; 02903 } 02904 02905 /** 02906 * @brief Selects gyroscope OIS chain full-scale.[get] 02907 * 02908 * @param ctx read / write interface definitions 02909 * @param val Get the values of fs_g_ois in reg CTRL1_OIS 02910 * 02911 */ 02912 int32_t lsm6dso_aux_gy_full_scale_get(lsm6dso_ctx_t *ctx, 02913 lsm6dso_fs_g_ois_t *val) 02914 { 02915 lsm6dso_ctrl1_ois_t reg; 02916 int32_t ret; 02917 02918 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1); 02919 switch (reg.fs_g_ois) { 02920 case LSM6DSO_250dps_AUX: 02921 *val = LSM6DSO_250dps_AUX; 02922 break; 02923 case LSM6DSO_125dps_AUX: 02924 *val = LSM6DSO_125dps_AUX; 02925 break; 02926 case LSM6DSO_500dps_AUX: 02927 *val = LSM6DSO_500dps_AUX; 02928 break; 02929 case LSM6DSO_1000dps_AUX: 02930 *val = LSM6DSO_1000dps_AUX; 02931 break; 02932 case LSM6DSO_2000dps_AUX: 02933 *val = LSM6DSO_2000dps_AUX; 02934 break; 02935 default: 02936 *val = LSM6DSO_250dps_AUX; 02937 break; 02938 } 02939 return ret; 02940 } 02941 02942 /** 02943 * @brief SPI2 3- or 4-wire interface.[set] 02944 * 02945 * @param ctx read / write interface definitions 02946 * @param val change the values of sim_ois in reg CTRL1_OIS 02947 * 02948 */ 02949 int32_t lsm6dso_aux_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_ois_t val) 02950 { 02951 lsm6dso_ctrl1_ois_t reg; 02952 int32_t ret; 02953 02954 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1); 02955 if (ret == 0) { 02956 reg.sim_ois = (uint8_t)val; 02957 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1); 02958 } 02959 return ret; 02960 } 02961 02962 /** 02963 * @brief SPI2 3- or 4-wire interface.[get] 02964 * 02965 * @param ctx read / write interface definitions 02966 * @param val Get the values of sim_ois in reg CTRL1_OIS 02967 * 02968 */ 02969 int32_t lsm6dso_aux_spi_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_sim_ois_t *val) 02970 { 02971 lsm6dso_ctrl1_ois_t reg; 02972 int32_t ret; 02973 02974 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t*)®, 1); 02975 switch (reg.sim_ois) { 02976 case LSM6DSO_AUX_SPI_4_WIRE: 02977 *val = LSM6DSO_AUX_SPI_4_WIRE; 02978 break; 02979 case LSM6DSO_AUX_SPI_3_WIRE: 02980 *val = LSM6DSO_AUX_SPI_3_WIRE; 02981 break; 02982 default: 02983 *val = LSM6DSO_AUX_SPI_4_WIRE; 02984 break; 02985 } 02986 return ret; 02987 } 02988 02989 /** 02990 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set] 02991 * 02992 * @param ctx read / write interface definitions 02993 * @param val change the values of ftype_ois in 02994 * reg CTRL2_OIS 02995 * 02996 */ 02997 int32_t lsm6dso_aux_gy_lp1_bandwidth_set(lsm6dso_ctx_t *ctx, 02998 lsm6dso_ftype_ois_t val) 02999 { 03000 lsm6dso_ctrl2_ois_t reg; 03001 int32_t ret; 03002 03003 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1); 03004 if (ret == 0) { 03005 reg.ftype_ois = (uint8_t)val; 03006 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1); 03007 } 03008 return ret; 03009 } 03010 03011 /** 03012 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get] 03013 * 03014 * @param ctx read / write interface definitions 03015 * @param val Get the values of ftype_ois in reg CTRL2_OIS 03016 * 03017 */ 03018 int32_t lsm6dso_aux_gy_lp1_bandwidth_get(lsm6dso_ctx_t *ctx, 03019 lsm6dso_ftype_ois_t *val) 03020 { 03021 lsm6dso_ctrl2_ois_t reg; 03022 int32_t ret; 03023 03024 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1); 03025 switch (reg.ftype_ois) { 03026 case LSM6DSO_351Hz39: 03027 *val = LSM6DSO_351Hz39; 03028 break; 03029 case LSM6DSO_236Hz63: 03030 *val = LSM6DSO_236Hz63; 03031 break; 03032 case LSM6DSO_172Hz70: 03033 *val = LSM6DSO_172Hz70; 03034 break; 03035 case LSM6DSO_937Hz91: 03036 *val = LSM6DSO_937Hz91; 03037 break; 03038 default: 03039 *val = LSM6DSO_351Hz39; 03040 break; 03041 } 03042 return ret; 03043 } 03044 03045 /** 03046 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set] 03047 * 03048 * @param ctx read / write interface definitions 03049 * @param val change the values of hpm_ois in reg CTRL2_OIS 03050 * 03051 */ 03052 int32_t lsm6dso_aux_gy_hp_bandwidth_set(lsm6dso_ctx_t *ctx, 03053 lsm6dso_hpm_ois_t val) 03054 { 03055 lsm6dso_ctrl2_ois_t reg; 03056 int32_t ret; 03057 03058 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1); 03059 if (ret == 0) { 03060 reg.hpm_ois = (uint8_t)val & 0x03U; 03061 reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4; 03062 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1); 03063 } 03064 return ret; 03065 } 03066 03067 /** 03068 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get] 03069 * 03070 * @param ctx read / write interface definitions 03071 * @param val Get the values of hpm_ois in reg CTRL2_OIS 03072 * 03073 */ 03074 int32_t lsm6dso_aux_gy_hp_bandwidth_get(lsm6dso_ctx_t *ctx, 03075 lsm6dso_hpm_ois_t *val) 03076 { 03077 lsm6dso_ctrl2_ois_t reg; 03078 int32_t ret; 03079 03080 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t*)®, 1); 03081 switch ((reg.hp_en_ois << 4) | reg.hpm_ois) { 03082 case LSM6DSO_AUX_HP_DISABLE: 03083 *val = LSM6DSO_AUX_HP_DISABLE; 03084 break; 03085 case LSM6DSO_AUX_HP_Hz016: 03086 *val = LSM6DSO_AUX_HP_Hz016; 03087 break; 03088 case LSM6DSO_AUX_HP_Hz065: 03089 *val = LSM6DSO_AUX_HP_Hz065; 03090 break; 03091 case LSM6DSO_AUX_HP_Hz260: 03092 *val = LSM6DSO_AUX_HP_Hz260; 03093 break; 03094 case LSM6DSO_AUX_HP_1Hz040: 03095 *val = LSM6DSO_AUX_HP_1Hz040; 03096 break; 03097 default: 03098 *val = LSM6DSO_AUX_HP_DISABLE; 03099 break; 03100 } 03101 return ret; 03102 } 03103 03104 /** 03105 * @brief Enable / Disables OIS chain clamp. 03106 * Enable: All OIS chain outputs = 8000h 03107 * during self-test; Disable: OIS chain self-test 03108 * outputs dependent from the aux gyro full 03109 * scale selected.[set] 03110 * 03111 * @param ctx read / write interface definitions 03112 * @param val change the values of st_ois_clampdis in 03113 * reg CTRL3_OIS 03114 * 03115 */ 03116 int32_t lsm6dso_aux_gy_clamp_set(lsm6dso_ctx_t *ctx, 03117 lsm6dso_st_ois_clampdis_t val) 03118 { 03119 lsm6dso_ctrl3_ois_t reg; 03120 int32_t ret; 03121 03122 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03123 if (ret == 0) { 03124 reg.st_ois_clampdis = (uint8_t)val; 03125 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03126 } 03127 return ret; 03128 } 03129 03130 /** 03131 * @brief Enable / Disables OIS chain clamp. 03132 * Enable: All OIS chain outputs = 8000h 03133 * during self-test; Disable: OIS chain self-test 03134 * outputs dependent from the aux gyro full 03135 * scale selected.[set] 03136 * 03137 * @param ctx read / write interface definitions 03138 * @param val Get the values of st_ois_clampdis in 03139 * reg CTRL3_OIS 03140 * 03141 */ 03142 int32_t lsm6dso_aux_gy_clamp_get(lsm6dso_ctx_t *ctx, 03143 lsm6dso_st_ois_clampdis_t *val) 03144 { 03145 lsm6dso_ctrl3_ois_t reg; 03146 int32_t ret; 03147 03148 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03149 switch (reg.st_ois_clampdis) { 03150 case LSM6DSO_ENABLE_CLAMP: 03151 *val = LSM6DSO_ENABLE_CLAMP; 03152 break; 03153 case LSM6DSO_DISABLE_CLAMP: 03154 *val = LSM6DSO_DISABLE_CLAMP; 03155 break; 03156 default: 03157 *val = LSM6DSO_ENABLE_CLAMP; 03158 break; 03159 } 03160 return ret; 03161 } 03162 03163 /** 03164 * @brief Selects gyroscope OIS chain self-test.[set] 03165 * 03166 * @param ctx read / write interface definitions 03167 * @param val change the values of st_ois in reg CTRL3_OIS 03168 * 03169 */ 03170 int32_t lsm6dso_aux_gy_self_test_set(lsm6dso_ctx_t *ctx, lsm6dso_st_ois_t val) 03171 { 03172 lsm6dso_ctrl3_ois_t reg; 03173 int32_t ret; 03174 03175 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03176 if (ret == 0) { 03177 reg.st_ois = (uint8_t)val; 03178 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03179 } 03180 return ret; 03181 } 03182 03183 /** 03184 * @brief Selects gyroscope OIS chain self-test.[get] 03185 * 03186 * @param ctx read / write interface definitions 03187 * @param val Get the values of st_ois in reg CTRL3_OIS 03188 * 03189 */ 03190 int32_t lsm6dso_aux_gy_self_test_get(lsm6dso_ctx_t *ctx, lsm6dso_st_ois_t *val) 03191 { 03192 lsm6dso_ctrl3_ois_t reg; 03193 int32_t ret; 03194 03195 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03196 switch (reg.st_ois) { 03197 case LSM6DSO_AUX_GY_DISABLE: 03198 *val = LSM6DSO_AUX_GY_DISABLE; 03199 break; 03200 case LSM6DSO_AUX_GY_POS: 03201 *val = LSM6DSO_AUX_GY_POS; 03202 break; 03203 case LSM6DSO_AUX_GY_NEG: 03204 *val = LSM6DSO_AUX_GY_NEG; 03205 break; 03206 default: 03207 *val = LSM6DSO_AUX_GY_DISABLE; 03208 break; 03209 } 03210 return ret; 03211 } 03212 03213 /** 03214 * @brief Selects accelerometer OIS channel bandwidth.[set] 03215 * 03216 * @param ctx read / write interface definitions 03217 * @param val change the values of 03218 * filter_xl_conf_ois in reg CTRL3_OIS 03219 * 03220 */ 03221 int32_t lsm6dso_aux_xl_bandwidth_set(lsm6dso_ctx_t *ctx, 03222 lsm6dso_filter_xl_conf_ois_t val) 03223 { 03224 lsm6dso_ctrl3_ois_t reg; 03225 int32_t ret; 03226 03227 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03228 if (ret == 0) { 03229 reg.filter_xl_conf_ois = (uint8_t)val; 03230 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03231 } 03232 return ret; 03233 } 03234 03235 /** 03236 * @brief Selects accelerometer OIS channel bandwidth.[get] 03237 * 03238 * @param ctx read / write interface definitions 03239 * @param val Get the values of 03240 * filter_xl_conf_ois in reg CTRL3_OIS 03241 * 03242 */ 03243 int32_t lsm6dso_aux_xl_bandwidth_get(lsm6dso_ctx_t *ctx, 03244 lsm6dso_filter_xl_conf_ois_t *val) 03245 { 03246 lsm6dso_ctrl3_ois_t reg; 03247 int32_t ret; 03248 03249 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03250 03251 switch (reg.filter_xl_conf_ois) { 03252 case LSM6DSO_289Hz: 03253 *val = LSM6DSO_289Hz; 03254 break; 03255 case LSM6DSO_258Hz: 03256 *val = LSM6DSO_258Hz; 03257 break; 03258 case LSM6DSO_120Hz: 03259 *val = LSM6DSO_120Hz; 03260 break; 03261 case LSM6DSO_65Hz2: 03262 *val = LSM6DSO_65Hz2; 03263 break; 03264 case LSM6DSO_33Hz2: 03265 *val = LSM6DSO_33Hz2; 03266 break; 03267 case LSM6DSO_16Hz6: 03268 *val = LSM6DSO_16Hz6; 03269 break; 03270 case LSM6DSO_8Hz30: 03271 *val = LSM6DSO_8Hz30; 03272 break; 03273 case LSM6DSO_4Hz15: 03274 *val = LSM6DSO_4Hz15; 03275 break; 03276 default: 03277 *val = LSM6DSO_289Hz; 03278 break; 03279 } 03280 return ret; 03281 } 03282 03283 /** 03284 * @brief Selects accelerometer OIS channel full-scale.[set] 03285 * 03286 * @param ctx read / write interface definitions 03287 * @param val change the values of fs_xl_ois in 03288 * reg CTRL3_OIS 03289 * 03290 */ 03291 int32_t lsm6dso_aux_xl_full_scale_set(lsm6dso_ctx_t *ctx, 03292 lsm6dso_fs_xl_ois_t val) 03293 { 03294 lsm6dso_ctrl3_ois_t reg; 03295 int32_t ret; 03296 03297 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03298 if (ret == 0) { 03299 reg.fs_xl_ois = (uint8_t)val; 03300 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03301 } 03302 return ret; 03303 } 03304 03305 /** 03306 * @brief Selects accelerometer OIS channel full-scale.[get] 03307 * 03308 * @param ctx read / write interface definitions 03309 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS 03310 * 03311 */ 03312 int32_t lsm6dso_aux_xl_full_scale_get(lsm6dso_ctx_t *ctx, 03313 lsm6dso_fs_xl_ois_t *val) 03314 { 03315 lsm6dso_ctrl3_ois_t reg; 03316 int32_t ret; 03317 03318 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t*)®, 1); 03319 switch (reg.fs_xl_ois) { 03320 case LSM6DSO_AUX_2g: 03321 *val = LSM6DSO_AUX_2g; 03322 break; 03323 case LSM6DSO_AUX_16g: 03324 *val = LSM6DSO_AUX_16g; 03325 break; 03326 case LSM6DSO_AUX_4g: 03327 *val = LSM6DSO_AUX_4g; 03328 break; 03329 case LSM6DSO_AUX_8g: 03330 *val = LSM6DSO_AUX_8g; 03331 break; 03332 default: 03333 *val = LSM6DSO_AUX_2g; 03334 break; 03335 } 03336 return ret; 03337 } 03338 03339 /** 03340 * @} 03341 * 03342 */ 03343 03344 /** 03345 * @defgroup LSM6DSO_ main_serial_interface 03346 * @brief This section groups all the functions concerning main 03347 * serial interface management (not auxiliary) 03348 * @{ 03349 * 03350 */ 03351 03352 /** 03353 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set] 03354 * 03355 * @param ctx read / write interface definitions 03356 * @param val change the values of sdo_pu_en in 03357 * reg PIN_CTRL 03358 * 03359 */ 03360 int32_t lsm6dso_sdo_sa0_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sdo_pu_en_t val) 03361 { 03362 lsm6dso_pin_ctrl_t reg; 03363 int32_t ret; 03364 03365 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1); 03366 if (ret == 0) { 03367 reg.sdo_pu_en = (uint8_t)val; 03368 ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1); 03369 } 03370 return ret; 03371 } 03372 03373 /** 03374 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get] 03375 * 03376 * @param ctx read / write interface definitions 03377 * @param val Get the values of sdo_pu_en in reg PIN_CTRL 03378 * 03379 */ 03380 int32_t lsm6dso_sdo_sa0_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_sdo_pu_en_t *val) 03381 { 03382 lsm6dso_pin_ctrl_t reg; 03383 int32_t ret; 03384 03385 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)®, 1); 03386 switch (reg.sdo_pu_en) { 03387 case LSM6DSO_PULL_UP_DISC: 03388 *val = LSM6DSO_PULL_UP_DISC; 03389 break; 03390 case LSM6DSO_PULL_UP_CONNECT: 03391 *val = LSM6DSO_PULL_UP_CONNECT; 03392 break; 03393 default: 03394 *val = LSM6DSO_PULL_UP_DISC; 03395 break; 03396 } 03397 return ret; 03398 } 03399 03400 /** 03401 * @brief SPI Serial Interface Mode selection.[set] 03402 * 03403 * @param ctx read / write interface definitions 03404 * @param val change the values of sim in reg CTRL3_C 03405 * 03406 */ 03407 int32_t lsm6dso_spi_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_sim_t val) 03408 { 03409 lsm6dso_ctrl3_c_t reg; 03410 int32_t ret; 03411 03412 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 03413 if (ret == 0) { 03414 reg.sim = (uint8_t)val; 03415 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 03416 } 03417 return ret; 03418 } 03419 03420 /** 03421 * @brief SPI Serial Interface Mode selection.[get] 03422 * 03423 * @param ctx read / write interface definitions 03424 * @param val Get the values of sim in reg CTRL3_C 03425 * 03426 */ 03427 int32_t lsm6dso_spi_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_sim_t *val) 03428 { 03429 lsm6dso_ctrl3_c_t reg; 03430 int32_t ret; 03431 03432 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 03433 switch (reg.sim) { 03434 case LSM6DSO_SPI_4_WIRE: 03435 *val = LSM6DSO_SPI_4_WIRE; 03436 break; 03437 case LSM6DSO_SPI_3_WIRE: 03438 *val = LSM6DSO_SPI_3_WIRE; 03439 break; 03440 default: 03441 *val = LSM6DSO_SPI_4_WIRE; 03442 break; 03443 } 03444 return ret; 03445 } 03446 03447 /** 03448 * @brief Disable / Enable I2C interface.[set] 03449 * 03450 * @param ctx read / write interface definitions 03451 * @param val change the values of i2c_disable in 03452 * reg CTRL4_C 03453 * 03454 */ 03455 int32_t lsm6dso_i2c_interface_set(lsm6dso_ctx_t *ctx, 03456 lsm6dso_i2c_disable_t val) 03457 { 03458 lsm6dso_ctrl4_c_t reg; 03459 int32_t ret; 03460 03461 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 03462 if (ret == 0) { 03463 reg.i2c_disable = (uint8_t)val; 03464 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 03465 } 03466 return ret; 03467 } 03468 03469 /** 03470 * @brief Disable / Enable I2C interface.[get] 03471 * 03472 * @param ctx read / write interface definitions 03473 * @param val Get the values of i2c_disable in 03474 * reg CTRL4_C 03475 * 03476 */ 03477 int32_t lsm6dso_i2c_interface_get(lsm6dso_ctx_t *ctx, 03478 lsm6dso_i2c_disable_t *val) 03479 { 03480 lsm6dso_ctrl4_c_t reg; 03481 int32_t ret; 03482 03483 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 03484 switch (reg.i2c_disable) { 03485 case LSM6DSO_I2C_ENABLE: 03486 *val = LSM6DSO_I2C_ENABLE; 03487 break; 03488 case LSM6DSO_I2C_DISABLE: 03489 *val = LSM6DSO_I2C_DISABLE; 03490 break; 03491 default: 03492 *val = LSM6DSO_I2C_ENABLE; 03493 break; 03494 } 03495 return ret; 03496 } 03497 03498 /** 03499 * @brief I3C Enable/Disable communication protocol[.set] 03500 * 03501 * @param ctx read / write interface definitions 03502 * @param val change the values of i3c_disable 03503 * in reg CTRL9_XL 03504 * 03505 */ 03506 int32_t lsm6dso_i3c_disable_set(lsm6dso_ctx_t *ctx, lsm6dso_i3c_disable_t val) 03507 { 03508 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 03509 lsm6dso_ctrl9_xl_t ctrl9_xl; 03510 int32_t ret; 03511 03512 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); 03513 if (ret == 0) { 03514 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7; 03515 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); 03516 } 03517 if (ret == 0) { 03518 03519 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, 03520 (uint8_t*)&i3c_bus_avb, 1); 03521 } 03522 if (ret == 0) { 03523 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U; 03524 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, 03525 (uint8_t*)&i3c_bus_avb, 1); 03526 } 03527 03528 return ret; 03529 } 03530 03531 /** 03532 * @brief I3C Enable/Disable communication protocol.[get] 03533 * 03534 * @param ctx read / write interface definitions 03535 * @param val change the values of i3c_disable in 03536 * reg CTRL9_XL 03537 * 03538 */ 03539 int32_t lsm6dso_i3c_disable_get(lsm6dso_ctx_t *ctx, lsm6dso_i3c_disable_t *val) 03540 { 03541 lsm6dso_ctrl9_xl_t ctrl9_xl; 03542 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 03543 int32_t ret; 03544 03545 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)&ctrl9_xl, 1); 03546 if (ret == 0) { 03547 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, 03548 (uint8_t*)&i3c_bus_avb, 1); 03549 03550 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel) { 03551 case LSM6DSO_I3C_DISABLE: 03552 *val = LSM6DSO_I3C_DISABLE; 03553 break; 03554 case LSM6DSO_I3C_ENABLE_T_50us: 03555 *val = LSM6DSO_I3C_ENABLE_T_50us; 03556 break; 03557 case LSM6DSO_I3C_ENABLE_T_2us: 03558 *val = LSM6DSO_I3C_ENABLE_T_2us; 03559 break; 03560 case LSM6DSO_I3C_ENABLE_T_1ms: 03561 *val = LSM6DSO_I3C_ENABLE_T_1ms; 03562 break; 03563 case LSM6DSO_I3C_ENABLE_T_25ms: 03564 *val = LSM6DSO_I3C_ENABLE_T_25ms; 03565 break; 03566 default: 03567 *val = LSM6DSO_I3C_DISABLE; 03568 break; 03569 } 03570 } 03571 return ret; 03572 } 03573 03574 /** 03575 * @} 03576 * 03577 */ 03578 03579 /** 03580 * @defgroup LSM6DSO_interrupt_pins 03581 * @brief This section groups all the functions that manage interrup pins 03582 * @{ 03583 * 03584 */ 03585 03586 /** 03587 * @brief Connect/Disconnect INT1 internal pull-down.[set] 03588 * 03589 * @param ctx read / write interface definitions 03590 * @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB 03591 * 03592 */ 03593 int32_t lsm6dso_int1_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_int1_pd_en_t val) 03594 { 03595 lsm6dso_i3c_bus_avb_t reg; 03596 int32_t ret; 03597 03598 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)®, 1); 03599 if (ret == 0) { 03600 reg.pd_dis_int1 = (uint8_t)val; 03601 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)®, 1); 03602 } 03603 return ret; 03604 } 03605 03606 /** 03607 * @brief Connect/Disconnect INT1 internal pull-down.[get] 03608 * 03609 * @param ctx read / write interface definitions 03610 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB 03611 * 03612 */ 03613 int32_t lsm6dso_int1_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_int1_pd_en_t *val) 03614 { 03615 lsm6dso_i3c_bus_avb_t reg; 03616 int32_t ret; 03617 03618 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t*)®, 1); 03619 switch (reg.pd_dis_int1) { 03620 case LSM6DSO_PULL_DOWN_DISC: 03621 *val = LSM6DSO_PULL_DOWN_DISC; 03622 break; 03623 case LSM6DSO_PULL_DOWN_CONNECT: 03624 *val = LSM6DSO_PULL_DOWN_CONNECT; 03625 break; 03626 default: 03627 *val = LSM6DSO_PULL_DOWN_DISC; 03628 break; 03629 } 03630 return ret; 03631 } 03632 03633 /** 03634 * @brief Push-pull/open drain selection on interrupt pads.[set] 03635 * 03636 * @param ctx read / write interface definitions 03637 * @param val change the values of pp_od in reg CTRL3_C 03638 * 03639 */ 03640 int32_t lsm6dso_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_pp_od_t val) 03641 { 03642 lsm6dso_ctrl3_c_t reg; 03643 int32_t ret; 03644 03645 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 03646 if (ret == 0) { 03647 reg.pp_od = (uint8_t)val; 03648 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 03649 } 03650 return ret; 03651 } 03652 03653 /** 03654 * @brief Push-pull/open drain selection on interrupt pads.[get] 03655 * 03656 * @param ctx read / write interface definitions 03657 * @param val Get the values of pp_od in reg CTRL3_C 03658 * 03659 */ 03660 int32_t lsm6dso_pin_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_pp_od_t *val) 03661 { 03662 lsm6dso_ctrl3_c_t reg; 03663 int32_t ret; 03664 03665 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 03666 03667 switch (reg.pp_od) { 03668 case LSM6DSO_PUSH_PULL: 03669 *val = LSM6DSO_PUSH_PULL; 03670 break; 03671 case LSM6DSO_OPEN_DRAIN: 03672 *val = LSM6DSO_OPEN_DRAIN; 03673 break; 03674 default: 03675 *val = LSM6DSO_PUSH_PULL; 03676 break; 03677 } 03678 return ret; 03679 } 03680 03681 /** 03682 * @brief Interrupt active-high/low.[set] 03683 * 03684 * @param ctx read / write interface definitions 03685 * @param val change the values of h_lactive in reg CTRL3_C 03686 * 03687 */ 03688 int32_t lsm6dso_pin_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_h_lactive_t val) 03689 { 03690 lsm6dso_ctrl3_c_t reg; 03691 int32_t ret; 03692 03693 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 03694 if (ret == 0) { 03695 reg.h_lactive = (uint8_t)val; 03696 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 03697 } 03698 03699 return ret; 03700 } 03701 03702 /** 03703 * @brief Interrupt active-high/low.[get] 03704 * 03705 * @param ctx read / write interface definitions 03706 * @param val Get the values of h_lactive in reg CTRL3_C 03707 * 03708 */ 03709 int32_t lsm6dso_pin_polarity_get(lsm6dso_ctx_t *ctx, lsm6dso_h_lactive_t *val) 03710 { 03711 lsm6dso_ctrl3_c_t reg; 03712 int32_t ret; 03713 03714 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)®, 1); 03715 03716 switch (reg.h_lactive) { 03717 case LSM6DSO_ACTIVE_HIGH: 03718 *val = LSM6DSO_ACTIVE_HIGH; 03719 break; 03720 case LSM6DSO_ACTIVE_LOW: 03721 *val = LSM6DSO_ACTIVE_LOW; 03722 break; 03723 default: 03724 *val = LSM6DSO_ACTIVE_HIGH; 03725 break; 03726 } 03727 return ret; 03728 } 03729 03730 /** 03731 * @brief All interrupt signals become available on INT1 pin.[set] 03732 * 03733 * @param ctx read / write interface definitions 03734 * @param val change the values of int2_on_int1 in reg CTRL4_C 03735 * 03736 */ 03737 int32_t lsm6dso_all_on_int1_set(lsm6dso_ctx_t *ctx, uint8_t val) 03738 { 03739 lsm6dso_ctrl4_c_t reg; 03740 int32_t ret; 03741 03742 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 03743 if (ret == 0) { 03744 reg.int2_on_int1 = val; 03745 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 03746 } 03747 03748 return ret; 03749 } 03750 03751 /** 03752 * @brief All interrupt signals become available on INT1 pin.[get] 03753 * 03754 * @param ctx read / write interface definitions 03755 * @param val change the values of int2_on_int1 in reg CTRL4_C 03756 * 03757 */ 03758 int32_t lsm6dso_all_on_int1_get(lsm6dso_ctx_t *ctx, uint8_t *val) 03759 { 03760 lsm6dso_ctrl4_c_t reg; 03761 int32_t ret; 03762 03763 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 03764 *val = reg.int2_on_int1; 03765 03766 return ret; 03767 } 03768 03769 /** 03770 * @brief Interrupt notification mode.[set] 03771 * 03772 * @param ctx read / write interface definitions 03773 * @param val change the values of lir in reg TAP_CFG0 03774 * 03775 */ 03776 int32_t lsm6dso_int_notification_set(lsm6dso_ctx_t *ctx, lsm6dso_lir_t val) 03777 { 03778 lsm6dso_tap_cfg0_t tap_cfg0; 03779 lsm6dso_page_rw_t page_rw; 03780 int32_t ret; 03781 03782 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 03783 if (ret == 0) { 03784 tap_cfg0.lir = (uint8_t)val & 0x01U; 03785 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U; 03786 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 03787 } 03788 if (ret == 0) { 03789 03790 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 03791 } 03792 if (ret == 0) { 03793 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 03794 } 03795 if (ret == 0) { 03796 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1; 03797 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 03798 } 03799 if (ret == 0) { 03800 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 03801 } 03802 03803 return ret; 03804 } 03805 03806 /** 03807 * @brief Interrupt notification mode.[get] 03808 * 03809 * @param ctx read / write interface definitions 03810 * @param val Get the values of lir in reg TAP_CFG0 03811 * 03812 */ 03813 int32_t lsm6dso_int_notification_get(lsm6dso_ctx_t *ctx, lsm6dso_lir_t *val) 03814 { 03815 lsm6dso_tap_cfg0_t tap_cfg0; 03816 lsm6dso_page_rw_t page_rw; 03817 int32_t ret; 03818 03819 03820 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 03821 if (ret == 0) { 03822 03823 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 03824 } 03825 if (ret == 0) { 03826 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 03827 } 03828 if (ret == 0) { 03829 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 03830 } 03831 if (ret == 0) { 03832 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir) { 03833 case LSM6DSO_ALL_INT_PULSED: 03834 *val = LSM6DSO_ALL_INT_PULSED; 03835 break; 03836 case LSM6DSO_BASE_LATCHED_EMB_PULSED: 03837 *val = LSM6DSO_BASE_LATCHED_EMB_PULSED; 03838 break; 03839 case LSM6DSO_BASE_PULSED_EMB_LATCHED: 03840 *val = LSM6DSO_BASE_PULSED_EMB_LATCHED; 03841 break; 03842 case LSM6DSO_ALL_INT_LATCHED: 03843 *val = LSM6DSO_ALL_INT_LATCHED; 03844 break; 03845 default: 03846 *val = LSM6DSO_ALL_INT_PULSED; 03847 break; 03848 } 03849 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 03850 } 03851 if (ret == 0) { 03852 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 03853 } 03854 if (ret == 0) { 03855 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 03856 } 03857 03858 return ret; 03859 } 03860 03861 /** 03862 * @} 03863 * 03864 */ 03865 03866 /** 03867 * @defgroup LSM6DSO_Wake_Up_event 03868 * @brief This section groups all the functions that manage the Wake Up 03869 * event generation. 03870 * @{ 03871 * 03872 */ 03873 03874 /** 03875 * @brief Weight of 1 LSB of wakeup threshold.[set] 03876 * 0: 1 LSB =FS_XL / 64 03877 * 1: 1 LSB = FS_XL / 256 03878 * 03879 * @param ctx read / write interface definitions 03880 * @param val change the values of wake_ths_w in 03881 * reg WAKE_UP_DUR 03882 * 03883 */ 03884 int32_t lsm6dso_wkup_ths_weight_set(lsm6dso_ctx_t *ctx, 03885 lsm6dso_wake_ths_w_t val) 03886 { 03887 lsm6dso_wake_up_dur_t reg; 03888 int32_t ret; 03889 03890 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1); 03891 if (ret == 0) { 03892 reg.wake_ths_w = (uint8_t)val; 03893 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1); 03894 } 03895 return ret; 03896 } 03897 03898 /** 03899 * @brief Weight of 1 LSB of wakeup threshold.[get] 03900 * 0: 1 LSB =FS_XL / 64 03901 * 1: 1 LSB = FS_XL / 256 03902 * 03903 * @param ctx read / write interface definitions 03904 * @param val Get the values of wake_ths_w in 03905 * reg WAKE_UP_DUR 03906 * 03907 */ 03908 int32_t lsm6dso_wkup_ths_weight_get(lsm6dso_ctx_t *ctx, 03909 lsm6dso_wake_ths_w_t *val) 03910 { 03911 lsm6dso_wake_up_dur_t reg; 03912 int32_t ret; 03913 03914 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1); 03915 03916 switch (reg.wake_ths_w) { 03917 case LSM6DSO_LSb_FS_DIV_64: 03918 *val = LSM6DSO_LSb_FS_DIV_64; 03919 break; 03920 case LSM6DSO_LSb_FS_DIV_256: 03921 *val = LSM6DSO_LSb_FS_DIV_256; 03922 break; 03923 default: 03924 *val = LSM6DSO_LSb_FS_DIV_64; 03925 break; 03926 } 03927 return ret; 03928 } 03929 03930 /** 03931 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in 03932 * WAKE_UP_DUR.[set] 03933 * 03934 * @param ctx read / write interface definitions 03935 * @param val change the values of wk_ths in reg WAKE_UP_THS 03936 * 03937 */ 03938 int32_t lsm6dso_wkup_threshold_set(lsm6dso_ctx_t *ctx, uint8_t val) 03939 { 03940 lsm6dso_wake_up_ths_t reg; 03941 int32_t ret; 03942 03943 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1); 03944 if (ret == 0) { 03945 reg.wk_ths = val; 03946 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1); 03947 } 03948 return ret; 03949 } 03950 03951 /** 03952 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in 03953 * WAKE_UP_DUR.[get] 03954 * 03955 * @param ctx read / write interface definitions 03956 * @param val change the values of wk_ths in reg WAKE_UP_THS 03957 * 03958 */ 03959 int32_t lsm6dso_wkup_threshold_get(lsm6dso_ctx_t *ctx, uint8_t *val) 03960 { 03961 lsm6dso_wake_up_ths_t reg; 03962 int32_t ret; 03963 03964 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1); 03965 *val = reg.wk_ths; 03966 03967 return ret; 03968 } 03969 03970 /** 03971 * @brief Wake up duration event.[set] 03972 * 1LSb = 1 / ODR 03973 * 03974 * @param ctx read / write interface definitions 03975 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS 03976 * 03977 */ 03978 int32_t lsm6dso_xl_usr_offset_on_wkup_set(lsm6dso_ctx_t *ctx, uint8_t val) 03979 { 03980 lsm6dso_wake_up_ths_t reg; 03981 int32_t ret; 03982 03983 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1); 03984 if (ret == 0) { 03985 reg.usr_off_on_wu = val; 03986 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1); 03987 } 03988 return ret; 03989 } 03990 03991 /** 03992 * @brief Wake up duration event.[get] 03993 * 1LSb = 1 / ODR 03994 * 03995 * @param ctx read / write interface definitions 03996 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS 03997 * 03998 */ 03999 int32_t lsm6dso_xl_usr_offset_on_wkup_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04000 { 04001 lsm6dso_wake_up_ths_t reg; 04002 int32_t ret; 04003 04004 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1); 04005 *val = reg.usr_off_on_wu; 04006 04007 return ret; 04008 } 04009 04010 /** 04011 * @brief Wake up duration event.[set] 04012 * 1LSb = 1 / ODR 04013 * 04014 * @param ctx read / write interface definitions 04015 * @param val change the values of wake_dur in reg WAKE_UP_DUR 04016 * 04017 */ 04018 int32_t lsm6dso_wkup_dur_set(lsm6dso_ctx_t *ctx, uint8_t val) 04019 { 04020 lsm6dso_wake_up_dur_t reg; 04021 int32_t ret; 04022 04023 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1); 04024 if (ret == 0) { 04025 reg.wake_dur = val; 04026 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1); 04027 } 04028 return ret; 04029 } 04030 04031 /** 04032 * @brief Wake up duration event.[get] 04033 * 1LSb = 1 / ODR 04034 * 04035 * @param ctx read / write interface definitions 04036 * @param val change the values of wake_dur in reg WAKE_UP_DUR 04037 * 04038 */ 04039 int32_t lsm6dso_wkup_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04040 { 04041 lsm6dso_wake_up_dur_t reg; 04042 int32_t ret; 04043 04044 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1); 04045 *val = reg.wake_dur; 04046 04047 return ret; 04048 } 04049 04050 /** 04051 * @} 04052 * 04053 */ 04054 04055 /** 04056 * @defgroup LSM6DSO_ Activity/Inactivity_detection 04057 * @brief This section groups all the functions concerning 04058 * activity/inactivity detection. 04059 * @{ 04060 * 04061 */ 04062 04063 /** 04064 * @brief Enables gyroscope Sleep mode.[set] 04065 * 04066 * @param ctx read / write interface definitions 04067 * @param val change the values of sleep_g in reg CTRL4_C 04068 * 04069 */ 04070 int32_t lsm6dso_gy_sleep_mode_set(lsm6dso_ctx_t *ctx, uint8_t val) 04071 { 04072 lsm6dso_ctrl4_c_t reg; 04073 int32_t ret; 04074 04075 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 04076 if (ret == 0) { 04077 reg.sleep_g = val; 04078 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 04079 } 04080 return ret; 04081 } 04082 04083 /** 04084 * @brief Enables gyroscope Sleep mode.[get] 04085 * 04086 * @param ctx read / write interface definitions 04087 * @param val change the values of sleep_g in reg CTRL4_C 04088 * 04089 */ 04090 int32_t lsm6dso_gy_sleep_mode_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04091 { 04092 lsm6dso_ctrl4_c_t reg; 04093 int32_t ret; 04094 04095 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)®, 1); 04096 *val = reg.sleep_g; 04097 04098 return ret; 04099 } 04100 04101 /** 04102 * @brief Drives the sleep status instead of 04103 * sleep change on INT pins 04104 * (only if INT1_SLEEP_CHANGE or 04105 * INT2_SLEEP_CHANGE bits are enabled).[set] 04106 * 04107 * @param ctx read / write interface definitions 04108 * @param val change the values of sleep_status_on_int in reg TAP_CFG0 04109 * 04110 */ 04111 int32_t lsm6dso_act_pin_notification_set(lsm6dso_ctx_t *ctx, 04112 lsm6dso_sleep_status_on_int_t val) 04113 { 04114 lsm6dso_tap_cfg0_t reg; 04115 int32_t ret; 04116 04117 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04118 if (ret == 0) { 04119 reg.sleep_status_on_int = (uint8_t)val; 04120 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04121 } 04122 return ret; 04123 } 04124 04125 /** 04126 * @brief Drives the sleep status instead of 04127 * sleep change on INT pins (only if 04128 * INT1_SLEEP_CHANGE or 04129 * INT2_SLEEP_CHANGE bits are enabled).[get] 04130 * 04131 * @param ctx read / write interface definitions 04132 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0 04133 * 04134 */ 04135 int32_t lsm6dso_act_pin_notification_get(lsm6dso_ctx_t *ctx, 04136 lsm6dso_sleep_status_on_int_t *val) 04137 { 04138 lsm6dso_tap_cfg0_t reg; 04139 int32_t ret; 04140 04141 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04142 switch (reg.sleep_status_on_int) { 04143 case LSM6DSO_DRIVE_SLEEP_CHG_EVENT: 04144 *val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT; 04145 break; 04146 case LSM6DSO_DRIVE_SLEEP_STATUS: 04147 *val = LSM6DSO_DRIVE_SLEEP_STATUS; 04148 break; 04149 default: 04150 *val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT; 04151 break; 04152 } 04153 return ret; 04154 } 04155 04156 /** 04157 * @brief Enable inactivity function.[set] 04158 * 04159 * @param ctx read / write interface definitions 04160 * @param val change the values of inact_en in reg TAP_CFG2 04161 * 04162 */ 04163 int32_t lsm6dso_act_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_inact_en_t val) 04164 { 04165 lsm6dso_tap_cfg2_t reg; 04166 int32_t ret; 04167 04168 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1); 04169 if (ret == 0) { 04170 reg.inact_en = (uint8_t)val; 04171 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1); 04172 } 04173 return ret; 04174 } 04175 04176 /** 04177 * @brief Enable inactivity function.[get] 04178 * 04179 * @param ctx read / write interface definitions 04180 * @param val Get the values of inact_en in reg TAP_CFG2 04181 * 04182 */ 04183 int32_t lsm6dso_act_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_inact_en_t *val) 04184 { 04185 lsm6dso_tap_cfg2_t reg; 04186 int32_t ret; 04187 04188 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1); 04189 switch (reg.inact_en) { 04190 case LSM6DSO_XL_AND_GY_NOT_AFFECTED: 04191 *val = LSM6DSO_XL_AND_GY_NOT_AFFECTED; 04192 break; 04193 case LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED: 04194 *val = LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED; 04195 break; 04196 case LSM6DSO_XL_12Hz5_GY_SLEEP: 04197 *val = LSM6DSO_XL_12Hz5_GY_SLEEP; 04198 break; 04199 case LSM6DSO_XL_12Hz5_GY_PD: 04200 *val = LSM6DSO_XL_12Hz5_GY_PD; 04201 break; 04202 default: 04203 *val = LSM6DSO_XL_AND_GY_NOT_AFFECTED; 04204 break; 04205 } 04206 return ret; 04207 } 04208 04209 /** 04210 * @brief Duration to go in sleep mode.[set] 04211 * 1 LSb = 512 / ODR 04212 * 04213 * @param ctx read / write interface definitions 04214 * @param val change the values of sleep_dur in reg WAKE_UP_DUR 04215 * 04216 */ 04217 int32_t lsm6dso_act_sleep_dur_set(lsm6dso_ctx_t *ctx, uint8_t val) 04218 { 04219 lsm6dso_wake_up_dur_t reg; 04220 int32_t ret; 04221 04222 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1); 04223 if (ret == 0) { 04224 reg.sleep_dur = val; 04225 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1); 04226 } 04227 return ret; 04228 } 04229 04230 /** 04231 * @brief Duration to go in sleep mode.[get] 04232 * 1 LSb = 512 / ODR 04233 * 04234 * @param ctx read / write interface definitions 04235 * @param val change the values of sleep_dur in reg WAKE_UP_DUR 04236 * 04237 */ 04238 int32_t lsm6dso_act_sleep_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04239 { 04240 lsm6dso_wake_up_dur_t reg; 04241 int32_t ret; 04242 04243 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)®, 1); 04244 *val = reg.sleep_dur; 04245 04246 return ret; 04247 } 04248 04249 /** 04250 * @} 04251 * 04252 */ 04253 04254 /** 04255 * @defgroup LSM6DSO_tap_generator 04256 * @brief This section groups all the functions that manage the 04257 * tap and double tap event generation. 04258 * @{ 04259 * 04260 */ 04261 04262 /** 04263 * @brief Enable Z direction in tap recognition.[set] 04264 * 04265 * @param ctx read / write interface definitions 04266 * @param val change the values of tap_z_en in reg TAP_CFG0 04267 * 04268 */ 04269 int32_t lsm6dso_tap_detection_on_z_set(lsm6dso_ctx_t *ctx, uint8_t val) 04270 { 04271 lsm6dso_tap_cfg0_t reg; 04272 int32_t ret; 04273 04274 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04275 if (ret == 0) { 04276 reg.tap_z_en = val; 04277 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04278 } 04279 return ret; 04280 } 04281 04282 /** 04283 * @brief Enable Z direction in tap recognition.[get] 04284 * 04285 * @param ctx read / write interface definitions 04286 * @param val change the values of tap_z_en in reg TAP_CFG0 04287 * 04288 */ 04289 int32_t lsm6dso_tap_detection_on_z_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04290 { 04291 lsm6dso_tap_cfg0_t reg; 04292 int32_t ret; 04293 04294 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04295 *val = reg.tap_z_en; 04296 04297 return ret; 04298 } 04299 04300 /** 04301 * @brief Enable Y direction in tap recognition.[set] 04302 * 04303 * @param ctx read / write interface definitions 04304 * @param val change the values of tap_y_en in reg TAP_CFG0 04305 * 04306 */ 04307 int32_t lsm6dso_tap_detection_on_y_set(lsm6dso_ctx_t *ctx, uint8_t val) 04308 { 04309 lsm6dso_tap_cfg0_t reg; 04310 int32_t ret; 04311 04312 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04313 if (ret == 0) { 04314 reg.tap_y_en = val; 04315 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04316 } 04317 return ret; 04318 } 04319 04320 /** 04321 * @brief Enable Y direction in tap recognition.[get] 04322 * 04323 * @param ctx read / write interface definitions 04324 * @param val change the values of tap_y_en in reg TAP_CFG0 04325 * 04326 */ 04327 int32_t lsm6dso_tap_detection_on_y_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04328 { 04329 lsm6dso_tap_cfg0_t reg; 04330 int32_t ret; 04331 04332 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04333 *val = reg.tap_y_en; 04334 04335 return ret; 04336 } 04337 04338 /** 04339 * @brief Enable X direction in tap recognition.[set] 04340 * 04341 * @param ctx read / write interface definitions 04342 * @param val change the values of tap_x_en in reg TAP_CFG0 04343 * 04344 */ 04345 int32_t lsm6dso_tap_detection_on_x_set(lsm6dso_ctx_t *ctx, uint8_t val) 04346 { 04347 lsm6dso_tap_cfg0_t reg; 04348 int32_t ret; 04349 04350 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04351 if (ret == 0) { 04352 reg.tap_x_en = val; 04353 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04354 } 04355 return ret; 04356 } 04357 04358 /** 04359 * @brief Enable X direction in tap recognition.[get] 04360 * 04361 * @param ctx read / write interface definitions 04362 * @param val change the values of tap_x_en in reg TAP_CFG0 04363 * 04364 */ 04365 int32_t lsm6dso_tap_detection_on_x_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04366 { 04367 lsm6dso_tap_cfg0_t reg; 04368 int32_t ret; 04369 04370 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*)®, 1); 04371 *val = reg.tap_x_en; 04372 04373 return ret; 04374 } 04375 04376 /** 04377 * @brief X-axis tap recognition threshold.[set] 04378 * 04379 * @param ctx read / write interface definitions 04380 * @param val change the values of tap_ths_x in reg TAP_CFG1 04381 * 04382 */ 04383 int32_t lsm6dso_tap_threshold_x_set(lsm6dso_ctx_t *ctx, uint8_t val) 04384 { 04385 lsm6dso_tap_cfg1_t reg; 04386 int32_t ret; 04387 04388 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1); 04389 if (ret == 0) { 04390 reg.tap_ths_x = val; 04391 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1); 04392 } 04393 return ret; 04394 } 04395 04396 /** 04397 * @brief X-axis tap recognition threshold.[get] 04398 * 04399 * @param ctx read / write interface definitions 04400 * @param val change the values of tap_ths_x in reg TAP_CFG1 04401 * 04402 */ 04403 int32_t lsm6dso_tap_threshold_x_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04404 { 04405 lsm6dso_tap_cfg1_t reg; 04406 int32_t ret; 04407 04408 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1); 04409 *val = reg.tap_ths_x; 04410 04411 return ret; 04412 } 04413 04414 /** 04415 * @brief Selection of axis priority for TAP detection.[set] 04416 * 04417 * @param ctx read / write interface definitions 04418 * @param val change the values of tap_priority in 04419 * reg TAP_CFG1 04420 * 04421 */ 04422 int32_t lsm6dso_tap_axis_priority_set(lsm6dso_ctx_t *ctx, 04423 lsm6dso_tap_priority_t val) 04424 { 04425 lsm6dso_tap_cfg1_t reg; 04426 int32_t ret; 04427 04428 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1); 04429 if (ret == 0) { 04430 reg.tap_priority = (uint8_t)val; 04431 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1); 04432 } 04433 return ret; 04434 } 04435 04436 /** 04437 * @brief Selection of axis priority for TAP detection.[get] 04438 * 04439 * @param ctx read / write interface definitions 04440 * @param val Get the values of tap_priority in 04441 * reg TAP_CFG1 04442 * 04443 */ 04444 int32_t lsm6dso_tap_axis_priority_get(lsm6dso_ctx_t *ctx, 04445 lsm6dso_tap_priority_t *val) 04446 { 04447 lsm6dso_tap_cfg1_t reg; 04448 int32_t ret; 04449 04450 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t*)®, 1); 04451 switch (reg.tap_priority) { 04452 case LSM6DSO_XYZ: 04453 *val = LSM6DSO_XYZ; 04454 break; 04455 case LSM6DSO_YXZ: 04456 *val = LSM6DSO_YXZ; 04457 break; 04458 case LSM6DSO_XZY: 04459 *val = LSM6DSO_XZY; 04460 break; 04461 case LSM6DSO_ZYX: 04462 *val = LSM6DSO_ZYX; 04463 break; 04464 case LSM6DSO_YZX: 04465 *val = LSM6DSO_YZX; 04466 break; 04467 case LSM6DSO_ZXY: 04468 *val = LSM6DSO_ZXY; 04469 break; 04470 default: 04471 *val = LSM6DSO_XYZ; 04472 break; 04473 } 04474 return ret; 04475 } 04476 04477 /** 04478 * @brief Y-axis tap recognition threshold.[set] 04479 * 04480 * @param ctx read / write interface definitions 04481 * @param val change the values of tap_ths_y in reg TAP_CFG2 04482 * 04483 */ 04484 int32_t lsm6dso_tap_threshold_y_set(lsm6dso_ctx_t *ctx, uint8_t val) 04485 { 04486 lsm6dso_tap_cfg2_t reg; 04487 int32_t ret; 04488 04489 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1); 04490 if (ret == 0) { 04491 reg.tap_ths_y = val; 04492 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1); 04493 } 04494 return ret; 04495 } 04496 04497 /** 04498 * @brief Y-axis tap recognition threshold.[get] 04499 * 04500 * @param ctx read / write interface definitions 04501 * @param val change the values of tap_ths_y in reg TAP_CFG2 04502 * 04503 */ 04504 int32_t lsm6dso_tap_threshold_y_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04505 { 04506 lsm6dso_tap_cfg2_t reg; 04507 int32_t ret; 04508 04509 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*)®, 1); 04510 *val = reg.tap_ths_y; 04511 04512 return ret; 04513 } 04514 04515 /** 04516 * @brief Z-axis recognition threshold.[set] 04517 * 04518 * @param ctx read / write interface definitions 04519 * @param val change the values of tap_ths_z in reg TAP_THS_6D 04520 * 04521 */ 04522 int32_t lsm6dso_tap_threshold_z_set(lsm6dso_ctx_t *ctx, uint8_t val) 04523 { 04524 lsm6dso_tap_ths_6d_t reg; 04525 int32_t ret; 04526 04527 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1); 04528 if (ret == 0) { 04529 reg.tap_ths_z = val; 04530 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1); 04531 } 04532 return ret; 04533 } 04534 04535 /** 04536 * @brief Z-axis recognition threshold.[get] 04537 * 04538 * @param ctx read / write interface definitions 04539 * @param val change the values of tap_ths_z in reg TAP_THS_6D 04540 * 04541 */ 04542 int32_t lsm6dso_tap_threshold_z_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04543 { 04544 lsm6dso_tap_ths_6d_t reg; 04545 int32_t ret; 04546 04547 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1); 04548 *val = reg.tap_ths_z; 04549 04550 return ret; 04551 } 04552 04553 /** 04554 * @brief Maximum duration is the maximum time of an 04555 * over threshold signal detection to be recognized 04556 * as a tap event. The default value of these bits 04557 * is 00b which corresponds to 4*ODR_XL time. 04558 * If the SHOCK[1:0] bits are set to a different 04559 * value, 1LSB corresponds to 8*ODR_XL time.[set] 04560 * 04561 * @param ctx read / write interface definitions 04562 * @param val change the values of shock in reg INT_DUR2 04563 * 04564 */ 04565 int32_t lsm6dso_tap_shock_set(lsm6dso_ctx_t *ctx, uint8_t val) 04566 { 04567 lsm6dso_int_dur2_t reg; 04568 int32_t ret; 04569 04570 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1); 04571 if (ret == 0) { 04572 reg.shock = val; 04573 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1); 04574 } 04575 return ret; 04576 } 04577 04578 /** 04579 * @brief Maximum duration is the maximum time of an 04580 * over threshold signal detection to be recognized 04581 * as a tap event. The default value of these bits 04582 * is 00b which corresponds to 4*ODR_XL time. 04583 * If the SHOCK[1:0] bits are set to a different 04584 * value, 1LSB corresponds to 8*ODR_XL time.[get] 04585 * 04586 * @param ctx read / write interface definitions 04587 * @param val change the values of shock in reg INT_DUR2 04588 * 04589 */ 04590 int32_t lsm6dso_tap_shock_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04591 { 04592 lsm6dso_int_dur2_t reg; 04593 int32_t ret; 04594 04595 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1); 04596 *val = reg.shock; 04597 04598 return ret; 04599 } 04600 04601 /** 04602 * @brief Quiet time is the time after the first detected 04603 * tap in which there must not be any over threshold 04604 * event. 04605 * The default value of these bits is 00b which 04606 * corresponds to 2*ODR_XL time. If the QUIET[1:0] 04607 * bits are set to a different value, 04608 * 1LSB corresponds to 4*ODR_XL time.[set] 04609 * 04610 * @param ctx read / write interface definitions 04611 * @param val change the values of quiet in reg INT_DUR2 04612 * 04613 */ 04614 int32_t lsm6dso_tap_quiet_set(lsm6dso_ctx_t *ctx, uint8_t val) 04615 { 04616 lsm6dso_int_dur2_t reg; 04617 int32_t ret; 04618 04619 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1); 04620 if (ret == 0) { 04621 reg.quiet = val; 04622 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1); 04623 } 04624 return ret; 04625 } 04626 04627 /** 04628 * @brief Quiet time is the time after the first detected 04629 * tap in which there must not be any over threshold 04630 * event. 04631 * The default value of these bits is 00b which 04632 * corresponds to 2*ODR_XL time. 04633 * If the QUIET[1:0] bits are set to a different 04634 * value, 1LSB corresponds to 4*ODR_XL time.[get] 04635 * 04636 * @param ctx read / write interface definitions 04637 * @param val change the values of quiet in reg INT_DUR2 04638 * 04639 */ 04640 int32_t lsm6dso_tap_quiet_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04641 { 04642 lsm6dso_int_dur2_t reg; 04643 int32_t ret; 04644 04645 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1); 04646 *val = reg.quiet; 04647 04648 return ret; 04649 } 04650 04651 /** 04652 * @brief When double tap recognition is enabled, 04653 * this register expresses the maximum time 04654 * between two consecutive detected taps to 04655 * determine a double tap event. 04656 * The default value of these bits is 0000b which 04657 * corresponds to 16*ODR_XL time. 04658 * If the DUR[3:0] bits are set to a different value, 04659 * 1LSB corresponds to 32*ODR_XL time.[set] 04660 * 04661 * @param ctx read / write interface definitions 04662 * @param val change the values of dur in reg INT_DUR2 04663 * 04664 */ 04665 int32_t lsm6dso_tap_dur_set(lsm6dso_ctx_t *ctx, uint8_t val) 04666 { 04667 lsm6dso_int_dur2_t reg; 04668 int32_t ret; 04669 04670 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1); 04671 if (ret == 0) { 04672 reg.dur = val; 04673 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1); 04674 } 04675 return ret; 04676 } 04677 04678 /** 04679 * @brief When double tap recognition is enabled, 04680 * this register expresses the maximum time 04681 * between two consecutive detected taps to 04682 * determine a double tap event. 04683 * The default value of these bits is 0000b which 04684 * corresponds to 16*ODR_XL time. If the DUR[3:0] 04685 * bits are set to a different value, 04686 * 1LSB corresponds to 32*ODR_XL time.[get] 04687 * 04688 * @param ctx read / write interface definitions 04689 * @param val change the values of dur in reg INT_DUR2 04690 * 04691 */ 04692 int32_t lsm6dso_tap_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04693 { 04694 lsm6dso_int_dur2_t reg; 04695 int32_t ret; 04696 04697 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t*)®, 1); 04698 *val = reg.dur; 04699 04700 return ret; 04701 } 04702 04703 /** 04704 * @brief Single/double-tap event enable.[set] 04705 * 04706 * @param ctx read / write interface definitions 04707 * @param val change the values of single_double_tap in reg WAKE_UP_THS 04708 * 04709 */ 04710 int32_t lsm6dso_tap_mode_set(lsm6dso_ctx_t *ctx, 04711 lsm6dso_single_double_tap_t val) 04712 { 04713 lsm6dso_wake_up_ths_t reg; 04714 int32_t ret; 04715 04716 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1); 04717 if (ret == 0) { 04718 reg.single_double_tap = (uint8_t)val; 04719 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1); 04720 } 04721 return ret; 04722 } 04723 04724 /** 04725 * @brief Single/double-tap event enable.[get] 04726 * 04727 * @param ctx read / write interface definitions 04728 * @param val Get the values of single_double_tap in reg WAKE_UP_THS 04729 * 04730 */ 04731 int32_t lsm6dso_tap_mode_get(lsm6dso_ctx_t *ctx, 04732 lsm6dso_single_double_tap_t *val) 04733 { 04734 lsm6dso_wake_up_ths_t reg; 04735 int32_t ret; 04736 04737 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t*)®, 1); 04738 04739 switch (reg.single_double_tap) { 04740 case LSM6DSO_ONLY_SINGLE: 04741 *val = LSM6DSO_ONLY_SINGLE; 04742 break; 04743 case LSM6DSO_BOTH_SINGLE_DOUBLE: 04744 *val = LSM6DSO_BOTH_SINGLE_DOUBLE; 04745 break; 04746 default: 04747 *val = LSM6DSO_ONLY_SINGLE; 04748 break; 04749 } 04750 04751 return ret; 04752 } 04753 04754 /** 04755 * @} 04756 * 04757 */ 04758 04759 /** 04760 * @defgroup LSM6DSO_ Six_position_detection(6D/4D) 04761 * @brief This section groups all the functions concerning six position 04762 * detection (6D). 04763 * @{ 04764 * 04765 */ 04766 04767 /** 04768 * @brief Threshold for 4D/6D function.[set] 04769 * 04770 * @param ctx read / write interface definitions 04771 * @param val change the values of sixd_ths in reg TAP_THS_6D 04772 * 04773 */ 04774 int32_t lsm6dso_6d_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_sixd_ths_t val) 04775 { 04776 lsm6dso_tap_ths_6d_t reg; 04777 int32_t ret; 04778 04779 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1); 04780 if (ret == 0) { 04781 reg.sixd_ths = (uint8_t)val; 04782 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1); 04783 } 04784 return ret; 04785 } 04786 04787 /** 04788 * @brief Threshold for 4D/6D function.[get] 04789 * 04790 * @param ctx read / write interface definitions 04791 * @param val Get the values of sixd_ths in reg TAP_THS_6D 04792 * 04793 */ 04794 int32_t lsm6dso_6d_threshold_get(lsm6dso_ctx_t *ctx, lsm6dso_sixd_ths_t *val) 04795 { 04796 lsm6dso_tap_ths_6d_t reg; 04797 int32_t ret; 04798 04799 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1); 04800 switch (reg.sixd_ths) { 04801 case LSM6DSO_DEG_80: 04802 *val = LSM6DSO_DEG_80; 04803 break; 04804 case LSM6DSO_DEG_70: 04805 *val = LSM6DSO_DEG_70; 04806 break; 04807 case LSM6DSO_DEG_60: 04808 *val = LSM6DSO_DEG_60; 04809 break; 04810 case LSM6DSO_DEG_50: 04811 *val = LSM6DSO_DEG_50; 04812 break; 04813 default: 04814 *val = LSM6DSO_DEG_80; 04815 break; 04816 } 04817 return ret; 04818 } 04819 04820 /** 04821 * @brief 4D orientation detection enable.[set] 04822 * 04823 * @param ctx read / write interface definitions 04824 * @param val change the values of d4d_en in reg TAP_THS_6D 04825 * 04826 */ 04827 int32_t lsm6dso_4d_mode_set(lsm6dso_ctx_t *ctx, uint8_t val) 04828 { 04829 lsm6dso_tap_ths_6d_t reg; 04830 int32_t ret; 04831 04832 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1); 04833 if (ret == 0) { 04834 reg.d4d_en = val; 04835 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1); 04836 } 04837 return ret; 04838 } 04839 04840 /** 04841 * @brief 4D orientation detection enable.[get] 04842 * 04843 * @param ctx read / write interface definitions 04844 * @param val change the values of d4d_en in reg TAP_THS_6D 04845 * 04846 */ 04847 int32_t lsm6dso_4d_mode_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04848 { 04849 lsm6dso_tap_ths_6d_t reg; 04850 int32_t ret; 04851 04852 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t*)®, 1); 04853 *val = reg.d4d_en; 04854 04855 return ret; 04856 } 04857 04858 /** 04859 * @} 04860 * 04861 */ 04862 04863 /** 04864 * @defgroup LSM6DSO_free_fall 04865 * @brief This section group all the functions concerning the free 04866 * fall detection. 04867 * @{ 04868 * 04869 */ 04870 /** 04871 * @brief Free fall threshold setting.[set] 04872 * 04873 * @param ctx read / write interface definitions 04874 * @param val change the values of ff_ths in reg FREE_FALL 04875 * 04876 */ 04877 int32_t lsm6dso_ff_threshold_set(lsm6dso_ctx_t *ctx, lsm6dso_ff_ths_t val) 04878 { 04879 lsm6dso_free_fall_t reg; 04880 int32_t ret; 04881 04882 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)®, 1); 04883 if (ret == 0) { 04884 reg.ff_ths = (uint8_t)val; 04885 ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)®, 1); 04886 } 04887 return ret; 04888 } 04889 04890 /** 04891 * @brief Free fall threshold setting.[get] 04892 * 04893 * @param ctx read / write interface definitions 04894 * @param val Get the values of ff_ths in reg FREE_FALL 04895 * 04896 */ 04897 int32_t lsm6dso_ff_threshold_get(lsm6dso_ctx_t *ctx, lsm6dso_ff_ths_t *val) 04898 { 04899 lsm6dso_free_fall_t reg; 04900 int32_t ret; 04901 04902 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)®, 1); 04903 switch (reg.ff_ths) { 04904 case LSM6DSO_FF_TSH_156mg: 04905 *val = LSM6DSO_FF_TSH_156mg; 04906 break; 04907 case LSM6DSO_FF_TSH_219mg: 04908 *val = LSM6DSO_FF_TSH_219mg; 04909 break; 04910 case LSM6DSO_FF_TSH_250mg: 04911 *val = LSM6DSO_FF_TSH_250mg; 04912 break; 04913 case LSM6DSO_FF_TSH_312mg: 04914 *val = LSM6DSO_FF_TSH_312mg; 04915 break; 04916 case LSM6DSO_FF_TSH_344mg: 04917 *val = LSM6DSO_FF_TSH_344mg; 04918 break; 04919 case LSM6DSO_FF_TSH_406mg: 04920 *val = LSM6DSO_FF_TSH_406mg; 04921 break; 04922 case LSM6DSO_FF_TSH_469mg: 04923 *val = LSM6DSO_FF_TSH_469mg; 04924 break; 04925 case LSM6DSO_FF_TSH_500mg: 04926 *val = LSM6DSO_FF_TSH_500mg; 04927 break; 04928 default: 04929 *val = LSM6DSO_FF_TSH_156mg; 04930 break; 04931 } 04932 return ret; 04933 } 04934 04935 /** 04936 * @brief Free-fall duration event.[set] 04937 * 1LSb = 1 / ODR 04938 * 04939 * @param ctx read / write interface definitions 04940 * @param val change the values of ff_dur in reg FREE_FALL 04941 * 04942 */ 04943 int32_t lsm6dso_ff_dur_set(lsm6dso_ctx_t *ctx, uint8_t val) 04944 { 04945 lsm6dso_wake_up_dur_t wake_up_dur; 04946 lsm6dso_free_fall_t free_fall; 04947 int32_t ret; 04948 04949 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); 04950 if (ret == 0) { 04951 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1); 04952 } 04953 if (ret == 0) { 04954 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5; 04955 free_fall.ff_dur = (uint8_t)val & 0x1FU; 04956 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, 04957 (uint8_t*)&wake_up_dur, 1); 04958 } 04959 if (ret == 0) { 04960 ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1); 04961 } 04962 return ret; 04963 } 04964 04965 /** 04966 * @brief Free-fall duration event.[get] 04967 * 1LSb = 1 / ODR 04968 * 04969 * @param ctx read / write interface definitions 04970 * @param val change the values of ff_dur in reg FREE_FALL 04971 * 04972 */ 04973 int32_t lsm6dso_ff_dur_get(lsm6dso_ctx_t *ctx, uint8_t *val) 04974 { 04975 lsm6dso_wake_up_dur_t wake_up_dur; 04976 lsm6dso_free_fall_t free_fall; 04977 int32_t ret; 04978 04979 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t*)&wake_up_dur, 1); 04980 if (ret == 0) { 04981 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t*)&free_fall, 1); 04982 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur; 04983 } 04984 return ret; 04985 } 04986 04987 /** 04988 * @} 04989 * 04990 */ 04991 04992 /** 04993 * @defgroup LSM6DSO_fifo 04994 * @brief This section group all the functions concerning the fifo usage 04995 * @{ 04996 * 04997 */ 04998 04999 /** 05000 * @brief FIFO watermark level selection.[set] 05001 * 05002 * @param ctx read / write interface definitions 05003 * @param val change the values of wtm in reg FIFO_CTRL1 05004 * 05005 */ 05006 int32_t lsm6dso_fifo_watermark_set(lsm6dso_ctx_t *ctx, uint16_t val) 05007 { 05008 lsm6dso_fifo_ctrl1_t fifo_ctrl1; 05009 lsm6dso_fifo_ctrl2_t fifo_ctrl2; 05010 int32_t ret; 05011 05012 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); 05013 if (ret == 0) { 05014 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val; 05015 fifo_ctrl2.wtm = (uint8_t)(( 0x0100U & val ) >> 8); 05016 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); 05017 } 05018 if (ret == 0) { 05019 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); 05020 } 05021 return ret; 05022 } 05023 05024 /** 05025 * @brief FIFO watermark level selection.[get] 05026 * 05027 * @param ctx read / write interface definitions 05028 * @param val change the values of wtm in reg FIFO_CTRL1 05029 * 05030 */ 05031 int32_t lsm6dso_fifo_watermark_get(lsm6dso_ctx_t *ctx, uint16_t *val) 05032 { 05033 lsm6dso_fifo_ctrl1_t fifo_ctrl1; 05034 lsm6dso_fifo_ctrl2_t fifo_ctrl2; 05035 int32_t ret; 05036 05037 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t*)&fifo_ctrl1, 1); 05038 if (ret == 0) { 05039 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)&fifo_ctrl2, 1); 05040 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm; 05041 } 05042 return ret; 05043 } 05044 05045 /** 05046 * @brief FIFO compression feature initialization request [set]. 05047 * 05048 * @param ctx read / write interface definitions 05049 * @param val change the values of FIFO_COMPR_INIT in 05050 * reg EMB_FUNC_INIT_B 05051 * 05052 */ 05053 int32_t lsm6dso_compression_algo_init_set(lsm6dso_ctx_t *ctx, uint8_t val) 05054 { 05055 lsm6dso_emb_func_init_b_t reg; 05056 int32_t ret; 05057 05058 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 05059 if (ret == 0) { 05060 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 05061 } 05062 if (ret == 0) { 05063 reg.fifo_compr_init = val; 05064 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 05065 } 05066 if (ret == 0) { 05067 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 05068 } 05069 05070 return ret; 05071 } 05072 05073 /** 05074 * @brief FIFO compression feature initialization request [get]. 05075 * 05076 * @param ctx read / write interface definitions 05077 * @param val change the values of FIFO_COMPR_INIT in 05078 * reg EMB_FUNC_INIT_B 05079 * 05080 */ 05081 int32_t lsm6dso_compression_algo_init_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05082 { 05083 lsm6dso_emb_func_init_b_t reg; 05084 int32_t ret; 05085 05086 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 05087 if (ret == 0) { 05088 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 05089 } 05090 if (ret == 0) { 05091 *val = reg.fifo_compr_init; 05092 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 05093 } 05094 05095 return ret; 05096 } 05097 05098 /** 05099 * @brief Enable and configure compression algo.[set] 05100 * 05101 * @param ctx read / write interface definitions 05102 * @param val change the values of uncoptr_rate in 05103 * reg FIFO_CTRL2 05104 * 05105 */ 05106 int32_t lsm6dso_compression_algo_set(lsm6dso_ctx_t *ctx, 05107 lsm6dso_uncoptr_rate_t val) 05108 { 05109 lsm6dso_fifo_ctrl2_t fifo_ctrl2; 05110 int32_t ret; 05111 05112 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, 05113 (uint8_t*)&fifo_ctrl2, 1); 05114 05115 if (ret == 0) { 05116 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2; 05117 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U; 05118 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, 05119 (uint8_t*)&fifo_ctrl2, 1); 05120 } 05121 return ret; 05122 } 05123 05124 /** 05125 * @brief Enable and configure compression algo.[get] 05126 * 05127 * @param ctx read / write interface definitions 05128 * @param val Get the values of uncoptr_rate in 05129 * reg FIFO_CTRL2 05130 * 05131 */ 05132 int32_t lsm6dso_compression_algo_get(lsm6dso_ctx_t *ctx, 05133 lsm6dso_uncoptr_rate_t *val) 05134 { 05135 lsm6dso_fifo_ctrl2_t reg; 05136 int32_t ret; 05137 05138 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1); 05139 05140 switch ((reg.fifo_compr_rt_en<<2) | reg.uncoptr_rate) { 05141 case LSM6DSO_CMP_DISABLE: 05142 *val = LSM6DSO_CMP_DISABLE; 05143 break; 05144 case LSM6DSO_CMP_ALWAYS: 05145 *val = LSM6DSO_CMP_ALWAYS; 05146 break; 05147 case LSM6DSO_CMP_8_TO_1: 05148 *val = LSM6DSO_CMP_8_TO_1; 05149 break; 05150 case LSM6DSO_CMP_16_TO_1: 05151 *val = LSM6DSO_CMP_16_TO_1; 05152 break; 05153 case LSM6DSO_CMP_32_TO_1: 05154 *val = LSM6DSO_CMP_32_TO_1; 05155 break; 05156 default: 05157 *val = LSM6DSO_CMP_DISABLE; 05158 break; 05159 } 05160 return ret; 05161 } 05162 05163 /** 05164 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set] 05165 * 05166 * @param ctx read / write interface definitions 05167 * @param val change the values of odrchg_en in reg FIFO_CTRL2 05168 * 05169 */ 05170 int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(lsm6dso_ctx_t *ctx, 05171 uint8_t val) 05172 { 05173 lsm6dso_fifo_ctrl2_t reg; 05174 int32_t ret; 05175 05176 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1); 05177 if (ret == 0) { 05178 reg.odrchg_en = val; 05179 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1); 05180 } 05181 return ret; 05182 } 05183 05184 /** 05185 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get] 05186 * 05187 * @param ctx read / write interface definitions 05188 * @param val change the values of odrchg_en in reg FIFO_CTRL2 05189 * 05190 */ 05191 int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(lsm6dso_ctx_t *ctx, 05192 uint8_t *val) 05193 { 05194 lsm6dso_fifo_ctrl2_t reg; 05195 int32_t ret; 05196 05197 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1); 05198 *val = reg.odrchg_en; 05199 05200 return ret; 05201 } 05202 05203 /** 05204 * @brief Enables/Disables compression algorithm runtime.[set] 05205 * 05206 * @param ctx read / write interface definitions 05207 * @param val change the values of fifo_compr_rt_en in 05208 * reg FIFO_CTRL2 05209 * 05210 */ 05211 int32_t lsm6dso_compression_algo_real_time_set(lsm6dso_ctx_t *ctx, 05212 uint8_t val) 05213 { 05214 lsm6dso_fifo_ctrl2_t reg; 05215 int32_t ret; 05216 05217 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1); 05218 if (ret == 0) { 05219 reg.fifo_compr_rt_en = val; 05220 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1); 05221 } 05222 return ret; 05223 } 05224 05225 /** 05226 * @brief Enables/Disables compression algorithm runtime. [get] 05227 * 05228 * @param ctx read / write interface definitions 05229 * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2 05230 * 05231 */ 05232 int32_t lsm6dso_compression_algo_real_time_get(lsm6dso_ctx_t *ctx, 05233 uint8_t *val) 05234 { 05235 lsm6dso_fifo_ctrl2_t reg; 05236 int32_t ret; 05237 05238 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1); 05239 *val = reg.fifo_compr_rt_en; 05240 05241 return ret; 05242 } 05243 05244 /** 05245 * @brief Sensing chain FIFO stop values memorization at 05246 * threshold level.[set] 05247 * 05248 * @param ctx read / write interface definitions 05249 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2 05250 * 05251 */ 05252 int32_t lsm6dso_fifo_stop_on_wtm_set(lsm6dso_ctx_t *ctx, uint8_t val) 05253 { 05254 lsm6dso_fifo_ctrl2_t reg; 05255 int32_t ret; 05256 05257 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1); 05258 if (ret == 0) { 05259 reg.stop_on_wtm = val; 05260 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1); 05261 } 05262 return ret; 05263 } 05264 05265 /** 05266 * @brief Sensing chain FIFO stop values memorization at 05267 * threshold level.[get] 05268 * 05269 * @param ctx read / write interface definitions 05270 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2 05271 * 05272 */ 05273 int32_t lsm6dso_fifo_stop_on_wtm_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05274 { 05275 lsm6dso_fifo_ctrl2_t reg; 05276 int32_t ret; 05277 05278 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t*)®, 1); 05279 *val = reg.stop_on_wtm; 05280 05281 return ret; 05282 } 05283 05284 /** 05285 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05286 * for accelerometer data.[set] 05287 * 05288 * @param ctx read / write interface definitions 05289 * @param val change the values of bdr_xl in reg FIFO_CTRL3 05290 * 05291 */ 05292 int32_t lsm6dso_fifo_xl_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_xl_t val) 05293 { 05294 lsm6dso_fifo_ctrl3_t reg; 05295 int32_t ret; 05296 05297 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1); 05298 if (ret == 0) { 05299 reg.bdr_xl = (uint8_t)val; 05300 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1); 05301 } 05302 return ret; 05303 } 05304 05305 /** 05306 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05307 * for accelerometer data.[get] 05308 * 05309 * @param ctx read / write interface definitions 05310 * @param val Get the values of bdr_xl in reg FIFO_CTRL3 05311 * 05312 */ 05313 int32_t lsm6dso_fifo_xl_batch_get(lsm6dso_ctx_t *ctx, lsm6dso_bdr_xl_t *val) 05314 { 05315 lsm6dso_fifo_ctrl3_t reg; 05316 int32_t ret; 05317 05318 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1); 05319 switch (reg.bdr_xl) { 05320 case LSM6DSO_XL_NOT_BATCHED: 05321 *val = LSM6DSO_XL_NOT_BATCHED; 05322 break; 05323 case LSM6DSO_XL_BATCHED_AT_12Hz5: 05324 *val = LSM6DSO_XL_BATCHED_AT_12Hz5; 05325 break; 05326 case LSM6DSO_XL_BATCHED_AT_26Hz: 05327 *val = LSM6DSO_XL_BATCHED_AT_26Hz; 05328 break; 05329 case LSM6DSO_XL_BATCHED_AT_52Hz: 05330 *val = LSM6DSO_XL_BATCHED_AT_52Hz; 05331 break; 05332 case LSM6DSO_XL_BATCHED_AT_104Hz: 05333 *val = LSM6DSO_XL_BATCHED_AT_104Hz; 05334 break; 05335 case LSM6DSO_XL_BATCHED_AT_208Hz: 05336 *val = LSM6DSO_XL_BATCHED_AT_208Hz; 05337 break; 05338 case LSM6DSO_XL_BATCHED_AT_417Hz: 05339 *val = LSM6DSO_XL_BATCHED_AT_417Hz; 05340 break; 05341 case LSM6DSO_XL_BATCHED_AT_833Hz: 05342 *val = LSM6DSO_XL_BATCHED_AT_833Hz; 05343 break; 05344 case LSM6DSO_XL_BATCHED_AT_1667Hz: 05345 *val = LSM6DSO_XL_BATCHED_AT_1667Hz; 05346 break; 05347 case LSM6DSO_XL_BATCHED_AT_3333Hz: 05348 *val = LSM6DSO_XL_BATCHED_AT_3333Hz; 05349 break; 05350 case LSM6DSO_XL_BATCHED_AT_6667Hz: 05351 *val = LSM6DSO_XL_BATCHED_AT_6667Hz; 05352 break; 05353 case LSM6DSO_XL_BATCHED_AT_6Hz5: 05354 *val = LSM6DSO_XL_BATCHED_AT_6Hz5; 05355 break; 05356 default: 05357 *val = LSM6DSO_XL_NOT_BATCHED; 05358 break; 05359 } 05360 05361 return ret; 05362 } 05363 05364 /** 05365 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05366 * for gyroscope data.[set] 05367 * 05368 * @param ctx read / write interface definitions 05369 * @param val change the values of bdr_gy in reg FIFO_CTRL3 05370 * 05371 */ 05372 int32_t lsm6dso_fifo_gy_batch_set(lsm6dso_ctx_t *ctx, lsm6dso_bdr_gy_t val) 05373 { 05374 lsm6dso_fifo_ctrl3_t reg; 05375 int32_t ret; 05376 05377 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1); 05378 if (ret == 0) { 05379 reg.bdr_gy = (uint8_t)val; 05380 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1); 05381 } 05382 return ret; 05383 } 05384 05385 /** 05386 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05387 * for gyroscope data.[get] 05388 * 05389 * @param ctx read / write interface definitions 05390 * @param val Get the values of bdr_gy in reg FIFO_CTRL3 05391 * 05392 */ 05393 int32_t lsm6dso_fifo_gy_batch_get(lsm6dso_ctx_t *ctx, lsm6dso_bdr_gy_t *val) 05394 { 05395 lsm6dso_fifo_ctrl3_t reg; 05396 int32_t ret; 05397 05398 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t*)®, 1); 05399 switch (reg.bdr_gy) { 05400 case LSM6DSO_GY_NOT_BATCHED: 05401 *val = LSM6DSO_GY_NOT_BATCHED; 05402 break; 05403 case LSM6DSO_GY_BATCHED_AT_12Hz5: 05404 *val = LSM6DSO_GY_BATCHED_AT_12Hz5; 05405 break; 05406 case LSM6DSO_GY_BATCHED_AT_26Hz: 05407 *val = LSM6DSO_GY_BATCHED_AT_26Hz; 05408 break; 05409 case LSM6DSO_GY_BATCHED_AT_52Hz: 05410 *val = LSM6DSO_GY_BATCHED_AT_52Hz; 05411 break; 05412 case LSM6DSO_GY_BATCHED_AT_104Hz: 05413 *val = LSM6DSO_GY_BATCHED_AT_104Hz; 05414 break; 05415 case LSM6DSO_GY_BATCHED_AT_208Hz: 05416 *val = LSM6DSO_GY_BATCHED_AT_208Hz; 05417 break; 05418 case LSM6DSO_GY_BATCHED_AT_417Hz: 05419 *val = LSM6DSO_GY_BATCHED_AT_417Hz; 05420 break; 05421 case LSM6DSO_GY_BATCHED_AT_833Hz: 05422 *val = LSM6DSO_GY_BATCHED_AT_833Hz; 05423 break; 05424 case LSM6DSO_GY_BATCHED_AT_1667Hz: 05425 *val = LSM6DSO_GY_BATCHED_AT_1667Hz; 05426 break; 05427 case LSM6DSO_GY_BATCHED_AT_3333Hz: 05428 *val = LSM6DSO_GY_BATCHED_AT_3333Hz; 05429 break; 05430 case LSM6DSO_GY_BATCHED_AT_6667Hz: 05431 *val = LSM6DSO_GY_BATCHED_AT_6667Hz; 05432 break; 05433 case LSM6DSO_GY_BATCHED_AT_6Hz5: 05434 *val = LSM6DSO_GY_BATCHED_AT_6Hz5; 05435 break; 05436 default: 05437 *val = LSM6DSO_GY_NOT_BATCHED; 05438 break; 05439 } 05440 return ret; 05441 } 05442 05443 /** 05444 * @brief FIFO mode selection.[set] 05445 * 05446 * @param ctx read / write interface definitions 05447 * @param val change the values of fifo_mode in reg FIFO_CTRL4 05448 * 05449 */ 05450 int32_t lsm6dso_fifo_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_fifo_mode_t val) 05451 { 05452 lsm6dso_fifo_ctrl4_t reg; 05453 int32_t ret; 05454 05455 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1); 05456 if (ret == 0) { 05457 reg.fifo_mode = (uint8_t)val; 05458 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1); 05459 } 05460 return ret; 05461 } 05462 05463 /** 05464 * @brief FIFO mode selection.[get] 05465 * 05466 * @param ctx read / write interface definitions 05467 * @param val Get the values of fifo_mode in reg FIFO_CTRL4 05468 * 05469 */ 05470 int32_t lsm6dso_fifo_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_fifo_mode_t *val) 05471 { 05472 lsm6dso_fifo_ctrl4_t reg; 05473 int32_t ret; 05474 05475 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1); 05476 05477 switch (reg.fifo_mode) { 05478 case LSM6DSO_BYPASS_MODE: 05479 *val = LSM6DSO_BYPASS_MODE; 05480 break; 05481 case LSM6DSO_FIFO_MODE: 05482 *val = LSM6DSO_FIFO_MODE; 05483 break; 05484 case LSM6DSO_STREAM_TO_FIFO_MODE: 05485 *val = LSM6DSO_STREAM_TO_FIFO_MODE; 05486 break; 05487 case LSM6DSO_BYPASS_TO_STREAM_MODE: 05488 *val = LSM6DSO_BYPASS_TO_STREAM_MODE; 05489 break; 05490 case LSM6DSO_STREAM_MODE: 05491 *val = LSM6DSO_STREAM_MODE; 05492 break; 05493 case LSM6DSO_BYPASS_TO_FIFO_MODE: 05494 *val = LSM6DSO_BYPASS_TO_FIFO_MODE; 05495 break; 05496 default: 05497 *val = LSM6DSO_BYPASS_MODE; 05498 break; 05499 } 05500 return ret; 05501 } 05502 05503 /** 05504 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05505 * for temperature data.[set] 05506 * 05507 * @param ctx read / write interface definitions 05508 * @param val change the values of odr_t_batch in reg FIFO_CTRL4 05509 * 05510 */ 05511 int32_t lsm6dso_fifo_temp_batch_set(lsm6dso_ctx_t *ctx, 05512 lsm6dso_odr_t_batch_t val) 05513 { 05514 lsm6dso_fifo_ctrl4_t reg; 05515 int32_t ret; 05516 05517 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1); 05518 if (ret == 0) { 05519 reg.odr_t_batch = (uint8_t)val; 05520 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1); 05521 } 05522 return ret; 05523 } 05524 05525 /** 05526 * @brief Selects Batching Data Rate (writing frequency in FIFO) 05527 * for temperature data.[get] 05528 * 05529 * @param ctx read / write interface definitions 05530 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4 05531 * 05532 */ 05533 int32_t lsm6dso_fifo_temp_batch_get(lsm6dso_ctx_t *ctx, 05534 lsm6dso_odr_t_batch_t *val) 05535 { 05536 lsm6dso_fifo_ctrl4_t reg; 05537 int32_t ret; 05538 05539 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1); 05540 05541 switch (reg.odr_t_batch) { 05542 case LSM6DSO_TEMP_NOT_BATCHED: 05543 *val = LSM6DSO_TEMP_NOT_BATCHED; 05544 break; 05545 case LSM6DSO_TEMP_BATCHED_AT_1Hz6: 05546 *val = LSM6DSO_TEMP_BATCHED_AT_1Hz6; 05547 break; 05548 case LSM6DSO_TEMP_BATCHED_AT_12Hz5: 05549 *val = LSM6DSO_TEMP_BATCHED_AT_12Hz5; 05550 break; 05551 case LSM6DSO_TEMP_BATCHED_AT_52Hz: 05552 *val = LSM6DSO_TEMP_BATCHED_AT_52Hz; 05553 break; 05554 default: 05555 *val = LSM6DSO_TEMP_NOT_BATCHED; 05556 break; 05557 } 05558 return ret; 05559 } 05560 05561 /** 05562 * @brief Selects decimation for timestamp batching in FIFO. 05563 * Writing rate will be the maximum rate between XL and 05564 * GYRO BDR divided by decimation decoder.[set] 05565 * 05566 * @param ctx read / write interface definitions 05567 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4 05568 * 05569 */ 05570 int32_t lsm6dso_fifo_timestamp_decimation_set(lsm6dso_ctx_t *ctx, 05571 lsm6dso_odr_ts_batch_t val) 05572 { 05573 lsm6dso_fifo_ctrl4_t reg; 05574 int32_t ret; 05575 05576 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1); 05577 if (ret == 0) { 05578 reg.odr_ts_batch = (uint8_t)val; 05579 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1); 05580 } 05581 return ret; 05582 } 05583 05584 /** 05585 * @brief Selects decimation for timestamp batching in FIFO. 05586 * Writing rate will be the maximum rate between XL and 05587 * GYRO BDR divided by decimation decoder.[get] 05588 * 05589 * @param ctx read / write interface definitions 05590 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4 05591 * 05592 */ 05593 int32_t lsm6dso_fifo_timestamp_decimation_get(lsm6dso_ctx_t *ctx, 05594 lsm6dso_odr_ts_batch_t *val) 05595 { 05596 lsm6dso_fifo_ctrl4_t reg; 05597 int32_t ret; 05598 05599 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t*)®, 1); 05600 switch (reg.odr_ts_batch) { 05601 case LSM6DSO_NO_DECIMATION: 05602 *val = LSM6DSO_NO_DECIMATION; 05603 break; 05604 case LSM6DSO_DEC_1: 05605 *val = LSM6DSO_DEC_1; 05606 break; 05607 case LSM6DSO_DEC_8: 05608 *val = LSM6DSO_DEC_8; 05609 break; 05610 case LSM6DSO_DEC_32: 05611 *val = LSM6DSO_DEC_32; 05612 break; 05613 default: 05614 *val = LSM6DSO_NO_DECIMATION; 05615 break; 05616 } 05617 return ret; 05618 } 05619 05620 /** 05621 * @brief Selects the trigger for the internal counter of batching events 05622 * between XL and gyro.[set] 05623 * 05624 * @param ctx read / write interface definitions 05625 * @param val change the values of trig_counter_bdr 05626 * in reg COUNTER_BDR_REG1 05627 * 05628 */ 05629 int32_t lsm6dso_fifo_cnt_event_batch_set(lsm6dso_ctx_t *ctx, 05630 lsm6dso_trig_counter_bdr_t val) 05631 { 05632 lsm6dso_counter_bdr_reg1_t reg; 05633 int32_t ret; 05634 05635 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05636 if (ret == 0) { 05637 reg.trig_counter_bdr = (uint8_t)val; 05638 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05639 } 05640 return ret; 05641 } 05642 05643 /** 05644 * @brief Selects the trigger for the internal counter of batching events 05645 * between XL and gyro.[get] 05646 * 05647 * @param ctx read / write interface definitions 05648 * @param val Get the values of trig_counter_bdr 05649 * in reg COUNTER_BDR_REG1 05650 * 05651 */ 05652 int32_t lsm6dso_fifo_cnt_event_batch_get(lsm6dso_ctx_t *ctx, 05653 lsm6dso_trig_counter_bdr_t *val) 05654 { 05655 lsm6dso_counter_bdr_reg1_t reg; 05656 int32_t ret; 05657 05658 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05659 switch (reg.trig_counter_bdr) { 05660 case LSM6DSO_XL_BATCH_EVENT: 05661 *val = LSM6DSO_XL_BATCH_EVENT; 05662 break; 05663 case LSM6DSO_GYRO_BATCH_EVENT: 05664 *val = LSM6DSO_GYRO_BATCH_EVENT; 05665 break; 05666 default: 05667 *val = LSM6DSO_XL_BATCH_EVENT; 05668 break; 05669 } 05670 return ret; 05671 } 05672 05673 /** 05674 * @brief Resets the internal counter of batching vents for a single sensor. 05675 * This bit is automatically reset to zero if it was set to ‘1’.[set] 05676 * 05677 * @param ctx read / write interface definitions 05678 * @param val change the values of rst_counter_bdr in 05679 * reg COUNTER_BDR_REG1 05680 * 05681 */ 05682 int32_t lsm6dso_rst_batch_counter_set(lsm6dso_ctx_t *ctx, uint8_t val) 05683 { 05684 lsm6dso_counter_bdr_reg1_t reg; 05685 int32_t ret; 05686 05687 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05688 if (ret == 0) { 05689 reg.rst_counter_bdr = val; 05690 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05691 } 05692 return ret; 05693 } 05694 05695 /** 05696 * @brief Resets the internal counter of batching events for a single sensor. 05697 * This bit is automatically reset to zero if it was set to ‘1’.[get] 05698 * 05699 * @param ctx read / write interface definitions 05700 * @param val change the values of rst_counter_bdr in 05701 * reg COUNTER_BDR_REG1 05702 * 05703 */ 05704 int32_t lsm6dso_rst_batch_counter_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05705 { 05706 lsm6dso_counter_bdr_reg1_t reg; 05707 int32_t ret; 05708 05709 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t*)®, 1); 05710 *val = reg.rst_counter_bdr; 05711 05712 return ret; 05713 } 05714 05715 /** 05716 * @brief Batch data rate counter.[set] 05717 * 05718 * @param ctx read / write interface definitions 05719 * @param val change the values of cnt_bdr_th in 05720 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1. 05721 * 05722 */ 05723 int32_t lsm6dso_batch_counter_threshold_set(lsm6dso_ctx_t *ctx, uint16_t val) 05724 { 05725 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1; 05726 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2; 05727 int32_t ret; 05728 05729 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, 05730 (uint8_t*)&counter_bdr_reg1, 1); 05731 if (ret == 0) { 05732 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val; 05733 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8; 05734 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, 05735 (uint8_t*)&counter_bdr_reg1, 1); 05736 } 05737 if (ret == 0) { 05738 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG2, 05739 (uint8_t*)&counter_bdr_reg2, 1); 05740 } 05741 return ret; 05742 } 05743 05744 /** 05745 * @brief Batch data rate counter.[get] 05746 * 05747 * @param ctx read / write interface definitions 05748 * @param val change the values of cnt_bdr_th in 05749 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1. 05750 * 05751 */ 05752 int32_t lsm6dso_batch_counter_threshold_get(lsm6dso_ctx_t *ctx, uint16_t *val) 05753 { 05754 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1; 05755 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2; 05756 int32_t ret; 05757 05758 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, 05759 (uint8_t*)&counter_bdr_reg1, 1); 05760 if (ret == 0) { 05761 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG2, 05762 (uint8_t*)&counter_bdr_reg2, 1); 05763 05764 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8) 05765 + (uint16_t)counter_bdr_reg2.cnt_bdr_th; 05766 } 05767 05768 return ret; 05769 } 05770 05771 /** 05772 * @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get] 05773 * 05774 * @param ctx read / write interface definitions 05775 * @param val change the values of diff_fifo in reg FIFO_STATUS1 05776 * 05777 */ 05778 int32_t lsm6dso_fifo_data_level_get(lsm6dso_ctx_t *ctx, uint16_t *val) 05779 { 05780 lsm6dso_fifo_status1_t fifo_status1; 05781 lsm6dso_fifo_status2_t fifo_status2; 05782 int32_t ret; 05783 05784 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1, 05785 (uint8_t*)&fifo_status1, 1); 05786 if (ret == 0) { 05787 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, 05788 (uint8_t*)&fifo_status2, 1); 05789 *val = ((uint16_t)fifo_status2.diff_fifo << 8) + 05790 (uint16_t)fifo_status1.diff_fifo; 05791 } 05792 return ret; 05793 } 05794 05795 /** 05796 * @brief FIFO status.[get] 05797 * 05798 * @param ctx read / write interface definitions 05799 * @param val registers FIFO_STATUS2 05800 * 05801 */ 05802 int32_t lsm6dso_fifo_status_get(lsm6dso_ctx_t *ctx, 05803 lsm6dso_fifo_status2_t *val) 05804 { 05805 int32_t ret; 05806 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*) val, 1); 05807 return ret; 05808 } 05809 05810 /** 05811 * @brief Smart FIFO full status.[get] 05812 * 05813 * @param ctx read / write interface definitions 05814 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2 05815 * 05816 */ 05817 int32_t lsm6dso_fifo_full_flag_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05818 { 05819 lsm6dso_fifo_status2_t reg; 05820 int32_t ret; 05821 05822 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)®, 1); 05823 *val = reg.fifo_full_ia; 05824 05825 return ret; 05826 } 05827 05828 /** 05829 * @brief FIFO overrun status.[get] 05830 * 05831 * @param ctx read / write interface definitions 05832 * @param val change the values of fifo_over_run_latched in 05833 * reg FIFO_STATUS2 05834 * 05835 */ 05836 int32_t lsm6dso_fifo_ovr_flag_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05837 { 05838 lsm6dso_fifo_status2_t reg; 05839 int32_t ret; 05840 05841 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)®, 1); 05842 *val = reg.fifo_ovr_ia; 05843 05844 return ret; 05845 } 05846 05847 /** 05848 * @brief FIFO watermark status.[get] 05849 * 05850 * @param ctx read / write interface definitions 05851 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2 05852 * 05853 */ 05854 int32_t lsm6dso_fifo_wtm_flag_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05855 { 05856 lsm6dso_fifo_status2_t reg; 05857 int32_t ret; 05858 05859 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t*)®, 1); 05860 *val = reg.fifo_wtm_ia; 05861 05862 return ret; 05863 } 05864 05865 /** 05866 * @brief Identifies the sensor in FIFO_DATA_OUT.[get] 05867 * 05868 * @param ctx read / write interface definitions 05869 * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG 05870 * 05871 */ 05872 int32_t lsm6dso_fifo_sensor_tag_get(lsm6dso_ctx_t *ctx, 05873 lsm6dso_fifo_tag_t *val) 05874 { 05875 lsm6dso_fifo_data_out_tag_t reg; 05876 int32_t ret; 05877 05878 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_TAG, (uint8_t*)®, 1); 05879 switch (reg.tag_sensor) { 05880 case LSM6DSO_GYRO_NC_TAG: 05881 *val = LSM6DSO_GYRO_NC_TAG; 05882 break; 05883 case LSM6DSO_XL_NC_TAG: 05884 *val = LSM6DSO_XL_NC_TAG; 05885 break; 05886 case LSM6DSO_TEMPERATURE_TAG: 05887 *val = LSM6DSO_TEMPERATURE_TAG; 05888 break; 05889 case LSM6DSO_CFG_CHANGE_TAG: 05890 *val = LSM6DSO_CFG_CHANGE_TAG; 05891 break; 05892 case LSM6DSO_XL_NC_T_2_TAG: 05893 *val = LSM6DSO_XL_NC_T_2_TAG; 05894 break; 05895 case LSM6DSO_XL_NC_T_1_TAG: 05896 *val = LSM6DSO_XL_NC_T_1_TAG; 05897 break; 05898 case LSM6DSO_XL_2XC_TAG: 05899 *val = LSM6DSO_XL_2XC_TAG; 05900 break; 05901 case LSM6DSO_XL_3XC_TAG: 05902 *val = LSM6DSO_XL_3XC_TAG; 05903 break; 05904 case LSM6DSO_GYRO_NC_T_2_TAG: 05905 *val = LSM6DSO_GYRO_NC_T_2_TAG; 05906 break; 05907 case LSM6DSO_GYRO_NC_T_1_TAG: 05908 *val = LSM6DSO_GYRO_NC_T_1_TAG; 05909 break; 05910 case LSM6DSO_GYRO_2XC_TAG: 05911 *val = LSM6DSO_GYRO_2XC_TAG; 05912 break; 05913 case LSM6DSO_GYRO_3XC_TAG: 05914 *val = LSM6DSO_GYRO_3XC_TAG; 05915 break; 05916 case LSM6DSO_SENSORHUB_SLAVE0_TAG: 05917 *val = LSM6DSO_SENSORHUB_SLAVE0_TAG; 05918 break; 05919 case LSM6DSO_SENSORHUB_SLAVE1_TAG: 05920 *val = LSM6DSO_SENSORHUB_SLAVE1_TAG; 05921 break; 05922 case LSM6DSO_SENSORHUB_SLAVE2_TAG: 05923 *val = LSM6DSO_SENSORHUB_SLAVE2_TAG; 05924 break; 05925 case LSM6DSO_SENSORHUB_SLAVE3_TAG: 05926 *val = LSM6DSO_SENSORHUB_SLAVE3_TAG; 05927 break; 05928 case LSM6DSO_STEP_CPUNTER_TAG: 05929 *val = LSM6DSO_STEP_CPUNTER_TAG; 05930 break; 05931 case LSM6DSO_GAME_ROTATION_TAG: 05932 *val = LSM6DSO_GAME_ROTATION_TAG; 05933 break; 05934 case LSM6DSO_GEOMAG_ROTATION_TAG: 05935 *val = LSM6DSO_GEOMAG_ROTATION_TAG; 05936 break; 05937 case LSM6DSO_ROTATION_TAG: 05938 *val = LSM6DSO_ROTATION_TAG; 05939 break; 05940 case LSM6DSO_SENSORHUB_NACK_TAG: 05941 *val = LSM6DSO_SENSORHUB_NACK_TAG; 05942 break; 05943 default: 05944 *val = LSM6DSO_GYRO_NC_TAG; 05945 break; 05946 } 05947 return ret; 05948 } 05949 05950 /** 05951 * @brief : Enable FIFO batching of pedometer embedded 05952 * function values.[set] 05953 * 05954 * @param ctx read / write interface definitions 05955 * @param val change the values of gbias_fifo_en in 05956 * reg LSM6DSO_EMB_FUNC_FIFO_CFG 05957 * 05958 */ 05959 int32_t lsm6dso_fifo_pedo_batch_set(lsm6dso_ctx_t *ctx, uint8_t val) 05960 { 05961 lsm6dso_emb_func_fifo_cfg_t reg; 05962 int32_t ret; 05963 05964 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 05965 if (ret == 0) { 05966 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t*)®, 1); 05967 } 05968 if (ret == 0) { 05969 reg.pedo_fifo_en = val; 05970 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, 05971 (uint8_t*)®, 1); 05972 } 05973 if (ret == 0) { 05974 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 05975 } 05976 return ret; 05977 } 05978 05979 /** 05980 * @brief Enable FIFO batching of pedometer embedded function values.[get] 05981 * 05982 * @param ctx read / write interface definitions 05983 * @param val change the values of pedo_fifo_en in 05984 * reg LSM6DSO_EMB_FUNC_FIFO_CFG 05985 * 05986 */ 05987 int32_t lsm6dso_fifo_pedo_batch_get(lsm6dso_ctx_t *ctx, uint8_t *val) 05988 { 05989 lsm6dso_emb_func_fifo_cfg_t reg; 05990 int32_t ret; 05991 05992 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 05993 if (ret == 0) { 05994 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t*)®, 1); 05995 } 05996 if (ret == 0) { 05997 *val = reg.pedo_fifo_en; 05998 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 05999 } 06000 return ret; 06001 } 06002 06003 /** 06004 * @brief Enable FIFO batching data of first slave.[set] 06005 * 06006 * @param ctx read / write interface definitions 06007 * @param val change the values of batch_ext_sens_0_en in 06008 * reg SLV0_CONFIG 06009 * 06010 */ 06011 int32_t lsm6dso_sh_batch_slave_0_set(lsm6dso_ctx_t *ctx, uint8_t val) 06012 { 06013 lsm6dso_slv0_config_t reg; 06014 int32_t ret; 06015 06016 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06017 if (ret == 0) { 06018 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)®, 1); 06019 } 06020 if (ret == 0) { 06021 reg.batch_ext_sens_0_en = val; 06022 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)®, 1); 06023 } 06024 if (ret == 0) { 06025 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06026 } 06027 return ret; 06028 } 06029 06030 /** 06031 * @brief Enable FIFO batching data of first slave.[get] 06032 * 06033 * @param ctx read / write interface definitions 06034 * @param val change the values of batch_ext_sens_0_en in 06035 * reg SLV0_CONFIG 06036 * 06037 */ 06038 int32_t lsm6dso_sh_batch_slave_0_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06039 { 06040 lsm6dso_slv0_config_t reg; 06041 int32_t ret; 06042 06043 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06044 if (ret == 0) { 06045 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t*)®, 1); 06046 } 06047 if (ret == 0) { 06048 *val = reg.batch_ext_sens_0_en; 06049 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06050 } 06051 return ret; 06052 } 06053 06054 /** 06055 * @brief Enable FIFO batching data of second slave.[set] 06056 * 06057 * @param ctx read / write interface definitions 06058 * @param val change the values of batch_ext_sens_1_en in 06059 * reg SLV1_CONFIG 06060 * 06061 */ 06062 int32_t lsm6dso_sh_batch_slave_1_set(lsm6dso_ctx_t *ctx, uint8_t val) 06063 { 06064 lsm6dso_slv1_config_t reg; 06065 int32_t ret; 06066 06067 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06068 if (ret == 0) { 06069 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1); 06070 } 06071 if (ret == 0) { 06072 reg.batch_ext_sens_1_en = val; 06073 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1); 06074 } 06075 if (ret == 0) { 06076 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06077 } 06078 06079 return ret; 06080 } 06081 06082 /** 06083 * @brief Enable FIFO batching data of second slave.[get] 06084 * 06085 * @param ctx read / write interface definitions 06086 * @param val change the values of batch_ext_sens_1_en in 06087 * reg SLV1_CONFIG 06088 * 06089 */ 06090 int32_t lsm6dso_sh_batch_slave_1_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06091 { 06092 lsm6dso_slv1_config_t reg; 06093 int32_t ret; 06094 06095 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06096 if (ret == 0) { 06097 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1); 06098 *val = reg.batch_ext_sens_1_en; 06099 } 06100 if (ret == 0) { 06101 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06102 } 06103 return ret; 06104 } 06105 06106 /** 06107 * @brief Enable FIFO batching data of third slave.[set] 06108 * 06109 * @param ctx read / write interface definitions 06110 * @param val change the values of batch_ext_sens_2_en in 06111 * reg SLV2_CONFIG 06112 * 06113 */ 06114 int32_t lsm6dso_sh_batch_slave_2_set(lsm6dso_ctx_t *ctx, uint8_t val) 06115 { 06116 lsm6dso_slv2_config_t reg; 06117 int32_t ret; 06118 06119 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06120 06121 if (ret == 0) { 06122 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)®, 1); 06123 } 06124 if (ret == 0) { 06125 reg.batch_ext_sens_2_en = val; 06126 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)®, 1); 06127 } 06128 if (ret == 0) { 06129 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06130 } 06131 return ret; 06132 } 06133 06134 /** 06135 * @brief Enable FIFO batching data of third slave.[get] 06136 * 06137 * @param ctx read / write interface definitions 06138 * @param val change the values of batch_ext_sens_2_en in 06139 * reg SLV2_CONFIG 06140 * 06141 */ 06142 int32_t lsm6dso_sh_batch_slave_2_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06143 { 06144 lsm6dso_slv2_config_t reg; 06145 int32_t ret; 06146 06147 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06148 if (ret == 0) { 06149 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t*)®, 1); 06150 } 06151 if (ret == 0) { 06152 *val = reg.batch_ext_sens_2_en; 06153 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06154 } 06155 06156 return ret; 06157 } 06158 06159 /** 06160 * @brief Enable FIFO batching data of fourth slave.[set] 06161 * 06162 * @param ctx read / write interface definitions 06163 * @param val change the values of batch_ext_sens_3_en 06164 * in reg SLV3_CONFIG 06165 * 06166 */ 06167 int32_t lsm6dso_sh_batch_slave_3_set(lsm6dso_ctx_t *ctx, uint8_t val) 06168 { 06169 lsm6dso_slv3_config_t reg; 06170 int32_t ret; 06171 06172 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06173 if (ret == 0) { 06174 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)®, 1); 06175 } 06176 if (ret == 0) { 06177 reg.batch_ext_sens_3_en = val; 06178 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)®, 1); 06179 } 06180 if (ret == 0) { 06181 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06182 } 06183 06184 return ret; 06185 } 06186 06187 /** 06188 * @brief Enable FIFO batching data of fourth slave.[get] 06189 * 06190 * @param ctx read / write interface definitions 06191 * @param val change the values of batch_ext_sens_3_en in 06192 * reg SLV3_CONFIG 06193 * 06194 */ 06195 int32_t lsm6dso_sh_batch_slave_3_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06196 { 06197 lsm6dso_slv3_config_t reg; 06198 int32_t ret; 06199 06200 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 06201 if (ret == 0) { 06202 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t*)®, 1); 06203 } 06204 if (ret == 0) { 06205 *val = reg.batch_ext_sens_3_en; 06206 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06207 } 06208 06209 return ret; 06210 } 06211 06212 /** 06213 * @} 06214 * 06215 */ 06216 06217 /** 06218 * @defgroup LSM6DSO_DEN_functionality 06219 * @brief This section groups all the functions concerning 06220 * DEN functionality. 06221 * @{ 06222 * 06223 */ 06224 06225 /** 06226 * @brief DEN functionality marking mode.[set] 06227 * 06228 * @param ctx read / write interface definitions 06229 * @param val change the values of den_mode in reg CTRL6_C 06230 * 06231 */ 06232 int32_t lsm6dso_den_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_den_mode_t val) 06233 { 06234 lsm6dso_ctrl6_c_t reg; 06235 int32_t ret; 06236 06237 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1); 06238 if (ret == 0) { 06239 reg.den_mode = (uint8_t)val; 06240 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1); 06241 } 06242 06243 return ret; 06244 } 06245 06246 /** 06247 * @brief DEN functionality marking mode.[get] 06248 * 06249 * @param ctx read / write interface definitions 06250 * @param val Get the values of den_mode in reg CTRL6_C 06251 * 06252 */ 06253 int32_t lsm6dso_den_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_den_mode_t *val) 06254 { 06255 lsm6dso_ctrl6_c_t reg; 06256 int32_t ret; 06257 06258 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t*)®, 1); 06259 06260 switch (reg.den_mode) { 06261 case LSM6DSO_DEN_DISABLE: 06262 *val = LSM6DSO_DEN_DISABLE; 06263 break; 06264 case LSM6DSO_LEVEL_FIFO: 06265 *val = LSM6DSO_LEVEL_FIFO; 06266 break; 06267 case LSM6DSO_LEVEL_LETCHED: 06268 *val = LSM6DSO_LEVEL_LETCHED; 06269 break; 06270 case LSM6DSO_LEVEL_TRIGGER: 06271 *val = LSM6DSO_LEVEL_TRIGGER; 06272 break; 06273 case LSM6DSO_EDGE_TRIGGER: 06274 *val = LSM6DSO_EDGE_TRIGGER; 06275 break; 06276 default: 06277 *val = LSM6DSO_DEN_DISABLE; 06278 break; 06279 } 06280 return ret; 06281 } 06282 06283 /** 06284 * @brief DEN active level configuration.[set] 06285 * 06286 * @param ctx read / write interface definitions 06287 * @param val change the values of den_lh in reg CTRL9_XL 06288 * 06289 */ 06290 int32_t lsm6dso_den_polarity_set(lsm6dso_ctx_t *ctx, lsm6dso_den_lh_t val) 06291 { 06292 lsm6dso_ctrl9_xl_t reg; 06293 int32_t ret; 06294 06295 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06296 if (ret == 0) { 06297 reg.den_lh = (uint8_t)val; 06298 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06299 } 06300 06301 return ret; 06302 } 06303 06304 /** 06305 * @brief DEN active level configuration.[get] 06306 * 06307 * @param ctx read / write interface definitions 06308 * @param val Get the values of den_lh in reg CTRL9_XL 06309 * 06310 */ 06311 int32_t lsm6dso_den_polarity_get(lsm6dso_ctx_t *ctx, lsm6dso_den_lh_t *val) 06312 { 06313 lsm6dso_ctrl9_xl_t reg; 06314 int32_t ret; 06315 06316 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06317 06318 switch (reg.den_lh) { 06319 case LSM6DSO_DEN_ACT_LOW: 06320 *val = LSM6DSO_DEN_ACT_LOW; 06321 break; 06322 case LSM6DSO_DEN_ACT_HIGH: 06323 *val = LSM6DSO_DEN_ACT_HIGH; 06324 break; 06325 default: 06326 *val = LSM6DSO_DEN_ACT_LOW; 06327 break; 06328 } 06329 return ret; 06330 } 06331 06332 /** 06333 * @brief DEN enable.[set] 06334 * 06335 * @param ctx read / write interface definitions 06336 * @param val change the values of den_xl_g in reg CTRL9_XL 06337 * 06338 */ 06339 int32_t lsm6dso_den_enable_set(lsm6dso_ctx_t *ctx, lsm6dso_den_xl_g_t val) 06340 { 06341 lsm6dso_ctrl9_xl_t reg; 06342 int32_t ret; 06343 06344 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06345 if (ret == 0) { 06346 reg.den_xl_g = (uint8_t)val; 06347 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06348 } 06349 06350 return ret; 06351 } 06352 06353 /** 06354 * @brief DEN enable.[get] 06355 * 06356 * @param ctx read / write interface definitions 06357 * @param val Get the values of den_xl_g in reg CTRL9_XL 06358 * 06359 */ 06360 int32_t lsm6dso_den_enable_get(lsm6dso_ctx_t *ctx, lsm6dso_den_xl_g_t *val) 06361 { 06362 lsm6dso_ctrl9_xl_t reg; 06363 int32_t ret; 06364 06365 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06366 06367 switch (reg.den_xl_g) { 06368 case LSM6DSO_STAMP_IN_GY_DATA: 06369 *val = LSM6DSO_STAMP_IN_GY_DATA; 06370 break; 06371 case LSM6DSO_STAMP_IN_XL_DATA: 06372 *val = LSM6DSO_STAMP_IN_XL_DATA; 06373 break; 06374 case LSM6DSO_STAMP_IN_GY_XL_DATA: 06375 *val = LSM6DSO_STAMP_IN_GY_XL_DATA; 06376 break; 06377 default: 06378 *val = LSM6DSO_STAMP_IN_GY_DATA; 06379 break; 06380 } 06381 return ret; 06382 } 06383 06384 /** 06385 * @brief DEN value stored in LSB of X-axis.[set] 06386 * 06387 * @param ctx read / write interface definitions 06388 * @param val change the values of den_z in reg CTRL9_XL 06389 * 06390 */ 06391 int32_t lsm6dso_den_mark_axis_x_set(lsm6dso_ctx_t *ctx, uint8_t val) 06392 { 06393 lsm6dso_ctrl9_xl_t reg; 06394 int32_t ret; 06395 06396 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06397 if (ret == 0) { 06398 reg.den_z = val; 06399 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06400 } 06401 06402 return ret; 06403 } 06404 06405 /** 06406 * @brief DEN value stored in LSB of X-axis.[get] 06407 * 06408 * @param ctx read / write interface definitions 06409 * @param val change the values of den_z in reg CTRL9_XL 06410 * 06411 */ 06412 int32_t lsm6dso_den_mark_axis_x_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06413 { 06414 lsm6dso_ctrl9_xl_t reg; 06415 int32_t ret; 06416 06417 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06418 *val = reg.den_z; 06419 06420 return ret; 06421 } 06422 06423 /** 06424 * @brief DEN value stored in LSB of Y-axis.[set] 06425 * 06426 * @param ctx read / write interface definitions 06427 * @param val change the values of den_y in reg CTRL9_XL 06428 * 06429 */ 06430 int32_t lsm6dso_den_mark_axis_y_set(lsm6dso_ctx_t *ctx, uint8_t val) 06431 { 06432 lsm6dso_ctrl9_xl_t reg; 06433 int32_t ret; 06434 06435 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06436 if (ret == 0) { 06437 reg.den_y = val; 06438 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06439 } 06440 06441 return ret; 06442 } 06443 06444 /** 06445 * @brief DEN value stored in LSB of Y-axis.[get] 06446 * 06447 * @param ctx read / write interface definitions 06448 * @param val change the values of den_y in reg CTRL9_XL 06449 * 06450 */ 06451 int32_t lsm6dso_den_mark_axis_y_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06452 { 06453 lsm6dso_ctrl9_xl_t reg; 06454 int32_t ret; 06455 06456 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06457 *val = reg.den_y; 06458 06459 return ret; 06460 } 06461 06462 /** 06463 * @brief DEN value stored in LSB of Z-axis.[set] 06464 * 06465 * @param ctx read / write interface definitions 06466 * @param val change the values of den_x in reg CTRL9_XL 06467 * 06468 */ 06469 int32_t lsm6dso_den_mark_axis_z_set(lsm6dso_ctx_t *ctx, uint8_t val) 06470 { 06471 lsm6dso_ctrl9_xl_t reg; 06472 int32_t ret; 06473 06474 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06475 if (ret == 0) { 06476 reg.den_x = val; 06477 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06478 } 06479 06480 return ret; 06481 } 06482 06483 /** 06484 * @brief DEN value stored in LSB of Z-axis.[get] 06485 * 06486 * @param ctx read / write interface definitions 06487 * @param val change the values of den_x in reg CTRL9_XL 06488 * 06489 */ 06490 int32_t lsm6dso_den_mark_axis_z_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06491 { 06492 lsm6dso_ctrl9_xl_t reg; 06493 int32_t ret; 06494 06495 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t*)®, 1); 06496 *val = reg.den_x; 06497 06498 return ret; 06499 } 06500 06501 /** 06502 * @} 06503 * 06504 */ 06505 06506 /** 06507 * @defgroup LSM6DSO_Pedometer 06508 * @brief This section groups all the functions that manage pedometer. 06509 * @{ 06510 * 06511 */ 06512 06513 /** 06514 * @brief Enable pedometer algorithm.[set] 06515 * 06516 * @param ctx read / write interface definitions 06517 * @param val turn on and configure pedometer 06518 * 06519 */ 06520 int32_t lsm6dso_pedo_sens_set(lsm6dso_ctx_t *ctx, lsm6dso_pedo_md_t val) 06521 { 06522 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg; 06523 int32_t ret; 06524 06525 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, 06526 (uint8_t*)&pedo_cmd_reg); 06527 06528 if (ret == 0) { 06529 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U)>>4; 06530 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U)>>5; 06531 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG, 06532 (uint8_t*)&pedo_cmd_reg); 06533 } 06534 return ret; 06535 } 06536 06537 /** 06538 * @brief Enable pedometer algorithm.[get] 06539 * 06540 * @param ctx read / write interface definitions 06541 * @param val turn on and configure pedometer 06542 * 06543 */ 06544 int32_t lsm6dso_pedo_sens_get(lsm6dso_ctx_t *ctx, lsm6dso_pedo_md_t *val) 06545 { 06546 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg; 06547 int32_t ret; 06548 06549 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, 06550 (uint8_t*)&pedo_cmd_reg); 06551 switch ( (pedo_cmd_reg.ad_det_en <<5) | (pedo_cmd_reg.fp_rejection_en << 4) ) { 06552 case LSM6DSO_PEDO_BASE_MODE: 06553 *val = LSM6DSO_PEDO_BASE_MODE; 06554 break; 06555 case LSM6DSO_FALSE_STEP_REJ: 06556 *val = LSM6DSO_FALSE_STEP_REJ; 06557 break; 06558 case LSM6DSO_FALSE_STEP_REJ_ADV_MODE: 06559 *val = LSM6DSO_FALSE_STEP_REJ_ADV_MODE; 06560 break; 06561 default: 06562 *val = LSM6DSO_PEDO_BASE_MODE; 06563 break; 06564 } 06565 return ret; 06566 } 06567 06568 /** 06569 * @brief Interrupt status bit for step detection.[get] 06570 * 06571 * @param ctx read / write interface definitions 06572 * @param val change the values of is_step_det in reg EMB_FUNC_STATUS 06573 * 06574 */ 06575 int32_t lsm6dso_pedo_step_detect_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06576 { 06577 lsm6dso_emb_func_status_t reg; 06578 int32_t ret; 06579 06580 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 06581 if (ret == 0) { 06582 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)®, 1); 06583 } 06584 if (ret == 0) { 06585 *val = reg.is_step_det; 06586 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06587 } 06588 06589 return ret; 06590 } 06591 06592 /** 06593 * @brief Pedometer debounce configuration register (r/w).[set] 06594 * 06595 * @param ctx read / write interface definitions 06596 * @param buff buffer that contains data to write 06597 * 06598 */ 06599 int32_t lsm6dso_pedo_debounce_steps_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 06600 { 06601 int32_t ret; 06602 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff); 06603 return ret; 06604 } 06605 06606 /** 06607 * @brief Pedometer debounce configuration register (r/w).[get] 06608 * 06609 * @param ctx read / write interface definitions 06610 * @param buff buffer that stores data read 06611 * 06612 */ 06613 int32_t lsm6dso_pedo_debounce_steps_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 06614 { 06615 int32_t ret; 06616 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff); 06617 return ret; 06618 } 06619 06620 /** 06621 * @brief Time period register for step detection on delta time (r/w).[set] 06622 * 06623 * @param ctx read / write interface definitions 06624 * @param buff buffer that contains data to write 06625 * 06626 */ 06627 int32_t lsm6dso_pedo_steps_period_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 06628 { 06629 int32_t ret; 06630 uint8_t index; 06631 06632 index = 0x00U; 06633 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]); 06634 if (ret == 0) { 06635 index++; 06636 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H, 06637 &buff[index]); 06638 } 06639 return ret; 06640 } 06641 06642 /** 06643 * @brief Time period register for step detection on delta time (r/w).[get] 06644 * 06645 * @param ctx read / write interface definitions 06646 * @param buff buffer that stores data read 06647 * 06648 */ 06649 int32_t lsm6dso_pedo_steps_period_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 06650 { 06651 int32_t ret; 06652 uint8_t index; 06653 06654 index = 0x00U; 06655 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[index]); 06656 if (ret == 0) { 06657 index++; 06658 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H, 06659 &buff[index]); 06660 } 06661 return ret; 06662 } 06663 06664 /** 06665 * @brief Set when user wants to generate interrupt on count overflow 06666 * event/every step.[set] 06667 * 06668 * @param ctx read / write interface definitions 06669 * @param val change the values of carry_count_en in reg PEDO_CMD_REG 06670 * 06671 */ 06672 int32_t lsm6dso_pedo_int_mode_set(lsm6dso_ctx_t *ctx, 06673 lsm6dso_carry_count_en_t val) 06674 { 06675 lsm6dso_pedo_cmd_reg_t reg; 06676 int32_t ret; 06677 06678 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t*)®); 06679 if (ret == 0) { 06680 reg.carry_count_en = (uint8_t)val; 06681 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG, 06682 (uint8_t*)®); 06683 } 06684 return ret; 06685 } 06686 06687 /** 06688 * @brief Set when user wants to generate interrupt on count overflow 06689 * event/every step.[get] 06690 * 06691 * @param ctx read / write interface definitions 06692 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG 06693 * 06694 */ 06695 int32_t lsm6dso_pedo_int_mode_get(lsm6dso_ctx_t *ctx, 06696 lsm6dso_carry_count_en_t *val) 06697 { 06698 lsm6dso_pedo_cmd_reg_t reg; 06699 int32_t ret; 06700 06701 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG, (uint8_t*)®); 06702 switch (reg.carry_count_en) { 06703 case LSM6DSO_EVERY_STEP: 06704 *val = LSM6DSO_EVERY_STEP; 06705 break; 06706 case LSM6DSO_COUNT_OVERFLOW: 06707 *val = LSM6DSO_COUNT_OVERFLOW; 06708 break; 06709 default: 06710 *val = LSM6DSO_EVERY_STEP; 06711 break; 06712 } 06713 return ret; 06714 } 06715 06716 /** 06717 * @} 06718 * 06719 */ 06720 06721 /** 06722 * @defgroup LSM6DSO_significant_motion 06723 * @brief This section groups all the functions that manage the 06724 * significant motion detection. 06725 * @{ 06726 * 06727 */ 06728 06729 /** 06730 * @brief Interrupt status bit for significant motion detection.[get] 06731 * 06732 * @param ctx read / write interface definitions 06733 * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS 06734 * 06735 */ 06736 int32_t lsm6dso_motion_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06737 { 06738 lsm6dso_emb_func_status_t reg; 06739 int32_t ret; 06740 06741 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 06742 if (ret == 0) { 06743 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)®, 1); 06744 } 06745 if (ret == 0) { 06746 *val = reg.is_sigmot; 06747 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06748 } 06749 06750 return ret; 06751 } 06752 06753 /** 06754 * @} 06755 * 06756 */ 06757 06758 /** 06759 * @defgroup LSM6DSO_tilt_detection 06760 * @brief This section groups all the functions that manage the tilt 06761 * event detection. 06762 * @{ 06763 * 06764 */ 06765 06766 /** 06767 * @brief Interrupt status bit for tilt detection.[get] 06768 * 06769 * @param ctx read / write interface definitions 06770 * @param val change the values of is_tilt in reg EMB_FUNC_STATUS 06771 * 06772 */ 06773 int32_t lsm6dso_tilt_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 06774 { 06775 lsm6dso_emb_func_status_t reg; 06776 int32_t ret; 06777 06778 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 06779 if (ret == 0) { 06780 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)®, 1); 06781 } 06782 if (ret == 0) { 06783 *val = reg.is_tilt; 06784 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 06785 } 06786 06787 return ret; 06788 } 06789 06790 /** 06791 * @} 06792 * 06793 */ 06794 06795 /** 06796 * @defgroup LSM6DSO_ magnetometer_sensor 06797 * @brief This section groups all the functions that manage additional 06798 * magnetometer sensor. 06799 * @{ 06800 * 06801 */ 06802 06803 /** 06804 * @brief External magnetometer sensitivity value register.[set] 06805 * 06806 * @param ctx read / write interface definitions 06807 * @param buff buffer that contains data to write 06808 * 06809 */ 06810 int32_t lsm6dso_mag_sensitivity_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 06811 { 06812 int32_t ret; 06813 uint8_t index; 06814 06815 index = 0x00U; 06816 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L, 06817 &buff[index]); 06818 if (ret == 0) { 06819 index++; 06820 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H, 06821 &buff[index]); 06822 } 06823 06824 return ret; 06825 } 06826 06827 /** 06828 * @brief External magnetometer sensitivity value register.[get] 06829 * 06830 * @param ctx read / write interface definitions 06831 * @param buff buffer that stores data read 06832 * 06833 */ 06834 int32_t lsm6dso_mag_sensitivity_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 06835 { 06836 int32_t ret; 06837 uint8_t index; 06838 06839 index = 0x00U; 06840 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L, 06841 &buff[index]); 06842 if (ret == 0) { 06843 index++; 06844 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H, 06845 &buff[index]); 06846 } 06847 06848 return ret; 06849 } 06850 06851 /** 06852 * @brief Offset for hard-iron compensation register (r/w).[set] 06853 * 06854 * @param ctx read / write interface definitions 06855 * @param buff buffer that contains data to write 06856 * 06857 */ 06858 int32_t lsm6dso_mag_offset_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 06859 { 06860 int32_t ret; 06861 uint8_t index; 06862 06863 index = 0x00U; 06864 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]); 06865 if (ret == 0) { 06866 index++; 06867 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]); 06868 } 06869 if (ret == 0) { 06870 index++; 06871 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]); 06872 } 06873 if (ret == 0) { 06874 index++; 06875 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]); 06876 } 06877 if (ret == 0) { 06878 index++; 06879 06880 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]); 06881 } 06882 if (ret == 0) { 06883 index++; 06884 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]); 06885 } 06886 06887 return ret; 06888 } 06889 06890 /** 06891 * @brief Offset for hard-iron compensation register (r/w).[get] 06892 * 06893 * @param ctx read / write interface definitions 06894 * @param buff buffer that stores data read 06895 * 06896 */ 06897 int32_t lsm6dso_mag_offset_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 06898 { 06899 int32_t ret; 06900 uint8_t index; 06901 06902 index = 0x00U; 06903 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[index]); 06904 if (ret == 0) { 06905 index++; 06906 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[index]); 06907 } 06908 if (ret == 0) { 06909 index++; 06910 06911 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[index]); 06912 } 06913 if (ret == 0) { 06914 index++; 06915 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[index]); 06916 } 06917 if (ret == 0) { 06918 index++; 06919 06920 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[index]); 06921 } 06922 if (ret == 0) { 06923 index++; 06924 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[index]); 06925 } 06926 return ret; 06927 } 06928 06929 /** 06930 * @brief Soft-iron (3x3 symmetric) matrix correction 06931 * register (r/w). The value is expressed as 06932 * half-precision floating-point format: 06933 * SEEEEEFFFFFFFFFF 06934 * S: 1 sign bit; 06935 * E: 5 exponent bits; 06936 * F: 10 fraction bits).[set] 06937 * 06938 * @param ctx read / write interface definitions 06939 * @param buff buffer that contains data to write 06940 * 06941 */ 06942 int32_t lsm6dso_mag_soft_iron_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 06943 { 06944 int32_t ret; 06945 uint8_t index; 06946 06947 index = 0x00U; 06948 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]); 06949 if (ret == 0) { 06950 index++; 06951 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]); 06952 } 06953 if (ret == 0) { 06954 index++; 06955 06956 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]); 06957 } 06958 if (ret == 0) { 06959 index++; 06960 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]); 06961 } 06962 if (ret == 0) { 06963 index++; 06964 06965 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]); 06966 } 06967 if (ret == 0) { 06968 index++; 06969 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]); 06970 } 06971 if (ret == 0) { 06972 index++; 06973 06974 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]); 06975 } 06976 if (ret == 0) { 06977 index++; 06978 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]); 06979 } 06980 if (ret == 0) { 06981 index++; 06982 06983 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]); 06984 } 06985 if (ret == 0) { 06986 index++; 06987 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]); 06988 } 06989 if (ret == 0) { 06990 index++; 06991 06992 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]); 06993 } 06994 if (ret == 0) { 06995 index++; 06996 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]); 06997 } 06998 06999 return ret; 07000 } 07001 07002 /** 07003 * @brief Soft-iron (3x3 symmetric) matrix 07004 * correction register (r/w). 07005 * The value is expressed as half-precision 07006 * floating-point format: 07007 * SEEEEEFFFFFFFFFF 07008 * S: 1 sign bit; 07009 * E: 5 exponent bits; 07010 * F: 10 fraction bits.[get] 07011 * 07012 * @param ctx read / write interface definitions 07013 * @param buff buffer that stores data read 07014 * 07015 */ 07016 int32_t lsm6dso_mag_soft_iron_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 07017 { 07018 int32_t ret; 07019 uint8_t index; 07020 07021 index = 0x00U; 07022 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]); 07023 if (ret == 0) { 07024 index++; 07025 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]); 07026 } 07027 if (ret == 0) { 07028 index++; 07029 07030 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]); 07031 } 07032 if (ret == 0) { 07033 index++; 07034 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]); 07035 } 07036 if (ret == 0) { 07037 index++; 07038 07039 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]); 07040 } 07041 if (ret == 0) { 07042 index++; 07043 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]); 07044 } 07045 if (ret == 0) { 07046 index++; 07047 07048 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]); 07049 } 07050 if (ret == 0) { 07051 index++; 07052 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]); 07053 } 07054 if (ret == 0) { 07055 index++; 07056 07057 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]); 07058 } 07059 if (ret == 0) { 07060 index++; 07061 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]); 07062 } 07063 if (ret == 0) { 07064 index++; 07065 07066 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]); 07067 } 07068 if (ret == 0) { 07069 index++; 07070 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]); 07071 } 07072 07073 return ret; 07074 } 07075 07076 /** 07077 * @brief Magnetometer Z-axis coordinates 07078 * rotation (to be aligned to 07079 * accelerometer/gyroscope axes 07080 * orientation).[set] 07081 * 07082 * @param ctx read / write interface definitions 07083 * @param val change the values of mag_z_axis in reg MAG_CFG_A 07084 * 07085 */ 07086 int32_t lsm6dso_mag_z_orient_set(lsm6dso_ctx_t *ctx, lsm6dso_mag_z_axis_t val) 07087 { 07088 lsm6dso_mag_cfg_a_t reg; 07089 int32_t ret; 07090 07091 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)®); 07092 if (ret == 0) { 07093 reg.mag_z_axis = (uint8_t) val; 07094 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)®); 07095 } 07096 07097 return ret; 07098 } 07099 07100 /** 07101 * @brief Magnetometer Z-axis coordinates 07102 * rotation (to be aligned to 07103 * accelerometer/gyroscope axes 07104 * orientation).[get] 07105 * 07106 * @param ctx read / write interface definitions 07107 * @param val Get the values of mag_z_axis in reg MAG_CFG_A 07108 * 07109 */ 07110 int32_t lsm6dso_mag_z_orient_get(lsm6dso_ctx_t *ctx, 07111 lsm6dso_mag_z_axis_t *val) 07112 { 07113 lsm6dso_mag_cfg_a_t reg; 07114 int32_t ret; 07115 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)®); 07116 switch (reg.mag_z_axis) { 07117 case LSM6DSO_Z_EQ_Y: 07118 *val = LSM6DSO_Z_EQ_Y; 07119 break; 07120 case LSM6DSO_Z_EQ_MIN_Y: 07121 *val = LSM6DSO_Z_EQ_MIN_Y; 07122 break; 07123 case LSM6DSO_Z_EQ_X: 07124 *val = LSM6DSO_Z_EQ_X; 07125 break; 07126 case LSM6DSO_Z_EQ_MIN_X: 07127 *val = LSM6DSO_Z_EQ_MIN_X; 07128 break; 07129 case LSM6DSO_Z_EQ_MIN_Z: 07130 *val = LSM6DSO_Z_EQ_MIN_Z; 07131 break; 07132 case LSM6DSO_Z_EQ_Z: 07133 *val = LSM6DSO_Z_EQ_Z; 07134 break; 07135 default: 07136 *val = LSM6DSO_Z_EQ_Y; 07137 break; 07138 } 07139 return ret; 07140 } 07141 07142 /** 07143 * @brief Magnetometer Y-axis coordinates 07144 * rotation (to be aligned to 07145 * accelerometer/gyroscope axes 07146 * orientation).[set] 07147 * 07148 * @param ctx read / write interface definitions 07149 * @param val change the values of mag_y_axis in reg MAG_CFG_A 07150 * 07151 */ 07152 int32_t lsm6dso_mag_y_orient_set(lsm6dso_ctx_t *ctx, 07153 lsm6dso_mag_y_axis_t val) 07154 { 07155 lsm6dso_mag_cfg_a_t reg; 07156 int32_t ret; 07157 07158 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)®); 07159 if (ret == 0) { 07160 reg.mag_y_axis = (uint8_t)val; 07161 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A,(uint8_t*) ®); 07162 } 07163 return ret; 07164 } 07165 07166 /** 07167 * @brief Magnetometer Y-axis coordinates 07168 * rotation (to be aligned to 07169 * accelerometer/gyroscope axes 07170 * orientation).[get] 07171 * 07172 * @param ctx read / write interface definitions 07173 * @param val Get the values of mag_y_axis in reg MAG_CFG_A 07174 * 07175 */ 07176 int32_t lsm6dso_mag_y_orient_get(lsm6dso_ctx_t *ctx, 07177 lsm6dso_mag_y_axis_t *val) 07178 { 07179 lsm6dso_mag_cfg_a_t reg; 07180 int32_t ret; 07181 07182 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t*)®); 07183 switch (reg.mag_y_axis) { 07184 case LSM6DSO_Y_EQ_Y: 07185 *val = LSM6DSO_Y_EQ_Y; 07186 break; 07187 case LSM6DSO_Y_EQ_MIN_Y: 07188 *val = LSM6DSO_Y_EQ_MIN_Y; 07189 break; 07190 case LSM6DSO_Y_EQ_X: 07191 *val = LSM6DSO_Y_EQ_X; 07192 break; 07193 case LSM6DSO_Y_EQ_MIN_X: 07194 *val = LSM6DSO_Y_EQ_MIN_X; 07195 break; 07196 case LSM6DSO_Y_EQ_MIN_Z: 07197 *val = LSM6DSO_Y_EQ_MIN_Z; 07198 break; 07199 case LSM6DSO_Y_EQ_Z: 07200 *val = LSM6DSO_Y_EQ_Z; 07201 break; 07202 default: 07203 *val = LSM6DSO_Y_EQ_Y; 07204 break; 07205 } 07206 return ret; 07207 } 07208 07209 /** 07210 * @brief Magnetometer X-axis coordinates 07211 * rotation (to be aligned to 07212 * accelerometer/gyroscope axes 07213 * orientation).[set] 07214 * 07215 * @param ctx read / write interface definitions 07216 * @param val change the values of mag_x_axis in reg MAG_CFG_B 07217 * 07218 */ 07219 int32_t lsm6dso_mag_x_orient_set(lsm6dso_ctx_t *ctx, 07220 lsm6dso_mag_x_axis_t val) 07221 { 07222 lsm6dso_mag_cfg_b_t reg; 07223 int32_t ret; 07224 07225 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)®); 07226 if (ret == 0) { 07227 reg.mag_x_axis = (uint8_t)val; 07228 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)®); 07229 } 07230 return ret; 07231 } 07232 07233 /** 07234 * @brief Magnetometer X-axis coordinates 07235 * rotation (to be aligned to 07236 * accelerometer/gyroscope axes 07237 * orientation).[get] 07238 * 07239 * @param ctx read / write interface definitions 07240 * @param val Get the values of mag_x_axis in reg MAG_CFG_B 07241 * 07242 */ 07243 int32_t lsm6dso_mag_x_orient_get(lsm6dso_ctx_t *ctx, 07244 lsm6dso_mag_x_axis_t *val) 07245 { 07246 lsm6dso_mag_cfg_b_t reg; 07247 int32_t ret; 07248 07249 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t*)®); 07250 switch (reg.mag_x_axis) { 07251 case LSM6DSO_X_EQ_Y: 07252 *val = LSM6DSO_X_EQ_Y; 07253 break; 07254 case LSM6DSO_X_EQ_MIN_Y: 07255 *val = LSM6DSO_X_EQ_MIN_Y; 07256 break; 07257 case LSM6DSO_X_EQ_X: 07258 *val = LSM6DSO_X_EQ_X; 07259 break; 07260 case LSM6DSO_X_EQ_MIN_X: 07261 *val = LSM6DSO_X_EQ_MIN_X; 07262 break; 07263 case LSM6DSO_X_EQ_MIN_Z: 07264 *val = LSM6DSO_X_EQ_MIN_Z; 07265 break; 07266 case LSM6DSO_X_EQ_Z: 07267 *val = LSM6DSO_X_EQ_Z; 07268 break; 07269 default: 07270 *val = LSM6DSO_X_EQ_Y; 07271 break; 07272 } 07273 return ret; 07274 } 07275 07276 /** 07277 * @} 07278 * 07279 */ 07280 07281 /** 07282 * @defgroup LSM6DSO_finite_state_machine 07283 * @brief This section groups all the functions that manage the 07284 * state_machine. 07285 * @{ 07286 * 07287 */ 07288 07289 /** 07290 * @brief Interrupt status bit for FSM long counter 07291 * timeout interrupt event.[get] 07292 * 07293 * @param ctx read / write interface definitions 07294 * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS 07295 * 07296 */ 07297 int32_t lsm6dso_long_cnt_flag_data_ready_get(lsm6dso_ctx_t *ctx, uint8_t *val) 07298 { 07299 lsm6dso_emb_func_status_t reg; 07300 int32_t ret; 07301 07302 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07303 if (ret == 0) { 07304 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t*)®, 1); 07305 } 07306 if (ret == 0) { 07307 *val = reg.is_fsm_lc; 07308 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07309 } 07310 return ret; 07311 } 07312 07313 /** 07314 * @brief Final State Machine enable.[set] 07315 * 07316 * @param ctx read / write interface definitions 07317 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B 07318 * 07319 */ 07320 int32_t lsm6dso_fsm_enable_set(lsm6dso_ctx_t *ctx, 07321 lsm6dso_emb_fsm_enable_t *val) 07322 { 07323 int32_t ret; 07324 07325 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07326 if (ret == 0) { 07327 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_A, 07328 (uint8_t*)&val->fsm_enable_a, 1); 07329 } 07330 if (ret == 0) { 07331 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_B, 07332 (uint8_t*)&val->fsm_enable_b, 1); 07333 } 07334 if (ret == 0) { 07335 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07336 } 07337 07338 return ret; 07339 } 07340 07341 /** 07342 * @brief Final State Machine enable.[get] 07343 * 07344 * @param ctx read / write interface definitions 07345 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B 07346 * 07347 */ 07348 int32_t lsm6dso_fsm_enable_get(lsm6dso_ctx_t *ctx, 07349 lsm6dso_emb_fsm_enable_t *val) 07350 { 07351 int32_t ret; 07352 07353 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07354 if (ret == 0) { 07355 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t*) val, 2); 07356 } 07357 if (ret == 0) { 07358 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07359 } 07360 return ret; 07361 } 07362 07363 /** 07364 * @brief FSM long counter status register. Long counter value is an 07365 * unsigned integer value (16-bit format).[set] 07366 * 07367 * @param ctx read / write interface definitions 07368 * @param buff buffer that contains data to write 07369 * 07370 */ 07371 int32_t lsm6dso_long_cnt_set(lsm6dso_ctx_t *ctx, uint8_t *buff) 07372 { 07373 int32_t ret; 07374 07375 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07376 if (ret == 0) { 07377 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2); 07378 } 07379 if (ret == 0) { 07380 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07381 } 07382 07383 return ret; 07384 } 07385 07386 /** 07387 * @brief FSM long counter status register. Long counter value is an 07388 * unsigned integer value (16-bit format).[get] 07389 * 07390 * @param ctx read / write interface definitions 07391 * @param buff buffer that stores data read 07392 * 07393 */ 07394 int32_t lsm6dso_long_cnt_get(lsm6dso_ctx_t *ctx, uint8_t *buff) 07395 { 07396 int32_t ret; 07397 07398 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07399 if (ret == 0) { 07400 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2); 07401 } 07402 if (ret == 0) { 07403 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07404 } 07405 07406 return ret; 07407 } 07408 07409 /** 07410 * @brief Clear FSM long counter value.[set] 07411 * 07412 * @param ctx read / write interface definitions 07413 * @param val change the values of fsm_lc_clr in 07414 * reg FSM_LONG_COUNTER_CLEAR 07415 * 07416 */ 07417 int32_t lsm6dso_long_clr_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_lc_clr_t val) 07418 { 07419 lsm6dso_fsm_long_counter_clear_t reg; 07420 int32_t ret; 07421 07422 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07423 if (ret == 0) { 07424 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR, 07425 (uint8_t*)®, 1); 07426 } 07427 if (ret == 0) { 07428 reg. fsm_lc_clr = (uint8_t)val; 07429 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR, 07430 (uint8_t*)®, 1); 07431 } 07432 if (ret == 0) { 07433 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07434 } 07435 return ret; 07436 } 07437 07438 /** 07439 * @brief Clear FSM long counter value.[get] 07440 * 07441 * @param ctx read / write interface definitions 07442 * @param val Get the values of fsm_lc_clr in 07443 * reg FSM_LONG_COUNTER_CLEAR 07444 * 07445 */ 07446 int32_t lsm6dso_long_clr_get(lsm6dso_ctx_t *ctx, lsm6dso_fsm_lc_clr_t *val) 07447 { 07448 lsm6dso_fsm_long_counter_clear_t reg; 07449 int32_t ret; 07450 07451 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07452 if (ret == 0) { 07453 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR, 07454 (uint8_t*)®, 1); 07455 } 07456 if (ret == 0) { 07457 switch (reg.fsm_lc_clr) { 07458 case LSM6DSO_LC_NORMAL: 07459 *val = LSM6DSO_LC_NORMAL; 07460 break; 07461 case LSM6DSO_LC_CLEAR: 07462 *val = LSM6DSO_LC_CLEAR; 07463 break; 07464 case LSM6DSO_LC_CLEAR_DONE: 07465 *val = LSM6DSO_LC_CLEAR_DONE; 07466 break; 07467 default: 07468 *val = LSM6DSO_LC_NORMAL; 07469 break; 07470 } 07471 } 07472 07473 if (ret == 0) { 07474 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07475 } 07476 07477 return ret; 07478 } 07479 07480 /** 07481 * @brief FSM output registers[get] 07482 * 07483 * @param ctx read / write interface definitions 07484 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16 07485 * 07486 */ 07487 int32_t lsm6dso_fsm_out_get(lsm6dso_ctx_t *ctx, lsm6dso_fsm_out_t *val) 07488 { 07489 int32_t ret; 07490 07491 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07492 if (ret == 0) { 07493 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_OUTS1, (uint8_t*)val, 16); 07494 } 07495 if (ret == 0) { 07496 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07497 } 07498 07499 return ret; 07500 } 07501 07502 /** 07503 * @brief Finite State Machine ODR configuration.[set] 07504 * 07505 * @param ctx read / write interface definitions 07506 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B 07507 * 07508 */ 07509 int32_t lsm6dso_fsm_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_fsm_odr_t val) 07510 { 07511 lsm6dso_emb_func_odr_cfg_b_t reg; 07512 int32_t ret; 07513 07514 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07515 if (ret == 0) { 07516 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, 07517 (uint8_t*)®, 1); 07518 } 07519 if (ret == 0) { 07520 reg.not_used_01 = 3; /* set default values */ 07521 reg.not_used_02 = 2; /* set default values */ 07522 reg.fsm_odr = (uint8_t)val; 07523 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, 07524 (uint8_t*)®, 1); 07525 } 07526 if (ret == 0) { 07527 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07528 } 07529 return ret; 07530 } 07531 07532 /** 07533 * @brief Finite State Machine ODR configuration.[get] 07534 * 07535 * @param ctx read / write interface definitions 07536 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B 07537 * 07538 */ 07539 int32_t lsm6dso_fsm_data_rate_get(lsm6dso_ctx_t *ctx, lsm6dso_fsm_odr_t *val) 07540 { 07541 lsm6dso_emb_func_odr_cfg_b_t reg; 07542 int32_t ret; 07543 07544 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07545 if (ret == 0) { 07546 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, 07547 (uint8_t*)®, 1); 07548 } 07549 if (ret == 0) { 07550 switch (reg.fsm_odr) { 07551 case LSM6DSO_ODR_FSM_12Hz5: 07552 *val = LSM6DSO_ODR_FSM_12Hz5; 07553 break; 07554 case LSM6DSO_ODR_FSM_26Hz: 07555 *val = LSM6DSO_ODR_FSM_26Hz; 07556 break; 07557 case LSM6DSO_ODR_FSM_52Hz: 07558 *val = LSM6DSO_ODR_FSM_52Hz; 07559 break; 07560 case LSM6DSO_ODR_FSM_104Hz: 07561 *val = LSM6DSO_ODR_FSM_104Hz; 07562 break; 07563 default: 07564 *val = LSM6DSO_ODR_FSM_12Hz5; 07565 break; 07566 } 07567 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07568 } 07569 07570 return ret; 07571 } 07572 07573 /** 07574 * @brief FSM initialization request.[set] 07575 * 07576 * @param ctx read / write interface definitions 07577 * @param val change the values of fsm_init in reg FSM_INIT 07578 * 07579 */ 07580 int32_t lsm6dso_fsm_init_set(lsm6dso_ctx_t *ctx, uint8_t val) 07581 { 07582 lsm6dso_emb_func_init_b_t reg; 07583 int32_t ret; 07584 07585 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07586 if (ret == 0) { 07587 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 07588 } 07589 if (ret == 0) { 07590 reg.fsm_init = val; 07591 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 07592 } 07593 if (ret == 0) { 07594 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07595 } 07596 07597 return ret; 07598 } 07599 07600 /** 07601 * @brief FSM initialization request.[get] 07602 * 07603 * @param ctx read / write interface definitions 07604 * @param val change the values of fsm_init in reg FSM_INIT 07605 * 07606 */ 07607 int32_t lsm6dso_fsm_init_get(lsm6dso_ctx_t *ctx, uint8_t *val) 07608 { 07609 lsm6dso_emb_func_init_b_t reg; 07610 int32_t ret; 07611 07612 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 07613 if (ret == 0) { 07614 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t*)®, 1); 07615 } 07616 if (ret == 0) { 07617 *val = reg.fsm_init; 07618 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07619 } 07620 return ret; 07621 } 07622 07623 /** 07624 * @brief FSM long counter timeout register (r/w). The long counter 07625 * timeout value is an unsigned integer value (16-bit format). 07626 * When the long counter value reached this value, 07627 * the FSM generates an interrupt.[set] 07628 * 07629 * @param ctx read / write interface definitions 07630 * @param val the value of long counter 07631 * 07632 */ 07633 int32_t lsm6dso_long_cnt_int_value_set(lsm6dso_ctx_t *ctx, uint16_t val) 07634 { 07635 int32_t ret; 07636 uint8_t add_l; 07637 uint8_t add_h; 07638 07639 add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 ); 07640 add_l = (uint8_t)( val & 0x00FFU ); 07641 07642 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l); 07643 if (ret == 0) { 07644 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h); 07645 } 07646 07647 return ret; 07648 } 07649 07650 /** 07651 * @brief FSM long counter timeout register (r/w). The long counter 07652 * timeout value is an unsigned integer value (16-bit format). 07653 * When the long counter value reached this value, 07654 * the FSM generates an interrupt.[get] 07655 * 07656 * @param ctx read / write interface definitions 07657 * @param val buffer that stores the value of long counter 07658 * 07659 */ 07660 int32_t lsm6dso_long_cnt_int_value_get(lsm6dso_ctx_t *ctx, uint16_t *val) 07661 { 07662 int32_t ret; 07663 uint8_t add_l; 07664 uint8_t add_h; 07665 07666 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &add_l); 07667 if (ret == 0) { 07668 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &add_h); 07669 *val = add_h; 07670 *val = *val << 8; 07671 *val += add_l; 07672 } 07673 07674 return ret; 07675 } 07676 07677 /** 07678 * @brief FSM number of programs register.[set] 07679 * 07680 * @param ctx read / write interface definitions 07681 * @param val value to write 07682 * 07683 */ 07684 int32_t lsm6dso_fsm_number_of_programs_set(lsm6dso_ctx_t *ctx, uint8_t val) 07685 { 07686 int32_t ret; 07687 07688 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_PROGRAMS, &val); 07689 07690 return ret; 07691 } 07692 07693 /** 07694 * @brief FSM number of programs register.[get] 07695 * 07696 * @param ctx read / write interface definitions 07697 * @param val buffer that stores data read. 07698 * 07699 */ 07700 int32_t lsm6dso_fsm_number_of_programs_get(lsm6dso_ctx_t *ctx, uint8_t *val) 07701 { 07702 int32_t ret; 07703 07704 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_PROGRAMS, val); 07705 07706 return ret; 07707 } 07708 07709 /** 07710 * @brief FSM start address register (r/w). 07711 * First available address is 0x033C.[set] 07712 * 07713 * @param ctx read / write interface definitions 07714 * @param val the value of start address 07715 * 07716 */ 07717 int32_t lsm6dso_fsm_start_address_set(lsm6dso_ctx_t *ctx, uint16_t val) 07718 { 07719 int32_t ret; 07720 uint8_t add_l; 07721 uint8_t add_h; 07722 07723 add_h = (uint8_t)( ( val & 0xFF00U ) >> 8 ); 07724 add_l = (uint8_t)( val & 0x00FFU ); 07725 07726 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l); 07727 if (ret == 0) { 07728 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h); 07729 } 07730 return ret; 07731 } 07732 07733 /** 07734 * @brief FSM start address register (r/w). 07735 * First available address is 0x033C.[get] 07736 * 07737 * @param ctx read / write interface definitions 07738 * @param val buffer the value of start address. 07739 * 07740 */ 07741 int32_t lsm6dso_fsm_start_address_get(lsm6dso_ctx_t *ctx, uint16_t *val) 07742 { 07743 int32_t ret; 07744 uint8_t add_l; 07745 uint8_t add_h; 07746 07747 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_L, &add_l); 07748 if (ret == 0) { 07749 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_H, &add_h); 07750 *val = add_h; 07751 *val = *val << 8; 07752 *val += add_l; 07753 } 07754 return ret; 07755 } 07756 07757 /** 07758 * @} 07759 * 07760 */ 07761 07762 /** 07763 * @defgroup LSM6DSO_Sensor_hub 07764 * @brief This section groups all the functions that manage the 07765 * sensor hub. 07766 * @{ 07767 * 07768 */ 07769 07770 /** 07771 * @brief Sensor hub output registers.[get] 07772 * 07773 * @param ctx read / write interface definitions 07774 * @param val values read from registers SENSOR_HUB_1 to SENSOR_HUB_18 07775 * @param len number of consecutive register to read (max 18) 07776 * 07777 */ 07778 int32_t lsm6dso_sh_read_data_raw_get(lsm6dso_ctx_t *ctx, uint8_t *val, 07779 uint8_t len) 07780 { 07781 int32_t ret; 07782 07783 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 07784 if (ret == 0) { 07785 ret = lsm6dso_read_reg(ctx, LSM6DSO_SENSOR_HUB_1, (uint8_t*) val, len); 07786 } 07787 if (ret == 0) { 07788 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07789 } 07790 07791 return ret; 07792 } 07793 07794 /** 07795 * @brief Number of external sensors to be read by the sensor hub.[set] 07796 * 07797 * @param ctx read / write interface definitions 07798 * @param val change the values of aux_sens_on in reg MASTER_CONFIG 07799 * 07800 */ 07801 int32_t lsm6dso_sh_slave_connected_set(lsm6dso_ctx_t *ctx, 07802 lsm6dso_aux_sens_on_t val) 07803 { 07804 lsm6dso_master_config_t reg; 07805 int32_t ret; 07806 07807 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 07808 if (ret == 0) { 07809 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07810 } 07811 if (ret == 0) { 07812 reg.aux_sens_on = (uint8_t)val; 07813 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07814 } 07815 if (ret == 0) { 07816 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07817 } 07818 return ret; 07819 } 07820 07821 /** 07822 * @brief Number of external sensors to be read by the sensor hub.[get] 07823 * 07824 * @param ctx read / write interface definitions 07825 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG 07826 * 07827 */ 07828 int32_t lsm6dso_sh_slave_connected_get(lsm6dso_ctx_t *ctx, 07829 lsm6dso_aux_sens_on_t *val) 07830 { 07831 lsm6dso_master_config_t reg; 07832 int32_t ret; 07833 07834 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 07835 if (ret == 0) { 07836 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07837 } 07838 if (ret == 0) { 07839 switch (reg.aux_sens_on) { 07840 case LSM6DSO_SLV_0: 07841 *val = LSM6DSO_SLV_0; 07842 break; 07843 case LSM6DSO_SLV_0_1: 07844 *val = LSM6DSO_SLV_0_1; 07845 break; 07846 case LSM6DSO_SLV_0_1_2: 07847 *val = LSM6DSO_SLV_0_1_2; 07848 break; 07849 case LSM6DSO_SLV_0_1_2_3: 07850 *val = LSM6DSO_SLV_0_1_2_3; 07851 break; 07852 default: 07853 *val = LSM6DSO_SLV_0; 07854 break; 07855 } 07856 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07857 } 07858 07859 return ret; 07860 } 07861 07862 /** 07863 * @brief Sensor hub I2C master enable.[set] 07864 * 07865 * @param ctx read / write interface definitions 07866 * @param val change the values of master_on in reg MASTER_CONFIG 07867 * 07868 */ 07869 int32_t lsm6dso_sh_master_set(lsm6dso_ctx_t *ctx, uint8_t val) 07870 { 07871 lsm6dso_master_config_t reg; 07872 int32_t ret; 07873 07874 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 07875 if (ret == 0) { 07876 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07877 } 07878 if (ret == 0) { 07879 reg.master_on = val; 07880 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07881 } 07882 if (ret == 0) { 07883 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07884 } 07885 return ret; 07886 } 07887 07888 /** 07889 * @brief Sensor hub I2C master enable.[get] 07890 * 07891 * @param ctx read / write interface definitions 07892 * @param val change the values of master_on in reg MASTER_CONFIG 07893 * 07894 */ 07895 int32_t lsm6dso_sh_master_get(lsm6dso_ctx_t *ctx, uint8_t *val) 07896 { 07897 lsm6dso_master_config_t reg; 07898 int32_t ret; 07899 07900 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 07901 if (ret == 0) { 07902 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07903 } 07904 if (ret == 0) { 07905 *val = reg.master_on; 07906 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07907 } 07908 07909 return ret; 07910 } 07911 07912 /** 07913 * @brief Master I2C pull-up enable.[set] 07914 * 07915 * @param ctx read / write interface definitions 07916 * @param val change the values of shub_pu_en in reg MASTER_CONFIG 07917 * 07918 */ 07919 int32_t lsm6dso_sh_pin_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_pu_en_t val) 07920 { 07921 lsm6dso_master_config_t reg; 07922 int32_t ret; 07923 07924 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 07925 if (ret == 0) { 07926 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07927 } 07928 if (ret == 0) { 07929 reg.shub_pu_en = (uint8_t)val; 07930 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07931 } 07932 if (ret == 0) { 07933 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07934 } 07935 07936 return ret; 07937 } 07938 07939 /** 07940 * @brief Master I2C pull-up enable.[get] 07941 * 07942 * @param ctx read / write interface definitions 07943 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG 07944 * 07945 */ 07946 int32_t lsm6dso_sh_pin_mode_get(lsm6dso_ctx_t *ctx, 07947 lsm6dso_shub_pu_en_t *val) 07948 { 07949 lsm6dso_master_config_t reg; 07950 int32_t ret; 07951 07952 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 07953 if (ret == 0) { 07954 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07955 } 07956 if (ret == 0) { 07957 switch (reg.shub_pu_en) { 07958 case LSM6DSO_EXT_PULL_UP: 07959 *val = LSM6DSO_EXT_PULL_UP; 07960 break; 07961 case LSM6DSO_INTERNAL_PULL_UP: 07962 *val = LSM6DSO_INTERNAL_PULL_UP; 07963 break; 07964 default: 07965 *val = LSM6DSO_EXT_PULL_UP; 07966 break; 07967 } 07968 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07969 } 07970 07971 return ret; 07972 } 07973 07974 /** 07975 * @brief I2C interface pass-through.[set] 07976 * 07977 * @param ctx read / write interface definitions 07978 * @param val change the values of pass_through_mode in 07979 * reg MASTER_CONFIG 07980 * 07981 */ 07982 int32_t lsm6dso_sh_pass_through_set(lsm6dso_ctx_t *ctx, uint8_t val) 07983 { 07984 lsm6dso_master_config_t reg; 07985 int32_t ret; 07986 07987 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 07988 if (ret == 0) { 07989 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07990 } 07991 if (ret == 0) { 07992 reg.pass_through_mode = val; 07993 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 07994 } 07995 if (ret == 0) { 07996 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 07997 } 07998 07999 return ret; 08000 } 08001 08002 /** 08003 * @brief I2C interface pass-through.[get] 08004 * 08005 * @param ctx read / write interface definitions 08006 * @param val change the values of pass_through_mode in 08007 * reg MASTER_CONFIG 08008 * 08009 */ 08010 int32_t lsm6dso_sh_pass_through_get(lsm6dso_ctx_t *ctx, uint8_t *val) 08011 { 08012 lsm6dso_master_config_t reg; 08013 int32_t ret; 08014 08015 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08016 if (ret == 0) { 08017 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08018 } 08019 if (ret == 0) { 08020 *val = reg.pass_through_mode; 08021 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08022 } 08023 08024 return ret; 08025 } 08026 08027 /** 08028 * @brief Sensor hub trigger signal selection.[set] 08029 * 08030 * @param ctx read / write interface definitions 08031 * @param val change the values of start_config in reg MASTER_CONFIG 08032 * 08033 */ 08034 int32_t lsm6dso_sh_syncro_mode_set(lsm6dso_ctx_t *ctx, 08035 lsm6dso_start_config_t val) 08036 { 08037 lsm6dso_master_config_t reg; 08038 int32_t ret; 08039 08040 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08041 if (ret == 0) { 08042 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08043 } 08044 if (ret == 0) { 08045 reg.start_config = (uint8_t)val; 08046 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08047 } 08048 if (ret == 0) { 08049 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08050 } 08051 08052 return ret; 08053 } 08054 08055 /** 08056 * @brief Sensor hub trigger signal selection.[get] 08057 * 08058 * @param ctx read / write interface definitions 08059 * @param val Get the values of start_config in reg MASTER_CONFIG 08060 * 08061 */ 08062 int32_t lsm6dso_sh_syncro_mode_get(lsm6dso_ctx_t *ctx, 08063 lsm6dso_start_config_t *val) 08064 { 08065 lsm6dso_master_config_t reg; 08066 int32_t ret; 08067 08068 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08069 if (ret == 0) { 08070 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08071 } 08072 if (ret == 0) { 08073 switch (reg.start_config) { 08074 case LSM6DSO_EXT_ON_INT2_PIN: 08075 *val = LSM6DSO_EXT_ON_INT2_PIN; 08076 break; 08077 case LSM6DSO_XL_GY_DRDY: 08078 *val = LSM6DSO_XL_GY_DRDY; 08079 break; 08080 default: 08081 *val = LSM6DSO_EXT_ON_INT2_PIN; 08082 break; 08083 } 08084 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08085 } 08086 return ret; 08087 } 08088 08089 /** 08090 * @brief Slave 0 write operation is performed only at the first 08091 * sensor hub cycle.[set] 08092 * 08093 * @param ctx read / write interface definitions 08094 * @param val change the values of write_once in reg MASTER_CONFIG 08095 * 08096 */ 08097 int32_t lsm6dso_sh_write_mode_set(lsm6dso_ctx_t *ctx, 08098 lsm6dso_write_once_t val) 08099 { 08100 lsm6dso_master_config_t reg; 08101 int32_t ret; 08102 08103 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08104 if (ret == 0) { 08105 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08106 } 08107 if (ret == 0) { 08108 reg.write_once = (uint8_t)val; 08109 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08110 } 08111 if (ret == 0) { 08112 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08113 } 08114 08115 return ret; 08116 } 08117 08118 /** 08119 * @brief Slave 0 write operation is performed only at the first sensor 08120 * hub cycle.[get] 08121 * 08122 * @param ctx read / write interface definitions 08123 * @param val Get the values of write_once in reg MASTER_CONFIG 08124 * 08125 */ 08126 int32_t lsm6dso_sh_write_mode_get(lsm6dso_ctx_t *ctx, 08127 lsm6dso_write_once_t *val) 08128 { 08129 lsm6dso_master_config_t reg; 08130 int32_t ret; 08131 08132 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08133 if (ret == 0) { 08134 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08135 } 08136 if (ret == 0) { 08137 switch (reg.write_once) { 08138 case LSM6DSO_EACH_SH_CYCLE: 08139 *val = LSM6DSO_EACH_SH_CYCLE; 08140 break; 08141 case LSM6DSO_ONLY_FIRST_CYCLE: 08142 *val = LSM6DSO_ONLY_FIRST_CYCLE; 08143 break; 08144 default: 08145 *val = LSM6DSO_EACH_SH_CYCLE; 08146 break; 08147 } 08148 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08149 } 08150 08151 return ret; 08152 } 08153 08154 /** 08155 * @brief Reset Master logic and output registers.[set] 08156 * 08157 * @param ctx read / write interface definitions 08158 * 08159 */ 08160 int32_t lsm6dso_sh_reset_set(lsm6dso_ctx_t *ctx) 08161 { 08162 lsm6dso_master_config_t reg; 08163 int32_t ret; 08164 08165 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08166 if (ret == 0) { 08167 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08168 } 08169 if (ret == 0) { 08170 reg.rst_master_regs = PROPERTY_ENABLE; 08171 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08172 } 08173 if (ret == 0) { 08174 reg.rst_master_regs = PROPERTY_DISABLE; 08175 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08176 } 08177 if (ret == 0) { 08178 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08179 } 08180 08181 return ret; 08182 } 08183 08184 /** 08185 * @brief Reset Master logic and output registers.[get] 08186 * 08187 * @param ctx read / write interface definitions 08188 * @param val change the values of rst_master_regs in reg MASTER_CONFIG 08189 * 08190 */ 08191 int32_t lsm6dso_sh_reset_get(lsm6dso_ctx_t *ctx, uint8_t *val) 08192 { 08193 lsm6dso_master_config_t reg; 08194 int32_t ret; 08195 08196 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08197 if (ret == 0) { 08198 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t*)®, 1); 08199 } 08200 if (ret == 0) { 08201 *val = reg.rst_master_regs; 08202 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08203 } 08204 return ret; 08205 } 08206 08207 /** 08208 * @brief Rate at which the master communicates.[set] 08209 * 08210 * @param ctx read / write interface definitions 08211 * @param val change the values of shub_odr in reg slv1_CONFIG 08212 * 08213 */ 08214 int32_t lsm6dso_sh_data_rate_set(lsm6dso_ctx_t *ctx, lsm6dso_shub_odr_t val) 08215 { 08216 lsm6dso_slv0_config_t reg; 08217 int32_t ret; 08218 08219 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08220 if (ret == 0) { 08221 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1); 08222 } 08223 if (ret == 0) { 08224 reg.shub_odr = (uint8_t)val; 08225 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1); 08226 } 08227 if (ret == 0) { 08228 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08229 } 08230 08231 return ret; 08232 } 08233 08234 /** 08235 * @brief Rate at which the master communicates.[get] 08236 * 08237 * @param ctx read / write interface definitions 08238 * @param val Get the values of shub_odr in reg slv1_CONFIG 08239 * 08240 */ 08241 int32_t lsm6dso_sh_data_rate_get(lsm6dso_ctx_t *ctx, 08242 lsm6dso_shub_odr_t *val) 08243 { 08244 lsm6dso_slv0_config_t reg; 08245 int32_t ret; 08246 08247 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08248 if (ret == 0) { 08249 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t*)®, 1); 08250 } 08251 if (ret == 0) { 08252 switch (reg.shub_odr) { 08253 case LSM6DSO_SH_ODR_104Hz: 08254 *val = LSM6DSO_SH_ODR_104Hz; 08255 break; 08256 case LSM6DSO_SH_ODR_52Hz: 08257 *val = LSM6DSO_SH_ODR_52Hz; 08258 break; 08259 case LSM6DSO_SH_ODR_26Hz: 08260 *val = LSM6DSO_SH_ODR_26Hz; 08261 break; 08262 case LSM6DSO_SH_ODR_13Hz: 08263 *val = LSM6DSO_SH_ODR_13Hz; 08264 break; 08265 default: 08266 *val = LSM6DSO_SH_ODR_104Hz; 08267 break; 08268 } 08269 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08270 } 08271 08272 return ret; 08273 } 08274 08275 /** 08276 * @brief Configure slave 0 for perform a write.[set] 08277 * 08278 * @param ctx read / write interface definitions 08279 * @param val a structure that contain 08280 * - uint8_t slv1_add; 8 bit i2c device address 08281 * - uint8_t slv1_subadd; 8 bit register device address 08282 * - uint8_t slv1_data; 8 bit data to write 08283 * 08284 */ 08285 int32_t lsm6dso_sh_cfg_write(lsm6dso_ctx_t *ctx, lsm6dso_sh_cfg_write_t *val) 08286 { 08287 lsm6dso_slv0_add_t reg; 08288 int32_t ret; 08289 08290 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08291 if (ret == 0) { 08292 reg.slave0 = val->slv0_add; 08293 reg.rw_0 = 0; 08294 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t*)®, 1); 08295 } 08296 if (ret == 0) { 08297 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD, 08298 &(val->slv0_subadd), 1); 08299 } 08300 if (ret == 0) { 08301 ret = lsm6dso_write_reg(ctx, LSM6DSO_DATAWRITE_SLV0, 08302 &(val->slv0_data), 1); 08303 } 08304 if (ret == 0) { 08305 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08306 } 08307 return ret; 08308 } 08309 08310 /** 08311 * @brief Configure slave 0 for perform a read.[set] 08312 * 08313 * @param ctx read / write interface definitions 08314 * @param val Structure that contain 08315 * - uint8_t slv1_add; 8 bit i2c device address 08316 * - uint8_t slv1_subadd; 8 bit register device address 08317 * - uint8_t slv1_len; num of bit to read 08318 * 08319 */ 08320 int32_t lsm6dso_sh_slv0_cfg_read(lsm6dso_ctx_t *ctx, 08321 lsm6dso_sh_cfg_read_t *val) 08322 { 08323 lsm6dso_slv0_add_t slv0_add; 08324 lsm6dso_slv0_config_t slv0_config; 08325 int32_t ret; 08326 08327 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08328 if (ret == 0) { 08329 slv0_add.slave0 = val->slv_add; 08330 slv0_add.rw_0 = 1; 08331 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t*)&slv0_add, 1); 08332 } 08333 if (ret == 0) { 08334 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD, 08335 &(val->slv_subadd), 1); 08336 } 08337 if (ret == 0) { 08338 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, 08339 (uint8_t*)&slv0_config, 1); 08340 } 08341 if (ret == 0) { 08342 slv0_config.slave0_numop = val->slv_len; 08343 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, 08344 (uint8_t*)&slv0_config, 1); 08345 } 08346 if (ret == 0) { 08347 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08348 } 08349 08350 return ret; 08351 } 08352 08353 /** 08354 * @brief Configure slave 0 for perform a write/read.[set] 08355 * 08356 * @param ctx read / write interface definitions 08357 * @param val Structure that contain 08358 * - uint8_t slv1_add; 8 bit i2c device address 08359 * - uint8_t slv1_subadd; 8 bit register device address 08360 * - uint8_t slv1_len; num of bit to read 08361 * 08362 */ 08363 int32_t lsm6dso_sh_slv1_cfg_read(lsm6dso_ctx_t *ctx, 08364 lsm6dso_sh_cfg_read_t *val) 08365 { 08366 lsm6dso_slv1_add_t slv1_add; 08367 lsm6dso_slv1_config_t slv1_config; 08368 int32_t ret; 08369 08370 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08371 if (ret == 0) { 08372 slv1_add.slave1_add = val->slv_add; 08373 slv1_add.r_1 = 1; 08374 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_ADD, (uint8_t*)&slv1_add, 1); 08375 } 08376 if (ret == 0) { 08377 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_SUBADD, 08378 &(val->slv_subadd), 1); 08379 } 08380 if (ret == 0) { 08381 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, 08382 (uint8_t*)&slv1_config, 1); 08383 } 08384 if (ret == 0) { 08385 slv1_config.slave1_numop = val->slv_len; 08386 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, 08387 (uint8_t*)&slv1_config, 1); 08388 } 08389 if (ret == 0) { 08390 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08391 } 08392 08393 return ret; 08394 } 08395 08396 /** 08397 * @brief Configure slave 0 for perform a write/read.[set] 08398 * 08399 * @param ctx read / write interface definitions 08400 * @param val Structure that contain 08401 * - uint8_t slv2_add; 8 bit i2c device address 08402 * - uint8_t slv2_subadd; 8 bit register device address 08403 * - uint8_t slv2_len; num of bit to read 08404 * 08405 */ 08406 int32_t lsm6dso_sh_slv2_cfg_read(lsm6dso_ctx_t *ctx, 08407 lsm6dso_sh_cfg_read_t *val) 08408 { 08409 lsm6dso_slv2_add_t slv2_add; 08410 lsm6dso_slv2_config_t slv2_config; 08411 int32_t ret; 08412 08413 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08414 if (ret == 0) { 08415 slv2_add.slave2_add = val->slv_add; 08416 slv2_add.r_2 = 1; 08417 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_ADD, (uint8_t*)&slv2_add, 1); 08418 } 08419 if (ret == 0) { 08420 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_SUBADD, 08421 &(val->slv_subadd), 1); 08422 } 08423 if (ret == 0) { 08424 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, 08425 (uint8_t*)&slv2_config, 1); 08426 } 08427 if (ret == 0) { 08428 slv2_config.slave2_numop = val->slv_len; 08429 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, 08430 (uint8_t*)&slv2_config, 1); 08431 } 08432 if (ret == 0) { 08433 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08434 } 08435 return ret; 08436 } 08437 08438 /** 08439 * @brief Configure slave 0 for perform a write/read.[set] 08440 * 08441 * @param ctx read / write interface definitions 08442 * @param val Structure that contain 08443 * - uint8_t slv3_add; 8 bit i2c device address 08444 * - uint8_t slv3_subadd; 8 bit register device address 08445 * - uint8_t slv3_len; num of bit to read 08446 * 08447 */ 08448 int32_t lsm6dso_sh_slv3_cfg_read(lsm6dso_ctx_t *ctx, 08449 lsm6dso_sh_cfg_read_t *val) 08450 { 08451 lsm6dso_slv3_add_t slv3_add; 08452 lsm6dso_slv3_config_t slv3_config; 08453 int32_t ret; 08454 08455 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08456 if (ret == 0) { 08457 slv3_add.slave3_add = val->slv_add; 08458 slv3_add.r_3 = 1; 08459 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_ADD, (uint8_t*)&slv3_add, 1); 08460 } 08461 if (ret == 0) { 08462 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_SUBADD, 08463 &(val->slv_subadd), 1); 08464 } 08465 if (ret == 0) { 08466 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, 08467 (uint8_t*)&slv3_config, 1); 08468 } 08469 if (ret == 0) { 08470 slv3_config.slave3_numop = val->slv_len; 08471 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, 08472 (uint8_t*)&slv3_config, 1); 08473 } 08474 if (ret == 0) { 08475 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08476 } 08477 return ret; 08478 } 08479 08480 /** 08481 * @brief Sensor hub source register.[get] 08482 * 08483 * @param ctx read / write interface definitions 08484 * @param val union of registers from STATUS_MASTER to 08485 * 08486 */ 08487 int32_t lsm6dso_sh_status_get(lsm6dso_ctx_t *ctx, 08488 lsm6dso_status_master_t *val) 08489 { 08490 int32_t ret; 08491 08492 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK); 08493 if (ret == 0) { 08494 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER, (uint8_t*) val, 1); 08495 } 08496 if (ret == 0) { 08497 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08498 } 08499 08500 return ret; 08501 } 08502 08503 /** 08504 * @} 08505 * 08506 */ 08507 08508 /** 08509 * @defgroup Basic configuration 08510 * @brief This section groups all the functions concerning 08511 * device basic configuration. 08512 * @{ 08513 * 08514 */ 08515 08516 /** 08517 * @brief Device "Who am I".[get] 08518 * 08519 * @param ctx communication interface handler. Use NULL to ingnore 08520 * this interface.(ptr) 08521 * @param aux_ctx auxiliary communication interface handler. Use NULL 08522 * to ingnore this interface.(ptr) 08523 * @param val ID values read from the two interfaces. ID values 08524 * will be the same.(ptr) 08525 * 08526 */ 08527 int32_t lsm6dso_id_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 08528 lsm6dso_id_t *val) 08529 { 08530 int32_t ret = 0; 08531 08532 if (ctx != NULL){ 08533 ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, 08534 (uint8_t*)&(val->ui), 1); 08535 } 08536 if (aux_ctx != NULL){ 08537 if (ret == 0) { 08538 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_WHO_AM_I, 08539 (uint8_t*)&(val->aux), 1); 08540 } 08541 } 08542 return ret; 08543 } 08544 08545 /** 08546 * @brief Re-initialize the device.[set] 08547 * 08548 * @param ctx communication interface handler.(ptr) 08549 * @param val re-initialization mode. Refer to datasheet 08550 * and application note for more information 08551 * about differencies beetween boot and sw_reset 08552 * procedure. 08553 * 08554 */ 08555 int32_t lsm6dso_init_set(lsm6dso_ctx_t *ctx, lsm6dso_init_t val) 08556 { 08557 lsm6dso_emb_func_init_a_t emb_func_init_a; 08558 lsm6dso_emb_func_init_b_t emb_func_init_b; 08559 lsm6dso_ctrl3_c_t ctrl3_c; 08560 int32_t ret; 08561 08562 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 08563 if (ret == 0) { 08564 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, 08565 (uint8_t*)&emb_func_init_b, 1); 08566 } 08567 if (ret == 0) { 08568 emb_func_init_b.fifo_compr_init = (uint8_t)val 08569 & ( (uint8_t)LSM6DSO_FIFO_COMP >> 2 ); 08570 emb_func_init_b.fsm_init = (uint8_t)val 08571 & ( (uint8_t)LSM6DSO_FSM >> 3 ); 08572 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, 08573 (uint8_t*)&emb_func_init_b, 1); 08574 } 08575 if (ret == 0) { 08576 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A, 08577 (uint8_t*)&emb_func_init_a, 1); 08578 } 08579 if (ret == 0) { 08580 emb_func_init_a.step_det_init = ( (uint8_t)val 08581 & (uint8_t)LSM6DSO_PEDO ) >> 5; 08582 emb_func_init_a.tilt_init = ( (uint8_t)val 08583 & (uint8_t)LSM6DSO_TILT ) >> 6; 08584 emb_func_init_a.sig_mot_init = ( (uint8_t)val 08585 & (uint8_t)LSM6DSO_SMOTION ) >> 7; 08586 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A, 08587 (uint8_t*)&emb_func_init_a, 1); 08588 } 08589 if (ret == 0) { 08590 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08591 } 08592 08593 if (ret == 0) { 08594 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 08595 } 08596 if ( ( (val == LSM6DSO_BOOT) || (val == LSM6DSO_RESET) ) && (ret == 0) ) { 08597 ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSO_BOOT; 08598 ctrl3_c.sw_reset = ( (uint8_t)val & (uint8_t)LSM6DSO_RESET) >> 1; 08599 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 08600 } 08601 if ( ( val == LSM6DSO_DRV_RDY ) 08602 && ( (ctrl3_c.bdu == PROPERTY_DISABLE) 08603 || (ctrl3_c.if_inc == PROPERTY_DISABLE) ) && (ret == 0) ) { 08604 ctrl3_c.bdu = PROPERTY_ENABLE; 08605 ctrl3_c.if_inc = PROPERTY_ENABLE; 08606 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 08607 } 08608 08609 return ret; 08610 } 08611 08612 /** 08613 * @brief Configures the bus operating mode.[set] 08614 * 08615 * @param ctx communication interface handler. Use NULL to ingnore 08616 * this interface.(ptr) 08617 * @param aux_ctx auxiliary communication interface handler. Use NULL 08618 * to ingnore this interface.(ptr) 08619 * @param val configures the bus operating mode for both the 08620 * main and the auxiliary interface. 08621 * 08622 */ 08623 int32_t lsm6dso_bus_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 08624 lsm6dso_bus_mode_t val) 08625 { 08626 lsm6dso_ctrl1_ois_t ctrl1_ois; 08627 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 08628 lsm6dso_ctrl9_xl_t ctrl9_xl; 08629 lsm6dso_ctrl3_c_t ctrl3_c; 08630 lsm6dso_ctrl4_c_t ctrl4_c; 08631 uint8_t bit_val; 08632 int32_t ret; 08633 08634 ret = 0; 08635 08636 if (aux_ctx != NULL) { 08637 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, 08638 (uint8_t*)&ctrl1_ois, 1); 08639 08640 bit_val = ( (uint8_t)val.aux_bus_md & 0x04U ) >> 2; 08641 if ( ( ret == 0 ) && ( ctrl1_ois.sim_ois != bit_val ) ) { 08642 ctrl1_ois.sim_ois = bit_val; 08643 ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS, 08644 (uint8_t*)&ctrl1_ois, 1); 08645 } 08646 } 08647 08648 if (ctx != NULL) { 08649 if (ret == 0) { 08650 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, 08651 (uint8_t*)&ctrl9_xl, 1); 08652 } 08653 08654 bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2; 08655 if ( ( ret == 0 ) && ( ctrl9_xl.i3c_disable != bit_val ) ) { 08656 ctrl9_xl.i3c_disable = bit_val; 08657 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, 08658 (uint8_t*)&ctrl9_xl, 1); 08659 } 08660 08661 if (ret == 0) { 08662 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, 08663 (uint8_t*)&i3c_bus_avb, 1); 08664 } 08665 08666 bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4; 08667 if ( ( ret == 0 ) && ( i3c_bus_avb.i3c_bus_avb_sel != bit_val ) ) { 08668 i3c_bus_avb.i3c_bus_avb_sel = bit_val; 08669 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, 08670 (uint8_t*)&i3c_bus_avb, 1); 08671 } 08672 if (ret == 0) { 08673 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, 08674 (uint8_t*)&ctrl4_c, 1); 08675 } 08676 bit_val = ( (uint8_t)val.ui_bus_md & 0x02U ) >> 1; 08677 if ( ( ret == 0 ) && ( ctrl4_c.i2c_disable != bit_val ) ) { 08678 ctrl4_c.i2c_disable = bit_val; 08679 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, 08680 (uint8_t*)&ctrl4_c, 1); 08681 } 08682 if (ret == 0) { 08683 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, 08684 (uint8_t*)&ctrl3_c, 1); 08685 } 08686 bit_val = (uint8_t)val.ui_bus_md & 0x01U; 08687 if ( ( ret == 0 ) && ( ctrl3_c.sim != bit_val ) ) { 08688 ctrl3_c.sim = bit_val; 08689 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, 08690 (uint8_t*)&ctrl3_c, 1); 08691 } 08692 } 08693 08694 return ret; 08695 08696 } 08697 08698 /** 08699 * @brief Get the bus operating mode.[get] 08700 * 08701 * @param ctx communication interface handler. Use NULL to ingnore 08702 * this interface.(ptr) 08703 * @param aux_ctx auxiliary communication interface handler. Use NULL 08704 * to ingnore this interface.(ptr) 08705 * @param val retrieves the bus operating mode for both the main 08706 * and the auxiliary interface.(ptr) 08707 * 08708 */ 08709 int32_t lsm6dso_bus_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 08710 lsm6dso_bus_mode_t *val) 08711 { 08712 lsm6dso_ctrl1_ois_t ctrl1_ois; 08713 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 08714 lsm6dso_ctrl9_xl_t ctrl9_xl; 08715 lsm6dso_ctrl3_c_t ctrl3_c; 08716 lsm6dso_ctrl4_c_t ctrl4_c; 08717 08718 int32_t ret = 0; 08719 08720 if (aux_ctx != NULL) { 08721 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, 08722 (uint8_t*)&ctrl1_ois, 1); 08723 switch ( ctrl1_ois.sim_ois ) { 08724 case LSM6DSO_SPI_4W_AUX: 08725 val->aux_bus_md = LSM6DSO_SPI_4W_AUX; 08726 break; 08727 case LSM6DSO_SPI_3W_AUX: 08728 val->aux_bus_md = LSM6DSO_SPI_3W_AUX; 08729 break; 08730 default: 08731 val->aux_bus_md = LSM6DSO_SPI_4W_AUX; 08732 break; 08733 } 08734 } 08735 08736 if (ctx != NULL) { 08737 if (ret == 0) { 08738 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, 08739 (uint8_t*)&ctrl9_xl, 1); 08740 } 08741 if (ret == 0) { 08742 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, 08743 (uint8_t*)&i3c_bus_avb, 1); 08744 } 08745 if (ret == 0) { 08746 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, 08747 (uint8_t*)&ctrl4_c, 1); 08748 } 08749 if (ret == 0) { 08750 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, 08751 (uint8_t*)&ctrl3_c, 1); 08752 08753 switch ( ( i3c_bus_avb.i3c_bus_avb_sel << 4 ) & 08754 ( ctrl9_xl.i3c_disable << 2 ) & 08755 ( ctrl4_c.i2c_disable << 1) & ctrl3_c.sim ) { 08756 case LSM6DSO_SEL_BY_HW: 08757 val->ui_bus_md = LSM6DSO_SEL_BY_HW; 08758 break; 08759 case LSM6DSO_SPI_4W: 08760 val->ui_bus_md = LSM6DSO_SPI_4W; 08761 break; 08762 case LSM6DSO_SPI_3W: 08763 val->ui_bus_md = LSM6DSO_SPI_3W; 08764 break; 08765 case LSM6DSO_I2C: 08766 val->ui_bus_md = LSM6DSO_I2C; 08767 break; 08768 case LSM6DSO_I3C_T_50us: 08769 val->ui_bus_md = LSM6DSO_I3C_T_50us; 08770 break; 08771 case LSM6DSO_I3C_T_2us: 08772 val->ui_bus_md = LSM6DSO_I3C_T_2us; 08773 break; 08774 case LSM6DSO_I3C_T_1ms: 08775 val->ui_bus_md = LSM6DSO_I3C_T_1ms; 08776 break; 08777 case LSM6DSO_I3C_T_25ms: 08778 val->ui_bus_md = LSM6DSO_I3C_T_25ms; 08779 break; 08780 default: 08781 val->ui_bus_md = LSM6DSO_SEL_BY_HW; 08782 break; 08783 } 08784 } 08785 } 08786 return ret; 08787 } 08788 08789 /** 08790 * @brief Get the status of the device.[get] 08791 * 08792 * @param ctx communication interface handler. Use NULL to ingnore 08793 * this interface.(ptr) 08794 * @param aux_ctx auxiliary communication interface handler. Use NULL 08795 * to ingnore this interface.(ptr) 08796 * @param val the status of the device.(ptr) 08797 * 08798 */ 08799 int32_t lsm6dso_status_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 08800 lsm6dso_status_t *val) 08801 { 08802 lsm6dso_status_spiaux_t status_spiaux; 08803 lsm6dso_status_reg_t status_reg; 08804 lsm6dso_ctrl3_c_t ctrl3_c; 08805 int32_t ret; 08806 08807 ret = 0; 08808 08809 if (aux_ctx != NULL){ 08810 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_STATUS_SPIAUX, 08811 (uint8_t*)&status_spiaux, 1); 08812 val->ois_drdy_xl = status_spiaux.xlda; 08813 val->ois_drdy_g = status_spiaux.gda; 08814 val->ois_gyro_settling = status_spiaux.gyro_settling; 08815 } 08816 08817 if (ctx != NULL){ 08818 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 08819 val->sw_reset = ctrl3_c.sw_reset; 08820 val->boot = ctrl3_c.boot; 08821 08822 if ( (ret == 0) && ( ctrl3_c.sw_reset == PROPERTY_DISABLE ) && 08823 ( ctrl3_c.boot == PROPERTY_DISABLE ) ) { 08824 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, 08825 (uint8_t*)&status_reg, 1); 08826 val->drdy_xl = status_reg.xlda; 08827 val->drdy_g = status_reg.gda; 08828 val->drdy_temp = status_reg.tda; 08829 } 08830 } 08831 return ret; 08832 } 08833 08834 /** 08835 * @brief Electrical pin configuration.[set] 08836 * 08837 * @param ctx communication interface handler.(ptr) 08838 * @param val the electrical settings for the configurable 08839 * pins. 08840 * 08841 */ 08842 int32_t lsm6dso_pin_conf_set(lsm6dso_ctx_t *ctx, lsm6dso_pin_conf_t val) 08843 { 08844 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 08845 lsm6dso_pin_ctrl_t pin_ctrl; 08846 lsm6dso_ctrl3_c_t ctrl3_c; 08847 int32_t ret; 08848 08849 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&pin_ctrl, 1); 08850 if (ret == 0) { 08851 pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up; 08852 pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up; 08853 ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&pin_ctrl, 1); 08854 } 08855 if (ret == 0) { 08856 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 08857 } 08858 if (ret == 0) { 08859 ctrl3_c.pp_od = ~val.int1_int2_push_pull; 08860 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 08861 } 08862 if (ret == 0) { 08863 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, 08864 (uint8_t*)&i3c_bus_avb, 1); 08865 } 08866 if (ret == 0) { 08867 i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down; 08868 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, 08869 (uint8_t*)&i3c_bus_avb, 1); 08870 } 08871 return ret; 08872 } 08873 08874 /** 08875 * @brief Electrical pin configuration.[get] 08876 * 08877 * @param ctx communication interface handler.(ptr) 08878 * @param val the electrical settings for the configurable 08879 * pins.(ptr) 08880 * 08881 */ 08882 int32_t lsm6dso_pin_conf_get(lsm6dso_ctx_t *ctx, lsm6dso_pin_conf_t *val) 08883 { 08884 lsm6dso_i3c_bus_avb_t i3c_bus_avb; 08885 lsm6dso_pin_ctrl_t pin_ctrl; 08886 lsm6dso_ctrl3_c_t ctrl3_c; 08887 int32_t ret; 08888 08889 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t*)&pin_ctrl, 1); 08890 if (ret == 0) { 08891 val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis; 08892 val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en; 08893 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 08894 } 08895 if (ret == 0) { 08896 val->int1_int2_push_pull = ~ctrl3_c.pp_od; 08897 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, 08898 (uint8_t*)&i3c_bus_avb, 1); 08899 } 08900 if (ret == 0) { 08901 val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1; 08902 } 08903 return ret; 08904 } 08905 08906 /** 08907 * @brief Interrupt pins hardware signal configuration.[set] 08908 * 08909 * @param ctx communication interface handler.(ptr) 08910 * @param val the pins hardware signal settings. 08911 * 08912 */ 08913 int32_t lsm6dso_interrupt_mode_set(lsm6dso_ctx_t *ctx, 08914 lsm6dso_int_mode_t val) 08915 { 08916 lsm6dso_tap_cfg0_t tap_cfg0; 08917 lsm6dso_page_rw_t page_rw; 08918 lsm6dso_ctrl3_c_t ctrl3_c; 08919 int32_t ret; 08920 08921 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 08922 if (ret == 0) { 08923 ctrl3_c.h_lactive = val.active_low; 08924 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 08925 } 08926 if (ret == 0) { 08927 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 08928 } 08929 if (ret == 0) { 08930 tap_cfg0.lir = val.base_latched; 08931 tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched; 08932 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 08933 } 08934 if (ret == 0) { 08935 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 08936 } 08937 if (ret == 0) { 08938 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 08939 } 08940 if (ret == 0) { 08941 page_rw.emb_func_lir = val.emb_latched; 08942 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 08943 } 08944 if (ret == 0) { 08945 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08946 } 08947 return ret; 08948 } 08949 08950 /** 08951 * @brief Interrupt pins hardware signal configuration.[get] 08952 * 08953 * @param ctx communication interface handler.(ptr) 08954 * @param val the pins hardware signal settings.(ptr) 08955 * 08956 */ 08957 int32_t lsm6dso_interrupt_mode_get(lsm6dso_ctx_t *ctx, 08958 lsm6dso_int_mode_t *val) 08959 { 08960 lsm6dso_tap_cfg0_t tap_cfg0; 08961 lsm6dso_page_rw_t page_rw; 08962 lsm6dso_ctrl3_c_t ctrl3_c; 08963 int32_t ret; 08964 08965 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t*)&ctrl3_c, 1); 08966 if (ret == 0) { 08967 ctrl3_c.h_lactive = val->active_low; 08968 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t*) &tap_cfg0, 1); 08969 } 08970 if (ret == 0) { 08971 tap_cfg0.lir = val->base_latched; 08972 tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched; 08973 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 08974 } 08975 if (ret == 0) { 08976 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 08977 } 08978 if (ret == 0) { 08979 page_rw.emb_func_lir = val->emb_latched; 08980 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t*) &page_rw, 1); 08981 } 08982 if (ret == 0) { 08983 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 08984 } 08985 return ret; 08986 } 08987 08988 /** 08989 * @brief Route interrupt signals on int1 pin.[set] 08990 * 08991 * @param ctx communication interface handler.(ptr) 08992 * @param val the signals to route on int1 pin. 08993 * 08994 */ 08995 int32_t lsm6dso_pin_int1_route_set(lsm6dso_ctx_t *ctx, 08996 lsm6dso_pin_int1_route_t val) 08997 { 08998 lsm6dso_pin_int2_route_t pin_int2_route; 08999 lsm6dso_emb_func_int1_t emb_func_int1; 09000 lsm6dso_fsm_int1_a_t fsm_int1_a; 09001 lsm6dso_fsm_int1_b_t fsm_int1_b; 09002 lsm6dso_int1_ctrl_t int1_ctrl; 09003 lsm6dso_int2_ctrl_t int2_ctrl; 09004 lsm6dso_tap_cfg2_t tap_cfg2; 09005 lsm6dso_md2_cfg_t md2_cfg; 09006 lsm6dso_md1_cfg_t md1_cfg; 09007 lsm6dso_ctrl4_c_t ctrl4_c; 09008 int32_t ret; 09009 09010 int1_ctrl.int1_drdy_xl = val.drdy_xl; 09011 int1_ctrl.int1_drdy_g = val.drdy_g; 09012 int1_ctrl.int1_boot = val.boot; 09013 int1_ctrl.int1_fifo_th = val.fifo_th; 09014 int1_ctrl.int1_fifo_ovr = val.fifo_ovr; 09015 int1_ctrl.int1_fifo_full = val.fifo_full; 09016 int1_ctrl.int1_cnt_bdr = val.fifo_bdr; 09017 int1_ctrl.den_drdy_flag = val.den_flag; 09018 09019 md1_cfg.int1_shub = val.sh_endop; 09020 md1_cfg.int1_6d = val.six_d; 09021 md1_cfg.int1_double_tap = val.double_tap; 09022 md1_cfg.int1_ff = val.free_fall; 09023 md1_cfg.int1_wu = val.wake_up; 09024 md1_cfg.int1_single_tap = val.single_tap; 09025 md1_cfg.int1_sleep_change = val.sleep_change; 09026 09027 emb_func_int1.not_used_01 = 0; 09028 emb_func_int1.int1_step_detector = val.step_detector; 09029 emb_func_int1.int1_tilt = val.tilt; 09030 emb_func_int1.int1_sig_mot = val.sig_mot; 09031 emb_func_int1.not_used_02 = 0; 09032 emb_func_int1.int1_fsm_lc = val.fsm_lc; 09033 09034 fsm_int1_a.int1_fsm1 = val.fsm1; 09035 fsm_int1_a.int1_fsm2 = val.fsm2; 09036 fsm_int1_a.int1_fsm3 = val.fsm3; 09037 fsm_int1_a.int1_fsm4 = val.fsm4; 09038 fsm_int1_a.int1_fsm5 = val.fsm5; 09039 fsm_int1_a.int1_fsm6 = val.fsm6; 09040 fsm_int1_a.int1_fsm7 = val.fsm7; 09041 fsm_int1_a.int1_fsm8 = val.fsm8; 09042 09043 fsm_int1_b.int1_fsm9 = val.fsm9 ; 09044 fsm_int1_b.int1_fsm10 = val.fsm10; 09045 fsm_int1_b.int1_fsm11 = val.fsm11; 09046 fsm_int1_b.int1_fsm12 = val.fsm12; 09047 fsm_int1_b.int1_fsm13 = val.fsm13; 09048 fsm_int1_b.int1_fsm14 = val.fsm14; 09049 fsm_int1_b.int1_fsm15 = val.fsm15; 09050 fsm_int1_b.int1_fsm16 = val.fsm16; 09051 09052 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 09053 if (ret == 0) { 09054 if( ( val.drdy_temp | val.timestamp ) != PROPERTY_DISABLE) { 09055 ctrl4_c.int2_on_int1 = PROPERTY_ENABLE; 09056 } 09057 else{ 09058 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE; 09059 } 09060 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 09061 } 09062 09063 if (ret == 0) { 09064 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 09065 } 09066 if (ret == 0) { 09067 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT1, 09068 (uint8_t*)&emb_func_int1, 1); 09069 } 09070 if (ret == 0) { 09071 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_A, 09072 (uint8_t*)&fsm_int1_a, 1); 09073 } 09074 if (ret == 0) { 09075 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_B, 09076 (uint8_t*)&fsm_int1_b, 1); 09077 } 09078 if (ret == 0) { 09079 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 09080 } 09081 09082 if (ret == 0) { 09083 if ( ( emb_func_int1.int1_fsm_lc 09084 | emb_func_int1.int1_sig_mot 09085 | emb_func_int1.int1_step_detector 09086 | emb_func_int1.int1_tilt 09087 | fsm_int1_a.int1_fsm1 09088 | fsm_int1_a.int1_fsm2 09089 | fsm_int1_a.int1_fsm3 09090 | fsm_int1_a.int1_fsm4 09091 | fsm_int1_a.int1_fsm5 09092 | fsm_int1_a.int1_fsm6 09093 | fsm_int1_a.int1_fsm7 09094 | fsm_int1_a.int1_fsm8 09095 | fsm_int1_b.int1_fsm9 09096 | fsm_int1_b.int1_fsm10 09097 | fsm_int1_b.int1_fsm11 09098 | fsm_int1_b.int1_fsm12 09099 | fsm_int1_b.int1_fsm13 09100 | fsm_int1_b.int1_fsm14 09101 | fsm_int1_b.int1_fsm15 09102 | fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE){ 09103 md1_cfg.int1_emb_func = PROPERTY_ENABLE; 09104 } 09105 else{ 09106 md1_cfg.int1_emb_func = PROPERTY_DISABLE; 09107 } 09108 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT1_CTRL, 09109 (uint8_t*)&int1_ctrl, 1); 09110 } 09111 if (ret == 0) { 09112 ret = lsm6dso_write_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t*)&md1_cfg, 1); 09113 } 09114 09115 if (ret == 0) { 09116 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); 09117 } 09118 if (ret == 0) { 09119 int2_ctrl.int2_drdy_temp = val.drdy_temp; 09120 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); 09121 } 09122 if (ret == 0) { 09123 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1); 09124 } 09125 if (ret == 0) { 09126 md2_cfg.int2_timestamp = val.timestamp; 09127 ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1); 09128 } 09129 09130 if (ret == 0) { 09131 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); 09132 } 09133 if (ret == 0) { 09134 ret = lsm6dso_pin_int2_route_get(ctx, NULL, &pin_int2_route); 09135 } 09136 if (ret == 0) { 09137 if ( ( pin_int2_route.fifo_bdr 09138 | pin_int2_route.drdy_g 09139 | pin_int2_route.drdy_temp 09140 | pin_int2_route.drdy_xl 09141 | pin_int2_route.fifo_full 09142 | pin_int2_route.fifo_ovr 09143 | pin_int2_route.fifo_th 09144 | pin_int2_route.six_d 09145 | pin_int2_route.double_tap 09146 | pin_int2_route.free_fall 09147 | pin_int2_route.wake_up 09148 | pin_int2_route.single_tap 09149 | pin_int2_route.sleep_change 09150 | int1_ctrl.den_drdy_flag 09151 | int1_ctrl.int1_boot 09152 | int1_ctrl.int1_cnt_bdr 09153 | int1_ctrl.int1_drdy_g 09154 | int1_ctrl.int1_drdy_xl 09155 | int1_ctrl.int1_fifo_full 09156 | int1_ctrl.int1_fifo_ovr 09157 | int1_ctrl.int1_fifo_th 09158 | md1_cfg.int1_shub 09159 | md1_cfg.int1_6d 09160 | md1_cfg.int1_double_tap 09161 | md1_cfg.int1_ff 09162 | md1_cfg.int1_wu 09163 | md1_cfg.int1_single_tap 09164 | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE) { 09165 tap_cfg2.interrupts_enable = PROPERTY_ENABLE; 09166 } 09167 else{ 09168 tap_cfg2.interrupts_enable = PROPERTY_DISABLE; 09169 } 09170 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); 09171 } 09172 return ret; 09173 } 09174 09175 /** 09176 * @brief Route interrupt signals on int1 pin.[get] 09177 * 09178 * @param ctx communication interface handler.(ptr) 09179 * @param val the signals that are routed on int1 pin.(ptr) 09180 * 09181 */ 09182 int32_t lsm6dso_pin_int1_route_get(lsm6dso_ctx_t *ctx, 09183 lsm6dso_pin_int1_route_t *val) 09184 { 09185 lsm6dso_emb_func_int1_t emb_func_int1; 09186 lsm6dso_fsm_int1_a_t fsm_int1_a; 09187 lsm6dso_fsm_int1_b_t fsm_int1_b; 09188 lsm6dso_int1_ctrl_t int1_ctrl; 09189 lsm6dso_int2_ctrl_t int2_ctrl; 09190 lsm6dso_md2_cfg_t md2_cfg; 09191 lsm6dso_md1_cfg_t md1_cfg; 09192 lsm6dso_ctrl4_c_t ctrl4_c; 09193 int32_t ret; 09194 09195 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 09196 if (ret == 0) { 09197 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT1, 09198 (uint8_t*)&emb_func_int1, 1); 09199 } 09200 if (ret == 0) { 09201 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_A, 09202 (uint8_t*)&fsm_int1_a, 1); 09203 } 09204 if (ret == 0) { 09205 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_B, 09206 (uint8_t*)&fsm_int1_b, 1); 09207 } 09208 if (ret == 0) { 09209 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 09210 } 09211 if (ret == 0) { 09212 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT1_CTRL, 09213 (uint8_t*)&int1_ctrl, 1); 09214 } 09215 if (ret == 0) { 09216 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t*)&md1_cfg, 1); 09217 } 09218 if (ret == 0) { 09219 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 09220 } 09221 if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE){ 09222 if (ret == 0) { 09223 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t*)&int2_ctrl, 1); 09224 val->drdy_temp = int2_ctrl.int2_drdy_temp; 09225 } 09226 if (ret == 0) { 09227 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1); 09228 val->timestamp = md2_cfg.int2_timestamp; 09229 } 09230 } 09231 else { 09232 val->drdy_temp = PROPERTY_DISABLE; 09233 val->timestamp = PROPERTY_DISABLE; 09234 } 09235 09236 val->drdy_xl = int1_ctrl.int1_drdy_xl; 09237 val->drdy_g = int1_ctrl.int1_drdy_g; 09238 val->boot = int1_ctrl.int1_boot; 09239 val->fifo_th = int1_ctrl.int1_fifo_th; 09240 val->fifo_ovr = int1_ctrl.int1_fifo_ovr; 09241 val->fifo_full = int1_ctrl.int1_fifo_full; 09242 val->fifo_bdr = int1_ctrl.int1_cnt_bdr; 09243 val->den_flag = int1_ctrl.den_drdy_flag; 09244 09245 val->sh_endop = md1_cfg.int1_shub; 09246 val->six_d = md1_cfg.int1_6d; 09247 val->double_tap = md1_cfg.int1_double_tap; 09248 val->free_fall = md1_cfg.int1_ff; 09249 val->wake_up = md1_cfg.int1_wu; 09250 val->single_tap = md1_cfg.int1_single_tap; 09251 val->sleep_change = md1_cfg.int1_sleep_change; 09252 09253 val->step_detector = emb_func_int1.int1_step_detector; 09254 val->tilt = emb_func_int1.int1_tilt; 09255 val->sig_mot = emb_func_int1.int1_sig_mot; 09256 val->fsm_lc = emb_func_int1.int1_fsm_lc; 09257 09258 val->fsm1 = fsm_int1_a.int1_fsm1; 09259 val->fsm2 = fsm_int1_a.int1_fsm2; 09260 val->fsm3 = fsm_int1_a.int1_fsm3; 09261 val->fsm4 = fsm_int1_a.int1_fsm4; 09262 val->fsm5 = fsm_int1_a.int1_fsm5; 09263 val->fsm6 = fsm_int1_a.int1_fsm6; 09264 val->fsm7 = fsm_int1_a.int1_fsm7; 09265 val->fsm8 = fsm_int1_a.int1_fsm8; 09266 09267 val->fsm9 = fsm_int1_b.int1_fsm9; 09268 val->fsm10 = fsm_int1_b.int1_fsm10; 09269 val->fsm11 = fsm_int1_b.int1_fsm11; 09270 val->fsm12 = fsm_int1_b.int1_fsm12; 09271 val->fsm13 = fsm_int1_b.int1_fsm13; 09272 val->fsm14 = fsm_int1_b.int1_fsm14; 09273 val->fsm15 = fsm_int1_b.int1_fsm15; 09274 val->fsm16 = fsm_int1_b.int1_fsm16; 09275 09276 return ret; 09277 } 09278 09279 /** 09280 * @brief Route interrupt signals on int2 pin.[set] 09281 * 09282 * @param ctx communication interface handler. Use NULL to ingnore 09283 * this interface.(ptr) 09284 * @param aux_ctx auxiliary communication interface handler. Use NULL 09285 * to ingnore this interface.(ptr) 09286 * @param val the signals to route on int2 pin. 09287 * 09288 */ 09289 int32_t lsm6dso_pin_int2_route_set(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 09290 lsm6dso_pin_int2_route_t val) 09291 { 09292 lsm6dso_pin_int1_route_t pin_int1_route; 09293 lsm6dso_emb_func_int2_t emb_func_int2; 09294 lsm6dso_fsm_int2_a_t fsm_int2_a; 09295 lsm6dso_fsm_int2_b_t fsm_int2_b; 09296 lsm6dso_int2_ctrl_t int2_ctrl; 09297 lsm6dso_tap_cfg2_t tap_cfg2; 09298 lsm6dso_md2_cfg_t md2_cfg; 09299 lsm6dso_ctrl4_c_t ctrl4_c; 09300 lsm6dso_int_ois_t int_ois; 09301 int32_t ret; 09302 09303 ret = 0; 09304 09305 if( aux_ctx != NULL ) { 09306 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS, 09307 (uint8_t*)&int_ois, 1); 09308 if (ret == 0) { 09309 int_ois.int2_drdy_ois = val.drdy_ois; 09310 ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_INT_OIS, 09311 (uint8_t*)&int_ois, 1); 09312 } 09313 } 09314 09315 if( ctx != NULL ) { 09316 int2_ctrl.int2_drdy_xl = val.drdy_xl; 09317 int2_ctrl.int2_drdy_g = val.drdy_g; 09318 int2_ctrl.int2_drdy_temp = val.drdy_temp; 09319 int2_ctrl.int2_fifo_th = val.fifo_th; 09320 int2_ctrl.int2_fifo_ovr = val.fifo_ovr; 09321 int2_ctrl.int2_fifo_full = val.fifo_full; 09322 int2_ctrl.int2_cnt_bdr = val.fifo_bdr; 09323 int2_ctrl.not_used_01 = 0; 09324 09325 md2_cfg.int2_timestamp = val.timestamp; 09326 md2_cfg.int2_6d = val.six_d; 09327 md2_cfg.int2_double_tap = val.double_tap; 09328 md2_cfg.int2_ff = val.free_fall; 09329 md2_cfg.int2_wu = val.wake_up; 09330 md2_cfg.int2_single_tap = val.single_tap; 09331 md2_cfg.int2_sleep_change = val.sleep_change; 09332 09333 emb_func_int2.not_used_01 = 0; 09334 emb_func_int2. int2_step_detector = val.step_detector; 09335 emb_func_int2.int2_tilt = val.tilt; 09336 emb_func_int2.int2_sig_mot = val.sig_mot; 09337 emb_func_int2.not_used_02 = 0; 09338 emb_func_int2.int2_fsm_lc = val.fsm_lc; 09339 09340 fsm_int2_a.int2_fsm1 = val.fsm1; 09341 fsm_int2_a.int2_fsm2 = val.fsm2; 09342 fsm_int2_a.int2_fsm3 = val.fsm3; 09343 fsm_int2_a.int2_fsm4 = val.fsm4; 09344 fsm_int2_a.int2_fsm5 = val.fsm5; 09345 fsm_int2_a.int2_fsm6 = val.fsm6; 09346 fsm_int2_a.int2_fsm7 = val.fsm7; 09347 fsm_int2_a.int2_fsm8 = val.fsm8; 09348 09349 fsm_int2_b.int2_fsm9 = val.fsm9 ; 09350 fsm_int2_b.int2_fsm10 = val.fsm10; 09351 fsm_int2_b.int2_fsm11 = val.fsm11; 09352 fsm_int2_b.int2_fsm12 = val.fsm12; 09353 fsm_int2_b.int2_fsm13 = val.fsm13; 09354 fsm_int2_b.int2_fsm14 = val.fsm14; 09355 fsm_int2_b.int2_fsm15 = val.fsm15; 09356 fsm_int2_b.int2_fsm16 = val.fsm16; 09357 09358 if (ret == 0) { 09359 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 09360 if (ret == 0) { 09361 if ( ( val.drdy_temp | val.timestamp ) != PROPERTY_DISABLE ) { 09362 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE; 09363 } 09364 09365 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 09366 } 09367 } 09368 09369 if (ret == 0) { 09370 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 09371 } 09372 if (ret == 0) { 09373 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT2, 09374 (uint8_t*)&emb_func_int2, 1); 09375 } 09376 if (ret == 0) { 09377 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_A, 09378 (uint8_t*)&fsm_int2_a, 1); 09379 } 09380 if (ret == 0) { 09381 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_B, 09382 (uint8_t*)&fsm_int2_b, 1); 09383 } 09384 if (ret == 0) { 09385 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 09386 } 09387 09388 if (ret == 0) { 09389 if (( emb_func_int2.int2_fsm_lc 09390 | emb_func_int2.int2_sig_mot 09391 | emb_func_int2.int2_step_detector 09392 | emb_func_int2.int2_tilt 09393 | fsm_int2_a.int2_fsm1 09394 | fsm_int2_a.int2_fsm2 09395 | fsm_int2_a.int2_fsm3 09396 | fsm_int2_a.int2_fsm4 09397 | fsm_int2_a.int2_fsm5 09398 | fsm_int2_a.int2_fsm6 09399 | fsm_int2_a.int2_fsm7 09400 | fsm_int2_a.int2_fsm8 09401 | fsm_int2_b.int2_fsm9 09402 | fsm_int2_b.int2_fsm10 09403 | fsm_int2_b.int2_fsm11 09404 | fsm_int2_b.int2_fsm12 09405 | fsm_int2_b.int2_fsm13 09406 | fsm_int2_b.int2_fsm14 09407 | fsm_int2_b.int2_fsm15 09408 | fsm_int2_b.int2_fsm16)!= PROPERTY_DISABLE ){ 09409 md2_cfg.int2_emb_func = PROPERTY_ENABLE; 09410 } 09411 else{ 09412 md2_cfg.int2_emb_func = PROPERTY_DISABLE; 09413 } 09414 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL, 09415 (uint8_t*)&int2_ctrl, 1); 09416 } 09417 if (ret == 0) { 09418 ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1); 09419 } 09420 if (ret == 0) { 09421 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); 09422 } 09423 09424 if (ret == 0) { 09425 ret = lsm6dso_pin_int1_route_get(ctx, &pin_int1_route); 09426 } 09427 09428 if (ret == 0) { 09429 if ( ( val.fifo_bdr 09430 | val.drdy_g 09431 | val.drdy_temp 09432 | val.drdy_xl 09433 | val.fifo_full 09434 | val.fifo_ovr 09435 | val.fifo_th 09436 | val.six_d 09437 | val.double_tap 09438 | val.free_fall 09439 | val.wake_up 09440 | val.single_tap 09441 | val.sleep_change 09442 | pin_int1_route.den_flag 09443 | pin_int1_route.boot 09444 | pin_int1_route.fifo_bdr 09445 | pin_int1_route.drdy_g 09446 | pin_int1_route.drdy_xl 09447 | pin_int1_route.fifo_full 09448 | pin_int1_route.fifo_ovr 09449 | pin_int1_route.fifo_th 09450 | pin_int1_route.six_d 09451 | pin_int1_route.double_tap 09452 | pin_int1_route.free_fall 09453 | pin_int1_route.wake_up 09454 | pin_int1_route.single_tap 09455 | pin_int1_route.sleep_change ) != PROPERTY_DISABLE) { 09456 tap_cfg2.interrupts_enable = PROPERTY_ENABLE; 09457 } 09458 else{ 09459 tap_cfg2.interrupts_enable = PROPERTY_DISABLE; 09460 } 09461 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t*) &tap_cfg2, 1); 09462 } 09463 } 09464 return ret; 09465 } 09466 09467 /** 09468 * @brief Route interrupt signals on int2 pin.[get] 09469 * 09470 * @param ctx communication interface handler. Use NULL to ingnore 09471 * this interface.(ptr) 09472 * @param aux_ctx auxiliary communication interface handler. Use NULL 09473 * to ingnore this interface.(ptr) 09474 * @param val the signals that are routed on int2 pin.(ptr) 09475 * 09476 */ 09477 int32_t lsm6dso_pin_int2_route_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 09478 lsm6dso_pin_int2_route_t *val) 09479 { 09480 lsm6dso_emb_func_int2_t emb_func_int2; 09481 lsm6dso_fsm_int2_a_t fsm_int2_a; 09482 lsm6dso_fsm_int2_b_t fsm_int2_b; 09483 lsm6dso_int2_ctrl_t int2_ctrl; 09484 lsm6dso_md2_cfg_t md2_cfg; 09485 lsm6dso_ctrl4_c_t ctrl4_c; 09486 lsm6dso_int_ois_t int_ois; 09487 int32_t ret; 09488 09489 ret = 0; 09490 09491 if( aux_ctx != NULL ) { 09492 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS, 09493 (uint8_t*)&int_ois, 1); 09494 val->drdy_ois = int_ois.int2_drdy_ois; 09495 } 09496 09497 if( ctx != NULL ) { 09498 if (ret == 0) { 09499 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 09500 } 09501 if (ret == 0) { 09502 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT2, 09503 (uint8_t*)&emb_func_int2, 1); 09504 } 09505 if (ret == 0) { 09506 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_A, 09507 (uint8_t*)&fsm_int2_a, 1); 09508 } 09509 if (ret == 0) { 09510 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_B, 09511 (uint8_t*)&fsm_int2_b, 1); 09512 } 09513 if (ret == 0) { 09514 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 09515 } 09516 if (ret == 0) { 09517 09518 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, 09519 (uint8_t*)&int2_ctrl, 1); 09520 } 09521 if (ret == 0) { 09522 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, 09523 (uint8_t*)&md2_cfg, 1); 09524 } 09525 09526 if (ret == 0) { 09527 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t*)&ctrl4_c, 1); 09528 } 09529 if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE){ 09530 if (ret == 0) { 09531 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, 09532 (uint8_t*)&int2_ctrl, 1); 09533 val->drdy_temp = int2_ctrl.int2_drdy_temp; 09534 } 09535 if (ret == 0) { 09536 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t*)&md2_cfg, 1); 09537 val->timestamp = md2_cfg.int2_timestamp; 09538 } 09539 } 09540 else { 09541 val->drdy_temp = PROPERTY_DISABLE; 09542 val->timestamp = PROPERTY_DISABLE; 09543 } 09544 09545 val->drdy_xl = int2_ctrl.int2_drdy_xl; 09546 val->drdy_g = int2_ctrl.int2_drdy_g; 09547 val->drdy_temp = int2_ctrl.int2_drdy_temp; 09548 val->fifo_th = int2_ctrl.int2_fifo_th; 09549 val->fifo_ovr = int2_ctrl.int2_fifo_ovr; 09550 val->fifo_full = int2_ctrl.int2_fifo_full; 09551 val->fifo_bdr = int2_ctrl.int2_cnt_bdr; 09552 09553 val->timestamp = md2_cfg.int2_timestamp; 09554 val->six_d = md2_cfg.int2_6d; 09555 val->double_tap = md2_cfg.int2_double_tap; 09556 val->free_fall = md2_cfg.int2_ff; 09557 val->wake_up = md2_cfg.int2_wu; 09558 val->single_tap = md2_cfg.int2_single_tap; 09559 val->sleep_change = md2_cfg.int2_sleep_change; 09560 09561 val->step_detector = emb_func_int2. int2_step_detector; 09562 val->tilt = emb_func_int2.int2_tilt; 09563 val->fsm_lc = emb_func_int2.int2_fsm_lc; 09564 09565 val->fsm1 = fsm_int2_a.int2_fsm1; 09566 val->fsm2 = fsm_int2_a.int2_fsm2; 09567 val->fsm3 = fsm_int2_a.int2_fsm3; 09568 val->fsm4 = fsm_int2_a.int2_fsm4; 09569 val->fsm5 = fsm_int2_a.int2_fsm5; 09570 val->fsm6 = fsm_int2_a.int2_fsm6; 09571 val->fsm7 = fsm_int2_a.int2_fsm7; 09572 val->fsm8 = fsm_int2_a.int2_fsm8; 09573 09574 val->fsm9 = fsm_int2_b.int2_fsm9; 09575 val->fsm10 = fsm_int2_b.int2_fsm10; 09576 val->fsm11 = fsm_int2_b.int2_fsm11; 09577 val->fsm12 = fsm_int2_b.int2_fsm12; 09578 val->fsm13 = fsm_int2_b.int2_fsm13; 09579 val->fsm14 = fsm_int2_b.int2_fsm14; 09580 val->fsm15 = fsm_int2_b.int2_fsm15; 09581 val->fsm16 = fsm_int2_b.int2_fsm16; 09582 09583 } 09584 09585 return ret; 09586 } 09587 09588 /** 09589 * @brief Get the status of all the interrupt sources.[get] 09590 * 09591 * @param ctx communication interface handler.(ptr) 09592 * @param val the status of all the interrupt sources.(ptr) 09593 * 09594 */ 09595 int32_t lsm6dso_all_sources_get(lsm6dso_ctx_t *ctx, 09596 lsm6dso_all_sources_t *val) 09597 { 09598 lsm6dso_emb_func_status_mainpage_t emb_func_status_mainpage; 09599 lsm6dso_status_master_mainpage_t status_master_mainpage; 09600 lsm6dso_fsm_status_a_mainpage_t fsm_status_a_mainpage; 09601 lsm6dso_fsm_status_b_mainpage_t fsm_status_b_mainpage; 09602 lsm6dso_fifo_status1_t fifo_status1; 09603 lsm6dso_fifo_status2_t fifo_status2; 09604 lsm6dso_all_int_src_t all_int_src; 09605 lsm6dso_wake_up_src_t wake_up_src; 09606 lsm6dso_status_reg_t status_reg; 09607 lsm6dso_tap_src_t tap_src; 09608 lsm6dso_d6d_src_t d6d_src; 09609 lsm6dso_ctrl5_c_t ctrl5_c; 09610 uint8_t reg[12]; 09611 int32_t ret; 09612 09613 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&ctrl5_c, 1); 09614 if (ret == 0) { 09615 ctrl5_c.not_used_01 = PROPERTY_ENABLE; 09616 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&ctrl5_c, 1); 09617 } 09618 if (ret == 0) { 09619 ret = lsm6dso_read_reg(ctx, LSM6DSO_ALL_INT_SRC, reg, 12); 09620 } 09621 09622 if (ret == 0) { 09623 bytecpy(( uint8_t*)&all_int_src, ®[0]); 09624 bytecpy(( uint8_t*)&wake_up_src, ®[1]); 09625 bytecpy(( uint8_t*)&tap_src, ®[2]); 09626 bytecpy(( uint8_t*)&d6d_src, ®[3]); 09627 bytecpy(( uint8_t*)&status_reg, ®[4]); 09628 bytecpy(( uint8_t*)&emb_func_status_mainpage, ®[5]); 09629 bytecpy(( uint8_t*)&fsm_status_a_mainpage, ®[6]); 09630 bytecpy(( uint8_t*)&fsm_status_b_mainpage, ®[7]); 09631 bytecpy(( uint8_t*)&status_master_mainpage, ®[9]); 09632 bytecpy(( uint8_t*)&fifo_status1, ®[10]); 09633 bytecpy(( uint8_t*)&fifo_status2, ®[11]); 09634 09635 val->timestamp = all_int_src.timestamp_endcount; 09636 09637 val->wake_up_z = wake_up_src.z_wu; 09638 val->wake_up_y = wake_up_src.y_wu; 09639 val->wake_up_x = wake_up_src.x_wu; 09640 val->wake_up = wake_up_src.wu_ia; 09641 val->sleep_state = wake_up_src.sleep_state; 09642 val->free_fall = wake_up_src.ff_ia; 09643 val->sleep_change = wake_up_src.sleep_change_ia; 09644 09645 val->tap_x = tap_src.x_tap; 09646 val->tap_y = tap_src.y_tap; 09647 val->tap_z = tap_src.z_tap; 09648 val->tap_sign = tap_src.tap_sign; 09649 val->double_tap = tap_src.double_tap; 09650 val->single_tap = tap_src.single_tap; 09651 09652 val->six_d_xl = d6d_src.xl; 09653 val->six_d_xh = d6d_src.xh; 09654 val->six_d_yl = d6d_src.yl; 09655 val->six_d_yh = d6d_src.yh; 09656 val->six_d_zl = d6d_src.zl; 09657 val->six_d_zh = d6d_src.zh; 09658 val->six_d = d6d_src.d6d_ia; 09659 val->den_flag = d6d_src.den_drdy; 09660 09661 val->drdy_xl = status_reg.xlda; 09662 val->drdy_g = status_reg.gda; 09663 val->drdy_temp = status_reg.tda; 09664 09665 val->step_detector = emb_func_status_mainpage.is_step_det; 09666 val->tilt = emb_func_status_mainpage.is_tilt; 09667 val->sig_mot = emb_func_status_mainpage.is_sigmot; 09668 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc; 09669 09670 val->fsm1 = fsm_status_a_mainpage.is_fsm1; 09671 val->fsm2 = fsm_status_a_mainpage.is_fsm2; 09672 val->fsm3 = fsm_status_a_mainpage.is_fsm3; 09673 val->fsm4 = fsm_status_a_mainpage.is_fsm4; 09674 val->fsm5 = fsm_status_a_mainpage.is_fsm5; 09675 val->fsm6 = fsm_status_a_mainpage.is_fsm6; 09676 val->fsm7 = fsm_status_a_mainpage.is_fsm7; 09677 val->fsm8 = fsm_status_a_mainpage.is_fsm8; 09678 09679 val->fsm9 = fsm_status_b_mainpage.is_fsm9; 09680 val->fsm10 = fsm_status_b_mainpage.is_fsm10; 09681 val->fsm11 = fsm_status_b_mainpage.is_fsm11; 09682 val->fsm12 = fsm_status_b_mainpage.is_fsm12; 09683 val->fsm13 = fsm_status_b_mainpage.is_fsm13; 09684 val->fsm14 = fsm_status_b_mainpage.is_fsm14; 09685 val->fsm15 = fsm_status_b_mainpage.is_fsm15; 09686 val->fsm16 = fsm_status_b_mainpage.is_fsm16; 09687 09688 val->sh_endop = status_master_mainpage.sens_hub_endop; 09689 val->sh_slave0_nack = status_master_mainpage.slave0_nack; 09690 val->sh_slave1_nack = status_master_mainpage.slave1_nack; 09691 val->sh_slave2_nack = status_master_mainpage.slave2_nack; 09692 val->sh_slave3_nack = status_master_mainpage.slave3_nack; 09693 val->sh_wr_once = status_master_mainpage.wr_once_done; 09694 09695 val->fifo_diff = (256U * fifo_status2.diff_fifo) + fifo_status1.diff_fifo; 09696 09697 val->fifo_ovr_latched = fifo_status2.over_run_latched; 09698 val->fifo_bdr = fifo_status2.counter_bdr_ia; 09699 val->fifo_full = fifo_status2.fifo_full_ia; 09700 val->fifo_ovr = fifo_status2.fifo_ovr_ia; 09701 val->fifo_th = fifo_status2.fifo_wtm_ia; 09702 09703 ctrl5_c.not_used_01 = PROPERTY_DISABLE; 09704 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t*)&ctrl5_c, 1); 09705 09706 } 09707 09708 return ret; 09709 } 09710 09711 /** 09712 * @brief Sensor conversion parameters selection.[set] 09713 * 09714 * @param ctx communication interface handler. Use NULL to ingnore 09715 * this interface.(ptr) 09716 * @param aux_ctx auxiliary communication interface handler. Use NULL 09717 * to ingnore this interface.(ptr) 09718 * @param val set the sensor conversion parameters by checking 09719 * the constraints of the device.(ptr) 09720 * 09721 */ 09722 int32_t lsm6dso_mode_set(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 09723 lsm6dso_md_t *val) 09724 { 09725 lsm6dso_func_cfg_access_t func_cfg_access; 09726 lsm6dso_ctrl1_ois_t ctrl1_ois; 09727 lsm6dso_ctrl2_ois_t ctrl2_ois; 09728 lsm6dso_ctrl3_ois_t ctrl3_ois; 09729 lsm6dso_ctrl1_xl_t ctrl1_xl; 09730 lsm6dso_ctrl8_xl_t ctrl8_xl; 09731 lsm6dso_ctrl2_g_t ctrl2_g; 09732 lsm6dso_ctrl3_c_t ctrl3_c; 09733 lsm6dso_ctrl4_c_t ctrl4_c; 09734 lsm6dso_ctrl5_c_t ctrl5_c; 09735 lsm6dso_ctrl6_c_t ctrl6_c; 09736 lsm6dso_ctrl7_g_t ctrl7_g; 09737 uint8_t xl_hm_mode; 09738 uint8_t g_hm_mode; 09739 uint8_t xl_ulp_en; 09740 uint8_t odr_gy; 09741 uint8_t odr_xl; 09742 uint8_t reg[8]; 09743 int32_t ret; 09744 09745 ret = 0; 09746 09747 /* reading input configuration */ 09748 xl_hm_mode = ( (uint8_t)val->ui.xl.odr & 0x10U ) >> 4; 09749 xl_ulp_en = ( (uint8_t)val->ui.xl.odr & 0x20U ) >> 5; 09750 odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU; 09751 09752 /* if enable xl ultra low power mode disable gy and OIS chain */ 09753 if (xl_ulp_en == PROPERTY_ENABLE) { 09754 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF; 09755 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF; 09756 val->ui.gy.odr = LSM6DSO_GY_UI_OFF; 09757 } 09758 /* if OIS xl is enabled also gyro OIS is enabled */ 09759 if (val->ois.xl.odr == LSM6DSO_XL_OIS_6667Hz_HP){ 09760 val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP; 09761 } 09762 g_hm_mode = ( (uint8_t)val->ui.gy.odr & 0x10U ) >> 4; 09763 odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU; 09764 09765 /* reading registers to be configured */ 09766 if( ctx != NULL ) { 09767 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 8); 09768 bytecpy(( uint8_t*)&ctrl1_xl, ®[0]); 09769 bytecpy(( uint8_t*)&ctrl2_g, ®[1]); 09770 bytecpy(( uint8_t*)&ctrl3_c, ®[2]); 09771 bytecpy(( uint8_t*)&ctrl4_c, ®[3]); 09772 bytecpy(( uint8_t*)&ctrl5_c, ®[4]); 09773 bytecpy(( uint8_t*)&ctrl6_c, ®[5]); 09774 bytecpy(( uint8_t*)&ctrl7_g, ®[6]); 09775 bytecpy(( uint8_t*)&ctrl8_xl, ®[7]); 09776 if ( ret == 0 ) { 09777 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, 09778 (uint8_t*)&func_cfg_access, 1); 09779 } 09780 /* if toggle xl ultra low power mode, turn off xl before reconfigure */ 09781 if (ctrl5_c.xl_ulp_en != xl_ulp_en) { 09782 ctrl1_xl.odr_xl = (uint8_t) 0x00U; 09783 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, 09784 (uint8_t*)&ctrl1_xl, 1); 09785 } 09786 } 09787 09788 /* reading OIS registers to be configured */ 09789 if( aux_ctx != NULL ) { 09790 if (ret == 0) { 09791 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3); 09792 } 09793 bytecpy(( uint8_t*)&ctrl1_ois, ®[0]); 09794 bytecpy(( uint8_t*)&ctrl2_ois, ®[1]); 09795 bytecpy(( uint8_t*)&ctrl3_ois, ®[2]); 09796 } 09797 else { 09798 if( ctx != NULL ) { 09799 if (ret == 0) { 09800 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3); 09801 } 09802 bytecpy(( uint8_t*)&ctrl1_ois, ®[0]); 09803 bytecpy(( uint8_t*)&ctrl2_ois, ®[1]); 09804 bytecpy(( uint8_t*)&ctrl3_ois, ®[2]); 09805 } 09806 } 09807 09808 /* Check the Finite State Machine data rate constraints */ 09809 if (val->fsm.sens != LSM6DSO_FSM_DISABLE) { 09810 switch (val->fsm.odr) { 09811 case LSM6DSO_FSM_12Hz5: 09812 if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl == 0x00U) ) { 09813 odr_xl = 0x01U; 09814 } 09815 if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy == 0x00U) ) { 09816 xl_ulp_en = PROPERTY_DISABLE; 09817 odr_gy = 0x01U; 09818 } 09819 break; 09820 case LSM6DSO_FSM_26Hz: 09821 if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x02U) ) { 09822 odr_xl = 0x02U; 09823 } 09824 if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x02U) ) { 09825 xl_ulp_en = PROPERTY_DISABLE; 09826 odr_gy = 0x02U; 09827 } 09828 break; 09829 case LSM6DSO_FSM_52Hz: 09830 if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x03U) ) { 09831 odr_xl = 0x03U; 09832 } 09833 if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x03U) ) { 09834 xl_ulp_en = PROPERTY_DISABLE; 09835 odr_gy = 0x03U; 09836 } 09837 break; 09838 case LSM6DSO_FSM_104Hz: 09839 if ( (val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x04U) ) { 09840 odr_xl = 0x04U; 09841 } 09842 if ( (val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x04U) ) { 09843 xl_ulp_en = PROPERTY_DISABLE; 09844 odr_gy = 0x04U; 09845 } 09846 break; 09847 default: 09848 odr_xl = 0x00U; 09849 odr_gy = 0x00U; 09850 break; 09851 } 09852 } 09853 09854 /* Updating the accelerometer data rate configuration */ 09855 switch ( ( ctrl5_c.xl_ulp_en << 5 ) | ( ctrl6_c.xl_hm_mode << 4 ) | 09856 ctrl1_xl.odr_xl ) { 09857 case LSM6DSO_XL_UI_OFF: 09858 val->ui.xl.odr = LSM6DSO_XL_UI_OFF; 09859 break; 09860 case LSM6DSO_XL_UI_12Hz5_HP: 09861 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP; 09862 break; 09863 case LSM6DSO_XL_UI_26Hz_HP: 09864 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP; 09865 break; 09866 case LSM6DSO_XL_UI_52Hz_HP: 09867 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP; 09868 break; 09869 case LSM6DSO_XL_UI_104Hz_HP: 09870 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP; 09871 break; 09872 case LSM6DSO_XL_UI_208Hz_HP: 09873 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP; 09874 break; 09875 case LSM6DSO_XL_UI_416Hz_HP: 09876 val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP; 09877 break; 09878 case LSM6DSO_XL_UI_833Hz_HP: 09879 val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP; 09880 break; 09881 case LSM6DSO_XL_UI_1667Hz_HP: 09882 val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP; 09883 break; 09884 case LSM6DSO_XL_UI_3333Hz_HP: 09885 val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP; 09886 break; 09887 case LSM6DSO_XL_UI_6667Hz_HP: 09888 val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP; 09889 break; 09890 case LSM6DSO_XL_UI_1Hz6_LP: 09891 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP; 09892 break; 09893 case LSM6DSO_XL_UI_12Hz5_LP: 09894 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP; 09895 break; 09896 case LSM6DSO_XL_UI_26Hz_LP: 09897 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP; 09898 break; 09899 case LSM6DSO_XL_UI_52Hz_LP: 09900 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP; 09901 break; 09902 case LSM6DSO_XL_UI_104Hz_NM: 09903 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM; 09904 break; 09905 case LSM6DSO_XL_UI_208Hz_NM: 09906 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM; 09907 break; 09908 case LSM6DSO_XL_UI_1Hz6_ULP: 09909 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP; 09910 break; 09911 case LSM6DSO_XL_UI_12Hz5_ULP: 09912 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP; 09913 break; 09914 case LSM6DSO_XL_UI_26Hz_ULP: 09915 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP; 09916 break; 09917 case LSM6DSO_XL_UI_52Hz_ULP: 09918 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP; 09919 break; 09920 case LSM6DSO_XL_UI_104Hz_ULP: 09921 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP; 09922 break; 09923 case LSM6DSO_XL_UI_208Hz_ULP: 09924 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP; 09925 break; 09926 default: 09927 val->ui.xl.odr = LSM6DSO_XL_UI_OFF; 09928 break; 09929 } 09930 09931 /* Updating the accelerometer data rate configuration */ 09932 switch ( (ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g) { 09933 case LSM6DSO_GY_UI_OFF: 09934 val->ui.gy.odr = LSM6DSO_GY_UI_OFF; 09935 break; 09936 case LSM6DSO_GY_UI_12Hz5_LP: 09937 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP; 09938 break; 09939 case LSM6DSO_GY_UI_12Hz5_HP: 09940 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP; 09941 break; 09942 case LSM6DSO_GY_UI_26Hz_LP: 09943 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP; 09944 break; 09945 case LSM6DSO_GY_UI_26Hz_HP: 09946 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP; 09947 break; 09948 case LSM6DSO_GY_UI_52Hz_LP: 09949 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP; 09950 break; 09951 case LSM6DSO_GY_UI_52Hz_HP: 09952 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP; 09953 break; 09954 case LSM6DSO_GY_UI_104Hz_NM: 09955 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM; 09956 break; 09957 case LSM6DSO_GY_UI_104Hz_HP: 09958 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP; 09959 break; 09960 case LSM6DSO_GY_UI_208Hz_NM: 09961 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM; 09962 break; 09963 case LSM6DSO_GY_UI_208Hz_HP: 09964 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP; 09965 break; 09966 case LSM6DSO_GY_UI_416Hz_HP: 09967 val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP; 09968 break; 09969 case LSM6DSO_GY_UI_833Hz_HP: 09970 val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP; 09971 break; 09972 case LSM6DSO_GY_UI_1667Hz_HP: 09973 val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP; 09974 break; 09975 case LSM6DSO_GY_UI_3333Hz_HP: 09976 val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP; 09977 break; 09978 case LSM6DSO_GY_UI_6667Hz_HP: 09979 val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP; 09980 break; 09981 default: 09982 val->ui.gy.odr = LSM6DSO_GY_UI_OFF; 09983 break; 09984 } 09985 09986 /* Check accelerometer full scale constraints */ 09987 /* Full scale of 16g must be the same for UI and OIS */ 09988 if ( (val->ui.xl.fs == LSM6DSO_XL_UI_16g) || 09989 (val->ois.xl.fs == LSM6DSO_XL_OIS_16g) ){ 09990 val->ui.xl.fs = LSM6DSO_XL_UI_16g; 09991 val->ois.xl.fs = LSM6DSO_XL_OIS_16g; 09992 } 09993 09994 /* prapare new configuration */ 09995 09996 /* Full scale of 16g must be the same for UI and OIS */ 09997 if (val->ui.xl.fs == LSM6DSO_XL_UI_16g) { 09998 ctrl8_xl.xl_fs_mode = PROPERTY_DISABLE; 09999 } 10000 else { 10001 ctrl8_xl.xl_fs_mode = PROPERTY_ENABLE; 10002 } 10003 10004 /* OIS new configuration */ 10005 ctrl7_g.ois_on_en = val->ois.ctrl_md & 0x01U; 10006 10007 switch (val->ois.ctrl_md) { 10008 case LSM6DSO_OIS_ONLY_AUX: 10009 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs; 10010 ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr; 10011 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr; 10012 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs; 10013 break; 10014 case LSM6DSO_OIS_MIXED: 10015 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs; 10016 ctrl7_g.ois_on = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr; 10017 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr; 10018 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs; 10019 break; 10020 default: 10021 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs; 10022 ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr; 10023 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr; 10024 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs; 10025 break; 10026 } 10027 10028 /* UI new configuration */ 10029 ctrl1_xl.odr_xl = odr_xl; 10030 ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs; 10031 ctrl5_c.xl_ulp_en = xl_ulp_en; 10032 ctrl6_c.xl_hm_mode = xl_hm_mode; 10033 ctrl7_g.g_hm_mode = g_hm_mode; 10034 ctrl2_g.odr_g = odr_gy; 10035 ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs; 10036 10037 /* writing checked configuration */ 10038 if( ctx != NULL ) { 10039 bytecpy(®[0], ( uint8_t*)&ctrl1_xl); 10040 bytecpy(®[1], ( uint8_t*)&ctrl2_g); 10041 bytecpy(®[2], ( uint8_t*)&ctrl3_c); 10042 bytecpy(®[3], ( uint8_t*)&ctrl4_c); 10043 bytecpy(®[4], ( uint8_t*)&ctrl5_c); 10044 bytecpy(®[5], ( uint8_t*)&ctrl6_c); 10045 bytecpy(®[6], ( uint8_t*)&ctrl7_g); 10046 bytecpy(®[7], ( uint8_t*)&ctrl8_xl); 10047 if ( ret == 0 ) { 10048 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t*)®, 8); 10049 } 10050 if ( ret == 0 ) { 10051 ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, 10052 (uint8_t*)&func_cfg_access, 1); 10053 } 10054 } 10055 10056 /* writing OIS checked configuration */ 10057 if( aux_ctx != NULL ) { 10058 bytecpy(®[0], ( uint8_t*)&ctrl1_ois); 10059 bytecpy(®[1], ( uint8_t*)&ctrl2_ois); 10060 bytecpy(®[2], ( uint8_t*)&ctrl3_ois); 10061 if (ret == 0) { 10062 ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3); 10063 } 10064 } 10065 10066 return ret; 10067 } 10068 10069 /** 10070 * @brief Sensor conversion parameters selection.[get] 10071 * 10072 * @param ctx communication interface handler. Use NULL to ingnore 10073 * this interface.(ptr) 10074 * @param aux_ctx auxiliary communication interface handler. Use NULL 10075 * to ingnore this interface.(ptr) 10076 * @param val get the sensor conversion parameters.(ptr) 10077 * 10078 */ 10079 int32_t lsm6dso_mode_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 10080 lsm6dso_md_t *val) 10081 { 10082 10083 lsm6dso_emb_func_odr_cfg_b_t emb_func_odr_cfg_b; 10084 lsm6dso_func_cfg_access_t func_cfg_access; 10085 lsm6dso_emb_func_en_b_t emb_func_en_b; 10086 lsm6dso_fsm_enable_a_t fsm_enable_a; 10087 lsm6dso_fsm_enable_b_t fsm_enable_b; 10088 lsm6dso_ctrl1_ois_t ctrl1_ois; 10089 lsm6dso_ctrl2_ois_t ctrl2_ois; 10090 lsm6dso_ctrl3_ois_t ctrl3_ois; 10091 lsm6dso_ctrl1_xl_t ctrl1_xl; 10092 lsm6dso_ctrl2_g_t ctrl2_g; 10093 lsm6dso_ctrl3_c_t ctrl3_c; 10094 lsm6dso_ctrl4_c_t ctrl4_c; 10095 lsm6dso_ctrl5_c_t ctrl5_c; 10096 lsm6dso_ctrl6_c_t ctrl6_c; 10097 lsm6dso_ctrl7_g_t ctrl7_g; 10098 10099 uint8_t reg[8]; 10100 int32_t ret; 10101 10102 ret = 0; 10103 10104 /* reading the registers of the device */ 10105 if( ctx != NULL ) { 10106 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 7); 10107 bytecpy(( uint8_t*)&ctrl1_xl, ®[0]); 10108 bytecpy(( uint8_t*)&ctrl2_g, ®[1]); 10109 bytecpy(( uint8_t*)&ctrl3_c, ®[2]); 10110 bytecpy(( uint8_t*)&ctrl4_c, ®[3]); 10111 bytecpy(( uint8_t*)&ctrl5_c, ®[4]); 10112 bytecpy(( uint8_t*)&ctrl6_c, ®[5]); 10113 bytecpy(( uint8_t*)&ctrl7_g, ®[6]); 10114 if ( ret == 0 ) { 10115 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, 10116 (uint8_t*)&func_cfg_access, 1); 10117 } 10118 if (ret == 0) { 10119 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 10120 } 10121 if (ret == 0) { 10122 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, reg, 1); 10123 bytecpy(( uint8_t*)&emb_func_odr_cfg_b, ®[0]); 10124 } 10125 if (ret == 0) { 10126 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 10127 (uint8_t*)&emb_func_en_b, 1); 10128 } 10129 if (ret == 0) { 10130 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, reg, 2); 10131 bytecpy(( uint8_t*)&fsm_enable_a, ®[0]); 10132 bytecpy(( uint8_t*)&fsm_enable_b, ®[1]); 10133 } 10134 if (ret == 0) { 10135 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 10136 } 10137 } 10138 10139 if( aux_ctx != NULL ) { 10140 if (ret == 0) { 10141 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3); 10142 } 10143 bytecpy(( uint8_t*)&ctrl1_ois, ®[0]); 10144 bytecpy(( uint8_t*)&ctrl2_ois, ®[1]); 10145 bytecpy(( uint8_t*)&ctrl3_ois, ®[2]); 10146 } 10147 else { 10148 if( ctx != NULL ) { 10149 if (ret == 0) { 10150 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3); 10151 } 10152 bytecpy(( uint8_t*)&ctrl1_ois, ®[0]); 10153 bytecpy(( uint8_t*)&ctrl2_ois, ®[1]); 10154 bytecpy(( uint8_t*)&ctrl3_ois, ®[2]); 10155 } 10156 } 10157 10158 /* fill the input structure */ 10159 10160 /* get accelerometer configuration */ 10161 switch ( (ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) | 10162 ctrl1_xl.odr_xl ) { 10163 case LSM6DSO_XL_UI_OFF: 10164 val->ui.xl.odr = LSM6DSO_XL_UI_OFF; 10165 break; 10166 case LSM6DSO_XL_UI_12Hz5_HP: 10167 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP; 10168 break; 10169 case LSM6DSO_XL_UI_26Hz_HP: 10170 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP; 10171 break; 10172 case LSM6DSO_XL_UI_52Hz_HP: 10173 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP; 10174 break; 10175 case LSM6DSO_XL_UI_104Hz_HP: 10176 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP; 10177 break; 10178 case LSM6DSO_XL_UI_208Hz_HP: 10179 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP; 10180 break; 10181 case LSM6DSO_XL_UI_416Hz_HP: 10182 val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP; 10183 break; 10184 case LSM6DSO_XL_UI_833Hz_HP: 10185 val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP; 10186 break; 10187 case LSM6DSO_XL_UI_1667Hz_HP: 10188 val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP; 10189 break; 10190 case LSM6DSO_XL_UI_3333Hz_HP: 10191 val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP; 10192 break; 10193 case LSM6DSO_XL_UI_6667Hz_HP: 10194 val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP; 10195 break; 10196 case LSM6DSO_XL_UI_1Hz6_LP: 10197 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP; 10198 break; 10199 case LSM6DSO_XL_UI_12Hz5_LP: 10200 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP; 10201 break; 10202 case LSM6DSO_XL_UI_26Hz_LP: 10203 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP; 10204 break; 10205 case LSM6DSO_XL_UI_52Hz_LP: 10206 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP; 10207 break; 10208 case LSM6DSO_XL_UI_104Hz_NM: 10209 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM; 10210 break; 10211 case LSM6DSO_XL_UI_208Hz_NM: 10212 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM; 10213 break; 10214 case LSM6DSO_XL_UI_1Hz6_ULP: 10215 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP; 10216 break; 10217 case LSM6DSO_XL_UI_12Hz5_ULP: 10218 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP; 10219 break; 10220 case LSM6DSO_XL_UI_26Hz_ULP: 10221 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP; 10222 break; 10223 case LSM6DSO_XL_UI_52Hz_ULP: 10224 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP; 10225 break; 10226 case LSM6DSO_XL_UI_104Hz_ULP: 10227 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP; 10228 break; 10229 case LSM6DSO_XL_UI_208Hz_ULP: 10230 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP; 10231 break; 10232 default: 10233 val->ui.xl.odr = LSM6DSO_XL_UI_OFF; 10234 break; 10235 } 10236 10237 switch ( ctrl1_xl.fs_xl ) { 10238 case LSM6DSO_XL_UI_2g: 10239 val->ui.xl.fs = LSM6DSO_XL_UI_2g; 10240 break; 10241 case LSM6DSO_XL_UI_4g: 10242 val->ui.xl.fs = LSM6DSO_XL_UI_4g; 10243 break; 10244 case LSM6DSO_XL_UI_8g: 10245 val->ui.xl.fs = LSM6DSO_XL_UI_8g; 10246 break; 10247 case LSM6DSO_XL_UI_16g: 10248 val->ui.xl.fs = LSM6DSO_XL_UI_16g; 10249 break; 10250 default: 10251 val->ui.xl.fs = LSM6DSO_XL_UI_2g; 10252 break; 10253 } 10254 10255 /* get gyroscope configuration */ 10256 switch ( (ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g) { 10257 case LSM6DSO_GY_UI_OFF: 10258 val->ui.gy.odr = LSM6DSO_GY_UI_OFF; 10259 break; 10260 case LSM6DSO_GY_UI_12Hz5_LP: 10261 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP; 10262 break; 10263 case LSM6DSO_GY_UI_12Hz5_HP: 10264 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP; 10265 break; 10266 case LSM6DSO_GY_UI_26Hz_LP: 10267 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP; 10268 break; 10269 case LSM6DSO_GY_UI_26Hz_HP: 10270 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP; 10271 break; 10272 case LSM6DSO_GY_UI_52Hz_LP: 10273 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP; 10274 break; 10275 case LSM6DSO_GY_UI_52Hz_HP: 10276 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP; 10277 break; 10278 case LSM6DSO_GY_UI_104Hz_NM: 10279 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM; 10280 break; 10281 case LSM6DSO_GY_UI_104Hz_HP: 10282 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP; 10283 break; 10284 case LSM6DSO_GY_UI_208Hz_NM: 10285 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM; 10286 break; 10287 case LSM6DSO_GY_UI_208Hz_HP: 10288 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP; 10289 break; 10290 case LSM6DSO_GY_UI_416Hz_HP: 10291 val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP; 10292 break; 10293 case LSM6DSO_GY_UI_833Hz_HP: 10294 val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP; 10295 break; 10296 case LSM6DSO_GY_UI_1667Hz_HP: 10297 val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP; 10298 break; 10299 case LSM6DSO_GY_UI_3333Hz_HP: 10300 val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP; 10301 break; 10302 case LSM6DSO_GY_UI_6667Hz_HP: 10303 val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP; 10304 break; 10305 default: 10306 val->ui.gy.odr = LSM6DSO_GY_UI_OFF; 10307 break; 10308 } 10309 10310 switch (ctrl2_g.fs_g) { 10311 case LSM6DSO_GY_UI_125dps: 10312 val->ui.gy.fs = LSM6DSO_GY_UI_125dps; 10313 break; 10314 case LSM6DSO_GY_UI_250dps: 10315 val->ui.gy.fs = LSM6DSO_GY_UI_250dps; 10316 break; 10317 case LSM6DSO_GY_UI_500dps: 10318 val->ui.gy.fs = LSM6DSO_GY_UI_500dps; 10319 break; 10320 case LSM6DSO_GY_UI_1000dps: 10321 val->ui.gy.fs = LSM6DSO_GY_UI_1000dps; 10322 break; 10323 case LSM6DSO_GY_UI_2000dps: 10324 val->ui.gy.fs = LSM6DSO_GY_UI_2000dps; 10325 break; 10326 default: 10327 val->ui.gy.fs = LSM6DSO_GY_UI_125dps; 10328 break; 10329 } 10330 10331 /* get finite state machine configuration */ 10332 if ( (fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en | fsm_enable_a.fsm3_en | 10333 fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en | 10334 fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en | 10335 fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en | 10336 fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en | 10337 fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en | 10338 fsm_enable_b.fsm16_en) == PROPERTY_ENABLE ){ 10339 switch (emb_func_odr_cfg_b.fsm_odr) { 10340 case LSM6DSO_FSM_12Hz5: 10341 val->fsm.odr = LSM6DSO_FSM_12Hz5; 10342 break; 10343 case LSM6DSO_FSM_26Hz: 10344 val->fsm.odr = LSM6DSO_FSM_26Hz; 10345 break; 10346 case LSM6DSO_FSM_52Hz: 10347 val->fsm.odr = LSM6DSO_FSM_52Hz; 10348 break; 10349 case LSM6DSO_FSM_104Hz: 10350 val->fsm.odr = LSM6DSO_FSM_104Hz; 10351 break; 10352 default: 10353 val->fsm.odr = LSM6DSO_FSM_12Hz5; 10354 break; 10355 } 10356 10357 val->fsm.sens = LSM6DSO_FSM_XL_GY; 10358 if (val->ui.gy.odr == LSM6DSO_GY_UI_OFF) { 10359 val->fsm.sens = LSM6DSO_FSM_XL; 10360 } 10361 if (val->ui.xl.odr == LSM6DSO_XL_UI_OFF) { 10362 val->fsm.sens = LSM6DSO_FSM_GY; 10363 } 10364 } 10365 else { 10366 val->fsm.sens = LSM6DSO_FSM_DISABLE; 10367 } 10368 10369 /* get ois configuration */ 10370 10371 /* OIS configuration mode */ 10372 switch ( ctrl7_g.ois_on_en ) { 10373 case LSM6DSO_OIS_ONLY_AUX: 10374 switch ( ctrl3_ois.fs_xl_ois ) { 10375 case LSM6DSO_XL_OIS_2g: 10376 val->ois.xl.fs = LSM6DSO_XL_OIS_2g; 10377 break; 10378 case LSM6DSO_XL_OIS_4g: 10379 val->ois.xl.fs = LSM6DSO_XL_OIS_4g; 10380 break; 10381 case LSM6DSO_XL_OIS_8g: 10382 val->ois.xl.fs = LSM6DSO_XL_OIS_8g; 10383 break; 10384 case LSM6DSO_XL_OIS_16g: 10385 val->ois.xl.fs = LSM6DSO_XL_OIS_16g; 10386 break; 10387 default: 10388 val->ois.xl.fs = LSM6DSO_XL_OIS_2g; 10389 break; 10390 } 10391 switch ( ctrl1_ois.mode4_en ) { 10392 case LSM6DSO_XL_OIS_OFF: 10393 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF; 10394 break; 10395 case LSM6DSO_XL_OIS_6667Hz_HP: 10396 val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP; 10397 break; 10398 default: 10399 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF; 10400 break; 10401 } 10402 switch ( ctrl1_ois.fs_g_ois ) { 10403 case LSM6DSO_GY_OIS_250dps: 10404 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps; 10405 break; 10406 case LSM6DSO_GY_OIS_500dps: 10407 val->ois.gy.fs = LSM6DSO_GY_OIS_500dps; 10408 break; 10409 case LSM6DSO_GY_OIS_1000dps: 10410 val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps; 10411 break; 10412 case LSM6DSO_GY_OIS_2000dps: 10413 val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps; 10414 break; 10415 default: 10416 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps; 10417 break; 10418 } 10419 switch ( ctrl1_ois.ois_en_spi2 ) { 10420 case LSM6DSO_GY_OIS_OFF: 10421 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF; 10422 break; 10423 case LSM6DSO_GY_OIS_6667Hz_HP: 10424 val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP; 10425 break; 10426 default: 10427 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF; 10428 break; 10429 } 10430 val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX; 10431 break; 10432 case LSM6DSO_OIS_MIXED: 10433 switch ( ctrl3_ois.fs_xl_ois ) { 10434 case LSM6DSO_XL_OIS_2g: 10435 val->ois.xl.fs = LSM6DSO_XL_OIS_2g; 10436 break; 10437 case LSM6DSO_XL_OIS_4g: 10438 val->ois.xl.fs = LSM6DSO_XL_OIS_4g; 10439 break; 10440 case LSM6DSO_XL_OIS_8g: 10441 val->ois.xl.fs = LSM6DSO_XL_OIS_8g; 10442 break; 10443 case LSM6DSO_XL_OIS_16g: 10444 val->ois.xl.fs = LSM6DSO_XL_OIS_16g; 10445 break; 10446 default: 10447 val->ois.xl.fs = LSM6DSO_XL_OIS_2g; 10448 break; 10449 } 10450 switch ( ctrl1_ois.mode4_en ) { 10451 case LSM6DSO_XL_OIS_OFF: 10452 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF; 10453 break; 10454 case LSM6DSO_XL_OIS_6667Hz_HP: 10455 val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP; 10456 break; 10457 default: 10458 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF; 10459 break; 10460 } 10461 switch ( ctrl1_ois.fs_g_ois ) { 10462 case LSM6DSO_GY_OIS_250dps: 10463 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps; 10464 break; 10465 case LSM6DSO_GY_OIS_500dps: 10466 val->ois.gy.fs = LSM6DSO_GY_OIS_500dps; 10467 break; 10468 case LSM6DSO_GY_OIS_1000dps: 10469 val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps; 10470 break; 10471 case LSM6DSO_GY_OIS_2000dps: 10472 val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps; 10473 break; 10474 default: 10475 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps; 10476 break; 10477 } 10478 switch ( ctrl1_ois.ois_en_spi2 ) { 10479 case LSM6DSO_GY_OIS_OFF: 10480 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF; 10481 break; 10482 case LSM6DSO_GY_OIS_6667Hz_HP: 10483 val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP; 10484 break; 10485 default: 10486 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF; 10487 break; 10488 } 10489 val->ois.ctrl_md = LSM6DSO_OIS_MIXED; 10490 break; 10491 default: 10492 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs; 10493 ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr; 10494 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr; 10495 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs; 10496 val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX; 10497 break; 10498 } 10499 10500 return ret; 10501 } 10502 10503 /** 10504 * @brief Read data in engineering unit.[get] 10505 * 10506 * @param ctx communication interface handler.(ptr) 10507 * @param md the sensor conversion parameters.(ptr) 10508 * 10509 */ 10510 int32_t lsm6dso_data_get(lsm6dso_ctx_t *ctx, lsm6dso_ctx_t *aux_ctx, 10511 lsm6dso_md_t *md, lsm6dso_data_t *data) 10512 { 10513 uint8_t buff[14]; 10514 int32_t ret; 10515 uint8_t i; 10516 uint8_t j; 10517 10518 ret = 0; 10519 10520 /* read data */ 10521 if( ctx != NULL ) { 10522 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 14); 10523 } 10524 j = 0; 10525 10526 /* temperature conversion */ 10527 data->ui.heat.raw = (int16_t)buff[j+1U]; 10528 data->ui.heat.raw = ( ((int16_t)data->ui.heat.raw * (int16_t)256) + (int16_t)buff[j] ); 10529 j+=2U; 10530 data->ui.heat.deg_c = lsm6dso_from_lsb_to_celsius((int16_t)data->ui.heat.raw); 10531 10532 /* angular rate conversion */ 10533 for (i = 0U; i < 3U; i++) { 10534 data->ui.gy.raw[i] = (int16_t)buff[j+1U]; 10535 data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j]; 10536 j+=2U; 10537 switch ( md->ui.gy.fs ) { 10538 case LSM6DSO_GY_UI_250dps: 10539 data->ui.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(data->ui.gy.raw[i]); 10540 break; 10541 case LSM6DSO_GY_UI_125dps: 10542 data->ui.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(data->ui.gy.raw[i]); 10543 break; 10544 case LSM6DSO_GY_UI_500dps: 10545 data->ui.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(data->ui.gy.raw[i]); 10546 break; 10547 case LSM6DSO_GY_UI_1000dps: 10548 data->ui.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(data->ui.gy.raw[i]); 10549 break; 10550 case LSM6DSO_GY_UI_2000dps: 10551 data->ui.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(data->ui.gy.raw[i]); 10552 break; 10553 default: 10554 data->ui.gy.mdps[i] = 0.0f; 10555 break; 10556 } 10557 } 10558 10559 /* acceleration conversion */ 10560 for (i = 0U; i < 3U; i++) { 10561 data->ui.xl.raw[i] = (int16_t)buff[j+1U]; 10562 data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j]; 10563 j+=2U; 10564 switch ( md->ui.xl.fs ) { 10565 case LSM6DSO_XL_UI_2g: 10566 data->ui.xl.mg[i] =lsm6dso_from_fs2_to_mg(data->ui.xl.raw[i]); 10567 break; 10568 case LSM6DSO_XL_UI_4g: 10569 data->ui.xl.mg[i] =lsm6dso_from_fs4_to_mg(data->ui.xl.raw[i]); 10570 break; 10571 case LSM6DSO_XL_UI_8g: 10572 data->ui.xl.mg[i] =lsm6dso_from_fs8_to_mg(data->ui.xl.raw[i]); 10573 break; 10574 case LSM6DSO_XL_UI_16g: 10575 data->ui.xl.mg[i] =lsm6dso_from_fs16_to_mg(data->ui.xl.raw[i]); 10576 break; 10577 default: 10578 data->ui.xl.mg[i] = 0.0f; 10579 break; 10580 } 10581 10582 } 10583 10584 /* read data from ois chain */ 10585 if (aux_ctx != NULL) { 10586 if (ret == 0) { 10587 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_OUTX_L_G, buff, 12); 10588 } 10589 } 10590 j = 0; 10591 10592 /* ois angular rate conversion */ 10593 for (i = 0U; i < 3U; i++) { 10594 data->ois.gy.raw[i] = (int16_t) buff[j+1U]; 10595 data->ois.gy.raw[i] = (data->ois.gy.raw[i] * 256) + (int16_t) buff[j]; 10596 j+=2U; 10597 switch ( md->ois.gy.fs ) { 10598 case LSM6DSO_GY_UI_250dps: 10599 data->ois.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(data->ois.gy.raw[i]); 10600 break; 10601 case LSM6DSO_GY_UI_125dps: 10602 data->ois.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(data->ois.gy.raw[i]); 10603 break; 10604 case LSM6DSO_GY_UI_500dps: 10605 data->ois.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(data->ois.gy.raw[i]); 10606 break; 10607 case LSM6DSO_GY_UI_1000dps: 10608 data->ois.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(data->ois.gy.raw[i]); 10609 break; 10610 case LSM6DSO_GY_UI_2000dps: 10611 data->ois.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(data->ois.gy.raw[i]); 10612 break; 10613 default: 10614 data->ois.gy.mdps[i] = 0.0f; 10615 break; 10616 } 10617 } 10618 10619 /* ois acceleration conversion */ 10620 for (i = 0U; i < 3U; i++) { 10621 data->ois.xl.raw[i] = (int16_t) buff[j+1U]; 10622 data->ois.xl.raw[i] = (data->ois.xl.raw[i] * 256) + (int16_t) buff[j]; 10623 j+=2U; 10624 switch ( md->ois.xl.fs ) { 10625 case LSM6DSO_XL_UI_2g: 10626 data->ois.xl.mg[i] =lsm6dso_from_fs2_to_mg(data->ois.xl.raw[i]); 10627 break; 10628 case LSM6DSO_XL_UI_4g: 10629 data->ois.xl.mg[i] =lsm6dso_from_fs4_to_mg(data->ois.xl.raw[i]); 10630 break; 10631 case LSM6DSO_XL_UI_8g: 10632 data->ois.xl.mg[i] =lsm6dso_from_fs8_to_mg(data->ois.xl.raw[i]); 10633 break; 10634 case LSM6DSO_XL_UI_16g: 10635 data->ois.xl.mg[i] =lsm6dso_from_fs16_to_mg(data->ois.xl.raw[i]); 10636 break; 10637 default: 10638 data->ois.xl.mg[i] = 0.0f; 10639 break; 10640 } 10641 } 10642 10643 return ret; 10644 } 10645 10646 /** 10647 * @brief Embedded functions.[set] 10648 * 10649 * @param ctx read / write interface definitions 10650 * @param val change the values of registers 10651 * EMB_FUNC_EN_A e EMB_FUNC_EN_B. 10652 * 10653 */ 10654 int32_t lsm6dso_embedded_sens_set(lsm6dso_ctx_t *ctx, 10655 lsm6dso_emb_sens_t *val) 10656 { 10657 lsm6dso_emb_func_en_a_t emb_func_en_a; 10658 lsm6dso_emb_func_en_b_t emb_func_en_b; 10659 int32_t ret; 10660 10661 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 10662 if (ret == 0) { 10663 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, 10664 (uint8_t*)&emb_func_en_a, 1); 10665 } 10666 if (ret == 0) { 10667 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 10668 (uint8_t*)&emb_func_en_b, 1); 10669 10670 emb_func_en_b.fsm_en = val->fsm; 10671 emb_func_en_a.tilt_en = val->tilt; 10672 emb_func_en_a.pedo_en = val->step; 10673 emb_func_en_b.pedo_adv_en = val->step_adv; 10674 emb_func_en_a.sign_motion_en = val->sig_mot; 10675 emb_func_en_b.fifo_compr_en = val->fifo_compr; 10676 10677 } 10678 if (ret == 0) { 10679 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, 10680 (uint8_t*)&emb_func_en_a, 1); 10681 } 10682 if (ret == 0) { 10683 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 10684 (uint8_t*)&emb_func_en_b, 1); 10685 } 10686 if (ret == 0) { 10687 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 10688 } 10689 10690 return ret; 10691 } 10692 10693 /** 10694 * @brief Embedded functions.[get] 10695 * 10696 * @param ctx read / write interface definitions 10697 * @param val get the values of registers 10698 * EMB_FUNC_EN_A e EMB_FUNC_EN_B. 10699 * 10700 */ 10701 int32_t lsm6dso_embedded_sens_get(lsm6dso_ctx_t *ctx, 10702 lsm6dso_emb_sens_t *emb_sens) 10703 { 10704 lsm6dso_emb_func_en_a_t emb_func_en_a; 10705 lsm6dso_emb_func_en_b_t emb_func_en_b; 10706 int32_t ret; 10707 10708 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 10709 if (ret == 0) { 10710 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, 10711 (uint8_t*)&emb_func_en_a, 1); 10712 } 10713 if (ret == 0) { 10714 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 10715 (uint8_t*)&emb_func_en_b, 1); 10716 10717 emb_sens->fsm = emb_func_en_b.fsm_en; 10718 emb_sens->tilt = emb_func_en_a.tilt_en; 10719 emb_sens->step = emb_func_en_a.pedo_en; 10720 emb_sens->step_adv = emb_func_en_b.pedo_adv_en; 10721 emb_sens->sig_mot = emb_func_en_a.sign_motion_en; 10722 emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en; 10723 10724 } 10725 if (ret == 0) { 10726 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 10727 } 10728 10729 return ret; 10730 } 10731 10732 /** 10733 * @brief turn off all embedded functions.[get] 10734 * 10735 * @param ctx read / write interface definitions 10736 * @param val get the values of registers 10737 * EMB_FUNC_EN_A e EMB_FUNC_EN_B. 10738 * 10739 */ 10740 int32_t lsm6dso_embedded_sens_off(lsm6dso_ctx_t *ctx) 10741 { 10742 lsm6dso_emb_func_en_a_t emb_func_en_a; 10743 lsm6dso_emb_func_en_b_t emb_func_en_b; 10744 int32_t ret; 10745 10746 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK); 10747 if (ret == 0) { 10748 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, 10749 (uint8_t*)&emb_func_en_a, 1); 10750 } 10751 if (ret == 0) { 10752 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 10753 (uint8_t*)&emb_func_en_b, 1); 10754 10755 emb_func_en_b.fsm_en = PROPERTY_DISABLE; 10756 emb_func_en_a.tilt_en = PROPERTY_DISABLE; 10757 emb_func_en_a.pedo_en = PROPERTY_DISABLE; 10758 emb_func_en_b.pedo_adv_en = PROPERTY_DISABLE; 10759 emb_func_en_a.sign_motion_en = PROPERTY_DISABLE; 10760 emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE; 10761 10762 } 10763 if (ret == 0) { 10764 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, 10765 (uint8_t*)&emb_func_en_a, 1); 10766 } 10767 if (ret == 0) { 10768 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, 10769 (uint8_t*)&emb_func_en_b, 1); 10770 } 10771 if (ret == 0) { 10772 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK); 10773 } 10774 10775 return ret; 10776 } 10777 10778 /** 10779 * @} 10780 * 10781 */ 10782 10783 /** 10784 * @} 10785 * 10786 */ 10787 10788 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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