SDMP_IOT
/
AdiSense1000_SmartBabySeat
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Fork of
Babyseat_NewFirmware_copy_sean
by 
Ross O'Halloran
Revision 2:625a45555a85, committed 2017-08-25
- Comitter:
- kevin1990
- Date:
- Fri Aug 25 11:17:37 2017 +0000
- Parent:
- 1:50fa490ecd89
- Child:
- 3:3796776e2c27
- Commit message:
- Sensor Channel 0 Type K example
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/adi_sense_types.h Fri Aug 25 11:17:37 2017 +0000
@@ -0,0 +1,104 @@
+/*!
+ ******************************************************************************
+ * @file: adi_sense_types.h
+ * @brief: Type definitions for ADI Sense API.
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ - Modified versions of the software must be conspicuously marked as such.
+ - This software is licensed solely and exclusively for use with processors
+ manufactured by or for Analog Devices, Inc.
+ - This software may not be combined or merged with other code in any manner
+ that would cause the software to become subject to terms and conditions
+ which differ from those listed here.
+ - Neither the name of Analog Devices, Inc. nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+ - The use of this software may or may not infringe the patent rights of one
+ or more patent holders. This license does not release you from the
+ requirement that you obtain separate licenses from these patent holders
+ to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+#ifndef __ADI_SENSE_TYPES_H__
+#define __ADI_SENSE_TYPES_H__
+
+/******************************************************************************/
+/* Include Files */
+/******************************************************************************/
+
+/*!
+ *****************************************************************************
+ * \enum ADI_SENSE_RESULT
+ *
+ * ADI Sense API Error Codes. #ADI_SENSE_SUCCESS is always zero
+ * The return value of all ADI Sense APIs returning #ADI_SENSE_RESULT
+ * should always be tested at the application level for success or failure.
+ *
+ *****************************************************************************/
+typedef enum
+{
+ /*! Generic success. */
+ ADI_SENSE_SUCCESS,
+ /*! Generic Failure. */
+ ADI_SENSE_FAILURE,
+ /*! Operation incomplete, call again */
+ ADI_SENSE_INCOMPLETE,
+ /*! Device is already initialized. */
+ ADI_SENSE_IN_USE,
+ /*! Invalid device handle. */
+ ADI_SENSE_INVALID_HANDLE,
+ /*! Invalid device ID. */
+ ADI_SENSE_INVALID_DEVICE_NUM,
+ /*! Device is uninitialized. */
+ ADI_SENSE_ERR_NOT_INITIALIZED,
+ /*! NULL data pointer not allowed. */
+ ADI_SENSE_INVALID_POINTER,
+ /*! Parameter is out of range. */
+ ADI_SENSE_INVALID_PARAM,
+ /*! Unsupported mode of operation. */
+ ADI_SENSE_UNSUPPORTED_MODE,
+ /*! Invalid operation */
+ ADI_SENSE_INVALID_OPERATION,
+ /*! No data available, or buffer full */
+ ADI_SENSE_NO_DATA,
+ /*! No buffer space available */
+ ADI_SENSE_NO_SPACE,
+ /*! Square root of a negative number */
+ ADI_SENSE_NEGATIVE_SQRT,
+ /*! Division by 0 or 0.0 */
+ ADI_SENSE_DIVIDE_BY_ZERO,
+ /*! Invalid signature */
+ ADI_SENSE_INVALID_SIGNATURE,
+ /*! Wrong size */
+ ADI_SENSE_WRONG_SIZE,
+ /*! Sample Out of the dsp data limits */
+ ADI_SENSE_OUT_OF_RANGE,
+ /*! Unable to operate with not a number */
+ ADI_SENSE_NAN_FOUND,
+} ADI_SENSE_RESULT;
+
+#endif /* __ADI_SENSE_TYPES_H__ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/adisense1000.h Fri Aug 25 11:17:37 2017 +0000
@@ -0,0 +1,621 @@
+/*!
+ ******************************************************************************
+ * @file: adisense1000.h
+ * @brief:
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ - Modified versions of the software must be conspicuously marked as such.
+ - This software is licensed solely and exclusively for use with processors
+ manufactured by or for Analog Devices, Inc.
+ - This software may not be combined or merged with other code in any manner
+ that would cause the software to become subject to terms and conditions
+ which differ from those listed here.
+ - Neither the name of Analog Devices, Inc. nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+ - The use of this software may or may not infringe the patent rights of one
+ or more patent holders. This license does not release you from the
+ requirement that you obtain separate licenses from these patent holders
+ to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+#include "inc/registers/ADISENSE1000_REGISTERS_typedefs.h"
+#include "inc/registers/ADISENSE1000_REGISTERS.h"
+#include "inc/adi_sense_types.h"
+#include "inc/register_interface.h"
+
+
+#define READ_ONLY 1
+#define READ_WRITE 2
+#define WRITE_ONLY 3
+#define REGISTER_MAP_COUNT 218
+
+struct REGMAP_INFO
+{
+ uint16_t addr;
+ uint8_t size;
+ uint8_t rw;
+};
+
+const REGMAP_INFO regMap[REGISTER_MAP_COUNT] =
+{
+// address size r/w index id to array
+
+ {REG_SPI_INTERFACE_CONFIG_A, 1, READ_WRITE}, // SPI_INTERFACE_CONFIG_A
+ {REG_SPI_INTERFACE_CONFIG_B, 1, READ_WRITE}, // SPI_INTERFACE_CONFIG_B
+ {REG_SPI_DEVICE_CONFIG, 1, READ_WRITE}, // SPI_DEVICE_CONFIG
+ {REG_SPI_CHIP_TYPE, 1, READ_ONLY}, // SPI_CHIP_TYPE
+ {REG_SPI_PRODUCT_ID_L, 1, READ_ONLY}, // SPI_PRODUCT_ID_L
+ {REG_SPI_PRODUCT_ID_H, 1, READ_ONLY}, // SPI_PRODUCT_ID_H
+ {REG_SPI_CHIP_GRADE, 1, READ_ONLY}, // SPI_CHIP_GRADE
+ {REG_SPI_SCRATCH_PAD, 1, READ_WRITE}, // SPI_SCRATCH_PAD
+ {REG_SPI_SPI_REVISION, 1, READ_ONLY}, // SPI_SPI_REVISION
+ {REG_SPI_VENDOR_L, 1, READ_ONLY}, // SPI_VENDOR_L
+ {REG_SPI_VENDOR_H, 1, READ_ONLY}, // SPI_VENDOR_H
+ {REG_SPI_STREAM_MODE, 1, READ_WRITE}, // SPI_STREAM_MODE
+ {REG_SPI_INTERFACE_CONFIG_C, 1, READ_WRITE}, // SPI_INTERFACE_CONFIG_C
+ {REG_SPI_INTERFACE_STATUS_A, 1, READ_ONLY}, // SPI_INTERFACE_STATUS_A
+ {REG_CORE_COMMAND, 1, WRITE_ONLY}, // CORE_COMMAND
+ {REG_CORE_MODE, 1, READ_WRITE}, // CORE_MODE
+ {REG_CORE_POWER_CONFIG, 1, READ_WRITE}, // CORE_POWER_CONFIG
+ {REG_CORE_CYCLE_CONTROL, 2, READ_WRITE}, // CORE_CYCLE_CONTROL
+ {REG_CORE_FIFO_NUM_CYCLES, 1, READ_WRITE}, // CORE_FIFO_NUM_CYCLES
+ {REG_CORE_MULTI_CYCLE_RATE, 1, READ_WRITE}, // CORE_MULTI_CYCLE_RATE
+ {REG_CORE_STATUS, 1, READ_ONLY}, // CORE_STATUS
+ {REG_CORE_DIAGNOSTICS_STATUS, 2, READ_ONLY}, // CORE_DIAGNOSTICS_STATUS
+ {REG_CORE_CHANNEL_ALERT_STATUS, 2, READ_ONLY}, // CORE_CHANNEL_ALERT_STATUS
+ {REG_CORE_ALERT_DETAIL_CH0, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH0
+ {REG_CORE_ALERT_DETAIL_CH1, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH1
+ {REG_CORE_ALERT_DETAIL_CH2, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH2
+ {REG_CORE_ALERT_DETAIL_CH3, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH3
+ {REG_CORE_ALERT_DETAIL_CH4, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH4
+ {REG_CORE_ALERT_DETAIL_CH5, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH5
+ {REG_CORE_ALERT_DETAIL_CH6, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH6
+ {REG_CORE_ALERT_DETAIL_CH7, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH7
+ {REG_CORE_ALERT_DETAIL_CH8, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH8
+ {REG_CORE_ALERT_DETAIL_CH9, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH9
+ {REG_CORE_ALERT_DETAIL_CH10, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH10
+ {REG_CORE_ALERT_DETAIL_CH11, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH11
+ {REG_CORE_ALERT_DETAIL_CH12, 1, READ_ONLY}, // CORE_ALERT_DETAIL_CH12
+ {REG_CORE_EXTERNAL_REFERENCE1, 4, READ_WRITE}, // CORE_EXTERNAL_REFERENCE1
+ {REG_CORE_EXTERNAL_REFERENCE2, 4, READ_WRITE}, // CORE_EXTERNAL_REFERENCE2
+ {REG_CORE_DIAGNOSTICS_CONTROL, 1, READ_WRITE}, // CORE_DIAGNOSTICS_CONTROL
+ {REG_CORE_DIAGNOSTICS_EXTRA, 1, READ_WRITE}, // CORE_DIAGNOSTICS_EXTRA
+ {REG_CORE_DATA_FIFO, 8, READ_ONLY}, // CORE_DATA_FIFO
+ {REG_CORE_LUT_SELECT, 1, READ_WRITE}, // CORE_LUT_SELECT
+ {REG_CORE_LUT_OFFSET, 2, READ_WRITE}, // CORE_LUT_OFFSET
+ {REG_CORE_LUT_DATA, 1, READ_WRITE}, // CORE_LUT_DATA
+ {REG_CORE_CAL_SELECT, 1, READ_WRITE}, // CORE_CAL_SELECT
+ {REG_CORE_CAL_OFFSET, 2, READ_WRITE}, // CORE_CAL_OFFSET
+ {REG_CORE_CAL_DATA, 1, READ_WRITE}, // CORE_CAL_DATA
+ {REG_CORE_REVISION, 4, READ_ONLY}, // CORE_REVISION
+
+ {REG_CORE_CHANNEL_COUNT0, 1, READ_WRITE}, // CORE_CHANNEL_COUNT0
+ {REG_CORE_SENSOR_TYPE0, 2, READ_WRITE}, // CORE_SENSOR_TYPE0
+ {REG_CORE_SENSOR_DETAILS0, 4, READ_WRITE}, // CORE_SENSOR_DETAILS0
+ {REG_CORE_CHANNEL_EXCITATION0, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION0
+ {REG_CORE_DIGITAL_SENSOR_CODING0, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING0
+ {REG_CORE_FILTER_SELECT0, 3, READ_WRITE}, // CORE_FILTER_SELECT0
+ {REG_CORE_SETTLING_TIME0, 2, READ_WRITE}, // CORE_SETTLING_TIME0
+ {REG_CORE_HIGH_THRESHOLD_LIMIT0, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT0
+ {REG_CORE_LOW_THRESHOLD_LIMIT0, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT0
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS0, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS0
+ {REG_CORE_DIGITAL_SENSOR_COMMAND10, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND10
+ {REG_CORE_DIGITAL_SENSOR_COMMAND20, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND20
+ {REG_CORE_DIGITAL_SENSOR_COMMAND30, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND30
+ {REG_CORE_SENSOR_LUT_INDEX10, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX10
+ {REG_CORE_SENSOR_LUT_INDEX20, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX20
+
+ {REG_CORE_CHANNEL_COUNT1, 1, READ_WRITE}, // CORE_CHANNEL_COUNT1
+ {REG_CORE_SENSOR_TYPE1, 2, READ_WRITE}, // CORE_SENSOR_TYPE1
+ {REG_CORE_SENSOR_DETAILS1, 4, READ_WRITE}, // CORE_SENSOR_DETAILS1
+ {REG_CORE_CHANNEL_EXCITATION1, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION1
+ {REG_CORE_DIGITAL_SENSOR_CODING1, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING1
+ {REG_CORE_FILTER_SELECT1, 3, READ_WRITE}, // CORE_FILTER_SELECT1
+ {REG_CORE_SETTLING_TIME1, 2, READ_WRITE}, // CORE_SETTLING_TIME1
+ {REG_CORE_HIGH_THRESHOLD_LIMIT1, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT1
+ {REG_CORE_LOW_THRESHOLD_LIMIT1, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT1
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS1, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS1
+ {REG_CORE_DIGITAL_SENSOR_COMMAND11, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND11
+ {REG_CORE_DIGITAL_SENSOR_COMMAND21, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND21
+ {REG_CORE_DIGITAL_SENSOR_COMMAND31, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND31
+ {REG_CORE_SENSOR_LUT_INDEX11, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX11
+ {REG_CORE_SENSOR_LUT_INDEX21, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX21
+
+ {REG_CORE_CHANNEL_COUNT2, 1, READ_WRITE}, // CORE_CHANNEL_COUNT2
+ {REG_CORE_SENSOR_TYPE2, 2, READ_WRITE}, // CORE_SENSOR_TYPE2
+ {REG_CORE_SENSOR_DETAILS2, 4, READ_WRITE}, // CORE_SENSOR_DETAILS2
+ {REG_CORE_CHANNEL_EXCITATION2, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION2
+ {REG_CORE_DIGITAL_SENSOR_CODING2, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING2
+ {REG_CORE_FILTER_SELECT2, 3, READ_WRITE}, // CORE_FILTER_SELECT2
+ {REG_CORE_SETTLING_TIME2, 2, READ_WRITE}, // CORE_SETTLING_TIME2
+ {REG_CORE_HIGH_THRESHOLD_LIMIT2, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT2
+ {REG_CORE_LOW_THRESHOLD_LIMIT2, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT2
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS2, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS2
+ {REG_CORE_DIGITAL_SENSOR_COMMAND12, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND12
+ {REG_CORE_DIGITAL_SENSOR_COMMAND22, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND22
+ {REG_CORE_DIGITAL_SENSOR_COMMAND32, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND32
+ {REG_CORE_SENSOR_LUT_INDEX12, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX12
+ {REG_CORE_SENSOR_LUT_INDEX22, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX22
+
+ {REG_CORE_CHANNEL_COUNT3, 1, READ_WRITE}, // CORE_CHANNEL_COUNT3
+ {REG_CORE_SENSOR_TYPE3, 2, READ_WRITE}, // CORE_SENSOR_TYPE3
+ {REG_CORE_SENSOR_DETAILS3, 4, READ_WRITE}, // CORE_SENSOR_DETAILS3
+ {REG_CORE_CHANNEL_EXCITATION3, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION3
+ {REG_CORE_DIGITAL_SENSOR_CODING3, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING3
+ {REG_CORE_FILTER_SELECT3, 3, READ_WRITE}, // CORE_FILTER_SELECT3
+ {REG_CORE_SETTLING_TIME3, 2, READ_WRITE}, // CORE_SETTLING_TIME3
+ {REG_CORE_HIGH_THRESHOLD_LIMIT3, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT3
+ {REG_CORE_LOW_THRESHOLD_LIMIT3, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT3
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS3, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS3
+ {REG_CORE_DIGITAL_SENSOR_COMMAND13, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND13
+ {REG_CORE_DIGITAL_SENSOR_COMMAND23, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND23
+ {REG_CORE_DIGITAL_SENSOR_COMMAND33, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND33
+ {REG_CORE_SENSOR_LUT_INDEX13, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX13
+ {REG_CORE_SENSOR_LUT_INDEX23, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX23
+
+ {REG_CORE_CHANNEL_COUNT4, 1, READ_WRITE}, // CORE_CHANNEL_COUNT4
+ {REG_CORE_SENSOR_TYPE4, 2, READ_WRITE}, // CORE_SENSOR_TYPE4
+ {REG_CORE_SENSOR_DETAILS4, 4, READ_WRITE}, // CORE_SENSOR_DETAILS4
+ {REG_CORE_CHANNEL_EXCITATION4, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION4
+ {REG_CORE_DIGITAL_SENSOR_CODING4, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING4
+ {REG_CORE_FILTER_SELECT4, 3, READ_WRITE}, // CORE_FILTER_SELECT4
+ {REG_CORE_SETTLING_TIME4, 2, READ_WRITE}, // CORE_SETTLING_TIME4
+ {REG_CORE_HIGH_THRESHOLD_LIMIT4, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT4
+ {REG_CORE_LOW_THRESHOLD_LIMIT4, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT4
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS4, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS4
+ {REG_CORE_DIGITAL_SENSOR_COMMAND14, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND14
+ {REG_CORE_DIGITAL_SENSOR_COMMAND24, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND24
+ {REG_CORE_DIGITAL_SENSOR_COMMAND34, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND34
+ {REG_CORE_SENSOR_LUT_INDEX14, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX14
+ {REG_CORE_SENSOR_LUT_INDEX24, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX24
+
+ {REG_CORE_CHANNEL_COUNT5, 1, READ_WRITE}, // CORE_CHANNEL_COUNT5
+ {REG_CORE_SENSOR_TYPE5, 2, READ_WRITE}, // CORE_SENSOR_TYPE5
+ {REG_CORE_SENSOR_DETAILS5, 4, READ_WRITE}, // CORE_SENSOR_DETAILS5
+ {REG_CORE_CHANNEL_EXCITATION5, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION5
+ {REG_CORE_DIGITAL_SENSOR_CODING5, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING5
+ {REG_CORE_FILTER_SELECT5, 3, READ_WRITE}, // CORE_FILTER_SELECT5
+ {REG_CORE_SETTLING_TIME5, 2, READ_WRITE}, // CORE_SETTLING_TIME5
+ {REG_CORE_HIGH_THRESHOLD_LIMIT5, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT5
+ {REG_CORE_LOW_THRESHOLD_LIMIT5, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT5
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS5, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS5
+ {REG_CORE_DIGITAL_SENSOR_COMMAND15, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND15
+ {REG_CORE_DIGITAL_SENSOR_COMMAND25, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND25
+ {REG_CORE_DIGITAL_SENSOR_COMMAND35, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND35
+ {REG_CORE_SENSOR_LUT_INDEX15, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX15
+ {REG_CORE_SENSOR_LUT_INDEX25, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX25
+
+ {REG_CORE_CHANNEL_COUNT6, 1, READ_WRITE}, // CORE_CHANNEL_COUNT6
+ {REG_CORE_SENSOR_TYPE6, 2, READ_WRITE}, // CORE_SENSOR_TYPE6
+ {REG_CORE_SENSOR_DETAILS6, 4, READ_WRITE}, // CORE_SENSOR_DETAILS6
+ {REG_CORE_CHANNEL_EXCITATION6, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION6
+ {REG_CORE_DIGITAL_SENSOR_CODING6, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING6
+ {REG_CORE_FILTER_SELECT6, 3, READ_WRITE}, // CORE_FILTER_SELECT6
+ {REG_CORE_SETTLING_TIME6, 2, READ_WRITE}, // CORE_SETTLING_TIME6
+ {REG_CORE_HIGH_THRESHOLD_LIMIT6, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT6
+ {REG_CORE_LOW_THRESHOLD_LIMIT6, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT6
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS6, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS6
+ {REG_CORE_DIGITAL_SENSOR_COMMAND16, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND16
+ {REG_CORE_DIGITAL_SENSOR_COMMAND26, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND26
+ {REG_CORE_DIGITAL_SENSOR_COMMAND36, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND36
+ {REG_CORE_SENSOR_LUT_INDEX16, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX16
+ {REG_CORE_SENSOR_LUT_INDEX26, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX26
+
+ {REG_CORE_CHANNEL_COUNT7, 1, READ_WRITE}, // CORE_CHANNEL_COUNT7
+ {REG_CORE_SENSOR_TYPE7, 2, READ_WRITE}, // CORE_SENSOR_TYPE7
+ {REG_CORE_SENSOR_DETAILS7, 4, READ_WRITE}, // CORE_SENSOR_DETAILS7
+ {REG_CORE_CHANNEL_EXCITATION7, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION7
+ {REG_CORE_DIGITAL_SENSOR_CODING7, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING7
+ {REG_CORE_FILTER_SELECT7, 3, READ_WRITE}, // CORE_FILTER_SELECT7
+ {REG_CORE_SETTLING_TIME7, 2, READ_WRITE}, // CORE_SETTLING_TIME7
+ {REG_CORE_HIGH_THRESHOLD_LIMIT7, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT7
+ {REG_CORE_LOW_THRESHOLD_LIMIT7, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT7
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS7, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS7
+ {REG_CORE_DIGITAL_SENSOR_COMMAND17, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND17
+ {REG_CORE_DIGITAL_SENSOR_COMMAND27, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND27
+ {REG_CORE_DIGITAL_SENSOR_COMMAND37, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND37
+ {REG_CORE_SENSOR_LUT_INDEX17, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX17
+ {REG_CORE_SENSOR_LUT_INDEX27, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX27
+
+ {REG_CORE_CHANNEL_COUNT8, 1, READ_WRITE}, // CORE_CHANNEL_COUNT8
+ {REG_CORE_SENSOR_TYPE8, 2, READ_WRITE}, // CORE_SENSOR_TYPE8
+ {REG_CORE_SENSOR_DETAILS8, 4, READ_WRITE}, // CORE_SENSOR_DETAILS8
+ {REG_CORE_CHANNEL_EXCITATION8, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION8
+ {REG_CORE_DIGITAL_SENSOR_CODING8, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING8
+ {REG_CORE_FILTER_SELECT8, 3, READ_WRITE}, // CORE_FILTER_SELECT8
+ {REG_CORE_SETTLING_TIME8, 2, READ_WRITE}, // CORE_SETTLING_TIME8
+ {REG_CORE_HIGH_THRESHOLD_LIMIT8, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT8
+ {REG_CORE_LOW_THRESHOLD_LIMIT8, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT8
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS8, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS8
+ {REG_CORE_DIGITAL_SENSOR_COMMAND18, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND18
+ {REG_CORE_DIGITAL_SENSOR_COMMAND28, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND28
+ {REG_CORE_DIGITAL_SENSOR_COMMAND38, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND38
+ {REG_CORE_SENSOR_LUT_INDEX18, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX18
+ {REG_CORE_SENSOR_LUT_INDEX28, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX28
+
+ {REG_CORE_CHANNEL_COUNT9, 1, READ_WRITE}, // CORE_CHANNEL_COUNT9
+ {REG_CORE_SENSOR_TYPE9, 2, READ_WRITE}, // CORE_SENSOR_TYPE9
+ {REG_CORE_SENSOR_DETAILS9, 4, READ_WRITE}, // CORE_SENSOR_DETAILS9
+ {REG_CORE_CHANNEL_EXCITATION9, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION9
+ {REG_CORE_DIGITAL_SENSOR_CODING9, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING9
+ {REG_CORE_FILTER_SELECT9, 3, READ_WRITE}, // CORE_FILTER_SELECT9
+ {REG_CORE_SETTLING_TIME9, 2, READ_WRITE}, // CORE_SETTLING_TIME9
+ {REG_CORE_HIGH_THRESHOLD_LIMIT9, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT9
+ {REG_CORE_LOW_THRESHOLD_LIMIT9, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT9
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS9, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS9
+ {REG_CORE_DIGITAL_SENSOR_COMMAND19, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND19
+ {REG_CORE_DIGITAL_SENSOR_COMMAND29, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND29
+ {REG_CORE_DIGITAL_SENSOR_COMMAND39, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND39
+ {REG_CORE_SENSOR_LUT_INDEX19, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX19
+ {REG_CORE_SENSOR_LUT_INDEX29, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX29
+
+ {REG_CORE_CHANNEL_COUNT10, 1, READ_WRITE}, // CORE_CHANNEL_COUNT10
+ {REG_CORE_SENSOR_TYPE10, 2, READ_WRITE}, // CORE_SENSOR_TYPE10
+ {REG_CORE_SENSOR_DETAILS10, 4, READ_WRITE}, // CORE_SENSOR_DETAILS10
+ {REG_CORE_CHANNEL_EXCITATION10, 1, READ_WRITE}, // CORE_CHANNEL_EXCITATION10
+ {REG_CORE_DIGITAL_SENSOR_CODING10, 2, READ_WRITE}, // CORE_DIGITAL_SENSOR_CODING10
+ {REG_CORE_FILTER_SELECT10, 3, READ_WRITE}, // CORE_FILTER_SELECT10
+ {REG_CORE_SETTLING_TIME10, 2, READ_WRITE}, // CORE_SETTLING_TIME10
+ {REG_CORE_HIGH_THRESHOLD_LIMIT10, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT10
+ {REG_CORE_LOW_THRESHOLD_LIMIT10, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT10
+ {REG_CORE_DIGITAL_SENSOR_ADDRESS10, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_ADDRESS10
+ {REG_CORE_DIGITAL_SENSOR_COMMAND110, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND110
+ {REG_CORE_DIGITAL_SENSOR_COMMAND210, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND210
+ {REG_CORE_DIGITAL_SENSOR_COMMAND310, 1, READ_WRITE}, // CORE_DIGITAL_SENSOR_COMMAND310
+ {REG_CORE_SENSOR_LUT_INDEX110, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX110
+ {REG_CORE_SENSOR_LUT_INDEX210, 4, READ_WRITE}, // CORE_SENSOR_LUT_INDEX210
+
+ {REG_CORE_HIGH_THRESHOLD_LIMIT11, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT11
+ {REG_CORE_HIGH_THRESHOLD_LIMIT12, 4, READ_WRITE}, // CORE_HIGH_THRESHOLD_LIMIT12
+ {REG_CORE_LOW_THRESHOLD_LIMIT11, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT11
+ {REG_CORE_LOW_THRESHOLD_LIMIT12, 4, READ_WRITE}, // CORE_LOW_THRESHOLD_LIMIT12
+ {REG_TEST_TEST_REG_0, 1, READ_WRITE} // TEST_TEST_REG_0
+};
+
+enum ADISENSE1000_REGMAP_INDEX
+{
+ SPI_INTERFACE_CONFIG_A = 0x00,
+ SPI_INTERFACE_CONFIG_B,
+ SPI_DEVICE_CONFIG,
+ SPI_CHIP_TYPE,
+ SPI_PRODUCT_ID_L,
+ SPI_PRODUCT_ID_H,
+ SPI_CHIP_GRADE,
+ SPI_SCRATCH_PAD,
+ SPI_SPI_REVISION,
+ SPI_VENDOR_L,
+ SPI_VENDOR_H,
+ SPI_STREAM_MODE,
+ SPI_INTERFACE_CONFIG_C,
+ SPI_INTERFACE_STATUS_A,
+ CORE_COMMAND,
+ CORE_MODE,
+ CORE_POWER_CONFIG,
+ CORE_CYCLE_CONTROL,
+ CORE_FIFO_NUM_CYCLES,
+ CORE_MULTI_CYCLE_RATE,
+ CORE_STATUS,
+ CORE_DIAGNOSTICS_STATUS,
+ CORE_CHANNEL_ALERT_STATUS,
+ CORE_ALERT_DETAIL_CH0,
+ CORE_ALERT_DETAIL_CH1,
+ CORE_ALERT_DETAIL_CH2,
+ CORE_ALERT_DETAIL_CH3,
+ CORE_ALERT_DETAIL_CH4,
+ CORE_ALERT_DETAIL_CH5,
+ CORE_ALERT_DETAIL_CH6,
+ CORE_ALERT_DETAIL_CH7,
+ CORE_ALERT_DETAIL_CH8,
+ CORE_ALERT_DETAIL_CH9,
+ CORE_ALERT_DETAIL_CH10,
+ CORE_ALERT_DETAIL_CH11,
+ CORE_ALERT_DETAIL_CH12,
+ CORE_EXTERNAL_REFERENCE1,
+ CORE_EXTERNAL_REFERENCE2,
+ CORE_DIAGNOSTICS_CONTROL,
+ CORE_DIAGNOSTICS_EXTRA,
+ CORE_DATA_FIFO,
+ CORE_LUT_SELECT,
+ CORE_LUT_OFFSET,
+ CORE_LUT_DATA,
+ CORE_CAL_SELECT,
+ CORE_CAL_OFFSET,
+ CORE_CAL_DATA,
+ CORE_REVISION,
+ CORE_CHANNEL_COUNT0,
+ CORE_SENSOR_TYPE0,
+ CORE_SENSOR_DETAILS0,
+ CORE_CHANNEL_EXCITATION0,
+ CORE_DIGITAL_SENSOR_CODING0,
+ CORE_FILTER_SELECT0,
+ CORE_SETTLING_TIME0,
+ CORE_HIGH_THRESHOLD_LIMIT0,
+ CORE_LOW_THRESHOLD_LIMIT0,
+ CORE_DIGITAL_SENSOR_ADDRESS0,
+ CORE_DIGITAL_SENSOR_COMMAND10,
+ CORE_DIGITAL_SENSOR_COMMAND20,
+ CORE_DIGITAL_SENSOR_COMMAND30,
+ CORE_SENSOR_LUT_INDEX10,
+ CORE_SENSOR_LUT_INDEX20,
+ CORE_CHANNEL_COUNT1,
+ CORE_SENSOR_TYPE1,
+ CORE_SENSOR_DETAILS1,
+ CORE_CHANNEL_EXCITATION1,
+ CORE_DIGITAL_SENSOR_CODING1,
+ CORE_FILTER_SELECT1,
+ CORE_SETTLING_TIME1,
+ CORE_HIGH_THRESHOLD_LIMIT1,
+ CORE_LOW_THRESHOLD_LIMIT1,
+ CORE_DIGITAL_SENSOR_ADDRESS1,
+ CORE_DIGITAL_SENSOR_COMMAND11,
+ CORE_DIGITAL_SENSOR_COMMAND21,
+ CORE_DIGITAL_SENSOR_COMMAND31,
+ CORE_SENSOR_LUT_INDEX11,
+ CORE_SENSOR_LUT_INDEX21,
+ CORE_CHANNEL_COUNT2,
+ CORE_SENSOR_TYPE2,
+ CORE_SENSOR_DETAILS2,
+ CORE_CHANNEL_EXCITATION2,
+ CORE_DIGITAL_SENSOR_CODING2,
+ CORE_FILTER_SELECT2,
+ CORE_SETTLING_TIME2,
+ CORE_HIGH_THRESHOLD_LIMIT2,
+ CORE_LOW_THRESHOLD_LIMIT2,
+ CORE_DIGITAL_SENSOR_ADDRESS2,
+ CORE_DIGITAL_SENSOR_COMMAND12,
+ CORE_DIGITAL_SENSOR_COMMAND22,
+ CORE_DIGITAL_SENSOR_COMMAND32,
+ CORE_SENSOR_LUT_INDEX12,
+ CORE_SENSOR_LUT_INDEX22,
+ CORE_CHANNEL_COUNT3,
+ CORE_SENSOR_TYPE3,
+ CORE_SENSOR_DETAILS3,
+ CORE_CHANNEL_EXCITATION3,
+ CORE_DIGITAL_SENSOR_CODING3,
+ CORE_FILTER_SELECT3,
+ CORE_SETTLING_TIME3,
+ CORE_HIGH_THRESHOLD_LIMIT3,
+ CORE_LOW_THRESHOLD_LIMIT3,
+ CORE_DIGITAL_SENSOR_ADDRESS3,
+ CORE_DIGITAL_SENSOR_COMMAND13,
+ CORE_DIGITAL_SENSOR_COMMAND23,
+ CORE_DIGITAL_SENSOR_COMMAND33,
+ CORE_SENSOR_LUT_INDEX13,
+ CORE_SENSOR_LUT_INDEX23,
+ CORE_CHANNEL_COUNT4,
+ CORE_SENSOR_TYPE4,
+ CORE_SENSOR_DETAILS4,
+ CORE_CHANNEL_EXCITATION4,
+ CORE_DIGITAL_SENSOR_CODING4,
+ CORE_FILTER_SELECT4,
+ CORE_SETTLING_TIME4,
+ CORE_HIGH_THRESHOLD_LIMIT4,
+ CORE_LOW_THRESHOLD_LIMIT4,
+ CORE_DIGITAL_SENSOR_ADDRESS4,
+ CORE_DIGITAL_SENSOR_COMMAND14,
+ CORE_DIGITAL_SENSOR_COMMAND24,
+ CORE_DIGITAL_SENSOR_COMMAND34,
+ CORE_SENSOR_LUT_INDEX14,
+ CORE_SENSOR_LUT_INDEX24,
+ CORE_CHANNEL_COUNT5,
+ CORE_SENSOR_TYPE5,
+ CORE_SENSOR_DETAILS5,
+ CORE_CHANNEL_EXCITATION5,
+ CORE_DIGITAL_SENSOR_CODING5,
+ CORE_FILTER_SELECT5,
+ CORE_SETTLING_TIME5,
+ CORE_HIGH_THRESHOLD_LIMIT5,
+ CORE_LOW_THRESHOLD_LIMIT5,
+ CORE_DIGITAL_SENSOR_ADDRESS5,
+ CORE_DIGITAL_SENSOR_COMMAND15,
+ CORE_DIGITAL_SENSOR_COMMAND25,
+ CORE_DIGITAL_SENSOR_COMMAND35,
+ CORE_SENSOR_LUT_INDEX15,
+ CORE_SENSOR_LUT_INDEX25,
+ CORE_CHANNEL_COUNT6,
+ CORE_SENSOR_TYPE6,
+ CORE_SENSOR_DETAILS6,
+ CORE_CHANNEL_EXCITATION6,
+ CORE_DIGITAL_SENSOR_CODING6,
+ CORE_FILTER_SELECT6,
+ CORE_SETTLING_TIME6,
+ CORE_HIGH_THRESHOLD_LIMIT6,
+ CORE_LOW_THRESHOLD_LIMIT6,
+ CORE_DIGITAL_SENSOR_ADDRESS6,
+ CORE_DIGITAL_SENSOR_COMMAND16,
+ CORE_DIGITAL_SENSOR_COMMAND26,
+ CORE_DIGITAL_SENSOR_COMMAND36,
+ CORE_SENSOR_LUT_INDEX16,
+ CORE_SENSOR_LUT_INDEX26,
+ CORE_CHANNEL_COUNT7,
+ CORE_SENSOR_TYPE7,
+ CORE_SENSOR_DETAILS7,
+ CORE_CHANNEL_EXCITATION7,
+ CORE_DIGITAL_SENSOR_CODING7,
+ CORE_FILTER_SELECT7,
+ CORE_SETTLING_TIME7,
+ CORE_HIGH_THRESHOLD_LIMIT7,
+ CORE_LOW_THRESHOLD_LIMIT7,
+ CORE_DIGITAL_SENSOR_ADDRESS7,
+ CORE_DIGITAL_SENSOR_COMMAND17,
+ CORE_DIGITAL_SENSOR_COMMAND27,
+ CORE_DIGITAL_SENSOR_COMMAND37,
+ CORE_SENSOR_LUT_INDEX17,
+ CORE_SENSOR_LUT_INDEX27,
+ CORE_CHANNEL_COUNT8,
+ CORE_SENSOR_TYPE8,
+ CORE_SENSOR_DETAILS8,
+ CORE_CHANNEL_EXCITATION8,
+ CORE_DIGITAL_SENSOR_CODING8,
+ CORE_FILTER_SELECT8,
+ CORE_SETTLING_TIME8,
+ CORE_HIGH_THRESHOLD_LIMIT8,
+ CORE_LOW_THRESHOLD_LIMIT8,
+ CORE_DIGITAL_SENSOR_ADDRESS8,
+ CORE_DIGITAL_SENSOR_COMMAND18,
+ CORE_DIGITAL_SENSOR_COMMAND28,
+ CORE_DIGITAL_SENSOR_COMMAND38,
+ CORE_SENSOR_LUT_INDEX18,
+ CORE_SENSOR_LUT_INDEX28,
+ CORE_CHANNEL_COUNT9,
+ CORE_SENSOR_TYPE9,
+ CORE_SENSOR_DETAILS9,
+ CORE_CHANNEL_EXCITATION9,
+ CORE_DIGITAL_SENSOR_CODING9,
+ CORE_FILTER_SELECT9,
+ CORE_SETTLING_TIME9,
+ CORE_HIGH_THRESHOLD_LIMIT9,
+ CORE_LOW_THRESHOLD_LIMIT9,
+ CORE_DIGITAL_SENSOR_ADDRESS9,
+ CORE_DIGITAL_SENSOR_COMMAND19,
+ CORE_DIGITAL_SENSOR_COMMAND29,
+ CORE_DIGITAL_SENSOR_COMMAND39,
+ CORE_SENSOR_LUT_INDEX19,
+ CORE_SENSOR_LUT_INDEX29,
+ CORE_CHANNEL_COUNT10,
+ CORE_SENSOR_TYPE10,
+ CORE_SENSOR_DETAILS10,
+ CORE_CHANNEL_EXCITATION10,
+ CORE_DIGITAL_SENSOR_CODING10,
+ CORE_FILTER_SELECT10,
+ CORE_SETTLING_TIME10,
+ CORE_HIGH_THRESHOLD_LIMIT10,
+ CORE_LOW_THRESHOLD_LIMIT10,
+ CORE_DIGITAL_SENSOR_ADDRESS10,
+ CORE_DIGITAL_SENSOR_COMMAND110,
+ CORE_DIGITAL_SENSOR_COMMAND210,
+ CORE_DIGITAL_SENSOR_COMMAND310,
+ CORE_SENSOR_LUT_INDEX110,
+ CORE_SENSOR_LUT_INDEX210,
+ CORE_HIGH_THRESHOLD_LIMIT11,
+ CORE_HIGH_THRESHOLD_LIMIT12,
+ CORE_LOW_THRESHOLD_LIMIT11,
+ CORE_LOW_THRESHOLD_LIMIT12,
+ TEST_TEST_REG_0
+};
+
+typedef enum {
+ ADI_SENSE_CJC0 = 0, /* Channel 0 */
+ ADI_SENSE_CJC1, /* Channel 1 */
+ ADI_SENSE_SENSOR_0, /* Channel 2 */
+ ADI_SENSE_SENSOR_1, /* Channel 3 */
+ ADI_SENSE_SENSOR_2, /* Channel 4 */
+ ADI_SENSE_SENSOR_3, /* Channel 5 */
+ ADI_SENSE_V_MEASURE, /* Channel 6 */
+ ADI_SENSE_I_MEASURE, /* Channel 7 */
+ ADI_SENSE_DIG_SENSOR_0, /* Channel 8 */
+ ADI_SENSE_DIG_SENSOR_1, /* Channel 9 */
+ ADI_SENSE_DIG_SENSOR_3, /* Channel 10 */
+ ADI_SENSE_NUM_CHANNELS,
+}ADI_Channel_ID_t;
+
+const uint16_t baseReg[ADI_SENSE_NUM_CHANNELS] =
+ {
+ CORE_CHANNEL_COUNT0, /* Channel 0 Base Register */
+ CORE_CHANNEL_COUNT1, /* Channel 1 Base Register */
+ CORE_CHANNEL_COUNT2, /* Channel 2 Base Register */
+ CORE_CHANNEL_COUNT3, /* Channel 3 Base Register */
+ CORE_CHANNEL_COUNT4, /* Channel 4 Base Register */
+ CORE_CHANNEL_COUNT5, /* Channel 5 Base Register */
+ CORE_CHANNEL_COUNT6, /* Channel 6 Base Register */
+ CORE_CHANNEL_COUNT7, /* Channel 7 Base Register */
+ CORE_CHANNEL_COUNT8, /* Channel 8 Base Register */
+ CORE_CHANNEL_COUNT9, /* Channel 9 Base Register */
+ CORE_CHANNEL_COUNT10, /* Channel 10 Base Register*/
+ };
+
+const uint8_t baseAlertReg[ADI_SENSE_NUM_CHANNELS] =
+ {
+ CORE_ALERT_DETAIL_CH0, /* Channel 0 Base Alert Register */
+ CORE_ALERT_DETAIL_CH1, /* Channel 1 Base Alert Register */
+ CORE_ALERT_DETAIL_CH2, /* Channel 2 Base Alert Register */
+ CORE_ALERT_DETAIL_CH3, /* Channel 3 Base Alert Register */
+ CORE_ALERT_DETAIL_CH4, /* Channel 4 Base Alert Register */
+ CORE_ALERT_DETAIL_CH5, /* Channel 5 Base Alert Register */
+ CORE_ALERT_DETAIL_CH6, /* Channel 6 Base Alert Register */
+ CORE_ALERT_DETAIL_CH7, /* Channel 7 Base Alert Register */
+ CORE_ALERT_DETAIL_CH8, /* Channel 8 Base Alert Register */
+ CORE_ALERT_DETAIL_CH9, /* Channel 9 Base Alert Register */
+ CORE_ALERT_DETAIL_CH10 /* Channel 10 Base Register*/ ,
+ };
+
+
+
+//typedef struct __attribute__((packed, aligned(4)))channel_registers {
+typedef struct channel_registers {
+ ADI_CORE_Channel_Count_t Count;
+ ADI_CORE_Sensor_Type_t Type;
+ ADI_CORE_Sensor_Details_t Details;
+ ADI_CORE_Channel_Excitation_t Excitation;
+ ADI_CORE_Digital_Sensor_Coding_t DigitalCoding;
+ ADI_CORE_Filter_Select_t FilterSelect;
+ ADI_CORE_Settling_Time_t SettlingTime;
+ ADI_CORE_High_Threshold_Limit_t HighThreshold;
+ ADI_CORE_Low_Threshold_Limit_t LowThreshold;
+ ADI_CORE_Digital_Sensor_Address_t DigitalAddress;
+ ADI_CORE_Digital_Sensor_Command1_t DigitalCommand1;
+ ADI_CORE_Digital_Sensor_Command2_t DigitalCommand2;
+ ADI_CORE_Digital_Sensor_Command3_t DigitalCommand3;
+ ADI_CORE_Sensor_LUT_Index1_t LUTIndex1;
+ ADI_CORE_Sensor_LUT_Index2_t LUTIndex2;
+}ADI_Channel_Config_t;
+
+
+typedef ADI_CORE_Alert_Detail_Ch_t ADI_Channel_Alert_t[ADI_SENSE_NUM_CHANNELS];
+
+
+
+
+
+ADI_SENSE_RESULT ADISense1000_Open(void);
+
+ADI_SENSE_RESULT ADISense1000_GetID(uint16_t *pProductID);
+
+ADI_SENSE_RESULT ADISense1000_ConfigureModule(void);
+
+ADI_SENSE_RESULT ADISense1000_GetStatus(ADI_CORE_Status_t *pStatus);
+
+ADI_SENSE_RESULT ADISense1000_GetChannelAlert(ADI_Channel_Alert_t pAlerts);
+
+ADI_SENSE_RESULT ADISense1000_ConfigureChannel(ADI_Channel_ID_t eChannel,
+ ADI_Channel_Config_t *pConfig);
+bool ADISense1000_SampleReady(void);
+
+ADI_SENSE_RESULT ADISense1000_StartMeasurement(
+ ADI_CORE_Command_Special_Command cmd);
+
+ADI_SENSE_RESULT ADISense1000_StopMeasurement(ADI_Channel_ID_t eChannel);
+
+ADI_SENSE_RESULT ADISense1000_GetData(uint32_t *pRaw, float *pSample,
+ uint8_t *pStatus);
+
+ADI_SENSE_RESULT ADISense1000_GetRegister(uint16_t reg, uint32_t *pRegValue);
+
+ADI_SENSE_RESULT ADISense1000_SetRegister(uint16_t reg, uint32_t regValue);
+
+
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/gpio_nucleo.h Fri Aug 25 11:17:37 2017 +0000 @@ -0,0 +1,63 @@ +/*! + ****************************************************************************** + * @file: gpio_nucleo.h + * @brief: ADISense1000 OS Dependant wrapper layer for gpio + *----------------------------------------------------------------------------- + * +Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __GPIO__NUCLEO_H__ +#define ___GPIO_NUCLEO_H__ + +/******************************************************************************/ +/* Include Files */ +/******************************************************************************/ +#include "inc/adi_sense_types.h" +#include "inc/interface.h" + +ADI_SENSE_RESULT ADISense1000_HostGpioOpen(gpioSettings *config); +ADI_SENSE_RESULT ADISense1000_HostGpioGet(gpioPins pinID, bool *bState); +ADI_SENSE_RESULT ADISense1000_HostGpioSet(gpioPins pinID, bool bState); +ADI_SENSE_RESULT ADISense1000_HostGpioIrqEnable(); +ADI_SENSE_RESULT ADISense1000_HostGpioIrqDisable(); +ADI_SENSE_RESULT ADISense1000_HostGpioClose(); + +#endif /* __GPIO__NUCLEO_H__ */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/interface.h Fri Aug 25 11:17:37 2017 +0000
@@ -0,0 +1,93 @@
+/*!
+ ******************************************************************************
+ * @file: interface.h
+ * @brief: Holds configuration for hardware interfaces
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ - Modified versions of the software must be conspicuously marked as such.
+ - This software is licensed solely and exclusively for use with processors
+ manufactured by or for Analog Devices, Inc.
+ - This software may not be combined or merged with other code in any manner
+ that would cause the software to become subject to terms and conditions
+ which differ from those listed here.
+ - Neither the name of Analog Devices, Inc. nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+ - The use of this software may or may not infringe the patent rights of one
+ or more patent holders. This license does not release you from the
+ requirement that you obtain separate licenses from these patent holders
+ to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __INTERFACE_H__
+#define __INTERFACE_H__
+
+#include <stdint.h>
+#include "mbed.h"
+
+#define OUTPUT 1
+#define INPUT 0
+#define HIGH 1
+#define LOW 0
+
+/** @addtogroup
+ * @{
+ */
+
+enum gpioPins
+{
+ HOST_RESET,
+ HOST_ERROR,
+ HOST_ALERT,
+ HOST_READY,
+ HOST_GPIO_COUNT
+};
+
+struct gpioSettings
+{
+ PinName nPin;
+ bool bOutput;
+ bool bInitHigh;
+};
+
+struct spiSettings
+{
+ uint8_t spiBus;
+ uint8_t spiChipSelect;
+};
+
+struct connInfo
+{
+ spiSettings spiConfig;
+ gpioSettings *configureGpio;
+};
+
+/**
+ * @}
+ */
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/register_interface.h Fri Aug 25 11:17:37 2017 +0000 @@ -0,0 +1,59 @@ +/*! + ****************************************************************************** + * @file: register_interface.h + * @brief: ADISense1000 interface to register map in adisense firmware + *----------------------------------------------------------------------------- + * +Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ +#ifndef __REGISTER_INTERFACE_H__ +#define __REGISTER_INTERFACE_H__ + +/******************************************************************************/ +/* Include Files */ +/******************************************************************************/ +#include <stdint.h> +#include "inc/adi_sense_types.h" + +ADI_SENSE_RESULT +ADISense1000_RegWrite(uint16_t addr, uint16_t size, uint8_t *data); +ADI_SENSE_RESULT +ADISense1000_RegRead(uint16_t addr, uint16_t size, uint8_t *data); +#endif /* __REGISTER_INTERFACE_H__ */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/registers/ADISENSE1000_REGISTERS.h Fri Aug 25 11:17:37 2017 +0000 @@ -0,0 +1,1203 @@ +/* ================================================================================ + + Created by : sherry + Created on : 2017 Jul 27, 19:13 IST + + Project : ADISENSE1000_REGISTERS + File : ADISENSE1000_REGISTERS.h + Description : Register Definitions + + !! ADI Confidential !! + INTERNAL USE ONLY + + Copyright (c) 2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + Auto generation script information: + Script: /usr/cadtools/bin/yoda.dir/generators/inc/genHeaders + Last modified: 26-MAY-2017 + + ================================================================================ */ + +#ifndef _DEF_ADISENSE1000_REGISTERS_H +#define _DEF_ADISENSE1000_REGISTERS_H + +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include <stdint.h> +#endif /* _LANGUAGE_C */ + +#ifndef __ADI_GENERATED_DEF_HEADERS__ +#define __ADI_GENERATED_DEF_HEADERS__ 1 +#endif + +#define __ADI_HAS_CORE__ 1 +#define __ADI_HAS_SPI__ 1 +#define __ADI_HAS_TEST__ 1 + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + SPI + ============================================================================================================================ */ +#define MOD_SPI_BASE 0x00000000 /* */ +#define MOD_SPI_MASK 0x00007FFF /* */ +#define REG_SPI_INTERFACE_CONFIG_A_RESET 0x00000010 /* Reset Value for Interface_Config_A */ +#define REG_SPI_INTERFACE_CONFIG_A 0x00000000 +#define REG_SPI_INTERFACE_CONFIG_B_RESET 0x00000000 /* Reset Value for Interface_Config_B */ +#define REG_SPI_INTERFACE_CONFIG_B 0x00000001 +#define REG_SPI_DEVICE_CONFIG_RESET 0x00000000 /* Reset Value for Device_Config */ +#define REG_SPI_DEVICE_CONFIG 0x00000002 +#define REG_SPI_CHIP_TYPE_RESET 0x00000007 /* Reset Value for Chip_Type */ +#define REG_SPI_CHIP_TYPE 0x00000003 +#define REG_SPI_PRODUCT_ID_L_RESET 0x00000020 /* Reset Value for Product_ID_L */ +#define REG_SPI_PRODUCT_ID_L 0x00000004 +#define REG_SPI_PRODUCT_ID_H_RESET 0x00000000 /* Reset Value for Product_ID_H */ +#define REG_SPI_PRODUCT_ID_H 0x00000005 +#define REG_SPI_CHIP_GRADE_RESET 0x00000000 /* Reset Value for Chip_Grade */ +#define REG_SPI_CHIP_GRADE 0x00000006 +#define REG_SPI_SCRATCH_PAD_RESET 0x00000000 /* Reset Value for Scratch_Pad */ +#define REG_SPI_SCRATCH_PAD 0x0000000A +#define REG_SPI_SPI_REVISION_RESET 0x00000082 /* Reset Value for SPI_Revision */ +#define REG_SPI_SPI_REVISION 0x0000000B +#define REG_SPI_VENDOR_L_RESET 0x00000056 /* Reset Value for Vendor_L */ +#define REG_SPI_VENDOR_L 0x0000000C +#define REG_SPI_VENDOR_H_RESET 0x00000004 /* Reset Value for Vendor_H */ +#define REG_SPI_VENDOR_H 0x0000000D +#define REG_SPI_STREAM_MODE_RESET 0x00000000 /* Reset Value for Stream_Mode */ +#define REG_SPI_STREAM_MODE 0x0000000E +#define REG_SPI_INTERFACE_CONFIG_C_RESET 0x00000023 /* Reset Value for Interface_Config_C */ +#define REG_SPI_INTERFACE_CONFIG_C 0x00000010 +#define REG_SPI_INTERFACE_STATUS_A_RESET 0x00000000 /* Reset Value for Interface_Status_A */ +#define REG_SPI_INTERFACE_STATUS_A 0x00000011 + +/* ============================================================================================================================ + SPI Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_INTERFACE_CONFIG_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_INTERFACE_CONFIG_A_SW_RESET 7 +#define BITP_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 5 +#define BITP_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 4 +#define BITP_SPI_INTERFACE_CONFIG_A_SW_RESETX 0 +#define BITM_SPI_INTERFACE_CONFIG_A_SW_RESET 0x00000080 +#define BITM_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 0x00000020 +#define BITM_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 0x00000010 +#define BITM_SPI_INTERFACE_CONFIG_A_SW_RESETX 0x00000001 +#define ENUM_SPI_INTERFACE_CONFIG_A_DESCEND 0x00000000 +#define ENUM_SPI_INTERFACE_CONFIG_A_ASCEND 0x00000020 + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_INTERFACE_CONFIG_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_INTERFACE_CONFIG_B_SINGLE_INST 7 +#define BITM_SPI_INTERFACE_CONFIG_B_SINGLE_INST 0x00000080 + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_DEVICE_CONFIG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_DEVICE_CONFIG_OPERATING_MODES 0 +#define BITM_SPI_DEVICE_CONFIG_OPERATING_MODES 0x00000003 +#define ENUM_SPI_DEVICE_CONFIG_NORMAL 0x00000000 +#define ENUM_SPI_DEVICE_CONFIG_SLEEP 0x00000003 + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CHIP_TYPE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CHIP_TYPE_CHIP_TYPE 0 +#define BITM_SPI_CHIP_TYPE_CHIP_TYPE 0x0000000F + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_PRODUCT_ID_L Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 4 +#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0 +#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 0x000000F0 +#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0x0000000F + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_PRODUCT_ID_H Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0 +#define BITM_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0x000000FF + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CHIP_GRADE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CHIP_GRADE_GRADE 4 +#define BITP_SPI_CHIP_GRADE_DEVICE_REVISION 0 +#define BITM_SPI_CHIP_GRADE_GRADE 0x000000F0 +#define BITM_SPI_CHIP_GRADE_DEVICE_REVISION 0x0000000F + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_SCRATCH_PAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_SCRATCH_PAD_SCRATCH_VALUE 0 +#define BITM_SPI_SCRATCH_PAD_SCRATCH_VALUE 0x000000FF + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_SPI_REVISION Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_SPI_REVISION_SPI_TYPE 6 +#define BITP_SPI_SPI_REVISION_VERSION 0 +#define BITM_SPI_SPI_REVISION_SPI_TYPE 0x000000C0 +#define BITM_SPI_SPI_REVISION_VERSION 0x0000003F +#define ENUM_SPI_SPI_REVISION_ADI_SPI 0x00000000 +#define ENUM_SPI_SPI_REVISION_LPT_SPI 0x00000080 +#define ENUM_SPI_SPI_REVISION_REV1_0 0x00000002 /* Version: Revision 1.0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_VENDOR_L Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_VENDOR_L_VID 0 +#define BITM_SPI_VENDOR_L_VID 0x000000FF + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_VENDOR_H Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_VENDOR_H_VID 0 +#define BITM_SPI_VENDOR_H_VID 0x000000FF + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_STREAM_MODE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_STREAM_MODE_LOOP_COUNT 0 +#define BITM_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_INTERFACE_CONFIG_C Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 6 +#define BITP_SPI_INTERFACE_CONFIG_C_STRICT_ENTITY_ACCESS 5 +#define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0 +#define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 0x000000C0 +#define BITM_SPI_INTERFACE_CONFIG_C_STRICT_ENTITY_ACCESS 0x00000020 +#define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0x00000003 +#define ENUM_SPI_INTERFACE_CONFIG_C_DISABLED 0x00000000 +#define ENUM_SPI_INTERFACE_CONFIG_C_ENABLED 0x00000040 + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_INTERFACE_STATUS_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 7 +#define BITP_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 4 +#define BITP_SPI_INTERFACE_STATUS_A_CRC_ERROR 3 +#define BITP_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 2 +#define BITP_SPI_INTERFACE_STATUS_A_PARTIAL_REG_WR_ERROR 1 +#define BITP_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0 +#define BITM_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 0x00000080 +#define BITM_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 0x00000010 +#define BITM_SPI_INTERFACE_STATUS_A_CRC_ERROR 0x00000008 +#define BITM_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 0x00000004 +#define BITM_SPI_INTERFACE_STATUS_A_PARTIAL_REG_WR_ERROR 0x00000002 +#define BITM_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0x00000001 + + +/* ============================================================================================================================ + ADISENSE1000 Core Registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + CORE + ============================================================================================================================ */ +#define MOD_CORE_BASE 0x00000010 /* ADISENSE1000 Core Registers */ +#define MOD_CORE_MASK 0x00007FFF /* ADISENSE1000 Core Registers */ +#define REG_CORE_COMMAND_RESET 0x00000000 /* Reset Value for Command */ +#define REG_CORE_COMMAND 0x00000014 /* CORE Special Command */ +#define REG_CORE_MODE_RESET 0x00000000 /* Reset Value for Mode */ +#define REG_CORE_MODE 0x00000018 /* CORE Operating Mode and DRDY Control */ +#define REG_CORE_POWER_CONFIG_RESET 0x00000000 /* Reset Value for Power_Config */ +#define REG_CORE_POWER_CONFIG 0x00000019 /* CORE General Configuration */ +#define REG_CORE_CYCLE_CONTROL_RESET 0x00000000 /* Reset Value for Cycle_Control */ +#define REG_CORE_CYCLE_CONTROL 0x0000001A /* CORE Measurement Cycle */ +#define REG_CORE_FIFO_NUM_CYCLES_RESET 0x00000001 /* Reset Value for Fifo_Num_Cycles */ +#define REG_CORE_FIFO_NUM_CYCLES 0x0000001C /* CORE Number of Measurement Cycles to Store in FIFO */ +#define REG_CORE_MULTI_CYCLE_RATE_RESET 0x00000000 /* Reset Value for Multi_Cycle_Rate */ +#define REG_CORE_MULTI_CYCLE_RATE 0x0000001D /* CORE Time Between Repeats of Multi-Cycle Conversions.... */ +#define REG_CORE_STATUS_RESET 0x00000000 /* Reset Value for Status */ +#define REG_CORE_STATUS 0x00000020 /* CORE General Status */ +#define REG_CORE_DIAGNOSTICS_STATUS_RESET 0x00000000 /* Reset Value for Diagnostics_Status */ +#define REG_CORE_DIAGNOSTICS_STATUS 0x00000024 /* CORE Diagnostics Status */ +#define REG_CORE_CHANNEL_ALERT_STATUS_RESET 0x00000000 /* Reset Value for Channel_Alert_Status */ +#define REG_CORE_CHANNEL_ALERT_STATUS 0x00000026 /* CORE Alert Status Summary */ +#define REG_CORE_ALERT_DETAIL_CHn_RESET 0x00000000 /* Reset Value for Alert_Detail_Ch[n] */ +#define REG_CORE_ALERT_DETAIL_CH0_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH0 */ +#define REG_CORE_ALERT_DETAIL_CH1_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH1 */ +#define REG_CORE_ALERT_DETAIL_CH2_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH2 */ +#define REG_CORE_ALERT_DETAIL_CH3_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH3 */ +#define REG_CORE_ALERT_DETAIL_CH4_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH4 */ +#define REG_CORE_ALERT_DETAIL_CH5_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH5 */ +#define REG_CORE_ALERT_DETAIL_CH6_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH6 */ +#define REG_CORE_ALERT_DETAIL_CH7_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH7 */ +#define REG_CORE_ALERT_DETAIL_CH8_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH8 */ +#define REG_CORE_ALERT_DETAIL_CH9_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH9 */ +#define REG_CORE_ALERT_DETAIL_CH10_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH10 */ +#define REG_CORE_ALERT_DETAIL_CH11_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH11 */ +#define REG_CORE_ALERT_DETAIL_CH12_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH12 */ +#define REG_CORE_ALERT_DETAIL_CH0 0x00000028 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH1 0x00000029 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH2 0x0000002A /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH3 0x0000002B /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH4 0x0000002C /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH5 0x0000002D /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH6 0x0000002E /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH7 0x0000002F /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH8 0x00000030 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH9 0x00000031 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH10 0x00000032 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH11 0x00000033 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH12 0x00000034 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CHn(i) (REG_CORE_ALERT_DETAIL_CH0 + ((i) * 1)) +#define REG_CORE_ALERT_DETAIL_CHn_COUNT 13 +#define REG_CORE_EXTERNAL_REFERENCE1_RESET 0x00000000 /* Reset Value for External_Reference1 */ +#define REG_CORE_EXTERNAL_REFERENCE1 0x00000040 /* CORE External Reference Information */ +#define REG_CORE_EXTERNAL_REFERENCE2_RESET 0x00000000 /* Reset Value for External_Reference2 */ +#define REG_CORE_EXTERNAL_REFERENCE2 0x00000044 /* CORE External Reference Information */ +#define REG_CORE_DIAGNOSTICS_CONTROL_RESET 0x00000000 /* Reset Value for Diagnostics_Control */ +#define REG_CORE_DIAGNOSTICS_CONTROL 0x00000048 /* CORE Diagnostic Control */ +#define REG_CORE_DIAGNOSTICS_EXTRA_RESET 0x00000000 /* Reset Value for Diagnostics_Extra */ +#define REG_CORE_DIAGNOSTICS_EXTRA 0x00000049 /* CORE Extra Diagnostics Control */ +#define REG_CORE_DATA_FIFO_RESET 0x00000000 /* Reset Value for Data_FIFO */ +#define REG_CORE_DATA_FIFO 0x00000050 /* CORE FIFO of Sensor Results */ +#define REG_CORE_LUT_SELECT_RESET 0x00000000 /* Reset Value for LUT_Select */ +#define REG_CORE_LUT_SELECT 0x00000060 /* CORE Pointer to Custom Lookup Table or Polynomial */ +#define REG_CORE_LUT_OFFSET_RESET 0x00000000 /* Reset Value for LUT_Offset */ +#define REG_CORE_LUT_OFFSET 0x00000062 /* CORE Offset into Selected LUT */ +#define REG_CORE_LUT_DATA_RESET 0x00000000 /* Reset Value for LUT_Data */ +#define REG_CORE_LUT_DATA 0x00000064 /* CORE Data to Read/Write from Addressed LUT Entry */ +#define REG_CORE_CAL_SELECT_RESET 0x00000000 /* Reset Value for CAL_Select */ +#define REG_CORE_CAL_SELECT 0x00000068 /* CORE Pointer to Calibration Values */ +#define REG_CORE_CAL_OFFSET_RESET 0x00000000 /* Reset Value for CAL_Offset */ +#define REG_CORE_CAL_OFFSET 0x0000006A /* CORE Offset into Selected Calibration Values */ +#define REG_CORE_CAL_DATA_RESET 0x00000000 /* Reset Value for CAL_Data */ +#define REG_CORE_CAL_DATA 0x0000006C /* CORE Data to Read/Write from Addressed Calibration Values */ +#define REG_CORE_REVISION_RESET 0x00000000 /* Reset Value for Revision */ +#define REG_CORE_REVISION 0x0000007C /* CORE Hardware, Firmware Revision */ +#define REG_CORE_CHANNEL_COUNTn_RESET 0x00000000 /* Reset Value for Channel_Count[n] */ +#define REG_CORE_CHANNEL_COUNT0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT0 */ +#define REG_CORE_CHANNEL_COUNT1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT1 */ +#define REG_CORE_CHANNEL_COUNT2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT2 */ +#define REG_CORE_CHANNEL_COUNT3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT3 */ +#define REG_CORE_CHANNEL_COUNT4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT4 */ +#define REG_CORE_CHANNEL_COUNT5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT5 */ +#define REG_CORE_CHANNEL_COUNT6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT6 */ +#define REG_CORE_CHANNEL_COUNT7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT7 */ +#define REG_CORE_CHANNEL_COUNT8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT8 */ +#define REG_CORE_CHANNEL_COUNT9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT9 */ +#define REG_CORE_CHANNEL_COUNT10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT10 */ +#define REG_CORE_CHANNEL_COUNT0 0x00000090 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT1 0x000000D0 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT2 0x00000110 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT3 0x00000150 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT4 0x00000190 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT5 0x000001D0 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT6 0x00000210 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT7 0x00000250 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT8 0x00000290 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT9 0x000002D0 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT10 0x00000310 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNTn(i) (REG_CORE_CHANNEL_COUNT0 + ((i) * 64)) +#define REG_CORE_CHANNEL_COUNTn_COUNT 11 +#define REG_CORE_SENSOR_TYPEn_RESET 0x00000000 /* Reset Value for Sensor_Type[n] */ +#define REG_CORE_SENSOR_TYPE0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE0 */ +#define REG_CORE_SENSOR_TYPE1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE1 */ +#define REG_CORE_SENSOR_TYPE2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE2 */ +#define REG_CORE_SENSOR_TYPE3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE3 */ +#define REG_CORE_SENSOR_TYPE4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE4 */ +#define REG_CORE_SENSOR_TYPE5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE5 */ +#define REG_CORE_SENSOR_TYPE6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE6 */ +#define REG_CORE_SENSOR_TYPE7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE7 */ +#define REG_CORE_SENSOR_TYPE8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE8 */ +#define REG_CORE_SENSOR_TYPE9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE9 */ +#define REG_CORE_SENSOR_TYPE10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE10 */ +#define REG_CORE_SENSOR_TYPE0 0x00000092 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE1 0x000000D2 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE2 0x00000112 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE3 0x00000152 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE4 0x00000192 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE5 0x000001D2 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE6 0x00000212 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE7 0x00000252 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE8 0x00000292 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE9 0x000002D2 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE10 0x00000312 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPEn(i) (REG_CORE_SENSOR_TYPE0 + ((i) * 64)) +#define REG_CORE_SENSOR_TYPEn_COUNT 11 +#define REG_CORE_SENSOR_DETAILSn_RESET 0x0000FF00 /* Reset Value for Sensor_Details[n] */ +#define REG_CORE_SENSOR_DETAILS0_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS0 */ +#define REG_CORE_SENSOR_DETAILS1_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS1 */ +#define REG_CORE_SENSOR_DETAILS2_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS2 */ +#define REG_CORE_SENSOR_DETAILS3_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS3 */ +#define REG_CORE_SENSOR_DETAILS4_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS4 */ +#define REG_CORE_SENSOR_DETAILS5_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS5 */ +#define REG_CORE_SENSOR_DETAILS6_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS6 */ +#define REG_CORE_SENSOR_DETAILS7_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS7 */ +#define REG_CORE_SENSOR_DETAILS8_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS8 */ +#define REG_CORE_SENSOR_DETAILS9_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS9 */ +#define REG_CORE_SENSOR_DETAILS10_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS10 */ +#define REG_CORE_SENSOR_DETAILS0 0x00000094 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS1 0x000000D4 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS2 0x00000114 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS3 0x00000154 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS4 0x00000194 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS5 0x000001D4 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS6 0x00000214 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS7 0x00000254 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS8 0x00000294 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS9 0x000002D4 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS10 0x00000314 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILSn(i) (REG_CORE_SENSOR_DETAILS0 + ((i) * 64)) +#define REG_CORE_SENSOR_DETAILSn_COUNT 11 +#define REG_CORE_CHANNEL_EXCITATIONn_RESET 0x00000000 /* Reset Value for Channel_Excitation[n] */ +#define REG_CORE_CHANNEL_EXCITATION0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION0 */ +#define REG_CORE_CHANNEL_EXCITATION1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION1 */ +#define REG_CORE_CHANNEL_EXCITATION2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION2 */ +#define REG_CORE_CHANNEL_EXCITATION3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION3 */ +#define REG_CORE_CHANNEL_EXCITATION4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION4 */ +#define REG_CORE_CHANNEL_EXCITATION5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION5 */ +#define REG_CORE_CHANNEL_EXCITATION6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION6 */ +#define REG_CORE_CHANNEL_EXCITATION7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION7 */ +#define REG_CORE_CHANNEL_EXCITATION8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION8 */ +#define REG_CORE_CHANNEL_EXCITATION9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION9 */ +#define REG_CORE_CHANNEL_EXCITATION10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION10 */ +#define REG_CORE_CHANNEL_EXCITATION0 0x00000098 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION1 0x000000D8 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION2 0x00000118 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION3 0x00000158 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION4 0x00000198 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION5 0x000001D8 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION6 0x00000218 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION7 0x00000258 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION8 0x00000298 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION9 0x000002D8 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION10 0x00000318 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATIONn(i) (REG_CORE_CHANNEL_EXCITATION0 + ((i) * 64)) +#define REG_CORE_CHANNEL_EXCITATIONn_COUNT 11 +#define REG_CORE_DIGITAL_SENSOR_CODINGn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Coding[n] */ +#define REG_CORE_DIGITAL_SENSOR_CODING0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING0 */ +#define REG_CORE_DIGITAL_SENSOR_CODING1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING1 */ +#define REG_CORE_DIGITAL_SENSOR_CODING2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING2 */ +#define REG_CORE_DIGITAL_SENSOR_CODING3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING3 */ +#define REG_CORE_DIGITAL_SENSOR_CODING4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING4 */ +#define REG_CORE_DIGITAL_SENSOR_CODING5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING5 */ +#define REG_CORE_DIGITAL_SENSOR_CODING6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING6 */ +#define REG_CORE_DIGITAL_SENSOR_CODING7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING7 */ +#define REG_CORE_DIGITAL_SENSOR_CODING8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING8 */ +#define REG_CORE_DIGITAL_SENSOR_CODING9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING9 */ +#define REG_CORE_DIGITAL_SENSOR_CODING10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING10 */ +#define REG_CORE_DIGITAL_SENSOR_CODING0 0x0000009A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING1 0x000000DA /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING2 0x0000011A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING3 0x0000015A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING4 0x0000019A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING5 0x000001DA /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING6 0x0000021A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING7 0x0000025A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING8 0x0000029A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING9 0x000002DA /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING10 0x0000031A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODINGn(i) (REG_CORE_DIGITAL_SENSOR_CODING0 + ((i) * 64)) +#define REG_CORE_DIGITAL_SENSOR_CODINGn_COUNT 11 +#define REG_CORE_FILTER_SELECTn_RESET 0x00000000 /* Reset Value for Filter_Select[n] */ +#define REG_CORE_FILTER_SELECT0_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT0 */ +#define REG_CORE_FILTER_SELECT1_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT1 */ +#define REG_CORE_FILTER_SELECT2_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT2 */ +#define REG_CORE_FILTER_SELECT3_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT3 */ +#define REG_CORE_FILTER_SELECT4_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT4 */ +#define REG_CORE_FILTER_SELECT5_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT5 */ +#define REG_CORE_FILTER_SELECT6_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT6 */ +#define REG_CORE_FILTER_SELECT7_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT7 */ +#define REG_CORE_FILTER_SELECT8_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT8 */ +#define REG_CORE_FILTER_SELECT9_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT9 */ +#define REG_CORE_FILTER_SELECT10_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT10 */ +#define REG_CORE_FILTER_SELECT0 0x0000009C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT1 0x000000DC /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT2 0x0000011C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT3 0x0000015C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT4 0x0000019C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT5 0x000001DC /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT6 0x0000021C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT7 0x0000025C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT8 0x0000029C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT9 0x000002DC /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT10 0x0000031C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECTn(i) (REG_CORE_FILTER_SELECT0 + ((i) * 64)) +#define REG_CORE_FILTER_SELECTn_COUNT 11 +#define REG_CORE_SETTLING_TIMEn_RESET 0x00000000 /* Reset Value for Settling_Time[n] */ +#define REG_CORE_SETTLING_TIME0_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME0 */ +#define REG_CORE_SETTLING_TIME1_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME1 */ +#define REG_CORE_SETTLING_TIME2_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME2 */ +#define REG_CORE_SETTLING_TIME3_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME3 */ +#define REG_CORE_SETTLING_TIME4_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME4 */ +#define REG_CORE_SETTLING_TIME5_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME5 */ +#define REG_CORE_SETTLING_TIME6_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME6 */ +#define REG_CORE_SETTLING_TIME7_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME7 */ +#define REG_CORE_SETTLING_TIME8_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME8 */ +#define REG_CORE_SETTLING_TIME9_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME9 */ +#define REG_CORE_SETTLING_TIME10_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME10 */ +#define REG_CORE_SETTLING_TIME0 0x000000A0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME1 0x000000E0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME2 0x00000120 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME3 0x00000160 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME4 0x000001A0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME5 0x000001E0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME6 0x00000220 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME7 0x00000260 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME8 0x000002A0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME9 0x000002E0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME10 0x00000320 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIMEn(i) (REG_CORE_SETTLING_TIME0 + ((i) * 64)) +#define REG_CORE_SETTLING_TIMEn_COUNT 11 +#define REG_CORE_HIGH_THRESHOLD_LIMITn_RESET 0x00000000 /* Reset Value for High_Threshold_Limit[n] */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT0_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT0 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT1_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT1 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT2_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT2 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT3_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT3 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT4_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT4 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT5_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT5 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT6_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT6 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT7_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT7 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT8_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT8 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT9_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT9 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT10_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT10 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT11_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT11 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT12_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT12 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT0 0x000000A4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT1 0x000000E4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT2 0x00000124 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT3 0x00000164 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT4 0x000001A4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT5 0x000001E4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT6 0x00000224 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT7 0x00000264 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT8 0x000002A4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT9 0x000002E4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT10 0x00000324 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT11 0x00000364 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT12 0x000003A4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMITn(i) (REG_CORE_HIGH_THRESHOLD_LIMIT0 + ((i) * 64)) +#define REG_CORE_HIGH_THRESHOLD_LIMITn_COUNT 13 +#define REG_CORE_LOW_THRESHOLD_LIMITn_RESET 0x00000000 /* Reset Value for Low_Threshold_Limit[n] */ +#define REG_CORE_LOW_THRESHOLD_LIMIT0_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT0 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT1_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT1 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT2_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT2 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT3_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT3 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT4_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT4 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT5_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT5 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT6_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT6 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT7_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT7 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT8_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT8 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT9_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT9 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT10_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT10 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT11_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT11 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT12_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT12 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT0 0x000000A8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT1 0x000000E8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT2 0x00000128 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT3 0x00000168 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT4 0x000001A8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT5 0x000001E8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT6 0x00000228 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT7 0x00000268 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT8 0x000002A8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT9 0x000002E8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT10 0x00000328 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT11 0x00000368 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT12 0x000003A8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMITn(i) (REG_CORE_LOW_THRESHOLD_LIMIT0 + ((i) * 64)) +#define REG_CORE_LOW_THRESHOLD_LIMITn_COUNT 13 +#define REG_CORE_DIGITAL_SENSOR_ADDRESSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Address[n] */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS0 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS1 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS2 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS3 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS4 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS5 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS6 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS7 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS8 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS9 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS10 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS0 0x000000AC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS1 0x000000EC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS2 0x0000012C /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS3 0x0000016C /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS4 0x000001AC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS5 0x000001EC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS6 0x0000022C /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS7 0x0000026C /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS8 0x000002AC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS9 0x000002EC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS10 0x0000032C /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESSn(i) (REG_CORE_DIGITAL_SENSOR_ADDRESS0 + ((i) * 64)) +#define REG_CORE_DIGITAL_SENSOR_ADDRESSn_COUNT 11 +#define REG_CORE_DIGITAL_SENSOR_COMMAND1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command1[n] */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND10 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND11 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND12 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND13_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND13 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND14_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND14 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND15_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND15 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND16_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND16 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND17_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND17 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND18_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND18 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND19_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND19 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND110_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND110 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND10 0x000000AD /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND11 0x000000ED /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND12 0x0000012D /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND13 0x0000016D /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND14 0x000001AD /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND15 0x000001ED /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND16 0x0000022D /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND17 0x0000026D /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND18 0x000002AD /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND19 0x000002ED /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND110 0x0000032D /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND1n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND10 + ((i) * 64)) +#define REG_CORE_DIGITAL_SENSOR_COMMAND1n_COUNT 11 +#define REG_CORE_DIGITAL_SENSOR_COMMAND2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command2[n] */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND20_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND20 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND21_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND21 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND22_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND22 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND23_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND23 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND24_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND24 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND25_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND25 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND26_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND26 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND27_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND27 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND28_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND28 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND29_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND29 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND210_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND210 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND20 0x000000AE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND21 0x000000EE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND22 0x0000012E /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND23 0x0000016E /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND24 0x000001AE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND25 0x000001EE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND26 0x0000022E /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND27 0x0000026E /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND28 0x000002AE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND29 0x000002EE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND210 0x0000032E /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND2n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND20 + ((i) * 64)) +#define REG_CORE_DIGITAL_SENSOR_COMMAND2n_COUNT 11 +#define REG_CORE_DIGITAL_SENSOR_COMMAND3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command3[n] */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND30_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND30 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND31_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND31 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND32_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND32 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND33_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND33 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND34_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND34 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND35_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND35 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND36_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND36 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND37_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND37 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND38_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND38 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND39_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND39 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND310_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND310 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND30 0x000000AF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND31 0x000000EF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND32 0x0000012F /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND33 0x0000016F /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND34 0x000001AF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND35 0x000001EF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND36 0x0000022F /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND37 0x0000026F /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND38 0x000002AF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND39 0x000002EF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND310 0x0000032F /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND3n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND30 + ((i) * 64)) +#define REG_CORE_DIGITAL_SENSOR_COMMAND3n_COUNT 11 +#define REG_CORE_SENSOR_LUT_INDEX1n_RESET 0x00000000 /* Reset Value for Sensor_LUT_Index1[n] */ +#define REG_CORE_SENSOR_LUT_INDEX10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX10 */ +#define REG_CORE_SENSOR_LUT_INDEX11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX11 */ +#define REG_CORE_SENSOR_LUT_INDEX12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX12 */ +#define REG_CORE_SENSOR_LUT_INDEX13_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX13 */ +#define REG_CORE_SENSOR_LUT_INDEX14_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX14 */ +#define REG_CORE_SENSOR_LUT_INDEX15_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX15 */ +#define REG_CORE_SENSOR_LUT_INDEX16_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX16 */ +#define REG_CORE_SENSOR_LUT_INDEX17_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX17 */ +#define REG_CORE_SENSOR_LUT_INDEX18_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX18 */ +#define REG_CORE_SENSOR_LUT_INDEX19_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX19 */ +#define REG_CORE_SENSOR_LUT_INDEX110_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX110 */ +#define REG_CORE_SENSOR_LUT_INDEX10 0x000000B0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX11 0x000000F0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX12 0x00000130 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX13 0x00000170 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX14 0x000001B0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX15 0x000001F0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX16 0x00000230 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX17 0x00000270 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX18 0x000002B0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX19 0x000002F0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX110 0x00000330 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX1n(i) (REG_CORE_SENSOR_LUT_INDEX10 + ((i) * 64)) +#define REG_CORE_SENSOR_LUT_INDEX1n_COUNT 11 +#define REG_CORE_SENSOR_LUT_INDEX2n_RESET 0x00000000 /* Reset Value for Sensor_LUT_Index2[n] */ +#define REG_CORE_SENSOR_LUT_INDEX20_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX20 */ +#define REG_CORE_SENSOR_LUT_INDEX21_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX21 */ +#define REG_CORE_SENSOR_LUT_INDEX22_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX22 */ +#define REG_CORE_SENSOR_LUT_INDEX23_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX23 */ +#define REG_CORE_SENSOR_LUT_INDEX24_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX24 */ +#define REG_CORE_SENSOR_LUT_INDEX25_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX25 */ +#define REG_CORE_SENSOR_LUT_INDEX26_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX26 */ +#define REG_CORE_SENSOR_LUT_INDEX27_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX27 */ +#define REG_CORE_SENSOR_LUT_INDEX28_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX28 */ +#define REG_CORE_SENSOR_LUT_INDEX29_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX29 */ +#define REG_CORE_SENSOR_LUT_INDEX210_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX210 */ +#define REG_CORE_SENSOR_LUT_INDEX20 0x000000B4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX21 0x000000F4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX22 0x00000134 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX23 0x00000174 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX24 0x000001B4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX25 0x000001F4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX26 0x00000234 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX27 0x00000274 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX28 0x000002B4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX29 0x000002F4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX210 0x00000334 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX2n(i) (REG_CORE_SENSOR_LUT_INDEX20 + ((i) * 64)) +#define REG_CORE_SENSOR_LUT_INDEX2n_COUNT 11 + +/* ============================================================================================================================ + CORE Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_COMMAND Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_COMMAND_SPECIAL_COMMAND 0 /* Special Command */ +#define BITM_CORE_COMMAND_SPECIAL_COMMAND 0x000000FF /* Special Command */ +#define ENUM_CORE_COMMAND_NOP 0x00000000 /* Special_Command: No Command */ +#define ENUM_CORE_COMMAND_CONVERT 0x00000001 /* Special_Command: Start ADC Conversions */ +#define ENUM_CORE_COMMAND_CONVERT_WITH_RAW 0x00000002 /* Special_Command: Start Conversions with Added RAW ADC Data */ +#define ENUM_CORE_COMMAND_RUN_DIAGNOSTICS 0x00000003 /* Special_Command: Initiate a Diagnostics Cycle */ +#define ENUM_CORE_COMMAND_LOAD_DEFAULTS 0x00000004 /* Special_Command: Load Relevant Registers With Default Values Appropriate to Sensor */ +#define ENUM_CORE_COMMAND_LOAD_CONFIG 0x00000005 /* Special_Command: Load Registers with Configuration from FLASH */ +#define ENUM_CORE_COMMAND_SAVE_CONFIG 0x00000006 /* Special_Command: Store Current Register Configuration to FLASH */ +#define ENUM_CORE_COMMAND_LATCH_CONFIG 0x00000007 /* Special_Command: Freeze Current Register Configuration and Prepare for Conversion */ +#define ENUM_CORE_COMMAND_LOAD_LUT 0x00000008 /* Special_Command: Load LUT from FLASH */ +#define ENUM_CORE_COMMAND_SAVE_LUT2 0x00000009 /* Special_Command: Save LUT to FLASH */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_MODE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_MODE_STDBY_EN 5 /* Standby */ +#define BITP_CORE_MODE_DRDY_MODE 2 /* Indicates Behavior of DRDY with Respect to FIFO State */ +#define BITP_CORE_MODE_CONVERSION_MODE 0 /* Conversion Mode */ +#define BITM_CORE_MODE_STDBY_EN 0x00000020 /* Standby */ +#define BITM_CORE_MODE_DRDY_MODE 0x0000000C /* Indicates Behavior of DRDY with Respect to FIFO State */ +#define BITM_CORE_MODE_CONVERSION_MODE 0x00000003 /* Conversion Mode */ +#define ENUM_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data Ready Per Conversion */ +#define ENUM_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data Ready Per Cycle */ +#define ENUM_CORE_MODE_DRDY_PER_FIFO_FILL 0x00000008 /* Drdy_Mode: Data Ready Per FIFO Fill */ +#define ENUM_CORE_MODE_DRDY_MODE3 0x0000000C /* Drdy_Mode: Undefined */ +#define ENUM_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single Cycle */ +#define ENUM_CORE_MODE_MULTICYCLE 0x00000001 /* Conversion_Mode: Multi Cycle */ +#define ENUM_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous Conversion */ +#define ENUM_CORE_MODE_MODE3 0x00000003 /* Conversion_Mode: Undefined */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_POWER_CONFIG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_POWER_CONFIG_POWER_MODE_MCU 2 /* MCU Power Mode */ +#define BITP_CORE_POWER_CONFIG_POWER_MODE_ADC 0 /* ADC Power Mode */ +#define BITM_CORE_POWER_CONFIG_POWER_MODE_MCU 0x0000000C /* MCU Power Mode */ +#define BITM_CORE_POWER_CONFIG_POWER_MODE_ADC 0x00000003 /* ADC Power Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CYCLE_CONTROL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 14 /* Units for Cycle Time */ +#define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME 0 /* Duration of a Full Measurement Cycle */ +#define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 0x0000C000 /* Units for Cycle Time */ +#define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME 0x00000FFF /* Duration of a Full Measurement Cycle */ +#define ENUM_CORE_CYCLE_CONTROL_MICROSECONDS 0x00000000 /* Cycle_Time_Units: Micro-Seconds */ +#define ENUM_CORE_CYCLE_CONTROL_MILLISECONDS 0x00004000 /* Cycle_Time_Units: Milli-Seconds */ +#define ENUM_CORE_CYCLE_CONTROL_SECONDS 0x00008000 /* Cycle_Time_Units: Seconds */ +#define ENUM_CORE_CYCLE_CONTROL_UNDEFINED 0x0000C000 /* Cycle_Time_Units: Undefined */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_FIFO_NUM_CYCLES Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0 /* How Many Cycles to Fill FIFO */ +#define BITM_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0x000000FF /* How Many Cycles to Fill FIFO */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_MULTI_CYCLE_RATE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_MULTI_CYCLE_RATE_MULTI_CYCLE_RATE 0 /* CHANGE NAME. Defines Time Between Repetitions of FIFO Fill */ +#define BITM_CORE_MULTI_CYCLE_RATE_MULTI_CYCLE_RATE 0x000000FF /* CHANGE NAME. Defines Time Between Repetitions of FIFO Fill */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_STATUS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_STATUS_CMD_RUNNING 4 /* Indicates a Special Command is Active */ +#define BITP_CORE_STATUS_DRDY 3 /* Indicates a New Sensor (ADC?) Result is Available to Be Read */ +#define BITP_CORE_STATUS_ERROR 2 /* Indicates an Error */ +#define BITP_CORE_STATUS_ALERT 1 /* Indicates One or More Sensors are Outside Specified Limits */ +#define BITM_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates a Special Command is Active */ +#define BITM_CORE_STATUS_DRDY 0x00000008 /* Indicates a New Sensor (ADC?) Result is Available to Be Read */ +#define BITM_CORE_STATUS_ERROR 0x00000004 /* Indicates an Error */ +#define BITM_CORE_STATUS_ALERT 0x00000002 /* Indicates One or More Sensors are Outside Specified Limits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIAGNOSTICS_STATUS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIAGNOSTICS_STATUS_DIAGNOSTICS_STATUS 0 /* Diagnostics Status */ +#define BITM_CORE_DIAGNOSTICS_STATUS_DIAGNOSTICS_STATUS 0x0000FFFF /* Diagnostics Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CHANNEL_ALERT_STATUS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 12 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 11 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 10 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 9 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 8 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 7 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 6 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 5 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 4 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 3 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 2 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 1 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 0x00001000 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 0x00000800 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 0x00000400 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 0x00000200 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 0x00000100 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 0x00000080 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 0x00000040 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 0x00000020 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 0x00000010 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 0x00000008 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 0x00000004 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 0x00000002 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0x00000001 /* Indicates Channel is Outside Specified Limits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_ALERT_DETAIL_CH[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_ALERT_DETAIL_CH_REF_DETECT 6 /* Indicates Whether ADC Reference is Valid */ +#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 5 /* Indicates Sensor Input is Open Circuit */ +#define BITP_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 4 /* Indicates Sensor Result is Greater Than High Limit */ +#define BITP_CORE_ALERT_DETAIL_CH_LOW_LIMIT 3 /* Indicates Sensor Result is Less Than Low Limit */ +#define BITP_CORE_ALERT_DETAIL_CH_OVER_RANGE 2 /* Indicates Channel Over-Range */ +#define BITP_CORE_ALERT_DETAIL_CH_UNDER_RANGE 1 /* Indicates Channel Under-Range */ +#define BITP_CORE_ALERT_DETAIL_CH_TIME_OUT 0 /* Indicates Time-Out Error from Digital Sensor */ +#define BITM_CORE_ALERT_DETAIL_CH_REF_DETECT 0x00000040 /* Indicates Whether ADC Reference is Valid */ +#define BITM_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 0x00000020 /* Indicates Sensor Input is Open Circuit */ +#define BITM_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 0x00000010 /* Indicates Sensor Result is Greater Than High Limit */ +#define BITM_CORE_ALERT_DETAIL_CH_LOW_LIMIT 0x00000008 /* Indicates Sensor Result is Less Than Low Limit */ +#define BITM_CORE_ALERT_DETAIL_CH_OVER_RANGE 0x00000004 /* Indicates Channel Over-Range */ +#define BITM_CORE_ALERT_DETAIL_CH_UNDER_RANGE 0x00000002 /* Indicates Channel Under-Range */ +#define BITM_CORE_ALERT_DETAIL_CH_TIME_OUT 0x00000001 /* Indicates Time-Out Error from Digital Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_EXTERNAL_REFERENCE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0 /* Refin1 Value */ +#define BITM_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0xFFFFFFFF /* Refin1 Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_EXTERNAL_REFERENCE2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0 /* Refin2 Value */ +#define BITM_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0xFFFFFFFF /* Refin2 Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIAGNOSTICS_CONTROL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_OCD_FREQ 2 /* Diagnostics Open Circuit Detect Frequency */ +#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 1 /* Diagnostics Measure Enable */ +#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0 /* Diagnostics Global Enable */ +#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_OCD_FREQ 0x0000000C /* Diagnostics Open Circuit Detect Frequency */ +#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000002 /* Diagnostics Measure Enable */ +#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0x00000001 /* Diagnostics Global Enable */ +#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ0 0x00000000 +#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ1 0x00000004 +#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ2 0x00000008 +#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ3 0x0000000C + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIAGNOSTICS_EXTRA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIAGNOSTICS_EXTRA_DIAGNOSTICS_EXTRA 0 /* Additional Diagnostics Control */ +#define BITM_CORE_DIAGNOSTICS_EXTRA_DIAGNOSTICS_EXTRA 0x000000FF /* Additional Diagnostics Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DATA_FIFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DATA_FIFO_RAW_SAMPLE 40 /* ADC Result */ +#define BITP_CORE_DATA_FIFO_CH_VALID 39 /* Indicates Whether Valid Data Read from FIFO */ +#define BITP_CORE_DATA_FIFO_CH_RAW 38 /* Indicates If RAW Data is Valid */ +#define BITP_CORE_DATA_FIFO_CH_ALERT 37 /* Indicates Alert on Channel */ +#define BITP_CORE_DATA_FIFO_CH_ERROR 36 /* Indicates Error on Channel */ +#define BITP_CORE_DATA_FIFO_CHANNEL_ID 32 /* Indicates Which Channel This FIFO Data Corresponds to */ +#define BITP_CORE_DATA_FIFO_SENSOR_RESULT 0 /* Linearized and Compensated Sensor Result */ +#define BITM_CORE_DATA_FIFO_RAW_SAMPLE 0xFFFFFF0000000000 /* ADC Result */ +#define BITM_CORE_DATA_FIFO_CH_VALID 0x8000000000 /* Indicates Whether Valid Data Read from FIFO */ +#define BITM_CORE_DATA_FIFO_CH_RAW 0x4000000000 /* Indicates If RAW Data is Valid */ +#define BITM_CORE_DATA_FIFO_CH_ALERT 0x2000000000 /* Indicates Alert on Channel */ +#define BITM_CORE_DATA_FIFO_CH_ERROR 0x1000000000 /* Indicates Error on Channel */ +#define BITM_CORE_DATA_FIFO_CHANNEL_ID 0xF00000000 /* Indicates Which Channel This FIFO Data Corresponds to */ +#define BITM_CORE_DATA_FIFO_SENSOR_RESULT 0xFFFFFFFF /* Linearized and Compensated Sensor Result */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_LUT_SELECT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_LUT_SELECT_LUT_RW 7 /* Read or Write LUT Data */ +#define BITP_CORE_LUT_SELECT_LUT_TYPE 4 /* Indicates Whether Look-Up-Table or Polynomial Equation */ +#define BITP_CORE_LUT_SELECT_LUT_CHANNEL 0 /* Which Channel's LUT / Polynomial to Access */ +#define BITM_CORE_LUT_SELECT_LUT_RW 0x00000080 /* Read or Write LUT Data */ +#define BITM_CORE_LUT_SELECT_LUT_TYPE 0x00000070 /* Indicates Whether Look-Up-Table or Polynomial Equation */ +#define BITM_CORE_LUT_SELECT_LUT_CHANNEL 0x0000000F /* Which Channel's LUT / Polynomial to Access */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_LUT_OFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_LUT_OFFSET_LUT_OFFSET 0 /* Offset into Look-Up-Table */ +#define BITM_CORE_LUT_OFFSET_LUT_OFFSET 0x00003FFF /* Offset into Look-Up-Table */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_LUT_DATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_LUT_DATA_LUT_DATA 0 /* Data Byte to Write to / Read from Look-Up-Table */ +#define BITM_CORE_LUT_DATA_LUT_DATA 0x000000FF /* Data Byte to Write to / Read from Look-Up-Table */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CAL_SELECT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CAL_SELECT_CAL_RW 7 /* Read or Write Calibration Data */ +#define BITP_CORE_CAL_SELECT_CAL_TYPE 4 /* NOT REQUIRED?? */ +#define BITP_CORE_CAL_SELECT_CAL_CHANNEL 0 /* Which Channel's Calibration Data to Access */ +#define BITM_CORE_CAL_SELECT_CAL_RW 0x00000080 /* Read or Write Calibration Data */ +#define BITM_CORE_CAL_SELECT_CAL_TYPE 0x00000070 /* NOT REQUIRED?? */ +#define BITM_CORE_CAL_SELECT_CAL_CHANNEL 0x0000000F /* Which Channel's Calibration Data to Access */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CAL_OFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CAL_OFFSET_CAL_OFFSET 0 /* Offset into Calibration Data */ +#define BITM_CORE_CAL_OFFSET_CAL_OFFSET 0x00003FFF /* Offset into Calibration Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CAL_DATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CAL_DATA_CAL_DATA 0 /* Data to Write to / Read from Calibration Data */ +#define BITM_CORE_CAL_DATA_CAL_DATA 0x000000FF /* Data to Write to / Read from Calibration Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_REVISION Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_REVISION_COMMS_PROTOCOL 16 /* ID Info */ +#define BITP_CORE_REVISION_HARDWARE_REVISION 8 /* ID Info */ +#define BITP_CORE_REVISION_FIRMWARE_REVISION 0 /* ID Info */ +#define BITM_CORE_REVISION_COMMS_PROTOCOL 0x00FF0000 /* ID Info */ +#define BITM_CORE_REVISION_HARDWARE_REVISION 0x0000FF00 /* ID Info */ +#define BITM_CORE_REVISION_FIRMWARE_REVISION 0x000000FF /* ID Info */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CHANNEL_COUNT[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 7 /* Enable Channel in Measurement Cycle */ +#define BITP_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0 /* How Many Times Channel Should Appear in One Cycle */ +#define BITM_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 0x00000080 /* Enable Channel in Measurement Cycle */ +#define BITM_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0x0000007F /* How Many Times Channel Should Appear in One Cycle */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_SENSOR_TYPE[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_SENSOR_TYPE_SENSOR_CATEGORY 13 /* Indicates Category of Sensor */ +#define BITP_CORE_SENSOR_TYPE_SENSOR_LOAD_DEFAULTS 12 /* Indicates to Use Default Register Values */ +#define BITP_CORE_SENSOR_TYPE_SENSOR_TYPE 0 /* Sensor Type */ +#define BITM_CORE_SENSOR_TYPE_SENSOR_CATEGORY 0x0000E000 /* Indicates Category of Sensor */ +#define BITM_CORE_SENSOR_TYPE_SENSOR_LOAD_DEFAULTS 0x00001000 /* Indicates to Use Default Register Values */ +#define BITM_CORE_SENSOR_TYPE_SENSOR_TYPE 0x00000FFF /* Sensor Type */ +#define ENUM_CORE_SENSOR_TYPE_ANALOG 0x00000000 +#define ENUM_CORE_SENSOR_TYPE_I2C 0x00002000 +#define ENUM_CORE_SENSOR_TYPE_SPI 0x00004000 +#define ENUM_CORE_SENSOR_TYPE_TBD3 0x00006000 +#define ENUM_CORE_SENSOR_TYPE_TBD4 0x00008000 +#define ENUM_CORE_SENSOR_TYPE_TBD5 0x0000A000 +#define ENUM_CORE_SENSOR_TYPE_TBD6 0x0000C000 +#define ENUM_CORE_SENSOR_TYPE_TBD7 0x0000E000 +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T 0x00000000 /* Sensor_Type: Thermocouple T-Type Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_CUSTOM1 0x0000000E /* Sensor_Type: Thermocouple Custom Sensor1 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_CUSTOM2 0x0000000F /* Sensor_Type: Thermocouple Custom Sensor2 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100 0x00000010 /* Sensor_Type: RTD 2 Wire PT100 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000 0x00000011 /* Sensor_Type: RTD 2 Wire PT1000 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_CUSTOM1 0x0000001E /* Sensor_Type: RTD 2 Wire Custom Sensor1 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_CUSTOM2 0x0000001F /* Sensor_Type: RTD 2 Wire Custom Sensor2 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100 0x00000020 /* Sensor_Type: RTD 3 Wire PT100 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000 0x00000021 /* Sensor_Type: RTD 3 Wire PT1000 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_ONECONV 0x0000002C /* Sensor_Type: RTD 3 Wire PT100 No Chop Custom Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_ONECONV 0x0000002D /* Sensor_Type: RTD 3 Wire PT1000 No Chop Custom Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_CUSTOM1 0x0000002E /* Sensor_Type: RTD 3 Wire Custom Sensor1 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_CUSTOM2 0x0000002F /* Sensor_Type: RTD 3 Wire Custom Sensor2 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100 0x00000030 /* Sensor_Type: RTD 4 Wire PT100 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000 0x00000031 /* Sensor_Type: RTD 4 Wire PT1000 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_CUSTOM1 0x0000003E /* Sensor_Type: RTD 4 Wire Custom Sensor1 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_CUSTOM2 0x0000003F /* Sensor_Type: RTD 4 Wire Custom Sensor2 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K 0x00000040 /* Sensor_Type: Thermistor Type A 10kOhm Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K 0x00000041 /* Sensor_Type: Thermistor Type B 10kOhm Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_CUSTOM 0x0000004F /* Sensor_Type: Thermistor Custom Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W 0x00000050 /* Sensor_Type: Bridge 4 Wire Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_CUSTOM 0x0000005F /* Sensor_Type: Bridge 4 Wire Custom Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W 0x00000060 /* Sensor_Type: Bridge 6 Wire Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_CUSTOM 0x0000006F /* Sensor_Type: Bridge 6 Wire Custom Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE 0x00000070 /* Sensor_Type: Voltage Input */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_CURRENT 0x00000080 /* Sensor_Type: Current Input */ +#define ENUM_CORE_SENSOR_TYPE_CUSTOM 0x000000A0 /* Sensor_Type: Custom */ +#define ENUM_CORE_SENSOR_TYPE_I2C_PRESSURE1 0x00000800 /* Sensor_Type: I2C Pressure Sensor Type 1 */ +#define ENUM_CORE_SENSOR_TYPE_I2C_PRESSURE2 0x00000801 /* Sensor_Type: I2C Pressure Sensor Type 2 */ +#define ENUM_CORE_SENSOR_TYPE_SPI_PRESSURE1 0x00000C00 /* Sensor_Type: SPI Pressure Sensor Type 1 */ +#define ENUM_CORE_SENSOR_TYPE_SPI_PRESSURE2 0x00000C01 /* Sensor_Type: SPI Pressure Sensor Type 2 */ +#define ENUM_CORE_SENSOR_TYPE_SPI_ACCELEROMETER1 0x00000C02 /* Sensor_Type: SPI Accelerometer Sensor Type 1 3-Axis */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_SENSOR_DETAILS[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_SENSOR_DETAILS_AVERAGING 28 /* Number of ADC Results to Average */ +#define BITP_CORE_SENSOR_DETAILS_PGA_GAIN 24 /* PGA Gain */ +#define BITP_CORE_SENSOR_DETAILS_REFERENCE_SELECT 20 /* Reference Selection */ +#define BITP_CORE_SENSOR_DETAILS_VBIAS 19 /* Controls ADC Vbias Output */ +#define BITP_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 18 /* Enable or Disable ADC Reference Buffer */ +#define BITP_CORE_SENSOR_DETAILS_CJC_PUBLISH 17 /* Publish Compensation Data */ +#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_ONLY 16 /* Indicates to Use This Channel Only as Compensation */ +#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL3 12 /* Indicates Channel for Third Term of Compensation */ +#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL2 8 /* Indicates Channel for Second Term of Compensation */ +#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 4 /* Indicates Which Channel is Used to Compensate Sensor Result */ +#define BITP_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0 /* Units of Sensor Measurement */ +#define BITM_CORE_SENSOR_DETAILS_AVERAGING 0x70000000 /* Number of ADC Results to Average */ +#define BITM_CORE_SENSOR_DETAILS_PGA_GAIN 0x07000000 /* PGA Gain */ +#define BITM_CORE_SENSOR_DETAILS_REFERENCE_SELECT 0x00F00000 /* Reference Selection */ +#define BITM_CORE_SENSOR_DETAILS_VBIAS 0x00080000 /* Controls ADC Vbias Output */ +#define BITM_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 0x00040000 /* Enable or Disable ADC Reference Buffer */ +#define BITM_CORE_SENSOR_DETAILS_CJC_PUBLISH 0x00020000 /* Publish Compensation Data */ +#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_ONLY 0x00010000 /* Indicates to Use This Channel Only as Compensation */ +#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL3 0x0000F000 /* Indicates Channel for Third Term of Compensation */ +#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL2 0x00000F00 /* Indicates Channel for Second Term of Compensation */ +#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 0x000000F0 /* Indicates Which Channel is Used to Compensate Sensor Result */ +#define BITM_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0x0000000F /* Units of Sensor Measurement */ +#define ENUM_CORE_SENSOR_DETAILS_REF_DEFAULT 0x00000000 /* Reference_Select: Default Based on Sensor Type */ +#define ENUM_CORE_SENSOR_DETAILS_REF_INT 0x00100000 /* Reference_Select: Internal Reference */ +#define ENUM_CORE_SENSOR_DETAILS_REF_RINT1 0x00200000 /* Reference_Select: Internal Resistor1 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_RINT2 0x00300000 /* Reference_Select: Internal Resistor2 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_REXT1 0x00400000 /* Reference_Select: External Resistor on Refin1 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_REXT2 0x00500000 /* Reference_Select: External Resistor on Refin2 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_VEXT1 0x00600000 /* Reference_Select: External Voltage on Refin1 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_VEXT2 0x00700000 /* Reference_Select: External Voltage on Refin2 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_AVDD 0x00800000 /* Reference_Select: AVDD */ +#define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGC 0x00000000 /* Measurement_Units: Degrees C */ +#define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGF 0x00000001 /* Measurement_Units: Degrees F */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CHANNEL_EXCITATION[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CHANNEL_EXCITATION_IOUT_DONTCHOP_3WIRE 7 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */ +#define BITP_CORE_CHANNEL_EXCITATION_IOUT1_DISABLE 4 /* NOT NEEDED?? Disable Second Current Source */ +#define BITP_CORE_CHANNEL_EXCITATION_IOUT0_DISABLE 3 /* NOT NEEDED?? Disable First Current Source */ +#define BITP_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0 /* Current Source Value */ +#define BITM_CORE_CHANNEL_EXCITATION_IOUT_DONTCHOP_3WIRE 0x00000080 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */ +#define BITM_CORE_CHANNEL_EXCITATION_IOUT1_DISABLE 0x00000010 /* NOT NEEDED?? Disable Second Current Source */ +#define BITM_CORE_CHANNEL_EXCITATION_IOUT0_DISABLE 0x00000008 /* NOT NEEDED?? Disable First Current Source */ +#define BITM_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0x00000007 /* Current Source Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIGITAL_SENSOR_CODING[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_MSB_POSITION 8 /* Position of Data MSB in the Read Frame */ +#define BITP_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_NUMBITS 2 /* Number of Relevant Data Bits in Digital Sensor */ +#define BITP_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_CODING 0 /* I2C Address or Write Address Command for SPI Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_MSB_POSITION 0x00001F00 /* Position of Data MSB in the Read Frame */ +#define BITM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_NUMBITS 0x0000007C /* Number of Relevant Data Bits in Digital Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_CODING 0x00000003 /* I2C Address or Write Address Command for SPI Sensor */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_8_BITS 0x00000000 /* Digital_Sensor_Numbits: 8 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_10_BITS 0x00000004 /* Digital_Sensor_Numbits: 10 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_12_BITS 0x00000008 /* Digital_Sensor_Numbits: 12 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_14_BITS 0x0000000C /* Digital_Sensor_Numbits: 14 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_16_BITS 0x00000010 /* Digital_Sensor_Numbits: 16 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_18_BITS 0x00000014 /* Digital_Sensor_Numbits: 18 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_20_BITS 0x00000018 /* Digital_Sensor_Numbits: 20 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_22_BITS 0x0000001C /* Digital_Sensor_Numbits: 22 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_24_BITS 0x00000020 /* Digital_Sensor_Numbits: 24 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_CODING_UNIPOLAR 0x00000000 /* Digital_Sensor_Coding: Unipolar */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_CODING_TWOS_COMPL 0x00000001 /* Digital_Sensor_Coding: Twos Complement */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_CODING_OFFSET_BINARY 0x00000002 /* Digital_Sensor_Coding: Offset Binary */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_FILTER_SELECT[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_FILTER_SELECT_ADC_FIR_SEL 16 /* ADC Digital Filter FIR Type */ +#define BITP_CORE_FILTER_SELECT_ADC_FILTER_TYPE 11 /* ADC Digital Filter Type */ +#define BITP_CORE_FILTER_SELECT_ADC_FS 0 /* ADC Digital Filter Select */ +#define BITM_CORE_FILTER_SELECT_ADC_FIR_SEL 0x00070000 /* ADC Digital Filter FIR Type */ +#define BITM_CORE_FILTER_SELECT_ADC_FILTER_TYPE 0x00007800 /* ADC Digital Filter Type */ +#define BITM_CORE_FILTER_SELECT_ADC_FS 0x000007FF /* ADC Digital Filter Select */ +#define ENUM_CORE_FILTER_SELECT_SINC4 0x00000000 /* ADC_Filter_Type: Sinc4 Filter */ +#define ENUM_CORE_FILTER_SELECT_TBD1 0x00000800 /* ADC_Filter_Type: TBD1 */ +#define ENUM_CORE_FILTER_SELECT_TBD2 0x00001000 /* ADC_Filter_Type: TBD2 */ +#define ENUM_CORE_FILTER_SELECT_FIR 0x00001800 /* ADC_Filter_Type: FIR Filter */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_SETTLING_TIME[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Settling Time to Allow When Switching to Channel */ +#define BITM_CORE_SETTLING_TIME_SETTLING_TIME 0x0000FFFF /* Settling Time to Allow When Switching to Channel */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_HIGH_THRESHOLD_LIMIT[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0 /* Upper Limit for Sensor Alert Comparison */ +#define BITM_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0xFFFFFFFF /* Upper Limit for Sensor Alert Comparison */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_LOW_THRESHOLD_LIMIT[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0 /* Lower Limit for Sensor Alert Comparison */ +#define BITM_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0xFFFFFFFF /* Lower Limit for Sensor Alert Comparison */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIGITAL_SENSOR_ADDRESS[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0 /* I2C Address or Write Address Command for SPI Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0x000000FF /* I2C Address or Write Address Command for SPI Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIGITAL_SENSOR_COMMAND1[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0 /* Command to Send to Digital I2C/SPI Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0x000000FF /* Command to Send to Digital I2C/SPI Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIGITAL_SENSOR_COMMAND2[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0 /* Command to Send to Digital I2C/SPI Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0x000000FF /* Command to Send to Digital I2C/SPI Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIGITAL_SENSOR_COMMAND3[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0 /* Command to Send to Digital I2C/SPI Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0x000000FF /* Command to Send to Digital I2C/SPI Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_SENSOR_LUT_INDEX1[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX3 24 /* Pointer to LUT or Polynomial Correction for 4th Range */ +#define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX2 16 /* Pointer to LUT or Polynomial Correction for 3rd Range */ +#define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX1 8 /* Pointer to LUT or Polynomial Correction for 2nd Range */ +#define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX0 0 /* Pointer to LUT or Polynomial Correction for 1st Range */ +#define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX3 0x3F000000 /* Pointer to LUT or Polynomial Correction for 4th Range */ +#define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX2 0x003F0000 /* Pointer to LUT or Polynomial Correction for 3rd Range */ +#define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX1 0x00003F00 /* Pointer to LUT or Polynomial Correction for 2nd Range */ +#define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX0 0x0000003F /* Pointer to LUT or Polynomial Correction for 1st Range */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_SENSOR_LUT_INDEX2[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX7 24 /* Pointer to LUT or Polynomial Correction for 8th Range */ +#define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX6 16 /* Pointer to LUT or Polynomial Correction for 7th Range */ +#define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX5 8 /* Pointer to LUT or Polynomial Correction for 6th Range */ +#define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX4 0 /* Pointer to LUT or Polynomial Correction for 5th Range */ +#define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX7 0x3F000000 /* Pointer to LUT or Polynomial Correction for 8th Range */ +#define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX6 0x003F0000 /* Pointer to LUT or Polynomial Correction for 7th Range */ +#define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX5 0x00003F00 /* Pointer to LUT or Polynomial Correction for 6th Range */ +#define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX4 0x0000003F /* Pointer to LUT or Polynomial Correction for 5th Range */ + + +/* ============================================================================================================================ + Test Registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + TEST + ============================================================================================================================ */ +#define MOD_TEST_BASE 0x00000400 /* Test Registers */ +#define MOD_TEST_MASK 0x00007FFF /* Test Registers */ +#define REG_TEST_TEST_REG_0_RESET 0x00000000 /* Reset Value for test_reg_0 */ +#define REG_TEST_TEST_REG_0 0x00000400 /* TEST Test Register 0 */ + +/* ============================================================================================================================ + TEST Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + TEST_TEST_REG_0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TEST_TEST_REG_0_TESTBIT6 7 +#define BITP_TEST_TEST_REG_0_TESTBIT5 6 +#define BITP_TEST_TEST_REG_0_TESTBIT4 5 +#define BITP_TEST_TEST_REG_0_TESTBIT7 4 +#define BITP_TEST_TEST_REG_0_TESTBIT3 3 +#define BITP_TEST_TEST_REG_0_TESTBIT2 1 +#define BITP_TEST_TEST_REG_0_TESTBIT1 0 +#define BITM_TEST_TEST_REG_0_TESTBIT6 0x00000080 +#define BITM_TEST_TEST_REG_0_TESTBIT5 0x00000040 +#define BITM_TEST_TEST_REG_0_TESTBIT4 0x00000020 +#define BITM_TEST_TEST_REG_0_TESTBIT7 0x00000010 +#define BITM_TEST_TEST_REG_0_TESTBIT3 0x00000008 +#define BITM_TEST_TEST_REG_0_TESTBIT2 0x00000006 +#define BITM_TEST_TEST_REG_0_TESTBIT1 0x00000001 + + +/* SPI Parameters */ + +/***** SPI */ +#define PARAM_SPI_SPI_STANDARD "LPT" /* A part must declare which SPI Standard it follows, either ADI or LPT */ +#define PARAM_SPI_CHIP_GRADE_VALUE 0 /* This is used to indicate speed grades/linearity. */ +#define PARAM_SPI_CHIP_REVISION_VALUE 0 /* This is used to indicate the silicon revision */ +#define PARAM_SPI_HAS_M_S_REGISTERS 0 /* If a design uses Master-Slave registers this must be set to true to enable relevant control bit fields */ +#define PARAM_SPI_M_S_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS the M-S Transfer bit field */ +#define PARAM_SPI_STREAM_MODE_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS of the stream mode transfer bit field */ +#define PARAM_SPI_MSB_AND_LSB_FIRST_SUPPORT 0 /* Determines if the parts supports MSB and LSB first options */ +#define PARAM_SPI_WIRE_MODE_SUPPORT "_4_WIRE" /* Configures which hardware SPI modes are supported */ +#define PARAM_SPI_WIRE_MODE_DEFAULT "_4_WIRE" /* Sets the default hardware SPI mode */ +#define PARAM_SPI_MULTI_IO_CHANNELS 1 /* Defines the number of SDIO pins supported by the SPI in Multi-IO Mode. Should be 1,2,4, or 8. */ +#define PARAM_SPI_LPT_STANDARD_VERSION "REV1_0" /* This is a string from the LPT_STANDARD_VERSION_OPTIONS array for the active LPT SPI Standard version */ +#define PARAM_SPI_HAS_CSB_PIN 1 /* Does the part have a csb pin? */ +#define PARAM_SPI_BUS_MODE_SUPPORT 1 /* When set to true, Bus mode is supported. */ +#define PARAM_SPI_ISOLATED_3_WIRE_SUPPORT 0 /* Does the part support the 3-wire isolate mode of operation */ +#define PARAM_SPI_DAISY_CHAIN_MODE_SUPPORT 0 /* When set to true, Daisy chain mode is supported. */ +#define PARAM_SPI_CHECK_GTE_1_MODE_SUPPORTED 1 /* This is used to check that at least mode is enabled */ +#define PARAM_SPI_INTERFACE_MODE_SWITCH "None" /* Valid options are 'None', 'HW' or 'SW' */ +#define PARAM_SPI_CRC_SUPPORT "CRC_CONFIGURABLE" /* Set to true to enable bit fields related to CRC. */ +#define PARAM_SPI_CRC_SUPPORT_ENABLED 0 /* Verilog output parameter for 'define */ +#define PARAM_SPI_CRC_SUPPORT_ENABLE 1 /* Configures if CRC features are enabled in the module */ +#define PARAM_SPI_LPT_STANDARD_VERSION_VALUE 2 /* Index value of the active LPT SPI Standard version */ +#define PARAM_SPI_ADDRESS_MODE_SUPPORT "_15_BIT" /* Configures which addressing modes are supported */ +#define PARAM_SPI_ADDRESS_MODE_DEFAULT "_15_BIT" /* Sets the default addressing mode */ +#define PARAM_SPI_ADDRESS_BUS_WIDTH 15 /* Verilog output parameter for 'define */ +#define PARAM_SPI_SLOW_IFACE_CTRL_SUPPORT 0 /* Does the part support the Slow Interface Control feature */ +#define PARAM_SPI_SOFT_RESET_0_BF_EXISTS 0 /* Used to control if the SOFT_RESET_0 bit field exists */ +#define PARAM_SPI_SOFT_RESET_1_BF_EXISTS 0 /* Used to control if the SOFT_RESET_1 bit field exists */ +#define PARAM_SPI_SEND_STATUS_SUPPORT "NO_SEND_STATUS" /* Determines if and how the part supports the SEND_STATUS feature */ +#define PARAM_SPI_SEND_STATUS_SUPPORT_ENABLE 0 /* This is used to enable various send status features */ +#define PARAM_SPI_SPI_STANDARD_VERSION_VALUE 2 /* Value for SPI Standard VERSION bit field */ +#define PARAM_SPI_ENTITY_ACCESS_SUPPORT "ENTITY_ACCESS_ALWAYS" /* Configures which entity access mode(s) are supported */ +#define PARAM_SPI_ENTITY_ACCESS_SUPPORT_ENABLE 1 /* This is used to enable/disable Strict Entity Access features */ +#define PARAM_SPI_ENTITY_ACCESS_DEFAULT 1 /* Sets the default entity access mode */ +#define PARAM_SPI_CHIP_INDEX_EXISTS 0 /* Used to control if the CHIP_INDEX register and related bit field exists */ +#define PARAM_SPI_OFFSET_DEV_INDEX_EXISTS 0 /* Used to control if the OFFSET_DEV_INDEX bit field and registers exists */ +#define PARAM_SPI_DEV_INDEX_EXISTS 0 /* Used to control if the DEV_INDEX bit field and register exists */ +#define PARAM_SPI_STATUS_BIT_0_EXISTS 0 /* Sets EXIST for Status Bit 0 */ +#define PARAM_SPI_STATUS_BIT_1_EXISTS 0 /* Sets EXIST for Status Bit 1 */ +#define PARAM_SPI_STATUS_BIT_2_EXISTS 0 /* Sets EXIST for Status Bit 2 */ +#define PARAM_SPI_STATUS_BIT_3_EXISTS 0 /* Sets EXIST for Status Bit 3 */ +#define PARAM_SPI_STATUS_BIT_0_SWNAME "Status_Bit_0" /* Software Name for Status Bit 0 */ +#define PARAM_SPI_STATUS_BIT_1_SWNAME "Status_Bit_1" /* Software Name for Status Bit 1 */ +#define PARAM_SPI_STATUS_BIT_2_SWNAME "Status_Bit_2" /* Software Name for Status Bit 2 */ +#define PARAM_SPI_STATUS_BIT_3_SWNAME "Status_Bit_3" /* Software Name for Status Bit 3 */ +#define PARAM_SPI_CHIP_TYPE "P_ADC" /* This is a string that corresponds to one of the values in the CHIP_TYPE_OPTIONS array and corresponds to the type of chip being developed */ +#define PARAM_SPI_CHIP_TYPE_VALUE 7 /* Integer value corresponding to selected CHIP_TYPE, and is used as bit field enum value */ +#define PARAM_SPI_PRODUCT_ID_VALUE 32 /* This value is used to identify a specific generic. */ +#define PARAM_SPI_PRODUCT_ID_TRIM_BITS 4 /* This defines the number of PRODUCT_ID bits that can be fuse/trimmed. */ + +#endif /* end ifndef _DEF_ADISENSE1000_REGISTERS_H */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/registers/ADISENSE1000_REGISTERS_cdef.h Fri Aug 25 11:17:37 2017 +0000 @@ -0,0 +1,276 @@ +/* ================================================================================ + + Created by : sherry + Created on : 2017 Jul 27, 19:13 IST + + Project : ADISENSE1000_REGISTERS + File : ADISENSE1000_REGISTERS_cdef.h + Description : C MMR Pointer Definitions + + !! ADI Confidential !! + INTERNAL USE ONLY + + Copyright (c) 2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + Auto generation script information: + Script: /usr/cadtools/bin/yoda.dir/generators/inc/genHeaders + Last modified: 26-MAY-2017 + + ================================================================================ */ + +#ifndef _ADISENSE1000_REGISTERS_CDEF_H +#define _ADISENSE1000_REGISTERS_CDEF_H + +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include <stdint.h> +#endif /* _LANGUAGE_C */ + +/* pickup register bitfield and bit masks */ +#include "ADISENSE1000_REGISTERS.h" + + +#ifndef __IO +#define __I volatile /* read-only */ +#define __C +#define __RC const /* read-only memory ROM*/ +#define __O volatile /* write-only */ +#define __IO volatile /* read-write */ +#endif + +/* ================================================================================= + * (SPI) + * ================================================================================= */ +#define pREG_SPI_INTERFACE_CONFIG_A ((__IO uint8_t *) REG_SPI_INTERFACE_CONFIG_A) /* */ +#define pREG_SPI_INTERFACE_CONFIG_B ((__IO uint8_t *) REG_SPI_INTERFACE_CONFIG_B) /* */ +#define pREG_SPI_DEVICE_CONFIG ((__IO uint8_t *) REG_SPI_DEVICE_CONFIG) /* */ +#define pREG_SPI_CHIP_TYPE ((__I __C uint8_t *) REG_SPI_CHIP_TYPE) /* */ +#define pREG_SPI_PRODUCT_ID_L ((__I __C uint8_t *) REG_SPI_PRODUCT_ID_L) /* */ +#define pREG_SPI_PRODUCT_ID_H ((__I __C uint8_t *) REG_SPI_PRODUCT_ID_H) /* */ +#define pREG_SPI_CHIP_GRADE ((__I __C uint8_t *) REG_SPI_CHIP_GRADE) /* */ +#define pREG_SPI_SCRATCH_PAD ((__IO uint8_t *) REG_SPI_SCRATCH_PAD) /* */ +#define pREG_SPI_SPI_REVISION ((__I __C uint8_t *) REG_SPI_SPI_REVISION) /* */ +#define pREG_SPI_VENDOR_L ((__I __C uint8_t *) REG_SPI_VENDOR_L) /* */ +#define pREG_SPI_VENDOR_H ((__I __C uint8_t *) REG_SPI_VENDOR_H) /* */ +#define pREG_SPI_STREAM_MODE ((__IO uint8_t *) REG_SPI_STREAM_MODE) /* */ +#define pREG_SPI_INTERFACE_CONFIG_C ((__IO uint8_t *) REG_SPI_INTERFACE_CONFIG_C) /* */ +#define pREG_SPI_INTERFACE_STATUS_A ((__I __C uint8_t *) REG_SPI_INTERFACE_STATUS_A) /* */ + +/* ================================================================================= + * ADISENSE1000 Core (CORE) + * ================================================================================= */ +#define pREG_CORE_COMMAND ((__O uint8_t *) REG_CORE_COMMAND) /* Special Command */ +#define pREG_CORE_MODE ((__IO uint8_t *) REG_CORE_MODE) /* Operating Mode and DRDY Control */ +#define pREG_CORE_POWER_CONFIG ((__IO uint8_t *) REG_CORE_POWER_CONFIG) /* General Configuration */ +#define pREG_CORE_CYCLE_CONTROL ((__IO uint16_t *) REG_CORE_CYCLE_CONTROL) /* Measurement Cycle */ +#define pREG_CORE_FIFO_NUM_CYCLES ((__IO uint8_t *) REG_CORE_FIFO_NUM_CYCLES) /* Number of Measurement Cycles to Store in FIFO */ +#define pREG_CORE_MULTI_CYCLE_RATE ((__IO uint8_t *) REG_CORE_MULTI_CYCLE_RATE) /* Time Between Repeats of Multi-Cycle Conversions.... */ +#define pREG_CORE_STATUS ((__I __C uint8_t *) REG_CORE_STATUS) /* General Status */ +#define pREG_CORE_DIAGNOSTICS_STATUS ((__I __C uint16_t *) REG_CORE_DIAGNOSTICS_STATUS) /* Diagnostics Status */ +#define pREG_CORE_CHANNEL_ALERT_STATUS ((__I __C uint16_t *) REG_CORE_CHANNEL_ALERT_STATUS) /* Alert Status Summary */ +#define pREG_CORE_ALERT_DETAIL_CH0 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH0) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH1 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH1) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH2 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH2) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH3 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH3) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH4 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH4) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH5 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH5) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH6 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH6) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH7 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH7) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH8 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH8) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH9 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH9) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH10 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH10) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH11 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH11) /* Detailed Error Information */ +#define pREG_CORE_ALERT_DETAIL_CH12 ((__I __C uint8_t *) REG_CORE_ALERT_DETAIL_CH12) /* Detailed Error Information */ +#define pREG_CORE_EXTERNAL_REFERENCE1 ((__IO uint32_t *) REG_CORE_EXTERNAL_REFERENCE1) /* External Reference Information */ +#define pREG_CORE_EXTERNAL_REFERENCE2 ((__IO uint32_t *) REG_CORE_EXTERNAL_REFERENCE2) /* External Reference Information */ +#define pREG_CORE_DIAGNOSTICS_CONTROL ((__IO uint8_t *) REG_CORE_DIAGNOSTICS_CONTROL) /* Diagnostic Control */ +#define pREG_CORE_DIAGNOSTICS_EXTRA ((__IO uint8_t *) REG_CORE_DIAGNOSTICS_EXTRA) /* Extra Diagnostics Control */ +#define pREG_CORE_DATA_FIFO ((__I __C uint64_t *) REG_CORE_DATA_FIFO) /* FIFO of Sensor Results */ +#define pREG_CORE_LUT_SELECT ((__IO uint8_t *) REG_CORE_LUT_SELECT) /* Pointer to Custom Lookup Table or Polynomial */ +#define pREG_CORE_LUT_OFFSET ((__IO uint16_t *) REG_CORE_LUT_OFFSET) /* Offset into Selected LUT */ +#define pREG_CORE_LUT_DATA ((__IO uint8_t *) REG_CORE_LUT_DATA) /* Data to Read/Write from Addressed LUT Entry */ +#define pREG_CORE_CAL_SELECT ((__IO uint8_t *) REG_CORE_CAL_SELECT) /* Pointer to Calibration Values */ +#define pREG_CORE_CAL_OFFSET ((__IO uint16_t *) REG_CORE_CAL_OFFSET) /* Offset into Selected Calibration Values */ +#define pREG_CORE_CAL_DATA ((__IO uint8_t *) REG_CORE_CAL_DATA) /* Data to Read/Write from Addressed Calibration Values */ +#define pREG_CORE_REVISION ((__I __C uint32_t *) REG_CORE_REVISION) /* Hardware, Firmware Revision */ +#define pREG_CORE_CHANNEL_COUNT0 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT0) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE0 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE0) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS0 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS0) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION0 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION0) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING0 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING0) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT0 ((__IO uint32_t *) REG_CORE_FILTER_SELECT0) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME0 ((__IO uint16_t *) REG_CORE_SETTLING_TIME0) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT0 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT0) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT0 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT0) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS0 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS0) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND10 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND10) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND20 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND20) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND30 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND30) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX10 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX10) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX20 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX20) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_CHANNEL_COUNT1 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT1) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE1 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE1) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS1 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS1) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION1 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION1) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING1 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING1) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT1 ((__IO uint32_t *) REG_CORE_FILTER_SELECT1) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME1 ((__IO uint16_t *) REG_CORE_SETTLING_TIME1) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT1 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT1) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT1 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT1) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS1 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS1) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND11 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND11) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND21 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND21) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND31 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND31) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX11 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX11) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX21 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX21) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_CHANNEL_COUNT2 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT2) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE2 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE2) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS2 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS2) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION2 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION2) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING2 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING2) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT2 ((__IO uint32_t *) REG_CORE_FILTER_SELECT2) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME2 ((__IO uint16_t *) REG_CORE_SETTLING_TIME2) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT2 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT2) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT2 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT2) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS2 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS2) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND12 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND12) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND22 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND22) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND32 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND32) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX12 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX12) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX22 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX22) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_CHANNEL_COUNT3 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT3) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE3 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE3) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS3 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS3) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION3 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION3) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING3 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING3) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT3 ((__IO uint32_t *) REG_CORE_FILTER_SELECT3) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME3 ((__IO uint16_t *) REG_CORE_SETTLING_TIME3) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT3 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT3) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT3 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT3) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS3 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS3) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND13 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND13) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND23 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND23) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND33 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND33) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX13 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX13) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX23 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX23) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_CHANNEL_COUNT4 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT4) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE4 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE4) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS4 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS4) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION4 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION4) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING4 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING4) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT4 ((__IO uint32_t *) REG_CORE_FILTER_SELECT4) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME4 ((__IO uint16_t *) REG_CORE_SETTLING_TIME4) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT4 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT4) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT4 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT4) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS4 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS4) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND14 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND14) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND24 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND24) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND34 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND34) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX14 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX14) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX24 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX24) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_CHANNEL_COUNT5 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT5) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE5 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE5) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS5 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS5) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION5 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION5) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING5 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING5) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT5 ((__IO uint32_t *) REG_CORE_FILTER_SELECT5) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME5 ((__IO uint16_t *) REG_CORE_SETTLING_TIME5) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT5 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT5) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT5 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT5) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS5 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS5) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND15 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND15) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND25 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND25) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND35 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND35) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX15 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX15) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX25 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX25) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_CHANNEL_COUNT6 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT6) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE6 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE6) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS6 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS6) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION6 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION6) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING6 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING6) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT6 ((__IO uint32_t *) REG_CORE_FILTER_SELECT6) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME6 ((__IO uint16_t *) REG_CORE_SETTLING_TIME6) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT6 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT6) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT6 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT6) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS6 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS6) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND16 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND16) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND26 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND26) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND36 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND36) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX16 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX16) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX26 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX26) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_CHANNEL_COUNT7 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT7) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE7 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE7) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS7 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS7) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION7 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION7) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING7 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING7) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT7 ((__IO uint32_t *) REG_CORE_FILTER_SELECT7) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME7 ((__IO uint16_t *) REG_CORE_SETTLING_TIME7) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT7 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT7) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT7 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT7) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS7 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS7) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND17 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND17) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND27 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND27) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND37 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND37) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX17 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX17) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX27 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX27) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_CHANNEL_COUNT8 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT8) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE8 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE8) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS8 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS8) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION8 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION8) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING8 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING8) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT8 ((__IO uint32_t *) REG_CORE_FILTER_SELECT8) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME8 ((__IO uint16_t *) REG_CORE_SETTLING_TIME8) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT8 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT8) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT8 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT8) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS8 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS8) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND18 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND18) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND28 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND28) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND38 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND38) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX18 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX18) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX28 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX28) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_CHANNEL_COUNT9 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT9) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE9 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE9) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS9 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS9) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION9 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION9) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING9 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING9) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT9 ((__IO uint32_t *) REG_CORE_FILTER_SELECT9) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME9 ((__IO uint16_t *) REG_CORE_SETTLING_TIME9) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT9 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT9) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT9 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT9) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS9 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS9) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND19 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND19) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND29 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND29) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND39 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND39) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX19 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX19) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX29 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX29) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_CHANNEL_COUNT10 ((__IO uint8_t *) REG_CORE_CHANNEL_COUNT10) /* Number of Channel Occurrences per Measurement Cycle */ +#define pREG_CORE_SENSOR_TYPE10 ((__IO uint16_t *) REG_CORE_SENSOR_TYPE10) /* Sensor Select */ +#define pREG_CORE_SENSOR_DETAILS10 ((__IO uint32_t *) REG_CORE_SENSOR_DETAILS10) /* Sensor Details */ +#define pREG_CORE_CHANNEL_EXCITATION10 ((__IO uint8_t *) REG_CORE_CHANNEL_EXCITATION10) /* Excitation Current */ +#define pREG_CORE_DIGITAL_SENSOR_CODING10 ((__IO uint16_t *) REG_CORE_DIGITAL_SENSOR_CODING10) /* Digital Sensor Data Coding */ +#define pREG_CORE_FILTER_SELECT10 ((__IO uint32_t *) REG_CORE_FILTER_SELECT10) /* ADC Digital Filter Selection */ +#define pREG_CORE_SETTLING_TIME10 ((__IO uint16_t *) REG_CORE_SETTLING_TIME10) /* Settling Time */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT10 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT10) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT10 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT10) /* Low Threshold */ +#define pREG_CORE_DIGITAL_SENSOR_ADDRESS10 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_ADDRESS10) /* Sensor Address */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND110 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND110) /* Sensor Command1 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND210 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND210) /* Sensor Command2 */ +#define pREG_CORE_DIGITAL_SENSOR_COMMAND310 ((__IO uint8_t *) REG_CORE_DIGITAL_SENSOR_COMMAND310) /* Sensor Command3 */ +#define pREG_CORE_SENSOR_LUT_INDEX110 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX110) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_SENSOR_LUT_INDEX210 ((__IO uint32_t *) REG_CORE_SENSOR_LUT_INDEX210) /* Sequence of Look-Up-Table Pointers */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT11 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT11) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT11 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT11) /* Low Threshold */ +#define pREG_CORE_HIGH_THRESHOLD_LIMIT12 ((__IO uint32_t *) REG_CORE_HIGH_THRESHOLD_LIMIT12) /* High Threshold */ +#define pREG_CORE_LOW_THRESHOLD_LIMIT12 ((__IO uint32_t *) REG_CORE_LOW_THRESHOLD_LIMIT12) /* Low Threshold */ + +/* ================================================================================= + * Test (TEST) + * ================================================================================= */ +#define pREG_TEST_TEST_REG_0 ((__IO uint8_t *) REG_TEST_TEST_REG_0) /* Test Register 0 */ + +#endif + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/registers/ADISENSE1000_REGISTERS_device.h Fri Aug 25 11:17:37 2017 +0000
@@ -0,0 +1,176 @@
+/* ================================================================================
+
+ Created by : sherry
+ Created on : 2017 Jul 27, 19:13 IST
+
+ Project : ADISENSE1000_REGISTERS
+ File : ADISENSE1000_REGISTERS_device.h
+ Description : C Register Definitions
+
+ !! ADI Confidential !!
+ INTERNAL USE ONLY
+
+ Copyright (c) 2017 Analog Devices, Inc. All Rights Reserved.
+ This software is proprietary and confidential to Analog Devices, Inc. and
+ its licensors.
+
+ This file was auto-generated. Do not make local changes to this file.
+
+ Auto generation script information:
+ Script: /usr/cadtools/bin/yoda.dir/generators/inc/genHeaders
+ Last modified: 26-MAY-2017
+
+ ================================================================================ */
+
+#ifndef _ADISENSE1000_REGISTERS_DEVICE_H
+#define _ADISENSE1000_REGISTERS_DEVICE_H
+
+/* pickup integer types */
+#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
+#include <stdint.h>
+#endif /* _LANGUAGE_C */
+
+/* pickup register bitfield and bit masks */
+#include "ADISENSE1000_REGISTERS_typedefs.h"
+
+#if defined ( __CC_ARM )
+#pragma push
+#pragma anon_unions
+#endif
+
+
+#ifndef __IO
+#define __I volatile /* read-only */
+#define __C
+#define __RC const /* read-only memory ROM*/
+#define __O volatile /* write-only */
+#define __IO volatile /* read-write */
+#endif
+/** @defgroup SPI (SPI) Module
+ *
+ * @{
+ */
+
+/*! ==========================================================================
+ * \struct ADI_SPI_TypeDef
+ * \brief
+ * ========================================================================== */
+typedef struct _ADI_SENSE_SPI_TypeDef
+{
+ __IO uint8_t INTERFACE_CONFIG_A; /*!< */
+ __IO uint8_t INTERFACE_CONFIG_B; /*!< */
+ __IO uint8_t DEVICE_CONFIG; /*!< */
+ __I __C uint8_t CHIP_TYPE; /*!< */
+ __I __C uint8_t PRODUCT_ID_L; /*!< */
+ __I __C uint8_t PRODUCT_ID_H; /*!< */
+ __I __C uint8_t CHIP_GRADE; /*!< */
+ __I __C uint8_t RESERVED0[3];
+ __IO uint8_t SCRATCH_PAD; /*!< */
+ __I __C uint8_t SPI_REVISION; /*!< */
+ __I __C uint8_t VENDOR_L; /*!< */
+ __I __C uint8_t VENDOR_H; /*!< */
+ __IO uint8_t STREAM_MODE; /*!< */
+ __I __C uint8_t RESERVED1;
+ __IO uint8_t INTERFACE_CONFIG_C; /*!< */
+ __I __C uint8_t INTERFACE_STATUS_A; /*!< */
+} ADI_SENSE_SPI_TypeDef;
+
+/*!@}*/
+
+/** @defgroup CORE ADISENSE1000 Core (CORE) Module
+ * ADISENSE1000 Core
+ * @{
+ */
+
+/*! ==========================================================================
+ * \struct ADI_CORE_TypeDef
+ * \brief ADISENSE1000 Core
+ * ========================================================================== */
+typedef struct _ADI_SENSE_CORE_TypeDef
+{
+ __I __C uint8_t RESERVED0[4];
+ __O uint8_t COMMAND; /*!< Special Command */
+ __I __C uint8_t RESERVED1[3];
+ __IO uint8_t MODE; /*!< Operating Mode and DRDY Control */
+ __IO uint8_t POWER_CONFIG; /*!< General Configuration */
+ __IO uint16_t CYCLE_CONTROL; /*!< Measurement Cycle */
+ __IO uint8_t FIFO_NUM_CYCLES; /*!< Number of Measurement Cycles to Store in FIFO */
+ __IO uint8_t MULTI_CYCLE_RATE; /*!< Time Between Repeats of Multi-Cycle Conversions.... */
+ __I __C uint8_t RESERVED2[2];
+ __I __C uint8_t STATUS; /*!< General Status */
+ __I __C uint8_t RESERVED3[3];
+ __I __C uint16_t DIAGNOSTICS_STATUS; /*!< Diagnostics Status */
+ __I __C uint16_t CHANNEL_ALERT_STATUS; /*!< Alert Status Summary */
+ __I __C uint8_t ALERT_DETAIL_CH[13]; /*!< Detailed Error Information */
+ __I __C uint8_t RESERVED4[11];
+ __IO uint32_t EXTERNAL_REFERENCE1; /*!< External Reference Information */
+ __IO uint32_t EXTERNAL_REFERENCE2; /*!< External Reference Information */
+ __IO uint8_t DIAGNOSTICS_CONTROL; /*!< Diagnostic Control */
+ __IO uint8_t DIAGNOSTICS_EXTRA; /*!< Extra Diagnostics Control */
+ __I __C uint8_t RESERVED5[6];
+ __I __C uint64_t DATA_FIFO; /*!< FIFO of Sensor Results */
+ __I __C uint8_t RESERVED6[8];
+ __IO uint8_t LUT_SELECT; /*!< Pointer to Custom Lookup Table or Polynomial */
+ __I __C uint8_t RESERVED7;
+ __IO uint16_t LUT_OFFSET; /*!< Offset into Selected LUT */
+ __IO uint8_t LUT_DATA; /*!< Data to Read/Write from Addressed LUT Entry */
+ __I __C uint8_t RESERVED8[3];
+ __IO uint8_t CAL_SELECT; /*!< Pointer to Calibration Values */
+ __I __C uint8_t RESERVED9;
+ __IO uint16_t CAL_OFFSET; /*!< Offset into Selected Calibration Values */
+ __IO uint8_t CAL_DATA; /*!< Data to Read/Write from Addressed Calibration Values */
+ __I __C uint8_t RESERVED10[15];
+ __I __C uint32_t REVISION; /*!< Hardware, Firmware Revision */
+ __I __C uint8_t RESERVED11[16];
+ __IO uint8_t CHANNEL_COUNT[11]; /*!< Number of Channel Occurrences per Measurement Cycle */
+} ADI_SENSE_CORE_TypeDef;
+
+/*!@}*/
+
+/** @defgroup TEST Test (TEST) Module
+ * Test
+ * @{
+ */
+
+/*! ==========================================================================
+ * \struct ADI_TEST_TypeDef
+ * \brief Test
+ * ========================================================================== */
+typedef struct _ADI_SENSE_TEST_TypeDef
+{
+ __IO uint8_t TEST_REG_0; /*!< Test Register 0 */
+} ADI_SENSE_TEST_TypeDef;
+
+/*!@}*/
+
+/* ******************************************************************************
+ * Peripheral Memory Map Declarations
+ * *****************************************************************************/
+/*! @defgroup PMEMMAPDEC Peripheral Memory Map Declarations
+ * \addtogroup PMEMMAPDEC
+ * @{ */
+#define ADI_SENSE_SPI_BASE 0x00000000 /*!< Base address of SPI */
+#define ADI_SENSE_CORE_BASE 0x00000010 /*!< Base address of CORE */
+#define ADI_SENSE_TEST_BASE 0x00000400 /*!< Base address of TEST */
+
+/*! @} */
+
+/* ******************************************************************************
+ * Peripheral Pointer Declarations
+ * *****************************************************************************/
+/*! @Defgroup Pptrdec Peripheral Pointer Declarations
+ * \Addtogroup Pptrdec
+ * @{ */
+#define pADI_SENSE_SPI ((ADI_SENSE_SPI_TypeDef *) ADI_SPI_BASE ) /*!< Pointer to (SPI) */
+#define pADI_SENSE_CORE ((ADI_SENSE_CORE_TypeDef *) ADI_CORE_BASE ) /*!< Pointer to ADISENSE1000 Core (CORE) */
+#define pADI_SENSE_TEST ((ADI_SENSE_TEST_TypeDef *) ADI_TEST_BASE ) /*!< Pointer to Test (TEST) */
+
+/*! @} */
+
+
+#if defined (__CC_ARM)
+#pragma pop
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/inc/registers/ADISENSE1000_REGISTERS_typedefs.h Fri Aug 25 11:17:37 2017 +0000
@@ -0,0 +1,1459 @@
+/* ================================================================================
+
+ Created by : sherry
+ Created on : 2017 Jul 27, 19:13 IST
+
+ Project : ADISENSE1000_REGISTERS
+ File : ADISENSE1000_REGISTERS_typedefs.h
+ Description : C Register Structures
+
+ !! ADI Confidential !!
+ INTERNAL USE ONLY
+
+ Copyright (c) 2017 Analog Devices, Inc. All Rights Reserved.
+ This software is proprietary and confidential to Analog Devices, Inc. and
+ its licensors.
+
+ This file was auto-generated. Do not make local changes to this file.
+
+ Auto generation script information:
+ Script: /usr/cadtools/bin/yoda.dir/generators/inc/genHeaders
+ Last modified: 26-MAY-2017
+
+ ================================================================================ */
+
+#ifndef _ADISENSE1000_REGISTERS_TYPEDEFS_H
+#define _ADISENSE1000_REGISTERS_TYPEDEFS_H
+
+/* pickup integer types */
+#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
+#include <stdint.h>
+#endif /* _LANGUAGE_C */
+
+#if defined ( __CC_ARM )
+#pragma push
+#pragma anon_unions
+#endif
+
+/** @defgroup Interface_Config_A (Interface_Config_A) Register
+ * (Interface_Config_A) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_SPI_Interface_Config_A_Addr_Ascension
+ *! \brief (Addr_Ascension) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ SPI_INTERFACE_CONFIG_A_DESCEND = 0, /**< */
+ SPI_INTERFACE_CONFIG_A_ASCEND = 1 /**< */
+} ADI_SPI_Interface_Config_A_Addr_Ascension;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Interface_Config_A_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Interface_Config_A_t {
+ union {
+ struct {
+ uint8_t SW_ResetX : 1;
+ uint8_t reserved1 : 3;
+ uint8_t SDO_Enable : 1;
+ uint8_t Addr_Ascension : 1;
+ uint8_t reserved6 : 1;
+ uint8_t SW_Reset : 1;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Interface_Config_A_t;
+
+/*@}*/
+
+/** @defgroup Interface_Config_B (Interface_Config_B) Register
+ * (Interface_Config_B) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Interface_Config_B_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Interface_Config_B_t {
+ union {
+ struct {
+ uint8_t reserved0 : 7;
+ uint8_t Single_Inst : 1;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Interface_Config_B_t;
+
+/*@}*/
+
+/** @defgroup Device_Config (Device_Config) Register
+ * (Device_Config) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_SPI_Device_Config_Operating_Modes
+ *! \brief (Operating_Modes) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ SPI_DEVICE_CONFIG_NORMAL = 0, /**< */
+ SPI_DEVICE_CONFIG_SLEEP = 3 /**< */
+} ADI_SPI_Device_Config_Operating_Modes;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Device_Config_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Device_Config_t {
+ union {
+ struct {
+ uint8_t Operating_Modes : 2;
+ uint8_t reserved2 : 6;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Device_Config_t;
+
+/*@}*/
+
+/** @defgroup Chip_Type (Chip_Type) Register
+ * (Chip_Type) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Chip_Type_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Chip_Type_t {
+ union {
+ struct {
+ uint8_t Chip_Type : 4;
+ uint8_t reserved4 : 4;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Chip_Type_t;
+
+/*@}*/
+
+/** @defgroup Product_ID_L (Product_ID_L) Register
+ * (Product_ID_L) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Product_ID_L_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Product_ID_L_t {
+ union {
+ struct {
+ uint8_t Product_ID_Trim_Bits : 4;
+ uint8_t Product_ID_Fixed_Bits : 4; /**< Product_ID_Fixed_Bits[3:0] */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Product_ID_L_t;
+
+/*@}*/
+
+/** @defgroup Product_ID_H (Product_ID_H) Register
+ * (Product_ID_H) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Product_ID_H_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Product_ID_H_t {
+ union {
+ struct {
+ uint8_t Product_ID_Fixed_Bits : 8; /**< Product_ID_Fixed_Bits[11:4] */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Product_ID_H_t;
+
+/*@}*/
+
+/** @defgroup Chip_Grade (Chip_Grade) Register
+ * (Chip_Grade) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Chip_Grade_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Chip_Grade_t {
+ union {
+ struct {
+ uint8_t Device_Revision : 4;
+ uint8_t Grade : 4;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Chip_Grade_t;
+
+/*@}*/
+
+/** @defgroup Scratch_Pad (Scratch_Pad) Register
+ * (Scratch_Pad) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Scratch_Pad_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Scratch_Pad_t {
+ union {
+ struct {
+ uint8_t Scratch_Value : 8;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Scratch_Pad_t;
+
+/*@}*/
+
+/** @defgroup SPI_Revision (SPI_Revision) Register
+ * (SPI_Revision) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_SPI_SPI_Revision_Version
+ *! \brief (Version) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ SPI_SPI_REVISION_REV1_0 = 2 /**< Revision 1.0 */
+} ADI_SPI_SPI_Revision_Version;
+
+
+/* =========================================================================
+ *! \enum ADI_SPI_SPI_Revision_SPI_Type
+ *! \brief (SPI_Type) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ SPI_SPI_REVISION_ADI_SPI = 0, /**< */
+ SPI_SPI_REVISION_LPT_SPI = 2 /**< */
+} ADI_SPI_SPI_Revision_SPI_Type;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPI_SPI_Revision_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_SPI_Revision_t {
+ union {
+ struct {
+ uint8_t Version : 6;
+ uint8_t SPI_Type : 2;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_SPI_Revision_t;
+
+/*@}*/
+
+/** @defgroup Vendor_L (Vendor_L) Register
+ * (Vendor_L) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Vendor_L_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Vendor_L_t {
+ union {
+ struct {
+ uint8_t VID : 8; /**< VID[7:0] */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Vendor_L_t;
+
+/*@}*/
+
+/** @defgroup Vendor_H (Vendor_H) Register
+ * (Vendor_H) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Vendor_H_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Vendor_H_t {
+ union {
+ struct {
+ uint8_t VID : 8; /**< VID[15:8] */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Vendor_H_t;
+
+/*@}*/
+
+/** @defgroup Stream_Mode (Stream_Mode) Register
+ * (Stream_Mode) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Stream_Mode_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Stream_Mode_t {
+ union {
+ struct {
+ uint8_t Loop_Count : 8;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Stream_Mode_t;
+
+/*@}*/
+
+/** @defgroup Interface_Config_C (Interface_Config_C) Register
+ * (Interface_Config_C) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_SPI_Interface_Config_C_CRC_Enable
+ *! \brief (CRC_Enable) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ SPI_INTERFACE_CONFIG_C_DISABLED = 0, /**< */
+ SPI_INTERFACE_CONFIG_C_ENABLED = 1 /**< */
+} ADI_SPI_Interface_Config_C_CRC_Enable;
+
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Interface_Config_C_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Interface_Config_C_t {
+ union {
+ struct {
+ uint8_t CRC_EnableB : 2;
+ uint8_t reserved2 : 3;
+ uint8_t Strict_Entity_Access : 1;
+ uint8_t CRC_Enable : 2;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Interface_Config_C_t;
+
+/*@}*/
+
+/** @defgroup Interface_Status_A (Interface_Status_A) Register
+ * (Interface_Status_A) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_SPI_Interface_Status_A_Struct
+ *! \brief Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_SPI_Interface_Status_A_t {
+ union {
+ struct {
+ uint8_t Address_Invalid_Error : 1;
+ uint8_t Partial_Reg_Wr_Error : 1;
+ uint8_t Wr_To_Rd_Only_Reg_Error : 1;
+ uint8_t CRC_Error : 1;
+ uint8_t Clock_Count_Error : 1;
+ uint8_t reserved5 : 2;
+ uint8_t Not_Ready_Error : 1;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_SPI_Interface_Status_A_t;
+
+/*@}*/
+
+/** @defgroup Command Special Command (Command) Register
+ * Special Command (Command) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_CORE_Command_Special_Command
+ *! \brief Special Command (Special_Command) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_COMMAND_NOP = 0, /**< No Command */
+ CORE_COMMAND_CONVERT = 1, /**< Start ADC Conversions */
+ CORE_COMMAND_CONVERT_WITH_RAW = 2, /**< Start Conversions with Added RAW ADC Data */
+ CORE_COMMAND_RUN_DIAGNOSTICS = 3, /**< Initiate a Diagnostics Cycle */
+ CORE_COMMAND_LOAD_DEFAULTS = 4, /**< Load Relevant Registers With Default Values Appropriate to Sensor */
+ CORE_COMMAND_LOAD_CONFIG = 5, /**< Load Registers with Configuration from FLASH */
+ CORE_COMMAND_SAVE_CONFIG = 6, /**< Store Current Register Configuration to FLASH */
+ CORE_COMMAND_LATCH_CONFIG = 7, /**< Freeze Current Register Configuration and Prepare for Conversion */
+ CORE_COMMAND_LOAD_LUT = 8, /**< Load LUT from FLASH */
+ CORE_COMMAND_SAVE_LUT2 = 9 /**< Save LUT to FLASH */
+} ADI_CORE_Command_Special_Command;
+
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Command_Struct
+ *! \brief Special Command Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Command_t {
+ union {
+ struct {
+ uint8_t Special_Command : 8; /**< Special Command */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Command_t;
+
+/*@}*/
+
+/** @defgroup Mode Operating Mode and DRDY Control (Mode) Register
+ * Operating Mode and DRDY Control (Mode) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_CORE_Mode_Conversion_Mode
+ *! \brief Conversion Mode (Conversion_Mode) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_MODE_SINGLECYCLE = 0, /**< Single Cycle */
+ CORE_MODE_MULTICYCLE = 1, /**< Multi Cycle */
+ CORE_MODE_CONTINUOUS = 2, /**< Continuous Conversion */
+ CORE_MODE_MODE3 = 3 /**< Undefined */
+} ADI_CORE_Mode_Conversion_Mode;
+
+
+/* =========================================================================
+ *! \enum ADI_CORE_Mode_Drdy_Mode
+ *! \brief Indicates Behavior of DRDY with Respect to FIFO State (Drdy_Mode) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_MODE_DRDY_PER_CONVERSION = 0, /**< Data Ready Per Conversion */
+ CORE_MODE_DRDY_PER_CYCLE = 1, /**< Data Ready Per Cycle */
+ CORE_MODE_DRDY_PER_FIFO_FILL = 2, /**< Data Ready Per FIFO Fill */
+ CORE_MODE_DRDY_MODE3 = 3 /**< Undefined */
+} ADI_CORE_Mode_Drdy_Mode;
+
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Mode_Struct
+ *! \brief Operating Mode and DRDY Control Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Mode_t {
+ union {
+ struct {
+ uint8_t Conversion_Mode : 2; /**< Conversion Mode */
+ uint8_t Drdy_Mode : 2; /**< Indicates Behavior of DRDY with Respect to FIFO State */
+ uint8_t reserved4 : 1;
+ uint8_t Stdby_En : 1; /**< Standby */
+ uint8_t reserved6 : 2;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Mode_t;
+
+/*@}*/
+
+/** @defgroup Power_Config General Configuration (Power_Config) Register
+ * General Configuration (Power_Config) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Power_Config_Struct
+ *! \brief General Configuration Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Power_Config_t {
+ union {
+ struct {
+ uint8_t Power_Mode_ADC : 2; /**< ADC Power Mode */
+ uint8_t Power_Mode_MCU : 2; /**< MCU Power Mode */
+ uint8_t reserved4 : 4;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Power_Config_t;
+
+/*@}*/
+
+/** @defgroup Cycle_Control Measurement Cycle (Cycle_Control) Register
+ * Measurement Cycle (Cycle_Control) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_CORE_Cycle_Control_Cycle_Time_Units
+ *! \brief Units for Cycle Time (Cycle_Time_Units) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_CYCLE_CONTROL_MICROSECONDS = 0, /**< Micro-Seconds */
+ CORE_CYCLE_CONTROL_MILLISECONDS = 1, /**< Milli-Seconds */
+ CORE_CYCLE_CONTROL_SECONDS = 2, /**< Seconds */
+ CORE_CYCLE_CONTROL_UNDEFINED = 3 /**< Undefined */
+} ADI_CORE_Cycle_Control_Cycle_Time_Units;
+
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Cycle_Control_Struct
+ *! \brief Measurement Cycle Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Cycle_Control_t {
+ union {
+ struct {
+ uint16_t Cycle_Time : 12; /**< Duration of a Full Measurement Cycle */
+ uint16_t reserved12 : 2;
+ uint16_t Cycle_Time_Units : 2; /**< Units for Cycle Time */
+ };
+ uint16_t VALUE16;
+ };
+} ADI_CORE_Cycle_Control_t;
+
+/*@}*/
+
+/** @defgroup Fifo_Num_Cycles Number of Measurement Cycles to Store in FIFO (Fifo_Num_Cycles) Register
+ * Number of Measurement Cycles to Store in FIFO (Fifo_Num_Cycles) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Fifo_Num_Cycles_Struct
+ *! \brief Number of Measurement Cycles to Store in FIFO Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Fifo_Num_Cycles_t {
+ union {
+ struct {
+ uint8_t Fifo_Num_Cycles : 8; /**< How Many Cycles to Fill FIFO */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Fifo_Num_Cycles_t;
+
+/*@}*/
+
+/** @defgroup Multi_Cycle_Rate Time Between Repeats of Multi-Cycle Conversions.... (Multi_Cycle_Rate) Register
+ * Time Between Repeats of Multi-Cycle Conversions.... (Multi_Cycle_Rate) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Multi_Cycle_Rate_Struct
+ *! \brief Time Between Repeats of Multi-Cycle Conversions.... Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Multi_Cycle_Rate_t {
+ union {
+ struct {
+ uint8_t Multi_Cycle_Rate : 8; /**< CHANGE NAME. Defines Time Between Repetitions of FIFO Fill */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Multi_Cycle_Rate_t;
+
+/*@}*/
+
+/** @defgroup Status General Status (Status) Register
+ * General Status (Status) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Status_Struct
+ *! \brief General Status Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Status_t {
+ union {
+ struct {
+ uint8_t reserved0 : 1;
+ uint8_t Alert : 1; /**< Indicates One or More Sensors are Outside Specified Limits */
+ uint8_t Error : 1; /**< Indicates an Error */
+ uint8_t Drdy : 1; /**< Indicates a New Sensor (ADC?) Result is Available to Be Read */
+ uint8_t Cmd_Running : 1; /**< Indicates a Special Command is Active */
+ uint8_t reserved5 : 3;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Status_t;
+
+/*@}*/
+
+/** @defgroup Diagnostics_Status Diagnostics Status (Diagnostics_Status) Register
+ * Diagnostics Status (Diagnostics_Status) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Diagnostics_Status_Struct
+ *! \brief Diagnostics Status Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Diagnostics_Status_t {
+ union {
+ struct {
+ uint16_t Diagnostics_Status : 16; /**< Diagnostics Status */
+ };
+ uint16_t VALUE16;
+ };
+} ADI_CORE_Diagnostics_Status_t;
+
+/*@}*/
+
+/** @defgroup Channel_Alert_Status Alert Status Summary (Channel_Alert_Status) Register
+ * Alert Status Summary (Channel_Alert_Status) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Channel_Alert_Status_Struct
+ *! \brief Alert Status Summary Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Channel_Alert_Status_t {
+ union {
+ struct {
+ uint16_t Alert_Ch0 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch1 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch2 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch3 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch4 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch5 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch6 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch7 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch8 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch9 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch10 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch11 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t Alert_Ch12 : 1; /**< Indicates Channel is Outside Specified Limits */
+ uint16_t reserved13 : 3;
+ };
+ uint16_t VALUE16;
+ };
+} ADI_CORE_Channel_Alert_Status_t;
+
+/*@}*/
+
+/** @defgroup Alert_Detail_Ch Detailed Error Information (Alert_Detail_Ch) Register
+ * Detailed Error Information (Alert_Detail_Ch) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Alert_Detail_Ch_Struct
+ *! \brief Detailed Error Information Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Alert_Detail_Ch_t {
+ union {
+ struct {
+ uint8_t Time_Out : 1; /**< Indicates Time-Out Error from Digital Sensor */
+ uint8_t Under_Range : 1; /**< Indicates Channel Under-Range */
+ uint8_t Over_Range : 1; /**< Indicates Channel Over-Range */
+ uint8_t Low_Limit : 1; /**< Indicates Sensor Result is Less Than Low Limit */
+ uint8_t High_Limit : 1; /**< Indicates Sensor Result is Greater Than High Limit */
+ uint8_t Sensor_Open : 1; /**< Indicates Sensor Input is Open Circuit */
+ uint8_t Ref_Detect : 1; /**< Indicates Whether ADC Reference is Valid */
+ uint8_t reserved7 : 1;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Alert_Detail_Ch_t;
+
+/*@}*/
+
+/** @defgroup External_Reference1 External Reference Information (External_Reference1) Register
+ * External Reference Information (External_Reference1) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_External_Reference1_Struct
+ *! \brief External Reference Information Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_External_Reference1_t {
+ union {
+ struct {
+ uint32_t Ext_Refin1_Value : 32; /**< Refin1 Value */
+ };
+ uint32_t VALUE32;
+ };
+} ADI_CORE_External_Reference1_t;
+
+/*@}*/
+
+/** @defgroup External_Reference2 External Reference Information (External_Reference2) Register
+ * External Reference Information (External_Reference2) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_External_Reference2_Struct
+ *! \brief External Reference Information Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_External_Reference2_t {
+ union {
+ struct {
+ uint32_t Ext_Refin2_Value : 32; /**< Refin2 Value */
+ };
+ uint32_t VALUE32;
+ };
+} ADI_CORE_External_Reference2_t;
+
+/*@}*/
+
+/** @defgroup Diagnostics_Control Diagnostic Control (Diagnostics_Control) Register
+ * Diagnostic Control (Diagnostics_Control) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_CORE_Diagnostics_Control_Diag_OCD_Freq
+ *! \brief Diagnostics Open Circuit Detect Frequency (Diag_OCD_Freq) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_DIAGNOSTICS_CONTROL_OCD_FREQ0 = 0, /**< */
+ CORE_DIAGNOSTICS_CONTROL_OCD_FREQ1 = 1, /**< */
+ CORE_DIAGNOSTICS_CONTROL_OCD_FREQ2 = 2, /**< */
+ CORE_DIAGNOSTICS_CONTROL_OCD_FREQ3 = 3 /**< */
+} ADI_CORE_Diagnostics_Control_Diag_OCD_Freq;
+
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Diagnostics_Control_Struct
+ *! \brief Diagnostic Control Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Diagnostics_Control_t {
+ union {
+ struct {
+ uint8_t Diag_Global_En : 1; /**< Diagnostics Global Enable */
+ uint8_t Diag_Meas_En : 1; /**< Diagnostics Measure Enable */
+ uint8_t Diag_OCD_Freq : 2; /**< Diagnostics Open Circuit Detect Frequency */
+ uint8_t reserved4 : 4;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Diagnostics_Control_t;
+
+/*@}*/
+
+/** @defgroup Diagnostics_Extra Extra Diagnostics Control (Diagnostics_Extra) Register
+ * Extra Diagnostics Control (Diagnostics_Extra) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Diagnostics_Extra_Struct
+ *! \brief Extra Diagnostics Control Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Diagnostics_Extra_t {
+ union {
+ struct {
+ uint8_t Diagnostics_Extra : 8; /**< Additional Diagnostics Control */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Diagnostics_Extra_t;
+
+/*@}*/
+
+/** @defgroup Data_FIFO FIFO of Sensor Results (Data_FIFO) Register
+ * FIFO of Sensor Results (Data_FIFO) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Data_FIFO_Struct
+ *! \brief FIFO of Sensor Results Register bit field structure
+ * ========================================================================== */
+typedef struct __attribute__((packed, aligned(4))) _ADI_CORE_Data_FIFO_t {
+ union {
+ struct {
+ float Sensor_Result; /**< Linearized and Compensated Sensor Result */
+ uint32_t Channel_ID : 4; /**< Indicates Which Channel This FIFO Data Corresponds to */
+ uint32_t Ch_Error : 1; /**< Indicates Error on Channel */
+ uint32_t Ch_Alert : 1; /**< Indicates Alert on Channel */
+ uint32_t Ch_Raw : 1; /**< Indicates If RAW Data is Valid */
+ uint32_t Ch_Valid : 1; /**< Indicates Whether Valid Data Read from FIFO */
+ uint32_t Raw_Sample : 24; /**< ADC Result */
+ };
+ uint64_t VALUE64;
+ };
+} ADI_CORE_Data_FIFO_t;
+
+/*@}*/
+
+/** @defgroup LUT_Select Pointer to Custom Lookup Table or Polynomial (LUT_Select) Register
+ * Pointer to Custom Lookup Table or Polynomial (LUT_Select) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_LUT_Select_Struct
+ *! \brief Pointer to Custom Lookup Table or Polynomial Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_LUT_Select_t {
+ union {
+ struct {
+ uint8_t LUT_Channel : 4; /**< Which Channel's LUT / Polynomial to Access */
+ uint8_t LUT_Type : 3; /**< Indicates Whether Look-Up-Table or Polynomial Equation */
+ uint8_t LUT_RW : 1; /**< Read or Write LUT Data */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_LUT_Select_t;
+
+/*@}*/
+
+/** @defgroup LUT_Offset Offset into Selected LUT (LUT_Offset) Register
+ * Offset into Selected LUT (LUT_Offset) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_LUT_Offset_Struct
+ *! \brief Offset into Selected LUT Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_LUT_Offset_t {
+ union {
+ struct {
+ uint16_t LUT_Offset : 14; /**< Offset into Look-Up-Table */
+ uint16_t reserved14 : 2;
+ };
+ uint16_t VALUE16;
+ };
+} ADI_CORE_LUT_Offset_t;
+
+/*@}*/
+
+/** @defgroup LUT_Data Data to Read/Write from Addressed LUT Entry (LUT_Data) Register
+ * Data to Read/Write from Addressed LUT Entry (LUT_Data) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_LUT_Data_Struct
+ *! \brief Data to Read/Write from Addressed LUT Entry Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_LUT_Data_t {
+ union {
+ struct {
+ uint8_t LUT_Data : 8; /**< Data Byte to Write to / Read from Look-Up-Table */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_LUT_Data_t;
+
+/*@}*/
+
+/** @defgroup CAL_Select Pointer to Calibration Values (CAL_Select) Register
+ * Pointer to Calibration Values (CAL_Select) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_CAL_Select_Struct
+ *! \brief Pointer to Calibration Values Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_CAL_Select_t {
+ union {
+ struct {
+ uint8_t CAL_Channel : 4; /**< Which Channel's Calibration Data to Access */
+ uint8_t CAL_Type : 3; /**< NOT REQUIRED?? */
+ uint8_t CAL_RW : 1; /**< Read or Write Calibration Data */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_CAL_Select_t;
+
+/*@}*/
+
+/** @defgroup CAL_Offset Offset into Selected Calibration Values (CAL_Offset) Register
+ * Offset into Selected Calibration Values (CAL_Offset) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_CAL_Offset_Struct
+ *! \brief Offset into Selected Calibration Values Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_CAL_Offset_t {
+ union {
+ struct {
+ uint16_t CAL_Offset : 14; /**< Offset into Calibration Data */
+ uint16_t reserved14 : 2;
+ };
+ uint16_t VALUE16;
+ };
+} ADI_CORE_CAL_Offset_t;
+
+/*@}*/
+
+/** @defgroup CAL_Data Data to Read/Write from Addressed Calibration Values (CAL_Data) Register
+ * Data to Read/Write from Addressed Calibration Values (CAL_Data) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_CAL_Data_Struct
+ *! \brief Data to Read/Write from Addressed Calibration Values Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_CAL_Data_t {
+ union {
+ struct {
+ uint8_t CAL_Data : 8; /**< Data to Write to / Read from Calibration Data */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_CAL_Data_t;
+
+/*@}*/
+
+/** @defgroup Revision Hardware, Firmware Revision (Revision) Register
+ * Hardware, Firmware Revision (Revision) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Revision_Struct
+ *! \brief Hardware, Firmware Revision Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Revision_t {
+ union {
+ struct {
+ uint32_t Firmware_Revision : 8; /**< ID Info */
+ uint32_t Hardware_Revision : 8; /**< ID Info */
+ uint32_t Comms_Protocol : 8; /**< ID Info */
+ uint32_t reserved24 : 8;
+ };
+ uint32_t VALUE32;
+ };
+} ADI_CORE_Revision_t;
+
+/*@}*/
+
+/** @defgroup Channel_Count Number of Channel Occurrences per Measurement Cycle (Channel_Count) Register
+ * Number of Channel Occurrences per Measurement Cycle (Channel_Count) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Channel_Count_Struct
+ *! \brief Number of Channel Occurrences per Measurement Cycle Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Channel_Count_t {
+ union {
+ struct {
+ uint8_t Channel_Count : 7; /**< How Many Times Channel Should Appear in One Cycle */
+ uint8_t Channel_Enable : 1; /**< Enable Channel in Measurement Cycle */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Channel_Count_t;
+
+/*@}*/
+
+/** @defgroup Sensor_Type Sensor Select (Sensor_Type) Register
+ * Sensor Select (Sensor_Type) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_CORE_Sensor_Type_Sensor_Type
+ *! \brief Sensor Type (Sensor_Type) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T = 0, /**< Thermocouple T-Type Sensor */
+ CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J = 1, /**< Thermocouple J-Type Sensor */
+ CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K = 2, /**< Thermocouple K-Type Sensor */
+ CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_CUSTOM1 = 14, /**< Thermocouple Custom Sensor1 */
+ CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_CUSTOM2 = 15, /**< Thermocouple Custom Sensor2 */
+ CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100 = 16, /**< RTD 2 Wire PT100 Sensor */
+ CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000 = 17, /**< RTD 2 Wire PT1000 Sensor */
+ CORE_SENSOR_TYPE_SENSOR_RTD_2W_CUSTOM1 = 30, /**< RTD 2 Wire Custom Sensor1 */
+ CORE_SENSOR_TYPE_SENSOR_RTD_2W_CUSTOM2 = 31, /**< RTD 2 Wire Custom Sensor2 */
+ CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100 = 32, /**< RTD 3 Wire PT100 Sensor */
+ CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000 = 33, /**< RTD 3 Wire PT1000 Sensor */
+ CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_ONECONV = 44, /**< RTD 3 Wire PT100 No Chop Custom Sensor */
+ CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_ONECONV = 45, /**< RTD 3 Wire PT1000 No Chop Custom Sensor */
+ CORE_SENSOR_TYPE_SENSOR_RTD_3W_CUSTOM1 = 46, /**< RTD 3 Wire Custom Sensor1 */
+ CORE_SENSOR_TYPE_SENSOR_RTD_3W_CUSTOM2 = 47, /**< RTD 3 Wire Custom Sensor2 */
+ CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100 = 48, /**< RTD 4 Wire PT100 Sensor */
+ CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000 = 49, /**< RTD 4 Wire PT1000 Sensor */
+ CORE_SENSOR_TYPE_SENSOR_RTD_4W_CUSTOM1 = 62, /**< RTD 4 Wire Custom Sensor1 */
+ CORE_SENSOR_TYPE_SENSOR_RTD_4W_CUSTOM2 = 63, /**< RTD 4 Wire Custom Sensor2 */
+ CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K = 64, /**< Thermistor Type A 10kOhm Sensor */
+ CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K = 65, /**< Thermistor Type B 10kOhm Sensor */
+ CORE_SENSOR_TYPE_SENSOR_THERMISTOR_CUSTOM = 79, /**< Thermistor Custom Sensor */
+ CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W = 80, /**< Bridge 4 Wire Sensor */
+ CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_CUSTOM = 95, /**< Bridge 4 Wire Custom Sensor */
+ CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W = 96, /**< Bridge 6 Wire Sensor */
+ CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_CUSTOM = 111, /**< Bridge 6 Wire Custom Sensor */
+ CORE_SENSOR_TYPE_SENSOR_VOLTAGE = 112, /**< Voltage Input */
+ CORE_SENSOR_TYPE_SENSOR_CURRENT = 128, /**< Current Input */
+ CORE_SENSOR_TYPE_CUSTOM = 160, /**< Custom */
+ CORE_SENSOR_TYPE_I2C_PRESSURE1 = 2048, /**< I2C Pressure Sensor Type 1 */
+ CORE_SENSOR_TYPE_I2C_PRESSURE2 = 2049, /**< I2C Pressure Sensor Type 2 */
+ CORE_SENSOR_TYPE_SPI_PRESSURE1 = 3072, /**< SPI Pressure Sensor Type 1 */
+ CORE_SENSOR_TYPE_SPI_PRESSURE2 = 3073, /**< SPI Pressure Sensor Type 2 */
+ CORE_SENSOR_TYPE_SPI_ACCELEROMETER1 = 3074 /**< SPI Accelerometer Sensor Type 1 3-Axis */
+} ADI_CORE_Sensor_Type_Sensor_Type;
+
+
+/* =========================================================================
+ *! \enum ADI_CORE_Sensor_Type_Sensor_Category
+ *! \brief Indicates Category of Sensor (Sensor_Category) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_SENSOR_TYPE_ANALOG = 0, /**< */
+ CORE_SENSOR_TYPE_I2C = 1, /**< */
+ CORE_SENSOR_TYPE_SPI = 2, /**< */
+ CORE_SENSOR_TYPE_TBD3 = 3, /**< */
+ CORE_SENSOR_TYPE_TBD4 = 4, /**< */
+ CORE_SENSOR_TYPE_TBD5 = 5, /**< */
+ CORE_SENSOR_TYPE_TBD6 = 6, /**< */
+ CORE_SENSOR_TYPE_TBD7 = 7 /**< */
+} ADI_CORE_Sensor_Type_Sensor_Category;
+
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Sensor_Type_Struct
+ *! \brief Sensor Select Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Sensor_Type_t {
+ union {
+ struct {
+ uint16_t Sensor_Type : 12; /**< Sensor Type */
+ uint16_t Sensor_Load_Defaults : 1; /**< Indicates to Use Default Register Values */
+ uint16_t Sensor_Category : 3; /**< Indicates Category of Sensor */
+ };
+ uint16_t VALUE16;
+ };
+} ADI_CORE_Sensor_Type_t;
+
+/*@}*/
+
+/** @defgroup Sensor_Details Sensor Details (Sensor_Details) Register
+ * Sensor Details (Sensor_Details) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_CORE_Sensor_Details_Measurement_Units
+ *! \brief Units of Sensor Measurement (Measurement_Units) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_SENSOR_DETAILS_UNITS_DEGC = 0, /**< Degrees C */
+ CORE_SENSOR_DETAILS_UNITS_DEGF = 1 /**< Degrees F */
+} ADI_CORE_Sensor_Details_Measurement_Units;
+
+
+/* =========================================================================
+ *! \enum ADI_CORE_Sensor_Details_Reference_Select
+ *! \brief Reference Selection (Reference_Select) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_SENSOR_DETAILS_REF_DEFAULT = 0, /**< Default Based on Sensor Type */
+ CORE_SENSOR_DETAILS_REF_INT = 1, /**< Internal Reference */
+ CORE_SENSOR_DETAILS_REF_RINT1 = 2, /**< Internal Resistor1 */
+ CORE_SENSOR_DETAILS_REF_RINT2 = 3, /**< Internal Resistor2 */
+ CORE_SENSOR_DETAILS_REF_REXT1 = 4, /**< External Resistor on Refin1 */
+ CORE_SENSOR_DETAILS_REF_REXT2 = 5, /**< External Resistor on Refin2 */
+ CORE_SENSOR_DETAILS_REF_VEXT1 = 6, /**< External Voltage on Refin1 */
+ CORE_SENSOR_DETAILS_REF_VEXT2 = 7, /**< External Voltage on Refin2 */
+ CORE_SENSOR_DETAILS_REF_AVDD = 8 /**< AVDD */
+} ADI_CORE_Sensor_Details_Reference_Select;
+
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Sensor_Details_Struct
+ *! \brief Sensor Details Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Sensor_Details_t {
+ union {
+ struct {
+ uint32_t Measurement_Units : 4; /**< Units of Sensor Measurement */
+ uint32_t Compensation_Channel : 4; /**< Indicates Which Channel is Used to Compensate Sensor Result */
+ uint32_t Compensation_Channel2 : 4; /**< Indicates Channel for Second Term of Compensation */
+ uint32_t Compensation_Channel3 : 4; /**< Indicates Channel for Third Term of Compensation */
+ uint32_t Compensation_Only : 1; /**< Indicates to Use This Channel Only as Compensation */
+ uint32_t CJC_Publish : 1; /**< Publish Compensation Data */
+ uint32_t Reference_Buffer_Disable : 1; /**< Enable or Disable ADC Reference Buffer */
+ uint32_t Vbias : 1; /**< Controls ADC Vbias Output */
+ uint32_t Reference_Select : 4; /**< Reference Selection */
+ uint32_t PGA_Gain : 3; /**< PGA Gain */
+ uint32_t reserved27 : 1;
+ uint32_t Averaging : 3; /**< Number of ADC Results to Average */
+ uint32_t reserved31 : 1;
+ };
+ uint32_t VALUE32;
+ };
+} ADI_CORE_Sensor_Details_t;
+
+/*@}*/
+
+/** @defgroup Channel_Excitation Excitation Current (Channel_Excitation) Register
+ * Excitation Current (Channel_Excitation) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Channel_Excitation_Struct
+ *! \brief Excitation Current Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Channel_Excitation_t {
+ union {
+ struct {
+ uint8_t IOUT_Excitation_Current : 3; /**< Current Source Value */
+ uint8_t IOUT0_Disable : 1; /**< NOT NEEDED?? Disable First Current Source */
+ uint8_t IOUT1_Disable : 1; /**< NOT NEEDED?? Disable Second Current Source */
+ uint8_t reserved5 : 2;
+ uint8_t IOUT_DontChop_3Wire : 1; /**< Indicates 3-Wire Excitation Currents Should Not Be Swapped */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Channel_Excitation_t;
+
+/*@}*/
+
+/** @defgroup Digital_Sensor_Coding Digital Sensor Data Coding (Digital_Sensor_Coding) Register
+ * Digital Sensor Data Coding (Digital_Sensor_Coding) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_CORE_Digital_Sensor_Coding_Digital_Sensor_Coding
+ *! \brief I2C Address or Write Address Command for SPI Sensor (Digital_Sensor_Coding) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_DIGITAL_SENSOR_CODING_CODING_UNIPOLAR = 0, /**< Unipolar */
+ CORE_DIGITAL_SENSOR_CODING_CODING_TWOS_COMPL = 1, /**< Twos Complement */
+ CORE_DIGITAL_SENSOR_CODING_CODING_OFFSET_BINARY = 2 /**< Offset Binary */
+} ADI_CORE_Digital_Sensor_Coding_Digital_Sensor_Coding;
+
+
+/* =========================================================================
+ *! \enum ADI_CORE_Digital_Sensor_Coding_Digital_Sensor_Numbits
+ *! \brief Number of Relevant Data Bits in Digital Sensor (Digital_Sensor_Numbits) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_DIGITAL_SENSOR_CODING_DIGITAL_8_BITS = 0, /**< 8 Bits */
+ CORE_DIGITAL_SENSOR_CODING_DIGITAL_10_BITS = 1, /**< 10 Bits */
+ CORE_DIGITAL_SENSOR_CODING_DIGITAL_12_BITS = 2, /**< 12 Bits */
+ CORE_DIGITAL_SENSOR_CODING_DIGITAL_14_BITS = 3, /**< 14 Bits */
+ CORE_DIGITAL_SENSOR_CODING_DIGITAL_16_BITS = 4, /**< 16 Bits */
+ CORE_DIGITAL_SENSOR_CODING_DIGITAL_18_BITS = 5, /**< 18 Bits */
+ CORE_DIGITAL_SENSOR_CODING_DIGITAL_20_BITS = 6, /**< 20 Bits */
+ CORE_DIGITAL_SENSOR_CODING_DIGITAL_22_BITS = 7, /**< 22 Bits */
+ CORE_DIGITAL_SENSOR_CODING_DIGITAL_24_BITS = 8 /**< 24 Bits */
+} ADI_CORE_Digital_Sensor_Coding_Digital_Sensor_Numbits;
+
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Digital_Sensor_Coding_Struct
+ *! \brief Digital Sensor Data Coding Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Digital_Sensor_Coding_t {
+ union {
+ struct {
+ uint16_t Digital_Sensor_Coding : 2; /**< I2C Address or Write Address Command for SPI Sensor */
+ uint16_t Digital_Sensor_Numbits : 5; /**< Number of Relevant Data Bits in Digital Sensor */
+ uint16_t reserved7 : 1;
+ uint16_t Digital_Sensor_MSB_Position : 5; /**< Position of Data MSB in the Read Frame */
+ uint16_t reserved13 : 3;
+ };
+ uint16_t VALUE16;
+ };
+} ADI_CORE_Digital_Sensor_Coding_t;
+
+/*@}*/
+
+/** @defgroup Filter_Select ADC Digital Filter Selection (Filter_Select) Register
+ * ADC Digital Filter Selection (Filter_Select) Register.
+ * @{
+ */
+
+/* =========================================================================
+ *! \enum ADI_CORE_Filter_Select_ADC_Filter_Type
+ *! \brief ADC Digital Filter Type (ADC_Filter_Type) Enumerations
+ * ========================================================================= */
+typedef enum
+{
+ CORE_FILTER_SELECT_SINC4 = 0, /**< Sinc4 Filter */
+ CORE_FILTER_SELECT_TBD1 = 1, /**< TBD1 */
+ CORE_FILTER_SELECT_TBD2 = 2, /**< TBD2 */
+ CORE_FILTER_SELECT_FIR = 3 /**< FIR Filter */
+} ADI_CORE_Filter_Select_ADC_Filter_Type;
+
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Filter_Select_Struct
+ *! \brief ADC Digital Filter Selection Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Filter_Select_t {
+ union {
+ struct {
+ uint32_t ADC_FS : 11; /**< ADC Digital Filter Select */
+ uint32_t ADC_Filter_Type : 4; /**< ADC Digital Filter Type */
+ uint32_t reserved15 : 1;
+ uint32_t ADC_FIR_Sel : 3; /**< ADC Digital Filter FIR Type */
+ uint32_t reserved19 : 5;
+ };
+ uint32_t VALUE24;
+ };
+} ADI_CORE_Filter_Select_t;
+
+/*@}*/
+
+/** @defgroup Settling_Time Settling Time (Settling_Time) Register
+ * Settling Time (Settling_Time) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Settling_Time_Struct
+ *! \brief Settling Time Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Settling_Time_t {
+ union {
+ struct {
+ uint16_t Settling_Time : 16; /**< Settling Time to Allow When Switching to Channel */
+ };
+ uint16_t VALUE16;
+ };
+} ADI_CORE_Settling_Time_t;
+
+/*@}*/
+
+/** @defgroup High_Threshold_Limit High Threshold (High_Threshold_Limit) Register
+ * High Threshold (High_Threshold_Limit) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_High_Threshold_Limit_Struct
+ *! \brief High Threshold Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_High_Threshold_Limit_t {
+ union {
+ struct {
+ uint32_t High_Threshold : 32; /**< Upper Limit for Sensor Alert Comparison */
+ };
+ uint32_t VALUE32;
+ };
+} ADI_CORE_High_Threshold_Limit_t;
+
+/*@}*/
+
+/** @defgroup Low_Threshold_Limit Low Threshold (Low_Threshold_Limit) Register
+ * Low Threshold (Low_Threshold_Limit) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Low_Threshold_Limit_Struct
+ *! \brief Low Threshold Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Low_Threshold_Limit_t {
+ union {
+ struct {
+ uint32_t Low_Threshold : 32; /**< Lower Limit for Sensor Alert Comparison */
+ };
+ uint32_t VALUE32;
+ };
+} ADI_CORE_Low_Threshold_Limit_t;
+
+/*@}*/
+
+/** @defgroup Digital_Sensor_Address Sensor Address (Digital_Sensor_Address) Register
+ * Sensor Address (Digital_Sensor_Address) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Digital_Sensor_Address_Struct
+ *! \brief Sensor Address Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Digital_Sensor_Address_t {
+ union {
+ struct {
+ uint8_t Digital_Sensor_Address : 8; /**< I2C Address or Write Address Command for SPI Sensor */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Digital_Sensor_Address_t;
+
+/*@}*/
+
+/** @defgroup Digital_Sensor_Command1 Sensor Command1 (Digital_Sensor_Command1) Register
+ * Sensor Command1 (Digital_Sensor_Command1) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Digital_Sensor_Command1_Struct
+ *! \brief Sensor Command1 Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Digital_Sensor_Command1_t {
+ union {
+ struct {
+ uint8_t Digital_Sensor_Command1 : 8; /**< Command to Send to Digital I2C/SPI Sensor */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Digital_Sensor_Command1_t;
+
+/*@}*/
+
+/** @defgroup Digital_Sensor_Command2 Sensor Command2 (Digital_Sensor_Command2) Register
+ * Sensor Command2 (Digital_Sensor_Command2) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Digital_Sensor_Command2_Struct
+ *! \brief Sensor Command2 Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Digital_Sensor_Command2_t {
+ union {
+ struct {
+ uint8_t Digital_Sensor_Command2 : 8; /**< Command to Send to Digital I2C/SPI Sensor */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Digital_Sensor_Command2_t;
+
+/*@}*/
+
+/** @defgroup Digital_Sensor_Command3 Sensor Command3 (Digital_Sensor_Command3) Register
+ * Sensor Command3 (Digital_Sensor_Command3) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Digital_Sensor_Command3_Struct
+ *! \brief Sensor Command3 Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Digital_Sensor_Command3_t {
+ union {
+ struct {
+ uint8_t Digital_Sensor_Command3 : 8; /**< Command to Send to Digital I2C/SPI Sensor */
+ };
+ uint8_t VALUE8;
+ };
+} ADI_CORE_Digital_Sensor_Command3_t;
+
+/*@}*/
+
+/** @defgroup Sensor_LUT_Index1 Sequence of Look-Up-Table Pointers (Sensor_LUT_Index1) Register
+ * Sequence of Look-Up-Table Pointers (Sensor_LUT_Index1) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Sensor_LUT_Index1_Struct
+ *! \brief Sequence of Look-Up-Table Pointers Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Sensor_LUT_Index1_t {
+ union {
+ struct {
+ uint32_t LUT_Index0 : 6; /**< Pointer to LUT or Polynomial Correction for 1st Range */
+ uint32_t reserved6 : 2;
+ uint32_t LUT_Index1 : 6; /**< Pointer to LUT or Polynomial Correction for 2nd Range */
+ uint32_t reserved14 : 2;
+ uint32_t LUT_Index2 : 6; /**< Pointer to LUT or Polynomial Correction for 3rd Range */
+ uint32_t reserved22 : 2;
+ uint32_t LUT_Index3 : 6; /**< Pointer to LUT or Polynomial Correction for 4th Range */
+ uint32_t reserved30 : 2;
+ };
+ uint32_t VALUE32;
+ };
+} ADI_CORE_Sensor_LUT_Index1_t;
+
+/*@}*/
+
+/** @defgroup Sensor_LUT_Index2 Sequence of Look-Up-Table Pointers (Sensor_LUT_Index2) Register
+ * Sequence of Look-Up-Table Pointers (Sensor_LUT_Index2) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_CORE_Sensor_LUT_Index2_Struct
+ *! \brief Sequence of Look-Up-Table Pointers Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_CORE_Sensor_LUT_Index2_t {
+ union {
+ struct {
+ uint32_t LUT_Index4 : 6; /**< Pointer to LUT or Polynomial Correction for 5th Range */
+ uint32_t reserved6 : 2;
+ uint32_t LUT_Index5 : 6; /**< Pointer to LUT or Polynomial Correction for 6th Range */
+ uint32_t reserved14 : 2;
+ uint32_t LUT_Index6 : 6; /**< Pointer to LUT or Polynomial Correction for 7th Range */
+ uint32_t reserved22 : 2;
+ uint32_t LUT_Index7 : 6; /**< Pointer to LUT or Polynomial Correction for 8th Range */
+ uint32_t reserved30 : 2;
+ };
+ uint32_t VALUE32;
+ };
+} ADI_CORE_Sensor_LUT_Index2_t;
+
+/*@}*/
+
+/** @defgroup test_reg_0 Test Register 0 (test_reg_0) Register
+ * Test Register 0 (test_reg_0) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADI_TEST_test_reg_0_Struct
+ *! \brief Test Register 0 Register bit field structure
+ * ========================================================================== */
+typedef struct _ADI_TEST_test_reg_0_t {
+ union {
+ struct {
+ uint8_t testbit1 : 1;
+ uint8_t testbit2 : 2;
+ uint8_t testbit3 : 1;
+ uint8_t testbit7 : 1;
+ uint8_t testbit4 : 1;
+ uint8_t testbit5 : 1;
+ uint8_t testbit6 : 1;
+ };
+ uint8_t VALUE8;
+ };
+} ADI_TEST_test_reg_0_t;
+
+/*@}*/
+
+
+#if defined (__CC_ARM)
+#pragma pop
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/spi_nucleo.h Fri Aug 25 11:17:37 2017 +0000 @@ -0,0 +1,62 @@ +/*! + ****************************************************************************** + * @file: spi_nucleo.h + * @brief: Thin wrapper for spi interface to nucleo + *----------------------------------------------------------------------------- + * +Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc. + +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + - Modified versions of the software must be conspicuously marked as such. + - This software is licensed solely and exclusively for use with processors + manufactured by or for Analog Devices, Inc. + - This software may not be combined or merged with other code in any manner + that would cause the software to become subject to terms and conditions + which differ from those listed here. + - Neither the name of Analog Devices, Inc. nor the names of its + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + - The use of this software may or may not infringe the patent rights of one + or more patent holders. This license does not release you from the + requirement that you obtain separate licenses from these patent holders + to use this software. + +THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN +NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL +PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __SPI_NUCLEO_H__ +#define __SPI_NUCLEO_H__ + +/******************************************************************************/ +/* Include Files */ +/******************************************************************************/ +#include "inc/interface.h" +#include "inc/adi_sense_types.h" + +#define REG_CMD_SIZE 2 + +ADI_SENSE_RESULT ADISense1000_HostSpiOpen(spiSettings spiConfig); +ADI_SENSE_RESULT +ADISense1000_HostSpiTransfer(uint8_t *pData, uint16_t nTxLen, bool bCsHold); +ADI_SENSE_RESULT ADISense1000_HostSpiClose(); +#endif /* __SPI_NUCLEO_H__ */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/main.cpp Fri Aug 25 11:17:37 2017 +0000
@@ -0,0 +1,167 @@
+/*!
+ ******************************************************************************
+ * @file: main.cpp
+ * @brief:
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ - Modified versions of the software must be conspicuously marked as such.
+ - This software is licensed solely and exclusively for use with processors
+ manufactured by or for Analog Devices, Inc.
+ - This software may not be combined or merged with other code in any manner
+ that would cause the software to become subject to terms and conditions
+ which differ from those listed here.
+ - Neither the name of Analog Devices, Inc. nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+ - The use of this software may or may not infringe the patent rights of one
+ or more patent holders. This license does not release you from the
+ requirement that you obtain separate licenses from these patent holders
+ to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+/******************************************************************************/
+/* Include Files */
+/******************************************************************************/
+#include "mbed.h"
+#include "inc/adisense1000.h"
+
+#define BITP_VALID_DATA (7)
+#define SAMPLE_COUNT (10)
+
+void setupCJC0(void);
+void setupSENSOR0(void);
+
+Serial pc(PA_11, PA_12, 115200);
+
+ADI_Channel_Config_t CJC0;
+ADI_Channel_Config_t SENSOR0;
+
+int main() {
+ uint8_t chStatus = 0;
+ uint16_t deviceID = 0;
+ uint32_t rawSample = 0;
+ float temperature = 0;
+ bool validSample = 0;
+ ADI_CORE_Status_t devStatus;
+ ADI_SENSE_RESULT retValue;
+
+ pc.printf("\r\n\r\n\r\n\r\n");
+
+ retValue = ADISense1000_Open();
+ pc.printf("Host - Device Comms Opened with return: %d\r\n", retValue);
+
+ retValue = ADISense1000_GetID(&deviceID);
+ pc.printf("Read device ID 0x%lx with return %d\r\n", deviceID, retValue);
+
+ retValue = ADISense1000_GetStatus(&devStatus);
+ pc.printf("Read Status 0x%lx with return %d\r\n", devStatus, retValue);
+
+ retValue = ADISense1000_ConfigureModule();
+ pc.printf("Configure Module with return %d\r\n", retValue);
+
+ setupCJC0();
+ pc.printf("\r\nStart CJC0 Channel Config \r\n");
+ retValue = ADISense1000_ConfigureChannel(ADI_SENSE_CJC0, &CJC0);
+ pc.printf("Channel setup complete with return: %d\r\n", retValue);
+
+ setupSENSOR0();
+ pc.printf("\r\nStart SENSOR0 Channel Config \r\n");
+ retValue = ADISense1000_ConfigureChannel(ADI_SENSE_SENSOR_0, &SENSOR0);
+ pc.printf("Channel setup complete with return: %d\r\n", retValue);
+
+ retValue = ADISense1000_StartMeasurement(CORE_COMMAND_CONVERT_WITH_RAW);
+ pc.printf("Measurement started with return: %d\r\n\r\n", retValue);
+
+
+ while(!ADISense1000_SampleReady()) {
+ }
+
+
+ for(uint8_t i=0; i<(SAMPLE_COUNT*2); i++)
+ {
+ /* Read data from the enabled channels */
+ retValue = ADISense1000_GetData(&rawSample, &temperature, &chStatus);
+ validSample = (chStatus >> BITP_VALID_DATA)&0x01;
+ pc.printf("-%s- :: Sample # %2d Channel # %2d :: -%s- :: Raw %8d :: Temperature %.7f\r\n",
+ ((retValue>0) ? "ERROR" : "OK") , (i+1), (chStatus&0x0f), (validSample ? "VALID" : "INVALID"), rawSample, temperature);
+ }
+
+ while (true) {
+ pc.printf("()\r");
+ wait(1);
+ pc.printf("[]\r");
+ wait(1);
+ }
+
+}
+
+
+void setupCJC0(void)
+{
+ CJC0.Count.Channel_Count = SAMPLE_COUNT - 1;
+ CJC0.Count.Channel_Enable = 1;
+
+ CJC0.Type.Sensor_Type = CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100;
+ CJC0.Type.Sensor_Category = CORE_SENSOR_TYPE_ANALOG;
+ CJC0.Type.Sensor_Load_Defaults = 0;
+
+ CJC0.Details.CJC_Publish = 1;
+ CJC0.Details.Vbias = 0;
+ CJC0.Details.Reference_Buffer_Disable = 0;
+ CJC0.Details.Reference_Select = CORE_SENSOR_DETAILS_REF_RINT1;
+ CJC0.Details.PGA_Gain = 3; /* G=8 */
+
+ CJC0.Excitation.IOUT_Excitation_Current = 4; /* 500uA */
+ CJC0.Excitation.IOUT0_Disable = 0;
+
+ CJC0.DigitalCoding.VALUE16 = 0;
+
+ CJC0.FilterSelect.ADC_Filter_Type = CORE_FILTER_SELECT_FIR;
+ CJC0.FilterSelect.ADC_FIR_Sel = 3; /* 25 SPS */;
+}
+
+
+void setupSENSOR0(void)
+{
+ SENSOR0.Count.Channel_Count = SAMPLE_COUNT - 1;
+ SENSOR0.Count.Channel_Enable = 1;
+
+ SENSOR0.Type.Sensor_Type = CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K;
+ SENSOR0.Type.Sensor_Category = CORE_SENSOR_TYPE_ANALOG;
+ SENSOR0.Type.Sensor_Load_Defaults = 0;
+
+ SENSOR0.Details.Vbias = 1;
+ SENSOR0.Details.Reference_Buffer_Disable = 1;
+ SENSOR0.Details.Compensation_Channel = 0; /* CJC0 */
+ SENSOR0.Details.Reference_Select = CORE_SENSOR_DETAILS_REF_INT;
+ SENSOR0.Details.PGA_Gain = 5; /* G=32 */
+
+ SENSOR0.Excitation.VALUE8 = 0;
+ SENSOR0.DigitalCoding.VALUE16 = 0;
+
+ SENSOR0.FilterSelect.ADC_Filter_Type = CORE_FILTER_SELECT_FIR;
+ SENSOR0.FilterSelect.ADC_FIR_Sel = 3; /* 25 SPS */;
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/adisense1000.cpp Fri Aug 25 11:17:37 2017 +0000
@@ -0,0 +1,633 @@
+/*!
+ ******************************************************************************
+ * @file: adisense1000.cpp
+ * @brief:
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ - Modified versions of the software must be conspicuously marked as such.
+ - This software is licensed solely and exclusively for use with processors
+ manufactured by or for Analog Devices, Inc.
+ - This software may not be combined or merged with other code in any manner
+ that would cause the software to become subject to terms and conditions
+ which differ from those listed here.
+ - Neither the name of Analog Devices, Inc. nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+ - The use of this software may or may not infringe the patent rights of one
+ or more patent holders. This license does not release you from the
+ requirement that you obtain separate licenses from these patent holders
+ to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+/******************************************************************************/
+/* Include Files */
+/******************************************************************************/
+
+#include "mbed.h"
+#include "inc/spi_nucleo.h"
+#include "inc/gpio_nucleo.h"
+#include "inc/adisense1000.h"
+
+#define BIT(n) (1 << (n))
+#define BIT_MASK(len) (BIT(len)-1)
+
+#define MAX_RCV_BYTES (100)
+#define MAX_REG_SIZE (4)
+
+#define GET_SAMPLE_TIMEOUT (1)
+
+extern Serial pc;
+Timer readTimeout;
+
+uint8_t rcvBuff[MAX_RCV_BYTES] = {0};
+uint8_t txdBuff[MAX_REG_SIZE] = {0};
+
+/*
+ For v0.1 we pass this into ADISense1000_HostGpioOpen but it is not being used.
+ This is because the os dependant wrapper for the nucleo is using classes which
+ are hardcoded globally. We should probally wrap the os layer in a c wrapper
+ so these c++ functions are hidden from the user
+ */
+gpioSettings gpioConfig[HOST_GPIO_COUNT] =
+{
+ {D2, OUTPUT, HIGH},
+ {D3, INPUT, LOW},
+ {D4, INPUT, LOW},
+ {D5, INPUT, LOW}
+};
+
+/* Same as mentioned for gpioConfig applies here */
+spiSettings spiConfigure;
+
+/*!
+ * @brief Init SPI and GPIO for ADISense1000.
+ *
+ * @param[in] void
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE If GPIO open failed.
+ * - #ADI_SENSE_FAILURE If SPI open failed.
+ *
+ * @details Configure GPIO for ADISense1000 module and open
+ * SPI communications to ADISense1000 module.
+ */
+ADI_SENSE_RESULT ADISense1000_Open(void)
+{
+ if (ADISense1000_HostGpioOpen(gpioConfig) != ADI_SENSE_SUCCESS)
+ {
+ return ADI_SENSE_FAILURE;
+ }
+
+ if (ADISense1000_HostSpiOpen(spiConfigure) != ADI_SENSE_SUCCESS)
+ {
+ return ADI_SENSE_FAILURE;
+ }
+
+ return ADI_SENSE_SUCCESS;
+}
+
+
+/*!
+ * @brief Get the product ID for Module
+ *
+ * @param[in]
+ * @param[out] pProductID : Pointer to uint16_t for Product ID.
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE If receive product ID fails.
+ *
+ * @details Read the product ID for ADISense1000 module.
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_GetID(uint16_t *pProductID)
+{
+ ADI_SENSE_RESULT eRet;
+ uint8_t id_l, id_h;
+
+ eRet = ADISense1000_RegRead(regMap[SPI_PRODUCT_ID_L].addr,
+ regMap[SPI_PRODUCT_ID_L].size,
+ rcvBuff);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ id_l = rcvBuff[0];
+
+ eRet = ADISense1000_RegRead(regMap[SPI_PRODUCT_ID_H].addr,
+ regMap[SPI_PRODUCT_ID_H].size,
+ rcvBuff);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ id_h = rcvBuff[0];
+ *pProductID = ((id_h << 8)&0xff00)|id_l;
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Basic configuration of module for V0.1
+ *
+ * @param[in] void
+ * @param[out]
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE If write module config fails.
+ *
+ * @details Basic function to set a fixed configuration.
+ */
+ADI_SENSE_RESULT ADISense1000_ConfigureModule(void)
+{
+ ADI_SENSE_RESULT eRet;
+ ADI_CORE_Mode_t modeReg;
+
+ modeReg.Conversion_Mode = CORE_MODE_SINGLECYCLE;
+ modeReg.Drdy_Mode = CORE_MODE_DRDY_PER_CYCLE;
+
+ eRet = ADISense1000_RegWrite(regMap[CORE_MODE].addr,
+ regMap[CORE_MODE].size,
+ (uint8_t*)&modeReg);
+
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Get general status of ADISense1000 module.
+ *
+ * @param[in]
+ * @param[out] pStatus : Pointer to CORE Status struct.
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE If status register read fails.
+ *
+ * @details Read the general status register for the ADISense1000
+ * module. Indicates Error, Alert conditions, data ready
+ * and command running.
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_GetStatus(ADI_CORE_Status_t *pStatus)
+{
+ ADI_SENSE_RESULT eRet;
+
+ pStatus->VALUE8 = 0;
+ eRet = ADISense1000_RegRead(regMap[CORE_STATUS].addr,
+ regMap[CORE_STATUS].size,
+ rcvBuff);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ pStatus->VALUE8 = rcvBuff[0];
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Get a list of channels with alerts.
+ *
+ * @param[in]
+ * @param[out] pStatus : List of Channel detailed alerts.
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE If request for channel alerts fails.
+ *
+ * @details Read the channel alert register. If channel alert register
+ * indicates alert on a channel, process the channel detailed
+ * alert register.
+ */
+ADI_SENSE_RESULT ADISense1000_GetChannelAlert(ADI_Channel_Alert_t pAlerts)
+{
+ ADI_SENSE_RESULT eRet;
+ uint8_t i;
+ uint8_t chAlertReg;
+ uint16_t n;
+
+ memset(pAlerts, 0, sizeof(ADI_Channel_Alert_t));
+
+ eRet = ADISense1000_RegRead(regMap[CORE_CHANNEL_ALERT_STATUS].addr,
+ regMap[CORE_CHANNEL_ALERT_STATUS].size,
+ rcvBuff);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ n = ((rcvBuff[1] << 8)&0xff00) | rcvBuff[0];
+ for (i=0; i<ADI_SENSE_NUM_CHANNELS; i++)
+ {
+ if ((n >> i)&0x1)
+ {
+ chAlertReg = baseAlertReg[i];
+ eRet = ADISense1000_RegRead(regMap[chAlertReg].addr,
+ regMap[chAlertReg].size,
+ rcvBuff);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ pAlerts[i].VALUE8 = rcvBuff[0];
+ }
+
+ }
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Send a configuration to one channel.
+ *
+ * @param[in] ADI_Channel_ID_t : Channel Identifier.
+ * @param[in] ADI_Channel_Config_t : Pointer to channel config data.
+ * @param[out]
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE If set channel config fails.
+ *
+ * @details Sends the entire configuration to the select channel during a
+ * single transfer.
+ */
+ADI_SENSE_RESULT ADISense1000_ConfigureChannel(ADI_Channel_ID_t eChannel,
+ ADI_Channel_Config_t *pConfig)
+{
+ ADI_SENSE_RESULT eRet;
+ uint8_t chBaseReg;
+
+ chBaseReg = baseReg[eChannel];
+ eRet = ADISense1000_RegWrite(regMap[chBaseReg].addr,
+ sizeof(ADI_Channel_Config_t),
+ (uint8_t*)pConfig);
+
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Start a measurement cycle.
+ *
+ * @param[in] ADI_CORE_Command_Special_Command : Conversion result format.
+ * @param[out]
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE
+ *
+ * @details Sends the latch config command. Configuration for channels in
+ * conversion cycle should be completed before this function.
+ * Channel enabled bit should be set before this function.
+ * Starts a conversion and configures the format of the sample.
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_StartMeasurement(
+ ADI_CORE_Command_Special_Command cmd)
+{
+ ADI_SENSE_RESULT eRet;
+ ADI_CORE_Command_t command;
+ ADI_CORE_Status_t *statusreg = (ADI_CORE_Status_t *)rcvBuff;
+
+ /* Send the latch command */
+ command.Special_Command = CORE_COMMAND_LATCH_CONFIG;
+ eRet = ADISense1000_RegWrite(regMap[CORE_COMMAND].addr,
+ regMap[CORE_COMMAND].size,
+ (uint8_t*)&command);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ /* Wait for command to finish */
+ statusreg->Cmd_Running = true;
+ while (statusreg->Cmd_Running)
+ {
+ wait_ms(10);
+ eRet = ADISense1000_RegRead(regMap[CORE_STATUS].addr,
+ regMap[CORE_STATUS].size,
+ rcvBuff);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+ }
+
+ /* Send the user command */
+ command.Special_Command = cmd;
+ eRet = ADISense1000_RegWrite(regMap[CORE_COMMAND].addr,
+ regMap[CORE_COMMAND].size,
+ (uint8_t*)&command);
+
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+
+ /* Wait for command to finish */
+ statusreg->Cmd_Running = true;
+ while (statusreg->Cmd_Running)
+ {
+ wait_ms(10);
+ eRet = ADISense1000_RegRead(regMap[CORE_STATUS].addr,
+ regMap[CORE_STATUS].size,
+ rcvBuff);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+ }
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Stop measurement on selected channel.
+ *
+ * @param[in] ADI_Channel_ID_t : Channel identifier.
+ * @param[out]
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE
+ *
+ * @details Un-sets the channel enable bit in the selected channel
+ * count register. Retains the cycle count in the channel
+ * count register.
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_StopMeasurement(ADI_Channel_ID_t eChannel)
+{
+ ADI_SENSE_RESULT eRet;
+ uint8_t setValue;
+ uint8_t chBaseReg;
+ ADI_CORE_Command_t command;
+ ADI_CORE_Status_t *statusreg = (ADI_CORE_Status_t *)rcvBuff;
+
+ /* Read back the count register to store the cycle count for this
+ * channel.
+ */
+ chBaseReg = baseReg[eChannel];
+ eRet = ADISense1000_RegRead(regMap[chBaseReg].addr,
+ regMap[chBaseReg].size, rcvBuff);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ /* Zero the enable bit of the count register */
+ setValue = rcvBuff[0] & 0x7f;
+ eRet = ADISense1000_RegWrite(regMap[chBaseReg].addr,
+ regMap[chBaseReg].size,
+ &setValue);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ /* Send the latch command */
+ command.Special_Command = CORE_COMMAND_LATCH_CONFIG;
+ eRet = ADISense1000_RegWrite(regMap[CORE_COMMAND].addr,
+ regMap[CORE_COMMAND].size,
+ (uint8_t*)&command);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ /* Wait for command to finish */
+ statusreg->Cmd_Running = true;
+ while (statusreg->Cmd_Running)
+ {
+ wait_ms(10);
+ eRet = ADISense1000_RegRead(regMap[CORE_STATUS].addr,
+ regMap[CORE_STATUS].size,
+ rcvBuff);
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+ }
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Get input status of data ready gpio
+ *
+ * @param[in] void
+ * @param[out]
+ *
+ * @return Status
+ * - #bool State of the data ready pin.
+ *
+ *
+ */
+bool ADISense1000_SampleReady(void)
+{
+ bool bDrdy=false;
+
+ ADISense1000_HostGpioGet(HOST_READY, &bDrdy);
+ return bDrdy;
+}
+
+/*!
+ * @brief Request sample for a selected channel.
+ *
+ * @param[in] ADI_Channel_ID_t : Channel identifier.
+ * @param[out] uint32_t : Pointer to raw ADC sample for channel.
+ * @param[out] float : Pointer to linearised ADC sample for channel.
+ * @param[out] uint8_t : Pointer to channel status.
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE
+ *
+ * @details Reads Data FIFO until a sample for the requested channel is
+ * received.
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_GetData(uint32_t *pRaw, float *pSample,
+ uint8_t *pStatus)
+{
+ ADI_SENSE_RESULT eRet;
+ ADI_CORE_Data_FIFO_t *pChSample = (ADI_CORE_Data_FIFO_t *)rcvBuff;
+ bool bTimeOut = false;
+ uint32_t timeNow;
+ uint32_t runTime;
+
+ /* Read Data FIFO buffer until sample for channel is read */
+ readTimeout.reset();
+ readTimeout.start();
+ timeNow = readTimeout.read();
+ do {
+ eRet = ADISense1000_RegRead(regMap[CORE_DATA_FIFO].addr,
+ regMap[CORE_DATA_FIFO].size,
+ rcvBuff);
+ runTime = (readTimeout.read() - timeNow);
+ if (runTime > GET_SAMPLE_TIMEOUT)
+ {
+ bTimeOut = true;
+ }
+ wait_ms(10);
+ }
+ while ((pChSample->Ch_Valid != 1) && eRet == ADI_SENSE_SUCCESS &&
+ !(bTimeOut));
+
+ readTimeout.stop();
+
+ if (eRet != ADI_SENSE_SUCCESS)
+ {
+ pChSample->Raw_Sample = 0;
+ pChSample->Sensor_Result = 0;
+ *pRaw = pChSample->Raw_Sample;
+ *pSample = pChSample->Sensor_Result;
+ *pStatus = (pChSample->Channel_ID)|((pChSample->Ch_Error << 4))|
+ ((pChSample->Ch_Alert << 5))|((pChSample->Ch_Raw << 6))|
+ ((pChSample->Ch_Valid << 7));
+
+ return eRet;
+ }
+
+ if (bTimeOut == true)
+ {
+ pChSample->Raw_Sample = 0;
+ pChSample->Sensor_Result = 0;
+ *pRaw = pChSample->Raw_Sample;
+ *pSample = pChSample->Sensor_Result;
+ *pStatus = (pChSample->Channel_ID)|((pChSample->Ch_Error << 4))|
+ ((pChSample->Ch_Alert << 5))|((pChSample->Ch_Raw << 6))|
+ ((pChSample->Ch_Valid << 7));
+
+ return ADI_SENSE_NO_DATA;
+ }
+
+ *pRaw = pChSample->Raw_Sample;
+ *pSample = pChSample->Sensor_Result;
+ *pStatus = (pChSample->Channel_ID)|((pChSample->Ch_Error << 4))|
+ ((pChSample->Ch_Alert << 5))|((pChSample->Ch_Raw << 6))|
+ ((pChSample->Ch_Valid << 7));
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Get register value from ADISense1000 Module
+ *
+ * @param[in] uint16_t : Register Identifier
+ * @param[out] uint32_t : Pointer to the register value.
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE
+ * - #ADI_SENSE_INVALID_OPERATION Invalid register identifier.
+ *
+ * @details Will return the value for any of the ADISense modules
+ * 1 byte to 4 byte size. Data FIFO register is not available to
+ * this function.
+ */
+ADI_SENSE_RESULT ADISense1000_GetRegister(uint16_t reg, uint32_t *pRegValue)
+{
+ ADI_SENSE_RESULT eRet;
+ uint8_t i;
+ uint32_t n;
+
+ if (regMap[reg].rw == WRITE_ONLY || reg > REGISTER_MAP_COUNT
+ || regMap[reg].size > 4)
+ {
+ return ADI_SENSE_INVALID_OPERATION;
+ }
+
+ eRet = ADISense1000_RegRead(regMap[reg].addr, regMap[reg].size, rcvBuff);
+
+ if(eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ n=0;
+ for (i=0; i<regMap[reg].size; i++)
+ {
+ n = n | (rcvBuff[i] << (i*8));
+ }
+
+ *pRegValue = n & BIT_MASK((regMap[reg].size*8));
+
+ return ADI_SENSE_SUCCESS;
+}
+
+
+/*!
+ * @brief Set register value to ADISense1000 Module
+ *
+ * @param[in] uint16_t : Register Identifier.
+ * @param[in] uint32_t : Value to write to register.
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - #ADI_SENSE_FAILURE
+ * - #ADI_SENSE_INVALID_OPERATION Invalid register identifier.
+ *
+ * @details Will write a value to any of the writable ADISense modules
+ * regiters from 1 byte to 4 byte size.
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_SetRegister(uint16_t reg, uint32_t regValue)
+{
+ ADI_SENSE_RESULT eRet;
+
+ if (regMap[reg].rw == READ_ONLY || reg > REGISTER_MAP_COUNT
+ || regMap[reg].size > 4)
+ {
+ return ADI_SENSE_INVALID_OPERATION;
+ }
+
+ eRet = ADISense1000_RegWrite(regMap[reg].addr, regMap[reg].size,
+ (uint8_t*)(®Value));
+
+ if(eRet != ADI_SENSE_SUCCESS)
+ {
+ return eRet;
+ }
+
+ return ADI_SENSE_SUCCESS;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/gpio_nucleo.cpp Fri Aug 25 11:17:37 2017 +0000
@@ -0,0 +1,197 @@
+/*!
+ ******************************************************************************
+ * @file: gpio_nucleo.c
+ * @brief: ADISense1000 OS Dependant wrapper layer for gpio
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ - Modified versions of the software must be conspicuously marked as such.
+ - This software is licensed solely and exclusively for use with processors
+ manufactured by or for Analog Devices, Inc.
+ - This software may not be combined or merged with other code in any manner
+ that would cause the software to become subject to terms and conditions
+ which differ from those listed here.
+ - Neither the name of Analog Devices, Inc. nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+ - The use of this software may or may not infringe the patent rights of one
+ or more patent holders. This license does not release you from the
+ requirement that you obtain separate licenses from these patent holders
+ to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+/******************************************************************************/
+/* Include Files */
+/******************************************************************************/
+
+#include "inc/gpio_nucleo.h"
+
+DigitalOut resetPin(D2, 1);
+DigitalIn errorPin(D3);
+DigitalIn alertPin(D4);
+DigitalIn readyPin(D5);
+
+/*!
+ * @brief Register a new gpio pin
+ *
+ * @param[in] config gpio connections to configure
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_HostGpioOpen(gpioSettings *config)
+{
+ /*
+ For v0.1 we are using the mbed api so this function is
+ not required. The digital classes are declared globally.
+ Parameters are placeholders for future revisions
+ */
+ resetPin = 1;
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Get input status of gpio
+ *
+ * @param[in] pinID Gpio to be read
+ * @param[out] bState State of gpio pin
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_HostGpioGet(gpioPins pinID, bool *bState)
+{
+ switch(pinID)
+ {
+ case HOST_RESET:
+ // Digital Output only
+ break;
+ case HOST_ERROR:
+ *bState = !errorPin ? false : true;
+ break;
+ case HOST_ALERT:
+ *bState = !alertPin ? false : true;
+ break;
+ case HOST_READY:
+ *bState = !readyPin ? false : true;
+ break;
+ default:
+ return ADI_SENSE_FAILURE;
+ }
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Set output status of gpio
+ *
+ * @param[in] pinID Gpio to be set
+ * @param[out] bState New state of pin
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_HostGpioSet(gpioPins pinID, bool bState)
+{
+ switch(pinID)
+ {
+ case HOST_RESET:
+ resetPin = bState;
+ break;
+ case HOST_ERROR:
+ // Digital Input only
+ break;
+ case HOST_ALERT:
+ // Digital Input only
+ break;
+ case HOST_READY:
+ // Digital Input only
+ break;
+ default:
+ return ADI_SENSE_FAILURE;
+ }
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief
+ *
+ * @param[in]
+ * @param[out]
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_HostGpioIrqEnable()
+{
+ // TODO: Not required for v0.1
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief
+ *
+ * @param[in]
+ * @param[out]
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_HostGpioIrqDisable()
+{
+ // TODO: Not required for v0.1
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief
+ *
+ * @param[in]
+ * @param[out]
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_HostGpioClose()
+{
+ return ADI_SENSE_SUCCESS;
+}
+/**
+ * @}
+ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/register_interface.cpp Fri Aug 25 11:17:37 2017 +0000
@@ -0,0 +1,127 @@
+/*!
+ ******************************************************************************
+ * @file: register_interface.cpp
+ * @brief: ADISense1000 interface to register map in adisense firmware
+ *-----------------------------------------------------------------------------
+ *
+Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc.
+
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ - Modified versions of the software must be conspicuously marked as such.
+ - This software is licensed solely and exclusively for use with processors
+ manufactured by or for Analog Devices, Inc.
+ - This software may not be combined or merged with other code in any manner
+ that would cause the software to become subject to terms and conditions
+ which differ from those listed here.
+ - Neither the name of Analog Devices, Inc. nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+ - The use of this software may or may not infringe the patent rights of one
+ or more patent holders. This license does not release you from the
+ requirement that you obtain separate licenses from these patent holders
+ to use this software.
+
+THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+/******************************************************************************/
+/* Include Files */
+/******************************************************************************/
+#include "inc/register_interface.h"
+#include "inc/spi_nucleo.h"
+
+#define BUFFER_SIZE 256
+#define CS_HOLD 1
+
+#define SET_WRITE_COMMAND(offset) \
+ do { \
+ uint16_t command = 0x8000 | (offset & 0x7FFF); \
+ txBuff[0] = command >> 8; \
+ txBuff[1] = command & 0xFF; \
+ } while(0)
+
+#define SET_READ_COMMAND(offset) \
+ do { \
+ uint16_t command = (offset & 0x7FFF); \
+ txBuff[0] = command >> 8; \
+ txBuff[1] = command & 0xFF; \
+ } while(0)
+
+static uint8_t txBuff[BUFFER_SIZE];
+
+/*!
+ * @brief Write configuration to adisense1000 register
+ *
+ * @param[in] addr id of register to write too
+ * @param[in] size size of register in bytes
+ * @param[in] pData data to be written
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT
+ADISense1000_RegWrite(uint16_t addr, uint16_t size, uint8_t *pData)
+{
+ memset(txBuff, 0, sizeof(txBuff));
+
+ SET_WRITE_COMMAND(addr);
+
+ for (int i = 2; i < (size + REG_CMD_SIZE); i++)
+ {
+ txBuff[i] = pData[i - REG_CMD_SIZE];
+ }
+
+ if (ADISense1000_HostSpiTransfer(txBuff, (size + REG_CMD_SIZE),
+ !CS_HOLD) != ADI_SENSE_SUCCESS)
+ return ADI_SENSE_FAILURE;
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Read value of adisense1000 register
+ *
+ * @param[in] addr id of register to read from
+ * @param[in] size size of register in bytes
+ * @param[out] pData value from register
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT
+ADISense1000_RegRead(uint16_t addr, uint16_t size, uint8_t *data)
+{
+ memset(txBuff, 0, sizeof(txBuff));
+
+ SET_READ_COMMAND(addr);
+
+ if (ADISense1000_HostSpiTransfer(txBuff, size, !CS_HOLD) != ADI_SENSE_SUCCESS)
+ return ADI_SENSE_FAILURE;
+
+ memcpy(data, txBuff, size);
+
+ return ADI_SENSE_SUCCESS;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/spi_nucleo.cpp Fri Aug 25 11:17:37 2017 +0000
@@ -0,0 +1,297 @@
+/*!
+ ******************************************************************************
+ * @file: spi_nucleo.cpp
+ * @brief: ADISense1000 OS Dependant wrapper layer for spi
+ *-----------------------------------------------------------------------------
+ *
+ Copyright (c) 2017 Emutex Ltd. / Analog Devices, Inc.
+
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without modification,
+ are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ - Modified versions of the software must be conspicuously marked as such.
+ - This software is licensed solely and exclusively for use with processors
+ manufactured by or for Analog Devices, Inc.
+ - This software may not be combined or merged with other code in any manner
+ that would cause the software to become subject to terms and conditions
+ which differ from those listed here.
+ - Neither the name of Analog Devices, Inc. nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+ - The use of this software may or may not infringe the patent rights of one
+ or more patent holders. This license does not release you from the
+ requirement that you obtain separate licenses from these patent holders
+ to use this software.
+
+ THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
+ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
+ TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
+ (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
+ PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+/******************************************************************************/
+/* Include Files */
+/******************************************************************************/
+#include "inc/spi_nucleo.h"
+
+#define BUFFER_SIZE 256
+#define CMD_BIT 7
+
+#define SPI_MODE_0 0
+#define SPI_FRAME_SIZE_8 8
+#define SPI_CLOCK_FREQUENCY_700KHZ 700000
+#define DEVICE_SPI_ASYNCH 1
+#define TIMEOUT_3_SEC 3.0
+
+// DummyByte config defines
+#define SPI_CHIP_TYPE_ADDR 0x03
+#define SPI_CHIP_TYPE_VALUE 0x07
+#define READ_CMD 0x00
+#define MAX_SYNC_ATTEMPTS 50
+#define DUMMY_BYTE_COUNT 1
+
+#define CHECK_BIT(var, pos) ((var) & (1 << (pos)))
+
+SPI spi(SPI_MOSI, SPI_MISO, SPI_SCK);
+DigitalOut chipSel(D10, 1);
+
+event_callback_t callbck;
+Timer timeout;
+
+volatile int intType;
+volatile bool cbkFired;
+
+static uint8_t rxBuff[BUFFER_SIZE];
+
+void callbackFired(int event)
+{
+ cbkFired = true;
+ intType = event;
+}
+
+static int transferComplete()
+{
+ int rc = 0;
+
+ timeout.start();
+ while ((cbkFired != true) && (intType != SPI_EVENT_COMPLETE))
+ {
+ if (timeout.read() > TIMEOUT_3_SEC)
+ {
+ rc = -1;
+ break;
+ }
+ }
+ timeout.stop();
+
+ cbkFired = false;
+ intType = 0;
+
+ return rc;
+}
+
+static int spiWrite(uint8_t *data, uint8_t txSize, bool bCsHold)
+{
+ int rc;
+
+ // Assert chip select
+ if (!bCsHold)
+ {
+ chipSel = 0;
+ }
+
+ rc = spi.transfer(data, txSize, (uint8_t *)NULL, 0,
+ callbck, SPI_EVENT_COMPLETE);
+
+ rc = transferComplete();
+
+ // De assert chip select
+ if (!bCsHold)
+ {
+ chipSel = 1;
+ }
+
+ return rc;
+}
+
+static int spiRead(uint8_t *data, uint16_t rxSize, bool bCsHold)
+{
+ int rc;
+
+ // Assert chip select
+ chipSel = 0;
+
+ // Send read command address
+ rc = spi.transfer(data, REG_CMD_SIZE, (uint8_t *)NULL, 0,
+ callbck, SPI_EVENT_COMPLETE);
+
+ rc = transferComplete();
+
+ if (rc < 0)
+ {
+ chipSel = 1;
+ return rc;
+ }
+
+ for (int i = 0; i < DUMMY_BYTE_COUNT; i++) {
+ rc = spi.write(0);
+ }
+
+ // Retrieve data from slave
+ rc = spi.transfer((uint8_t *)NULL, rxSize, rxBuff, rxSize,
+ callbck, SPI_EVENT_COMPLETE);
+
+ rc = transferComplete();
+
+ if (rc < 0)
+ {
+ chipSel = 1;
+ return rc;
+ }
+
+ // De assert chip select
+ if (!bCsHold)
+ {
+ chipSel = 1;
+ }
+
+ return rc;
+}
+
+static int syncWithAdisense1000()
+{
+ uint8_t txBuff[20];
+ uint8_t nRxLen = 1;
+ bool bCsHoldOff = false;
+ uint16_t nAttempts = 0;
+
+ memset(txBuff, 0, sizeof(txBuff));
+
+ txBuff[0] = READ_CMD;
+ txBuff[1] = SPI_CHIP_TYPE_ADDR;
+
+ while (rxBuff[0] != SPI_CHIP_TYPE_VALUE)
+ {
+ if(spiRead(txBuff, nRxLen, bCsHoldOff) < 0)
+ {
+ return -1;
+ }
+
+ if (nAttempts >= MAX_SYNC_ATTEMPTS)
+ {
+ return -1;
+ }
+
+ nAttempts++;
+ wait_ms(100);
+ }
+ /* TODO: Reminder not to forget about the following routine which was previously
+ used: Not valid currently as we are hardcoding the dummy byte count
+ This is a temporary fix until we have a defined spi protocall.
+ This function reads the spi chip type (fixed value) and determines how many
+ dummy bytes need to be sent in a spi read transaction.
+ The dummy bytes varies depending on clock speed, debug/release build on
+ adisense, and will keep varying as the code grows. So this elimantes the need
+ to manually modify the dummy bytes.
+ */
+
+ return 0;
+}
+
+/*!
+ * @brief Register a new spi connection
+ *
+ * @param[in] spiConfig spi settings for connection
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_HostSpiOpen(spiSettings spiConfig)
+{
+ /*
+ For v0.1 we are using the mbed api.
+ The digital classes are declared globally.
+ Parameters are placeholders for future revisions.
+ */
+
+ cbkFired = false;
+ intType = 0;
+
+ callbck.attach(callbackFired);
+
+ spi.format(SPI_FRAME_SIZE_8, SPI_MODE_0);
+ spi.frequency(SPI_CLOCK_FREQUENCY_700KHZ);
+
+ if (syncWithAdisense1000() != ADI_SENSE_SUCCESS)
+ return ADI_SENSE_FAILURE;
+
+ return ADI_SENSE_SUCCESS;
+}
+
+/*!
+ * @brief Transfer data to slave device
+ *
+ * @param[in] pData array with transfer data
+ * @param[in] nTxLen number of bytes to transfer
+ * @param[in] bCsHold keep cs high/low after transfer
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT
+ADISense1000_HostSpiTransfer(uint8_t *pData, uint16_t nTxLen, bool bCsHold)
+{
+ int txWrite = CHECK_BIT(pData[0], CMD_BIT);
+
+ if (txWrite)
+ {
+ if (spiWrite(pData, nTxLen, bCsHold) < 0)
+ return ADI_SENSE_FAILURE;
+ else
+ return ADI_SENSE_SUCCESS;
+ }
+
+ if(spiRead(pData, nTxLen, bCsHold) < 0)
+ return ADI_SENSE_FAILURE;
+
+ memcpy(pData, rxBuff, nTxLen);
+
+ return ADI_SENSE_SUCCESS;
+}
+
+
+/*!
+ * @brief Close spi connection
+ *
+ * @param[in]
+ *
+ * @return Status
+ * - #ADI_SENSE_SUCCESS Call completed successfully.
+ * - todo
+ *
+ */
+ADI_SENSE_RESULT ADISense1000_HostSpiClose()
+{
+ return ADI_SENSE_SUCCESS;
+}
+/**
+ * @}
+ */
+