SDMP_IOT / Mbed OS AdiSense1000_SmartBabySeat

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inc/registers/ADISENSE1000_REGISTERS.h@2:625a45555a85, 2017-08-25 (annotated)

Committer:
kevin1990
Date:
Fri Aug 25 11:17:37 2017 +0000
Revision:
2:625a45555a85
Sensor Channel 0 Type K example

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kevin1990 2:625a45555a85 1 /* ================================================================================
kevin1990 2:625a45555a85 2
kevin1990 2:625a45555a85 3 Created by : sherry
kevin1990 2:625a45555a85 4 Created on : 2017 Jul 27, 19:13 IST
kevin1990 2:625a45555a85 5
kevin1990 2:625a45555a85 6 Project : ADISENSE1000_REGISTERS
kevin1990 2:625a45555a85 7 File : ADISENSE1000_REGISTERS.h
kevin1990 2:625a45555a85 8 Description : Register Definitions
kevin1990 2:625a45555a85 9
kevin1990 2:625a45555a85 10 !! ADI Confidential !!
kevin1990 2:625a45555a85 11 INTERNAL USE ONLY
kevin1990 2:625a45555a85 12
kevin1990 2:625a45555a85 13 Copyright (c) 2017 Analog Devices, Inc. All Rights Reserved.
kevin1990 2:625a45555a85 14 This software is proprietary and confidential to Analog Devices, Inc. and
kevin1990 2:625a45555a85 15 its licensors.
kevin1990 2:625a45555a85 16
kevin1990 2:625a45555a85 17 This file was auto-generated. Do not make local changes to this file.
kevin1990 2:625a45555a85 18
kevin1990 2:625a45555a85 19 Auto generation script information:
kevin1990 2:625a45555a85 20 Script: /usr/cadtools/bin/yoda.dir/generators/inc/genHeaders
kevin1990 2:625a45555a85 21 Last modified: 26-MAY-2017
kevin1990 2:625a45555a85 22
kevin1990 2:625a45555a85 23 ================================================================================ */
kevin1990 2:625a45555a85 24
kevin1990 2:625a45555a85 25 #ifndef _DEF_ADISENSE1000_REGISTERS_H
kevin1990 2:625a45555a85 26 #define _DEF_ADISENSE1000_REGISTERS_H
kevin1990 2:625a45555a85 27
kevin1990 2:625a45555a85 28 #if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
kevin1990 2:625a45555a85 29 #include <stdint.h>
kevin1990 2:625a45555a85 30 #endif /* _LANGUAGE_C */
kevin1990 2:625a45555a85 31
kevin1990 2:625a45555a85 32 #ifndef __ADI_GENERATED_DEF_HEADERS__
kevin1990 2:625a45555a85 33 #define __ADI_GENERATED_DEF_HEADERS__ 1
kevin1990 2:625a45555a85 34 #endif
kevin1990 2:625a45555a85 35
kevin1990 2:625a45555a85 36 #define __ADI_HAS_CORE__ 1
kevin1990 2:625a45555a85 37 #define __ADI_HAS_SPI__ 1
kevin1990 2:625a45555a85 38 #define __ADI_HAS_TEST__ 1
kevin1990 2:625a45555a85 39
kevin1990 2:625a45555a85 40 /* ============================================================================================================================
kevin1990 2:625a45555a85 41
kevin1990 2:625a45555a85 42 ============================================================================================================================ */
kevin1990 2:625a45555a85 43
kevin1990 2:625a45555a85 44 /* ============================================================================================================================
kevin1990 2:625a45555a85 45 SPI
kevin1990 2:625a45555a85 46 ============================================================================================================================ */
kevin1990 2:625a45555a85 47 #define MOD_SPI_BASE 0x00000000 /* */
kevin1990 2:625a45555a85 48 #define MOD_SPI_MASK 0x00007FFF /* */
kevin1990 2:625a45555a85 49 #define REG_SPI_INTERFACE_CONFIG_A_RESET 0x00000010 /* Reset Value for Interface_Config_A */
kevin1990 2:625a45555a85 50 #define REG_SPI_INTERFACE_CONFIG_A 0x00000000
kevin1990 2:625a45555a85 51 #define REG_SPI_INTERFACE_CONFIG_B_RESET 0x00000000 /* Reset Value for Interface_Config_B */
kevin1990 2:625a45555a85 52 #define REG_SPI_INTERFACE_CONFIG_B 0x00000001
kevin1990 2:625a45555a85 53 #define REG_SPI_DEVICE_CONFIG_RESET 0x00000000 /* Reset Value for Device_Config */
kevin1990 2:625a45555a85 54 #define REG_SPI_DEVICE_CONFIG 0x00000002
kevin1990 2:625a45555a85 55 #define REG_SPI_CHIP_TYPE_RESET 0x00000007 /* Reset Value for Chip_Type */
kevin1990 2:625a45555a85 56 #define REG_SPI_CHIP_TYPE 0x00000003
kevin1990 2:625a45555a85 57 #define REG_SPI_PRODUCT_ID_L_RESET 0x00000020 /* Reset Value for Product_ID_L */
kevin1990 2:625a45555a85 58 #define REG_SPI_PRODUCT_ID_L 0x00000004
kevin1990 2:625a45555a85 59 #define REG_SPI_PRODUCT_ID_H_RESET 0x00000000 /* Reset Value for Product_ID_H */
kevin1990 2:625a45555a85 60 #define REG_SPI_PRODUCT_ID_H 0x00000005
kevin1990 2:625a45555a85 61 #define REG_SPI_CHIP_GRADE_RESET 0x00000000 /* Reset Value for Chip_Grade */
kevin1990 2:625a45555a85 62 #define REG_SPI_CHIP_GRADE 0x00000006
kevin1990 2:625a45555a85 63 #define REG_SPI_SCRATCH_PAD_RESET 0x00000000 /* Reset Value for Scratch_Pad */
kevin1990 2:625a45555a85 64 #define REG_SPI_SCRATCH_PAD 0x0000000A
kevin1990 2:625a45555a85 65 #define REG_SPI_SPI_REVISION_RESET 0x00000082 /* Reset Value for SPI_Revision */
kevin1990 2:625a45555a85 66 #define REG_SPI_SPI_REVISION 0x0000000B
kevin1990 2:625a45555a85 67 #define REG_SPI_VENDOR_L_RESET 0x00000056 /* Reset Value for Vendor_L */
kevin1990 2:625a45555a85 68 #define REG_SPI_VENDOR_L 0x0000000C
kevin1990 2:625a45555a85 69 #define REG_SPI_VENDOR_H_RESET 0x00000004 /* Reset Value for Vendor_H */
kevin1990 2:625a45555a85 70 #define REG_SPI_VENDOR_H 0x0000000D
kevin1990 2:625a45555a85 71 #define REG_SPI_STREAM_MODE_RESET 0x00000000 /* Reset Value for Stream_Mode */
kevin1990 2:625a45555a85 72 #define REG_SPI_STREAM_MODE 0x0000000E
kevin1990 2:625a45555a85 73 #define REG_SPI_INTERFACE_CONFIG_C_RESET 0x00000023 /* Reset Value for Interface_Config_C */
kevin1990 2:625a45555a85 74 #define REG_SPI_INTERFACE_CONFIG_C 0x00000010
kevin1990 2:625a45555a85 75 #define REG_SPI_INTERFACE_STATUS_A_RESET 0x00000000 /* Reset Value for Interface_Status_A */
kevin1990 2:625a45555a85 76 #define REG_SPI_INTERFACE_STATUS_A 0x00000011
kevin1990 2:625a45555a85 77
kevin1990 2:625a45555a85 78 /* ============================================================================================================================
kevin1990 2:625a45555a85 79 SPI Register BitMasks, Positions & Enumerations
kevin1990 2:625a45555a85 80 ============================================================================================================================ */
kevin1990 2:625a45555a85 81 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 82 SPI_INTERFACE_CONFIG_A Pos/Masks Description
kevin1990 2:625a45555a85 83 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 84 #define BITP_SPI_INTERFACE_CONFIG_A_SW_RESET 7
kevin1990 2:625a45555a85 85 #define BITP_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 5
kevin1990 2:625a45555a85 86 #define BITP_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 4
kevin1990 2:625a45555a85 87 #define BITP_SPI_INTERFACE_CONFIG_A_SW_RESETX 0
kevin1990 2:625a45555a85 88 #define BITM_SPI_INTERFACE_CONFIG_A_SW_RESET 0x00000080
kevin1990 2:625a45555a85 89 #define BITM_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 0x00000020
kevin1990 2:625a45555a85 90 #define BITM_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 0x00000010
kevin1990 2:625a45555a85 91 #define BITM_SPI_INTERFACE_CONFIG_A_SW_RESETX 0x00000001
kevin1990 2:625a45555a85 92 #define ENUM_SPI_INTERFACE_CONFIG_A_DESCEND 0x00000000
kevin1990 2:625a45555a85 93 #define ENUM_SPI_INTERFACE_CONFIG_A_ASCEND 0x00000020
kevin1990 2:625a45555a85 94
kevin1990 2:625a45555a85 95 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 96 SPI_INTERFACE_CONFIG_B Pos/Masks Description
kevin1990 2:625a45555a85 97 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 98 #define BITP_SPI_INTERFACE_CONFIG_B_SINGLE_INST 7
kevin1990 2:625a45555a85 99 #define BITM_SPI_INTERFACE_CONFIG_B_SINGLE_INST 0x00000080
kevin1990 2:625a45555a85 100
kevin1990 2:625a45555a85 101 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 102 SPI_DEVICE_CONFIG Pos/Masks Description
kevin1990 2:625a45555a85 103 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 104 #define BITP_SPI_DEVICE_CONFIG_OPERATING_MODES 0
kevin1990 2:625a45555a85 105 #define BITM_SPI_DEVICE_CONFIG_OPERATING_MODES 0x00000003
kevin1990 2:625a45555a85 106 #define ENUM_SPI_DEVICE_CONFIG_NORMAL 0x00000000
kevin1990 2:625a45555a85 107 #define ENUM_SPI_DEVICE_CONFIG_SLEEP 0x00000003
kevin1990 2:625a45555a85 108
kevin1990 2:625a45555a85 109 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 110 SPI_CHIP_TYPE Pos/Masks Description
kevin1990 2:625a45555a85 111 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 112 #define BITP_SPI_CHIP_TYPE_CHIP_TYPE 0
kevin1990 2:625a45555a85 113 #define BITM_SPI_CHIP_TYPE_CHIP_TYPE 0x0000000F
kevin1990 2:625a45555a85 114
kevin1990 2:625a45555a85 115 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 116 SPI_PRODUCT_ID_L Pos/Masks Description
kevin1990 2:625a45555a85 117 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 118 #define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 4
kevin1990 2:625a45555a85 119 #define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0
kevin1990 2:625a45555a85 120 #define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 0x000000F0
kevin1990 2:625a45555a85 121 #define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0x0000000F
kevin1990 2:625a45555a85 122
kevin1990 2:625a45555a85 123 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 124 SPI_PRODUCT_ID_H Pos/Masks Description
kevin1990 2:625a45555a85 125 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 126 #define BITP_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0
kevin1990 2:625a45555a85 127 #define BITM_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0x000000FF
kevin1990 2:625a45555a85 128
kevin1990 2:625a45555a85 129 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 130 SPI_CHIP_GRADE Pos/Masks Description
kevin1990 2:625a45555a85 131 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 132 #define BITP_SPI_CHIP_GRADE_GRADE 4
kevin1990 2:625a45555a85 133 #define BITP_SPI_CHIP_GRADE_DEVICE_REVISION 0
kevin1990 2:625a45555a85 134 #define BITM_SPI_CHIP_GRADE_GRADE 0x000000F0
kevin1990 2:625a45555a85 135 #define BITM_SPI_CHIP_GRADE_DEVICE_REVISION 0x0000000F
kevin1990 2:625a45555a85 136
kevin1990 2:625a45555a85 137 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 138 SPI_SCRATCH_PAD Pos/Masks Description
kevin1990 2:625a45555a85 139 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 140 #define BITP_SPI_SCRATCH_PAD_SCRATCH_VALUE 0
kevin1990 2:625a45555a85 141 #define BITM_SPI_SCRATCH_PAD_SCRATCH_VALUE 0x000000FF
kevin1990 2:625a45555a85 142
kevin1990 2:625a45555a85 143 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 144 SPI_SPI_REVISION Pos/Masks Description
kevin1990 2:625a45555a85 145 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 146 #define BITP_SPI_SPI_REVISION_SPI_TYPE 6
kevin1990 2:625a45555a85 147 #define BITP_SPI_SPI_REVISION_VERSION 0
kevin1990 2:625a45555a85 148 #define BITM_SPI_SPI_REVISION_SPI_TYPE 0x000000C0
kevin1990 2:625a45555a85 149 #define BITM_SPI_SPI_REVISION_VERSION 0x0000003F
kevin1990 2:625a45555a85 150 #define ENUM_SPI_SPI_REVISION_ADI_SPI 0x00000000
kevin1990 2:625a45555a85 151 #define ENUM_SPI_SPI_REVISION_LPT_SPI 0x00000080
kevin1990 2:625a45555a85 152 #define ENUM_SPI_SPI_REVISION_REV1_0 0x00000002 /* Version: Revision 1.0 */
kevin1990 2:625a45555a85 153
kevin1990 2:625a45555a85 154 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 155 SPI_VENDOR_L Pos/Masks Description
kevin1990 2:625a45555a85 156 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 157 #define BITP_SPI_VENDOR_L_VID 0
kevin1990 2:625a45555a85 158 #define BITM_SPI_VENDOR_L_VID 0x000000FF
kevin1990 2:625a45555a85 159
kevin1990 2:625a45555a85 160 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 161 SPI_VENDOR_H Pos/Masks Description
kevin1990 2:625a45555a85 162 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 163 #define BITP_SPI_VENDOR_H_VID 0
kevin1990 2:625a45555a85 164 #define BITM_SPI_VENDOR_H_VID 0x000000FF
kevin1990 2:625a45555a85 165
kevin1990 2:625a45555a85 166 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 167 SPI_STREAM_MODE Pos/Masks Description
kevin1990 2:625a45555a85 168 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 169 #define BITP_SPI_STREAM_MODE_LOOP_COUNT 0
kevin1990 2:625a45555a85 170 #define BITM_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF
kevin1990 2:625a45555a85 171
kevin1990 2:625a45555a85 172 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 173 SPI_INTERFACE_CONFIG_C Pos/Masks Description
kevin1990 2:625a45555a85 174 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 175 #define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 6
kevin1990 2:625a45555a85 176 #define BITP_SPI_INTERFACE_CONFIG_C_STRICT_ENTITY_ACCESS 5
kevin1990 2:625a45555a85 177 #define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0
kevin1990 2:625a45555a85 178 #define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 0x000000C0
kevin1990 2:625a45555a85 179 #define BITM_SPI_INTERFACE_CONFIG_C_STRICT_ENTITY_ACCESS 0x00000020
kevin1990 2:625a45555a85 180 #define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0x00000003
kevin1990 2:625a45555a85 181 #define ENUM_SPI_INTERFACE_CONFIG_C_DISABLED 0x00000000
kevin1990 2:625a45555a85 182 #define ENUM_SPI_INTERFACE_CONFIG_C_ENABLED 0x00000040
kevin1990 2:625a45555a85 183
kevin1990 2:625a45555a85 184 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 185 SPI_INTERFACE_STATUS_A Pos/Masks Description
kevin1990 2:625a45555a85 186 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 187 #define BITP_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 7
kevin1990 2:625a45555a85 188 #define BITP_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 4
kevin1990 2:625a45555a85 189 #define BITP_SPI_INTERFACE_STATUS_A_CRC_ERROR 3
kevin1990 2:625a45555a85 190 #define BITP_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 2
kevin1990 2:625a45555a85 191 #define BITP_SPI_INTERFACE_STATUS_A_PARTIAL_REG_WR_ERROR 1
kevin1990 2:625a45555a85 192 #define BITP_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0
kevin1990 2:625a45555a85 193 #define BITM_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 0x00000080
kevin1990 2:625a45555a85 194 #define BITM_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 0x00000010
kevin1990 2:625a45555a85 195 #define BITM_SPI_INTERFACE_STATUS_A_CRC_ERROR 0x00000008
kevin1990 2:625a45555a85 196 #define BITM_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 0x00000004
kevin1990 2:625a45555a85 197 #define BITM_SPI_INTERFACE_STATUS_A_PARTIAL_REG_WR_ERROR 0x00000002
kevin1990 2:625a45555a85 198 #define BITM_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0x00000001
kevin1990 2:625a45555a85 199
kevin1990 2:625a45555a85 200
kevin1990 2:625a45555a85 201 /* ============================================================================================================================
kevin1990 2:625a45555a85 202 ADISENSE1000 Core Registers
kevin1990 2:625a45555a85 203 ============================================================================================================================ */
kevin1990 2:625a45555a85 204
kevin1990 2:625a45555a85 205 /* ============================================================================================================================
kevin1990 2:625a45555a85 206 CORE
kevin1990 2:625a45555a85 207 ============================================================================================================================ */
kevin1990 2:625a45555a85 208 #define MOD_CORE_BASE 0x00000010 /* ADISENSE1000 Core Registers */
kevin1990 2:625a45555a85 209 #define MOD_CORE_MASK 0x00007FFF /* ADISENSE1000 Core Registers */
kevin1990 2:625a45555a85 210 #define REG_CORE_COMMAND_RESET 0x00000000 /* Reset Value for Command */
kevin1990 2:625a45555a85 211 #define REG_CORE_COMMAND 0x00000014 /* CORE Special Command */
kevin1990 2:625a45555a85 212 #define REG_CORE_MODE_RESET 0x00000000 /* Reset Value for Mode */
kevin1990 2:625a45555a85 213 #define REG_CORE_MODE 0x00000018 /* CORE Operating Mode and DRDY Control */
kevin1990 2:625a45555a85 214 #define REG_CORE_POWER_CONFIG_RESET 0x00000000 /* Reset Value for Power_Config */
kevin1990 2:625a45555a85 215 #define REG_CORE_POWER_CONFIG 0x00000019 /* CORE General Configuration */
kevin1990 2:625a45555a85 216 #define REG_CORE_CYCLE_CONTROL_RESET 0x00000000 /* Reset Value for Cycle_Control */
kevin1990 2:625a45555a85 217 #define REG_CORE_CYCLE_CONTROL 0x0000001A /* CORE Measurement Cycle */
kevin1990 2:625a45555a85 218 #define REG_CORE_FIFO_NUM_CYCLES_RESET 0x00000001 /* Reset Value for Fifo_Num_Cycles */
kevin1990 2:625a45555a85 219 #define REG_CORE_FIFO_NUM_CYCLES 0x0000001C /* CORE Number of Measurement Cycles to Store in FIFO */
kevin1990 2:625a45555a85 220 #define REG_CORE_MULTI_CYCLE_RATE_RESET 0x00000000 /* Reset Value for Multi_Cycle_Rate */
kevin1990 2:625a45555a85 221 #define REG_CORE_MULTI_CYCLE_RATE 0x0000001D /* CORE Time Between Repeats of Multi-Cycle Conversions.... */
kevin1990 2:625a45555a85 222 #define REG_CORE_STATUS_RESET 0x00000000 /* Reset Value for Status */
kevin1990 2:625a45555a85 223 #define REG_CORE_STATUS 0x00000020 /* CORE General Status */
kevin1990 2:625a45555a85 224 #define REG_CORE_DIAGNOSTICS_STATUS_RESET 0x00000000 /* Reset Value for Diagnostics_Status */
kevin1990 2:625a45555a85 225 #define REG_CORE_DIAGNOSTICS_STATUS 0x00000024 /* CORE Diagnostics Status */
kevin1990 2:625a45555a85 226 #define REG_CORE_CHANNEL_ALERT_STATUS_RESET 0x00000000 /* Reset Value for Channel_Alert_Status */
kevin1990 2:625a45555a85 227 #define REG_CORE_CHANNEL_ALERT_STATUS 0x00000026 /* CORE Alert Status Summary */
kevin1990 2:625a45555a85 228 #define REG_CORE_ALERT_DETAIL_CHn_RESET 0x00000000 /* Reset Value for Alert_Detail_Ch[n] */
kevin1990 2:625a45555a85 229 #define REG_CORE_ALERT_DETAIL_CH0_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH0 */
kevin1990 2:625a45555a85 230 #define REG_CORE_ALERT_DETAIL_CH1_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH1 */
kevin1990 2:625a45555a85 231 #define REG_CORE_ALERT_DETAIL_CH2_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH2 */
kevin1990 2:625a45555a85 232 #define REG_CORE_ALERT_DETAIL_CH3_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH3 */
kevin1990 2:625a45555a85 233 #define REG_CORE_ALERT_DETAIL_CH4_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH4 */
kevin1990 2:625a45555a85 234 #define REG_CORE_ALERT_DETAIL_CH5_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH5 */
kevin1990 2:625a45555a85 235 #define REG_CORE_ALERT_DETAIL_CH6_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH6 */
kevin1990 2:625a45555a85 236 #define REG_CORE_ALERT_DETAIL_CH7_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH7 */
kevin1990 2:625a45555a85 237 #define REG_CORE_ALERT_DETAIL_CH8_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH8 */
kevin1990 2:625a45555a85 238 #define REG_CORE_ALERT_DETAIL_CH9_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH9 */
kevin1990 2:625a45555a85 239 #define REG_CORE_ALERT_DETAIL_CH10_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH10 */
kevin1990 2:625a45555a85 240 #define REG_CORE_ALERT_DETAIL_CH11_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH11 */
kevin1990 2:625a45555a85 241 #define REG_CORE_ALERT_DETAIL_CH12_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH12 */
kevin1990 2:625a45555a85 242 #define REG_CORE_ALERT_DETAIL_CH0 0x00000028 /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 243 #define REG_CORE_ALERT_DETAIL_CH1 0x00000029 /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 244 #define REG_CORE_ALERT_DETAIL_CH2 0x0000002A /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 245 #define REG_CORE_ALERT_DETAIL_CH3 0x0000002B /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 246 #define REG_CORE_ALERT_DETAIL_CH4 0x0000002C /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 247 #define REG_CORE_ALERT_DETAIL_CH5 0x0000002D /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 248 #define REG_CORE_ALERT_DETAIL_CH6 0x0000002E /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 249 #define REG_CORE_ALERT_DETAIL_CH7 0x0000002F /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 250 #define REG_CORE_ALERT_DETAIL_CH8 0x00000030 /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 251 #define REG_CORE_ALERT_DETAIL_CH9 0x00000031 /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 252 #define REG_CORE_ALERT_DETAIL_CH10 0x00000032 /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 253 #define REG_CORE_ALERT_DETAIL_CH11 0x00000033 /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 254 #define REG_CORE_ALERT_DETAIL_CH12 0x00000034 /* CORE Detailed Error Information */
kevin1990 2:625a45555a85 255 #define REG_CORE_ALERT_DETAIL_CHn(i) (REG_CORE_ALERT_DETAIL_CH0 + ((i) * 1))
kevin1990 2:625a45555a85 256 #define REG_CORE_ALERT_DETAIL_CHn_COUNT 13
kevin1990 2:625a45555a85 257 #define REG_CORE_EXTERNAL_REFERENCE1_RESET 0x00000000 /* Reset Value for External_Reference1 */
kevin1990 2:625a45555a85 258 #define REG_CORE_EXTERNAL_REFERENCE1 0x00000040 /* CORE External Reference Information */
kevin1990 2:625a45555a85 259 #define REG_CORE_EXTERNAL_REFERENCE2_RESET 0x00000000 /* Reset Value for External_Reference2 */
kevin1990 2:625a45555a85 260 #define REG_CORE_EXTERNAL_REFERENCE2 0x00000044 /* CORE External Reference Information */
kevin1990 2:625a45555a85 261 #define REG_CORE_DIAGNOSTICS_CONTROL_RESET 0x00000000 /* Reset Value for Diagnostics_Control */
kevin1990 2:625a45555a85 262 #define REG_CORE_DIAGNOSTICS_CONTROL 0x00000048 /* CORE Diagnostic Control */
kevin1990 2:625a45555a85 263 #define REG_CORE_DIAGNOSTICS_EXTRA_RESET 0x00000000 /* Reset Value for Diagnostics_Extra */
kevin1990 2:625a45555a85 264 #define REG_CORE_DIAGNOSTICS_EXTRA 0x00000049 /* CORE Extra Diagnostics Control */
kevin1990 2:625a45555a85 265 #define REG_CORE_DATA_FIFO_RESET 0x00000000 /* Reset Value for Data_FIFO */
kevin1990 2:625a45555a85 266 #define REG_CORE_DATA_FIFO 0x00000050 /* CORE FIFO of Sensor Results */
kevin1990 2:625a45555a85 267 #define REG_CORE_LUT_SELECT_RESET 0x00000000 /* Reset Value for LUT_Select */
kevin1990 2:625a45555a85 268 #define REG_CORE_LUT_SELECT 0x00000060 /* CORE Pointer to Custom Lookup Table or Polynomial */
kevin1990 2:625a45555a85 269 #define REG_CORE_LUT_OFFSET_RESET 0x00000000 /* Reset Value for LUT_Offset */
kevin1990 2:625a45555a85 270 #define REG_CORE_LUT_OFFSET 0x00000062 /* CORE Offset into Selected LUT */
kevin1990 2:625a45555a85 271 #define REG_CORE_LUT_DATA_RESET 0x00000000 /* Reset Value for LUT_Data */
kevin1990 2:625a45555a85 272 #define REG_CORE_LUT_DATA 0x00000064 /* CORE Data to Read/Write from Addressed LUT Entry */
kevin1990 2:625a45555a85 273 #define REG_CORE_CAL_SELECT_RESET 0x00000000 /* Reset Value for CAL_Select */
kevin1990 2:625a45555a85 274 #define REG_CORE_CAL_SELECT 0x00000068 /* CORE Pointer to Calibration Values */
kevin1990 2:625a45555a85 275 #define REG_CORE_CAL_OFFSET_RESET 0x00000000 /* Reset Value for CAL_Offset */
kevin1990 2:625a45555a85 276 #define REG_CORE_CAL_OFFSET 0x0000006A /* CORE Offset into Selected Calibration Values */
kevin1990 2:625a45555a85 277 #define REG_CORE_CAL_DATA_RESET 0x00000000 /* Reset Value for CAL_Data */
kevin1990 2:625a45555a85 278 #define REG_CORE_CAL_DATA 0x0000006C /* CORE Data to Read/Write from Addressed Calibration Values */
kevin1990 2:625a45555a85 279 #define REG_CORE_REVISION_RESET 0x00000000 /* Reset Value for Revision */
kevin1990 2:625a45555a85 280 #define REG_CORE_REVISION 0x0000007C /* CORE Hardware, Firmware Revision */
kevin1990 2:625a45555a85 281 #define REG_CORE_CHANNEL_COUNTn_RESET 0x00000000 /* Reset Value for Channel_Count[n] */
kevin1990 2:625a45555a85 282 #define REG_CORE_CHANNEL_COUNT0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT0 */
kevin1990 2:625a45555a85 283 #define REG_CORE_CHANNEL_COUNT1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT1 */
kevin1990 2:625a45555a85 284 #define REG_CORE_CHANNEL_COUNT2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT2 */
kevin1990 2:625a45555a85 285 #define REG_CORE_CHANNEL_COUNT3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT3 */
kevin1990 2:625a45555a85 286 #define REG_CORE_CHANNEL_COUNT4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT4 */
kevin1990 2:625a45555a85 287 #define REG_CORE_CHANNEL_COUNT5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT5 */
kevin1990 2:625a45555a85 288 #define REG_CORE_CHANNEL_COUNT6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT6 */
kevin1990 2:625a45555a85 289 #define REG_CORE_CHANNEL_COUNT7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT7 */
kevin1990 2:625a45555a85 290 #define REG_CORE_CHANNEL_COUNT8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT8 */
kevin1990 2:625a45555a85 291 #define REG_CORE_CHANNEL_COUNT9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT9 */
kevin1990 2:625a45555a85 292 #define REG_CORE_CHANNEL_COUNT10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT10 */
kevin1990 2:625a45555a85 293 #define REG_CORE_CHANNEL_COUNT0 0x00000090 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 294 #define REG_CORE_CHANNEL_COUNT1 0x000000D0 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 295 #define REG_CORE_CHANNEL_COUNT2 0x00000110 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 296 #define REG_CORE_CHANNEL_COUNT3 0x00000150 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 297 #define REG_CORE_CHANNEL_COUNT4 0x00000190 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 298 #define REG_CORE_CHANNEL_COUNT5 0x000001D0 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 299 #define REG_CORE_CHANNEL_COUNT6 0x00000210 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 300 #define REG_CORE_CHANNEL_COUNT7 0x00000250 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 301 #define REG_CORE_CHANNEL_COUNT8 0x00000290 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 302 #define REG_CORE_CHANNEL_COUNT9 0x000002D0 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 303 #define REG_CORE_CHANNEL_COUNT10 0x00000310 /* CORE Number of Channel Occurrences per Measurement Cycle */
kevin1990 2:625a45555a85 304 #define REG_CORE_CHANNEL_COUNTn(i) (REG_CORE_CHANNEL_COUNT0 + ((i) * 64))
kevin1990 2:625a45555a85 305 #define REG_CORE_CHANNEL_COUNTn_COUNT 11
kevin1990 2:625a45555a85 306 #define REG_CORE_SENSOR_TYPEn_RESET 0x00000000 /* Reset Value for Sensor_Type[n] */
kevin1990 2:625a45555a85 307 #define REG_CORE_SENSOR_TYPE0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE0 */
kevin1990 2:625a45555a85 308 #define REG_CORE_SENSOR_TYPE1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE1 */
kevin1990 2:625a45555a85 309 #define REG_CORE_SENSOR_TYPE2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE2 */
kevin1990 2:625a45555a85 310 #define REG_CORE_SENSOR_TYPE3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE3 */
kevin1990 2:625a45555a85 311 #define REG_CORE_SENSOR_TYPE4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE4 */
kevin1990 2:625a45555a85 312 #define REG_CORE_SENSOR_TYPE5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE5 */
kevin1990 2:625a45555a85 313 #define REG_CORE_SENSOR_TYPE6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE6 */
kevin1990 2:625a45555a85 314 #define REG_CORE_SENSOR_TYPE7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE7 */
kevin1990 2:625a45555a85 315 #define REG_CORE_SENSOR_TYPE8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE8 */
kevin1990 2:625a45555a85 316 #define REG_CORE_SENSOR_TYPE9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE9 */
kevin1990 2:625a45555a85 317 #define REG_CORE_SENSOR_TYPE10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE10 */
kevin1990 2:625a45555a85 318 #define REG_CORE_SENSOR_TYPE0 0x00000092 /* CORE Sensor Select */
kevin1990 2:625a45555a85 319 #define REG_CORE_SENSOR_TYPE1 0x000000D2 /* CORE Sensor Select */
kevin1990 2:625a45555a85 320 #define REG_CORE_SENSOR_TYPE2 0x00000112 /* CORE Sensor Select */
kevin1990 2:625a45555a85 321 #define REG_CORE_SENSOR_TYPE3 0x00000152 /* CORE Sensor Select */
kevin1990 2:625a45555a85 322 #define REG_CORE_SENSOR_TYPE4 0x00000192 /* CORE Sensor Select */
kevin1990 2:625a45555a85 323 #define REG_CORE_SENSOR_TYPE5 0x000001D2 /* CORE Sensor Select */
kevin1990 2:625a45555a85 324 #define REG_CORE_SENSOR_TYPE6 0x00000212 /* CORE Sensor Select */
kevin1990 2:625a45555a85 325 #define REG_CORE_SENSOR_TYPE7 0x00000252 /* CORE Sensor Select */
kevin1990 2:625a45555a85 326 #define REG_CORE_SENSOR_TYPE8 0x00000292 /* CORE Sensor Select */
kevin1990 2:625a45555a85 327 #define REG_CORE_SENSOR_TYPE9 0x000002D2 /* CORE Sensor Select */
kevin1990 2:625a45555a85 328 #define REG_CORE_SENSOR_TYPE10 0x00000312 /* CORE Sensor Select */
kevin1990 2:625a45555a85 329 #define REG_CORE_SENSOR_TYPEn(i) (REG_CORE_SENSOR_TYPE0 + ((i) * 64))
kevin1990 2:625a45555a85 330 #define REG_CORE_SENSOR_TYPEn_COUNT 11
kevin1990 2:625a45555a85 331 #define REG_CORE_SENSOR_DETAILSn_RESET 0x0000FF00 /* Reset Value for Sensor_Details[n] */
kevin1990 2:625a45555a85 332 #define REG_CORE_SENSOR_DETAILS0_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS0 */
kevin1990 2:625a45555a85 333 #define REG_CORE_SENSOR_DETAILS1_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS1 */
kevin1990 2:625a45555a85 334 #define REG_CORE_SENSOR_DETAILS2_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS2 */
kevin1990 2:625a45555a85 335 #define REG_CORE_SENSOR_DETAILS3_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS3 */
kevin1990 2:625a45555a85 336 #define REG_CORE_SENSOR_DETAILS4_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS4 */
kevin1990 2:625a45555a85 337 #define REG_CORE_SENSOR_DETAILS5_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS5 */
kevin1990 2:625a45555a85 338 #define REG_CORE_SENSOR_DETAILS6_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS6 */
kevin1990 2:625a45555a85 339 #define REG_CORE_SENSOR_DETAILS7_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS7 */
kevin1990 2:625a45555a85 340 #define REG_CORE_SENSOR_DETAILS8_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS8 */
kevin1990 2:625a45555a85 341 #define REG_CORE_SENSOR_DETAILS9_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS9 */
kevin1990 2:625a45555a85 342 #define REG_CORE_SENSOR_DETAILS10_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS10 */
kevin1990 2:625a45555a85 343 #define REG_CORE_SENSOR_DETAILS0 0x00000094 /* CORE Sensor Details */
kevin1990 2:625a45555a85 344 #define REG_CORE_SENSOR_DETAILS1 0x000000D4 /* CORE Sensor Details */
kevin1990 2:625a45555a85 345 #define REG_CORE_SENSOR_DETAILS2 0x00000114 /* CORE Sensor Details */
kevin1990 2:625a45555a85 346 #define REG_CORE_SENSOR_DETAILS3 0x00000154 /* CORE Sensor Details */
kevin1990 2:625a45555a85 347 #define REG_CORE_SENSOR_DETAILS4 0x00000194 /* CORE Sensor Details */
kevin1990 2:625a45555a85 348 #define REG_CORE_SENSOR_DETAILS5 0x000001D4 /* CORE Sensor Details */
kevin1990 2:625a45555a85 349 #define REG_CORE_SENSOR_DETAILS6 0x00000214 /* CORE Sensor Details */
kevin1990 2:625a45555a85 350 #define REG_CORE_SENSOR_DETAILS7 0x00000254 /* CORE Sensor Details */
kevin1990 2:625a45555a85 351 #define REG_CORE_SENSOR_DETAILS8 0x00000294 /* CORE Sensor Details */
kevin1990 2:625a45555a85 352 #define REG_CORE_SENSOR_DETAILS9 0x000002D4 /* CORE Sensor Details */
kevin1990 2:625a45555a85 353 #define REG_CORE_SENSOR_DETAILS10 0x00000314 /* CORE Sensor Details */
kevin1990 2:625a45555a85 354 #define REG_CORE_SENSOR_DETAILSn(i) (REG_CORE_SENSOR_DETAILS0 + ((i) * 64))
kevin1990 2:625a45555a85 355 #define REG_CORE_SENSOR_DETAILSn_COUNT 11
kevin1990 2:625a45555a85 356 #define REG_CORE_CHANNEL_EXCITATIONn_RESET 0x00000000 /* Reset Value for Channel_Excitation[n] */
kevin1990 2:625a45555a85 357 #define REG_CORE_CHANNEL_EXCITATION0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION0 */
kevin1990 2:625a45555a85 358 #define REG_CORE_CHANNEL_EXCITATION1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION1 */
kevin1990 2:625a45555a85 359 #define REG_CORE_CHANNEL_EXCITATION2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION2 */
kevin1990 2:625a45555a85 360 #define REG_CORE_CHANNEL_EXCITATION3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION3 */
kevin1990 2:625a45555a85 361 #define REG_CORE_CHANNEL_EXCITATION4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION4 */
kevin1990 2:625a45555a85 362 #define REG_CORE_CHANNEL_EXCITATION5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION5 */
kevin1990 2:625a45555a85 363 #define REG_CORE_CHANNEL_EXCITATION6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION6 */
kevin1990 2:625a45555a85 364 #define REG_CORE_CHANNEL_EXCITATION7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION7 */
kevin1990 2:625a45555a85 365 #define REG_CORE_CHANNEL_EXCITATION8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION8 */
kevin1990 2:625a45555a85 366 #define REG_CORE_CHANNEL_EXCITATION9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION9 */
kevin1990 2:625a45555a85 367 #define REG_CORE_CHANNEL_EXCITATION10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION10 */
kevin1990 2:625a45555a85 368 #define REG_CORE_CHANNEL_EXCITATION0 0x00000098 /* CORE Excitation Current */
kevin1990 2:625a45555a85 369 #define REG_CORE_CHANNEL_EXCITATION1 0x000000D8 /* CORE Excitation Current */
kevin1990 2:625a45555a85 370 #define REG_CORE_CHANNEL_EXCITATION2 0x00000118 /* CORE Excitation Current */
kevin1990 2:625a45555a85 371 #define REG_CORE_CHANNEL_EXCITATION3 0x00000158 /* CORE Excitation Current */
kevin1990 2:625a45555a85 372 #define REG_CORE_CHANNEL_EXCITATION4 0x00000198 /* CORE Excitation Current */
kevin1990 2:625a45555a85 373 #define REG_CORE_CHANNEL_EXCITATION5 0x000001D8 /* CORE Excitation Current */
kevin1990 2:625a45555a85 374 #define REG_CORE_CHANNEL_EXCITATION6 0x00000218 /* CORE Excitation Current */
kevin1990 2:625a45555a85 375 #define REG_CORE_CHANNEL_EXCITATION7 0x00000258 /* CORE Excitation Current */
kevin1990 2:625a45555a85 376 #define REG_CORE_CHANNEL_EXCITATION8 0x00000298 /* CORE Excitation Current */
kevin1990 2:625a45555a85 377 #define REG_CORE_CHANNEL_EXCITATION9 0x000002D8 /* CORE Excitation Current */
kevin1990 2:625a45555a85 378 #define REG_CORE_CHANNEL_EXCITATION10 0x00000318 /* CORE Excitation Current */
kevin1990 2:625a45555a85 379 #define REG_CORE_CHANNEL_EXCITATIONn(i) (REG_CORE_CHANNEL_EXCITATION0 + ((i) * 64))
kevin1990 2:625a45555a85 380 #define REG_CORE_CHANNEL_EXCITATIONn_COUNT 11
kevin1990 2:625a45555a85 381 #define REG_CORE_DIGITAL_SENSOR_CODINGn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Coding[n] */
kevin1990 2:625a45555a85 382 #define REG_CORE_DIGITAL_SENSOR_CODING0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING0 */
kevin1990 2:625a45555a85 383 #define REG_CORE_DIGITAL_SENSOR_CODING1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING1 */
kevin1990 2:625a45555a85 384 #define REG_CORE_DIGITAL_SENSOR_CODING2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING2 */
kevin1990 2:625a45555a85 385 #define REG_CORE_DIGITAL_SENSOR_CODING3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING3 */
kevin1990 2:625a45555a85 386 #define REG_CORE_DIGITAL_SENSOR_CODING4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING4 */
kevin1990 2:625a45555a85 387 #define REG_CORE_DIGITAL_SENSOR_CODING5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING5 */
kevin1990 2:625a45555a85 388 #define REG_CORE_DIGITAL_SENSOR_CODING6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING6 */
kevin1990 2:625a45555a85 389 #define REG_CORE_DIGITAL_SENSOR_CODING7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING7 */
kevin1990 2:625a45555a85 390 #define REG_CORE_DIGITAL_SENSOR_CODING8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING8 */
kevin1990 2:625a45555a85 391 #define REG_CORE_DIGITAL_SENSOR_CODING9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING9 */
kevin1990 2:625a45555a85 392 #define REG_CORE_DIGITAL_SENSOR_CODING10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING10 */
kevin1990 2:625a45555a85 393 #define REG_CORE_DIGITAL_SENSOR_CODING0 0x0000009A /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 394 #define REG_CORE_DIGITAL_SENSOR_CODING1 0x000000DA /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 395 #define REG_CORE_DIGITAL_SENSOR_CODING2 0x0000011A /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 396 #define REG_CORE_DIGITAL_SENSOR_CODING3 0x0000015A /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 397 #define REG_CORE_DIGITAL_SENSOR_CODING4 0x0000019A /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 398 #define REG_CORE_DIGITAL_SENSOR_CODING5 0x000001DA /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 399 #define REG_CORE_DIGITAL_SENSOR_CODING6 0x0000021A /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 400 #define REG_CORE_DIGITAL_SENSOR_CODING7 0x0000025A /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 401 #define REG_CORE_DIGITAL_SENSOR_CODING8 0x0000029A /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 402 #define REG_CORE_DIGITAL_SENSOR_CODING9 0x000002DA /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 403 #define REG_CORE_DIGITAL_SENSOR_CODING10 0x0000031A /* CORE Digital Sensor Data Coding */
kevin1990 2:625a45555a85 404 #define REG_CORE_DIGITAL_SENSOR_CODINGn(i) (REG_CORE_DIGITAL_SENSOR_CODING0 + ((i) * 64))
kevin1990 2:625a45555a85 405 #define REG_CORE_DIGITAL_SENSOR_CODINGn_COUNT 11
kevin1990 2:625a45555a85 406 #define REG_CORE_FILTER_SELECTn_RESET 0x00000000 /* Reset Value for Filter_Select[n] */
kevin1990 2:625a45555a85 407 #define REG_CORE_FILTER_SELECT0_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT0 */
kevin1990 2:625a45555a85 408 #define REG_CORE_FILTER_SELECT1_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT1 */
kevin1990 2:625a45555a85 409 #define REG_CORE_FILTER_SELECT2_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT2 */
kevin1990 2:625a45555a85 410 #define REG_CORE_FILTER_SELECT3_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT3 */
kevin1990 2:625a45555a85 411 #define REG_CORE_FILTER_SELECT4_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT4 */
kevin1990 2:625a45555a85 412 #define REG_CORE_FILTER_SELECT5_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT5 */
kevin1990 2:625a45555a85 413 #define REG_CORE_FILTER_SELECT6_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT6 */
kevin1990 2:625a45555a85 414 #define REG_CORE_FILTER_SELECT7_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT7 */
kevin1990 2:625a45555a85 415 #define REG_CORE_FILTER_SELECT8_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT8 */
kevin1990 2:625a45555a85 416 #define REG_CORE_FILTER_SELECT9_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT9 */
kevin1990 2:625a45555a85 417 #define REG_CORE_FILTER_SELECT10_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT10 */
kevin1990 2:625a45555a85 418 #define REG_CORE_FILTER_SELECT0 0x0000009C /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 419 #define REG_CORE_FILTER_SELECT1 0x000000DC /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 420 #define REG_CORE_FILTER_SELECT2 0x0000011C /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 421 #define REG_CORE_FILTER_SELECT3 0x0000015C /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 422 #define REG_CORE_FILTER_SELECT4 0x0000019C /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 423 #define REG_CORE_FILTER_SELECT5 0x000001DC /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 424 #define REG_CORE_FILTER_SELECT6 0x0000021C /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 425 #define REG_CORE_FILTER_SELECT7 0x0000025C /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 426 #define REG_CORE_FILTER_SELECT8 0x0000029C /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 427 #define REG_CORE_FILTER_SELECT9 0x000002DC /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 428 #define REG_CORE_FILTER_SELECT10 0x0000031C /* CORE ADC Digital Filter Selection */
kevin1990 2:625a45555a85 429 #define REG_CORE_FILTER_SELECTn(i) (REG_CORE_FILTER_SELECT0 + ((i) * 64))
kevin1990 2:625a45555a85 430 #define REG_CORE_FILTER_SELECTn_COUNT 11
kevin1990 2:625a45555a85 431 #define REG_CORE_SETTLING_TIMEn_RESET 0x00000000 /* Reset Value for Settling_Time[n] */
kevin1990 2:625a45555a85 432 #define REG_CORE_SETTLING_TIME0_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME0 */
kevin1990 2:625a45555a85 433 #define REG_CORE_SETTLING_TIME1_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME1 */
kevin1990 2:625a45555a85 434 #define REG_CORE_SETTLING_TIME2_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME2 */
kevin1990 2:625a45555a85 435 #define REG_CORE_SETTLING_TIME3_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME3 */
kevin1990 2:625a45555a85 436 #define REG_CORE_SETTLING_TIME4_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME4 */
kevin1990 2:625a45555a85 437 #define REG_CORE_SETTLING_TIME5_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME5 */
kevin1990 2:625a45555a85 438 #define REG_CORE_SETTLING_TIME6_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME6 */
kevin1990 2:625a45555a85 439 #define REG_CORE_SETTLING_TIME7_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME7 */
kevin1990 2:625a45555a85 440 #define REG_CORE_SETTLING_TIME8_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME8 */
kevin1990 2:625a45555a85 441 #define REG_CORE_SETTLING_TIME9_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME9 */
kevin1990 2:625a45555a85 442 #define REG_CORE_SETTLING_TIME10_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME10 */
kevin1990 2:625a45555a85 443 #define REG_CORE_SETTLING_TIME0 0x000000A0 /* CORE Settling Time */
kevin1990 2:625a45555a85 444 #define REG_CORE_SETTLING_TIME1 0x000000E0 /* CORE Settling Time */
kevin1990 2:625a45555a85 445 #define REG_CORE_SETTLING_TIME2 0x00000120 /* CORE Settling Time */
kevin1990 2:625a45555a85 446 #define REG_CORE_SETTLING_TIME3 0x00000160 /* CORE Settling Time */
kevin1990 2:625a45555a85 447 #define REG_CORE_SETTLING_TIME4 0x000001A0 /* CORE Settling Time */
kevin1990 2:625a45555a85 448 #define REG_CORE_SETTLING_TIME5 0x000001E0 /* CORE Settling Time */
kevin1990 2:625a45555a85 449 #define REG_CORE_SETTLING_TIME6 0x00000220 /* CORE Settling Time */
kevin1990 2:625a45555a85 450 #define REG_CORE_SETTLING_TIME7 0x00000260 /* CORE Settling Time */
kevin1990 2:625a45555a85 451 #define REG_CORE_SETTLING_TIME8 0x000002A0 /* CORE Settling Time */
kevin1990 2:625a45555a85 452 #define REG_CORE_SETTLING_TIME9 0x000002E0 /* CORE Settling Time */
kevin1990 2:625a45555a85 453 #define REG_CORE_SETTLING_TIME10 0x00000320 /* CORE Settling Time */
kevin1990 2:625a45555a85 454 #define REG_CORE_SETTLING_TIMEn(i) (REG_CORE_SETTLING_TIME0 + ((i) * 64))
kevin1990 2:625a45555a85 455 #define REG_CORE_SETTLING_TIMEn_COUNT 11
kevin1990 2:625a45555a85 456 #define REG_CORE_HIGH_THRESHOLD_LIMITn_RESET 0x00000000 /* Reset Value for High_Threshold_Limit[n] */
kevin1990 2:625a45555a85 457 #define REG_CORE_HIGH_THRESHOLD_LIMIT0_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT0 */
kevin1990 2:625a45555a85 458 #define REG_CORE_HIGH_THRESHOLD_LIMIT1_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT1 */
kevin1990 2:625a45555a85 459 #define REG_CORE_HIGH_THRESHOLD_LIMIT2_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT2 */
kevin1990 2:625a45555a85 460 #define REG_CORE_HIGH_THRESHOLD_LIMIT3_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT3 */
kevin1990 2:625a45555a85 461 #define REG_CORE_HIGH_THRESHOLD_LIMIT4_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT4 */
kevin1990 2:625a45555a85 462 #define REG_CORE_HIGH_THRESHOLD_LIMIT5_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT5 */
kevin1990 2:625a45555a85 463 #define REG_CORE_HIGH_THRESHOLD_LIMIT6_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT6 */
kevin1990 2:625a45555a85 464 #define REG_CORE_HIGH_THRESHOLD_LIMIT7_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT7 */
kevin1990 2:625a45555a85 465 #define REG_CORE_HIGH_THRESHOLD_LIMIT8_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT8 */
kevin1990 2:625a45555a85 466 #define REG_CORE_HIGH_THRESHOLD_LIMIT9_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT9 */
kevin1990 2:625a45555a85 467 #define REG_CORE_HIGH_THRESHOLD_LIMIT10_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT10 */
kevin1990 2:625a45555a85 468 #define REG_CORE_HIGH_THRESHOLD_LIMIT11_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT11 */
kevin1990 2:625a45555a85 469 #define REG_CORE_HIGH_THRESHOLD_LIMIT12_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT12 */
kevin1990 2:625a45555a85 470 #define REG_CORE_HIGH_THRESHOLD_LIMIT0 0x000000A4 /* CORE High Threshold */
kevin1990 2:625a45555a85 471 #define REG_CORE_HIGH_THRESHOLD_LIMIT1 0x000000E4 /* CORE High Threshold */
kevin1990 2:625a45555a85 472 #define REG_CORE_HIGH_THRESHOLD_LIMIT2 0x00000124 /* CORE High Threshold */
kevin1990 2:625a45555a85 473 #define REG_CORE_HIGH_THRESHOLD_LIMIT3 0x00000164 /* CORE High Threshold */
kevin1990 2:625a45555a85 474 #define REG_CORE_HIGH_THRESHOLD_LIMIT4 0x000001A4 /* CORE High Threshold */
kevin1990 2:625a45555a85 475 #define REG_CORE_HIGH_THRESHOLD_LIMIT5 0x000001E4 /* CORE High Threshold */
kevin1990 2:625a45555a85 476 #define REG_CORE_HIGH_THRESHOLD_LIMIT6 0x00000224 /* CORE High Threshold */
kevin1990 2:625a45555a85 477 #define REG_CORE_HIGH_THRESHOLD_LIMIT7 0x00000264 /* CORE High Threshold */
kevin1990 2:625a45555a85 478 #define REG_CORE_HIGH_THRESHOLD_LIMIT8 0x000002A4 /* CORE High Threshold */
kevin1990 2:625a45555a85 479 #define REG_CORE_HIGH_THRESHOLD_LIMIT9 0x000002E4 /* CORE High Threshold */
kevin1990 2:625a45555a85 480 #define REG_CORE_HIGH_THRESHOLD_LIMIT10 0x00000324 /* CORE High Threshold */
kevin1990 2:625a45555a85 481 #define REG_CORE_HIGH_THRESHOLD_LIMIT11 0x00000364 /* CORE High Threshold */
kevin1990 2:625a45555a85 482 #define REG_CORE_HIGH_THRESHOLD_LIMIT12 0x000003A4 /* CORE High Threshold */
kevin1990 2:625a45555a85 483 #define REG_CORE_HIGH_THRESHOLD_LIMITn(i) (REG_CORE_HIGH_THRESHOLD_LIMIT0 + ((i) * 64))
kevin1990 2:625a45555a85 484 #define REG_CORE_HIGH_THRESHOLD_LIMITn_COUNT 13
kevin1990 2:625a45555a85 485 #define REG_CORE_LOW_THRESHOLD_LIMITn_RESET 0x00000000 /* Reset Value for Low_Threshold_Limit[n] */
kevin1990 2:625a45555a85 486 #define REG_CORE_LOW_THRESHOLD_LIMIT0_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT0 */
kevin1990 2:625a45555a85 487 #define REG_CORE_LOW_THRESHOLD_LIMIT1_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT1 */
kevin1990 2:625a45555a85 488 #define REG_CORE_LOW_THRESHOLD_LIMIT2_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT2 */
kevin1990 2:625a45555a85 489 #define REG_CORE_LOW_THRESHOLD_LIMIT3_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT3 */
kevin1990 2:625a45555a85 490 #define REG_CORE_LOW_THRESHOLD_LIMIT4_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT4 */
kevin1990 2:625a45555a85 491 #define REG_CORE_LOW_THRESHOLD_LIMIT5_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT5 */
kevin1990 2:625a45555a85 492 #define REG_CORE_LOW_THRESHOLD_LIMIT6_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT6 */
kevin1990 2:625a45555a85 493 #define REG_CORE_LOW_THRESHOLD_LIMIT7_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT7 */
kevin1990 2:625a45555a85 494 #define REG_CORE_LOW_THRESHOLD_LIMIT8_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT8 */
kevin1990 2:625a45555a85 495 #define REG_CORE_LOW_THRESHOLD_LIMIT9_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT9 */
kevin1990 2:625a45555a85 496 #define REG_CORE_LOW_THRESHOLD_LIMIT10_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT10 */
kevin1990 2:625a45555a85 497 #define REG_CORE_LOW_THRESHOLD_LIMIT11_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT11 */
kevin1990 2:625a45555a85 498 #define REG_CORE_LOW_THRESHOLD_LIMIT12_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT12 */
kevin1990 2:625a45555a85 499 #define REG_CORE_LOW_THRESHOLD_LIMIT0 0x000000A8 /* CORE Low Threshold */
kevin1990 2:625a45555a85 500 #define REG_CORE_LOW_THRESHOLD_LIMIT1 0x000000E8 /* CORE Low Threshold */
kevin1990 2:625a45555a85 501 #define REG_CORE_LOW_THRESHOLD_LIMIT2 0x00000128 /* CORE Low Threshold */
kevin1990 2:625a45555a85 502 #define REG_CORE_LOW_THRESHOLD_LIMIT3 0x00000168 /* CORE Low Threshold */
kevin1990 2:625a45555a85 503 #define REG_CORE_LOW_THRESHOLD_LIMIT4 0x000001A8 /* CORE Low Threshold */
kevin1990 2:625a45555a85 504 #define REG_CORE_LOW_THRESHOLD_LIMIT5 0x000001E8 /* CORE Low Threshold */
kevin1990 2:625a45555a85 505 #define REG_CORE_LOW_THRESHOLD_LIMIT6 0x00000228 /* CORE Low Threshold */
kevin1990 2:625a45555a85 506 #define REG_CORE_LOW_THRESHOLD_LIMIT7 0x00000268 /* CORE Low Threshold */
kevin1990 2:625a45555a85 507 #define REG_CORE_LOW_THRESHOLD_LIMIT8 0x000002A8 /* CORE Low Threshold */
kevin1990 2:625a45555a85 508 #define REG_CORE_LOW_THRESHOLD_LIMIT9 0x000002E8 /* CORE Low Threshold */
kevin1990 2:625a45555a85 509 #define REG_CORE_LOW_THRESHOLD_LIMIT10 0x00000328 /* CORE Low Threshold */
kevin1990 2:625a45555a85 510 #define REG_CORE_LOW_THRESHOLD_LIMIT11 0x00000368 /* CORE Low Threshold */
kevin1990 2:625a45555a85 511 #define REG_CORE_LOW_THRESHOLD_LIMIT12 0x000003A8 /* CORE Low Threshold */
kevin1990 2:625a45555a85 512 #define REG_CORE_LOW_THRESHOLD_LIMITn(i) (REG_CORE_LOW_THRESHOLD_LIMIT0 + ((i) * 64))
kevin1990 2:625a45555a85 513 #define REG_CORE_LOW_THRESHOLD_LIMITn_COUNT 13
kevin1990 2:625a45555a85 514 #define REG_CORE_DIGITAL_SENSOR_ADDRESSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Address[n] */
kevin1990 2:625a45555a85 515 #define REG_CORE_DIGITAL_SENSOR_ADDRESS0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS0 */
kevin1990 2:625a45555a85 516 #define REG_CORE_DIGITAL_SENSOR_ADDRESS1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS1 */
kevin1990 2:625a45555a85 517 #define REG_CORE_DIGITAL_SENSOR_ADDRESS2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS2 */
kevin1990 2:625a45555a85 518 #define REG_CORE_DIGITAL_SENSOR_ADDRESS3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS3 */
kevin1990 2:625a45555a85 519 #define REG_CORE_DIGITAL_SENSOR_ADDRESS4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS4 */
kevin1990 2:625a45555a85 520 #define REG_CORE_DIGITAL_SENSOR_ADDRESS5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS5 */
kevin1990 2:625a45555a85 521 #define REG_CORE_DIGITAL_SENSOR_ADDRESS6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS6 */
kevin1990 2:625a45555a85 522 #define REG_CORE_DIGITAL_SENSOR_ADDRESS7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS7 */
kevin1990 2:625a45555a85 523 #define REG_CORE_DIGITAL_SENSOR_ADDRESS8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS8 */
kevin1990 2:625a45555a85 524 #define REG_CORE_DIGITAL_SENSOR_ADDRESS9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS9 */
kevin1990 2:625a45555a85 525 #define REG_CORE_DIGITAL_SENSOR_ADDRESS10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS10 */
kevin1990 2:625a45555a85 526 #define REG_CORE_DIGITAL_SENSOR_ADDRESS0 0x000000AC /* CORE Sensor Address */
kevin1990 2:625a45555a85 527 #define REG_CORE_DIGITAL_SENSOR_ADDRESS1 0x000000EC /* CORE Sensor Address */
kevin1990 2:625a45555a85 528 #define REG_CORE_DIGITAL_SENSOR_ADDRESS2 0x0000012C /* CORE Sensor Address */
kevin1990 2:625a45555a85 529 #define REG_CORE_DIGITAL_SENSOR_ADDRESS3 0x0000016C /* CORE Sensor Address */
kevin1990 2:625a45555a85 530 #define REG_CORE_DIGITAL_SENSOR_ADDRESS4 0x000001AC /* CORE Sensor Address */
kevin1990 2:625a45555a85 531 #define REG_CORE_DIGITAL_SENSOR_ADDRESS5 0x000001EC /* CORE Sensor Address */
kevin1990 2:625a45555a85 532 #define REG_CORE_DIGITAL_SENSOR_ADDRESS6 0x0000022C /* CORE Sensor Address */
kevin1990 2:625a45555a85 533 #define REG_CORE_DIGITAL_SENSOR_ADDRESS7 0x0000026C /* CORE Sensor Address */
kevin1990 2:625a45555a85 534 #define REG_CORE_DIGITAL_SENSOR_ADDRESS8 0x000002AC /* CORE Sensor Address */
kevin1990 2:625a45555a85 535 #define REG_CORE_DIGITAL_SENSOR_ADDRESS9 0x000002EC /* CORE Sensor Address */
kevin1990 2:625a45555a85 536 #define REG_CORE_DIGITAL_SENSOR_ADDRESS10 0x0000032C /* CORE Sensor Address */
kevin1990 2:625a45555a85 537 #define REG_CORE_DIGITAL_SENSOR_ADDRESSn(i) (REG_CORE_DIGITAL_SENSOR_ADDRESS0 + ((i) * 64))
kevin1990 2:625a45555a85 538 #define REG_CORE_DIGITAL_SENSOR_ADDRESSn_COUNT 11
kevin1990 2:625a45555a85 539 #define REG_CORE_DIGITAL_SENSOR_COMMAND1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command1[n] */
kevin1990 2:625a45555a85 540 #define REG_CORE_DIGITAL_SENSOR_COMMAND10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND10 */
kevin1990 2:625a45555a85 541 #define REG_CORE_DIGITAL_SENSOR_COMMAND11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND11 */
kevin1990 2:625a45555a85 542 #define REG_CORE_DIGITAL_SENSOR_COMMAND12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND12 */
kevin1990 2:625a45555a85 543 #define REG_CORE_DIGITAL_SENSOR_COMMAND13_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND13 */
kevin1990 2:625a45555a85 544 #define REG_CORE_DIGITAL_SENSOR_COMMAND14_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND14 */
kevin1990 2:625a45555a85 545 #define REG_CORE_DIGITAL_SENSOR_COMMAND15_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND15 */
kevin1990 2:625a45555a85 546 #define REG_CORE_DIGITAL_SENSOR_COMMAND16_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND16 */
kevin1990 2:625a45555a85 547 #define REG_CORE_DIGITAL_SENSOR_COMMAND17_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND17 */
kevin1990 2:625a45555a85 548 #define REG_CORE_DIGITAL_SENSOR_COMMAND18_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND18 */
kevin1990 2:625a45555a85 549 #define REG_CORE_DIGITAL_SENSOR_COMMAND19_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND19 */
kevin1990 2:625a45555a85 550 #define REG_CORE_DIGITAL_SENSOR_COMMAND110_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND110 */
kevin1990 2:625a45555a85 551 #define REG_CORE_DIGITAL_SENSOR_COMMAND10 0x000000AD /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 552 #define REG_CORE_DIGITAL_SENSOR_COMMAND11 0x000000ED /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 553 #define REG_CORE_DIGITAL_SENSOR_COMMAND12 0x0000012D /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 554 #define REG_CORE_DIGITAL_SENSOR_COMMAND13 0x0000016D /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 555 #define REG_CORE_DIGITAL_SENSOR_COMMAND14 0x000001AD /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 556 #define REG_CORE_DIGITAL_SENSOR_COMMAND15 0x000001ED /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 557 #define REG_CORE_DIGITAL_SENSOR_COMMAND16 0x0000022D /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 558 #define REG_CORE_DIGITAL_SENSOR_COMMAND17 0x0000026D /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 559 #define REG_CORE_DIGITAL_SENSOR_COMMAND18 0x000002AD /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 560 #define REG_CORE_DIGITAL_SENSOR_COMMAND19 0x000002ED /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 561 #define REG_CORE_DIGITAL_SENSOR_COMMAND110 0x0000032D /* CORE Sensor Command1 */
kevin1990 2:625a45555a85 562 #define REG_CORE_DIGITAL_SENSOR_COMMAND1n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND10 + ((i) * 64))
kevin1990 2:625a45555a85 563 #define REG_CORE_DIGITAL_SENSOR_COMMAND1n_COUNT 11
kevin1990 2:625a45555a85 564 #define REG_CORE_DIGITAL_SENSOR_COMMAND2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command2[n] */
kevin1990 2:625a45555a85 565 #define REG_CORE_DIGITAL_SENSOR_COMMAND20_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND20 */
kevin1990 2:625a45555a85 566 #define REG_CORE_DIGITAL_SENSOR_COMMAND21_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND21 */
kevin1990 2:625a45555a85 567 #define REG_CORE_DIGITAL_SENSOR_COMMAND22_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND22 */
kevin1990 2:625a45555a85 568 #define REG_CORE_DIGITAL_SENSOR_COMMAND23_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND23 */
kevin1990 2:625a45555a85 569 #define REG_CORE_DIGITAL_SENSOR_COMMAND24_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND24 */
kevin1990 2:625a45555a85 570 #define REG_CORE_DIGITAL_SENSOR_COMMAND25_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND25 */
kevin1990 2:625a45555a85 571 #define REG_CORE_DIGITAL_SENSOR_COMMAND26_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND26 */
kevin1990 2:625a45555a85 572 #define REG_CORE_DIGITAL_SENSOR_COMMAND27_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND27 */
kevin1990 2:625a45555a85 573 #define REG_CORE_DIGITAL_SENSOR_COMMAND28_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND28 */
kevin1990 2:625a45555a85 574 #define REG_CORE_DIGITAL_SENSOR_COMMAND29_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND29 */
kevin1990 2:625a45555a85 575 #define REG_CORE_DIGITAL_SENSOR_COMMAND210_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND210 */
kevin1990 2:625a45555a85 576 #define REG_CORE_DIGITAL_SENSOR_COMMAND20 0x000000AE /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 577 #define REG_CORE_DIGITAL_SENSOR_COMMAND21 0x000000EE /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 578 #define REG_CORE_DIGITAL_SENSOR_COMMAND22 0x0000012E /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 579 #define REG_CORE_DIGITAL_SENSOR_COMMAND23 0x0000016E /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 580 #define REG_CORE_DIGITAL_SENSOR_COMMAND24 0x000001AE /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 581 #define REG_CORE_DIGITAL_SENSOR_COMMAND25 0x000001EE /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 582 #define REG_CORE_DIGITAL_SENSOR_COMMAND26 0x0000022E /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 583 #define REG_CORE_DIGITAL_SENSOR_COMMAND27 0x0000026E /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 584 #define REG_CORE_DIGITAL_SENSOR_COMMAND28 0x000002AE /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 585 #define REG_CORE_DIGITAL_SENSOR_COMMAND29 0x000002EE /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 586 #define REG_CORE_DIGITAL_SENSOR_COMMAND210 0x0000032E /* CORE Sensor Command2 */
kevin1990 2:625a45555a85 587 #define REG_CORE_DIGITAL_SENSOR_COMMAND2n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND20 + ((i) * 64))
kevin1990 2:625a45555a85 588 #define REG_CORE_DIGITAL_SENSOR_COMMAND2n_COUNT 11
kevin1990 2:625a45555a85 589 #define REG_CORE_DIGITAL_SENSOR_COMMAND3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command3[n] */
kevin1990 2:625a45555a85 590 #define REG_CORE_DIGITAL_SENSOR_COMMAND30_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND30 */
kevin1990 2:625a45555a85 591 #define REG_CORE_DIGITAL_SENSOR_COMMAND31_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND31 */
kevin1990 2:625a45555a85 592 #define REG_CORE_DIGITAL_SENSOR_COMMAND32_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND32 */
kevin1990 2:625a45555a85 593 #define REG_CORE_DIGITAL_SENSOR_COMMAND33_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND33 */
kevin1990 2:625a45555a85 594 #define REG_CORE_DIGITAL_SENSOR_COMMAND34_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND34 */
kevin1990 2:625a45555a85 595 #define REG_CORE_DIGITAL_SENSOR_COMMAND35_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND35 */
kevin1990 2:625a45555a85 596 #define REG_CORE_DIGITAL_SENSOR_COMMAND36_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND36 */
kevin1990 2:625a45555a85 597 #define REG_CORE_DIGITAL_SENSOR_COMMAND37_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND37 */
kevin1990 2:625a45555a85 598 #define REG_CORE_DIGITAL_SENSOR_COMMAND38_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND38 */
kevin1990 2:625a45555a85 599 #define REG_CORE_DIGITAL_SENSOR_COMMAND39_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND39 */
kevin1990 2:625a45555a85 600 #define REG_CORE_DIGITAL_SENSOR_COMMAND310_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND310 */
kevin1990 2:625a45555a85 601 #define REG_CORE_DIGITAL_SENSOR_COMMAND30 0x000000AF /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 602 #define REG_CORE_DIGITAL_SENSOR_COMMAND31 0x000000EF /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 603 #define REG_CORE_DIGITAL_SENSOR_COMMAND32 0x0000012F /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 604 #define REG_CORE_DIGITAL_SENSOR_COMMAND33 0x0000016F /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 605 #define REG_CORE_DIGITAL_SENSOR_COMMAND34 0x000001AF /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 606 #define REG_CORE_DIGITAL_SENSOR_COMMAND35 0x000001EF /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 607 #define REG_CORE_DIGITAL_SENSOR_COMMAND36 0x0000022F /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 608 #define REG_CORE_DIGITAL_SENSOR_COMMAND37 0x0000026F /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 609 #define REG_CORE_DIGITAL_SENSOR_COMMAND38 0x000002AF /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 610 #define REG_CORE_DIGITAL_SENSOR_COMMAND39 0x000002EF /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 611 #define REG_CORE_DIGITAL_SENSOR_COMMAND310 0x0000032F /* CORE Sensor Command3 */
kevin1990 2:625a45555a85 612 #define REG_CORE_DIGITAL_SENSOR_COMMAND3n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND30 + ((i) * 64))
kevin1990 2:625a45555a85 613 #define REG_CORE_DIGITAL_SENSOR_COMMAND3n_COUNT 11
kevin1990 2:625a45555a85 614 #define REG_CORE_SENSOR_LUT_INDEX1n_RESET 0x00000000 /* Reset Value for Sensor_LUT_Index1[n] */
kevin1990 2:625a45555a85 615 #define REG_CORE_SENSOR_LUT_INDEX10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX10 */
kevin1990 2:625a45555a85 616 #define REG_CORE_SENSOR_LUT_INDEX11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX11 */
kevin1990 2:625a45555a85 617 #define REG_CORE_SENSOR_LUT_INDEX12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX12 */
kevin1990 2:625a45555a85 618 #define REG_CORE_SENSOR_LUT_INDEX13_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX13 */
kevin1990 2:625a45555a85 619 #define REG_CORE_SENSOR_LUT_INDEX14_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX14 */
kevin1990 2:625a45555a85 620 #define REG_CORE_SENSOR_LUT_INDEX15_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX15 */
kevin1990 2:625a45555a85 621 #define REG_CORE_SENSOR_LUT_INDEX16_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX16 */
kevin1990 2:625a45555a85 622 #define REG_CORE_SENSOR_LUT_INDEX17_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX17 */
kevin1990 2:625a45555a85 623 #define REG_CORE_SENSOR_LUT_INDEX18_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX18 */
kevin1990 2:625a45555a85 624 #define REG_CORE_SENSOR_LUT_INDEX19_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX19 */
kevin1990 2:625a45555a85 625 #define REG_CORE_SENSOR_LUT_INDEX110_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX110 */
kevin1990 2:625a45555a85 626 #define REG_CORE_SENSOR_LUT_INDEX10 0x000000B0 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 627 #define REG_CORE_SENSOR_LUT_INDEX11 0x000000F0 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 628 #define REG_CORE_SENSOR_LUT_INDEX12 0x00000130 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 629 #define REG_CORE_SENSOR_LUT_INDEX13 0x00000170 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 630 #define REG_CORE_SENSOR_LUT_INDEX14 0x000001B0 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 631 #define REG_CORE_SENSOR_LUT_INDEX15 0x000001F0 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 632 #define REG_CORE_SENSOR_LUT_INDEX16 0x00000230 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 633 #define REG_CORE_SENSOR_LUT_INDEX17 0x00000270 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 634 #define REG_CORE_SENSOR_LUT_INDEX18 0x000002B0 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 635 #define REG_CORE_SENSOR_LUT_INDEX19 0x000002F0 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 636 #define REG_CORE_SENSOR_LUT_INDEX110 0x00000330 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 637 #define REG_CORE_SENSOR_LUT_INDEX1n(i) (REG_CORE_SENSOR_LUT_INDEX10 + ((i) * 64))
kevin1990 2:625a45555a85 638 #define REG_CORE_SENSOR_LUT_INDEX1n_COUNT 11
kevin1990 2:625a45555a85 639 #define REG_CORE_SENSOR_LUT_INDEX2n_RESET 0x00000000 /* Reset Value for Sensor_LUT_Index2[n] */
kevin1990 2:625a45555a85 640 #define REG_CORE_SENSOR_LUT_INDEX20_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX20 */
kevin1990 2:625a45555a85 641 #define REG_CORE_SENSOR_LUT_INDEX21_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX21 */
kevin1990 2:625a45555a85 642 #define REG_CORE_SENSOR_LUT_INDEX22_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX22 */
kevin1990 2:625a45555a85 643 #define REG_CORE_SENSOR_LUT_INDEX23_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX23 */
kevin1990 2:625a45555a85 644 #define REG_CORE_SENSOR_LUT_INDEX24_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX24 */
kevin1990 2:625a45555a85 645 #define REG_CORE_SENSOR_LUT_INDEX25_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX25 */
kevin1990 2:625a45555a85 646 #define REG_CORE_SENSOR_LUT_INDEX26_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX26 */
kevin1990 2:625a45555a85 647 #define REG_CORE_SENSOR_LUT_INDEX27_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX27 */
kevin1990 2:625a45555a85 648 #define REG_CORE_SENSOR_LUT_INDEX28_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX28 */
kevin1990 2:625a45555a85 649 #define REG_CORE_SENSOR_LUT_INDEX29_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX29 */
kevin1990 2:625a45555a85 650 #define REG_CORE_SENSOR_LUT_INDEX210_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX210 */
kevin1990 2:625a45555a85 651 #define REG_CORE_SENSOR_LUT_INDEX20 0x000000B4 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 652 #define REG_CORE_SENSOR_LUT_INDEX21 0x000000F4 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 653 #define REG_CORE_SENSOR_LUT_INDEX22 0x00000134 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 654 #define REG_CORE_SENSOR_LUT_INDEX23 0x00000174 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 655 #define REG_CORE_SENSOR_LUT_INDEX24 0x000001B4 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 656 #define REG_CORE_SENSOR_LUT_INDEX25 0x000001F4 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 657 #define REG_CORE_SENSOR_LUT_INDEX26 0x00000234 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 658 #define REG_CORE_SENSOR_LUT_INDEX27 0x00000274 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 659 #define REG_CORE_SENSOR_LUT_INDEX28 0x000002B4 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 660 #define REG_CORE_SENSOR_LUT_INDEX29 0x000002F4 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 661 #define REG_CORE_SENSOR_LUT_INDEX210 0x00000334 /* CORE Sequence of Look-Up-Table Pointers */
kevin1990 2:625a45555a85 662 #define REG_CORE_SENSOR_LUT_INDEX2n(i) (REG_CORE_SENSOR_LUT_INDEX20 + ((i) * 64))
kevin1990 2:625a45555a85 663 #define REG_CORE_SENSOR_LUT_INDEX2n_COUNT 11
kevin1990 2:625a45555a85 664
kevin1990 2:625a45555a85 665 /* ============================================================================================================================
kevin1990 2:625a45555a85 666 CORE Register BitMasks, Positions & Enumerations
kevin1990 2:625a45555a85 667 ============================================================================================================================ */
kevin1990 2:625a45555a85 668 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 669 CORE_COMMAND Pos/Masks Description
kevin1990 2:625a45555a85 670 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 671 #define BITP_CORE_COMMAND_SPECIAL_COMMAND 0 /* Special Command */
kevin1990 2:625a45555a85 672 #define BITM_CORE_COMMAND_SPECIAL_COMMAND 0x000000FF /* Special Command */
kevin1990 2:625a45555a85 673 #define ENUM_CORE_COMMAND_NOP 0x00000000 /* Special_Command: No Command */
kevin1990 2:625a45555a85 674 #define ENUM_CORE_COMMAND_CONVERT 0x00000001 /* Special_Command: Start ADC Conversions */
kevin1990 2:625a45555a85 675 #define ENUM_CORE_COMMAND_CONVERT_WITH_RAW 0x00000002 /* Special_Command: Start Conversions with Added RAW ADC Data */
kevin1990 2:625a45555a85 676 #define ENUM_CORE_COMMAND_RUN_DIAGNOSTICS 0x00000003 /* Special_Command: Initiate a Diagnostics Cycle */
kevin1990 2:625a45555a85 677 #define ENUM_CORE_COMMAND_LOAD_DEFAULTS 0x00000004 /* Special_Command: Load Relevant Registers With Default Values Appropriate to Sensor */
kevin1990 2:625a45555a85 678 #define ENUM_CORE_COMMAND_LOAD_CONFIG 0x00000005 /* Special_Command: Load Registers with Configuration from FLASH */
kevin1990 2:625a45555a85 679 #define ENUM_CORE_COMMAND_SAVE_CONFIG 0x00000006 /* Special_Command: Store Current Register Configuration to FLASH */
kevin1990 2:625a45555a85 680 #define ENUM_CORE_COMMAND_LATCH_CONFIG 0x00000007 /* Special_Command: Freeze Current Register Configuration and Prepare for Conversion */
kevin1990 2:625a45555a85 681 #define ENUM_CORE_COMMAND_LOAD_LUT 0x00000008 /* Special_Command: Load LUT from FLASH */
kevin1990 2:625a45555a85 682 #define ENUM_CORE_COMMAND_SAVE_LUT2 0x00000009 /* Special_Command: Save LUT to FLASH */
kevin1990 2:625a45555a85 683
kevin1990 2:625a45555a85 684 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 685 CORE_MODE Pos/Masks Description
kevin1990 2:625a45555a85 686 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 687 #define BITP_CORE_MODE_STDBY_EN 5 /* Standby */
kevin1990 2:625a45555a85 688 #define BITP_CORE_MODE_DRDY_MODE 2 /* Indicates Behavior of DRDY with Respect to FIFO State */
kevin1990 2:625a45555a85 689 #define BITP_CORE_MODE_CONVERSION_MODE 0 /* Conversion Mode */
kevin1990 2:625a45555a85 690 #define BITM_CORE_MODE_STDBY_EN 0x00000020 /* Standby */
kevin1990 2:625a45555a85 691 #define BITM_CORE_MODE_DRDY_MODE 0x0000000C /* Indicates Behavior of DRDY with Respect to FIFO State */
kevin1990 2:625a45555a85 692 #define BITM_CORE_MODE_CONVERSION_MODE 0x00000003 /* Conversion Mode */
kevin1990 2:625a45555a85 693 #define ENUM_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data Ready Per Conversion */
kevin1990 2:625a45555a85 694 #define ENUM_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data Ready Per Cycle */
kevin1990 2:625a45555a85 695 #define ENUM_CORE_MODE_DRDY_PER_FIFO_FILL 0x00000008 /* Drdy_Mode: Data Ready Per FIFO Fill */
kevin1990 2:625a45555a85 696 #define ENUM_CORE_MODE_DRDY_MODE3 0x0000000C /* Drdy_Mode: Undefined */
kevin1990 2:625a45555a85 697 #define ENUM_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single Cycle */
kevin1990 2:625a45555a85 698 #define ENUM_CORE_MODE_MULTICYCLE 0x00000001 /* Conversion_Mode: Multi Cycle */
kevin1990 2:625a45555a85 699 #define ENUM_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous Conversion */
kevin1990 2:625a45555a85 700 #define ENUM_CORE_MODE_MODE3 0x00000003 /* Conversion_Mode: Undefined */
kevin1990 2:625a45555a85 701
kevin1990 2:625a45555a85 702 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 703 CORE_POWER_CONFIG Pos/Masks Description
kevin1990 2:625a45555a85 704 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 705 #define BITP_CORE_POWER_CONFIG_POWER_MODE_MCU 2 /* MCU Power Mode */
kevin1990 2:625a45555a85 706 #define BITP_CORE_POWER_CONFIG_POWER_MODE_ADC 0 /* ADC Power Mode */
kevin1990 2:625a45555a85 707 #define BITM_CORE_POWER_CONFIG_POWER_MODE_MCU 0x0000000C /* MCU Power Mode */
kevin1990 2:625a45555a85 708 #define BITM_CORE_POWER_CONFIG_POWER_MODE_ADC 0x00000003 /* ADC Power Mode */
kevin1990 2:625a45555a85 709
kevin1990 2:625a45555a85 710 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 711 CORE_CYCLE_CONTROL Pos/Masks Description
kevin1990 2:625a45555a85 712 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 713 #define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 14 /* Units for Cycle Time */
kevin1990 2:625a45555a85 714 #define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME 0 /* Duration of a Full Measurement Cycle */
kevin1990 2:625a45555a85 715 #define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 0x0000C000 /* Units for Cycle Time */
kevin1990 2:625a45555a85 716 #define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME 0x00000FFF /* Duration of a Full Measurement Cycle */
kevin1990 2:625a45555a85 717 #define ENUM_CORE_CYCLE_CONTROL_MICROSECONDS 0x00000000 /* Cycle_Time_Units: Micro-Seconds */
kevin1990 2:625a45555a85 718 #define ENUM_CORE_CYCLE_CONTROL_MILLISECONDS 0x00004000 /* Cycle_Time_Units: Milli-Seconds */
kevin1990 2:625a45555a85 719 #define ENUM_CORE_CYCLE_CONTROL_SECONDS 0x00008000 /* Cycle_Time_Units: Seconds */
kevin1990 2:625a45555a85 720 #define ENUM_CORE_CYCLE_CONTROL_UNDEFINED 0x0000C000 /* Cycle_Time_Units: Undefined */
kevin1990 2:625a45555a85 721
kevin1990 2:625a45555a85 722 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 723 CORE_FIFO_NUM_CYCLES Pos/Masks Description
kevin1990 2:625a45555a85 724 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 725 #define BITP_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0 /* How Many Cycles to Fill FIFO */
kevin1990 2:625a45555a85 726 #define BITM_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0x000000FF /* How Many Cycles to Fill FIFO */
kevin1990 2:625a45555a85 727
kevin1990 2:625a45555a85 728 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 729 CORE_MULTI_CYCLE_RATE Pos/Masks Description
kevin1990 2:625a45555a85 730 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 731 #define BITP_CORE_MULTI_CYCLE_RATE_MULTI_CYCLE_RATE 0 /* CHANGE NAME. Defines Time Between Repetitions of FIFO Fill */
kevin1990 2:625a45555a85 732 #define BITM_CORE_MULTI_CYCLE_RATE_MULTI_CYCLE_RATE 0x000000FF /* CHANGE NAME. Defines Time Between Repetitions of FIFO Fill */
kevin1990 2:625a45555a85 733
kevin1990 2:625a45555a85 734 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 735 CORE_STATUS Pos/Masks Description
kevin1990 2:625a45555a85 736 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 737 #define BITP_CORE_STATUS_CMD_RUNNING 4 /* Indicates a Special Command is Active */
kevin1990 2:625a45555a85 738 #define BITP_CORE_STATUS_DRDY 3 /* Indicates a New Sensor (ADC?) Result is Available to Be Read */
kevin1990 2:625a45555a85 739 #define BITP_CORE_STATUS_ERROR 2 /* Indicates an Error */
kevin1990 2:625a45555a85 740 #define BITP_CORE_STATUS_ALERT 1 /* Indicates One or More Sensors are Outside Specified Limits */
kevin1990 2:625a45555a85 741 #define BITM_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates a Special Command is Active */
kevin1990 2:625a45555a85 742 #define BITM_CORE_STATUS_DRDY 0x00000008 /* Indicates a New Sensor (ADC?) Result is Available to Be Read */
kevin1990 2:625a45555a85 743 #define BITM_CORE_STATUS_ERROR 0x00000004 /* Indicates an Error */
kevin1990 2:625a45555a85 744 #define BITM_CORE_STATUS_ALERT 0x00000002 /* Indicates One or More Sensors are Outside Specified Limits */
kevin1990 2:625a45555a85 745
kevin1990 2:625a45555a85 746 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 747 CORE_DIAGNOSTICS_STATUS Pos/Masks Description
kevin1990 2:625a45555a85 748 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 749 #define BITP_CORE_DIAGNOSTICS_STATUS_DIAGNOSTICS_STATUS 0 /* Diagnostics Status */
kevin1990 2:625a45555a85 750 #define BITM_CORE_DIAGNOSTICS_STATUS_DIAGNOSTICS_STATUS 0x0000FFFF /* Diagnostics Status */
kevin1990 2:625a45555a85 751
kevin1990 2:625a45555a85 752 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 753 CORE_CHANNEL_ALERT_STATUS Pos/Masks Description
kevin1990 2:625a45555a85 754 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 755 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 12 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 756 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 11 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 757 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 10 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 758 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 9 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 759 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 8 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 760 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 7 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 761 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 6 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 762 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 5 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 763 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 4 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 764 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 3 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 765 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 2 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 766 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 1 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 767 #define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 768 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 0x00001000 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 769 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 0x00000800 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 770 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 0x00000400 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 771 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 0x00000200 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 772 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 0x00000100 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 773 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 0x00000080 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 774 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 0x00000040 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 775 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 0x00000020 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 776 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 0x00000010 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 777 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 0x00000008 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 778 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 0x00000004 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 779 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 0x00000002 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 780 #define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0x00000001 /* Indicates Channel is Outside Specified Limits */
kevin1990 2:625a45555a85 781
kevin1990 2:625a45555a85 782 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 783 CORE_ALERT_DETAIL_CH[n] Pos/Masks Description
kevin1990 2:625a45555a85 784 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 785 #define BITP_CORE_ALERT_DETAIL_CH_REF_DETECT 6 /* Indicates Whether ADC Reference is Valid */
kevin1990 2:625a45555a85 786 #define BITP_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 5 /* Indicates Sensor Input is Open Circuit */
kevin1990 2:625a45555a85 787 #define BITP_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 4 /* Indicates Sensor Result is Greater Than High Limit */
kevin1990 2:625a45555a85 788 #define BITP_CORE_ALERT_DETAIL_CH_LOW_LIMIT 3 /* Indicates Sensor Result is Less Than Low Limit */
kevin1990 2:625a45555a85 789 #define BITP_CORE_ALERT_DETAIL_CH_OVER_RANGE 2 /* Indicates Channel Over-Range */
kevin1990 2:625a45555a85 790 #define BITP_CORE_ALERT_DETAIL_CH_UNDER_RANGE 1 /* Indicates Channel Under-Range */
kevin1990 2:625a45555a85 791 #define BITP_CORE_ALERT_DETAIL_CH_TIME_OUT 0 /* Indicates Time-Out Error from Digital Sensor */
kevin1990 2:625a45555a85 792 #define BITM_CORE_ALERT_DETAIL_CH_REF_DETECT 0x00000040 /* Indicates Whether ADC Reference is Valid */
kevin1990 2:625a45555a85 793 #define BITM_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 0x00000020 /* Indicates Sensor Input is Open Circuit */
kevin1990 2:625a45555a85 794 #define BITM_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 0x00000010 /* Indicates Sensor Result is Greater Than High Limit */
kevin1990 2:625a45555a85 795 #define BITM_CORE_ALERT_DETAIL_CH_LOW_LIMIT 0x00000008 /* Indicates Sensor Result is Less Than Low Limit */
kevin1990 2:625a45555a85 796 #define BITM_CORE_ALERT_DETAIL_CH_OVER_RANGE 0x00000004 /* Indicates Channel Over-Range */
kevin1990 2:625a45555a85 797 #define BITM_CORE_ALERT_DETAIL_CH_UNDER_RANGE 0x00000002 /* Indicates Channel Under-Range */
kevin1990 2:625a45555a85 798 #define BITM_CORE_ALERT_DETAIL_CH_TIME_OUT 0x00000001 /* Indicates Time-Out Error from Digital Sensor */
kevin1990 2:625a45555a85 799
kevin1990 2:625a45555a85 800 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 801 CORE_EXTERNAL_REFERENCE1 Pos/Masks Description
kevin1990 2:625a45555a85 802 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 803 #define BITP_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0 /* Refin1 Value */
kevin1990 2:625a45555a85 804 #define BITM_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0xFFFFFFFF /* Refin1 Value */
kevin1990 2:625a45555a85 805
kevin1990 2:625a45555a85 806 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 807 CORE_EXTERNAL_REFERENCE2 Pos/Masks Description
kevin1990 2:625a45555a85 808 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 809 #define BITP_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0 /* Refin2 Value */
kevin1990 2:625a45555a85 810 #define BITM_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0xFFFFFFFF /* Refin2 Value */
kevin1990 2:625a45555a85 811
kevin1990 2:625a45555a85 812 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 813 CORE_DIAGNOSTICS_CONTROL Pos/Masks Description
kevin1990 2:625a45555a85 814 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 815 #define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_OCD_FREQ 2 /* Diagnostics Open Circuit Detect Frequency */
kevin1990 2:625a45555a85 816 #define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 1 /* Diagnostics Measure Enable */
kevin1990 2:625a45555a85 817 #define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0 /* Diagnostics Global Enable */
kevin1990 2:625a45555a85 818 #define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_OCD_FREQ 0x0000000C /* Diagnostics Open Circuit Detect Frequency */
kevin1990 2:625a45555a85 819 #define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000002 /* Diagnostics Measure Enable */
kevin1990 2:625a45555a85 820 #define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0x00000001 /* Diagnostics Global Enable */
kevin1990 2:625a45555a85 821 #define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ0 0x00000000
kevin1990 2:625a45555a85 822 #define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ1 0x00000004
kevin1990 2:625a45555a85 823 #define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ2 0x00000008
kevin1990 2:625a45555a85 824 #define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ3 0x0000000C
kevin1990 2:625a45555a85 825
kevin1990 2:625a45555a85 826 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 827 CORE_DIAGNOSTICS_EXTRA Pos/Masks Description
kevin1990 2:625a45555a85 828 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 829 #define BITP_CORE_DIAGNOSTICS_EXTRA_DIAGNOSTICS_EXTRA 0 /* Additional Diagnostics Control */
kevin1990 2:625a45555a85 830 #define BITM_CORE_DIAGNOSTICS_EXTRA_DIAGNOSTICS_EXTRA 0x000000FF /* Additional Diagnostics Control */
kevin1990 2:625a45555a85 831
kevin1990 2:625a45555a85 832 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 833 CORE_DATA_FIFO Pos/Masks Description
kevin1990 2:625a45555a85 834 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 835 #define BITP_CORE_DATA_FIFO_RAW_SAMPLE 40 /* ADC Result */
kevin1990 2:625a45555a85 836 #define BITP_CORE_DATA_FIFO_CH_VALID 39 /* Indicates Whether Valid Data Read from FIFO */
kevin1990 2:625a45555a85 837 #define BITP_CORE_DATA_FIFO_CH_RAW 38 /* Indicates If RAW Data is Valid */
kevin1990 2:625a45555a85 838 #define BITP_CORE_DATA_FIFO_CH_ALERT 37 /* Indicates Alert on Channel */
kevin1990 2:625a45555a85 839 #define BITP_CORE_DATA_FIFO_CH_ERROR 36 /* Indicates Error on Channel */
kevin1990 2:625a45555a85 840 #define BITP_CORE_DATA_FIFO_CHANNEL_ID 32 /* Indicates Which Channel This FIFO Data Corresponds to */
kevin1990 2:625a45555a85 841 #define BITP_CORE_DATA_FIFO_SENSOR_RESULT 0 /* Linearized and Compensated Sensor Result */
kevin1990 2:625a45555a85 842 #define BITM_CORE_DATA_FIFO_RAW_SAMPLE 0xFFFFFF0000000000 /* ADC Result */
kevin1990 2:625a45555a85 843 #define BITM_CORE_DATA_FIFO_CH_VALID 0x8000000000 /* Indicates Whether Valid Data Read from FIFO */
kevin1990 2:625a45555a85 844 #define BITM_CORE_DATA_FIFO_CH_RAW 0x4000000000 /* Indicates If RAW Data is Valid */
kevin1990 2:625a45555a85 845 #define BITM_CORE_DATA_FIFO_CH_ALERT 0x2000000000 /* Indicates Alert on Channel */
kevin1990 2:625a45555a85 846 #define BITM_CORE_DATA_FIFO_CH_ERROR 0x1000000000 /* Indicates Error on Channel */
kevin1990 2:625a45555a85 847 #define BITM_CORE_DATA_FIFO_CHANNEL_ID 0xF00000000 /* Indicates Which Channel This FIFO Data Corresponds to */
kevin1990 2:625a45555a85 848 #define BITM_CORE_DATA_FIFO_SENSOR_RESULT 0xFFFFFFFF /* Linearized and Compensated Sensor Result */
kevin1990 2:625a45555a85 849
kevin1990 2:625a45555a85 850 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 851 CORE_LUT_SELECT Pos/Masks Description
kevin1990 2:625a45555a85 852 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 853 #define BITP_CORE_LUT_SELECT_LUT_RW 7 /* Read or Write LUT Data */
kevin1990 2:625a45555a85 854 #define BITP_CORE_LUT_SELECT_LUT_TYPE 4 /* Indicates Whether Look-Up-Table or Polynomial Equation */
kevin1990 2:625a45555a85 855 #define BITP_CORE_LUT_SELECT_LUT_CHANNEL 0 /* Which Channel's LUT / Polynomial to Access */
kevin1990 2:625a45555a85 856 #define BITM_CORE_LUT_SELECT_LUT_RW 0x00000080 /* Read or Write LUT Data */
kevin1990 2:625a45555a85 857 #define BITM_CORE_LUT_SELECT_LUT_TYPE 0x00000070 /* Indicates Whether Look-Up-Table or Polynomial Equation */
kevin1990 2:625a45555a85 858 #define BITM_CORE_LUT_SELECT_LUT_CHANNEL 0x0000000F /* Which Channel's LUT / Polynomial to Access */
kevin1990 2:625a45555a85 859
kevin1990 2:625a45555a85 860 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 861 CORE_LUT_OFFSET Pos/Masks Description
kevin1990 2:625a45555a85 862 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 863 #define BITP_CORE_LUT_OFFSET_LUT_OFFSET 0 /* Offset into Look-Up-Table */
kevin1990 2:625a45555a85 864 #define BITM_CORE_LUT_OFFSET_LUT_OFFSET 0x00003FFF /* Offset into Look-Up-Table */
kevin1990 2:625a45555a85 865
kevin1990 2:625a45555a85 866 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 867 CORE_LUT_DATA Pos/Masks Description
kevin1990 2:625a45555a85 868 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 869 #define BITP_CORE_LUT_DATA_LUT_DATA 0 /* Data Byte to Write to / Read from Look-Up-Table */
kevin1990 2:625a45555a85 870 #define BITM_CORE_LUT_DATA_LUT_DATA 0x000000FF /* Data Byte to Write to / Read from Look-Up-Table */
kevin1990 2:625a45555a85 871
kevin1990 2:625a45555a85 872 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 873 CORE_CAL_SELECT Pos/Masks Description
kevin1990 2:625a45555a85 874 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 875 #define BITP_CORE_CAL_SELECT_CAL_RW 7 /* Read or Write Calibration Data */
kevin1990 2:625a45555a85 876 #define BITP_CORE_CAL_SELECT_CAL_TYPE 4 /* NOT REQUIRED?? */
kevin1990 2:625a45555a85 877 #define BITP_CORE_CAL_SELECT_CAL_CHANNEL 0 /* Which Channel's Calibration Data to Access */
kevin1990 2:625a45555a85 878 #define BITM_CORE_CAL_SELECT_CAL_RW 0x00000080 /* Read or Write Calibration Data */
kevin1990 2:625a45555a85 879 #define BITM_CORE_CAL_SELECT_CAL_TYPE 0x00000070 /* NOT REQUIRED?? */
kevin1990 2:625a45555a85 880 #define BITM_CORE_CAL_SELECT_CAL_CHANNEL 0x0000000F /* Which Channel's Calibration Data to Access */
kevin1990 2:625a45555a85 881
kevin1990 2:625a45555a85 882 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 883 CORE_CAL_OFFSET Pos/Masks Description
kevin1990 2:625a45555a85 884 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 885 #define BITP_CORE_CAL_OFFSET_CAL_OFFSET 0 /* Offset into Calibration Data */
kevin1990 2:625a45555a85 886 #define BITM_CORE_CAL_OFFSET_CAL_OFFSET 0x00003FFF /* Offset into Calibration Data */
kevin1990 2:625a45555a85 887
kevin1990 2:625a45555a85 888 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 889 CORE_CAL_DATA Pos/Masks Description
kevin1990 2:625a45555a85 890 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 891 #define BITP_CORE_CAL_DATA_CAL_DATA 0 /* Data to Write to / Read from Calibration Data */
kevin1990 2:625a45555a85 892 #define BITM_CORE_CAL_DATA_CAL_DATA 0x000000FF /* Data to Write to / Read from Calibration Data */
kevin1990 2:625a45555a85 893
kevin1990 2:625a45555a85 894 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 895 CORE_REVISION Pos/Masks Description
kevin1990 2:625a45555a85 896 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 897 #define BITP_CORE_REVISION_COMMS_PROTOCOL 16 /* ID Info */
kevin1990 2:625a45555a85 898 #define BITP_CORE_REVISION_HARDWARE_REVISION 8 /* ID Info */
kevin1990 2:625a45555a85 899 #define BITP_CORE_REVISION_FIRMWARE_REVISION 0 /* ID Info */
kevin1990 2:625a45555a85 900 #define BITM_CORE_REVISION_COMMS_PROTOCOL 0x00FF0000 /* ID Info */
kevin1990 2:625a45555a85 901 #define BITM_CORE_REVISION_HARDWARE_REVISION 0x0000FF00 /* ID Info */
kevin1990 2:625a45555a85 902 #define BITM_CORE_REVISION_FIRMWARE_REVISION 0x000000FF /* ID Info */
kevin1990 2:625a45555a85 903
kevin1990 2:625a45555a85 904 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 905 CORE_CHANNEL_COUNT[n] Pos/Masks Description
kevin1990 2:625a45555a85 906 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 907 #define BITP_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 7 /* Enable Channel in Measurement Cycle */
kevin1990 2:625a45555a85 908 #define BITP_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0 /* How Many Times Channel Should Appear in One Cycle */
kevin1990 2:625a45555a85 909 #define BITM_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 0x00000080 /* Enable Channel in Measurement Cycle */
kevin1990 2:625a45555a85 910 #define BITM_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0x0000007F /* How Many Times Channel Should Appear in One Cycle */
kevin1990 2:625a45555a85 911
kevin1990 2:625a45555a85 912 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 913 CORE_SENSOR_TYPE[n] Pos/Masks Description
kevin1990 2:625a45555a85 914 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 915 #define BITP_CORE_SENSOR_TYPE_SENSOR_CATEGORY 13 /* Indicates Category of Sensor */
kevin1990 2:625a45555a85 916 #define BITP_CORE_SENSOR_TYPE_SENSOR_LOAD_DEFAULTS 12 /* Indicates to Use Default Register Values */
kevin1990 2:625a45555a85 917 #define BITP_CORE_SENSOR_TYPE_SENSOR_TYPE 0 /* Sensor Type */
kevin1990 2:625a45555a85 918 #define BITM_CORE_SENSOR_TYPE_SENSOR_CATEGORY 0x0000E000 /* Indicates Category of Sensor */
kevin1990 2:625a45555a85 919 #define BITM_CORE_SENSOR_TYPE_SENSOR_LOAD_DEFAULTS 0x00001000 /* Indicates to Use Default Register Values */
kevin1990 2:625a45555a85 920 #define BITM_CORE_SENSOR_TYPE_SENSOR_TYPE 0x00000FFF /* Sensor Type */
kevin1990 2:625a45555a85 921 #define ENUM_CORE_SENSOR_TYPE_ANALOG 0x00000000
kevin1990 2:625a45555a85 922 #define ENUM_CORE_SENSOR_TYPE_I2C 0x00002000
kevin1990 2:625a45555a85 923 #define ENUM_CORE_SENSOR_TYPE_SPI 0x00004000
kevin1990 2:625a45555a85 924 #define ENUM_CORE_SENSOR_TYPE_TBD3 0x00006000
kevin1990 2:625a45555a85 925 #define ENUM_CORE_SENSOR_TYPE_TBD4 0x00008000
kevin1990 2:625a45555a85 926 #define ENUM_CORE_SENSOR_TYPE_TBD5 0x0000A000
kevin1990 2:625a45555a85 927 #define ENUM_CORE_SENSOR_TYPE_TBD6 0x0000C000
kevin1990 2:625a45555a85 928 #define ENUM_CORE_SENSOR_TYPE_TBD7 0x0000E000
kevin1990 2:625a45555a85 929 #define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T 0x00000000 /* Sensor_Type: Thermocouple T-Type Sensor */
kevin1990 2:625a45555a85 930 #define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor */
kevin1990 2:625a45555a85 931 #define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor */
kevin1990 2:625a45555a85 932 #define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_CUSTOM1 0x0000000E /* Sensor_Type: Thermocouple Custom Sensor1 */
kevin1990 2:625a45555a85 933 #define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_CUSTOM2 0x0000000F /* Sensor_Type: Thermocouple Custom Sensor2 */
kevin1990 2:625a45555a85 934 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100 0x00000010 /* Sensor_Type: RTD 2 Wire PT100 Sensor */
kevin1990 2:625a45555a85 935 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000 0x00000011 /* Sensor_Type: RTD 2 Wire PT1000 Sensor */
kevin1990 2:625a45555a85 936 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_CUSTOM1 0x0000001E /* Sensor_Type: RTD 2 Wire Custom Sensor1 */
kevin1990 2:625a45555a85 937 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_CUSTOM2 0x0000001F /* Sensor_Type: RTD 2 Wire Custom Sensor2 */
kevin1990 2:625a45555a85 938 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100 0x00000020 /* Sensor_Type: RTD 3 Wire PT100 Sensor */
kevin1990 2:625a45555a85 939 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000 0x00000021 /* Sensor_Type: RTD 3 Wire PT1000 Sensor */
kevin1990 2:625a45555a85 940 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_ONECONV 0x0000002C /* Sensor_Type: RTD 3 Wire PT100 No Chop Custom Sensor */
kevin1990 2:625a45555a85 941 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_ONECONV 0x0000002D /* Sensor_Type: RTD 3 Wire PT1000 No Chop Custom Sensor */
kevin1990 2:625a45555a85 942 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_CUSTOM1 0x0000002E /* Sensor_Type: RTD 3 Wire Custom Sensor1 */
kevin1990 2:625a45555a85 943 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_CUSTOM2 0x0000002F /* Sensor_Type: RTD 3 Wire Custom Sensor2 */
kevin1990 2:625a45555a85 944 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100 0x00000030 /* Sensor_Type: RTD 4 Wire PT100 Sensor */
kevin1990 2:625a45555a85 945 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000 0x00000031 /* Sensor_Type: RTD 4 Wire PT1000 Sensor */
kevin1990 2:625a45555a85 946 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_CUSTOM1 0x0000003E /* Sensor_Type: RTD 4 Wire Custom Sensor1 */
kevin1990 2:625a45555a85 947 #define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_CUSTOM2 0x0000003F /* Sensor_Type: RTD 4 Wire Custom Sensor2 */
kevin1990 2:625a45555a85 948 #define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K 0x00000040 /* Sensor_Type: Thermistor Type A 10kOhm Sensor */
kevin1990 2:625a45555a85 949 #define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K 0x00000041 /* Sensor_Type: Thermistor Type B 10kOhm Sensor */
kevin1990 2:625a45555a85 950 #define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_CUSTOM 0x0000004F /* Sensor_Type: Thermistor Custom Sensor */
kevin1990 2:625a45555a85 951 #define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W 0x00000050 /* Sensor_Type: Bridge 4 Wire Sensor */
kevin1990 2:625a45555a85 952 #define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_CUSTOM 0x0000005F /* Sensor_Type: Bridge 4 Wire Custom Sensor */
kevin1990 2:625a45555a85 953 #define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W 0x00000060 /* Sensor_Type: Bridge 6 Wire Sensor */
kevin1990 2:625a45555a85 954 #define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_CUSTOM 0x0000006F /* Sensor_Type: Bridge 6 Wire Custom Sensor */
kevin1990 2:625a45555a85 955 #define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE 0x00000070 /* Sensor_Type: Voltage Input */
kevin1990 2:625a45555a85 956 #define ENUM_CORE_SENSOR_TYPE_SENSOR_CURRENT 0x00000080 /* Sensor_Type: Current Input */
kevin1990 2:625a45555a85 957 #define ENUM_CORE_SENSOR_TYPE_CUSTOM 0x000000A0 /* Sensor_Type: Custom */
kevin1990 2:625a45555a85 958 #define ENUM_CORE_SENSOR_TYPE_I2C_PRESSURE1 0x00000800 /* Sensor_Type: I2C Pressure Sensor Type 1 */
kevin1990 2:625a45555a85 959 #define ENUM_CORE_SENSOR_TYPE_I2C_PRESSURE2 0x00000801 /* Sensor_Type: I2C Pressure Sensor Type 2 */
kevin1990 2:625a45555a85 960 #define ENUM_CORE_SENSOR_TYPE_SPI_PRESSURE1 0x00000C00 /* Sensor_Type: SPI Pressure Sensor Type 1 */
kevin1990 2:625a45555a85 961 #define ENUM_CORE_SENSOR_TYPE_SPI_PRESSURE2 0x00000C01 /* Sensor_Type: SPI Pressure Sensor Type 2 */
kevin1990 2:625a45555a85 962 #define ENUM_CORE_SENSOR_TYPE_SPI_ACCELEROMETER1 0x00000C02 /* Sensor_Type: SPI Accelerometer Sensor Type 1 3-Axis */
kevin1990 2:625a45555a85 963
kevin1990 2:625a45555a85 964 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 965 CORE_SENSOR_DETAILS[n] Pos/Masks Description
kevin1990 2:625a45555a85 966 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 967 #define BITP_CORE_SENSOR_DETAILS_AVERAGING 28 /* Number of ADC Results to Average */
kevin1990 2:625a45555a85 968 #define BITP_CORE_SENSOR_DETAILS_PGA_GAIN 24 /* PGA Gain */
kevin1990 2:625a45555a85 969 #define BITP_CORE_SENSOR_DETAILS_REFERENCE_SELECT 20 /* Reference Selection */
kevin1990 2:625a45555a85 970 #define BITP_CORE_SENSOR_DETAILS_VBIAS 19 /* Controls ADC Vbias Output */
kevin1990 2:625a45555a85 971 #define BITP_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 18 /* Enable or Disable ADC Reference Buffer */
kevin1990 2:625a45555a85 972 #define BITP_CORE_SENSOR_DETAILS_CJC_PUBLISH 17 /* Publish Compensation Data */
kevin1990 2:625a45555a85 973 #define BITP_CORE_SENSOR_DETAILS_COMPENSATION_ONLY 16 /* Indicates to Use This Channel Only as Compensation */
kevin1990 2:625a45555a85 974 #define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL3 12 /* Indicates Channel for Third Term of Compensation */
kevin1990 2:625a45555a85 975 #define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL2 8 /* Indicates Channel for Second Term of Compensation */
kevin1990 2:625a45555a85 976 #define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 4 /* Indicates Which Channel is Used to Compensate Sensor Result */
kevin1990 2:625a45555a85 977 #define BITP_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0 /* Units of Sensor Measurement */
kevin1990 2:625a45555a85 978 #define BITM_CORE_SENSOR_DETAILS_AVERAGING 0x70000000 /* Number of ADC Results to Average */
kevin1990 2:625a45555a85 979 #define BITM_CORE_SENSOR_DETAILS_PGA_GAIN 0x07000000 /* PGA Gain */
kevin1990 2:625a45555a85 980 #define BITM_CORE_SENSOR_DETAILS_REFERENCE_SELECT 0x00F00000 /* Reference Selection */
kevin1990 2:625a45555a85 981 #define BITM_CORE_SENSOR_DETAILS_VBIAS 0x00080000 /* Controls ADC Vbias Output */
kevin1990 2:625a45555a85 982 #define BITM_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 0x00040000 /* Enable or Disable ADC Reference Buffer */
kevin1990 2:625a45555a85 983 #define BITM_CORE_SENSOR_DETAILS_CJC_PUBLISH 0x00020000 /* Publish Compensation Data */
kevin1990 2:625a45555a85 984 #define BITM_CORE_SENSOR_DETAILS_COMPENSATION_ONLY 0x00010000 /* Indicates to Use This Channel Only as Compensation */
kevin1990 2:625a45555a85 985 #define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL3 0x0000F000 /* Indicates Channel for Third Term of Compensation */
kevin1990 2:625a45555a85 986 #define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL2 0x00000F00 /* Indicates Channel for Second Term of Compensation */
kevin1990 2:625a45555a85 987 #define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 0x000000F0 /* Indicates Which Channel is Used to Compensate Sensor Result */
kevin1990 2:625a45555a85 988 #define BITM_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0x0000000F /* Units of Sensor Measurement */
kevin1990 2:625a45555a85 989 #define ENUM_CORE_SENSOR_DETAILS_REF_DEFAULT 0x00000000 /* Reference_Select: Default Based on Sensor Type */
kevin1990 2:625a45555a85 990 #define ENUM_CORE_SENSOR_DETAILS_REF_INT 0x00100000 /* Reference_Select: Internal Reference */
kevin1990 2:625a45555a85 991 #define ENUM_CORE_SENSOR_DETAILS_REF_RINT1 0x00200000 /* Reference_Select: Internal Resistor1 */
kevin1990 2:625a45555a85 992 #define ENUM_CORE_SENSOR_DETAILS_REF_RINT2 0x00300000 /* Reference_Select: Internal Resistor2 */
kevin1990 2:625a45555a85 993 #define ENUM_CORE_SENSOR_DETAILS_REF_REXT1 0x00400000 /* Reference_Select: External Resistor on Refin1 */
kevin1990 2:625a45555a85 994 #define ENUM_CORE_SENSOR_DETAILS_REF_REXT2 0x00500000 /* Reference_Select: External Resistor on Refin2 */
kevin1990 2:625a45555a85 995 #define ENUM_CORE_SENSOR_DETAILS_REF_VEXT1 0x00600000 /* Reference_Select: External Voltage on Refin1 */
kevin1990 2:625a45555a85 996 #define ENUM_CORE_SENSOR_DETAILS_REF_VEXT2 0x00700000 /* Reference_Select: External Voltage on Refin2 */
kevin1990 2:625a45555a85 997 #define ENUM_CORE_SENSOR_DETAILS_REF_AVDD 0x00800000 /* Reference_Select: AVDD */
kevin1990 2:625a45555a85 998 #define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGC 0x00000000 /* Measurement_Units: Degrees C */
kevin1990 2:625a45555a85 999 #define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGF 0x00000001 /* Measurement_Units: Degrees F */
kevin1990 2:625a45555a85 1000
kevin1990 2:625a45555a85 1001 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1002 CORE_CHANNEL_EXCITATION[n] Pos/Masks Description
kevin1990 2:625a45555a85 1003 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1004 #define BITP_CORE_CHANNEL_EXCITATION_IOUT_DONTCHOP_3WIRE 7 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */
kevin1990 2:625a45555a85 1005 #define BITP_CORE_CHANNEL_EXCITATION_IOUT1_DISABLE 4 /* NOT NEEDED?? Disable Second Current Source */
kevin1990 2:625a45555a85 1006 #define BITP_CORE_CHANNEL_EXCITATION_IOUT0_DISABLE 3 /* NOT NEEDED?? Disable First Current Source */
kevin1990 2:625a45555a85 1007 #define BITP_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0 /* Current Source Value */
kevin1990 2:625a45555a85 1008 #define BITM_CORE_CHANNEL_EXCITATION_IOUT_DONTCHOP_3WIRE 0x00000080 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */
kevin1990 2:625a45555a85 1009 #define BITM_CORE_CHANNEL_EXCITATION_IOUT1_DISABLE 0x00000010 /* NOT NEEDED?? Disable Second Current Source */
kevin1990 2:625a45555a85 1010 #define BITM_CORE_CHANNEL_EXCITATION_IOUT0_DISABLE 0x00000008 /* NOT NEEDED?? Disable First Current Source */
kevin1990 2:625a45555a85 1011 #define BITM_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0x00000007 /* Current Source Value */
kevin1990 2:625a45555a85 1012
kevin1990 2:625a45555a85 1013 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1014 CORE_DIGITAL_SENSOR_CODING[n] Pos/Masks Description
kevin1990 2:625a45555a85 1015 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1016 #define BITP_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_MSB_POSITION 8 /* Position of Data MSB in the Read Frame */
kevin1990 2:625a45555a85 1017 #define BITP_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_NUMBITS 2 /* Number of Relevant Data Bits in Digital Sensor */
kevin1990 2:625a45555a85 1018 #define BITP_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_CODING 0 /* I2C Address or Write Address Command for SPI Sensor */
kevin1990 2:625a45555a85 1019 #define BITM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_MSB_POSITION 0x00001F00 /* Position of Data MSB in the Read Frame */
kevin1990 2:625a45555a85 1020 #define BITM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_NUMBITS 0x0000007C /* Number of Relevant Data Bits in Digital Sensor */
kevin1990 2:625a45555a85 1021 #define BITM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_CODING 0x00000003 /* I2C Address or Write Address Command for SPI Sensor */
kevin1990 2:625a45555a85 1022 #define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_8_BITS 0x00000000 /* Digital_Sensor_Numbits: 8 Bits */
kevin1990 2:625a45555a85 1023 #define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_10_BITS 0x00000004 /* Digital_Sensor_Numbits: 10 Bits */
kevin1990 2:625a45555a85 1024 #define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_12_BITS 0x00000008 /* Digital_Sensor_Numbits: 12 Bits */
kevin1990 2:625a45555a85 1025 #define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_14_BITS 0x0000000C /* Digital_Sensor_Numbits: 14 Bits */
kevin1990 2:625a45555a85 1026 #define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_16_BITS 0x00000010 /* Digital_Sensor_Numbits: 16 Bits */
kevin1990 2:625a45555a85 1027 #define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_18_BITS 0x00000014 /* Digital_Sensor_Numbits: 18 Bits */
kevin1990 2:625a45555a85 1028 #define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_20_BITS 0x00000018 /* Digital_Sensor_Numbits: 20 Bits */
kevin1990 2:625a45555a85 1029 #define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_22_BITS 0x0000001C /* Digital_Sensor_Numbits: 22 Bits */
kevin1990 2:625a45555a85 1030 #define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_24_BITS 0x00000020 /* Digital_Sensor_Numbits: 24 Bits */
kevin1990 2:625a45555a85 1031 #define ENUM_CORE_DIGITAL_SENSOR_CODING_CODING_UNIPOLAR 0x00000000 /* Digital_Sensor_Coding: Unipolar */
kevin1990 2:625a45555a85 1032 #define ENUM_CORE_DIGITAL_SENSOR_CODING_CODING_TWOS_COMPL 0x00000001 /* Digital_Sensor_Coding: Twos Complement */
kevin1990 2:625a45555a85 1033 #define ENUM_CORE_DIGITAL_SENSOR_CODING_CODING_OFFSET_BINARY 0x00000002 /* Digital_Sensor_Coding: Offset Binary */
kevin1990 2:625a45555a85 1034
kevin1990 2:625a45555a85 1035 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1036 CORE_FILTER_SELECT[n] Pos/Masks Description
kevin1990 2:625a45555a85 1037 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1038 #define BITP_CORE_FILTER_SELECT_ADC_FIR_SEL 16 /* ADC Digital Filter FIR Type */
kevin1990 2:625a45555a85 1039 #define BITP_CORE_FILTER_SELECT_ADC_FILTER_TYPE 11 /* ADC Digital Filter Type */
kevin1990 2:625a45555a85 1040 #define BITP_CORE_FILTER_SELECT_ADC_FS 0 /* ADC Digital Filter Select */
kevin1990 2:625a45555a85 1041 #define BITM_CORE_FILTER_SELECT_ADC_FIR_SEL 0x00070000 /* ADC Digital Filter FIR Type */
kevin1990 2:625a45555a85 1042 #define BITM_CORE_FILTER_SELECT_ADC_FILTER_TYPE 0x00007800 /* ADC Digital Filter Type */
kevin1990 2:625a45555a85 1043 #define BITM_CORE_FILTER_SELECT_ADC_FS 0x000007FF /* ADC Digital Filter Select */
kevin1990 2:625a45555a85 1044 #define ENUM_CORE_FILTER_SELECT_SINC4 0x00000000 /* ADC_Filter_Type: Sinc4 Filter */
kevin1990 2:625a45555a85 1045 #define ENUM_CORE_FILTER_SELECT_TBD1 0x00000800 /* ADC_Filter_Type: TBD1 */
kevin1990 2:625a45555a85 1046 #define ENUM_CORE_FILTER_SELECT_TBD2 0x00001000 /* ADC_Filter_Type: TBD2 */
kevin1990 2:625a45555a85 1047 #define ENUM_CORE_FILTER_SELECT_FIR 0x00001800 /* ADC_Filter_Type: FIR Filter */
kevin1990 2:625a45555a85 1048
kevin1990 2:625a45555a85 1049 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1050 CORE_SETTLING_TIME[n] Pos/Masks Description
kevin1990 2:625a45555a85 1051 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1052 #define BITP_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Settling Time to Allow When Switching to Channel */
kevin1990 2:625a45555a85 1053 #define BITM_CORE_SETTLING_TIME_SETTLING_TIME 0x0000FFFF /* Settling Time to Allow When Switching to Channel */
kevin1990 2:625a45555a85 1054
kevin1990 2:625a45555a85 1055 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1056 CORE_HIGH_THRESHOLD_LIMIT[n] Pos/Masks Description
kevin1990 2:625a45555a85 1057 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1058 #define BITP_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0 /* Upper Limit for Sensor Alert Comparison */
kevin1990 2:625a45555a85 1059 #define BITM_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0xFFFFFFFF /* Upper Limit for Sensor Alert Comparison */
kevin1990 2:625a45555a85 1060
kevin1990 2:625a45555a85 1061 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1062 CORE_LOW_THRESHOLD_LIMIT[n] Pos/Masks Description
kevin1990 2:625a45555a85 1063 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1064 #define BITP_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0 /* Lower Limit for Sensor Alert Comparison */
kevin1990 2:625a45555a85 1065 #define BITM_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0xFFFFFFFF /* Lower Limit for Sensor Alert Comparison */
kevin1990 2:625a45555a85 1066
kevin1990 2:625a45555a85 1067 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1068 CORE_DIGITAL_SENSOR_ADDRESS[n] Pos/Masks Description
kevin1990 2:625a45555a85 1069 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1070 #define BITP_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0 /* I2C Address or Write Address Command for SPI Sensor */
kevin1990 2:625a45555a85 1071 #define BITM_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0x000000FF /* I2C Address or Write Address Command for SPI Sensor */
kevin1990 2:625a45555a85 1072
kevin1990 2:625a45555a85 1073 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1074 CORE_DIGITAL_SENSOR_COMMAND1[n] Pos/Masks Description
kevin1990 2:625a45555a85 1075 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1076 #define BITP_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0 /* Command to Send to Digital I2C/SPI Sensor */
kevin1990 2:625a45555a85 1077 #define BITM_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0x000000FF /* Command to Send to Digital I2C/SPI Sensor */
kevin1990 2:625a45555a85 1078
kevin1990 2:625a45555a85 1079 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1080 CORE_DIGITAL_SENSOR_COMMAND2[n] Pos/Masks Description
kevin1990 2:625a45555a85 1081 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1082 #define BITP_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0 /* Command to Send to Digital I2C/SPI Sensor */
kevin1990 2:625a45555a85 1083 #define BITM_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0x000000FF /* Command to Send to Digital I2C/SPI Sensor */
kevin1990 2:625a45555a85 1084
kevin1990 2:625a45555a85 1085 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1086 CORE_DIGITAL_SENSOR_COMMAND3[n] Pos/Masks Description
kevin1990 2:625a45555a85 1087 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1088 #define BITP_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0 /* Command to Send to Digital I2C/SPI Sensor */
kevin1990 2:625a45555a85 1089 #define BITM_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0x000000FF /* Command to Send to Digital I2C/SPI Sensor */
kevin1990 2:625a45555a85 1090
kevin1990 2:625a45555a85 1091 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1092 CORE_SENSOR_LUT_INDEX1[n] Pos/Masks Description
kevin1990 2:625a45555a85 1093 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1094 #define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX3 24 /* Pointer to LUT or Polynomial Correction for 4th Range */
kevin1990 2:625a45555a85 1095 #define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX2 16 /* Pointer to LUT or Polynomial Correction for 3rd Range */
kevin1990 2:625a45555a85 1096 #define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX1 8 /* Pointer to LUT or Polynomial Correction for 2nd Range */
kevin1990 2:625a45555a85 1097 #define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX0 0 /* Pointer to LUT or Polynomial Correction for 1st Range */
kevin1990 2:625a45555a85 1098 #define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX3 0x3F000000 /* Pointer to LUT or Polynomial Correction for 4th Range */
kevin1990 2:625a45555a85 1099 #define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX2 0x003F0000 /* Pointer to LUT or Polynomial Correction for 3rd Range */
kevin1990 2:625a45555a85 1100 #define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX1 0x00003F00 /* Pointer to LUT or Polynomial Correction for 2nd Range */
kevin1990 2:625a45555a85 1101 #define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX0 0x0000003F /* Pointer to LUT or Polynomial Correction for 1st Range */
kevin1990 2:625a45555a85 1102
kevin1990 2:625a45555a85 1103 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1104 CORE_SENSOR_LUT_INDEX2[n] Pos/Masks Description
kevin1990 2:625a45555a85 1105 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1106 #define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX7 24 /* Pointer to LUT or Polynomial Correction for 8th Range */
kevin1990 2:625a45555a85 1107 #define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX6 16 /* Pointer to LUT or Polynomial Correction for 7th Range */
kevin1990 2:625a45555a85 1108 #define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX5 8 /* Pointer to LUT or Polynomial Correction for 6th Range */
kevin1990 2:625a45555a85 1109 #define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX4 0 /* Pointer to LUT or Polynomial Correction for 5th Range */
kevin1990 2:625a45555a85 1110 #define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX7 0x3F000000 /* Pointer to LUT or Polynomial Correction for 8th Range */
kevin1990 2:625a45555a85 1111 #define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX6 0x003F0000 /* Pointer to LUT or Polynomial Correction for 7th Range */
kevin1990 2:625a45555a85 1112 #define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX5 0x00003F00 /* Pointer to LUT or Polynomial Correction for 6th Range */
kevin1990 2:625a45555a85 1113 #define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX4 0x0000003F /* Pointer to LUT or Polynomial Correction for 5th Range */
kevin1990 2:625a45555a85 1114
kevin1990 2:625a45555a85 1115
kevin1990 2:625a45555a85 1116 /* ============================================================================================================================
kevin1990 2:625a45555a85 1117 Test Registers
kevin1990 2:625a45555a85 1118 ============================================================================================================================ */
kevin1990 2:625a45555a85 1119
kevin1990 2:625a45555a85 1120 /* ============================================================================================================================
kevin1990 2:625a45555a85 1121 TEST
kevin1990 2:625a45555a85 1122 ============================================================================================================================ */
kevin1990 2:625a45555a85 1123 #define MOD_TEST_BASE 0x00000400 /* Test Registers */
kevin1990 2:625a45555a85 1124 #define MOD_TEST_MASK 0x00007FFF /* Test Registers */
kevin1990 2:625a45555a85 1125 #define REG_TEST_TEST_REG_0_RESET 0x00000000 /* Reset Value for test_reg_0 */
kevin1990 2:625a45555a85 1126 #define REG_TEST_TEST_REG_0 0x00000400 /* TEST Test Register 0 */
kevin1990 2:625a45555a85 1127
kevin1990 2:625a45555a85 1128 /* ============================================================================================================================
kevin1990 2:625a45555a85 1129 TEST Register BitMasks, Positions & Enumerations
kevin1990 2:625a45555a85 1130 ============================================================================================================================ */
kevin1990 2:625a45555a85 1131 /* -------------------------------------------------------------------------------------------------------------------------
kevin1990 2:625a45555a85 1132 TEST_TEST_REG_0 Pos/Masks Description
kevin1990 2:625a45555a85 1133 ------------------------------------------------------------------------------------------------------------------------- */
kevin1990 2:625a45555a85 1134 #define BITP_TEST_TEST_REG_0_TESTBIT6 7
kevin1990 2:625a45555a85 1135 #define BITP_TEST_TEST_REG_0_TESTBIT5 6
kevin1990 2:625a45555a85 1136 #define BITP_TEST_TEST_REG_0_TESTBIT4 5
kevin1990 2:625a45555a85 1137 #define BITP_TEST_TEST_REG_0_TESTBIT7 4
kevin1990 2:625a45555a85 1138 #define BITP_TEST_TEST_REG_0_TESTBIT3 3
kevin1990 2:625a45555a85 1139 #define BITP_TEST_TEST_REG_0_TESTBIT2 1
kevin1990 2:625a45555a85 1140 #define BITP_TEST_TEST_REG_0_TESTBIT1 0
kevin1990 2:625a45555a85 1141 #define BITM_TEST_TEST_REG_0_TESTBIT6 0x00000080
kevin1990 2:625a45555a85 1142 #define BITM_TEST_TEST_REG_0_TESTBIT5 0x00000040
kevin1990 2:625a45555a85 1143 #define BITM_TEST_TEST_REG_0_TESTBIT4 0x00000020
kevin1990 2:625a45555a85 1144 #define BITM_TEST_TEST_REG_0_TESTBIT7 0x00000010
kevin1990 2:625a45555a85 1145 #define BITM_TEST_TEST_REG_0_TESTBIT3 0x00000008
kevin1990 2:625a45555a85 1146 #define BITM_TEST_TEST_REG_0_TESTBIT2 0x00000006
kevin1990 2:625a45555a85 1147 #define BITM_TEST_TEST_REG_0_TESTBIT1 0x00000001
kevin1990 2:625a45555a85 1148
kevin1990 2:625a45555a85 1149
kevin1990 2:625a45555a85 1150 /* SPI Parameters */
kevin1990 2:625a45555a85 1151
kevin1990 2:625a45555a85 1152 /***** SPI */
kevin1990 2:625a45555a85 1153 #define PARAM_SPI_SPI_STANDARD "LPT" /* A part must declare which SPI Standard it follows, either ADI or LPT */
kevin1990 2:625a45555a85 1154 #define PARAM_SPI_CHIP_GRADE_VALUE 0 /* This is used to indicate speed grades/linearity. */
kevin1990 2:625a45555a85 1155 #define PARAM_SPI_CHIP_REVISION_VALUE 0 /* This is used to indicate the silicon revision */
kevin1990 2:625a45555a85 1156 #define PARAM_SPI_HAS_M_S_REGISTERS 0 /* If a design uses Master-Slave registers this must be set to true to enable relevant control bit fields */
kevin1990 2:625a45555a85 1157 #define PARAM_SPI_M_S_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS the M-S Transfer bit field */
kevin1990 2:625a45555a85 1158 #define PARAM_SPI_STREAM_MODE_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS of the stream mode transfer bit field */
kevin1990 2:625a45555a85 1159 #define PARAM_SPI_MSB_AND_LSB_FIRST_SUPPORT 0 /* Determines if the parts supports MSB and LSB first options */
kevin1990 2:625a45555a85 1160 #define PARAM_SPI_WIRE_MODE_SUPPORT "_4_WIRE" /* Configures which hardware SPI modes are supported */
kevin1990 2:625a45555a85 1161 #define PARAM_SPI_WIRE_MODE_DEFAULT "_4_WIRE" /* Sets the default hardware SPI mode */
kevin1990 2:625a45555a85 1162 #define PARAM_SPI_MULTI_IO_CHANNELS 1 /* Defines the number of SDIO pins supported by the SPI in Multi-IO Mode. Should be 1,2,4, or 8. */
kevin1990 2:625a45555a85 1163 #define PARAM_SPI_LPT_STANDARD_VERSION "REV1_0" /* This is a string from the LPT_STANDARD_VERSION_OPTIONS array for the active LPT SPI Standard version */
kevin1990 2:625a45555a85 1164 #define PARAM_SPI_HAS_CSB_PIN 1 /* Does the part have a csb pin? */
kevin1990 2:625a45555a85 1165 #define PARAM_SPI_BUS_MODE_SUPPORT 1 /* When set to true, Bus mode is supported. */
kevin1990 2:625a45555a85 1166 #define PARAM_SPI_ISOLATED_3_WIRE_SUPPORT 0 /* Does the part support the 3-wire isolate mode of operation */
kevin1990 2:625a45555a85 1167 #define PARAM_SPI_DAISY_CHAIN_MODE_SUPPORT 0 /* When set to true, Daisy chain mode is supported. */
kevin1990 2:625a45555a85 1168 #define PARAM_SPI_CHECK_GTE_1_MODE_SUPPORTED 1 /* This is used to check that at least mode is enabled */
kevin1990 2:625a45555a85 1169 #define PARAM_SPI_INTERFACE_MODE_SWITCH "None" /* Valid options are 'None', 'HW' or 'SW' */
kevin1990 2:625a45555a85 1170 #define PARAM_SPI_CRC_SUPPORT "CRC_CONFIGURABLE" /* Set to true to enable bit fields related to CRC. */
kevin1990 2:625a45555a85 1171 #define PARAM_SPI_CRC_SUPPORT_ENABLED 0 /* Verilog output parameter for 'define */
kevin1990 2:625a45555a85 1172 #define PARAM_SPI_CRC_SUPPORT_ENABLE 1 /* Configures if CRC features are enabled in the module */
kevin1990 2:625a45555a85 1173 #define PARAM_SPI_LPT_STANDARD_VERSION_VALUE 2 /* Index value of the active LPT SPI Standard version */
kevin1990 2:625a45555a85 1174 #define PARAM_SPI_ADDRESS_MODE_SUPPORT "_15_BIT" /* Configures which addressing modes are supported */
kevin1990 2:625a45555a85 1175 #define PARAM_SPI_ADDRESS_MODE_DEFAULT "_15_BIT" /* Sets the default addressing mode */
kevin1990 2:625a45555a85 1176 #define PARAM_SPI_ADDRESS_BUS_WIDTH 15 /* Verilog output parameter for 'define */
kevin1990 2:625a45555a85 1177 #define PARAM_SPI_SLOW_IFACE_CTRL_SUPPORT 0 /* Does the part support the Slow Interface Control feature */
kevin1990 2:625a45555a85 1178 #define PARAM_SPI_SOFT_RESET_0_BF_EXISTS 0 /* Used to control if the SOFT_RESET_0 bit field exists */
kevin1990 2:625a45555a85 1179 #define PARAM_SPI_SOFT_RESET_1_BF_EXISTS 0 /* Used to control if the SOFT_RESET_1 bit field exists */
kevin1990 2:625a45555a85 1180 #define PARAM_SPI_SEND_STATUS_SUPPORT "NO_SEND_STATUS" /* Determines if and how the part supports the SEND_STATUS feature */
kevin1990 2:625a45555a85 1181 #define PARAM_SPI_SEND_STATUS_SUPPORT_ENABLE 0 /* This is used to enable various send status features */
kevin1990 2:625a45555a85 1182 #define PARAM_SPI_SPI_STANDARD_VERSION_VALUE 2 /* Value for SPI Standard VERSION bit field */
kevin1990 2:625a45555a85 1183 #define PARAM_SPI_ENTITY_ACCESS_SUPPORT "ENTITY_ACCESS_ALWAYS" /* Configures which entity access mode(s) are supported */
kevin1990 2:625a45555a85 1184 #define PARAM_SPI_ENTITY_ACCESS_SUPPORT_ENABLE 1 /* This is used to enable/disable Strict Entity Access features */
kevin1990 2:625a45555a85 1185 #define PARAM_SPI_ENTITY_ACCESS_DEFAULT 1 /* Sets the default entity access mode */
kevin1990 2:625a45555a85 1186 #define PARAM_SPI_CHIP_INDEX_EXISTS 0 /* Used to control if the CHIP_INDEX register and related bit field exists */
kevin1990 2:625a45555a85 1187 #define PARAM_SPI_OFFSET_DEV_INDEX_EXISTS 0 /* Used to control if the OFFSET_DEV_INDEX bit field and registers exists */
kevin1990 2:625a45555a85 1188 #define PARAM_SPI_DEV_INDEX_EXISTS 0 /* Used to control if the DEV_INDEX bit field and register exists */
kevin1990 2:625a45555a85 1189 #define PARAM_SPI_STATUS_BIT_0_EXISTS 0 /* Sets EXIST for Status Bit 0 */
kevin1990 2:625a45555a85 1190 #define PARAM_SPI_STATUS_BIT_1_EXISTS 0 /* Sets EXIST for Status Bit 1 */
kevin1990 2:625a45555a85 1191 #define PARAM_SPI_STATUS_BIT_2_EXISTS 0 /* Sets EXIST for Status Bit 2 */
kevin1990 2:625a45555a85 1192 #define PARAM_SPI_STATUS_BIT_3_EXISTS 0 /* Sets EXIST for Status Bit 3 */
kevin1990 2:625a45555a85 1193 #define PARAM_SPI_STATUS_BIT_0_SWNAME "Status_Bit_0" /* Software Name for Status Bit 0 */
kevin1990 2:625a45555a85 1194 #define PARAM_SPI_STATUS_BIT_1_SWNAME "Status_Bit_1" /* Software Name for Status Bit 1 */
kevin1990 2:625a45555a85 1195 #define PARAM_SPI_STATUS_BIT_2_SWNAME "Status_Bit_2" /* Software Name for Status Bit 2 */
kevin1990 2:625a45555a85 1196 #define PARAM_SPI_STATUS_BIT_3_SWNAME "Status_Bit_3" /* Software Name for Status Bit 3 */
kevin1990 2:625a45555a85 1197 #define PARAM_SPI_CHIP_TYPE "P_ADC" /* This is a string that corresponds to one of the values in the CHIP_TYPE_OPTIONS array and corresponds to the type of chip being developed */
kevin1990 2:625a45555a85 1198 #define PARAM_SPI_CHIP_TYPE_VALUE 7 /* Integer value corresponding to selected CHIP_TYPE, and is used as bit field enum value */
kevin1990 2:625a45555a85 1199 #define PARAM_SPI_PRODUCT_ID_VALUE 32 /* This value is used to identify a specific generic. */
kevin1990 2:625a45555a85 1200 #define PARAM_SPI_PRODUCT_ID_TRIM_BITS 4 /* This defines the number of PRODUCT_ID bits that can be fuse/trimmed. */
kevin1990 2:625a45555a85 1201
kevin1990 2:625a45555a85 1202 #endif /* end ifndef _DEF_ADISENSE1000_REGISTERS_H */
kevin1990 2:625a45555a85 1203