SDMP_IOT
/
AdiSense1000_SmartBabySeat
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Fork of
Babyseat_NewFirmware_copy_sean
by 
Ross O'Halloran
Diff: inc/registers/ADISENSE1000_REGISTERS.h
- Revision:
- 2:625a45555a85
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/inc/registers/ADISENSE1000_REGISTERS.h Fri Aug 25 11:17:37 2017 +0000 @@ -0,0 +1,1203 @@ +/* ================================================================================ + + Created by : sherry + Created on : 2017 Jul 27, 19:13 IST + + Project : ADISENSE1000_REGISTERS + File : ADISENSE1000_REGISTERS.h + Description : Register Definitions + + !! ADI Confidential !! + INTERNAL USE ONLY + + Copyright (c) 2017 Analog Devices, Inc. All Rights Reserved. + This software is proprietary and confidential to Analog Devices, Inc. and + its licensors. + + This file was auto-generated. Do not make local changes to this file. + + Auto generation script information: + Script: /usr/cadtools/bin/yoda.dir/generators/inc/genHeaders + Last modified: 26-MAY-2017 + + ================================================================================ */ + +#ifndef _DEF_ADISENSE1000_REGISTERS_H +#define _DEF_ADISENSE1000_REGISTERS_H + +#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__)) +#include <stdint.h> +#endif /* _LANGUAGE_C */ + +#ifndef __ADI_GENERATED_DEF_HEADERS__ +#define __ADI_GENERATED_DEF_HEADERS__ 1 +#endif + +#define __ADI_HAS_CORE__ 1 +#define __ADI_HAS_SPI__ 1 +#define __ADI_HAS_TEST__ 1 + +/* ============================================================================================================================ + + ============================================================================================================================ */ + +/* ============================================================================================================================ + SPI + ============================================================================================================================ */ +#define MOD_SPI_BASE 0x00000000 /* */ +#define MOD_SPI_MASK 0x00007FFF /* */ +#define REG_SPI_INTERFACE_CONFIG_A_RESET 0x00000010 /* Reset Value for Interface_Config_A */ +#define REG_SPI_INTERFACE_CONFIG_A 0x00000000 +#define REG_SPI_INTERFACE_CONFIG_B_RESET 0x00000000 /* Reset Value for Interface_Config_B */ +#define REG_SPI_INTERFACE_CONFIG_B 0x00000001 +#define REG_SPI_DEVICE_CONFIG_RESET 0x00000000 /* Reset Value for Device_Config */ +#define REG_SPI_DEVICE_CONFIG 0x00000002 +#define REG_SPI_CHIP_TYPE_RESET 0x00000007 /* Reset Value for Chip_Type */ +#define REG_SPI_CHIP_TYPE 0x00000003 +#define REG_SPI_PRODUCT_ID_L_RESET 0x00000020 /* Reset Value for Product_ID_L */ +#define REG_SPI_PRODUCT_ID_L 0x00000004 +#define REG_SPI_PRODUCT_ID_H_RESET 0x00000000 /* Reset Value for Product_ID_H */ +#define REG_SPI_PRODUCT_ID_H 0x00000005 +#define REG_SPI_CHIP_GRADE_RESET 0x00000000 /* Reset Value for Chip_Grade */ +#define REG_SPI_CHIP_GRADE 0x00000006 +#define REG_SPI_SCRATCH_PAD_RESET 0x00000000 /* Reset Value for Scratch_Pad */ +#define REG_SPI_SCRATCH_PAD 0x0000000A +#define REG_SPI_SPI_REVISION_RESET 0x00000082 /* Reset Value for SPI_Revision */ +#define REG_SPI_SPI_REVISION 0x0000000B +#define REG_SPI_VENDOR_L_RESET 0x00000056 /* Reset Value for Vendor_L */ +#define REG_SPI_VENDOR_L 0x0000000C +#define REG_SPI_VENDOR_H_RESET 0x00000004 /* Reset Value for Vendor_H */ +#define REG_SPI_VENDOR_H 0x0000000D +#define REG_SPI_STREAM_MODE_RESET 0x00000000 /* Reset Value for Stream_Mode */ +#define REG_SPI_STREAM_MODE 0x0000000E +#define REG_SPI_INTERFACE_CONFIG_C_RESET 0x00000023 /* Reset Value for Interface_Config_C */ +#define REG_SPI_INTERFACE_CONFIG_C 0x00000010 +#define REG_SPI_INTERFACE_STATUS_A_RESET 0x00000000 /* Reset Value for Interface_Status_A */ +#define REG_SPI_INTERFACE_STATUS_A 0x00000011 + +/* ============================================================================================================================ + SPI Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_INTERFACE_CONFIG_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_INTERFACE_CONFIG_A_SW_RESET 7 +#define BITP_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 5 +#define BITP_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 4 +#define BITP_SPI_INTERFACE_CONFIG_A_SW_RESETX 0 +#define BITM_SPI_INTERFACE_CONFIG_A_SW_RESET 0x00000080 +#define BITM_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 0x00000020 +#define BITM_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 0x00000010 +#define BITM_SPI_INTERFACE_CONFIG_A_SW_RESETX 0x00000001 +#define ENUM_SPI_INTERFACE_CONFIG_A_DESCEND 0x00000000 +#define ENUM_SPI_INTERFACE_CONFIG_A_ASCEND 0x00000020 + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_INTERFACE_CONFIG_B Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_INTERFACE_CONFIG_B_SINGLE_INST 7 +#define BITM_SPI_INTERFACE_CONFIG_B_SINGLE_INST 0x00000080 + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_DEVICE_CONFIG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_DEVICE_CONFIG_OPERATING_MODES 0 +#define BITM_SPI_DEVICE_CONFIG_OPERATING_MODES 0x00000003 +#define ENUM_SPI_DEVICE_CONFIG_NORMAL 0x00000000 +#define ENUM_SPI_DEVICE_CONFIG_SLEEP 0x00000003 + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CHIP_TYPE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CHIP_TYPE_CHIP_TYPE 0 +#define BITM_SPI_CHIP_TYPE_CHIP_TYPE 0x0000000F + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_PRODUCT_ID_L Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 4 +#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0 +#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 0x000000F0 +#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0x0000000F + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_PRODUCT_ID_H Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0 +#define BITM_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0x000000FF + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_CHIP_GRADE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_CHIP_GRADE_GRADE 4 +#define BITP_SPI_CHIP_GRADE_DEVICE_REVISION 0 +#define BITM_SPI_CHIP_GRADE_GRADE 0x000000F0 +#define BITM_SPI_CHIP_GRADE_DEVICE_REVISION 0x0000000F + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_SCRATCH_PAD Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_SCRATCH_PAD_SCRATCH_VALUE 0 +#define BITM_SPI_SCRATCH_PAD_SCRATCH_VALUE 0x000000FF + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_SPI_REVISION Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_SPI_REVISION_SPI_TYPE 6 +#define BITP_SPI_SPI_REVISION_VERSION 0 +#define BITM_SPI_SPI_REVISION_SPI_TYPE 0x000000C0 +#define BITM_SPI_SPI_REVISION_VERSION 0x0000003F +#define ENUM_SPI_SPI_REVISION_ADI_SPI 0x00000000 +#define ENUM_SPI_SPI_REVISION_LPT_SPI 0x00000080 +#define ENUM_SPI_SPI_REVISION_REV1_0 0x00000002 /* Version: Revision 1.0 */ + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_VENDOR_L Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_VENDOR_L_VID 0 +#define BITM_SPI_VENDOR_L_VID 0x000000FF + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_VENDOR_H Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_VENDOR_H_VID 0 +#define BITM_SPI_VENDOR_H_VID 0x000000FF + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_STREAM_MODE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_STREAM_MODE_LOOP_COUNT 0 +#define BITM_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_INTERFACE_CONFIG_C Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 6 +#define BITP_SPI_INTERFACE_CONFIG_C_STRICT_ENTITY_ACCESS 5 +#define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0 +#define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 0x000000C0 +#define BITM_SPI_INTERFACE_CONFIG_C_STRICT_ENTITY_ACCESS 0x00000020 +#define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0x00000003 +#define ENUM_SPI_INTERFACE_CONFIG_C_DISABLED 0x00000000 +#define ENUM_SPI_INTERFACE_CONFIG_C_ENABLED 0x00000040 + +/* ------------------------------------------------------------------------------------------------------------------------- + SPI_INTERFACE_STATUS_A Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 7 +#define BITP_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 4 +#define BITP_SPI_INTERFACE_STATUS_A_CRC_ERROR 3 +#define BITP_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 2 +#define BITP_SPI_INTERFACE_STATUS_A_PARTIAL_REG_WR_ERROR 1 +#define BITP_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0 +#define BITM_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 0x00000080 +#define BITM_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 0x00000010 +#define BITM_SPI_INTERFACE_STATUS_A_CRC_ERROR 0x00000008 +#define BITM_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 0x00000004 +#define BITM_SPI_INTERFACE_STATUS_A_PARTIAL_REG_WR_ERROR 0x00000002 +#define BITM_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0x00000001 + + +/* ============================================================================================================================ + ADISENSE1000 Core Registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + CORE + ============================================================================================================================ */ +#define MOD_CORE_BASE 0x00000010 /* ADISENSE1000 Core Registers */ +#define MOD_CORE_MASK 0x00007FFF /* ADISENSE1000 Core Registers */ +#define REG_CORE_COMMAND_RESET 0x00000000 /* Reset Value for Command */ +#define REG_CORE_COMMAND 0x00000014 /* CORE Special Command */ +#define REG_CORE_MODE_RESET 0x00000000 /* Reset Value for Mode */ +#define REG_CORE_MODE 0x00000018 /* CORE Operating Mode and DRDY Control */ +#define REG_CORE_POWER_CONFIG_RESET 0x00000000 /* Reset Value for Power_Config */ +#define REG_CORE_POWER_CONFIG 0x00000019 /* CORE General Configuration */ +#define REG_CORE_CYCLE_CONTROL_RESET 0x00000000 /* Reset Value for Cycle_Control */ +#define REG_CORE_CYCLE_CONTROL 0x0000001A /* CORE Measurement Cycle */ +#define REG_CORE_FIFO_NUM_CYCLES_RESET 0x00000001 /* Reset Value for Fifo_Num_Cycles */ +#define REG_CORE_FIFO_NUM_CYCLES 0x0000001C /* CORE Number of Measurement Cycles to Store in FIFO */ +#define REG_CORE_MULTI_CYCLE_RATE_RESET 0x00000000 /* Reset Value for Multi_Cycle_Rate */ +#define REG_CORE_MULTI_CYCLE_RATE 0x0000001D /* CORE Time Between Repeats of Multi-Cycle Conversions.... */ +#define REG_CORE_STATUS_RESET 0x00000000 /* Reset Value for Status */ +#define REG_CORE_STATUS 0x00000020 /* CORE General Status */ +#define REG_CORE_DIAGNOSTICS_STATUS_RESET 0x00000000 /* Reset Value for Diagnostics_Status */ +#define REG_CORE_DIAGNOSTICS_STATUS 0x00000024 /* CORE Diagnostics Status */ +#define REG_CORE_CHANNEL_ALERT_STATUS_RESET 0x00000000 /* Reset Value for Channel_Alert_Status */ +#define REG_CORE_CHANNEL_ALERT_STATUS 0x00000026 /* CORE Alert Status Summary */ +#define REG_CORE_ALERT_DETAIL_CHn_RESET 0x00000000 /* Reset Value for Alert_Detail_Ch[n] */ +#define REG_CORE_ALERT_DETAIL_CH0_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH0 */ +#define REG_CORE_ALERT_DETAIL_CH1_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH1 */ +#define REG_CORE_ALERT_DETAIL_CH2_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH2 */ +#define REG_CORE_ALERT_DETAIL_CH3_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH3 */ +#define REG_CORE_ALERT_DETAIL_CH4_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH4 */ +#define REG_CORE_ALERT_DETAIL_CH5_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH5 */ +#define REG_CORE_ALERT_DETAIL_CH6_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH6 */ +#define REG_CORE_ALERT_DETAIL_CH7_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH7 */ +#define REG_CORE_ALERT_DETAIL_CH8_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH8 */ +#define REG_CORE_ALERT_DETAIL_CH9_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH9 */ +#define REG_CORE_ALERT_DETAIL_CH10_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH10 */ +#define REG_CORE_ALERT_DETAIL_CH11_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH11 */ +#define REG_CORE_ALERT_DETAIL_CH12_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH12 */ +#define REG_CORE_ALERT_DETAIL_CH0 0x00000028 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH1 0x00000029 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH2 0x0000002A /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH3 0x0000002B /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH4 0x0000002C /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH5 0x0000002D /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH6 0x0000002E /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH7 0x0000002F /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH8 0x00000030 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH9 0x00000031 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH10 0x00000032 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH11 0x00000033 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CH12 0x00000034 /* CORE Detailed Error Information */ +#define REG_CORE_ALERT_DETAIL_CHn(i) (REG_CORE_ALERT_DETAIL_CH0 + ((i) * 1)) +#define REG_CORE_ALERT_DETAIL_CHn_COUNT 13 +#define REG_CORE_EXTERNAL_REFERENCE1_RESET 0x00000000 /* Reset Value for External_Reference1 */ +#define REG_CORE_EXTERNAL_REFERENCE1 0x00000040 /* CORE External Reference Information */ +#define REG_CORE_EXTERNAL_REFERENCE2_RESET 0x00000000 /* Reset Value for External_Reference2 */ +#define REG_CORE_EXTERNAL_REFERENCE2 0x00000044 /* CORE External Reference Information */ +#define REG_CORE_DIAGNOSTICS_CONTROL_RESET 0x00000000 /* Reset Value for Diagnostics_Control */ +#define REG_CORE_DIAGNOSTICS_CONTROL 0x00000048 /* CORE Diagnostic Control */ +#define REG_CORE_DIAGNOSTICS_EXTRA_RESET 0x00000000 /* Reset Value for Diagnostics_Extra */ +#define REG_CORE_DIAGNOSTICS_EXTRA 0x00000049 /* CORE Extra Diagnostics Control */ +#define REG_CORE_DATA_FIFO_RESET 0x00000000 /* Reset Value for Data_FIFO */ +#define REG_CORE_DATA_FIFO 0x00000050 /* CORE FIFO of Sensor Results */ +#define REG_CORE_LUT_SELECT_RESET 0x00000000 /* Reset Value for LUT_Select */ +#define REG_CORE_LUT_SELECT 0x00000060 /* CORE Pointer to Custom Lookup Table or Polynomial */ +#define REG_CORE_LUT_OFFSET_RESET 0x00000000 /* Reset Value for LUT_Offset */ +#define REG_CORE_LUT_OFFSET 0x00000062 /* CORE Offset into Selected LUT */ +#define REG_CORE_LUT_DATA_RESET 0x00000000 /* Reset Value for LUT_Data */ +#define REG_CORE_LUT_DATA 0x00000064 /* CORE Data to Read/Write from Addressed LUT Entry */ +#define REG_CORE_CAL_SELECT_RESET 0x00000000 /* Reset Value for CAL_Select */ +#define REG_CORE_CAL_SELECT 0x00000068 /* CORE Pointer to Calibration Values */ +#define REG_CORE_CAL_OFFSET_RESET 0x00000000 /* Reset Value for CAL_Offset */ +#define REG_CORE_CAL_OFFSET 0x0000006A /* CORE Offset into Selected Calibration Values */ +#define REG_CORE_CAL_DATA_RESET 0x00000000 /* Reset Value for CAL_Data */ +#define REG_CORE_CAL_DATA 0x0000006C /* CORE Data to Read/Write from Addressed Calibration Values */ +#define REG_CORE_REVISION_RESET 0x00000000 /* Reset Value for Revision */ +#define REG_CORE_REVISION 0x0000007C /* CORE Hardware, Firmware Revision */ +#define REG_CORE_CHANNEL_COUNTn_RESET 0x00000000 /* Reset Value for Channel_Count[n] */ +#define REG_CORE_CHANNEL_COUNT0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT0 */ +#define REG_CORE_CHANNEL_COUNT1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT1 */ +#define REG_CORE_CHANNEL_COUNT2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT2 */ +#define REG_CORE_CHANNEL_COUNT3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT3 */ +#define REG_CORE_CHANNEL_COUNT4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT4 */ +#define REG_CORE_CHANNEL_COUNT5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT5 */ +#define REG_CORE_CHANNEL_COUNT6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT6 */ +#define REG_CORE_CHANNEL_COUNT7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT7 */ +#define REG_CORE_CHANNEL_COUNT8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT8 */ +#define REG_CORE_CHANNEL_COUNT9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT9 */ +#define REG_CORE_CHANNEL_COUNT10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT10 */ +#define REG_CORE_CHANNEL_COUNT0 0x00000090 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT1 0x000000D0 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT2 0x00000110 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT3 0x00000150 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT4 0x00000190 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT5 0x000001D0 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT6 0x00000210 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT7 0x00000250 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT8 0x00000290 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT9 0x000002D0 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNT10 0x00000310 /* CORE Number of Channel Occurrences per Measurement Cycle */ +#define REG_CORE_CHANNEL_COUNTn(i) (REG_CORE_CHANNEL_COUNT0 + ((i) * 64)) +#define REG_CORE_CHANNEL_COUNTn_COUNT 11 +#define REG_CORE_SENSOR_TYPEn_RESET 0x00000000 /* Reset Value for Sensor_Type[n] */ +#define REG_CORE_SENSOR_TYPE0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE0 */ +#define REG_CORE_SENSOR_TYPE1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE1 */ +#define REG_CORE_SENSOR_TYPE2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE2 */ +#define REG_CORE_SENSOR_TYPE3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE3 */ +#define REG_CORE_SENSOR_TYPE4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE4 */ +#define REG_CORE_SENSOR_TYPE5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE5 */ +#define REG_CORE_SENSOR_TYPE6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE6 */ +#define REG_CORE_SENSOR_TYPE7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE7 */ +#define REG_CORE_SENSOR_TYPE8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE8 */ +#define REG_CORE_SENSOR_TYPE9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE9 */ +#define REG_CORE_SENSOR_TYPE10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_TYPE10 */ +#define REG_CORE_SENSOR_TYPE0 0x00000092 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE1 0x000000D2 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE2 0x00000112 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE3 0x00000152 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE4 0x00000192 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE5 0x000001D2 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE6 0x00000212 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE7 0x00000252 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE8 0x00000292 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE9 0x000002D2 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPE10 0x00000312 /* CORE Sensor Select */ +#define REG_CORE_SENSOR_TYPEn(i) (REG_CORE_SENSOR_TYPE0 + ((i) * 64)) +#define REG_CORE_SENSOR_TYPEn_COUNT 11 +#define REG_CORE_SENSOR_DETAILSn_RESET 0x0000FF00 /* Reset Value for Sensor_Details[n] */ +#define REG_CORE_SENSOR_DETAILS0_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS0 */ +#define REG_CORE_SENSOR_DETAILS1_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS1 */ +#define REG_CORE_SENSOR_DETAILS2_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS2 */ +#define REG_CORE_SENSOR_DETAILS3_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS3 */ +#define REG_CORE_SENSOR_DETAILS4_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS4 */ +#define REG_CORE_SENSOR_DETAILS5_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS5 */ +#define REG_CORE_SENSOR_DETAILS6_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS6 */ +#define REG_CORE_SENSOR_DETAILS7_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS7 */ +#define REG_CORE_SENSOR_DETAILS8_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS8 */ +#define REG_CORE_SENSOR_DETAILS9_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS9 */ +#define REG_CORE_SENSOR_DETAILS10_RESET 0x0000FF00 /* Reset Value for REG_CORE_SENSOR_DETAILS10 */ +#define REG_CORE_SENSOR_DETAILS0 0x00000094 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS1 0x000000D4 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS2 0x00000114 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS3 0x00000154 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS4 0x00000194 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS5 0x000001D4 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS6 0x00000214 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS7 0x00000254 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS8 0x00000294 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS9 0x000002D4 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILS10 0x00000314 /* CORE Sensor Details */ +#define REG_CORE_SENSOR_DETAILSn(i) (REG_CORE_SENSOR_DETAILS0 + ((i) * 64)) +#define REG_CORE_SENSOR_DETAILSn_COUNT 11 +#define REG_CORE_CHANNEL_EXCITATIONn_RESET 0x00000000 /* Reset Value for Channel_Excitation[n] */ +#define REG_CORE_CHANNEL_EXCITATION0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION0 */ +#define REG_CORE_CHANNEL_EXCITATION1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION1 */ +#define REG_CORE_CHANNEL_EXCITATION2_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION2 */ +#define REG_CORE_CHANNEL_EXCITATION3_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION3 */ +#define REG_CORE_CHANNEL_EXCITATION4_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION4 */ +#define REG_CORE_CHANNEL_EXCITATION5_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION5 */ +#define REG_CORE_CHANNEL_EXCITATION6_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION6 */ +#define REG_CORE_CHANNEL_EXCITATION7_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION7 */ +#define REG_CORE_CHANNEL_EXCITATION8_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION8 */ +#define REG_CORE_CHANNEL_EXCITATION9_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION9 */ +#define REG_CORE_CHANNEL_EXCITATION10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_EXCITATION10 */ +#define REG_CORE_CHANNEL_EXCITATION0 0x00000098 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION1 0x000000D8 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION2 0x00000118 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION3 0x00000158 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION4 0x00000198 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION5 0x000001D8 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION6 0x00000218 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION7 0x00000258 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION8 0x00000298 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION9 0x000002D8 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATION10 0x00000318 /* CORE Excitation Current */ +#define REG_CORE_CHANNEL_EXCITATIONn(i) (REG_CORE_CHANNEL_EXCITATION0 + ((i) * 64)) +#define REG_CORE_CHANNEL_EXCITATIONn_COUNT 11 +#define REG_CORE_DIGITAL_SENSOR_CODINGn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Coding[n] */ +#define REG_CORE_DIGITAL_SENSOR_CODING0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING0 */ +#define REG_CORE_DIGITAL_SENSOR_CODING1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING1 */ +#define REG_CORE_DIGITAL_SENSOR_CODING2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING2 */ +#define REG_CORE_DIGITAL_SENSOR_CODING3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING3 */ +#define REG_CORE_DIGITAL_SENSOR_CODING4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING4 */ +#define REG_CORE_DIGITAL_SENSOR_CODING5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING5 */ +#define REG_CORE_DIGITAL_SENSOR_CODING6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING6 */ +#define REG_CORE_DIGITAL_SENSOR_CODING7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING7 */ +#define REG_CORE_DIGITAL_SENSOR_CODING8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING8 */ +#define REG_CORE_DIGITAL_SENSOR_CODING9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING9 */ +#define REG_CORE_DIGITAL_SENSOR_CODING10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CODING10 */ +#define REG_CORE_DIGITAL_SENSOR_CODING0 0x0000009A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING1 0x000000DA /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING2 0x0000011A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING3 0x0000015A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING4 0x0000019A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING5 0x000001DA /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING6 0x0000021A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING7 0x0000025A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING8 0x0000029A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING9 0x000002DA /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODING10 0x0000031A /* CORE Digital Sensor Data Coding */ +#define REG_CORE_DIGITAL_SENSOR_CODINGn(i) (REG_CORE_DIGITAL_SENSOR_CODING0 + ((i) * 64)) +#define REG_CORE_DIGITAL_SENSOR_CODINGn_COUNT 11 +#define REG_CORE_FILTER_SELECTn_RESET 0x00000000 /* Reset Value for Filter_Select[n] */ +#define REG_CORE_FILTER_SELECT0_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT0 */ +#define REG_CORE_FILTER_SELECT1_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT1 */ +#define REG_CORE_FILTER_SELECT2_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT2 */ +#define REG_CORE_FILTER_SELECT3_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT3 */ +#define REG_CORE_FILTER_SELECT4_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT4 */ +#define REG_CORE_FILTER_SELECT5_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT5 */ +#define REG_CORE_FILTER_SELECT6_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT6 */ +#define REG_CORE_FILTER_SELECT7_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT7 */ +#define REG_CORE_FILTER_SELECT8_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT8 */ +#define REG_CORE_FILTER_SELECT9_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT9 */ +#define REG_CORE_FILTER_SELECT10_RESET 0x00000000 /* Reset Value for REG_CORE_FILTER_SELECT10 */ +#define REG_CORE_FILTER_SELECT0 0x0000009C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT1 0x000000DC /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT2 0x0000011C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT3 0x0000015C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT4 0x0000019C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT5 0x000001DC /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT6 0x0000021C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT7 0x0000025C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT8 0x0000029C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT9 0x000002DC /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECT10 0x0000031C /* CORE ADC Digital Filter Selection */ +#define REG_CORE_FILTER_SELECTn(i) (REG_CORE_FILTER_SELECT0 + ((i) * 64)) +#define REG_CORE_FILTER_SELECTn_COUNT 11 +#define REG_CORE_SETTLING_TIMEn_RESET 0x00000000 /* Reset Value for Settling_Time[n] */ +#define REG_CORE_SETTLING_TIME0_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME0 */ +#define REG_CORE_SETTLING_TIME1_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME1 */ +#define REG_CORE_SETTLING_TIME2_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME2 */ +#define REG_CORE_SETTLING_TIME3_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME3 */ +#define REG_CORE_SETTLING_TIME4_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME4 */ +#define REG_CORE_SETTLING_TIME5_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME5 */ +#define REG_CORE_SETTLING_TIME6_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME6 */ +#define REG_CORE_SETTLING_TIME7_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME7 */ +#define REG_CORE_SETTLING_TIME8_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME8 */ +#define REG_CORE_SETTLING_TIME9_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME9 */ +#define REG_CORE_SETTLING_TIME10_RESET 0x00000000 /* Reset Value for REG_CORE_SETTLING_TIME10 */ +#define REG_CORE_SETTLING_TIME0 0x000000A0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME1 0x000000E0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME2 0x00000120 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME3 0x00000160 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME4 0x000001A0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME5 0x000001E0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME6 0x00000220 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME7 0x00000260 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME8 0x000002A0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME9 0x000002E0 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIME10 0x00000320 /* CORE Settling Time */ +#define REG_CORE_SETTLING_TIMEn(i) (REG_CORE_SETTLING_TIME0 + ((i) * 64)) +#define REG_CORE_SETTLING_TIMEn_COUNT 11 +#define REG_CORE_HIGH_THRESHOLD_LIMITn_RESET 0x00000000 /* Reset Value for High_Threshold_Limit[n] */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT0_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT0 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT1_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT1 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT2_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT2 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT3_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT3 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT4_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT4 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT5_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT5 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT6_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT6 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT7_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT7 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT8_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT8 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT9_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT9 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT10_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT10 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT11_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT11 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT12_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT12 */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT0 0x000000A4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT1 0x000000E4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT2 0x00000124 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT3 0x00000164 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT4 0x000001A4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT5 0x000001E4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT6 0x00000224 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT7 0x00000264 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT8 0x000002A4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT9 0x000002E4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT10 0x00000324 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT11 0x00000364 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMIT12 0x000003A4 /* CORE High Threshold */ +#define REG_CORE_HIGH_THRESHOLD_LIMITn(i) (REG_CORE_HIGH_THRESHOLD_LIMIT0 + ((i) * 64)) +#define REG_CORE_HIGH_THRESHOLD_LIMITn_COUNT 13 +#define REG_CORE_LOW_THRESHOLD_LIMITn_RESET 0x00000000 /* Reset Value for Low_Threshold_Limit[n] */ +#define REG_CORE_LOW_THRESHOLD_LIMIT0_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT0 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT1_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT1 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT2_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT2 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT3_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT3 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT4_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT4 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT5_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT5 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT6_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT6 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT7_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT7 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT8_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT8 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT9_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT9 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT10_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT10 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT11_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT11 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT12_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT12 */ +#define REG_CORE_LOW_THRESHOLD_LIMIT0 0x000000A8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT1 0x000000E8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT2 0x00000128 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT3 0x00000168 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT4 0x000001A8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT5 0x000001E8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT6 0x00000228 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT7 0x00000268 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT8 0x000002A8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT9 0x000002E8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT10 0x00000328 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT11 0x00000368 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMIT12 0x000003A8 /* CORE Low Threshold */ +#define REG_CORE_LOW_THRESHOLD_LIMITn(i) (REG_CORE_LOW_THRESHOLD_LIMIT0 + ((i) * 64)) +#define REG_CORE_LOW_THRESHOLD_LIMITn_COUNT 13 +#define REG_CORE_DIGITAL_SENSOR_ADDRESSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Address[n] */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS0 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS1 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS2 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS3 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS4 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS5 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS6 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS7 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS8 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS9 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_ADDRESS10 */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS0 0x000000AC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS1 0x000000EC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS2 0x0000012C /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS3 0x0000016C /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS4 0x000001AC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS5 0x000001EC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS6 0x0000022C /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS7 0x0000026C /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS8 0x000002AC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS9 0x000002EC /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESS10 0x0000032C /* CORE Sensor Address */ +#define REG_CORE_DIGITAL_SENSOR_ADDRESSn(i) (REG_CORE_DIGITAL_SENSOR_ADDRESS0 + ((i) * 64)) +#define REG_CORE_DIGITAL_SENSOR_ADDRESSn_COUNT 11 +#define REG_CORE_DIGITAL_SENSOR_COMMAND1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command1[n] */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND10 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND11 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND12 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND13_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND13 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND14_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND14 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND15_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND15 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND16_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND16 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND17_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND17 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND18_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND18 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND19_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND19 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND110_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND110 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND10 0x000000AD /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND11 0x000000ED /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND12 0x0000012D /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND13 0x0000016D /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND14 0x000001AD /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND15 0x000001ED /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND16 0x0000022D /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND17 0x0000026D /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND18 0x000002AD /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND19 0x000002ED /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND110 0x0000032D /* CORE Sensor Command1 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND1n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND10 + ((i) * 64)) +#define REG_CORE_DIGITAL_SENSOR_COMMAND1n_COUNT 11 +#define REG_CORE_DIGITAL_SENSOR_COMMAND2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command2[n] */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND20_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND20 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND21_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND21 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND22_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND22 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND23_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND23 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND24_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND24 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND25_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND25 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND26_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND26 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND27_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND27 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND28_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND28 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND29_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND29 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND210_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND210 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND20 0x000000AE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND21 0x000000EE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND22 0x0000012E /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND23 0x0000016E /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND24 0x000001AE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND25 0x000001EE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND26 0x0000022E /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND27 0x0000026E /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND28 0x000002AE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND29 0x000002EE /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND210 0x0000032E /* CORE Sensor Command2 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND2n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND20 + ((i) * 64)) +#define REG_CORE_DIGITAL_SENSOR_COMMAND2n_COUNT 11 +#define REG_CORE_DIGITAL_SENSOR_COMMAND3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command3[n] */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND30_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND30 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND31_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND31 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND32_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND32 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND33_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND33 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND34_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND34 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND35_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND35 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND36_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND36 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND37_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND37 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND38_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND38 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND39_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND39 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND310_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND310 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND30 0x000000AF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND31 0x000000EF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND32 0x0000012F /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND33 0x0000016F /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND34 0x000001AF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND35 0x000001EF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND36 0x0000022F /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND37 0x0000026F /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND38 0x000002AF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND39 0x000002EF /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND310 0x0000032F /* CORE Sensor Command3 */ +#define REG_CORE_DIGITAL_SENSOR_COMMAND3n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND30 + ((i) * 64)) +#define REG_CORE_DIGITAL_SENSOR_COMMAND3n_COUNT 11 +#define REG_CORE_SENSOR_LUT_INDEX1n_RESET 0x00000000 /* Reset Value for Sensor_LUT_Index1[n] */ +#define REG_CORE_SENSOR_LUT_INDEX10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX10 */ +#define REG_CORE_SENSOR_LUT_INDEX11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX11 */ +#define REG_CORE_SENSOR_LUT_INDEX12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX12 */ +#define REG_CORE_SENSOR_LUT_INDEX13_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX13 */ +#define REG_CORE_SENSOR_LUT_INDEX14_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX14 */ +#define REG_CORE_SENSOR_LUT_INDEX15_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX15 */ +#define REG_CORE_SENSOR_LUT_INDEX16_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX16 */ +#define REG_CORE_SENSOR_LUT_INDEX17_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX17 */ +#define REG_CORE_SENSOR_LUT_INDEX18_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX18 */ +#define REG_CORE_SENSOR_LUT_INDEX19_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX19 */ +#define REG_CORE_SENSOR_LUT_INDEX110_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX110 */ +#define REG_CORE_SENSOR_LUT_INDEX10 0x000000B0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX11 0x000000F0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX12 0x00000130 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX13 0x00000170 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX14 0x000001B0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX15 0x000001F0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX16 0x00000230 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX17 0x00000270 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX18 0x000002B0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX19 0x000002F0 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX110 0x00000330 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX1n(i) (REG_CORE_SENSOR_LUT_INDEX10 + ((i) * 64)) +#define REG_CORE_SENSOR_LUT_INDEX1n_COUNT 11 +#define REG_CORE_SENSOR_LUT_INDEX2n_RESET 0x00000000 /* Reset Value for Sensor_LUT_Index2[n] */ +#define REG_CORE_SENSOR_LUT_INDEX20_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX20 */ +#define REG_CORE_SENSOR_LUT_INDEX21_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX21 */ +#define REG_CORE_SENSOR_LUT_INDEX22_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX22 */ +#define REG_CORE_SENSOR_LUT_INDEX23_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX23 */ +#define REG_CORE_SENSOR_LUT_INDEX24_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX24 */ +#define REG_CORE_SENSOR_LUT_INDEX25_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX25 */ +#define REG_CORE_SENSOR_LUT_INDEX26_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX26 */ +#define REG_CORE_SENSOR_LUT_INDEX27_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX27 */ +#define REG_CORE_SENSOR_LUT_INDEX28_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX28 */ +#define REG_CORE_SENSOR_LUT_INDEX29_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX29 */ +#define REG_CORE_SENSOR_LUT_INDEX210_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_LUT_INDEX210 */ +#define REG_CORE_SENSOR_LUT_INDEX20 0x000000B4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX21 0x000000F4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX22 0x00000134 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX23 0x00000174 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX24 0x000001B4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX25 0x000001F4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX26 0x00000234 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX27 0x00000274 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX28 0x000002B4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX29 0x000002F4 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX210 0x00000334 /* CORE Sequence of Look-Up-Table Pointers */ +#define REG_CORE_SENSOR_LUT_INDEX2n(i) (REG_CORE_SENSOR_LUT_INDEX20 + ((i) * 64)) +#define REG_CORE_SENSOR_LUT_INDEX2n_COUNT 11 + +/* ============================================================================================================================ + CORE Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_COMMAND Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_COMMAND_SPECIAL_COMMAND 0 /* Special Command */ +#define BITM_CORE_COMMAND_SPECIAL_COMMAND 0x000000FF /* Special Command */ +#define ENUM_CORE_COMMAND_NOP 0x00000000 /* Special_Command: No Command */ +#define ENUM_CORE_COMMAND_CONVERT 0x00000001 /* Special_Command: Start ADC Conversions */ +#define ENUM_CORE_COMMAND_CONVERT_WITH_RAW 0x00000002 /* Special_Command: Start Conversions with Added RAW ADC Data */ +#define ENUM_CORE_COMMAND_RUN_DIAGNOSTICS 0x00000003 /* Special_Command: Initiate a Diagnostics Cycle */ +#define ENUM_CORE_COMMAND_LOAD_DEFAULTS 0x00000004 /* Special_Command: Load Relevant Registers With Default Values Appropriate to Sensor */ +#define ENUM_CORE_COMMAND_LOAD_CONFIG 0x00000005 /* Special_Command: Load Registers with Configuration from FLASH */ +#define ENUM_CORE_COMMAND_SAVE_CONFIG 0x00000006 /* Special_Command: Store Current Register Configuration to FLASH */ +#define ENUM_CORE_COMMAND_LATCH_CONFIG 0x00000007 /* Special_Command: Freeze Current Register Configuration and Prepare for Conversion */ +#define ENUM_CORE_COMMAND_LOAD_LUT 0x00000008 /* Special_Command: Load LUT from FLASH */ +#define ENUM_CORE_COMMAND_SAVE_LUT2 0x00000009 /* Special_Command: Save LUT to FLASH */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_MODE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_MODE_STDBY_EN 5 /* Standby */ +#define BITP_CORE_MODE_DRDY_MODE 2 /* Indicates Behavior of DRDY with Respect to FIFO State */ +#define BITP_CORE_MODE_CONVERSION_MODE 0 /* Conversion Mode */ +#define BITM_CORE_MODE_STDBY_EN 0x00000020 /* Standby */ +#define BITM_CORE_MODE_DRDY_MODE 0x0000000C /* Indicates Behavior of DRDY with Respect to FIFO State */ +#define BITM_CORE_MODE_CONVERSION_MODE 0x00000003 /* Conversion Mode */ +#define ENUM_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data Ready Per Conversion */ +#define ENUM_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data Ready Per Cycle */ +#define ENUM_CORE_MODE_DRDY_PER_FIFO_FILL 0x00000008 /* Drdy_Mode: Data Ready Per FIFO Fill */ +#define ENUM_CORE_MODE_DRDY_MODE3 0x0000000C /* Drdy_Mode: Undefined */ +#define ENUM_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single Cycle */ +#define ENUM_CORE_MODE_MULTICYCLE 0x00000001 /* Conversion_Mode: Multi Cycle */ +#define ENUM_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous Conversion */ +#define ENUM_CORE_MODE_MODE3 0x00000003 /* Conversion_Mode: Undefined */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_POWER_CONFIG Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_POWER_CONFIG_POWER_MODE_MCU 2 /* MCU Power Mode */ +#define BITP_CORE_POWER_CONFIG_POWER_MODE_ADC 0 /* ADC Power Mode */ +#define BITM_CORE_POWER_CONFIG_POWER_MODE_MCU 0x0000000C /* MCU Power Mode */ +#define BITM_CORE_POWER_CONFIG_POWER_MODE_ADC 0x00000003 /* ADC Power Mode */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CYCLE_CONTROL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 14 /* Units for Cycle Time */ +#define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME 0 /* Duration of a Full Measurement Cycle */ +#define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 0x0000C000 /* Units for Cycle Time */ +#define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME 0x00000FFF /* Duration of a Full Measurement Cycle */ +#define ENUM_CORE_CYCLE_CONTROL_MICROSECONDS 0x00000000 /* Cycle_Time_Units: Micro-Seconds */ +#define ENUM_CORE_CYCLE_CONTROL_MILLISECONDS 0x00004000 /* Cycle_Time_Units: Milli-Seconds */ +#define ENUM_CORE_CYCLE_CONTROL_SECONDS 0x00008000 /* Cycle_Time_Units: Seconds */ +#define ENUM_CORE_CYCLE_CONTROL_UNDEFINED 0x0000C000 /* Cycle_Time_Units: Undefined */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_FIFO_NUM_CYCLES Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0 /* How Many Cycles to Fill FIFO */ +#define BITM_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0x000000FF /* How Many Cycles to Fill FIFO */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_MULTI_CYCLE_RATE Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_MULTI_CYCLE_RATE_MULTI_CYCLE_RATE 0 /* CHANGE NAME. Defines Time Between Repetitions of FIFO Fill */ +#define BITM_CORE_MULTI_CYCLE_RATE_MULTI_CYCLE_RATE 0x000000FF /* CHANGE NAME. Defines Time Between Repetitions of FIFO Fill */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_STATUS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_STATUS_CMD_RUNNING 4 /* Indicates a Special Command is Active */ +#define BITP_CORE_STATUS_DRDY 3 /* Indicates a New Sensor (ADC?) Result is Available to Be Read */ +#define BITP_CORE_STATUS_ERROR 2 /* Indicates an Error */ +#define BITP_CORE_STATUS_ALERT 1 /* Indicates One or More Sensors are Outside Specified Limits */ +#define BITM_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates a Special Command is Active */ +#define BITM_CORE_STATUS_DRDY 0x00000008 /* Indicates a New Sensor (ADC?) Result is Available to Be Read */ +#define BITM_CORE_STATUS_ERROR 0x00000004 /* Indicates an Error */ +#define BITM_CORE_STATUS_ALERT 0x00000002 /* Indicates One or More Sensors are Outside Specified Limits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIAGNOSTICS_STATUS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIAGNOSTICS_STATUS_DIAGNOSTICS_STATUS 0 /* Diagnostics Status */ +#define BITM_CORE_DIAGNOSTICS_STATUS_DIAGNOSTICS_STATUS 0x0000FFFF /* Diagnostics Status */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CHANNEL_ALERT_STATUS Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 12 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 11 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 10 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 9 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 8 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 7 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 6 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 5 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 4 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 3 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 2 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 1 /* Indicates Channel is Outside Specified Limits */ +#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 0x00001000 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 0x00000800 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 0x00000400 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 0x00000200 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 0x00000100 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 0x00000080 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 0x00000040 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 0x00000020 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 0x00000010 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 0x00000008 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 0x00000004 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 0x00000002 /* Indicates Channel is Outside Specified Limits */ +#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0x00000001 /* Indicates Channel is Outside Specified Limits */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_ALERT_DETAIL_CH[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_ALERT_DETAIL_CH_REF_DETECT 6 /* Indicates Whether ADC Reference is Valid */ +#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 5 /* Indicates Sensor Input is Open Circuit */ +#define BITP_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 4 /* Indicates Sensor Result is Greater Than High Limit */ +#define BITP_CORE_ALERT_DETAIL_CH_LOW_LIMIT 3 /* Indicates Sensor Result is Less Than Low Limit */ +#define BITP_CORE_ALERT_DETAIL_CH_OVER_RANGE 2 /* Indicates Channel Over-Range */ +#define BITP_CORE_ALERT_DETAIL_CH_UNDER_RANGE 1 /* Indicates Channel Under-Range */ +#define BITP_CORE_ALERT_DETAIL_CH_TIME_OUT 0 /* Indicates Time-Out Error from Digital Sensor */ +#define BITM_CORE_ALERT_DETAIL_CH_REF_DETECT 0x00000040 /* Indicates Whether ADC Reference is Valid */ +#define BITM_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 0x00000020 /* Indicates Sensor Input is Open Circuit */ +#define BITM_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 0x00000010 /* Indicates Sensor Result is Greater Than High Limit */ +#define BITM_CORE_ALERT_DETAIL_CH_LOW_LIMIT 0x00000008 /* Indicates Sensor Result is Less Than Low Limit */ +#define BITM_CORE_ALERT_DETAIL_CH_OVER_RANGE 0x00000004 /* Indicates Channel Over-Range */ +#define BITM_CORE_ALERT_DETAIL_CH_UNDER_RANGE 0x00000002 /* Indicates Channel Under-Range */ +#define BITM_CORE_ALERT_DETAIL_CH_TIME_OUT 0x00000001 /* Indicates Time-Out Error from Digital Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_EXTERNAL_REFERENCE1 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0 /* Refin1 Value */ +#define BITM_CORE_EXTERNAL_REFERENCE1_EXT_REFIN1_VALUE 0xFFFFFFFF /* Refin1 Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_EXTERNAL_REFERENCE2 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0 /* Refin2 Value */ +#define BITM_CORE_EXTERNAL_REFERENCE2_EXT_REFIN2_VALUE 0xFFFFFFFF /* Refin2 Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIAGNOSTICS_CONTROL Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_OCD_FREQ 2 /* Diagnostics Open Circuit Detect Frequency */ +#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 1 /* Diagnostics Measure Enable */ +#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0 /* Diagnostics Global Enable */ +#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_OCD_FREQ 0x0000000C /* Diagnostics Open Circuit Detect Frequency */ +#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000002 /* Diagnostics Measure Enable */ +#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0x00000001 /* Diagnostics Global Enable */ +#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ0 0x00000000 +#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ1 0x00000004 +#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ2 0x00000008 +#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_FREQ3 0x0000000C + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIAGNOSTICS_EXTRA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIAGNOSTICS_EXTRA_DIAGNOSTICS_EXTRA 0 /* Additional Diagnostics Control */ +#define BITM_CORE_DIAGNOSTICS_EXTRA_DIAGNOSTICS_EXTRA 0x000000FF /* Additional Diagnostics Control */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DATA_FIFO Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DATA_FIFO_RAW_SAMPLE 40 /* ADC Result */ +#define BITP_CORE_DATA_FIFO_CH_VALID 39 /* Indicates Whether Valid Data Read from FIFO */ +#define BITP_CORE_DATA_FIFO_CH_RAW 38 /* Indicates If RAW Data is Valid */ +#define BITP_CORE_DATA_FIFO_CH_ALERT 37 /* Indicates Alert on Channel */ +#define BITP_CORE_DATA_FIFO_CH_ERROR 36 /* Indicates Error on Channel */ +#define BITP_CORE_DATA_FIFO_CHANNEL_ID 32 /* Indicates Which Channel This FIFO Data Corresponds to */ +#define BITP_CORE_DATA_FIFO_SENSOR_RESULT 0 /* Linearized and Compensated Sensor Result */ +#define BITM_CORE_DATA_FIFO_RAW_SAMPLE 0xFFFFFF0000000000 /* ADC Result */ +#define BITM_CORE_DATA_FIFO_CH_VALID 0x8000000000 /* Indicates Whether Valid Data Read from FIFO */ +#define BITM_CORE_DATA_FIFO_CH_RAW 0x4000000000 /* Indicates If RAW Data is Valid */ +#define BITM_CORE_DATA_FIFO_CH_ALERT 0x2000000000 /* Indicates Alert on Channel */ +#define BITM_CORE_DATA_FIFO_CH_ERROR 0x1000000000 /* Indicates Error on Channel */ +#define BITM_CORE_DATA_FIFO_CHANNEL_ID 0xF00000000 /* Indicates Which Channel This FIFO Data Corresponds to */ +#define BITM_CORE_DATA_FIFO_SENSOR_RESULT 0xFFFFFFFF /* Linearized and Compensated Sensor Result */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_LUT_SELECT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_LUT_SELECT_LUT_RW 7 /* Read or Write LUT Data */ +#define BITP_CORE_LUT_SELECT_LUT_TYPE 4 /* Indicates Whether Look-Up-Table or Polynomial Equation */ +#define BITP_CORE_LUT_SELECT_LUT_CHANNEL 0 /* Which Channel's LUT / Polynomial to Access */ +#define BITM_CORE_LUT_SELECT_LUT_RW 0x00000080 /* Read or Write LUT Data */ +#define BITM_CORE_LUT_SELECT_LUT_TYPE 0x00000070 /* Indicates Whether Look-Up-Table or Polynomial Equation */ +#define BITM_CORE_LUT_SELECT_LUT_CHANNEL 0x0000000F /* Which Channel's LUT / Polynomial to Access */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_LUT_OFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_LUT_OFFSET_LUT_OFFSET 0 /* Offset into Look-Up-Table */ +#define BITM_CORE_LUT_OFFSET_LUT_OFFSET 0x00003FFF /* Offset into Look-Up-Table */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_LUT_DATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_LUT_DATA_LUT_DATA 0 /* Data Byte to Write to / Read from Look-Up-Table */ +#define BITM_CORE_LUT_DATA_LUT_DATA 0x000000FF /* Data Byte to Write to / Read from Look-Up-Table */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CAL_SELECT Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CAL_SELECT_CAL_RW 7 /* Read or Write Calibration Data */ +#define BITP_CORE_CAL_SELECT_CAL_TYPE 4 /* NOT REQUIRED?? */ +#define BITP_CORE_CAL_SELECT_CAL_CHANNEL 0 /* Which Channel's Calibration Data to Access */ +#define BITM_CORE_CAL_SELECT_CAL_RW 0x00000080 /* Read or Write Calibration Data */ +#define BITM_CORE_CAL_SELECT_CAL_TYPE 0x00000070 /* NOT REQUIRED?? */ +#define BITM_CORE_CAL_SELECT_CAL_CHANNEL 0x0000000F /* Which Channel's Calibration Data to Access */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CAL_OFFSET Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CAL_OFFSET_CAL_OFFSET 0 /* Offset into Calibration Data */ +#define BITM_CORE_CAL_OFFSET_CAL_OFFSET 0x00003FFF /* Offset into Calibration Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CAL_DATA Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CAL_DATA_CAL_DATA 0 /* Data to Write to / Read from Calibration Data */ +#define BITM_CORE_CAL_DATA_CAL_DATA 0x000000FF /* Data to Write to / Read from Calibration Data */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_REVISION Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_REVISION_COMMS_PROTOCOL 16 /* ID Info */ +#define BITP_CORE_REVISION_HARDWARE_REVISION 8 /* ID Info */ +#define BITP_CORE_REVISION_FIRMWARE_REVISION 0 /* ID Info */ +#define BITM_CORE_REVISION_COMMS_PROTOCOL 0x00FF0000 /* ID Info */ +#define BITM_CORE_REVISION_HARDWARE_REVISION 0x0000FF00 /* ID Info */ +#define BITM_CORE_REVISION_FIRMWARE_REVISION 0x000000FF /* ID Info */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CHANNEL_COUNT[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 7 /* Enable Channel in Measurement Cycle */ +#define BITP_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0 /* How Many Times Channel Should Appear in One Cycle */ +#define BITM_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 0x00000080 /* Enable Channel in Measurement Cycle */ +#define BITM_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0x0000007F /* How Many Times Channel Should Appear in One Cycle */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_SENSOR_TYPE[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_SENSOR_TYPE_SENSOR_CATEGORY 13 /* Indicates Category of Sensor */ +#define BITP_CORE_SENSOR_TYPE_SENSOR_LOAD_DEFAULTS 12 /* Indicates to Use Default Register Values */ +#define BITP_CORE_SENSOR_TYPE_SENSOR_TYPE 0 /* Sensor Type */ +#define BITM_CORE_SENSOR_TYPE_SENSOR_CATEGORY 0x0000E000 /* Indicates Category of Sensor */ +#define BITM_CORE_SENSOR_TYPE_SENSOR_LOAD_DEFAULTS 0x00001000 /* Indicates to Use Default Register Values */ +#define BITM_CORE_SENSOR_TYPE_SENSOR_TYPE 0x00000FFF /* Sensor Type */ +#define ENUM_CORE_SENSOR_TYPE_ANALOG 0x00000000 +#define ENUM_CORE_SENSOR_TYPE_I2C 0x00002000 +#define ENUM_CORE_SENSOR_TYPE_SPI 0x00004000 +#define ENUM_CORE_SENSOR_TYPE_TBD3 0x00006000 +#define ENUM_CORE_SENSOR_TYPE_TBD4 0x00008000 +#define ENUM_CORE_SENSOR_TYPE_TBD5 0x0000A000 +#define ENUM_CORE_SENSOR_TYPE_TBD6 0x0000C000 +#define ENUM_CORE_SENSOR_TYPE_TBD7 0x0000E000 +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_T 0x00000000 /* Sensor_Type: Thermocouple T-Type Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_J 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_K 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_CUSTOM1 0x0000000E /* Sensor_Type: Thermocouple Custom Sensor1 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMOCOUPLE_CUSTOM2 0x0000000F /* Sensor_Type: Thermocouple Custom Sensor2 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT100 0x00000010 /* Sensor_Type: RTD 2 Wire PT100 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_PT1000 0x00000011 /* Sensor_Type: RTD 2 Wire PT1000 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_CUSTOM1 0x0000001E /* Sensor_Type: RTD 2 Wire Custom Sensor1 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_2W_CUSTOM2 0x0000001F /* Sensor_Type: RTD 2 Wire Custom Sensor2 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100 0x00000020 /* Sensor_Type: RTD 3 Wire PT100 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000 0x00000021 /* Sensor_Type: RTD 3 Wire PT1000 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT100_ONECONV 0x0000002C /* Sensor_Type: RTD 3 Wire PT100 No Chop Custom Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_PT1000_ONECONV 0x0000002D /* Sensor_Type: RTD 3 Wire PT1000 No Chop Custom Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_CUSTOM1 0x0000002E /* Sensor_Type: RTD 3 Wire Custom Sensor1 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_3W_CUSTOM2 0x0000002F /* Sensor_Type: RTD 3 Wire Custom Sensor2 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT100 0x00000030 /* Sensor_Type: RTD 4 Wire PT100 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_PT1000 0x00000031 /* Sensor_Type: RTD 4 Wire PT1000 Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_CUSTOM1 0x0000003E /* Sensor_Type: RTD 4 Wire Custom Sensor1 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_RTD_4W_CUSTOM2 0x0000003F /* Sensor_Type: RTD 4 Wire Custom Sensor2 */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_A_10K 0x00000040 /* Sensor_Type: Thermistor Type A 10kOhm Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_B_10K 0x00000041 /* Sensor_Type: Thermistor Type B 10kOhm Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_THERMISTOR_CUSTOM 0x0000004F /* Sensor_Type: Thermistor Custom Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W 0x00000050 /* Sensor_Type: Bridge 4 Wire Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_4W_CUSTOM 0x0000005F /* Sensor_Type: Bridge 4 Wire Custom Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W 0x00000060 /* Sensor_Type: Bridge 6 Wire Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_BRIDGE_6W_CUSTOM 0x0000006F /* Sensor_Type: Bridge 6 Wire Custom Sensor */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_VOLTAGE 0x00000070 /* Sensor_Type: Voltage Input */ +#define ENUM_CORE_SENSOR_TYPE_SENSOR_CURRENT 0x00000080 /* Sensor_Type: Current Input */ +#define ENUM_CORE_SENSOR_TYPE_CUSTOM 0x000000A0 /* Sensor_Type: Custom */ +#define ENUM_CORE_SENSOR_TYPE_I2C_PRESSURE1 0x00000800 /* Sensor_Type: I2C Pressure Sensor Type 1 */ +#define ENUM_CORE_SENSOR_TYPE_I2C_PRESSURE2 0x00000801 /* Sensor_Type: I2C Pressure Sensor Type 2 */ +#define ENUM_CORE_SENSOR_TYPE_SPI_PRESSURE1 0x00000C00 /* Sensor_Type: SPI Pressure Sensor Type 1 */ +#define ENUM_CORE_SENSOR_TYPE_SPI_PRESSURE2 0x00000C01 /* Sensor_Type: SPI Pressure Sensor Type 2 */ +#define ENUM_CORE_SENSOR_TYPE_SPI_ACCELEROMETER1 0x00000C02 /* Sensor_Type: SPI Accelerometer Sensor Type 1 3-Axis */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_SENSOR_DETAILS[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_SENSOR_DETAILS_AVERAGING 28 /* Number of ADC Results to Average */ +#define BITP_CORE_SENSOR_DETAILS_PGA_GAIN 24 /* PGA Gain */ +#define BITP_CORE_SENSOR_DETAILS_REFERENCE_SELECT 20 /* Reference Selection */ +#define BITP_CORE_SENSOR_DETAILS_VBIAS 19 /* Controls ADC Vbias Output */ +#define BITP_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 18 /* Enable or Disable ADC Reference Buffer */ +#define BITP_CORE_SENSOR_DETAILS_CJC_PUBLISH 17 /* Publish Compensation Data */ +#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_ONLY 16 /* Indicates to Use This Channel Only as Compensation */ +#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL3 12 /* Indicates Channel for Third Term of Compensation */ +#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL2 8 /* Indicates Channel for Second Term of Compensation */ +#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 4 /* Indicates Which Channel is Used to Compensate Sensor Result */ +#define BITP_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0 /* Units of Sensor Measurement */ +#define BITM_CORE_SENSOR_DETAILS_AVERAGING 0x70000000 /* Number of ADC Results to Average */ +#define BITM_CORE_SENSOR_DETAILS_PGA_GAIN 0x07000000 /* PGA Gain */ +#define BITM_CORE_SENSOR_DETAILS_REFERENCE_SELECT 0x00F00000 /* Reference Selection */ +#define BITM_CORE_SENSOR_DETAILS_VBIAS 0x00080000 /* Controls ADC Vbias Output */ +#define BITM_CORE_SENSOR_DETAILS_REFERENCE_BUFFER_DISABLE 0x00040000 /* Enable or Disable ADC Reference Buffer */ +#define BITM_CORE_SENSOR_DETAILS_CJC_PUBLISH 0x00020000 /* Publish Compensation Data */ +#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_ONLY 0x00010000 /* Indicates to Use This Channel Only as Compensation */ +#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL3 0x0000F000 /* Indicates Channel for Third Term of Compensation */ +#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL2 0x00000F00 /* Indicates Channel for Second Term of Compensation */ +#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 0x000000F0 /* Indicates Which Channel is Used to Compensate Sensor Result */ +#define BITM_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0x0000000F /* Units of Sensor Measurement */ +#define ENUM_CORE_SENSOR_DETAILS_REF_DEFAULT 0x00000000 /* Reference_Select: Default Based on Sensor Type */ +#define ENUM_CORE_SENSOR_DETAILS_REF_INT 0x00100000 /* Reference_Select: Internal Reference */ +#define ENUM_CORE_SENSOR_DETAILS_REF_RINT1 0x00200000 /* Reference_Select: Internal Resistor1 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_RINT2 0x00300000 /* Reference_Select: Internal Resistor2 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_REXT1 0x00400000 /* Reference_Select: External Resistor on Refin1 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_REXT2 0x00500000 /* Reference_Select: External Resistor on Refin2 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_VEXT1 0x00600000 /* Reference_Select: External Voltage on Refin1 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_VEXT2 0x00700000 /* Reference_Select: External Voltage on Refin2 */ +#define ENUM_CORE_SENSOR_DETAILS_REF_AVDD 0x00800000 /* Reference_Select: AVDD */ +#define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGC 0x00000000 /* Measurement_Units: Degrees C */ +#define ENUM_CORE_SENSOR_DETAILS_UNITS_DEGF 0x00000001 /* Measurement_Units: Degrees F */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_CHANNEL_EXCITATION[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_CHANNEL_EXCITATION_IOUT_DONTCHOP_3WIRE 7 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */ +#define BITP_CORE_CHANNEL_EXCITATION_IOUT1_DISABLE 4 /* NOT NEEDED?? Disable Second Current Source */ +#define BITP_CORE_CHANNEL_EXCITATION_IOUT0_DISABLE 3 /* NOT NEEDED?? Disable First Current Source */ +#define BITP_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0 /* Current Source Value */ +#define BITM_CORE_CHANNEL_EXCITATION_IOUT_DONTCHOP_3WIRE 0x00000080 /* Indicates 3-Wire Excitation Currents Should Not Be Swapped */ +#define BITM_CORE_CHANNEL_EXCITATION_IOUT1_DISABLE 0x00000010 /* NOT NEEDED?? Disable Second Current Source */ +#define BITM_CORE_CHANNEL_EXCITATION_IOUT0_DISABLE 0x00000008 /* NOT NEEDED?? Disable First Current Source */ +#define BITM_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0x00000007 /* Current Source Value */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIGITAL_SENSOR_CODING[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_MSB_POSITION 8 /* Position of Data MSB in the Read Frame */ +#define BITP_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_NUMBITS 2 /* Number of Relevant Data Bits in Digital Sensor */ +#define BITP_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_CODING 0 /* I2C Address or Write Address Command for SPI Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_MSB_POSITION 0x00001F00 /* Position of Data MSB in the Read Frame */ +#define BITM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_NUMBITS 0x0000007C /* Number of Relevant Data Bits in Digital Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_SENSOR_CODING 0x00000003 /* I2C Address or Write Address Command for SPI Sensor */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_8_BITS 0x00000000 /* Digital_Sensor_Numbits: 8 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_10_BITS 0x00000004 /* Digital_Sensor_Numbits: 10 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_12_BITS 0x00000008 /* Digital_Sensor_Numbits: 12 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_14_BITS 0x0000000C /* Digital_Sensor_Numbits: 14 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_16_BITS 0x00000010 /* Digital_Sensor_Numbits: 16 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_18_BITS 0x00000014 /* Digital_Sensor_Numbits: 18 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_20_BITS 0x00000018 /* Digital_Sensor_Numbits: 20 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_22_BITS 0x0000001C /* Digital_Sensor_Numbits: 22 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_DIGITAL_24_BITS 0x00000020 /* Digital_Sensor_Numbits: 24 Bits */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_CODING_UNIPOLAR 0x00000000 /* Digital_Sensor_Coding: Unipolar */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_CODING_TWOS_COMPL 0x00000001 /* Digital_Sensor_Coding: Twos Complement */ +#define ENUM_CORE_DIGITAL_SENSOR_CODING_CODING_OFFSET_BINARY 0x00000002 /* Digital_Sensor_Coding: Offset Binary */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_FILTER_SELECT[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_FILTER_SELECT_ADC_FIR_SEL 16 /* ADC Digital Filter FIR Type */ +#define BITP_CORE_FILTER_SELECT_ADC_FILTER_TYPE 11 /* ADC Digital Filter Type */ +#define BITP_CORE_FILTER_SELECT_ADC_FS 0 /* ADC Digital Filter Select */ +#define BITM_CORE_FILTER_SELECT_ADC_FIR_SEL 0x00070000 /* ADC Digital Filter FIR Type */ +#define BITM_CORE_FILTER_SELECT_ADC_FILTER_TYPE 0x00007800 /* ADC Digital Filter Type */ +#define BITM_CORE_FILTER_SELECT_ADC_FS 0x000007FF /* ADC Digital Filter Select */ +#define ENUM_CORE_FILTER_SELECT_SINC4 0x00000000 /* ADC_Filter_Type: Sinc4 Filter */ +#define ENUM_CORE_FILTER_SELECT_TBD1 0x00000800 /* ADC_Filter_Type: TBD1 */ +#define ENUM_CORE_FILTER_SELECT_TBD2 0x00001000 /* ADC_Filter_Type: TBD2 */ +#define ENUM_CORE_FILTER_SELECT_FIR 0x00001800 /* ADC_Filter_Type: FIR Filter */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_SETTLING_TIME[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Settling Time to Allow When Switching to Channel */ +#define BITM_CORE_SETTLING_TIME_SETTLING_TIME 0x0000FFFF /* Settling Time to Allow When Switching to Channel */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_HIGH_THRESHOLD_LIMIT[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0 /* Upper Limit for Sensor Alert Comparison */ +#define BITM_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0xFFFFFFFF /* Upper Limit for Sensor Alert Comparison */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_LOW_THRESHOLD_LIMIT[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0 /* Lower Limit for Sensor Alert Comparison */ +#define BITM_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0xFFFFFFFF /* Lower Limit for Sensor Alert Comparison */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIGITAL_SENSOR_ADDRESS[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0 /* I2C Address or Write Address Command for SPI Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0x000000FF /* I2C Address or Write Address Command for SPI Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIGITAL_SENSOR_COMMAND1[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0 /* Command to Send to Digital I2C/SPI Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0x000000FF /* Command to Send to Digital I2C/SPI Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIGITAL_SENSOR_COMMAND2[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0 /* Command to Send to Digital I2C/SPI Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0x000000FF /* Command to Send to Digital I2C/SPI Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_DIGITAL_SENSOR_COMMAND3[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0 /* Command to Send to Digital I2C/SPI Sensor */ +#define BITM_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0x000000FF /* Command to Send to Digital I2C/SPI Sensor */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_SENSOR_LUT_INDEX1[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX3 24 /* Pointer to LUT or Polynomial Correction for 4th Range */ +#define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX2 16 /* Pointer to LUT or Polynomial Correction for 3rd Range */ +#define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX1 8 /* Pointer to LUT or Polynomial Correction for 2nd Range */ +#define BITP_CORE_SENSOR_LUT_INDEX1_LUT_INDEX0 0 /* Pointer to LUT or Polynomial Correction for 1st Range */ +#define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX3 0x3F000000 /* Pointer to LUT or Polynomial Correction for 4th Range */ +#define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX2 0x003F0000 /* Pointer to LUT or Polynomial Correction for 3rd Range */ +#define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX1 0x00003F00 /* Pointer to LUT or Polynomial Correction for 2nd Range */ +#define BITM_CORE_SENSOR_LUT_INDEX1_LUT_INDEX0 0x0000003F /* Pointer to LUT or Polynomial Correction for 1st Range */ + +/* ------------------------------------------------------------------------------------------------------------------------- + CORE_SENSOR_LUT_INDEX2[n] Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX7 24 /* Pointer to LUT or Polynomial Correction for 8th Range */ +#define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX6 16 /* Pointer to LUT or Polynomial Correction for 7th Range */ +#define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX5 8 /* Pointer to LUT or Polynomial Correction for 6th Range */ +#define BITP_CORE_SENSOR_LUT_INDEX2_LUT_INDEX4 0 /* Pointer to LUT or Polynomial Correction for 5th Range */ +#define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX7 0x3F000000 /* Pointer to LUT or Polynomial Correction for 8th Range */ +#define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX6 0x003F0000 /* Pointer to LUT or Polynomial Correction for 7th Range */ +#define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX5 0x00003F00 /* Pointer to LUT or Polynomial Correction for 6th Range */ +#define BITM_CORE_SENSOR_LUT_INDEX2_LUT_INDEX4 0x0000003F /* Pointer to LUT or Polynomial Correction for 5th Range */ + + +/* ============================================================================================================================ + Test Registers + ============================================================================================================================ */ + +/* ============================================================================================================================ + TEST + ============================================================================================================================ */ +#define MOD_TEST_BASE 0x00000400 /* Test Registers */ +#define MOD_TEST_MASK 0x00007FFF /* Test Registers */ +#define REG_TEST_TEST_REG_0_RESET 0x00000000 /* Reset Value for test_reg_0 */ +#define REG_TEST_TEST_REG_0 0x00000400 /* TEST Test Register 0 */ + +/* ============================================================================================================================ + TEST Register BitMasks, Positions & Enumerations + ============================================================================================================================ */ +/* ------------------------------------------------------------------------------------------------------------------------- + TEST_TEST_REG_0 Pos/Masks Description + ------------------------------------------------------------------------------------------------------------------------- */ +#define BITP_TEST_TEST_REG_0_TESTBIT6 7 +#define BITP_TEST_TEST_REG_0_TESTBIT5 6 +#define BITP_TEST_TEST_REG_0_TESTBIT4 5 +#define BITP_TEST_TEST_REG_0_TESTBIT7 4 +#define BITP_TEST_TEST_REG_0_TESTBIT3 3 +#define BITP_TEST_TEST_REG_0_TESTBIT2 1 +#define BITP_TEST_TEST_REG_0_TESTBIT1 0 +#define BITM_TEST_TEST_REG_0_TESTBIT6 0x00000080 +#define BITM_TEST_TEST_REG_0_TESTBIT5 0x00000040 +#define BITM_TEST_TEST_REG_0_TESTBIT4 0x00000020 +#define BITM_TEST_TEST_REG_0_TESTBIT7 0x00000010 +#define BITM_TEST_TEST_REG_0_TESTBIT3 0x00000008 +#define BITM_TEST_TEST_REG_0_TESTBIT2 0x00000006 +#define BITM_TEST_TEST_REG_0_TESTBIT1 0x00000001 + + +/* SPI Parameters */ + +/***** SPI */ +#define PARAM_SPI_SPI_STANDARD "LPT" /* A part must declare which SPI Standard it follows, either ADI or LPT */ +#define PARAM_SPI_CHIP_GRADE_VALUE 0 /* This is used to indicate speed grades/linearity. */ +#define PARAM_SPI_CHIP_REVISION_VALUE 0 /* This is used to indicate the silicon revision */ +#define PARAM_SPI_HAS_M_S_REGISTERS 0 /* If a design uses Master-Slave registers this must be set to true to enable relevant control bit fields */ +#define PARAM_SPI_M_S_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS the M-S Transfer bit field */ +#define PARAM_SPI_STREAM_MODE_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS of the stream mode transfer bit field */ +#define PARAM_SPI_MSB_AND_LSB_FIRST_SUPPORT 0 /* Determines if the parts supports MSB and LSB first options */ +#define PARAM_SPI_WIRE_MODE_SUPPORT "_4_WIRE" /* Configures which hardware SPI modes are supported */ +#define PARAM_SPI_WIRE_MODE_DEFAULT "_4_WIRE" /* Sets the default hardware SPI mode */ +#define PARAM_SPI_MULTI_IO_CHANNELS 1 /* Defines the number of SDIO pins supported by the SPI in Multi-IO Mode. Should be 1,2,4, or 8. */ +#define PARAM_SPI_LPT_STANDARD_VERSION "REV1_0" /* This is a string from the LPT_STANDARD_VERSION_OPTIONS array for the active LPT SPI Standard version */ +#define PARAM_SPI_HAS_CSB_PIN 1 /* Does the part have a csb pin? */ +#define PARAM_SPI_BUS_MODE_SUPPORT 1 /* When set to true, Bus mode is supported. */ +#define PARAM_SPI_ISOLATED_3_WIRE_SUPPORT 0 /* Does the part support the 3-wire isolate mode of operation */ +#define PARAM_SPI_DAISY_CHAIN_MODE_SUPPORT 0 /* When set to true, Daisy chain mode is supported. */ +#define PARAM_SPI_CHECK_GTE_1_MODE_SUPPORTED 1 /* This is used to check that at least mode is enabled */ +#define PARAM_SPI_INTERFACE_MODE_SWITCH "None" /* Valid options are 'None', 'HW' or 'SW' */ +#define PARAM_SPI_CRC_SUPPORT "CRC_CONFIGURABLE" /* Set to true to enable bit fields related to CRC. */ +#define PARAM_SPI_CRC_SUPPORT_ENABLED 0 /* Verilog output parameter for 'define */ +#define PARAM_SPI_CRC_SUPPORT_ENABLE 1 /* Configures if CRC features are enabled in the module */ +#define PARAM_SPI_LPT_STANDARD_VERSION_VALUE 2 /* Index value of the active LPT SPI Standard version */ +#define PARAM_SPI_ADDRESS_MODE_SUPPORT "_15_BIT" /* Configures which addressing modes are supported */ +#define PARAM_SPI_ADDRESS_MODE_DEFAULT "_15_BIT" /* Sets the default addressing mode */ +#define PARAM_SPI_ADDRESS_BUS_WIDTH 15 /* Verilog output parameter for 'define */ +#define PARAM_SPI_SLOW_IFACE_CTRL_SUPPORT 0 /* Does the part support the Slow Interface Control feature */ +#define PARAM_SPI_SOFT_RESET_0_BF_EXISTS 0 /* Used to control if the SOFT_RESET_0 bit field exists */ +#define PARAM_SPI_SOFT_RESET_1_BF_EXISTS 0 /* Used to control if the SOFT_RESET_1 bit field exists */ +#define PARAM_SPI_SEND_STATUS_SUPPORT "NO_SEND_STATUS" /* Determines if and how the part supports the SEND_STATUS feature */ +#define PARAM_SPI_SEND_STATUS_SUPPORT_ENABLE 0 /* This is used to enable various send status features */ +#define PARAM_SPI_SPI_STANDARD_VERSION_VALUE 2 /* Value for SPI Standard VERSION bit field */ +#define PARAM_SPI_ENTITY_ACCESS_SUPPORT "ENTITY_ACCESS_ALWAYS" /* Configures which entity access mode(s) are supported */ +#define PARAM_SPI_ENTITY_ACCESS_SUPPORT_ENABLE 1 /* This is used to enable/disable Strict Entity Access features */ +#define PARAM_SPI_ENTITY_ACCESS_DEFAULT 1 /* Sets the default entity access mode */ +#define PARAM_SPI_CHIP_INDEX_EXISTS 0 /* Used to control if the CHIP_INDEX register and related bit field exists */ +#define PARAM_SPI_OFFSET_DEV_INDEX_EXISTS 0 /* Used to control if the OFFSET_DEV_INDEX bit field and registers exists */ +#define PARAM_SPI_DEV_INDEX_EXISTS 0 /* Used to control if the DEV_INDEX bit field and register exists */ +#define PARAM_SPI_STATUS_BIT_0_EXISTS 0 /* Sets EXIST for Status Bit 0 */ +#define PARAM_SPI_STATUS_BIT_1_EXISTS 0 /* Sets EXIST for Status Bit 1 */ +#define PARAM_SPI_STATUS_BIT_2_EXISTS 0 /* Sets EXIST for Status Bit 2 */ +#define PARAM_SPI_STATUS_BIT_3_EXISTS 0 /* Sets EXIST for Status Bit 3 */ +#define PARAM_SPI_STATUS_BIT_0_SWNAME "Status_Bit_0" /* Software Name for Status Bit 0 */ +#define PARAM_SPI_STATUS_BIT_1_SWNAME "Status_Bit_1" /* Software Name for Status Bit 1 */ +#define PARAM_SPI_STATUS_BIT_2_SWNAME "Status_Bit_2" /* Software Name for Status Bit 2 */ +#define PARAM_SPI_STATUS_BIT_3_SWNAME "Status_Bit_3" /* Software Name for Status Bit 3 */ +#define PARAM_SPI_CHIP_TYPE "P_ADC" /* This is a string that corresponds to one of the values in the CHIP_TYPE_OPTIONS array and corresponds to the type of chip being developed */ +#define PARAM_SPI_CHIP_TYPE_VALUE 7 /* Integer value corresponding to selected CHIP_TYPE, and is used as bit field enum value */ +#define PARAM_SPI_PRODUCT_ID_VALUE 32 /* This value is used to identify a specific generic. */ +#define PARAM_SPI_PRODUCT_ID_TRIM_BITS 4 /* This defines the number of PRODUCT_ID bits that can be fuse/trimmed. */ + +#endif /* end ifndef _DEF_ADISENSE1000_REGISTERS_H */ +