Pipe Inpection Robot / Mbed OS capstone_finish

capstone_finish

Dependencies:   BufferedSerial motor_sn7544

ov7670.h@10:ca4e4062701a, 2019-11-26 (annotated)

Committer:
Jeonghoon
Date:
Tue Nov 26 15:30:27 2019 +0000
Revision:
10:ca4e4062701a
Parent:
7:152fba230106 
capstone finish

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mio 0:f3f80a0695ff 1 #include "mbed.h"
mio 0:f3f80a0695ff 2 #include "ov7670reg.h"
mio 0:f3f80a0695ff 3
mio 0:f3f80a0695ff 4 #define OV7670_WRITE (0x42)
mio 0:f3f80a0695ff 5 #define OV7670_READ (0x43)
mio 0:f3f80a0695ff 6 #define OV7670_WRITEWAIT (20)
mio 0:f3f80a0695ff 7 #define OV7670_NOACK (0)
mio 0:f3f80a0695ff 8 #define OV7670_REGMAX (201)
kangmingyo 7:152fba230106 9 #define OV7670_I2CFREQ (10000)
mio 0:f3f80a0695ff 10
mio 0:f3f80a0695ff 11 //
mio 0:f3f80a0695ff 12 // OV7670 + FIFO AL422B camera board test
kangmingyo 7:152fba230106 13 //wen =1일 때 read시작 wen = 0일때 안읽음
kangmingyo 2:e98408458d2b 14 class OV7670
mio 0:f3f80a0695ff 15 {
mio 0:f3f80a0695ff 16 public:
kangmingyo 4:7b63cf3d205f 17 I2C _i2c ;
mio 0:f3f80a0695ff 18 InterruptIn vsync,href;
mio 0:f3f80a0695ff 19 DigitalOut wen ;
mio 0:f3f80a0695ff 20 PortIn data ;
kangmingyo 7:152fba230106 21 DigitalOut rrst,oe,rclk,wrst ;
mio 0:f3f80a0695ff 22 volatile int LineCounter ;
mio 0:f3f80a0695ff 23 volatile int LastLines ;
mio 0:f3f80a0695ff 24 volatile bool CaptureReq ;
mio 0:f3f80a0695ff 25 volatile bool Busy ;
mio 0:f3f80a0695ff 26 volatile bool Done ;
mio 0:f3f80a0695ff 27
mio 0:f3f80a0695ff 28 OV7670(
mio 0:f3f80a0695ff 29 PinName sda,// Camera I2C port
mio 0:f3f80a0695ff 30 PinName scl,// Camera I2C port
mio 0:f3f80a0695ff 31 PinName vs, // VSYNC
mio 0:f3f80a0695ff 32 PinName hr, // HREF
mio 0:f3f80a0695ff 33 PinName we, // WEN
mio 0:f3f80a0695ff 34 PortName port, // 8bit bus port
mio 0:f3f80a0695ff 35 int mask, // 0b0000_0M65_4000_0321_L000_0000_0000_0000 = 0x07878000
mio 0:f3f80a0695ff 36 PinName rt, // /RRST
mio 0:f3f80a0695ff 37 PinName o, // /OE
kangmingyo 7:152fba230106 38 PinName rc,
kangmingyo 7:152fba230106 39 PinName wt // RCLK
kangmingyo 7:152fba230106 40 ) : _i2c(sda,scl),vsync(vs),href(hr),wen(we),data(port,mask),rrst(rt),oe(o),rclk(rc),wrst(wt)
mio 0:f3f80a0695ff 41 {
kangmingyo 4:7b63cf3d205f 42 _i2c.stop() ;
kangmingyo 4:7b63cf3d205f 43 _i2c.frequency(OV7670_I2CFREQ) ;
mio 0:f3f80a0695ff 44 vsync.fall(this,&OV7670::VsyncHandler) ;
kangmingyo 7:152fba230106 45 // vsync.rise(this,&OV7670::VsyncHandler) ;
mio 0:f3f80a0695ff 46 CaptureReq = false ;
mio 0:f3f80a0695ff 47 Busy = false ;
mio 0:f3f80a0695ff 48 Done = false ;
mio 0:f3f80a0695ff 49 LineCounter = 0 ;
mio 0:f3f80a0695ff 50 rrst = 1 ;
kangmingyo 7:152fba230106 51
mio 0:f3f80a0695ff 52 oe = 1 ;
mio 0:f3f80a0695ff 53 rclk = 1 ;
mio 0:f3f80a0695ff 54 wen = 0 ;
mio 0:f3f80a0695ff 55 }
mio 0:f3f80a0695ff 56
mio 0:f3f80a0695ff 57 // capture request
mio 0:f3f80a0695ff 58 void CaptureNext(void)
mio 0:f3f80a0695ff 59 {
mio 0:f3f80a0695ff 60 CaptureReq = true ;
mio 0:f3f80a0695ff 61 Busy = true ;
mio 0:f3f80a0695ff 62 }
kangmingyo 2:e98408458d2b 63
mio 0:f3f80a0695ff 64 // capture done? (with clear)
mio 0:f3f80a0695ff 65 bool CaptureDone(void)
mio 0:f3f80a0695ff 66 {
mio 0:f3f80a0695ff 67 bool result ;
mio 0:f3f80a0695ff 68 if (Busy) {
mio 0:f3f80a0695ff 69 result = false ;
mio 0:f3f80a0695ff 70 } else {
mio 0:f3f80a0695ff 71 result = Done ;
mio 0:f3f80a0695ff 72 Done = false ;
mio 0:f3f80a0695ff 73 }
mio 0:f3f80a0695ff 74 return result ;
mio 0:f3f80a0695ff 75 }
mio 0:f3f80a0695ff 76
mio 0:f3f80a0695ff 77 // write to camera
mio 0:f3f80a0695ff 78 void WriteReg(int addr,int data)
mio 0:f3f80a0695ff 79 {
kangmingyo 7:152fba230106 80 wait_us(10);
kangmingyo 7:152fba230106 81 int status;
kangmingyo 7:152fba230106 82 char data_write[2];
kangmingyo 7:152fba230106 83 data_write[0]= addr;
kangmingyo 7:152fba230106 84 data_write[1]= data;
kangmingyo 7:152fba230106 85 status = _i2c.write(OV7670_WRITE,data_write,2,0);
kangmingyo 7:152fba230106 86 if(status!=0) {
kangmingyo 7:152fba230106 87 printf("I2C configuration error(adr: %x)!\r\n",addr);
kangmingyo 7:152fba230106 88 while(1) {
kangmingyo 7:152fba230106 89 }
kangmingyo 4:7b63cf3d205f 90 }
kangmingyo 4:7b63cf3d205f 91 }
mio 0:f3f80a0695ff 92
mio 0:f3f80a0695ff 93 // read from camera
mio 0:f3f80a0695ff 94 int ReadReg(int addr)
mio 0:f3f80a0695ff 95 {
kangmingyo 7:152fba230106 96 char data_write[2];
kangmingyo 7:152fba230106 97 char data_read[2];
kangmingyo 7:152fba230106 98 int data;
kangmingyo 7:152fba230106 99 int status;
kangmingyo 7:152fba230106 100
kangmingyo 7:152fba230106 101 data_write[0]=addr;
kangmingyo 7:152fba230106 102 _i2c.write(OV7670_WRITE, data_write, 1, 0);
kangmingyo 7:152fba230106 103 status =_i2c.read(OV7670_READ, data_read, 1, 0);
kangmingyo 7:152fba230106 104 data = (int)data_read[0];
kangmingyo 5:53dd2abce6b3 105 // printf("Data is %x\r\n",data);
kangmingyo 4:7b63cf3d205f 106 // printf("Status is %d\r\n",status);
mio 0:f3f80a0695ff 107 return data ;
mio 0:f3f80a0695ff 108 }
mio 0:f3f80a0695ff 109
kangmingyo 2:e98408458d2b 110 void Reset(void)
kangmingyo 2:e98408458d2b 111 {
kangmingyo 7:152fba230106 112
mio 0:f3f80a0695ff 113 WriteReg(0x12,0x80) ; // RESET CAMERA
mio 0:f3f80a0695ff 114 wait_ms(200) ;
kangmingyo 7:152fba230106 115 wait_us(1) ;
kangmingyo 7:152fba230106 116
mio 0:f3f80a0695ff 117 }
kangmingyo 2:e98408458d2b 118
kangmingyo 2:e98408458d2b 119 void InitQQVGA565(bool flipv,bool fliph)
kangmingyo 2:e98408458d2b 120 {
mio 0:f3f80a0695ff 121 // QQVGA RGB565
mio 0:f3f80a0695ff 122 WriteReg(REG_CLKRC,0x80);
kangmingyo 7:152fba230106 123 WriteReg(REG_COM11,0x0A) ;
mio 0:f3f80a0695ff 124 WriteReg(REG_TSLB,0x04);
mio 0:f3f80a0695ff 125 WriteReg(REG_COM7,0x04) ;
mio 0:f3f80a0695ff 126 WriteReg(REG_RGB444, 0x00);
mio 0:f3f80a0695ff 127 WriteReg(REG_COM15, 0xd0);
mio 0:f3f80a0695ff 128 WriteReg(REG_HSTART,0x16) ;
mio 0:f3f80a0695ff 129 WriteReg(REG_HSTOP,0x04) ;
mio 0:f3f80a0695ff 130 WriteReg(REG_HREF,0x24) ;
mio 0:f3f80a0695ff 131 WriteReg(REG_VSTART,0x02) ;
mio 0:f3f80a0695ff 132 WriteReg(REG_VSTOP,0x7a) ;
mio 0:f3f80a0695ff 133 WriteReg(REG_VREF,0x0a) ;
mio 0:f3f80a0695ff 134 WriteReg(REG_COM10,0x02) ;
mio 0:f3f80a0695ff 135 WriteReg(REG_COM3, 0x04);
mio 0:f3f80a0695ff 136 WriteReg(REG_COM14, 0x1a);
mio 1:509676f3be32 137 WriteReg(REG_MVFP,0x07 | (flipv ? 0x10:0) | (fliph ? 0x20:0)) ;
mio 0:f3f80a0695ff 138 WriteReg(0x72, 0x22);
mio 0:f3f80a0695ff 139 WriteReg(0x73, 0xf2);
mio 0:f3f80a0695ff 140
mio 0:f3f80a0695ff 141 // COLOR SETTING
mio 0:f3f80a0695ff 142 WriteReg(0x4f,0x80);
mio 0:f3f80a0695ff 143 WriteReg(0x50,0x80);
mio 0:f3f80a0695ff 144 WriteReg(0x51,0x00);
mio 0:f3f80a0695ff 145 WriteReg(0x52,0x22);
mio 0:f3f80a0695ff 146 WriteReg(0x53,0x5e);
mio 0:f3f80a0695ff 147 WriteReg(0x54,0x80);
mio 0:f3f80a0695ff 148 WriteReg(0x56,0x40);
mio 0:f3f80a0695ff 149 WriteReg(0x58,0x9e);
mio 0:f3f80a0695ff 150 WriteReg(0x59,0x88);
mio 0:f3f80a0695ff 151 WriteReg(0x5a,0x88);
mio 0:f3f80a0695ff 152 WriteReg(0x5b,0x44);
mio 0:f3f80a0695ff 153 WriteReg(0x5c,0x67);
mio 0:f3f80a0695ff 154 WriteReg(0x5d,0x49);
mio 0:f3f80a0695ff 155 WriteReg(0x5e,0x0e);
mio 0:f3f80a0695ff 156 WriteReg(0x69,0x00);
mio 0:f3f80a0695ff 157 WriteReg(0x6a,0x40);
mio 0:f3f80a0695ff 158 WriteReg(0x6b,0x0a);
mio 0:f3f80a0695ff 159 WriteReg(0x6c,0x0a);
mio 0:f3f80a0695ff 160 WriteReg(0x6d,0x55);
mio 0:f3f80a0695ff 161 WriteReg(0x6e,0x11);
mio 0:f3f80a0695ff 162 WriteReg(0x6f,0x9f);
mio 0:f3f80a0695ff 163
mio 0:f3f80a0695ff 164 WriteReg(0xb0,0x84);
kangmingyo 2:e98408458d2b 165 }
mio 0:f3f80a0695ff 166
kangmingyo 2:e98408458d2b 167 void InitQVGA565(bool flipv,bool fliph)
kangmingyo 2:e98408458d2b 168 {
mio 0:f3f80a0695ff 169 // QVGA RGB565
mio 0:f3f80a0695ff 170 WriteReg(REG_CLKRC,0x80);
mio 0:f3f80a0695ff 171 WriteReg(REG_COM11,0x0A) ;
mio 0:f3f80a0695ff 172 WriteReg(REG_TSLB,0x04);
mio 0:f3f80a0695ff 173 WriteReg(REG_COM7,0x04) ;
mio 0:f3f80a0695ff 174 WriteReg(REG_RGB444, 0x00);
mio 0:f3f80a0695ff 175 WriteReg(REG_COM15, 0xd0);
mio 0:f3f80a0695ff 176 WriteReg(REG_HSTART,0x16) ;
mio 0:f3f80a0695ff 177 WriteReg(REG_HSTOP,0x04) ;
mio 0:f3f80a0695ff 178 WriteReg(REG_HREF,0x80) ;
mio 0:f3f80a0695ff 179 WriteReg(REG_VSTART,0x02) ;
mio 0:f3f80a0695ff 180 WriteReg(REG_VSTOP,0x7a) ;
mio 0:f3f80a0695ff 181 WriteReg(REG_VREF,0x0a) ;
mio 0:f3f80a0695ff 182 WriteReg(REG_COM10,0x02) ;
mio 0:f3f80a0695ff 183 WriteReg(REG_COM3, 0x04);
mio 0:f3f80a0695ff 184 WriteReg(REG_COM14, 0x19);
mio 1:509676f3be32 185 WriteReg(REG_MVFP,0x07 | (flipv ? 0x10:0) | (fliph ? 0x20:0)) ;
mio 0:f3f80a0695ff 186 WriteReg(0x72, 0x11);
mio 0:f3f80a0695ff 187 WriteReg(0x73, 0xf1);
mio 0:f3f80a0695ff 188
mio 0:f3f80a0695ff 189 // COLOR SETTING
mio 0:f3f80a0695ff 190 WriteReg(0x4f,0x80);
mio 0:f3f80a0695ff 191 WriteReg(0x50,0x80);
mio 0:f3f80a0695ff 192 WriteReg(0x51,0x00);
mio 0:f3f80a0695ff 193 WriteReg(0x52,0x22);
mio 0:f3f80a0695ff 194 WriteReg(0x53,0x5e);
mio 0:f3f80a0695ff 195 WriteReg(0x54,0x80);
mio 0:f3f80a0695ff 196 WriteReg(0x56,0x40);
mio 0:f3f80a0695ff 197 WriteReg(0x58,0x9e);
mio 0:f3f80a0695ff 198 WriteReg(0x59,0x88);
mio 0:f3f80a0695ff 199 WriteReg(0x5a,0x88);
mio 0:f3f80a0695ff 200 WriteReg(0x5b,0x44);
mio 0:f3f80a0695ff 201 WriteReg(0x5c,0x67);
mio 0:f3f80a0695ff 202 WriteReg(0x5d,0x49);
mio 0:f3f80a0695ff 203 WriteReg(0x5e,0x0e);
mio 0:f3f80a0695ff 204 WriteReg(0x69,0x00);
mio 0:f3f80a0695ff 205 WriteReg(0x6a,0x40);
mio 0:f3f80a0695ff 206 WriteReg(0x6b,0x0a);
mio 0:f3f80a0695ff 207 WriteReg(0x6c,0x0a);
mio 0:f3f80a0695ff 208 WriteReg(0x6d,0x55);
mio 0:f3f80a0695ff 209 WriteReg(0x6e,0x11);
mio 0:f3f80a0695ff 210 WriteReg(0x6f,0x9f);
mio 0:f3f80a0695ff 211
mio 0:f3f80a0695ff 212 WriteReg(0xb0,0x84);
kangmingyo 2:e98408458d2b 213 }
kangmingyo 6:fe8b32cb9357 214 void InitQQVGAYUV(bool flipv,bool fliph)
kangmingyo 7:152fba230106 215 {
kangmingyo 7:152fba230106 216 WriteReg(REG_COM10,0x02) ;
kangmingyo 7:152fba230106 217 // WriteReg(0x11,0x81);
kangmingyo 7:152fba230106 218 WriteReg(REG_HSTART,0x16) ;
kangmingyo 7:152fba230106 219 WriteReg(REG_HSTOP,0x04) ;
kangmingyo 7:152fba230106 220 WriteReg(REG_HREF,0x24) ;
kangmingyo 7:152fba230106 221 WriteReg(REG_VSTART,0x02) ;
kangmingyo 7:152fba230106 222 WriteReg(REG_VSTOP,0x7a) ;
kangmingyo 7:152fba230106 223 WriteReg(REG_VREF,0x0a) ;
kangmingyo 7:152fba230106 224 WriteReg(REG_COM14, 0x1a);
kangmingyo 7:152fba230106 225 WriteReg(0x72, 0x22);
kangmingyo 7:152fba230106 226 WriteReg(0x73, 0xf2);
kangmingyo 7:152fba230106 227 WriteReg(0x70,0x3A);
kangmingyo 7:152fba230106 228 WriteReg(0x71,0x35);
kangmingyo 7:152fba230106 229 WriteReg(REG_TSLB,0x0C);
kangmingyo 7:152fba230106 230 WriteReg(0xA2,0x02);
kangmingyo 7:152fba230106 231
kangmingyo 7:152fba230106 232
kangmingyo 2:e98408458d2b 233 WriteReg(REG_COM7, 0x00); // YUV
kangmingyo 2:e98408458d2b 234 WriteReg(REG_COM17, 0x00); // color bar disable
kangmingyo 5:53dd2abce6b3 235 WriteReg(REG_COM3, 0x04);
kangmingyo 7:152fba230106 236 WriteReg(0x8C, 0x00);//RGB444
kangmingyo 7:152fba230106 237 WriteReg(0x04, 0x00);//COM1
kangmingyo 7:152fba230106 238 WriteReg(0x40, 0xC0);//COM15
kangmingyo 2:e98408458d2b 239 WriteReg(0x14, 0x1A);//COM9
kangmingyo 2:e98408458d2b 240 WriteReg(0x3D, 0x40);//COM13
kangmingyo 7:152fba230106 241
kangmingyo 6:fe8b32cb9357 242
kangmingyo 7:152fba230106 243 /* END MARKER */
kangmingyo 2:e98408458d2b 244 }
mio 0:f3f80a0695ff 245
mio 0:f3f80a0695ff 246
mio 0:f3f80a0695ff 247 // vsync handler
mio 0:f3f80a0695ff 248 void VsyncHandler(void)
mio 0:f3f80a0695ff 249 {
mio 0:f3f80a0695ff 250 // Capture Enable
mio 0:f3f80a0695ff 251 if (CaptureReq) {
kangmingyo 7:152fba230106 252 wrst=0;
kangmingyo 7:152fba230106 253 wait_us(1);
mio 0:f3f80a0695ff 254 wen = 1 ;
kangmingyo 7:152fba230106 255 wrst=1;
mio 0:f3f80a0695ff 256 Done = false ;
mio 0:f3f80a0695ff 257 CaptureReq = false ;
mio 0:f3f80a0695ff 258 } else {
mio 0:f3f80a0695ff 259 wen = 0 ;
kangmingyo 7:152fba230106 260 if (Busy) { //next exit
mio 0:f3f80a0695ff 261 Busy = false ;
mio 0:f3f80a0695ff 262 Done = true ;
mio 0:f3f80a0695ff 263 }
mio 0:f3f80a0695ff 264 }
mio 0:f3f80a0695ff 265
mio 0:f3f80a0695ff 266 // Hline Counter
mio 0:f3f80a0695ff 267 LastLines = LineCounter ;
mio 0:f3f80a0695ff 268 LineCounter = 0 ;
mio 0:f3f80a0695ff 269 }
kangmingyo 2:e98408458d2b 270
mio 0:f3f80a0695ff 271 // href handler
mio 0:f3f80a0695ff 272 void HrefHandler(void)
mio 0:f3f80a0695ff 273 {
mio 0:f3f80a0695ff 274 LineCounter++ ;
mio 0:f3f80a0695ff 275 }
kangmingyo 2:e98408458d2b 276
mio 0:f3f80a0695ff 277 // Data Read
mio 0:f3f80a0695ff 278 int ReadOneByte(void)
mio 0:f3f80a0695ff 279 {
mio 0:f3f80a0695ff 280 int result ;
mio 0:f3f80a0695ff 281 rclk = 1 ;
kangmingyo 7:152fba230106 282 wait_us(1);
kangmingyo 7:152fba230106 283 result = data.read() ;
mio 0:f3f80a0695ff 284 rclk = 0 ;
mio 0:f3f80a0695ff 285 return result ;
mio 0:f3f80a0695ff 286 }
mio 0:f3f80a0695ff 287
mio 0:f3f80a0695ff 288 // Data Read (PortIn)
kangmingyo 4:7b63cf3d205f 289 int ReadOneWord(void)
mio 0:f3f80a0695ff 290 {
kangmingyo 2:e98408458d2b 291 // int r,r1,r2,r3,r4 ;
kangmingyo 2:e98408458d2b 292 // rclk = 1 ;
kangmingyo 2:e98408458d2b 293 // r = data ;
kangmingyo 2:e98408458d2b 294 // rclk = 0 ;
kangmingyo 2:e98408458d2b 295 // r1 = r & 0x07800000 ;
kangmingyo 2:e98408458d2b 296 // r1 = r1 >> (26-7-0) ; // bit26 to bit7
kangmingyo 2:e98408458d2b 297 // r2 = r & 0x00078000 ;
kangmingyo 2:e98408458d2b 298 // r2 = r2 >> (18-3-0) ; // bit18 to bit3
kangmingyo 2:e98408458d2b 299 // rclk = 1 ;
kangmingyo 2:e98408458d2b 300 // r = data ;
kangmingyo 2:e98408458d2b 301 // rclk = 0 ;
kangmingyo 2:e98408458d2b 302 // r3 = r & 0x07800000 ;
kangmingyo 2:e98408458d2b 303 // r3 = r3 >> (26-7-8) ; // bit26 to bit7
kangmingyo 2:e98408458d2b 304 // r4 = r & 0x00078000 ;
kangmingyo 2:e98408458d2b 305 // r4 = r4 >> (18-3-8) ; // bit18 to bit3
kangmingyo 2:e98408458d2b 306
kangmingyo 2:e98408458d2b 307 int r,r1,r2;
kangmingyo 2:e98408458d2b 308 rclk=1;
kangmingyo 7:152fba230106 309 wait_us(1);
kangmingyo 7:152fba230106 310 r = data.read();
kangmingyo 2:e98408458d2b 311 rclk=0;
kangmingyo 7:152fba230106 312 // wait_us(50);
kangmingyo 7:152fba230106 313 r1 = r;
kangmingyo 7:152fba230106 314 wait_us(1);
kangmingyo 2:e98408458d2b 315 rclk=1;
kangmingyo 7:152fba230106 316 wait_us(1);
kangmingyo 7:152fba230106 317 r= data.read();
kangmingyo 2:e98408458d2b 318 rclk=0;
kangmingyo 2:e98408458d2b 319 r2 = r;
kangmingyo 2:e98408458d2b 320
kangmingyo 7:152fba230106 321 // wait_us(50);
kangmingyo 7:152fba230106 322 return r2 ;
mio 0:f3f80a0695ff 323 }
kangmingyo 2:e98408458d2b 324
mio 0:f3f80a0695ff 325 // Data Start
mio 0:f3f80a0695ff 326 void ReadStart(void)
kangmingyo 2:e98408458d2b 327 {
kangmingyo 7:152fba230106 328 rrst=0;
mio 0:f3f80a0695ff 329 oe = 0 ;
mio 0:f3f80a0695ff 330 rclk = 0 ;
kangmingyo 7:152fba230106 331 wait_us(1);
kangmingyo 7:152fba230106 332 rclk = 1 ;
mio 0:f3f80a0695ff 333 wait_us(1) ;
kangmingyo 7:152fba230106 334 rclk = 0 ;
kangmingyo 7:152fba230106 335 rrst=1;
kangmingyo 7:152fba230106 336
kangmingyo 7:152fba230106 337 // wait_us(1);
kangmingyo 7:152fba230106 338
mio 0:f3f80a0695ff 339 }
kangmingyo 2:e98408458d2b 340
mio 0:f3f80a0695ff 341 // Data Stop
mio 0:f3f80a0695ff 342 void ReadStop(void)
mio 0:f3f80a0695ff 343 {
mio 0:f3f80a0695ff 344 oe = 1 ;
mio 0:f3f80a0695ff 345 ReadOneByte() ;
mio 0:f3f80a0695ff 346 rclk = 1 ;
mio 0:f3f80a0695ff 347 }
mio 0:f3f80a0695ff 348 };
kangmingyo 7:152fba230106 349