Pipe Inpection Robot / Mbed OS capstone_finish

capstone_finish

Dependencies:   BufferedSerial motor_sn7544

ov7670.h@1:509676f3be32, 2012-02-17 (annotated)

Committer:
mio
Date:
Fri Feb 17 15:06:15 2012 +0000
Revision:
1:509676f3be32
Parent:
0:f3f80a0695ff
Child:
2:e98408458d2b
Hflip Vflip init param support.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mio 0:f3f80a0695ff 1 #include "mbed.h"
mio 0:f3f80a0695ff 2 #include "ov7670reg.h"
mio 0:f3f80a0695ff 3
mio 0:f3f80a0695ff 4 #define OV7670_WRITE (0x42)
mio 0:f3f80a0695ff 5 #define OV7670_READ (0x43)
mio 0:f3f80a0695ff 6 #define OV7670_WRITEWAIT (20)
mio 0:f3f80a0695ff 7 #define OV7670_NOACK (0)
mio 0:f3f80a0695ff 8 #define OV7670_REGMAX (201)
mio 0:f3f80a0695ff 9 #define OV7670_I2CFREQ (50000)
mio 0:f3f80a0695ff 10
mio 0:f3f80a0695ff 11 //
mio 0:f3f80a0695ff 12 // OV7670 + FIFO AL422B camera board test
mio 0:f3f80a0695ff 13 //
mio 0:f3f80a0695ff 14 class OV7670 : public Base
mio 0:f3f80a0695ff 15 {
mio 0:f3f80a0695ff 16 public:
mio 0:f3f80a0695ff 17 I2C camera ;
mio 0:f3f80a0695ff 18 InterruptIn vsync,href;
mio 0:f3f80a0695ff 19 DigitalOut wen ;
mio 0:f3f80a0695ff 20 PortIn data ;
mio 0:f3f80a0695ff 21 DigitalOut rrst,oe,rclk ;
mio 0:f3f80a0695ff 22 volatile int LineCounter ;
mio 0:f3f80a0695ff 23 volatile int LastLines ;
mio 0:f3f80a0695ff 24 volatile bool CaptureReq ;
mio 0:f3f80a0695ff 25 volatile bool Busy ;
mio 0:f3f80a0695ff 26 volatile bool Done ;
mio 0:f3f80a0695ff 27
mio 0:f3f80a0695ff 28 OV7670(
mio 0:f3f80a0695ff 29 PinName sda,// Camera I2C port
mio 0:f3f80a0695ff 30 PinName scl,// Camera I2C port
mio 0:f3f80a0695ff 31 PinName vs, // VSYNC
mio 0:f3f80a0695ff 32 PinName hr, // HREF
mio 0:f3f80a0695ff 33 PinName we, // WEN
mio 0:f3f80a0695ff 34 PortName port, // 8bit bus port
mio 0:f3f80a0695ff 35 int mask, // 0b0000_0M65_4000_0321_L000_0000_0000_0000 = 0x07878000
mio 0:f3f80a0695ff 36 PinName rt, // /RRST
mio 0:f3f80a0695ff 37 PinName o, // /OE
mio 0:f3f80a0695ff 38 PinName rc // RCLK
mio 0:f3f80a0695ff 39 ) : camera(sda,scl),vsync(vs),href(hr),wen(we),data(port,mask),rrst(rt),oe(o),rclk(rc)
mio 0:f3f80a0695ff 40 {
mio 0:f3f80a0695ff 41 camera.stop() ;
mio 0:f3f80a0695ff 42 camera.frequency(OV7670_I2CFREQ) ;
mio 0:f3f80a0695ff 43 vsync.fall(this,&OV7670::VsyncHandler) ;
mio 0:f3f80a0695ff 44 href.rise(this,&OV7670::HrefHandler) ;
mio 0:f3f80a0695ff 45 CaptureReq = false ;
mio 0:f3f80a0695ff 46 Busy = false ;
mio 0:f3f80a0695ff 47 Done = false ;
mio 0:f3f80a0695ff 48 LineCounter = 0 ;
mio 0:f3f80a0695ff 49 rrst = 1 ;
mio 0:f3f80a0695ff 50 oe = 1 ;
mio 0:f3f80a0695ff 51 rclk = 1 ;
mio 0:f3f80a0695ff 52 wen = 0 ;
mio 0:f3f80a0695ff 53 }
mio 0:f3f80a0695ff 54
mio 0:f3f80a0695ff 55 // capture request
mio 0:f3f80a0695ff 56 void CaptureNext(void)
mio 0:f3f80a0695ff 57 {
mio 0:f3f80a0695ff 58 CaptureReq = true ;
mio 0:f3f80a0695ff 59 Busy = true ;
mio 0:f3f80a0695ff 60 }
mio 0:f3f80a0695ff 61
mio 0:f3f80a0695ff 62 // capture done? (with clear)
mio 0:f3f80a0695ff 63 bool CaptureDone(void)
mio 0:f3f80a0695ff 64 {
mio 0:f3f80a0695ff 65 bool result ;
mio 0:f3f80a0695ff 66 if (Busy) {
mio 0:f3f80a0695ff 67 result = false ;
mio 0:f3f80a0695ff 68 } else {
mio 0:f3f80a0695ff 69 result = Done ;
mio 0:f3f80a0695ff 70 Done = false ;
mio 0:f3f80a0695ff 71 }
mio 0:f3f80a0695ff 72 return result ;
mio 0:f3f80a0695ff 73 }
mio 0:f3f80a0695ff 74
mio 0:f3f80a0695ff 75 // write to camera
mio 0:f3f80a0695ff 76 void WriteReg(int addr,int data)
mio 0:f3f80a0695ff 77 {
mio 0:f3f80a0695ff 78 // WRITE 0x42,ADDR,DATA
mio 0:f3f80a0695ff 79 camera.start() ;
mio 0:f3f80a0695ff 80 camera.write(OV7670_WRITE) ;
mio 0:f3f80a0695ff 81 wait_us(OV7670_WRITEWAIT);
mio 0:f3f80a0695ff 82 camera.write(addr) ;
mio 0:f3f80a0695ff 83 wait_us(OV7670_WRITEWAIT);
mio 0:f3f80a0695ff 84 camera.write(data) ;
mio 0:f3f80a0695ff 85 camera.stop() ;
mio 0:f3f80a0695ff 86 }
mio 0:f3f80a0695ff 87
mio 0:f3f80a0695ff 88 // read from camera
mio 0:f3f80a0695ff 89 int ReadReg(int addr)
mio 0:f3f80a0695ff 90 {
mio 0:f3f80a0695ff 91 int data ;
mio 0:f3f80a0695ff 92
mio 0:f3f80a0695ff 93 // WRITE 0x42,ADDR
mio 0:f3f80a0695ff 94 camera.start() ;
mio 0:f3f80a0695ff 95 camera.write(OV7670_WRITE) ;
mio 0:f3f80a0695ff 96 wait_us(OV7670_WRITEWAIT);
mio 0:f3f80a0695ff 97 camera.write(addr) ;
mio 0:f3f80a0695ff 98 camera.stop() ;
mio 0:f3f80a0695ff 99 wait_us(OV7670_WRITEWAIT);
mio 0:f3f80a0695ff 100
mio 0:f3f80a0695ff 101 // WRITE 0x43,READ
mio 0:f3f80a0695ff 102 camera.start() ;
mio 0:f3f80a0695ff 103 camera.write(OV7670_READ) ;
mio 0:f3f80a0695ff 104 wait_us(OV7670_WRITEWAIT);
mio 0:f3f80a0695ff 105 data = camera.read(OV7670_NOACK) ;
mio 0:f3f80a0695ff 106 camera.stop() ;
mio 0:f3f80a0695ff 107
mio 0:f3f80a0695ff 108 return data ;
mio 0:f3f80a0695ff 109 }
mio 0:f3f80a0695ff 110
mio 0:f3f80a0695ff 111 void Reset(void) {
mio 0:f3f80a0695ff 112 WriteReg(0x12,0x80) ; // RESET CAMERA
mio 0:f3f80a0695ff 113 wait_ms(200) ;
mio 0:f3f80a0695ff 114 }
mio 0:f3f80a0695ff 115
mio 1:509676f3be32 116 void InitQQVGA565(bool flipv,bool fliph) {
mio 0:f3f80a0695ff 117 // QQVGA RGB565
mio 0:f3f80a0695ff 118 WriteReg(REG_CLKRC,0x80);
mio 0:f3f80a0695ff 119 WriteReg(REG_COM11,0x0A) ;
mio 0:f3f80a0695ff 120 WriteReg(REG_TSLB,0x04);
mio 0:f3f80a0695ff 121 WriteReg(REG_COM7,0x04) ;
mio 0:f3f80a0695ff 122 WriteReg(REG_RGB444, 0x00);
mio 0:f3f80a0695ff 123 WriteReg(REG_COM15, 0xd0);
mio 0:f3f80a0695ff 124 WriteReg(REG_HSTART,0x16) ;
mio 0:f3f80a0695ff 125 WriteReg(REG_HSTOP,0x04) ;
mio 0:f3f80a0695ff 126 WriteReg(REG_HREF,0x24) ;
mio 0:f3f80a0695ff 127 WriteReg(REG_VSTART,0x02) ;
mio 0:f3f80a0695ff 128 WriteReg(REG_VSTOP,0x7a) ;
mio 0:f3f80a0695ff 129 WriteReg(REG_VREF,0x0a) ;
mio 0:f3f80a0695ff 130 WriteReg(REG_COM10,0x02) ;
mio 0:f3f80a0695ff 131 WriteReg(REG_COM3, 0x04);
mio 0:f3f80a0695ff 132 WriteReg(REG_COM14, 0x1a);
mio 1:509676f3be32 133 WriteReg(REG_MVFP,0x07 | (flipv ? 0x10:0) | (fliph ? 0x20:0)) ;
mio 0:f3f80a0695ff 134 WriteReg(0x72, 0x22);
mio 0:f3f80a0695ff 135 WriteReg(0x73, 0xf2);
mio 0:f3f80a0695ff 136
mio 0:f3f80a0695ff 137 // COLOR SETTING
mio 0:f3f80a0695ff 138 WriteReg(0x4f,0x80);
mio 0:f3f80a0695ff 139 WriteReg(0x50,0x80);
mio 0:f3f80a0695ff 140 WriteReg(0x51,0x00);
mio 0:f3f80a0695ff 141 WriteReg(0x52,0x22);
mio 0:f3f80a0695ff 142 WriteReg(0x53,0x5e);
mio 0:f3f80a0695ff 143 WriteReg(0x54,0x80);
mio 0:f3f80a0695ff 144 WriteReg(0x56,0x40);
mio 0:f3f80a0695ff 145 WriteReg(0x58,0x9e);
mio 0:f3f80a0695ff 146 WriteReg(0x59,0x88);
mio 0:f3f80a0695ff 147 WriteReg(0x5a,0x88);
mio 0:f3f80a0695ff 148 WriteReg(0x5b,0x44);
mio 0:f3f80a0695ff 149 WriteReg(0x5c,0x67);
mio 0:f3f80a0695ff 150 WriteReg(0x5d,0x49);
mio 0:f3f80a0695ff 151 WriteReg(0x5e,0x0e);
mio 0:f3f80a0695ff 152 WriteReg(0x69,0x00);
mio 0:f3f80a0695ff 153 WriteReg(0x6a,0x40);
mio 0:f3f80a0695ff 154 WriteReg(0x6b,0x0a);
mio 0:f3f80a0695ff 155 WriteReg(0x6c,0x0a);
mio 0:f3f80a0695ff 156 WriteReg(0x6d,0x55);
mio 0:f3f80a0695ff 157 WriteReg(0x6e,0x11);
mio 0:f3f80a0695ff 158 WriteReg(0x6f,0x9f);
mio 0:f3f80a0695ff 159
mio 0:f3f80a0695ff 160 WriteReg(0xb0,0x84);
mio 0:f3f80a0695ff 161 }
mio 0:f3f80a0695ff 162
mio 1:509676f3be32 163 void InitQVGA565(bool flipv,bool fliph) {
mio 0:f3f80a0695ff 164 // QVGA RGB565
mio 0:f3f80a0695ff 165 WriteReg(REG_CLKRC,0x80);
mio 0:f3f80a0695ff 166 WriteReg(REG_COM11,0x0A) ;
mio 0:f3f80a0695ff 167 WriteReg(REG_TSLB,0x04);
mio 0:f3f80a0695ff 168 WriteReg(REG_COM7,0x04) ;
mio 0:f3f80a0695ff 169 WriteReg(REG_RGB444, 0x00);
mio 0:f3f80a0695ff 170 WriteReg(REG_COM15, 0xd0);
mio 0:f3f80a0695ff 171 WriteReg(REG_HSTART,0x16) ;
mio 0:f3f80a0695ff 172 WriteReg(REG_HSTOP,0x04) ;
mio 0:f3f80a0695ff 173 WriteReg(REG_HREF,0x80) ;
mio 0:f3f80a0695ff 174 WriteReg(REG_VSTART,0x02) ;
mio 0:f3f80a0695ff 175 WriteReg(REG_VSTOP,0x7a) ;
mio 0:f3f80a0695ff 176 WriteReg(REG_VREF,0x0a) ;
mio 0:f3f80a0695ff 177 WriteReg(REG_COM10,0x02) ;
mio 0:f3f80a0695ff 178 WriteReg(REG_COM3, 0x04);
mio 0:f3f80a0695ff 179 WriteReg(REG_COM14, 0x19);
mio 1:509676f3be32 180 WriteReg(REG_MVFP,0x07 | (flipv ? 0x10:0) | (fliph ? 0x20:0)) ;
mio 0:f3f80a0695ff 181 WriteReg(0x72, 0x11);
mio 0:f3f80a0695ff 182 WriteReg(0x73, 0xf1);
mio 0:f3f80a0695ff 183
mio 0:f3f80a0695ff 184 // COLOR SETTING
mio 0:f3f80a0695ff 185 WriteReg(0x4f,0x80);
mio 0:f3f80a0695ff 186 WriteReg(0x50,0x80);
mio 0:f3f80a0695ff 187 WriteReg(0x51,0x00);
mio 0:f3f80a0695ff 188 WriteReg(0x52,0x22);
mio 0:f3f80a0695ff 189 WriteReg(0x53,0x5e);
mio 0:f3f80a0695ff 190 WriteReg(0x54,0x80);
mio 0:f3f80a0695ff 191 WriteReg(0x56,0x40);
mio 0:f3f80a0695ff 192 WriteReg(0x58,0x9e);
mio 0:f3f80a0695ff 193 WriteReg(0x59,0x88);
mio 0:f3f80a0695ff 194 WriteReg(0x5a,0x88);
mio 0:f3f80a0695ff 195 WriteReg(0x5b,0x44);
mio 0:f3f80a0695ff 196 WriteReg(0x5c,0x67);
mio 0:f3f80a0695ff 197 WriteReg(0x5d,0x49);
mio 0:f3f80a0695ff 198 WriteReg(0x5e,0x0e);
mio 0:f3f80a0695ff 199 WriteReg(0x69,0x00);
mio 0:f3f80a0695ff 200 WriteReg(0x6a,0x40);
mio 0:f3f80a0695ff 201 WriteReg(0x6b,0x0a);
mio 0:f3f80a0695ff 202 WriteReg(0x6c,0x0a);
mio 0:f3f80a0695ff 203 WriteReg(0x6d,0x55);
mio 0:f3f80a0695ff 204 WriteReg(0x6e,0x11);
mio 0:f3f80a0695ff 205 WriteReg(0x6f,0x9f);
mio 0:f3f80a0695ff 206
mio 0:f3f80a0695ff 207 WriteReg(0xb0,0x84);
mio 0:f3f80a0695ff 208 }
mio 0:f3f80a0695ff 209
mio 0:f3f80a0695ff 210
mio 0:f3f80a0695ff 211 // vsync handler
mio 0:f3f80a0695ff 212 void VsyncHandler(void)
mio 0:f3f80a0695ff 213 {
mio 0:f3f80a0695ff 214 // Capture Enable
mio 0:f3f80a0695ff 215 if (CaptureReq) {
mio 0:f3f80a0695ff 216 wen = 1 ;
mio 0:f3f80a0695ff 217 Done = false ;
mio 0:f3f80a0695ff 218 CaptureReq = false ;
mio 0:f3f80a0695ff 219 } else {
mio 0:f3f80a0695ff 220 wen = 0 ;
mio 0:f3f80a0695ff 221 if (Busy) {
mio 0:f3f80a0695ff 222 Busy = false ;
mio 0:f3f80a0695ff 223 Done = true ;
mio 0:f3f80a0695ff 224 }
mio 0:f3f80a0695ff 225 }
mio 0:f3f80a0695ff 226
mio 0:f3f80a0695ff 227 // Hline Counter
mio 0:f3f80a0695ff 228 LastLines = LineCounter ;
mio 0:f3f80a0695ff 229 LineCounter = 0 ;
mio 0:f3f80a0695ff 230 }
mio 0:f3f80a0695ff 231
mio 0:f3f80a0695ff 232 // href handler
mio 0:f3f80a0695ff 233 void HrefHandler(void)
mio 0:f3f80a0695ff 234 {
mio 0:f3f80a0695ff 235 LineCounter++ ;
mio 0:f3f80a0695ff 236 }
mio 0:f3f80a0695ff 237
mio 0:f3f80a0695ff 238 // Data Read
mio 0:f3f80a0695ff 239 int ReadOneByte(void)
mio 0:f3f80a0695ff 240 {
mio 0:f3f80a0695ff 241 int result ;
mio 0:f3f80a0695ff 242 rclk = 1 ;
mio 0:f3f80a0695ff 243 // wait_us(1) ;
mio 0:f3f80a0695ff 244 result = data ;
mio 0:f3f80a0695ff 245 rclk = 0 ;
mio 0:f3f80a0695ff 246 return result ;
mio 0:f3f80a0695ff 247 }
mio 0:f3f80a0695ff 248
mio 0:f3f80a0695ff 249 // Data Read (PortIn)
mio 0:f3f80a0695ff 250 int ReadOneWord(void)
mio 0:f3f80a0695ff 251 {
mio 0:f3f80a0695ff 252 int r,r1,r2,r3,r4 ;
mio 0:f3f80a0695ff 253 rclk = 1 ;
mio 0:f3f80a0695ff 254 r = data ;
mio 0:f3f80a0695ff 255 rclk = 0 ;
mio 0:f3f80a0695ff 256 r1 = r & 0x07800000 ;
mio 0:f3f80a0695ff 257 r1 = r1 >> (26-7-0) ; // bit26 to bit7
mio 0:f3f80a0695ff 258 r2 = r & 0x00078000 ;
mio 0:f3f80a0695ff 259 r2 = r2 >> (18-3-0) ; // bit18 to bit3
mio 0:f3f80a0695ff 260 rclk = 1 ;
mio 0:f3f80a0695ff 261 r = data ;
mio 0:f3f80a0695ff 262 rclk = 0 ;
mio 0:f3f80a0695ff 263 r3 = r & 0x07800000 ;
mio 0:f3f80a0695ff 264 r3 = r3 >> (26-7-8) ; // bit26 to bit7
mio 0:f3f80a0695ff 265 r4 = r & 0x00078000 ;
mio 0:f3f80a0695ff 266 r4 = r4 >> (18-3-8) ; // bit18 to bit3
mio 0:f3f80a0695ff 267 return r4+r3+r2+r1 ;
mio 0:f3f80a0695ff 268 }
mio 0:f3f80a0695ff 269
mio 0:f3f80a0695ff 270 // Data Start
mio 0:f3f80a0695ff 271 void ReadStart(void)
mio 0:f3f80a0695ff 272 {
mio 0:f3f80a0695ff 273 rrst = 0 ;
mio 0:f3f80a0695ff 274 oe = 0 ;
mio 0:f3f80a0695ff 275 wait_us(1) ;
mio 0:f3f80a0695ff 276 rclk = 0 ;
mio 0:f3f80a0695ff 277 wait_us(1) ;
mio 0:f3f80a0695ff 278 rclk = 1 ;
mio 0:f3f80a0695ff 279 wait_us(1) ;
mio 0:f3f80a0695ff 280 rrst = 1 ;
mio 0:f3f80a0695ff 281 }
mio 0:f3f80a0695ff 282
mio 0:f3f80a0695ff 283 // Data Stop
mio 0:f3f80a0695ff 284 void ReadStop(void)
mio 0:f3f80a0695ff 285 {
mio 0:f3f80a0695ff 286 oe = 1 ;
mio 0:f3f80a0695ff 287 ReadOneByte() ;
mio 0:f3f80a0695ff 288 rclk = 1 ;
mio 0:f3f80a0695ff 289 }
mio 0:f3f80a0695ff 290 };