Pipe Inpection Robot / Mbed OS capstone_finish

capstone_finish

Dependencies:   BufferedSerial motor_sn7544

ov7670.h@5:53dd2abce6b3, 2019-08-13 (annotated)

Committer:
kangmingyo
Date:
Tue Aug 13 07:38:19 2019 +0000
Revision:
5:53dd2abce6b3
Parent:
4:7b63cf3d205f
Child:
6:fe8b32cb9357
revised QQVGA register;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mio 0:f3f80a0695ff 1 #include "mbed.h"
mio 0:f3f80a0695ff 2 #include "ov7670reg.h"
mio 0:f3f80a0695ff 3
mio 0:f3f80a0695ff 4 #define OV7670_WRITE (0x42)
mio 0:f3f80a0695ff 5 #define OV7670_READ (0x43)
mio 0:f3f80a0695ff 6 #define OV7670_WRITEWAIT (20)
mio 0:f3f80a0695ff 7 #define OV7670_NOACK (0)
mio 0:f3f80a0695ff 8 #define OV7670_REGMAX (201)
kangmingyo 4:7b63cf3d205f 9 #define OV7670_I2CFREQ (40000)
mio 0:f3f80a0695ff 10
mio 0:f3f80a0695ff 11 //
mio 0:f3f80a0695ff 12 // OV7670 + FIFO AL422B camera board test
mio 0:f3f80a0695ff 13 //
kangmingyo 2:e98408458d2b 14 class OV7670
mio 0:f3f80a0695ff 15 {
mio 0:f3f80a0695ff 16 public:
kangmingyo 4:7b63cf3d205f 17 I2C _i2c ;
mio 0:f3f80a0695ff 18 InterruptIn vsync,href;
mio 0:f3f80a0695ff 19 DigitalOut wen ;
mio 0:f3f80a0695ff 20 PortIn data ;
mio 0:f3f80a0695ff 21 DigitalOut rrst,oe,rclk ;
mio 0:f3f80a0695ff 22 volatile int LineCounter ;
mio 0:f3f80a0695ff 23 volatile int LastLines ;
mio 0:f3f80a0695ff 24 volatile bool CaptureReq ;
mio 0:f3f80a0695ff 25 volatile bool Busy ;
mio 0:f3f80a0695ff 26 volatile bool Done ;
mio 0:f3f80a0695ff 27
mio 0:f3f80a0695ff 28 OV7670(
mio 0:f3f80a0695ff 29 PinName sda,// Camera I2C port
mio 0:f3f80a0695ff 30 PinName scl,// Camera I2C port
mio 0:f3f80a0695ff 31 PinName vs, // VSYNC
mio 0:f3f80a0695ff 32 PinName hr, // HREF
mio 0:f3f80a0695ff 33 PinName we, // WEN
mio 0:f3f80a0695ff 34 PortName port, // 8bit bus port
mio 0:f3f80a0695ff 35 int mask, // 0b0000_0M65_4000_0321_L000_0000_0000_0000 = 0x07878000
mio 0:f3f80a0695ff 36 PinName rt, // /RRST
mio 0:f3f80a0695ff 37 PinName o, // /OE
kangmingyo 2:e98408458d2b 38 PinName rc // RCLK
kangmingyo 4:7b63cf3d205f 39 ) : _i2c(sda,scl),vsync(vs),href(hr),wen(we),data(port,mask),rrst(rt),oe(o),rclk(rc)
mio 0:f3f80a0695ff 40 {
kangmingyo 4:7b63cf3d205f 41 _i2c.stop() ;
kangmingyo 4:7b63cf3d205f 42 _i2c.frequency(OV7670_I2CFREQ) ;
mio 0:f3f80a0695ff 43 vsync.fall(this,&OV7670::VsyncHandler) ;
mio 0:f3f80a0695ff 44 href.rise(this,&OV7670::HrefHandler) ;
mio 0:f3f80a0695ff 45 CaptureReq = false ;
mio 0:f3f80a0695ff 46 Busy = false ;
mio 0:f3f80a0695ff 47 Done = false ;
mio 0:f3f80a0695ff 48 LineCounter = 0 ;
mio 0:f3f80a0695ff 49 rrst = 1 ;
mio 0:f3f80a0695ff 50 oe = 1 ;
mio 0:f3f80a0695ff 51 rclk = 1 ;
mio 0:f3f80a0695ff 52 wen = 0 ;
mio 0:f3f80a0695ff 53 }
mio 0:f3f80a0695ff 54
mio 0:f3f80a0695ff 55 // capture request
mio 0:f3f80a0695ff 56 void CaptureNext(void)
mio 0:f3f80a0695ff 57 {
mio 0:f3f80a0695ff 58 CaptureReq = true ;
mio 0:f3f80a0695ff 59 Busy = true ;
mio 0:f3f80a0695ff 60 }
kangmingyo 2:e98408458d2b 61
mio 0:f3f80a0695ff 62 // capture done? (with clear)
mio 0:f3f80a0695ff 63 bool CaptureDone(void)
mio 0:f3f80a0695ff 64 {
mio 0:f3f80a0695ff 65 bool result ;
mio 0:f3f80a0695ff 66 if (Busy) {
mio 0:f3f80a0695ff 67 result = false ;
mio 0:f3f80a0695ff 68 } else {
mio 0:f3f80a0695ff 69 result = Done ;
mio 0:f3f80a0695ff 70 Done = false ;
mio 0:f3f80a0695ff 71 }
mio 0:f3f80a0695ff 72 return result ;
mio 0:f3f80a0695ff 73 }
mio 0:f3f80a0695ff 74
mio 0:f3f80a0695ff 75 // write to camera
mio 0:f3f80a0695ff 76 void WriteReg(int addr,int data)
mio 0:f3f80a0695ff 77 {
kangmingyo 4:7b63cf3d205f 78 int status;
kangmingyo 4:7b63cf3d205f 79 char data_write[2];
kangmingyo 4:7b63cf3d205f 80 data_write[0]= addr;
kangmingyo 4:7b63cf3d205f 81 data_write[1]= data;
kangmingyo 4:7b63cf3d205f 82 status = _i2c.write(OV7670_WRITE,data_write,2,0);
kangmingyo 4:7b63cf3d205f 83 if(status!=0){
kangmingyo 4:7b63cf3d205f 84 // printf("I2C configuration error(adr: %x)!\r\n",addr);
kangmingyo 4:7b63cf3d205f 85 while(1){
kangmingyo 4:7b63cf3d205f 86 }
kangmingyo 4:7b63cf3d205f 87 }
mio 0:f3f80a0695ff 88 }
mio 0:f3f80a0695ff 89
mio 0:f3f80a0695ff 90 // read from camera
mio 0:f3f80a0695ff 91 int ReadReg(int addr)
mio 0:f3f80a0695ff 92 {
kangmingyo 4:7b63cf3d205f 93 char data_write[2];
kangmingyo 4:7b63cf3d205f 94 char data_read[2];
kangmingyo 4:7b63cf3d205f 95 int data;
kangmingyo 4:7b63cf3d205f 96 int status;
kangmingyo 4:7b63cf3d205f 97
kangmingyo 4:7b63cf3d205f 98 data_write[0]=addr;
kangmingyo 4:7b63cf3d205f 99 _i2c.write(OV7670_WRITE, data_write, 1, 0);
kangmingyo 4:7b63cf3d205f 100 status =_i2c.read(OV7670_READ, data_read, 1, 0);
kangmingyo 4:7b63cf3d205f 101 data = (int)data_read[0];
kangmingyo 5:53dd2abce6b3 102 // printf("Data is %x\r\n",data);
kangmingyo 4:7b63cf3d205f 103 // printf("Status is %d\r\n",status);
mio 0:f3f80a0695ff 104 return data ;
mio 0:f3f80a0695ff 105 }
mio 0:f3f80a0695ff 106
kangmingyo 2:e98408458d2b 107 void Reset(void)
kangmingyo 2:e98408458d2b 108 {
mio 0:f3f80a0695ff 109 WriteReg(0x12,0x80) ; // RESET CAMERA
mio 0:f3f80a0695ff 110 wait_ms(200) ;
mio 0:f3f80a0695ff 111 }
kangmingyo 2:e98408458d2b 112
kangmingyo 2:e98408458d2b 113 void InitQQVGA565(bool flipv,bool fliph)
kangmingyo 2:e98408458d2b 114 {
mio 0:f3f80a0695ff 115 // QQVGA RGB565
mio 0:f3f80a0695ff 116 WriteReg(REG_CLKRC,0x80);
kangmingyo 2:e98408458d2b 117 WriteReg(REG_COM11,0x0A) ;
mio 0:f3f80a0695ff 118 WriteReg(REG_TSLB,0x04);
mio 0:f3f80a0695ff 119 WriteReg(REG_COM7,0x04) ;
mio 0:f3f80a0695ff 120 WriteReg(REG_RGB444, 0x00);
mio 0:f3f80a0695ff 121 WriteReg(REG_COM15, 0xd0);
mio 0:f3f80a0695ff 122 WriteReg(REG_HSTART,0x16) ;
mio 0:f3f80a0695ff 123 WriteReg(REG_HSTOP,0x04) ;
mio 0:f3f80a0695ff 124 WriteReg(REG_HREF,0x24) ;
mio 0:f3f80a0695ff 125 WriteReg(REG_VSTART,0x02) ;
mio 0:f3f80a0695ff 126 WriteReg(REG_VSTOP,0x7a) ;
mio 0:f3f80a0695ff 127 WriteReg(REG_VREF,0x0a) ;
mio 0:f3f80a0695ff 128 WriteReg(REG_COM10,0x02) ;
mio 0:f3f80a0695ff 129 WriteReg(REG_COM3, 0x04);
mio 0:f3f80a0695ff 130 WriteReg(REG_COM14, 0x1a);
mio 1:509676f3be32 131 WriteReg(REG_MVFP,0x07 | (flipv ? 0x10:0) | (fliph ? 0x20:0)) ;
mio 0:f3f80a0695ff 132 WriteReg(0x72, 0x22);
mio 0:f3f80a0695ff 133 WriteReg(0x73, 0xf2);
mio 0:f3f80a0695ff 134
mio 0:f3f80a0695ff 135 // COLOR SETTING
mio 0:f3f80a0695ff 136 WriteReg(0x4f,0x80);
mio 0:f3f80a0695ff 137 WriteReg(0x50,0x80);
mio 0:f3f80a0695ff 138 WriteReg(0x51,0x00);
mio 0:f3f80a0695ff 139 WriteReg(0x52,0x22);
mio 0:f3f80a0695ff 140 WriteReg(0x53,0x5e);
mio 0:f3f80a0695ff 141 WriteReg(0x54,0x80);
mio 0:f3f80a0695ff 142 WriteReg(0x56,0x40);
mio 0:f3f80a0695ff 143 WriteReg(0x58,0x9e);
mio 0:f3f80a0695ff 144 WriteReg(0x59,0x88);
mio 0:f3f80a0695ff 145 WriteReg(0x5a,0x88);
mio 0:f3f80a0695ff 146 WriteReg(0x5b,0x44);
mio 0:f3f80a0695ff 147 WriteReg(0x5c,0x67);
mio 0:f3f80a0695ff 148 WriteReg(0x5d,0x49);
mio 0:f3f80a0695ff 149 WriteReg(0x5e,0x0e);
mio 0:f3f80a0695ff 150 WriteReg(0x69,0x00);
mio 0:f3f80a0695ff 151 WriteReg(0x6a,0x40);
mio 0:f3f80a0695ff 152 WriteReg(0x6b,0x0a);
mio 0:f3f80a0695ff 153 WriteReg(0x6c,0x0a);
mio 0:f3f80a0695ff 154 WriteReg(0x6d,0x55);
mio 0:f3f80a0695ff 155 WriteReg(0x6e,0x11);
mio 0:f3f80a0695ff 156 WriteReg(0x6f,0x9f);
mio 0:f3f80a0695ff 157
mio 0:f3f80a0695ff 158 WriteReg(0xb0,0x84);
kangmingyo 2:e98408458d2b 159 }
mio 0:f3f80a0695ff 160
kangmingyo 2:e98408458d2b 161 void InitQVGA565(bool flipv,bool fliph)
kangmingyo 2:e98408458d2b 162 {
mio 0:f3f80a0695ff 163 // QVGA RGB565
mio 0:f3f80a0695ff 164 WriteReg(REG_CLKRC,0x80);
mio 0:f3f80a0695ff 165 WriteReg(REG_COM11,0x0A) ;
mio 0:f3f80a0695ff 166 WriteReg(REG_TSLB,0x04);
mio 0:f3f80a0695ff 167 WriteReg(REG_COM7,0x04) ;
mio 0:f3f80a0695ff 168 WriteReg(REG_RGB444, 0x00);
mio 0:f3f80a0695ff 169 WriteReg(REG_COM15, 0xd0);
mio 0:f3f80a0695ff 170 WriteReg(REG_HSTART,0x16) ;
mio 0:f3f80a0695ff 171 WriteReg(REG_HSTOP,0x04) ;
mio 0:f3f80a0695ff 172 WriteReg(REG_HREF,0x80) ;
mio 0:f3f80a0695ff 173 WriteReg(REG_VSTART,0x02) ;
mio 0:f3f80a0695ff 174 WriteReg(REG_VSTOP,0x7a) ;
mio 0:f3f80a0695ff 175 WriteReg(REG_VREF,0x0a) ;
mio 0:f3f80a0695ff 176 WriteReg(REG_COM10,0x02) ;
mio 0:f3f80a0695ff 177 WriteReg(REG_COM3, 0x04);
mio 0:f3f80a0695ff 178 WriteReg(REG_COM14, 0x19);
mio 1:509676f3be32 179 WriteReg(REG_MVFP,0x07 | (flipv ? 0x10:0) | (fliph ? 0x20:0)) ;
mio 0:f3f80a0695ff 180 WriteReg(0x72, 0x11);
mio 0:f3f80a0695ff 181 WriteReg(0x73, 0xf1);
mio 0:f3f80a0695ff 182
mio 0:f3f80a0695ff 183 // COLOR SETTING
mio 0:f3f80a0695ff 184 WriteReg(0x4f,0x80);
mio 0:f3f80a0695ff 185 WriteReg(0x50,0x80);
mio 0:f3f80a0695ff 186 WriteReg(0x51,0x00);
mio 0:f3f80a0695ff 187 WriteReg(0x52,0x22);
mio 0:f3f80a0695ff 188 WriteReg(0x53,0x5e);
mio 0:f3f80a0695ff 189 WriteReg(0x54,0x80);
mio 0:f3f80a0695ff 190 WriteReg(0x56,0x40);
mio 0:f3f80a0695ff 191 WriteReg(0x58,0x9e);
mio 0:f3f80a0695ff 192 WriteReg(0x59,0x88);
mio 0:f3f80a0695ff 193 WriteReg(0x5a,0x88);
mio 0:f3f80a0695ff 194 WriteReg(0x5b,0x44);
mio 0:f3f80a0695ff 195 WriteReg(0x5c,0x67);
mio 0:f3f80a0695ff 196 WriteReg(0x5d,0x49);
mio 0:f3f80a0695ff 197 WriteReg(0x5e,0x0e);
mio 0:f3f80a0695ff 198 WriteReg(0x69,0x00);
mio 0:f3f80a0695ff 199 WriteReg(0x6a,0x40);
mio 0:f3f80a0695ff 200 WriteReg(0x6b,0x0a);
mio 0:f3f80a0695ff 201 WriteReg(0x6c,0x0a);
mio 0:f3f80a0695ff 202 WriteReg(0x6d,0x55);
mio 0:f3f80a0695ff 203 WriteReg(0x6e,0x11);
mio 0:f3f80a0695ff 204 WriteReg(0x6f,0x9f);
mio 0:f3f80a0695ff 205
mio 0:f3f80a0695ff 206 WriteReg(0xb0,0x84);
kangmingyo 2:e98408458d2b 207 }
kangmingyo 2:e98408458d2b 208 void InitQVGAYUV(bool flipv,bool fliph)
kangmingyo 2:e98408458d2b 209 {
kangmingyo 5:53dd2abce6b3 210 WriteReg(0x11,0x01);
kangmingyo 2:e98408458d2b 211 WriteReg(REG_COM7, 0x00); // YUV
kangmingyo 2:e98408458d2b 212 WriteReg(REG_COM17, 0x00); // color bar disable
kangmingyo 5:53dd2abce6b3 213 WriteReg(REG_COM3, 0x04);
kangmingyo 2:e98408458d2b 214 WriteReg(0x12, 0x00);//COM7
kangmingyo 5:53dd2abce6b3 215
kangmingyo 2:e98408458d2b 216 WriteReg(0x14, 0x1A);//COM9
kangmingyo 2:e98408458d2b 217 WriteReg(0x3D, 0x40);//COM13
kangmingyo 2:e98408458d2b 218 WriteReg(REG_COM15, 0xC0);
kangmingyo 5:53dd2abce6b3 219 WriteReg(REG_TSLB,0x0C);
kangmingyo 5:53dd2abce6b3 220 WriteReg(REG_COM14, 0x1a); // divide by 4
kangmingyo 2:e98408458d2b 221 WriteReg(0x72, 0x22); // downsample by 4
kangmingyo 2:e98408458d2b 222 WriteReg(0x73, 0xf2); // divide by 4
kangmingyo 2:e98408458d2b 223 WriteReg(REG_HREF, 0xa4);
kangmingyo 2:e98408458d2b 224 WriteReg(REG_HSTART, 0x16);
kangmingyo 2:e98408458d2b 225 WriteReg(REG_HSTOP, 0x04);
kangmingyo 2:e98408458d2b 226 WriteReg(REG_VREF, 0x0a);
kangmingyo 2:e98408458d2b 227 WriteReg(REG_VSTART, 0x02);
kangmingyo 5:53dd2abce6b3 228 WriteReg(REG_VSTOP, 0x7a);
kangmingyo 5:53dd2abce6b3 229 WriteReg(0x70,0x3A);
kangmingyo 5:53dd2abce6b3 230 WriteReg(0x71,0x35);
kangmingyo 5:53dd2abce6b3 231 WriteReg(0x72,0x22);
kangmingyo 5:53dd2abce6b3 232 WriteReg(0x73,0xF2);
kangmingyo 5:53dd2abce6b3 233 WriteReg(0xA2,0x02);
kangmingyo 5:53dd2abce6b3 234
kangmingyo 5:53dd2abce6b3 235
kangmingyo 5:53dd2abce6b3 236
kangmingyo 5:53dd2abce6b3 237
kangmingyo 5:53dd2abce6b3 238
kangmingyo 5:53dd2abce6b3 239
kangmingyo 5:53dd2abce6b3 240 /* END MARKER */
kangmingyo 2:e98408458d2b 241 }
mio 0:f3f80a0695ff 242
mio 0:f3f80a0695ff 243
mio 0:f3f80a0695ff 244 // vsync handler
mio 0:f3f80a0695ff 245 void VsyncHandler(void)
mio 0:f3f80a0695ff 246 {
mio 0:f3f80a0695ff 247 // Capture Enable
mio 0:f3f80a0695ff 248 if (CaptureReq) {
mio 0:f3f80a0695ff 249 wen = 1 ;
mio 0:f3f80a0695ff 250 Done = false ;
mio 0:f3f80a0695ff 251 CaptureReq = false ;
mio 0:f3f80a0695ff 252 } else {
mio 0:f3f80a0695ff 253 wen = 0 ;
mio 0:f3f80a0695ff 254 if (Busy) {
mio 0:f3f80a0695ff 255 Busy = false ;
mio 0:f3f80a0695ff 256 Done = true ;
mio 0:f3f80a0695ff 257 }
mio 0:f3f80a0695ff 258 }
mio 0:f3f80a0695ff 259
mio 0:f3f80a0695ff 260 // Hline Counter
mio 0:f3f80a0695ff 261 LastLines = LineCounter ;
mio 0:f3f80a0695ff 262 LineCounter = 0 ;
mio 0:f3f80a0695ff 263 }
kangmingyo 2:e98408458d2b 264
mio 0:f3f80a0695ff 265 // href handler
mio 0:f3f80a0695ff 266 void HrefHandler(void)
mio 0:f3f80a0695ff 267 {
mio 0:f3f80a0695ff 268 LineCounter++ ;
mio 0:f3f80a0695ff 269 }
kangmingyo 2:e98408458d2b 270
mio 0:f3f80a0695ff 271 // Data Read
mio 0:f3f80a0695ff 272 int ReadOneByte(void)
mio 0:f3f80a0695ff 273 {
mio 0:f3f80a0695ff 274 int result ;
mio 0:f3f80a0695ff 275 rclk = 1 ;
mio 0:f3f80a0695ff 276 // wait_us(1) ;
mio 0:f3f80a0695ff 277 result = data ;
mio 0:f3f80a0695ff 278 rclk = 0 ;
mio 0:f3f80a0695ff 279 return result ;
mio 0:f3f80a0695ff 280 }
mio 0:f3f80a0695ff 281
mio 0:f3f80a0695ff 282 // Data Read (PortIn)
kangmingyo 4:7b63cf3d205f 283 int ReadOneWord(void)
mio 0:f3f80a0695ff 284 {
kangmingyo 2:e98408458d2b 285 // int r,r1,r2,r3,r4 ;
kangmingyo 2:e98408458d2b 286 // rclk = 1 ;
kangmingyo 2:e98408458d2b 287 // r = data ;
kangmingyo 2:e98408458d2b 288 // rclk = 0 ;
kangmingyo 2:e98408458d2b 289 // r1 = r & 0x07800000 ;
kangmingyo 2:e98408458d2b 290 // r1 = r1 >> (26-7-0) ; // bit26 to bit7
kangmingyo 2:e98408458d2b 291 // r2 = r & 0x00078000 ;
kangmingyo 2:e98408458d2b 292 // r2 = r2 >> (18-3-0) ; // bit18 to bit3
kangmingyo 2:e98408458d2b 293 // rclk = 1 ;
kangmingyo 2:e98408458d2b 294 // r = data ;
kangmingyo 2:e98408458d2b 295 // rclk = 0 ;
kangmingyo 2:e98408458d2b 296 // r3 = r & 0x07800000 ;
kangmingyo 2:e98408458d2b 297 // r3 = r3 >> (26-7-8) ; // bit26 to bit7
kangmingyo 2:e98408458d2b 298 // r4 = r & 0x00078000 ;
kangmingyo 2:e98408458d2b 299 // r4 = r4 >> (18-3-8) ; // bit18 to bit3
kangmingyo 2:e98408458d2b 300
kangmingyo 2:e98408458d2b 301 int r,r1,r2;
kangmingyo 2:e98408458d2b 302 rclk=1;
kangmingyo 2:e98408458d2b 303 r = data;
kangmingyo 2:e98408458d2b 304 rclk=0;
kangmingyo 2:e98408458d2b 305 r1 = r<<8;
kangmingyo 2:e98408458d2b 306 rclk=1;
kangmingyo 2:e98408458d2b 307 r= data;
kangmingyo 2:e98408458d2b 308 rclk=0;
kangmingyo 2:e98408458d2b 309 r2 = r;
kangmingyo 2:e98408458d2b 310
kangmingyo 2:e98408458d2b 311
kangmingyo 2:e98408458d2b 312 return r2+r1 ;
mio 0:f3f80a0695ff 313 }
kangmingyo 2:e98408458d2b 314
mio 0:f3f80a0695ff 315 // Data Start
mio 0:f3f80a0695ff 316 void ReadStart(void)
kangmingyo 2:e98408458d2b 317 {
mio 0:f3f80a0695ff 318 rrst = 0 ;
mio 0:f3f80a0695ff 319 oe = 0 ;
mio 0:f3f80a0695ff 320 wait_us(1) ;
mio 0:f3f80a0695ff 321 rclk = 0 ;
mio 0:f3f80a0695ff 322 wait_us(1) ;
mio 0:f3f80a0695ff 323 rclk = 1 ;
kangmingyo 2:e98408458d2b 324 wait_us(1) ;
mio 0:f3f80a0695ff 325 rrst = 1 ;
mio 0:f3f80a0695ff 326 }
kangmingyo 2:e98408458d2b 327
mio 0:f3f80a0695ff 328 // Data Stop
mio 0:f3f80a0695ff 329 void ReadStop(void)
mio 0:f3f80a0695ff 330 {
mio 0:f3f80a0695ff 331 oe = 1 ;
mio 0:f3f80a0695ff 332 ReadOneByte() ;
mio 0:f3f80a0695ff 333 rclk = 1 ;
mio 0:f3f80a0695ff 334 }
mio 0:f3f80a0695ff 335 };