interrupt handling
readerComm.h@13:16a5b43ac874, 2015-04-30 (annotated)
- Committer:
- soumi_ghsoh
- Date:
- Thu Apr 30 23:30:55 2015 +0000
- Revision:
- 13:16a5b43ac874
- Parent:
- 11:d5e8f47880f1
2015apr30
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
soumi_ghsoh | 13:16a5b43ac874 | 1 | |
soumi_ghsoh | 13:16a5b43ac874 | 2 | //#define EN_7970_PIN p0 |
soumi_ghsoh | 13:16a5b43ac874 | 3 | //#define DETECT_METAL_PIN p1 |
soumi_ghsoh | 13:16a5b43ac874 | 4 | //#define METAL_THRESH_PIN p2 |
soumi_ghsoh | 13:16a5b43ac874 | 5 | //#define SPI_CLK_PIN p3 |
soumi_ghsoh | 13:16a5b43ac874 | 6 | //#define EN2_7970_PIN p4 |
soumi_ghsoh | 13:16a5b43ac874 | 7 | //#define VUSBMON_PIN p5 |
soumi_ghsoh | 13:16a5b43ac874 | 8 | //#define VBATMON_PIN p6 |
soumi_ghsoh | 13:16a5b43ac874 | 9 | //#define SPI_MOSI_PIN p7 |
soumi_ghsoh | 13:16a5b43ac874 | 10 | //#define SPI_MISO_PIN p8 |
soumi_ghsoh | 13:16a5b43ac874 | 11 | //#define CS_7970_PIN p9 |
soumi_ghsoh | 13:16a5b43ac874 | 12 | //#define TP1_PIN p10 //use this one for the serial port TX |
soumi_ghsoh | 13:16a5b43ac874 | 13 | //#define WD_CONTROL_PIN p11 |
soumi_ghsoh | 13:16a5b43ac874 | 14 | //#define WATCHDOG_PIN p12 |
soumi_ghsoh | 13:16a5b43ac874 | 15 | //#define CHARGING_PIN p13 |
soumi_ghsoh | 13:16a5b43ac874 | 16 | //#define SCL_PIN p14 |
soumi_ghsoh | 13:16a5b43ac874 | 17 | //#define SDA_PIN p15 |
soumi_ghsoh | 13:16a5b43ac874 | 18 | //#define ADXL345_INT_PIN p16 |
soumi_ghsoh | 13:16a5b43ac874 | 19 | //#define BLED_PIN p17 |
soumi_ghsoh | 13:16a5b43ac874 | 20 | //#define GLED_PIN p18 |
soumi_ghsoh | 13:16a5b43ac874 | 21 | //#define RLED_PIN p19 |
soumi_ghsoh | 13:16a5b43ac874 | 22 | //#define UNUSED_20_PIN p20 |
soumi_ghsoh | 13:16a5b43ac874 | 23 | //#define DETECT_METAL_INT_PIN p21 |
soumi_ghsoh | 13:16a5b43ac874 | 24 | //#define COILPWR_PIN p22 |
soumi_ghsoh | 13:16a5b43ac874 | 25 | //#define UNUSED_23_PIN p23 |
soumi_ghsoh | 13:16a5b43ac874 | 26 | //#define TP4_PIN p24 |
soumi_ghsoh | 13:16a5b43ac874 | 27 | //#define TP5_PIN p25 |
soumi_ghsoh | 13:16a5b43ac874 | 28 | //#define IRQ_7970_PIN p28 |
soumi_ghsoh | 13:16a5b43ac874 | 29 | //#define AO_7970_PIN p29 |
soumi_ghsoh | 13:16a5b43ac874 | 30 | //#define MOD_7970_PIN p30 |
rwclough | 1:1eb96189824d | 31 | |
rwclough | 1:1eb96189824d | 32 | // Prototypes |
soumi_ghsoh | 7:96baf1b2fd07 | 33 | //void SpiInit1(void); // SPI 250 Khz |
soumi_ghsoh | 7:96baf1b2fd07 | 34 | void SpiInit(void); // SPI 1Mhz |
soumi_ghsoh | 7:96baf1b2fd07 | 35 | void trf797xDirectCommand(uint8_t *buffer); // send direct command to trf7970a |
soumi_ghsoh | 7:96baf1b2fd07 | 36 | void trf797xWriteSingle(uint8_t *buffer, uint8_t length); // write to trf7970a register |
soumi_ghsoh | 7:96baf1b2fd07 | 37 | void trf797xReadSingle(uint8_t *buffer, uint8_t number); // read trf7970a register |
soumi_ghsoh | 7:96baf1b2fd07 | 38 | void trf797xReadContinuous(uint8_t *buffer, uint8_t length); // read continuous bytes from trf7970a |
soumi_ghsoh | 7:96baf1b2fd07 | 39 | void trf797xRawWrite(uint8_t *buffer, uint8_t length); // raw write to trf7970a FIFO |
soumi_ghsoh | 7:96baf1b2fd07 | 40 | void PowerUpNFC(void); // powerup trf7970a |
soumi_ghsoh | 9:9266e0109d26 | 41 | void PowerUpNFC2(void); |
soumi_ghsoh | 7:96baf1b2fd07 | 42 | void PowerDownNFC(void); // powerdown trf7970a |
soumi_ghsoh | 7:96baf1b2fd07 | 43 | void NFCInit(void); // initialize trf7970 iso control =0x02, chip status control=0x20, modulator=0x21 |
soumi_ghsoh | 7:96baf1b2fd07 | 44 | void RegisterReInitNFC(void); // reinitialize nfc status registers |
soumi_ghsoh | 7:96baf1b2fd07 | 45 | void RegistersReadNFC(void); // read nfc status registers |
soumi_ghsoh | 7:96baf1b2fd07 | 46 | void InventoryReqNFC(void); // inventory request to trf7970a |
soumi_ghsoh | 7:96baf1b2fd07 | 47 | void MemReadReqNFC(void); // memory read request to trf7970a |
soumi_ghsoh | 7:96baf1b2fd07 | 48 | void ReadNFC(void); // read teag ID/Single Read |
soumi_ghsoh | 11:d5e8f47880f1 | 49 | void FindNFC(uint8_t *irqStatus); // read irq from trf7970a. |
soumi_ghsoh | 9:9266e0109d26 | 50 | void handlerNFC(void); // trf7970 irq handler |
soumi_ghsoh | 10:98a58968dc7d | 51 | void StandByNFC(void); |
soumi_ghsoh | 11:d5e8f47880f1 | 52 | void SleepNFC(void); |
soumi_ghsoh | 11:d5e8f47880f1 | 53 | bool PollNFC(void); |
soumi_ghsoh | 10:98a58968dc7d | 54 | //uint8_t pwr_mode ; |
soumi_ghsoh | 9:9266e0109d26 | 55 | |
soumi_ghsoh | 9:9266e0109d26 | 56 | |
soumi_ghsoh | 5:93c612f43ec2 | 57 | // Booleans |
soumi_ghsoh | 10:98a58968dc7d | 58 | #define DESELECT 1 |
soumi_ghsoh | 10:98a58968dc7d | 59 | #define SELECT 0 |
soumi_ghsoh | 10:98a58968dc7d | 60 | #define ADDRESS 0 |
soumi_ghsoh | 10:98a58968dc7d | 61 | #define COMMAND 1 |
soumi_ghsoh | 10:98a58968dc7d | 62 | #define WRITE 0 |
soumi_ghsoh | 10:98a58968dc7d | 63 | #define READ 1 |
soumi_ghsoh | 10:98a58968dc7d | 64 | |
soumi_ghsoh | 5:93c612f43ec2 | 65 | //led |
soumi_ghsoh | 5:93c612f43ec2 | 66 | #define LED_ON 0 |
soumi_ghsoh | 5:93c612f43ec2 | 67 | #define LED_OFF 1 |
soumi_ghsoh | 5:93c612f43ec2 | 68 | #define FALSE 0 |
soumi_ghsoh | 5:93c612f43ec2 | 69 | #define TRUE 1 |
rwclough | 1:1eb96189824d | 70 | |
soumi_ghsoh | 5:93c612f43ec2 | 71 | // Direct commands for trf797x |
rwclough | 1:1eb96189824d | 72 | #define IDLE 0x00 |
rwclough | 1:1eb96189824d | 73 | #define SOFT_INIT 0x03 |
rwclough | 1:1eb96189824d | 74 | #define INITIAL_RF_COLLISION 0x04 |
rwclough | 1:1eb96189824d | 75 | #define RESPONSE_RF_COLLISION_N 0x05 |
rwclough | 1:1eb96189824d | 76 | #define RESPONSE_RF_COLLISION_0 0x06 |
rwclough | 1:1eb96189824d | 77 | #define RESET 0x0F |
rwclough | 1:1eb96189824d | 78 | #define TRANSMIT_NO_CRC 0x10 |
rwclough | 1:1eb96189824d | 79 | #define TRANSMIT_CRC 0x11 |
rwclough | 1:1eb96189824d | 80 | #define DELAY_TRANSMIT_NO_CRC 0x12 |
rwclough | 1:1eb96189824d | 81 | #define DELAY_TRANSMIT_CRC 0x13 |
rwclough | 1:1eb96189824d | 82 | #define TRANSMIT_NEXT_SLOT 0x14 |
rwclough | 1:1eb96189824d | 83 | #define CLOSE_SLOT_SEQUENCE 0x15 |
rwclough | 1:1eb96189824d | 84 | #define STOP_DECODERS 0x16 |
rwclough | 1:1eb96189824d | 85 | #define RUN_DECODERS 0x17 |
rwclough | 1:1eb96189824d | 86 | #define CHECK_INTERNAL_RF 0x18 |
rwclough | 1:1eb96189824d | 87 | #define CHECK_EXTERNAL_RF 0x19 |
rwclough | 1:1eb96189824d | 88 | #define ADJUST_GAIN 0x1A |
rwclough | 1:1eb96189824d | 89 | |
soumi_ghsoh | 5:93c612f43ec2 | 90 | // Registers for trf797x |
rwclough | 1:1eb96189824d | 91 | #define CHIP_STATUS_CONTROL 0x00 |
rwclough | 1:1eb96189824d | 92 | #define ISO_CONTROL 0x01 |
rwclough | 1:1eb96189824d | 93 | #define ISO_14443B_OPTIONS 0x02 |
rwclough | 1:1eb96189824d | 94 | #define ISO_14443A_OPTIONS 0x03 |
rwclough | 1:1eb96189824d | 95 | #define TX_TIMER_EPC_HIGH 0x04 |
rwclough | 1:1eb96189824d | 96 | #define TX_TIMER_EPC_LOW 0x05 |
rwclough | 1:1eb96189824d | 97 | #define TX_PULSE_LENGTH_CONTROL 0x06 |
rwclough | 1:1eb96189824d | 98 | #define RX_NO_RESPONSE_WAIT_TIME 0x07 |
rwclough | 1:1eb96189824d | 99 | #define RX_WAIT_TIME 0x08 |
rwclough | 1:1eb96189824d | 100 | #define MODULATOR_CONTROL 0x09 |
rwclough | 1:1eb96189824d | 101 | #define RX_SPECIAL_SETTINGS 0x0A |
rwclough | 1:1eb96189824d | 102 | #define REGULATOR_CONTROL 0x0B |
rwclough | 1:1eb96189824d | 103 | #define IRQ_STATUS 0x0C |
rwclough | 1:1eb96189824d | 104 | #define IRQ_MASK 0x0D |
rwclough | 1:1eb96189824d | 105 | #define COLLISION_POSITION 0x0E |
rwclough | 1:1eb96189824d | 106 | #define RSSI_LEVELS 0x0F |
rwclough | 1:1eb96189824d | 107 | #define SPECIAL_FUNCTION_1 0x10 |
rwclough | 1:1eb96189824d | 108 | #define SPECIAL_FUNCTION_2 0x11 |
rwclough | 1:1eb96189824d | 109 | #define RAM_0 0x12 |
rwclough | 1:1eb96189824d | 110 | #define RAM_1 0x13 |
rwclough | 1:1eb96189824d | 111 | #define FIFO_IRQ_LEVELS_ADJ 0x14 |
rwclough | 1:1eb96189824d | 112 | #define RESERVED 0x15 |
rwclough | 1:1eb96189824d | 113 | #define NFC_LOW_DETECTION 0x16 |
rwclough | 2:bd5afc5aa139 | 114 | #define NFCID 0x17 |
rwclough | 1:1eb96189824d | 115 | #define NFC_TARGET_LEVEL 0x18 |
rwclough | 1:1eb96189824d | 116 | #define NFC_TARGET_PROTOCOL 0x19 |
rwclough | 1:1eb96189824d | 117 | #define TEST_SETTINGS_1 0x1A |
rwclough | 1:1eb96189824d | 118 | #define TEST_SETTINGS_2 0x1B |
soumi_ghsoh | 7:96baf1b2fd07 | 119 | #define FIFO_COUNTER 0x1C |
rwclough | 2:bd5afc5aa139 | 120 | #define TX_LENGTH_BYTE_1 0x1D |
rwclough | 2:bd5afc5aa139 | 121 | #define TX_LENGTH_BYTE_2 0x1E |
rwclough | 2:bd5afc5aa139 | 122 | #define FIFO 0x1F |
rwclough | 2:bd5afc5aa139 | 123 | |
rwclough | 2:bd5afc5aa139 | 124 | // BITs |
rwclough | 2:bd5afc5aa139 | 125 | #define BIT0 0x01 // 0b00000001 |
rwclough | 2:bd5afc5aa139 | 126 | #define BIT1 0x02 // 0b00000010 |
rwclough | 2:bd5afc5aa139 | 127 | #define BIT2 0x40 // 0b00000100 |
rwclough | 2:bd5afc5aa139 | 128 | #define BIT3 0x08 // 0b00001000 |
rwclough | 2:bd5afc5aa139 | 129 | #define BIT4 0x10 // 0b00010000 |
rwclough | 2:bd5afc5aa139 | 130 | #define BIT5 0x20 // 0b00100000 |
rwclough | 2:bd5afc5aa139 | 131 | #define BIT6 0x40 // 0b01000000 |
rwclough | 2:bd5afc5aa139 | 132 | #define BIT7 0x80 // 0b10000000 |
rwclough | 2:bd5afc5aa139 | 133 | |
rwclough | 2:bd5afc5aa139 | 134 | // Misc |
rwclough | 2:bd5afc5aa139 | 135 | #define SIXTEEN_SLOTS 0x06 |
rwclough | 2:bd5afc5aa139 | 136 | #define ONE_SLOT 0x26 |
soumi_ghsoh | 5:93c612f43ec2 | 137 |