Gymtrack / RFIDTestNFC

interrupt handling

Dependencies:  

readerComm.h@1:1eb96189824d, 2015-03-02 (annotated)

Committer:
rwclough
Date:
Mon Mar 02 19:50:31 2015 +0000
Revision:
1:1eb96189824d
Child:
2:bd5afc5aa139
The SPI interface between nRF51-DK and TRF7970 eval board works such that RAM_0 register can be written and read. Test values are 0xAA and 0x55.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rwclough 1:1eb96189824d 1 /*
rwclough 1:1eb96189824d 2 Header file for readerComm.c
rwclough 1:1eb96189824d 3 */
rwclough 1:1eb96189824d 4
rwclough 1:1eb96189824d 5 // Prototypes
rwclough 1:1eb96189824d 6 void firstComm(void);
rwclough 1:1eb96189824d 7 void directCommand(int *buffer);
rwclough 1:1eb96189824d 8 void writeSingle(int *buffer, int length);
rwclough 1:1eb96189824d 9 void readSingle(int *buffer, int number);
rwclough 1:1eb96189824d 10 void turnRfOn(void);
rwclough 1:1eb96189824d 11 void turnRfOff(void);
rwclough 1:1eb96189824d 12 void writeIsoControl(int iso_control);
rwclough 1:1eb96189824d 13 void resetIrqStatus(void);
rwclough 1:1eb96189824d 14 void iso15693FindTag(void);
rwclough 1:1eb96189824d 15 void Iso15693Anticollision(int *mask, int length);
rwclough 1:1eb96189824d 16
rwclough 1:1eb96189824d 17 // Booleans
rwclough 1:1eb96189824d 18 #define DESELECT 1
rwclough 1:1eb96189824d 19 #define SELECT 0
rwclough 1:1eb96189824d 20 #define ADDRESS 0
rwclough 1:1eb96189824d 21 #define COMMAND 1
rwclough 1:1eb96189824d 22 #define WRITE 0
rwclough 1:1eb96189824d 23 #define READ 1
rwclough 1:1eb96189824d 24
rwclough 1:1eb96189824d 25 // Direct commands
rwclough 1:1eb96189824d 26 #define IDLE 0x00
rwclough 1:1eb96189824d 27 #define SOFT_INIT 0x03
rwclough 1:1eb96189824d 28 #define INITIAL_RF_COLLISION 0x04
rwclough 1:1eb96189824d 29 #define RESPONSE_RF_COLLISION_N 0x05
rwclough 1:1eb96189824d 30 #define RESPONSE_RF_COLLISION_0 0x06
rwclough 1:1eb96189824d 31 #define RESET 0x0F
rwclough 1:1eb96189824d 32 #define TRANSMIT_NO_CRC 0x10
rwclough 1:1eb96189824d 33 #define TRANSMIT_CRC 0x11
rwclough 1:1eb96189824d 34 #define DELAY_TRANSMIT_NO_CRC 0x12
rwclough 1:1eb96189824d 35 #define DELAY_TRANSMIT_CRC 0x13
rwclough 1:1eb96189824d 36 #define TRANSMIT_NEXT_SLOT 0x14
rwclough 1:1eb96189824d 37 #define CLOSE_SLOT_SEQUENCE 0x15
rwclough 1:1eb96189824d 38 #define STOP_DECODERS 0x16
rwclough 1:1eb96189824d 39 #define RUN_DECODERS 0x17
rwclough 1:1eb96189824d 40 #define CHECK_INTERNAL_RF 0x18
rwclough 1:1eb96189824d 41 #define CHECK_EXTERNAL_RF 0x19
rwclough 1:1eb96189824d 42 #define ADJUST_GAIN 0x1A
rwclough 1:1eb96189824d 43
rwclough 1:1eb96189824d 44 // Registers
rwclough 1:1eb96189824d 45 #define CHIP_STATUS_CONTROL 0x00
rwclough 1:1eb96189824d 46 #define ISO_CONTROL 0x01
rwclough 1:1eb96189824d 47 #define ISO_14443B_OPTIONS 0x02
rwclough 1:1eb96189824d 48 #define ISO_14443A_OPTIONS 0x03
rwclough 1:1eb96189824d 49 #define TX_TIMER_EPC_HIGH 0x04
rwclough 1:1eb96189824d 50 #define TX_TIMER_EPC_LOW 0x05
rwclough 1:1eb96189824d 51 #define TX_PULSE_LENGTH_CONTROL 0x06
rwclough 1:1eb96189824d 52 #define RX_NO_RESPONSE_WAIT_TIME 0x07
rwclough 1:1eb96189824d 53 #define RX_WAIT_TIME 0x08
rwclough 1:1eb96189824d 54 #define MODULATOR_CONTROL 0x09
rwclough 1:1eb96189824d 55 #define RX_SPECIAL_SETTINGS 0x0A
rwclough 1:1eb96189824d 56 #define REGULATOR_CONTROL 0x0B
rwclough 1:1eb96189824d 57 #define IRQ_STATUS 0x0C
rwclough 1:1eb96189824d 58 #define IRQ_MASK 0x0D
rwclough 1:1eb96189824d 59 #define COLLISION_POSITION 0x0E
rwclough 1:1eb96189824d 60 #define RSSI_LEVELS 0x0F
rwclough 1:1eb96189824d 61 #define SPECIAL_FUNCTION_1 0x10
rwclough 1:1eb96189824d 62 #define SPECIAL_FUNCTION_2 0x11
rwclough 1:1eb96189824d 63 #define RAM_0 0x12
rwclough 1:1eb96189824d 64 #define RAM_1 0x13
rwclough 1:1eb96189824d 65 #define FIFO_IRQ_LEVELS_ADJ 0x14
rwclough 1:1eb96189824d 66 #define RESERVED 0x15
rwclough 1:1eb96189824d 67 #define NFC_LOW_DETECTION 0x16
rwclough 1:1eb96189824d 68 #define UNKNOWN 0x17
rwclough 1:1eb96189824d 69 #define NFC_TARGET_LEVEL 0x18
rwclough 1:1eb96189824d 70 #define NFC_TARGET_PROTOCOL 0x19
rwclough 1:1eb96189824d 71 #define TEST_SETTINGS_1 0x1A
rwclough 1:1eb96189824d 72 #define TEST_SETTINGS_2 0x1B
rwclough 1:1eb96189824d 73 #define FIFO_STATUS 0x1C