interrupt handling
readerComm.h@10:98a58968dc7d, 2015-04-09 (annotated)
- Committer:
- soumi_ghsoh
- Date:
- Thu Apr 09 22:09:35 2015 +0000
- Revision:
- 10:98a58968dc7d
- Parent:
- 9:9266e0109d26
- Child:
- 11:d5e8f47880f1
sg apr 9/15
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
rwclough | 1:1eb96189824d | 1 | |
rwclough | 1:1eb96189824d | 2 | // Prototypes |
soumi_ghsoh | 7:96baf1b2fd07 | 3 | //void SpiInit1(void); // SPI 250 Khz |
soumi_ghsoh | 7:96baf1b2fd07 | 4 | void SpiInit(void); // SPI 1Mhz |
soumi_ghsoh | 7:96baf1b2fd07 | 5 | void trf797xDirectCommand(uint8_t *buffer); // send direct command to trf7970a |
soumi_ghsoh | 7:96baf1b2fd07 | 6 | void trf797xWriteSingle(uint8_t *buffer, uint8_t length); // write to trf7970a register |
soumi_ghsoh | 7:96baf1b2fd07 | 7 | void trf797xReadSingle(uint8_t *buffer, uint8_t number); // read trf7970a register |
soumi_ghsoh | 7:96baf1b2fd07 | 8 | void trf797xReadContinuous(uint8_t *buffer, uint8_t length); // read continuous bytes from trf7970a |
soumi_ghsoh | 7:96baf1b2fd07 | 9 | void trf797xRawWrite(uint8_t *buffer, uint8_t length); // raw write to trf7970a FIFO |
soumi_ghsoh | 7:96baf1b2fd07 | 10 | void PowerUpNFC(void); // powerup trf7970a |
soumi_ghsoh | 9:9266e0109d26 | 11 | void PowerUpNFC2(void); |
soumi_ghsoh | 7:96baf1b2fd07 | 12 | void PowerDownNFC(void); // powerdown trf7970a |
soumi_ghsoh | 7:96baf1b2fd07 | 13 | void NFCInit(void); // initialize trf7970 iso control =0x02, chip status control=0x20, modulator=0x21 |
soumi_ghsoh | 7:96baf1b2fd07 | 14 | void RegisterReInitNFC(void); // reinitialize nfc status registers |
soumi_ghsoh | 7:96baf1b2fd07 | 15 | void RegistersReadNFC(void); // read nfc status registers |
soumi_ghsoh | 7:96baf1b2fd07 | 16 | void InventoryReqNFC(void); // inventory request to trf7970a |
soumi_ghsoh | 7:96baf1b2fd07 | 17 | void MemReadReqNFC(void); // memory read request to trf7970a |
soumi_ghsoh | 7:96baf1b2fd07 | 18 | void ReadNFC(void); // read teag ID/Single Read |
soumi_ghsoh | 7:96baf1b2fd07 | 19 | void PollNFC(uint8_t *irqStatus); // read rx complete irq from trf7970a. |
soumi_ghsoh | 9:9266e0109d26 | 20 | void handlerNFC(void); // trf7970 irq handler |
soumi_ghsoh | 10:98a58968dc7d | 21 | void StandByNFC(void); |
soumi_ghsoh | 10:98a58968dc7d | 22 | //uint8_t pwr_mode ; |
soumi_ghsoh | 9:9266e0109d26 | 23 | |
soumi_ghsoh | 9:9266e0109d26 | 24 | |
soumi_ghsoh | 5:93c612f43ec2 | 25 | // Booleans |
soumi_ghsoh | 10:98a58968dc7d | 26 | #define DESELECT 1 |
soumi_ghsoh | 10:98a58968dc7d | 27 | #define SELECT 0 |
soumi_ghsoh | 10:98a58968dc7d | 28 | #define ADDRESS 0 |
soumi_ghsoh | 10:98a58968dc7d | 29 | #define COMMAND 1 |
soumi_ghsoh | 10:98a58968dc7d | 30 | #define WRITE 0 |
soumi_ghsoh | 10:98a58968dc7d | 31 | #define READ 1 |
soumi_ghsoh | 10:98a58968dc7d | 32 | |
soumi_ghsoh | 5:93c612f43ec2 | 33 | //led |
soumi_ghsoh | 5:93c612f43ec2 | 34 | #define LED_ON 0 |
soumi_ghsoh | 5:93c612f43ec2 | 35 | #define LED_OFF 1 |
soumi_ghsoh | 5:93c612f43ec2 | 36 | #define FALSE 0 |
soumi_ghsoh | 5:93c612f43ec2 | 37 | #define TRUE 1 |
rwclough | 1:1eb96189824d | 38 | |
soumi_ghsoh | 5:93c612f43ec2 | 39 | // Direct commands for trf797x |
rwclough | 1:1eb96189824d | 40 | #define IDLE 0x00 |
rwclough | 1:1eb96189824d | 41 | #define SOFT_INIT 0x03 |
rwclough | 1:1eb96189824d | 42 | #define INITIAL_RF_COLLISION 0x04 |
rwclough | 1:1eb96189824d | 43 | #define RESPONSE_RF_COLLISION_N 0x05 |
rwclough | 1:1eb96189824d | 44 | #define RESPONSE_RF_COLLISION_0 0x06 |
rwclough | 1:1eb96189824d | 45 | #define RESET 0x0F |
rwclough | 1:1eb96189824d | 46 | #define TRANSMIT_NO_CRC 0x10 |
rwclough | 1:1eb96189824d | 47 | #define TRANSMIT_CRC 0x11 |
rwclough | 1:1eb96189824d | 48 | #define DELAY_TRANSMIT_NO_CRC 0x12 |
rwclough | 1:1eb96189824d | 49 | #define DELAY_TRANSMIT_CRC 0x13 |
rwclough | 1:1eb96189824d | 50 | #define TRANSMIT_NEXT_SLOT 0x14 |
rwclough | 1:1eb96189824d | 51 | #define CLOSE_SLOT_SEQUENCE 0x15 |
rwclough | 1:1eb96189824d | 52 | #define STOP_DECODERS 0x16 |
rwclough | 1:1eb96189824d | 53 | #define RUN_DECODERS 0x17 |
rwclough | 1:1eb96189824d | 54 | #define CHECK_INTERNAL_RF 0x18 |
rwclough | 1:1eb96189824d | 55 | #define CHECK_EXTERNAL_RF 0x19 |
rwclough | 1:1eb96189824d | 56 | #define ADJUST_GAIN 0x1A |
rwclough | 1:1eb96189824d | 57 | |
soumi_ghsoh | 5:93c612f43ec2 | 58 | // Registers for trf797x |
rwclough | 1:1eb96189824d | 59 | #define CHIP_STATUS_CONTROL 0x00 |
rwclough | 1:1eb96189824d | 60 | #define ISO_CONTROL 0x01 |
rwclough | 1:1eb96189824d | 61 | #define ISO_14443B_OPTIONS 0x02 |
rwclough | 1:1eb96189824d | 62 | #define ISO_14443A_OPTIONS 0x03 |
rwclough | 1:1eb96189824d | 63 | #define TX_TIMER_EPC_HIGH 0x04 |
rwclough | 1:1eb96189824d | 64 | #define TX_TIMER_EPC_LOW 0x05 |
rwclough | 1:1eb96189824d | 65 | #define TX_PULSE_LENGTH_CONTROL 0x06 |
rwclough | 1:1eb96189824d | 66 | #define RX_NO_RESPONSE_WAIT_TIME 0x07 |
rwclough | 1:1eb96189824d | 67 | #define RX_WAIT_TIME 0x08 |
rwclough | 1:1eb96189824d | 68 | #define MODULATOR_CONTROL 0x09 |
rwclough | 1:1eb96189824d | 69 | #define RX_SPECIAL_SETTINGS 0x0A |
rwclough | 1:1eb96189824d | 70 | #define REGULATOR_CONTROL 0x0B |
rwclough | 1:1eb96189824d | 71 | #define IRQ_STATUS 0x0C |
rwclough | 1:1eb96189824d | 72 | #define IRQ_MASK 0x0D |
rwclough | 1:1eb96189824d | 73 | #define COLLISION_POSITION 0x0E |
rwclough | 1:1eb96189824d | 74 | #define RSSI_LEVELS 0x0F |
rwclough | 1:1eb96189824d | 75 | #define SPECIAL_FUNCTION_1 0x10 |
rwclough | 1:1eb96189824d | 76 | #define SPECIAL_FUNCTION_2 0x11 |
rwclough | 1:1eb96189824d | 77 | #define RAM_0 0x12 |
rwclough | 1:1eb96189824d | 78 | #define RAM_1 0x13 |
rwclough | 1:1eb96189824d | 79 | #define FIFO_IRQ_LEVELS_ADJ 0x14 |
rwclough | 1:1eb96189824d | 80 | #define RESERVED 0x15 |
rwclough | 1:1eb96189824d | 81 | #define NFC_LOW_DETECTION 0x16 |
rwclough | 2:bd5afc5aa139 | 82 | #define NFCID 0x17 |
rwclough | 1:1eb96189824d | 83 | #define NFC_TARGET_LEVEL 0x18 |
rwclough | 1:1eb96189824d | 84 | #define NFC_TARGET_PROTOCOL 0x19 |
rwclough | 1:1eb96189824d | 85 | #define TEST_SETTINGS_1 0x1A |
rwclough | 1:1eb96189824d | 86 | #define TEST_SETTINGS_2 0x1B |
soumi_ghsoh | 7:96baf1b2fd07 | 87 | #define FIFO_COUNTER 0x1C |
rwclough | 2:bd5afc5aa139 | 88 | #define TX_LENGTH_BYTE_1 0x1D |
rwclough | 2:bd5afc5aa139 | 89 | #define TX_LENGTH_BYTE_2 0x1E |
rwclough | 2:bd5afc5aa139 | 90 | #define FIFO 0x1F |
rwclough | 2:bd5afc5aa139 | 91 | |
rwclough | 2:bd5afc5aa139 | 92 | // BITs |
rwclough | 2:bd5afc5aa139 | 93 | #define BIT0 0x01 // 0b00000001 |
rwclough | 2:bd5afc5aa139 | 94 | #define BIT1 0x02 // 0b00000010 |
rwclough | 2:bd5afc5aa139 | 95 | #define BIT2 0x40 // 0b00000100 |
rwclough | 2:bd5afc5aa139 | 96 | #define BIT3 0x08 // 0b00001000 |
rwclough | 2:bd5afc5aa139 | 97 | #define BIT4 0x10 // 0b00010000 |
rwclough | 2:bd5afc5aa139 | 98 | #define BIT5 0x20 // 0b00100000 |
rwclough | 2:bd5afc5aa139 | 99 | #define BIT6 0x40 // 0b01000000 |
rwclough | 2:bd5afc5aa139 | 100 | #define BIT7 0x80 // 0b10000000 |
rwclough | 2:bd5afc5aa139 | 101 | |
rwclough | 2:bd5afc5aa139 | 102 | // Misc |
rwclough | 2:bd5afc5aa139 | 103 | #define SIXTEEN_SLOTS 0x06 |
rwclough | 2:bd5afc5aa139 | 104 | #define ONE_SLOT 0x26 |
soumi_ghsoh | 10:98a58968dc7d | 105 | //power modes |
soumi_ghsoh | 10:98a58968dc7d | 106 | //#if STANDBY |
soumi_ghsoh | 10:98a58968dc7d | 107 | //#endif |
soumi_ghsoh | 10:98a58968dc7d | 108 | // |
soumi_ghsoh | 10:98a58968dc7d | 109 | //#if NFC_3V |
soumi_ghsoh | 10:98a58968dc7d | 110 | //#define PWR_MODE4_3V pwr_mode=0x20 |
soumi_ghsoh | 10:98a58968dc7d | 111 | //#endif |
soumi_ghsoh | 10:98a58968dc7d | 112 | // |
soumi_ghsoh | 10:98a58968dc7d | 113 | //#if NFV_5V |
soumi_ghsoh | 10:98a58968dc7d | 114 | ////#define PWR_MODE4_5V pwr_mode=0x21 |
soumi_ghsoh | 10:98a58968dc7d | 115 | //#endif |
soumi_ghsoh | 5:93c612f43ec2 | 116 | |
soumi_ghsoh | 10:98a58968dc7d | 117 | #define NFC_SLEEP EN2=1 |
soumi_ghsoh | 10:98a58968dc7d | 118 | #define NFC_C_PWR_DOWN EN2=0 |
soumi_ghsoh | 10:98a58968dc7d | 119 | #define NFC_ON EN=1 |
soumi_ghsoh | 10:98a58968dc7d | 120 | #define NFC_OFF EN=0 |
soumi_ghsoh | 10:98a58968dc7d | 121 | //#define PWR_MODE4_3V pwr_mode=0x20 |
soumi_ghsoh | 10:98a58968dc7d | 122 | //#define PWR_MODE4_5V pwr_mode=0x21 |
soumi_ghsoh | 10:98a58968dc7d | 123 | //#define PWR_STANDBY_3V pwr_mode =0x81 //enable this to operate trf7970a in standby mode. |
soumi_ghsoh | 10:98a58968dc7d | 124 | //#define PWR_STANDBY_5V pwr_mode =0x80 |