Sorry if this is off-topic for an Mbed but I'll try here first as I'm new to this ARM stuff. If it's off-topic then a pointer to a forum where I should post questions like this would be great, tia.

I'm trying to use the SSP1 is slave mode and wanted to assert an interrupt when a new byte of data enters the Rx FIFO. However, after looking at the user manual (chapter 18 / 6.6) it seems the only interrupt I have is RTIM. But this only happens when the fifo is not empty and after no data has been read for a "timeout period". Problem is, how is this "timeout period" defined? I can't find anywhere that this period is setup or defined in the user manual. Even reading chapter 6 section 3 I can see ID 14 and 15 are the IRQ vectors but still can't find out what this timeout period thing is.

The only other interrupt seems to be RXIM but this is only going to assert when "the Rx FIFO is half full" and not on "byte going into the Rx FIFO".

Hi Andy,

A really good forum for support on the low level details of the LPC chips is the Yahoo LPC2000 forum (I know it is an LPC1000, but that is the main forum people use).

That said, I don't think it is off topic here either (maybe we should have a ninja/low-level forum for these chip-specific questions?). I don't know the answer, but these facts might help you:

• I'm pretty sure the SSP block is an ARM Primecell IP block; see the ARM Primecell SSP Technical Reference Manual
• 3.4.4 SSPRTINTR says "The receive timeout interrupt is asserted when the receive FIFO is not empty and the PrimeCell SSP has remained idle for a fixed 32 bit period.". This suggests there timeout is configurable by the chip implementor.
• I suspect therefore that this has been set to a fixed power-of-2 number, and will therefore be a power of 2 multiple of the pre-scaler clk output.

If you can't find this anywhere in the NXP documentation, you could possibly run a test with the SSP block set really slow, and just time how long it takes between a rx and interrupt. Of course, final thing is I could raise a issue with NXP to find it out, but I suspect with this information you may find it quicker to determine yourself!

Hope that helps,

Simon

Hi Simon,

Thanks for the excellent reply :)  With regards to a new forum I'm yes/no on that. Good idea to group stuff like that but bad idea to take useful information away into another area people may think "woo, that's not for me" when in fact it often can be. So, best leave that with the site admins to ponder!

I'll go take a look at the references you supplied to enlighten myself. I've 25yrs of 8bit experience but the ARM is all new to me. I do find it odd that this interrupt basically says "hey dude, there's data you've not polled for in a while waiting here" rather than "hey dude, handle this now". Imho I wouldn't describe that as an "interrupt", more of a "nudge nudge, you missed something" ;)

I do have some decent test equipment so I may welll time it. But first I need to get LPC17xx.h more firmly in my grasp as I don't want to test the latency of the mbed C++ libraries (which I've already had some issues with http://mbed.org/forum/mbed/topic/584 ).

I'll update this thread if and when I find out more.

--Andy