Hi,

Can we make the clock of any peripheral (say the PWM) be higher than 24 MHz, which is the frequency set by the mbed initialization code?

Thank you.

Cesar Pascual

No one knows?

Simon Ford?

Hi Cesar,

Assuming you are happy to poke registers, you should just be able to set the clock divider register for your chosen peripheral to /1, /2 or /4 (default is /4).

See LPC17xx.h L137

Simon

Hi Simon. Thanks for answering.

I'm happy to poke registers, but the errata sheet for the LPC1768 says we can't change PCLKSEL0 after PLL0 has been set. And, of course, PLL0 has already been set by the mbed initialization code.

The errata sheet ES_LPC1768.pdf Rev.4 (19 July 2010) says that there is a functional problem with PCLKSELx. See Section 3.5:
------------------------------------
3.5 PCLKSELx.1: Peripheral Clock Selection Registers must be set before enabling and connecting PLL0
Introduction:
A pair of bits in the Peripheral Clock Registers (PCLKSEL0 and PCLKSEL1) controls the
rate of the clock signal that will be supplied to APB0 and APB1 peripherals.
Problem:
If the Peripheral Clock Registers (PCLKSEL0 and PCLKSEL1) are set or changed after
PLL0 is enabled and connected, the value written into the Peripheral Clock Selection
Registers may not take effect. It is not possible to change the Peripheral Clock Selection
settings once PLL0 is enabled and connected.
Work-around:
Peripheral Clock Selection Registers must be set before enabling and connecting PLL0.
------------------------------------

So, do I have any way to set PCLKSEL0 to the value I want? I need to run the PWM module at 96 MHz.

Thanks.

I think it just means that you need to disconnect and disable PLL, set clocks, then enable PLL again.

I'll pray it is that way, but I find it suspicious that NXP didn't write a sentence like yours in their "Work-around" paragraph.

Thanks.

Hi Cesar,

Please get back to me when you know the results. If you are still having problems, we'll investigate.

Simon

Hi Simon,

I thought I couldn't check it until quite later, because I was stuck with another thing, but I solved that other part, and I have just been able to check this thing of the peripheral clock.

Result: Yes, I am able to change the peripheral clock (just writing to PCLKSEL0) even after PLL0 has been activated (by the mbed initialization code). The errata sheet seems to be wrong or, at least, that problem not always exists. The errata sheet is for LPC1768 revision "-", my LPC1768 (in the mbed) is revision "-" (so, the exact same revision), and that problem does NOT exist for me (at least as far as the PWM peripheral is concerned). I have double checked it in several ways. For instance, I have even been able to generate a PWM signal with a repetition rate of 48 MHz (which is higher than the default 24 MHz clock that all peripherals get). And I have NOT needed to disable PLL0, change PCLKSEL0, and enable PLL0 again.

Conclusion: Don't worry too much about that problem described in the errata sheet.

Thanks.