Can you not manually disable the watchdog timer before entering ISP?
I think this code might disable it:
Regarding WDMOD, Section 28.4.1 of the user manual states:
Quote:
Once the WDEN and/or WDRESET bits are set they can not be cleared by software. Both flags are cleared by an external reset or a Watchdog timer underflow.
So, this is not possible, but that's by design - the intent is that once you've set the WDT, under no circumstances can it be disabled by rogue code.
My intended solution to the problem makes use of an external EEPROM. Once my application receives a serial command to enter bootloader mode, it will do the following:
- write a special code to a given location in EEPROM
- force a reset in software
- during the boot sequence, before the WDT is initialized, it will check this EEPROM location for the code. If found, it will clear the code and enter bootloader mode (skipping WDT init altogether).
The net effect is the same... Haven't implemented it yet but I don't expect any problems.
I found this technote(ics.nxp.com/support/documents/microcontrollers/pdf/an10356.pdf) at NXP site, showing ISP entry from user code for the LPC21xx series. I've tried to adapt the following to existing code to the LPC1768 using the online compiler. I think my problem is remapping the interrupt vectors can anyone shed some light on this. Should this still be possible?
The steps involved in entering ISP mode from user code are as follows: (LPC21xx)
• Configure the RXD0 pin (UART 0 receive) as input. This is done by entering the appropriate values in the PINSEL0 and IODIR0 registers.
• Configure P0.14 as an output pin.
• Clear P0.14 (Set low)
• Disable interrupts by setting the corresponding bits in the VIC Interrupt Enable Clear register (VICIntEnClear at address 0xFFFF F014) for anyinterrupt source that was previously enabled for interrupts.
• If the PLL is connected, disconnect it (Recommended).
• Set the Peripheral Bus Divider to ¼ if needed.
• If the UART is equipped with a Fractional Baud Rate generator then the Fractional Divider register (FDR) should be set to its reset value (This is not shown in the code below).
• Restore Timer1 to its reset state. Timer 1 is used by the ISP to auto baud.
• Re-Map the interrupt vectors to the boot block.
• Invoke the bootloader by calling a function that is located at the bootloader entry point, i.e. the reset vector at 0x00.
My current LPC1768 version