Revision 3:1d62b3be52e8, committed 2020-10-28

Comitter:

yuliyasm

Date:

Wed Oct 28 15:35:08 2020 +0000

Parent:

2:f480200c8600

Commit message:

new

Changed in this revision

diff -r f480200c8600 -r 1d62b3be52e8 ADE7912.cpp
--- a/ADE7912.cpp	Tue Oct 27 13:23:41 2020 +0000
+++ b/ADE7912.cpp	Wed Oct 28 15:35:08 2020 +0000
@@ -8,25 +8,35 @@
 uint8_t spiPackageReceived = 0;
 
 
+
+void ADE7912_WriteToReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length);
+void ADE7912_ReadFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length);
+uint8_t ADE7912_ReadADCVersionFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
+uint8_t ADE7912_ReadTemposFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
+//void ADE7912_InitEXTIForDReady(struct ADE7912_Inst *ade, GPIO_TypeDef *port, uint16_t pin);
+
+
+
 void ADE7912_WriteToReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length)
 {
-    HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_RESET);
+	HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_RESET);
+	
+	uint8_t addrBuf = addr | ADE7912_WRITE_MODE;
+	WriteToRegisterBySPI(ade->spi, addrBuf, buf, length);
+	
+	HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_SET);
+}
 
-    uint8_t addrBuf = addr | ADE7912_WRITE_MODE;
-    WriteToRegisterBySPI(ade->spi, addrBuf, buf, length);
-
-    HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_SET);
-}
 
 
 void ADE7912_ReadFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length)
 {
-    HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_RESET);
+	HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_RESET);
+	
+	uint8_t addrBuf = addr | ADE7912_READ_MODE;
+	ReadFromRegisterBySPI(ade->spi, addrBuf, buf, length);
 
-    uint8_t addrBuf = addr | ADE7912_READ_MODE;
-    ReadFromRegisterBySPI(ade->spi, addrBuf, buf, length);
-
-    HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_SET);
+	HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_SET);
 }
 
 
@@ -35,7 +45,7 @@
 //{
 //	ade->DReadyPort = port;
 //	ade->DReadyPin = pin;
-//
+//	
 //	switch (pin)
 //	{
 //		case GPIO_PIN_0:
@@ -87,7 +97,7 @@
 //			ade->EXTIinterrupt = EXTI15_10_IRQn;
 //		break;
 //	}
-//
+//	
 //	GPIO_InitTypeDef GPIO_InitStruct = {0};
 
 //  /* GPIO Ports Clock Enable */
@@ -100,319 +110,332 @@
 //  HAL_GPIO_Init(port, &GPIO_InitStruct);
 
 //  /* EXTI interrupt init*/
-//
-//
-//
-//
+//	
+//	
+//	
+//	
 //  HAL_NVIC_SetPriority(EXTIinterrupt, 0, 0);
 //  HAL_NVIC_EnableIRQ(EXTIinterrupt);
 //}
 
 
+
 struct ADE7912_Inst* New_ADE7912(SPI_HandleTypeDef *spi)
 {
-    struct ADE7912_Inst *ade = (struct ADE7912_Inst *)malloc(sizeof(struct ADE7912_Inst));
-    ade->spi = spi;
-    for(int phase = 0; phase < 4; phase += 1) {
-        ade->CS_pins[phase] = NULL;
-        ade->CS_ports[phase] = GPIOA;
-        ade->phasesData[phase] = NULL;
-        ade->phasesEnable[phase] = 0;
-    }
-    return ade;
+	struct ADE7912_Inst *ade = (struct ADE7912_Inst *)malloc(sizeof(struct ADE7912_Inst));
+	ade->spi = spi;
+	for(int phase = 0; phase < 4; phase += 1)
+	{
+		ade->CS_pins[phase] = NULL;
+		ade->CS_ports[phase] = GPIOA;
+		ade->phasesData[phase] = NULL;
+		ade->phasesEnable[phase] = 0;
+	}
+	return ade;
 }
 
 
 
 void ADE7912_PhaseInit(struct ADE7912_Inst *ade, struct ADE7912_Phase_Settings *settings, enum ADE7912_Phases phase)
 {
-    ade->CS_ports[phase] = settings->CS_port;
-    ade->CS_pins[phase] = settings->CS_pin;
-
-    ade->phasesData[phase] = (struct ADE7912_BrushRead_Data *)malloc(sizeof(struct ADE7912_BrushRead_Data));
-    ade->phasesData[phase]->V1WV = 0;
-    ade->phasesData[phase]->V2WV = 0;
-    ade->phasesData[phase]->IWV = 0;
-    ade->phasesData[phase]->ADC_CRC = 0;
-    ade->phasesData[phase]->STATUS0 = 0;
-    ade->phasesData[phase]->CNT_SNAPSHOT = 0;
-
-    ADE7912_ResetPhase(ade, phase);
-
-    ade->version[phase] = ADE7912_ReadADCVersionFromReg(ade, phase);
-
-    ADE7912_SetDataUpdateFreq(ade, phase, settings->freq);
+	ade->CS_ports[phase] = settings->CS_port;
+	ade->CS_pins[phase] = settings->CS_pin;
 
-    ADE7912_SetPwrConverterEnabled(ade, phase, 1);
-
-    ADE7912_SetTempEnabled(ade, phase, 0);
-
-    ADE7912_SetBandwidth(ade, phase, settings->bandwidth);
-
-    ade->tempGain[phase] = settings->bandwidth == BW_3K3HZ ? ADE7912_TEMPGAIN_WITH_3K3_BW : ADE7912_TEMPGAIN_WITH_2K_BW;
-
-    ADE7912_SetCLKOUTFunctionality(ade, phase, settings->clkoutFunc);
-
-    uint32_t tmp;
-    tmp = ADE7912_ReadTemposFromReg(ade, phase) << 11;
-    //if (tmp & 0x00040000) tmp = ~(~(tmp - 1) | 0x0007FFFF) + 1;
-    ade->tempos[phase] = ADE7912_TEMPGAIN_WITH_3K3_BW * (float)tmp;
-
-    ADE7912_EnablePhase(ade, phase);
-
+	ade->phasesData[phase] = (struct ADE7912_BrushRead_Data *)malloc(sizeof(struct ADE7912_BrushRead_Data));
+	ade->phasesData[phase]->V1WV = 0;
+	ade->phasesData[phase]->V2WV = 0;
+	ade->phasesData[phase]->IWV = 0;
+	ade->phasesData[phase]->ADC_CRC = 0;
+	ade->phasesData[phase]->STATUS0 = 0;
+	ade->phasesData[phase]->CNT_SNAPSHOT = 0;
+	
+	ADE7912_ResetPhase(ade, phase);
+	
+	ade->version[phase] = ADE7912_ReadADCVersionFromReg(ade, phase);
+	
+	ADE7912_SetDataUpdateFreq(ade, phase, settings->freq);
+	
+	ADE7912_SetPwrConverterEnabled(ade, phase, 1);
+	
+	ADE7912_SetTempEnabled(ade, phase, 0);
+	
+	ADE7912_SetBandwidth(ade, phase, settings->bandwidth);
+	
+	ade->tempGain[phase] = settings->bandwidth == BW_3K3HZ ? ADE7912_TEMPGAIN_WITH_3K3_BW : ADE7912_TEMPGAIN_WITH_2K_BW;
+	
+	ADE7912_SetCLKOUTFunctionality(ade, phase, settings->clkoutFunc);
+	
+	uint32_t tmp;
+	tmp = ADE7912_ReadTemposFromReg(ade, phase) << 11;
+	//if (tmp & 0x00040000) tmp = ~(~(tmp - 1) | 0x0007FFFF) + 1;
+	ade->tempos[phase] = ADE7912_TEMPGAIN_WITH_3K3_BW * (float)tmp;
+	
+	ADE7912_EnablePhase(ade, phase);
+	
 }
 
 
 
 void ADE7912_EnablePhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    ade->phasesEnable[phase] = 1;
+	ade->phasesEnable[phase] = 1;
 }
 
 
 
 void ADE7912_DisablePhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    ade->phasesEnable[phase] = 0;
+	ade->phasesEnable[phase] = 0;
 }
 
 void ADE7912_ResetPhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    // Software reset start
-    uint8_t buf;
-    ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
-
-    buf |= ADE7912_CONFIG_BIT_SWRST;
-    ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
-
-    // Wait for reset finished
-    while (1) {
-        uint8_t buf;
-        ADE7912_ReadFromReg(ade, phase, ADE7912_STATUS0_REG_ADDRESS, &buf, 1);
-
-        if (~buf & ADE7912_STATUS0_BIT_RESET_ON) break;
-    }
+	// Software reset start
+	uint8_t buf;
+	ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
+	
+	buf |= ADE7912_CONFIG_BIT_SWRST;
+	ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
+	
+	// Wait for reset finished
+	while (1)
+	{
+		uint8_t buf;
+		ADE7912_ReadFromReg(ade, phase, ADE7912_STATUS0_REG_ADDRESS, &buf, 1); 
+		
+		if (~buf & ADE7912_STATUS0_BIT_RESET_ON) break;
+	}
 }
 
-
+uint8_t buf[14];
+			uint32_t tmp;
 
 void ADE7912_UpdateData(struct ADE7912_Inst *ade)
 {
-    uint8_t buf[14];
 
-    for(int phase = 0; phase < 4; phase += 1) {
-        if (ade->phasesEnable[phase]) {
-            ADE7912_ReadFromReg(ade, static_cast<ADE7912_Phases>(phase), ADE7912_BRUSH_READ_MODE, buf, 14);
-
-            uint32_t tmp;
-
-            tmp = (buf[0] << 16) | (buf[1] << 8) | buf[2];
-            if (tmp > 0x007FFFFF) tmp |= 0xFF000000;
-            ade->phasesData[phase]->IWV = (int32_t)tmp;
+	
+	for(int phase = 0; phase < 4; phase += 1)
+	{
+		if (ade->phasesEnable[phase])
+		{
+			ADE7912_ReadFromReg(ade, static_cast<ADE7912_Phases>(phase), ADE7912_BRUSH_READ_MODE, buf, 14);
+			
 
-            tmp = (buf[3] << 16) | (buf[4] << 8) | buf[5];
-            if (tmp > 0x007FFFFF) tmp |= 0xFF000000;
-            ade->phasesData[phase]->V1WV = (int32_t)tmp;
-
-            tmp = (buf[6] << 16) | (buf[7] << 8) | buf[8];
-            if (tmp > 0x007FFFFF) tmp |= 0xFF000000;
-            ade->phasesData[phase]->V2WV = (int32_t)tmp;
-
-            ade->phasesData[phase]->ADC_CRC = (buf[9] << 8) | buf[10];
-            ade->phasesData[phase]->STATUS0 = buf[11];
-            ade->phasesData[phase]->CNT_SNAPSHOT = (buf[12] << 8) | buf[13];
-        }
-    }
+			
+			tmp = (buf[0] << 16) | (buf[1] << 8) | buf[2];
+			if (tmp > 0x007FFFFF) tmp |= 0xFF000000; 
+			ade->phasesData[phase]->IWV = (int32_t)tmp;
+			
+			tmp = (buf[3] << 16) | (buf[4] << 8) | buf[5];
+			if (tmp > 0x007FFFFF) tmp |= 0xFF000000; 
+			ade->phasesData[phase]->V1WV = (int32_t)tmp;
+			
+			tmp = (buf[6] << 16) | (buf[7] << 8) | buf[8];
+			if (tmp > 0x007FFFFF) tmp |= 0xFF000000; 
+			ade->phasesData[phase]->V2WV = (int32_t)tmp;
+			
+			ade->phasesData[phase]->ADC_CRC = (buf[9] << 8) | buf[10];
+			ade->phasesData[phase]->STATUS0 = buf[11];
+			ade->phasesData[phase]->CNT_SNAPSHOT = (buf[12] << 8) | buf[13];
+		}
+	}
 }
 
 
 
 int ADE7912_BrrushReadData(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, struct ADE7912_BrushRead_Data *data)
 {
-    if (ade->phasesEnable[phase]) {
-        data->IWV = ade->phasesData[phase]->IWV;
-        data->V1WV = ade->phasesData[phase]->V1WV;
-        data->V2WV = ade->phasesData[phase]->V2WV;
-        data->ADC_CRC = ade->phasesData[phase]->ADC_CRC;
-        data->STATUS0 = ade->phasesData[phase]->STATUS0;
-        data->CNT_SNAPSHOT = ade->phasesData[phase]->CNT_SNAPSHOT;
-
-        return 0;
-    } else return 1;
+	if (ade->phasesEnable[phase]) 
+	{
+		data->IWV = ade->phasesData[phase]->IWV;
+		data->V1WV = ade->phasesData[phase]->V1WV;
+		data->V2WV = ade->phasesData[phase]->V2WV;
+		data->ADC_CRC = ade->phasesData[phase]->ADC_CRC;
+		data->STATUS0 = ade->phasesData[phase]->STATUS0;
+		data->CNT_SNAPSHOT = ade->phasesData[phase]->CNT_SNAPSHOT;
+		
+		return 0;
+	} else return 1;
 }
 
 
 
 void ADE7912_SetDataUpdateFreq(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_DataUpdateFreq freq)
 {
-
-    uint8_t buf;
-    ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
-
-    HAL_Delay(1);
-
-    buf &= (uint8_t)~ADE7912_CONFIG_ADC_FREQ;
-    switch(freq) {
-        case F_8KHZ:
-            buf |= ADE7912_CONFIG_ADC_FREQ_8K;
-            break;
-        case F_4KHZ:
-            buf |= ADE7912_CONFIG_ADC_FREQ_4K;
-            break;
-        case F_2KHZ:
-            buf |= ADE7912_CONFIG_ADC_FREQ_2K;
-            break;
-        case F_1KHZ:
-            buf |= ADE7912_CONFIG_ADC_FREQ_1K;
-            break;
-    }
-    ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
+	
+	uint8_t buf;
+	ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1); 
+	
+	HAL_Delay(1);
+	
+	buf &= (uint8_t)~ADE7912_CONFIG_ADC_FREQ;
+	switch(freq)
+	{
+		case F_8KHZ:
+			buf |= ADE7912_CONFIG_ADC_FREQ_8K;
+		break;
+		case F_4KHZ:
+			buf |= ADE7912_CONFIG_ADC_FREQ_4K;
+		break;
+		case F_2KHZ:
+			buf |= ADE7912_CONFIG_ADC_FREQ_2K;
+		break;
+		case F_1KHZ:
+			buf |= ADE7912_CONFIG_ADC_FREQ_1K;
+		break;
+	}
+	ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1); 
 }
 
 
 
 uint8_t ADE7912_ReadADCVersionFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    uint8_t buf;
-    ADE7912_ReadFromReg(ade, phase, ADE7912_STATUS1_REG_ADDRESS, &buf, 1);
-
-    return buf & ADE7912_STATUS1_BIT_VERSION;
+	uint8_t buf;
+	ADE7912_ReadFromReg(ade, phase, ADE7912_STATUS1_REG_ADDRESS, &buf, 1); 
+	
+	return buf & ADE7912_STATUS1_BIT_VERSION;
 }
 
 
 
 uint8_t ADE7912_ReadTemposFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    uint8_t buf;
-    ADE7912_ReadFromReg(ade, phase, ADE7912_TEMPOS_REG_ADDRESS, &buf, 1);
-
-    return buf;
+	uint8_t buf;
+	ADE7912_ReadFromReg(ade, phase, ADE7912_TEMPOS_REG_ADDRESS, &buf, 1); 
+	
+	return buf;
 }
 
 
 
 void ADE7912_SetPwrConverterEnabled(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, bool enabled)
 {
-    uint8_t buf;
-    ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
-
-    HAL_Delay(1);
-
-    buf &= (uint8_t)~ADE7912_CONFIG_BIT_PWRDWNENB;
-    buf |= enabled ? ADE7912_CONFIG_BIT_PWRDWNENB : 0;
-    ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
+	uint8_t buf;
+	ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1); 
+	
+	HAL_Delay(1);
+	
+	buf &= (uint8_t)~ADE7912_CONFIG_BIT_PWRDWNENB;
+	buf |= enabled ? ADE7912_CONFIG_BIT_PWRDWNENB : 0;
+	ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1); 
 }
 
 
 
 void ADE7912_SetTempEnabled(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, bool enabled)
 {
-    uint8_t buf;
-    ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
-
-    HAL_Delay(1);
-
-    buf &= (uint8_t)~ADE7912_CONFIG_BIT_TEMPENB;
-    buf |= enabled ? ADE7912_CONFIG_BIT_TEMPENB : 0;
-    ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
+	uint8_t buf;
+	ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1); 
+	
+	HAL_Delay(1);
+	
+	buf &= (uint8_t)~ADE7912_CONFIG_BIT_TEMPENB;
+	buf |= enabled ? ADE7912_CONFIG_BIT_TEMPENB : 0;
+	ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1); 
 }
 
 
 
 void ADE7912_SetBandwidth(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_Bandwidths bandwidth)
 {
-    uint8_t buf;
-    ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
-
-    HAL_Delay(1);
-
-    buf &= (uint8_t)~ADE7912_CONFIG_BIT_BW;
-    switch(bandwidth) {
-        case BW_3K3HZ:
-            buf |= 0;
-            break;
-        case BW_2KHZ:
-            buf |= ADE7912_CONFIG_BIT_BW;
-            break;
-    }
-    ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
+	uint8_t buf;
+	ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1); 
+	
+	HAL_Delay(1);
+	
+	buf &= (uint8_t)~ADE7912_CONFIG_BIT_BW;
+	switch(bandwidth)
+	{
+		case BW_3K3HZ:
+			buf |= 0;
+		break;
+		case BW_2KHZ:
+			buf |= ADE7912_CONFIG_BIT_BW;
+		break;
+	}
+	ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1); 
 }
 
 
 
 void ADE7912_LockConfigurationRegisters(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    uint8_t buf = 0xCA;
-    ADE7912_WriteToReg(ade, phase, ADE7912_LOCK_REG_ADDRESS, &buf, 1);
+	uint8_t buf = 0xCA;
+	ADE7912_WriteToReg(ade, phase, ADE7912_LOCK_REG_ADDRESS, &buf, 1); 
 }
 
 
 
 void ADE7912_UnlockConfigurationRegisters(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    uint8_t buf = 0x9C;
-    ADE7912_WriteToReg(ade, phase, ADE7912_LOCK_REG_ADDRESS, &buf, 1);
+	uint8_t buf = 0x9C;
+	ADE7912_WriteToReg(ade, phase, ADE7912_LOCK_REG_ADDRESS, &buf, 1); 
 }
 
 
 
 void ADE7912_SetCLKOUTFunctionality(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_CLKOUT_Functionality functionality)
 {
-    uint8_t buf;
-    ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
-
-    HAL_Delay(1);
-
-    buf &= (uint8_t)~ADE7912_CONFIG_BIT_CLKOUTENB;
-    switch(functionality) {
-        case CLKOUT:
-            buf |= ADE7912_CONFIG_BIT_CLKOUTENB;
-            break;
-        case DREADY:
-            buf |= 0;
-            break;
-    }
-    ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
+	uint8_t buf;
+	ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1); 
+	
+	HAL_Delay(1);
+	
+	buf &= (uint8_t)~ADE7912_CONFIG_BIT_CLKOUTENB;
+	switch(functionality)
+	{
+		case CLKOUT:
+			buf |= ADE7912_CONFIG_BIT_CLKOUTENB;
+		break;
+		case DREADY:
+			buf |= 0;
+		break;
+	}
+	ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1); 
 }
 
 
 
 uint8_t ADE7912_GetADCVersion(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    return ade->version[phase];
+	return ade->version[phase];
 }
 
 
 
 float ADE7912_GetVoltage(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    if (ade->phasesEnable[phase] == 1) {
-        return ade->phasesData[phase]->V1WV * ADE7912_VWV_TRANSLATE_COEF;
-    } else {
-        return 0;
-    }
+	if (ade->phasesEnable[phase] == 1) 
+	{
+		return ade->phasesData[phase]->V1WV * ADE7912_VWV_TRANSLATE_COEF;
+	} else {
+		return 0;
+	}
 }
 
 
 
 float ADE7912_GetCurrent(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    if (ade->phasesEnable[phase] == 1) {
-        return ade->phasesData[phase]->IWV * ADE7912_IWV_TRANSLATE_COEF;
-    } else {
-        return 0;
-    }
+	if (ade->phasesEnable[phase] == 1) 
+	{
+		return ade->phasesData[phase]->IWV * ADE7912_IWV_TRANSLATE_COEF;
+	} else {
+		return 0;
+	}
 }
 
 
 
 float ADE7912_GetTemp(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
 {
-    if (ade->phasesEnable[phase] == 1) {
-        return ade->tempGain[phase] * (float)ade->phasesData[phase]->V2WV - ade->tempos[phase] - ADE7912_CONST_TEMPOS;
-    } else {
-        return 0;
-    }
+	if (ade->phasesEnable[phase] == 1) 
+	{
+		return ade->tempGain[phase] * (float)ade->phasesData[phase]->V2WV - ade->tempos[phase] - ADE7912_CONST_TEMPOS;
+	} else {
+		return 0;
+	}
 }
 
 

diff -r f480200c8600 -r 1d62b3be52e8 ADE7912.h
--- a/ADE7912.h	Tue Oct 27 13:23:41 2020 +0000
+++ b/ADE7912.h	Wed Oct 28 15:35:08 2020 +0000
@@ -4,7 +4,6 @@
 #include "stm32h7xx_hal.h"
 #include "stdlib.h"
 
-
 // ADE7912 registers addresses
 #define ADE7912_IWV_REG_ADDRESS 						0x00
 #define ADE7912_V1WV_REG_ADDRESS 						0x08
@@ -58,61 +57,68 @@
 #define ADE7912_IWV_TRANSLATE_COEF          5.87344e-9f
 #define ADE7912_VWV_TRANSLATE_COEF          9.39369e-8f
 
-struct ADE7912_BrushRead_Data {
-    int32_t IWV;
-    int32_t V1WV;
-    int32_t V2WV;
-    uint16_t ADC_CRC;
-    uint8_t STATUS0;
-    uint16_t CNT_SNAPSHOT;
+struct ADE7912_BrushRead_Data
+{
+	int32_t IWV; 
+	int32_t V1WV;
+	int32_t V2WV;
+	uint16_t ADC_CRC;
+	uint8_t STATUS0;
+	uint16_t CNT_SNAPSHOT;
 };
 
-struct ADE7912_Inst {
-    SPI_HandleTypeDef *spi;
-    uint8_t phasesEnable[4];
-    GPIO_TypeDef *CS_ports[4];
-    uint16_t CS_pins[4];
-    struct ADE7912_BrushRead_Data *phasesData[4];
-    uint8_t version[4];
-    float tempos[4];
-    float tempGain[4];
-    GPIO_TypeDef *DReadyPort;
-    uint16_t DReadyPin;
-    IRQn_Type EXTIinterrupt;
+struct ADE7912_Inst 
+{
+	SPI_HandleTypeDef *spi;
+	uint8_t phasesEnable[4];
+	GPIO_TypeDef *CS_ports[4];
+	uint16_t CS_pins[4];
+	struct ADE7912_BrushRead_Data *phasesData[4];
+	uint8_t version[4];
+	float tempos[4];
+	float tempGain[4];
+	GPIO_TypeDef *DReadyPort;
+	uint16_t DReadyPin;
+	IRQn_Type EXTIinterrupt;
 };
 
 
 
-enum ADE7912_Phases {
-    PHASE_A = 0,
-    PHASE_B,
-    PHASE_C,
-    COM
+enum ADE7912_Phases
+{
+	PHASE_A = 0,
+	PHASE_B,
+	PHASE_C,
+	COM
 };
 
-enum ADE7912_DataUpdateFreq {
-    F_8KHZ,
-    F_4KHZ,
-    F_2KHZ,
-    F_1KHZ
+enum ADE7912_DataUpdateFreq
+{
+	F_8KHZ,
+	F_4KHZ,
+	F_2KHZ,
+	F_1KHZ
 };
 
-enum ADE7912_Bandwidths {
-    BW_3K3HZ,
-    BW_2KHZ
+enum ADE7912_Bandwidths
+{
+	BW_3K3HZ,
+	BW_2KHZ
 };
 
-enum ADE7912_CLKOUT_Functionality {
-    CLKOUT,
-    DREADY
+enum ADE7912_CLKOUT_Functionality
+{
+	CLKOUT,
+	DREADY
 };
 
-struct ADE7912_Phase_Settings {
-    GPIO_TypeDef *CS_port;
-    uint16_t CS_pin;
-    enum ADE7912_DataUpdateFreq freq;
-    enum ADE7912_Bandwidths bandwidth;
-    enum ADE7912_CLKOUT_Functionality clkoutFunc;
+struct ADE7912_Phase_Settings
+{
+	GPIO_TypeDef *CS_port;
+	uint16_t CS_pin;
+	enum ADE7912_DataUpdateFreq freq;
+	enum ADE7912_Bandwidths bandwidth;
+	enum ADE7912_CLKOUT_Functionality clkoutFunc;
 };
 
 
@@ -140,10 +146,4 @@
 float ADE7912_GetCurrent(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
 float ADE7912_GetTemp(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
 
-void ADE7912_WriteToReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length);
-void ADE7912_ReadFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length);
-uint8_t ADE7912_ReadADCVersionFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
-uint8_t ADE7912_ReadTemposFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
-//void ADE7912_InitEXTIForDReady(struct ADE7912_Inst *ade, GPIO_TypeDef *port, uint16_t pin);
-
 #endif

diff -r f480200c8600 -r 1d62b3be52e8 communication.cpp
--- a/communication.cpp	Tue Oct 27 13:23:41 2020 +0000
+++ b/communication.cpp	Wed Oct 28 15:35:08 2020 +0000
@@ -1,31 +1,36 @@
 #include "communication.h"
 #include "cmsis_os.h"
+#include <cstring>
 
-extern UART_HandleTypeDef huart3;
+//extern UART_HandleTypeDef huart3;
 enum _BOOL_ uart3PkgTransmited = _FALSE_;
 enum _BOOL_ uart3PkgReceived = _FALSE_;
 
 extern SPI_HandleTypeDef hspi1;
+ALIGN_32BYTES(volatile uint8_t spi1Buf[ALIGN32_SIZE(256)] __attribute__((section(".SRAM"))));
+ALIGN_32BYTES(volatile uint8_t spi1AddrBuf __attribute__((section(".SRAM"))));
 enum _BOOL_ spi1PkgTransmited = _FALSE_; 
 enum _BOOL_ spi1PkgReceived = _FALSE_;
 enum OP_TYPE spi1OpType = NONE;
-uint8_t *spi1Buf;
+//uint8_t *spi1Buf;
 uint8_t spi1Len;
 
 //void ReceiveUARTPackage(UART_HandleTypeDef *huart, uint8_t *buf, uint8_t len)
 //{
 //	TickType_t timeBegin = xTaskGetTickCount();
+//	//SCB_InvalidateDCache();
 //	HAL_StatusTypeDef err = HAL_UART_Receive_DMA(huart, buf, len);
 //  while (!uart3PkgReceived  && xTaskGetTickCount() - timeBegin < COMMUNICATION_WAITTING) osDelay(COMMUNICATION_DELAY);
 //  
 //	uart3PkgReceived = _FALSE_;
 //}
-//
-//
-//
+
+
+
 //void TransmitUARTPackage(UART_HandleTypeDef *huart, uint8_t *buf, uint8_t len)
 //{
 //	TickType_t timeBegin = xTaskGetTickCount();
+//	//SCB_CleanDCache();
 //	HAL_StatusTypeDef err = HAL_UART_Transmit_DMA(huart, buf, len);
 //  while (!uart3PkgTransmited  && xTaskGetTickCount() - timeBegin < COMMUNICATION_WAITTING) osDelay(COMMUNICATION_DELAY);
 //	
@@ -54,17 +59,19 @@
 
 void WriteToRegisterBySPI(SPI_HandleTypeDef *hspi, uint8_t addr, uint8_t *buf, uint8_t len)
 {
-	//TickType_t timeBegin = xTaskGetTickCount();
+//	TickType_t timeBegin = xTaskGetTickCount();
 
 	enum _BOOL_ *cpltCheck;
 	if(hspi == &hspi1) {
-		spi1Buf = buf;
+		//spi1Buf = buf;
 		spi1Len = len;
 		spi1OpType = WRITE;
 		cpltCheck = &spi1PkgTransmited;
   } 
-	
-	HAL_SPI_Transmit_DMA(hspi, &addr, 1);
+	memcpy((void*)&spi1AddrBuf, (void*)&addr, 1);
+	SCB_CleanDCache_by_Addr((uint32_t*)&spi1AddrBuf, ALIGN32_SIZE(1));
+	HAL_SPI_Transmit_DMA(hspi, (uint8_t*)&spi1AddrBuf, 1);
+	memcpy((void*)&spi1Buf, (void*)buf, 1);
 //  while (!*cpltCheck  && xTaskGetTickCount() - timeBegin < COMMUNICATION_WAITTING) osDelay(COMMUNICATION_DELAY);
 	*cpltCheck = _FALSE_;
 }
@@ -77,16 +84,18 @@
 	
 	enum _BOOL_ *cpltCheck;
 	if(hspi == &hspi1) {
-		spi1Buf = buf;
+		//spi1Buf = buf;
 		spi1Len = len;
 		spi1OpType = READ;
 		cpltCheck = &spi1PkgReceived;
   } 
 	
-	uint8_t addrBuf = addr;
-	HAL_SPI_Transmit_DMA(hspi, &addrBuf, 1);
+	memcpy((void*)&spi1AddrBuf, (void*)&addr, 1);
+	SCB_CleanDCache_by_Addr((uint32_t*)&spi1AddrBuf, ALIGN32_SIZE(1));
+	HAL_SPI_Transmit_DMA(hspi, (uint8_t*)&spi1AddrBuf, 1);
 //  while (!*cpltCheck  && xTaskGetTickCount() - timeBegin < COMMUNICATION_WAITTING) osDelay(COMMUNICATION_DELAY);
 	*cpltCheck = _FALSE_;
+	memcpy((void*)buf, (void*)&spi1Buf, spi1Len);
 }
 
 
@@ -98,11 +107,12 @@
 		{
 			case WRITE:
 				spi1OpType = CPLT;
-				HAL_SPI_Transmit_DMA(hspi, spi1Buf, spi1Len);
+				SCB_CleanDCache_by_Addr((uint32_t*)&spi1Buf, ALIGN32_SIZE(spi1Len));
+				HAL_SPI_Transmit_DMA(hspi, (uint8_t*)spi1Buf, spi1Len);
 			break;
 			case READ:
 				spi1OpType = CPLT;
-				HAL_SPI_Receive_DMA(hspi, spi1Buf, spi1Len);
+				HAL_SPI_Receive_DMA(hspi, (uint8_t*)spi1Buf, spi1Len);
 			break;
 			case CPLT:
 				spi1PkgTransmited = _TRUE_;
@@ -119,6 +129,7 @@
 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
 {
 	if(hspi == &hspi1) {
+		SCB_InvalidateDCache_by_Addr((uint32_t*)&spi1Buf, ALIGN32_SIZE(spi1Len));
 		spi1PkgReceived = _TRUE_;
 		spi1OpType = NONE;
   } 

diff -r f480200c8600 -r 1d62b3be52e8 communication.h
--- a/communication.h	Tue Oct 27 13:23:41 2020 +0000
+++ b/communication.h	Wed Oct 28 15:35:08 2020 +0000
@@ -6,6 +6,8 @@
 #define COMMUNICATION_DELAY 1
 #define COMMUNICATION_WAITTING COMMUNICATION_DELAY * 5
 
+#define ALIGN32_SIZE(SIZE_ALIGN) (((SIZE_ALIGN + 31)/32)*32)
+
 enum _BOOL_
 {
 	_TRUE_ = 1,

diff -r f480200c8600 -r 1d62b3be52e8 dma.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/dma.cpp	Wed Oct 28 15:35:08 2020 +0000
@@ -0,0 +1,73 @@
+/**
+  ******************************************************************************
+  * File Name          : dma.c
+  * Description        : This file provides code for the configuration
+  *                      of all the requested memory to memory DMA transfers.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "dma.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*----------------------------------------------------------------------------*/
+/* Configure DMA                                                              */
+/*----------------------------------------------------------------------------*/
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/**
+  * Enable DMA controller clock
+  */
+void MX_DMA_Init(void)
+{
+
+  /* DMA controller clock enable */
+  __HAL_RCC_DMA1_CLK_ENABLE();
+
+  /* DMA interrupt init */
+  /* DMA1_Stream0_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
+  /* DMA1_Stream1_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
+  /* DMA1_Stream2_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
+  /* DMA1_Stream3_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 0, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
+
+}
+
+/* USER CODE BEGIN 2 */
+
+/* USER CODE END 2 */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

diff -r f480200c8600 -r 1d62b3be52e8 dma.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/dma.h	Wed Oct 28 15:35:08 2020 +0000
@@ -0,0 +1,57 @@
+/**
+  ******************************************************************************
+  * File Name          : dma.h
+  * Description        : This file contains all the function prototypes for
+  *                      the dma.c file
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __dma_H
+#define __dma_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* DMA memory to memory transfer handles -------------------------------------*/
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_DMA_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __dma_H */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

diff -r f480200c8600 -r 1d62b3be52e8 gpio.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gpio.cpp	Wed Oct 28 15:35:08 2020 +0000
@@ -0,0 +1,102 @@
+/**
+  ******************************************************************************
+  * File Name          : gpio.c
+  * Description        : This file provides code for the configuration
+  *                      of all used GPIO pins.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "gpio.h"
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/*----------------------------------------------------------------------------*/
+/* Configure GPIO                                                             */
+/*----------------------------------------------------------------------------*/
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/** Configure pins
+     PC14-OSC32_IN (OSC32_IN)   ------> RCC_OSC32_IN
+     PC15-OSC32_OUT (OSC32_OUT)   ------> RCC_OSC32_OUT
+     PH0-OSC_IN (PH0)   ------> RCC_OSC_IN
+     PH1-OSC_OUT (PH1)   ------> RCC_OSC_OUT
+*/
+void MX_GPIO_Init(void)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, LD1_Pin|LD3_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, USB_OTG_FS_PWR_EN_Pin|PHASE_A_CS_Pin|PHASE_B_CS_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = B1_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PBPin PBPin */
+  GPIO_InitStruct.Pin = LD1_Pin|LD3_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PDPin PDPin PDPin */
+  GPIO_InitStruct.Pin = USB_OTG_FS_PWR_EN_Pin|PHASE_A_CS_Pin|PHASE_B_CS_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = USB_OTG_FS_OVCR_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  HAL_GPIO_Init(USB_OTG_FS_OVCR_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PtPin */
+  GPIO_InitStruct.Pin = LD2_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
+
+}
+
+/* USER CODE BEGIN 2 */
+
+/* USER CODE END 2 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

diff -r f480200c8600 -r 1d62b3be52e8 gpio.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gpio.h	Wed Oct 28 15:35:08 2020 +0000
@@ -0,0 +1,58 @@
+/**
+  ******************************************************************************
+  * File Name          : gpio.h
+  * Description        : This file contains all the functions prototypes for
+  *                      the gpio
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __gpio_H
+#define __gpio_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_GPIO_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ pinoutConfig_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

diff -r f480200c8600 -r 1d62b3be52e8 spi.cpp
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/spi.cpp	Wed Oct 28 15:35:08 2020 +0000
@@ -0,0 +1,188 @@
+void Error_Handler(){};
+/**
+  ******************************************************************************
+  * File Name          : SPI.c
+  * Description        : This file provides code for the configuration
+  *                      of the SPI instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "spi.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+SPI_HandleTypeDef hspi1;
+DMA_HandleTypeDef hdma_spi1_rx;
+DMA_HandleTypeDef hdma_spi1_tx;
+
+/* SPI1 init function */
+void MX_SPI1_Init(void)
+{
+
+  hspi1.Instance = SPI1;
+  hspi1.Init.Mode = SPI_MODE_MASTER;
+  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
+  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
+  hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
+  hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
+  hspi1.Init.NSS = SPI_NSS_SOFT;
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_128;
+  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
+  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
+  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
+  hspi1.Init.CRCPolynomial = 0x0;
+  hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
+  hspi1.Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
+  hspi1.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
+  hspi1.Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+  hspi1.Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
+  hspi1.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
+  hspi1.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
+  hspi1.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
+  hspi1.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE;
+  hspi1.Init.IOSwap = SPI_IO_SWAP_DISABLE;
+  if (HAL_SPI_Init(&hspi1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+}
+
+void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(spiHandle->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspInit 0 */
+
+  /* USER CODE END SPI1_MspInit 0 */
+    /* SPI1 clock enable */
+    __HAL_RCC_SPI1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**SPI1 GPIO Configuration
+    PA5     ------> SPI1_SCK
+    PA6     ------> SPI1_MISO
+    PB5     ------> SPI1_MOSI
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_6;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_5;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* SPI1 DMA Init */
+    /* SPI1_RX Init */
+    hdma_spi1_rx.Instance = DMA1_Stream0;
+    hdma_spi1_rx.Init.Request = DMA_REQUEST_SPI1_RX;
+    hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi1_rx.Init.Mode = DMA_NORMAL;
+    hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
+    hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(spiHandle,hdmarx,hdma_spi1_rx);
+
+    /* SPI1_TX Init */
+    hdma_spi1_tx.Instance = DMA1_Stream1;
+    hdma_spi1_tx.Init.Request = DMA_REQUEST_SPI1_TX;
+    hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi1_tx.Init.Mode = DMA_NORMAL;
+    hdma_spi1_tx.Init.Priority = DMA_PRIORITY_HIGH;
+    hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+    if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(spiHandle,hdmatx,hdma_spi1_tx);
+
+    /* SPI1 interrupt Init */
+    HAL_NVIC_SetPriority(SPI1_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(SPI1_IRQn);
+  /* USER CODE BEGIN SPI1_MspInit 1 */
+
+  /* USER CODE END SPI1_MspInit 1 */
+  }
+}
+
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle)
+{
+
+  if(spiHandle->Instance==SPI1)
+  {
+  /* USER CODE BEGIN SPI1_MspDeInit 0 */
+
+  /* USER CODE END SPI1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_SPI1_CLK_DISABLE();
+
+    /**SPI1 GPIO Configuration
+    PA5     ------> SPI1_SCK
+    PA6     ------> SPI1_MISO
+    PB5     ------> SPI1_MOSI
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6);
+
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5);
+
+    /* SPI1 DMA DeInit */
+    HAL_DMA_DeInit(spiHandle->hdmarx);
+    HAL_DMA_DeInit(spiHandle->hdmatx);
+
+    /* SPI1 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(SPI1_IRQn);
+  /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+  /* USER CODE END SPI1_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

diff -r f480200c8600 -r 1d62b3be52e8 spi.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/spi.h	Wed Oct 28 15:35:08 2020 +0000
@@ -0,0 +1,59 @@
+/**
+  ******************************************************************************
+  * File Name          : SPI.h
+  * Description        : This file provides code for the configuration
+  *                      of the SPI instances.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under Ultimate Liberty license
+  * SLA0044, the "License"; You may not use this file except in compliance with
+  * the License. You may obtain a copy of the License at:
+  *                             www.st.com/SLA0044
+  *
+  ******************************************************************************
+  */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __spi_H
+#define __spi_H
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern SPI_HandleTypeDef hspi1;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_SPI1_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /*__ spi_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+