Yuliya Smirnova / ADE7912

adc

Dependents:   h7adc

ADE7912.cpp@3:1d62b3be52e8, 2020-10-28 (annotated)

Committer:
yuliyasm
Date:
Wed Oct 28 15:35:08 2020 +0000
Revision:
3:1d62b3be52e8
Parent:
2:f480200c8600 
new

Who changed what in which revision?

UserRevisionLine numberNew contents of line
yuliyasm 2:f480200c8600 1 #include "ADE7912.h"
yuliyasm 2:f480200c8600 2 #include "communication.h"
yuliyasm 2:f480200c8600 3 #include "stm32h7xx_hal.h"
yuliyasm 2:f480200c8600 4
yuliyasm 2:f480200c8600 5
yuliyasm 2:f480200c8600 6
yuliyasm 2:f480200c8600 7 uint8_t spiPackageTransmited = 0;
yuliyasm 2:f480200c8600 8 uint8_t spiPackageReceived = 0;
yuliyasm 2:f480200c8600 9
yuliyasm 2:f480200c8600 10
yuliyasm 3:1d62b3be52e8 11
yuliyasm 3:1d62b3be52e8 12 void ADE7912_WriteToReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length);
yuliyasm 3:1d62b3be52e8 13 void ADE7912_ReadFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length);
yuliyasm 3:1d62b3be52e8 14 uint8_t ADE7912_ReadADCVersionFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
yuliyasm 3:1d62b3be52e8 15 uint8_t ADE7912_ReadTemposFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase);
yuliyasm 3:1d62b3be52e8 16 //void ADE7912_InitEXTIForDReady(struct ADE7912_Inst *ade, GPIO_TypeDef *port, uint16_t pin);
yuliyasm 3:1d62b3be52e8 17
yuliyasm 3:1d62b3be52e8 18
yuliyasm 3:1d62b3be52e8 19
yuliyasm 2:f480200c8600 20 void ADE7912_WriteToReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length)
yuliyasm 2:f480200c8600 21 {
yuliyasm 3:1d62b3be52e8 22 HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_RESET);
yuliyasm 3:1d62b3be52e8 23
yuliyasm 3:1d62b3be52e8 24 uint8_t addrBuf = addr | ADE7912_WRITE_MODE;
yuliyasm 3:1d62b3be52e8 25 WriteToRegisterBySPI(ade->spi, addrBuf, buf, length);
yuliyasm 3:1d62b3be52e8 26
yuliyasm 3:1d62b3be52e8 27 HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_SET);
yuliyasm 3:1d62b3be52e8 28 }
yuliyasm 2:f480200c8600 29
yuliyasm 2:f480200c8600 30
yuliyasm 2:f480200c8600 31
yuliyasm 2:f480200c8600 32 void ADE7912_ReadFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, uint8_t addr, uint8_t *buf, uint8_t length)
yuliyasm 2:f480200c8600 33 {
yuliyasm 3:1d62b3be52e8 34 HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_RESET);
yuliyasm 3:1d62b3be52e8 35
yuliyasm 3:1d62b3be52e8 36 uint8_t addrBuf = addr | ADE7912_READ_MODE;
yuliyasm 3:1d62b3be52e8 37 ReadFromRegisterBySPI(ade->spi, addrBuf, buf, length);
yuliyasm 2:f480200c8600 38
yuliyasm 3:1d62b3be52e8 39 HAL_GPIO_WritePin(ade->CS_ports[phase], ade->CS_pins[phase], GPIO_PIN_SET);
yuliyasm 2:f480200c8600 40 }
yuliyasm 2:f480200c8600 41
yuliyasm 2:f480200c8600 42
yuliyasm 2:f480200c8600 43
yuliyasm 2:f480200c8600 44 //void ADE7912_InitEXTIForDReady(struct ADE7912_Inst *ade, GPIO_TypeDef *port, uint16_t pin)
yuliyasm 2:f480200c8600 45 //{
yuliyasm 2:f480200c8600 46 // ade->DReadyPort = port;
yuliyasm 2:f480200c8600 47 // ade->DReadyPin = pin;
yuliyasm 3:1d62b3be52e8 48 //
yuliyasm 2:f480200c8600 49 // switch (pin)
yuliyasm 2:f480200c8600 50 // {
yuliyasm 2:f480200c8600 51 // case GPIO_PIN_0:
yuliyasm 2:f480200c8600 52 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 53 // break;
yuliyasm 2:f480200c8600 54 // case GPIO_PIN_1:
yuliyasm 2:f480200c8600 55 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 56 // break;
yuliyasm 2:f480200c8600 57 // case GPIO_PIN_2:
yuliyasm 2:f480200c8600 58 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 59 // break;
yuliyasm 2:f480200c8600 60 // case GPIO_PIN_3:
yuliyasm 2:f480200c8600 61 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 62 // break;
yuliyasm 2:f480200c8600 63 // case GPIO_PIN_4:
yuliyasm 2:f480200c8600 64 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 65 // break;
yuliyasm 2:f480200c8600 66 // case GPIO_PIN_5:
yuliyasm 2:f480200c8600 67 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 68 // break;
yuliyasm 2:f480200c8600 69 // case GPIO_PIN_6:
yuliyasm 2:f480200c8600 70 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 71 // break;
yuliyasm 2:f480200c8600 72 // case GPIO_PIN_7:
yuliyasm 2:f480200c8600 73 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 74 // break;
yuliyasm 2:f480200c8600 75 // case GPIO_PIN_8:
yuliyasm 2:f480200c8600 76 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 77 // break;
yuliyasm 2:f480200c8600 78 // case GPIO_PIN_9:
yuliyasm 2:f480200c8600 79 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 80 // break;
yuliyasm 2:f480200c8600 81 // case GPIO_PIN_10:
yuliyasm 2:f480200c8600 82 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 83 // break;
yuliyasm 2:f480200c8600 84 // case GPIO_PIN_11:
yuliyasm 2:f480200c8600 85 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 86 // break;
yuliyasm 2:f480200c8600 87 // case GPIO_PIN_12:
yuliyasm 2:f480200c8600 88 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 89 // break;
yuliyasm 2:f480200c8600 90 // case GPIO_PIN_13:
yuliyasm 2:f480200c8600 91 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 92 // break;
yuliyasm 2:f480200c8600 93 // case GPIO_PIN_14:
yuliyasm 2:f480200c8600 94 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 95 // break;
yuliyasm 2:f480200c8600 96 // case GPIO_PIN_15:
yuliyasm 2:f480200c8600 97 // ade->EXTIinterrupt = EXTI15_10_IRQn;
yuliyasm 2:f480200c8600 98 // break;
yuliyasm 2:f480200c8600 99 // }
yuliyasm 3:1d62b3be52e8 100 //
yuliyasm 2:f480200c8600 101 // GPIO_InitTypeDef GPIO_InitStruct = {0};
yuliyasm 2:f480200c8600 102
yuliyasm 2:f480200c8600 103 // /* GPIO Ports Clock Enable */
yuliyasm 2:f480200c8600 104 // __HAL_RCC_GPIOA_CLK_ENABLE();
yuliyasm 2:f480200c8600 105
yuliyasm 2:f480200c8600 106 // /*Configure GPIO pin : PA11 */
yuliyasm 2:f480200c8600 107 // GPIO_InitStruct.Pin = pin;
yuliyasm 2:f480200c8600 108 // GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
yuliyasm 2:f480200c8600 109 // GPIO_InitStruct.Pull = GPIO_NOPULL;
yuliyasm 2:f480200c8600 110 // HAL_GPIO_Init(port, &GPIO_InitStruct);
yuliyasm 2:f480200c8600 111
yuliyasm 2:f480200c8600 112 // /* EXTI interrupt init*/
yuliyasm 3:1d62b3be52e8 113 //
yuliyasm 3:1d62b3be52e8 114 //
yuliyasm 3:1d62b3be52e8 115 //
yuliyasm 3:1d62b3be52e8 116 //
yuliyasm 2:f480200c8600 117 // HAL_NVIC_SetPriority(EXTIinterrupt, 0, 0);
yuliyasm 2:f480200c8600 118 // HAL_NVIC_EnableIRQ(EXTIinterrupt);
yuliyasm 2:f480200c8600 119 //}
yuliyasm 2:f480200c8600 120
yuliyasm 2:f480200c8600 121
yuliyasm 3:1d62b3be52e8 122
yuliyasm 2:f480200c8600 123 struct ADE7912_Inst* New_ADE7912(SPI_HandleTypeDef *spi)
yuliyasm 2:f480200c8600 124 {
yuliyasm 3:1d62b3be52e8 125 struct ADE7912_Inst *ade = (struct ADE7912_Inst *)malloc(sizeof(struct ADE7912_Inst));
yuliyasm 3:1d62b3be52e8 126 ade->spi = spi;
yuliyasm 3:1d62b3be52e8 127 for(int phase = 0; phase < 4; phase += 1)
yuliyasm 3:1d62b3be52e8 128 {
yuliyasm 3:1d62b3be52e8 129 ade->CS_pins[phase] = NULL;
yuliyasm 3:1d62b3be52e8 130 ade->CS_ports[phase] = GPIOA;
yuliyasm 3:1d62b3be52e8 131 ade->phasesData[phase] = NULL;
yuliyasm 3:1d62b3be52e8 132 ade->phasesEnable[phase] = 0;
yuliyasm 3:1d62b3be52e8 133 }
yuliyasm 3:1d62b3be52e8 134 return ade;
yuliyasm 2:f480200c8600 135 }
yuliyasm 2:f480200c8600 136
yuliyasm 2:f480200c8600 137
yuliyasm 2:f480200c8600 138
yuliyasm 2:f480200c8600 139 void ADE7912_PhaseInit(struct ADE7912_Inst *ade, struct ADE7912_Phase_Settings *settings, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 140 {
yuliyasm 3:1d62b3be52e8 141 ade->CS_ports[phase] = settings->CS_port;
yuliyasm 3:1d62b3be52e8 142 ade->CS_pins[phase] = settings->CS_pin;
yuliyasm 2:f480200c8600 143
yuliyasm 3:1d62b3be52e8 144 ade->phasesData[phase] = (struct ADE7912_BrushRead_Data *)malloc(sizeof(struct ADE7912_BrushRead_Data));
yuliyasm 3:1d62b3be52e8 145 ade->phasesData[phase]->V1WV = 0;
yuliyasm 3:1d62b3be52e8 146 ade->phasesData[phase]->V2WV = 0;
yuliyasm 3:1d62b3be52e8 147 ade->phasesData[phase]->IWV = 0;
yuliyasm 3:1d62b3be52e8 148 ade->phasesData[phase]->ADC_CRC = 0;
yuliyasm 3:1d62b3be52e8 149 ade->phasesData[phase]->STATUS0 = 0;
yuliyasm 3:1d62b3be52e8 150 ade->phasesData[phase]->CNT_SNAPSHOT = 0;
yuliyasm 3:1d62b3be52e8 151
yuliyasm 3:1d62b3be52e8 152 ADE7912_ResetPhase(ade, phase);
yuliyasm 3:1d62b3be52e8 153
yuliyasm 3:1d62b3be52e8 154 ade->version[phase] = ADE7912_ReadADCVersionFromReg(ade, phase);
yuliyasm 3:1d62b3be52e8 155
yuliyasm 3:1d62b3be52e8 156 ADE7912_SetDataUpdateFreq(ade, phase, settings->freq);
yuliyasm 3:1d62b3be52e8 157
yuliyasm 3:1d62b3be52e8 158 ADE7912_SetPwrConverterEnabled(ade, phase, 1);
yuliyasm 3:1d62b3be52e8 159
yuliyasm 3:1d62b3be52e8 160 ADE7912_SetTempEnabled(ade, phase, 0);
yuliyasm 3:1d62b3be52e8 161
yuliyasm 3:1d62b3be52e8 162 ADE7912_SetBandwidth(ade, phase, settings->bandwidth);
yuliyasm 3:1d62b3be52e8 163
yuliyasm 3:1d62b3be52e8 164 ade->tempGain[phase] = settings->bandwidth == BW_3K3HZ ? ADE7912_TEMPGAIN_WITH_3K3_BW : ADE7912_TEMPGAIN_WITH_2K_BW;
yuliyasm 3:1d62b3be52e8 165
yuliyasm 3:1d62b3be52e8 166 ADE7912_SetCLKOUTFunctionality(ade, phase, settings->clkoutFunc);
yuliyasm 3:1d62b3be52e8 167
yuliyasm 3:1d62b3be52e8 168 uint32_t tmp;
yuliyasm 3:1d62b3be52e8 169 tmp = ADE7912_ReadTemposFromReg(ade, phase) << 11;
yuliyasm 3:1d62b3be52e8 170 //if (tmp & 0x00040000) tmp = ~(~(tmp - 1) | 0x0007FFFF) + 1;
yuliyasm 3:1d62b3be52e8 171 ade->tempos[phase] = ADE7912_TEMPGAIN_WITH_3K3_BW * (float)tmp;
yuliyasm 3:1d62b3be52e8 172
yuliyasm 3:1d62b3be52e8 173 ADE7912_EnablePhase(ade, phase);
yuliyasm 3:1d62b3be52e8 174
yuliyasm 2:f480200c8600 175 }
yuliyasm 2:f480200c8600 176
yuliyasm 2:f480200c8600 177
yuliyasm 2:f480200c8600 178
yuliyasm 2:f480200c8600 179 void ADE7912_EnablePhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 180 {
yuliyasm 3:1d62b3be52e8 181 ade->phasesEnable[phase] = 1;
yuliyasm 2:f480200c8600 182 }
yuliyasm 2:f480200c8600 183
yuliyasm 2:f480200c8600 184
yuliyasm 2:f480200c8600 185
yuliyasm 2:f480200c8600 186 void ADE7912_DisablePhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 187 {
yuliyasm 3:1d62b3be52e8 188 ade->phasesEnable[phase] = 0;
yuliyasm 2:f480200c8600 189 }
yuliyasm 2:f480200c8600 190
yuliyasm 2:f480200c8600 191 void ADE7912_ResetPhase(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 192 {
yuliyasm 3:1d62b3be52e8 193 // Software reset start
yuliyasm 3:1d62b3be52e8 194 uint8_t buf;
yuliyasm 3:1d62b3be52e8 195 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 3:1d62b3be52e8 196
yuliyasm 3:1d62b3be52e8 197 buf |= ADE7912_CONFIG_BIT_SWRST;
yuliyasm 3:1d62b3be52e8 198 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 3:1d62b3be52e8 199
yuliyasm 3:1d62b3be52e8 200 // Wait for reset finished
yuliyasm 3:1d62b3be52e8 201 while (1)
yuliyasm 3:1d62b3be52e8 202 {
yuliyasm 3:1d62b3be52e8 203 uint8_t buf;
yuliyasm 3:1d62b3be52e8 204 ADE7912_ReadFromReg(ade, phase, ADE7912_STATUS0_REG_ADDRESS, &buf, 1);
yuliyasm 3:1d62b3be52e8 205
yuliyasm 3:1d62b3be52e8 206 if (~buf & ADE7912_STATUS0_BIT_RESET_ON) break;
yuliyasm 3:1d62b3be52e8 207 }
yuliyasm 2:f480200c8600 208 }
yuliyasm 2:f480200c8600 209
yuliyasm 3:1d62b3be52e8 210 uint8_t buf[14];
yuliyasm 3:1d62b3be52e8 211 uint32_t tmp;
yuliyasm 2:f480200c8600 212
yuliyasm 2:f480200c8600 213 void ADE7912_UpdateData(struct ADE7912_Inst *ade)
yuliyasm 2:f480200c8600 214 {
yuliyasm 2:f480200c8600 215
yuliyasm 3:1d62b3be52e8 216
yuliyasm 3:1d62b3be52e8 217 for(int phase = 0; phase < 4; phase += 1)
yuliyasm 3:1d62b3be52e8 218 {
yuliyasm 3:1d62b3be52e8 219 if (ade->phasesEnable[phase])
yuliyasm 3:1d62b3be52e8 220 {
yuliyasm 3:1d62b3be52e8 221 ADE7912_ReadFromReg(ade, static_cast<ADE7912_Phases>(phase), ADE7912_BRUSH_READ_MODE, buf, 14);
yuliyasm 3:1d62b3be52e8 222
yuliyasm 2:f480200c8600 223
yuliyasm 3:1d62b3be52e8 224
yuliyasm 3:1d62b3be52e8 225 tmp = (buf[0] << 16) | (buf[1] << 8) | buf[2];
yuliyasm 3:1d62b3be52e8 226 if (tmp > 0x007FFFFF) tmp |= 0xFF000000;
yuliyasm 3:1d62b3be52e8 227 ade->phasesData[phase]->IWV = (int32_t)tmp;
yuliyasm 3:1d62b3be52e8 228
yuliyasm 3:1d62b3be52e8 229 tmp = (buf[3] << 16) | (buf[4] << 8) | buf[5];
yuliyasm 3:1d62b3be52e8 230 if (tmp > 0x007FFFFF) tmp |= 0xFF000000;
yuliyasm 3:1d62b3be52e8 231 ade->phasesData[phase]->V1WV = (int32_t)tmp;
yuliyasm 3:1d62b3be52e8 232
yuliyasm 3:1d62b3be52e8 233 tmp = (buf[6] << 16) | (buf[7] << 8) | buf[8];
yuliyasm 3:1d62b3be52e8 234 if (tmp > 0x007FFFFF) tmp |= 0xFF000000;
yuliyasm 3:1d62b3be52e8 235 ade->phasesData[phase]->V2WV = (int32_t)tmp;
yuliyasm 3:1d62b3be52e8 236
yuliyasm 3:1d62b3be52e8 237 ade->phasesData[phase]->ADC_CRC = (buf[9] << 8) | buf[10];
yuliyasm 3:1d62b3be52e8 238 ade->phasesData[phase]->STATUS0 = buf[11];
yuliyasm 3:1d62b3be52e8 239 ade->phasesData[phase]->CNT_SNAPSHOT = (buf[12] << 8) | buf[13];
yuliyasm 3:1d62b3be52e8 240 }
yuliyasm 3:1d62b3be52e8 241 }
yuliyasm 2:f480200c8600 242 }
yuliyasm 2:f480200c8600 243
yuliyasm 2:f480200c8600 244
yuliyasm 2:f480200c8600 245
yuliyasm 2:f480200c8600 246 int ADE7912_BrrushReadData(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, struct ADE7912_BrushRead_Data *data)
yuliyasm 2:f480200c8600 247 {
yuliyasm 3:1d62b3be52e8 248 if (ade->phasesEnable[phase])
yuliyasm 3:1d62b3be52e8 249 {
yuliyasm 3:1d62b3be52e8 250 data->IWV = ade->phasesData[phase]->IWV;
yuliyasm 3:1d62b3be52e8 251 data->V1WV = ade->phasesData[phase]->V1WV;
yuliyasm 3:1d62b3be52e8 252 data->V2WV = ade->phasesData[phase]->V2WV;
yuliyasm 3:1d62b3be52e8 253 data->ADC_CRC = ade->phasesData[phase]->ADC_CRC;
yuliyasm 3:1d62b3be52e8 254 data->STATUS0 = ade->phasesData[phase]->STATUS0;
yuliyasm 3:1d62b3be52e8 255 data->CNT_SNAPSHOT = ade->phasesData[phase]->CNT_SNAPSHOT;
yuliyasm 3:1d62b3be52e8 256
yuliyasm 3:1d62b3be52e8 257 return 0;
yuliyasm 3:1d62b3be52e8 258 } else return 1;
yuliyasm 2:f480200c8600 259 }
yuliyasm 2:f480200c8600 260
yuliyasm 2:f480200c8600 261
yuliyasm 2:f480200c8600 262
yuliyasm 2:f480200c8600 263 void ADE7912_SetDataUpdateFreq(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_DataUpdateFreq freq)
yuliyasm 2:f480200c8600 264 {
yuliyasm 3:1d62b3be52e8 265
yuliyasm 3:1d62b3be52e8 266 uint8_t buf;
yuliyasm 3:1d62b3be52e8 267 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 3:1d62b3be52e8 268
yuliyasm 3:1d62b3be52e8 269 HAL_Delay(1);
yuliyasm 3:1d62b3be52e8 270
yuliyasm 3:1d62b3be52e8 271 buf &= (uint8_t)~ADE7912_CONFIG_ADC_FREQ;
yuliyasm 3:1d62b3be52e8 272 switch(freq)
yuliyasm 3:1d62b3be52e8 273 {
yuliyasm 3:1d62b3be52e8 274 case F_8KHZ:
yuliyasm 3:1d62b3be52e8 275 buf |= ADE7912_CONFIG_ADC_FREQ_8K;
yuliyasm 3:1d62b3be52e8 276 break;
yuliyasm 3:1d62b3be52e8 277 case F_4KHZ:
yuliyasm 3:1d62b3be52e8 278 buf |= ADE7912_CONFIG_ADC_FREQ_4K;
yuliyasm 3:1d62b3be52e8 279 break;
yuliyasm 3:1d62b3be52e8 280 case F_2KHZ:
yuliyasm 3:1d62b3be52e8 281 buf |= ADE7912_CONFIG_ADC_FREQ_2K;
yuliyasm 3:1d62b3be52e8 282 break;
yuliyasm 3:1d62b3be52e8 283 case F_1KHZ:
yuliyasm 3:1d62b3be52e8 284 buf |= ADE7912_CONFIG_ADC_FREQ_1K;
yuliyasm 3:1d62b3be52e8 285 break;
yuliyasm 3:1d62b3be52e8 286 }
yuliyasm 3:1d62b3be52e8 287 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 288 }
yuliyasm 2:f480200c8600 289
yuliyasm 2:f480200c8600 290
yuliyasm 2:f480200c8600 291
yuliyasm 2:f480200c8600 292 uint8_t ADE7912_ReadADCVersionFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 293 {
yuliyasm 3:1d62b3be52e8 294 uint8_t buf;
yuliyasm 3:1d62b3be52e8 295 ADE7912_ReadFromReg(ade, phase, ADE7912_STATUS1_REG_ADDRESS, &buf, 1);
yuliyasm 3:1d62b3be52e8 296
yuliyasm 3:1d62b3be52e8 297 return buf & ADE7912_STATUS1_BIT_VERSION;
yuliyasm 2:f480200c8600 298 }
yuliyasm 2:f480200c8600 299
yuliyasm 2:f480200c8600 300
yuliyasm 2:f480200c8600 301
yuliyasm 2:f480200c8600 302 uint8_t ADE7912_ReadTemposFromReg(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 303 {
yuliyasm 3:1d62b3be52e8 304 uint8_t buf;
yuliyasm 3:1d62b3be52e8 305 ADE7912_ReadFromReg(ade, phase, ADE7912_TEMPOS_REG_ADDRESS, &buf, 1);
yuliyasm 3:1d62b3be52e8 306
yuliyasm 3:1d62b3be52e8 307 return buf;
yuliyasm 2:f480200c8600 308 }
yuliyasm 2:f480200c8600 309
yuliyasm 2:f480200c8600 310
yuliyasm 2:f480200c8600 311
yuliyasm 2:f480200c8600 312 void ADE7912_SetPwrConverterEnabled(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, bool enabled)
yuliyasm 2:f480200c8600 313 {
yuliyasm 3:1d62b3be52e8 314 uint8_t buf;
yuliyasm 3:1d62b3be52e8 315 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 3:1d62b3be52e8 316
yuliyasm 3:1d62b3be52e8 317 HAL_Delay(1);
yuliyasm 3:1d62b3be52e8 318
yuliyasm 3:1d62b3be52e8 319 buf &= (uint8_t)~ADE7912_CONFIG_BIT_PWRDWNENB;
yuliyasm 3:1d62b3be52e8 320 buf |= enabled ? ADE7912_CONFIG_BIT_PWRDWNENB : 0;
yuliyasm 3:1d62b3be52e8 321 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 322 }
yuliyasm 2:f480200c8600 323
yuliyasm 2:f480200c8600 324
yuliyasm 2:f480200c8600 325
yuliyasm 2:f480200c8600 326 void ADE7912_SetTempEnabled(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, bool enabled)
yuliyasm 2:f480200c8600 327 {
yuliyasm 3:1d62b3be52e8 328 uint8_t buf;
yuliyasm 3:1d62b3be52e8 329 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 3:1d62b3be52e8 330
yuliyasm 3:1d62b3be52e8 331 HAL_Delay(1);
yuliyasm 3:1d62b3be52e8 332
yuliyasm 3:1d62b3be52e8 333 buf &= (uint8_t)~ADE7912_CONFIG_BIT_TEMPENB;
yuliyasm 3:1d62b3be52e8 334 buf |= enabled ? ADE7912_CONFIG_BIT_TEMPENB : 0;
yuliyasm 3:1d62b3be52e8 335 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 336 }
yuliyasm 2:f480200c8600 337
yuliyasm 2:f480200c8600 338
yuliyasm 2:f480200c8600 339
yuliyasm 2:f480200c8600 340 void ADE7912_SetBandwidth(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_Bandwidths bandwidth)
yuliyasm 2:f480200c8600 341 {
yuliyasm 3:1d62b3be52e8 342 uint8_t buf;
yuliyasm 3:1d62b3be52e8 343 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 3:1d62b3be52e8 344
yuliyasm 3:1d62b3be52e8 345 HAL_Delay(1);
yuliyasm 3:1d62b3be52e8 346
yuliyasm 3:1d62b3be52e8 347 buf &= (uint8_t)~ADE7912_CONFIG_BIT_BW;
yuliyasm 3:1d62b3be52e8 348 switch(bandwidth)
yuliyasm 3:1d62b3be52e8 349 {
yuliyasm 3:1d62b3be52e8 350 case BW_3K3HZ:
yuliyasm 3:1d62b3be52e8 351 buf |= 0;
yuliyasm 3:1d62b3be52e8 352 break;
yuliyasm 3:1d62b3be52e8 353 case BW_2KHZ:
yuliyasm 3:1d62b3be52e8 354 buf |= ADE7912_CONFIG_BIT_BW;
yuliyasm 3:1d62b3be52e8 355 break;
yuliyasm 3:1d62b3be52e8 356 }
yuliyasm 3:1d62b3be52e8 357 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 358 }
yuliyasm 2:f480200c8600 359
yuliyasm 2:f480200c8600 360
yuliyasm 2:f480200c8600 361
yuliyasm 2:f480200c8600 362 void ADE7912_LockConfigurationRegisters(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 363 {
yuliyasm 3:1d62b3be52e8 364 uint8_t buf = 0xCA;
yuliyasm 3:1d62b3be52e8 365 ADE7912_WriteToReg(ade, phase, ADE7912_LOCK_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 366 }
yuliyasm 2:f480200c8600 367
yuliyasm 2:f480200c8600 368
yuliyasm 2:f480200c8600 369
yuliyasm 2:f480200c8600 370 void ADE7912_UnlockConfigurationRegisters(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 371 {
yuliyasm 3:1d62b3be52e8 372 uint8_t buf = 0x9C;
yuliyasm 3:1d62b3be52e8 373 ADE7912_WriteToReg(ade, phase, ADE7912_LOCK_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 374 }
yuliyasm 2:f480200c8600 375
yuliyasm 2:f480200c8600 376
yuliyasm 2:f480200c8600 377
yuliyasm 2:f480200c8600 378 void ADE7912_SetCLKOUTFunctionality(struct ADE7912_Inst *ade, enum ADE7912_Phases phase, enum ADE7912_CLKOUT_Functionality functionality)
yuliyasm 2:f480200c8600 379 {
yuliyasm 3:1d62b3be52e8 380 uint8_t buf;
yuliyasm 3:1d62b3be52e8 381 ADE7912_ReadFromReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 3:1d62b3be52e8 382
yuliyasm 3:1d62b3be52e8 383 HAL_Delay(1);
yuliyasm 3:1d62b3be52e8 384
yuliyasm 3:1d62b3be52e8 385 buf &= (uint8_t)~ADE7912_CONFIG_BIT_CLKOUTENB;
yuliyasm 3:1d62b3be52e8 386 switch(functionality)
yuliyasm 3:1d62b3be52e8 387 {
yuliyasm 3:1d62b3be52e8 388 case CLKOUT:
yuliyasm 3:1d62b3be52e8 389 buf |= ADE7912_CONFIG_BIT_CLKOUTENB;
yuliyasm 3:1d62b3be52e8 390 break;
yuliyasm 3:1d62b3be52e8 391 case DREADY:
yuliyasm 3:1d62b3be52e8 392 buf |= 0;
yuliyasm 3:1d62b3be52e8 393 break;
yuliyasm 3:1d62b3be52e8 394 }
yuliyasm 3:1d62b3be52e8 395 ADE7912_WriteToReg(ade, phase, ADE7912_CONFIG_REG_ADDRESS, &buf, 1);
yuliyasm 2:f480200c8600 396 }
yuliyasm 2:f480200c8600 397
yuliyasm 2:f480200c8600 398
yuliyasm 2:f480200c8600 399
yuliyasm 2:f480200c8600 400 uint8_t ADE7912_GetADCVersion(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 401 {
yuliyasm 3:1d62b3be52e8 402 return ade->version[phase];
yuliyasm 2:f480200c8600 403 }
yuliyasm 2:f480200c8600 404
yuliyasm 2:f480200c8600 405
yuliyasm 2:f480200c8600 406
yuliyasm 2:f480200c8600 407 float ADE7912_GetVoltage(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 408 {
yuliyasm 3:1d62b3be52e8 409 if (ade->phasesEnable[phase] == 1)
yuliyasm 3:1d62b3be52e8 410 {
yuliyasm 3:1d62b3be52e8 411 return ade->phasesData[phase]->V1WV * ADE7912_VWV_TRANSLATE_COEF;
yuliyasm 3:1d62b3be52e8 412 } else {
yuliyasm 3:1d62b3be52e8 413 return 0;
yuliyasm 3:1d62b3be52e8 414 }
yuliyasm 2:f480200c8600 415 }
yuliyasm 2:f480200c8600 416
yuliyasm 2:f480200c8600 417
yuliyasm 2:f480200c8600 418
yuliyasm 2:f480200c8600 419 float ADE7912_GetCurrent(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 420 {
yuliyasm 3:1d62b3be52e8 421 if (ade->phasesEnable[phase] == 1)
yuliyasm 3:1d62b3be52e8 422 {
yuliyasm 3:1d62b3be52e8 423 return ade->phasesData[phase]->IWV * ADE7912_IWV_TRANSLATE_COEF;
yuliyasm 3:1d62b3be52e8 424 } else {
yuliyasm 3:1d62b3be52e8 425 return 0;
yuliyasm 3:1d62b3be52e8 426 }
yuliyasm 2:f480200c8600 427 }
yuliyasm 2:f480200c8600 428
yuliyasm 2:f480200c8600 429
yuliyasm 2:f480200c8600 430
yuliyasm 2:f480200c8600 431 float ADE7912_GetTemp(struct ADE7912_Inst *ade, enum ADE7912_Phases phase)
yuliyasm 2:f480200c8600 432 {
yuliyasm 3:1d62b3be52e8 433 if (ade->phasesEnable[phase] == 1)
yuliyasm 3:1d62b3be52e8 434 {
yuliyasm 3:1d62b3be52e8 435 return ade->tempGain[phase] * (float)ade->phasesData[phase]->V2WV - ade->tempos[phase] - ADE7912_CONST_TEMPOS;
yuliyasm 3:1d62b3be52e8 436 } else {
yuliyasm 3:1d62b3be52e8 437 return 0;
yuliyasm 3:1d62b3be52e8 438 }
yuliyasm 2:f480200c8600 439 }
yuliyasm 2:f480200c8600 440
yuliyasm 2:f480200c8600 441
yuliyasm 2:f480200c8600 442