Forked from romilly. Changed the way SPI handler is injected in constructor
Fork of MCP23S17 by
MCP23S17.h@4:d501c74550a0, 2010-08-22 (annotated)
- Committer:
- romilly
- Date:
- Sun Aug 22 12:12:58 2010 +0000
- Revision:
- 4:d501c74550a0
- Parent:
- 3:089a2a754567
- Child:
- 5:cb3c24f94370
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
romilly | 2:6144709f1700 | 1 | /* MCP23S17 - drive the Microchip MCP23S17 16-bit Port Extender using SPI |
romilly | 2:6144709f1700 | 2 | * Copyright (c) 2010 Romilly Cocking |
romilly | 2:6144709f1700 | 3 | * Released under the MIT License: http://mbed.org/license/mit |
romilly | 2:6144709f1700 | 4 | * |
romilly | 2:6144709f1700 | 5 | * version 0.1 |
romilly | 2:6144709f1700 | 6 | */ |
romilly | 2:6144709f1700 | 7 | #include "mbed.h" |
romilly | 2:6144709f1700 | 8 | |
romilly | 2:6144709f1700 | 9 | #ifndef SER23K256_H |
romilly | 2:6144709f1700 | 10 | #define SER23K256_H |
romilly | 2:6144709f1700 | 11 | |
romilly | 4:d501c74550a0 | 12 | // all register addresses assume IOCON.BANK = 0 (POR default) |
romilly | 2:6144709f1700 | 13 | |
romilly | 4:d501c74550a0 | 14 | #define IODIRA 0x00 |
romilly | 4:d501c74550a0 | 15 | #define IODIRB 0x01 |
romilly | 4:d501c74550a0 | 16 | #define GPINTENA 0x02 |
romilly | 4:d501c74550a0 | 17 | #define IOCON 0x0A |
romilly | 4:d501c74550a0 | 18 | #define GPIOA 0x12 |
romilly | 4:d501c74550a0 | 19 | #define GPIOB 0x13 |
romilly | 4:d501c74550a0 | 20 | #define OLATA 0x14 |
romilly | 4:d501c74550a0 | 21 | #define OLATB 0x15 |
romilly | 2:6144709f1700 | 22 | |
romilly | 2:6144709f1700 | 23 | // Control settings |
romilly | 2:6144709f1700 | 24 | |
romilly | 2:6144709f1700 | 25 | #define IOCON_BANK 0x80 // Banked registers |
romilly | 2:6144709f1700 | 26 | #define IOCON_BYTE_MODE 0x20 // Disables sequential operation. If bank = 0, operations toggle between A and B registers |
romilly | 2:6144709f1700 | 27 | #define IOCON_HAEN 0x08 // Hardware address enable |
romilly | 2:6144709f1700 | 28 | |
romilly | 2:6144709f1700 | 29 | class MCP23S17 { |
romilly | 2:6144709f1700 | 30 | public: |
romilly | 2:6144709f1700 | 31 | MCP23S17(SPI& spi, PinName ncs, char writeOpcode); |
romilly | 2:6144709f1700 | 32 | void directionA(char direction); |
romilly | 2:6144709f1700 | 33 | void directionB(char direction); |
romilly | 4:d501c74550a0 | 34 | void gpIntEnA(char interruptsEnabledMask); |
romilly | 2:6144709f1700 | 35 | char inputA(); |
romilly | 2:6144709f1700 | 36 | char inputB(); |
romilly | 2:6144709f1700 | 37 | void outputA(char byte); |
romilly | 2:6144709f1700 | 38 | void outputB(char byte); |
romilly | 2:6144709f1700 | 39 | protected: |
romilly | 2:6144709f1700 | 40 | SPI& _spi; |
romilly | 2:6144709f1700 | 41 | DigitalOut _ncs; |
romilly | 2:6144709f1700 | 42 | void _init(); |
romilly | 2:6144709f1700 | 43 | void _write(char address, char data); |
romilly | 2:6144709f1700 | 44 | char _read(char address); |
romilly | 2:6144709f1700 | 45 | char _readOpcode; |
romilly | 2:6144709f1700 | 46 | char _writeOpcode; |
romilly | 2:6144709f1700 | 47 | }; |
romilly | 2:6144709f1700 | 48 | |
romilly | 2:6144709f1700 | 49 | #endif |