Wiljan Arias / MCP23S17

Forked from romilly. Changed the way SPI handler is injected in constructor

Fork of MCP23S17 by Romilly Cocking

MCP23S17.h@9:068b1e8909bb, 2010-08-28 (annotated)

Committer:
romilly
Date:
Sat Aug 28 09:48:38 2010 +0000
Revision:
9:068b1e8909bb
Parent:
8:841b19734955
Child:
10:ca0429a15915
Added pull=up configuration

Who changed what in which revision?

UserRevisionLine numberNew contents of line
romilly 7:53498e24592c 1 /* MCP23S17 - drive the Microchip MCP23S17 16-bit Port Extender using SPI
romilly 7:53498e24592c 2 * Copyright (c) 2010 Romilly Cocking
romilly 7:53498e24592c 3 * Released under the MIT License: http://mbed.org/license/mit
romilly 7:53498e24592c 4 *
romilly 9:068b1e8909bb 5 * version 0.4
romilly 7:53498e24592c 6 */
romilly 7:53498e24592c 7 #include "mbed.h"
romilly 7:53498e24592c 8
romilly 7:53498e24592c 9 #ifndef MCP23S17_H
romilly 7:53498e24592c 10 #define MCP23S17_H
romilly 7:53498e24592c 11
romilly 7:53498e24592c 12 #define INTERRUPT_POLARITY_BIT 0x02
romilly 7:53498e24592c 13 #define INTERRUPT_MIRROR_BIT 0x40
romilly 7:53498e24592c 14
romilly 7:53498e24592c 15 // all register addresses assume IOCON.BANK = 0 (POR default)
romilly 7:53498e24592c 16
romilly 7:53498e24592c 17 #define IODIRA 0x00
romilly 7:53498e24592c 18 #define GPINTENA 0x04
romilly 7:53498e24592c 19 #define DEFVALA 0x06
romilly 7:53498e24592c 20 #define INTCONA 0x08
romilly 7:53498e24592c 21 #define IOCON 0x0A
romilly 9:068b1e8909bb 22 #define GPPUA 0x0C
romilly 7:53498e24592c 23 #define GPIOA 0x12
romilly 7:53498e24592c 24 #define OLATA 0x14
romilly 7:53498e24592c 25
romilly 7:53498e24592c 26 // Control settings
romilly 7:53498e24592c 27
romilly 7:53498e24592c 28 #define IOCON_BANK 0x80 // Banked registers
romilly 7:53498e24592c 29 #define IOCON_BYTE_MODE 0x20 // Disables sequential operation. If bank = 0, operations toggle between A and B registers
romilly 7:53498e24592c 30 #define IOCON_HAEN 0x08 // Hardware address enable
romilly 7:53498e24592c 31
romilly 7:53498e24592c 32 enum Polarity { ACTIVE_LOW , ACTIVE_HIGH };
romilly 8:841b19734955 33 enum Port { PORT_A, PORT_B };
romilly 7:53498e24592c 34
romilly 7:53498e24592c 35 class MCP23S17 {
romilly 7:53498e24592c 36 public:
romilly 7:53498e24592c 37 MCP23S17(SPI& spi, PinName ncs, char writeOpcode);
romilly 8:841b19734955 38 void direction(Port port, char direction);
romilly 9:068b1e8909bb 39 void configurePullUps(Port port, char offOrOn);
romilly 8:841b19734955 40 void interruptEnable(Port port, char interruptsEnabledMask);
romilly 7:53498e24592c 41 void interruptPolarity(Polarity polarity);
romilly 7:53498e24592c 42 void mirrorInterrupts(bool mirror);
romilly 8:841b19734955 43 void defaultValue(Port port, char valuesToCompare);
romilly 8:841b19734955 44 void interruptControl(Port port, char interruptContolBits);
romilly 8:841b19734955 45 char read(Port port);
romilly 8:841b19734955 46 void write(Port port, char byte);
romilly 7:53498e24592c 47 protected:
romilly 7:53498e24592c 48 SPI& _spi;
romilly 7:53498e24592c 49 DigitalOut _ncs;
romilly 7:53498e24592c 50 void _init();
romilly 8:841b19734955 51 void _write(Port port, char address, char data);
romilly 7:53498e24592c 52 void _write(char address, char data);
romilly 8:841b19734955 53 char _read(Port port, char address);
romilly 7:53498e24592c 54 char _read(char address);
romilly 7:53498e24592c 55 char _readOpcode;
romilly 7:53498e24592c 56 char _writeOpcode;
romilly 7:53498e24592c 57 };
romilly 7:53498e24592c 58
romilly 2:6144709f1700 59 #endif