sw ADC SPI interface for the SOLID Slow control beta!!
AD9249.h@2:1fb81137d906, 2015-10-23 (annotated)
- Committer:
- wbeaumont
- Date:
- Fri Oct 23 11:22:44 2015 +0000
- Revision:
- 2:1fb81137d906
- Parent:
- 1:01459a6ab296
production version archiving
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
wbeaumont | 0:9efb460e962b | 1 | #ifndef AD9249_H |
wbeaumont | 0:9efb460e962b | 2 | #define AD9249_H |
wbeaumont | 0:9efb460e962b | 3 | /* interface for controlling the AD9249 ADC , 16 channel ADC Analog Devices |
wbeaumont | 0:9efb460e962b | 4 | |
wbeaumont | 0:9efb460e962b | 5 | -only one CSB line , so assumes the pins CSB1 and CSB2 are connected together . |
wbeaumont | 0:9efb460e962b | 6 | -only MSB mode is supported, so configuration register MSB is set at the start. |
wbeaumont | 0:9efb460e962b | 7 | |
wbeaumont | 2:1fb81137d906 | 8 | * (C) Wim Beaumont Univeristeit Antwerpen 2014 , 2015 |
wbeaumont | 0:9efb460e962b | 9 | |
wbeaumont | 0:9efb460e962b | 10 | |
wbeaumont | 0:9efb460e962b | 11 | */ |
wbeaumont | 1:01459a6ab296 | 12 | |
wbeaumont | 1:01459a6ab296 | 13 | #define AD9249_HDR_VER "1.22" |
wbeaumont | 1:01459a6ab296 | 14 | #include "getVersion.h" |
wbeaumont | 1:01459a6ab296 | 15 | |
wbeaumont | 0:9efb460e962b | 16 | class SWSPI_BI; |
wbeaumont | 0:9efb460e962b | 17 | //class DigitalIn; |
wbeaumont | 0:9efb460e962b | 18 | |
wbeaumont | 1:01459a6ab296 | 19 | class AD9249: public getVersion { |
wbeaumont | 0:9efb460e962b | 20 | typedef unsigned char u8; |
wbeaumont | 0:9efb460e962b | 21 | typedef unsigned int u32; |
wbeaumont | 0:9efb460e962b | 22 | typedef unsigned short u16; |
wbeaumont | 0:9efb460e962b | 23 | // address defs |
wbeaumont | 0:9efb460e962b | 24 | static const u16 configreg= 0x0; |
wbeaumont | 0:9efb460e962b | 25 | static const u16 chip_id_reg= 0x1; |
wbeaumont | 0:9efb460e962b | 26 | static const u16 chip_grade_reg= 0x2; |
wbeaumont | 0:9efb460e962b | 27 | // static const u16 unused_reg= { 0x3, 0x07, 0xA, 0xE, 0xF ,0x11, 0x12,0x13, 0x17, 0x1D, 0x1E, 0x1F,0x20 }; |
wbeaumont | 0:9efb460e962b | 28 | static const u16 dev_index2_reg= 0x4; |
wbeaumont | 0:9efb460e962b | 29 | static const u16 dev_index1_reg= 0x4; |
wbeaumont | 0:9efb460e962b | 30 | static const u16 transfer_reg= 0xFF; |
wbeaumont | 0:9efb460e962b | 31 | static const u16 power_mode_reg= 0x8; |
wbeaumont | 0:9efb460e962b | 32 | static const u16 clock_gobal_reg= 0x9; |
wbeaumont | 0:9efb460e962b | 33 | static const u16 clock_divide_reg= 0xB; |
wbeaumont | 0:9efb460e962b | 34 | static const u16 enhancement_ctr_reg= 0xC; |
wbeaumont | 0:9efb460e962b | 35 | static const u16 test_mode_reg= 0xD; |
wbeaumont | 0:9efb460e962b | 36 | static const u16 offset_adj_reg= 0x10; |
wbeaumont | 0:9efb460e962b | 37 | static const u16 output_mode_reg= 0x14; |
wbeaumont | 0:9efb460e962b | 38 | static const u16 output_adj_reg= 0x15; |
wbeaumont | 0:9efb460e962b | 39 | static const u16 output_phase_reg= 0x16; |
wbeaumont | 0:9efb460e962b | 40 | static const u16 vref_reg= 0x18; |
wbeaumont | 0:9efb460e962b | 41 | static const u16 usserpatt1_LSB_reg= 0x19; |
wbeaumont | 0:9efb460e962b | 42 | static const u16 usserpatt1_MSB_reg= 0x1A; |
wbeaumont | 0:9efb460e962b | 43 | static const u16 usserpatt2_LSB_reg= 0x1B; |
wbeaumont | 0:9efb460e962b | 44 | static const u16 usserpatt2_MSB_reg= 0x1C; |
wbeaumont | 0:9efb460e962b | 45 | static const u16 serial_out_cntr_reg= 0x21; |
wbeaumont | 0:9efb460e962b | 46 | static const u16 serial_status_reg= 0x22; |
wbeaumont | 0:9efb460e962b | 47 | static const u16 sample_rate_reg= 0x100; |
wbeaumont | 0:9efb460e962b | 48 | static const u16 user_io_ctr2_reg= 0x101; |
wbeaumont | 0:9efb460e962b | 49 | static const u16 user_io_ctr3_reg= 0x102; |
wbeaumont | 0:9efb460e962b | 50 | static const u16 sync_reg= 0x109; |
wbeaumont | 0:9efb460e962b | 51 | |
wbeaumont | 0:9efb460e962b | 52 | u32 spi_cycle( u16 reg , bool rw , u16 nrbytes, u32 data); |
wbeaumont | 0:9efb460e962b | 53 | SWSPI_BI* spi; |
wbeaumont | 0:9efb460e962b | 54 | DigitalOut* csb; |
wbeaumont | 0:9efb460e962b | 55 | public: |
wbeaumont | 0:9efb460e962b | 56 | AD9249( SWSPI_BI* spi_dev, DigitalOut* csb_dev); |
wbeaumont | 0:9efb460e962b | 57 | bool getDevInfo(u8& chipid,u8& grade, u16& rb ); |
wbeaumont | 0:9efb460e962b | 58 | bool getDevId(u8&chipid ); |
wbeaumont | 0:9efb460e962b | 59 | bool getGrade(u8&grade ); |
wbeaumont | 0:9efb460e962b | 60 | bool setPattern1(u16 pattern); |
wbeaumont | 0:9efb460e962b | 61 | bool setPattern2(u16 pattern); |
wbeaumont | 0:9efb460e962b | 62 | bool readPattern1(u16& pattern); |
wbeaumont | 0:9efb460e962b | 63 | bool readPattern2(u16& pattern); |
wbeaumont | 0:9efb460e962b | 64 | //general read write |
wbeaumont | 0:9efb460e962b | 65 | bool setReg16( u16 regaddr, u16 data); |
wbeaumont | 0:9efb460e962b | 66 | bool setReg8 ( u16 regaddr, u8 data); |
wbeaumont | 0:9efb460e962b | 67 | bool readReg16( u16 regaddr, u16& data); |
wbeaumont | 1:01459a6ab296 | 68 | bool readReg8 ( u16 regaddr, u8& data); |
wbeaumont | 1:01459a6ab296 | 69 | void init1(); |
wbeaumont | 1:01459a6ab296 | 70 | void init2(); |
wbeaumont | 0:9efb460e962b | 71 | |
wbeaumont | 0:9efb460e962b | 72 | }; |
wbeaumont | 0:9efb460e962b | 73 | |
wbeaumont | 0:9efb460e962b | 74 | |
wbeaumont | 0:9efb460e962b | 75 | |
wbeaumont | 0:9efb460e962b | 76 | |
wbeaumont | 0:9efb460e962b | 77 | |
wbeaumont | 0:9efb460e962b | 78 | #endif |
wbeaumont | 0:9efb460e962b | 79 | |
wbeaumont | 0:9efb460e962b | 80 | |
wbeaumont | 0:9efb460e962b | 81 | |
wbeaumont | 0:9efb460e962b | 82 |