Ward Mattar / Mbed 2 deprecated Formula_LoRa_Receiver

This is code is part of a Technion course project in advanced IoT, implementing a device to receive and present sensors data from a Formula racing car built by students at Technion - Israel Institute of Technology.

Dependencies:   mbed Buffer

Fork of DISCO-L072CZ-LRWAN1_LoRa_PingPong by ST

This is code is part of a Technion course project in advanced IoT, implementing a device to receive sensors data from another L072CZ-LRWAN1 installed on a Formula racing car (built by students at Technion - Israel Institute of Technology), and sends it to a GUI presenting the data (GUI project: github.com/ward-mattar/TechnionFormulaGUI).

How to install

  • Create an account on Mbed: https://os.mbed.com/account/signup/
  • Import project into Compiler
  • In the Program Workspace select "Formula_Nucleo_Receiver"
  • Select a Platform like so:
  1. Click button at top-left
  2. Add Board
  3. Search "NUCLEO F103RB" and then "Add to your Mbed Compiler"
  • Finally click "Compile", if the build was successful, the binary would download automatically
  • To install it on device simply plug it in to a PC, open device drive and drag then drop binary file in it

SX1276GenericLib/sx1276/sx1276.cpp@12:046346a16ff4, 2018-05-19 (annotated)

Committer:
wardm
Date:
Sat May 19 15:42:38 2018 +0000
Revision:
12:046346a16ff4
V1.0.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
wardm 12:046346a16ff4 1 /*
wardm 12:046346a16ff4 2 / _____) _ | |
wardm 12:046346a16ff4 3 ( (____ _____ ____ _| |_ _____ ____| |__
wardm 12:046346a16ff4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
wardm 12:046346a16ff4 5 _____) ) ____| | | || |_| ____( (___| | | |
wardm 12:046346a16ff4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
wardm 12:046346a16ff4 7 (C) 2014 Semtech
wardm 12:046346a16ff4 8
wardm 12:046346a16ff4 9 Description: Actual implementation of a SX1276 radio, inherits Radio
wardm 12:046346a16ff4 10
wardm 12:046346a16ff4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
wardm 12:046346a16ff4 12
wardm 12:046346a16ff4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
wardm 12:046346a16ff4 14 */
wardm 12:046346a16ff4 15
wardm 12:046346a16ff4 16 /*
wardm 12:046346a16ff4 17 * additional development to make it more generic across multiple OS versions
wardm 12:046346a16ff4 18 * (c) 2017 Helmut Tschemernjak
wardm 12:046346a16ff4 19 * 30826 Garbsen (Hannover) Germany
wardm 12:046346a16ff4 20 */
wardm 12:046346a16ff4 21
wardm 12:046346a16ff4 22 #include "sx1276.h"
wardm 12:046346a16ff4 23
wardm 12:046346a16ff4 24
wardm 12:046346a16ff4 25
wardm 12:046346a16ff4 26 const SX1276::BandwidthMap SX1276::FskBandwidths[] =
wardm 12:046346a16ff4 27 {
wardm 12:046346a16ff4 28 { 2600 , 0x17 },
wardm 12:046346a16ff4 29 { 3100 , 0x0F },
wardm 12:046346a16ff4 30 { 3900 , 0x07 },
wardm 12:046346a16ff4 31 { 5200 , 0x16 },
wardm 12:046346a16ff4 32 { 6300 , 0x0E },
wardm 12:046346a16ff4 33 { 7800 , 0x06 },
wardm 12:046346a16ff4 34 { 10400 , 0x15 },
wardm 12:046346a16ff4 35 { 12500 , 0x0D },
wardm 12:046346a16ff4 36 { 15600 , 0x05 },
wardm 12:046346a16ff4 37 { 20800 , 0x14 },
wardm 12:046346a16ff4 38 { 25000 , 0x0C },
wardm 12:046346a16ff4 39 { 31300 , 0x04 },
wardm 12:046346a16ff4 40 { 41700 , 0x13 },
wardm 12:046346a16ff4 41 { 50000 , 0x0B },
wardm 12:046346a16ff4 42 { 62500 , 0x03 },
wardm 12:046346a16ff4 43 { 83333 , 0x12 },
wardm 12:046346a16ff4 44 { 100000, 0x0A },
wardm 12:046346a16ff4 45 { 125000, 0x02 },
wardm 12:046346a16ff4 46 { 166700, 0x11 },
wardm 12:046346a16ff4 47 { 200000, 0x09 },
wardm 12:046346a16ff4 48 { 250000, 0x01 },
wardm 12:046346a16ff4 49 { 300000, 0x00 }, // Invalid Bandwidth
wardm 12:046346a16ff4 50 };
wardm 12:046346a16ff4 51
wardm 12:046346a16ff4 52 const SX1276::BandwidthMap SX1276::LoRaBandwidths[] =
wardm 12:046346a16ff4 53 {
wardm 12:046346a16ff4 54 { 7800, 0 }, // 7.8 kHz requires TCXO
wardm 12:046346a16ff4 55 { 10400, 1 }, // 10.4 kHz requires TCXO
wardm 12:046346a16ff4 56 { 15600, 2 }, // 15.6 kHz requires TCXO
wardm 12:046346a16ff4 57 { 20800, 3 }, // 20.8 kHz requires TCXO
wardm 12:046346a16ff4 58 { 31250, 4 }, // 31.25 kHz requires TCXO
wardm 12:046346a16ff4 59 { 41700, 5 }, // 41.7 kHz requires TCXO
wardm 12:046346a16ff4 60 { 62500, 6 }, // 62.5 kHz requires TCXO
wardm 12:046346a16ff4 61 { 125000, 7 }, // 125 kHz the LoRa protocol default
wardm 12:046346a16ff4 62 { 250000, 8 }, // 250 kHz
wardm 12:046346a16ff4 63 { 500000, 9 }, // 500 kHz
wardm 12:046346a16ff4 64 { 600000, 10 }, // Invalid Bandwidth, reserved
wardm 12:046346a16ff4 65 };
wardm 12:046346a16ff4 66
wardm 12:046346a16ff4 67
wardm 12:046346a16ff4 68
wardm 12:046346a16ff4 69 /*!
wardm 12:046346a16ff4 70 * @brief Radio hardware registers initialization definition
wardm 12:046346a16ff4 71 *
wardm 12:046346a16ff4 72 * @remark Can be automatically generated by the SX1276 GUI (not yet implemented)
wardm 12:046346a16ff4 73 */
wardm 12:046346a16ff4 74
wardm 12:046346a16ff4 75 const SX1276::RadioRegisters SX1276::RadioRegsInit[] = {
wardm 12:046346a16ff4 76 { MODEM_FSK , REG_LNA , 0x23 },
wardm 12:046346a16ff4 77 { MODEM_FSK , REG_RXCONFIG , 0x1E },
wardm 12:046346a16ff4 78 { MODEM_FSK , REG_RSSICONFIG , 0xD2 },
wardm 12:046346a16ff4 79 { MODEM_FSK , REG_AFCFEI , 0x01 },
wardm 12:046346a16ff4 80 { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },
wardm 12:046346a16ff4 81 { MODEM_FSK , REG_OSC , 0x07 },
wardm 12:046346a16ff4 82 { MODEM_FSK , REG_SYNCCONFIG , 0x12 },
wardm 12:046346a16ff4 83 { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },
wardm 12:046346a16ff4 84 { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },
wardm 12:046346a16ff4 85 { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },
wardm 12:046346a16ff4 86 { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },
wardm 12:046346a16ff4 87 { MODEM_FSK , REG_FIFOTHRESH , 0x8F },
wardm 12:046346a16ff4 88 { MODEM_FSK , REG_IMAGECAL , 0x02 },
wardm 12:046346a16ff4 89 { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },
wardm 12:046346a16ff4 90 { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },
wardm 12:046346a16ff4 91 { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },
wardm 12:046346a16ff4 92
wardm 12:046346a16ff4 93 };
wardm 12:046346a16ff4 94
wardm 12:046346a16ff4 95
wardm 12:046346a16ff4 96 SX1276::SX1276( RadioEvents_t *events) : Radio( events ), isRadioActive( false )
wardm 12:046346a16ff4 97 {
wardm 12:046346a16ff4 98 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
wardm 12:046346a16ff4 99
wardm 12:046346a16ff4 100 this->RadioEvents = events;
wardm 12:046346a16ff4 101
wardm 12:046346a16ff4 102 this->dioIrq = new DioIrqHandler[6];
wardm 12:046346a16ff4 103
wardm 12:046346a16ff4 104 this->dioIrq[0] = &SX1276::OnDio0Irq;
wardm 12:046346a16ff4 105 this->dioIrq[1] = &SX1276::OnDio1Irq;
wardm 12:046346a16ff4 106 this->dioIrq[2] = &SX1276::OnDio2Irq;
wardm 12:046346a16ff4 107 this->dioIrq[3] = &SX1276::OnDio3Irq;
wardm 12:046346a16ff4 108 this->dioIrq[4] = &SX1276::OnDio4Irq;
wardm 12:046346a16ff4 109 this->dioIrq[5] = NULL;
wardm 12:046346a16ff4 110
wardm 12:046346a16ff4 111 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 112 }
wardm 12:046346a16ff4 113
wardm 12:046346a16ff4 114 SX1276::~SX1276( )
wardm 12:046346a16ff4 115 {
wardm 12:046346a16ff4 116 delete this->rxtxBuffer;
wardm 12:046346a16ff4 117 delete this->dioIrq;
wardm 12:046346a16ff4 118 }
wardm 12:046346a16ff4 119
wardm 12:046346a16ff4 120 bool SX1276::Init( RadioEvents_t *events )
wardm 12:046346a16ff4 121 {
wardm 12:046346a16ff4 122 if (Read(REG_VERSION) == 0x00)
wardm 12:046346a16ff4 123 return false;
wardm 12:046346a16ff4 124
wardm 12:046346a16ff4 125 this->RadioEvents = events;
wardm 12:046346a16ff4 126 return true;
wardm 12:046346a16ff4 127 }
wardm 12:046346a16ff4 128
wardm 12:046346a16ff4 129
wardm 12:046346a16ff4 130 void SX1276::RadioRegistersInit( )
wardm 12:046346a16ff4 131 {
wardm 12:046346a16ff4 132 uint8_t i = 0;
wardm 12:046346a16ff4 133 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters ); i++ )
wardm 12:046346a16ff4 134 {
wardm 12:046346a16ff4 135 SetModem( RadioRegsInit[i].Modem );
wardm 12:046346a16ff4 136 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
wardm 12:046346a16ff4 137 }
wardm 12:046346a16ff4 138 }
wardm 12:046346a16ff4 139
wardm 12:046346a16ff4 140
wardm 12:046346a16ff4 141 RadioState SX1276::GetStatus( void )
wardm 12:046346a16ff4 142 {
wardm 12:046346a16ff4 143 return this->settings.State;
wardm 12:046346a16ff4 144 }
wardm 12:046346a16ff4 145
wardm 12:046346a16ff4 146 void SX1276::SetChannel( uint32_t freq )
wardm 12:046346a16ff4 147 {
wardm 12:046346a16ff4 148 this->settings.Channel = freq;
wardm 12:046346a16ff4 149 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
wardm 12:046346a16ff4 150 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
wardm 12:046346a16ff4 151 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
wardm 12:046346a16ff4 152 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
wardm 12:046346a16ff4 153 }
wardm 12:046346a16ff4 154
wardm 12:046346a16ff4 155 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
wardm 12:046346a16ff4 156 {
wardm 12:046346a16ff4 157 int16_t rssi = 0;
wardm 12:046346a16ff4 158
wardm 12:046346a16ff4 159 SetModem( modem );
wardm 12:046346a16ff4 160
wardm 12:046346a16ff4 161 SetChannel( freq );
wardm 12:046346a16ff4 162
wardm 12:046346a16ff4 163 SetOpMode( RF_OPMODE_RECEIVER );
wardm 12:046346a16ff4 164
wardm 12:046346a16ff4 165 Sleep_ms( 1 );
wardm 12:046346a16ff4 166
wardm 12:046346a16ff4 167 rssi = GetRssi( modem );
wardm 12:046346a16ff4 168
wardm 12:046346a16ff4 169 Sleep( );
wardm 12:046346a16ff4 170
wardm 12:046346a16ff4 171 if( rssi > rssiThresh )
wardm 12:046346a16ff4 172 {
wardm 12:046346a16ff4 173 return false;
wardm 12:046346a16ff4 174 }
wardm 12:046346a16ff4 175 return true;
wardm 12:046346a16ff4 176 }
wardm 12:046346a16ff4 177
wardm 12:046346a16ff4 178 uint32_t SX1276::Random( void )
wardm 12:046346a16ff4 179 {
wardm 12:046346a16ff4 180 uint8_t i;
wardm 12:046346a16ff4 181 uint32_t rnd = 0;
wardm 12:046346a16ff4 182
wardm 12:046346a16ff4 183 /*
wardm 12:046346a16ff4 184 * Radio setup for random number generation
wardm 12:046346a16ff4 185 */
wardm 12:046346a16ff4 186 // Set LoRa modem ON
wardm 12:046346a16ff4 187 SetModem( MODEM_LORA );
wardm 12:046346a16ff4 188
wardm 12:046346a16ff4 189 // Disable LoRa modem interrupts
wardm 12:046346a16ff4 190 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
wardm 12:046346a16ff4 191 RFLR_IRQFLAGS_RXDONE |
wardm 12:046346a16ff4 192 RFLR_IRQFLAGS_PAYLOADCRCERROR |
wardm 12:046346a16ff4 193 RFLR_IRQFLAGS_VALIDHEADER |
wardm 12:046346a16ff4 194 RFLR_IRQFLAGS_TXDONE |
wardm 12:046346a16ff4 195 RFLR_IRQFLAGS_CADDONE |
wardm 12:046346a16ff4 196 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
wardm 12:046346a16ff4 197 RFLR_IRQFLAGS_CADDETECTED );
wardm 12:046346a16ff4 198
wardm 12:046346a16ff4 199 // Set radio in continuous reception
wardm 12:046346a16ff4 200 SetOpMode( RF_OPMODE_RECEIVER );
wardm 12:046346a16ff4 201
wardm 12:046346a16ff4 202 for( i = 0; i < 32; i++ )
wardm 12:046346a16ff4 203 {
wardm 12:046346a16ff4 204 Sleep_ms( 1 );
wardm 12:046346a16ff4 205 // Unfiltered RSSI value reading. Only takes the LSB value
wardm 12:046346a16ff4 206 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
wardm 12:046346a16ff4 207 }
wardm 12:046346a16ff4 208
wardm 12:046346a16ff4 209 Sleep( );
wardm 12:046346a16ff4 210
wardm 12:046346a16ff4 211 return rnd;
wardm 12:046346a16ff4 212 }
wardm 12:046346a16ff4 213
wardm 12:046346a16ff4 214 /*!
wardm 12:046346a16ff4 215 * Performs the Rx chain calibration for LF and HF bands
wardm 12:046346a16ff4 216 * \remark Must be called just after the reset so all registers are at their
wardm 12:046346a16ff4 217 * default values
wardm 12:046346a16ff4 218 */
wardm 12:046346a16ff4 219 void SX1276::RxChainCalibration( void )
wardm 12:046346a16ff4 220 {
wardm 12:046346a16ff4 221 uint8_t regPaConfigInitVal;
wardm 12:046346a16ff4 222 uint32_t initialFreq;
wardm 12:046346a16ff4 223
wardm 12:046346a16ff4 224 // Save context
wardm 12:046346a16ff4 225 regPaConfigInitVal = this->Read( REG_PACONFIG );
wardm 12:046346a16ff4 226 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
wardm 12:046346a16ff4 227 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
wardm 12:046346a16ff4 228 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
wardm 12:046346a16ff4 229
wardm 12:046346a16ff4 230 // Cut the PA just in case, RFO output, power = -1 dBm
wardm 12:046346a16ff4 231 this->Write( REG_PACONFIG, 0x00 );
wardm 12:046346a16ff4 232
wardm 12:046346a16ff4 233 // Launch Rx chain calibration for LF band
wardm 12:046346a16ff4 234 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
wardm 12:046346a16ff4 235 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
wardm 12:046346a16ff4 236 {
wardm 12:046346a16ff4 237 }
wardm 12:046346a16ff4 238
wardm 12:046346a16ff4 239 // Sets a Frequency in HF band
wardm 12:046346a16ff4 240 SetChannel( 868000000 );
wardm 12:046346a16ff4 241
wardm 12:046346a16ff4 242 // Launch Rx chain calibration for HF band
wardm 12:046346a16ff4 243 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
wardm 12:046346a16ff4 244 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
wardm 12:046346a16ff4 245 {
wardm 12:046346a16ff4 246 }
wardm 12:046346a16ff4 247
wardm 12:046346a16ff4 248 // Restore context
wardm 12:046346a16ff4 249 this->Write( REG_PACONFIG, regPaConfigInitVal );
wardm 12:046346a16ff4 250 SetChannel( initialFreq );
wardm 12:046346a16ff4 251 }
wardm 12:046346a16ff4 252
wardm 12:046346a16ff4 253 /*!
wardm 12:046346a16ff4 254 * Returns the known FSK bandwidth registers value
wardm 12:046346a16ff4 255 *
wardm 12:046346a16ff4 256 * \param [IN] bandwidth Bandwidth value in Hz
wardm 12:046346a16ff4 257 * \retval regValue Bandwidth register value.
wardm 12:046346a16ff4 258 */
wardm 12:046346a16ff4 259 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
wardm 12:046346a16ff4 260 {
wardm 12:046346a16ff4 261 uint8_t i;
wardm 12:046346a16ff4 262
wardm 12:046346a16ff4 263 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( BandwidthMap ) ) - 1; i++ )
wardm 12:046346a16ff4 264 {
wardm 12:046346a16ff4 265 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
wardm 12:046346a16ff4 266 {
wardm 12:046346a16ff4 267 return FskBandwidths[i].RegValue;
wardm 12:046346a16ff4 268 }
wardm 12:046346a16ff4 269 }
wardm 12:046346a16ff4 270 // ERROR: Value not found
wardm 12:046346a16ff4 271 while( 1 );
wardm 12:046346a16ff4 272 }
wardm 12:046346a16ff4 273
wardm 12:046346a16ff4 274 /*!
wardm 12:046346a16ff4 275 * Returns the known LoRa bandwidth registers value
wardm 12:046346a16ff4 276 *
wardm 12:046346a16ff4 277 * \param [IN] bandwidth Bandwidth value in Hz
wardm 12:046346a16ff4 278 * \retval regValue Bandwidth register value.
wardm 12:046346a16ff4 279 */
wardm 12:046346a16ff4 280 uint8_t SX1276::GetLoRaBandwidthRegValue( uint32_t bandwidth )
wardm 12:046346a16ff4 281 {
wardm 12:046346a16ff4 282 uint8_t i;
wardm 12:046346a16ff4 283
wardm 12:046346a16ff4 284 for( i = 0; i < ( sizeof( LoRaBandwidths ) / sizeof( BandwidthMap ) ) - 1; i++ )
wardm 12:046346a16ff4 285 {
wardm 12:046346a16ff4 286 if( ( bandwidth >= LoRaBandwidths[i].bandwidth ) && ( bandwidth < LoRaBandwidths[i + 1].bandwidth ) )
wardm 12:046346a16ff4 287 {
wardm 12:046346a16ff4 288 return LoRaBandwidths[i].RegValue;
wardm 12:046346a16ff4 289 }
wardm 12:046346a16ff4 290 }
wardm 12:046346a16ff4 291 // ERROR: Value not found
wardm 12:046346a16ff4 292 while( 1 );
wardm 12:046346a16ff4 293 }
wardm 12:046346a16ff4 294
wardm 12:046346a16ff4 295 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
wardm 12:046346a16ff4 296 uint32_t datarate, uint8_t coderate,
wardm 12:046346a16ff4 297 uint32_t bandwidthAfc, uint16_t preambleLen,
wardm 12:046346a16ff4 298 uint16_t symbTimeout, bool fixLen,
wardm 12:046346a16ff4 299 uint8_t payloadLen,
wardm 12:046346a16ff4 300 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
wardm 12:046346a16ff4 301 bool iqInverted, bool rxContinuous )
wardm 12:046346a16ff4 302 {
wardm 12:046346a16ff4 303 SetModem( modem );
wardm 12:046346a16ff4 304
wardm 12:046346a16ff4 305 switch( modem )
wardm 12:046346a16ff4 306 {
wardm 12:046346a16ff4 307 case MODEM_FSK:
wardm 12:046346a16ff4 308 {
wardm 12:046346a16ff4 309 this->settings.Fsk.Bandwidth = bandwidth;
wardm 12:046346a16ff4 310 this->settings.Fsk.Datarate = datarate;
wardm 12:046346a16ff4 311 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
wardm 12:046346a16ff4 312 this->settings.Fsk.FixLen = fixLen;
wardm 12:046346a16ff4 313 this->settings.Fsk.PayloadLen = payloadLen;
wardm 12:046346a16ff4 314 this->settings.Fsk.CrcOn = crcOn;
wardm 12:046346a16ff4 315 this->settings.Fsk.IqInverted = iqInverted;
wardm 12:046346a16ff4 316 this->settings.Fsk.RxContinuous = rxContinuous;
wardm 12:046346a16ff4 317 this->settings.Fsk.PreambleLen = preambleLen;
wardm 12:046346a16ff4 318 this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3;
wardm 12:046346a16ff4 319
wardm 12:046346a16ff4 320
wardm 12:046346a16ff4 321 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
wardm 12:046346a16ff4 322 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
wardm 12:046346a16ff4 323 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
wardm 12:046346a16ff4 324
wardm 12:046346a16ff4 325 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
wardm 12:046346a16ff4 326 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
wardm 12:046346a16ff4 327
wardm 12:046346a16ff4 328 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
wardm 12:046346a16ff4 329 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
wardm 12:046346a16ff4 330
wardm 12:046346a16ff4 331 if( fixLen == 1 )
wardm 12:046346a16ff4 332 {
wardm 12:046346a16ff4 333 Write( REG_PAYLOADLENGTH, payloadLen );
wardm 12:046346a16ff4 334 }
wardm 12:046346a16ff4 335 else
wardm 12:046346a16ff4 336 {
wardm 12:046346a16ff4 337 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
wardm 12:046346a16ff4 338 }
wardm 12:046346a16ff4 339
wardm 12:046346a16ff4 340 Write( REG_PACKETCONFIG1,
wardm 12:046346a16ff4 341 ( Read( REG_PACKETCONFIG1 ) &
wardm 12:046346a16ff4 342 RF_PACKETCONFIG1_CRC_MASK &
wardm 12:046346a16ff4 343 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
wardm 12:046346a16ff4 344 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
wardm 12:046346a16ff4 345 ( crcOn << 4 ) );
wardm 12:046346a16ff4 346 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
wardm 12:046346a16ff4 347 }
wardm 12:046346a16ff4 348 break;
wardm 12:046346a16ff4 349 case MODEM_LORA:
wardm 12:046346a16ff4 350 {
wardm 12:046346a16ff4 351 if (bandwidth > 11) // specified in Hz, needs mapping
wardm 12:046346a16ff4 352 bandwidth = GetLoRaBandwidthRegValue(bandwidth);
wardm 12:046346a16ff4 353 if( bandwidth > LORA_BANKWIDTH_500kHz )
wardm 12:046346a16ff4 354 {
wardm 12:046346a16ff4 355 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
wardm 12:046346a16ff4 356 while( 1 );
wardm 12:046346a16ff4 357 }
wardm 12:046346a16ff4 358 this->settings.LoRa.Bandwidth = bandwidth;
wardm 12:046346a16ff4 359 this->settings.LoRa.Datarate = datarate;
wardm 12:046346a16ff4 360 this->settings.LoRa.Coderate = coderate;
wardm 12:046346a16ff4 361 this->settings.LoRa.PreambleLen = preambleLen;
wardm 12:046346a16ff4 362 this->settings.LoRa.FixLen = fixLen;
wardm 12:046346a16ff4 363 this->settings.LoRa.PayloadLen = payloadLen;
wardm 12:046346a16ff4 364 this->settings.LoRa.CrcOn = crcOn;
wardm 12:046346a16ff4 365 this->settings.LoRa.FreqHopOn = freqHopOn;
wardm 12:046346a16ff4 366 this->settings.LoRa.HopPeriod = hopPeriod;
wardm 12:046346a16ff4 367 this->settings.LoRa.IqInverted = iqInverted;
wardm 12:046346a16ff4 368 this->settings.LoRa.RxContinuous = rxContinuous;
wardm 12:046346a16ff4 369
wardm 12:046346a16ff4 370 if( datarate > LORA_SF12 )
wardm 12:046346a16ff4 371 {
wardm 12:046346a16ff4 372 datarate = LORA_SF12;
wardm 12:046346a16ff4 373 }
wardm 12:046346a16ff4 374 else if( datarate < LORA_SF6 )
wardm 12:046346a16ff4 375 {
wardm 12:046346a16ff4 376 datarate = LORA_SF6;
wardm 12:046346a16ff4 377 }
wardm 12:046346a16ff4 378
wardm 12:046346a16ff4 379 if( ( ( bandwidth == LORA_BANKWIDTH_125kHz ) && ( ( datarate == LORA_SF11 ) || ( datarate == LORA_SF12 ) ) ) ||
wardm 12:046346a16ff4 380 ( ( bandwidth == LORA_BANKWIDTH_250kHz ) && ( datarate == LORA_SF12 ) ) )
wardm 12:046346a16ff4 381 {
wardm 12:046346a16ff4 382 this->settings.LoRa.LowDatarateOptimize = 0x01;
wardm 12:046346a16ff4 383 }
wardm 12:046346a16ff4 384 else
wardm 12:046346a16ff4 385 {
wardm 12:046346a16ff4 386 this->settings.LoRa.LowDatarateOptimize = 0x00;
wardm 12:046346a16ff4 387 }
wardm 12:046346a16ff4 388
wardm 12:046346a16ff4 389 Write( REG_LR_MODEMCONFIG1,
wardm 12:046346a16ff4 390 ( Read( REG_LR_MODEMCONFIG1 ) &
wardm 12:046346a16ff4 391 RFLR_MODEMCONFIG1_BW_MASK &
wardm 12:046346a16ff4 392 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
wardm 12:046346a16ff4 393 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
wardm 12:046346a16ff4 394 ( bandwidth << 4 ) | ( coderate << 1 ) |
wardm 12:046346a16ff4 395 fixLen );
wardm 12:046346a16ff4 396
wardm 12:046346a16ff4 397 Write( REG_LR_MODEMCONFIG2,
wardm 12:046346a16ff4 398 ( Read( REG_LR_MODEMCONFIG2 ) &
wardm 12:046346a16ff4 399 RFLR_MODEMCONFIG2_SF_MASK &
wardm 12:046346a16ff4 400 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
wardm 12:046346a16ff4 401 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
wardm 12:046346a16ff4 402 ( datarate << 4 ) | ( crcOn << 2 ) |
wardm 12:046346a16ff4 403 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
wardm 12:046346a16ff4 404
wardm 12:046346a16ff4 405 Write( REG_LR_MODEMCONFIG3,
wardm 12:046346a16ff4 406 ( Read( REG_LR_MODEMCONFIG3 ) &
wardm 12:046346a16ff4 407 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
wardm 12:046346a16ff4 408 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
wardm 12:046346a16ff4 409
wardm 12:046346a16ff4 410 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
wardm 12:046346a16ff4 411
wardm 12:046346a16ff4 412 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
wardm 12:046346a16ff4 413 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
wardm 12:046346a16ff4 414
wardm 12:046346a16ff4 415 if( fixLen == 1 )
wardm 12:046346a16ff4 416 {
wardm 12:046346a16ff4 417 Write( REG_LR_PAYLOADLENGTH, payloadLen );
wardm 12:046346a16ff4 418 }
wardm 12:046346a16ff4 419
wardm 12:046346a16ff4 420 if( this->settings.LoRa.FreqHopOn == true )
wardm 12:046346a16ff4 421 {
wardm 12:046346a16ff4 422 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
wardm 12:046346a16ff4 423 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
wardm 12:046346a16ff4 424 }
wardm 12:046346a16ff4 425
wardm 12:046346a16ff4 426 if( ( bandwidth == LORA_BANKWIDTH_500kHz ) && ( this->settings.Channel > RF_MID_BAND_THRESH ) )
wardm 12:046346a16ff4 427 {
wardm 12:046346a16ff4 428 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
wardm 12:046346a16ff4 429 Write( REG_LR_TEST36, 0x02 );
wardm 12:046346a16ff4 430 Write( REG_LR_TEST3A, 0x64 );
wardm 12:046346a16ff4 431 }
wardm 12:046346a16ff4 432 else if( bandwidth == LORA_BANKWIDTH_500kHz )
wardm 12:046346a16ff4 433 {
wardm 12:046346a16ff4 434 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
wardm 12:046346a16ff4 435 Write( REG_LR_TEST36, 0x02 );
wardm 12:046346a16ff4 436 Write( REG_LR_TEST3A, 0x7F );
wardm 12:046346a16ff4 437 }
wardm 12:046346a16ff4 438 else
wardm 12:046346a16ff4 439 {
wardm 12:046346a16ff4 440 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
wardm 12:046346a16ff4 441 Write( REG_LR_TEST36, 0x03 );
wardm 12:046346a16ff4 442 }
wardm 12:046346a16ff4 443
wardm 12:046346a16ff4 444 if( datarate == LORA_SF6 )
wardm 12:046346a16ff4 445 {
wardm 12:046346a16ff4 446 Write( REG_LR_DETECTOPTIMIZE,
wardm 12:046346a16ff4 447 ( Read( REG_LR_DETECTOPTIMIZE ) &
wardm 12:046346a16ff4 448 RFLR_DETECTIONOPTIMIZE_MASK ) |
wardm 12:046346a16ff4 449 RFLR_DETECTIONOPTIMIZE_SF6 );
wardm 12:046346a16ff4 450 Write( REG_LR_DETECTIONTHRESHOLD,
wardm 12:046346a16ff4 451 RFLR_DETECTIONTHRESH_SF6 );
wardm 12:046346a16ff4 452 }
wardm 12:046346a16ff4 453 else
wardm 12:046346a16ff4 454 {
wardm 12:046346a16ff4 455 Write( REG_LR_DETECTOPTIMIZE,
wardm 12:046346a16ff4 456 ( Read( REG_LR_DETECTOPTIMIZE ) &
wardm 12:046346a16ff4 457 RFLR_DETECTIONOPTIMIZE_MASK ) |
wardm 12:046346a16ff4 458 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
wardm 12:046346a16ff4 459 Write( REG_LR_DETECTIONTHRESHOLD,
wardm 12:046346a16ff4 460 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
wardm 12:046346a16ff4 461 }
wardm 12:046346a16ff4 462 }
wardm 12:046346a16ff4 463 break;
wardm 12:046346a16ff4 464 }
wardm 12:046346a16ff4 465 }
wardm 12:046346a16ff4 466
wardm 12:046346a16ff4 467 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
wardm 12:046346a16ff4 468 uint32_t bandwidth, uint32_t datarate,
wardm 12:046346a16ff4 469 uint8_t coderate, uint16_t preambleLen,
wardm 12:046346a16ff4 470 bool fixLen, bool crcOn, bool freqHopOn,
wardm 12:046346a16ff4 471 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
wardm 12:046346a16ff4 472 {
wardm 12:046346a16ff4 473 SetModem( modem );
wardm 12:046346a16ff4 474 SetRfTxPower( power );
wardm 12:046346a16ff4 475
wardm 12:046346a16ff4 476 switch( modem )
wardm 12:046346a16ff4 477 {
wardm 12:046346a16ff4 478 case MODEM_FSK:
wardm 12:046346a16ff4 479 {
wardm 12:046346a16ff4 480 this->settings.Fsk.Power = power;
wardm 12:046346a16ff4 481 this->settings.Fsk.Fdev = fdev;
wardm 12:046346a16ff4 482 this->settings.Fsk.Bandwidth = bandwidth;
wardm 12:046346a16ff4 483 this->settings.Fsk.Datarate = datarate;
wardm 12:046346a16ff4 484 this->settings.Fsk.PreambleLen = preambleLen;
wardm 12:046346a16ff4 485 this->settings.Fsk.FixLen = fixLen;
wardm 12:046346a16ff4 486 this->settings.Fsk.CrcOn = crcOn;
wardm 12:046346a16ff4 487 this->settings.Fsk.IqInverted = iqInverted;
wardm 12:046346a16ff4 488 this->settings.Fsk.TxTimeout = timeout;
wardm 12:046346a16ff4 489
wardm 12:046346a16ff4 490 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
wardm 12:046346a16ff4 491 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
wardm 12:046346a16ff4 492 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
wardm 12:046346a16ff4 493
wardm 12:046346a16ff4 494 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
wardm 12:046346a16ff4 495 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
wardm 12:046346a16ff4 496 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
wardm 12:046346a16ff4 497
wardm 12:046346a16ff4 498 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
wardm 12:046346a16ff4 499 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
wardm 12:046346a16ff4 500
wardm 12:046346a16ff4 501 Write( REG_PACKETCONFIG1,
wardm 12:046346a16ff4 502 ( Read( REG_PACKETCONFIG1 ) &
wardm 12:046346a16ff4 503 RF_PACKETCONFIG1_CRC_MASK &
wardm 12:046346a16ff4 504 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
wardm 12:046346a16ff4 505 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
wardm 12:046346a16ff4 506 ( crcOn << 4 ) );
wardm 12:046346a16ff4 507 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
wardm 12:046346a16ff4 508 }
wardm 12:046346a16ff4 509 break;
wardm 12:046346a16ff4 510 case MODEM_LORA:
wardm 12:046346a16ff4 511 {
wardm 12:046346a16ff4 512 this->settings.LoRa.Power = power;
wardm 12:046346a16ff4 513 if (bandwidth > 11) // specified in Hz, needs mapping
wardm 12:046346a16ff4 514 bandwidth = GetLoRaBandwidthRegValue(bandwidth);
wardm 12:046346a16ff4 515 if( bandwidth > LORA_BANKWIDTH_500kHz )
wardm 12:046346a16ff4 516 {
wardm 12:046346a16ff4 517 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
wardm 12:046346a16ff4 518 while( 1 );
wardm 12:046346a16ff4 519 }
wardm 12:046346a16ff4 520 this->settings.LoRa.Bandwidth = bandwidth;
wardm 12:046346a16ff4 521 this->settings.LoRa.Datarate = datarate;
wardm 12:046346a16ff4 522 this->settings.LoRa.Coderate = coderate;
wardm 12:046346a16ff4 523 this->settings.LoRa.PreambleLen = preambleLen;
wardm 12:046346a16ff4 524 this->settings.LoRa.FixLen = fixLen;
wardm 12:046346a16ff4 525 this->settings.LoRa.FreqHopOn = freqHopOn;
wardm 12:046346a16ff4 526 this->settings.LoRa.HopPeriod = hopPeriod;
wardm 12:046346a16ff4 527 this->settings.LoRa.CrcOn = crcOn;
wardm 12:046346a16ff4 528 this->settings.LoRa.IqInverted = iqInverted;
wardm 12:046346a16ff4 529 this->settings.LoRa.TxTimeout = timeout;
wardm 12:046346a16ff4 530
wardm 12:046346a16ff4 531 if( datarate > LORA_SF12 )
wardm 12:046346a16ff4 532 {
wardm 12:046346a16ff4 533 datarate = LORA_SF12;
wardm 12:046346a16ff4 534 }
wardm 12:046346a16ff4 535 else if( datarate < LORA_SF6 )
wardm 12:046346a16ff4 536 {
wardm 12:046346a16ff4 537 datarate = LORA_SF6;
wardm 12:046346a16ff4 538 }
wardm 12:046346a16ff4 539 if( ( ( bandwidth == LORA_BANKWIDTH_125kHz ) && ( ( datarate == LORA_SF11 ) || ( datarate == LORA_SF12 ) ) ) ||
wardm 12:046346a16ff4 540 ( ( bandwidth == LORA_BANKWIDTH_250kHz ) && ( datarate == LORA_SF12 ) ) )
wardm 12:046346a16ff4 541 {
wardm 12:046346a16ff4 542 this->settings.LoRa.LowDatarateOptimize = 0x01;
wardm 12:046346a16ff4 543 }
wardm 12:046346a16ff4 544 else
wardm 12:046346a16ff4 545 {
wardm 12:046346a16ff4 546 this->settings.LoRa.LowDatarateOptimize = 0x00;
wardm 12:046346a16ff4 547 }
wardm 12:046346a16ff4 548
wardm 12:046346a16ff4 549 if( this->settings.LoRa.FreqHopOn == true )
wardm 12:046346a16ff4 550 {
wardm 12:046346a16ff4 551 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
wardm 12:046346a16ff4 552 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
wardm 12:046346a16ff4 553 }
wardm 12:046346a16ff4 554
wardm 12:046346a16ff4 555 Write( REG_LR_MODEMCONFIG1,
wardm 12:046346a16ff4 556 ( Read( REG_LR_MODEMCONFIG1 ) &
wardm 12:046346a16ff4 557 RFLR_MODEMCONFIG1_BW_MASK &
wardm 12:046346a16ff4 558 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
wardm 12:046346a16ff4 559 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
wardm 12:046346a16ff4 560 ( bandwidth << 4 ) | ( coderate << 1 ) |
wardm 12:046346a16ff4 561 fixLen );
wardm 12:046346a16ff4 562
wardm 12:046346a16ff4 563 Write( REG_LR_MODEMCONFIG2,
wardm 12:046346a16ff4 564 ( Read( REG_LR_MODEMCONFIG2 ) &
wardm 12:046346a16ff4 565 RFLR_MODEMCONFIG2_SF_MASK &
wardm 12:046346a16ff4 566 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
wardm 12:046346a16ff4 567 ( datarate << 4 ) | ( crcOn << 2 ) );
wardm 12:046346a16ff4 568
wardm 12:046346a16ff4 569 Write( REG_LR_MODEMCONFIG3,
wardm 12:046346a16ff4 570 ( Read( REG_LR_MODEMCONFIG3 ) &
wardm 12:046346a16ff4 571 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
wardm 12:046346a16ff4 572 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
wardm 12:046346a16ff4 573
wardm 12:046346a16ff4 574 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
wardm 12:046346a16ff4 575 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
wardm 12:046346a16ff4 576
wardm 12:046346a16ff4 577 if( datarate == LORA_SF6 )
wardm 12:046346a16ff4 578 {
wardm 12:046346a16ff4 579 Write( REG_LR_DETECTOPTIMIZE,
wardm 12:046346a16ff4 580 ( Read( REG_LR_DETECTOPTIMIZE ) &
wardm 12:046346a16ff4 581 RFLR_DETECTIONOPTIMIZE_MASK ) |
wardm 12:046346a16ff4 582 RFLR_DETECTIONOPTIMIZE_SF6 );
wardm 12:046346a16ff4 583 Write( REG_LR_DETECTIONTHRESHOLD,
wardm 12:046346a16ff4 584 RFLR_DETECTIONTHRESH_SF6 );
wardm 12:046346a16ff4 585 }
wardm 12:046346a16ff4 586 else
wardm 12:046346a16ff4 587 {
wardm 12:046346a16ff4 588 Write( REG_LR_DETECTOPTIMIZE,
wardm 12:046346a16ff4 589 ( Read( REG_LR_DETECTOPTIMIZE ) &
wardm 12:046346a16ff4 590 RFLR_DETECTIONOPTIMIZE_MASK ) |
wardm 12:046346a16ff4 591 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
wardm 12:046346a16ff4 592 Write( REG_LR_DETECTIONTHRESHOLD,
wardm 12:046346a16ff4 593 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
wardm 12:046346a16ff4 594 }
wardm 12:046346a16ff4 595 }
wardm 12:046346a16ff4 596 break;
wardm 12:046346a16ff4 597 }
wardm 12:046346a16ff4 598 }
wardm 12:046346a16ff4 599
wardm 12:046346a16ff4 600 uint32_t SX1276::TimeOnAir( RadioModems_t modem, int16_t pktLen )
wardm 12:046346a16ff4 601 {
wardm 12:046346a16ff4 602 uint32_t airTime = 0;
wardm 12:046346a16ff4 603
wardm 12:046346a16ff4 604 switch( modem )
wardm 12:046346a16ff4 605 {
wardm 12:046346a16ff4 606 case MODEM_FSK:
wardm 12:046346a16ff4 607 {
wardm 12:046346a16ff4 608 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
wardm 12:046346a16ff4 609 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
wardm 12:046346a16ff4 610 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
wardm 12:046346a16ff4 611 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
wardm 12:046346a16ff4 612 pktLen +
wardm 12:046346a16ff4 613 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
wardm 12:046346a16ff4 614 this->settings.Fsk.Datarate ) * 1e3 );
wardm 12:046346a16ff4 615 }
wardm 12:046346a16ff4 616 break;
wardm 12:046346a16ff4 617 case MODEM_LORA:
wardm 12:046346a16ff4 618 {
wardm 12:046346a16ff4 619 double bw = 0.0;
wardm 12:046346a16ff4 620 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
wardm 12:046346a16ff4 621 switch( this->settings.LoRa.Bandwidth )
wardm 12:046346a16ff4 622 {
wardm 12:046346a16ff4 623 case LORA_BANKWIDTH_7kHz: // 7.8 kHz
wardm 12:046346a16ff4 624 bw = 78e2;
wardm 12:046346a16ff4 625 break;
wardm 12:046346a16ff4 626 case LORA_BANKWIDTH_10kHz: // 10.4 kHz
wardm 12:046346a16ff4 627 bw = 104e2;
wardm 12:046346a16ff4 628 break;
wardm 12:046346a16ff4 629 case LORA_BANKWIDTH_15kHz: // 15.6 kHz
wardm 12:046346a16ff4 630 bw = 156e2;
wardm 12:046346a16ff4 631 break;
wardm 12:046346a16ff4 632 case LORA_BANKWIDTH_20kHz: // 20.8 kHz
wardm 12:046346a16ff4 633 bw = 208e2;
wardm 12:046346a16ff4 634 break;
wardm 12:046346a16ff4 635 case LORA_BANKWIDTH_31kHz: // 31.25 kHz
wardm 12:046346a16ff4 636 bw = 312e2;
wardm 12:046346a16ff4 637 break;
wardm 12:046346a16ff4 638 case LORA_BANKWIDTH_41kHz: // 41.7 kHz
wardm 12:046346a16ff4 639 bw = 414e2;
wardm 12:046346a16ff4 640 break;
wardm 12:046346a16ff4 641 case LORA_BANKWIDTH_62kHz: // 62.5 kHz
wardm 12:046346a16ff4 642 bw = 625e2;
wardm 12:046346a16ff4 643 break;
wardm 12:046346a16ff4 644 case LORA_BANKWIDTH_125kHz: // 125 kHz
wardm 12:046346a16ff4 645 bw = 125e3;
wardm 12:046346a16ff4 646 break;
wardm 12:046346a16ff4 647 case LORA_BANKWIDTH_250kHz: // 250 kHz
wardm 12:046346a16ff4 648 bw = 250e3;
wardm 12:046346a16ff4 649 break;
wardm 12:046346a16ff4 650 case LORA_BANKWIDTH_500kHz: // 500 kHz
wardm 12:046346a16ff4 651 bw = 500e3;
wardm 12:046346a16ff4 652 break;
wardm 12:046346a16ff4 653 }
wardm 12:046346a16ff4 654
wardm 12:046346a16ff4 655 // Symbol rate : time for one symbol (secs)
wardm 12:046346a16ff4 656 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
wardm 12:046346a16ff4 657 double ts = 1 / rs;
wardm 12:046346a16ff4 658 // time of preamble
wardm 12:046346a16ff4 659 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
wardm 12:046346a16ff4 660 // Symbol length of payload and time
wardm 12:046346a16ff4 661 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
wardm 12:046346a16ff4 662 28 + 16 * this->settings.LoRa.CrcOn -
wardm 12:046346a16ff4 663 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
wardm 12:046346a16ff4 664 ( double )( 4 * ( this->settings.LoRa.Datarate -
wardm 12:046346a16ff4 665 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) *
wardm 12:046346a16ff4 666 ( this->settings.LoRa.Coderate + 4 );
wardm 12:046346a16ff4 667 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
wardm 12:046346a16ff4 668 double tPayload = nPayload * ts;
wardm 12:046346a16ff4 669 // Time on air
wardm 12:046346a16ff4 670 double tOnAir = tPreamble + tPayload;
wardm 12:046346a16ff4 671 // return ms secs
wardm 12:046346a16ff4 672 airTime = floor( tOnAir * 1e3 + 0.999 );
wardm 12:046346a16ff4 673 }
wardm 12:046346a16ff4 674 break;
wardm 12:046346a16ff4 675 }
wardm 12:046346a16ff4 676 return airTime;
wardm 12:046346a16ff4 677 }
wardm 12:046346a16ff4 678
wardm 12:046346a16ff4 679 void SX1276::Send( void *buffer, int16_t size, void *header, int16_t hsize )
wardm 12:046346a16ff4 680 {
wardm 12:046346a16ff4 681 uint32_t txTimeout = 0;
wardm 12:046346a16ff4 682
wardm 12:046346a16ff4 683 switch( this->settings.Modem )
wardm 12:046346a16ff4 684 {
wardm 12:046346a16ff4 685 case MODEM_FSK:
wardm 12:046346a16ff4 686 {
wardm 12:046346a16ff4 687 this->settings.FskPacketHandler.NbBytes = 0;
wardm 12:046346a16ff4 688 this->settings.FskPacketHandler.Size = size + hsize;
wardm 12:046346a16ff4 689
wardm 12:046346a16ff4 690 if( this->settings.Fsk.FixLen == false )
wardm 12:046346a16ff4 691 {
wardm 12:046346a16ff4 692 uint8_t tmpsize = size + hsize;
wardm 12:046346a16ff4 693 WriteFifo( ( uint8_t* )&tmpsize, 1 );
wardm 12:046346a16ff4 694 }
wardm 12:046346a16ff4 695 else
wardm 12:046346a16ff4 696 {
wardm 12:046346a16ff4 697 Write( REG_PAYLOADLENGTH, size + hsize);
wardm 12:046346a16ff4 698 }
wardm 12:046346a16ff4 699
wardm 12:046346a16ff4 700 if( ( size + hsize > 0 ) && ( size + hsize <= 64 ) )
wardm 12:046346a16ff4 701 {
wardm 12:046346a16ff4 702 this->settings.FskPacketHandler.ChunkSize = size + hsize;
wardm 12:046346a16ff4 703 }
wardm 12:046346a16ff4 704 else
wardm 12:046346a16ff4 705 {
wardm 12:046346a16ff4 706 if (header) {
wardm 12:046346a16ff4 707 WriteFifo( header, hsize );
wardm 12:046346a16ff4 708 memcpy( rxtxBuffer, header, hsize );
wardm 12:046346a16ff4 709 }
wardm 12:046346a16ff4 710 memcpy( rxtxBuffer+hsize, (uint8_t *)buffer+hsize, size );
wardm 12:046346a16ff4 711 this->settings.FskPacketHandler.ChunkSize = 32;
wardm 12:046346a16ff4 712 }
wardm 12:046346a16ff4 713
wardm 12:046346a16ff4 714 // Write payload buffer
wardm 12:046346a16ff4 715 if (header)
wardm 12:046346a16ff4 716 WriteFifo( header, hsize );
wardm 12:046346a16ff4 717 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
wardm 12:046346a16ff4 718 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
wardm 12:046346a16ff4 719 txTimeout = this->settings.Fsk.TxTimeout;
wardm 12:046346a16ff4 720 }
wardm 12:046346a16ff4 721 break;
wardm 12:046346a16ff4 722 case MODEM_LORA:
wardm 12:046346a16ff4 723 {
wardm 12:046346a16ff4 724 if( this->settings.LoRa.IqInverted == true )
wardm 12:046346a16ff4 725 {
wardm 12:046346a16ff4 726 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
wardm 12:046346a16ff4 727 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
wardm 12:046346a16ff4 728 }
wardm 12:046346a16ff4 729 else
wardm 12:046346a16ff4 730 {
wardm 12:046346a16ff4 731 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
wardm 12:046346a16ff4 732 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
wardm 12:046346a16ff4 733 }
wardm 12:046346a16ff4 734
wardm 12:046346a16ff4 735 this->settings.LoRaPacketHandler.Size = size + hsize;
wardm 12:046346a16ff4 736
wardm 12:046346a16ff4 737 // Initializes the payload size
wardm 12:046346a16ff4 738 Write( REG_LR_PAYLOADLENGTH, size + hsize);
wardm 12:046346a16ff4 739
wardm 12:046346a16ff4 740 // Full buffer used for Tx
wardm 12:046346a16ff4 741 Write( REG_LR_FIFOTXBASEADDR, 0 );
wardm 12:046346a16ff4 742 Write( REG_LR_FIFOADDRPTR, 0 );
wardm 12:046346a16ff4 743
wardm 12:046346a16ff4 744 // FIFO operations can not take place in Sleep mode
wardm 12:046346a16ff4 745 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
wardm 12:046346a16ff4 746 {
wardm 12:046346a16ff4 747 Standby( );
wardm 12:046346a16ff4 748 Sleep_ms( 1 );
wardm 12:046346a16ff4 749 }
wardm 12:046346a16ff4 750 // Write payload buffer
wardm 12:046346a16ff4 751 if (header)
wardm 12:046346a16ff4 752 WriteFifo( header, hsize );
wardm 12:046346a16ff4 753 WriteFifo( buffer, size );
wardm 12:046346a16ff4 754 txTimeout = this->settings.LoRa.TxTimeout;
wardm 12:046346a16ff4 755 }
wardm 12:046346a16ff4 756 break;
wardm 12:046346a16ff4 757 }
wardm 12:046346a16ff4 758
wardm 12:046346a16ff4 759 Tx( txTimeout );
wardm 12:046346a16ff4 760 }
wardm 12:046346a16ff4 761
wardm 12:046346a16ff4 762 void SX1276::Sleep( void )
wardm 12:046346a16ff4 763 {
wardm 12:046346a16ff4 764 SetTimeout(TXTimeoutTimer, NULL);
wardm 12:046346a16ff4 765 SetTimeout(RXTimeoutTimer, NULL);
wardm 12:046346a16ff4 766
wardm 12:046346a16ff4 767 SetOpMode( RF_OPMODE_SLEEP );
wardm 12:046346a16ff4 768 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 769 }
wardm 12:046346a16ff4 770
wardm 12:046346a16ff4 771 void SX1276::Standby( void )
wardm 12:046346a16ff4 772 {
wardm 12:046346a16ff4 773 SetTimeout(TXTimeoutTimer, NULL);
wardm 12:046346a16ff4 774 SetTimeout(RXTimeoutTimer, NULL);
wardm 12:046346a16ff4 775
wardm 12:046346a16ff4 776 SetOpMode( RF_OPMODE_STANDBY );
wardm 12:046346a16ff4 777 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 778 }
wardm 12:046346a16ff4 779
wardm 12:046346a16ff4 780 void SX1276::Rx( uint32_t timeout )
wardm 12:046346a16ff4 781 {
wardm 12:046346a16ff4 782 bool rxContinuous = false;
wardm 12:046346a16ff4 783
wardm 12:046346a16ff4 784 switch( this->settings.Modem )
wardm 12:046346a16ff4 785 {
wardm 12:046346a16ff4 786 case MODEM_FSK:
wardm 12:046346a16ff4 787 {
wardm 12:046346a16ff4 788 rxContinuous = this->settings.Fsk.RxContinuous;
wardm 12:046346a16ff4 789
wardm 12:046346a16ff4 790 // DIO0=PayloadReady
wardm 12:046346a16ff4 791 // DIO1=FifoLevel
wardm 12:046346a16ff4 792 // DIO2=SyncAddr
wardm 12:046346a16ff4 793 // DIO3=FifoEmpty
wardm 12:046346a16ff4 794 // DIO4=Preamble
wardm 12:046346a16ff4 795 // DIO5=ModeReady
wardm 12:046346a16ff4 796 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
wardm 12:046346a16ff4 797 RF_DIOMAPPING1_DIO1_MASK &
wardm 12:046346a16ff4 798 RF_DIOMAPPING1_DIO2_MASK ) |
wardm 12:046346a16ff4 799 RF_DIOMAPPING1_DIO0_00 |
wardm 12:046346a16ff4 800 RF_DIOMAPPING1_DIO1_00 |
wardm 12:046346a16ff4 801 RF_DIOMAPPING1_DIO2_11 );
wardm 12:046346a16ff4 802
wardm 12:046346a16ff4 803 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
wardm 12:046346a16ff4 804 RF_DIOMAPPING2_MAP_MASK ) |
wardm 12:046346a16ff4 805 RF_DIOMAPPING2_DIO4_11 |
wardm 12:046346a16ff4 806 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
wardm 12:046346a16ff4 807
wardm 12:046346a16ff4 808 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
wardm 12:046346a16ff4 809
wardm 12:046346a16ff4 810 Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
wardm 12:046346a16ff4 811
wardm 12:046346a16ff4 812 this->settings.FskPacketHandler.PreambleDetected = false;
wardm 12:046346a16ff4 813 this->settings.FskPacketHandler.SyncWordDetected = false;
wardm 12:046346a16ff4 814 this->settings.FskPacketHandler.NbBytes = 0;
wardm 12:046346a16ff4 815 this->settings.FskPacketHandler.Size = 0;
wardm 12:046346a16ff4 816 }
wardm 12:046346a16ff4 817 break;
wardm 12:046346a16ff4 818 case MODEM_LORA:
wardm 12:046346a16ff4 819 {
wardm 12:046346a16ff4 820 if( this->settings.LoRa.IqInverted == true )
wardm 12:046346a16ff4 821 {
wardm 12:046346a16ff4 822 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
wardm 12:046346a16ff4 823 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
wardm 12:046346a16ff4 824 }
wardm 12:046346a16ff4 825 else
wardm 12:046346a16ff4 826 {
wardm 12:046346a16ff4 827 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
wardm 12:046346a16ff4 828 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
wardm 12:046346a16ff4 829 }
wardm 12:046346a16ff4 830
wardm 12:046346a16ff4 831 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
wardm 12:046346a16ff4 832 if( this->settings.LoRa.Bandwidth < LORA_BANKWIDTH_500kHz )
wardm 12:046346a16ff4 833 {
wardm 12:046346a16ff4 834 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
wardm 12:046346a16ff4 835 Write( REG_LR_TEST30, 0x00 );
wardm 12:046346a16ff4 836 switch( this->settings.LoRa.Bandwidth )
wardm 12:046346a16ff4 837 {
wardm 12:046346a16ff4 838 case LORA_BANKWIDTH_7kHz: // 7.8 kHz
wardm 12:046346a16ff4 839 Write( REG_LR_TEST2F, 0x48 );
wardm 12:046346a16ff4 840 SetChannel(this->settings.Channel + 7.81e3 );
wardm 12:046346a16ff4 841 break;
wardm 12:046346a16ff4 842 case LORA_BANKWIDTH_10kHz: // 10.4 kHz
wardm 12:046346a16ff4 843 Write( REG_LR_TEST2F, 0x44 );
wardm 12:046346a16ff4 844 SetChannel(this->settings.Channel + 10.42e3 );
wardm 12:046346a16ff4 845 break;
wardm 12:046346a16ff4 846 case LORA_BANKWIDTH_15kHz: // 15.6 kHz
wardm 12:046346a16ff4 847 Write( REG_LR_TEST2F, 0x44 );
wardm 12:046346a16ff4 848 SetChannel(this->settings.Channel + 15.62e3 );
wardm 12:046346a16ff4 849 break;
wardm 12:046346a16ff4 850 case LORA_BANKWIDTH_20kHz: // 20.8 kHz
wardm 12:046346a16ff4 851 Write( REG_LR_TEST2F, 0x44 );
wardm 12:046346a16ff4 852 SetChannel(this->settings.Channel + 20.83e3 );
wardm 12:046346a16ff4 853 break;
wardm 12:046346a16ff4 854 case LORA_BANKWIDTH_31kHz: // 31.25 kHz
wardm 12:046346a16ff4 855 Write( REG_LR_TEST2F, 0x44 );
wardm 12:046346a16ff4 856 SetChannel(this->settings.Channel + 31.25e3 );
wardm 12:046346a16ff4 857 break;
wardm 12:046346a16ff4 858 case LORA_BANKWIDTH_41kHz: // 41.4 kHz
wardm 12:046346a16ff4 859 Write( REG_LR_TEST2F, 0x44 );
wardm 12:046346a16ff4 860 SetChannel(this->settings.Channel + 41.67e3 );
wardm 12:046346a16ff4 861 break;
wardm 12:046346a16ff4 862 case LORA_BANKWIDTH_62kHz: // 62.5 kHz
wardm 12:046346a16ff4 863 Write( REG_LR_TEST2F, 0x40 );
wardm 12:046346a16ff4 864 break;
wardm 12:046346a16ff4 865 case LORA_BANKWIDTH_125kHz: // 125 kHz
wardm 12:046346a16ff4 866 Write( REG_LR_TEST2F, 0x40 );
wardm 12:046346a16ff4 867 break;
wardm 12:046346a16ff4 868 case LORA_BANKWIDTH_250kHz: // 250 kHz
wardm 12:046346a16ff4 869 Write( REG_LR_TEST2F, 0x40 );
wardm 12:046346a16ff4 870 break;
wardm 12:046346a16ff4 871 }
wardm 12:046346a16ff4 872 }
wardm 12:046346a16ff4 873 else
wardm 12:046346a16ff4 874 {
wardm 12:046346a16ff4 875 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
wardm 12:046346a16ff4 876 }
wardm 12:046346a16ff4 877
wardm 12:046346a16ff4 878 rxContinuous = this->settings.LoRa.RxContinuous;
wardm 12:046346a16ff4 879
wardm 12:046346a16ff4 880 if( this->settings.LoRa.FreqHopOn == true )
wardm 12:046346a16ff4 881 {
wardm 12:046346a16ff4 882 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
wardm 12:046346a16ff4 883 //RFLR_IRQFLAGS_RXDONE |
wardm 12:046346a16ff4 884 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
wardm 12:046346a16ff4 885 RFLR_IRQFLAGS_VALIDHEADER |
wardm 12:046346a16ff4 886 RFLR_IRQFLAGS_TXDONE |
wardm 12:046346a16ff4 887 RFLR_IRQFLAGS_CADDONE |
wardm 12:046346a16ff4 888 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
wardm 12:046346a16ff4 889 RFLR_IRQFLAGS_CADDETECTED );
wardm 12:046346a16ff4 890
wardm 12:046346a16ff4 891 // DIO0=RxDone, DIO2=FhssChangeChannel
wardm 12:046346a16ff4 892 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
wardm 12:046346a16ff4 893 }
wardm 12:046346a16ff4 894 else
wardm 12:046346a16ff4 895 {
wardm 12:046346a16ff4 896 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
wardm 12:046346a16ff4 897 //RFLR_IRQFLAGS_RXDONE |
wardm 12:046346a16ff4 898 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
wardm 12:046346a16ff4 899 RFLR_IRQFLAGS_VALIDHEADER |
wardm 12:046346a16ff4 900 RFLR_IRQFLAGS_TXDONE |
wardm 12:046346a16ff4 901 RFLR_IRQFLAGS_CADDONE |
wardm 12:046346a16ff4 902 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
wardm 12:046346a16ff4 903 RFLR_IRQFLAGS_CADDETECTED );
wardm 12:046346a16ff4 904
wardm 12:046346a16ff4 905 // DIO0=RxDone
wardm 12:046346a16ff4 906 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
wardm 12:046346a16ff4 907 }
wardm 12:046346a16ff4 908 Write( REG_LR_FIFORXBASEADDR, 0 );
wardm 12:046346a16ff4 909 Write( REG_LR_FIFOADDRPTR, 0 );
wardm 12:046346a16ff4 910 }
wardm 12:046346a16ff4 911 break;
wardm 12:046346a16ff4 912 }
wardm 12:046346a16ff4 913
wardm 12:046346a16ff4 914 this->settings.State = RF_RX_RUNNING;
wardm 12:046346a16ff4 915 if( timeout != 0 )
wardm 12:046346a16ff4 916 {
wardm 12:046346a16ff4 917 SetTimeout(RXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout * 1e3);
wardm 12:046346a16ff4 918 }
wardm 12:046346a16ff4 919
wardm 12:046346a16ff4 920 if( this->settings.Modem == MODEM_FSK )
wardm 12:046346a16ff4 921 {
wardm 12:046346a16ff4 922 SetOpMode( RF_OPMODE_RECEIVER );
wardm 12:046346a16ff4 923
wardm 12:046346a16ff4 924 if( rxContinuous == false )
wardm 12:046346a16ff4 925 {
wardm 12:046346a16ff4 926 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
wardm 12:046346a16ff4 927 }
wardm 12:046346a16ff4 928 }
wardm 12:046346a16ff4 929 else
wardm 12:046346a16ff4 930 {
wardm 12:046346a16ff4 931 if( rxContinuous == true )
wardm 12:046346a16ff4 932 {
wardm 12:046346a16ff4 933 SetOpMode( RFLR_OPMODE_RECEIVER );
wardm 12:046346a16ff4 934 }
wardm 12:046346a16ff4 935 else
wardm 12:046346a16ff4 936 {
wardm 12:046346a16ff4 937 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
wardm 12:046346a16ff4 938 }
wardm 12:046346a16ff4 939 }
wardm 12:046346a16ff4 940 }
wardm 12:046346a16ff4 941
wardm 12:046346a16ff4 942 bool SX1276::RxSignalPending()
wardm 12:046346a16ff4 943 {
wardm 12:046346a16ff4 944 if (this->settings.State != RF_RX_RUNNING)
wardm 12:046346a16ff4 945 return false;
wardm 12:046346a16ff4 946
wardm 12:046346a16ff4 947 switch( this->settings.Modem )
wardm 12:046346a16ff4 948 {
wardm 12:046346a16ff4 949 case MODEM_FSK:
wardm 12:046346a16ff4 950 break;
wardm 12:046346a16ff4 951 case MODEM_LORA:
wardm 12:046346a16ff4 952 if (Read(REG_LR_MODEMSTAT) & (RFLR_MODEMSTAT_SIGNAL_DETECTED|RFLR_MODEMSTAT_SIGNAL_SYNCRONIZED|RFLR_MODEMSTAT_HEADERINFO_VALID|RFLR_MODEMSTAT_MODEM_CLEAR))
wardm 12:046346a16ff4 953 return true;
wardm 12:046346a16ff4 954 break;
wardm 12:046346a16ff4 955 }
wardm 12:046346a16ff4 956 return false;
wardm 12:046346a16ff4 957 }
wardm 12:046346a16ff4 958
wardm 12:046346a16ff4 959 void SX1276::Tx( uint32_t timeout )
wardm 12:046346a16ff4 960 {
wardm 12:046346a16ff4 961
wardm 12:046346a16ff4 962 switch( this->settings.Modem )
wardm 12:046346a16ff4 963 {
wardm 12:046346a16ff4 964 case MODEM_FSK:
wardm 12:046346a16ff4 965 {
wardm 12:046346a16ff4 966 // DIO0=PacketSent
wardm 12:046346a16ff4 967 // DIO1=FifoEmpty
wardm 12:046346a16ff4 968 // DIO2=FifoFull
wardm 12:046346a16ff4 969 // DIO3=FifoEmpty
wardm 12:046346a16ff4 970 // DIO4=LowBat
wardm 12:046346a16ff4 971 // DIO5=ModeReady
wardm 12:046346a16ff4 972 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
wardm 12:046346a16ff4 973 RF_DIOMAPPING1_DIO1_MASK &
wardm 12:046346a16ff4 974 RF_DIOMAPPING1_DIO2_MASK ) |
wardm 12:046346a16ff4 975 RF_DIOMAPPING1_DIO1_01 );
wardm 12:046346a16ff4 976
wardm 12:046346a16ff4 977 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
wardm 12:046346a16ff4 978 RF_DIOMAPPING2_MAP_MASK ) );
wardm 12:046346a16ff4 979 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
wardm 12:046346a16ff4 980 }
wardm 12:046346a16ff4 981 break;
wardm 12:046346a16ff4 982 case MODEM_LORA:
wardm 12:046346a16ff4 983 {
wardm 12:046346a16ff4 984 if( this->settings.LoRa.FreqHopOn == true )
wardm 12:046346a16ff4 985 {
wardm 12:046346a16ff4 986 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
wardm 12:046346a16ff4 987 RFLR_IRQFLAGS_RXDONE |
wardm 12:046346a16ff4 988 RFLR_IRQFLAGS_PAYLOADCRCERROR |
wardm 12:046346a16ff4 989 RFLR_IRQFLAGS_VALIDHEADER |
wardm 12:046346a16ff4 990 //RFLR_IRQFLAGS_TXDONE |
wardm 12:046346a16ff4 991 RFLR_IRQFLAGS_CADDONE |
wardm 12:046346a16ff4 992 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
wardm 12:046346a16ff4 993 RFLR_IRQFLAGS_CADDETECTED );
wardm 12:046346a16ff4 994
wardm 12:046346a16ff4 995 // DIO0=TxDone, DIO2=FhssChangeChannel
wardm 12:046346a16ff4 996 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
wardm 12:046346a16ff4 997 }
wardm 12:046346a16ff4 998 else
wardm 12:046346a16ff4 999 {
wardm 12:046346a16ff4 1000 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
wardm 12:046346a16ff4 1001 RFLR_IRQFLAGS_RXDONE |
wardm 12:046346a16ff4 1002 RFLR_IRQFLAGS_PAYLOADCRCERROR |
wardm 12:046346a16ff4 1003 RFLR_IRQFLAGS_VALIDHEADER |
wardm 12:046346a16ff4 1004 //RFLR_IRQFLAGS_TXDONE |
wardm 12:046346a16ff4 1005 RFLR_IRQFLAGS_CADDONE |
wardm 12:046346a16ff4 1006 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
wardm 12:046346a16ff4 1007 RFLR_IRQFLAGS_CADDETECTED );
wardm 12:046346a16ff4 1008
wardm 12:046346a16ff4 1009 // DIO0=TxDone
wardm 12:046346a16ff4 1010 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
wardm 12:046346a16ff4 1011 }
wardm 12:046346a16ff4 1012 }
wardm 12:046346a16ff4 1013 break;
wardm 12:046346a16ff4 1014 }
wardm 12:046346a16ff4 1015
wardm 12:046346a16ff4 1016 this->settings.State = RF_TX_RUNNING;
wardm 12:046346a16ff4 1017 SetTimeout(TXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout * 1e3);
wardm 12:046346a16ff4 1018 SetOpMode( RF_OPMODE_TRANSMITTER );
wardm 12:046346a16ff4 1019 }
wardm 12:046346a16ff4 1020
wardm 12:046346a16ff4 1021 void SX1276::StartCad( void )
wardm 12:046346a16ff4 1022 {
wardm 12:046346a16ff4 1023 switch( this->settings.Modem )
wardm 12:046346a16ff4 1024 {
wardm 12:046346a16ff4 1025 case MODEM_FSK:
wardm 12:046346a16ff4 1026 {
wardm 12:046346a16ff4 1027
wardm 12:046346a16ff4 1028 }
wardm 12:046346a16ff4 1029 break;
wardm 12:046346a16ff4 1030 case MODEM_LORA:
wardm 12:046346a16ff4 1031 {
wardm 12:046346a16ff4 1032 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
wardm 12:046346a16ff4 1033 RFLR_IRQFLAGS_RXDONE |
wardm 12:046346a16ff4 1034 RFLR_IRQFLAGS_PAYLOADCRCERROR |
wardm 12:046346a16ff4 1035 RFLR_IRQFLAGS_VALIDHEADER |
wardm 12:046346a16ff4 1036 RFLR_IRQFLAGS_TXDONE |
wardm 12:046346a16ff4 1037 //RFLR_IRQFLAGS_CADDONE |
wardm 12:046346a16ff4 1038 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
wardm 12:046346a16ff4 1039 //RFLR_IRQFLAGS_CADDETECTED
wardm 12:046346a16ff4 1040 );
wardm 12:046346a16ff4 1041
wardm 12:046346a16ff4 1042 // DIO3=CADDone
wardm 12:046346a16ff4 1043 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
wardm 12:046346a16ff4 1044
wardm 12:046346a16ff4 1045 this->settings.State = RF_CAD;
wardm 12:046346a16ff4 1046 SetOpMode( RFLR_OPMODE_CAD );
wardm 12:046346a16ff4 1047 }
wardm 12:046346a16ff4 1048 break;
wardm 12:046346a16ff4 1049 default:
wardm 12:046346a16ff4 1050 break;
wardm 12:046346a16ff4 1051 }
wardm 12:046346a16ff4 1052 }
wardm 12:046346a16ff4 1053
wardm 12:046346a16ff4 1054 void SX1276::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
wardm 12:046346a16ff4 1055 {
wardm 12:046346a16ff4 1056 uint32_t timeout = ( uint32_t )( time * 1e6 );
wardm 12:046346a16ff4 1057
wardm 12:046346a16ff4 1058 SetChannel( freq );
wardm 12:046346a16ff4 1059
wardm 12:046346a16ff4 1060 SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
wardm 12:046346a16ff4 1061
wardm 12:046346a16ff4 1062 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
wardm 12:046346a16ff4 1063 // Disable radio interrupts
wardm 12:046346a16ff4 1064 Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
wardm 12:046346a16ff4 1065 Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
wardm 12:046346a16ff4 1066
wardm 12:046346a16ff4 1067 this->settings.State = RF_TX_RUNNING;
wardm 12:046346a16ff4 1068 SetTimeout(TXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout);
wardm 12:046346a16ff4 1069 SetOpMode( RF_OPMODE_TRANSMITTER );
wardm 12:046346a16ff4 1070 }
wardm 12:046346a16ff4 1071
wardm 12:046346a16ff4 1072 int16_t SX1276::MaxMTUSize( RadioModems_t modem )
wardm 12:046346a16ff4 1073 {
wardm 12:046346a16ff4 1074 int16_t mtuSize = 0;
wardm 12:046346a16ff4 1075
wardm 12:046346a16ff4 1076 switch( modem )
wardm 12:046346a16ff4 1077 {
wardm 12:046346a16ff4 1078 case MODEM_FSK:
wardm 12:046346a16ff4 1079 mtuSize = RX_BUFFER_SIZE;
wardm 12:046346a16ff4 1080 case MODEM_LORA:
wardm 12:046346a16ff4 1081 mtuSize = RX_BUFFER_SIZE;
wardm 12:046346a16ff4 1082 break;
wardm 12:046346a16ff4 1083 default:
wardm 12:046346a16ff4 1084 mtuSize = -1;
wardm 12:046346a16ff4 1085 break;
wardm 12:046346a16ff4 1086 }
wardm 12:046346a16ff4 1087 return mtuSize;
wardm 12:046346a16ff4 1088 }
wardm 12:046346a16ff4 1089
wardm 12:046346a16ff4 1090 int16_t SX1276::GetRssi( RadioModems_t modem )
wardm 12:046346a16ff4 1091 {
wardm 12:046346a16ff4 1092 int16_t rssi = 0;
wardm 12:046346a16ff4 1093
wardm 12:046346a16ff4 1094 switch( modem )
wardm 12:046346a16ff4 1095 {
wardm 12:046346a16ff4 1096 case MODEM_FSK:
wardm 12:046346a16ff4 1097 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
wardm 12:046346a16ff4 1098 break;
wardm 12:046346a16ff4 1099 case MODEM_LORA:
wardm 12:046346a16ff4 1100 if( this->settings.Channel > RF_MID_BAND_THRESH )
wardm 12:046346a16ff4 1101 {
wardm 12:046346a16ff4 1102 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
wardm 12:046346a16ff4 1103 }
wardm 12:046346a16ff4 1104 else
wardm 12:046346a16ff4 1105 {
wardm 12:046346a16ff4 1106 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
wardm 12:046346a16ff4 1107 }
wardm 12:046346a16ff4 1108 break;
wardm 12:046346a16ff4 1109 default:
wardm 12:046346a16ff4 1110 rssi = -1;
wardm 12:046346a16ff4 1111 break;
wardm 12:046346a16ff4 1112 }
wardm 12:046346a16ff4 1113 return rssi;
wardm 12:046346a16ff4 1114 }
wardm 12:046346a16ff4 1115
wardm 12:046346a16ff4 1116 int32_t SX1276::GetFrequencyError(RadioModems_t modem )
wardm 12:046346a16ff4 1117 {
wardm 12:046346a16ff4 1118 int32_t val = 0;
wardm 12:046346a16ff4 1119
wardm 12:046346a16ff4 1120 if (modem != MODEM_LORA)
wardm 12:046346a16ff4 1121 return 0;
wardm 12:046346a16ff4 1122
wardm 12:046346a16ff4 1123 val = (Read(REG_LR_FEIMSB) & 0b1111) << 16; // high word, 4 valid bits only
wardm 12:046346a16ff4 1124 val |= (Read(REG_LR_FEIMID) << 8) | Read(REG_LR_FEILSB); // high byte, low byte
wardm 12:046346a16ff4 1125 if (val & 0x8000) //sconvert ign bit
wardm 12:046346a16ff4 1126 val |= 0xfff00000;
wardm 12:046346a16ff4 1127
wardm 12:046346a16ff4 1128 int32_t bandwidth = 0;
wardm 12:046346a16ff4 1129 for (int i = 0; i < (int)(sizeof(LoRaBandwidths) / sizeof(BandwidthMap)) -1; i++ ) {
wardm 12:046346a16ff4 1130 if (LoRaBandwidths[i].RegValue == this->settings.LoRa.Bandwidth) {
wardm 12:046346a16ff4 1131 bandwidth = LoRaBandwidths[i].bandwidth;
wardm 12:046346a16ff4 1132 break;
wardm 12:046346a16ff4 1133 }
wardm 12:046346a16ff4 1134 }
wardm 12:046346a16ff4 1135 if (!bandwidth)
wardm 12:046346a16ff4 1136 return 0;
wardm 12:046346a16ff4 1137
wardm 12:046346a16ff4 1138 float bandWidthkHz = (float)bandwidth/1000;
wardm 12:046346a16ff4 1139
wardm 12:046346a16ff4 1140 int32_t hz = (((float)val * (float)(1<<24)) / ((float)XTAL_FREQ)) * (bandWidthkHz / 500.0);
wardm 12:046346a16ff4 1141
wardm 12:046346a16ff4 1142 return hz;
wardm 12:046346a16ff4 1143 }
wardm 12:046346a16ff4 1144
wardm 12:046346a16ff4 1145
wardm 12:046346a16ff4 1146 void SX1276::SetOpMode( uint8_t opMode )
wardm 12:046346a16ff4 1147 {
wardm 12:046346a16ff4 1148 if( opMode == RF_OPMODE_SLEEP )
wardm 12:046346a16ff4 1149 {
wardm 12:046346a16ff4 1150 SetAntSwLowPower( true );
wardm 12:046346a16ff4 1151 }
wardm 12:046346a16ff4 1152 else
wardm 12:046346a16ff4 1153 {
wardm 12:046346a16ff4 1154 SetAntSwLowPower( false );
wardm 12:046346a16ff4 1155 SetAntSw( opMode );
wardm 12:046346a16ff4 1156 }
wardm 12:046346a16ff4 1157 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
wardm 12:046346a16ff4 1158 }
wardm 12:046346a16ff4 1159
wardm 12:046346a16ff4 1160 void SX1276::SetModem( RadioModems_t modem )
wardm 12:046346a16ff4 1161 {
wardm 12:046346a16ff4 1162 if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 )
wardm 12:046346a16ff4 1163 {
wardm 12:046346a16ff4 1164 this->settings.Modem = MODEM_LORA;
wardm 12:046346a16ff4 1165 }
wardm 12:046346a16ff4 1166 else
wardm 12:046346a16ff4 1167 {
wardm 12:046346a16ff4 1168 this->settings.Modem = MODEM_FSK;
wardm 12:046346a16ff4 1169 }
wardm 12:046346a16ff4 1170
wardm 12:046346a16ff4 1171 if( this->settings.Modem == modem )
wardm 12:046346a16ff4 1172 {
wardm 12:046346a16ff4 1173 return;
wardm 12:046346a16ff4 1174 }
wardm 12:046346a16ff4 1175
wardm 12:046346a16ff4 1176 this->settings.Modem = modem;
wardm 12:046346a16ff4 1177 switch( this->settings.Modem )
wardm 12:046346a16ff4 1178 {
wardm 12:046346a16ff4 1179 default:
wardm 12:046346a16ff4 1180 case MODEM_FSK:
wardm 12:046346a16ff4 1181 Sleep( );
wardm 12:046346a16ff4 1182 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
wardm 12:046346a16ff4 1183
wardm 12:046346a16ff4 1184 Write( REG_DIOMAPPING1, 0x00 );
wardm 12:046346a16ff4 1185 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
wardm 12:046346a16ff4 1186 break;
wardm 12:046346a16ff4 1187 case MODEM_LORA:
wardm 12:046346a16ff4 1188 Sleep( );
wardm 12:046346a16ff4 1189 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
wardm 12:046346a16ff4 1190
wardm 12:046346a16ff4 1191 Write( REG_DIOMAPPING1, 0x00 );
wardm 12:046346a16ff4 1192 Write( REG_DIOMAPPING2, 0x00 );
wardm 12:046346a16ff4 1193 break;
wardm 12:046346a16ff4 1194 }
wardm 12:046346a16ff4 1195 }
wardm 12:046346a16ff4 1196
wardm 12:046346a16ff4 1197 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
wardm 12:046346a16ff4 1198 {
wardm 12:046346a16ff4 1199 this->SetModem( modem );
wardm 12:046346a16ff4 1200
wardm 12:046346a16ff4 1201 switch( modem )
wardm 12:046346a16ff4 1202 {
wardm 12:046346a16ff4 1203 case MODEM_FSK:
wardm 12:046346a16ff4 1204 if( this->settings.Fsk.FixLen == false )
wardm 12:046346a16ff4 1205 {
wardm 12:046346a16ff4 1206 this->Write( REG_PAYLOADLENGTH, max );
wardm 12:046346a16ff4 1207 }
wardm 12:046346a16ff4 1208 break;
wardm 12:046346a16ff4 1209 case MODEM_LORA:
wardm 12:046346a16ff4 1210 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
wardm 12:046346a16ff4 1211 break;
wardm 12:046346a16ff4 1212 }
wardm 12:046346a16ff4 1213 }
wardm 12:046346a16ff4 1214
wardm 12:046346a16ff4 1215 void SX1276::SetPublicNetwork( bool enable )
wardm 12:046346a16ff4 1216 {
wardm 12:046346a16ff4 1217 SetModem( MODEM_LORA );
wardm 12:046346a16ff4 1218 this->settings.LoRa.PublicNetwork = enable;
wardm 12:046346a16ff4 1219 if( enable == true )
wardm 12:046346a16ff4 1220 {
wardm 12:046346a16ff4 1221 // Change LoRa modem SyncWord
wardm 12:046346a16ff4 1222 Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD );
wardm 12:046346a16ff4 1223 }
wardm 12:046346a16ff4 1224 else
wardm 12:046346a16ff4 1225 {
wardm 12:046346a16ff4 1226 // Change LoRa modem SyncWord
wardm 12:046346a16ff4 1227 Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD );
wardm 12:046346a16ff4 1228 }
wardm 12:046346a16ff4 1229 }
wardm 12:046346a16ff4 1230
wardm 12:046346a16ff4 1231
wardm 12:046346a16ff4 1232 void SX1276::OnTimeoutIrq( void )
wardm 12:046346a16ff4 1233 {
wardm 12:046346a16ff4 1234 switch( this->settings.State )
wardm 12:046346a16ff4 1235 {
wardm 12:046346a16ff4 1236 case RF_RX_RUNNING:
wardm 12:046346a16ff4 1237 if( this->settings.Modem == MODEM_FSK )
wardm 12:046346a16ff4 1238 {
wardm 12:046346a16ff4 1239 this->settings.FskPacketHandler.PreambleDetected = false;
wardm 12:046346a16ff4 1240 this->settings.FskPacketHandler.SyncWordDetected = false;
wardm 12:046346a16ff4 1241 this->settings.FskPacketHandler.NbBytes = 0;
wardm 12:046346a16ff4 1242 this->settings.FskPacketHandler.Size = 0;
wardm 12:046346a16ff4 1243
wardm 12:046346a16ff4 1244 // Clear Irqs
wardm 12:046346a16ff4 1245 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
wardm 12:046346a16ff4 1246 RF_IRQFLAGS1_PREAMBLEDETECT |
wardm 12:046346a16ff4 1247 RF_IRQFLAGS1_SYNCADDRESSMATCH );
wardm 12:046346a16ff4 1248 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
wardm 12:046346a16ff4 1249
wardm 12:046346a16ff4 1250 if( this->settings.Fsk.RxContinuous == true )
wardm 12:046346a16ff4 1251 {
wardm 12:046346a16ff4 1252 // Continuous mode restart Rx chain
wardm 12:046346a16ff4 1253 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
wardm 12:046346a16ff4 1254 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
wardm 12:046346a16ff4 1255 }
wardm 12:046346a16ff4 1256 else
wardm 12:046346a16ff4 1257 {
wardm 12:046346a16ff4 1258 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 1259 SetTimeout(RXTimeoutSyncWordTimer, NULL);
wardm 12:046346a16ff4 1260 }
wardm 12:046346a16ff4 1261 }
wardm 12:046346a16ff4 1262 if (this->RadioEvents && this->RadioEvents->RxTimeout)
wardm 12:046346a16ff4 1263 {
wardm 12:046346a16ff4 1264 this->RadioEvents->RxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
wardm 12:046346a16ff4 1265 }
wardm 12:046346a16ff4 1266 break;
wardm 12:046346a16ff4 1267 case RF_TX_RUNNING:
wardm 12:046346a16ff4 1268 // Tx timeout shouldn't happen.
wardm 12:046346a16ff4 1269 // But it has been observed that when it happens it is a result of a corrupted SPI transfer
wardm 12:046346a16ff4 1270 // it depends on the platform design.
wardm 12:046346a16ff4 1271 //
wardm 12:046346a16ff4 1272 // The workaround is to put the radio in a known state. Thus, we re-initialize it.
wardm 12:046346a16ff4 1273 // BEGIN WORKAROUND
wardm 12:046346a16ff4 1274
wardm 12:046346a16ff4 1275 // Reset the radio
wardm 12:046346a16ff4 1276 Reset( );
wardm 12:046346a16ff4 1277
wardm 12:046346a16ff4 1278 // Calibrate Rx chain
wardm 12:046346a16ff4 1279 RxChainCalibration( );
wardm 12:046346a16ff4 1280
wardm 12:046346a16ff4 1281 // Initialize radio default values
wardm 12:046346a16ff4 1282 SetOpMode( RF_OPMODE_SLEEP );
wardm 12:046346a16ff4 1283
wardm 12:046346a16ff4 1284 RadioRegistersInit( );
wardm 12:046346a16ff4 1285
wardm 12:046346a16ff4 1286 SetModem( MODEM_FSK );
wardm 12:046346a16ff4 1287
wardm 12:046346a16ff4 1288 // Restore previous network type setting.
wardm 12:046346a16ff4 1289 SetPublicNetwork( this->settings.LoRa.PublicNetwork );
wardm 12:046346a16ff4 1290 // END WORKAROUND
wardm 12:046346a16ff4 1291
wardm 12:046346a16ff4 1292 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 1293 if (this->RadioEvents && this->RadioEvents->TxTimeout)
wardm 12:046346a16ff4 1294 {
wardm 12:046346a16ff4 1295 this->RadioEvents->TxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
wardm 12:046346a16ff4 1296 }
wardm 12:046346a16ff4 1297 break;
wardm 12:046346a16ff4 1298 default:
wardm 12:046346a16ff4 1299 break;
wardm 12:046346a16ff4 1300 }
wardm 12:046346a16ff4 1301 }
wardm 12:046346a16ff4 1302
wardm 12:046346a16ff4 1303 void SX1276::OnDio0Irq( void )
wardm 12:046346a16ff4 1304 {
wardm 12:046346a16ff4 1305 volatile uint8_t irqFlags = 0;
wardm 12:046346a16ff4 1306
wardm 12:046346a16ff4 1307 switch( this->settings.State )
wardm 12:046346a16ff4 1308 {
wardm 12:046346a16ff4 1309 case RF_RX_RUNNING:
wardm 12:046346a16ff4 1310 //TimerStop( &RxTimeoutTimer );
wardm 12:046346a16ff4 1311 // RxDone interrupt
wardm 12:046346a16ff4 1312 switch( this->settings.Modem )
wardm 12:046346a16ff4 1313 {
wardm 12:046346a16ff4 1314 case MODEM_FSK:
wardm 12:046346a16ff4 1315 if( this->settings.Fsk.CrcOn == true )
wardm 12:046346a16ff4 1316 {
wardm 12:046346a16ff4 1317 irqFlags = Read( REG_IRQFLAGS2 );
wardm 12:046346a16ff4 1318 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
wardm 12:046346a16ff4 1319 {
wardm 12:046346a16ff4 1320 // Clear Irqs
wardm 12:046346a16ff4 1321 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
wardm 12:046346a16ff4 1322 RF_IRQFLAGS1_PREAMBLEDETECT |
wardm 12:046346a16ff4 1323 RF_IRQFLAGS1_SYNCADDRESSMATCH );
wardm 12:046346a16ff4 1324 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
wardm 12:046346a16ff4 1325
wardm 12:046346a16ff4 1326 SetTimeout(RXTimeoutTimer, NULL);
wardm 12:046346a16ff4 1327
wardm 12:046346a16ff4 1328 if( this->settings.Fsk.RxContinuous == false )
wardm 12:046346a16ff4 1329 {
wardm 12:046346a16ff4 1330 SetTimeout(RXTimeoutSyncWordTimer, NULL);
wardm 12:046346a16ff4 1331 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 1332 }
wardm 12:046346a16ff4 1333 else
wardm 12:046346a16ff4 1334 {
wardm 12:046346a16ff4 1335 // Continuous mode restart Rx chain
wardm 12:046346a16ff4 1336 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
wardm 12:046346a16ff4 1337 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
wardm 12:046346a16ff4 1338 }
wardm 12:046346a16ff4 1339
wardm 12:046346a16ff4 1340 if (this->RadioEvents && this->RadioEvents->RxError)
wardm 12:046346a16ff4 1341 {
wardm 12:046346a16ff4 1342 this->RadioEvents->RxError(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
wardm 12:046346a16ff4 1343 }
wardm 12:046346a16ff4 1344 this->settings.FskPacketHandler.PreambleDetected = false;
wardm 12:046346a16ff4 1345 this->settings.FskPacketHandler.SyncWordDetected = false;
wardm 12:046346a16ff4 1346 this->settings.FskPacketHandler.NbBytes = 0;
wardm 12:046346a16ff4 1347 this->settings.FskPacketHandler.Size = 0;
wardm 12:046346a16ff4 1348 break;
wardm 12:046346a16ff4 1349 }
wardm 12:046346a16ff4 1350 }
wardm 12:046346a16ff4 1351
wardm 12:046346a16ff4 1352 // Read received packet size
wardm 12:046346a16ff4 1353 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
wardm 12:046346a16ff4 1354 {
wardm 12:046346a16ff4 1355 if( this->settings.Fsk.FixLen == false )
wardm 12:046346a16ff4 1356 {
wardm 12:046346a16ff4 1357 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
wardm 12:046346a16ff4 1358 }
wardm 12:046346a16ff4 1359 else
wardm 12:046346a16ff4 1360 {
wardm 12:046346a16ff4 1361 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
wardm 12:046346a16ff4 1362 }
wardm 12:046346a16ff4 1363 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
wardm 12:046346a16ff4 1364 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
wardm 12:046346a16ff4 1365 }
wardm 12:046346a16ff4 1366 else
wardm 12:046346a16ff4 1367 {
wardm 12:046346a16ff4 1368 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
wardm 12:046346a16ff4 1369 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
wardm 12:046346a16ff4 1370 }
wardm 12:046346a16ff4 1371
wardm 12:046346a16ff4 1372 SetTimeout(RXTimeoutTimer, NULL);
wardm 12:046346a16ff4 1373
wardm 12:046346a16ff4 1374 if( this->settings.Fsk.RxContinuous == false )
wardm 12:046346a16ff4 1375 {
wardm 12:046346a16ff4 1376 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 1377 SetTimeout(RXTimeoutSyncWordTimer, NULL);
wardm 12:046346a16ff4 1378 }
wardm 12:046346a16ff4 1379 else
wardm 12:046346a16ff4 1380 {
wardm 12:046346a16ff4 1381 // Continuous mode restart Rx chain
wardm 12:046346a16ff4 1382 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
wardm 12:046346a16ff4 1383 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
wardm 12:046346a16ff4 1384 }
wardm 12:046346a16ff4 1385
wardm 12:046346a16ff4 1386 if (this->RadioEvents && this->RadioEvents->RxDone)
wardm 12:046346a16ff4 1387 {
wardm 12:046346a16ff4 1388 this->RadioEvents->RxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
wardm 12:046346a16ff4 1389 }
wardm 12:046346a16ff4 1390 this->settings.FskPacketHandler.PreambleDetected = false;
wardm 12:046346a16ff4 1391 this->settings.FskPacketHandler.SyncWordDetected = false;
wardm 12:046346a16ff4 1392 this->settings.FskPacketHandler.NbBytes = 0;
wardm 12:046346a16ff4 1393 this->settings.FskPacketHandler.Size = 0;
wardm 12:046346a16ff4 1394 break;
wardm 12:046346a16ff4 1395 case MODEM_LORA:
wardm 12:046346a16ff4 1396 {
wardm 12:046346a16ff4 1397 int8_t snr = 0;
wardm 12:046346a16ff4 1398
wardm 12:046346a16ff4 1399 // Clear Irq
wardm 12:046346a16ff4 1400 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
wardm 12:046346a16ff4 1401
wardm 12:046346a16ff4 1402 irqFlags = Read( REG_LR_IRQFLAGS );
wardm 12:046346a16ff4 1403 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
wardm 12:046346a16ff4 1404 {
wardm 12:046346a16ff4 1405 // Clear Irq
wardm 12:046346a16ff4 1406 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
wardm 12:046346a16ff4 1407
wardm 12:046346a16ff4 1408 if( this->settings.LoRa.RxContinuous == false )
wardm 12:046346a16ff4 1409 {
wardm 12:046346a16ff4 1410 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 1411 }
wardm 12:046346a16ff4 1412 SetTimeout(RXTimeoutTimer, NULL);
wardm 12:046346a16ff4 1413
wardm 12:046346a16ff4 1414 if(this->RadioEvents && this->RadioEvents->RxError)
wardm 12:046346a16ff4 1415 {
wardm 12:046346a16ff4 1416 this->RadioEvents->RxError(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
wardm 12:046346a16ff4 1417 }
wardm 12:046346a16ff4 1418 break;
wardm 12:046346a16ff4 1419 }
wardm 12:046346a16ff4 1420
wardm 12:046346a16ff4 1421 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
wardm 12:046346a16ff4 1422 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
wardm 12:046346a16ff4 1423 {
wardm 12:046346a16ff4 1424 // Invert and divide by 4
wardm 12:046346a16ff4 1425 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
wardm 12:046346a16ff4 1426 snr = -snr;
wardm 12:046346a16ff4 1427 }
wardm 12:046346a16ff4 1428 else
wardm 12:046346a16ff4 1429 {
wardm 12:046346a16ff4 1430 // Divide by 4
wardm 12:046346a16ff4 1431 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
wardm 12:046346a16ff4 1432 }
wardm 12:046346a16ff4 1433
wardm 12:046346a16ff4 1434 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
wardm 12:046346a16ff4 1435 if( snr < 0 )
wardm 12:046346a16ff4 1436 {
wardm 12:046346a16ff4 1437 if( this->settings.Channel > RF_MID_BAND_THRESH )
wardm 12:046346a16ff4 1438 {
wardm 12:046346a16ff4 1439 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
wardm 12:046346a16ff4 1440 snr;
wardm 12:046346a16ff4 1441 }
wardm 12:046346a16ff4 1442 else
wardm 12:046346a16ff4 1443 {
wardm 12:046346a16ff4 1444 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
wardm 12:046346a16ff4 1445 snr;
wardm 12:046346a16ff4 1446 }
wardm 12:046346a16ff4 1447 }
wardm 12:046346a16ff4 1448 else
wardm 12:046346a16ff4 1449 {
wardm 12:046346a16ff4 1450 if( this->settings.Channel > RF_MID_BAND_THRESH )
wardm 12:046346a16ff4 1451 {
wardm 12:046346a16ff4 1452 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
wardm 12:046346a16ff4 1453 }
wardm 12:046346a16ff4 1454 else
wardm 12:046346a16ff4 1455 {
wardm 12:046346a16ff4 1456 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
wardm 12:046346a16ff4 1457 }
wardm 12:046346a16ff4 1458 }
wardm 12:046346a16ff4 1459
wardm 12:046346a16ff4 1460 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
wardm 12:046346a16ff4 1461 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
wardm 12:046346a16ff4 1462
wardm 12:046346a16ff4 1463 if( this->settings.LoRa.RxContinuous == false )
wardm 12:046346a16ff4 1464 {
wardm 12:046346a16ff4 1465 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 1466 }
wardm 12:046346a16ff4 1467 SetTimeout(RXTimeoutTimer, NULL);
wardm 12:046346a16ff4 1468
wardm 12:046346a16ff4 1469 if(this->RadioEvents && this->RadioEvents->RxDone)
wardm 12:046346a16ff4 1470 {
wardm 12:046346a16ff4 1471 this->RadioEvents->RxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
wardm 12:046346a16ff4 1472 }
wardm 12:046346a16ff4 1473 }
wardm 12:046346a16ff4 1474 break;
wardm 12:046346a16ff4 1475 default:
wardm 12:046346a16ff4 1476 break;
wardm 12:046346a16ff4 1477 }
wardm 12:046346a16ff4 1478 break;
wardm 12:046346a16ff4 1479 case RF_TX_RUNNING:
wardm 12:046346a16ff4 1480 SetTimeout(TXTimeoutTimer, NULL);
wardm 12:046346a16ff4 1481 // TxDone interrupt
wardm 12:046346a16ff4 1482 switch( this->settings.Modem )
wardm 12:046346a16ff4 1483 {
wardm 12:046346a16ff4 1484 case MODEM_LORA:
wardm 12:046346a16ff4 1485 // Clear Irq
wardm 12:046346a16ff4 1486 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
wardm 12:046346a16ff4 1487 // Intentional fall through
wardm 12:046346a16ff4 1488 case MODEM_FSK:
wardm 12:046346a16ff4 1489 default:
wardm 12:046346a16ff4 1490 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 1491 if (this->RadioEvents && this->RadioEvents->TxDone)
wardm 12:046346a16ff4 1492 {
wardm 12:046346a16ff4 1493 this->RadioEvents->TxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
wardm 12:046346a16ff4 1494 }
wardm 12:046346a16ff4 1495 break;
wardm 12:046346a16ff4 1496 }
wardm 12:046346a16ff4 1497 break;
wardm 12:046346a16ff4 1498 default:
wardm 12:046346a16ff4 1499 break;
wardm 12:046346a16ff4 1500 }
wardm 12:046346a16ff4 1501 }
wardm 12:046346a16ff4 1502
wardm 12:046346a16ff4 1503 void SX1276::OnDio1Irq( void )
wardm 12:046346a16ff4 1504 {
wardm 12:046346a16ff4 1505 switch( this->settings.State )
wardm 12:046346a16ff4 1506 {
wardm 12:046346a16ff4 1507 case RF_RX_RUNNING:
wardm 12:046346a16ff4 1508 switch( this->settings.Modem )
wardm 12:046346a16ff4 1509 {
wardm 12:046346a16ff4 1510 case MODEM_FSK:
wardm 12:046346a16ff4 1511 // FifoLevel interrupt
wardm 12:046346a16ff4 1512 // Read received packet size
wardm 12:046346a16ff4 1513 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
wardm 12:046346a16ff4 1514 {
wardm 12:046346a16ff4 1515 if( this->settings.Fsk.FixLen == false )
wardm 12:046346a16ff4 1516 {
wardm 12:046346a16ff4 1517 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
wardm 12:046346a16ff4 1518 }
wardm 12:046346a16ff4 1519 else
wardm 12:046346a16ff4 1520 {
wardm 12:046346a16ff4 1521 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
wardm 12:046346a16ff4 1522 }
wardm 12:046346a16ff4 1523 }
wardm 12:046346a16ff4 1524
wardm 12:046346a16ff4 1525 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
wardm 12:046346a16ff4 1526 {
wardm 12:046346a16ff4 1527 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
wardm 12:046346a16ff4 1528 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
wardm 12:046346a16ff4 1529 }
wardm 12:046346a16ff4 1530 else
wardm 12:046346a16ff4 1531 {
wardm 12:046346a16ff4 1532 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
wardm 12:046346a16ff4 1533 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
wardm 12:046346a16ff4 1534 }
wardm 12:046346a16ff4 1535 break;
wardm 12:046346a16ff4 1536 case MODEM_LORA:
wardm 12:046346a16ff4 1537 // Sync time out
wardm 12:046346a16ff4 1538 SetTimeout(RXTimeoutTimer, NULL);
wardm 12:046346a16ff4 1539 // Clear Irq
wardm 12:046346a16ff4 1540 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
wardm 12:046346a16ff4 1541
wardm 12:046346a16ff4 1542 this->settings.State = RF_IDLE;
wardm 12:046346a16ff4 1543 if (this->RadioEvents && this->RadioEvents->RxTimeout)
wardm 12:046346a16ff4 1544 {
wardm 12:046346a16ff4 1545 this->RadioEvents->RxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
wardm 12:046346a16ff4 1546 }
wardm 12:046346a16ff4 1547 break;
wardm 12:046346a16ff4 1548 default:
wardm 12:046346a16ff4 1549 break;
wardm 12:046346a16ff4 1550 }
wardm 12:046346a16ff4 1551 break;
wardm 12:046346a16ff4 1552 case RF_TX_RUNNING:
wardm 12:046346a16ff4 1553 switch( this->settings.Modem )
wardm 12:046346a16ff4 1554 {
wardm 12:046346a16ff4 1555 case MODEM_FSK:
wardm 12:046346a16ff4 1556 // FifoEmpty interrupt
wardm 12:046346a16ff4 1557 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
wardm 12:046346a16ff4 1558 {
wardm 12:046346a16ff4 1559 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
wardm 12:046346a16ff4 1560 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
wardm 12:046346a16ff4 1561 }
wardm 12:046346a16ff4 1562 else
wardm 12:046346a16ff4 1563 {
wardm 12:046346a16ff4 1564 // Write the last chunk of data
wardm 12:046346a16ff4 1565 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
wardm 12:046346a16ff4 1566 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
wardm 12:046346a16ff4 1567 }
wardm 12:046346a16ff4 1568 break;
wardm 12:046346a16ff4 1569 case MODEM_LORA:
wardm 12:046346a16ff4 1570 break;
wardm 12:046346a16ff4 1571 default:
wardm 12:046346a16ff4 1572 break;
wardm 12:046346a16ff4 1573 }
wardm 12:046346a16ff4 1574 break;
wardm 12:046346a16ff4 1575 default:
wardm 12:046346a16ff4 1576 break;
wardm 12:046346a16ff4 1577 }
wardm 12:046346a16ff4 1578 }
wardm 12:046346a16ff4 1579
wardm 12:046346a16ff4 1580 void SX1276::OnDio2Irq( void )
wardm 12:046346a16ff4 1581 {
wardm 12:046346a16ff4 1582 switch( this->settings.State )
wardm 12:046346a16ff4 1583 {
wardm 12:046346a16ff4 1584 case RF_RX_RUNNING:
wardm 12:046346a16ff4 1585 switch( this->settings.Modem )
wardm 12:046346a16ff4 1586 {
wardm 12:046346a16ff4 1587 case MODEM_FSK:
wardm 12:046346a16ff4 1588 // Checks if DIO4 is connected. If it is not PreambleDtected is set to true.
wardm 12:046346a16ff4 1589 if( this->dioIrq[4] == NULL )
wardm 12:046346a16ff4 1590 {
wardm 12:046346a16ff4 1591 this->settings.FskPacketHandler.PreambleDetected = true;
wardm 12:046346a16ff4 1592 }
wardm 12:046346a16ff4 1593
wardm 12:046346a16ff4 1594 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
wardm 12:046346a16ff4 1595 {
wardm 12:046346a16ff4 1596 SetTimeout(RXTimeoutSyncWordTimer, NULL);
wardm 12:046346a16ff4 1597
wardm 12:046346a16ff4 1598 this->settings.FskPacketHandler.SyncWordDetected = true;
wardm 12:046346a16ff4 1599
wardm 12:046346a16ff4 1600 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
wardm 12:046346a16ff4 1601
wardm 12:046346a16ff4 1602 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
wardm 12:046346a16ff4 1603 ( uint16_t )Read( REG_AFCLSB ) ) *
wardm 12:046346a16ff4 1604 ( double )FREQ_STEP;
wardm 12:046346a16ff4 1605 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
wardm 12:046346a16ff4 1606 }
wardm 12:046346a16ff4 1607 break;
wardm 12:046346a16ff4 1608 case MODEM_LORA:
wardm 12:046346a16ff4 1609 if( this->settings.LoRa.FreqHopOn == true )
wardm 12:046346a16ff4 1610 {
wardm 12:046346a16ff4 1611 // Clear Irq
wardm 12:046346a16ff4 1612 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
wardm 12:046346a16ff4 1613
wardm 12:046346a16ff4 1614 if (this->RadioEvents && this->RadioEvents->FhssChangeChannel)
wardm 12:046346a16ff4 1615 {
wardm 12:046346a16ff4 1616 this->RadioEvents->FhssChangeChannel(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
wardm 12:046346a16ff4 1617 }
wardm 12:046346a16ff4 1618 }
wardm 12:046346a16ff4 1619 break;
wardm 12:046346a16ff4 1620 default:
wardm 12:046346a16ff4 1621 break;
wardm 12:046346a16ff4 1622 }
wardm 12:046346a16ff4 1623 break;
wardm 12:046346a16ff4 1624 case RF_TX_RUNNING:
wardm 12:046346a16ff4 1625 switch( this->settings.Modem )
wardm 12:046346a16ff4 1626 {
wardm 12:046346a16ff4 1627 case MODEM_FSK:
wardm 12:046346a16ff4 1628 break;
wardm 12:046346a16ff4 1629 case MODEM_LORA:
wardm 12:046346a16ff4 1630 if( this->settings.LoRa.FreqHopOn == true )
wardm 12:046346a16ff4 1631 {
wardm 12:046346a16ff4 1632 // Clear Irq
wardm 12:046346a16ff4 1633 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
wardm 12:046346a16ff4 1634
wardm 12:046346a16ff4 1635 if (this->RadioEvents && this->RadioEvents->FhssChangeChannel)
wardm 12:046346a16ff4 1636 {
wardm 12:046346a16ff4 1637 this->RadioEvents->FhssChangeChannel(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
wardm 12:046346a16ff4 1638 }
wardm 12:046346a16ff4 1639 }
wardm 12:046346a16ff4 1640 break;
wardm 12:046346a16ff4 1641 default:
wardm 12:046346a16ff4 1642 break;
wardm 12:046346a16ff4 1643 }
wardm 12:046346a16ff4 1644 break;
wardm 12:046346a16ff4 1645 default:
wardm 12:046346a16ff4 1646 break;
wardm 12:046346a16ff4 1647 }
wardm 12:046346a16ff4 1648 }
wardm 12:046346a16ff4 1649
wardm 12:046346a16ff4 1650 void SX1276::OnDio3Irq( void )
wardm 12:046346a16ff4 1651 {
wardm 12:046346a16ff4 1652 switch( this->settings.Modem )
wardm 12:046346a16ff4 1653 {
wardm 12:046346a16ff4 1654 case MODEM_FSK:
wardm 12:046346a16ff4 1655 break;
wardm 12:046346a16ff4 1656 case MODEM_LORA:
wardm 12:046346a16ff4 1657 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
wardm 12:046346a16ff4 1658 {
wardm 12:046346a16ff4 1659 // Clear Irq
wardm 12:046346a16ff4 1660 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
wardm 12:046346a16ff4 1661 if (this->RadioEvents && this->RadioEvents->CadDone)
wardm 12:046346a16ff4 1662 {
wardm 12:046346a16ff4 1663 this->RadioEvents->CadDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, true );
wardm 12:046346a16ff4 1664 }
wardm 12:046346a16ff4 1665 }
wardm 12:046346a16ff4 1666 else
wardm 12:046346a16ff4 1667 {
wardm 12:046346a16ff4 1668 // Clear Irq
wardm 12:046346a16ff4 1669 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
wardm 12:046346a16ff4 1670 if (this->RadioEvents && this->RadioEvents->CadDone)
wardm 12:046346a16ff4 1671 {
wardm 12:046346a16ff4 1672 this->RadioEvents->CadDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, false );
wardm 12:046346a16ff4 1673 }
wardm 12:046346a16ff4 1674 }
wardm 12:046346a16ff4 1675 break;
wardm 12:046346a16ff4 1676 default:
wardm 12:046346a16ff4 1677 break;
wardm 12:046346a16ff4 1678 }
wardm 12:046346a16ff4 1679 }
wardm 12:046346a16ff4 1680
wardm 12:046346a16ff4 1681 void SX1276::OnDio4Irq( void )
wardm 12:046346a16ff4 1682 {
wardm 12:046346a16ff4 1683 switch( this->settings.Modem )
wardm 12:046346a16ff4 1684 {
wardm 12:046346a16ff4 1685 case MODEM_FSK:
wardm 12:046346a16ff4 1686 {
wardm 12:046346a16ff4 1687 if( this->settings.FskPacketHandler.PreambleDetected == false )
wardm 12:046346a16ff4 1688 {
wardm 12:046346a16ff4 1689 this->settings.FskPacketHandler.PreambleDetected = true;
wardm 12:046346a16ff4 1690 }
wardm 12:046346a16ff4 1691 }
wardm 12:046346a16ff4 1692 break;
wardm 12:046346a16ff4 1693 case MODEM_LORA:
wardm 12:046346a16ff4 1694 break;
wardm 12:046346a16ff4 1695 default:
wardm 12:046346a16ff4 1696 break;
wardm 12:046346a16ff4 1697 }
wardm 12:046346a16ff4 1698 }
wardm 12:046346a16ff4 1699
wardm 12:046346a16ff4 1700 void SX1276::OnDio5Irq( void )
wardm 12:046346a16ff4 1701 {
wardm 12:046346a16ff4 1702 switch( this->settings.Modem )
wardm 12:046346a16ff4 1703 {
wardm 12:046346a16ff4 1704 case MODEM_FSK:
wardm 12:046346a16ff4 1705 break;
wardm 12:046346a16ff4 1706 case MODEM_LORA:
wardm 12:046346a16ff4 1707 break;
wardm 12:046346a16ff4 1708 default:
wardm 12:046346a16ff4 1709 break;
wardm 12:046346a16ff4 1710 }
wardm 12:046346a16ff4 1711 }