canuck lehead / lib_mma8451q

mma8451q driver with a few minor modifications

Dependents:   Senet NAMote

Fork of lib_mma8451q by wayne roberts

mma8451q.cpp@6:828b08201d8b, 2016-08-12 (annotated)

Committer:
shaunkrnelson
Date:
Fri Aug 12 14:13:17 2016 +0000
Revision:
6:828b08201d8b
Parent:
5:7bcda574c0fa
Parent:
4:b06535efa239 
Merging unnecessary branch to clean up revision history

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dudmuck 0:cb0046a629c1 1 #include "mma8451q.h"
dudmuck 0:cb0046a629c1 2 /* turn on: CTRL_REG1 active_bit = 1
dudmuck 0:cb0046a629c1 3 * back to standby: CTRL_REG1 active_bit = 0
dudmuck 0:cb0046a629c1 4 */
dudmuck 0:cb0046a629c1 5
dudmuck 0:cb0046a629c1 6 /* STANDBY: SYSMOD = 00 */
dudmuck 0:cb0046a629c1 7
dudmuck 0:cb0046a629c1 8 /*
dudmuck 0:cb0046a629c1 9 * MMA8451 I2C address
dudmuck 0:cb0046a629c1 10 */
dudmuck 0:cb0046a629c1 11 #define MMA8451_I2C_ADDRESS 0x38 //0x1C
dudmuck 0:cb0046a629c1 12
dudmuck 1:778b685c3ad0 13 MMA8451Q::MMA8451Q(I2C& r, DigitalIn& int_pin) : m_i2c(r), m_int_pin(int_pin)
dudmuck 0:cb0046a629c1 14 {
dudmuck 1:778b685c3ad0 15 /* INT pins on this chip default to push-pull output */
dudmuck 1:778b685c3ad0 16 write(MMA8451_CTRL_REG3, 0x01); // set PP_OD
dudmuck 1:778b685c3ad0 17 /* INT1 and INT2 are tied together */
dudmuck 0:cb0046a629c1 18
dudmuck 0:cb0046a629c1 19 }
dudmuck 0:cb0046a629c1 20
dudmuck 0:cb0046a629c1 21 MMA8451Q::~MMA8451Q()
dudmuck 0:cb0046a629c1 22 {
dudmuck 0:cb0046a629c1 23 }
dudmuck 0:cb0046a629c1 24
dudmuck 0:cb0046a629c1 25 void MMA8451Q::read(uint8_t addr, uint8_t *dst_buf, int length)
dudmuck 0:cb0046a629c1 26 {
dudmuck 0:cb0046a629c1 27 char cmd[2];
dudmuck 0:cb0046a629c1 28
dudmuck 0:cb0046a629c1 29 cmd[0] = addr;
dudmuck 0:cb0046a629c1 30 if (m_i2c.write(MMA8451_I2C_ADDRESS, cmd, 1, true))
dudmuck 1:778b685c3ad0 31 printf("MMA write-fail %02x\n", addr);
dudmuck 0:cb0046a629c1 32 if (m_i2c.read(MMA8451_I2C_ADDRESS, (char *)dst_buf, length))
dudmuck 1:778b685c3ad0 33 printf("MMA read-fail\n");
dudmuck 0:cb0046a629c1 34 }
dudmuck 0:cb0046a629c1 35
dudmuck 0:cb0046a629c1 36 uint8_t MMA8451Q::read_single(uint8_t addr)
dudmuck 0:cb0046a629c1 37 {
dudmuck 0:cb0046a629c1 38 char cmd[2];
dudmuck 0:cb0046a629c1 39
dudmuck 0:cb0046a629c1 40 cmd[0] = addr;
dudmuck 0:cb0046a629c1 41 if (m_i2c.write(MMA8451_I2C_ADDRESS, cmd, 1, true))
dudmuck 1:778b685c3ad0 42 printf("MMA write-fail %02x\n", addr);
dudmuck 0:cb0046a629c1 43 if (m_i2c.read(MMA8451_I2C_ADDRESS, cmd, 1))
dudmuck 1:778b685c3ad0 44 printf("MMA read-fail\n");
dudmuck 0:cb0046a629c1 45
dudmuck 0:cb0046a629c1 46 return cmd[0];
dudmuck 0:cb0046a629c1 47 }
dudmuck 0:cb0046a629c1 48
dudmuck 0:cb0046a629c1 49 void MMA8451Q::print_regs()
dudmuck 0:cb0046a629c1 50 {
shaunkrnelson 3:96faac0d688e 51 printf("ID: %02x\r\n", read_single(MMA8451_ID));
shaunkrnelson 3:96faac0d688e 52 printf("sysmod:%02x\r\n", read_single(MMA8451_SYSMOD));
dudmuck 0:cb0046a629c1 53 ctrl_reg1.octet = read_single(MMA8451_CTRL_REG1);
shaunkrnelson 3:96faac0d688e 54 printf("ctrl_reg1:%02x\r\n", ctrl_reg1.octet);
shaunkrnelson 3:96faac0d688e 55 printf("ctrl_reg2:%02x\r\n", read_single(MMA8451_CTRL_REG2));
shaunkrnelson 3:96faac0d688e 56 printf("ctrl_reg3:%02x\r\n", read_single(MMA8451_CTRL_REG3)); /* TODO: PP_OD is bit 0 (1=open drain) */
shaunkrnelson 3:96faac0d688e 57 printf("(int en) ctrl_reg4:%02x\r\n", read_single(MMA8451_CTRL_REG4));
shaunkrnelson 3:96faac0d688e 58 printf("(int cfg) ctrl_reg5:%02x\r\n", read_single(MMA8451_CTRL_REG5));
shaunkrnelson 3:96faac0d688e 59 printf("status:%02x\r\n", read_single(MMA8451_STATUS));
dudmuck 1:778b685c3ad0 60 /* (interrupt status) int src at 0x0c (MMA8451_INT_SOURCE): data ready, motion/freefall, pulse, orientation, transient, auto sleep */
shaunkrnelson 3:96faac0d688e 61 printf("INT_SOURCE:%02x\r\n", read_single(MMA8451_INT_SOURCE));
dudmuck 0:cb0046a629c1 62 }
dudmuck 0:cb0046a629c1 63
dudmuck 0:cb0046a629c1 64 void MMA8451Q::write(uint8_t addr, uint8_t data)
dudmuck 0:cb0046a629c1 65 {
dudmuck 0:cb0046a629c1 66 uint8_t cmd[2];
dudmuck 0:cb0046a629c1 67
dudmuck 0:cb0046a629c1 68 cmd[0] = addr;
dudmuck 0:cb0046a629c1 69 cmd[1] = data;
dudmuck 0:cb0046a629c1 70
dudmuck 0:cb0046a629c1 71 if (m_i2c.write(MMA8451_I2C_ADDRESS, (char *)cmd, 2))
dudmuck 1:778b685c3ad0 72 printf("MMA write-fail %02x\n", addr);
dudmuck 0:cb0046a629c1 73 }
dudmuck 0:cb0046a629c1 74
dudmuck 0:cb0046a629c1 75 void MMA8451Q::set_active(char arg)
dudmuck 0:cb0046a629c1 76 {
dudmuck 0:cb0046a629c1 77 char cmd[2];
dudmuck 0:cb0046a629c1 78
dudmuck 0:cb0046a629c1 79 cmd[0] = MMA8451_CTRL_REG1;
dudmuck 0:cb0046a629c1 80 cmd[1] = arg;
dudmuck 0:cb0046a629c1 81
dudmuck 0:cb0046a629c1 82 if (m_i2c.write(MMA8451_I2C_ADDRESS, cmd, 2))
dudmuck 1:778b685c3ad0 83 printf("MMA write-fail %02x\n", cmd[0]);
dudmuck 0:cb0046a629c1 84 }
dudmuck 0:cb0046a629c1 85
dudmuck 1:778b685c3ad0 86 bool MMA8451Q::get_active(void)
dudmuck 0:cb0046a629c1 87 {
dudmuck 0:cb0046a629c1 88 uint8_t ret = read_single(MMA8451_CTRL_REG1);
dudmuck 1:778b685c3ad0 89 //printf("CTRL_REG1: %x\n", ret);
dudmuck 1:778b685c3ad0 90 if (ret & 1)
dudmuck 1:778b685c3ad0 91 return true;
dudmuck 1:778b685c3ad0 92 else
dudmuck 1:778b685c3ad0 93 return false;
dudmuck 0:cb0046a629c1 94 }
dudmuck 0:cb0046a629c1 95
dudmuck 2:4bc96749141e 96 void MMA8451Q::orient_detect()
dudmuck 2:4bc96749141e 97 {
dudmuck 2:4bc96749141e 98 uint8_t v;
dudmuck 2:4bc96749141e 99
dudmuck 2:4bc96749141e 100 ctrl_reg1.octet = read_single(MMA8451_CTRL_REG1);
dudmuck 2:4bc96749141e 101 /* AN4068 Sensors Freescale Semiconductor, Inc.
dudmuck 2:4bc96749141e 102 * 4.1 Example Steps for Implementing the Embedded Orientation Detection */
dudmuck 2:4bc96749141e 103
dudmuck 2:4bc96749141e 104 /* Step 1: Put the part into Standby Mode */
dudmuck 2:4bc96749141e 105 ctrl_reg1.bits.ACTIVE = 0;
dudmuck 2:4bc96749141e 106 write(MMA8451_CTRL_REG1, ctrl_reg1.octet);
dudmuck 2:4bc96749141e 107
dudmuck 2:4bc96749141e 108 /* Step 2: Set the data rate to 50 Hz (for example, but can choose any sample rate). */
dudmuck 2:4bc96749141e 109 ctrl_reg1.bits.DR = 4;
dudmuck 2:4bc96749141e 110 write(MMA8451_CTRL_REG1, ctrl_reg1.octet);
dudmuck 2:4bc96749141e 111
dudmuck 2:4bc96749141e 112 /* Step 3: Set the PL_EN bit in Register 0x11 PL_CFG. This will enable the orientation detection. */
dudmuck 2:4bc96749141e 113 v = read_single(MMA8451_PL_CFG);
dudmuck 2:4bc96749141e 114 v |= 0x40;
dudmuck 2:4bc96749141e 115 write(MMA8451_PL_CFG, v);
dudmuck 2:4bc96749141e 116
dudmuck 2:4bc96749141e 117 /* Step 4: Set the Back/Front Angle trip points in register 0x13 following the table in the data sheet. */
dudmuck 2:4bc96749141e 118 v = read_single(MMA8451_PL_BF_ZCOMP);
dudmuck 2:4bc96749141e 119 /*v &= 0x3f;
dudmuck 2:4bc96749141e 120 v |= 0xX0;
dudmuck 2:4bc96749141e 121 write(MMA8451_PL_BF_ZCOMP, v);*/
dudmuck 2:4bc96749141e 122
dudmuck 2:4bc96749141e 123 /* Step 5: Set the Z-Lockout angle trip point in register 0x13 following the table in the data sheet. */
dudmuck 2:4bc96749141e 124 /* v &= 0xf8;
dudmuck 2:4bc96749141e 125 v |= 0x0X;
dudmuck 2:4bc96749141e 126 */
dudmuck 2:4bc96749141e 127
dudmuck 2:4bc96749141e 128 /* Step 6: Set the Trip Threshold Angle */
dudmuck 2:4bc96749141e 129 v = read_single(MMA8451_PL_THS_REG);
dudmuck 2:4bc96749141e 130 /*v &= 0x07;
dudmuck 2:4bc96749141e 131 v |= 0x0X << 3;
dudmuck 2:4bc96749141e 132 write(MMA8451_PL_THS_REG. v);*/
dudmuck 2:4bc96749141e 133
dudmuck 2:4bc96749141e 134 /* Step 7: Set the Hysteresis Angle */
dudmuck 2:4bc96749141e 135 v = read_single(MMA8451_PL_THS_REG);
dudmuck 2:4bc96749141e 136 /*v &= 0xf8;
dudmuck 2:4bc96749141e 137 v |= 0x0X;
dudmuck 2:4bc96749141e 138 write(MMA8451_PL_THS_REG. v);*/
dudmuck 2:4bc96749141e 139
dudmuck 2:4bc96749141e 140 /* Step 8: Register 0x2D, Control Register 4 configures all embedded features for interrupt */
dudmuck 2:4bc96749141e 141 ctrl_reg4.octet = 0;
dudmuck 2:4bc96749141e 142 ctrl_reg4.bits.INT_EN_LNDPRT = 1;
dudmuck 2:4bc96749141e 143 write(MMA8451_CTRL_REG4, ctrl_reg4.octet);
dudmuck 2:4bc96749141e 144
dudmuck 2:4bc96749141e 145 /* Step 9: Register 0x2E is Control Register 5 which gives the option of routing the interrupt to either INT1 or INT2 */
dudmuck 2:4bc96749141e 146 ctrl_reg5.octet = 0;
dudmuck 2:4bc96749141e 147 ctrl_reg5.bits.INT_CFG_LNDPRT = 1;
dudmuck 2:4bc96749141e 148 write(MMA8451_CTRL_REG5, ctrl_reg5.octet);
dudmuck 2:4bc96749141e 149
dudmuck 2:4bc96749141e 150 /* Step 10: Set the debounce counter in register 0x12 */
dudmuck 2:4bc96749141e 151 write(MMA8451_PL_COUNT, 5); // 5: debounce to 100ms at 50hz
dudmuck 2:4bc96749141e 152
dudmuck 2:4bc96749141e 153 /* Step 11: Put the device in Active Mode */
dudmuck 2:4bc96749141e 154 ctrl_reg1.octet = read_single(MMA8451_CTRL_REG1);
dudmuck 2:4bc96749141e 155 ctrl_reg1.bits.ACTIVE = 1;
dudmuck 2:4bc96749141e 156 write(MMA8451_CTRL_REG1, ctrl_reg1.octet);
dudmuck 2:4bc96749141e 157
dudmuck 2:4bc96749141e 158 /* Step 12: in service() function */
dudmuck 2:4bc96749141e 159 }
dudmuck 2:4bc96749141e 160
dudmuck 0:cb0046a629c1 161
dudmuck 0:cb0046a629c1 162 void MMA8451Q::transient_detect()
dudmuck 0:cb0046a629c1 163 {
dudmuck 0:cb0046a629c1 164 ctrl_reg1.octet = read_single(MMA8451_CTRL_REG1);
dudmuck 0:cb0046a629c1 165 /* AN4071 Sensors Freescale Semiconductor, Inc.
dudmuck 0:cb0046a629c1 166 * 7.1 Example Steps for Configuring Transient Detection
dudmuck 0:cb0046a629c1 167 * Change in X or Y > 0.5g for 50 ms at 100 Hz ODR, Normal mode */
dudmuck 0:cb0046a629c1 168
dudmuck 0:cb0046a629c1 169 /* Step 1: Put the device in Standby Mode: Register 0x2A CTRL_REG1 */
dudmuck 0:cb0046a629c1 170 ctrl_reg1.bits.ACTIVE = 0;
dudmuck 0:cb0046a629c1 171 write(MMA8451_CTRL_REG1, ctrl_reg1.octet);
dudmuck 0:cb0046a629c1 172 ctrl_reg1.bits.DR = 3; //Set device in 100 Hz ODR, Standby
dudmuck 0:cb0046a629c1 173 write(MMA8451_CTRL_REG1, ctrl_reg1.octet);
dudmuck 0:cb0046a629c1 174
dudmuck 0:cb0046a629c1 175 /* Step 2: Enable X and Y Axes and enable the latch: Register 0x1D Configuration Register */
dudmuck 0:cb0046a629c1 176 transient_cfg.octet = 0;
dudmuck 0:cb0046a629c1 177 transient_cfg.bits.ELE = 1; // enable latch
dudmuck 0:cb0046a629c1 178 transient_cfg.bits.YTEFE = 1; // enable Y
dudmuck 0:cb0046a629c1 179 transient_cfg.bits.XTEFE = 1; // enable X
dudmuck 0:cb0046a629c1 180 transient_cfg.bits.ZTEFE = 1; // enable Z
dudmuck 0:cb0046a629c1 181 write(MMA8451_TRANSIENT_CFG, transient_cfg.octet);
dudmuck 0:cb0046a629c1 182
dudmuck 0:cb0046a629c1 183 /* Step 3: Set the Threshold: Register 0x1F
dudmuck 0:cb0046a629c1 184 * Note: Step count is 0.063g per count, 0.5g / 0.063g = 7.93.
dudmuck 0:cb0046a629c1 185 * Therefore set the threshold to 8 counts */
dudmuck 0:cb0046a629c1 186 write(MMA8451_TRANSIENT_THS, 8);
dudmuck 0:cb0046a629c1 187
dudmuck 0:cb0046a629c1 188 /* Step 4: Set the Debounce Counter for 50 ms: Register 0x20
dudmuck 0:cb0046a629c1 189 * Note: 100 Hz ODR, therefore 10 ms step sizes */
dudmuck 0:cb0046a629c1 190 write(MMA8451_TRANSIENT_COUNT, 5);
dudmuck 0:cb0046a629c1 191
dudmuck 0:cb0046a629c1 192 /* Step 5: Enable Transient Detection Interrupt in the System (CTRL_REG4) */
dudmuck 0:cb0046a629c1 193 ctrl_reg4.octet = 0;
dudmuck 0:cb0046a629c1 194 ctrl_reg4.bits.INT_EN_TRANS = 1;
dudmuck 0:cb0046a629c1 195 write(MMA8451_CTRL_REG4, ctrl_reg4.octet);
dudmuck 0:cb0046a629c1 196
dudmuck 0:cb0046a629c1 197 /* Step 6: Route the Transient Interrupt to INT 1 hardware pin (CTRL_REG5) */
dudmuck 0:cb0046a629c1 198 ctrl_reg5.octet = 0;
dudmuck 0:cb0046a629c1 199 ctrl_reg5.bits.INT_CFG_TRANS = 1;
dudmuck 0:cb0046a629c1 200 write(MMA8451_CTRL_REG5, ctrl_reg5.octet);
dudmuck 0:cb0046a629c1 201
dudmuck 0:cb0046a629c1 202 /* Step 7: Put the device in Active Mode: Register 0x2A CTRL_REG1 */
dudmuck 0:cb0046a629c1 203 ctrl_reg1.octet = read_single(MMA8451_CTRL_REG1);
dudmuck 0:cb0046a629c1 204 ctrl_reg1.bits.ACTIVE = 1;
dudmuck 0:cb0046a629c1 205 write(MMA8451_CTRL_REG1, ctrl_reg1.octet);
dudmuck 0:cb0046a629c1 206
dudmuck 0:cb0046a629c1 207 /* Step 8: Write Interrupt Service Routine Reading the
dudmuck 0:cb0046a629c1 208 * System Interrupt Status and the Transient Status */
dudmuck 0:cb0046a629c1 209 }
dudmuck 0:cb0046a629c1 210
dudmuck 2:4bc96749141e 211 uint8_t MMA8451Q::service()
dudmuck 1:778b685c3ad0 212 {
dudmuck 1:778b685c3ad0 213 mma_int_source_t int_src;
shaunkrnelson 3:96faac0d688e 214
dudmuck 1:778b685c3ad0 215 if (m_int_pin)
dudmuck 2:4bc96749141e 216 return 0; // no interrupt
dudmuck 1:778b685c3ad0 217
dudmuck 1:778b685c3ad0 218 int_src.octet = read_single(MMA8451_INT_SOURCE);
dudmuck 1:778b685c3ad0 219
dudmuck 1:778b685c3ad0 220 if (int_src.bits.SRC_DRDY) {
dudmuck 1:778b685c3ad0 221 read(MMA8451_OUT_X_MSB, out.octets, 6);
dudmuck 1:778b685c3ad0 222 }
dudmuck 1:778b685c3ad0 223 if (int_src.bits.SRC_FF_MT) {
dudmuck 1:778b685c3ad0 224 read_single(MMA8451_FF_MT_SRC);
dudmuck 1:778b685c3ad0 225 }
dudmuck 1:778b685c3ad0 226 if (int_src.bits.SRC_PULSE) {
dudmuck 1:778b685c3ad0 227 read_single(MMA8451_PULSE_SRC);
dudmuck 1:778b685c3ad0 228 }
dudmuck 1:778b685c3ad0 229 if (int_src.bits.SRC_LNDPRT) {
shaunkrnelson 4:b06535efa239 230 /*AN4068 Step 12: Write a Service Routine to Service the Interrupt */
dudmuck 2:4bc96749141e 231 mma_pl_status_t pl_status;
dudmuck 2:4bc96749141e 232 pl_status.octet = read_single(MMA8451_PL_STATUS);
shaunkrnelson 3:96faac0d688e 233
shaunkrnelson 3:96faac0d688e 234 if (pl_status.bits.NEWLP)
shaunkrnelson 3:96faac0d688e 235 {
shaunkrnelson 3:96faac0d688e 236 orientation.reset();
shaunkrnelson 4:b06535efa239 237 orientation.pl_status.octet = pl_status.octet;
shaunkrnelson 3:96faac0d688e 238
shaunkrnelson 4:b06535efa239 239 if (orientation.pl_status.bits.LO)
shaunkrnelson 3:96faac0d688e 240 {
shaunkrnelson 3:96faac0d688e 241 orientation.low = true;
shaunkrnelson 3:96faac0d688e 242 if(verbose)
dudmuck 2:4bc96749141e 243 printf("Z-tilt-LO ");
shaunkrnelson 3:96faac0d688e 244 }
shaunkrnelson 3:96faac0d688e 245
shaunkrnelson 4:b06535efa239 246 if (orientation.pl_status.bits.LAPO == 0)
shaunkrnelson 3:96faac0d688e 247 {
shaunkrnelson 3:96faac0d688e 248 orientation.up = true;
shaunkrnelson 3:96faac0d688e 249 if(verbose)
dudmuck 2:4bc96749141e 250 printf("up ");
shaunkrnelson 3:96faac0d688e 251 }
shaunkrnelson 4:b06535efa239 252 else if (orientation.pl_status.bits.LAPO == 1)
shaunkrnelson 3:96faac0d688e 253 {
shaunkrnelson 3:96faac0d688e 254 orientation.down = true;
shaunkrnelson 3:96faac0d688e 255 if(verbose)
dudmuck 2:4bc96749141e 256 printf("down ");
shaunkrnelson 3:96faac0d688e 257 }
shaunkrnelson 4:b06535efa239 258 else if (orientation.pl_status.bits.LAPO == 2)
shaunkrnelson 3:96faac0d688e 259 {
shaunkrnelson 5:7bcda574c0fa 260 orientation.right = true;
shaunkrnelson 5:7bcda574c0fa 261 if(verbose)
shaunkrnelson 5:7bcda574c0fa 262 printf("right ");
shaunkrnelson 5:7bcda574c0fa 263 }
shaunkrnelson 5:7bcda574c0fa 264 else if (pl_status.bits.LAPO == 3)
shaunkrnelson 5:7bcda574c0fa 265 {
shaunkrnelson 3:96faac0d688e 266 orientation.left = true;
shaunkrnelson 3:96faac0d688e 267 if(verbose)
dudmuck 2:4bc96749141e 268 printf("left ");
shaunkrnelson 3:96faac0d688e 269 }
shaunkrnelson 6:828b08201d8b 270
shaunkrnelson 3:96faac0d688e 271
shaunkrnelson 4:b06535efa239 272 if (orientation.pl_status.bits.BAFRO)
shaunkrnelson 3:96faac0d688e 273 {
shaunkrnelson 3:96faac0d688e 274 orientation.back = true;
shaunkrnelson 3:96faac0d688e 275 if(verbose)
dudmuck 2:4bc96749141e 276 printf("back ");
shaunkrnelson 3:96faac0d688e 277 }
shaunkrnelson 3:96faac0d688e 278 else
shaunkrnelson 3:96faac0d688e 279 {
shaunkrnelson 3:96faac0d688e 280 orientation.front = true;
shaunkrnelson 3:96faac0d688e 281 if(verbose)
dudmuck 2:4bc96749141e 282 printf("front ");
dudmuck 2:4bc96749141e 283 }
shaunkrnelson 3:96faac0d688e 284 }
shaunkrnelson 3:96faac0d688e 285
shaunkrnelson 3:96faac0d688e 286 if(verbose)
dudmuck 2:4bc96749141e 287 printf("\r\n");
dudmuck 2:4bc96749141e 288 } // ...int_src.bits.SRC_LNDPRT
dudmuck 2:4bc96749141e 289
dudmuck 1:778b685c3ad0 290 if (int_src.bits.SRC_TRANS) {
dudmuck 1:778b685c3ad0 291 transient_src_t t_src;
dudmuck 1:778b685c3ad0 292 t_src.octet = read_single(MMA8451_TRANSIENT_SRC);
dudmuck 2:4bc96749141e 293 if (verbose) {
dudmuck 2:4bc96749141e 294 printf("transient src:%x ", t_src.octet);
dudmuck 2:4bc96749141e 295 if (t_src.bits.XTRANSE)
dudmuck 2:4bc96749141e 296 printf("X_Pol:%d ", t_src.bits.X_Trans_Pol);
dudmuck 2:4bc96749141e 297 if (t_src.bits.YTRANSE)
dudmuck 2:4bc96749141e 298 printf("Y_Pol:%d ", t_src.bits.Y_Trans_Pol);
dudmuck 2:4bc96749141e 299 if (t_src.bits.ZTRANSE)
dudmuck 2:4bc96749141e 300 printf("Z_Pol:%d ", t_src.bits.Z_Trans_Pol);
dudmuck 2:4bc96749141e 301 printf("\r\n");
shaunkrnelson 3:96faac0d688e 302 }
dudmuck 2:4bc96749141e 303 } // ...int_src.bits.SRC_TRANS
dudmuck 1:778b685c3ad0 304
dudmuck 1:778b685c3ad0 305 if (int_src.bits.SRC_ASLP) {
dudmuck 1:778b685c3ad0 306 read_single(MMA8451_SYSMOD);
dudmuck 1:778b685c3ad0 307 }
dudmuck 1:778b685c3ad0 308
dudmuck 2:4bc96749141e 309 return int_src.octet;
dudmuck 1:778b685c3ad0 310 }