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LPC11Uxx.h
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00001 00002 /****************************************************************************************************//** 00003 * @file LPC11Uxx.h 00004 * 00005 * 00006 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for 00007 * default LPC11Uxx Device Series 00008 * 00009 * @version V0.1 00010 * @date 21. March 2011 00011 * 00012 * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45 00013 * 00014 * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1, 00015 * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40 00016 * 00017 *******************************************************************************************************/ 00018 00019 // ################################################################################ 00020 // Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000 00021 // ################################################################################ 00022 00023 /** @addtogroup NXP 00024 * @{ 00025 */ 00026 00027 /** @addtogroup LPC11Uxx 00028 * @{ 00029 */ 00030 00031 #ifndef __LPC11UXX_H__ 00032 #define __LPC11UXX_H__ 00033 00034 #ifdef __cplusplus 00035 extern "C" { 00036 #endif 00037 00038 00039 #if defined ( __CC_ARM ) 00040 #pragma anon_unions 00041 #endif 00042 00043 /* Interrupt Number Definition */ 00044 00045 typedef enum { 00046 // ------------------------- Cortex-M0 Processor Exceptions Numbers ----------------------------- 00047 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ 00048 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ 00049 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ 00050 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ 00051 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ 00052 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ 00053 SysTick_IRQn = -1, /*!< 15 System Tick Timer */ 00054 // --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------ 00055 FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */ 00056 FLEX_INT1_IRQn = 1, 00057 FLEX_INT2_IRQn = 2, 00058 FLEX_INT3_IRQn = 3, 00059 FLEX_INT4_IRQn = 4, 00060 FLEX_INT5_IRQn = 5, 00061 FLEX_INT6_IRQn = 6, 00062 FLEX_INT7_IRQn = 7, 00063 GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */ 00064 GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */ 00065 Reserved0_IRQn = 10, /*!< Reserved Interrupt */ 00066 Reserved1_IRQn = 11, 00067 Reserved2_IRQn = 12, 00068 Reserved3_IRQn = 13, 00069 SSP1_IRQn = 14, /*!< SSP1 Interrupt */ 00070 I2C_IRQn = 15, /*!< I2C Interrupt */ 00071 TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */ 00072 TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */ 00073 TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */ 00074 TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */ 00075 SSP0_IRQn = 20, /*!< SSP0 Interrupt */ 00076 UART_IRQn = 21, /*!< UART Interrupt */ 00077 USB_IRQn = 22, /*!< USB IRQ Interrupt */ 00078 USB_FIQn = 23, /*!< USB FIQ Interrupt */ 00079 ADC_IRQn = 24, /*!< A/D Converter Interrupt */ 00080 WDT_IRQn = 25, /*!< Watchdog timer Interrupt */ 00081 BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */ 00082 FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */ 00083 Reserved4_IRQn = 28, /*!< Reserved Interrupt */ 00084 Reserved5_IRQn = 29, /*!< Reserved Interrupt */ 00085 USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */ 00086 Reserved6_IRQn = 31, /*!< Reserved Interrupt */ 00087 } IRQn_Type ; 00088 00089 00090 /** @addtogroup Configuration_of_CMSIS 00091 * @{ 00092 */ 00093 00094 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */ 00095 00096 #define __MPU_PRESENT 0 /*!< MPU present or not */ 00097 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ 00098 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 00099 /** @} */ /* End of group Configuration_of_CMSIS */ 00100 00101 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ 00102 #include "system_LPC11Uxx.h" /*!< LPC11Uxx System */ 00103 00104 /** @addtogroup Device_Peripheral_Registers 00105 * @{ 00106 */ 00107 00108 00109 // ------------------------------------------------------------------------------------------------ 00110 // ----- I2C ----- 00111 // ------------------------------------------------------------------------------------------------ 00112 00113 00114 /** 00115 * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C) 00116 */ 00117 00118 typedef struct { /*!< (@ 0x40000000) I2C Structure */ 00119 __IO uint32_t CONSET ; /*!< (@ 0x40000000) I2C Control Set Register */ 00120 __I uint32_t STAT ; /*!< (@ 0x40000004) I2C Status Register */ 00121 __IO uint32_t DAT ; /*!< (@ 0x40000008) I2C Data Register. */ 00122 __IO uint32_t ADR0 ; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */ 00123 __IO uint32_t SCLH ; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */ 00124 __IO uint32_t SCLL ; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */ 00125 __IO uint32_t CONCLR ; /*!< (@ 0x40000018) I2C Control Clear Register*/ 00126 __IO uint32_t MMCTRL ; /*!< (@ 0x4000001C) Monitor mode control register*/ 00127 __IO uint32_t ADR1 ; /*!< (@ 0x40000020) I2C Slave Address Register 1*/ 00128 __IO uint32_t ADR2 ; /*!< (@ 0x40000024) I2C Slave Address Register 2*/ 00129 __IO uint32_t ADR3 ; /*!< (@ 0x40000028) I2C Slave Address Register 3*/ 00130 __I uint32_t DATA_BUFFER ; /*!< (@ 0x4000002C) Data buffer register */ 00131 union{ 00132 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */ 00133 struct{ 00134 __IO uint32_t MASK0; 00135 __IO uint32_t MASK1; 00136 __IO uint32_t MASK2; 00137 __IO uint32_t MASK3; 00138 }; 00139 }; 00140 } LPC_I2C_Type; 00141 00142 00143 // ------------------------------------------------------------------------------------------------ 00144 // ----- WWDT ----- 00145 // ------------------------------------------------------------------------------------------------ 00146 00147 00148 /** 00149 * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT) 00150 */ 00151 00152 typedef struct { /*!< (@ 0x40004000) WWDT Structure */ 00153 __IO uint32_t MOD ; /*!< (@ 0x40004000) Watchdog mode register*/ 00154 __IO uint32_t TC ; /*!< (@ 0x40004004) Watchdog timer constant register */ 00155 __IO uint32_t FEED ; /*!< (@ 0x40004008) Watchdog feed sequence register */ 00156 __I uint32_t TV ; /*!< (@ 0x4000400C) Watchdog timer value register */ 00157 __IO uint32_t CLKSEL ; /*!< (@ 0x40004010) Watchdog clock select register. */ 00158 __IO uint32_t WARNINT ; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */ 00159 __IO uint32_t WINDOW ; /*!< (@ 0x40004018) Watchdog Window compare value. */ 00160 } LPC_WWDT_Type; 00161 00162 00163 // ------------------------------------------------------------------------------------------------ 00164 // ----- USART ----- 00165 // ------------------------------------------------------------------------------------------------ 00166 00167 00168 /** 00169 * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART) 00170 */ 00171 00172 typedef struct { /*!< (@ 0x40008000) USART Structure */ 00173 00174 union { 00175 __IO uint32_t DLL ; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ 00176 __O uint32_t THR ; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */ 00177 __I uint32_t RBR ; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */ 00178 }; 00179 00180 union { 00181 __IO uint32_t IER ; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */ 00182 __IO uint32_t DLM ; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */ 00183 }; 00184 00185 union { 00186 __O uint32_t FCR ; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */ 00187 __I uint32_t IIR ; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */ 00188 }; 00189 __IO uint32_t LCR ; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */ 00190 __IO uint32_t MCR ; /*!< (@ 0x40008010) Modem Control Register. */ 00191 __I uint32_t LSR ; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */ 00192 __I uint32_t MSR ; /*!< (@ 0x40008018) Modem Status Register. */ 00193 __IO uint32_t SCR ; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */ 00194 __IO uint32_t ACR ; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */ 00195 __IO uint32_t ICR ; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */ 00196 __IO uint32_t FDR ; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */ 00197 __IO uint32_t OSR ; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */ 00198 __IO uint32_t TER ; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */ 00199 __I uint32_t RESERVED0[3]; 00200 __IO uint32_t HDEN ; /*!< (@ 0x40008040) Half duplex enable register. */ 00201 __I uint32_t RESERVED1; 00202 __IO uint32_t SCICTRL ; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */ 00203 __IO uint32_t RS485CTRL ; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */ 00204 __IO uint32_t RS485ADRMATCH ; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */ 00205 __IO uint32_t RS485DLY ; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */ 00206 __IO uint32_t SYNCCTRL; 00207 } LPC_USART_Type; 00208 00209 00210 // ------------------------------------------------------------------------------------------------ 00211 // ----- Timer ----- 00212 // ------------------------------------------------------------------------------------------------ 00213 00214 00215 /** 00216 * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3 00217 */ 00218 00219 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */ 00220 __IO uint32_t IR ; /*!< (@ 0x40014000) Interrupt Register */ 00221 __IO uint32_t TCR ; /*!< (@ 0x40014004) Timer Control Register */ 00222 __IO uint32_t TC ; /*!< (@ 0x40014008) Timer Counter */ 00223 __IO uint32_t PR ; /*!< (@ 0x4001400C) Prescale Register */ 00224 __IO uint32_t PC ; /*!< (@ 0x40014010) Prescale Counter */ 00225 __IO uint32_t MCR ; /*!< (@ 0x40014014) Match Control Register */ 00226 union { 00227 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */ 00228 struct{ 00229 __IO uint32_t MR0 ; /*!< (@ 0x40018018) Match Register. MR0 */ 00230 __IO uint32_t MR1 ; /*!< (@ 0x4001801C) Match Register. MR1 */ 00231 __IO uint32_t MR2 ; /*!< (@ 0x40018020) Match Register. MR2 */ 00232 __IO uint32_t MR3 ; /*!< (@ 0x40018024) Match Register. MR3 */ 00233 }; 00234 }; 00235 __IO uint32_t CCR ; /*!< (@ 0x40014028) Capture Control Register */ 00236 union{ 00237 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */ 00238 struct{ 00239 __I uint32_t CR0 ; /*!< (@ 0x4001802C) Capture Register. CR 0 */ 00240 __I uint32_t CR1 ; /*!< (@ 0x40018030) Capture Register. CR 1 */ 00241 __I uint32_t CR2 ; /*!< (@ 0x40018034) Capture Register. CR 2 */ 00242 __I uint32_t CR3 ; /*!< (@ 0x40018038) Capture Register. CR 3 */ 00243 }; 00244 }; 00245 __IO uint32_t EMR ; /*!< (@ 0x4001403C) External Match Register */ 00246 __I uint32_t RESERVED0[12]; 00247 __IO uint32_t CTCR ; /*!< (@ 0x40014070) Count Control Register */ 00248 __IO uint32_t PWMC ; /*!< (@ 0x40014074) PWM Control Register */ 00249 } LPC_CTxxBx_Type; 00250 00251 00252 00253 // ------------------------------------------------------------------------------------------------ 00254 // ----- ADC ----- 00255 // ------------------------------------------------------------------------------------------------ 00256 00257 00258 /** 00259 * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC) 00260 */ 00261 00262 typedef struct { /*!< (@ 0x4001C000) ADC Structure */ 00263 __IO uint32_t CR ; /*!< (@ 0x4001C000) A/D Control Register */ 00264 __IO uint32_t GDR ; /*!< (@ 0x4001C004) A/D Global Data Register */ 00265 __I uint32_t RESERVED0[1]; 00266 __IO uint32_t INTEN ; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */ 00267 union{ 00268 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/ 00269 struct{ 00270 __IO uint32_t DR0 ; /*!< (@ 0x40020010) A/D Channel Data Register 0*/ 00271 __IO uint32_t DR1 ; /*!< (@ 0x40020014) A/D Channel Data Register 1*/ 00272 __IO uint32_t DR2 ; /*!< (@ 0x40020018) A/D Channel Data Register 2*/ 00273 __IO uint32_t DR3 ; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/ 00274 __IO uint32_t DR4 ; /*!< (@ 0x40020020) A/D Channel Data Register 4*/ 00275 __IO uint32_t DR5 ; /*!< (@ 0x40020024) A/D Channel Data Register 5*/ 00276 __IO uint32_t DR6 ; /*!< (@ 0x40020028) A/D Channel Data Register 6*/ 00277 __IO uint32_t DR7 ; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/ 00278 }; 00279 }; 00280 __I uint32_t STAT ; /*!< (@ 0x4001C030) A/D Status Register. */ 00281 } LPC_ADC_Type; 00282 00283 00284 // ------------------------------------------------------------------------------------------------ 00285 // ----- PMU ----- 00286 // ------------------------------------------------------------------------------------------------ 00287 00288 00289 /** 00290 * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU) 00291 */ 00292 00293 typedef struct { /*!< (@ 0x40038000) PMU Structure */ 00294 __IO uint32_t PCON ; /*!< (@ 0x40038000) Power control register */ 00295 union{ 00296 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */ 00297 struct{ 00298 __IO uint32_t GPREG0 ; /*!< (@ 0x40038004) General purpose register 0 */ 00299 __IO uint32_t GPREG1 ; /*!< (@ 0x40038008) General purpose register 1 */ 00300 __IO uint32_t GPREG2 ; /*!< (@ 0x4003800C) General purpose register 2 */ 00301 __IO uint32_t GPREG3 ; /*!< (@ 0x40038010) General purpose register 3 */ 00302 }; 00303 }; 00304 } LPC_PMU_Type; 00305 00306 00307 // ------------------------------------------------------------------------------------------------ 00308 // ----- FLASHCTRL ----- 00309 // ------------------------------------------------------------------------------------------------ 00310 00311 00312 /** 00313 * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL) 00314 */ 00315 00316 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */ 00317 __I uint32_t RESERVED0[4]; 00318 __IO uint32_t FLASHCFG ; /*!< (@ 0x4003C010) Flash memory access time configuration register */ 00319 __I uint32_t RESERVED1[3]; 00320 __IO uint32_t FMSSTART ; /*!< (@ 0x4003C020) Signature start address register */ 00321 __IO uint32_t FMSSTOP ; /*!< (@ 0x4003C024) Signature stop-address register */ 00322 __I uint32_t RESERVED2[1]; 00323 __I uint32_t FMSW0 ; /*!< (@ 0x4003C02C) Word 0 [31:0] */ 00324 __I uint32_t FMSW1 ; /*!< (@ 0x4003C030) Word 1 [63:32] */ 00325 __I uint32_t FMSW2 ; /*!< (@ 0x4003C034) Word 2 [95:64] */ 00326 __I uint32_t FMSW3 ; /*!< (@ 0x4003C038) Word 3 [127:96] */ 00327 __I uint32_t RESERVED3[1001]; 00328 __I uint32_t FMSTAT ; /*!< (@ 0x4003CFE0) Signature generation status register */ 00329 __I uint32_t RESERVED4[1]; 00330 __IO uint32_t FMSTATCLR ; /*!< (@ 0x4003CFE8) Signature generation status clear register */ 00331 } LPC_FLASHCTRL_Type; 00332 00333 00334 // ------------------------------------------------------------------------------------------------ 00335 // ----- SSP0/1 ----- 00336 // ------------------------------------------------------------------------------------------------ 00337 00338 00339 /** 00340 * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0) 00341 */ 00342 00343 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */ 00344 __IO uint32_t CR0 ; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */ 00345 __IO uint32_t CR1 ; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */ 00346 __IO uint32_t DR ; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */ 00347 __I uint32_t SR ; /*!< (@ 0x4004000C) Status Register */ 00348 __IO uint32_t CPSR ; /*!< (@ 0x40040010) Clock Prescale Register */ 00349 __IO uint32_t IMSC ; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */ 00350 __I uint32_t RIS ; /*!< (@ 0x40040018) Raw Interrupt Status Register */ 00351 __I uint32_t MIS ; /*!< (@ 0x4004001C) Masked Interrupt Status Register */ 00352 __IO uint32_t ICR ; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */ 00353 } LPC_SSPx_Type; 00354 00355 00356 00357 // ------------------------------------------------------------------------------------------------ 00358 // ----- IOCONFIG ----- 00359 // ------------------------------------------------------------------------------------------------ 00360 00361 00362 /** 00363 * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) 00364 */ 00365 00366 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ 00367 __IO uint32_t RESET_PIO0_0 ; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */ 00368 __IO uint32_t PIO0_1 ; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */ 00369 __IO uint32_t PIO0_2 ; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */ 00370 __IO uint32_t PIO0_3 ; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */ 00371 __IO uint32_t PIO0_4 ; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */ 00372 __IO uint32_t PIO0_5 ; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */ 00373 __IO uint32_t PIO0_6 ; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */ 00374 __IO uint32_t PIO0_7 ; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */ 00375 __IO uint32_t PIO0_8 ; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */ 00376 __IO uint32_t PIO0_9 ; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */ 00377 __IO uint32_t SWCLK_PIO0_10 ; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */ 00378 __IO uint32_t TDI_PIO0_11 ; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */ 00379 __IO uint32_t TMS_PIO0_12 ; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */ 00380 __IO uint32_t TDO_PIO0_13 ; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */ 00381 __IO uint32_t TRST_PIO0_14 ; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */ 00382 __IO uint32_t SWDIO_PIO0_15 ; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */ 00383 __IO uint32_t PIO0_16 ; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */ 00384 __IO uint32_t PIO0_17 ; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */ 00385 __IO uint32_t PIO0_18 ; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */ 00386 __IO uint32_t PIO0_19 ; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */ 00387 __IO uint32_t PIO0_20 ; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */ 00388 __IO uint32_t PIO0_21 ; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */ 00389 __IO uint32_t PIO0_22 ; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */ 00390 __IO uint32_t PIO0_23 ; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */ 00391 __IO uint32_t PIO1_0 ; /*!< Offset: 0x060 */ 00392 __IO uint32_t PIO1_1; 00393 __IO uint32_t PIO1_2; 00394 __IO uint32_t PIO1_3; 00395 __IO uint32_t PIO1_4 ; /*!< Offset: 0x070 */ 00396 __IO uint32_t PIO1_5 ; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */ 00397 __IO uint32_t PIO1_6; 00398 __IO uint32_t PIO1_7; 00399 __IO uint32_t PIO1_8 ; /*!< Offset: 0x080 */ 00400 __IO uint32_t PIO1_9; 00401 __IO uint32_t PIO1_10; 00402 __IO uint32_t PIO1_11; 00403 __IO uint32_t PIO1_12 ; /*!< Offset: 0x090 */ 00404 __IO uint32_t PIO1_13 ; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */ 00405 __IO uint32_t PIO1_14 ; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */ 00406 __IO uint32_t PIO1_15 ; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */ 00407 __IO uint32_t PIO1_16 ; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */ 00408 __IO uint32_t PIO1_17; 00409 __IO uint32_t PIO1_18; 00410 __IO uint32_t PIO1_19 ; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */ 00411 __IO uint32_t PIO1_20 ; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */ 00412 __IO uint32_t PIO1_21 ; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */ 00413 __IO uint32_t PIO1_22 ; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */ 00414 __IO uint32_t PIO1_23 ; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */ 00415 __IO uint32_t PIO1_24 ; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */ 00416 __IO uint32_t PIO1_25 ; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */ 00417 __IO uint32_t PIO1_26 ; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */ 00418 __IO uint32_t PIO1_27 ; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */ 00419 __IO uint32_t PIO1_28 ; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */ 00420 __IO uint32_t PIO1_29 ; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */ 00421 __IO uint32_t PIO1_30; 00422 __IO uint32_t PIO1_31 ; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */ 00423 } LPC_IOCON_Type; 00424 00425 00426 // ------------------------------------------------------------------------------------------------ 00427 // ----- SYSCON ----- 00428 // ------------------------------------------------------------------------------------------------ 00429 00430 00431 /** 00432 * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON) 00433 */ 00434 00435 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ 00436 __IO uint32_t SYSMEMREMAP ; /*!< (@ 0x40048000) System memory remap */ 00437 __IO uint32_t PRESETCTRL ; /*!< (@ 0x40048004) Peripheral reset control */ 00438 __IO uint32_t SYSPLLCTRL ; /*!< (@ 0x40048008) System PLL control */ 00439 __I uint32_t SYSPLLSTAT ; /*!< (@ 0x4004800C) System PLL status */ 00440 __IO uint32_t USBPLLCTRL ; /*!< (@ 0x40048010) USB PLL control */ 00441 __I uint32_t USBPLLSTAT ; /*!< (@ 0x40048014) USB PLL status */ 00442 __I uint32_t RESERVED0[2]; 00443 __IO uint32_t SYSOSCCTRL ; /*!< (@ 0x40048020) System oscillator control */ 00444 __IO uint32_t WDTOSCCTRL ; /*!< (@ 0x40048024) Watchdog oscillator control */ 00445 __I uint32_t RESERVED1[2]; 00446 __IO uint32_t SYSRSTSTAT ; /*!< (@ 0x40048030) System reset status register */ 00447 __I uint32_t RESERVED2[3]; 00448 __IO uint32_t SYSPLLCLKSEL ; /*!< (@ 0x40048040) System PLL clock source select */ 00449 __IO uint32_t SYSPLLCLKUEN ; /*!< (@ 0x40048044) System PLL clock source update enable */ 00450 __IO uint32_t USBPLLCLKSEL ; /*!< (@ 0x40048048) USB PLL clock source select */ 00451 __IO uint32_t USBPLLCLKUEN ; /*!< (@ 0x4004804C) USB PLL clock source update enable */ 00452 __I uint32_t RESERVED3[8]; 00453 __IO uint32_t MAINCLKSEL ; /*!< (@ 0x40048070) Main clock source select */ 00454 __IO uint32_t MAINCLKUEN ; /*!< (@ 0x40048074) Main clock source update enable */ 00455 __IO uint32_t SYSAHBCLKDIV ; /*!< (@ 0x40048078) System clock divider */ 00456 __I uint32_t RESERVED4[1]; 00457 __IO uint32_t SYSAHBCLKCTRL ; /*!< (@ 0x40048080) System clock control */ 00458 __I uint32_t RESERVED5[4]; 00459 __IO uint32_t SSP0CLKDIV ; /*!< (@ 0x40048094) SSP0 clock divider */ 00460 __IO uint32_t UARTCLKDIV ; /*!< (@ 0x40048098) UART clock divider */ 00461 __IO uint32_t SSP1CLKDIV ; /*!< (@ 0x4004809C) SSP1 clock divider */ 00462 __I uint32_t RESERVED6[8]; 00463 __IO uint32_t USBCLKSEL ; /*!< (@ 0x400480C0) USB clock source select */ 00464 __IO uint32_t USBCLKUEN ; /*!< (@ 0x400480C4) USB clock source update enable */ 00465 __IO uint32_t USBCLKDIV ; /*!< (@ 0x400480C8) USB clock source divider */ 00466 __I uint32_t RESERVED7[5]; 00467 __IO uint32_t CLKOUTSEL ; /*!< (@ 0x400480E0) CLKOUT clock source select */ 00468 __IO uint32_t CLKOUTUEN ; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ 00469 __IO uint32_t CLKOUTDIV ; /*!< (@ 0x400480E8) CLKOUT clock divider */ 00470 __I uint32_t RESERVED8[5]; 00471 __I uint32_t PIOPORCAP0 ; /*!< (@ 0x40048100) POR captured PIO status 0 */ 00472 __I uint32_t PIOPORCAP1 ; /*!< (@ 0x40048104) POR captured PIO status 1 */ 00473 __I uint32_t RESERVED9[18]; 00474 __IO uint32_t BODCTRL ; /*!< (@ 0x40048150) Brown-Out Detect */ 00475 __IO uint32_t SYSTCKCAL ; /*!< (@ 0x40048154) System tick counter calibration */ 00476 __I uint32_t RESERVED10[6]; 00477 __IO uint32_t IRQLATENCY ; /*!< (@ 0x40048170) IQR delay */ 00478 __IO uint32_t NMISRC ; /*!< (@ 0x40048174) NMI Source Control */ 00479 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ 00480 __IO uint32_t USBCLKCTRL ; /*!< (@ 0x40048198) USB clock control */ 00481 __I uint32_t USBCLKST ; /*!< (@ 0x4004819C) USB clock status */ 00482 __I uint32_t RESERVED11[25]; 00483 __IO uint32_t STARTERP0 ; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */ 00484 __I uint32_t RESERVED12[3]; 00485 __IO uint32_t STARTERP1 ; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */ 00486 __I uint32_t RESERVED13[6]; 00487 __IO uint32_t PDSLEEPCFG ; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */ 00488 __IO uint32_t PDAWAKECFG ; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */ 00489 __IO uint32_t PDRUNCFG ; /*!< (@ 0x40048238) Power configuration register */ 00490 __I uint32_t RESERVED14[110]; 00491 __I uint32_t DEVICE_ID ; /*!< (@ 0x400483F4) Device ID */ 00492 } LPC_SYSCON_Type; 00493 00494 00495 // ------------------------------------------------------------------------------------------------ 00496 // ----- GPIO_PIN_INT ----- 00497 // ------------------------------------------------------------------------------------------------ 00498 00499 00500 /** 00501 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT) 00502 */ 00503 00504 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */ 00505 __IO uint32_t ISEL ; /*!< (@ 0x4004C000) Pin Interrupt Mode register */ 00506 __IO uint32_t IENR ; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */ 00507 __IO uint32_t SIENR ; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */ 00508 __IO uint32_t CIENR ; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */ 00509 __IO uint32_t IENF ; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */ 00510 __IO uint32_t SIENF ; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */ 00511 __IO uint32_t CIENF ; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ 00512 __IO uint32_t RISE ; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */ 00513 __IO uint32_t FALL ; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */ 00514 __IO uint32_t IST ; /*!< (@ 0x4004C024) Pin Interrupt Status register */ 00515 } LPC_GPIO_PIN_INT_Type; 00516 00517 00518 // ------------------------------------------------------------------------------------------------ 00519 // ----- GPIO_GROUP_INT0/1 ----- 00520 // ------------------------------------------------------------------------------------------------ 00521 00522 00523 /** 00524 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0) 00525 */ 00526 00527 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */ 00528 __IO uint32_t CTRL ; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */ 00529 __I uint32_t RESERVED0[7]; 00530 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */ 00531 __I uint32_t RESERVED1[6]; 00532 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */ 00533 } LPC_GPIO_GROUP_INTx_Type; 00534 00535 00536 00537 // ------------------------------------------------------------------------------------------------ 00538 // ----- USB ----- 00539 // ------------------------------------------------------------------------------------------------ 00540 00541 00542 /** 00543 * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB) 00544 */ 00545 00546 typedef struct { /*!< (@ 0x40080000) USB Structure */ 00547 __IO uint32_t DEVCMDSTAT ; /*!< (@ 0x40080000) USB Device Command/Status register */ 00548 __IO uint32_t INFO ; /*!< (@ 0x40080004) USB Info register */ 00549 __IO uint32_t EPLISTSTART ; /*!< (@ 0x40080008) USB EP Command/Status List start address */ 00550 __IO uint32_t DATABUFSTART ; /*!< (@ 0x4008000C) USB Data buffer start address */ 00551 __IO uint32_t LPM ; /*!< (@ 0x40080010) Link Power Management register */ 00552 __IO uint32_t EPSKIP ; /*!< (@ 0x40080014) USB Endpoint skip */ 00553 __IO uint32_t EPINUSE ; /*!< (@ 0x40080018) USB Endpoint Buffer in use */ 00554 __IO uint32_t EPBUFCFG ; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */ 00555 __IO uint32_t INTSTAT ; /*!< (@ 0x40080020) USB interrupt status register */ 00556 __IO uint32_t INTEN ; /*!< (@ 0x40080024) USB interrupt enable register */ 00557 __IO uint32_t INTSETSTAT ; /*!< (@ 0x40080028) USB set interrupt status register */ 00558 __IO uint32_t INTROUTING ; /*!< (@ 0x4008002C) USB interrupt routing register */ 00559 __I uint32_t RESERVED0[1]; 00560 __I uint32_t EPTOGGLE ; /*!< (@ 0x40080034) USB Endpoint toggle register */ 00561 } LPC_USB_Type; 00562 00563 00564 // ------------------------------------------------------------------------------------------------ 00565 // ----- GPIO_PORT ----- 00566 // ------------------------------------------------------------------------------------------------ 00567 00568 00569 /** 00570 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) 00571 */ 00572 00573 typedef struct { 00574 union { 00575 struct { 00576 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */ 00577 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */ 00578 }; 00579 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */ 00580 }; 00581 __I uint32_t RESERVED0[1008]; 00582 union { 00583 struct { 00584 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */ 00585 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */ 00586 }; 00587 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */ 00588 }; 00589 uint32_t RESERVED1[960]; 00590 __IO uint32_t DIR[2]; /* 0x2000 */ 00591 uint32_t RESERVED2[30]; 00592 __IO uint32_t MASK[2]; /* 0x2080 */ 00593 uint32_t RESERVED3[30]; 00594 __IO uint32_t PIN[2]; /* 0x2100 */ 00595 uint32_t RESERVED4[30]; 00596 __IO uint32_t MPIN[2]; /* 0x2180 */ 00597 uint32_t RESERVED5[30]; 00598 __IO uint32_t SET[2]; /* 0x2200 */ 00599 uint32_t RESERVED6[30]; 00600 __O uint32_t CLR[2]; /* 0x2280 */ 00601 uint32_t RESERVED7[30]; 00602 __O uint32_t NOT[2]; /* 0x2300 */ 00603 } LPC_GPIO_Type; 00604 00605 00606 #if defined ( __CC_ARM ) 00607 #pragma no_anon_unions 00608 #endif 00609 00610 00611 // ------------------------------------------------------------------------------------------------ 00612 // ----- Peripheral memory map ----- 00613 // ------------------------------------------------------------------------------------------------ 00614 00615 #define LPC_I2C_BASE (0x40000000) 00616 #define LPC_WWDT_BASE (0x40004000) 00617 #define LPC_USART_BASE (0x40008000) 00618 #define LPC_CT16B0_BASE (0x4000C000) 00619 #define LPC_CT16B1_BASE (0x40010000) 00620 #define LPC_CT32B0_BASE (0x40014000) 00621 #define LPC_CT32B1_BASE (0x40018000) 00622 #define LPC_ADC_BASE (0x4001C000) 00623 #define LPC_PMU_BASE (0x40038000) 00624 #define LPC_FLASHCTRL_BASE (0x4003C000) 00625 #define LPC_SSP0_BASE (0x40040000) 00626 #define LPC_SSP1_BASE (0x40058000) 00627 #define LPC_IOCON_BASE (0x40044000) 00628 #define LPC_SYSCON_BASE (0x40048000) 00629 #define LPC_GPIO_PIN_INT_BASE (0x4004C000) 00630 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000) 00631 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000) 00632 #define LPC_USB_BASE (0x40080000) 00633 #define LPC_GPIO_BASE (0x50000000) 00634 00635 00636 // ------------------------------------------------------------------------------------------------ 00637 // ----- Peripheral declaration ----- 00638 // ------------------------------------------------------------------------------------------------ 00639 00640 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE) 00641 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) 00642 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE) 00643 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE) 00644 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE) 00645 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE) 00646 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE) 00647 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) 00648 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) 00649 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) 00650 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE) 00651 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE) 00652 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) 00653 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) 00654 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE) 00655 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE) 00656 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE) 00657 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE) 00658 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE) 00659 00660 00661 /** @} */ /* End of group Device_Peripheral_Registers */ 00662 /** @} */ /* End of group (null) */ 00663 /** @} */ /* End of group LPC11Uxx */ 00664 00665 #ifdef __cplusplus 00666 } 00667 #endif 00668 00669 00670 #endif // __LPC11UXX_H__
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