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LPC_SSPx_Type Struct Reference
[Device_Peripheral_Registers]
Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0) More...
#include <LPC11Uxx.h>
Data Fields | |
| __IO uint32_t | CR0 |
| __IO uint32_t | CR1 |
| __IO uint32_t | DR |
| __I uint32_t | SR |
| __IO uint32_t | CPSR |
| __IO uint32_t | IMSC |
| __I uint32_t | RIS |
| __I uint32_t | MIS |
| __IO uint32_t | ICR |
Detailed Description
Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
Definition at line 343 of file LPC11Uxx.h.
Field Documentation
| __IO uint32_t CPSR |
(@ 0x40040010) Clock Prescale Register
Definition at line 348 of file LPC11Uxx.h.
| __IO uint32_t CR0 |
< (@ 0x40040000) SSP0 Structure (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size.
Definition at line 344 of file LPC11Uxx.h.
| __IO uint32_t CR1 |
(@ 0x40040004) Control Register 1. Selects master/slave and other modes.
Definition at line 345 of file LPC11Uxx.h.
| __IO uint32_t DR |
(@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
Definition at line 346 of file LPC11Uxx.h.
| __IO uint32_t ICR |
(@ 0x40040020) SSPICR Interrupt Clear Register
Definition at line 352 of file LPC11Uxx.h.
| __IO uint32_t IMSC |
(@ 0x40040014) Interrupt Mask Set and Clear Register
Definition at line 349 of file LPC11Uxx.h.
| __I uint32_t MIS |
(@ 0x4004001C) Masked Interrupt Status Register
Definition at line 351 of file LPC11Uxx.h.
| __I uint32_t RIS |
(@ 0x40040018) Raw Interrupt Status Register
Definition at line 350 of file LPC11Uxx.h.
| __I uint32_t SR |
(@ 0x4004000C) Status Register
Definition at line 347 of file LPC11Uxx.h.
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