Revision 185:08ed48f1de7f, committed 2018-04-19

Comitter:

AnnaBridge

Date:

Thu Apr 19 17:12:19 2018 +0100

Parent:

184:5166a824ec1a

Child:

186:9c2029bfadbe

Commit message:

mbed-dev library. Release version 161

Changed in this revision

--- a/drivers/CAN.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/CAN.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -18,7 +18,7 @@
 #if DEVICE_CAN
 
 #include "cmsis.h"
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 
 namespace mbed {
 

--- a/drivers/Ethernet.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/Ethernet.h	Thu Apr 19 17:12:19 2018 +0100
@@ -98,7 +98,7 @@
      */
     int send();
 
-    /** Recevies an arrived ethernet packet.
+    /** Receives an arrived ethernet packet.
      *
      *  Receiving an ethernet packet will drop the last received ethernet packet
      *  and make a new ethernet packet ready to read.
@@ -110,7 +110,7 @@
      */
     int receive();
 
-    /** Read from an recevied ethernet packet.
+    /** Read from an received ethernet packet.
      *
      *  After receive returned a number bigger than 0 it is
      *  possible to read bytes from this packet.
@@ -131,11 +131,11 @@
      */
     void address(char *mac);
 
-    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
+    /** Returns if an ethernet link is present or not. It takes a while after Ethernet initialization to show up.
      *
      *  @returns
-     *   0 if no ethernet link is pressent,
-     *   1 if an ethernet link is pressent.
+     *   0 if no ethernet link is present,
+     *   1 if an ethernet link is present.
      *
      * Example:
      * @code

--- a/drivers/FlashIAP.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/FlashIAP.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -20,7 +20,9 @@
  * SOFTWARE.
  */
 
+#include <stdio.h>
 #include <string.h>
+#include <algorithm>
 #include "FlashIAP.h"
 #include "mbed_assert.h"
 
@@ -57,6 +59,9 @@
     if (flash_init(&_flash)) {
         ret = -1;
     }
+    uint32_t page_size = get_page_size();
+    _page_buf = new uint8_t[page_size];
+
     _mutex->unlock();
     return ret;
 }
@@ -68,6 +73,7 @@
     if (flash_free(&_flash)) {
         ret = -1;
     }
+    delete[] _page_buf;
     _mutex->unlock();
     return ret;
 }
@@ -85,22 +91,43 @@
 int FlashIAP::program(const void *buffer, uint32_t addr, uint32_t size)
 {
     uint32_t page_size = get_page_size();
-    uint32_t current_sector_size = flash_get_sector_size(&_flash, addr);
-    // addr and size should be aligned to page size, and multiple of page size
-    // page program should not cross sector boundaries
-    if (!is_aligned(addr, page_size) ||
-        !is_aligned(size, page_size) ||
-        (size < page_size) ||
-        (((addr % current_sector_size) + size) > current_sector_size)) {
+    uint32_t flash_size = flash_get_size(&_flash);
+    uint32_t flash_start_addr = flash_get_start_address(&_flash);
+    uint32_t chunk, prog_size;
+    const uint8_t *buf = (uint8_t *) buffer;
+    const uint8_t *prog_buf;
+
+    // addr should be aligned to page size
+    if (!is_aligned(addr, page_size) || (!buffer) ||
+        ((addr + size) > (flash_start_addr + flash_size))) {
         return -1;
     }
 
     int ret = 0;
     _mutex->lock();
-    if (flash_program_page(&_flash, addr, (const uint8_t *)buffer, size)) {
-        ret = -1;
+    while (size) {
+        uint32_t current_sector_size = flash_get_sector_size(&_flash, addr);
+        chunk = std::min(current_sector_size - (addr % current_sector_size), size);
+        if (chunk < page_size) {
+            memcpy(_page_buf, buf, chunk);
+            memset(_page_buf + chunk, 0xFF, page_size - chunk);
+            prog_buf = _page_buf;
+            prog_size = page_size;
+        } else {
+            chunk = chunk / page_size * page_size;
+            prog_buf = buf;
+            prog_size = chunk;
+        }
+        if (flash_program_page(&_flash, addr, prog_buf, prog_size)) {
+            ret = -1;
+            break;
+        }
+        size -= chunk;
+        addr += chunk;
+        buf += chunk;
     }
     _mutex->unlock();
+
     return ret;
 }
 
@@ -117,10 +144,19 @@
 
 int FlashIAP::erase(uint32_t addr, uint32_t size)
 {
-    uint32_t current_sector_size = 0UL;
+    uint32_t current_sector_size;
+    uint32_t flash_size = flash_get_size(&_flash);
+    uint32_t flash_start_addr = flash_get_start_address(&_flash);
+    uint32_t flash_end_addr = flash_start_addr + flash_size;
+    uint32_t erase_end_addr = addr + size;
 
-    if (!is_aligned_to_sector(addr, size)) {
+    if (erase_end_addr > flash_end_addr) {
         return -1;
+    } else if (erase_end_addr < flash_end_addr){
+        uint32_t following_sector_size = flash_get_sector_size(&_flash, erase_end_addr);
+        if (!is_aligned(erase_end_addr, following_sector_size)) {
+            return -1;
+        }
     }
 
     int32_t ret = 0;
@@ -132,10 +168,6 @@
             break;
         }
         current_sector_size = flash_get_sector_size(&_flash, addr);
-        if (!is_aligned_to_sector(addr, size)) {
-            ret = -1;
-            break;
-        }
         size -= current_sector_size;
         addr += current_sector_size;
     }

--- a/drivers/FlashIAP.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/FlashIAP.h	Thu Apr 19 17:12:19 2018 +0100
@@ -72,8 +72,8 @@
      *  The sectors must have been erased prior to being programmed
      *
      *  @param buffer Buffer of data to be written
-     *  @param addr   Address of a page to begin writing to, must be a multiple of program and sector sizes
-     *  @param size   Size to write in bytes, must be a multiple of program and sector sizes
+     *  @param addr   Address of a page to begin writing to
+     *  @param size   Size to write in bytes, must be a multiple of program size
      *  @return       0 on success, negative error code on failure
      */
     int program(const void *buffer, uint32_t addr, uint32_t size);
@@ -128,6 +128,7 @@
     bool is_aligned_to_sector(uint32_t addr, uint32_t size);
 
     flash_t _flash;
+    uint8_t *_page_buf;
     static SingletonPtr<PlatformMutex> _mutex;
 };
 

--- a/drivers/I2C.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/I2C.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -18,7 +18,7 @@
 #if DEVICE_I2C
 
 #if DEVICE_I2C_ASYNCH
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 #endif
 
 namespace mbed {
@@ -81,7 +81,7 @@
     return ret;
 }
 
-// read - Master Reciever Mode
+// read - Master Receiver Mode
 int I2C::read(int address, char* data, int length, bool repeated) {
     lock();
     aquire();

--- a/drivers/I2C.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/I2C.h	Thu Apr 19 17:12:19 2018 +0100
@@ -159,9 +159,9 @@
 
     /** Start non-blocking I2C transfer.
      *
-     * This function locks the deep sleep until any event has occured
+     * This function locks the deep sleep until any event has occurred
      * 
-     * @param address   8/10 bit I2c slave address
+     * @param address   8/10 bit I2C slave address
      * @param tx_buffer The TX buffer with data to be transfered
      * @param tx_length The length of TX buffer in bytes
      * @param rx_buffer The RX buffer which is used for received data

--- a/drivers/InterruptManager.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/InterruptManager.h	Thu Apr 19 17:12:19 2018 +0100
@@ -26,6 +26,7 @@
 /** \addtogroup drivers */
 
 /** Use this singleton if you need to chain interrupt handlers.
+ *  @deprecated Do not use this class. This class is not part of the public API of mbed-os and is being removed in the future.
  *
  * @note Synchronization level: Thread safe
  *
@@ -57,6 +58,8 @@
 class InterruptManager : private NonCopyable<InterruptManager> {
 public:
     /** Get the instance of InterruptManager Class
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
      *
      *  @return the only instance of this class
      */
@@ -65,12 +68,17 @@
     static InterruptManager* get();
 
     /** Destroy the current instance of the interrupt manager
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+     *
      */
     MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
         "public API of mbed-os and is being removed in the future.")
     static void destroy();
 
     /** Add a handler for an interrupt at the end of the handler list
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
      *
      *  @param function the handler to add
      *  @param irq interrupt number
@@ -86,6 +94,8 @@
     }
 
     /** Add a handler for an interrupt at the beginning of the handler list
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
      *
      *  @param function the handler to add
      *  @param irq interrupt number
@@ -101,6 +111,8 @@
     }
 
     /** Add a handler for an interrupt at the end of the handler list
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
      *
      *  @param tptr pointer to the object that has the handler function
      *  @param mptr pointer to the actual handler function
@@ -118,6 +130,8 @@
     }
 
     /** Add a handler for an interrupt at the beginning of the handler list
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
      *
      *  @param tptr pointer to the object that has the handler function
      *  @param mptr pointer to the actual handler function
@@ -135,6 +149,8 @@
     }
 
     /** Remove a handler from an interrupt
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
      *
      *  @param handler the function object for the handler to remove
      *  @param irq the interrupt number

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/MbedCRC.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stddef.h>
+#include "drivers/TableCRC.h"
+#include "drivers/MbedCRC.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+/** @{*/
+
+/* Default values for different types of polynomials
+*/
+template<>
+MbedCRC<POLY_32BIT_ANSI, 32>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
+        _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+        _crc_table((uint32_t *)Table_CRC_32bit_ANSI)
+{
+    mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_8BIT_CCITT, 8>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
+        _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+        _crc_table((uint32_t *)Table_CRC_8bit_CCITT)
+{
+    mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_7BIT_SD, 7>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
+        _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+        _crc_table((uint32_t *)Table_CRC_7Bit_SD)
+{
+    mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_16BIT_CCITT, 16>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
+        _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+        _crc_table((uint32_t *)Table_CRC_16bit_CCITT)
+{
+}
+
+template<>
+MbedCRC<POLY_16BIT_IBM, 16>::MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder):
+        _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data), _reflect_remainder(reflect_remainder),
+        _crc_table((uint32_t *)Table_CRC_16bit_IBM)
+{
+    mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_32BIT_ANSI, 32>::MbedCRC():
+    _initial_value(~(0x0)), _final_xor(~(0x0)), _reflect_data(true), _reflect_remainder(true),
+    _crc_table((uint32_t *)Table_CRC_32bit_ANSI)
+{
+    mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_16BIT_IBM, 16>::MbedCRC():
+    _initial_value(0), _final_xor(0), _reflect_data(true), _reflect_remainder(true),
+    _crc_table((uint32_t *)Table_CRC_16bit_IBM)
+{
+    mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_16BIT_CCITT, 16>::MbedCRC():
+    _initial_value(~(0x0)), _final_xor(0), _reflect_data(false), _reflect_remainder(false),
+    _crc_table((uint32_t *)Table_CRC_16bit_CCITT)
+{
+    mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_7BIT_SD, 7>::MbedCRC():
+    _initial_value(0), _final_xor(0), _reflect_data(false), _reflect_remainder(false),
+    _crc_table((uint32_t *)Table_CRC_7Bit_SD)
+{
+    mbed_crc_ctor();
+}
+
+template<>
+MbedCRC<POLY_8BIT_CCITT, 8>::MbedCRC():
+    _initial_value(0), _final_xor(0), _reflect_data(false), _reflect_remainder(false),
+    _crc_table((uint32_t *)Table_CRC_8bit_CCITT)
+{
+    mbed_crc_ctor();
+}
+
+/** @}*/
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/MbedCRC.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,425 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CRC_API_H
+#define MBED_CRC_API_H
+
+#include <stdint.h>
+#include "drivers/TableCRC.h"
+#include "platform/mbed_assert.h"
+
+/* This is invalid warning from the compiler for below section of code
+if ((width < 8) && (NULL == _crc_table)) {
+    p_crc = (uint32_t)(p_crc << (8 - width));
+}
+Compiler warns of the shift operation with width as it is width=(std::uint8_t),
+but we check for ( width < 8) before performing shift, so it should not be an issue.
+*/
+#if defined ( __CC_ARM )
+#pragma diag_suppress 62  // Shift count is negative
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wshift-count-negative"
+#endif
+
+namespace mbed {
+/** \addtogroup drivers */
+/** @{*/
+
+/** CRC Polynomial value
+ *
+ * Different polynomial values supported
+ */
+typedef enum crc_polynomial {
+    POLY_OTHER = 0,
+    POLY_8BIT_CCITT = 0x07,         // x8+x2+x+1
+    POLY_7BIT_SD = 0x9,             // x7+x3+1;
+    POLY_16BIT_CCITT = 0x1021,      // x16+x12+x5+1
+    POLY_16BIT_IBM = 0x8005,        // x16+x15+x2+1
+    POLY_32BIT_ANSI = 0x04C11DB7,    // x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
+} crc_polynomial_t;
+
+/** CRC object provides CRC generation through hardware/software
+ *
+ *  ROM polynomial tables for supported polynomials (:: crc_polynomial_t) will be used for
+ *  software CRC computation, if ROM tables are not available then CRC is computed runtime
+ *  bit by bit for all data input.
+ *
+ *  @tparam  polynomial CRC polynomial value in hex
+ *  @tparam  width CRC polynomial width
+ *
+ * Example: Compute CRC data
+ * @code
+ *
+ *  #include "mbed.h"
+ *
+ *  int main() {
+ *      MbedCRC<POLY_32BIT_ANSI, 32> ct;
+ *
+ *      char  test[] = "123456789";
+ *      uint32_t crc = 0;
+ *
+ *      printf("\nPolynomial = 0x%lx  Width = %d \n", ct.get_polynomial(), ct.get_width());
+ *
+ *      ct.compute((void *)test, strlen((const char*)test), &crc);
+ *
+ *      printf("The CRC of data \"123456789\" is : 0x%lx\n", crc);
+ *      return 0;
+ *  }
+ * @endcode
+ * Example: Compute CRC with data available in parts
+ * @code
+ *
+ *  #include "mbed.h"
+ *  int main() {
+ *      MbedCRC<POLY_32BIT_ANSI, 32> ct;
+ *
+ *      char  test[] = "123456789";
+ *      uint32_t crc = 0;
+ *
+ *      printf("\nPolynomial = 0x%lx  Width = %d \n", ct.get_polynomial(), ct.get_width());
+ *
+ *      ct.compute_partial_start(&crc);
+ *      ct.compute_partial((void *)&test, 4, &crc);
+ *      ct.compute_partial((void *)&test[4], 5, &crc);
+ *      ct.compute_partial_stop(&crc);
+ *
+ *      printf("The CRC of data \"123456789\" is : 0x%lx\n", crc);
+ *      return 0;
+ *  }
+ * @endcode
+ * @ingroup drivers
+ */
+
+template <uint32_t polynomial=POLY_32BIT_ANSI, uint8_t width=32>
+class MbedCRC
+{
+public:
+    typedef uint64_t crc_data_size_t;
+
+    /** Lifetime of CRC object
+     *
+     *  @param  initial_xor  Inital value/seed to Xor
+     *  @param  final_xor  Final Xor value
+     *  @param  reflect_data
+     *  @param  reflect_remainder
+*  @note   Default constructor without any arguments is valid only for supported CRC polynomials. :: crc_polynomial_t
+     *          MbedCRC <POLY_7BIT_SD, 7> ct; --- Valid POLY_7BIT_SD
+     *          MbedCRC <0x1021, 16> ct; --- Valid POLY_16BIT_CCITT
+     *          MbedCRC <POLY_16BIT_CCITT, 32> ct; --- Invalid, compilation error
+     *          MbedCRC <POLY_16BIT_CCITT, 32> ct (i,f,rd,rr) Consturctor can be used for not supported polynomials
+     *          MbedCRC<POLY_16BIT_CCITT, 16> sd(0, 0, false, false); Constructor can also be used for supported
+     *             polynomials with different intial/final/reflect values
+     *
+     */
+    MbedCRC(uint32_t initial_xor, uint32_t final_xor, bool reflect_data, bool reflect_remainder) :
+                    _initial_value(initial_xor), _final_xor(final_xor), _reflect_data(reflect_data),
+                    _reflect_remainder(reflect_remainder), _crc_table(NULL)
+    {
+        mbed_crc_ctor();
+    }
+    MbedCRC();
+    virtual ~MbedCRC()
+    {
+        // Do nothing
+    }
+
+    /** Compute CRC for the data input
+     *
+     *  @param  buffer  Data bytes
+     *  @param  size  Size of data
+     *  @param  crc  CRC is the output value
+     *  @return  0 on success, negative error code on failure
+     */
+    int32_t compute(void *buffer, crc_data_size_t size, uint32_t *crc)
+    {
+        MBED_ASSERT(crc != NULL);
+        int32_t status;
+        if (0 != (status = compute_partial_start(crc))) {
+            *crc = 0;
+            return status;
+        }
+        if (0 != (status = compute_partial(buffer, size, crc))) {
+            *crc = 0;
+            return status;
+        }
+        if (0 != (status = compute_partial_stop(crc))) {
+            *crc = 0;
+            return status;
+        }
+        return 0;
+    }
+
+    /** Compute partial CRC for the data input.
+     *
+     *  CRC data if not available fully, CRC can be computed in parts with available data.
+     *  Previous CRC output should be passed as argument to the current compute_partial call.
+     *  @pre: Call \ref compute_partial_start to start the partial CRC calculation.
+     *  @post: Call \ref compute_partial_stop to get the final CRC value.
+     *
+     *  @param  buffer  Data bytes
+     *  @param  size  Size of data
+     *  @param  crc  CRC value is intermediate CRC value filled by API.
+     *  @return  0  on success or a negative error code on failure
+     *  @note: CRC as output in compute_partial is not final CRC value, call @ref compute_partial_stop
+     *         to get final correct CRC value.
+     */
+    int32_t compute_partial(void *buffer, crc_data_size_t size, uint32_t *crc)
+    {
+        if (NULL == _crc_table) {
+            // Compute bitwise CRC
+            return bitwise_compute_partial(buffer, size, crc);
+        } else {
+            // Table CRC
+            return table_compute_partial(buffer, size, crc);
+        }
+    }
+
+    /** Compute partial start, indicate start of partial computation
+     *
+     *  This API should be called before performing any partial computation
+     *  with compute_partial API.
+     *
+     *  @param  crc  Initial CRC value set by the API
+     *  @return  0  on success or a negative in case of failure
+     *  @note: CRC is an out parameter and must be reused with compute_partial
+     *         and compute_partial_stop without any modifications in application.
+     */
+    int32_t compute_partial_start(uint32_t *crc)
+    {
+        MBED_ASSERT(crc != NULL);
+        *crc = _initial_value;
+        return 0;
+    }
+
+    /** Get the final CRC value of partial computation.
+     *
+     *  CRC value available in partial computation is not correct CRC, as some
+     *  algorithms require remainder to be reflected and final value to be XORed
+     *  This API is used to perform final computation to get correct CRC value.
+     *
+     *  @param crc  CRC result
+     */
+    int32_t compute_partial_stop(uint32_t *crc)
+    {
+        MBED_ASSERT(crc != NULL);
+        uint32_t p_crc = *crc;
+        if ((width < 8) && (NULL == _crc_table)) {
+            p_crc = (uint32_t)(p_crc << (8 - width));
+        }
+        *crc = (reflect_remainder(p_crc) ^ _final_xor) & get_crc_mask();
+        return 0;
+    }
+
+    /** Get the current CRC polynomial
+     *
+     * @return  Polynomial value
+     */
+    uint32_t get_polynomial(void) const
+    {
+        return polynomial;
+    }
+
+    /** Get the current CRC width
+     *
+     * @return  CRC width
+     */
+    uint8_t get_width(void) const
+    {
+        return width;
+    }
+
+private:
+    uint32_t _initial_value;
+    uint32_t _final_xor;
+    bool _reflect_data;
+    bool _reflect_remainder;
+    uint32_t *_crc_table;
+
+    /** Get the current CRC data size
+     *
+     * @return  CRC data size in bytes
+     */
+    uint8_t get_data_size(void) const
+    {
+        return (width <= 8 ? 1 : (width <= 16 ? 2 : 4));
+    }
+
+    /** Get the top bit of current CRC
+     *
+     * @return  Top bit is set high for respective data width of current CRC
+     *          Top bit for CRC width less then 8 bits will be set as 8th bit.
+     */
+    uint32_t get_top_bit(void) const
+    {
+        return (width < 8 ? (1u << 7) : (uint32_t)(1ul << (width - 1)));
+    }
+
+    /** Get the CRC data mask
+     *
+     * @return  CRC data mask is generated based on current CRC width
+     */
+    uint32_t get_crc_mask(void) const
+    {
+        return (width < 8 ? ((1u << 8) - 1) : (uint32_t)((uint64_t)(1ull << width) - 1));
+    }
+
+    /** Final value of CRC is reflected
+     *
+     * @param  data final crc value, which should be reflected
+     * @return  Reflected CRC value
+     */
+    uint32_t reflect_remainder(uint32_t data) const
+    {
+        if (_reflect_remainder) {
+            uint32_t reflection = 0x0;
+            uint8_t const nBits = (width < 8 ? 8 : width);
+
+            for (uint8_t bit = 0; bit < nBits; ++bit) {
+                if (data & 0x01) {
+                    reflection |= (1 << ((nBits - 1) - bit));
+                }
+                data = (data >> 1);
+            }
+            return (reflection);
+        } else {
+            return data;
+        }
+    }
+
+    /** Data bytes are reflected
+     *
+     * @param  data value to be reflected
+     * @return  Reflected data value
+     */
+    uint32_t reflect_bytes(uint32_t data) const
+    {
+        if(_reflect_data) {
+            uint32_t reflection = 0x0;
+
+            for (uint8_t bit = 0; bit < 8; ++bit) {
+                if (data & 0x01) {
+                    reflection |= (1 << (7 - bit));
+                }
+                data = (data >> 1);
+            }
+            return (reflection);
+        } else {
+            return data;
+        }
+    }
+
+    /** Bitwise CRC computation
+     *
+     * @param  buffer  data buffer
+     * @param  size  size of the data
+     * @param  crc  CRC value is filled in, but the value is not the final
+     * @return  0  on success or a negative error code on failure
+     */
+    int32_t bitwise_compute_partial(const void *buffer, crc_data_size_t size, uint32_t *crc) const
+    {
+        MBED_ASSERT(crc != NULL);
+        MBED_ASSERT(buffer != NULL);
+
+        const uint8_t *data = static_cast<const uint8_t *>(buffer);
+        uint32_t p_crc = *crc;
+
+        if (width < 8) {
+            uint8_t data_byte;
+            for (crc_data_size_t byte = 0; byte < size; byte++) {
+                data_byte = reflect_bytes(data[byte]);
+                for (uint8_t bit = 8; bit > 0; --bit) {
+                    p_crc <<= 1;
+                    if (( data_byte ^ p_crc) & get_top_bit()) {
+                        p_crc ^= polynomial;
+                    }
+                    data_byte <<= 1;
+                }
+            }
+        } else {
+            for (crc_data_size_t byte = 0; byte < size; byte++) {
+                p_crc ^= (reflect_bytes(data[byte]) << (width - 8));
+
+                // Perform modulo-2 division, a bit at a time
+                for (uint8_t bit = 8; bit > 0; --bit) {
+                    if (p_crc & get_top_bit()) {
+                        p_crc = (p_crc << 1) ^ polynomial;
+                    } else {
+                        p_crc = (p_crc << 1);
+                    }
+                }
+            }
+        }
+        *crc = p_crc & get_crc_mask();
+        return 0;
+    }
+
+     /** CRC computation using ROM tables
+     *
+     * @param  buffer  data buffer
+     * @param  size  size of the data
+     * @param  crc  CRC value is filled in, but the value is not the final
+     * @return  0  on success or a negative error code on failure
+     */
+    int32_t table_compute_partial(const void *buffer, crc_data_size_t size, uint32_t *crc) const
+    {
+        MBED_ASSERT(crc != NULL);
+        MBED_ASSERT(buffer != NULL);
+
+        const uint8_t *data = static_cast<const uint8_t *>(buffer);
+        uint32_t p_crc = *crc;
+        uint8_t data_byte = 0;
+
+        if (width <= 8) {
+            uint8_t *crc_table = (uint8_t *)_crc_table;
+            for (crc_data_size_t byte = 0; byte < size; byte++) {
+                data_byte = reflect_bytes(data[byte]) ^ p_crc;
+                p_crc = crc_table[data_byte];
+            }
+        } else if (width <= 16) {
+            uint16_t *crc_table = (uint16_t *)_crc_table;
+            for (crc_data_size_t byte = 0; byte < size; byte++) {
+                data_byte = reflect_bytes(data[byte]) ^ (p_crc >> (width - 8));
+                p_crc = crc_table[data_byte] ^ (p_crc << 8);
+            }
+        } else {
+            uint32_t *crc_table = (uint32_t *)_crc_table;
+            for (crc_data_size_t byte = 0; byte < size; byte++) {
+                data_byte = reflect_bytes(data[byte]) ^ (p_crc >> (width - 8));
+                p_crc = crc_table[data_byte] ^ (p_crc << 8);
+            }
+        }
+        *crc = p_crc & get_crc_mask();
+        return 0;
+    }
+
+    /** Constructor init called from all specialized cases of constructor
+     *  Note: All construtor common code should be in this function.
+     */
+    void mbed_crc_ctor(void) const
+    {
+        MBED_STATIC_ASSERT(width <= 32, "Max 32-bit CRC supported");
+    }
+};
+
+#if   defined ( __CC_ARM )
+#elif defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+/** @}*/
+} // namespace mbed
+
+#endif

--- a/drivers/PwmOut.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/PwmOut.h	Thu Apr 19 17:12:19 2018 +0100
@@ -21,7 +21,7 @@
 #if defined (DEVICE_PWMOUT) || defined(DOXYGEN_ONLY)
 #include "hal/pwmout_api.h"
 #include "platform/mbed_critical.h"
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 
 namespace mbed {
 /** \addtogroup drivers */

--- a/drivers/RawSerial.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/RawSerial.h	Thu Apr 19 17:12:19 2018 +0100
@@ -68,7 +68,7 @@
      *
      * @param c The char to write
      *
-     * @returns The written char or -1 if an error occured
+     * @returns The written char or -1 if an error occurred
      */
     int putc(int c);
 

--- a/drivers/SPI.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/SPI.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -17,7 +17,7 @@
 #include "platform/mbed_critical.h"
 
 #if DEVICE_SPI_ASYNCH
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 #endif
 
 #if DEVICE_SPI
@@ -49,8 +49,8 @@
     lock();
     _bits = bits;
     _mode = mode;
-    // If changing format while you are the owner than just
-    // update format, but if owner is changed than even frequency should be
+    // If changing format while you are the owner then just
+    // update format, but if owner is changed then even frequency should be
     // updated which is done by acquire.
     if (_owner == this) {
         spi_format(&_spi, _bits, _mode, 0);
@@ -63,8 +63,8 @@
 void SPI::frequency(int hz) {
     lock();
     _hz = hz;
-    // If changing format while you are the owner than just
-    // update frequency, but if owner is changed than even frequency should be
+    // If changing format while you are the owner then just
+    // update frequency, but if owner is changed then even frequency should be
     // updated which is done by acquire.
     if (_owner == this) {
         spi_frequency(&_spi, _hz);
@@ -77,7 +77,7 @@
 SPI* SPI::_owner = NULL;
 SingletonPtr<PlatformMutex> SPI::_mutex;
 
-// ignore the fact there are multiple physical spis, and always update if it wasnt us last
+// ignore the fact there are multiple physical spis, and always update if it wasn't us last
 void SPI::aquire() {
     lock();
      if (_owner != this) {
@@ -252,7 +252,7 @@
     }
 #if TRANSACTION_QUEUE_SIZE_SPI
     if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
-        // SPI peripheral is free (event happend), dequeue transaction
+        // SPI peripheral is free (event happened), dequeue transaction
         dequeue_transaction();
     }
 #endif

--- a/drivers/SPI.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/SPI.h	Thu Apr 19 17:12:19 2018 +0100
@@ -79,7 +79,7 @@
 
     /** Create a SPI master connected to the specified pins
      *
-     *  mosi or miso can be specfied as NC if not used
+     *  mosi or miso can be specified as NC if not used
      *
      *  @param mosi SPI Master Out, Slave In pin
      *  @param miso SPI Master In, Slave Out pin
@@ -121,7 +121,7 @@
 
     /** Write to the SPI Slave and obtain the response
      *
-     *  The total number of bytes sent and recieved will be the maximum of
+     *  The total number of bytes sent and received will be the maximum of
      *  tx_length and rx_length. The bytes written will be padded with the
      *  value 0xff.
      *
@@ -156,7 +156,7 @@
 
     /** Start non-blocking SPI transfer using 8bit buffers.
      *
-     * This function locks the deep sleep until any event has occured
+     * This function locks the deep sleep until any event has occurred
      * 
      * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
      *                  the default SPI value is sent

--- a/drivers/SPISlave.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/SPISlave.h	Thu Apr 19 17:12:19 2018 +0100
@@ -59,7 +59,7 @@
 
     /** Create a SPI slave connected to the specified pins
      *
-     *  mosi or miso can be specfied as NC if not used
+     *  mosi or miso can be specified as NC if not used
      *
      *  @param mosi SPI Master Out, Slave In pin
      *  @param miso SPI Master In, Slave Out pin

--- a/drivers/SerialBase.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/SerialBase.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -16,7 +16,7 @@
 #include "drivers/SerialBase.h"
 #include "platform/mbed_wait_api.h"
 #include "platform/mbed_critical.h"
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 
 #if DEVICE_SERIAL
 

--- a/drivers/SerialBase.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/SerialBase.h	Thu Apr 19 17:12:19 2018 +0100
@@ -167,7 +167,7 @@
 
     /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
      *
-     *  This function locks the deep sleep until any event has occured
+     *  This function locks the deep sleep until any event has occurred
      * 
      *  @param buffer   The buffer where received data will be stored
      *  @param length   The buffer length in bytes
@@ -178,7 +178,7 @@
 
     /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
      *
-     *  This function locks the deep sleep until any event has occured
+     *  This function locks the deep sleep until any event has occurred
      * 
      *  @param buffer   The buffer where received data will be stored
      *  @param length   The buffer length in bytes
@@ -193,7 +193,7 @@
 
     /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
      *
-     *  This function locks the deep sleep until any event has occured
+     *  This function locks the deep sleep until any event has occurred
      * 
      *  @param buffer     The buffer where received data will be stored
      *  @param length     The buffer length in bytes
@@ -205,7 +205,7 @@
 
     /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
      *
-     *  This function locks the deep sleep until any event has occured
+     *  This function locks the deep sleep until any event has occurred
      * 
      *  @param buffer     The buffer where received data will be stored
      *  @param length     The buffer length in bytes

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/SerialWireOutput.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(DEVICE_ITM)
+
+#include "hal/itm_api.h"
+#include "platform/FileHandle.h"
+
+class SerialWireOutput : public FileHandle {
+public:
+    SerialWireOutput(void)
+    {
+        /* Initialize ITM using internal init function. */
+        mbed_itm_init();
+    }
+
+    virtual ssize_t write(const void *buffer, size_t size)
+    {
+        const unsigned char *buf = static_cast<const unsigned char *>(buffer);
+
+        /* Send buffer one character at a time over the ITM SWO port */
+        for (size_t i = 0; i < size; i++) {
+            mbed_itm_send(ITM_PORT_SWO, buf[i]);
+        }
+        return size;
+    }
+
+    virtual ssize_t read(void *buffer, size_t size)
+    {
+        /* Reading is not supported by this file handle */
+        return -EBADF;
+    }
+
+    virtual off_t seek(off_t offset, int whence = SEEK_SET)
+    {
+        /* Seeking is not support by this file handler */
+        return -ESPIPE;
+    }
+
+    virtual off_t size()
+    {
+        /* Size is not defined for this file handle */
+        return -EINVAL;
+    }
+
+    virtual int isatty()
+    {
+        /* File handle is used for terminal output */
+        return true;
+    }
+
+    virtual int close()
+    {
+        return 0;
+    }
+};
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/TableCRC.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,147 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <stdint.h>
+#include "drivers/TableCRC.h"
+
+namespace mbed {
+/** \addtogroup drivers */
+/** @{*/
+
+extern const uint8_t Table_CRC_7Bit_SD[MBED_CRC_TABLE_SIZE] = {
+    0x0,  0x12, 0x24, 0x36, 0x48, 0x5a, 0x6c, 0x7e, 0x90, 0x82, 0xb4, 0xa6, 0xd8, 0xca, 0xfc, 0xee,
+    0x32, 0x20, 0x16, 0x4,  0x7a, 0x68, 0x5e, 0x4c, 0xa2, 0xb0, 0x86, 0x94, 0xea, 0xf8, 0xce, 0xdc,
+    0x64, 0x76, 0x40, 0x52, 0x2c, 0x3e, 0x8,  0x1a, 0xf4, 0xe6, 0xd0, 0xc2, 0xbc, 0xae, 0x98, 0x8a,
+    0x56, 0x44, 0x72, 0x60, 0x1e, 0xc,  0x3a, 0x28, 0xc6, 0xd4, 0xe2, 0xf0, 0x8e, 0x9c, 0xaa, 0xb8,
+    0xc8, 0xda, 0xec, 0xfe, 0x80, 0x92, 0xa4, 0xb6, 0x58, 0x4a, 0x7c, 0x6e, 0x10, 0x2,  0x34, 0x26,
+    0xfa, 0xe8, 0xde, 0xcc, 0xb2, 0xa0, 0x96, 0x84, 0x6a, 0x78, 0x4e, 0x5c, 0x22, 0x30, 0x6,  0x14,
+    0xac, 0xbe, 0x88, 0x9a, 0xe4, 0xf6, 0xc0, 0xd2, 0x3c, 0x2e, 0x18, 0xa,  0x74, 0x66, 0x50, 0x42,
+    0x9e, 0x8c, 0xba, 0xa8, 0xd6, 0xc4, 0xf2, 0xe0, 0xe,  0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 0x70,
+    0x82, 0x90, 0xa6, 0xb4, 0xca, 0xd8, 0xee, 0xfc, 0x12, 0x0,  0x36, 0x24, 0x5a, 0x48, 0x7e, 0x6c,
+    0xb0, 0xa2, 0x94, 0x86, 0xf8, 0xea, 0xdc, 0xce, 0x20, 0x32, 0x4,  0x16, 0x68, 0x7a, 0x4c, 0x5e,
+    0xe6, 0xf4, 0xc2, 0xd0, 0xae, 0xbc, 0x8a, 0x98, 0x76, 0x64, 0x52, 0x40, 0x3e, 0x2c, 0x1a, 0x8,
+    0xd4, 0xc6, 0xf0, 0xe2, 0x9c, 0x8e, 0xb8, 0xaa, 0x44, 0x56, 0x60, 0x72, 0xc,  0x1e, 0x28, 0x3a,
+    0x4a, 0x58, 0x6e, 0x7c, 0x2,  0x10, 0x26, 0x34, 0xda, 0xc8, 0xfe, 0xec, 0x92, 0x80, 0xb6, 0xa4,
+    0x78, 0x6a, 0x5c, 0x4e, 0x30, 0x22, 0x14, 0x6,  0xe8, 0xfa, 0xcc, 0xde, 0xa0, 0xb2, 0x84, 0x96,
+    0x2e, 0x3c, 0xa,  0x18, 0x66, 0x74, 0x42, 0x50, 0xbe, 0xac, 0x9a, 0x88, 0xf6, 0xe4, 0xd2, 0xc0,
+    0x1c, 0xe,  0x38, 0x2a, 0x54, 0x46, 0x70, 0x62, 0x8c, 0x9e, 0xa8, 0xba, 0xc4, 0xd6, 0xe0, 0xf2
+};
+
+extern const uint8_t Table_CRC_8bit_CCITT[MBED_CRC_TABLE_SIZE] = {
+    0x0,  0x7,  0xe,  0x9,  0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d,
+    0x70, 0x77, 0x7e, 0x79, 0x6c, 0x6b, 0x62, 0x65, 0x48, 0x4f, 0x46, 0x41, 0x54, 0x53, 0x5a, 0x5d,
+    0xe0, 0xe7, 0xee, 0xe9, 0xfc, 0xfb, 0xf2, 0xf5, 0xd8, 0xdf, 0xd6, 0xd1, 0xc4, 0xc3, 0xca, 0xcd,
+    0x90, 0x97, 0x9e, 0x99, 0x8c, 0x8b, 0x82, 0x85, 0xa8, 0xaf, 0xa6, 0xa1, 0xb4, 0xb3, 0xba, 0xbd,
+    0xc7, 0xc0, 0xc9, 0xce, 0xdb, 0xdc, 0xd5, 0xd2, 0xff, 0xf8, 0xf1, 0xf6, 0xe3, 0xe4, 0xed, 0xea,
+    0xb7, 0xb0, 0xb9, 0xbe, 0xab, 0xac, 0xa5, 0xa2, 0x8f, 0x88, 0x81, 0x86, 0x93, 0x94, 0x9d, 0x9a,
+    0x27, 0x20, 0x29, 0x2e, 0x3b, 0x3c, 0x35, 0x32, 0x1f, 0x18, 0x11, 0x16, 0x3,  0x4,  0xd,  0xa,
+    0x57, 0x50, 0x59, 0x5e, 0x4b, 0x4c, 0x45, 0x42, 0x6f, 0x68, 0x61, 0x66, 0x73, 0x74, 0x7d, 0x7a,
+    0x89, 0x8e, 0x87, 0x80, 0x95, 0x92, 0x9b, 0x9c, 0xb1, 0xb6, 0xbf, 0xb8, 0xad, 0xaa, 0xa3, 0xa4,
+    0xf9, 0xfe, 0xf7, 0xf0, 0xe5, 0xe2, 0xeb, 0xec, 0xc1, 0xc6, 0xcf, 0xc8, 0xdd, 0xda, 0xd3, 0xd4,
+    0x69, 0x6e, 0x67, 0x60, 0x75, 0x72, 0x7b, 0x7c, 0x51, 0x56, 0x5f, 0x58, 0x4d, 0x4a, 0x43, 0x44,
+    0x19, 0x1e, 0x17, 0x10, 0x5,  0x2,  0xb,  0xc,  0x21, 0x26, 0x2f, 0x28, 0x3d, 0x3a, 0x33, 0x34,
+    0x4e, 0x49, 0x40, 0x47, 0x52, 0x55, 0x5c, 0x5b, 0x76, 0x71, 0x78, 0x7f, 0x6a, 0x6d, 0x64, 0x63,
+    0x3e, 0x39, 0x30, 0x37, 0x22, 0x25, 0x2c, 0x2b, 0x6,  0x1,  0x8,  0xf,  0x1a, 0x1d, 0x14, 0x13,
+    0xae, 0xa9, 0xa0, 0xa7, 0xb2, 0xb5, 0xbc, 0xbb, 0x96, 0x91, 0x98, 0x9f, 0x8a, 0x8d, 0x84, 0x83,
+    0xde, 0xd9, 0xd0, 0xd7, 0xc2, 0xc5, 0xcc, 0xcb, 0xe6, 0xe1, 0xe8, 0xef, 0xfa, 0xfd, 0xf4, 0xf3
+};
+
+extern const uint16_t Table_CRC_16bit_CCITT[MBED_CRC_TABLE_SIZE] = {
+    0x0,    0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, 0x8108, 0x9129, 0xa14a, 0xb16b,
+    0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, 0x1231, 0x210,  0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
+    0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, 0x2462, 0x3443, 0x420,  0x1401,
+    0x64e6, 0x74c7, 0x44a4, 0x5485, 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
+    0x3653, 0x2672, 0x1611, 0x630,  0x76d7, 0x66f6, 0x5695, 0x46b4, 0xb75b, 0xa77a, 0x9719, 0x8738,
+    0xf7df, 0xe7fe, 0xd79d, 0xc7bc, 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x840,  0x1861, 0x2802, 0x3823,
+    0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, 0x5af5, 0x4ad4, 0x7ab7, 0x6a96,
+    0x1a71, 0xa50,  0x3a33, 0x2a12, 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
+    0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0xc60,  0x1c41, 0xedae, 0xfd8f, 0xcdec, 0xddcd,
+    0xad2a, 0xbd0b, 0x8d68, 0x9d49, 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0xe70,
+    0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, 0x9188, 0x81a9, 0xb1ca, 0xa1eb,
+    0xd10c, 0xc12d, 0xf14e, 0xe16f, 0x1080, 0xa1,   0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
+    0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, 0x2b1,  0x1290, 0x22f3, 0x32d2,
+    0x4235, 0x5214, 0x6277, 0x7256, 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
+    0x34e2, 0x24c3, 0x14a0, 0x481,  0x7466, 0x6447, 0x5424, 0x4405, 0xa7db, 0xb7fa, 0x8799, 0x97b8,
+    0xe75f, 0xf77e, 0xc71d, 0xd73c, 0x26d3, 0x36f2, 0x691,  0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
+    0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, 0x5844, 0x4865, 0x7806, 0x6827,
+    0x18c0, 0x8e1,  0x3882, 0x28a3, 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
+    0x4a75, 0x5a54, 0x6a37, 0x7a16, 0xaf1,  0x1ad0, 0x2ab3, 0x3a92, 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d,
+    0xbdaa, 0xad8b, 0x9de8, 0x8dc9, 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0xcc1,
+    0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, 0x6e17, 0x7e36, 0x4e55, 0x5e74,
+    0x2e93, 0x3eb2, 0x0ed1, 0x1ef0
+};
+
+extern const uint16_t Table_CRC_16bit_IBM[MBED_CRC_TABLE_SIZE] = {
+    0x0,    0x8005, 0x800f, 0xa,    0x801b, 0x1e,   0x14,   0x8011, 0x8033, 0x36,   0x3c,   0x8039,
+    0x28,   0x802d, 0x8027, 0x22,   0x8063, 0x66,   0x6c,   0x8069, 0x78,   0x807d, 0x8077, 0x72,
+    0x50,   0x8055, 0x805f, 0x5a,   0x804b, 0x4e,   0x44,   0x8041, 0x80c3, 0xc6,   0xcc,   0x80c9,
+    0xd8,   0x80dd, 0x80d7, 0xd2,   0xf0,   0x80f5, 0x80ff, 0xfa,   0x80eb, 0xee,   0xe4,   0x80e1,
+    0xa0,   0x80a5, 0x80af, 0xaa,   0x80bb, 0xbe,   0xb4,   0x80b1, 0x8093, 0x96,   0x9c,   0x8099,
+    0x88,   0x808d, 0x8087, 0x82,   0x8183, 0x186,  0x18c,  0x8189, 0x198,  0x819d, 0x8197, 0x192,
+    0x1b0,  0x81b5, 0x81bf, 0x1ba,  0x81ab, 0x1ae,  0x1a4,  0x81a1, 0x1e0,  0x81e5, 0x81ef, 0x1ea,
+    0x81fb, 0x1fe,  0x1f4,  0x81f1, 0x81d3, 0x1d6,  0x1dc,  0x81d9, 0x1c8,  0x81cd, 0x81c7, 0x1c2,
+    0x140,  0x8145, 0x814f, 0x14a,  0x815b, 0x15e,  0x154,  0x8151, 0x8173, 0x176,  0x17c,  0x8179,
+    0x168,  0x816d, 0x8167, 0x162,  0x8123, 0x126,  0x12c,  0x8129, 0x138,  0x813d, 0x8137, 0x132,
+    0x110,  0x8115, 0x811f, 0x11a,  0x810b, 0x10e,  0x104,  0x8101, 0x8303, 0x306,  0x30c,  0x8309,
+    0x318,  0x831d, 0x8317, 0x312,  0x330,  0x8335, 0x833f, 0x33a,  0x832b, 0x32e,  0x324,  0x8321,
+    0x360,  0x8365, 0x836f, 0x36a,  0x837b, 0x37e,  0x374,  0x8371, 0x8353, 0x356,  0x35c,  0x8359,
+    0x348,  0x834d, 0x8347, 0x342,  0x3c0,  0x83c5, 0x83cf, 0x3ca,  0x83db, 0x3de,  0x3d4,  0x83d1,
+    0x83f3, 0x3f6,  0x3fc,  0x83f9, 0x3e8,  0x83ed, 0x83e7, 0x3e2,  0x83a3, 0x3a6,  0x3ac,  0x83a9,
+    0x3b8,  0x83bd, 0x83b7, 0x3b2,  0x390,  0x8395, 0x839f, 0x39a,  0x838b, 0x38e,  0x384,  0x8381,
+    0x280,  0x8285, 0x828f, 0x28a,  0x829b, 0x29e,  0x294,  0x8291, 0x82b3, 0x2b6,  0x2bc,  0x82b9,
+    0x2a8,  0x82ad, 0x82a7, 0x2a2,  0x82e3, 0x2e6,  0x2ec,  0x82e9, 0x2f8,  0x82fd, 0x82f7, 0x2f2,
+    0x2d0,  0x82d5, 0x82df, 0x2da,  0x82cb, 0x2ce,  0x2c4,  0x82c1, 0x8243, 0x246,  0x24c,  0x8249,
+    0x258,  0x825d, 0x8257, 0x252,  0x270,  0x8275, 0x827f, 0x27a,  0x826b, 0x26e,  0x264,  0x8261,
+    0x220,  0x8225, 0x822f, 0x22a,  0x823b, 0x23e,  0x234,  0x8231, 0x8213, 0x216,  0x21c,  0x8219
+};
+
+extern const uint32_t Table_CRC_32bit_ANSI[MBED_CRC_TABLE_SIZE] = {
+    0x0,        0x4c11db7,  0x9823b6e,  0xd4326d9,  0x130476dc, 0x17c56b6b, 0x1a864db2, 0x1e475005,
+    0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61, 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd,
+    0x4c11db70, 0x48d0c6c7, 0x4593e01e, 0x4152fda9, 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75,
+    0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, 0x791d4014, 0x7ddc5da3, 0x709f7b7a, 0x745e66cd,
+    0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039, 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5,
+    0xbe2b5b58, 0xbaea46ef, 0xb7a96036, 0xb3687d81, 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d,
+    0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, 0xc7361b4c, 0xc3f706fb, 0xceb42022, 0xca753d95,
+    0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1, 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d,
+    0x34867077, 0x30476dc0, 0x3d044b19, 0x39c556ae, 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072,
+    0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, 0x18aeb13,  0x54bf6a4,  0x808d07d,  0xcc9cdca,
+    0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde, 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02,
+    0x5e9f46bf, 0x5a5e5b08, 0x571d7dd1, 0x53dc6066, 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba,
+    0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, 0xbfa1b04b, 0xbb60adfc, 0xb6238b25, 0xb2e29692,
+    0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6, 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a,
+    0xe0b41de7, 0xe4750050, 0xe9362689, 0xedf73b3e, 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2,
+    0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, 0xd5b88683, 0xd1799b34, 0xdc3abded, 0xd8fba05a,
+    0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637, 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb,
+    0x4f040d56, 0x4bc510e1, 0x46863638, 0x42472b8f, 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53,
+    0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, 0x36194d42, 0x32d850f5, 0x3f9b762c, 0x3b5a6b9b,
+    0x315d626,  0x7d4cb91,  0xa97ed48,  0xe56f0ff,  0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623,
+    0xf12f560e, 0xf5ee4bb9, 0xf8ad6d60, 0xfc6c70d7, 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b,
+    0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, 0xc423cd6a, 0xc0e2d0dd, 0xcda1f604, 0xc960ebb3,
+    0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7, 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b,
+    0x9b3660c6, 0x9ff77d71, 0x92b45ba8, 0x9675461f, 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3,
+    0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, 0x4e8ee645, 0x4a4ffbf2, 0x470cdd2b, 0x43cdc09c,
+    0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8, 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24,
+    0x119b4be9, 0x155a565e, 0x18197087, 0x1cd86d30, 0x29f3d35,  0x65e2082,  0xb1d065b,  0xfdc1bec,
+    0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, 0x2497d08d, 0x2056cd3a, 0x2d15ebe3, 0x29d4f654,
+    0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0, 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c,
+    0xe3a1cbc1, 0xe760d676, 0xea23f0af, 0xeee2ed18, 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4,
+    0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, 0x9abc8bd5, 0x9e7d9662, 0x933eb0bb, 0x97ffad0c,
+    0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668, 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4
+};
+
+/** @}*/
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/TableCRC.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,37 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TABLE_CRC_H
+#define TABLE_CRC_H
+
+#include <stdint.h>
+
+namespace mbed {
+/** \addtogroup drivers */
+/** @{*/
+
+#define MBED_CRC_TABLE_SIZE     256
+
+extern const uint8_t Table_CRC_7Bit_SD[MBED_CRC_TABLE_SIZE];
+extern const uint8_t Table_CRC_8bit_CCITT[MBED_CRC_TABLE_SIZE];
+extern const uint16_t Table_CRC_16bit_CCITT[MBED_CRC_TABLE_SIZE];
+extern const uint16_t Table_CRC_16bit_IBM[MBED_CRC_TABLE_SIZE];
+extern const uint32_t Table_CRC_32bit_ANSI[MBED_CRC_TABLE_SIZE];
+
+/** @}*/
+} // namespace mbed
+
+#endif

--- a/drivers/Ticker.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/Ticker.h	Thu Apr 19 17:12:19 2018 +0100
@@ -20,7 +20,7 @@
 #include "platform/Callback.h"
 #include "platform/mbed_toolchain.h"
 #include "platform/NonCopyable.h"
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 #include "hal/lp_ticker_api.h"
 #include "platform/mbed_critical.h"
 
@@ -71,7 +71,6 @@
 
     // When low power ticker is in use, then do not disable deep-sleep.
     Ticker(const ticker_data_t *data) : TimerEvent(data), _function(0), _lock_deepsleep(true)  {
-        data->interface->init();
 #if DEVICE_LOWPOWERTIMER
         _lock_deepsleep = (data != get_lp_ticker_data());
 #endif

--- a/drivers/Timeout.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/Timeout.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -18,7 +18,9 @@
 namespace mbed {
 
 void Timeout::handler() {
-    _function.call();
+    Callback<void()> local = _function;
+    detach();
+    local.call();
 }
 
 } // namespace mbed

--- a/drivers/Timeout.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/Timeout.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,7 +18,7 @@
 
 #include "drivers/Ticker.h"
 #include "platform/NonCopyable.h"
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 
 namespace mbed {
 /** \addtogroup drivers */

--- a/drivers/Timer.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/drivers/Timer.h	Thu Apr 19 17:12:19 2018 +0100
@@ -19,7 +19,7 @@
 #include "platform/platform.h"
 #include "hal/ticker_api.h"
 #include "platform/NonCopyable.h"
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 
 namespace mbed {
 /** \addtogroup drivers */

--- a/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/hal/TARGET_FLASH_CMSIS_ALGO/flash_data.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,35 +18,44 @@
 
 #include <stdint.h>
 
-// Target flash algorithm structure
+/** Target flash algorithm structure
+ */
 typedef struct {
-    const uint32_t init;
-    const uint32_t uninit;
-    const uint32_t erase_sector;
-    const uint32_t program_page;
-    const uint32_t static_base;
-    uint32_t *algo_blob;
+    const uint32_t init; /**< Init function address */
+    const uint32_t uninit; /**< Uninit function address */
+    const uint32_t erase_sector; /**< Erase sector function address */
+    const uint32_t program_page; /**< Program page function address */
+    const uint32_t static_base; /**< Static base address */
+    uint32_t *algo_blob; /**< Pointer to flash algo binary blob */
 } flash_algo_t;
 
+/** Sector information structure
+ */
 typedef struct {
-    const uint32_t start;
-    const uint32_t size;
+    const uint32_t start; /**< Sector start address */
+    const uint32_t size; /**< Sector size */
 } sector_info_t;
 
+/** Flash configuration structure
+ */
 typedef struct {
-    const uint32_t page_size;
-    const uint32_t flash_start;
-    const uint32_t flash_size;
-    const sector_info_t *sectors;
-    const uint32_t sector_info_count;
+    const uint32_t page_size; /**< The minimum program page size that can be written */
+    const uint32_t flash_start; /**< Start address of the flash <0, flash_size) */
+    const uint32_t flash_size; /**<  Flash size. The size is accumulative sum of all sector sizes */
+    const sector_info_t *sectors; /**<  List of sectors - sector can vary in sizes */
+    const uint32_t sector_info_count; /**< Number of sectors */
 } flash_target_config_t;
 
-// Target flash configuration
+/** Target flash configuration
+ */
 struct flash_s {
     const flash_target_config_t *target_config;
     const flash_algo_t *flash_algo;
 };
 
+/** Flash algo argument structure
+ *  Contains all registers that should be preserved
+ */
 typedef struct {
     uint32_t r0;
     uint32_t r1;

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/critical_section_api.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,107 @@
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CRITICAL_SECTION_API_H
+#define MBED_CRITICAL_SECTION_API_H
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup hal_critical Critical Section HAL functions
+ * @{
+ */
+
+/**
+ * Mark the start of a critical section
+ *
+ * This function will be called by core_util_critical_section_enter() each time
+ * the application requests to enter a critical section. The purpose of the
+ * critical section is to ensure mutual-exclusion synchronisation of the
+ * processor by preventing any change in processor control, the default
+ * behaviour requires storing the state of interrupts in the system before
+ * disabling them.
+ *
+ * The critical section code supports nesting. When a thread has entered a
+ * critical section it can make additional calls to
+ * core_util_critical_section_enter() without deadlocking itself. The critical
+ * section driver API tracks the number of nested calls to the critical section.
+ * The critical section will only be exited when
+ * core_util_critical_section_exit() has been called once for each time it
+ * entered the critical section.
+ *
+ * On the first call to enter a critical section this function MUST store the
+ * state of any interrupts or other application settings it will modify to
+ * facilitate the critical section.
+ *
+ * Each successive call to enter the critical section MUST ignore storing or
+ * modifying any application state.
+ *
+ * The default implementation of this function which will save the current state
+ * of interrupts before disabling them. This implementation can be found in
+ * mbed_critical_section_api.c. This behaviour is can be overridden on a per
+ * platform basis by providing a different implementation within the correct
+ * targets directory.
+ */
+void hal_critical_section_enter(void);
+
+
+/** Mark the end of a critical section.
+ *
+ * The purpose of this function is to restore any state that was modified upon
+ * entering the critical section, allowing other threads or interrupts to change
+ * the processor control.
+ *
+ * This function will be called once by core_util_critical_section_exit() per
+ * critical section on last call to exit. When called, the application MUST
+ * restore the saved interrupt/application state that was saved when entering
+ * the critical section.
+ *
+ * There is a default implementation of this function, it will restore the state
+ * of interrupts that were previously saved when hal_critical_section_enter was
+ * first called, this implementation can be found in
+ * mbed_critical_section_api.c. This behaviour is overridable by providing a
+ * different function implementation within the correct targets directory.
+ */
+void hal_critical_section_exit(void);
+
+
+/** Determine if the application is currently running in a critical section
+ *
+ * The purpose of this function is to inform the caller whether or not the
+ * application is running in a critical section. This is done by checking if
+ * the current interrupt state has been saved in the underlying implementation,
+ * this could also be done by checking the state of the interrupts at the time
+ * of calling.
+ *
+ *  @return  True if running in a critical section, false if not.
+ */
+bool hal_in_critical_section(void);
+
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MBED_CRITICAL_SECTION_API_H
+
+/** @}*/

--- a/hal/ethernet_api.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/hal/ethernet_api.h	Thu Apr 19 17:12:19 2018 +0100
@@ -40,7 +40,7 @@
 // send ethernet write buffer, returning the packet size sent
 int ethernet_send(void);
 
-// recieve from ethernet buffer, returning packet size, or 0 if no packet
+// receive from ethernet buffer, returning packet size, or 0 if no packet
 int ethernet_receive(void);
 
 // read size bytes in to data, return actual num bytes read (0..size)

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/itm_api.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,87 @@
+/** \addtogroup hal */
+/** @{*/
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_ITM_API_H
+#define MBED_ITM_API_H
+
+#if defined(DEVICE_ITM)
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup itm_hal Instrumented Trace Macrocell HAL API
+ * @{
+ */
+
+enum {
+    ITM_PORT_SWO = 0
+};
+
+/**
+ * @brief      Target specific initialization function.
+ *             This function is responsible for initializing and configuring 
+ *             the debug clock for the ITM and setting up the SWO pin for 
+ *             debug output.
+ *             
+ *             The only Cortex-M register that should be modified is the clock
+ *             prescaler in TPI->ACPR.
+ *             
+ *             The generic mbed_itm_init initialization function will setup: 
+ *             
+ *                  ITM->LAR
+ *                  ITM->TPR
+ *                  ITM->TCR
+ *                  ITM->TER
+ *                  TPI->SPPR
+ *                  TPI->FFCR
+ *                  DWT->CTRL
+ *                  
+ *             for SWO output on stimulus port 0.
+ */
+void itm_init(void);
+
+/**
+ * @brief      Initialization function for both generic registers and target specific clock and pin.
+ */
+void mbed_itm_init(void);
+
+/**
+ * @brief      Send data over ITM stimulus port.
+ *
+ * @param[in]  port  The stimulus port to send data over.
+ * @param[in]  data  The data to send.
+ *
+ * @return     value of data sent.
+ */
+uint32_t mbed_itm_send(uint32_t port, uint32_t data);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif /* MBED_ITM_API_H */
+
+/**@}*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/mbed_critical_section_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "hal/critical_section_api.h"
+#include "platform/mbed_assert.h"
+#include "platform/mbed_toolchain.h"
+
+#include <stdbool.h>
+
+static volatile bool critical_interrupts_enabled = false;
+static volatile bool state_saved = false;
+
+static bool are_interrupts_enabled(void)
+{
+#if defined(__CORTEX_A9)
+    return ((__get_CPSR() & 0x80) == 0);
+#else
+    return ((__get_PRIMASK() & 0x1) == 0);
+#endif
+}
+
+
+MBED_WEAK void hal_critical_section_enter(void)
+{
+    const bool interrupt_state = are_interrupts_enabled();
+
+    __disable_irq();
+
+    if (state_saved == true) {
+        return;
+    }
+
+    critical_interrupts_enabled = interrupt_state;
+    state_saved = true;
+}
+
+MBED_WEAK void hal_critical_section_exit(void)
+{
+#ifndef FEATURE_UVISOR
+    // Interrupts must be disabled on invoking an exit from a critical section
+    MBED_ASSERT(!are_interrupts_enabled());
+#endif
+    state_saved = false;
+
+    // Restore the IRQs to their state prior to entering the critical section
+    if (critical_interrupts_enabled == true) {
+        __enable_irq();
+    }
+}
+
+MBED_WEAK bool hal_in_critical_section(void)
+{
+    return (state_saved == true);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/hal/mbed_itm_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,87 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(DEVICE_ITM)
+
+#include "hal/itm_api.h"
+#include "cmsis.h"
+
+#include <stdbool.h>
+
+#define ITM_ENABLE_WRITE 0xC5ACCE55 
+
+#define SWO_NRZ 0x02
+#define SWO_STIMULUS_PORT 0x01
+
+void mbed_itm_init(void)
+{
+    static bool do_init = true;
+
+    if (do_init) {
+        do_init = false;
+
+        itm_init();
+
+        /* Enable write access to ITM registers. */
+        ITM->LAR  = ITM_ENABLE_WRITE;
+
+        /* Trace Port Interface Selected Pin Protocol Register. */
+        TPI->SPPR = (SWO_NRZ << TPI_SPPR_TXMODE_Pos);
+
+        /* Trace Port Interface Formatter and Flush Control Register */
+        TPI->FFCR = (1 << TPI_FFCR_TrigIn_Pos);
+
+        /* Data Watchpoint and Trace Control Register */
+        DWT->CTRL = (1 << DWT_CTRL_CYCTAP_Pos)       |
+                    (0xF << DWT_CTRL_POSTINIT_Pos)   |
+                    (0xF << DWT_CTRL_POSTPRESET_Pos) |
+                    (1 << DWT_CTRL_CYCCNTENA_Pos);
+
+        /* Trace Privilege Register.
+         * Disable access to trace channel configuration from non-privileged mode.
+         */
+        ITM->TPR  = 0x0;
+
+        /* Trace Control Register */
+        ITM->TCR  = (1 << ITM_TCR_TraceBusID_Pos) | 
+                    (1 << ITM_TCR_DWTENA_Pos)     | 
+                    (1 << ITM_TCR_SYNCENA_Pos)    |
+                    (1 << ITM_TCR_ITMENA_Pos);
+
+        /* Trace Enable Register */
+        ITM->TER = SWO_STIMULUS_PORT;    
+    }
+}
+
+uint32_t mbed_itm_send(uint32_t port, uint32_t data)
+{
+    /* Check if ITM and port is enabled */
+    if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+        ((ITM->TER & (1UL << port)     ) != 0UL)   )     /* ITM Port enabled */
+    {
+        /* write data to port */
+        ITM->PORT[port].u32 = data;
+
+        /* Wait until data has been clocked out */
+        while (ITM->PORT[port].u32 == 0UL) {
+            __NOP();
+        }
+    }
+
+    return data;
+}
+
+#endif // defined(DEVICE_ITM)

--- a/hal/mbed_sleep_manager.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/hal/mbed_sleep_manager.c	Thu Apr 19 17:12:19 2018 +0100
@@ -14,18 +14,107 @@
  * limitations under the License.
  */
 
-#include "mbed_sleep.h"
+#include "mbed_assert.h"
+#include "mbed_power_mgmt.h"
 #include "mbed_critical.h"
 #include "sleep_api.h"
 #include "mbed_error.h"
+#include "mbed_debug.h"
 #include <limits.h>
+#include <stdio.h>
 
 #if DEVICE_SLEEP
 
 // deep sleep locking counter. A target is allowed to deep sleep if counter == 0
 static uint16_t deep_sleep_lock = 0U;
 
-void sleep_manager_lock_deep_sleep(void)
+#ifdef MBED_SLEEP_TRACING_ENABLED
+
+// Number of drivers that can be stored in the structure
+#define STATISTIC_COUNT  10
+
+typedef struct sleep_statistic {
+    const char* identifier;
+    uint8_t count;
+} sleep_statistic_t;
+
+static sleep_statistic_t sleep_stats[STATISTIC_COUNT];
+
+static sleep_statistic_t* sleep_tracker_find(const char *const filename)
+{
+    for (int i = 0; i < STATISTIC_COUNT; ++i) {
+        if (sleep_stats[i].identifier == filename) {
+            return &sleep_stats[i];
+        }
+    }
+
+    return NULL;
+}
+
+static sleep_statistic_t* sleep_tracker_add(const char* const filename)
+{
+    for (int i = 0; i < STATISTIC_COUNT; ++i) {
+        if (sleep_stats[i].identifier == NULL) {
+            sleep_stats[i].identifier = filename;
+
+            return &sleep_stats[i];
+        }
+    }
+
+    debug("No free indexes left to use in mbed sleep tracker.\r\n");
+
+    return NULL;
+}
+
+static void sleep_tracker_print_stats(void)
+{
+    debug("Sleep locks held:\r\n");
+    for (int i = 0; i < STATISTIC_COUNT; ++i) {
+        if (sleep_stats[i].count == 0) {
+            continue;
+        }
+
+        if (sleep_stats[i].identifier == NULL) {
+            return;
+        }
+
+        debug("[id: %s, count: %u]\r\n", sleep_stats[i].identifier,
+                                         sleep_stats[i].count);
+    }
+}
+
+void sleep_tracker_lock(const char* const filename, int line)
+{
+    sleep_statistic_t *stat = sleep_tracker_find(filename);
+
+    // Entry for this driver does not exist, create one.
+    if (stat == NULL) {
+        stat = sleep_tracker_add(filename);
+    }
+
+    core_util_atomic_incr_u8(&stat->count, 1);
+
+    debug("LOCK: %s, ln: %i, lock count: %u\r\n", filename, line, deep_sleep_lock);
+}
+
+void sleep_tracker_unlock(const char* const filename, int line)
+{
+    sleep_statistic_t *stat = sleep_tracker_find(filename);
+
+    // Entry for this driver does not exist, something went wrong.
+    if (stat == NULL) {
+        debug("Unlocking sleep for driver that was not previously locked: %s, ln: %i\r\n", filename, line);
+        return;
+    }
+
+    core_util_atomic_decr_u8(&stat->count, 1);
+
+    debug("UNLOCK: %s, ln: %i, lock count: %u\r\n", filename, line, deep_sleep_lock);
+}
+
+#endif // MBED_SLEEP_TRACING_ENABLED
+
+void sleep_manager_lock_deep_sleep_internal(void)
 {
     core_util_critical_section_enter();
     if (deep_sleep_lock == USHRT_MAX) {
@@ -36,7 +125,7 @@
     core_util_critical_section_exit();
 }
 
-void sleep_manager_unlock_deep_sleep(void)
+void sleep_manager_unlock_deep_sleep_internal(void)
 {
     core_util_critical_section_enter();
     if (deep_sleep_lock == 0) {
@@ -54,6 +143,9 @@
 
 void sleep_manager_sleep_auto(void)
 {
+#ifdef MBED_SLEEP_TRACING_ENABLED
+    sleep_tracker_print_stats();
+#endif
     core_util_critical_section_enter();
 // debug profile should keep debuggers attached, no deep sleep allowed
 #ifdef MBED_DEBUG
@@ -73,12 +165,12 @@
 // locking is valid only if DEVICE_SLEEP is defined
 // we provide empty implementation
 
-void sleep_manager_lock_deep_sleep(void)
+void sleep_manager_lock_deep_sleep_internal(void)
 {
 
 }
 
-void sleep_manager_unlock_deep_sleep(void)
+void sleep_manager_unlock_deep_sleep_internal(void)
 {
 
 }

--- a/hal/spi_api.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/hal/spi_api.h	Thu Apr 19 17:12:19 2018 +0100
@@ -119,7 +119,7 @@
 
 /** Write a block out in master mode and receive a value
  *
- *  The total number of bytes sent and recieved will be the maximum of
+ *  The total number of bytes sent and received will be the maximum of
  *  tx_length and rx_length. The bytes written will be padded with the
  *  value 0xff.
  *

--- a/mbed.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/mbed.h	Thu Apr 19 17:12:19 2018 +0100
@@ -21,8 +21,8 @@
 #if MBED_CONF_RTOS_PRESENT
 // RTOS present, this is valid only for mbed OS 5
 #define MBED_MAJOR_VERSION 5
-#define MBED_MINOR_VERSION 7
-#define MBED_PATCH_VERSION 7
+#define MBED_MINOR_VERSION 8
+#define MBED_PATCH_VERSION 2
 
 #else
 // mbed 2
@@ -87,6 +87,7 @@
 #include "drivers/RawSerial.h"
 #include "drivers/UARTSerial.h"
 #include "drivers/FlashIAP.h"
+#include "drivers/MbedCRC.h"
 
 // mbed Internal components
 #include "drivers/Timer.h"
@@ -99,7 +100,7 @@
 #include "drivers/InterruptIn.h"
 #include "platform/mbed_wait_api.h"
 #include "hal/sleep_api.h"
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 #include "platform/mbed_rtc_time.h"
 #include "platform/mbed_poll.h"
 #include "platform/ATCmdParser.h"
@@ -112,6 +113,7 @@
 // mbed Non-hardware components
 #include "platform/Callback.h"
 #include "platform/FunctionPointer.h"
+#include "platform/ScopedLock.h"
 
 using namespace mbed;
 using namespace std;

--- a/platform/ATCmdParser.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/ATCmdParser.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -158,7 +158,7 @@
         if (j+1 >= _buffer_size - offset) {
             return false;
         }
-        // Recieve next character
+        // Receive next character
         int c = getc();
         if (c < 0) {
             return -1;
@@ -394,6 +394,19 @@
         if (c < 0) {
             return false;
         }
+        // Simplify newlines (borrowed from retarget.cpp)
+        if ((c == CR && _in_prev != LF) ||
+            (c == LF && _in_prev != CR)) {
+            _in_prev = c;
+            c = '\n';
+        } else if ((c == CR && _in_prev == LF) ||
+                   (c == LF && _in_prev == CR)) {
+            _in_prev = c;
+            // onto next character
+            continue;
+        } else {
+            _in_prev = c;
+        }
         _buffer[i++] = c;
         _buffer[i] = 0;
 
@@ -411,9 +424,7 @@
         
         // Clear the buffer when we hit a newline or ran out of space
         // running out of space usually means we ran into binary data
-        if (i+1 >= _buffer_size ||
-            strcmp(&_buffer[i-_output_delim_size], _output_delimiter) == 0) {
-
+        if (((i+1) >= _buffer_size) || (c == '\n')) {
             debug_if(_dbg_on, "AT< %s", _buffer);
             i = 0;
         }

--- a/platform/ATCmdParser.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/ATCmdParser.h	Thu Apr 19 17:12:19 2018 +0100
@@ -124,6 +124,7 @@
 
     /**
      * For backwards compatibility.
+     * @deprecated Do not use this function. This function has been replaced with set_timeout for consistency.
      *
      * Please use set_timeout(int) API only from now on.
      * Allows timeout to be changed between commands
@@ -149,6 +150,7 @@
 
     /**
      * For backwards compatibility.
+     * @deprecated Do not use this function. This function has been replaced with set_delimiter for consistency.
      *
      * Please use set_delimiter(const char *) API only from now on.
      * Sets string of characters to use as line delimiters
@@ -173,6 +175,7 @@
 
     /**
      * For backwards compatibility.
+     * @deprecated Do not use this function. This function has been replaced with debug_on for consistency.
      *
      * Allows traces from modem to be turned on or off
      *

--- a/platform/CallChain.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/CallChain.h	Thu Apr 19 17:12:19 2018 +0100
@@ -38,6 +38,7 @@
  * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
  * but can be used for other purposes.
  *
+ * @deprecated Do not use this class. This class is not part of the public API of mbed-os and is being removed in the future.
  * @note Synchronization level: Not protected
  *
  * Example:
@@ -74,6 +75,8 @@
 class CallChain : private NonCopyable<CallChain> {
 public:
     /** Create an empty chain
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
      *
      *  @param size (optional) Initial size of the chain
      */
@@ -81,12 +84,19 @@
         "public API of mbed-os and is being removed in the future.")
     CallChain(int size = 4);
 
+    /** Create an empty chain
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+     */
     MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
         "public API of mbed-os and is being removed in the future.")
     virtual ~CallChain();
 
     /** Add a function at the end of the chain
      *
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+     *
      *  @param func A pointer to a void function
      *
      *  @returns
@@ -117,6 +127,9 @@
     }
 
     /** Add a function at the beginning of the chain
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+     *
      *
      *  @param func A pointer to a void function
      *
@@ -148,12 +161,17 @@
     }
 
     /** Get the number of functions in the chain
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+     *
      */
     MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
         "public API of mbed-os and is being removed in the future.")
     int size() const;
 
     /** Get a function object from the chain
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
      *
      *  @param i function object index
      *
@@ -165,6 +183,8 @@
     pFunctionPointer_t get(int i) const;
 
     /** Look for a function object in the call chain
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
      *
      *  @param f the function object to search
      *
@@ -176,12 +196,15 @@
     int find(pFunctionPointer_t f) const;
 
     /** Clear the call chain (remove all functions in the chain).
+     *  @deprecated Do not use this function. This class is not part of the public API of mbed-os and is being removed in the future.
      */
     MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
         "public API of mbed-os and is being removed in the future.")
     void clear();
 
     /** Remove a function object from the chain
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
      *
      *  @arg f the function object to remove
      *
@@ -193,17 +216,30 @@
     bool remove(pFunctionPointer_t f);
 
     /** Call all the functions in the chain in sequence
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+     *
      */
     MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
         "public API of mbed-os and is being removed in the future.")
     void call();
 
+    /** 
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+     *
+     */
     MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
         "public API of mbed-os and is being removed in the future.")
     void operator ()(void) {
         call();
     }
 
+    /** 
+     *  @deprecated 
+     *  Do not use this function, this class is not part of the public API of mbed-os and is being removed in the future.
+     *
+     */
     MBED_DEPRECATED_SINCE("mbed-os-5.6", "This class is not part of the "
         "public API of mbed-os and is being removed in the future.")
     pFunctionPointer_t operator [](int i) const {

--- a/platform/Callback.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/Callback.h	Thu Apr 19 17:12:19 2018 +0100
@@ -565,7 +565,7 @@
 private:
     // Stored as pointer to function and pointer to optional object
     // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
+    // to guarantee proper size and alignment
     struct _class;
     union {
         void (*_staticfunc)();
@@ -1140,7 +1140,7 @@
 private:
     // Stored as pointer to function and pointer to optional object
     // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
+    // to guarantee proper size and alignment
     struct _class;
     union {
         void (*_staticfunc)(A0);
@@ -1716,7 +1716,7 @@
 private:
     // Stored as pointer to function and pointer to optional object
     // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
+    // to guarantee proper size and alignment
     struct _class;
     union {
         void (*_staticfunc)(A0, A1);
@@ -2293,7 +2293,7 @@
 private:
     // Stored as pointer to function and pointer to optional object
     // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
+    // to guarantee proper size and alignment
     struct _class;
     union {
         void (*_staticfunc)(A0, A1, A2);
@@ -2871,7 +2871,7 @@
 private:
     // Stored as pointer to function and pointer to optional object
     // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
+    // to guarantee proper size and alignment
     struct _class;
     union {
         void (*_staticfunc)(A0, A1, A2, A3);
@@ -3450,7 +3450,7 @@
 private:
     // Stored as pointer to function and pointer to optional object
     // Function pointer is stored as union of possible function types
-    // to garuntee proper size and alignment
+    // to guarantee proper size and alignment
     struct _class;
     union {
         void (*_staticfunc)(A0, A1, A2, A3, A4);

--- a/platform/CircularBuffer.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/CircularBuffer.h	Thu Apr 19 17:12:19 2018 +0100
@@ -17,8 +17,26 @@
 #define MBED_CIRCULARBUFFER_H
 
 #include "platform/mbed_critical.h"
+#include "platform/mbed_assert.h"
 
 namespace mbed {
+
+namespace internal {
+/* Detect if CounterType of the Circular buffer is of unsigned type. */
+template<typename T>
+struct is_unsigned { static const bool value = false; };
+template<>
+struct is_unsigned<unsigned char> { static const bool value = true; };
+template<>
+struct is_unsigned<unsigned short> { static const bool value = true; };
+template<>
+struct is_unsigned<unsigned int> { static const bool value = true; };
+template<>
+struct is_unsigned<unsigned long> { static const bool value = true; };
+template<>
+struct is_unsigned<unsigned long long> { static const bool value = true; };
+};
+
 /** \addtogroup platform */
 /** @{*/
 /**
@@ -29,11 +47,22 @@
 /** Templated Circular buffer class
  *
  *  @note Synchronization level: Interrupt safe
+ *  @note CounterType must be unsigned and consistent with BufferSize
  */
 template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
 class CircularBuffer {
 public:
     CircularBuffer() : _head(0), _tail(0), _full(false) {
+        MBED_STATIC_ASSERT(
+            internal::is_unsigned<CounterType>::value,
+            "CounterType must be unsigned"
+        );
+
+        MBED_STATIC_ASSERT(
+            (sizeof(CounterType) >= sizeof(uint32_t)) ||
+            (BufferSize < (((uint64_t) 1) << (sizeof(CounterType) * 8))),
+            "Invalid BufferSize for the CounterType"
+        );
     }
 
     ~CircularBuffer() {
@@ -140,4 +169,3 @@
 }
 
 #endif
-

--- a/platform/CriticalSectionLock.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/CriticalSectionLock.h	Thu Apr 19 17:12:19 2018 +0100
@@ -34,14 +34,25 @@
   * Usage:
   * @code
   *
-  * void f() {
-  *     // some code here
-  *     {
-  *         CriticalSectionLock lock;
-  *         // Code in this block will run with interrupts disabled
-  *     }
-  *     // interrupts will be restored to their previous state
+  * // RAII style usage
+  * unsigned int atomic_counter_increment(unsigned int &counter) {
+  *     CriticalSectionLock lock;
+  *     // Code in this block will run with interrupts disabled
+  *     // Interrupts will be restored to their previous state automatically
+  *     // at the end of function scope
+  *     return ++counter;
   * }
+  *
+  * // free locking usage
+  * unsigned int atomic_counter_decrement(unsigned int &counter) {
+  *     CriticalSectionLock::enable();
+  *     // Code in this block will run with interrupts disabled
+  *     counter--;
+  *     CriticalSectionLock::disable(); // need explicitly to disable critical section lock
+  *     // interrupts will be restored to their previous state here
+  *     return counter;
+  * }
+  *
   * @endcode
   */
 class CriticalSectionLock {
@@ -57,20 +68,42 @@
     }
 
     /** Mark the start of a critical section
-     *     
+     *  @deprecated This function is inconsistent with RAII and is being removed in the future. Replaced by static function CriticalSectionLock::enable.
+     *
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.8",
+            "This function is inconsistent with RAII and is being removed in the future."
+            "Replaced by static function CriticalSectionLock::enable.")
     void lock()
     {
         core_util_critical_section_enter();
     }
 
     /** Mark the end of a critical section
-     *     
+     *  @deprecated This function is inconsistent with RAII and is being removed in the future. Replaced by static function CriticalSectionLock::enable.
+     *
      */
+    MBED_DEPRECATED_SINCE("mbed-os-5.8",
+            "This function is inconsistent with RAII and is being removed in the future."
+            "Replaced by static function CriticalSectionLock::disable.")
     void unlock()
     {
         core_util_critical_section_exit();
     }
+
+    /** Mark the start of a critical section
+     */
+    static void enable()
+    {
+        core_util_critical_section_enter();
+    }
+
+    /** Mark the end of a critical section
+     */
+    static void disable()
+    {
+        core_util_critical_section_exit();
+    }
 };
 
 /**@}*/

--- a/platform/DeepSleepLock.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/DeepSleepLock.h	Thu Apr 19 17:12:19 2018 +0100
@@ -17,7 +17,7 @@
 #define MBED_DEEPSLEEPLOCK_H
 
 #include <limits.h>
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 #include "platform/mbed_critical.h"
 
 namespace mbed {

--- a/platform/FileHandle.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/FileHandle.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -33,9 +33,4 @@
     return size;
 }
 
-std::FILE *fdopen(FileHandle *fh, const char *mode)
-{
-    return mbed_fdopen(fh, mode);
-}
-
 } // namespace mbed

--- a/platform/FileHandle.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/FileHandle.h	Thu Apr 19 17:12:19 2018 +0100
@@ -252,18 +252,6 @@
     }
 };
 
-/** Not a member function
- *  This call is equivalent to posix fdopen().
- *  It associates a Stream to an already opened file descriptor (FileHandle)
- *
- *  @param fh       a pointer to an opened file descriptor
- *  @param mode     operation upon the file descriptor, e.g., 'wb+'
- *
- *  @returns        a pointer to std::FILE
-*/
-
-std::FILE *fdopen(FileHandle *fh, const char *mode);
-
 /**@}*/
 
 /**@}*/

--- a/platform/FileSystemHandle.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/FileSystemHandle.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -42,3 +42,8 @@
 {
     return -ENOSYS;
 }
+
+int FileSystemHandle::statvfs(const char *path, struct statvfs *buf)
+{
+    return -ENOSYS;
+}

--- a/platform/FileSystemHandle.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/FileSystemHandle.h	Thu Apr 19 17:12:19 2018 +0100
@@ -94,6 +94,14 @@
      *  @return         0 on success, negative error code on failure
      */
     virtual int mkdir(const char *path, mode_t mode);
+
+    /** Store information about the mounted filesystem in a statvfs structure
+     *
+     *  @param path     The name of the file to find information about
+     *  @param buf      The stat buffer to write to
+     *  @return         0 on success, negative error code on failure
+     */
+     virtual int statvfs(const char *path, struct statvfs *buf);
 };
 /**@}*/
 

--- a/platform/NonCopyable.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/NonCopyable.h	Thu Apr 19 17:12:19 2018 +0100
@@ -25,11 +25,11 @@
 
 /**
  * Inheriting from this class autogeneration of copy construction and copy
- * assignement operations.
+ * assignment operations.
  *
  * Classes which are not value type should inherit privately from this class
- * to avoid generation of invalid copy constructor or copy assignement operator
- * which can lead to unoticeable programming errors.
+ * to avoid generation of invalid copy constructor or copy assignment operator
+ * which can lead to unnoticeable programming errors.
  *
  * As an example consider the following signature:
  *
@@ -50,7 +50,7 @@
  * @endcode
  *
  * There is a bug in this function, it returns a temporary value which will be
- * byte copied into foo then destroyed. Unfortunately, internaly the Foo class
+ * byte copied into foo then destroyed. Unfortunately, internally the Foo class
  * manage a pointer to a Resource object. This pointer will be released when the
  * temporary is destroyed and foo will manage a pointer to an already released
  * Resource.
@@ -71,9 +71,9 @@
  * Foo* m = make_foo();
  * @endcode
  *
- *   - Copy constructor and copy assignement operator has to be made private
+ *   - Copy constructor and copy assignment operator has to be made private
  *     in the Foo class. It prevents unwanted copy of Foo objects. This can be
- *     done by declaring copy constructor and copy assignement in the private
+ *     done by declaring copy constructor and copy assignment in the private
  *     section of the Foo class.
  *
  * @code
@@ -92,7 +92,7 @@
  *
  * Another solution is to inherit privately from the NonCopyable class.
  * It reduces the boiler plate needed to avoid copy operations but more
- * importantly it clarifies the programer intent and the object semantic.
+ * importantly it clarifies the programmer intent and the object semantic.
  *
  * class Foo : private NonCopyable<Foo> {
  * public:
@@ -121,7 +121,7 @@
  * };
  *
  * // empty base optimization cannot be applied here because A from C and A from
- * // B shall have a different address. In that case, with the alignement
+ * // B shall have a different address. In that case, with the alignment
  * // sizeof(C) == 2* sizeof(int)
  * @endcode
  *
@@ -150,11 +150,11 @@
 class NonCopyable {
 protected:
     /**
-     * Disalow construction of NonCopyable objects from outside of its hierarchy.
+     * Disallow construction of NonCopyable objects from outside of its hierarchy.
      */
     NonCopyable() { }
     /**
-     * Disalow destruction of NonCopyable objects from outside of its hierarchy.
+     * Disallow destruction of NonCopyable objects from outside of its hierarchy.
      */
     ~NonCopyable() { }
 
@@ -199,7 +199,7 @@
     NonCopyable(const NonCopyable&);
 
     /**
-     * Declare copy assignement operator as private, any attempt to copy assign
+     * Declare copy assignment operator as private, any attempt to copy assign
      * a NonCopyable will fail at compile time.
      */
     NonCopyable& operator=(const NonCopyable&);

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/ScopedLock.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,87 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SCOPEDLOCK_H
+#define MBED_SCOPEDLOCK_H
+
+#include "platform/NonCopyable.h"
+
+namespace mbed {
+
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_ScopedLock ScopedLock functions
+ * @{
+ */
+
+/** RAII-style mechanism for owning a lock of Lockable object for the duration of a scoped block
+ *
+ * @tparam Lockable The type implementing BasicLockable concept
+ *
+ * @note For type Lockable to be BasicLockable, the following conditions have to be satisfied:
+ *        - has public member function @a lock which blocks until a lock can be obtained for the current execution context
+ *        - has public member function @a unlock which releases the lock
+ *
+ * Usage:
+ *
+ * Example with rtos::Mutex
+ *
+ * @code
+ * void foo(Mutex &m) {
+ *     ScopedLock<Mutex> lock(m);
+ *     // Mutex lock protects code in this block
+ * }
+ * @endcode
+ *
+ *
+ * More generic example
+ *
+ * @code
+ * template<typename Lockable>
+ * void foo(Lockable& lockable) {
+ *     ScopedLock<Lockable> lock(lockable);
+ *     // Code in this block runs under lock
+ * }
+ * @endcode
+ */
+template <typename Lockable>
+class ScopedLock : private NonCopyable<ScopedLock<Lockable> > {
+public:
+    /** Locks given locable object
+     *
+     * @param lockable reference to the instance of Lockable object
+     * @note lockable object should outlive the ScopedLock object
+     */
+    ScopedLock(Lockable& lockable): _lockable(lockable)
+    {
+        _lockable.lock();
+    }
+
+    ~ScopedLock()
+    {
+        _lockable.unlock();
+    }
+private:
+    Lockable& _lockable;
+};
+
+/**@}*/
+
+/**@}*/
+
+} // embed
+
+#endif // MBED_SCOPEDLOCK_H

--- a/platform/mbed_critical.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_critical.c	Thu Apr 19 17:12:19 2018 +0100
@@ -17,14 +17,33 @@
 
 /* Declare __STDC_LIMIT_MACROS so stdint.h defines UINT32_MAX when using C++ */
 #define __STDC_LIMIT_MACROS
-#include "platform/mbed_critical.h"
+#include "hal/critical_section_api.h"
 
 #include "cmsis.h"
 #include "platform/mbed_assert.h"
+#include "platform/mbed_critical.h"
 #include "platform/mbed_toolchain.h"
 
-static volatile uint32_t interrupt_enable_counter = 0;
-static volatile bool critical_interrupts_disabled = false;
+// if __EXCLUSIVE_ACCESS rtx macro not defined, we need to get this via own-set architecture macros
+#ifndef MBED_EXCLUSIVE_ACCESS
+#ifndef __EXCLUSIVE_ACCESS
+#if ((__ARM_ARCH_7M__      == 1U) || \
+    (__ARM_ARCH_7EM__     == 1U) || \
+    (__ARM_ARCH_8M_BASE__ == 1U) || \
+    (__ARM_ARCH_8M_MAIN__ == 1U)) || \
+    (__ARM_ARCH_7A__ == 1U)
+#define MBED_EXCLUSIVE_ACCESS      1U
+#elif (__ARM_ARCH_6M__ == 1U)
+#define MBED_EXCLUSIVE_ACCESS      0U
+#else
+#error "Unknown architecture for exclusive access"
+#endif
+#else 
+#define MBED_EXCLUSIVE_ACCESS __EXCLUSIVE_ACCESS
+#endif
+#endif
+
+static volatile uint32_t critical_section_reentrancy_counter = 0;
 
 bool core_util_are_interrupts_enabled(void)
 {
@@ -51,161 +70,150 @@
 #endif
 }
 
-MBED_WEAK void core_util_critical_section_enter(void)
+bool core_util_in_critical_section(void)
+{
+    return hal_in_critical_section();
+}
+
+void core_util_critical_section_enter(void)
 {
-    bool interrupts_disabled = !core_util_are_interrupts_enabled();
-    __disable_irq();
+// FIXME
+#ifdef FEATURE_UVISOR
+    #warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
+#else
+    // If the reentrancy counter overflows something has gone badly wrong.
+    MBED_ASSERT(critical_section_reentrancy_counter < UINT32_MAX);
+#endif /* FEATURE_UVISOR */
+
+    hal_critical_section_enter();
 
-    /* Save the interrupt disabled state as it was prior to any nested critical section lock use */
-    if (!interrupt_enable_counter) {
-        critical_interrupts_disabled = interrupts_disabled;
+    ++critical_section_reentrancy_counter;
+}
+
+void core_util_critical_section_exit(void)
+{
+// FIXME
+#ifdef FEATURE_UVISOR
+    #warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
+#endif /* FEATURE_UVISOR */
+
+    // If critical_section_enter has not previously been called, do nothing
+    if (critical_section_reentrancy_counter == 0) {
+        return;
     }
 
-    /* If the interrupt_enable_counter overflows or we are in a nested critical section and interrupts
-       are enabled, then something has gone badly wrong thus assert an error.
-    */
-    MBED_ASSERT(interrupt_enable_counter < UINT32_MAX); 
-// FIXME
-#ifndef   FEATURE_UVISOR
-    if (interrupt_enable_counter > 0) {
-        MBED_ASSERT(interrupts_disabled);
-    }
-#else
-#warning "core_util_critical_section_enter needs fixing to work from unprivileged code"
-#endif /* FEATURE_UVISOR */
-    interrupt_enable_counter++;
-}
+    --critical_section_reentrancy_counter;
 
-MBED_WEAK void core_util_critical_section_exit(void)
-{
-    /* If critical_section_enter has not previously been called, do nothing */
-    if (interrupt_enable_counter) {
-
-// FIXME
-#ifndef   FEATURE_UVISOR
-        bool interrupts_disabled = !core_util_are_interrupts_enabled(); /* get the current interrupt disabled state */
-
-        MBED_ASSERT(interrupts_disabled); /* Interrupts must be disabled on invoking an exit from a critical section */
-#else
-#warning "core_util_critical_section_exit needs fixing to work from unprivileged code"
-#endif /* FEATURE_UVISOR */
-
-        interrupt_enable_counter--;
-
-        /* Only re-enable interrupts if we are exiting the last of the nested critical sections and
-           interrupts were enabled on entry to the first critical section.
-        */
-        if (!interrupt_enable_counter && !critical_interrupts_disabled) {
-            __enable_irq();
-        }
+    if (critical_section_reentrancy_counter == 0) {
+        hal_critical_section_exit();
     }
 }
 
-#if __EXCLUSIVE_ACCESS
+#if MBED_EXCLUSIVE_ACCESS
 
 /* Supress __ldrex and __strex deprecated warnings - "#3731-D: intrinsic is deprecated" */
 #if defined (__CC_ARM) 
 #pragma diag_suppress 3731
 #endif
 
-bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
 {
     do {
-        uint8_t currentValue = __LDREXB((volatile uint8_t*)ptr);
+        uint8_t currentValue = __LDREXB(ptr);
         if (currentValue != *expectedCurrentValue) {
             *expectedCurrentValue = currentValue;
             __CLREX();
             return false;
         }
-    } while (__STREXB(desiredValue, (volatile uint8_t*)ptr));
+    } while (__STREXB(desiredValue, ptr));
     return true;
 }
 
-bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
 {
     do {
-        uint16_t currentValue = __LDREXH((volatile uint16_t*)ptr);
+        uint16_t currentValue = __LDREXH(ptr);
         if (currentValue != *expectedCurrentValue) {
             *expectedCurrentValue = currentValue;
             __CLREX();
             return false;
         }
-    } while (__STREXH(desiredValue, (volatile uint16_t*)ptr));
+    } while (__STREXH(desiredValue, ptr));
     return true;
 }
 
 
-bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
 {
     do {
-        uint32_t currentValue = __LDREXW((volatile uint32_t*)ptr);
+        uint32_t currentValue = __LDREXW(ptr);
         if (currentValue != *expectedCurrentValue) {
             *expectedCurrentValue = currentValue;
             __CLREX();
             return false;
         }
-    } while (__STREXW(desiredValue, (volatile uint32_t*)ptr));
+    } while (__STREXW(desiredValue, ptr));
     return true;
 }
 
-uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
+uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta)
 {
     uint8_t newValue;
     do {
-        newValue = __LDREXB((volatile uint8_t*)valuePtr) + delta;
-    } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
+        newValue = __LDREXB(valuePtr) + delta;
+    } while (__STREXB(newValue, valuePtr));
     return newValue;
 }
 
-uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
+uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta)
 {
     uint16_t newValue;
     do {
-        newValue = __LDREXH((volatile uint16_t*)valuePtr) + delta;
-    } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
+        newValue = __LDREXH(valuePtr) + delta;
+    } while (__STREXH(newValue, valuePtr));
     return newValue;
 }
 
-uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
+uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta)
 {
     uint32_t newValue;
     do {
-        newValue = __LDREXW((volatile uint32_t*)valuePtr) + delta;
-    } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
+        newValue = __LDREXW(valuePtr) + delta;
+    } while (__STREXW(newValue, valuePtr));
     return newValue;
 }
 
 
-uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
+uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta)
 {
     uint8_t newValue;
     do {
-        newValue = __LDREXB((volatile uint8_t*)valuePtr) - delta;
-    } while (__STREXB(newValue, (volatile uint8_t*)valuePtr));
+        newValue = __LDREXB(valuePtr) - delta;
+    } while (__STREXB(newValue, valuePtr));
     return newValue;
 }
 
-uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
+uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta)
 {
     uint16_t newValue;
     do {
-        newValue = __LDREXH((volatile uint16_t*)valuePtr) - delta;
-    } while (__STREXH(newValue, (volatile uint16_t*)valuePtr));
+        newValue = __LDREXH(valuePtr) - delta;
+    } while (__STREXH(newValue, valuePtr));
     return newValue;
 }
 
-uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
+uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta)
 {
     uint32_t newValue;
     do {
-        newValue = __LDREXW((volatile uint32_t*)valuePtr) - delta;
-    } while (__STREXW(newValue, (volatile uint32_t*)valuePtr));
+        newValue = __LDREXW(valuePtr) - delta;
+    } while (__STREXW(newValue, valuePtr));
     return newValue;
 }
 
 #else
 
-bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
+bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue)
 {
     bool success;
     uint8_t currentValue;
@@ -222,7 +230,7 @@
     return success;
 }
 
-bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
+bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue)
 {
     bool success;
     uint16_t currentValue;
@@ -240,7 +248,7 @@
 }
 
 
-bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
+bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue)
 {
     bool success;
     uint32_t currentValue;
@@ -258,7 +266,7 @@
 }
 
 
-uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta)
+uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta)
 {
     uint8_t newValue;
     core_util_critical_section_enter();
@@ -268,7 +276,7 @@
     return newValue;
 }
 
-uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta)
+uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta)
 {
     uint16_t newValue;
     core_util_critical_section_enter();
@@ -278,7 +286,7 @@
     return newValue;
 }
 
-uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta)
+uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta)
 {
     uint32_t newValue;
     core_util_critical_section_enter();
@@ -289,7 +297,7 @@
 }
 
 
-uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta)
+uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta)
 {
     uint8_t newValue;
     core_util_critical_section_enter();
@@ -299,7 +307,7 @@
     return newValue;
 }
 
-uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta)
+uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta)
 {
     uint16_t newValue;
     core_util_critical_section_enter();
@@ -309,7 +317,7 @@
     return newValue;
 }
 
-uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta)
+uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta)
 {
     uint32_t newValue;
     core_util_critical_section_enter();
@@ -322,18 +330,18 @@
 #endif
 
 
-bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue) {
+bool core_util_atomic_cas_ptr(void * volatile *ptr, void **expectedCurrentValue, void *desiredValue) {
     return core_util_atomic_cas_u32(
-            (uint32_t *)ptr,
+            (volatile uint32_t *)ptr,
             (uint32_t *)expectedCurrentValue,
             (uint32_t)desiredValue);
 }
 
-void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta) {
-    return (void *)core_util_atomic_incr_u32((uint32_t *)valuePtr, (uint32_t)delta);
+void *core_util_atomic_incr_ptr(void * volatile *valuePtr, ptrdiff_t delta) {
+    return (void *)core_util_atomic_incr_u32((volatile uint32_t *)valuePtr, (uint32_t)delta);
 }
 
-void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta) {
-    return (void *)core_util_atomic_decr_u32((uint32_t *)valuePtr, (uint32_t)delta);
+void *core_util_atomic_decr_ptr(void * volatile *valuePtr, ptrdiff_t delta) {
+    return (void *)core_util_atomic_decr_u32((volatile uint32_t *)valuePtr, (uint32_t)delta);
 }
 

--- a/platform/mbed_critical.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_critical.h	Thu Apr 19 17:12:19 2018 +0100
@@ -83,6 +83,13 @@
 void core_util_critical_section_exit(void);
 
 /**
+ * Determine if we are currently in a critical section
+ *
+ * @return true if in a critical section, false otherwise.
+ */
+bool core_util_in_critical_section(void);
+
+/**
  * Atomic compare and set. It compares the contents of a memory location to a
  * given value and, only if they are the same, modifies the contents of that
  * memory location to a given new value. This is done as a single atomic
@@ -137,7 +144,7 @@
  * always succeeds if the current value is expected, as per the pseudocode
  * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
  */
-bool core_util_atomic_cas_u8(uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
+bool core_util_atomic_cas_u8(volatile uint8_t *ptr, uint8_t *expectedCurrentValue, uint8_t desiredValue);
 
 /**
  * Atomic compare and set. It compares the contents of a memory location to a
@@ -194,7 +201,7 @@
  * always succeeds if the current value is expected, as per the pseudocode
  * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
  */
-bool core_util_atomic_cas_u16(uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
+bool core_util_atomic_cas_u16(volatile uint16_t *ptr, uint16_t *expectedCurrentValue, uint16_t desiredValue);
 
 /**
  * Atomic compare and set. It compares the contents of a memory location to a
@@ -251,7 +258,7 @@
  * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
  * }
  */
-bool core_util_atomic_cas_u32(uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
+bool core_util_atomic_cas_u32(volatile uint32_t *ptr, uint32_t *expectedCurrentValue, uint32_t desiredValue);
 
 /**
  * Atomic compare and set. It compares the contents of a memory location to a
@@ -308,7 +315,7 @@
  * always succeeds if the current value is expected, as per the pseudocode
  * above; it will not spuriously fail as "atomic_compare_exchange_weak" may.
  */
-bool core_util_atomic_cas_ptr(void **ptr, void **expectedCurrentValue, void *desiredValue);
+bool core_util_atomic_cas_ptr(void * volatile *ptr, void **expectedCurrentValue, void *desiredValue);
 
 /**
  * Atomic increment.
@@ -316,7 +323,7 @@
  * @param  delta    The amount being incremented.
  * @return          The new incremented value.
  */
-uint8_t core_util_atomic_incr_u8(uint8_t *valuePtr, uint8_t delta);
+uint8_t core_util_atomic_incr_u8(volatile uint8_t *valuePtr, uint8_t delta);
 
 /**
  * Atomic increment.
@@ -324,7 +331,7 @@
  * @param  delta    The amount being incremented.
  * @return          The new incremented value.
  */
-uint16_t core_util_atomic_incr_u16(uint16_t *valuePtr, uint16_t delta);
+uint16_t core_util_atomic_incr_u16(volatile uint16_t *valuePtr, uint16_t delta);
 
 /**
  * Atomic increment.
@@ -332,7 +339,7 @@
  * @param  delta    The amount being incremented.
  * @return          The new incremented value.
  */
-uint32_t core_util_atomic_incr_u32(uint32_t *valuePtr, uint32_t delta);
+uint32_t core_util_atomic_incr_u32(volatile uint32_t *valuePtr, uint32_t delta);
 
 /**
  * Atomic increment.
@@ -343,7 +350,7 @@
  * @note The type of the pointer argument is not taken into account
  *       and the pointer is incremented by bytes.
  */
-void *core_util_atomic_incr_ptr(void **valuePtr, ptrdiff_t delta);
+void *core_util_atomic_incr_ptr(void * volatile *valuePtr, ptrdiff_t delta);
 
 /**
  * Atomic decrement.
@@ -351,7 +358,7 @@
  * @param  delta    The amount being decremented.
  * @return          The new decremented value.
  */
-uint8_t core_util_atomic_decr_u8(uint8_t *valuePtr, uint8_t delta);
+uint8_t core_util_atomic_decr_u8(volatile uint8_t *valuePtr, uint8_t delta);
 
 /**
  * Atomic decrement.
@@ -359,7 +366,7 @@
  * @param  delta    The amount being decremented.
  * @return          The new decremented value.
  */
-uint16_t core_util_atomic_decr_u16(uint16_t *valuePtr, uint16_t delta);
+uint16_t core_util_atomic_decr_u16(volatile uint16_t *valuePtr, uint16_t delta);
 
 /**
  * Atomic decrement.
@@ -367,7 +374,7 @@
  * @param  delta    The amount being decremented.
  * @return          The new decremented value.
  */
-uint32_t core_util_atomic_decr_u32(uint32_t *valuePtr, uint32_t delta);
+uint32_t core_util_atomic_decr_u32(volatile uint32_t *valuePtr, uint32_t delta);
 
 /**
  * Atomic decrement.
@@ -378,7 +385,7 @@
  * @note The type of the pointer argument is not taken into account
  *       and the pointer is decremented by bytes
  */
-void *core_util_atomic_decr_ptr(void **valuePtr, ptrdiff_t delta);
+void *core_util_atomic_decr_ptr(void * volatile *valuePtr, ptrdiff_t delta);
 
 #ifdef __cplusplus
 } // extern "C"

--- a/platform/mbed_interface.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_interface.c	Thu Apr 19 17:12:19 2018 +0100
@@ -71,7 +71,8 @@
     }
 }
 
-// for backward compatibility
+MBED_DEPRECATED_SINCE("mbed-os-5.9", "This function shouldn't be used in new code."
+    "For system reset funcionality use system_reset()")
 void mbed_reset(void) {
     mbed_interface_reset();
 }

--- a/platform/mbed_lib.json	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_lib.json	Thu Apr 19 17:12:19 2018 +0100
@@ -2,7 +2,17 @@
     "name": "platform",
     "config": {
         "stdio-convert-newlines": {
-            "help": "Enable conversion to standard newlines on stdin/stdout",
+            "help": "Enable conversion to standard newlines on stdin/stdout/stderr",
+            "value": false
+        },
+
+        "stdio-convert-tty-newlines": {
+            "help": "Enable conversion to standard newlines on any tty FILE stream",
+            "value": false
+        },
+
+        "stdio-buffered-serial": {
+            "help": "Use UARTSerial driver to obtain buffered serial I/O on stdin/stdout/stderr. If false, unbuffered serial_getc and serial_putc are used directly.",
             "value": false
         },
 

--- a/platform/mbed_mktime.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_mktime.c	Thu Apr 19 17:12:19 2018 +0100
@@ -16,14 +16,17 @@
 
 #include "mbed_mktime.h"
 
-/*
- * time constants 
- */
+/* Time constants. */
 #define SECONDS_BY_MINUTES 60
 #define MINUTES_BY_HOUR 60
 #define SECONDS_BY_HOUR (SECONDS_BY_MINUTES * MINUTES_BY_HOUR)
 #define HOURS_BY_DAY 24 
 #define SECONDS_BY_DAY (SECONDS_BY_HOUR * HOURS_BY_DAY)
+#define LAST_VALID_YEAR 206
+
+/* Macros which will be used to determine if we are within valid range. */
+#define EDGE_TIMESTAMP_FULL_LEAP_YEAR_SUPPORT 3220095     // 7th of February 1970 at 06:28:15
+#define EDGE_TIMESTAMP_4_YEAR_LEAP_YEAR_SUPPORT 3133695  // 6th of February 1970 at 06:28:15
 
 /*
  * 2 dimensional array containing the number of seconds elapsed before a given 
@@ -63,10 +66,10 @@
     }
 };
 
-bool _rtc_is_leap_year(int year) {
+bool _rtc_is_leap_year(int year, rtc_leap_year_support_t leap_year_support) {
     /* 
      * since in practice, the value manipulated by this algorithm lie in the 
-     * range [70 : 138], the algorith can be reduced to: year % 4.
+     * range: [70 : 206] the algorithm can be reduced to: year % 4 with exception for 200 (year 2100 is not leap year).
      * The algorithm valid over the full range of value is: 
 
         year = 1900 + year;
@@ -80,86 +83,108 @@
         return true;
 
      */ 
+    if (leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT && year == 200) {
+        return false; // 2100 is not a leap year
+    }
+
     return (year) % 4 ? false : true;
 }
 
-time_t _rtc_mktime(const struct tm* time) {
-    // partial check for the upper bound of the range
-    // normalization might happen at the end of the function 
-    // this solution is faster than checking if the input is after the 19th of 
-    // january 2038 at 03:14:07.  
-    if ((time->tm_year < 70) || (time->tm_year > 138)) { 
-        return ((time_t) -1);
+bool _rtc_maketime(const struct tm* time, time_t * seconds, rtc_leap_year_support_t leap_year_support) {
+    if (seconds == NULL || time == NULL) {
+        return false;
+    }
+
+    /* Partial check for the upper bound of the range - check years only. Full check will be performed after the
+     * elapsed time since the beginning of the year is calculated.
+     */
+    if ((time->tm_year < 70) || (time->tm_year > LAST_VALID_YEAR)) {
+        return false;
     }
 
     uint32_t result = time->tm_sec;
     result += time->tm_min * SECONDS_BY_MINUTES;
     result += time->tm_hour * SECONDS_BY_HOUR;
     result += (time->tm_mday - 1) * SECONDS_BY_DAY;
-    result += seconds_before_month[_rtc_is_leap_year(time->tm_year)][time->tm_mon];
+    result += seconds_before_month[_rtc_is_leap_year(time->tm_year, leap_year_support)][time->tm_mon];
+
+    /* Check if we are within valid range. */
+    if (time->tm_year == LAST_VALID_YEAR) {
+        if ((leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT && result > EDGE_TIMESTAMP_FULL_LEAP_YEAR_SUPPORT) ||
+            (leap_year_support == RTC_4_YEAR_LEAP_YEAR_SUPPORT && result > EDGE_TIMESTAMP_4_YEAR_LEAP_YEAR_SUPPORT)) {
+        return false;
+        }
+    }
 
     if (time->tm_year > 70) { 
-        // valid in the range [70:138] 
+        /* Valid in the range [70:206]. */
         uint32_t count_of_leap_days = ((time->tm_year - 1) / 4) - (70 / 4);
+        if (leap_year_support == RTC_FULL_LEAP_YEAR_SUPPORT) {
+            if (time->tm_year > 200) {
+                count_of_leap_days--; // 2100 is not a leap year
+            }
+        }
+
         result += (((time->tm_year - 70) * 365) + count_of_leap_days) * SECONDS_BY_DAY;
     }
 
-    if (result > INT32_MAX) { 
-        return (time_t) -1;
-    }
+    *seconds = result;
 
-    return result;
+    return true;
 }
 
-bool _rtc_localtime(time_t timestamp, struct tm* time_info) {
-    if (((int32_t) timestamp) < 0) { 
+bool _rtc_localtime(time_t timestamp, struct tm* time_info, rtc_leap_year_support_t leap_year_support) {
+    if (time_info == NULL) {
         return false;
-    } 
+    }
+
+    uint32_t seconds = (uint32_t)timestamp;
 
-    time_info->tm_sec = timestamp % 60;
-    timestamp = timestamp / 60;   // timestamp in minutes
-    time_info->tm_min = timestamp % 60;
-    timestamp = timestamp / 60;  // timestamp in hours
-    time_info->tm_hour = timestamp % 24;
-    timestamp = timestamp / 24;  // timestamp in days;
+    time_info->tm_sec = seconds % 60;
+    seconds = seconds / 60;   // timestamp in minutes
+    time_info->tm_min = seconds % 60;
+    seconds = seconds / 60;  // timestamp in hours
+    time_info->tm_hour = seconds % 24;
+    seconds = seconds / 24;  // timestamp in days;
 
-    // compute the weekday
-    // The 1st of January 1970 was a Thursday which is equal to 4 in the weekday
-    // representation ranging from [0:6]
-    time_info->tm_wday = (timestamp + 4) % 7;
+    /* Compute the weekday.
+     * The 1st of January 1970 was a Thursday which is equal to 4 in the weekday representation ranging from [0:6].
+     */
+    time_info->tm_wday = (seconds + 4) % 7;
 
-    // years start at 70
+    /* Years start at 70. */
     time_info->tm_year = 70;
     while (true) { 
-        if (_rtc_is_leap_year(time_info->tm_year) && timestamp >= 366) {
+        if (_rtc_is_leap_year(time_info->tm_year, leap_year_support) && seconds >= 366) {
             ++time_info->tm_year;
-            timestamp -= 366;
-        } else if (!_rtc_is_leap_year(time_info->tm_year) && timestamp >= 365) {
+            seconds -= 366;
+        } else if (!_rtc_is_leap_year(time_info->tm_year, leap_year_support) && seconds >= 365) {
             ++time_info->tm_year;
-            timestamp -= 365;
+            seconds -= 365;
         } else {
-            // the remaining days are less than a years
+            /* The remaining days are less than a years. */
             break;
         }
     }
 
-    time_info->tm_yday = timestamp;
+    time_info->tm_yday = seconds;
 
-    // convert days into seconds and find the current month
-    timestamp *= SECONDS_BY_DAY;
+    /* Convert days into seconds and find the current month. */
+    seconds *= SECONDS_BY_DAY;
     time_info->tm_mon = 11;
-    bool leap = _rtc_is_leap_year(time_info->tm_year);
+    bool leap = _rtc_is_leap_year(time_info->tm_year, leap_year_support);
     for (uint32_t i = 0; i < 12; ++i) {
-        if ((uint32_t) timestamp < seconds_before_month[leap][i]) {
+        if ((uint32_t) seconds < seconds_before_month[leap][i]) {
             time_info->tm_mon = i - 1;
             break;
         }
     }
 
-    // remove month from timestamp and compute the number of days.
-    // note: unlike other fields, days are not 0 indexed.
-    timestamp -= seconds_before_month[leap][time_info->tm_mon];
-    time_info->tm_mday = (timestamp / SECONDS_BY_DAY) + 1;
+    /* Remove month from timestamp and compute the number of days.
+     * Note: unlike other fields, days are not 0 indexed.
+     */
+    seconds -= seconds_before_month[leap][time_info->tm_mon];
+    time_info->tm_mday = (seconds / SECONDS_BY_DAY) + 1;
 
     return true;
 }

--- a/platform/mbed_mktime.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_mktime.h	Thu Apr 19 17:12:19 2018 +0100
@@ -33,14 +33,34 @@
  * @{
  */
 
+/* Time range across the whole 32-bit range should be supported which means that years in range 1970 - 2106 can be
+ * encoded. We have two types of RTC devices:
+ * a) RTCs which handles all leap years in the mentioned year range correctly. Leap year is determined by checking if
+ *    the year counter value is divisible by 400, 100, and 4. No problem here.
+ * b) RTCs which handles leap years correctly up to 2100. The RTC does a simple bit comparison to see if the two
+ *    lowest order bits of the year counter are zero. In this case 2100 year will be considered
+ *    incorrectly as a leap year, so the last valid point in time will be 28.02.2100 23:59:59 and next day will be
+ *    29.02.2100 (invalid). So after 28.02.2100 the day counter will be off by a day.
+ */
+typedef enum {
+    RTC_FULL_LEAP_YEAR_SUPPORT,
+    RTC_4_YEAR_LEAP_YEAR_SUPPORT
+} rtc_leap_year_support_t;
+
 /** Compute if a year is a leap year or not.
  *
- * @param year The year to test it shall be in the range [70:138]. Year 0 is
+ * @param year The year to test it shall be in the range [70:206]. Year 0 is
  * translated into year 1900 CE.
+ * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
+ * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
+ *
  * @return true if the year in input is a leap year and false otherwise.
- * @note - For use by the HAL only
+ *
+ * @note For use by the HAL only
+ * @note Year 2100 is treated differently for devices with full leap year support and devices with
+ * partial leap year support. Devices with partial leap year support treats 2100 as a leap year.
  */
-bool _rtc_is_leap_year(int year);
+bool _rtc_is_leap_year(int year, rtc_leap_year_support_t leap_year_support);
 
 /* Convert a calendar time into time since UNIX epoch as a time_t.
  *
@@ -48,7 +68,7 @@
  * tailored around RTC peripherals needs and is not by any mean a complete
  * replacement of mktime.
  *
- * @param calendar_time The calendar time to convert into a time_t since epoch.
+ * @param time The calendar time to convert into a time_t since epoch.
  * The fields from tm used for the computation are:
  *   - tm_sec
  *   - tm_min
@@ -57,17 +77,20 @@
  *   - tm_mon
  *   - tm_year
  * Other fields are ignored and won't be renormalized by a call to this function.
- * A valid calendar time is comprised between the 1st january of 1970 at
- * 00:00:00 and the 19th of january 2038 at 03:14:07.
+ * A valid calendar time is comprised between:
+ * the 1st of January 1970 at 00:00:00 to the 7th of February 2106 at 06:28:15.
+ * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
+ * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
+ * @param seconds holder for the result - calendar time as seconds since UNIX epoch.
  *
- * @return The calendar time as seconds since UNIX epoch if the input is in the
- * valid range. Otherwise ((time_t) -1).
+ * @return true on success, false if conversion error occurred.
  *
  * @note Leap seconds are not supported.
- * @note Values in output range from 0 to INT_MAX.
- * @note - For use by the HAL only
+ * @note Values in output range from 0 to UINT_MAX.
+ * @note Full and partial leap years support.
+ * @note For use by the HAL only
  */
-time_t _rtc_mktime(const struct tm* calendar_time);
+bool _rtc_maketime(const struct tm* time, time_t * seconds, rtc_leap_year_support_t leap_year_support);
 
 /* Convert a given time in seconds since epoch into calendar time.
  *
@@ -76,7 +99,7 @@
  * complete of localtime.
  *
  * @param timestamp The time (in seconds) to convert into calendar time. Valid
- * input are in the range [0 : INT32_MAX].
+ * input are in the range [0 : UINT32_MAX].
  * @param calendar_time Pointer to the object which will contain the result of
  * the conversion. The tm fields filled by this function are:
  *   - tm_sec
@@ -88,11 +111,14 @@
  *   - tm_wday
  *   - tm_yday
  * The object remains untouched if the time in input is invalid.
+ * @param leap_year_support use RTC_FULL_LEAP_YEAR_SUPPORT if RTC device is able
+ * to correctly detect all leap years in range [70:206] otherwise use RTC_4_YEAR_LEAP_YEAR_SUPPORT.
  * @return true if the conversion was successful, false otherwise.
  *
- * @note - For use by the HAL only
+ * @note For use by the HAL only.
+ * @note Full and partial leap years support.
  */
-bool _rtc_localtime(time_t timestamp, struct tm* calendar_time);
+bool _rtc_localtime(time_t timestamp, struct tm* time_info, rtc_leap_year_support_t leap_year_support);
 
 /** @}*/
 

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/platform/mbed_power_mgmt.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,216 @@
+/** \addtogroup platform */
+/** @{*/
+/**
+ * \defgroup platform_power_mgmt Power management functions
+ * @{
+ */
+
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_POWER_MGMT_H
+#define MBED_POWER_MGMT_H
+
+#include "sleep_api.h"
+#include "mbed_toolchain.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Sleep manager API
+ * The sleep manager provides API to automatically select sleep mode.
+ *
+ * There are two sleep modes:
+ * - sleep
+ * - deepsleep
+ *
+ * Use locking/unlocking deepsleep for drivers that depend on features that
+ * are not allowed (=disabled) during the deepsleep. For instance, high frequency
+ * clocks.
+ *
+ * Example:
+ * @code
+ *
+ * void driver::handler()
+ * {
+ *     if (_sensor.get_event()) {
+ *         // any event - we are finished, unlock the deepsleep
+ *         sleep_manager_unlock_deep_sleep();
+ *         _callback();
+ *     }
+ * }
+ *
+ * int driver::measure(event_t event, callback_t& callback)
+ * {
+ *      _callback = callback;
+ *      sleep_manager_lock_deep_sleep();
+ *      // start async transaction, we are waiting for an event
+ *      return _sensor.start(event, callback);
+ * }
+ * @endcode
+ */
+#ifdef MBED_SLEEP_TRACING_ENABLED
+
+void sleep_tracker_lock(const char *const filename, int line);
+void sleep_tracker_unlock(const char *const filename, int line);
+
+#define sleep_manager_lock_deep_sleep()              \
+    do                                               \
+    {                                                \
+        sleep_manager_lock_deep_sleep_internal();    \
+        sleep_tracker_lock(MBED_FILENAME, __LINE__); \
+    } while (0);
+
+#define sleep_manager_unlock_deep_sleep()              \
+    do                                                 \
+    {                                                  \
+        sleep_manager_unlock_deep_sleep_internal();    \
+        sleep_tracker_unlock(MBED_FILENAME, __LINE__); \
+    } while (0);
+
+#else
+
+#define sleep_manager_lock_deep_sleep() \
+    sleep_manager_lock_deep_sleep_internal()
+
+#define sleep_manager_unlock_deep_sleep() \
+    sleep_manager_unlock_deep_sleep_internal()
+
+#endif // MBED_SLEEP_TRACING_ENABLED
+
+/** Lock the deep sleep mode
+ *
+ * This locks the automatic deep mode selection.
+ * sleep_manager_sleep_auto() will ignore deepsleep mode if
+ * this function is invoked at least once (the internal counter is non-zero)
+ *
+ * Use this locking mechanism for interrupt driven API that are
+ * running in the background and deepsleep could affect their functionality
+ *
+ * The lock is a counter, can be locked up to USHRT_MAX
+ * This function is IRQ and thread safe
+ */
+void sleep_manager_lock_deep_sleep_internal(void);
+
+/** Unlock the deep sleep mode
+ *
+ * Use unlocking in pair with sleep_manager_lock_deep_sleep().
+ *
+ * The lock is a counter, should be equally unlocked as locked
+ * This function is IRQ and thread safe
+ */
+void sleep_manager_unlock_deep_sleep_internal(void);
+
+/** Get the status of deep sleep allowance for a target
+ *
+ * @return true if a target can go to deepsleep, false otherwise
+ */
+bool sleep_manager_can_deep_sleep(void);
+
+/** Enter auto selected sleep mode. It chooses the sleep or deeepsleep modes based
+ *  on the deepsleep locking counter
+ *
+ * This function is IRQ and thread safe
+ *
+ * @note
+ * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger
+ * to be active for debug modes.
+ *
+ */
+void sleep_manager_sleep_auto(void);
+
+/** Send the microcontroller to sleep
+ *
+ * @note This function can be a noop if not implemented by the platform.
+ * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined).
+ * @note This function will be a noop while uVisor is in use.
+ * @note This function will be a noop if the following conditions are met:
+ *   - The RTOS is present
+ *   - The processor turn off the Systick clock during sleep
+ *   - The target does not implement tickless mode
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+static inline void sleep(void)
+{
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+#if DEVICE_SLEEP
+#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS)
+    sleep_manager_sleep_auto();
+#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */
+#endif /* DEVICE_SLEEP */
+#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
+}
+
+/** Send the microcontroller to deep sleep
+ *
+ * @deprecated
+ * Do not use this function. Applications should use sleep() API which puts the system in deepsleep mode if supported. 
+ *
+ * @note This function can be a noop if not implemented by the platform.
+ * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined)
+ * @note This function will be a noop while uVisor is in use.
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep. This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+
+MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()")
+static inline void deepsleep(void)
+{
+#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
+#if DEVICE_SLEEP
+    sleep_manager_sleep_auto();
+#endif /* DEVICE_SLEEP */
+#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
+}
+
+/** Resets the processor and most of the sub-system
+ *
+ * @note Does not affect the debug sub-system
+ */
+static inline void system_reset(void)
+{
+    NVIC_SystemReset();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+/** @}*/
+/** @}*/

--- a/platform/mbed_retarget.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_retarget.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -26,15 +26,18 @@
 #include "platform/mbed_error.h"
 #include "platform/mbed_stats.h"
 #include "platform/mbed_critical.h"
+#include "platform/mbed_poll.h"
 #include "platform/PlatformMutex.h"
+#include "drivers/UARTSerial.h"
 #include "us_ticker_api.h"
 #include "lp_ticker_api.h"
 #include <stdlib.h>
 #include <string.h>
 #include <limits.h>
-#if DEVICE_STDIO_MESSAGES
+#ifndef SSIZE_MAX
+#define SSIZE_MAX INT_MAX
+#endif
 #include <stdio.h>
-#endif
 #include <errno.h>
 #include "platform/mbed_retarget.h"
 
@@ -67,7 +70,7 @@
 #   define PREFIX(x)    x
 #endif
 
-#define FILE_HANDLE_RESERVED    0xFFFFFFFF
+#define FILE_HANDLE_RESERVED    ((FileHandle*)0xFFFFFFFF)
 
 using namespace mbed;
 
@@ -89,12 +92,15 @@
 /* newlib has the filehandle field in the FILE struct as a short, so
  * we can't just return a Filehandle* from _open and instead have to
  * put it in a filehandles array and return the index into that array
- * (or rather index+3, as filehandles 0-2 are stdin/out/err).
  */
-static FileHandle *filehandles[OPEN_MAX];
+static FileHandle *filehandles[OPEN_MAX] = { FILE_HANDLE_RESERVED, FILE_HANDLE_RESERVED, FILE_HANDLE_RESERVED };
+static char stdio_in_prev[OPEN_MAX];
+static char stdio_out_prev[OPEN_MAX];
 static SingletonPtr<PlatformMutex> filehandle_mutex;
 
 namespace mbed {
+void mbed_set_unbuffered_stream(std::FILE *_file);
+
 void remove_filehandle(FileHandle *file) {
     filehandle_mutex->lock();
     /* Remove all open filehandles for this */
@@ -110,20 +116,138 @@
 #if DEVICE_SERIAL
 extern int stdio_uart_inited;
 extern serial_t stdio_uart;
-#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
-static char stdio_in_prev;
-static char stdio_out_prev;
-#endif
 #endif
 
-static void init_serial() {
-#if DEVICE_SERIAL
+/* Private FileHandle to implement backwards-compatible functionality of
+ * direct HAL serial access for default stdin/stdout/stderr.
+ * This is not a particularly well-behaved FileHandle for a stream, which
+ * is why it's not public. People should be using UARTSerial.
+ */
+class DirectSerial : public FileHandle {
+public:
+    DirectSerial(PinName tx, PinName rx, int baud);
+    virtual ssize_t write(const void *buffer, size_t size);
+    virtual ssize_t read(void *buffer, size_t size);
+    virtual off_t seek(off_t offset, int whence = SEEK_SET) {
+        return -ESPIPE;
+    }
+    virtual off_t size() {
+        return -EINVAL;
+    }
+    virtual int isatty() {
+        return true;
+    }
+    virtual int close() {
+        return 0;
+    }
+    virtual short poll(short events) const;
+};
+
+DirectSerial::DirectSerial(PinName tx, PinName rx, int baud) {
     if (stdio_uart_inited) return;
-    serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
-#if MBED_CONF_PLATFORM_STDIO_BAUD_RATE
-    serial_baud(&stdio_uart, MBED_CONF_PLATFORM_STDIO_BAUD_RATE);
+    serial_init(&stdio_uart, tx, rx);
+    serial_baud(&stdio_uart, baud);
+}
+
+ssize_t DirectSerial::write(const void *buffer, size_t size) {
+    const unsigned char *buf = static_cast<const unsigned char *>(buffer);
+    for (size_t i = 0; i < size; i++) {
+        serial_putc(&stdio_uart, buf[i]);
+    }
+    return size;
+}
+
+ssize_t DirectSerial::read(void *buffer, size_t size) {
+    unsigned char *buf = static_cast<unsigned char *>(buffer);
+    if (size == 0) {
+        return 0;
+    }
+    buf[0] = serial_getc(&stdio_uart);
+    return 1;
+}
+
+short DirectSerial::poll(short events) const {
+    short revents = 0;
+    if ((events & POLLIN) && serial_readable(&stdio_uart)) {
+        revents |= POLLIN;
+    }
+    if ((events & POLLOUT) && serial_writable(&stdio_uart)) {
+        revents |= POLLOUT;
+    }
+    return revents;
+}
+
+class Sink : public FileHandle {
+public:
+    virtual ssize_t write(const void *buffer, size_t size);
+    virtual ssize_t read(void *buffer, size_t size);
+    virtual off_t seek(off_t offset, int whence = SEEK_SET) { return ESPIPE; }
+    virtual off_t size() { return -EINVAL; }
+    virtual int isatty() { return true; }
+    virtual int close() { return 0; }
+};
+
+ssize_t Sink::write(const void *buffer, size_t size) {
+    // Just swallow the data - this is historical non-DEVICE_SERIAL behaviour
+    return size;
+}
+
+ssize_t Sink::read(void *buffer, size_t size) {
+    // Produce 1 zero byte - historical behaviour returned 1 without touching
+    // the buffer
+    unsigned char *buf = static_cast<unsigned char *>(buffer);
+    buf[0] = 0;
+    return 1;
+}
+
+
+MBED_WEAK FileHandle* mbed::mbed_target_override_console(int fd)
+{
+    return NULL;
+}
+
+MBED_WEAK FileHandle* mbed::mbed_override_console(int fd)
+{
+    return NULL;
+}
+
+static FileHandle* default_console()
+{
+#if DEVICE_SERIAL
+#  if MBED_CONF_PLATFORM_STDIO_BUFFERED_SERIAL
+    static UARTSerial console(STDIO_UART_TX, STDIO_UART_RX, MBED_CONF_PLATFORM_STDIO_BAUD_RATE);
+#  else
+    static DirectSerial console(STDIO_UART_TX, STDIO_UART_RX, MBED_CONF_PLATFORM_STDIO_BAUD_RATE);
+#  endif
+#else // DEVICE_SERIAL
+    static Sink console;
 #endif
-#endif
+    return &console;
+}
+
+/* Locate the default console for stdout, stdin, stderr */
+static FileHandle* get_console(int fd) {
+    FileHandle *fh = mbed_override_console(fd);
+    if (fh) {
+        return fh;
+    }
+    fh = mbed_target_override_console(fd);
+    if (fh) {
+        return fh;
+    }
+    return default_console();
+}
+
+/* Deal with the fact C library may not _open descriptors 0, 1, 2 - auto bind */
+static FileHandle* get_fhc(int fd) {
+    if (fd >= OPEN_MAX) {
+        return NULL;
+    }
+    FileHandle *fh = filehandles[fd];
+    if (fh == FILE_HANDLE_RESERVED && fd < 3) {
+        filehandles[fd] = fh = get_console(fd);
+    }
+    return fh;
 }
 
 /**
@@ -140,41 +264,123 @@
     return -1;
 }
 
-static inline int openmode_to_posix(int openmode) {
-    int posix = openmode;
+static inline int openflags_to_posix(int openflags) {
+    int posix = openflags;
 #ifdef __ARMCC_VERSION
-    if (openmode & OPEN_PLUS) {
+    if (openflags & OPEN_PLUS) {
         posix = O_RDWR;
-    } else if(openmode & OPEN_W) {
+    } else if(openflags & OPEN_W) {
         posix = O_WRONLY;
-    } else if(openmode & OPEN_A) {
+    } else if(openflags & OPEN_A) {
         posix = O_WRONLY|O_APPEND;
     } else {
         posix = O_RDONLY;
     }
     /* a, w, a+, w+ all create if file does not already exist */
-    if (openmode & (OPEN_A|OPEN_W)) {
+    if (openflags & (OPEN_A|OPEN_W)) {
         posix |= O_CREAT;
     }
     /* w and w+ truncate */
-    if (openmode & OPEN_W) {
+    if (openflags & OPEN_W) {
         posix |= O_TRUNC;
     }
 #elif defined(__ICCARM__)
-    switch (openmode & _LLIO_RDWRMASK) {
+    switch (openflags & _LLIO_RDWRMASK) {
         case _LLIO_RDONLY: posix = O_RDONLY; break;
         case _LLIO_WRONLY: posix = O_WRONLY; break;
         case _LLIO_RDWR  : posix = O_RDWR  ; break;
     }
-    if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
-    if (openmode & _LLIO_APPEND) posix |= O_APPEND;
-    if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
+    if (openflags & _LLIO_CREAT ) posix |= O_CREAT;
+    if (openflags & _LLIO_APPEND) posix |= O_APPEND;
+    if (openflags & _LLIO_TRUNC ) posix |= O_TRUNC;
 #elif defined(TOOLCHAIN_GCC)
     posix &= ~O_BINARY;
 #endif
     return posix;
 }
 
+static int reserve_filehandle() {
+    // find the first empty slot in filehandles, after the slots reserved for stdin/stdout/stderr
+    filehandle_mutex->lock();
+    int fh_i;
+    for (fh_i = 3; fh_i < OPEN_MAX; fh_i++) {
+        /* Take a next free filehandle slot available. */
+        if (filehandles[fh_i] == NULL) break;
+    }
+    if (fh_i >= OPEN_MAX) {
+        /* Too many file handles have been opened */
+        errno = EMFILE;
+        filehandle_mutex->unlock();
+        return -1;
+    }
+    filehandles[fh_i] = FILE_HANDLE_RESERVED;
+    filehandle_mutex->unlock();
+
+    return fh_i;
+}
+
+int mbed::bind_to_fd(FileHandle *fh) {
+    int fh_i = reserve_filehandle();
+    if (fh_i < 0) {
+        return fh_i;
+    }
+
+    filehandles[fh_i] = fh;
+    stdio_in_prev[fh_i] = 0;
+    stdio_out_prev[fh_i] = 0;
+
+    return fh_i;
+}
+
+static int unbind_from_fd(int fd, FileHandle *fh) {
+    if (filehandles[fd] == fh) {
+        filehandles[fd] = NULL;
+        return 0;
+    } else {
+        errno = EBADF;
+        return -1;
+    }
+}
+
+#ifndef __IAR_SYSTEMS_ICC__
+/* IAR provides fdopen itself */
+extern "C" std::FILE* fdopen(int fildes, const char *mode)
+{
+    // This is to avoid scanf and the bloat it brings.
+    char buf[1 + sizeof fildes]; /* @(integer) */
+    MBED_STATIC_ASSERT(sizeof buf == 5, "Integers should be 4 bytes.");
+    buf[0] = '@';
+    memcpy(buf + 1, &fildes, sizeof fildes);
+
+    std::FILE *stream = std::fopen(buf, mode);
+    /* newlib-nano doesn't appear to ever call _isatty itself, so
+     * happily fully buffers an interactive stream. Deal with that here.
+     */
+    if (stream && isatty(fildes)) {
+        mbed_set_unbuffered_stream(stream);
+    }
+    return stream;
+}
+#endif
+
+namespace mbed {
+std::FILE *fdopen(FileHandle *fh, const char *mode)
+{
+    // First reserve the integer file descriptor
+    int fd = bind_to_fd(fh);
+    if (!fd) {
+        return NULL;
+    }
+    // Then bind that to the C stream. If successful, C library
+    // takes ownership and responsibility to close.
+    std::FILE *stream = ::fdopen(fd, mode);
+    if (!stream) {
+        unbind_from_fd(fd, fh);
+    }
+    return stream;
+}
+}
+
 /* @brief 	standard c library fopen() retargeting function.
  *
  * This function is invoked by the standard c library retargeting to handle fopen()
@@ -186,8 +392,8 @@
  *	 EMFILE		the maximum number of open files was exceeded.
  *
  * */
-extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
-    #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+extern "C" FILEHANDLE PREFIX(_open)(const char *name, int openflags) {
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
 #if !defined(MBED_CONF_RTOS_PRESENT)
     // valid only for mbed 2
     // for ulib, this is invoked after RAM init, prior c++
@@ -205,82 +411,77 @@
     // Before version 5.03, we were using a patched version of microlib with proper names
     // This is the workaround that the microlib author suggested us
     static int n = 0;
-    if (!std::strcmp(name, ":tt")) return n++;
-    #else
+    if (std::strcmp(name, ":tt") == 0 && n < 3) {
+        return n++;
+    }
+#else
     /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
      */
     if (std::strcmp(name, __stdin_name) == 0) {
-        init_serial();
-        return 0;
+        get_fhc(STDIN_FILENO);
+        return STDIN_FILENO;
     } else if (std::strcmp(name, __stdout_name) == 0) {
-        init_serial();
-        return 1;
+        get_fhc(STDOUT_FILENO);
+        return STDOUT_FILENO;
     } else if (std::strcmp(name, __stderr_name) == 0) {
-        init_serial();
-        return 2;
+        get_fhc(STDERR_FILENO);
+        return STDERR_FILENO;
     }
-    #endif
+#endif
+#ifndef __IAR_SYSTEMS_ICC__
+    /* FILENAME: "@(integer)" gives an already-allocated descriptor */
+    if (name[0] == '@') {
+        int fd;
+        memcpy(&fd, name + 1, sizeof fd);
+        return fd;
+    }
+#endif
+    return open(name, openflags_to_posix(openflags));
+}
 
-    // find the first empty slot in filehandles
-    filehandle_mutex->lock();
-    unsigned int fh_i;
-    for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
-    	/* Take a next free filehandle slot available. */
-        if (filehandles[fh_i] == NULL) break;
+extern "C" int open(const char *name, int oflag, ...) {
+    int fh_i = reserve_filehandle();
+    if (fh_i < 0) {
+        return fh_i;
     }
-    if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
-        /* Too many file handles have been opened */
-        errno = EMFILE;
-        filehandle_mutex->unlock();
-        return -1;
-    }
-    filehandles[fh_i] = (FileHandle*)FILE_HANDLE_RESERVED;
-    filehandle_mutex->unlock();
 
     FileHandle *res = NULL;
-
-    /* FILENAME: ":(pointer)" describes a FileHandle* */
-    if (name[0] == ':') {
-        void *p;
-        memcpy(&p, name + 1, sizeof(p));
-        res = (FileHandle*)p;
+    FilePath path(name);
 
-    /* FILENAME: "/file_system/file_name" */
-    } else {
-        FilePath path(name);
+    if (!path.exists()) {
+        /* The first part of the filename (between first 2 '/') is not a
+         * registered mount point in the namespace.
+         */
+        return handle_open_errors(-ENODEV, fh_i);
+    }
 
-        if (!path.exists()) {
-            /* The first part of the filename (between first 2 '/') is not a
-             * registered mount point in the namespace.
-             */
+    if (path.isFile()) {
+        res = path.file();
+    } else {
+        FileSystemHandle *fs = path.fileSystem();
+        if (fs == NULL) {
             return handle_open_errors(-ENODEV, fh_i);
         }
-
-        if (path.isFile()) {
-            res = path.file();
-        } else {
-            FileSystemHandle *fs = path.fileSystem();
-            if (fs == NULL) {
-                return handle_open_errors(-ENODEV, fh_i);
-            }
-            int posix_mode = openmode_to_posix(openmode);
-            int err = fs->open(&res, path.fileName(), posix_mode);
-            if (err) {
-                return handle_open_errors(err, fh_i);
-            }
+        int err = fs->open(&res, path.fileName(), oflag);
+        if (err) {
+            return handle_open_errors(err, fh_i);
         }
     }
 
     filehandles[fh_i] = res;
+    stdio_in_prev[fh_i] = 0;
+    stdio_out_prev[fh_i] = 0;
 
-    return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
+    return fh_i;
 }
 
 extern "C" int PREFIX(_close)(FILEHANDLE fh) {
-    if (fh < 3) return 0;
+    return close(fh);
+}
 
-    FileHandle* fhc = filehandles[fh-3];
-    filehandles[fh-3] = NULL;
+extern "C" int close(int fh) {
+    FileHandle* fhc = get_fhc(fh);
+    filehandles[fh] = NULL;
     if (fhc == NULL) {
         errno = EBADF;
         return -1;
@@ -295,12 +496,21 @@
     }
 }
 
+static bool convert_crlf(int fd) {
+#if MBED_CONF_PLATFORM_STDIO_CONVERT_TTY_NEWLINES
+    return isatty(fd);
+#elif MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+    return fd < 3 && isatty(fd);
+#else
+    return false;
+#endif
+}
+
 #if defined(__ICCARM__)
 extern "C" size_t    __write (int        fh, const unsigned char *buffer, size_t length) {
 #else
 extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
 #endif
-    int n; // n is the number of bytes written
 
 #if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED && defined(MBED_CONF_RTOS_PRESENT)
     if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) {
@@ -308,52 +518,99 @@
     }
 #endif
 
-    if (fh < 3) {
-#if DEVICE_SERIAL
-        if (!stdio_uart_inited) init_serial();
-#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
-        for (unsigned int i = 0; i < length; i++) {
-            if (buffer[i] == '\n' && stdio_out_prev != '\r') {
-                 serial_putc(&stdio_uart, '\r');
+    if (length > SSIZE_MAX) {
+        errno = EINVAL;
+        return -1;
+    }
+
+    ssize_t slength = length;
+    ssize_t written = 0;
+
+    if (convert_crlf(fh)) {
+        // local prev is previous in buffer during seek
+        // stdio_out_prev[fh] is last thing actually written
+        char prev = stdio_out_prev[fh];
+        // Seek for '\n' without preceding '\r'; if found flush
+        // preceding and insert '\r'. Continue until end of input.
+        for (ssize_t cur = 0; cur < slength; cur++) {
+            if (buffer[cur] == '\n' && prev != '\r') {
+                ssize_t r;
+                // flush stuff preceding the \n
+                if (cur > written) {
+                    r = write(fh, buffer + written, cur - written);
+                    if (r < 0) {
+                        return -1;
+                    }
+                    written += r;
+                    if (written < cur) {
+                        // For some reason, didn't write all - give up now
+                        goto finish;
+                    }
+                    stdio_out_prev[fh] = prev;
+                }
+                // insert a \r now, leaving the \n still to be written
+                r = write(fh, "\r", 1);
+                if (r < 0) {
+                    return -1;
+                }
+                if (r < 1) {
+                    goto finish;
+                }
+                stdio_out_prev[fh] = '\r';
             }
-            serial_putc(&stdio_uart, buffer[i]);
-            stdio_out_prev = buffer[i];
+            prev = buffer[cur];
         }
-#else
-        for (unsigned int i = 0; i < length; i++) {
-            serial_putc(&stdio_uart, buffer[i]);
-        }
-#endif
-#endif
-        n = length;
-    } else {
-        FileHandle* fhc = filehandles[fh-3];
-        if (fhc == NULL) {
-            errno = EBADF;
+    }
+
+    // Flush remaining from conversion, or the whole thing if no conversion
+    if (written < slength) {
+        ssize_t r = write(fh, buffer + written, slength - written);
+        if (r < 0) {
             return -1;
         }
-
-        n = fhc->write(buffer, length);
-        if (n < 0) {
-            errno = -n;
+        written += r;
+        if (written > 0) {
+            stdio_out_prev[fh] = buffer[written - 1];
         }
     }
+
+finish:
 #ifdef __ARMCC_VERSION
-    return length-n;
+    if (written >= 0) {
+        return slength - written;
+    } else {
+        return written;
+    }
 #else
-    return n;
+    return written;
 #endif
 }
 
+extern "C" ssize_t write(int fh, const void *buf, size_t length) {
+
+    FileHandle* fhc = get_fhc(fh);
+    if (fhc == NULL) {
+        errno = EBADF;
+        return -1;
+    }
+
+    ssize_t ret = fhc->write(buf, length);
+    if (ret < 0) {
+        errno = -ret;
+        return -1;
+    } else {
+        return ret;
+    }
+}
+
 #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
 extern "C" void PREFIX(_exit)(int return_code) {
     while(1) {}
 }
 
 extern "C" void _ttywrch(int ch) {
-#if DEVICE_SERIAL
-    serial_putc(&stdio_uart, ch);
-#endif
+    char c = ch;
+    write(STDOUT_FILENO, &c, 1);
 }
 #endif
 
@@ -362,7 +619,6 @@
 #else
 extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
 #endif
-    int n; // n is the number of bytes read
 
 #if defined(MBED_TRAP_ERRORS_ENABLED) && MBED_TRAP_ERRORS_ENABLED && defined(MBED_CONF_RTOS_PRESENT)
     if (core_util_is_isr_active() || !core_util_are_interrupts_enabled()) {
@@ -370,51 +626,71 @@
     }
 #endif
 
-    if (fh < 3) {
-        // only read a character at a time from stdin
-#if DEVICE_SERIAL
-        if (!stdio_uart_inited) init_serial();
-#if MBED_CONF_PLATFORM_STDIO_CONVERT_NEWLINES
+    if (length > SSIZE_MAX) {
+        errno = EINVAL;
+        return -1;
+    }
+
+    ssize_t bytes_read = 0;
+
+    if (convert_crlf(fh)) {
         while (true) {
-            char c = serial_getc(&stdio_uart);
-            if ((c == '\r' && stdio_in_prev != '\n') ||
-                (c == '\n' && stdio_in_prev != '\r')) {
-                stdio_in_prev = c;
+            char c;
+            ssize_t r = read(fh, &c, 1);
+            if (r < 0) {
+                return -1;
+            }
+            if (r == 0) {
+                return bytes_read;
+            }
+            if ((c == '\r' && stdio_in_prev[fh] != '\n') ||
+                (c == '\n' && stdio_in_prev[fh] != '\r')) {
+                stdio_in_prev[fh] = c;
                 *buffer = '\n';
                 break;
-            } else if ((c == '\r' && stdio_in_prev == '\n') ||
-                       (c == '\n' && stdio_in_prev == '\r')) {
-                stdio_in_prev = c;
-                // onto next character
+            } else if ((c == '\r' && stdio_in_prev[fh] == '\n') ||
+                       (c == '\n' && stdio_in_prev[fh] == '\r')) {
+                stdio_in_prev[fh] = c;
                 continue;
             } else {
-                stdio_in_prev = c;
+                stdio_in_prev[fh] = c;
                 *buffer = c;
                 break;
             }
         }
-#else
-        *buffer = serial_getc(&stdio_uart);
-#endif
-#endif
-        n = 1;
+        bytes_read = 1;
+    } else {
+        bytes_read = read(fh, buffer, length);
+    }
+
+#ifdef __ARMCC_VERSION
+    if (bytes_read < 0) {
+        return -1;
+    } else if (bytes_read == 0) {
+        return 0x80000000 | length; // weird EOF indication
     } else {
-        FileHandle* fhc = filehandles[fh-3];
-        if (fhc == NULL) {
-            errno = EBADF;
-            return -1;
-        }
+        return (ssize_t)length - bytes_read;
+    }
+#else
+    return bytes_read;
+#endif
+}
+
+extern "C" ssize_t read(int fh, void *buf, size_t length) {
 
-        n = fhc->read(buffer, length);
-        if (n < 0) {
-            errno = -n;
-        }
+    FileHandle* fhc = get_fhc(fh);
+    if (fhc == NULL) {
+        errno = EBADF;
+        return -1;
     }
-#ifdef __ARMCC_VERSION
-    return length-n;
-#else
-    return n;
-#endif
+
+    ssize_t ret = fhc->read(buf, length);
+    if (ret < 0) {
+        errno = -ret;
+        return -1;
+    } else {
+        return ret;
+    }
 }
 
 
@@ -424,10 +700,11 @@
 extern "C" int _isatty(FILEHANDLE fh)
 #endif
 {
-    /* stdin, stdout and stderr should be tty */
-    if (fh < 3) return 1;
+    return isatty(fh);
+}
 
-    FileHandle* fhc = filehandles[fh-3];
+extern "C" int isatty(int fh) {
+    FileHandle* fhc = get_fhc(fh);
     if (fhc == NULL) {
         errno = EBADF;
         return 0;
@@ -455,12 +732,17 @@
     int whence = SEEK_SET;
 #endif
 
-    if (fh < 3) {
-        errno = ESPIPE;
+    off_t off = lseek(fh, offset, whence);
+    // Assuming INT_MAX = LONG_MAX, so we don't care about prototype difference
+    if (off > INT_MAX) {
+        errno = EOVERFLOW;
         return -1;
     }
+    return off;
+}
 
-    FileHandle* fhc = filehandles[fh-3];
+extern "C" off_t lseek(int fh, off_t offset, int whence) {
+    FileHandle* fhc = get_fhc(fh);
     if (fhc == NULL) {
         errno = EBADF;
         return -1;
@@ -471,19 +753,17 @@
         errno = -off;
         return -1;
     }
-    // Assuming INT_MAX = LONG_MAX, so we don't care about prototype difference
-    if (off > INT_MAX) {
-        errno = EOVERFLOW;
-        return -1;
-    }
     return off;
 }
 
 #ifdef __ARMCC_VERSION
 extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
-    if (fh < 3) return 0;
+    return fsync(fh);
+}
+#endif
 
-    FileHandle* fhc = filehandles[fh-3];
+extern "C" int fsync(int fh) {
+    FileHandle* fhc = get_fhc(fh);
     if (fhc == NULL) {
         errno = EBADF;
         return -1;
@@ -498,13 +778,9 @@
     }
 }
 
+#ifdef __ARMCC_VERSION
 extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
-    if (fh < 3) {
-        errno = EINVAL;
-        return -1;
-    }
-
-    FileHandle* fhc = filehandles[fh-3];
+    FileHandle* fhc = get_fhc(fh);
     if (fhc == NULL) {
         errno = EBADF;
         return -1;
@@ -546,12 +822,12 @@
 
 #if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
 extern "C" int _fstat(int fh, struct stat *st) {
-    if (fh < 3) {
-        st->st_mode = S_IFCHR;
-        return  0;
-    }
+    return fstat(fh, st);
+}
+#endif
 
-    FileHandle* fhc = filehandles[fh-3];
+extern "C" int fstat(int fh, struct stat *st) {
+    FileHandle* fhc = get_fhc(fh);
     if (fhc == NULL) {
         errno = EBADF;
         return -1;
@@ -561,7 +837,27 @@
     st->st_size = fhc->size();
     return 0;
 }
-#endif
+
+extern "C" int poll(struct pollfd fds[], nfds_t nfds, int timeout)
+{
+    if (nfds > OPEN_MAX) {
+        errno = EINVAL;
+        return -1;
+    }
+
+    struct mbed::pollfh fhs[OPEN_MAX];
+    for (nfds_t n = 0; n < nfds; n++) {
+        // Underlying FileHandle poll returns POLLNVAL if given NULL, so
+        // we don't need to take special action.
+        fhs[n].fh = get_fhc(fds[n].fd);
+        fhs[n].events = fds[n].events;
+    }
+    int ret = poll(fhs, nfds, timeout);
+    for (nfds_t n = 0; n < nfds; n++) {
+        fds[n].revents = fhs[n].revents;
+    }
+    return ret;
+}
 
 namespace std {
 extern "C" int remove(const char *path) {
@@ -711,6 +1007,23 @@
     }
 }
 
+extern "C" int statvfs(const char *path, struct statvfs *buf) {
+    FilePath fp(path);
+    FileSystemHandle *fs = fp.fileSystem();
+    if (fs == NULL) {
+        errno = ENODEV;
+        return -1;
+    }
+
+    int err = fs->statvfs(fp.fileName(), buf);
+    if (err < 0) {
+        errno = -err;
+        return -1;
+    } else {
+        return 0;
+    }
+}
+
 #if defined(TOOLCHAIN_GCC)
 /* prevents the exception handling name demangling code getting pulled in */
 #include "mbed_error.h"
@@ -881,28 +1194,6 @@
 #endif
 }
 
-/* Applications are expected to use fdopen()
- * not this function directly. This code had to live here because FILE and FileHandle
- * processes are all linked together here.
- */
-std::FILE *mbed_fdopen(FileHandle *fh, const char *mode)
-{
-    // This is to avoid scanf(buf, ":%.4s", fh) and the bloat it brings.
-    char buf[1 + sizeof(fh)]; /* :(pointer) */
-    MBED_STATIC_ASSERT(sizeof(buf) == 5, "Pointers should be 4 bytes.");
-    buf[0] = ':';
-    memcpy(buf + 1, &fh, sizeof(fh));
-
-    std::FILE *stream = std::fopen(buf, mode);
-    /* newlib-nano doesn't appear to ever call _isatty itself, so
-     * happily fully buffers an interactive stream. Deal with that here.
-     */
-    if (stream && fh->isatty()) {
-        mbed_set_unbuffered_stream(stream);
-    }
-    return stream;
-}
-
 int mbed_getc(std::FILE *_file){
 #if defined(__IAR_SYSTEMS_ICC__ ) && (__VER__ < 8000000)
     /*This is only valid for unbuffered streams*/

--- a/platform/mbed_retarget.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_retarget.h	Thu Apr 19 17:12:19 2018 +0100
@@ -21,6 +21,8 @@
 
 #if __cplusplus
 #include <cstdio>
+#else
+#include <stdio.h>
 #endif //__cplusplus
 #include <stdint.h>
 #include <stddef.h>
@@ -30,6 +32,8 @@
  * target embedded systems */
 typedef signed   int  ssize_t;  ///< Signed size type, usually encodes negative errors
 typedef signed   long off_t;    ///< Offset in a data stream
+typedef unsigned int  nfds_t;   ///< Number of file descriptors
+typedef unsigned long long fsblkcnt_t;  ///< Count of file system blocks
 #if defined(__ARMCC_VERSION) || !defined(__GNUC__)
 typedef unsigned int  mode_t;   ///< Mode for opening files
 typedef unsigned int  dev_t;    ///< Device ID type
@@ -50,6 +54,10 @@
 
 #define NAME_MAX 255    ///< Maximum size of a name in a file path
 
+#define STDIN_FILENO  0
+#define STDOUT_FILENO 1
+#define STDERR_FILENO 2
+
 #include <time.h>
 
 /** \addtogroup platform */
@@ -62,32 +70,57 @@
 /* DIR declarations must also be here */
 #if __cplusplus
 namespace mbed {
-    
+
 class FileHandle;
 class DirHandle;
-std::FILE *mbed_fdopen(FileHandle *fh, const char *mode);
+
+/** Targets may implement this to change stdin, stdout, stderr.
+ *
+ * If the application hasn't provided mbed_override_console, this is called
+ * to give the target a chance to specify a FileHandle for the console.
+ *
+ * If this is not provided or returns NULL, the console will be:
+ *   - UARTSerial if configuration option "platform.stdio-buffered-serial" is
+ *     true and the target has DEVICE_SERIAL;
+ *   - Raw HAL serial via serial_getc and serial_putc if
+ *     "platform.stdio-buffered-serial" is false and the target has DEVICE_SERIAL;
+ *   - stdout/stderr will be a sink and stdin will input a stream of 0s if the
+ *     target does not have DEVICE_SERIAL.
+ *
+ * @param fd file descriptor - STDIN_FILENO, STDOUT_FILENO or STDERR_FILENO
+ * @return  pointer to FileHandle to override normal stream otherwise NULL
+ */
+FileHandle* mbed_target_override_console(int fd);
+
+/** Applications may implement this to change stdin, stdout, stderr.
+ *
+ * This hook gives the application a chance to specify a custom FileHandle
+ * for the console.
+ *
+ * If this is not provided or returns NULL, the console will be specified
+ * by mbed_target_override_console, else will default to serial - see
+ * mbed_target_override_console for more details.
+ *
+ * Example:
+ * @code
+ * FileHandle* mbed::mbed_override_console(int) {
+ *     static UARTSerial my_serial(D0, D1);
+ *     return &my_serial;
+ * }
+ * @endcode
+
+ * @param fd file descriptor - STDIN_FILENO, STDOUT_FILENO or STDERR_FILENO
+ * @return  pointer to FileHandle to override normal stream otherwise NULL
+ */
+FileHandle* mbed_override_console(int fd);
 
 }
+
 typedef mbed::DirHandle DIR;
 #else
 typedef struct Dir DIR;
 #endif
 
-#if __cplusplus
-extern "C" {
-#endif
-    DIR *opendir(const char*);
-    struct dirent *readdir(DIR *);
-    int closedir(DIR*);
-    void rewinddir(DIR*);
-    long telldir(DIR*);
-    void seekdir(DIR*, long);
-    int mkdir(const char *name, mode_t n);
-#if __cplusplus
-};
-#endif
-
-
 /* The intent of this section is to unify the errno error values to match
  * the POSIX definitions for the GCC_ARM, ARMCC and IAR compilers. This is
  * necessary because the ARMCC/IAR errno.h, or sys/stat.h are missing some
@@ -389,7 +422,7 @@
 #define     S_IXUSR 0000100 ///< execute/search permission, owner
 #define S_IRWXG     (S_IRGRP | S_IWGRP | S_IXGRP)
 #define     S_IRGRP 0000040 ///< read permission, group
-#define     S_IWGRP 0000020 ///< write permission, grougroup
+#define     S_IWGRP 0000020 ///< write permission, group
 #define     S_IXGRP 0000010 ///< execute/search permission, group
 #define S_IRWXO     (S_IROTH | S_IWOTH | S_IXOTH)
 #define     S_IROTH 0000004 ///< read permission, other
@@ -415,16 +448,20 @@
     time_t    st_ctime;   ///< Time of last status change
 };
 
-#if __cplusplus
-extern "C" {
-#endif
-    int stat(const char *path, struct stat *st);
-#if __cplusplus
+struct statvfs {
+    unsigned long  f_bsize;    ///< Filesystem block size
+    unsigned long  f_frsize;   ///< Fragment size (block size)
+
+    fsblkcnt_t     f_blocks;   ///< Number of blocks
+    fsblkcnt_t     f_bfree;    ///< Number of free blocks
+    fsblkcnt_t     f_bavail;   ///< Number of free blocks for unprivileged users
+
+    unsigned long  f_fsid;     ///< Filesystem ID
+
+    unsigned long  f_namemax;  ///< Maximum filename length
 };
-#endif
 
-
-/* The following are dirent.h definitions are declared here to garuntee
+/* The following are dirent.h definitions are declared here to guarantee
  * consistency where structure may be different with different toolchains
  */
 struct dirent {
@@ -443,6 +480,78 @@
     DT_SOCK,    ///< This is a UNIX domain socket.
 };
 
+struct pollfd {
+    int fd;
+    short events;
+    short revents;
+};
+
+/* POSIX-compatible I/O functions */
+#if __cplusplus
+extern "C" {
+#endif
+    int open(const char *path, int oflag, ...);
+#ifndef __IAR_SYSTEMS_ICC__ /* IAR provides fdopen itself */
+#if __cplusplus
+    std::FILE* fdopen(int fildes, const char *mode);
+#else
+    FILE* fdopen(int fildes, const char *mode);
+#endif
+#endif
+    ssize_t write(int fildes, const void *buf, size_t nbyte);
+    ssize_t read(int fildes, void *buf, size_t nbyte);
+    off_t lseek(int fildes, off_t offset, int whence);
+    int isatty(int fildes);
+    int fsync(int fildes);
+    int fstat(int fh, struct stat *st);
+    int poll(struct pollfd fds[], nfds_t nfds, int timeout);
+    int close(int fildes);
+    int stat(const char *path, struct stat *st);
+    int statvfs(const char *path, struct statvfs *buf);
+    DIR *opendir(const char*);
+    struct dirent *readdir(DIR *);
+    int closedir(DIR*);
+    void rewinddir(DIR*);
+    long telldir(DIR*);
+    void seekdir(DIR*, long);
+    int mkdir(const char *name, mode_t n);
+#if __cplusplus
+}; // extern "C"
+
+namespace mbed {
+
+/** This call is an analogue to POSIX fdopen().
+ *
+ *  It associates a C stream to an already-opened FileHandle, to allow you to
+ *  use C printf/scanf/fwrite etc. The provided FileHandle must remain open -
+ *  it will be closed by the C library when fclose(FILE) is called.
+ *
+ *  The net effect is fdopen(bind_to_fd(fh), mode), with error handling.
+ *
+ *  @param fh       a pointer to an opened FileHandle
+ *  @param mode     operation upon the file descriptor, e.g., "w+"
+ *
+ *  @returns        a pointer to FILE
+ */
+std::FILE* fdopen(mbed::FileHandle *fh, const char *mode);
+
+/** Bind an mbed FileHandle to a POSIX file descriptor
+ *
+ * This is similar to fdopen, but only operating at the POSIX layer - it
+ * associates a POSIX integer file descriptor with a FileHandle, to allow you
+ * to use POSIX read/write calls etc. The provided FileHandle must remain open -
+ * it will be closed when close(int) is called.
+ *
+ *  @param fh       a pointer to an opened FileHandle
+ *
+ *  @return         an integer file descriptor, or negative if no descriptors available
+ */
+int bind_to_fd(mbed::FileHandle *fh);
+
+} // namespace mbed
+
+#endif // __cplusplus
+
 /**@}*/
 
 /**@}*/

--- a/platform/mbed_sleep.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_sleep.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,177 +1,23 @@
-
-/** \addtogroup platform */
-/** @{*/
-/**
- * \defgroup platform_sleep Sleep functions
- * @{
- */
- 
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
+/*
+ * Copyright (c) 2018, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
  * You may obtain a copy of the License at
  *
- *     http://www.apache.org/licenses/LICENSE-2.0
+ * http://www.apache.org/licenses/LICENSE-2.0
  *
  * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#ifndef MBED_SLEEP_H
-#define MBED_SLEEP_H
-
-#include "hal/sleep_api.h"
-#include "mbed_toolchain.h"
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Sleep manager API
- * The sleep manager provides API to automatically select sleep mode.
- *
- * There are two sleep modes:
- * - sleep
- * - deepsleep
- *
- * Use locking/unlocking deepsleep for drivers that depend on features that
- * are not allowed (=disabled) during the deepsleep. For instance, high frequency
- * clocks.
- *
- * Example:
- * @code
- *
- * void driver::handler()
- * {
- *     if (_sensor.get_event()) {
- *         // any event - we are finished, unlock the deepsleep
- *         sleep_manager_unlock_deep_sleep();
- *         _callback();
- *     }
- * }
- *
- * int driver::measure(event_t event, callback_t& callback)
- * {
- *      _callback = callback;
- *      sleep_manager_lock_deep_sleep();
- *      // start async transaction, we are waiting for an event
- *      return _sensor.start(event, callback);
- * }
- * @endcode
- */
-
-/** Lock the deep sleep mode
- *
- * This locks the automatic deep mode selection.
- * sleep_manager_sleep_auto() will ignore deepsleep mode if
- * this function is invoked at least once (the internal counter is non-zero)
- *
- * Use this locking mechanism for interrupt driven API that are
- * running in the background and deepsleep could affect their functionality
- *
- * The lock is a counter, can be locked up to USHRT_MAX
- * This function is IRQ and thread safe
- */
-void sleep_manager_lock_deep_sleep(void);
-
-/** Unlock the deep sleep mode
- *
- * Use unlocking in pair with sleep_manager_lock_deep_sleep().
- *
- * The lock is a counter, should be equally unlocked as locked
- * This function is IRQ and thread safe
- */
-void sleep_manager_unlock_deep_sleep(void);
-
-/** Get the status of deep sleep allowance for a target
- *
- * @return true if a target can go to deepsleep, false otherwise
- */
-bool sleep_manager_can_deep_sleep(void);
+#ifndef MBED_MBED_SLEEP_H
+#define MBED_MBED_SLEEP_H
 
-/** Enter auto selected sleep mode. It chooses the sleep or deeepsleep modes based
- *  on the deepsleep locking counter
- *
- * This function is IRQ and thread safe
- *
- * @note
- * If MBED_DEBUG is defined, only hal_sleep is allowed. This ensures the debugger
- * to be active for debug modes.
- *
- */
-void sleep_manager_sleep_auto(void);
-
-/** Send the microcontroller to sleep
- *
- * @note This function can be a noop if not implemented by the platform.
- * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined).
- * @note This function will be a noop while uVisor is in use.
- * @note This function will be a noop if the following conditions are met:
- *   - The RTOS is present
- *   - The processor turn off the Systick clock during sleep
- *   - The target does not implement tickless mode
- *
- * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
- * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
- * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
- * memory state are maintained, and the peripherals continue to work and can generate interrupts.
- *
- * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
- *
- * @note
- *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-static inline void sleep(void)
-{
-#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
-#if DEVICE_SLEEP
-#if (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS)
-    sleep_manager_sleep_auto();
-#endif /* (MBED_CONF_RTOS_PRESENT == 0) || (DEVICE_STCLK_OFF_DURING_SLEEP == 0) || defined(MBED_TICKLESS) */
-#endif /* DEVICE_SLEEP */
-#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
-}
-
-/** Send the microcontroller to deep sleep
- *
- * @note This function can be a noop if not implemented by the platform.
- * @note This function will be a noop in debug mode (debug build profile when MBED_DEBUG is defined)
- * @note This function will be a noop while uVisor is in use.
- *
- * This processor is setup ready for deep sleep, and sent to sleep. This mode
- * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
- * is still maintained.
- *
- * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
- *
- * @note
- *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-
-MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()")
-static inline void deepsleep(void)
-{
-#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
-#if DEVICE_SLEEP
-    sleep_manager_sleep_auto();
-#endif /* DEVICE_SLEEP */
-#endif /* !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED)) */
-}
-
-#ifdef __cplusplus
-}
-#endif
+#warning mbed_sleep.h has been replaced by mbed_power_mgmt.h, please update to mbed_power_mgmt.h [since mbed-os-5.8]
+#include "platform/mbed_power_mgmt.h"
 
 #endif
-
-/** @}*/
-/** @}*/

--- a/platform/mbed_toolchain.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_toolchain.h	Thu Apr 19 17:12:19 2018 +0100
@@ -376,13 +376,27 @@
 #endif
 #endif
 
+// Macro containing the filename part of the value of __FILE__. Defined as
+// string literal.
+#ifndef MBED_FILENAME
+#if defined(__CC_ARM)
+#define MBED_FILENAME __MODULE__
+#elif defined(__GNUC__)
+#define MBED_FILENAME (__builtin_strrchr(__FILE__, '/') ? __builtin_strrchr(__FILE__, '/') + 1 : __builtin_strrchr(__FILE__, '\\') ? __builtin_strrchr(__FILE__, '\\') + 1 : __FILE__)
+#elif defined(__ICCARM__)
+#define MBED_FILENAME (strrchr(__FILE__, '/') ? strrchr(__FILE__, '/') + 1 : strrchr(__FILE__, '\\') ? strrchr(__FILE__, '\\') + 1 : __FILE__)
+#else
+#define MBED_FILENAME __FILE__
+#endif
+#endif // #ifndef MBED_FILENAME
+
 // FILEHANDLE declaration
 #if defined(TOOLCHAIN_ARM)
 #include <rt_sys.h>
 #endif
 
 #ifndef FILEHANDLE
-typedef int FILEHANDLE;
+    typedef int FILEHANDLE;
 #endif
 
 // Backwards compatibility

--- a/platform/mbed_wait_api_rtos.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/mbed_wait_api_rtos.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -22,7 +22,7 @@
 #include "hal/us_ticker_api.h"
 #include "rtos/rtos.h"
 #include "platform/mbed_critical.h"
-#include "platform/mbed_sleep.h"
+#include "platform/mbed_power_mgmt.h"
 
 void wait(float s) {
     wait_us(s * 1000000.0f);

--- a/platform/sleep.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/platform/sleep.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,7 +18,7 @@
 #ifndef MBED_OLD_SLEEP_H
 #define MBED_OLD_SLEEP_H
 
-#warning sleep.h has been replaced by mbed_sleep.h, please update to mbed_sleep.h [since mbed-os-5.3]
-#include "platform/mbed_sleep.h"
+#warning sleep.h has been replaced by mbed_power_mgmt.h, please update to mbed_power_mgmt.h [since mbed-os-5.8]
+#include "platform/mbed_power_mgmt.h"
 
 #endif

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PeripheralNames.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PeripheralNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
+ * Copyright (c) 2006-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -23,11 +23,11 @@
 #endif
 
 typedef enum {
-    UART_0 = (int)CMSDK_UART0_BASE, /* MCC UART */
-    UART_1 = (int)CMSDK_UART1_BASE, /* MPS2+ UART */
-    UART_2 = (int)CMSDK_UART2_BASE, /* Shield 0 UART */
-    UART_3 = (int)CMSDK_UART3_BASE, /* Shield 1 UART */
-    UART_4 = (int)CMSDK_UART4_BASE  /* Shield BT UART */
+    UART_0 = 0, /* MCC UART */
+    UART_1,     /* MPS2+ UART */
+    UART_2,     /* Shield 0 UART */
+    UART_3,     /* Shield 1 UART */
+    UART_4      /* Shield BT UART */
 } UARTName;
 
 typedef enum {
@@ -53,11 +53,12 @@
 } ADCName;
 
 typedef enum {
-    SPI_0 = (int)MPS2_SSP0_BASE,
-    SPI_1 = (int)MPS2_SSP1_BASE,
-    SPI_2 = (int)MPS2_SSP2_BASE,
-    SPI_3 = (int)MPS2_SSP3_BASE,
-    SPI_4 = (int)MPS2_SSP4_BASE
+    SPI_0 = 0,
+    SPI_1,
+    SPI_2,
+    SPI_3,
+    SPI_4,
+    SPI_NC = (SPI_4 + 1)
 } SPIName;
 
 typedef enum {

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PinNames.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PinNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
+ * Copyright (c) 2006-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2017 ARM Limited
+ * Copyright (c) 2017-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -426,6 +426,53 @@
     return 0;
 }
 
+/**
+ * \brief Fill the SMSC9220 TX FIFO with a number of words at an aligned
+ *        address.
+ *
+ * \param[in] data Pointer to the aligned data that should be sent.
+ * \param[in] dwords_to_write Number of data words to write.
+ */
+static void fill_tx_fifo_aligned(unsigned int *data,
+                                 unsigned int dwords_to_write)
+{
+    while (dwords_to_write > 0) {
+        SMSC9220->TX_DATA_PORT = *data;
+        data++;
+        dwords_to_write--;
+    }
+}
+
+/**
+ * \brief Fill the SMSC9220 TX FIFO with a number of words at an unaligned
+ *        address. This function ensures that loading words at that address will
+ *        not generate unaligned access which can trigger an exception to the
+ *        processor.
+ *
+ * \param[in] data Pointer to the unaligned data that should be sent.
+ * \param[in] dwords_to_write Number of data words to write.
+ */
+static void fill_tx_fifo_unaligned(uint8_t *data, unsigned int dwords_to_write)
+{
+    /*
+     * Prevent unaligned word access from data pointer, 4 bytes are copied to
+     * this variable for each word that need to be sent.
+     */
+    unsigned int tx_data_port_tmp = 0;
+    uint8_t *tx_data_port_tmp_ptr = (uint8_t *)&tx_data_port_tmp;
+
+    while (dwords_to_write > 0) {
+        /* Keep the same endianness in data than in the temp variable */
+        tx_data_port_tmp_ptr[0] = data[0];
+        tx_data_port_tmp_ptr[1] = data[1];
+        tx_data_port_tmp_ptr[2] = data[2];
+        tx_data_port_tmp_ptr[3] = data[3];
+        SMSC9220->TX_DATA_PORT = tx_data_port_tmp;
+        data += 4;
+        dwords_to_write--;
+    }
+}
+
 /*----------------------------------------------------------------------------
   Public API
  *----------------------------------------------------------------------------*/
@@ -574,7 +621,6 @@
     int is_last_segment = 0; /* signing this is the last segment of the packet to be sent */
     unsigned int txcmd_a, txcmd_b = 0;
     unsigned int dwords_to_write = 0;
-    unsigned int *pktptr = 0;
     unsigned int xmit_inf = 0;
     unsigned int tx_buffer_free_space = 0;
     volatile unsigned int xmit_stat = 0;
@@ -602,7 +648,6 @@
         is_last_segment = 1;
     }
 
-    pktptr = (unsigned int *) data;
     txcmd_a = 0;
     txcmd_b = 0;
 
@@ -616,11 +661,16 @@
     SMSC9220->TX_DATA_PORT = txcmd_b;
     dwords_to_write = (current_size + 3) >> 2;
 
-    /* PIO Copy to FIFO. Could replace this with DMA. */
-    while(dwords_to_write > 0) {
-        SMSC9220->TX_DATA_PORT = *pktptr;
-        pktptr++;
-        dwords_to_write--;
+    /*
+     * Copy to TX FIFO
+     * The function to use depends on the alignment of the data pointer on a 32
+     * bits boundary.
+     */
+    if (((unsigned int)data % sizeof(uint32_t)) == 0) {
+        /* Cast is safe because we know data is aligned */
+        fill_tx_fifo_aligned((unsigned int *)data, dwords_to_write);
+    } else {
+        fill_tx_fifo_unaligned((uint8_t *)data, dwords_to_write);
     }
 
     if (is_last_segment) {

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/cmsdk_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file cmsdk_ticker.c
+ * Two abstracted functionalities for CMSDK APB Timers
+ *   1. Measure elapsed time
+ *   2. Timer interval interrupt
+ *
+ *   Passed \ref tick_drv_data_t should be initialized by the caller
+ *   for using these services accordingly.
+ *   See details \ref tick_cfg_t and \ref tick_data_t.
+ */
+
+#include "cmsdk_ticker.h"
+
+void cmsdk_ticker_init(const struct tick_drv_data_t* timer_data)
+{
+    if (!timer_data->data->is_initialized) {
+        timer_cmsdk_init(timer_data->cfg->timer_driver);
+        timer_cmsdk_set_reload_value(timer_data->cfg->timer_driver,
+                                     TIMER_CMSDK_MAX_RELOAD);
+        timer_cmsdk_enable_interrupt(timer_data->cfg->timer_driver);
+        NVIC_EnableIRQ(timer_data->cfg->irq_n);
+
+        timer_data->data->max_interval_time =
+                timer_data->cfg->convert_tick_to_time(TIMER_CMSDK_MAX_RELOAD);
+        timer_data->data->reload_time = timer_data->data->max_interval_time;
+        timer_data->data->is_initialized = true;
+        timer_cmsdk_enable(timer_data->cfg->timer_driver);
+    }
+}
+
+uint32_t cmsdk_ticker_read(const struct tick_drv_data_t* timer_data)
+{
+    uint32_t current_elapsed = 0;
+
+    if (!timer_data->data->is_initialized) {
+        cmsdk_ticker_init(timer_data);
+    }
+    current_elapsed = timer_cmsdk_get_elapsed_value(timer_data->cfg->timer_driver);
+    /*
+     * If for the same reload cycle (ie. cumulated_time is the same) the
+     * current elapsed time is lower than the previous one, it means that the
+     * timer has wrapped around without the system logging it. To ensure that
+     * we are always returning an increasing time in those condition, we return
+     * the time perviously read.
+     */
+    if ((timer_data->data->previous_cumulated_time ==
+         timer_data->data->cumulated_time) &&
+        (current_elapsed < timer_data->data->previous_elapsed)) {
+        current_elapsed = timer_data->data->previous_elapsed;
+    }
+
+    timer_data->data->previous_elapsed = current_elapsed;
+    timer_data->data->previous_cumulated_time =
+                                               timer_data->data->cumulated_time;
+
+    return (timer_data->data->cumulated_time +
+            timer_data->cfg->convert_tick_to_time(current_elapsed));
+}
+
+void cmsdk_ticker_set_interrupt(const struct tick_drv_data_t* timer_data,
+                                uint32_t timestamp)
+{
+    uint32_t interval = 0;
+    uint32_t interval_reload_tick = 0;
+
+    /* Stop before read to avoid race condition with IRQ. */
+    timer_cmsdk_disable(timer_data->cfg->timer_driver);
+    uint32_t current_time = cmsdk_ticker_read(timer_data);
+
+    timer_data->data->interval_callback_enabled = true;
+
+    /*
+     * We always assume that the event is in the future, even if this
+     * substraction underflows it is still corect.
+     */
+    interval = (timestamp - current_time);
+
+    if (interval >= timer_data->data->max_interval_time) {
+        /* Event will be in the future but the time is too big: set max */
+        interval_reload_tick = TIMER_CMSDK_MAX_RELOAD;
+        timer_data->data->reload_time = timer_data->data->max_interval_time;
+    } else {
+        /* Event will be in the future in a time that can be set */
+        interval_reload_tick =
+        timer_data->cfg->convert_time_to_tick(interval);
+        timer_data->data->reload_time = interval;
+    }
+
+    /* Store the current elapsed time, before reset the timer */
+    timer_data->data->cumulated_time = current_time;
+    /* Reset the timer with new reload value */
+    timer_cmsdk_set_reload_value(timer_data->cfg->timer_driver,
+                                 interval_reload_tick);
+    timer_cmsdk_reset(timer_data->cfg->timer_driver);
+
+    timer_cmsdk_enable(timer_data->cfg->timer_driver);
+}
+
+void cmsdk_ticker_disable_interrupt(const struct tick_drv_data_t* timer_data)
+{
+    if (!timer_data->data->is_initialized) {
+        cmsdk_ticker_init(timer_data);
+    }
+
+    timer_data->data->interval_callback_enabled = false;
+
+    /* Stop before read to avoid race condition with IRQ. */
+    timer_cmsdk_disable(timer_data->cfg->timer_driver);
+    /* If interval interrupt is disabled, restore the default max interval,
+     * but save the current elapsed time before changing the timer. */
+    timer_data->data->cumulated_time = cmsdk_ticker_read(timer_data);
+    /* Reset the timer with default reload value */
+    timer_cmsdk_set_reload_value(timer_data->cfg->timer_driver,
+                                 TIMER_CMSDK_MAX_RELOAD);
+    timer_data->data->reload_time = timer_data->data->max_interval_time;
+
+    timer_cmsdk_reset(timer_data->cfg->timer_driver);
+    timer_cmsdk_enable(timer_data->cfg->timer_driver);
+}
+
+void cmsdk_ticker_clear_interrupt(const struct tick_drv_data_t* timer_data)
+{
+    timer_cmsdk_clear_interrupt(timer_data->cfg->timer_driver);
+}
+
+void cmsdk_ticker_fire_interrupt(const struct tick_drv_data_t* timer_data)
+{
+    NVIC_SetPendingIRQ(timer_data->cfg->irq_n);
+}
+
+void cmsdk_ticker_irq_handler(const struct tick_drv_data_t* timer_data)
+{
+    uint32_t reload_val = 0;
+    /* If timer's internal interrupt status is not active, then not overflow,
+     * but explicit interrupt request was fired by cmsdk_ticker_fire_interrupt.
+     */
+    if (timer_cmsdk_is_interrupt_active(timer_data->cfg->timer_driver)) {
+    /* 1. Calculate cumulated time by overflow */
+        timer_cmsdk_clear_interrupt(timer_data->cfg->timer_driver);
+        reload_val = timer_cmsdk_get_reload_value(timer_data->cfg->timer_driver);
+        timer_data->data->cumulated_time +=
+                timer_data->cfg->convert_tick_to_time(reload_val);
+    }
+
+    /* 2. Call mbed interval interrupt handler if it's required */
+    if (timer_data->data->interval_callback_enabled) {
+        cmsdk_ticker_disable_interrupt(timer_data);
+        timer_data->cfg->interval_callback();
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/cmsdk_ticker.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+/**
+ * \file cmsdk_ticker.h
+ * CMSDK Ticker implements the functionalities of mbed tickers:
+ * 1. Elapsed time measurement
+ * 2. Interval interrupt request
+ *
+ * This ticker service is based on CMSDK APB Timers, abstracting
+ * the HAL logic, the timer driver and interrupt number.
+ * These parameters should be passed to the functions by
+ * an initialized \ref tick_drv_data_t pointer.
+ */
+
+#ifndef CMSDK_TICKER_H
+#define CMSDK_TICKER_H
+
+#include <stdbool.h>
+
+#include "CMSDK_CM3DS.h"
+#include "timer_cmsdk_drv.h"
+
+#define SEC_TO_USEC_MULTIPLIER    1000000U
+
+/**
+ * brief Encapsulating struct for config data \ref tick_cfg_t and
+ *       the current status \ref tick_data_t.
+ */
+struct tick_drv_data_t {
+    const struct tick_cfg_t* const cfg;
+    struct tick_data_t* const data;
+};
+
+/**
+ * brief Configuration data of the CMSDK ticker
+ */
+struct tick_cfg_t {
+    /** Pointer to the used CMSDK Timer's device structure */
+    struct timer_cmsdk_dev_t* const timer_driver;
+    /** IRQ number of the used CMSDK Timer */
+    const IRQn_Type irq_n;
+    /** Interval callback of mbed*/
+    void (*const interval_callback)();
+    /** Function pointers to call for conversions of clock ticks and defined
+     *  time unit.
+     *  These conversions define the unit of the measured time.
+     */
+    uint32_t (*const convert_tick_to_time)(uint32_t tick);
+    uint32_t (*const convert_time_to_tick)(uint32_t time);
+};
+
+/**
+ * brief Current state data of the CMSDK ticker
+ */
+struct tick_data_t {
+    /** True if initialized the ticker, false otherwise */
+    bool is_initialized;
+    /** Measured elapsed time in the defined unit by
+     *  \ref convert_tick_to_time and \ref convert_time_to_tick */
+    uint32_t cumulated_time;
+    /** Max interval time possible to set, in the defined unit by
+     *  \ref convert_tick_to_time and \ref convert_time_to_tick */
+    uint32_t max_interval_time;
+    /** Current reload time in the defined unit by
+     *  \ref convert_tick_to_time and \ref convert_time_to_tick */
+    uint32_t reload_time;
+    /** Interval IRQ callback is requested */
+    bool interval_callback_enabled;
+    /** Previous cumulated time calculated for this ticker. Used in the
+     *  cmsdk_ticker_read function to detect that the timer has wrapped. */
+    uint32_t previous_cumulated_time;
+    /** Previous elapsed value for this ticker. Used in the
+     *  cmsdk_ticker_read function to detect that the timer has wrapped. */
+    uint32_t previous_elapsed;
+};
+
+/**
+ * \brief Init the CMSDK Ticker
+ *
+ * \param[in] timer_data Pointer to the used CMSDK Timer's device structure
+ */
+void cmsdk_ticker_init(const struct tick_drv_data_t* timer_data);
+
+/**
+ * \brief Read elapsed time by CMSDK Ticker
+ *
+ * \param[in] timer_data Pointer to the used CMSDK Timer's device structure
+ *
+ * \return Elapsed time in the unit defined by \ref convert_tick_to_time
+ */
+
+uint32_t cmsdk_ticker_read(const struct tick_drv_data_t* timer_data);
+
+/**
+ * \brief Request interval interrupt by time stamp \ref timestamp_t
+ *
+ * \param[in] timer_data Pointer to the used CMSDK Timer's device structure
+ * \param[in] timestamp Absolute time \ref timestamp_t value when the interval
+ *                     is requested. Unit of the timestamp is defined by
+ *                     \ref convert_tick_to_time and \ref convert_time_to_tick
+ */
+void cmsdk_ticker_set_interrupt(const struct tick_drv_data_t* timer_data,
+                                uint32_t timestamp);
+
+/**
+ * \brief Disable interval interrupt
+ *
+ * \param[in] timer_data Pointer to the used CMSDK Timer's device structure
+ */
+void cmsdk_ticker_disable_interrupt(const struct tick_drv_data_t* timer_data);
+
+/**
+ * \brief Clear interval interrupt
+ *
+ * \param[in] timer_data Pointer to the used CMSDK Timer's device structure
+ */
+void cmsdk_ticker_clear_interrupt(const struct tick_drv_data_t* timer_data);
+
+/**
+ * \brief Set pending interrupt that should be fired right away.
+ *
+ * \param[in] timer_data Pointer to the used CMSDK Timer's device structure
+ */
+void cmsdk_ticker_fire_interrupt(const struct tick_drv_data_t* timer_data);
+
+/**
+ * \brief Interrupt handler of the given CMSDK Timer
+ *
+ * \warning This function may be called from multiple interrupt handlers,
+ *          so extra care must be taken for re-entrancy!
+ *
+ * \param[in] timer_data Pointer to the used CMSDK Timer's device structure
+ */
+void cmsdk_ticker_irq_handler(const struct tick_drv_data_t* timer_data);
+#endif

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/CMSDK_CM3DS.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/CMSDK_CM3DS.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -135,420 +135,6 @@
   #warning Not supported compiler type
 #endif
 
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-typedef struct
-{
-  __IO   uint32_t  DATA;                     /* Offset: 0x000 (R/W) Data Register    */
-  __IO   uint32_t  STATE;                    /* Offset: 0x004 (R/W) Status Register  */
-  __IO   uint32_t  CTRL;                     /* Offset: 0x008 (R/W) Control Register */
-  union {
-    __I    uint32_t  INTSTATUS;              /* Offset: 0x00C (R/ ) Interrupt Status Register */
-    __O    uint32_t  INTCLEAR;               /* Offset: 0x00C ( /W) Interrupt Clear Register  */
-    };
-  __IO   uint32_t  BAUDDIV;                  /* Offset: 0x010 (R/W) Baudrate Divider Register */
-
-} CMSDK_UART_TypeDef;
-
-/* CMSDK_UART DATA Register Definitions */
-
-#define CMSDK_UART_DATA_Pos               0                                             /* CMSDK_UART_DATA_Pos: DATA Position */
-#define CMSDK_UART_DATA_Msk              (0xFFul << CMSDK_UART_DATA_Pos)                /* CMSDK_UART DATA: DATA Mask */
-
-#define CMSDK_UART_STATE_RXOR_Pos         3                                             /* CMSDK_UART STATE: RXOR Position */
-#define CMSDK_UART_STATE_RXOR_Msk         (0x1ul << CMSDK_UART_STATE_RXOR_Pos)          /* CMSDK_UART STATE: RXOR Mask */
-
-#define CMSDK_UART_STATE_TXOR_Pos         2                                             /* CMSDK_UART STATE: TXOR Position */
-#define CMSDK_UART_STATE_TXOR_Msk         (0x1ul << CMSDK_UART_STATE_TXOR_Pos)          /* CMSDK_UART STATE: TXOR Mask */
-
-#define CMSDK_UART_STATE_RXBF_Pos         1                                             /* CMSDK_UART STATE: RXBF Position */
-#define CMSDK_UART_STATE_RXBF_Msk         (0x1ul << CMSDK_UART_STATE_RXBF_Pos)          /* CMSDK_UART STATE: RXBF Mask */
-
-#define CMSDK_UART_STATE_TXBF_Pos         0                                             /* CMSDK_UART STATE: TXBF Position */
-#define CMSDK_UART_STATE_TXBF_Msk         (0x1ul << CMSDK_UART_STATE_TXBF_Pos )         /* CMSDK_UART STATE: TXBF Mask */
-
-#define CMSDK_UART_CTRL_HSTM_Pos          6                                             /* CMSDK_UART CTRL: HSTM Position */
-#define CMSDK_UART_CTRL_HSTM_Msk          (0x01ul << CMSDK_UART_CTRL_HSTM_Pos)          /* CMSDK_UART CTRL: HSTM Mask */
-
-#define CMSDK_UART_CTRL_RXORIRQEN_Pos     5                                             /* CMSDK_UART CTRL: RXORIRQEN Position */
-#define CMSDK_UART_CTRL_RXORIRQEN_Msk     (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos)     /* CMSDK_UART CTRL: RXORIRQEN Mask */
-
-#define CMSDK_UART_CTRL_TXORIRQEN_Pos     4                                             /* CMSDK_UART CTRL: TXORIRQEN Position */
-#define CMSDK_UART_CTRL_TXORIRQEN_Msk     (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos)     /* CMSDK_UART CTRL: TXORIRQEN Mask */
-
-#define CMSDK_UART_CTRL_RXIRQEN_Pos       3                                             /* CMSDK_UART CTRL: RXIRQEN Position */
-#define CMSDK_UART_CTRL_RXIRQEN_Msk       (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos)       /* CMSDK_UART CTRL: RXIRQEN Mask */
-
-#define CMSDK_UART_CTRL_TXIRQEN_Pos       2                                             /* CMSDK_UART CTRL: TXIRQEN Position */
-#define CMSDK_UART_CTRL_TXIRQEN_Msk       (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos)       /* CMSDK_UART CTRL: TXIRQEN Mask */
-
-#define CMSDK_UART_CTRL_RXEN_Pos          1                                             /* CMSDK_UART CTRL: RXEN Position */
-#define CMSDK_UART_CTRL_RXEN_Msk          (0x01ul << CMSDK_UART_CTRL_RXEN_Pos)          /* CMSDK_UART CTRL: RXEN Mask */
-
-#define CMSDK_UART_CTRL_TXEN_Pos          0                                             /* CMSDK_UART CTRL: TXEN Position */
-#define CMSDK_UART_CTRL_TXEN_Msk          (0x01ul << CMSDK_UART_CTRL_TXEN_Pos)          /* CMSDK_UART CTRL: TXEN Mask */
-
-#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos  3                                             /* CMSDK_UART CTRL: RXORIRQ Position */
-#define CMSDK_UART_INTSTATUS_RXORIRQ_Msk  (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos)  /* CMSDK_UART CTRL: RXORIRQ Mask */
-
-#define CMSDK_UART_INTSTATUS_TXORIRQ_Pos   2                                             /* CMSDK_UART CTRL: TXORIRQ Position */
-#define CMSDK_UART_INTSTATUS_TXORIRQ_Msk   (0x01ul << CMSDK_UART_INTSTATUS_TXORIRQ_Pos)  /* CMSDK_UART CTRL: TXORIRQ Mask */
-
-#define CMSDK_UART_INTSTATUS_RXIRQ_Pos     1                                             /* CMSDK_UART CTRL: RXIRQ Position */
-#define CMSDK_UART_INTSTATUS_RXIRQ_Msk     (0x01ul << CMSDK_UART_INTSTATUS_RXIRQ_Pos)    /* CMSDK_UART CTRL: RXIRQ Mask */
-
-#define CMSDK_UART_INTSTATUS_TXIRQ_Pos     0                                             /* CMSDK_UART CTRL: TXIRQ Position */
-#define CMSDK_UART_INTSTATUS_TXIRQ_Msk     (0x01ul << CMSDK_UART_INTSTATUS_TXIRQ_Pos)    /* CMSDK_UART CTRL: TXIRQ Mask */
-
-#define CMSDK_UART_BAUDDIV_Pos            0                                             /* CMSDK_UART BAUDDIV: BAUDDIV Position */
-#define CMSDK_UART_BAUDDIV_Msk           (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos)          /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
-
-
-/*----------------------------- Timer (TIMER) -------------------------------*/
-typedef struct
-{
-  __IO   uint32_t  CTRL;                     /* Offset: 0x000 (R/W) Control Register */
-  __IO   uint32_t  VALUE;                    /* Offset: 0x004 (R/W) Current Value Register */
-  __IO   uint32_t  RELOAD;                   /* Offset: 0x008 (R/W) Reload Value Register */
-  union {
-    __I    uint32_t  INTSTATUS;              /* Offset: 0x00C (R/ ) Interrupt Status Register */
-    __O    uint32_t  INTCLEAR;               /* Offset: 0x00C ( /W) Interrupt Clear Register */
-    };
-
-} CMSDK_TIMER_TypeDef;
-
-/* CMSDK_TIMER CTRL Register Definitions */
-
-#define CMSDK_TIMER_CTRL_IRQEN_Pos          3                                              /* CMSDK_TIMER CTRL: IRQEN Position */
-#define CMSDK_TIMER_CTRL_IRQEN_Msk          (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos)         /* CMSDK_TIMER CTRL: IRQEN Mask */
-
-#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos      2                                              /* CMSDK_TIMER CTRL: SELEXTCLK Position */
-#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk      (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos)     /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
-
-#define CMSDK_TIMER_CTRL_SELEXTEN_Pos       1                                              /* CMSDK_TIMER CTRL: SELEXTEN Position */
-#define CMSDK_TIMER_CTRL_SELEXTEN_Msk       (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos)      /* CMSDK_TIMER CTRL: SELEXTEN Mask */
-
-#define CMSDK_TIMER_CTRL_EN_Pos             0                                              /* CMSDK_TIMER CTRL: EN Position */
-#define CMSDK_TIMER_CTRL_EN_Msk             (0x01ul << CMSDK_TIMER_CTRL_EN_Pos)            /* CMSDK_TIMER CTRL: EN Mask */
-
-#define CMSDK_TIMER_VAL_CURRENT_Pos         0                                              /* CMSDK_TIMER VALUE: CURRENT Position */
-#define CMSDK_TIMER_VAL_CURRENT_Msk         (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos)  /* CMSDK_TIMER VALUE: CURRENT Mask */
-
-#define CMSDK_TIMER_RELOAD_VAL_Pos          0                                              /* CMSDK_TIMER RELOAD: RELOAD Position */
-#define CMSDK_TIMER_RELOAD_VAL_Msk          (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos)   /* CMSDK_TIMER RELOAD: RELOAD Mask */
-
-#define CMSDK_TIMER_INTSTATUS_Pos           0                                              /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
-#define CMSDK_TIMER_INTSTATUS_Msk           (0x01ul << CMSDK_TIMER_INTSTATUS_Pos)          /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
-
-#define CMSDK_TIMER_INTCLEAR_Pos            0                                              /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
-#define CMSDK_TIMER_INTCLEAR_Msk            (0x01ul << CMSDK_TIMER_INTCLEAR_Pos)           /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
-
-
-/*------------- Timer (TIM) --------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t Timer1Load;                  /* Offset: 0x000 (R/W) Timer 1 Load */
-  __I  uint32_t Timer1Value;                 /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
-  __IO uint32_t Timer1Control;               /* Offset: 0x008 (R/W) Timer 1 Control */
-  __O  uint32_t Timer1IntClr;                /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
-  __I  uint32_t Timer1RIS;                   /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
-  __I  uint32_t Timer1MIS;                   /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
-  __IO uint32_t Timer1BGLoad;                /* Offset: 0x018 (R/W) Background Load Register */
-       uint32_t RESERVED0;
-  __IO uint32_t Timer2Load;                  /* Offset: 0x020 (R/W) Timer 2 Load */
-  __I  uint32_t Timer2Value;                 /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
-  __IO uint32_t Timer2Control;               /* Offset: 0x028 (R/W) Timer 2 Control */
-  __O  uint32_t Timer2IntClr;                /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
-  __I  uint32_t Timer2RIS;                   /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
-  __I  uint32_t Timer2MIS;                   /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
-  __IO uint32_t Timer2BGLoad;                /* Offset: 0x038 (R/W) Background Load Register */
-       uint32_t RESERVED1[945];
-  __IO uint32_t ITCR;                        /* Offset: 0xF00 (R/W) Integration Test Control Register */
-  __O  uint32_t ITOP;                        /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
-} CMSDK_DUALTIMER_BOTH_TypeDef;
-
-#define CMSDK_DUALTIMER1_LOAD_Pos            0                                                /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
-#define CMSDK_DUALTIMER1_LOAD_Msk            (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos)      /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
-
-#define CMSDK_DUALTIMER1_VALUE_Pos           0                                                /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
-#define CMSDK_DUALTIMER1_VALUE_Msk           (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos)     /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
-
-#define CMSDK_DUALTIMER1_CTRL_EN_Pos         7                                                /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
-#define CMSDK_DUALTIMER1_CTRL_EN_Msk         (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos)          /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
-
-#define CMSDK_DUALTIMER1_CTRL_MODE_Pos       6                                                /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
-#define CMSDK_DUALTIMER1_CTRL_MODE_Msk       (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos)        /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
-
-#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos      5                                                /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
-#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk      (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos)       /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
-
-#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos   2                                                /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
-#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk   (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos)    /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
-
-#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos       1                                                /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
-#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk       (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos)        /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
-
-#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos   0                                                /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
-#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk   (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos)    /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
-
-#define CMSDK_DUALTIMER1_INTCLR_Pos          0                                                /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
-#define CMSDK_DUALTIMER1_INTCLR_Msk          (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos)           /* CMSDK_DUALTIMER1 INTCLR: INT Clear  Mask */
-
-#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos      0                                                /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
-#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk      (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos)       /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
-
-#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos     0                                                /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
-#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk     (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos)      /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
-
-#define CMSDK_DUALTIMER1_BGLOAD_Pos          0                                                /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
-#define CMSDK_DUALTIMER1_BGLOAD_Msk          (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos)    /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
-
-#define CMSDK_DUALTIMER2_LOAD_Pos            0                                                /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
-#define CMSDK_DUALTIMER2_LOAD_Msk            (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos)      /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
-
-#define CMSDK_DUALTIMER2_VALUE_Pos           0                                                /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
-#define CMSDK_DUALTIMER2_VALUE_Msk           (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos)     /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
-
-#define CMSDK_DUALTIMER2_CTRL_EN_Pos         7                                                /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
-#define CMSDK_DUALTIMER2_CTRL_EN_Msk         (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos)          /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
-
-#define CMSDK_DUALTIMER2_CTRL_MODE_Pos       6                                                /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
-#define CMSDK_DUALTIMER2_CTRL_MODE_Msk       (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos)        /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
-
-#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos      5                                                /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
-#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk      (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos)       /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
-
-#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos   2                                                /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
-#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk   (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos)    /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
-
-#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos       1                                                /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
-#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk       (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos)        /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
-
-#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos   0                                                /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
-#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk   (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos)    /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
-
-#define CMSDK_DUALTIMER2_INTCLR_Pos          0                                                /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
-#define CMSDK_DUALTIMER2_INTCLR_Msk          (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos)           /* CMSDK_DUALTIMER2 INTCLR: INT Clear  Mask */
-
-#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos      0                                                /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
-#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk      (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos)       /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
-
-#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos     0                                                /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
-#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk     (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos)      /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
-
-#define CMSDK_DUALTIMER2_BGLOAD_Pos          0                                                /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
-#define CMSDK_DUALTIMER2_BGLOAD_Msk          (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos)    /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
-
-
-typedef struct
-{
-  __IO uint32_t TimerLoad;                   /* Offset: 0x000 (R/W) Timer Load */
-  __I  uint32_t TimerValue;                  /* Offset: 0x000 (R/W) Timer Counter Current Value */
-  __IO uint32_t TimerControl;                /* Offset: 0x000 (R/W) Timer Control */
-  __O  uint32_t TimerIntClr;                 /* Offset: 0x000 (R/W) Timer Interrupt Clear */
-  __I  uint32_t TimerRIS;                    /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
-  __I  uint32_t TimerMIS;                    /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
-  __IO uint32_t TimerBGLoad;                 /* Offset: 0x000 (R/W) Background Load Register */
-} CMSDK_DUALTIMER_SINGLE_TypeDef;
-
-#define CMSDK_DUALTIMER_LOAD_Pos             0                                               /* CMSDK_DUALTIMER LOAD: LOAD Position */
-#define CMSDK_DUALTIMER_LOAD_Msk             (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos)      /* CMSDK_DUALTIMER LOAD: LOAD Mask */
-
-#define CMSDK_DUALTIMER_VALUE_Pos            0                                               /* CMSDK_DUALTIMER VALUE: VALUE Position */
-#define CMSDK_DUALTIMER_VALUE_Msk            (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos)     /* CMSDK_DUALTIMER VALUE: VALUE Mask */
-
-#define CMSDK_DUALTIMER_CTRL_EN_Pos          7                                               /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
-#define CMSDK_DUALTIMER_CTRL_EN_Msk          (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos)          /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
-
-#define CMSDK_DUALTIMER_CTRL_MODE_Pos        6                                               /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
-#define CMSDK_DUALTIMER_CTRL_MODE_Msk        (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos)        /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
-
-#define CMSDK_DUALTIMER_CTRL_INTEN_Pos       5                                               /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
-#define CMSDK_DUALTIMER_CTRL_INTEN_Msk       (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos)       /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
-
-#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos    2                                               /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
-#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk    (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos)    /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
-
-#define CMSDK_DUALTIMER_CTRL_SIZE_Pos        1                                               /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
-#define CMSDK_DUALTIMER_CTRL_SIZE_Msk        (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos)        /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
-
-#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos    0                                               /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
-#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk    (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos)    /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
-
-#define CMSDK_DUALTIMER_INTCLR_Pos           0                                               /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
-#define CMSDK_DUALTIMER_INTCLR_Msk           (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos)           /* CMSDK_DUALTIMER INTCLR: INT Clear  Mask */
-
-#define CMSDK_DUALTIMER_RAWINTSTAT_Pos       0                                               /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
-#define CMSDK_DUALTIMER_RAWINTSTAT_Msk       (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos)       /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
-
-#define CMSDK_DUALTIMER_MASKINTSTAT_Pos      0                                               /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
-#define CMSDK_DUALTIMER_MASKINTSTAT_Msk      (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos)      /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
-
-#define CMSDK_DUALTIMER_BGLOAD_Pos           0                                               /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
-#define CMSDK_DUALTIMER_BGLOAD_Msk           (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos)    /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
-
-
-/*-------------------- General Purpose Input Output (GPIO) -------------------*/
-typedef struct
-{
-  __IO   uint32_t  DATA;                     /* Offset: 0x000 (R/W) DATA Register */
-  __IO   uint32_t  DATAOUT;                  /* Offset: 0x004 (R/W) Data Output Latch Register */
-         uint32_t  RESERVED0[2];
-  __IO   uint32_t  OUTENABLESET;             /* Offset: 0x010 (R/W) Output Enable Set Register */
-  __IO   uint32_t  OUTENABLECLR;             /* Offset: 0x014 (R/W) Output Enable Clear Register */
-  __IO   uint32_t  ALTFUNCSET;               /* Offset: 0x018 (R/W) Alternate Function Set Register */
-  __IO   uint32_t  ALTFUNCCLR;               /* Offset: 0x01C (R/W) Alternate Function Clear Register */
-  __IO   uint32_t  INTENSET;                 /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
-  __IO   uint32_t  INTENCLR;                 /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
-  __IO   uint32_t  INTTYPESET;               /* Offset: 0x028 (R/W) Interrupt Type Set Register */
-  __IO   uint32_t  INTTYPECLR;               /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
-  __IO   uint32_t  INTPOLSET;                /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
-  __IO   uint32_t  INTPOLCLR;                /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
-  union {
-    __I    uint32_t  INTSTATUS;              /* Offset: 0x038 (R/ ) Interrupt Status Register */
-    __O    uint32_t  INTCLEAR;               /* Offset: 0x038 ( /W) Interrupt Clear Register */
-    };
-         uint32_t RESERVED1[241];
-  __IO   uint32_t LB_MASKED[256];            /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
-  __IO   uint32_t UB_MASKED[256];            /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
-} CMSDK_GPIO_TypeDef;
-
-#define CMSDK_GPIO_DATA_Pos            0                                          /* CMSDK_GPIO DATA: DATA Position */
-#define CMSDK_GPIO_DATA_Msk            (0xFFFFul << CMSDK_GPIO_DATA_Pos)          /* CMSDK_GPIO DATA: DATA Mask */
-
-#define CMSDK_GPIO_DATAOUT_Pos         0                                          /* CMSDK_GPIO DATAOUT: DATAOUT Position */
-#define CMSDK_GPIO_DATAOUT_Msk         (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos)       /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
-
-#define CMSDK_GPIO_OUTENSET_Pos        0                                          /* CMSDK_GPIO OUTEN: OUTEN Position */
-#define CMSDK_GPIO_OUTENSET_Msk        (0xFFFFul << CMSDK_GPIO_OUTEN_Pos)         /* CMSDK_GPIO OUTEN: OUTEN Mask */
-
-#define CMSDK_GPIO_OUTENCLR_Pos        0                                          /* CMSDK_GPIO OUTEN: OUTEN Position */
-#define CMSDK_GPIO_OUTENCLR_Msk        (0xFFFFul << CMSDK_GPIO_OUTEN_Pos)         /* CMSDK_GPIO OUTEN: OUTEN Mask */
-
-#define CMSDK_GPIO_ALTFUNCSET_Pos      0                                          /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
-#define CMSDK_GPIO_ALTFUNCSET_Msk      (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos)       /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
-
-#define CMSDK_GPIO_ALTFUNCCLR_Pos      0                                          /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
-#define CMSDK_GPIO_ALTFUNCCLR_Msk      (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos)       /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
-
-#define CMSDK_GPIO_INTENSET_Pos        0                                          /* CMSDK_GPIO INTEN: INTEN Position */
-#define CMSDK_GPIO_INTENSET_Msk        (0xFFFFul << CMSDK_GPIO_INTEN_Pos)         /* CMSDK_GPIO INTEN: INTEN Mask */
-
-#define CMSDK_GPIO_INTENCLR_Pos        0                                          /* CMSDK_GPIO INTEN: INTEN Position */
-#define CMSDK_GPIO_INTENCLR_Msk        (0xFFFFul << CMSDK_GPIO_INTEN_Pos)         /* CMSDK_GPIO INTEN: INTEN Mask */
-
-#define CMSDK_GPIO_INTTYPESET_Pos      0                                          /* CMSDK_GPIO INTTYPE: INTTYPE Position */
-#define CMSDK_GPIO_INTTYPESET_Msk      (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos)       /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
-
-#define CMSDK_GPIO_INTTYPECLR_Pos      0                                          /* CMSDK_GPIO INTTYPE: INTTYPE Position */
-#define CMSDK_GPIO_INTTYPECLR_Msk      (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos)       /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
-
-#define CMSDK_GPIO_INTPOLSET_Pos       0                                          /* CMSDK_GPIO INTPOL: INTPOL Position */
-#define CMSDK_GPIO_INTPOLSET_Msk       (0xFFFFul << CMSDK_GPIO_INTPOL_Pos)        /* CMSDK_GPIO INTPOL: INTPOL Mask */
-
-#define CMSDK_GPIO_INTPOLCLR_Pos       0                                          /* CMSDK_GPIO INTPOL: INTPOL Position */
-#define CMSDK_GPIO_INTPOLCLR_Msk       (0xFFFFul << CMSDK_GPIO_INTPOL_Pos)        /* CMSDK_GPIO INTPOL: INTPOL Mask */
-
-#define CMSDK_GPIO_INTSTATUS_Pos       0                                          /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
-#define CMSDK_GPIO_INTSTATUS_Msk       (0xFFul << CMSDK_GPIO_INTSTATUS_Pos)       /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
-
-#define CMSDK_GPIO_INTCLEAR_Pos        0                                          /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
-#define CMSDK_GPIO_INTCLEAR_Msk        (0xFFul << CMSDK_GPIO_INTCLEAR_Pos)        /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
-
-#define CMSDK_GPIO_MASKLOWBYTE_Pos     0                                          /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
-#define CMSDK_GPIO_MASKLOWBYTE_Msk     (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos)   /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
-
-#define CMSDK_GPIO_MASKHIGHBYTE_Pos    0                                          /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
-#define CMSDK_GPIO_MASKHIGHBYTE_Msk    (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos)  /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
-
-/* GPIO Alternate function pin numbers */
-#define CMSDK_GPIO_ALTFUNC_SH0_UART2_RX          0    /* Shield 0 UART 2 Rx */
-#define CMSDK_GPIO_ALTFUNC_SH0_UART2_RX_SET      (CMSDK_GPIO_ALTFUNC_SH0_UART2_RX % 16)
-#define CMSDK_GPIO_SH0_UART2_RX_GPIO_NUM         (CMSDK_GPIO_ALTFUNC_SH0_UART2_RX / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH0_UART2_TX          4    /* Shield 0 UART 2 Tx */
-#define CMSDK_GPIO_ALTFUNC_SH0_UART2_TX_SET      (CMSDK_GPIO_ALTFUNC_SH0_UART2_TX % 16)
-#define CMSDK_GPIO_SH0_UART2_TX_GPIO_NUM         (CMSDK_GPIO_ALTFUNC_SH0_UART2_TX / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH1_UART3_RX          26   /* Shield 1 UART 3 Rx */
-#define CMSDK_GPIO_ALTFUNC_SH1_UART3_RX_SET      (CMSDK_GPIO_ALTFUNC_SH1_UART3_RX % 16)
-#define CMSDK_GPIO_SH1_UART3_RX_GPIO_NUM         (CMSDK_GPIO_ALTFUNC_SH1_UART3_RX / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH1_UART3_TX          30   /* Shield 1 UART 3 Tx */
-#define CMSDK_GPIO_ALTFUNC_SH1_UART3_TX_SET      (CMSDK_GPIO_ALTFUNC_SH1_UART3_TX % 16)
-#define CMSDK_GPIO_SH1_UART3_TX_GPIO_NUM         (CMSDK_GPIO_ALTFUNC_SH1_UART3_TX / 16)
-
-#define CMSDK_GPIO_ALTFUNC_UART4_RX              23   /* UART 4 Rx */
-#define CMSDK_GPIO_ALTFUNC_UART4_RX_SET          (CMSDK_GPIO_ALTFUNC_UART4_RX % 16)
-#define CMSDK_GPIO_UART4_RX_GPIO_NUM             (CMSDK_GPIO_ALTFUNC_UART4_RX / 16)
-
-#define CMSDK_GPIO_ALTFUNC_UART4_TX              24   /* UART 4 Tx */
-#define CMSDK_GPIO_ALTFUNC_UART4_TX_SET          (CMSDK_GPIO_ALTFUNC_UART4_TX % 16)
-#define CMSDK_GPIO_UART4_TX_GPIO_NUM             (CMSDK_GPIO_ALTFUNC_UART4_TX / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C           5    /* Shield 0 SCL I2S */
-#define CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C_SET       (CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C % 16)
-#define CMSDK_GPIO_SH0_SCL_I2C_GPIO_NUM          (CMSDK_GPIO_ALTFUNC_SH0_SCL_I2C / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C           15   /* Shield 0 SDA I2S */
-#define CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C_SET       (CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C % 16)
-#define CMSDK_GPIO_SH0_SDA_I2C_GPIO_NUM          (CMSDK_GPIO_ALTFUNC_SH0_SDA_I2C / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C           31   /* Shield 1 SCL I2S */
-#define CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C_SET       (CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C % 16)
-#define CMSDK_GPIO_SH1_SCL_I2C_GPIO_NUM          (CMSDK_GPIO_ALTFUNC_SH1_SCL_I2C / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C           41   /* Shield 1 SDA I2S */
-#define CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C_SET       (CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C % 16)
-#define CMSDK_GPIO_SH1_SDA_I2C_GPIO_NUM          (CMSDK_GPIO_ALTFUNC_SH1_SDA_I2C / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI           11   /* Shield 0 SCK SPI */
-#define CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI_SET       (CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI % 16)
-#define CMSDK_GPIO_SH0_SCK_SPI_GPIO_NUM          (CMSDK_GPIO_ALTFUNC_SH0_SCK_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH0_CS_SPI            12   /* Shield 0 CS SPI */
-#define CMSDK_GPIO_ALTFUNC_SH0_CS_SPI_SET        (CMSDK_GPIO_ALTFUNC_SH0_CS_SPI % 16)
-#define CMSDK_GPIO_SH0_CS_SPI_GPIO_NUM           (CMSDK_GPIO_ALTFUNC_SH0_CS_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI          13   /* Shield 0 MOSI SPI */
-#define CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI_SET      (CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI % 16)
-#define CMSDK_GPIO_SH0_MOSI_SPI_GPIO_NUM         (CMSDK_GPIO_ALTFUNC_SH0_MOSI_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI          14   /* Shield 0 MISO SPI */
-#define CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI_SET      (CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI % 16)
-#define CMSDK_GPIO_SH0_MISO_SPI_GPIO_NUM         (CMSDK_GPIO_ALTFUNC_SH0_MISO_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI           44   /* Shield 1 SCK SPI */
-#define CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI_SET       (CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI % 16)
-#define CMSDK_GPIO_SH1_SCK_SPI_GPIO_NUM          (CMSDK_GPIO_ALTFUNC_SH1_SCK_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH1_CS_SPI            38   /* Shield 1 CS SPI */
-#define CMSDK_GPIO_ALTFUNC_SH1_CS_SPI_SET        (CMSDK_GPIO_ALTFUNC_SH1_CS_SPI % 16)
-#define CMSDK_GPIO_SH1_CS_SPI_GPIO_NUM           (CMSDK_GPIO_ALTFUNC_SH1_CS_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI          39   /* Shield 1 MOSI SPI */
-#define CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI_SET      (CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI % 16)
-#define CMSDK_GPIO_SH1_MOSI_SPI_GPIO_NUM         (CMSDK_GPIO_ALTFUNC_SH1_MOSI_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI          40   /* Shield 1 MISO SPI */
-#define CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI_SET      (CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI % 16)
-#define CMSDK_GPIO_SH1_MISO_SPI_GPIO_NUM         (CMSDK_GPIO_ALTFUNC_SH1_MISO_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI           19   /* Shield ADC SCK SPI */
-#define CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI_SET       (CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI % 16)
-#define CMSDK_GPIO_ADC_SCK_SPI_GPIO_NUM          (CMSDK_GPIO_ALTFUNC_ADC_SCK_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_ADC_CS_SPI            16   /* Shield ADC CS SPI */
-#define CMSDK_GPIO_ALTFUNC_ADC_CS_SPI_SET        (CMSDK_GPIO_ALTFUNC_ADC_CS_SPI % 16)
-#define CMSDK_GPIO_ADC_CS_SPI_GPIO_NUM           (CMSDK_GPIO_ALTFUNC_ADC_CS_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI          18   /* Shield ADC MOSI SPI */
-#define CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI_SET      (CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI % 16)
-#define CMSDK_GPIO_ADC_MOSI_SPI_GPIO_NUM         (CMSDK_GPIO_ALTFUNC_ADC_MOSI_SPI / 16)
-
-#define CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI          17   /* Shield ADC MISO SPI */
-#define CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI_SET      (CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI % 16)
-#define CMSDK_GPIO_ADC_MISO_SPI_GPIO_NUM         (CMSDK_GPIO_ALTFUNC_ADC_MISO_SPI / 16)
-
 /*------------- System Control (SYSCON) --------------------------------------*/
 typedef struct
 {
@@ -755,28 +341,12 @@
 /* ================             Peripheral declaration             ================ */
 /* ================================================================================ */
 
-#define CMSDK_UART0             ((CMSDK_UART_TypeDef   *) CMSDK_UART0_BASE )
-#define CMSDK_UART1             ((CMSDK_UART_TypeDef   *) CMSDK_UART1_BASE )
-#define CMSDK_UART2             ((CMSDK_UART_TypeDef   *) CMSDK_UART2_BASE )
-#define CMSDK_UART3             ((CMSDK_UART_TypeDef   *) CMSDK_UART3_BASE )
-#define CMSDK_UART4             ((CMSDK_UART_TypeDef   *) CMSDK_UART4_BASE )
-#define CMSDK_TIMER0            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER0_BASE )
-#define CMSDK_TIMER1            ((CMSDK_TIMER_TypeDef  *) CMSDK_TIMER1_BASE )
-#define CMSDK_DUALTIMER         ((CMSDK_DUALTIMER_BOTH_TypeDef  *) CMSDK_DUALTIMER_BASE )
-#define CMSDK_DUALTIMER1        ((CMSDK_DUALTIMER_SINGLE_TypeDef  *) CMSDK_DUALTIMER_1_BASE )
-#define CMSDK_DUALTIMER2        ((CMSDK_DUALTIMER_SINGLE_TypeDef  *) CMSDK_DUALTIMER_2_BASE )
 #define CMSDK_RTC               ((CMSDK_RTC_TypeDef    *) CMSDK_RTC_BASE )
 #define CMSDK_WATCHDOG          ((CMSDK_WATCHDOG_TypeDef  *) CMSDK_WATCHDOG_BASE )
-#define CMSDK_GPIO0             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO0_BASE )
-#define CMSDK_GPIO1             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO1_BASE )
-#define CMSDK_GPIO2             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO2_BASE )
-#define CMSDK_GPIO3             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO3_BASE )
-#define CMSDK_GPIO4             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO4_BASE )
-#define CMSDK_GPIO5             ((CMSDK_GPIO_TypeDef   *) CMSDK_GPIO5_BASE )
 #define CMSDK_SYSCON            ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif  /* CMSDK_BEETLE_H */
+#endif  /* CMSDK_CM3DS_H */

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/SMM_MPS2.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/SMM_MPS2.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,6 +1,6 @@
 /* MPS2 CMSIS Library
  *
- * Copyright (c) 2006-2017 ARM Limited
+ * Copyright (c) 2006-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -154,154 +154,6 @@
 
 
 /******************************************************************************/
-/*                        SSP Peripheral declaration                          */
-/******************************************************************************/
-
-typedef struct                   // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
-{
-  __IO uint32_t CR0;             // Offset: 0x000 (R/W)  Control register 0
-                                 //                        [31:16] : Reserved
-                                 //                         [15:8] : Serial clock rate
-                                 //                            [7] : SSPCLKOUT phase,    applicable to Motorola SPI frame format only
-                                 //                            [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
-                                 //                          [5:4] : Frame format
-                                 //                          [3:0] : Data Size Select
-  __IO uint32_t CR1;             // Offset: 0x004 (R/W)  Control register 1
-                                 //                         [31:4] : Reserved
-                                 //                            [3] : Slave-mode output disable
-                                 //                            [2] : Master or slave mode select
-                                 //                            [1] : Synchronous serial port enable
-                                 //                            [0] : Loop back mode
-  __IO uint32_t DR;              // Offset: 0x008 (R/W)  Data register
-                                 //                        [31:16] : Reserved
-                                 //                         [15:0] : Transmit/Receive FIFO
-  __I  uint32_t SR;              // Offset: 0x00C (R/ )  Status register
-                                 //                         [31:5] : Reserved
-                                 //                            [4] : PrimeCell SSP busy flag
-                                 //                            [3] : Receive FIFO full
-                                 //                            [2] : Receive FIFO not empty
-                                 //                            [1] : Transmit FIFO not full
-                                 //                            [0] : Transmit FIFO empty
-  __IO uint32_t CPSR;            // Offset: 0x010 (R/W)  Clock prescale register
-                                 //                         [31:8] : Reserved
-                                 //                          [8:0] : Clock prescale divisor
-  __IO uint32_t IMSC;            // Offset: 0x014 (R/W)  Interrupt mask set or clear register
-                                 //                         [31:4] : Reserved
-                                 //                            [3] : Transmit FIFO interrupt mask
-                                 //                            [2] : Receive FIFO interrupt mask
-                                 //                            [1] : Receive timeout interrupt mask
-                                 //                            [0] : Receive overrun interrupt mask
-  __I  uint32_t RIS;             // Offset: 0x018 (R/ )  Raw interrupt status register
-                                 //                         [31:4] : Reserved
-                                 //                            [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
-                                 //                            [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
-                                 //                            [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
-                                 //                            [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
-  __I  uint32_t MIS;             // Offset: 0x01C (R/ )  Masked interrupt status register
-                                 //                         [31:4] : Reserved
-                                 //                            [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
-                                 //                            [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
-                                 //                            [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
-                                 //                            [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
-  __O  uint32_t ICR;             // Offset: 0x020 ( /W)  Interrupt clear register
-                                 //                         [31:2] : Reserved
-                                 //                            [1] : Clears the SSPRTINTR interrupt
-                                 //                            [0] : Clears the SSPRORINTR interrupt
-  __IO uint32_t DMACR;           // Offset: 0x024 (R/W)  DMA control register
-                                 //                         [31:2] : Reserved
-                                 //                            [1] : Transmit DMA Enable
-                                 //                            [0] : Receive DMA Enable
-} MPS2_SSP_TypeDef;
-
-
-// SSP_CR0 Control register 0
-#define SSP_CR0_DSS_Pos         0           // Data Size Select
-#define SSP_CR0_DSS_Msk         (0xF<<SSP_CR0_DSS_Pos)
-#define SSP_CR0_FRF_Pos         4           // Frame Format Select
-#define SSP_CR0_FRF_Msk         (3UL<<SSP_CR0_FRM_Pos)
-#define SSP_CR0_SPO_Pos         6           // SSPCLKOUT polarity
-#define SSP_CR0_SPO_Msk         (1UL<<SSP_CR0_SPO_Pos)
-#define SSP_CR0_SPH_Pos         7           // SSPCLKOUT phase
-#define SSP_CR0_SPH_Msk         (1UL<<SSP_CR0_SPH_Pos)
-#define SSP_CR0_SCR_Pos         8           // Serial Clock Rate (divide)
-#define SSP_CR0_SCR_Msk         (0xFF<<SSP_CR0_SCR_Pos)
-
-#define SSP_CR0_SCR_DFLT        0x0300      // Serial Clock Rate (divide), default set at 3
-#define SSP_CR0_FRF_MOT         0x0000      // Frame format, Motorola
-#define SSP_CR0_DSS_8           0x0007      // Data packet size, 8bits
-#define SSP_CR0_DSS_16          0x000F      // Data packet size, 16bits
-
-// SSP_CR1 Control register 1
-#define SSP_CR1_LBM_Pos         0           // Loop Back Mode
-#define SSP_CR1_LBM_Msk         (1UL<<SSP_CR1_LBM_Pos)
-#define SSP_CR1_SSE_Pos         1           // Serial port enable
-#define SSP_CR1_SSE_Msk         (1UL<<SSP_CR1_SSE_Pos)
-#define SSP_CR1_MS_Pos          2           // Master or Slave mode
-#define SSP_CR1_MS_Msk          (1UL<<SSP_CR1_MS_Pos)
-#define SSP_CR1_SOD_Pos         3           // Slave Output mode Disable
-#define SSP_CR1_SOD_Msk         (1UL<<SSP_CR1_SOD_Pos)
-
-// SSP_SR Status register
-#define SSP_SR_TFE_Pos          0           // Transmit FIFO empty
-#define SSP_SR_TFE_Msk          (1UL<<SSP_SR_TFE_Pos)
-#define SSP_SR_TNF_Pos          1           // Transmit FIFO not full
-#define SSP_SR_TNF_Msk          (1UL<<SSP_SR_TNF_Pos)
-#define SSP_SR_RNE_Pos          2           // Receive  FIFO not empty
-#define SSP_SR_RNE_Msk          (1UL<<SSP_SR_RNE_Pos)
-#define SSP_SR_RFF_Pos          3           // Receive  FIFO full
-#define SSP_SR_RFF_Msk          (1UL<<SSP_SR_RFF_Pos)
-#define SSP_SR_BSY_Pos          4           // Busy
-#define SSP_SR_BSY_Msk          (1UL<<SSP_SR_BSY_Pos)
-
-// SSP_CPSR Clock prescale register
-#define SSP_CPSR_CPD_Pos        0           // Clock prescale divisor
-#define SSP_CPSR_CPD_Msk        (0xFF<<SSP_CPSR_CDP_Pos)
-
-#define SSP_CPSR_DFLT           0x0008      // Clock prescale (use with SCR), default set at 8
-
-// SSPIMSC Interrupt mask set and clear register
-#define SSP_IMSC_RORIM_Pos         0           // Receive overrun not Masked
-#define SSP_IMSC_RORIM_Msk         (1UL<<SSP_IMSC_RORIM_Pos)
-#define SSP_IMSC_RTIM_Pos          1           // Receive timeout not Masked
-#define SSP_IMSC_RTIM_Msk          (1UL<<SSP_IMSC_RTIM_Pos)
-#define SSP_IMSC_RXIM_Pos          2           // Receive  FIFO not Masked
-#define SSP_IMSC_RXIM_Msk          (1UL<<SSP_IMSC_RXIM_Pos)
-#define SSP_IMSC_TXIM_Pos          3           // Transmit FIFO not Masked
-#define SSP_IMSC_TXIM_Msk          (1UL<<SSP_IMSC_TXIM_Pos)
-
-// SSPRIS Raw interrupt status register
-#define SSP_RIS_RORRIS_Pos         0           // Raw Overrun  interrupt flag
-#define SSP_RIS_RORRIS_Msk         (1UL<<SSP_RIS_RORRIS_Pos)
-#define SSP_RIS_RTRIS_Pos          1           // Raw Timemout interrupt flag
-#define SSP_RIS_RTRIS_Msk          (1UL<<SSP_RIS_RTRIS_Pos)
-#define SSP_RIS_RXRIS_Pos          2           // Raw Receive  interrupt flag
-#define SSP_RIS_RXRIS_Msk          (1UL<<SSP_RIS_RXRIS_Pos)
-#define SSP_RIS_TXRIS_Pos          3           // Raw Transmit interrupt flag
-#define SSP_RIS_TXRIS_Msk          (1UL<<SSP_RIS_TXRIS_Pos)
-
-// SSPMIS Masked interrupt status register
-#define SSP_MIS_RORMIS_Pos         0           // Masked Overrun  interrupt flag
-#define SSP_MIS_RORMIS_Msk         (1UL<<SSP_MIS_RORMIS_Pos)
-#define SSP_MIS_RTMIS_Pos          1           // Masked Timemout interrupt flag
-#define SSP_MIS_RTMIS_Msk          (1UL<<SSP_MIS_RTMIS_Pos)
-#define SSP_MIS_RXMIS_Pos          2           // Masked Receive  interrupt flag
-#define SSP_MIS_RXMIS_Msk          (1UL<<SSP_MIS_RXMIS_Pos)
-#define SSP_MIS_TXMIS_Pos          3           // Masked Transmit interrupt flag
-#define SSP_MIS_TXMIS_Msk          (1UL<<SSP_MIS_TXMIS_Pos)
-
-// SSPICR Interrupt clear register
-#define SSP_ICR_RORIC_Pos           0           // Clears Overrun  interrupt flag
-#define SSP_ICR_RORIC_Msk           (1UL<<SSP_ICR_RORIC_Pos)
-#define SSP_ICR_RTIC_Pos            1           // Clears Timemout interrupt flag
-#define SSP_ICR_RTIC_Msk            (1UL<<SSP_ICR_RTIC_Pos)
-
-// SSPDMACR DMA control register
-#define SSP_DMACR_RXDMAE_Pos        0           // Enable Receive  FIFO DMA
-#define SSP_DMACR_RXDMAE_Msk        (1UL<<SSP_DMACR_RXDMAE_Pos)
-#define SSP_DMACR_TXDMAE_Pos        1           // Enable Transmit FIFO DMA
-#define SSP_DMACR_TXDMAE_Msk        (1UL<<SSP_DMACR_TXDMAE_Pos)
-
-/******************************************************************************/
 /*               Audio and Touch Screen (I2C) Peripheral declaration          */
 /******************************************************************************/
 
@@ -577,11 +429,6 @@
 #define MPS2_AAIC_I2S           ((MPS2_I2S_TypeDef    *) MPS2_AAIC_I2S_BASE )
 #define MPS2_FPGAIO             ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
 #define MPS2_SCC                ((MPS2_SCC_TypeDef    *) MPS2_SCC_BASE )
-#define MPS2_SSP0               ((MPS2_SSP_TypeDef    *) MPS2_SSP0_BASE )
-#define MPS2_SSP1               ((MPS2_SSP_TypeDef    *) MPS2_SSP1_BASE )
-#define MPS2_SSP2               ((MPS2_SSP_TypeDef    *) MPS2_SSP2_BASE )
-#define MPS2_SSP3               ((MPS2_SSP_TypeDef    *) MPS2_SSP3_BASE )
-#define MPS2_SSP4               ((MPS2_SSP_TypeDef    *) MPS2_SSP4_BASE )
 
 /******************************************************************************/
 /*                     General Function Definitions                           */

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/MPS2.sct	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/MPS2.sct	Thu Apr 19 17:12:19 2018 +0100
@@ -1,7 +1,9 @@
+#! armcc -E
+
 /*
  * MPS2 CMSIS Library
  *
- * Copyright (c) 2006-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2006-2018 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,16 +24,25 @@
  *************************************************************
  */
 
-LR_IROM1 0x00000000 0x00040000  {    ; load region size_region
-  ER_IROM1 0x00000000 0x00040000  {  ; load address = execution address
+#include "../memory_zones.h"
+#include "../cmsis_nvic.h"
+
+; The vector table is loaded at address 0x00000000 in Flash memory region.
+LR_IROM1 FLASH_START FLASH_SIZE  {
+  ER_IROM1 FLASH_START FLASH_SIZE  {
    *.o (RESET, +First)
+  }
+}
+
+; Rest of the code is loaded to the ZBT SSRAM1.
+LR_IROM2 ZBT_SSRAM1_START ZBT_SSRAM1_SIZE {
+  ER_IROM2 ZBT_SSRAM1_START ZBT_SSRAM1_SIZE  {
    *(InRoot$$Sections)
    .ANY (+RO)
   }
-  ; Total: 80 vectors = 320 bytes (0x140) to be reserved in RAM
-  ; This is a bit more than is necessary based on the number of 
-  ; exception handlers.
-  RW_IRAM1 (0x20000000+0x140) (0x20000-0x140)  {  ; RW data
+  ; At execution, RAM is set to be in ZBT SSRAM2 and 3, just after the vector
+  ; table previously moved from Flash.
+  RW_IRAM1 (ZBT_SSRAM23_START + NVIC_VECTORS_SIZE) (ZBT_SSRAM23_SIZE - NVIC_VECTORS_SIZE)  {
    .ANY (+RW +ZI)
   }
 }

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_ARM_STD/startup_MPS2.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,7 +1,7 @@
 /*
  * MPS2 CMSIS Library
  *
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,11 +20,11 @@
  *
  * This file is derivative of CMSIS V5.00 startup_ARMCM3.s
  *
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  */
 
+#include "memory_zones.h"
 
-__initial_sp        EQU     0x20020000  ; Top of RAM
+__initial_sp    EQU     ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE ; Top of ZBT SSRAM2 and 3, used for data
 
                 PRESERVE8
                 THUMB

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_GCC_ARM/MPS2.ld	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_GCC_ARM/MPS2.ld	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,5 @@
 /*
- * MPS2 CMSIS Library
- */
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,21 +14,20 @@
  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  * See the License for the specific language governing permissions and
  * limitations under the License.
- */
-/*
+ *
  * This file is derivative of CMSIS V5.00 gcc_arm.ld
+ *
+ * Linker script for mbed CM3DS on MPS2
  */
-/* Linker script for mbed CM3DS on MPS2 */
 
-/* Linker script to configure memory regions. */
-/* The length of the VECTORS region is a bit larger than
- * is necessary based on the number of exception handlers.
- */
+#include "../memory_zones.h"
+#include "../cmsis_nvic.h"
+
 MEMORY
 {
-  VECTORS (rx)          : ORIGIN = 0x00000000, LENGTH = 0x00000400
-  FLASH (rx)            : ORIGIN = 0x00000400, LENGTH = 0x00040000 - 0x00000400
-  RAM (rwx)             : ORIGIN = 0x20000000, LENGTH = 0x00020000
+  VECTORS (rx)          : ORIGIN = FLASH_START,       LENGTH = FLASH_SIZE
+  FLASH (rx)            : ORIGIN = ZBT_SSRAM1_START,  LENGTH = ZBT_SSRAM1_SIZE
+  RAM (rwx)             : ORIGIN = ZBT_SSRAM23_START, LENGTH = ZBT_SSRAM23_SIZE
 }
 
 /* Linker script to place sections and symbol values. Should be used together
@@ -66,7 +62,7 @@
 STACK_SIZE = 0x1000;
 
 /* Size of the vector table in SRAM */
-M_VECTOR_RAM_SIZE = 0x140;
+M_VECTOR_RAM_SIZE = NVIC_VECTORS_SIZE;
 
 SECTIONS
 {

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/MPS2.icf	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/TOOLCHAIN_IAR/MPS2.icf	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,5 @@
 /*
- * MPS2 CMSIS Library
- */
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2018 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,26 +16,49 @@
  * limitations under the License.
  */
 
-/* The RAM region doesn't start at the beginning of the RAM address
- * space to create space for the vector table copied over to the RAM by mbed.
- * The space left is a bit bigger than is necessary based on the number of
- * interrupt handlers.
+/*
+ * WARNING: these symbols are the same as the defines in ../memory_zones.h but
+ * can not be included here. Please make sure that the two definitions match.
  */
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x00000000;
-/*-Memory Regions-*/
-define symbol __ICFEDIT_region_ROM_start__    = 0x00000000;
-define symbol __ICFEDIT_region_ROM_end__      = 0x0003FFFF;
-define symbol __ICFEDIT_region_RAM_start__    = 0x20000140;
-define symbol __ICFEDIT_region_RAM_end__      = 0x2001FFFF;
-/*-Sizes-*/
+/* Code memory zones */
+define symbol FLASH_START       = 0x00000000;
+define symbol FLASH_SIZE        = 0x00040000; /* 256 KiB */
+define symbol ZBT_SSRAM1_START  = 0x00400000;
+define symbol ZBT_SSRAM1_SIZE   = 0x00400000; /* 4 MiB */
+
+/* Data memory zones */
+define symbol SRAM0_START       = 0x20000000;
+define symbol SRAM0_SIZE        = 0x00008000; /* 32 KiB */
+define symbol SRAM1_START       = 0x20008000;
+define symbol SRAM1_SIZE        = 0x00008000; /* 32 KiB */
+define symbol SRAM2_START       = 0x20010000;
+define symbol SRAM2_SIZE        = 0x00008000; /* 32 KiB */
+define symbol SRAM3_START       = 0x20018000;
+define symbol SRAM3_SIZE        = 0x00008000; /* 32 KiB */
+define symbol ZBT_SSRAM23_START = 0x20400000;
+define symbol ZBT_SSRAM23_SIZE  = 0x00400000; /* 4 MiB */
+
+/* NVIC vector numbers and size. */
+define symbol NVIC_NUM_VECTORS        = 16 + 57;
+define symbol NVIC_VECTORS_SIZE       = NVIC_NUM_VECTORS * 4;
+
+/* Specials */
+define symbol __ICFEDIT_intvec_start__ = FLASH_START;
+
+/* Memory Regions */
+define symbol __ICFEDIT_region_ROM_start__    = ZBT_SSRAM1_START;
+define symbol __ICFEDIT_region_ROM_end__      = ZBT_SSRAM1_START + ZBT_SSRAM1_SIZE - 1;
+/*
+ * At execution, RAM is set to be in ZBT SSRAM2 and 3, just after the vector
+ * table previously moved from Flash.
+ */
+define symbol __ICFEDIT_region_RAM_start__    = ZBT_SSRAM23_START + NVIC_VECTORS_SIZE;
+define symbol __ICFEDIT_region_RAM_end__      = ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE;
+
+/* Sizes */
 /* Heap and Stack size */
-define symbol __ICFEDIT_size_heap__   = 0x4000;
+define symbol __ICFEDIT_size_heap__   = 0xF000;
 define symbol __ICFEDIT_size_cstack__ = 0x1000;
-/**** End of ICF editor section. ###ICF###*/
 
 define memory mem with size = 4G;
 define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/apb_timer.c	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,265 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "cmsis.h"
-#include "apb_timer.h"
-
-/* Timer Private Data */
-typedef struct {
-    /* Timer Definition */
-    CMSDK_TIMER_TypeDef *timerN;
-    /* Timer IRQn */
-    uint32_t timerIRQn;
-    /* Timer Reload Value */
-    uint32_t timerReload;
-    /* Timer state */
-    uint32_t state;
-} apb_timer_t;
-
-/* Timer state definitions */
-#define TIMER_INITIALIZED   (1)
-#define TIMER_ENABLED       (1 << 1)
-
-/*
- * This Timer is written for MBED OS and keeps count
- * of the ticks. All the elaboration logic is demanded
- * to the upper layers.
- */
-#define TIMER_MAX_VALUE     0xFFFFFFFF
-#define TIMER_TICKS_US      (SystemCoreClock/1000000)
-
-/* Timers Array */
-static apb_timer_t Timers[NUM_TIMERS];
-
-void Timer_Index_Init(uint32_t timer, uint32_t reload,
-    CMSDK_TIMER_TypeDef *TimerN, uint32_t IRQn)
-{
-    Timers[timer].timerN = TimerN;
-    Timers[timer].timerIRQn = IRQn;
-    Timers[timer].timerReload = reload;
-    Timers[timer].state = TIMER_INITIALIZED;
-}
-
-/*
- * Timer_Initialize(): Initializes an hardware timer
- * timer: timer to be Initialized
- * time_us: timer reload value in us - 0 to reload to timer max value
- *          time_us = tick_value / TIMER_TICKS_US
- */
-#define TIMER_INIT(index, reload) Timer_Index_Init(index, reload, CMSDK_TIMER##index, TIMER##index##_IRQn)
-void Timer_Initialize(uint32_t timer, uint32_t time_us)
-{
-    uint32_t reload = 0;
-
-    if (timer < NUM_TIMERS) {
-        if (time_us == 0) {
-            reload = TIMER_MAX_VALUE;
-        } else {
-            reload = (time_us) * TIMER_TICKS_US;
-        }
-        switch (timer) {
-            case 0:
-                TIMER_INIT(0, reload);
-                break;
-            case 1:
-                TIMER_INIT(1, reload);
-                break;
-            default:
-                break;
-        }
-    }
-}
-
-/*
- * Timer_Enable(): Enables a hardware timer
- * timer: timer to be enabled
- */
-void Timer_Enable(uint32_t timer)
-{
-    /* The timer has to be contained in a valid range */
-    if (timer < NUM_TIMERS) {
-        /* Timer has to be already initialized */
-        if (Timers[timer].state == TIMER_INITIALIZED) {
-            /* Disable Timer */
-            (Timers[timer].timerN)->CTRL = 0x0;
-            /* Reload Value */
-            (Timers[timer].timerN)->RELOAD = Timers[timer].timerReload;
-            /* Enable Interrupt */
-            (Timers[timer].timerN)->CTRL = CMSDK_TIMER_CTRL_IRQEN_Msk;
-            /* Enable Counter */
-            (Timers[timer].timerN)->CTRL |= CMSDK_TIMER_CTRL_EN_Msk;
-            /* Change timer state */
-            Timers[timer].state |= TIMER_ENABLED;
-        }
-    }
-}
-
-/*
- * Timer_Disable(): Disables a hardware timer
- * timer: timer to be disabled
- */
-void Timer_Disable(uint32_t timer)
-{
-    /* The timer has to be contained in a valid range */
-    if (timer < NUM_TIMERS) {
-        /* Timer has to be already initialized and enabled */
-        if (Timers[timer].state == (TIMER_INITIALIZED | TIMER_ENABLED)) {
-            /* Disable Timer */
-            (Timers[timer].timerN)->CTRL = 0x0;
-            /* Change timer state */
-            Timers[timer].state = TIMER_INITIALIZED;
-        }
-    }
-}
-
-/*
- * Timer_isEnabled(): verifies if a timer is enabled
- * timer: timer to be verified
- * @return: 0 disabled - 1 enabled
- */
-uint32_t Timer_isEnabled(uint32_t timer)
-{
-    /* The timer has to be contained in a valid range */
-    if (timer < NUM_TIMERS) {
-        /* Timer has to be already initialized and enabled */
-        if (Timers[timer].state == (TIMER_INITIALIZED | TIMER_ENABLED)) {
-            return 1;
-        }
-    }
-
-    return 0;
-}
-
-/*
- * Timer_Read(): provides timer VALUE
- * timer: timer to be read
- * @return: timer VALUE us
- */
-uint32_t Timer_Read(uint32_t timer)
-{
-    uint32_t return_value = 0;
-    /* Verify if the Timer is enabled */
-    if (Timer_isEnabled(timer) == 1) {
-        return_value = (Timers[timer].timerReload
-                        - (Timers[timer].timerN)->VALUE) / TIMER_TICKS_US;
-    }
-
-    return return_value;
-}
-
-/*
- * Timer_SetInterrupt(): sets timer Interrupt
- * timer: timer on which interrupt is set
- * time_us: reloading time in us
- */
-void Timer_SetInterrupt(uint32_t timer, uint32_t time_us)
-{
-    uint32_t load_time_us = 0;
-    /* Verify if the Timer is enabled */
-    if (Timer_isEnabled(timer) == 1) {
-        /* Disable Timer */
-        Timer_Disable(timer);
-        /* Enable Interrupt */
-        (Timers[timer].timerN)->CTRL = CMSDK_TIMER_CTRL_IRQEN_Msk;
-
-        /* Check time us condition */
-        if (time_us == TIMER_DEFAULT_RELOAD) {
-            load_time_us = TIMER_MAX_VALUE;
-        } else {
-            load_time_us = time_us * TIMER_TICKS_US;
-        }
-
-        /* Initialize Timer Value */
-        Timers[timer].timerReload = load_time_us;
-        (Timers[timer].timerN)->RELOAD = Timers[timer].timerReload;
-        (Timers[timer].timerN)->VALUE = Timers[timer].timerReload;
-        /* Enable Counter */
-        (Timers[timer].timerN)->CTRL |= CMSDK_TIMER_CTRL_EN_Msk;
-        /* Change timer state */
-        Timers[timer].state |= TIMER_ENABLED;
-    }
-}
-
-/*
- * Timer_DisableInterrupt(): disables timer interrupt
- * timer: timer on which interrupt is disabled
- */
-void Timer_DisableInterrupt(uint32_t timer)
-{
-    /* Verify if the Timer is enabled */
-    if (Timer_isEnabled(timer) == 1) {
-        /* Disable Interrupt */
-        (Timers[timer].timerN)->CTRL &= CMSDK_TIMER_CTRL_EN_Msk;
-    }
-}
-
-/*
- * Timer_ClearInterrupt(): clear timer interrupt
- * timer: timer on which interrupt needs to be cleared
- */
-void Timer_ClearInterrupt(uint32_t timer)
-{
-    /* Verify if the Timer is enabled */
-    if (Timer_isEnabled(timer) == 1) {
-        /* Clear Interrupt */
-        (Timers[timer].timerN)->INTCLEAR = CMSDK_TIMER_INTCLEAR_Msk;
-    }
-}
-
-/*
- * Timer_GetIRQn(): returns IRQn of a Timer
- * timer: timer on which IRQn is defined - 0 if it is not defined
- */
-uint32_t Timer_GetIRQn(uint32_t timer)
-{
-    /* Verify if the Timer is enabled */
-    if (Timer_isEnabled(timer) == 1) {
-        return Timers[timer].timerIRQn;
-    }
-    return 0;
-}
-
-/*
- * Timer_GetTicksUS(): returns the number of Ticks per us
- * timer: timer associated with the Ticks per us
- * @return: Ticks per us - 0 if the timer is disables
- */
-uint32_t Timer_GetTicksUS(uint32_t timer)
-{
-    /* Verify if the Timer is enabled */
-    if (Timer_isEnabled(timer) == 1) {
-        return TIMER_TICKS_US;
-    }
-    return 0;
-}
-
-/*
- * Timer_GetReloadValue(): returns the load value of the selected
- * timer.
- * timer: timer associated with the Ticks per us
- * @return: reload value of the selected singletimer
- */
-uint32_t Timer_GetReloadValue(uint32_t timer)
-{
-    /* Verify if the Timer is enabled */
-    if (Timer_isEnabled(timer) == 1) {
-        if (timer == TIMER1) {
-            return Timers[timer].timerReload / TIMER_TICKS_US;
-        } else {
-            return Timers[timer].timerReload / TIMER_TICKS_US;
-        }
-    }
-    return 0;
-}

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/apb_timer.h	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,111 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2016 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* This file is derivative of apb_timer.h from BEETLE */
-
-#ifndef _APB_TIMER_DRV_H
-#define _APB_TIMER_DRV_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Supported Number of Timers */
-#define NUM_TIMERS  2
-#define TIMER0  0
-#define TIMER1  1
-
-/* Default reload */
-#define TIMER_DEFAULT_RELOAD    0xFFFFFFFF
-
-/*
- * Timer_Initialize(): Initializes an hardware timer
- * timer: timer to be Initialized
- * time_us: timer reload value in us - 0 to reload to timer max value
- *          time_us = tick_value / TIMER_TICK_US
- */
-void Timer_Initialize(uint32_t timer, uint32_t time_us);
-
-/*
- * Timer_Enable(): Enables an hardware timer
- * timer: timer to be enabled
- */
-void Timer_Enable(uint32_t timer);
-
-/*
- * Timer_Disable(): Disables an hardware timer
- * timer: timer to be disabled
- */
-void Timer_Disable(uint32_t timer);
-
-/*
- * Timer_isEnabled(): verifies if a timer is enabled
- * timer: timer to be verified
- * @return: 0 disabled - 1 enabled
- */
-uint32_t Timer_isEnabled(uint32_t timer);
-
-/*
- * Timer_Read(): provides timer VALUE
- * timer: timer to be read
- * @return: timer VALUE
- */
-uint32_t Timer_Read(uint32_t timer);
-
-/*
- * Timer_SetInterrupt(): sets timer Interrupt
- * timer: timer on which interrupt is set
- * time_us: reloading time in us
- */
-void Timer_SetInterrupt(uint32_t timer, uint32_t time_us);
-
-/*
- * Timer_DisableInterrupt(): disables timer interrupt
- * timer: timer on which interrupt is disabled
- */
-void Timer_DisableInterrupt(uint32_t timer);
-
-/*
- * Timer_ClearInterrupt(): clear timer interrupt
- * timer: timer on which interrupt needs to be cleared
- */
-void Timer_ClearInterrupt(uint32_t timer);
-
-/*
- * Timer_GetIRQn(): returns IRQn of a Timer
- * timer: timer on which IRQn is defined - 0 if it is not defined
- */
-uint32_t Timer_GetIRQn(uint32_t timer);
-
-/*
- * Timer_GetTicksUS(): returns the number of Ticks per us
- * timer: timer associated with the Ticks per us
- * @return: Ticks per us - 0 if the timer is disables
- */
-uint32_t Timer_GetTicksUS(uint32_t timer);
-
-/*
- * Timer_GetReloadValue(): returns the load value of the selected
- * timer.
- * timer: timer associated with the Ticks per us
- * @return: reload value of the selected singletimer
- */
-uint32_t Timer_GetReloadValue(uint32_t timer);
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* _APB_TIMER_DRV_H */

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/cmsis.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/cmsis.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2015-2017 ARM Limited
+ * Copyright (c) 2015-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -25,7 +25,5 @@
 #include "SMM_MPS2.h"
 /* NVIC Driver */
 #include "cmsis_nvic.h"
-/* APB Timer */
-#include "apb_timer.h"
 
 #endif /* MBED_CMSIS_H */

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/cmsis_nvic.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/cmsis_nvic.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2015-2017 ARM Limited
+ * Copyright (c) 2015-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -14,12 +14,35 @@
  * limitations under the License.
  *
  * CMSIS-style functionality to support dynamic vectors
+ *
+ * This file is included in ARM and GCC_ARM linker scripts.
+ *
+ * WARNING: IAR does not include this file and re-define these values in
+ * MPS2.icf file. Please make sure that the two files share the same values.
  */
 
+#include "memory_zones.h"
+
 #ifndef MBED_CMSIS_NVIC_H
 #define MBED_CMSIS_NVIC_H
 
-#define NVIC_NUM_VECTORS        (16 + 48)
-#define NVIC_RAM_VECTOR_ADDRESS 0x20000000   /* Location of vectors in RAM */
+/*
+ * 16 vectors for initial stack pointer and internal exceptions (defined in
+ * Armv7-M ARM).
+ * 57 vectors for external interrupts (defined in CM3DS Eval RTL and Testbench
+ * User Guide).
+ */
+#define NVIC_NUM_VECTORS        (16 + 57)
+
+/*
+ * Location of vectors in RAM, they are copied at boot from adress 0x00000000 to
+ * that address.
+ */
+#define NVIC_RAM_VECTOR_ADDRESS ZBT_SSRAM23_START
+
+/*
+ * Size of the whole vector table in bytes. Each vector is on 32 bits.
+ */
+#define NVIC_VECTORS_SIZE       (NVIC_NUM_VECTORS * 4)
 
 #endif /* MBED_CMSIS_NVIC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/device_cfg.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_DEVICE_CFG_H__
+#define __ARM_LTD_DEVICE_CFG_H__
+
+/**
+ * \file device_cfg.h
+ * \brief
+ * This is the default device configuration file with all peripherals
+ * defined and configured to be used via the non-secure base address.
+ * This file is an example of how to define your own configuration file
+ * with the peripherals required for your application.
+ */
+
+/* CMSDK Timers */
+#define ARM_CMSDK_TIMER0
+#define ARM_CMSDK_TIMER1
+
+/* ARM GPIO */
+#define ARM_GPIO0
+#define ARM_GPIO1
+#define ARM_GPIO2
+#define ARM_GPIO3
+
+/* ARM MPS2 IO FPGAIO */
+#define ARM_MPS2_IO_FPGAIO
+
+/* ARM MPS2 IO SCC */
+#define ARM_MPS2_IO_SCC
+
+/* ARM SPI PL022 */
+#define DEFAULT_SPI_SPEED_HZ  4000000U /* 4MHz */
+#define ARM_SPI0
+#define ARM_SPI1
+#define ARM_SPI2
+#define ARM_SPI3
+#define ARM_SPI4
+
+/* ARM UART */
+#define DEFAULT_UART_BAUDRATE  9600
+#define ARM_UART0
+#define ARM_UART1
+#define ARM_UART2
+#define ARM_UART3
+#define ARM_UART4
+
+#endif  /* __ARM_LTD_DEVICE_CFG_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/arm_gpio_drv.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_gpio_drv.h"
+
+#include <stddef.h>
+
+/* GPIO state definitions */
+#define ARM_GPIO_INITIALIZED  (1 << 0)
+
+#define MAX_PIN_NBR           16
+
+/* GPIO register map structure */
+struct arm_gpio_reg_map_t {
+    volatile uint32_t  data;           /* Offset: 0x000 (R/W) Data register */
+    volatile uint32_t  dataout;        /* Offset: 0x004 (R/W) Data output
+                                        *                     latch register */
+    volatile uint32_t  reserved0[2];
+    volatile uint32_t  outenableset;   /* Offset: 0x010 (R/W) Output enable
+                                        *                     set register */
+    volatile uint32_t  outenableclr;   /* Offset: 0x014 (R/W) Output enable
+                                        *                     clear register */
+    volatile uint32_t  altfuncset;     /* Offset: 0x018 (R/W) Alternate function
+                                        *                     set register */
+    volatile uint32_t  altfuncclr;     /* Offset: 0x01C (R/W) Alternate function
+                                        *                     clear register */
+    volatile uint32_t  intenset;       /* Offset: 0x020 (R/W) Interrupt enable
+                                        *                     set register */
+    volatile uint32_t  intenclr;       /* Offset: 0x024 (R/W) Interrupt enable
+                                        *                     clear register */
+    volatile uint32_t  inttypeset;     /* Offset: 0x028 (R/W) Interrupt type
+                                        *                     set register */
+    volatile uint32_t  inttypeclr;     /* Offset: 0x02C (R/W) Interrupt type
+                                        *                     clear register */
+    volatile uint32_t  intpolset;      /* Offset: 0x030 (R/W) Interrupt polarity
+                                        *                     set register */
+    volatile uint32_t  intpolclr;      /* Offset: 0x034 (R/W) Interrupt polarity
+                                        *                     clear register */
+    union {
+        volatile uint32_t  intstatus;  /* Offset: 0x038 (R/ ) Interrupt status
+                                        *                     register */
+        volatile uint32_t  intclear;   /* Offset: 0x038 ( /W) Interrupt clear
+                                        *                     register */
+    }intreg;
+    volatile uint32_t reserved1[241];
+    volatile uint32_t lb_masked[256];  /* Offset: 0x400 - 0x7FC (R/W)
+                                        * Lower byte masked access register */
+    volatile uint32_t ub_masked[256];  /* Offset: 0x800 - 0xBFC (R/W)
+                                        * Upper byte masked access register */
+};
+
+/*
+ * \brief  Configures the pin or port.
+ *
+ * \param[in]  p_gpio_port  GPIO port to configure \ref ahbarm_gpio_reg_map_t
+ * \param[in]  mask         Pin bit mask.
+ * \param[in]  flags        Pin flags.
+ */
+static void set_port_config(struct arm_gpio_reg_map_t* p_gpio_port,
+                            uint32_t mask,
+                            uint32_t flags)
+{
+    if(flags & ARM_GPIO_PIN_DISABLE) {
+        p_gpio_port->altfuncset = mask;
+        return;
+    }
+
+    if(flags & ARM_GPIO_OUTPUT) {
+        p_gpio_port->outenableset = mask;
+    } else if(flags & ARM_GPIO_INPUT) {
+        p_gpio_port->outenableclr = mask;
+    }
+
+    /* Sets interrupt configuration */
+    if(flags & ARM_GPIO_IRQ) {
+        /* Interrupt type: EDGE = 1 - LEVEL = 0 */
+        if(flags & ARM_GPIO_IRQ_EDGE) {
+            p_gpio_port->inttypeset = mask;
+        } else if(flags & ARM_GPIO_IRQ_LEVEL) {
+            p_gpio_port->inttypeclr = mask;
+        }
+
+        /* Interrupt polarity */
+        if(flags & ARM_GPIO_IRQ_ACTIVE_LOW) {
+            p_gpio_port->intpolclr = mask;
+        } else if(flags & ARM_GPIO_IRQ_ACTIVE_HIGH) {
+            p_gpio_port->intpolset = mask;
+        }
+    }
+
+    if(flags & ARM_GPIO_PIN_ENABLE) {
+        p_gpio_port->altfuncclr = mask;
+    }
+}
+
+void arm_gpio_init(struct arm_gpio_dev_t* dev)
+{
+    struct arm_gpio_reg_map_t* p_gpio_port =
+                                     (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+    if(dev->data->state != ARM_GPIO_INITIALIZED) {
+        /* Disables all pins in this port */
+        set_port_config(p_gpio_port, DEFAULT_PORT_MASK, ARM_GPIO_PIN_DISABLE);
+
+        dev->data->port_mask = DEFAULT_PORT_MASK;
+        dev->data->state = ARM_GPIO_INITIALIZED;
+    }
+}
+
+enum arm_gpio_error_t arm_gpio_config(struct arm_gpio_dev_t* dev,
+                                      enum arm_gpio_access_t access,
+                                      uint8_t pin_num,
+                                      uint32_t flags)
+{
+    uint32_t pin_mask;
+    struct arm_gpio_reg_map_t* p_gpio_port =
+                                     (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+    if(dev->data->state != ARM_GPIO_INITIALIZED) {
+        return ARM_GPIO_ERR_PORT_NOT_INIT;
+    }
+
+    if(pin_num >= MAX_PIN_NBR) {
+        return ARM_GPIO_ERR_INVALID_ARG;
+    }
+
+    switch(access) {
+    case ARM_GPIO_ACCESS_PIN:
+        pin_mask = (1UL << pin_num);
+        set_port_config(p_gpio_port, pin_mask, flags);
+        break;
+    case ARM_GPIO_ACCESS_PORT:
+        set_port_config(p_gpio_port, dev->data->port_mask, flags);
+        break;
+    /* default:  The default is not defined intentionally to force the
+     *           compiler to check that all the enumeration values are
+     *           covered in the switch.*/
+    }
+
+    return ARM_GPIO_ERR_NONE;
+}
+
+enum arm_gpio_error_t arm_gpio_write(struct arm_gpio_dev_t* dev,
+                                     enum arm_gpio_access_t access,
+                                     uint8_t pin_num,
+                                     uint32_t value)
+{
+    struct arm_gpio_reg_map_t* p_gpio_port =
+                                     (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+    if(pin_num >= MAX_PIN_NBR) {
+        return ARM_GPIO_ERR_INVALID_ARG;
+    }
+
+    /* As ARM is a read-modify-write architecture, before set a
+     * value on a GPIO register it is required to disable the
+     * interrupts to prevent problems in a multitasking
+     * environment */
+    switch(access) {
+    case ARM_GPIO_ACCESS_PIN:
+        if(value) {
+            /* Sets the pin */
+            p_gpio_port->dataout |= (1UL << pin_num);
+        } else {
+            /* Clears the pin */
+            p_gpio_port->dataout &= ~(1UL << pin_num);
+        }
+        break;
+    case ARM_GPIO_ACCESS_PORT:
+        if(value) {
+            /* Sets masked pins */
+            p_gpio_port->dataout |= dev->data->port_mask;
+        } else {
+            /* Clears masked pins */
+            p_gpio_port->dataout &= ~(dev->data->port_mask);
+        }
+        break;
+    /* default: The default is not defined intentionally to force the
+     *          compiler to check that all the enumeration values are
+     *          covered in the switch. */
+    }
+
+    return ARM_GPIO_ERR_NONE;
+}
+
+int32_t arm_gpio_read(struct arm_gpio_dev_t* dev, enum arm_gpio_access_t access,
+                      uint8_t pin_num)
+{
+    uint32_t value;
+    struct arm_gpio_reg_map_t* p_gpio_port =
+                                     (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+    value = p_gpio_port->data;
+
+    if(access == ARM_GPIO_ACCESS_PIN) {
+        if(pin_num >= MAX_PIN_NBR) {
+            return -1;
+        }
+        value = ((value >> pin_num) & 1UL);
+    } else {
+        value &= dev->data->port_mask;
+    }
+
+    return (int32_t)value;
+}
+
+enum arm_gpio_error_t arm_gpio_set_interrupt(struct arm_gpio_dev_t* dev,
+                                             enum arm_gpio_access_t access,
+                                             uint8_t pin_num,
+                                             enum arm_gpio_irq_status_t status)
+{
+    uint32_t mask = 0;
+    struct arm_gpio_reg_map_t* p_gpio_port =
+                                     (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+    if(dev->data->state != ARM_GPIO_INITIALIZED) {
+        return ARM_GPIO_ERR_PORT_NOT_INIT;
+    }
+
+    if(pin_num >= MAX_PIN_NBR) {
+        return ARM_GPIO_ERR_INVALID_ARG;
+    }
+
+    switch(access) {
+    case ARM_GPIO_ACCESS_PIN:
+        mask = (1UL << pin_num);
+        break;
+    case ARM_GPIO_ACCESS_PORT:
+        mask = dev->data->port_mask;
+        break;
+    /* default: The default is not defined intentionally to force the
+     *          compiler to check that all the enumeration values are
+     *          covered in the switch.*/
+    }
+
+    if(status == ARM_GPIO_IRQ_ENABLE) {
+        p_gpio_port->intenset = mask;
+    } else {
+        p_gpio_port->intenclr = mask;
+    }
+
+    return ARM_GPIO_ERR_NONE;
+}
+
+enum arm_gpio_error_t arm_gpio_get_irq_status(struct arm_gpio_dev_t* dev,
+                                              enum arm_gpio_access_t access,
+                                              uint8_t pin_num,
+                                              uint32_t* status)
+{
+    struct arm_gpio_reg_map_t* p_gpio_port =
+                                    (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+    if(dev->data->state != ARM_GPIO_INITIALIZED) {
+        return ARM_GPIO_ERR_PORT_NOT_INIT;
+    }
+
+    if(pin_num >= MAX_PIN_NBR) {
+        return ARM_GPIO_ERR_INVALID_ARG;
+    }
+
+    *status = p_gpio_port->intreg.intstatus;
+
+    if(access == ARM_GPIO_ACCESS_PIN) {
+        *status = ((*status >> pin_num) & 1UL);
+    } else {
+        *status &= dev->data->port_mask;
+    }
+
+    return ARM_GPIO_ERR_NONE;
+}
+
+enum arm_gpio_error_t arm_gpio_clear_interrupt(struct arm_gpio_dev_t* dev,
+                                               uint8_t pin_num)
+{
+    struct arm_gpio_reg_map_t* p_gpio_port =
+                                     (struct arm_gpio_reg_map_t*)dev->cfg->base;
+
+    if(dev->data->state != ARM_GPIO_INITIALIZED) {
+        return ARM_GPIO_ERR_PORT_NOT_INIT;
+    }
+
+    if(pin_num >= MAX_PIN_NBR) {
+        return ARM_GPIO_ERR_INVALID_ARG;
+    }
+
+    p_gpio_port->intreg.intstatus = (1UL << pin_num);
+
+    return ARM_GPIO_ERR_NONE;
+}
+
+void arm_gpio_set_port_mask(struct arm_gpio_dev_t* dev, uint32_t port_mask)
+{
+    dev->data->port_mask = (port_mask & DEFAULT_PORT_MASK);
+}
+
+uint32_t arm_gpio_get_port_mask(struct arm_gpio_dev_t* dev)
+{
+    if(dev->data->state != ARM_GPIO_INITIALIZED) {
+        return 0;
+    }
+
+    return (dev->data->port_mask & DEFAULT_PORT_MASK);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/arm_gpio_drv.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file arm_gpio_drv.h
+ * \brief Generic driver for ARM GPIO.
+ */
+
+#ifndef __ARM_GPIO_DRV_H__
+#define __ARM_GPIO_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DEFAULT_PORT_MASK         0xFFFF  /* Default port mask */
+
+/* GPIO flags */
+#define ARM_GPIO_PIN_DISABLE      (1 << 0)
+#define ARM_GPIO_PIN_ENABLE       (1 << 1)
+#define ARM_GPIO_OUTPUT           (1 << 2)
+#define ARM_GPIO_INPUT            (1 << 3)
+#define ARM_GPIO_IRQ              (1 << 4)
+#define ARM_GPIO_IRQ_EDGE         (1 << 5)
+#define ARM_GPIO_IRQ_LEVEL        (1 << 6)
+#define ARM_GPIO_IRQ_ACTIVE_LOW   (1 << 7)
+#define ARM_GPIO_IRQ_ACTIVE_HIGH  (1 << 8)
+
+/* ARM GPIO enumeration types */
+enum arm_gpio_access_t {
+    ARM_GPIO_ACCESS_PIN = 0,  /*!< Pin access to GPIO */
+    ARM_GPIO_ACCESS_PORT      /*!< Port access to GPIO */
+};
+
+enum arm_gpio_irq_status_t {
+    ARM_GPIO_IRQ_DISABLE = 0,  /*!< Disable interruptions */
+    ARM_GPIO_IRQ_ENABLE        /*!< Enable interruptions */
+};
+
+enum arm_gpio_error_t {
+    ARM_GPIO_ERR_NONE = 0,      /*!< No error */
+    ARM_GPIO_ERR_INVALID_ARG,   /*!< Error invalid input argument */
+    ARM_GPIO_ERR_PORT_NOT_INIT  /*!< Error GPIO port not initialized */
+};
+
+/* ARM GPIO device configuration structure */
+struct arm_gpio_dev_cfg_t {
+    const uint32_t base;  /*!< GPIO base address */
+};
+
+/* ARM GPIO device data structure */
+struct arm_gpio_dev_data_t {
+    uint32_t state;      /*!< Indicates if the gpio driver
+                              is initialized and enabled */
+    uint32_t port_mask;  /*!< Port mask used for any port access */
+};
+
+/* ARM GPIO device structure */
+struct arm_gpio_dev_t {
+    const struct arm_gpio_dev_cfg_t* const cfg;  /*!< GPIO configuration */
+    struct arm_gpio_dev_data_t* const data;      /*!< GPIO data */
+};
+
+/* ARM GPIO pin structure */
+struct arm_gpio_pin_t {
+    uint32_t                number;       /*!< Pin number */
+    enum arm_gpio_access_t  access_type;  /*!< Type of access in the
+                                               GPIO block */
+};
+
+/**
+ * \brief Initializes GPIO port.
+ *
+ * \param[in] dev  GPIO port to initalize \ref arm_gpio_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_gpio_init(struct arm_gpio_dev_t* dev);
+
+/**
+ * \brief Configurates pin or port.
+ *
+ * \param[in] dev      GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] access   Access type \ref arm_gpio_access_t
+ * \param[in] pin_num  Pin number.
+ * \param[in] flags    Pin flags \ref arm_gpio_flags_t
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_gpio_error_t arm_gpio_config(struct arm_gpio_dev_t* dev,
+                                      enum arm_gpio_access_t access,
+                                      uint8_t pin_num,
+                                      uint32_t flags);
+
+/**
+ * \brief  Writes to output pin or port.
+ *
+ * \param[in] dev      GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] access   Access type \ref arm_gpio_access_t
+ * \param[in] pin_num  Pin number.
+ * \param[in] value    Value(s) to set.
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ * \note As ARM is a read-modify-write architecture, before writing a
+ *       value on a GPIO pin it is required to disable the
+ *       interrupts to prevent problems in a multitasking
+ *       environment.
+ */
+enum arm_gpio_error_t arm_gpio_write(struct arm_gpio_dev_t* dev,
+                                     enum arm_gpio_access_t access,
+                                     uint8_t pin_num,
+                                     uint32_t value);
+
+/**
+ * \brief Reads the pin or port status.
+ *
+ * \param[in] dev      GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] access   Access type \ref arm_gpio_access_t
+ * \param[in] pin_num  Pin number.
+ * \param[in] value    Value of input pin(s).
+ *
+ * \return Returns bit value for Pin access or port value for port access.
+ *  Negative value for error.
+ * \note This function doesn't check if dev is NULL.
+ */
+int32_t arm_gpio_read(struct arm_gpio_dev_t* dev, enum arm_gpio_access_t access,
+                      uint8_t pin_num);
+
+/**
+ * \brief Sets interrupt status for the given pin or port.
+ *
+ * \param[in] dev      GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] access   Access type \ref arm_gpio_access_t
+ * \param[in] pin_num  Pin number.
+ * \param[in] status   Interrupt status \ref arm_gpio_irq_status
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_gpio_error_t arm_gpio_set_interrupt(struct arm_gpio_dev_t* dev,
+                                             enum arm_gpio_access_t access,
+                                             uint8_t pin_num,
+                                             enum arm_gpio_irq_status_t status);
+
+/**
+ * \brief Gets interrupt status for the given pin or port.
+ *
+ * \param[in]  dev      GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in]  access   Access type \ref arm_gpio_access_t
+ * \param[in]  pin_num  Pin number.
+ * \param[out] status   Interrupt status values. If the access is by pin, then
+ *                      the status will be 0 or 1.
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_gpio_error_t arm_gpio_get_irq_status(struct arm_gpio_dev_t* dev,
+                                              enum arm_gpio_access_t access,
+                                              uint8_t pin_num,
+                                              uint32_t* status);
+
+/**
+ * \brief Clears gpio interrupt.
+ *
+ * \param[in] dev      GPIO port to initalize \ref arm_gpio_dev_t
+ * \param[in] pin_num  Pin number.
+ *
+ * \return Returns error code as specified in \ref arm_gpio_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_gpio_error_t arm_gpio_clear_interrupt(struct arm_gpio_dev_t* dev,
+                                               uint8_t pin_num);
+
+/**
+ * \brief Sets gpio mask for port access.
+ *
+ * \param[in] dev        GPIO port \ref arm_gpio_dev_t
+ * \param[in] port_mask  New port mask to set, only the 16 LSb are taken into
+ *                       account
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_gpio_set_port_mask(struct arm_gpio_dev_t* dev, uint32_t port_mask);
+
+/**
+ * \brief Gets gpio mask for port access.
+ *
+ * \param[in] dev  GPIO port \ref arm_gpio_dev_t
+ *
+ * \return Returns the current port mask
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_gpio_get_port_mask(struct arm_gpio_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ARM_GPIO_DRV_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/arm_mps2_io_drv.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_mps2_io_drv.h"
+
+/* There is at most 8 LEDs and switches on MPS2 SCC and 2 on FPGA IO */
+#define MAX_PIN_NBR_SCC    8
+#define MAX_PIN_NBR_FPGAIO 2
+
+/* Mask to 1 the first X bits */
+#define MASK(X)            ((1 << (X)) - 1)
+
+/* MPS2 IO register map structure */
+struct arm_mps2_io_reg_map_t {
+    union {
+        volatile uint32_t scc_leds;     /* Offset: 0x000 (R/W) Controls the MCC
+                                         *                     user LEDs
+                                         *         [31:8] : Reserved
+                                         *         [7:0]  : MCC LEDs */
+        volatile uint32_t fpgaio_leds;  /* Offset: 0x000 (R/W) LED connections
+                                         *         [31:2] : Reserved
+                                         *         [1:0]  : FPGAIO LEDs */
+    } led_reg;
+    volatile uint32_t reserved[1];
+    union {
+        volatile uint32_t scc_switches;  /* Offset: 0x008 (R/ ) Denotes the
+                                          *                     state of the MCC
+                                          *                     user switches
+                                          *         [31:8] : Reserved
+                                          *         [7:0]  : State of the MCC
+                                          *                  switches */
+        volatile uint32_t fpgaio_buttons;/* Offset: 0x008 (R/ ) Buttons
+                                          *         [31:2] : Reserved
+                                          *         [1:0]  : Buttons */
+    } button_reg;
+};
+
+void arm_mps2_io_write_leds(struct arm_mps2_io_dev_t* dev,
+                            enum arm_mps2_io_access_t access,
+                            uint8_t pin_num,
+                            uint32_t value)
+{
+    struct arm_mps2_io_reg_map_t* p_mps2_io_port =
+                                  (struct arm_mps2_io_reg_map_t*)dev->cfg->base;
+    /* Mask of involved bits */
+    uint32_t write_mask = 0;
+
+    switch (dev->cfg->type) {
+    case ARM_MPS2_IO_TYPE_SCC:
+        if (pin_num >= MAX_PIN_NBR_SCC) {
+            return;
+        }
+
+        switch (access) {
+        case ARM_MPS2_IO_ACCESS_PIN:
+            write_mask = (1UL << pin_num);
+            break;
+        case ARM_MPS2_IO_ACCESS_PORT:
+            write_mask = MASK(MAX_PIN_NBR_SCC);
+            break;
+        /*
+         * default: explicitely not used to force to cover all enumeration
+         * cases
+         */
+        }
+
+        if (value) {
+            p_mps2_io_port->led_reg.scc_leds |= write_mask;
+        } else {
+            p_mps2_io_port->led_reg.scc_leds &= ~write_mask;
+        }
+
+        break;
+    case ARM_MPS2_IO_TYPE_FPGAIO:
+        if (pin_num >= MAX_PIN_NBR_FPGAIO) {
+            return;
+        }
+
+        switch (access) {
+        case ARM_MPS2_IO_ACCESS_PIN:
+            write_mask = (1UL << pin_num);
+            break;
+        case ARM_MPS2_IO_ACCESS_PORT:
+            write_mask = MASK(MAX_PIN_NBR_FPGAIO);
+            break;
+        /*
+         * default: explicitely not used to force to cover all enumeration
+         * cases
+         */
+        }
+
+        if (value) {
+            p_mps2_io_port->led_reg.fpgaio_leds |= write_mask;
+        } else {
+            p_mps2_io_port->led_reg.fpgaio_leds &= ~write_mask;
+        }
+
+        break;
+    /* default: explicitely not used to force to cover all enumeration cases */
+    }
+}
+
+uint32_t arm_mps2_io_read_buttons(struct arm_mps2_io_dev_t* dev,
+                                  enum arm_mps2_io_access_t access,
+                                  uint8_t pin_num)
+{
+    struct arm_mps2_io_reg_map_t* p_mps2_io_port =
+                                  (struct arm_mps2_io_reg_map_t*)dev->cfg->base;
+    uint32_t value = 0;
+
+    switch (dev->cfg->type) {
+    case ARM_MPS2_IO_TYPE_SCC:
+        if (pin_num >= MAX_PIN_NBR_SCC) {
+            return 0;
+        }
+
+        /* Only read significant bits from this register */
+        value = p_mps2_io_port->button_reg.scc_switches & MASK(MAX_PIN_NBR_SCC);
+
+        break;
+    case ARM_MPS2_IO_TYPE_FPGAIO:
+        if (pin_num >= MAX_PIN_NBR_FPGAIO) {
+            return 0;
+        }
+
+        /* Only read significant bits from this register */
+        value = p_mps2_io_port->button_reg.fpgaio_buttons &
+                MASK(MAX_PIN_NBR_FPGAIO);
+
+        break;
+    /* default: explicitely not used to force to cover all enumeration cases */
+    }
+
+    if (access == ARM_MPS2_IO_ACCESS_PIN) {
+        value = ((value >> pin_num) & 1UL);
+    }
+
+    return value;
+}
+
+uint32_t arm_mps2_io_read_leds(struct arm_mps2_io_dev_t* dev,
+                               enum arm_mps2_io_access_t access,
+                               uint8_t pin_num)
+{
+    struct arm_mps2_io_reg_map_t* p_mps2_io_port =
+                                  (struct arm_mps2_io_reg_map_t*)dev->cfg->base;
+    uint32_t value = 0;
+
+    switch (dev->cfg->type) {
+    case ARM_MPS2_IO_TYPE_SCC:
+        if (pin_num >= MAX_PIN_NBR_SCC) {
+            return 0;
+        }
+
+        /* Only read significant bits from this register */
+        value = p_mps2_io_port->led_reg.scc_leds & MASK(MAX_PIN_NBR_SCC);
+
+        break;
+    case ARM_MPS2_IO_TYPE_FPGAIO:
+        if (pin_num >= MAX_PIN_NBR_FPGAIO) {
+            return 0;
+        }
+
+        /* Only read significant bits from this register */
+        value = p_mps2_io_port->led_reg.fpgaio_leds & MASK(MAX_PIN_NBR_FPGAIO);
+
+        break;
+    /* default: explicitely not used to force to cover all enumeration cases */
+    }
+
+    if (access == ARM_MPS2_IO_ACCESS_PIN) {
+        value = ((value >> pin_num) & 1UL);
+    }
+
+    return value;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/arm_mps2_io_drv.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file arm_mps2_io_drv.h
+ * \brief Generic driver for ARM MPS2 IO.
+ */
+
+#ifndef __ARM_MPS2_IO_DRV_H__
+#define __ARM_MPS2_IO_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ARM MPS2 IO enumeration types */
+enum arm_mps2_io_access_t {
+    ARM_MPS2_IO_ACCESS_PIN = 0,  /*!< Pin access to MPS2 IO */
+    ARM_MPS2_IO_ACCESS_PORT      /*!< Port access to MPS2 IO */
+};
+
+enum arm_mps2_io_type_t {
+    ARM_MPS2_IO_TYPE_SCC = 0,  /*!< Use the SCC IO device */
+    ARM_MPS2_IO_TYPE_FPGAIO    /*!< Use the FPGA IO device */
+};
+
+/* ARM MPS2 IO device configuration structure */
+struct arm_mps2_io_dev_cfg_t {
+    const uint32_t base;                 /*!< MPS2 IO base address */
+    const enum arm_mps2_io_type_t type;  /*!< SCC or FPGAIO */
+};
+
+/* ARM MPS2 IO device structure */
+struct arm_mps2_io_dev_t {
+    const struct arm_mps2_io_dev_cfg_t* const cfg; /*!< MPS2 IO configuration */
+};
+
+/**
+ * \brief  Writes to output LEDs.
+ *
+ * \param[in] dev      MPS2 IO device where to write \ref arm_mps2_io_dev_t
+ * \param[in] access   Access type \ref arm_mps2_io_access_t
+ * \param[in] pin_num  Pin number.
+ * \param[in] value    Value(s) to set.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_mps2_io_write_leds(struct arm_mps2_io_dev_t* dev,
+                            enum arm_mps2_io_access_t access,
+                            uint8_t pin_num,
+                            uint32_t value);
+
+/**
+ * \brief Reads the buttons status.
+ *
+ * \param[in] dev      MPS2 IO device where to read \ref arm_mps2_io_dev_t
+ * \param[in] access   Access type \ref arm_mps2_io_access_t
+ * \param[in] pin_num  Pin number.
+ *
+ * \return Returns bit value for Pin access or port value for port access.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_mps2_io_read_buttons(struct arm_mps2_io_dev_t* dev,
+                                  enum arm_mps2_io_access_t access,
+                                  uint8_t pin_num);
+
+/**
+ * \brief Reads the LED status.
+ *
+ * \param[in] dev      MPS2 IO device where to read \ref arm_mps2_io_dev_t
+ * \param[in] access   Access type \ref arm_mps2_io_access_t
+ * \param[in] pin_num  Pin number.
+ *
+ * \return Returns bit value for Pin access or port value for port access.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_mps2_io_read_leds(struct arm_mps2_io_dev_t* dev,
+                               enum arm_mps2_io_access_t access,
+                               uint8_t pin_num);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ARM_MPS2_IO_DRV_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/arm_uart_drv.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "arm_uart_drv.h"
+
+#include <stddef.h>
+
+/* UART register map structure */
+struct _arm_uart_reg_map_t {
+    volatile uint32_t data;   /* Offset: 0x000 (R/W) data register    */
+    volatile uint32_t state;  /* Offset: 0x004 (R/W) status register  */
+    volatile uint32_t ctrl;   /* Offset: 0x008 (R/W) control register */
+    union {
+        volatile uint32_t intrstatus;  /* Offset: 0x00c (R/ ) interrupt status
+                                        *                     register */
+        volatile uint32_t intrclear;   /* Offset: 0x00c ( /W) interrupt clear
+                                        *                     register  */
+    }intr_reg;
+    volatile uint32_t bauddiv;        /* Offset: 0x010 (R/W) Baudrate divider
+                                       *                     register */
+};
+
+/* CTRL Register */
+#define ARM_UART_TX_EN       (1ul << 0)
+#define ARM_UART_RX_EN       (1ul << 1)
+#define ARM_UART_TX_INTR_EN  (1ul << 2)
+#define ARM_UART_RX_INTR_EN  (1ul << 3)
+
+/* STATE Register */
+#define ARM_UART_TX_BF  (1ul << 0)
+#define ARM_UART_RX_BF  (1ul << 1)
+
+/* INTSTATUS Register */
+#define ARM_UART_TX_INTR  (1ul << 0)
+#define ARM_UART_RX_INTR  (1ul << 1)
+
+/* UART state definitions */
+#define ARM_UART_INITIALIZED  (1ul << 0)
+
+enum arm_uart_error_t arm_uart_init(struct arm_uart_dev_t* dev,
+                                    uint32_t system_clk)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+    if(system_clk == 0) {
+        return ARM_UART_ERR_INVALID_ARG;
+    }
+
+    /* Sets baudrate and system clock */
+    dev->data->system_clk = system_clk;
+    dev->data->baudrate = dev->cfg->default_baudrate;
+
+    /* Sets baudrate */
+    p_uart->bauddiv = (dev->data->system_clk / dev->cfg->default_baudrate);
+
+    /* Enables receiver and transmitter */
+    p_uart->ctrl = ARM_UART_RX_EN | ARM_UART_TX_EN;
+
+    dev->data->state = ARM_UART_INITIALIZED;
+
+    return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_set_baudrate(struct arm_uart_dev_t* dev,
+                                            uint32_t baudrate)
+{
+    uint32_t bauddiv;
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(baudrate == 0) {
+        return ARM_UART_ERR_INVALID_BAUD;
+    }
+
+    if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+        return ARM_UART_ERR_NOT_INIT;
+    }
+
+    /* Sets baudrate */
+    bauddiv = (dev->data->system_clk / baudrate);
+    dev->data->baudrate = baudrate;
+
+    /* Minimum bauddiv value */
+    if(bauddiv < 16) {
+        return ARM_UART_ERR_INVALID_BAUD;
+    }
+
+    p_uart->bauddiv = bauddiv;
+
+    return ARM_UART_ERR_NONE;
+}
+
+uint32_t arm_uart_get_baudrate(struct arm_uart_dev_t* dev)
+{
+    return dev->data->baudrate;
+}
+
+enum arm_uart_error_t arm_uart_set_clock(struct arm_uart_dev_t* dev,
+                                         uint32_t system_clk)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(system_clk == 0) {
+        return ARM_UART_ERR_INVALID_ARG;
+    }
+
+    if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+        return ARM_UART_ERR_NOT_INIT;
+    }
+
+    /* Sets system clock */
+    dev->data->system_clk = system_clk;
+
+    /* Updates baudrate divider */
+    p_uart->bauddiv = (dev->data->system_clk / dev->data->baudrate);
+
+    /* Enables receiver and transmitter */
+    return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_read(struct arm_uart_dev_t* dev, uint8_t* byte)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(!(p_uart->state & ARM_UART_RX_BF)) {
+        return ARM_UART_ERR_NOT_READY;
+    }
+
+    /* Reads data */
+    *byte = (uint8_t)p_uart->data;
+
+    return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_write(struct arm_uart_dev_t* dev, uint8_t byte)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(p_uart->state & ARM_UART_TX_BF) {
+        return ARM_UART_ERR_NOT_READY;
+    }
+
+    /* Sends data */
+    p_uart->data = byte;
+
+    return ARM_UART_ERR_NONE;
+}
+
+enum arm_uart_error_t arm_uart_irq_tx_enable(struct arm_uart_dev_t* dev)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+        return ARM_UART_ERR_NOT_INIT;
+    }
+
+    p_uart->ctrl |= ARM_UART_TX_INTR_EN;
+
+    return ARM_UART_ERR_NONE;
+}
+
+void arm_uart_irq_tx_disable(struct arm_uart_dev_t* dev)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(dev->data->state & ARM_UART_INITIALIZED ) {
+        p_uart->ctrl &= ~ARM_UART_TX_INTR_EN;
+    }
+}
+
+uint32_t arm_uart_tx_ready(struct arm_uart_dev_t* dev)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+        return 0;
+    }
+
+    return !(p_uart->state & ARM_UART_TX_BF);
+}
+
+enum arm_uart_error_t arm_uart_irq_rx_enable(struct arm_uart_dev_t* dev)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+        return ARM_UART_ERR_NOT_INIT;
+    }
+
+    p_uart->ctrl |= ARM_UART_RX_INTR_EN;
+
+    return ARM_UART_ERR_NONE;
+}
+
+void arm_uart_irq_rx_disable(struct arm_uart_dev_t* dev)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(dev->data->state & ARM_UART_INITIALIZED) {
+        p_uart->ctrl &= ~ARM_UART_RX_INTR_EN;
+    }
+}
+
+uint32_t arm_uart_rx_ready(struct arm_uart_dev_t* dev)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(!(dev->data->state & ARM_UART_INITIALIZED)) {
+        return 0;
+    }
+
+    return (p_uart->state & ARM_UART_RX_BF);
+}
+
+void arm_uart_clear_interrupt(struct arm_uart_dev_t* dev,
+                              enum arm_uart_irq_t irq)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+    if(dev->data->state & ARM_UART_INITIALIZED) {
+        /* Clears pending interrupts */
+        switch(irq) {
+        case ARM_UART_IRQ_RX:
+            p_uart->intr_reg.intrclear = ARM_UART_RX_INTR;
+            break;
+        case ARM_UART_IRQ_TX:
+            p_uart->intr_reg.intrclear = ARM_UART_TX_INTR;
+            break;
+        case ARM_UART_IRQ_COMBINED:
+            p_uart->intr_reg.intrclear = (ARM_UART_RX_INTR | ARM_UART_TX_INTR);
+            break;
+        case ARM_UART_IRQ_NONE:
+            break;
+        /* default: not defined to force all cases to be handled */
+        }
+    }
+}
+
+enum arm_uart_irq_t arm_uart_get_interrupt_status(struct arm_uart_dev_t* dev)
+{
+    struct _arm_uart_reg_map_t* p_uart =
+                                    (struct _arm_uart_reg_map_t*)dev->cfg->base;
+
+
+    if(dev->data->state & ARM_UART_INITIALIZED) {
+        switch(p_uart->intr_reg.intrstatus) {
+        case ARM_UART_TX_INTR:
+            return ARM_UART_IRQ_TX;
+            break;
+        case ARM_UART_RX_INTR:
+            return ARM_UART_IRQ_RX;
+            break;
+        case ARM_UART_TX_INTR | ARM_UART_RX_INTR:
+            return ARM_UART_IRQ_COMBINED;
+            break;
+        /* default: not defined to force all cases to be handled */
+        }
+    }
+    return ARM_UART_IRQ_NONE;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/arm_uart_drv.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file arm_uart_drv.h
+ * \brief Generic driver for ARM UART.
+ */
+
+#ifndef __ARM_UART_DRV_H__
+#define __ARM_UART_DRV_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ARM UART device configuration structure */
+struct arm_uart_dev_cfg_t {
+    const uint32_t base;              /*!< UART base address */
+    const uint32_t default_baudrate;  /*!< Default baudrate */
+};
+
+/* ARM UART device data structure */
+struct arm_uart_dev_data_t {
+    uint32_t state;       /*!< Indicates if the uart driver
+                               is initialized and enabled */
+    uint32_t system_clk;  /*!< System clock */
+    uint32_t baudrate;    /*!< Baudrate */
+};
+
+/* ARM UART device structure */
+struct arm_uart_dev_t {
+    const struct arm_uart_dev_cfg_t* const cfg;  /*!< UART configuration */
+    struct arm_uart_dev_data_t* const data;      /*!< UART data */
+};
+
+/* ARM UART enumeration types */
+enum arm_uart_error_t {
+    ARM_UART_ERR_NONE = 0,      /*!< No error */
+    ARM_UART_ERR_INVALID_ARG,   /*!< Error invalid input argument */
+    ARM_UART_ERR_INVALID_BAUD,  /*!< Invalid baudrate */
+    ARM_UART_ERR_NOT_INIT,      /*!< Error UART not initialized */
+    ARM_UART_ERR_NOT_READY,     /*!< Error UART not ready */
+};
+
+enum arm_uart_irq_t {
+    ARM_UART_IRQ_RX,          /*!< RX interrupt source */
+    ARM_UART_IRQ_TX,          /*!< TX interrupt source */
+    ARM_UART_IRQ_COMBINED,    /*!< RX-TX combined interrupt source */
+    ARM_UART_IRQ_NONE = 0xFF  /*!< RX-TX combined interrupt source */
+};
+
+/**
+ * \brief Initializes UART. It uses the default baudrate to configure
+ * the peripheral at this point.
+ *
+ * \param[in] dev         UART device struct \ref arm_uart_dev_t
+ * \param[in] system_clk  System clock used by the device.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_init(struct arm_uart_dev_t* dev,
+                                    uint32_t system_clk);
+
+/**
+ * \brief Sets the UART baudrate.
+ *
+ * \param[in] dev       UART device struct \ref arm_uart_dev_t
+ * \param[in] baudrate  New baudrate.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_set_baudrate(struct arm_uart_dev_t* dev,
+                                            uint32_t baudrate);
+
+/**
+ * \brief Gets the UART baudrate.
+ *
+ * \param[in] dev  UART device struct \ref arm_uart_dev_t
+ *
+ * \return Returns the UART baudrate.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_uart_get_baudrate(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Sets system clock.
+ *
+ * \param[in] dev         UART device struct \ref arm_uart_dev_t
+ * \param[in] system_clk  System clock used by the device.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_set_clock(struct arm_uart_dev_t* dev,
+                                         uint32_t system_clk);
+/**
+ * \brief Reads one byte from UART dev.
+ *
+ * \param[in] dev   UART device struct \ref arm_uart_dev_t
+ * \param[in] byte  Pointer to byte.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note For better performance, this function doesn't check if dev and byte
+ * pointer are NULL, and if the driver is initialized.
+ */
+enum arm_uart_error_t arm_uart_read(struct arm_uart_dev_t* dev, uint8_t* byte);
+
+/**
+ * \brief Writes a byte to UART dev.
+ *
+ * \param[in] dev   UART device struct \ref arm_uart_dev_t
+ * \param[in] byte  Byte to write.
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note For better performance, this function doesn't check if dev is NULL and
+ * if the driver is initialized to have better performance.
+ */
+enum arm_uart_error_t arm_uart_write(struct arm_uart_dev_t* dev, uint8_t byte);
+
+/**
+ * \brief Enables TX interrupt.
+ *
+ * \param[in] dev  UART device struct \ref arm_uart_dev_t
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_irq_tx_enable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Disables TX interrupt.
+ *
+ * \param[in] dev  UART device struct \ref arm_uart_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_uart_irq_tx_disable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief  Verifies if Tx is ready to send more data.
+ *
+ * \param[in] dev  UART device struct \ref arm_uart_dev_t
+ *
+ * \return  1 if TX is ready, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_uart_tx_ready(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Enables RX interrupt.
+ *
+ * \param[in] dev  UART device struct \ref arm_uart_dev_t
+ *
+ * \return Returns error code as specified in \ref arm_uart_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_error_t arm_uart_irq_rx_enable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Disables RX interrupt
+ *
+ * \param[in] dev  UART device struct \ref arm_uart_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_uart_irq_rx_disable(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Verifies if Rx has data.
+ *
+ * \param[in] dev  UART device struct \ref arm_uart_dev_t
+ *
+ * \return 1 if RX has data, 0 otherwise.
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t arm_uart_rx_ready(struct arm_uart_dev_t* dev);
+
+/**
+ * \brief Clears UART interrupt.
+ *
+ * \param[in] dev  UART device struct \ref arm_uart_dev_t
+ * \param[in] irq  IRQ source to clean \ref arm_uart_irq_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void arm_uart_clear_interrupt(struct arm_uart_dev_t* dev,
+                              enum arm_uart_irq_t irq);
+
+/**
+ * \brief Returns UART interrupt status.
+ *
+ * \param[in] dev  UART device struct \ref arm_uart_dev_t
+ *
+ * \return IRQ status \ref arm_uart_irq_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum arm_uart_irq_t arm_uart_get_interrupt_status(struct arm_uart_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ARM_UART_DRV_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/spi_pl022_drv.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,870 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "spi_pl022_drv.h"
+
+/******************************************************************************
+ * PL022 device specific definitions based on DDI0194H_ssp_pl022_trm.pdf which
+ * is available from infocenter.arm.com.
+ *
+ * This version of driver aims at necessary functionality for MPS2 board only
+ *****************************************************************************/
+
+/* Structure for the SSP Primary Cell device registers */
+struct spi_pl022_dev_reg_map_t {
+    volatile uint32_t sspcr0;        /* Control register 0 */
+    volatile uint32_t sspcr1;        /* Control register 1 */
+    volatile uint32_t sspdr;         /* Data register */
+    volatile uint32_t sspsr;         /* Status register */
+    volatile uint32_t sspcpsr;       /* Clock prescale register */
+    volatile uint32_t sspimsc;       /* Interrupt mask set or clear register */
+    volatile uint32_t sspris;        /* Raw interrupt status register */
+    volatile uint32_t sspmis;        /* Masked interrupt status register */
+    volatile uint32_t sspicr;        /* Interrupt clear register */
+    volatile uint32_t sspdmacr;      /* DMA control register */
+    volatile uint32_t reserved[1006];/* Reserved from Base+0x28-0xFE0 */
+    volatile uint32_t sspperiphid0;  /* Peripheral id register 0 */
+    volatile uint32_t sspperiphid1;  /* Peripheral id register 1 */
+    volatile uint32_t sspperiphid2;  /* Peripheral id register 2 */
+    volatile uint32_t sspperiphid3;  /* Peripheral id register 3 */
+    volatile uint32_t ssppcellid0;   /* Primary cell id register 0 */
+    volatile uint32_t ssppcellid1;   /* Primary cell id register 1 */
+    volatile uint32_t ssppcellid2;   /* Primary cell id register 2 */
+    volatile uint32_t ssppcellid3;   /* Primary cell id register 3 */
+};
+
+/*--- SSP Control Register 0 ---*/
+
+/* Data Size Select {0x3=4 ... 0xF=16} */
+#define SPI_PL022_SSPCR0_DSS_POS         0
+#define SPI_PL022_SSPCR0_DSS_MSK         0xF
+
+/* Frame format */
+#define SPI_PL022_SSPCR0_FRF_POS         4
+#define SPI_PL022_SSPCR0_FRF_MSK         (0x3ul<<SPI_PL022_SSPCR0_FRF_POS)
+#define SPI_PL022_SSPCR0_FRF_MOT_SPI     0x0
+#define SPI_PL022_SSPCR0_FRF_TI_SS       0x1
+#define SPI_PL022_SSPCR0_FRF_MICROWIRE   0x2
+#define SPI_PL022_SSPCR0_FRF_RES         0x3
+
+/* Clock polarity applicable to Motorola SPI format only */
+#define SPI_PL022_SSPCR0_SPO_POS         6
+#define SPI_PL022_SSPCR0_SPO_MSK         (0x1ul<<SPI_PL022_SSPCR0_SPO_POS)
+
+/* Clock phase applicable to Motorola SPI format only */
+#define SPI_PL022_SSPCR0_SPH_POS         7
+#define SPI_PL022_SSPCR0_SPH_MSK         (0x1ul<<SPI_PL022_SSPCR0_SPH_POS)
+
+/* Serial clock rate */
+#define SPI_PL022_SSPCR0_SCR_POS         8
+#define SPI_PL022_SSPCR0_SCR_MSK         (0xFFul<<SPI_PL022_SSPCR0_SCR_POS)
+
+/*--- SSP Control Register 1 ---*/
+
+/* Loopback mode*/
+#define SPI_PL022_SSPCR1_LBM_POS         0
+#define SPI_PL022_SSPCR1_LBM_MSK         (0x1ul<<SPI_PL022_SSPCR1_LBM_POS)
+
+/* Syncrhonous serial port enable*/
+#define SPI_PL022_SSPCR1_SSE_POS         1
+#define SPI_PL022_SSPCR1_SSE_MSK         (0x1ul<<SPI_PL022_SSPCR1_SSE_POS)
+
+/* Master or Slave select */
+#define SPI_PL022_SSPCR1_MS_POS          2
+#define SPI_PL022_SSPCR1_MS_MSK          (0x1ul<<SPI_PL022_SSPCR1_MS_POS)
+
+/* Slave mode output disable */
+#define SPI_PL022_SSPCR1_SOD_POS         3
+#define SPI_PL022_SSPCR1_SOD_MSK         (0x1ul<<SPI_PL022_SSPCR1_SOD_POS)
+
+/*--- Clock PreScale Register ---*/
+
+/* Divisor */
+#define SPI_PL022_SSPCPSR_CPSDVSR_POS   0
+#define SPI_PL022_SSPCPSR_CPSDVSR_MSK   (0xFFul<<SPI_PL022_SSPCPSR_CPSDVSR_POS)
+#define SPI_PL022_INVALID_SSPCPSR_VALUE 0
+#define SPI_PL022_MIN_SSPCPSR_VALUE     2
+#define SPI_PL022_MAX_SSPCPSR_VALUE     254
+#define SPI_PL022_MAX_SCR_VALUE         255
+
+
+/*--- Interrupt Mask Set or Clear Register --- */
+
+/* Receive Overrun Interrupt Mask */
+#define SPI_PL022_SSPIMSC_RORIM_POS     0
+#define SPI_PL022_SSPIMSC_RORIM_MSK     (0x1ul<<SPI_PL022_SSPIMSC_RORIM_POS)
+
+/* Receive Timeout Interrupt Mask */
+#define SPI_PL022_SSPIMSC_RTIM_POS      1
+#define SPI_PL022_SSPIMSC_RTIM_MSK      (0x1ul<<SPI_PL022_SSPIMSC_RTIM_POS)
+
+/* Receive FIFO Interrupt Mask */
+#define SPI_PL022_SSPIMSC_RXIM_POS      2
+#define SPI_PL022_SSPIMSC_RXIM_MSK      (0x1ul<<SPI_PL022_SSPIMSC_RXIM_POS)
+
+/* Transmit FIFO Interrupt Mask */
+#define SPI_PL022_SSPIMSC_TXIM_POS      3
+#define SPI_PL022_SSPIMSC_TXIM_MSK      (0x1ul<<SPI_PL022_SSPIMSC_TXIM_POS)
+
+/*--- Interrupt Mask Set or Clear Register ---*/
+
+/* Receive Overrun Interrupt Mask */
+#define SPI_PL022_SSPIMSC_RORIM_POS     0
+#define SPI_PL022_SSPIMSC_RORIM_MSK     (0x1ul<<SPI_PL022_SSPIMSC_RORIM_POS)
+
+/* Receive Timeout Interrupt Mask */
+#define SPI_PL022_SSPIMSC_RTIM_POS      1
+#define SPI_PL022_SSPIMSC_RTIM_MSK      (0x1ul<<SPI_PL022_SSPIMSC_RTIM_POS)
+
+/* Receive FIFO Interrupt Mask */
+#define SPI_PL022_SSPIMSC_RXIM_POS      2
+#define SPI_PL022_SSPIMSC_RXIM_MSK      (0x1ul<<SPI_PL022_SSPIMSC_RXIM_POS)
+
+/* Transmit FIFO Interrupt Mask */
+#define SPI_PL022_SSPIMSC_TXIM_POS      3
+#define SPI_PL022_SSPIMSC_TXIM_MSK      (0x1ul<<SPI_PL022_SSPIMSC_TXIM_POS)
+
+#define SPI_PL022_SSPIMSC_VALID_MSK     \
+                               ((0x1ul<<(SPI_PL022_SSPIMSC_TXIM_POS+1))-1)
+
+/*--- Raw Interrupt Status Register ---*/
+
+/* SSPRORINTR */
+#define SPI_PL022_SSPRIS_RORRIS_POS     0
+#define SPI_PL022_SSPRIS_RORRIS_MSK     (0x1ul<<SPI_PL022_SSPRIS_RORRIS_POS)
+
+/* SSPRTINTR */
+#define SPI_PL022_SSPRIS_RTRIS_POS      1
+#define SPI_PL022_SSPRIS_RTRIS_MSK      (0x1ul<<SPI_PL022_SSPRIS_RTRIS_POS)
+
+/* SSPRXINTR */
+#define SPI_PL022_SSPRIS_RXRIS_POS      2
+#define SPI_PL022_SSPRIS_RXRIS_MSK      (0x1ul<<SPI_PL022_SSPRIS_RXRIS_POS)
+
+/* SSPTXINTR */
+#define SPI_PL022_SSPRIS_TXRIS_POS      3
+#define SPI_PL022_SSPRIS_TXRIS_MSK      (0x1ul<<SPI_PL022_SSPRIS_TXRIS_POS)
+
+#define SPI_PL022_SSPRIS_VALID_MSK      \
+                               ((0x1ul<<(SPI_PL022_SSPRIS_TXRIS_POS+1))-1)
+
+/*--- Masked Interrupt Status Register ---*/
+
+/* SSPRORINTR */
+#define SPI_PL022_SSPMIS_RORMIS_POS     0
+#define SPI_PL022_SSPMIS_RORMIS_MSK     (0x1ul<<SPI_PL022_SSPMIS_RORMIS_POS)
+
+/* SSPRTINTR */
+#define SPI_PL022_SSPMIS_RTMIS_POS      1
+#define SPI_PL022_SSPMIS_RTMIS_MSK      (0x1ul<<SPI_PL022_SSPMIS_RTMIS_POS)
+
+/* SSPRXINTR */
+#define SPI_PL022_SSPMIS_RXMIS_POS      2
+#define SPI_PL022_SSPMIS_RXMIS_MSK      (0x1ul<<SPI_PL022_SSPMIS_RXMIS_POS)
+
+/* SSPTXINTR */
+#define SPI_PL022_SSPMIS_TXMIS_POS      3
+#define SPI_PL022_SSPMIS_TXMIS_MSK      (0x1ul<<SPI_PL022_SSPMIS_TXMIS_POS)
+
+#define SPI_PL022_SSPMIS_VALID_MSK      \
+                               ((0x1ul<<(SPI_PL022_SSPMIS_TXMIS_POS+1))-1)
+
+/*--- Interrupt Clear Register --- */
+
+/* SSPRORINTR Clear */
+#define SPI_PL022_SSPICR_RORIC_POS      0
+#define SPI_PL022_SSPICR_RORIC_MSK      (0x1ul<<SPI_PL022_SSPICR_RORIC_POS)
+
+/* SSPRTINTR Clear */
+#define SPI_PL022_SSPICR_RTIC_POS       1
+#define SPI_PL022_SSPICR_RTIC_MSK       (0x1ul<<SPI_PL022_SSPICR_RTIC_POS)
+
+#define SPI_PL022_SSPICR_VALID_MSK      ((0x1ul<<(SPI_PL022_SSPICR_RTIC_POS+1))-1)
+
+/*--- DMA Control Register --- */
+
+/* Receive DMA Enable */
+#define SPI_PL022_SSPDMACR_RXDMAE_POS   0
+#define SPI_PL022_SSPDMACR_RXDMAE_MSK   (0x1ul<<SPI_PL022_SSPDMACR_RXDMAE_POS)
+
+/* Transmit DMA Enable */
+#define SPI_PL022_SSPDMACR_TXDMAE_POS   1
+#define SPI_PL022_SSPDMACR_TXDMAE_MSK   (0x1ul<<SPI_PL022_SSPDMACR_TXDMAE_POS)
+
+#define SPI_PL022_SSPDMACR_VALID_MSK    ((0x1ul<<(SPI_PL022_SSPDMACR_TXDMAE_POS+1))-1)
+
+/*--- Peripheral Identification Registers ---*/
+
+#define SPI_PL022_SSPPERIPH_ID_OFFSET (0xFE0ul)
+
+/* Part Number 0 */
+#define SPI_PL022_SSPPERIPH_ID0_PARTNO_0_POS   0
+#define SPI_PL022_SSPPERIPH_ID0_PARTNO_0_SIZE  8
+#define SPI_PL022_SSPPERIPH_ID0_PARTNO_0_MSK   \
+                                 (0xFFul<<SPI_PL022_SSPPERIPH_ID0_PARTNO_0_POS)
+
+/* Part Number 1 */
+#define SPI_PL022_SSPPERIPH_ID1_PARTNO_1_POS  0
+#define SPI_PL022_SSPPERIPH_ID1_PARTNO_1_SIZE 0
+#define SPI_PL022_SSPPERIPH_ID1_PARTNO_1_MSK \
+                                 (0xFul<<SPI_PL022_SSPPERIPH_ID1_PARTNO_1_POS)
+
+/* Designer 0 */
+#define SPI_PL022_SSPPERIPH_ID1_DESIGNER_0_POS  4
+#define SPI_PL022_SSPPERIPH_ID1_DESIGNER_0_SIZE 4
+#define SPI_PL022_SSPPERIPH_ID1_DESIGNER_0_MSK \
+                                 (0xFul<<SPI_PL022_SSPPERIPH_ID1_DESIGNER_0_POS)
+
+/* Designer 1 */
+#define SPI_PL022_SSPPERIPH_ID2_DESIGNER_1_POS  0
+#define SPI_PL022_SSPPERIPH_ID2_DESIGNER_1_SIZE 4
+#define SPI_PL022_SSPPERIPH_ID2_DESIGNER_1_MSK \
+                                 (0xFul<<SPI_PL022_SSPPERIPH_ID2_DESIGNER_1_POS)
+
+/* Revision */
+#define SPI_PL022_SSPPERIPH_ID2_REVISION_POS  4
+#define SPI_PL022_SSPPERIPH_ID2_REVISION_SIZE 4
+#define SPI_PL022_SSPPERIPH_ID2_REVIISON_MSK \
+                                 (0xFul<<SPI_PL022_SSPPERIPH_ID2_REVISION_POS)
+
+/* Config */
+#define SPI_PL022_SSPPERIPH_ID3_CONFIG_POS   0
+#define SPI_PL022_SSPPERIPH_ID3_CONFIG_MSK   \
+                                 (0xFFul<<SPI_PL022_SSPPERIPH_ID3_CONFIG_POS)
+
+/*--- PrimeCell Identification Registers ---*/
+
+#define SPI_PL022_SSPPCELL_ID_OFFSET   (0xFF0ul)
+
+#define SPI_PL022_SSPPCELL_ID0_POS     0
+#define SPI_PL022_SSPPCELL_ID0_MSK     (0xFFul<<SPI_PL022_SSPPCELL_ID0_POS)
+
+#define SPI_PL022_SSPPCELL_ID1_POS     0
+#define SPI_PL022_SSPPCELL_ID1_MSK     (0xFFul<<SPI_PL022_SSPPCELL_ID1_POS)
+
+#define SPI_PL022_SSPPCELL_ID2_POS     0
+#define SPI_PL022_SSPPCELL_ID2_MSK     (0xFFul<<SPI_PL022_SSPPCELL_ID2_POS)
+
+#define SPI_PL022_SSPPCELL_ID3_POS     0
+#define SPI_PL022_SSPPCELL_ID3_MSK     (0xFFul<<SPI_PL022_SSPPCELL_ID3_POS)
+
+/* ARM SPI PL022 state definitions */
+#define SPI_PL022_INITIALIZED          (1 << 0)
+
+#define WORD_1BYTE_MASK                (0xFFul)
+#define WORD_2BYTES_MASK               (0xFFFFul)
+
+
+/************************* PL022 TEST Definitions ******************************/
+#define SPI_PL022_TEST_REG_BASE        (0x80ul)
+
+struct spi_pl022_dev_test_reg_map_t {
+    volatile uint32_t ssptcr;        /* Test Control register */
+    volatile uint32_t sspitip;       /* Integration test input register */
+    volatile uint32_t sspitop;       /* Integration test output register */
+    volatile uint32_t ssptdr;        /* Test data register */
+};
+
+/* Test control register */
+#define SPI_PL022_SSPTCR_ITEN_POS           0
+#define SPI_PL022_SSPTCR_ITEN_MSK          (0x1ul<<SPI_PL022_SSPTCR_ITEN_POS)
+
+#define SPI_PL022_SSPTCR_TESTFIFO_POS       1
+#define SPI_PL022_SSPTCR_TESTFIFO_MSK       (0x1ul<<SPI_PL022_SSPTCR_TESTFIFO_POS)
+
+
+/* Integration test input register */
+#define SPI_PL022_SSPITIP_RXD_POS           0
+#define SPI_PL022_SSPITIP_RXD_MSK           (0x1ul<<SPI_PL022_SSPITIP_RXD_POS)
+
+#define SPI_PL022_SSPITIP_FSSIN_POS         1
+#define SPI_PL022_SSPITIP_FSSIN_MSK         (0x1ul<<SPI_PL022_SSPITIP_FSSIN_POS)
+
+#define SPI_PL022_SSPITIP_CLKIN_POS         2
+#define SPI_PL022_SSPITIP_CLKIN_MSK         (0x1ul<<SPI_PL022_SSPITIP_CLKIN_POS)
+
+#define SPI_PL022_SSPITIP_RXDMACLR_POS      3
+#define SPI_PL022_SSPITIP_RXDMACLR_MSK      (0x1ul<<SPI_PL022_SSPITIP_RXDMACLR_POS)
+
+#define SPI_PL022_SSPITIP_TXDMACLR_POS      4
+#define SPI_PL022_SSPITIP_TXDMACLR_MSK      (0x1ul<<SPI_PL022_SSPITIP_TXDMACLR_POS)
+
+/* Integration test output register */
+#define SPI_PL022_SSPITOP_RXDMABREQ_POS     10
+#define SPI_PL022_SSPITOP_RXDMABREQ_MSK     (0x1ul<<SPI_PL022_SSPITOP_RXDMABREQ_POS)
+
+#define SPI_PL022_SSPITOP_RXDMASREQ_POS     11
+#define SPI_PL022_SSPITOP_RXDMASREQ_MSK     (0x1ul<<SPI_PL022_SSPITOP_RXDMASREQ_POS)
+
+#define SPI_PL022_SSPITOP_TXDMABREQ_POS     12
+#define SPI_PL022_SSPITOP_TXDMABREQ_MSK     (0x1ul<<SPI_PL022_SSPITOP_TXDMABREQ_POS)
+
+#define SPI_PL022_SSPITOP_TXDMASREQ_POS     13
+#define SPI_PL022_SSPITOP_TXDMASREQ_MSK     (0x1ul<<SPI_PL022_SSPITOP_TXDMASREQ_POS)
+
+/************************* PL022 Definitions End ******************************/
+
+
+/*
+ * \brief Calculates clock prescale divisor and sets serial clock rate
+ *        for the SPI PL022 device.
+ *
+ * \param[in] ctrl_cfg  SPI control configuration \ref spi_pl022_ctrl_cfg_t
+ * \param[in] sys_clk   System clock.
+ * \param[in/out] cr0   Pointer to PL022 control register 0
+ *                                             \ref spi_pl022_dev_reg_map_t
+ *
+ * \return Value of the SSPCPSR register \ref spi_pl022_dev_reg_map_t
+ *
+ * \note This function doesn't check if sys_clk or ctrl_cfg->bit_rate is 0
+ */
+static uint32_t spi_calc_clock_rate(
+                            const struct spi_pl022_ctrl_cfg_t* ctrl_cfg,
+                            uint32_t sys_clk, volatile uint32_t *cr0)
+{
+    uint32_t clkps_dvsr;  /* clock prescale divisor */
+    uint32_t scr;         /* serial clock rate */
+
+    for(clkps_dvsr = SPI_PL022_MIN_SSPCPSR_VALUE;
+        clkps_dvsr <= SPI_PL022_MAX_SSPCPSR_VALUE; clkps_dvsr += 2) {
+
+        /* Calculate clock rate based on the new clock prescale divisor */
+        scr = (sys_clk / (clkps_dvsr * ctrl_cfg->bit_rate)) - 1;
+
+        /* Checks if it can be supported by the divider */
+        if (scr <= SPI_PL022_MAX_SCR_VALUE) {
+            *cr0 &= ~SPI_PL022_SSPCR0_SCR_MSK;
+            *cr0 |= (scr << SPI_PL022_SSPCR0_SCR_POS);
+            return clkps_dvsr;
+        }
+    }
+
+    /* no good value was found */
+    *cr0 &= ~SPI_PL022_SSPCR0_SCR_MSK;
+    return SPI_PL022_INVALID_SSPCPSR_VALUE;
+}
+
+void spi_pl022_dev_enable(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                              (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    p_spi->sspcr1 |= SPI_PL022_SSPCR1_SSE_MSK;
+}
+
+void spi_pl022_dev_disable(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                              (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    p_spi->sspcr1 &= ~SPI_PL022_SSPCR1_SSE_MSK;
+}
+
+uint32_t spi_pl022_get_status(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    return p_spi->sspsr;
+}
+
+/*
+ * \brief Configures the SPI PL022 device.
+ *
+ * \param[in] spi_dev   Pointer to SPI memory map \ref spi_pl022_dev_reg_map_t
+ * \param[in] ctrl_cfg  SPI control configuration \ref spi_pl022_ctrl_cfg_t
+ * \param[in] sys_clk   System clock.
+ *
+ * \return Error code from \ref spi_pl022_error_t
+ */
+static enum spi_pl022_error_t spi_set_configuration(
+                                    struct spi_pl022_dev_reg_map_t* spi_dev,
+                                    const struct spi_pl022_ctrl_cfg_t* ctrl_cfg,
+                                    uint32_t sys_clk)
+{
+    uint32_t tmp_cr0, tmp_cr1;
+    uint32_t clk_dvsr;
+
+    if(!sys_clk || !ctrl_cfg->bit_rate) {
+        return SPI_PL022_ERR_INVALID_ARGS;
+    }
+
+    /* Word size */
+    tmp_cr0 = ((ctrl_cfg->word_size -1) << SPI_PL022_SSPCR0_DSS_POS)
+              & SPI_PL022_SSPCR0_DSS_MSK;
+
+    /* Frame format is stored in the least 2 bits*/
+    switch(ctrl_cfg->frame_format & 0x3ul)
+    {
+    case SPI_PL022_CFG_FRF_MOT:
+        tmp_cr0 |= (SPI_PL022_SSPCR0_FRF_MOT_SPI << SPI_PL022_SSPCR0_FRF_POS)
+                   & SPI_PL022_SSPCR0_FRF_MSK;
+        /* Add motorola phase & polarity */
+        tmp_cr0 |= (SPI_PL022_SSPCR0_SPO_MSK & SPI_PL022_SSPCR0_SPH_MSK);
+        break;
+    case SPI_PL022_CFG_FRF_TI:
+        tmp_cr0 |= (SPI_PL022_SSPCR0_FRF_TI_SS << SPI_PL022_SSPCR0_FRF_POS)
+                   & SPI_PL022_SSPCR0_FRF_MSK;
+        break;
+    case SPI_PL022_CFG_FRF_MICROWIRE:
+        tmp_cr0 |= (SPI_PL022_SSPCR0_FRF_MICROWIRE << SPI_PL022_SSPCR0_FRF_POS)
+                   & SPI_PL022_SSPCR0_FRF_MSK;
+        break;
+    default:
+        return SPI_PL022_ERR_BAD_CONFIG;
+        /* break; */
+    }
+
+    /* Clock logic */
+    clk_dvsr = spi_calc_clock_rate(ctrl_cfg, sys_clk, &tmp_cr0);
+
+    if (SPI_PL022_INVALID_SSPCPSR_VALUE == clk_dvsr) {
+        return SPI_PL022_ERR_BAD_CONFIG;
+    }
+
+    /* Enable device and set configured mode */
+    tmp_cr1 = (0x1 << SPI_PL022_SSPCR1_SSE_POS) & SPI_PL022_SSPCR1_SSE_MSK;
+    tmp_cr1 |= ((ctrl_cfg->spi_mode << SPI_PL022_SSPCR1_MS_POS)
+                                                    & SPI_PL022_SSPCR1_MS_MSK);
+
+
+    /* Start initialization by disabling the device */
+    spi_dev->sspcr1 = 0;
+
+    /* Set the value received for the configuration */
+    spi_dev->sspcpsr = clk_dvsr;
+    spi_dev->sspcr0  = tmp_cr0;
+
+    /* Default setup hard coded */
+    spi_dev->sspimsc  = 0;
+    spi_dev->sspdmacr = 0;
+    spi_dev->sspicr = (SPI_PL022_SSPICR_RORIC_MSK | SPI_PL022_SSPICR_RTIC_MSK);
+
+    spi_dev->sspcr1 = tmp_cr1;
+
+    return SPI_PL022_ERR_NONE;
+}
+
+enum spi_pl022_error_t spi_pl022_init(struct spi_pl022_dev_t* dev,
+                                      uint32_t sys_clk)
+{
+    enum spi_pl022_error_t ret;
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    ret = spi_set_configuration(p_spi, &dev->cfg->default_ctrl_cfg, sys_clk);
+
+    if(ret != SPI_PL022_ERR_NONE) {
+        return ret;
+    }
+
+    dev->data->sys_clk = sys_clk;
+
+    /* Initilizes current SPI control configuration */
+    memcpy(&dev->data->ctrl_cfg, &dev->cfg->default_ctrl_cfg,
+           sizeof(struct spi_pl022_ctrl_cfg_t));
+
+    dev->data->state = SPI_PL022_INITIALIZED;
+
+    return ret;
+}
+
+enum spi_pl022_error_t spi_pl022_set_ctrl_cfg(struct spi_pl022_dev_t* dev,
+                                    const struct spi_pl022_ctrl_cfg_t* ctrl_cfg)
+{
+    enum spi_pl022_error_t ret;
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    if(!(dev->data->state & SPI_PL022_INITIALIZED)) {
+        return SPI_PL022_ERR_NOT_INIT;
+    }
+
+    if(ctrl_cfg == NULL) {
+        return SPI_PL022_ERR_INVALID_ARGS;
+    }
+
+    ret = spi_set_configuration(p_spi, ctrl_cfg, dev->data->sys_clk);
+
+    if(ret != SPI_PL022_ERR_NONE) {
+        return ret;
+    }
+
+    /* Updates current SPI control configuration */
+    memcpy(&dev->data->ctrl_cfg, ctrl_cfg,
+           sizeof(struct spi_pl022_ctrl_cfg_t));
+
+    return SPI_PL022_ERR_NONE;
+}
+
+enum spi_pl022_error_t spi_pl022_get_ctrl_cfg(struct spi_pl022_dev_t* dev,
+                                          struct spi_pl022_ctrl_cfg_t* ctrl_cfg)
+{
+    if(!(dev->data->state & SPI_PL022_INITIALIZED)) {
+        return SPI_PL022_ERR_NOT_INIT;
+    }
+
+    if(ctrl_cfg == NULL) {
+        return SPI_PL022_ERR_INVALID_ARGS;
+    }
+
+    /* Copy current SPI control configuration */
+    memcpy(ctrl_cfg, &dev->data->ctrl_cfg,
+           sizeof(struct spi_pl022_ctrl_cfg_t));
+
+    return SPI_PL022_ERR_NONE;
+}
+
+void spi_pl022_select_mode(struct spi_pl022_dev_t* dev,
+                           enum spi_pl022_mode_select_t mode)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                             (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+
+    /* Disable device */
+    p_spi->sspcr1 &= ~SPI_PL022_SSPCR1_SSE_MSK;
+    /* Set mode */
+    p_spi->sspcr1 = (p_spi->sspcr1 & ~SPI_PL022_SSPCR1_MS_MSK)
+                                           | (mode << SPI_PL022_SSPCR1_MS_POS);
+    dev->data->ctrl_cfg.spi_mode = mode;
+    /* Re-enable device */
+    p_spi->sspcr1 |= SPI_PL022_SSPCR1_SSE_MSK;
+}
+
+void spi_pl022_set_slave_output(struct spi_pl022_dev_t* dev,
+                                enum spi_pl022_slave_output_mode_t mode)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    p_spi->sspcr1 = (p_spi->sspcr1 & ~SPI_PL022_SSPCR1_SOD_MSK)
+                                          | (mode << SPI_PL022_SSPCR1_SOD_POS);
+}
+
+void spi_pl022_set_loopback_mode(struct spi_pl022_dev_t* dev,
+                                 enum spi_pl022_loopback_select_t mode)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    p_spi->sspcr1 = (p_spi->sspcr1 & ~SPI_PL022_SSPCR1_LBM_MSK)
+                                          | (mode << SPI_PL022_SSPCR1_LBM_POS);
+}
+
+void spi_pl022_enable_interrupt(struct spi_pl022_dev_t* dev,
+                                uint32_t irq_mask)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                              (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    p_spi->sspimsc |= (irq_mask & SPI_PL022_SSPIMSC_VALID_MSK);
+}
+
+void spi_pl022_disable_interrupt(struct spi_pl022_dev_t* dev,
+                                 uint32_t irq_mask)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                              (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    p_spi->sspimsc &= ~(irq_mask & SPI_PL022_SSPIMSC_VALID_MSK);
+}
+
+uint32_t spi_pl022_get_raw_irq_status(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                              (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    return (p_spi->sspris & SPI_PL022_SSPRIS_VALID_MSK);
+}
+
+uint32_t spi_pl022_get_masked_irq_status(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                              (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    return (p_spi->sspmis & SPI_PL022_SSPMIS_VALID_MSK);
+}
+
+void spi_pl022_clear_interrupt(struct spi_pl022_dev_t* dev,
+                               uint32_t irq_mask)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                              (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    p_spi->sspicr = (irq_mask & SPI_PL022_SSPICR_VALID_MSK);
+}
+
+void spi_pl022_dma_mode_enable(struct spi_pl022_dev_t* dev,
+                               uint32_t dma)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    p_spi->sspdmacr |= (dma & SPI_PL022_SSPDMACR_VALID_MSK);
+}
+
+void spi_pl022_dma_mode_disable(struct spi_pl022_dev_t* dev,
+                                uint32_t dma)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    p_spi->sspdmacr &= ~(dma & SPI_PL022_SSPDMACR_VALID_MSK);
+}
+
+void spi_pl022_get_periphID(struct spi_pl022_dev_t* dev,
+                            struct spi_pl022_periphid_t* periphid)
+{
+    uint32_t tempid, tempid2;
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                                   (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    tempid = p_spi->sspperiphid0 & SPI_PL022_SSPPERIPH_ID0_PARTNO_0_MSK;
+    tempid2 = (p_spi->sspperiphid1 & SPI_PL022_SSPPERIPH_ID1_PARTNO_1_MSK)
+                                    << SPI_PL022_SSPPERIPH_ID0_PARTNO_0_SIZE;
+    periphid->partNumber = tempid | tempid2;
+
+    tempid =  (p_spi->sspperiphid1 & SPI_PL022_SSPPERIPH_ID1_DESIGNER_0_MSK)
+                                    >> SPI_PL022_SSPPERIPH_ID1_DESIGNER_0_POS;
+    tempid2 = (p_spi->sspperiphid2 & SPI_PL022_SSPPERIPH_ID2_DESIGNER_1_MSK)
+                                    << SPI_PL022_SSPPERIPH_ID1_DESIGNER_0_SIZE;
+    periphid->designerID = tempid | tempid2;
+
+    tempid = (p_spi->sspperiphid2 & SPI_PL022_SSPPERIPH_ID2_REVIISON_MSK)
+                                    >> SPI_PL022_SSPPERIPH_ID2_REVISION_SIZE;
+    periphid->revision = tempid;
+
+    tempid = p_spi->sspperiphid3 & SPI_PL022_SSPPERIPH_ID3_CONFIG_MSK;
+    periphid->configuration = tempid;
+}
+
+void spi_pl022_get_PrimeCell_ID(struct spi_pl022_dev_t* dev,
+                          struct spi_pl022_primecell_id_t* cellid)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                                   (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    cellid->cellid0 = (uint8_t) p_spi->ssppcellid0;
+    cellid->cellid1 = (uint8_t) p_spi->ssppcellid1;
+    cellid->cellid2 = (uint8_t) p_spi->ssppcellid2;
+    cellid->cellid3 = (uint8_t) p_spi->ssppcellid3;
+}
+
+enum spi_pl022_error_t spi_pl022_set_sys_clk(struct spi_pl022_dev_t* dev,
+                                             uint32_t sys_clk)
+{
+    uint32_t clk_dvsr;
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    if(!(dev->data->state & SPI_PL022_INITIALIZED)) {
+        return SPI_PL022_ERR_NOT_INIT;
+    }
+
+    if(!sys_clk) {
+        return SPI_PL022_ERR_INVALID_ARGS;
+    }
+
+    clk_dvsr = spi_calc_clock_rate(&dev->data->ctrl_cfg, sys_clk, &p_spi->sspcr0);
+
+    if(SPI_PL022_INVALID_SSPCPSR_VALUE == clk_dvsr) {
+        return SPI_PL022_ERR_BAD_CONFIG;
+    }
+
+    p_spi->sspcpsr = clk_dvsr;
+    dev->data->sys_clk = sys_clk;
+
+    return SPI_PL022_ERR_NONE;
+}
+
+enum spi_pl022_error_t spi_pl022_read(struct spi_pl022_dev_t* dev,
+                                      void *rx_ptr)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    if(p_spi->sspsr & SPI_PL022_SSPSR_RNE_MSK) {
+        if(dev->data->ctrl_cfg.word_size <= 8) {
+            *(uint8_t*)rx_ptr = p_spi->sspdr & WORD_1BYTE_MASK;
+        } else {
+            *(uint16_t*)rx_ptr = p_spi->sspdr & WORD_2BYTES_MASK;
+        }
+        return SPI_PL022_ERR_NONE;
+    }
+    return SPI_PL022_ERR_NO_RX;
+}
+
+uint32_t spi_pl022_slave_read(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+    uint32_t data;
+
+    if(dev->data->ctrl_cfg.word_size <= 8) {
+        data = p_spi->sspdr & WORD_1BYTE_MASK;
+    } else {
+        data = p_spi->sspdr & WORD_2BYTES_MASK;
+    }
+    return data;
+}
+
+enum spi_pl022_error_t spi_pl022_write(struct spi_pl022_dev_t* dev,
+                                       const enum spi_pl022_mode_select_t mode,
+                                       const void *tx_ptr)
+{
+   struct spi_pl022_dev_reg_map_t* p_spi =
+                               (struct spi_pl022_dev_reg_map_t*) dev->cfg->base;
+
+    if(p_spi->sspsr & SPI_PL022_SSPSR_TNF_MSK){
+        if(dev->data->ctrl_cfg.word_size <= 8) {
+            p_spi->sspdr = *(const uint8_t*)tx_ptr;
+        } else {
+            p_spi->sspdr = *(const uint16_t*)tx_ptr;
+        }
+        /* Wait for write to go through */
+        if (mode == SPI_PL022_MASTER_SELECT) {
+            while(p_spi->sspsr & SPI_PL022_SSPSR_BSY_MSK) {};
+        }
+        return SPI_PL022_ERR_NONE;
+    }
+    return SPI_PL022_ERR_NO_TX;
+}
+
+enum spi_pl022_error_t spi_pl022_txrx_blocking(struct spi_pl022_dev_t* dev,
+                                               const void *tx_ptr,
+                                               uint32_t *tx_len_ptr,
+                                               void *rx_ptr,
+                                               uint32_t *rx_len_ptr)
+{
+    uint32_t i;
+    enum spi_pl022_error_t retval = SPI_PL022_ERR_NONE;
+    uint8_t word_size = 1;
+    uint32_t rx_data, tx_data, total_len;
+
+    if(dev->data->ctrl_cfg.word_size > 8) {
+        word_size = 2;
+        /* return error if sizes are not word_size aligned */
+        if ((*tx_len_ptr & 0x1) || (*rx_len_ptr & 0x1)) {
+            return SPI_PL022_ERR_INVALID_ARGS;
+        }
+    }
+
+    total_len = (*tx_len_ptr > *rx_len_ptr) ? *tx_len_ptr : *rx_len_ptr;
+
+    for(i=0;i<total_len;i+=word_size){
+        if (i<*tx_len_ptr) {
+            tx_data = *(const uint16_t*)tx_ptr;
+        } else {
+            /* send FF if there is no more valid data to send */
+            tx_data = 0xFFFF;
+        }
+        retval = spi_pl022_write(dev, dev->data->ctrl_cfg.spi_mode, &tx_data);
+        if(retval != SPI_PL022_ERR_NONE) {
+            *tx_len_ptr = i;
+            *rx_len_ptr = i;
+            break;
+        }
+        if(i < *tx_len_ptr) {
+            tx_ptr = (const uint8_t*)tx_ptr + word_size;
+        }
+        retval = spi_pl022_read(dev, &rx_data);
+        if(retval != SPI_PL022_ERR_NONE) {
+            /* send went through, align tx_len to the updated tx_ptr */
+            *tx_len_ptr = i + word_size;
+            /* don't update rx_len if there is an overflow */
+            if (i < *rx_len_ptr) {
+                *rx_len_ptr = i;
+            }
+            break;
+        }
+        /* do not overflow rx buffer */
+        if(i<*rx_len_ptr) {
+            if (word_size == 1) {
+                *(uint8_t*)rx_ptr = (uint8_t) rx_data;
+            } else {
+                *(uint16_t*)rx_ptr = (uint16_t) rx_data;
+            }
+            rx_ptr = (uint8_t*)rx_ptr + word_size;
+        }
+    }
+
+    return retval;
+}
+
+/*
+ * TEST APIs
+ */
+void spi_pl022_test_fifo_enable(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_test_reg_map_t* p_spi =
+                 (struct spi_pl022_dev_test_reg_map_t*)
+                                    (dev->cfg->base + SPI_PL022_TEST_REG_BASE);
+
+    p_spi->ssptcr |= SPI_PL022_SSPTCR_TESTFIFO_MSK;
+}
+
+void spi_pl022_test_fifo_disable(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_test_reg_map_t* p_spi =
+                 (struct spi_pl022_dev_test_reg_map_t*)
+                                    (dev->cfg->base + SPI_PL022_TEST_REG_BASE);
+
+    p_spi->ssptcr &= ~SPI_PL022_SSPTCR_TESTFIFO_MSK;
+}
+
+void spi_pl022_integration_test_enable(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_test_reg_map_t* p_spi =
+                 (struct spi_pl022_dev_test_reg_map_t*)
+                                    (dev->cfg->base + SPI_PL022_TEST_REG_BASE);
+
+    p_spi->ssptcr |= SPI_PL022_SSPTCR_ITEN_MSK;
+}
+
+void spi_pl022_integration_test_disable(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_test_reg_map_t* p_spi =
+                 (struct spi_pl022_dev_test_reg_map_t*)
+                                    (dev->cfg->base + SPI_PL022_TEST_REG_BASE);
+
+    p_spi->ssptcr &= ~SPI_PL022_SSPTCR_ITEN_MSK;
+}
+
+
+void spi_pl022_write_test_data(struct spi_pl022_dev_t* dev,
+                                                    void *tx_ptr)
+{
+    struct spi_pl022_dev_test_reg_map_t* p_spi =
+                 (struct spi_pl022_dev_test_reg_map_t*)
+                                    (dev->cfg->base + SPI_PL022_TEST_REG_BASE);
+
+    if(dev->data->ctrl_cfg.word_size <= 8) {
+        p_spi->ssptdr = *(const uint8_t*)tx_ptr;
+    } else {
+        p_spi->ssptdr = *(const uint16_t*)tx_ptr;
+    }
+}
+
+uint32_t spi_pl022_read_test_output_reg(struct spi_pl022_dev_t* dev)
+{
+    struct spi_pl022_dev_test_reg_map_t* p_spi =
+                 (struct spi_pl022_dev_test_reg_map_t*)
+                                    (dev->cfg->base + SPI_PL022_TEST_REG_BASE);
+
+    return p_spi->sspitop;
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/spi_pl022_drv.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,501 @@
+/*
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file spi_pl022_drv.h
+ * \brief Generic driver for ARM SPI PL022.
+ */
+
+#ifndef __SPI_PL022_DRV_H__
+#define __SPI_PL022_DRV_H__
+
+#include <stdint.h>
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Frame format */
+#define SPI_PL022_CFG_FRF_MOT         0
+#define SPI_PL022_CFG_FRF_TI          1
+#define SPI_PL022_CFG_FRF_MICROWIRE   2
+
+enum spi_pl022_mode_select_t {
+    SPI_PL022_MASTER_SELECT = 0,
+    SPI_PL022_SLAVE_SELECT,
+};
+
+enum spi_pl022_slave_output_mode_t {
+    SPI_PL022_SLAVE_OUTPUT_EN = 0,
+    SPI_PL022_SLAVE_OUTPUT_DIS,
+};
+
+enum spi_pl022_loopback_select_t {
+    SPI_PL022_LOOPBACK_MODE_DIS = 0,
+    SPI_PL022_LOOPBACK_MODE_EN,
+};
+
+struct spi_pl022_periphid_t {
+    uint32_t partNumber;
+    uint32_t designerID;
+    uint32_t revision;
+    uint32_t configuration;
+};
+
+struct spi_pl022_primecell_id_t {
+    uint8_t cellid0;
+    uint8_t cellid1;
+    uint8_t cellid2;
+    uint8_t cellid3;
+};
+
+/* ARM SPI PL022 device control configuration structure */
+struct spi_pl022_ctrl_cfg_t {
+    enum spi_pl022_mode_select_t spi_mode;  /*!< master-slave */
+    uint8_t frame_format;                   /*!< frame format bitmap
+                                                 clock phase [7] polarity [6]
+                                                 reserved [5:3]
+                                                 frame_format [1:0] */
+    uint8_t word_size;                      /*!< value 4 to 16 */
+    uint8_t reserved[2];                    /*!< to keep 32 bits aligned */
+    uint32_t bit_rate;                      /*!< required bit rate */
+};
+
+/* ARM SPI PL022 device configuration structure */
+struct spi_pl022_dev_cfg_t {
+    const uint32_t base;  /*!< SPI PL022 base address */
+    const struct spi_pl022_ctrl_cfg_t default_ctrl_cfg; /*!< Default SPI
+                                                             configuration */
+};
+
+/* ARM SPI PL022 device data structure */
+struct spi_pl022_dev_data_t {
+    uint32_t state;                        /*!< SPI driver state */
+    uint32_t sys_clk;                      /*!< System clock frequency */
+    struct spi_pl022_ctrl_cfg_t ctrl_cfg;  /*!< SPI control
+                                                configuration data */
+};
+
+/* ARM SPI PL022 device structure */
+struct spi_pl022_dev_t {
+    const struct spi_pl022_dev_cfg_t* const cfg;  /*!< SPI driver
+                                                       configuration */
+    struct spi_pl022_dev_data_t* const data;      /*!< SPI driver data */
+};
+
+enum spi_pl022_error_t {
+    SPI_PL022_ERR_NONE = 0,      /*!< No error */
+    SPI_PL022_ERR_INVALID_ARGS,  /*!< Invalid input arguments */
+    SPI_PL022_ERR_NOT_INIT,      /*!< SPI driver is not initialized */
+    SPI_PL022_ERR_NO_TX,         /*!< SPI transm FIFO full */
+    SPI_PL022_ERR_NO_RX,         /*!< SPI receive FIFO empty */
+    SPI_PL022_ERR_BAD_CONFIG,    /*!< Bad SPI configuration */
+};
+
+
+/* Interrupt mask defines for the interrupt APIs */
+
+/* Receive Overrun Interrupt */
+#define SPI_PL022_RX_OR_INTR_POS        0
+#define SPI_PL022_RX_OR_INTR_MSK        (0x1ul<<SPI_PL022_RX_OR_INTR_POS)
+
+/* Receive Timeout Interrupt */
+#define SPI_PL022_RX_TO_INTR_POS        1
+#define SPI_PL022_RX_TO_INTR_MSK        (0x1ul<<SPI_PL022_RX_TO_INTR_POS)
+
+/* Receive FIFO Interrupt */
+#define SPI_PL022_RX_FIFO_INTR_POS      2
+#define SPI_PL022_RX_FIFO_INTR_MSK      (0x1ul<<SPI_PL022_RX_FIFO_INTR_POS)
+
+/* Transmit FIFO Interrupt */
+#define SPI_PL022_TX_FIFO_INTR_POS      3
+#define SPI_PL022_TX_FIFO_INTR_MSK      (0x1ul<<SPI_PL022_TX_FIFO_INTR_POS)
+
+#define SPI_PL022_ALL_INTR_MSK          \
+                                ((0x1ul<<(SPI_PL022_TX_FIFO_INTR_POS+1))-1)
+
+/* Status register bit defines */
+
+/* Transmit FIFO empty */
+#define SPI_PL022_SSPSR_TFE_POS         0
+#define SPI_PL022_SSPSR_TFE_MSK         (0x1ul<<SPI_PL022_SSPSR_TFE_POS)
+
+/* Transmit FIFO not full */
+#define SPI_PL022_SSPSR_TNF_POS         1
+#define SPI_PL022_SSPSR_TNF_MSK         (0x1ul<<SPI_PL022_SSPSR_TNF_POS)
+
+/* Receive FIFO not empty */
+#define SPI_PL022_SSPSR_RNE_POS         2
+#define SPI_PL022_SSPSR_RNE_MSK         (0x1ul<<SPI_PL022_SSPSR_RNE_POS)
+
+/* Receive FIFO full */
+#define SPI_PL022_SSPSR_RFF_POS         3
+#define SPI_PL022_SSPSR_RFF_MSK         (0x1ul<<SPI_PL022_SSPSR_RFF_POS)
+
+/* Busy either tx/rx or transmit fifo not empty */
+#define SPI_PL022_SSPSR_BSY_POS         4
+#define SPI_PL022_SSPSR_BSY_MSK         (0x1ul<<SPI_PL022_SSPSR_BSY_POS)
+
+/**
+ * \brief Enables PL022 SPI device
+ *
+ * \param[in] dev      SPI device structure \ref spi_pl022_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void spi_pl022_dev_enable(struct spi_pl022_dev_t* dev);
+
+/**
+ * \brief Disables PL022 SPI device
+ *
+ * \param[in] dev      SPI device structure \ref spi_pl022_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void spi_pl022_dev_disable(struct spi_pl022_dev_t* dev);
+
+/**
+ * \brief Returns SPI status register
+ *
+ * \param[in] dev      SPI device structure \ref spi_pl022_dev_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+uint32_t spi_pl022_get_status(struct spi_pl022_dev_t* dev);
+
+/**
+ * \brief Initializes the SPI PL022 device.
+ *
+ * \param[in] dev      SPI device structure \ref spi_pl022_dev_t
+ * \param[in] sys_clk  System clock.
+ *
+ * \return Error code from \ref spi_pl022_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum spi_pl022_error_t spi_pl022_init(struct spi_pl022_dev_t* dev,
+                                      uint32_t sys_clk);
+
+/**
+ * \brief Sets the SPI PL022 device configuration.
+ *
+ * \param[in] dev       SPI device structure \ref spi_pl022_dev_t
+ * \param[in] ctrl_cfg  SPI control configuration.
+ *
+ * \return  Error code from \ref spi_pl022_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum spi_pl022_error_t spi_pl022_set_ctrl_cfg(struct spi_pl022_dev_t* dev,
+                                   const struct spi_pl022_ctrl_cfg_t* ctrl_cfg);
+
+/**
+ * \brief Gets the SPI PL022 device configuration.
+ *
+ * \param[in]  dev       SPI device structure \ref spi_pl022_dev_t
+ * \param[out] ctrl_cfg  Pointer to fill the SPI control configuration.
+ *
+ * \return  Error code from \ref spi_pl022_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum spi_pl022_error_t spi_pl022_get_ctrl_cfg(struct spi_pl022_dev_t* dev,
+                                         struct spi_pl022_ctrl_cfg_t* ctrl_cfg);
+
+
+/**
+* \brief Selects SPI PL022 device as Master or Slave
+*
+* \param[in]  dev       SPI device structure \ref spi_pl022_dev_t
+* \param[in]  mode      Mode selection \ref spi_pl022_mode_select_t
+*
+* \note This function doesn't check if dev is NULL.
+*/
+void spi_pl022_select_mode(struct spi_pl022_dev_t* dev,
+                           enum spi_pl022_mode_select_t mode);
+
+/**
+* \brief Enables/disables SPI PL022 Slave device output
+*
+* \param[in]  dev       SPI device structure \ref spi_pl022_dev_t
+* \param[in]  mode      Mode selection \ref spi_pl022_slave_output_mode_t
+*
+* \note This function doesn't check if dev is NULL.
+* \note This function doesn't check if dev is Slave or Master
+*/
+void spi_pl022_set_slave_output(struct spi_pl022_dev_t* dev,
+                                enum spi_pl022_slave_output_mode_t mode);
+
+/**
+* \brief Enables SPI PL022 device in loopback mode
+*
+* \param[in]  dev       SPI device structure \ref spi_pl022_dev_t
+* \param[in]  mode      Mode selection \ref spi_pl022_loopback_select_t
+*
+* \note This function doesn't check if dev is NULL.
+*/
+void spi_pl022_set_loopback_mode(struct spi_pl022_dev_t* dev,
+                                 enum spi_pl022_loopback_select_t mode);
+
+/**
+* \brief Clears interrupt mask of SPI PL022
+*
+* \param[in]  dev           SPI device structure \ref spi_pl022_dev_t
+* \param[in]  irq_mask      Selection of interrupts to enable
+*
+* \note This function doesn't check if dev is NULL.
+*/
+void spi_pl022_enable_interrupt(struct spi_pl022_dev_t* dev,
+                                uint32_t irq_mask);
+
+/**
+* \brief Sets interrupt mask of SPI PL022
+*
+* \param[in]  dev           SPI device structure \ref spi_pl022_dev_t
+* \param[in]  irq_mask      Selection of interrupts to disable
+*
+* \note This function doesn't check if dev is NULL.
+*/
+void spi_pl022_disable_interrupt(struct spi_pl022_dev_t* dev,
+                                 uint32_t irq_mask);
+
+/**
+* \brief Gets raw interrupt status of SPI PL022
+*
+* \param[in]  dev           SPI device structure \ref spi_pl022_dev_t
+*
+* \return  Returns raw interrupt status value
+*
+* \note This function doesn't check if dev is NULL.
+*/
+uint32_t spi_pl022_get_raw_irq_status(struct spi_pl022_dev_t* dev);
+
+/**
+* \brief Gets masked interrupt status of SPI PL022
+*
+* \param[in]  dev           SPI device structure \ref spi_pl022_dev_t
+*
+* \return  Returns masked interrupt status value
+*
+* \note This function doesn't check if dev is NULL.
+*/
+uint32_t spi_pl022_get_masked_irq_status(struct spi_pl022_dev_t* dev);
+
+/**
+* \brief Sets interrupt mask of SPI PL022
+*
+* \param[in]  dev           SPI device structure \ref spi_pl022_dev_t
+* \param[in]  irq_mask      Selection of interrupts to disable
+*
+* \note This function doesn't check if dev is NULL.
+*/
+void spi_pl022_clear_interrupt(struct spi_pl022_dev_t* dev,
+                               uint32_t irq_mask);
+
+/**
+* \brief Enables transmit or receive DMA
+*
+* \param[in]  dev           SPI device structure \ref spi_pl022_dev_t
+* \param[in]  dma           Selects the DMA to be enabled
+*                           - bit position 0 - Receive DMA
+*                           - bit position 1 - Transmit DMA
+*
+* \note This function doesn't check if dev is NULL.
+*/
+void spi_pl022_dma_mode_enable(struct spi_pl022_dev_t* dev,
+                               uint32_t dma);
+
+/**
+* \brief Disables transmit or receive DMA
+*
+* \param[in]  dev           SPI device structure \ref spi_pl022_dev_t
+* \param[in]  dma           Selects the DMA to be disabled
+*                           - bit position 0 - Receive DMA
+*                           - bit position 1 - Transmit DMA
+*
+* \note This function doesn't check if dev is NULL.
+*/
+void spi_pl022_dma_mode_disable(struct spi_pl022_dev_t* dev,
+                                uint32_t dma);
+
+/**
+ * \brief Gets peripheral identification of the device
+ *
+ * \param[in]  dev        SPI device structure \ref spi_pl022_dev_t
+ * \param[out] periphid   Pointer to fill peripheral ids
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void spi_pl022_get_periphID(struct spi_pl022_dev_t* dev,
+                            struct spi_pl022_periphid_t* periphid);
+
+/**
+ * \brief Gets PrimeCell identification of the device
+ *
+ * \param[in]  dev      SPI device structure \ref spi_pl022_dev_t
+ * \param[out] cellid   Pointer to fill PrimeCell ids
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+void spi_pl022_get_PrimeCell_ID(struct spi_pl022_dev_t* dev,
+                                struct spi_pl022_primecell_id_t* cellid);
+
+/**
+ * \brief Sets system clock.
+ *
+ * \param[in] dev      SPI device structure \ref spi_pl022_dev_t
+ * \param[in] sys_clk  System clock.
+ *
+ * \return  Error code from \ref spi_pl022_error_t
+ *
+ * \note This function doesn't check if dev is NULL.
+ */
+enum spi_pl022_error_t spi_pl022_set_sys_clk(struct spi_pl022_dev_t* dev,
+                                             uint32_t sys_clk);
+
+/**
+ * \brief Reads single data from SPI. Non blocking.
+ *
+ * \param[in]  dev      SPI device structure \ref spi_pl022_dev_t
+ * \param[out] rx_ptr   Buffer pointer to be filled
+ *                      must be enough for configured word size
+ *
+ * \return  Error code from \ref spi_pl022_error_t
+ *
+ * \note This function doesn't check if dev is NULL and
+ * if the driver is initialized to reduce the number of checks and
+ * make the function execution faster.
+ */
+enum spi_pl022_error_t spi_pl022_read(struct spi_pl022_dev_t* dev,
+                                      void *rx_ptr);
+
+/**
+ * \brief Reads single data from slave SPI. Non blocking.
+ *
+ * \param[in]  dev      SPI device structure \ref spi_pl022_dev_t
+ *
+ * \return  Returns data value from the device
+ *
+ * \note This function doesn't check if dev is NULL and
+ * does not validate whether there is any data in the RX buffer
+ */
+uint32_t spi_pl022_slave_read(struct spi_pl022_dev_t* dev);
+
+/**
+ * \brief  Writes single data to SPI. Non blocking.
+ *
+ * \param[in]  dev      SPI device structure \ref spi_pl022_dev_t
+ * \param[in]  mode     Master or slave \ref spi_pl022_mode_select_t
+ * \param[out] tx_ptr   Pointer to the data to be sent
+ *
+ * \return  Error code from \ref spi_pl022_error_t
+ *
+ * \note This function doesn't check if dev is NULL and
+ * if the driver is initialized to reduce the number of checks and
+ * make the function execution faster.
+ */
+enum spi_pl022_error_t spi_pl022_write(struct spi_pl022_dev_t* dev,
+                                       const enum spi_pl022_mode_select_t mode,
+                                       const void *tx_ptr);
+
+/**
+ * \brief  Transmit and Receive data on SPI in a blocking call
+ *
+ * \param[in]     dev         SPI device structure \ref spi_pl022_dev_t
+ * \param[in]     tx_ptr      Buffer pointer to be filled
+ * \param[in/out] tx_len_ptr  Num values to transfer (updated on error)
+ *                            need to be multiples of transfer word length
+ * \param[out]    rx_ptr      Buffer pointer to be filled
+ * \param[in/out] rx_len_ptr  Num values to receive (updated on error)
+ *                            need to be multiples of transfer word length
+ *
+ * \return  Error code from \ref spi_pl022_error_t
+ *
+ * \note This function doesn't check if dev is NULL and
+ * if the driver is initialized to reduce the number of checks and
+ * make the function execution faster.
+ */
+enum spi_pl022_error_t spi_pl022_txrx_blocking(struct spi_pl022_dev_t* dev,
+                                               const void *tx_ptr,
+                                               uint32_t *tx_len_ptr,
+                                               void *rx_ptr,
+                                               uint32_t *rx_len_ptr);
+
+
+/************************** TEST APIs ****************************/
+
+/**
+ * \brief  Enables Test FIFO mode
+ *
+ * \param[in]  dev      SPI device structure \ref spi_pl022_dev_t
+ *
+ * \note This function doesn't check if dev is NULL
+ */
+void spi_pl022_test_fifo_enable(struct spi_pl022_dev_t* dev);
+
+/**
+ * \brief  Disables Test FIFO mode
+ *
+ * \param[in]  dev      SPI device structure \ref spi_pl022_dev_t
+ *
+ * \note This function doesn't check if dev is NULL
+ */
+void spi_pl022_test_fifo_disable(struct spi_pl022_dev_t* dev);
+
+/**
+ * \brief  Enables Integration Test mode
+ *
+ * \param[in]  dev      SPI device structure \ref spi_pl022_dev_t
+ *
+ * \note This function doesn't check if dev is NULL
+ */
+void spi_pl022_integration_test_enable(struct spi_pl022_dev_t* dev);
+
+/**
+ * \brief  Disables Integration Test mode
+ *
+ * \param[in]  dev      SPI device structure \ref spi_pl022_dev_t
+ *
+ * \note This function doesn't check if dev is NULL
+ */
+void spi_pl022_integration_test_disable(struct spi_pl022_dev_t* dev);
+
+
+/**
+ * \brief  Writes data to Test data register
+ *
+ * \param[in]  dev      SPI device structure \ref spi_pl022_dev_t
+ *
+ * \note This function doesn't check if dev is NULL and
+ *       whether Test FIFO mode is enabled
+ */
+void spi_pl022_write_test_data(struct spi_pl022_dev_t* dev, void *tx_ptr);
+
+/**
+ * \brief  Reads integration test output register
+ *
+ * \param[in]  dev      SPI device structure \ref spi_pl022_dev_t
+ *
+ * \note This function doesn't check if dev is NULL
+ */
+uint32_t spi_pl022_read_test_output_reg(struct spi_pl022_dev_t* dev);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __SPI_PL022_DRV_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/timer_cmsdk/timer_cmsdk_drv.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file timer_cmsdk_drv.c
+ * \brief Generic driver for CMSDK APB Timers.
+ *        The timer is a 32-bit down-counter with the following features:
+ *        - optional programmable external clock source
+ *        - programmable interrupt source, triggered if counter reaches 0
+ *        - automatic reload if counter reaches 0
+ */
+
+#include "timer_cmsdk_drv.h"
+
+/** Setter bit manipulation macro */
+#define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX)))
+/** Clearing bit manipulation macro */
+#define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX)))
+/** Getter bit manipulation macro */
+#define GET_BIT(WORD, BIT_INDEX) (bool)(((WORD) & (1U << (BIT_INDEX))))
+
+/**
+ * \brief Timer register map structure
+ *
+ */
+struct timer_cmsdk_reg_map_t {
+    volatile uint32_t ctrl;    /* Offset: 0x000 (R/W) control register */
+    volatile uint32_t value;   /* Offset: 0x004 (R/W) current value register */
+    volatile uint32_t reload;  /* Offset: 0x008 (R/W) reload value register */
+    union {
+        volatile uint32_t intstatus;  /* Offset: 0x00C (R/ ) interrupt
+                                       * status register */
+        volatile uint32_t intclear;   /* Offset: 0x00C ( /W) interrupt
+                                       * clear register */
+    }intreg;
+};
+
+/**
+ * \brief CTRL register bit definitions
+ *
+ */
+enum ctrl_reg_bits_t{
+    CTRL_REG_ENUM_ENABLE_INDEX = 0,
+    CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX = 1,
+    CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX = 2,
+    CTRL_REG_ENUM_IRQ_ENABLE_INDEX = 3
+};
+
+/**
+ * \brief INTSTATUS/INTCLEAR register bit definitions
+ *
+ */
+enum interrupt_reg_bits_t{
+    INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX = 0
+};
+
+void timer_cmsdk_init(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+
+    if (dev->data->is_initialized == 0) {
+        register_map->ctrl = 0;
+        register_map->reload = TIMER_CMSDK_DEFAULT_RELOAD;
+        dev->data->is_initialized = 1;
+    }
+}
+
+bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev)
+{
+    return dev->data->is_initialized;
+}
+
+void timer_cmsdk_enable_external_input(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+void timer_cmsdk_disable_external_input(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+bool timer_cmsdk_is_external_input_enabled(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    return GET_BIT(register_map->ctrl,
+                   CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX);
+}
+
+void timer_cmsdk_set_clock_to_internal(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+void timer_cmsdk_set_clock_to_external(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+bool timer_cmsdk_is_clock_external(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    return GET_BIT(register_map->ctrl,
+                   CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX);
+}
+
+void timer_cmsdk_enable(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+void timer_cmsdk_disable(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+bool timer_cmsdk_is_enabled(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX);
+}
+
+void timer_cmsdk_enable_interrupt(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+void timer_cmsdk_disable_interrupt(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+bool timer_cmsdk_is_interrupt_enabled(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    return GET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX);
+}
+
+bool timer_cmsdk_is_interrupt_active(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    return GET_BIT(register_map->intreg.intstatus,
+                   INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
+}
+
+void timer_cmsdk_clear_interrupt(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    SET_BIT(register_map->intreg.intclear,
+            INTERRUPT_REG_ENUM_STATUS_AND_CLEAR_INDEX);
+}
+
+uint32_t timer_cmsdk_get_current_value(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    return register_map->value;
+}
+
+void timer_cmsdk_set_reload_value(const struct timer_cmsdk_dev_t* dev,
+                                uint32_t reload)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    register_map->reload = reload;
+}
+
+void timer_cmsdk_reset(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    register_map->value = register_map->reload;
+}
+
+uint32_t timer_cmsdk_get_reload_value(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    return register_map->reload;
+}
+
+uint32_t timer_cmsdk_get_elapsed_value(const struct timer_cmsdk_dev_t* dev)
+{
+    struct timer_cmsdk_reg_map_t* register_map =
+            (struct timer_cmsdk_reg_map_t*)dev->cfg->base;
+    return register_map->reload - register_map->value;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/timer_cmsdk/timer_cmsdk_drv.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,254 @@
+/*
+ * Copyright (c) 2016-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * \file timer_cmsdk_drv.h
+ * \brief Generic driver for CMSDK APB Timers.
+ *        The timer is a 32-bit down-counter with the following features:
+ *        - optional programmable external clock source
+ *        - programmable interrupt source, triggered if counter reaches 0
+ *        - automatic reload if counter reaches 0
+ */
+
+#ifndef __TIMER_CMSDK_DRV_H__
+#define __TIMER_CMSDK_DRV_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Maximum reload value */
+#define TIMER_CMSDK_MAX_RELOAD        UINT32_MAX /* max of 32-bit */
+#define TIMER_CMSDK_DEFAULT_RELOAD    TIMER_CMSDK_MAX_RELOAD
+
+/** CMSDK timer device configuration structure */
+struct timer_cmsdk_dev_cfg_t {
+    const uintptr_t base;  /*!< Timer base address */
+};
+
+/** CMSDK timer device data structure */
+struct timer_cmsdk_dev_data_t {
+    bool is_initialized;  /*!< Indicates if the timer is initialized */
+};
+
+/* CMSDK timer device structure */
+struct timer_cmsdk_dev_t {
+    const struct timer_cmsdk_dev_cfg_t* const cfg;  /*!< Timer configuration */
+    struct timer_cmsdk_dev_data_t* const data;      /*!< Timer data */
+};
+
+/**
+ * \brief Initializes timer to a known default state, which is:
+ *          - timer disabled
+ *          - timer interrupt disabled
+ *          - clock source set to internal
+ *          - external input disabled
+ *          - reload value maxed out
+ *        Init should be called prior to any other process and
+ *        it's the caller's responsibility to follow proper call order.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_init(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Checks if a timer is initialized.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return true if initialized, false otherwise
+ */
+bool timer_cmsdk_is_initialized(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Enables external input, which could be used as clock source
+ *        by calling \ref timer_cmsdk_set_clock_to_external.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_enable_external_input(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Disables external input.
+ *        Make sure if the timer is explicitly wanted to be stopped or set
+ *        the clock source to internal by \ref timer_cmsdk_set_clock_to_internal.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_disable_external_input(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Checks if external input is enabled.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool timer_cmsdk_is_external_input_enabled(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Sets the clock source to internal.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_set_clock_to_internal(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Sets the clock source to external.
+ *        Make sure external input is enabled correspondingly
+ *        by \ref timer_cmsdk_enable_external_input.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_set_clock_to_external(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Checks if clock source is external input.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return true if external, false if internal
+ */
+bool timer_cmsdk_is_clock_external(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Enables timer operation.
+ *
+ * \param[in] dev Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_enable(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Disables the given hardware timer.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_disable(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Checks if a timer is enabled.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool timer_cmsdk_is_enabled(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Enables timer interrupt.
+ *
+ * \param[in] dev       Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_enable_interrupt(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Disables timer interrupt.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_disable_interrupt(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Checks if a timer interrupt is enabled.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return true if enabled, false otherwise
+ */
+bool timer_cmsdk_is_interrupt_enabled(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Gets timer interrupt status
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * * \return true if active, false otherwise
+ */
+bool timer_cmsdk_is_interrupt_active(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Clears timer interrupt
+ *        The interrupt request is held until it is cleared.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_clear_interrupt(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Reads timer current value.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return Timer value
+ */
+uint32_t timer_cmsdk_get_current_value(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Sets the reload value of the selected timer.
+ *
+ *        New reload value takes effect when:
+ *        - timer is restarted
+ *        - on timer underflow
+ *        - when timer_cmsdk_reset is called
+ *
+ * \note  In r1p0 technical reference manual it's incorrectly stated
+ *        writing the reload value automatically sets the current value also.
+ *        r1p1 technical reference manual includes the fix.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ * \param[in] reload Timer reload value to set.
+ *            This is the start value of the 32-bit down counter,
+ *            which automatically reloaded if 0 is reached.
+ */
+void timer_cmsdk_set_reload_value(const struct timer_cmsdk_dev_t* dev,
+                                  uint32_t reload);
+
+/**
+ * \brief Resets the timer counter to the reload value instantly
+ *        (i.e. without waiting for underflow).
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ */
+void timer_cmsdk_reset(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Gets the reload value of the selected timer.
+ *        This is the start value of the 32-bit down counter,
+ *        which is automatically reloaded if 0 is reached by the counter.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return Reload value of the selected timer.
+ */
+uint32_t timer_cmsdk_get_reload_value(const struct timer_cmsdk_dev_t* dev);
+
+/**
+ * \brief Reads the number of ticks elapsed in the current cycle.
+ *
+ * \param[in] dev  Timer configuration \ref timer_cmsdk_dev_t
+ *
+ * \return Get elapsed number of ticks since last reload was set.
+ *         Elapsed = (Reload value - Current value)
+ */
+uint32_t timer_cmsdk_get_elapsed_value(const struct timer_cmsdk_dev_t* dev);
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* __TIMER_CMSDK_DRV_H__ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/memory_zones.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * This file contains the information of memory zones for code and data on
+ * CM3DS.
+ * It is used in startup code and linker scripts of supported compilers (ARM and
+ * GCC_ARM).
+ *
+ * WARNING: IAR does not include this file and re-define these values in
+ * MPS2.icf file. Please make sure that the two files share the same values.
+ *
+ * These memory zones are defined in section 4.1.1 of CM3DS Eval RTL and
+ * Testbench User Guide.
+ */
+
+#ifndef MEMORY_ZONES_H
+#define MEMORY_ZONES_H
+
+/*
+ * Code memory zones
+ * Please note that CM3DS on MPS2 does not contain any persistent flash memory.
+ * The FLASH memory zone is a 256 KiB SRAM block in the FPGA and named FLASH
+ * only to keep the same name than in the CM3DS Eval RTL and Testbench User
+ * Guide.
+ */
+#define FLASH_START       0x00000000
+#define FLASH_SIZE        0x00040000 /* 256 KiB */
+#define ZBT_SSRAM1_START  0x00400000
+#define ZBT_SSRAM1_SIZE   0x00400000 /* 4 MiB */
+
+/* Data memory zones */
+#define SRAM0_START       0x20000000
+#define SRAM0_SIZE        0x00008000 /* 32 KiB */
+#define SRAM1_START       0x20008000
+#define SRAM1_SIZE        0x00008000 /* 32 KiB */
+#define SRAM2_START       0x20010000
+#define SRAM2_SIZE        0x00008000 /* 32 KiB */
+#define SRAM3_START       0x20018000
+#define SRAM3_SIZE        0x00008000 /* 32 KiB */
+#define ZBT_SSRAM23_START 0x20400000
+#define ZBT_SSRAM23_SIZE  0x00400000 /* 4 MiB */
+
+#endif /* MEMORY_ZONES_H */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform_devices.h"
+#include "SMM_MPS2.h"
+
+/* ARM CMSDK Timer driver structures */
+#ifdef ARM_CMSDK_TIMER0
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG = {
+    .base = CMSDK_TIMER0_BASE};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA = {
+    .is_initialized = 0};
+struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV = {&(CMSDK_TIMER0_DEV_CFG),
+                                           &(CMSDK_TIMER0_DEV_DATA)};
+#endif
+
+#ifdef ARM_CMSDK_TIMER1
+static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG = {
+    .base = CMSDK_TIMER1_BASE};
+static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA = {
+    .is_initialized = 0};
+struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV = {&(CMSDK_TIMER1_DEV_CFG),
+                                           &(CMSDK_TIMER1_DEV_DATA)};
+#endif
+
+/* ARM GPIO driver structures */
+#ifdef ARM_GPIO0
+static const struct arm_gpio_dev_cfg_t ARM_GPIO0_DEV_CFG = {
+  .base = CMSDK_GPIO0_BASE};
+static struct arm_gpio_dev_data_t ARM_GPIO0_DEV_DATA = {
+    .state = 0,
+    .port_mask = DEFAULT_PORT_MASK};
+struct arm_gpio_dev_t ARM_GPIO0_DEV = {&(ARM_GPIO0_DEV_CFG),
+                                       &(ARM_GPIO0_DEV_DATA)};
+#endif /* ARM_GPIO0 */
+
+#ifdef ARM_GPIO1
+static const struct arm_gpio_dev_cfg_t ARM_GPIO1_DEV_CFG = {
+  .base = CMSDK_GPIO1_BASE};
+static struct arm_gpio_dev_data_t ARM_GPIO1_DEV_DATA = {
+    .state = 0,
+    .port_mask = DEFAULT_PORT_MASK};
+struct arm_gpio_dev_t ARM_GPIO1_DEV = {&(ARM_GPIO1_DEV_CFG),
+                                       &(ARM_GPIO1_DEV_DATA)};
+#endif /* ARM_GPIO1 */
+
+#ifdef ARM_GPIO2
+static const struct arm_gpio_dev_cfg_t ARM_GPIO2_DEV_CFG = {
+  .base = CMSDK_GPIO2_BASE};
+static struct arm_gpio_dev_data_t ARM_GPIO2_DEV_DATA = {
+    .state = 0,
+    .port_mask = DEFAULT_PORT_MASK};
+struct arm_gpio_dev_t ARM_GPIO2_DEV = {&(ARM_GPIO2_DEV_CFG),
+                                       &(ARM_GPIO2_DEV_DATA)};
+#endif /* ARM_GPIO2 */
+
+#ifdef ARM_GPIO3
+static const struct arm_gpio_dev_cfg_t ARM_GPIO3_DEV_CFG = {
+  .base = CMSDK_GPIO3_BASE};
+static struct arm_gpio_dev_data_t ARM_GPIO3_DEV_DATA = {
+    .state = 0,
+    .port_mask = DEFAULT_PORT_MASK};
+struct arm_gpio_dev_t ARM_GPIO3_DEV = {&(ARM_GPIO3_DEV_CFG),
+                                       &(ARM_GPIO3_DEV_DATA)};
+#endif /* ARM_GPIO3 */
+
+/* ARM MPS2 IO FPGAIO driver structures */
+#ifdef ARM_MPS2_IO_FPGAIO
+static const struct arm_mps2_io_dev_cfg_t ARM_MPS2_IO_FPGAIO_DEV_CFG = {
+  .base = MPS2_FPGAIO_BASE,
+  .type = ARM_MPS2_IO_TYPE_FPGAIO};
+struct arm_mps2_io_dev_t ARM_MPS2_IO_FPGAIO_DEV =
+                                                {&(ARM_MPS2_IO_FPGAIO_DEV_CFG)};
+#endif /* ARM_MPS2_IO_FPGAIO */
+
+/* ARM MPS2 IO SCC driver structures */
+#ifdef ARM_MPS2_IO_SCC
+static const struct arm_mps2_io_dev_cfg_t ARM_MPS2_IO_SCC_DEV_CFG = {
+  /*
+   * MPS2 IO SCC and FPGAIO registers have similar structure
+   * with 4 byte offset addresses.
+   */
+  .base = MPS2_SCC_BASE + 4,
+  .type = ARM_MPS2_IO_TYPE_SCC};
+struct arm_mps2_io_dev_t ARM_MPS2_IO_SCC_DEV = {&(ARM_MPS2_IO_SCC_DEV_CFG)};
+#endif /* ARM_MPS2_IO_SCC */
+
+/* ARM SPI driver structure */
+#ifdef ARM_SPI0
+static const struct spi_pl022_dev_cfg_t SPI0_PL022_DEV_CFG = {
+    .base = MPS2_SSP0_BASE,
+    .default_ctrl_cfg = {
+       .spi_mode = SPI_PL022_MASTER_SELECT,
+       .frame_format = SPI_PL022_CFG_FRF_MOT,
+       .word_size = 8,
+       .bit_rate = DEFAULT_SPI_SPEED_HZ
+    }};
+static struct spi_pl022_dev_data_t SPI0_PL022_DEV_DATA = {
+    .state = 0,
+    .sys_clk = 0,
+    .ctrl_cfg = {
+       .spi_mode = SPI_PL022_MASTER_SELECT,
+       .frame_format = 0,
+       .word_size = 0,
+       .bit_rate = 0
+     }};
+struct spi_pl022_dev_t SPI0_PL022_DEV = {&(SPI0_PL022_DEV_CFG),
+                                           &(SPI0_PL022_DEV_DATA)};
+#endif /* ARM_SPI0 */
+
+#ifdef ARM_SPI1
+static const struct spi_pl022_dev_cfg_t SPI1_PL022_DEV_CFG = {
+    .base = MPS2_SSP1_BASE,
+    .default_ctrl_cfg = {
+       .spi_mode = SPI_PL022_MASTER_SELECT,
+       .frame_format = SPI_PL022_CFG_FRF_MOT,
+       .word_size = 8,
+       .bit_rate = DEFAULT_SPI_SPEED_HZ
+    }};
+static struct spi_pl022_dev_data_t SPI1_PL022_DEV_DATA = {
+    .state = 0,
+    .sys_clk = 0,
+    .ctrl_cfg = {
+       .spi_mode = SPI_PL022_MASTER_SELECT,
+       .frame_format = 0,
+       .word_size = 0,
+       .bit_rate = 0
+     }};
+struct spi_pl022_dev_t SPI1_PL022_DEV = {&(SPI1_PL022_DEV_CFG),
+                                           &(SPI1_PL022_DEV_DATA)};
+#endif /* ARM_SPI1 */
+
+#ifdef ARM_SPI2
+static const struct spi_pl022_dev_cfg_t SPI2_PL022_DEV_CFG = {
+    .base = MPS2_SSP2_BASE,
+    .default_ctrl_cfg = {
+       .spi_mode = SPI_PL022_MASTER_SELECT,
+       .frame_format = SPI_PL022_CFG_FRF_MOT,
+       .word_size = 8,
+       .bit_rate = DEFAULT_SPI_SPEED_HZ
+    }};
+static struct spi_pl022_dev_data_t SPI2_PL022_DEV_DATA = {
+    .state = 0,
+    .sys_clk = 0,
+    .ctrl_cfg = {
+       .spi_mode = SPI_PL022_MASTER_SELECT,
+       .frame_format = 0,
+       .word_size = 0,
+       .bit_rate = 0
+     }};
+struct spi_pl022_dev_t SPI2_PL022_DEV = {&(SPI2_PL022_DEV_CFG),
+                                           &(SPI2_PL022_DEV_DATA)};
+#endif /* ARM_SPI2 */
+
+#ifdef ARM_SPI3
+static const struct spi_pl022_dev_cfg_t SPI3_PL022_DEV_CFG = {
+    .base = MPS2_SSP3_BASE,
+    .default_ctrl_cfg = {
+       .spi_mode = SPI_PL022_MASTER_SELECT,
+       .frame_format = SPI_PL022_CFG_FRF_MOT,
+       .word_size = 8,
+       .bit_rate = DEFAULT_SPI_SPEED_HZ
+    }};
+static struct spi_pl022_dev_data_t SPI3_PL022_DEV_DATA = {
+    .state = 0,
+    .sys_clk = 0,
+    .ctrl_cfg = {
+       .spi_mode = SPI_PL022_MASTER_SELECT,
+       .frame_format = 0,
+       .word_size = 0,
+       .bit_rate = 0
+     }};
+struct spi_pl022_dev_t SPI3_PL022_DEV = {&(SPI3_PL022_DEV_CFG),
+                                           &(SPI3_PL022_DEV_DATA)};
+#endif /* ARM_SPI3 */
+
+#ifdef ARM_SPI4
+static const struct spi_pl022_dev_cfg_t SPI4_PL022_DEV_CFG = {
+    .base = MPS2_SSP4_BASE,
+    .default_ctrl_cfg = {
+       .spi_mode = SPI_PL022_MASTER_SELECT,
+       .frame_format = SPI_PL022_CFG_FRF_MOT,
+       .word_size = 8,
+       .bit_rate = DEFAULT_SPI_SPEED_HZ
+    }};
+static struct spi_pl022_dev_data_t SPI4_PL022_DEV_DATA = {
+    .state = 0,
+    .sys_clk = 0,
+    .ctrl_cfg = {
+       .spi_mode = SPI_PL022_MASTER_SELECT,
+       .frame_format = 0,
+       .word_size = 0,
+       .bit_rate = 0
+     }};
+struct spi_pl022_dev_t SPI4_PL022_DEV = {&(SPI4_PL022_DEV_CFG),
+                                           &(SPI4_PL022_DEV_DATA)};
+#endif /* ARM_SPI4 */
+
+/* ARM UART driver structures */
+#ifdef ARM_UART0
+static const struct arm_uart_dev_cfg_t ARM_UART0_DEV_CFG = {
+  .base = CMSDK_UART0_BASE,
+  .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART0_DEV_DATA = {
+  .state = 0,
+  .system_clk = 0,
+  .baudrate = 0};
+struct arm_uart_dev_t ARM_UART0_DEV = {&(ARM_UART0_DEV_CFG),
+                                       &(ARM_UART0_DEV_DATA)};
+#endif /* ARM_UART0 */
+
+#ifdef ARM_UART1
+static const struct arm_uart_dev_cfg_t ARM_UART1_DEV_CFG = {
+  .base = CMSDK_UART1_BASE,
+  .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART1_DEV_DATA = {
+  .state = 0,
+  .system_clk = 0,
+  .baudrate = 0};
+struct arm_uart_dev_t ARM_UART1_DEV = {&(ARM_UART1_DEV_CFG),
+                                       &(ARM_UART1_DEV_DATA)};
+#endif /* ARM_UART1 */
+
+#ifdef ARM_UART2
+static const struct arm_uart_dev_cfg_t ARM_UART2_DEV_CFG = {
+  .base = CMSDK_UART2_BASE,
+  .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART2_DEV_DATA = {
+  .state = 0,
+  .system_clk = 0,
+  .baudrate = 0};
+struct arm_uart_dev_t ARM_UART2_DEV = {&(ARM_UART2_DEV_CFG),
+                                       &(ARM_UART2_DEV_DATA)};
+#endif /* ARM_UART2 */
+
+#ifdef ARM_UART3
+static const struct arm_uart_dev_cfg_t ARM_UART3_DEV_CFG = {
+  .base = CMSDK_UART3_BASE,
+  .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART3_DEV_DATA = {
+  .state = 0,
+  .system_clk = 0,
+  .baudrate = 0};
+struct arm_uart_dev_t ARM_UART3_DEV = {&(ARM_UART3_DEV_CFG),
+                                       &(ARM_UART3_DEV_DATA)};
+#endif /* ARM_UART3 */
+
+#ifdef ARM_UART4
+static const struct arm_uart_dev_cfg_t ARM_UART4_DEV_CFG = {
+  .base = CMSDK_UART4_BASE,
+  .default_baudrate = DEFAULT_UART_BAUDRATE};
+static struct arm_uart_dev_data_t ARM_UART4_DEV_DATA = {
+  .state = 0,
+  .system_clk = 0,
+  .baudrate = 0};
+struct arm_uart_dev_t ARM_UART4_DEV = {&(ARM_UART4_DEV_CFG),
+                                       &(ARM_UART4_DEV_DATA)};
+#endif /* ARM_UART4 */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2017-2018 ARM Limited
+ *
+ * Licensed under the Apache License Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing software
+ * distributed under the License is distributed on an "AS IS" BASIS
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __ARM_LTD_PLATFORM_DEVICES_H__
+#define __ARM_LTD_PLATFORM_DEVICES_H__
+
+#include "device_cfg.h"
+
+/* ======= Includes generic driver headers ======= */
+#include "timer_cmsdk_drv.h"
+#include "arm_gpio_drv.h"
+#include "arm_mps2_io_drv.h"
+#include "spi_pl022_drv.h"
+#include "arm_uart_drv.h"
+
+/* ======= Defines peripheral configuration structures ======= */
+
+/* ARM CMSDK Timer driver structures */
+#ifdef ARM_CMSDK_TIMER0
+extern struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV;
+#endif
+
+#ifdef ARM_CMSDK_TIMER1
+extern struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV;
+#endif
+
+/* ARM GPIO driver structures */
+#ifdef ARM_GPIO0
+extern struct arm_gpio_dev_t ARM_GPIO0_DEV;
+#endif
+#ifdef ARM_GPIO1
+extern struct arm_gpio_dev_t ARM_GPIO1_DEV;
+#endif
+#ifdef ARM_GPIO2
+extern struct arm_gpio_dev_t ARM_GPIO2_DEV;
+#endif
+#ifdef ARM_GPIO3
+extern struct arm_gpio_dev_t ARM_GPIO3_DEV;
+#endif
+
+/* ARM MPS2 IO FPGAIO driver structures */
+#ifdef ARM_MPS2_IO_FPGAIO
+extern struct arm_mps2_io_dev_t ARM_MPS2_IO_FPGAIO_DEV;
+#endif
+
+/* ARM MPS2 IO SCC driver structures */
+#ifdef ARM_MPS2_IO_SCC
+extern struct arm_mps2_io_dev_t ARM_MPS2_IO_SCC_DEV;
+#endif
+
+/* ARM SPI driver structures */
+#ifdef ARM_SPI0
+extern struct spi_pl022_dev_t SPI0_PL022_DEV;
+#endif
+#ifdef ARM_SPI1
+extern struct spi_pl022_dev_t SPI1_PL022_DEV;
+#endif
+#ifdef ARM_SPI2
+extern struct spi_pl022_dev_t SPI2_PL022_DEV;
+#endif
+#ifdef ARM_SPI3
+extern struct spi_pl022_dev_t SPI3_PL022_DEV;
+#endif
+#ifdef ARM_SPI4
+extern struct spi_pl022_dev_t SPI4_PL022_DEV;
+#endif
+
+/* ARM UART driver structures */
+#ifdef ARM_UART0
+extern struct arm_uart_dev_t ARM_UART0_DEV;
+#endif
+#ifdef ARM_UART1
+extern struct arm_uart_dev_t ARM_UART1_DEV;
+#endif
+#ifdef ARM_UART2
+extern struct arm_uart_dev_t ARM_UART2_DEV;
+#endif
+#ifdef ARM_UART3
+extern struct arm_uart_dev_t ARM_UART3_DEV;
+#endif
+#ifdef ARM_UART4
+extern struct arm_uart_dev_t ARM_UART4_DEV;
+#endif
+
+#endif  /* __ARM_LTD_PLATFORM_DEVICES_H__ */

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
+ * Copyright (c) 2006-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -17,177 +17,236 @@
 #include <stddef.h>
 #include "gpio_api.h"
 #include "pinmap.h"
+#include "objects.h"
+#include "mbed_error.h"
 
-#define GPIO_PIN_POS_MASK 0x0F /* pin % 16 */
-#define RESERVED_MISC_PIN 7
+enum io_type {
+    GPIO_DEVICE,
+    MPS2_IO_DEVICE,
+    DEVICE_UNKNOWN
+};
 
-/* \brief Gets the FPGA MISC (Miscellaneous control) bit position for the given
- *        pin name
- *
- *  FPGA MISC bit mapping:
- *    [31:7] Reserved
- *    [6] CLCD_BL_CTRL
- *    [5] CLCD_RD
- *    [4] CLCD_RS
- *    [3] CLCD_RESET
- *    [2] Reserved
- *    [1] SPI_nSS
- *    [0] CLCD_CS
- *
- *  \param[in] pin  MISC pin name
- *
- *  \return FPGA MISC bit position
- */
-static uint8_t get_fpga_misc_pin_pos(PinName pin)
+/* Tell if the gpio is from GPIO device or MPS2 IO */
+static enum io_type io_type(gpio_t *obj)
 {
-    uint8_t pin_position = RESERVED_MISC_PIN;
-
-    if (pin == SPI_SCLK) {
-        pin_position = 0;
-    } else if (pin == CLCD_SSEL) {
-        pin_position = 1;
-    } else if (pin == CLCD_RESET) {
-        pin_position = 3;
-    } else if (pin == CLCD_RS) {
-        pin_position = 4;
-    } else if (pin == CLCD_RD) {
-        pin_position = 5;
-    } else if (pin == CLCD_BL_CTRL){
-        pin_position = 6;
+    if (obj->gpio_dev != NULL && obj->mps2_io_dev == NULL) {
+        return GPIO_DEVICE;
     }
-
-    return pin_position;
+    if (obj->gpio_dev == NULL && obj->mps2_io_dev != NULL) {
+        return MPS2_IO_DEVICE;
+    }
+    return DEVICE_UNKNOWN;
 }
 
+/* Return the correct mask of the given PIN */
 uint32_t gpio_set(PinName pin)
 {
-    uint8_t pin_position;
+    pin_function(pin, (int)GPIO_FUNC);
 
-    if (pin >=EXP0 && pin <= EXP51) {
-        /* Set pin functinality as GPIO. pin_function asserts if pin == NC */
-        pin_function(pin, GPIO_FUNC);
+    if (pin >= EXP0 && pin <= EXP51) {
+        /* GPIO pins */
+        return (1 << GPIO_PIN_NUMBER(pin));
+    } else if (pin == USERLED1 || pin == USERLED2) {
+        /* User LEDs */
+        return (1 << (pin - USERLED1));
+    } else if (pin == USERSW1 || pin == USERSW2) {
+        /* User Push buttons */
+        return (1 << (pin - USERSW1));
+    } else if (pin >= LED1 && pin <= LED8) {
+        /* MCC LEDs */
+        return (1 << (pin - LED1));
+    } else if (pin >= SW1 && pin <= SW8) {
+        /* MCC Switches */
+        return (1 << (pin - SW1));
     } else {
-        /* Check if pin is a MISC pin */
-        pin_position = get_fpga_misc_pin_pos(pin);
-        if (pin_position != RESERVED_MISC_PIN) {
-            return (1 << pin_position);
-        }
+        return 0;
     }
-
-    /* Return pin mask */
-    return (1 << (pin & 0xFF));
 }
 
 void gpio_init(gpio_t *obj, PinName pin)
 {
-    uint8_t pin_position;
+    struct arm_gpio_dev_t *gpio_dev;
 
-    if (pin == NC) {
-       return;
+    if (pin >= EXP0 && pin <= EXP51) {
+        /* GPIO pins */
+        switch (GPIO_DEV_NUMBER(pin)) {
+#ifdef ARM_GPIO0
+        case GPIO0_NUMBER:
+            gpio_dev = &ARM_GPIO0_DEV;
+            break;
+#endif /* ARM_GPIO0 */
+#ifdef ARM_GPIO1
+        case GPIO1_NUMBER:
+            gpio_dev = &ARM_GPIO1_DEV;
+            break;
+#endif /* ARM_GPIO1 */
+#ifdef ARM_GPIO2
+        case GPIO2_NUMBER:
+            gpio_dev = &ARM_GPIO2_DEV;
+            break;
+#endif /* ARM_GPIO2 */
+#ifdef ARM_GPIO3
+        case GPIO3_NUMBER:
+            gpio_dev = &ARM_GPIO3_DEV;
+            break;
+#endif /* ARM_GPIO3 */
+        default:
+            error("GPIO %d, associated with expansion pin %d, is disabled",
+                  GPIO_DEV_NUMBER(pin), pin);
+            return;
+        }
+
+        arm_gpio_init(gpio_dev);
+
+        obj->gpio_dev = gpio_dev;
+        obj->mps2_io_dev = NULL;
+        obj->pin_number = GPIO_PIN_NUMBER(pin);
+        /* GPIO is input by default */
+        obj->direction = PIN_INPUT;
+        return;
     }
 
-    obj->pin = pin;
-    obj->pin_number = pin;
-
-    if (pin <= EXP15) {
-        obj->reg_data   = &CMSDK_GPIO0->DATAOUT;
-        obj->reg_in     = &CMSDK_GPIO0->DATA;
-        obj->reg_dir    = &CMSDK_GPIO0->OUTENABLESET;
-        obj->reg_dirclr = &CMSDK_GPIO0->OUTENABLECLR;
-        /* Set pin function as a GPIO */
-        pin_function(pin, GPIO_FUNC);
-        pin_position = pin;
-    } else if (pin >= EXP16 && pin <= EXP31) {
-        obj->reg_data   = &CMSDK_GPIO1->DATAOUT;
-        obj->reg_in     = &CMSDK_GPIO1->DATA;
-        obj->reg_dir    = &CMSDK_GPIO1->OUTENABLESET;
-        obj->reg_dirclr = &CMSDK_GPIO1->OUTENABLECLR;
-        /* Set pin function as a GPIO */
-        pin_function(pin, GPIO_FUNC);
-        pin_position = (pin & GPIO_PIN_POS_MASK);
-    } else if (pin >= EXP32 && pin <= EXP47) {
-        obj->reg_data   = &CMSDK_GPIO2->DATAOUT;
-        obj->reg_in     = &CMSDK_GPIO2->DATA;
-        obj->reg_dir    = &CMSDK_GPIO2->OUTENABLESET;
-        obj->reg_dirclr = &CMSDK_GPIO2->OUTENABLECLR;
-        /* Set pin function as a GPIO */
-        pin_function(pin, GPIO_FUNC);
-        pin_position = (pin & GPIO_PIN_POS_MASK);
-    } else if (pin >= EXP48 && pin <= EXP51) {
-        obj->reg_data   = &CMSDK_GPIO3->DATAOUT;
-        obj->reg_in     = &CMSDK_GPIO3->DATA;
-        obj->reg_dir    = &CMSDK_GPIO3->OUTENABLESET;
-        obj->reg_dirclr = &CMSDK_GPIO3->OUTENABLECLR;
-        /* Set pin function as a GPIO */
-        pin_function(pin, GPIO_FUNC);
-        pin_position = (pin & GPIO_PIN_POS_MASK);
-    } else if (pin == 100 || pin == 101) {
+#ifdef ARM_MPS2_IO_FPGAIO
+    if (pin == USERLED1 || pin == USERLED2) {
         /* User LEDs */
-        pin_position = (pin - 100);
-        obj->reg_data   = &MPS2_FPGAIO->LED;
-        obj->reg_in     = &MPS2_FPGAIO->LED;
-        obj->reg_dir    = NULL;
-        obj->reg_dirclr = NULL;
-    } else if (pin == 110 || pin == 111) {
-        /* User buttons */
-        pin_position = (pin - 110);
-        obj->reg_data   = &MPS2_FPGAIO->BUTTON;
-        obj->reg_in     = &MPS2_FPGAIO->BUTTON;
-        obj->reg_dir    = NULL;
-        obj->reg_dirclr = NULL;
-    } else if (pin >= 200 && pin <= 207) {
+        obj->gpio_dev = NULL;
+        obj->mps2_io_dev = &ARM_MPS2_IO_FPGAIO_DEV;
+        obj->pin_number = pin - USERLED1;
+        obj->direction = PIN_OUTPUT;
+        return;
+    } else if (pin == USERSW1 || pin == USERSW2) {
+        /* User Push buttons */
+        obj->gpio_dev = NULL;
+        obj->mps2_io_dev = &ARM_MPS2_IO_FPGAIO_DEV;
+        obj->pin_number = pin - USERSW1;
+        obj->direction = PIN_INPUT;
+        return;
+    }
+#endif /* ARM_MPS2_IO_FPGAIO */
+
+#ifdef ARM_MPS2_IO_SCC
+    if (pin >= LED1 && pin <= LED8) {
         /* MCC LEDs */
-        pin_position = (pin - 200);
-        obj->reg_data   = &MPS2_SCC->LEDS;
-        obj->reg_in     = &MPS2_SCC->LEDS;
-        obj->reg_dir    = NULL;
-        obj->reg_dirclr = NULL;
-    } else if (pin >= 210 && pin <= 217) {
-        /* MCC switches */
-        pin_position = (pin - 210);
-        obj->reg_in     = &MPS2_SCC->SWITCHES;
-        obj->reg_data   = NULL;
-        obj->reg_dir    = NULL;
-        obj->reg_dirclr = NULL;
-    } else {
-        /* Check if pin is a MISC pin */
-        pin_position = get_fpga_misc_pin_pos(pin);
-        if (pin_position != RESERVED_MISC_PIN) {
-            obj->reg_data = &MPS2_FPGAIO->MISC;
-        } else {
-            pin_position = 0;
-        }
+        obj->gpio_dev = NULL;
+        obj->mps2_io_dev = &ARM_MPS2_IO_SCC_DEV;
+        obj->pin_number = pin - LED1;
+        obj->direction = PIN_OUTPUT;
+        return;
+    } else if (pin >= SW1 && pin <= SW8) {
+        /* MCC Switches */
+        obj->gpio_dev = NULL;
+        obj->mps2_io_dev = &ARM_MPS2_IO_SCC_DEV;
+        obj->pin_number = pin - SW1;
+        obj->direction = PIN_INPUT;
+        return;
     }
+#endif /* ARM_MPS2_IO_SCC */
 
-    /* Set pin mask */
-    obj->mask = (1 << pin_position);
+    error("pin %d is not a GPIO", pin);
 }
 
 void gpio_mode(gpio_t *obj, PinMode mode)
 {
-    pin_mode(obj->pin, mode);
+    /* PinMode is not supported */
 }
 
 void gpio_dir(gpio_t *obj, PinDirection direction)
 {
-    if (obj->pin >= EXP0 && obj->pin <= EXP51) {
+    uint32_t flags = ARM_GPIO_PIN_ENABLE;
+
+    obj->direction = direction;
+
+    switch (io_type(obj)) {
+    case GPIO_DEVICE:
         switch (direction) {
-            case PIN_INPUT :
-                *obj->reg_dirclr = obj->mask;
-                break;
-            case PIN_OUTPUT:
-                *obj->reg_dir |= obj->mask;
-                break;
+        case PIN_INPUT:
+            flags |= ARM_GPIO_INPUT;
+            break;
+        case PIN_OUTPUT:
+            flags |= ARM_GPIO_OUTPUT;
+            break;
+        /* default: not added to force to cover all enumeration cases */
         }
+
+        (void)arm_gpio_config(obj->gpio_dev, ARM_GPIO_ACCESS_PIN,
+                              obj->pin_number, flags);
+        return;
+    case MPS2_IO_DEVICE:
+        /* Do nothing as MPS2 IO direction can not be changed */
+        return;
+    case DEVICE_UNKNOWN:
+        break;
+    /* default:  The default is not defined intentionally to force the
+     *           compiler to check that all the enumeration values are
+     *           covered in the switch.*/
     }
+
+    error("can not change the direction of pin");
 }
 
 int gpio_is_connected(const gpio_t *obj)
 {
-    if (obj->pin != (PinName)NC) {
+    if (obj->pin_number == (uint32_t)NC) {
+        return 0;
+    } else {
         return 1;
     }
+}
+
+void gpio_write(gpio_t *obj, int value)
+{
+    switch (io_type(obj)) {
+    case GPIO_DEVICE:
+        (void)arm_gpio_write(obj->gpio_dev, ARM_GPIO_ACCESS_PIN,
+                             obj->pin_number, (uint32_t)value);
+        return;
+    case MPS2_IO_DEVICE:
+        if (obj->direction == PIN_INPUT) {
+            /*
+             * If the given gpio is in fact a button, ignore the call to not
+             * write to the corresponding LED instead.
+             */
+            return;
+        }
+        arm_mps2_io_write_leds(obj->mps2_io_dev, ARM_MPS2_IO_ACCESS_PIN,
+                               obj->pin_number, (uint32_t)value);
+        return;
+    case DEVICE_UNKNOWN:
+        break;
+    /* default:  The default is not defined intentionally to force the
+     *           compiler to check that all the enumeration values are
+     *           covered in the switch.*/
+    }
 
+    error("can not write pin");
+}
+
+int gpio_read(gpio_t *obj)
+{
+    switch (io_type(obj)) {
+    case GPIO_DEVICE:
+        return (int)arm_gpio_read(obj->gpio_dev, ARM_GPIO_ACCESS_PIN,
+                                  obj->pin_number);
+    case MPS2_IO_DEVICE:
+        switch (obj->direction) {
+        case PIN_INPUT:
+
+            return (int)arm_mps2_io_read_buttons(obj->mps2_io_dev,
+                                                 ARM_MPS2_IO_ACCESS_PIN,
+                                                 obj->pin_number);
+        case PIN_OUTPUT:
+            return (int)arm_mps2_io_read_leds(obj->mps2_io_dev,
+                                              ARM_MPS2_IO_ACCESS_PIN,
+                                              obj->pin_number);
+        }
+
+    case DEVICE_UNKNOWN:
+        break;
+    /* default:  The default is not defined intentionally to force the
+     *           compiler to check that all the enumeration values are
+     *           covered in the switch.*/
+    }
+
+    error("can not read pin");
     return 0;
 }
-

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_irq_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_irq_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
+ * Copyright (c) 2006-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -14,425 +14,192 @@
  * limitations under the License.
  */
 #include <stddef.h>
-#include "cmsis.h"
+#include "objects.h"
 #include "gpio_irq_api.h"
 #include "mbed_error.h"
 
-#define CHANNEL_NUM  32
-#define CMSDK_GPIO_0 CMSDK_GPIO0
-#define CMSDK_GPIO_1 CMSDK_GPIO1
-#define PININT_IRQ   0
-
-static uint32_t channel_ids[CHANNEL_NUM] = {0};
-static gpio_irq_handler irq_handler;
+#define ERROR_BIT_NUMBER 0xFF
 
-static inline void handle_interrupt_in(uint32_t channel)
-{
-    uint32_t ch_bit = (1 << channel);
-    // Return immediately if:
-    //   * The interrupt was already served
-    //   * There is no user handler
-    //   * It is a level interrupt, not an edge interrupt
-    if (ch_bit < 16) {
-        if (((CMSDK_GPIO_0->INTSTATUS) == 0)
-             || (channel_ids[channel] == 0)
-             || ((CMSDK_GPIO_0->INTTYPESET) == 0) ) {
-            return;
-        }
+struct gpio_irq_handler_t {
+    gpio_irq_handler handler;
+    gpio_irq_event event;
+    uint32_t id;
+};
 
-        if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && (CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
-            irq_handler(channel_ids[channel], IRQ_RISE);
-            CMSDK_GPIO_0->INTPOLSET = ch_bit;
-        }
-        if ((CMSDK_GPIO_0->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_0->INTPOLSET & ch_bit)) {
-            irq_handler(channel_ids[channel], IRQ_FALL);
-        }
-
-        CMSDK_GPIO_0->INTCLEAR = ch_bit;
-    } else {
-        if (((CMSDK_GPIO_1->INTSTATUS) == 0)
-             || (channel_ids[channel] == 0)
-             || ((CMSDK_GPIO_1->INTTYPESET) == 0)) {
-            return;
-        }
+/* Handlers registered */
+static struct gpio_irq_handler_t gpio_irq[PINS_NUMBER];
 
-        if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && (CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
-            irq_handler(channel_ids[channel], IRQ_RISE);
-            CMSDK_GPIO_1->INTPOLSET = ch_bit;
-        }
-        if ((CMSDK_GPIO_1->INTTYPESET & ch_bit) && ~(CMSDK_GPIO_1->INTPOLSET & ch_bit)) {
-            irq_handler(channel_ids[channel], IRQ_FALL);
-        }
-        CMSDK_GPIO_1->INTCLEAR = ch_bit;
-    }
-}
-
-void gpio0_irq0(void)
+/*
+ * Return the bit number of the lowest significant bit set to 1 or
+ * ERROR_BIT_NUMBER if there is no bit set.
+ */
+static uint8_t find_first_set_bit(uint32_t word)
 {
-    handle_interrupt_in(0);
-}
-
-void gpio0_irq1(void)
-{
-    handle_interrupt_in(1);
-}
+    uint8_t bit_number = 0;
 
-void gpio0_irq2(void)
-{
-    handle_interrupt_in(2);
-}
-
-void gpio0_irq3(void)
-{
-    handle_interrupt_in(3);
-}
+    if (word == 0) {
+        return ERROR_BIT_NUMBER;
+    }
 
-void gpio0_irq4(void)
-{
-    handle_interrupt_in(4);
-}
+    while (((word >> bit_number++) & 1UL) == 0);
 
-void gpio0_irq5(void)
-{
-    handle_interrupt_in(5);
-}
-
-void gpio0_irq6(void)
-{
-    handle_interrupt_in(6);
+    return (bit_number - 1);
 }
 
-void gpio0_irq7(void)
-{
-    handle_interrupt_in(7);
-}
-
-void gpio0_irq8(void)
-{
-    handle_interrupt_in(8);
-}
-
-void gpio0_irq9(void)
-{
-    handle_interrupt_in(9);
-}
-
-void gpio0_irq10(void)
-{
-    handle_interrupt_in(10);
-}
-
-void gpio0_irq11(void)
-{
-    handle_interrupt_in(11);
-}
-
-void gpio0_irq12(void)
-{
-    handle_interrupt_in(12);
-}
-
-void gpio0_irq13(void)
-{
-    handle_interrupt_in(13);
-}
-
-void gpio0_irq14(void)
-{
-    handle_interrupt_in(14);
-}
-
-void gpio0_irq15(void)
+static void handler(struct arm_gpio_dev_t* dev, uint32_t gpio_number,
+                    uint32_t exp_pin_base)
 {
-    handle_interrupt_in(15);
-}
-
-void gpio1_irq0(void)
-{
-    handle_interrupt_in(16);
-}
+    uint32_t irq_status = 0;
+    /* Pin that triggered the IRQ in this GPIO */
+    uint8_t pin_number;
+    /* Pin number in the expension port */
+    uint8_t exp_pin_number;
 
-void gpio1_irq1(void)
-{
-    handle_interrupt_in(17);
-}
-void gpio1_irq2(void)
-{
-    handle_interrupt_in(18);
-}
-
-void gpio1_irq3(void)
-{
-    handle_interrupt_in(19);
-}
+    (void)arm_gpio_get_irq_status(dev, ARM_GPIO_ACCESS_PORT, ARG_NOT_USED,
+                                  &irq_status);
 
-void gpio1_irq4(void)
-{
-    handle_interrupt_in(20);
-}
-
-void gpio1_irq5(void)
-{
-    handle_interrupt_in(21);
-}
+    pin_number = find_first_set_bit(irq_status);
+    if (pin_number == ERROR_BIT_NUMBER) {
+        /* There was no IRQ */
+        return;
+    }
 
-void gpio1_irq6(void)
-{
-    handle_interrupt_in(22);
-}
+    (void)arm_gpio_clear_interrupt(dev, pin_number);
 
-void gpio1_irq7(void)
-{
-    handle_interrupt_in(23);
-}
+    exp_pin_number = exp_pin_base + pin_number;
 
-void gpio1_irq8(void)
-{
-    handle_interrupt_in(24);
+    gpio_irq[exp_pin_number].handler(gpio_irq[exp_pin_number].id,
+                                     gpio_irq[exp_pin_number].event);
 }
 
-void gpio1_irq9(void)
+#ifdef ARM_GPIO0
+void PORT0_IRQHandler(void)
 {
-    handle_interrupt_in(25);
+    handler(&ARM_GPIO0_DEV, GPIO0_NUMBER, EXP_PIN_BASE0);
 }
+#endif /* ARM_GPIO0 */
 
-void gpio1_irq10(void)
+#ifdef ARM_GPIO1
+void PORT1_ALL_IRQHandler(void)
 {
-    handle_interrupt_in(26);
+    handler(&ARM_GPIO1_DEV, GPIO1_NUMBER, EXP_PIN_BASE1);
 }
+#endif /* ARM_GPIO1 */
 
-void gpio1_irq11(void)
+#ifdef ARM_GPIO2
+void PORT2_ALL_IRQHandler(void)
 {
-    handle_interrupt_in(27);
+    handler(&ARM_GPIO2_DEV, GPIO2_NUMBER, EXP_PIN_BASE2);
 }
+#endif /* ARM_GPIO2 */
 
-void gpio1_irq12(void)
+#ifdef ARM_GPIO3
+void PORT3_ALL_IRQHandler(void)
 {
-    handle_interrupt_in(28);
+    handler(&ARM_GPIO3_DEV, GPIO3_NUMBER, EXP_PIN_BASE3);
 }
+#endif /* ARM_GPIO3 */
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler,
+                  uint32_t id)
+{
+    struct arm_gpio_dev_t *gpio_dev;
 
-void gpio1_irq13(void)
-{
-    handle_interrupt_in(29);
-}
-
-void gpio1_irq14(void)
-{
-    handle_interrupt_in(30);
-}
+    if (pin >= EXP0 && pin <= EXP51) {
+        /* GPIO pins */
+        switch (GPIO_DEV_NUMBER(pin)) {
+#ifdef ARM_GPIO0
+            case 0:
+                gpio_dev = &ARM_GPIO0_DEV;
+                obj->irq_number = PORT0_ALL_IRQn;
+                break;
+#endif /* ARM_GPIO0 */
+#ifdef ARM_GPIO1
+            case 1:
+                gpio_dev = &ARM_GPIO1_DEV;
+                obj->irq_number = PORT1_ALL_IRQn;
+                break;
+#endif /* ARM_GPIO1 */
+#ifdef ARM_GPIO2
+            case 2:
+                gpio_dev = &ARM_GPIO2_DEV;
+                obj->irq_number = PORT2_ALL_IRQn;
+                break;
+#endif /* ARM_GPIO2 */
+#ifdef ARM_GPIO3
+            case 3:
+                gpio_dev = &ARM_GPIO3_DEV;
+                obj->irq_number = PORT3_ALL_IRQn;
+                break;
+#endif /* ARM_GPIO3 */
+            default:
+                error("GPIO %d is not enabled", GPIO_DEV_NUMBER(pin));
+                return -1;
+        }
 
-void gpio1_irq15(void)
-{
-    handle_interrupt_in(31);
-}
+        obj->gpio_dev = gpio_dev;
+        obj->pin_number = GPIO_PIN_NUMBER(pin);
+        obj->exp_pin_number = pin;
+
+        arm_gpio_init(gpio_dev);
 
-int gpio_irq_init(gpio_irq_t *obj, PinName pin,
-                  gpio_irq_handler handler, uint32_t id)
-{
-    int found_free_channel = 0;
-    int i = 0;
+        /* Save the handler and id into the global structure */
+        gpio_irq[pin].handler = handler;
+        gpio_irq[pin].id = id;
 
-    if (pin == NC) {
+        return 0;
+    } else {
+        /* The pin is not concerned with GPIO IRQ */
+        error("Pin %d is not a GPIO", pin);
         return -1;
     }
-
-    irq_handler = handler;
-
-    for (i=0; i<CHANNEL_NUM; i++) {
-        if (channel_ids[i] == 0) {
-            channel_ids[i] = id;
-            obj->ch = i;
-            found_free_channel = 1;
-            break;
-        }
-    }
-
-    if (!found_free_channel) {
-       return -1;
-    }
-
-    /* To select a pin for any of the eight pin interrupts, write the pin number
-    * as 0 to 23 for pins PIO0_0 to PIO0_23 and 24 to 55.
-    * @see: mbed_capi/PinNames.h
-    */
-    if (pin <16) {
-        CMSDK_GPIO_0->INTENSET |= (0x1 << pin);
-    }
-
-    if (pin >= 16) {
-        CMSDK_GPIO_1->INTENSET |= (0x1 << pin);
-    }
-
-    void (*channels_irq)(void) = NULL;
-    switch (obj->ch) {
-        case 0:
-            channels_irq = &gpio0_irq0;
-            break;
-        case 1:
-            channels_irq = &gpio0_irq1;
-            break;
-        case 2:
-            channels_irq = &gpio0_irq2;
-            break;
-        case 3:
-            channels_irq = &gpio0_irq3;
-            break;
-        case 4:
-            channels_irq = &gpio0_irq4;
-            break;
-        case 5:
-            channels_irq = &gpio0_irq5;
-            break;
-        case 6:
-            channels_irq = &gpio0_irq6;
-            break;
-        case 7:
-            channels_irq = &gpio0_irq7;
-            break;
-        case 8:
-            channels_irq = &gpio0_irq8;
-            break;
-        case 9:
-            channels_irq = &gpio0_irq9;
-            break;
-        case 10:
-            channels_irq = &gpio0_irq10;
-            break;
-        case 11:
-            channels_irq = &gpio0_irq11;
-            break;
-        case 12:
-            channels_irq = &gpio0_irq12;
-            break;
-        case 13:
-            channels_irq = &gpio0_irq13;
-            break;
-        case 14:
-            channels_irq = &gpio0_irq14;
-            break;
-        case 15:
-            channels_irq = &gpio0_irq15;
-            break;
-        case 16:
-            channels_irq = &gpio1_irq0;
-            break;
-        case 17:
-            channels_irq = &gpio1_irq1;
-            break;
-        case 18:
-            channels_irq = &gpio1_irq2;
-            break;
-        case 19:
-            channels_irq = &gpio1_irq3;
-            break;
-        case 20:
-            channels_irq = &gpio1_irq4;
-            break;
-        case 21:
-            channels_irq = &gpio1_irq5;
-            break;
-        case 22:
-            channels_irq = &gpio1_irq6;
-            break;
-        case 23:
-            channels_irq = &gpio1_irq7;
-            break;
-        case 24:
-            channels_irq = &gpio1_irq8;
-            break;
-        case 25:
-            channels_irq = &gpio1_irq9;
-            break;
-        case 26:
-            channels_irq = &gpio1_irq10;
-            break;
-        case 27:
-            channels_irq = &gpio1_irq11;
-            break;
-        case 28:
-            channels_irq = &gpio1_irq12;
-            break;
-        case 29:
-            channels_irq = &gpio1_irq13;
-            break;
-        case 30:
-            channels_irq = &gpio1_irq14;
-            break;
-        case 31:
-            channels_irq = &gpio1_irq15;
-            break;
-    }
-
-    NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq);
-    NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
-
-    return 0;
 }
 
 void gpio_irq_free(gpio_irq_t *obj)
 {
-   channel_ids[obj->ch] = 0;
+    /* Not implemented because the device can not be uninitialized. */
 }
 
 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
 {
-    unsigned int ch_bit = (1 << obj->ch);
-
-    if (obj->ch <16) {
-        /* Clear interrupt */
-        if (!(CMSDK_GPIO_0->INTTYPESET & ch_bit)) {
-            CMSDK_GPIO_0->INTCLEAR = ch_bit;
-        }
-        CMSDK_GPIO_0->INTTYPESET &= ch_bit;
+    /* Interrupt is set on an input pin on rising or falling edge */
+    uint32_t flags = ARM_GPIO_PIN_ENABLE | ARM_GPIO_INPUT | ARM_GPIO_IRQ |
+                     ARM_GPIO_IRQ_EDGE;
 
-        /* Set interrupt */
-        if (event == IRQ_RISE) {
-            CMSDK_GPIO_0->INTPOLSET |= ch_bit;
-            if (enable) {
-                CMSDK_GPIO_0->INTENSET |= ch_bit;
-            } else {
-                CMSDK_GPIO_0->INTENCLR |= ch_bit;
-            }
-        } else {
-            CMSDK_GPIO_0->INTPOLCLR |= ch_bit;
-            if (enable) {
-                CMSDK_GPIO_0->INTENSET |= ch_bit;
-            } else {
-                CMSDK_GPIO_0->INTENCLR |= ch_bit;
-            }
-        }
+    switch (event) {
+        case IRQ_RISE:
+            flags |= ARM_GPIO_IRQ_ACTIVE_HIGH;
+            break;
+        case IRQ_FALL:
+            flags |= ARM_GPIO_IRQ_ACTIVE_LOW;
+            break;
+        case IRQ_NONE:
+            return;
+    }
+
+    (void)arm_gpio_config(obj->gpio_dev, ARM_GPIO_ACCESS_PIN, obj->pin_number,
+                          flags);
+
+    /* Record the event type of this pin */
+    gpio_irq[obj->exp_pin_number].event = event;
+
+    NVIC_EnableIRQ(obj->irq_number);
+
+    if (enable) {
+        gpio_irq_enable(obj);
     } else {
-        /* Clear interrupt */
-        if (!(CMSDK_GPIO_1->INTTYPESET & ch_bit)) {
-            CMSDK_GPIO_1->INTCLEAR = ch_bit;
-        }
-        CMSDK_GPIO_1->INTTYPESET &= ch_bit;
-
-        /* Set interrupt */
-        if (event == IRQ_RISE) {
-            CMSDK_GPIO_1->INTPOLSET |= ch_bit;
-            if (enable) {
-                CMSDK_GPIO_1->INTENSET |= ch_bit;
-            } else {
-                CMSDK_GPIO_1->INTENCLR |= ch_bit;
-            }
-        } else {
-            CMSDK_GPIO_1->INTPOLCLR |= ch_bit;
-            if (enable) {
-                CMSDK_GPIO_1->INTENSET |= ch_bit;
-            } else {
-                CMSDK_GPIO_1->INTENCLR |= ch_bit;
-            }
-        }
+        gpio_irq_disable(obj);
     }
 }
 
 void gpio_irq_enable(gpio_irq_t *obj)
 {
-    NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+    (void)arm_gpio_set_interrupt(obj->gpio_dev, ARM_GPIO_ACCESS_PIN,
+                                 obj->pin_number, ARM_GPIO_IRQ_ENABLE);
 }
 
 void gpio_irq_disable(gpio_irq_t *obj)
 {
-    NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch));
+    (void)arm_gpio_set_interrupt(obj->gpio_dev, ARM_GPIO_ACCESS_PIN,
+                                 obj->pin_number, ARM_GPIO_IRQ_DISABLE);
 }

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_object.h	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName  pin;
-    uint32_t mask;
-    uint32_t pin_number;
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_dirclr;
-    __IO uint32_t *reg_data;
-    __I uint32_t *reg_in;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
-    if (value) {
-        *obj->reg_data |= (obj->mask);
-    } else {
-        *obj->reg_data &= ~(obj->mask);
-    }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/gpio_objects.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MBED_GPIO_OBJECTS_H__
+#define __MBED_GPIO_OBJECTS_H__
+
+/*
+ * GPIO device number, there are 16 pins per GPIO
+ * equivalent: pin / 16
+ */
+#define GPIO_DEV_NUMBER(pin)  ((pin) >> 4)
+/*
+ * Pin number of this pin inside its GPIO
+ * equivalent: pin % 16
+ */
+#define GPIO_PIN_NUMBER(pin)  ((pin) & 0xF)
+
+/* Number of the GPIO device */
+#define GPIO0_NUMBER          0
+#define GPIO1_NUMBER          1
+#define GPIO2_NUMBER          2
+#define GPIO3_NUMBER          3
+
+/* Base EXP pin number for the corresponding GPIO */
+#define EXP_PIN_BASE0         EXP0
+#define EXP_PIN_BASE1         EXP16
+#define EXP_PIN_BASE2         EXP32
+#define EXP_PIN_BASE3         EXP48
+
+#define GPIO_DEVICES          4
+#define PINS_PER_GPIO         16
+/* Pins 4 to 15 of GPIO3 are not used */
+#define PINS_NOT_USED         12
+#define PINS_NUMBER           (GPIO_DEVICES * PINS_PER_GPIO - PINS_NOT_USED)
+
+/* GPIO3 port only uses first 4 pins */
+#define GPIO3_PIN_NUMBER  4
+
+/* When doing a port access, the pin number argument is useless */
+#define ARG_NOT_USED          0
+
+#endif /* __MBED_GPIO_OBJECTS_H__ */
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/lp_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+ /**
+  * Low-power elapsed time measure and interval timer in micro-secundum,
+  * servicing \ref lp_ticker_api.h, using CMSDK Timer1 \ref CMSDK_TIMER1_DEV.
+  */
+
+#include <limits.h>
+
+#include "cmsdk_ticker.h"
+#include "lp_ticker_api.h"
+#include "platform_devices.h"
+
+/**
+ * \brief Calculate clocks to us
+ *
+ * \param[in] tick Number of clock ticks
+ *
+ * \return Number of usec, relative to the timer frequency,
+ *         that a given ammount of ticks equates to.
+ */
+ static uint32_t convert_tick_to_us(uint32_t tick)
+ {
+     return (tick / (SystemCoreClock / SEC_TO_USEC_MULTIPLIER));
+ }
+
+/**
+ * \brief Calculate us to clock ticks
+ *
+ * \param[in] us Time to convert to clock ticks
+ *
+ * \return Number of clock ticks relative to the timer frequency,
+ *         that a given period of usec equates to.
+ */
+ static uint32_t convert_us_to_tick(uint32_t us)
+ {
+     return (us * (SystemCoreClock / SEC_TO_USEC_MULTIPLIER));
+ }
+
+static const struct tick_cfg_t cfg =
+{
+    .timer_driver = &CMSDK_TIMER1_DEV,
+    .irq_n = TIMER1_IRQn,
+    .interval_callback = &lp_ticker_irq_handler,
+    .convert_tick_to_time = &convert_tick_to_us,
+    .convert_time_to_tick = &convert_us_to_tick
+};
+
+static struct tick_data_t data =
+{
+    .is_initialized = false,
+    .cumulated_time = 0,
+    .max_interval_time = 0,
+    .reload_time = 0,
+    .interval_callback_enabled = false,
+    .previous_cumulated_time = 0,
+    .previous_elapsed = 0
+};
+
+static struct tick_drv_data_t timer_data =
+{
+    .cfg = &cfg,
+    .data = &data
+};
+
+void lp_ticker_init(void)
+{
+    cmsdk_ticker_init(&timer_data);
+}
+
+uint32_t lp_ticker_read()
+{
+    return cmsdk_ticker_read(&timer_data);
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+    cmsdk_ticker_set_interrupt(&timer_data, timestamp);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+    cmsdk_ticker_disable_interrupt(&timer_data);
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+    cmsdk_ticker_clear_interrupt(&timer_data);
+}
+
+void lp_ticker_fire_interrupt(void)
+{
+    cmsdk_ticker_fire_interrupt(&timer_data);
+}
+
+void TIMER1_IRQHandler(void)
+{
+    cmsdk_ticker_irq_handler(&timer_data);
+}

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
+ * Copyright (c) 2006-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -13,34 +13,44 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
+#ifndef __MBED_OBJECTS_H__
+#define __MBED_OBJECTS_H__
 
 #include "cmsis.h"
 #include "PortNames.h"
 #include "PeripheralNames.h"
 #include "PinNames.h"
+#include "platform_devices.h"
+#include "gpio_objects.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+typedef struct gpio_s {
+    struct arm_gpio_dev_t *gpio_dev;
+    struct arm_mps2_io_dev_t *mps2_io_dev;
+    uint32_t pin_number;
+    PinDirection direction;
+} gpio_t;
+
 struct gpio_irq_s {
-    uint32_t ch;
+    struct arm_gpio_dev_t *gpio_dev;
+    uint32_t pin_number;             /* Pin number inside the GPIO */
+    uint32_t exp_pin_number;         /* Pin number on the expension port */
+    IRQn_Type irq_number;            /* IRQ number of the GPIO interrupt of
+                                        this pin */
 };
 
 struct port_s {
-    __IO uint32_t *reg_dir;
-    __IO uint32_t *reg_dirclr;
-    __IO uint32_t *reg_out;
-    __IO  uint32_t *reg_in;
-    PortName port;
-    uint32_t mask;
+    struct arm_gpio_dev_t *gpio_dev;
 };
 
 struct serial_s {
-    CMSDK_UART_TypeDef *uart;
-    int index;
+    struct arm_uart_dev_t *uart;
+    UARTName index;
+    IRQn_Type irq_number;               /* IRQ number of the RX interrupt for
+                                            this UART device */
 };
 
 struct i2c_s {
@@ -58,21 +68,15 @@
 };
 
 struct spi_s {
-    MPS2_SSP_TypeDef *spi;
-};
-
-struct clcd_s {
-    MPS2_SSP_TypeDef *clcd;
+    struct spi_pl022_dev_t *spi;
 };
 
 struct analogin_s {
     uint16_t ctrl_register;  /* Control bits with the channel identifier */
 };
 
-#include "gpio_object.h"
-
 #ifdef __cplusplus
 }
 #endif
 
-#endif
+#endif /* __MBED_OBJECTS_H__ */

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/pinmap.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/pinmap.c	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
+ * Copyright (c) 2006-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -16,40 +16,64 @@
 #include "mbed_assert.h"
 #include "pinmap.h"
 #include "mbed_error.h"
-
-#define GET_GPIO_PIN_POS(pin)  (pin & 0x0F)  /* pin % 16 */
-#define GET_GPIO_MAP_NUM(pin)  (pin >> 4)    /* pin / 16 */
-#define GPIO_NUM               4
-
-static CMSDK_GPIO_TypeDef* GPIO_MAP[GPIO_NUM] = {
-    CMSDK_GPIO0,
-    CMSDK_GPIO1,
-    CMSDK_GPIO2,
-    CMSDK_GPIO3
-};
+#include "objects.h"
 
 void pin_function(PinName pin, int function)
 {
-    CMSDK_GPIO_TypeDef* p_gpio_map = 0;
+    struct arm_gpio_dev_t *gpio_dev;
+    uint32_t flags;
 
-    MBED_ASSERT(pin != (PinName)NC);
+    MBED_ASSERT(pin != NC);
 
+    /* The pin has to be a GPIO pin */
     if (pin >= EXP0 && pin <= EXP51) {
-        if (function == ALTERNATE_FUNC) {
-            p_gpio_map = GPIO_MAP[GET_GPIO_MAP_NUM(pin)];
-            p_gpio_map->ALTFUNCSET = (1 << GET_GPIO_PIN_POS(pin));
-        } else if(function == GPIO_FUNC) {
-            p_gpio_map = GPIO_MAP[GET_GPIO_MAP_NUM(pin)];
-            p_gpio_map->ALTFUNCCLR = (1 << GET_GPIO_PIN_POS(pin));
-        } else {
-            error("Invalid pin_function value %d", function);
+        switch (function) {
+            case ALTERNATE_FUNC:
+                flags = ARM_GPIO_PIN_DISABLE;
+                break;
+            case GPIO_FUNC:
+                flags = ARM_GPIO_PIN_ENABLE;
+                break;
+            default:
+                return;
         }
+
+        switch (GPIO_DEV_NUMBER(pin)) {
+#ifdef ARM_GPIO0
+        case GPIO0_NUMBER:
+            gpio_dev = &ARM_GPIO0_DEV;
+            break;
+#endif /* ARM_GPIO0 */
+#ifdef ARM_GPIO1
+        case GPIO1_NUMBER:
+            gpio_dev = &ARM_GPIO1_DEV;
+            break;
+#endif /* ARM_GPIO1 */
+#ifdef ARM_GPIO2
+        case GPIO2_NUMBER:
+            gpio_dev = &ARM_GPIO2_DEV;
+            break;
+#endif /* ARM_GPIO2 */
+#ifdef ARM_GPIO3
+        case GPIO3_NUMBER:
+            gpio_dev = &ARM_GPIO3_DEV;
+            break;
+#endif /* ARM_GPIO3 */
+        default:
+            error("GPIO %d, associated with expansion pin %d, is disabled",
+                  pin, GPIO_DEV_NUMBER(pin));
+            return;
+        }
+
+        arm_gpio_init(gpio_dev);
+        (void)arm_gpio_config(gpio_dev, ARM_GPIO_ACCESS_PIN,
+                              GPIO_PIN_NUMBER(pin), flags);
     }
 }
 
 void pin_mode(PinName pin, PinMode mode)
 {
-    MBED_ASSERT(pin != (PinName)NC);
+    MBED_ASSERT(pin != NC);
 
-    /* Pin modes configuration is not supported */
+    /* PinMode is not supported */
 }

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/port_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/port_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
+ * Copyright (c) 2006-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -13,86 +13,90 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+#include <stddef.h>
 #include "port_api.h"
-#include "pinmap.h"
-#include "gpio_api.h"
-
-#define MAX_GPIO_PINS  16
+#include "objects.h"
+#include "mbed_error.h"
 
 PinName port_pin(PortName port, int pin_n)
 {
-    if (pin_n < 0 || pin_n > MAX_GPIO_PINS) {
-        error("Invalid GPIO pin number %d", pin_n);
+    if (pin_n < 0 || pin_n >= PINS_PER_GPIO ||
+        ((port == Port3) && (pin_n >= GPIO3_PIN_NUMBER))) {
+        return NC;
     }
 
-    return (PinName)((port << PORT_SHIFT) | pin_n);
+    return (PINS_PER_GPIO * port + pin_n);
 }
 
 void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
 {
-    uint32_t i;
-    CMSDK_GPIO_TypeDef *port_reg;
+    struct arm_gpio_dev_t *gpio_dev;
+    uint32_t flags = ARM_GPIO_PIN_ENABLE;
 
     switch (port) {
-        case Port0:
-            port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO0_BASE);
-            break;
-        case Port1:
-            port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO1_BASE);
-            break;
-        case Port2:
-            port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO2_BASE);
-            break;
-        case Port3:
-            port_reg = (CMSDK_GPIO_TypeDef *)(CMSDK_GPIO3_BASE);
-            break;
+#ifdef ARM_GPIO0
+    case Port0:
+        gpio_dev = &ARM_GPIO0_DEV;
+        break;
+#endif /* ARM_GPIO0 */
+#ifdef ARM_GPIO1
+    case Port1:
+        gpio_dev = &ARM_GPIO1_DEV;
+        break;
+#endif /* ARM_GPIO1 */
+#ifdef ARM_GPIO2
+    case Port2:
+        gpio_dev = &ARM_GPIO2_DEV;
+        break;
+#endif /* ARM_GPIO2 */
+#ifdef ARM_GPIO3
+    case Port3:
+        gpio_dev = &ARM_GPIO3_DEV;
+        break;
+#endif /* ARM_GPIO3 */
+    default:
+        error("Port%d is not enabled", port);
+        return;
     }
 
-    obj->port       = port;
-    obj->mask       = mask;
-    obj->reg_in     = &port_reg->DATAOUT;
-    obj->reg_dir    = &port_reg->OUTENABLESET;
-    obj->reg_dirclr = &port_reg->OUTENABLECLR;
+    arm_gpio_init(gpio_dev);
+    obj->gpio_dev = gpio_dev;
+
+    arm_gpio_set_port_mask(gpio_dev, mask);
 
-    /* The function is set per pin: reuse gpio logic */
-    for (i=0; i < MAX_GPIO_PINS; i++) {
-        if (obj->mask & (1<<i)) {
-            gpio_set(port_pin(obj->port, i));
-        }
+    switch (dir) {
+    case PIN_INPUT:
+        flags |= ARM_GPIO_INPUT;
+        break;
+    case PIN_OUTPUT:
+        flags |= ARM_GPIO_OUTPUT;
+        break;
+    /* default: not added to force to cover all enumeration cases */
     }
 
-    port_dir(obj, dir);
+    (void)arm_gpio_config(gpio_dev, ARM_GPIO_ACCESS_PORT, ARG_NOT_USED, flags);
 }
 
 void port_mode(port_t *obj, PinMode mode)
 {
-    uint32_t i;
-    /* The mode is set per pin: reuse pinmap logic */
-    for (i=0; i < MAX_GPIO_PINS; i++) {
-        if (obj->mask & (1 << i)) {
-            pin_mode(port_pin(obj->port, i), mode);
-        }
-    }
+    /* PinMode is not supported */
 }
 
 void port_dir(port_t *obj, PinDirection dir)
 {
-    switch (dir) {
-        case PIN_INPUT:
-            *obj->reg_dir &= ~obj->mask;
-            break;
-        case PIN_OUTPUT:
-            *obj->reg_dir |= obj->mask;
-            break;
-    }
+    uint32_t flags = (dir == PIN_OUTPUT) ? ARM_GPIO_OUTPUT : ARM_GPIO_INPUT;
+    (void)arm_gpio_config(obj->gpio_dev, ARM_GPIO_ACCESS_PORT, ARG_NOT_USED,
+                          flags);
 }
 
 void port_write(port_t *obj, int value)
 {
-    *obj->reg_in = value;
+    (void)arm_gpio_write(obj->gpio_dev, ARM_GPIO_ACCESS_PORT, ARG_NOT_USED,
+                         (uint32_t)value);
 }
 
 int port_read(port_t *obj)
 {
-    return (*obj->reg_in);
+    return (int)arm_gpio_read(obj->gpio_dev, ARM_GPIO_ACCESS_PORT,
+                              ARG_NOT_USED);
 }

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
+ * Copyright (c) 2006-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -20,174 +20,138 @@
 #include <stdlib.h>
 
 #include "serial_api.h"
-#include "cmsis.h"
 #include "pinmap.h"
 #include "mbed_error.h"
 #include "gpio_api.h"
+#include "platform_devices.h"
 
 /******************************************************************************
  * INITIALIZATION
  ******************************************************************************/
 
+#define STDIO_UART_NOT_INITED 0
+#define STDIO_UART_INITED     1
+#define UART_NUMBER           5
+
+struct uart_irq_t {
+    uart_irq_handler handler;
+    uint32_t id;
+};
+
 static const PinMap PinMap_UART_TX[] = {
-    {MCC_TX  , UART_0, 0},
-    {USBTX   , UART_1, 0},
-    {SH0_TX  , UART_2, ALTERNATE_FUNC},
-    {SH1_TX  , UART_3, ALTERNATE_FUNC},
-    {XB_TX   , UART_4, ALTERNATE_FUNC},
-    {NC      , NC    , 0}
+    {MCC_TX, UART_0, 0},
+    {USBTX,  UART_1, 0},
+    {SH0_TX, UART_2, ALTERNATE_FUNC},
+    {SH1_TX, UART_3, ALTERNATE_FUNC},
+    {XB_TX,  UART_4, ALTERNATE_FUNC},
+    {NC,     NC,     0}
 };
 
 static const PinMap PinMap_UART_RX[] = {
-    {MCC_RX  , UART_0, 0},
-    {USBRX   , UART_1, 0},
-    {SH0_RX  , UART_2, ALTERNATE_FUNC},
-    {SH1_RX  , UART_3, ALTERNATE_FUNC},
-    {XB_RX   , UART_4, ALTERNATE_FUNC},
-    {NC      , NC    , 0}
+    {MCC_RX, UART_0, 0},
+    {USBRX,  UART_1, 0},
+    {SH0_RX, UART_2, ALTERNATE_FUNC},
+    {SH1_RX, UART_3, ALTERNATE_FUNC},
+    {XB_RX,  UART_4, ALTERNATE_FUNC},
+    {NC,     NC,     0}
 };
 
-#define UART_NUM    5
+/* Handlers registered */
+static struct uart_irq_t uart_irq[UART_NUMBER];
 
-static uart_irq_handler irq_handler;
-
-int stdio_uart_inited = 0;
+/* Global variables needed for mbed */
+int stdio_uart_inited = STDIO_UART_NOT_INITED;
 serial_t stdio_uart;
 
-struct serial_global_data_s {
-    uint32_t serial_irq_id;
-    gpio_t sw_rts, sw_cts;
-    uint8_t count, rx_irq_set_flow, rx_irq_set_api;
-};
+/*
+ * Fill the serial_obj structure with good elements.
+ */
+static uint32_t fill_serial_object(struct serial_s *serial_obj, PinName tx,
+                                   PinName rx)
+{
+    UARTName uart_peripheral;
+
+    if (serial_obj == NULL) {
+        error("serial_s structure is NULL");
+        return 1;
+    }
+
+    uart_peripheral = pinmap_merge(pinmap_peripheral(tx, PinMap_UART_TX),
+                                   pinmap_peripheral(rx, PinMap_UART_RX));
 
-static struct serial_global_data_s uart_data[UART_NUM];
+    switch (uart_peripheral) {
+#ifdef ARM_UART0
+    case UART_0:
+        serial_obj->uart = &ARM_UART0_DEV;
+        serial_obj->index = UART_0;
+        serial_obj->irq_number = UART0_IRQn;
+        /* Fill stdio_uart global variable with these settings */
+        memcpy(&stdio_uart, serial_obj, sizeof(struct serial_s));
+        stdio_uart_inited = STDIO_UART_INITED;
+        return 0;
+#endif /* ARM_UART0 */
+#ifdef ARM_UART1
+    case UART_1:
+        serial_obj->uart = &ARM_UART1_DEV;
+        serial_obj->index = UART_1;
+        serial_obj->irq_number = UART1_IRQn;
+        return 0;
+#endif /* ARM_UART1 */
+#ifdef ARM_UART2
+    case UART_2:
+        serial_obj->uart = &ARM_UART2_DEV;
+        serial_obj->index = UART_2;
+        serial_obj->irq_number = UART2_IRQn;
+        return 0;
+#endif /* ARM_UART2 */
+#ifdef ARM_UART3
+    case UART_3:
+        serial_obj->uart = &ARM_UART3_DEV;
+        serial_obj->index = UART_3;
+        serial_obj->irq_number = UART3_IRQn;
+        return 0;
+#endif /* ARM_UART3 */
+#ifdef ARM_UART4
+    case UART_4:
+        serial_obj->uart = &ARM_UART4_DEV;
+        serial_obj->index = UART_4;
+        serial_obj->irq_number = UART4_IRQn;
+        return 0;
+#endif /* ARM_UART4 */
+    default:
+        error("can not assign a valid UART peripheral to TX and RX pins given");
+        return 1;
+    }
+}
 
 void serial_init(serial_t *obj, PinName tx, PinName rx)
 {
-    uint32_t uart_ctrl = 0;
-
-    /* Determine the UART to use */
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-    UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-
-    if ((int)uart == NC) {
-        error("Serial pinout mapping failed");
+    if (fill_serial_object(obj, tx, rx) != 0) {
         return;
     }
 
-    obj->uart = (CMSDK_UART_TypeDef *)uart;
-
-    if (tx != NC) {
-        uart_ctrl = 0x01;   /* TX enable */
-    }
-    if (rx != NC) {
-        uart_ctrl |= 0x02;  /* RX enable */
-    }
-
-    switch (uart) {
-        case UART_0:
-            CMSDK_UART0->CTRL = uart_ctrl;
-            obj->index = 0;
-            break;
-        case UART_1:
-            CMSDK_UART1->CTRL = uart_ctrl;
-            obj->index = 1;
-            break;
-        case UART_2:
-            CMSDK_UART2->CTRL = 0;
-            obj->index = 2;
-            pin_function(tx, ALTERNATE_FUNC);
-            pin_function(rx, ALTERNATE_FUNC);
-            CMSDK_UART2->CTRL = uart_ctrl;
-            break;
-        case UART_3:
-            CMSDK_UART3->CTRL = 0;
-            obj->index = 3;
-            pin_function(tx, ALTERNATE_FUNC);
-            pin_function(rx, ALTERNATE_FUNC);
-            CMSDK_UART3->CTRL = uart_ctrl;
-            break;
-        case UART_4:
-            CMSDK_UART4->CTRL = 0;
-            obj->index = 4;
-            pin_function(tx, ALTERNATE_FUNC);
-            pin_function(rx, ALTERNATE_FUNC);
-            CMSDK_UART4->CTRL = uart_ctrl;
-            break;
-    }
-
-    /* Set default baud rate and format */
-    serial_baud(obj, 9600);
+    (void)arm_uart_init(obj->uart, SystemCoreClock);
 
     /*
-     *  The CMSDK APB UART doesn't have support for flow control.
-     *  Ref. DDI0479C_cortex_m_system_design_kit_r1p0_trm.pdf
+     * If tx and rx pins are not linked to a GPIO (like for UART0),
+     * pin_function will have no effect.
      */
-    uart_data[obj->index].sw_rts.pin = NC;
-    uart_data[obj->index].sw_cts.pin = NC;
-
-    if (uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-
-    /* Clear UART */
-    serial_clear(obj);
+    pin_function(tx, pinmap_function(tx, PinMap_UART_TX));
+    pin_function(rx, pinmap_function(rx, PinMap_UART_RX));
 }
 
 void serial_free(serial_t *obj)
 {
-      uart_data[obj->index].serial_irq_id = 0;
+    uart_irq[obj->index].id = 0;
+    uart_irq[obj->index].handler = 0;
 }
 
 void serial_baud(serial_t *obj, int baudrate)
 {
-    /*
-     * The MPS2 has a simple divider to control the baud rate.
-     * The formula is:
-     * Baudrate = PCLK / BAUDDIV  where  PCLK = SystemCoreClock and
-     *                                   BAUDDIV is the desire baudrate
-     *
-     * So, if the desired baud rate is 9600 the calculation will be:
-     * Baudrate = SystemCoreClock / 9600;
-     */
-
-    /* Check to see if minimum baud value entered */
-    int baudrate_div = 0;
-
-    if (baudrate == 0) {
-        error("Invalid baudrate value");
-        return;
+    if (arm_uart_set_baudrate(obj->uart, (uint32_t)baudrate) !=
+        ARM_UART_ERR_NONE) {
+        error("Invalid baudrate value or uart not initialized");
     }
-
-    baudrate_div = SystemCoreClock / baudrate;
-
-    if (baudrate >= 16) {
-        switch ((int)obj->uart) {
-            case UART_0:
-                CMSDK_UART0->BAUDDIV = baudrate_div;
-                break;
-            case UART_1:
-                CMSDK_UART1->BAUDDIV = baudrate_div;
-                break;
-            case UART_2:
-                CMSDK_UART2->BAUDDIV = baudrate_div;
-                break;
-            case UART_3:
-                CMSDK_UART3->BAUDDIV = baudrate_div;
-                break;
-            case UART_4:
-                CMSDK_UART4->BAUDDIV = baudrate_div;
-                break;
-            default:
-                error("Invalid uart object");
-                break;
-        }
-    } else {
-        error("Invalid baudrate value");
-    }
-
 }
 
 void serial_format(serial_t *obj, int data_bits,
@@ -204,138 +168,160 @@
 /******************************************************************************
  * INTERRUPTS HANDLING
  ******************************************************************************/
-static inline void uart_irq(uint32_t intstatus, uint32_t index,
-                            CMSDK_UART_TypeDef *puart)
+#ifdef ARM_UART0
+void UART0_IRQHandler()
 {
-    SerialIrq irq_type;
-
-    switch (intstatus) {
-        case 1:
-            irq_type = TxIrq;
+    enum arm_uart_irq_t irq = arm_uart_get_interrupt_status(&ARM_UART0_DEV);
+    arm_uart_clear_interrupt(&ARM_UART0_DEV, irq);
+    if(uart_irq[UART_0].handler) {
+        switch(irq) {
+        case ARM_UART_IRQ_RX:
+            uart_irq[UART_0].handler(uart_irq[UART_0].id, RxIrq);
             break;
-        case 2:
-            irq_type = RxIrq;
+        case ARM_UART_IRQ_TX:
+            uart_irq[UART_0].handler(uart_irq[UART_0].id, TxIrq);
             break;
+        case ARM_UART_IRQ_COMBINED:
+            uart_irq[UART_0].handler(uart_irq[UART_0].id, RxIrq);
+            uart_irq[UART_0].handler(uart_irq[UART_0].id, TxIrq);
+            break;
+        case ARM_UART_IRQ_NONE:
         default:
-            return;
-    }
-
-    if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
-        gpio_write(&uart_data[index].sw_rts, 1);
-        /* Disable interrupt if it wasn't enabled by the application */
-        if (!uart_data[index].rx_irq_set_api) {
-            /* Disable Rx interrupt */
-            puart->CTRL &= ~(CMSDK_UART_CTRL_RXIRQEN_Msk);
+            break;
         }
     }
+}
+#endif /* ARM_UART0 */
 
-    if (uart_data[index].serial_irq_id != 0) {
-        if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api)) {
-            irq_handler(uart_data[index].serial_irq_id, irq_type);
+#ifdef ARM_UART1
+void UART1_IRQHandler()
+{
+    enum arm_uart_irq_t irq = arm_uart_get_interrupt_status(&ARM_UART1_DEV);
+    arm_uart_clear_interrupt(&ARM_UART1_DEV, irq);
+    if(uart_irq[UART_1].handler) {
+        switch(irq) {
+        case ARM_UART_IRQ_RX:
+            uart_irq[UART_1].handler(uart_irq[UART_1].id, RxIrq);
+            break;
+        case ARM_UART_IRQ_TX:
+            uart_irq[UART_1].handler(uart_irq[UART_1].id, TxIrq);
+            break;
+        case ARM_UART_IRQ_COMBINED:
+            uart_irq[UART_1].handler(uart_irq[UART_1].id, RxIrq);
+            uart_irq[UART_1].handler(uart_irq[UART_1].id, TxIrq);
+            break;
+        case ARM_UART_IRQ_NONE:
+        default:
+            break;
         }
     }
+}
+#endif /* ARM_UART1 */
 
-    if (irq_type == TxIrq) {
-        /* Clear the TX interrupt Flag */
-        puart->INTCLEAR |= 0x01;
-    } else {
-        /* Clear the Rx interupt Flag */
-        puart->INTCLEAR |= 0x02;
+#ifdef ARM_UART2
+void UART2_IRQHandler()
+{
+    enum arm_uart_irq_t irq = arm_uart_get_interrupt_status(&ARM_UART2_DEV);
+    arm_uart_clear_interrupt(&ARM_UART2_DEV, irq);
+    if(uart_irq[UART_2].handler) {
+        switch(irq) {
+        case ARM_UART_IRQ_RX:
+            uart_irq[UART_2].handler(uart_irq[UART_2].id, RxIrq);
+            break;
+        case ARM_UART_IRQ_TX:
+            uart_irq[UART_2].handler(uart_irq[UART_2].id, TxIrq);
+            break;
+        case ARM_UART_IRQ_COMBINED:
+            uart_irq[UART_2].handler(uart_irq[UART_2].id, RxIrq);
+            uart_irq[UART_2].handler(uart_irq[UART_2].id, TxIrq);
+            break;
+        case ARM_UART_IRQ_NONE:
+        default:
+            break;
+        }
     }
 }
-
-void uart0_irq()
-{
-    uart_irq(CMSDK_UART0->INTSTATUS & 0x3, 0, (CMSDK_UART_TypeDef*)CMSDK_UART0);
-}
-
-void uart1_irq()
-{
-    uart_irq(CMSDK_UART1->INTSTATUS & 0x3, 1, (CMSDK_UART_TypeDef*)CMSDK_UART1);
-}
+#endif /* ARM_UART2 */
 
-void uart2_irq()
+#ifdef ARM_UART3
+void UART3_IRQHandler()
 {
-    uart_irq(CMSDK_UART2->INTSTATUS & 0x3, 2, (CMSDK_UART_TypeDef*)CMSDK_UART2);
+    enum arm_uart_irq_t irq = arm_uart_get_interrupt_status(&ARM_UART3_DEV);
+    arm_uart_clear_interrupt(&ARM_UART3_DEV, irq);
+    if(uart_irq[UART_3].handler) {
+        switch(irq) {
+        case ARM_UART_IRQ_RX:
+            uart_irq[UART_3].handler(uart_irq[UART_3].id, RxIrq);
+            break;
+        case ARM_UART_IRQ_TX:
+            uart_irq[UART_3].handler(uart_irq[UART_3].id, TxIrq);
+            break;
+        case ARM_UART_IRQ_COMBINED:
+            uart_irq[UART_3].handler(uart_irq[UART_3].id, RxIrq);
+            uart_irq[UART_3].handler(uart_irq[UART_3].id, TxIrq);
+            break;
+        case ARM_UART_IRQ_NONE:
+        default:
+            break;
+        }
+    }
 }
+#endif /* ARM_UART3 */
 
-void uart3_irq() {
-    uart_irq(CMSDK_UART3->INTSTATUS & 0x3, 3, (CMSDK_UART_TypeDef*)CMSDK_UART3);
+#ifdef ARM_UART4
+void UART4_IRQHandler()
+{
+    enum arm_uart_irq_t irq = arm_uart_get_interrupt_status(&ARM_UART4_DEV);
+    arm_uart_clear_interrupt(&ARM_UART4_DEV, irq);
+    if(uart_irq[UART_4].handler) {
+        switch(irq) {
+        case ARM_UART_IRQ_RX:
+            uart_irq[UART_4].handler(uart_irq[UART_4].id, RxIrq);
+            break;
+        case ARM_UART_IRQ_TX:
+            uart_irq[UART_4].handler(uart_irq[UART_4].id, TxIrq);
+            break;
+        case ARM_UART_IRQ_COMBINED:
+            uart_irq[UART_4].handler(uart_irq[UART_4].id, RxIrq);
+            uart_irq[UART_4].handler(uart_irq[UART_4].id, TxIrq);
+            break;
+        case ARM_UART_IRQ_NONE:
+        default:
+            break;
+        }
+    }
 }
-
-void uart4_irq() {
-    uart_irq(CMSDK_UART4->INTSTATUS & 0x3, 4, (CMSDK_UART_TypeDef*)CMSDK_UART4);
-}
+#endif /* ARM_UART4 */
 
 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
 {
-    irq_handler = handler;
-    uart_data[obj->index].serial_irq_id = id;
-}
-
-static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable)
-{
-
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-
-    switch ((int)obj->uart) {
-        case UART_0:
-            irq_n = UART0_IRQn;
-            vector = (uint32_t)&uart0_irq;
-            break;
-        case UART_1:
-            irq_n = UART1_IRQn;
-            vector = (uint32_t)&uart1_irq;
-            break;
-        case UART_2:
-            irq_n = UART2_IRQn;
-            vector  = (uint32_t)&uart2_irq;
-            break;
-        case UART_3:
-            irq_n = UART3_IRQn;
-            vector  = (uint32_t)&uart3_irq;
-            break;
-        case UART_4:
-            irq_n = UART4_IRQn;
-            vector  = (uint32_t)&uart4_irq;
-            break;
-    }
-
-    if (enable) {
-        if (irq == TxIrq) {
-            /* Set TX interrupt enable in CTRL REG */
-            obj->uart->CTRL |= CMSDK_UART_CTRL_TXIRQEN_Msk;
-        }  else {
-            /* Set Rx interrupt on in CTRL REG */
-            obj->uart->CTRL |= CMSDK_UART_CTRL_RXIRQEN_Msk;
-        }
-        NVIC_SetVector(irq_n, vector);
-        NVIC_EnableIRQ(irq_n);
-    } else if ((irq == TxIrq) ||
-               (uart_data[obj->index].rx_irq_set_api
-                + uart_data[obj->index].rx_irq_set_flow == 0)) {
-         /* Disable IRQ */
-        int all_disabled = 0;
-        SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
-
-        obj->uart->CTRL &= ~(1 << (irq + 2));
-
-        all_disabled = (obj->uart->CTRL & (1 << (other_irq + 2))) == 0;
-
-        if (all_disabled) {
-            NVIC_DisableIRQ(irq_n);
-        }
-    }
+    uart_irq[obj->index].handler = handler;
+    uart_irq[obj->index].id = id;
 }
 
 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
 {
-    if (RxIrq == irq) {
-        uart_data[obj->index].rx_irq_set_api = enable;
+    switch (irq) {
+    case RxIrq:
+        if (enable) {
+            NVIC_EnableIRQ(obj->irq_number);
+            (void)arm_uart_irq_rx_enable(obj->uart);
+        } else {
+            arm_uart_irq_rx_disable(obj->uart);
+            NVIC_DisableIRQ(obj->irq_number);
+        }
+        break;
+    case TxIrq:
+        if (enable) {
+            NVIC_EnableIRQ(obj->irq_number);
+            (void)arm_uart_irq_tx_enable(obj->uart);
+        } else {
+            arm_uart_irq_tx_disable(obj->uart);
+            NVIC_DisableIRQ(obj->irq_number);
+        }
+        break;
     }
-
-    serial_irq_set_internal(obj, irq, enable);
+    /* default: not added to force to cover all enumeration cases */
 }
 
 /******************************************************************************
@@ -343,34 +329,33 @@
  ******************************************************************************/
 int serial_getc(serial_t *obj)
 {
-    while (serial_readable(obj) == 0) {
-        /* NOP */
-    }
+    uint8_t byte = 0;
 
-    return obj->uart->DATA;
+    while (!serial_readable(obj)){};
+    (void)arm_uart_read(obj->uart, &byte);
+
+    return (int)byte;
 }
 
 void serial_putc(serial_t *obj, int c)
 {
-    while (serial_writable(obj)) {
-        /* NOP */
-    }
-    obj->uart->DATA = c;
+    while (!serial_writable(obj)){};
+    (void)arm_uart_write(obj->uart, (int)c);
 }
 
 int serial_readable(serial_t *obj)
 {
-    return obj->uart->STATE & 0x2;
+    return arm_uart_rx_ready(obj->uart);
 }
 
 int serial_writable(serial_t *obj)
 {
-    return obj->uart->STATE & 0x1;
+    return arm_uart_tx_ready(obj->uart);
 }
 
 void serial_clear(serial_t *obj)
 {
-    obj->uart->DATA = 0x00;
+    (void)arm_uart_write(obj->uart, 0x00);
 }
 
 void serial_pinout_tx(PinName tx)
@@ -395,7 +380,8 @@
      */
     error("serial_break_clear function not supported");
 }
-void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow,
+                                PinName txflow)
 {
     /*
      *  The CMSDK APB UART doesn't have support for flow control.

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/spi_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/spi_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
+ * Copyright (c) 2017-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -13,282 +13,253 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-#include <math.h>
 
 #include "spi_api.h"
-#include "spi_def.h"
-#include "cmsis.h"
 #include "pinmap.h"
 #include "mbed_error.h"
 #include "mbed_wait_api.h"
+#include "platform_devices.h"
 
-#define SPI_PL022_MIN_SSPCPSR_VALUE  2
-#define SPI_PL022_MAX_SSPCPSR_VALUE  254
-#define SPI_PL022_MAX_SRC_VALUE      255
-#define SPI_PL022_SSPCR0_SCR_POS     8
-#define SPI_PL022_SSPCR0_SCR_MSK     (0xFFul<<SPI_PL022_SSPCR0_SCR_POS)
 
 static const PinMap PinMap_SPI_SCLK[] = {
-    {SPI_SCLK         , SPI_0, 0},
-    {CLCD_SCLK        , SPI_1, 0},
-    {ADC_SCLK         , SPI_2, ALTERNATE_FUNC},
-    {SHIELD_0_SPI_SCK , SPI_3, ALTERNATE_FUNC},
-    {SHIELD_1_SPI_SCK , SPI_4, ALTERNATE_FUNC},
-    {NC               , NC   , 0}
+    {SPI_SCLK,         SPI_0, 0},
+    {CLCD_SCLK,        SPI_1, 0},
+    {ADC_SCLK,         SPI_2, ALTERNATE_FUNC},
+    {SHIELD_0_SPI_SCK, SPI_3, ALTERNATE_FUNC},
+    {SHIELD_1_SPI_SCK, SPI_4, ALTERNATE_FUNC},
+    {NC,               NC,    0}
 };
 
 static const PinMap PinMap_SPI_MOSI[] = {
-    {SPI_MOSI         , SPI_0, 0},
-    {CLCD_MOSI        , SPI_1, 0},
-    {ADC_MOSI         , SPI_2, ALTERNATE_FUNC},
+    {SPI_MOSI,          SPI_0, 0},
+    {CLCD_MOSI,         SPI_1, 0},
+    {ADC_MOSI,          SPI_2, ALTERNATE_FUNC},
     {SHIELD_0_SPI_MOSI, SPI_3, ALTERNATE_FUNC},
     {SHIELD_1_SPI_MOSI, SPI_4, ALTERNATE_FUNC},
-    {NC               , NC   , 0}
+    {NC,                NC,    0}
 };
 
 static const PinMap PinMap_SPI_MISO[] = {
-    {SPI_MISO         , SPI_0, 0},
-    {CLCD_MISO        , SPI_1, 0},
-    {ADC_MISO         , SPI_2, ALTERNATE_FUNC},
+    {SPI_MISO,          SPI_0, 0},
+    {CLCD_MISO,         SPI_1, 0},
+    {ADC_MISO,          SPI_2, ALTERNATE_FUNC},
     {SHIELD_0_SPI_MISO, SPI_3, ALTERNATE_FUNC},
     {SHIELD_1_SPI_MISO, SPI_4, ALTERNATE_FUNC},
-    {NC               , NC   , 0}
+    {NC,                NC,    0}
 };
 
 static const PinMap PinMap_SPI_SSEL[] = {
-    {SPI_SSEL        , SPI_0, 0},
-    {CLCD_SSEL       , SPI_1, 0},
-    {ADC_SSEL        , SPI_2, ALTERNATE_FUNC},
+    {SPI_SSEL,         SPI_0, 0},
+    {CLCD_SSEL,        SPI_1, 0},
+    {ADC_SSEL,         SPI_2, ALTERNATE_FUNC},
     {SHIELD_0_SPI_nCS, SPI_3, ALTERNATE_FUNC},
     {SHIELD_1_SPI_nCS, SPI_4, ALTERNATE_FUNC},
-    {NC              , NC   , 0}
+    {NC,               NC,    0}
 };
 
-static inline int ssp_disable(spi_t *obj);
-static inline int ssp_enable(spi_t *obj);
+/* SPI configuration values */
+#define SPI_BITS_MIN_VALUE          4
+#define SPI_BITS_MAX_VALUE          16
+#define SPI_MODE_PHASE_BIT          0
+#define SPI_MODE_PHASE_BIT_MSK      (0x1ul << SPI_MODE_PHASE_BIT)
+#define SPI_MODE_POLARITY_BIT       1
+#define SPI_MODE_POLARITY_BIT_MSK   (0x1ul << SPI_MODE_POLARITY_BIT)
+#define SPI_MODE_MAX_VALUE_MSK      ((0x1ul << (SPI_MODE_POLARITY_BIT+1))-1)
+
+static uint32_t spi_fill_object(spi_t *obj, PinName mosi, PinName miso,
+                                PinName sclk, PinName ssel)
+{
+    /* Determine the SPI to use */
+    uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
+    uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
+    uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
+    uint32_t spi_index = pinmap_merge(spi_data, spi_cntl);
+    if ((spi_data == (uint32_t)NC) || (spi_index == (uint32_t)NC)) {
+        /* Both miso and mosi or all 4 pins are NC */
+        error("SPI pinout mapping failed");
+        return 1;
+    }
+
+    switch (spi_index) {
+#ifdef ARM_SPI0
+        case SPI_0:
+            obj->spi = &SPI0_PL022_DEV;
+            return 0;
+#endif /* ARM_SPI0 */
+#ifdef ARM_SPI1
+        case SPI_1:
+            obj->spi = &SPI1_PL022_DEV;
+            return 0;
+#endif /* ARM_SPI1 */
+#ifdef ARM_SPI2
+        case SPI_2:
+            obj->spi = &SPI2_PL022_DEV;
+            return 0;
+#endif /* ARM_SPI2 */
+#ifdef ARM_SPI3
+        case SPI_3:
+            obj->spi = &SPI3_PL022_DEV;
+            return 0;
+#endif /* ARM_SPI3 */
+#ifdef ARM_SPI4
+        case SPI_4:
+            obj->spi = &SPI4_PL022_DEV;
+            return 0;
+#endif /* ARM_SPI4 */
+        default:
+            error("Can not assign valid SPI peripheral to the pins given");
+            return 1;
+    }
+}
 
 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
 {
-    /* Determine the SPI to use */
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (MPS2_SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
-    if ((int)obj->spi == NC) {
-        error("SPI pinout mapping failed");
+    if (spi_fill_object(obj, mosi, miso, sclk, ssel) != 0) {
+        return;
     }
 
-    /* Enable power and clocking */
-    switch ((int)obj->spi) {
-        case SPI_0:
-            obj->spi->CR1   = 0;
-            obj->spi->CR0   = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
-            obj->spi->CPSR  = SSP_CPSR_DFLT;
-            obj->spi->IMSC  = 0x8;
-            obj->spi->DMACR = 0;
-            obj->spi->CR1   = SSP_CR1_SSE_Msk;
-            obj->spi->ICR   = 0x3;
-            break;
-        case SPI_1: /* Configure SSP used for LCD */
-            obj->spi->CR1   = 0;                /* Synchronous serial port disable  */
-            obj->spi->DMACR = 0;                /* Disable FIFO DMA                 */
-            obj->spi->IMSC  = 0;                /* Mask all FIFO/IRQ interrupts     */
-            obj->spi->ICR   = ((1ul <<  0) |    /* Clear SSPRORINTR interrupt       */
-                               (1ul <<  1) );   /* Clear SSPRTINTR interrupt        */
-            obj->spi->CR0   = ((7ul <<  0) |    /* 8 bit data size                  */
-                               (0ul <<  4) |    /* Motorola frame format            */
-                               (0ul <<  6) |    /* CPOL = 0                         */
-                               (0ul <<  7) |    /* CPHA = 0                         */
-                               (1ul <<  8) );   /* Set serial clock rate            */
-            obj->spi->CPSR  = (2ul <<  0);      /* set SSP clk to 6MHz (6.6MHz max) */
-            obj->spi->CR1   = ((1ul <<  1) |    /* Synchronous serial port enable   */
-                               (0ul <<  2) );   /* Device configured as master      */
-            break;
-        case SPI_2:  /* Shield ADC SPI */
-        case SPI_3:  /* Shield 0 SPI */
-        case SPI_4:  /* Shield 1 SPI */
-            obj->spi->CR1   = 0;
-            obj->spi->CR0   = SSP_CR0_SCR_DFLT | SSP_CR0_FRF_MOT | SSP_CR0_DSS_8;
-            obj->spi->CPSR  = SSP_CPSR_DFLT;
-            obj->spi->IMSC  = 0x8;
-            obj->spi->DMACR = 0;
-            obj->spi->CR1   = SSP_CR1_SSE_Msk;
-            obj->spi->ICR   = 0x3;
-            /* Set pin function as an alt-function */
-            if (mosi != NC) {
-                pin_function(mosi, ALTERNATE_FUNC);
-            }
-            if (miso != NC) {
-                pin_function(miso, ALTERNATE_FUNC);
-            }
-            if (sclk != NC) {
-                pin_function(sclk, ALTERNATE_FUNC);
-            }
-            if (ssel != NC) {
-                pin_function(ssel, ALTERNATE_FUNC);
-            }
-            break;
+    (void)spi_pl022_init(obj->spi, SystemCoreClock);
+
+    /*
+     * If the pins are not linked to a GPIO,
+     * pin_function will have no effect.
+     * Mosi, miso and ssel pins are allowed to be NC,
+     * call pin_function only if they are connected
+     */
+    if (mosi != NC) {
+        pin_function(mosi, pinmap_function(mosi, PinMap_SPI_MOSI));
     }
-
-    /* Set default format and frequency */
-    if (ssel == NC) {
-        spi_format(obj, 8, 0, 0);  /* 8 bits, mode 0, master */
-    } else {
-        spi_format(obj, 8, 0, 1);  /* 8 bits, mode 0, slave */
+    if (miso != NC) {
+        pin_function(miso, pinmap_function(miso, PinMap_SPI_MISO));
     }
-
-    /* Default SPI frequency */
-    spi_frequency(obj, 1000000);
-
-    /* Enable the ssp channel */
-    ssp_enable(obj);
+    if (ssel != NC) {
+        pin_function(ssel, pinmap_function(ssel, PinMap_SPI_SSEL));
+    }
+    pin_function(sclk, pinmap_function(sclk, PinMap_SPI_SCLK));
 }
 
 void spi_free(spi_t *obj)
 {
-    error("SPI free error");
+    /* No need to implement free function, this API is intentionally blank */
 }
 
 void spi_format(spi_t *obj, int bits, int mode, int slave)
 {
-    ssp_disable(obj);
-    if (!(bits >= 4 && bits <= 16) || !(mode >= 0 && mode <= 3)) {
+    uint32_t polarity, phase, frame_format;
+    struct spi_pl022_ctrl_cfg_t ctrl_cfg;
+
+    if (!(bits >= SPI_BITS_MIN_VALUE && bits <= SPI_BITS_MAX_VALUE) ||
+        (mode & ~SPI_MODE_MAX_VALUE_MSK)) {
         error("SPI format error");
+        return;
     }
 
-    int polarity = (mode & 0x2) ? 1 : 0;
-    int phase = (mode & 0x1) ? 1 : 0;
-
-    // set it up
-    int DSS = bits - 1;            /* DSS (data select size) */
-    int SPO = (polarity) ? 1 : 0;  /* SPO - clock out polarity */
-    int SPH = (phase) ? 1 : 0;     /* SPH - clock out phase */
+    spi_pl022_dev_disable(obj->spi);
+    if (spi_pl022_get_ctrl_cfg(obj->spi, &ctrl_cfg) != 0) {
+        error("SPI not initialized");
+        return;
+    };
 
-    int FRF = 0;                   /* FRF (frame format) = SPI */
-    uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
-    tmp |= DSS << 0
-        | FRF << 4
-        | SPO << 6
-        | SPH << 7;
-    obj->spi->CR0 = tmp;
+    polarity = (mode & SPI_MODE_POLARITY_BIT_MSK) ? 1u : 0;
+    phase = (mode & SPI_MODE_PHASE_BIT_MSK) ? 1u : 0;
+    frame_format = (SPI_PL022_CFG_FRF_MOT << 0 |
+                    polarity << 6 |
+                    phase << 7);
 
-    tmp = obj->spi->CR1;
-    tmp &= ~(0xD);
-    tmp |= 0 << 0                  /* LBM - loop back mode - off */
-        | ((slave) ? 1 : 0) << 2   /* MS  - master slave mode, 1 = slave */
-        | 0 << 3;                  /* SOD - slave output disable - na */
-    obj->spi->CR1 = tmp;
+    ctrl_cfg.frame_format = (uint8_t) frame_format;
+    ctrl_cfg.word_size = (uint8_t) bits;
+    ctrl_cfg.spi_mode =
+                  slave ? SPI_PL022_SLAVE_SELECT : SPI_PL022_MASTER_SELECT;
 
-    ssp_enable(obj);
+    if (spi_pl022_set_ctrl_cfg(obj->spi, &ctrl_cfg) != 0) {
+        error("SPI configuration failed");
+    }
+
+    spi_pl022_dev_enable(obj->spi);
 }
 
 void spi_frequency(spi_t *obj, int hz)
 {
-    uint32_t clkps_dvsr, scr;
-    uint32_t sys_clk = SystemCoreClock;
-
-    for(clkps_dvsr = SPI_PL022_MIN_SSPCPSR_VALUE;
-        clkps_dvsr <= SPI_PL022_MAX_SSPCPSR_VALUE; clkps_dvsr += 2) {
-
-        /* Calculate clock rate based on the new clock prescale divisor */
-        scr = (sys_clk / (clkps_dvsr * hz)) - 1;
+    spi_pl022_dev_disable(obj->spi);
 
-        /* Checks if it can be supported by the divider */
-        if (scr <= SPI_PL022_MAX_SRC_VALUE) {
-            ssp_disable(obj);
-            obj->spi->CPSR = clkps_dvsr;
-            obj->spi->CR0 &= ~SPI_PL022_SSPCR0_SCR_MSK;
-            obj->spi->CR0 |= (scr << SPI_PL022_SSPCR0_SCR_POS);
-            ssp_enable(obj);
-            return;
-        }
+    obj->spi->data->ctrl_cfg.bit_rate = hz;
+    if (spi_pl022_set_sys_clk(obj->spi, SystemCoreClock) != 0) {
+        error("SPI frequency config failed");
     }
 
-    error("Couldn't setup requested SPI frequency %dHz", hz);
-}
-
-static inline int ssp_disable(spi_t *obj)
-{
-    return obj->spi->CR1 &= ~(1 << 1);
-}
-
-static inline int ssp_enable(spi_t *obj)
-{
-    return obj->spi->CR1 |= SSP_CR1_SSE_Msk;
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    return obj->spi->SR & (1 << 2);
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    return obj->spi->SR & SSP_SR_BSY_Msk;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    obj->spi->DR = value;
-    while (ssp_writeable(obj));
-}
-static inline int ssp_read(spi_t *obj)
-{
-    int read_DR = obj->spi->DR;
-    return read_DR;
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+    spi_pl022_dev_enable(obj->spi);
 }
 
 int spi_master_write(spi_t *obj, int value)
 {
-    ssp_write(obj, value);
-    while (obj->spi->SR & SSP_SR_BSY_Msk);  /* Wait for send to finish */
-    return (ssp_read(obj));
+    int32_t rx_data = 0;
+    uint32_t size = 1;
+
+    if(obj->spi->data->ctrl_cfg.word_size > 8) {
+        size = 2;
+    }
+
+    if (spi_pl022_txrx_blocking(obj->spi, &value, &size, &rx_data, &size) ) {
+        return 0;
+    }
+
+    return rx_data;
 }
 
 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
                            char *rx_buffer, int rx_length, char write_fill)
 {
-    int total = (tx_length > rx_length) ? tx_length : rx_length;
-    char out, in;
-
-    for (int i = 0; i < total; i++) {
-        out = (i < tx_length) ? tx_buffer[i] : write_fill;
-        in = spi_master_write(obj, out);
-        if (i < rx_length) {
-            rx_buffer[i] = in;
-        }
+    if (spi_pl022_txrx_blocking(obj->spi, tx_buffer, (uint32_t*)&tx_length,
+                                          rx_buffer, (uint32_t*)&rx_length)) {
+        return 0;
     }
 
-    return total;
+    return ((tx_length > rx_length) ? tx_length : rx_length);
 }
 
 int spi_slave_receive(spi_t *obj)
 {
-    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+    int32_t status = spi_pl022_get_status(obj->spi);
+    /* Rx FIFO not empty and device not busy */
+    int32_t ret = ((status & SPI_PL022_SSPSR_RNE_MSK) &&
+                        !(status & SPI_PL022_SSPSR_BSY_MSK));
+    return ret;
+}
+
+uint8_t spi_get_module(spi_t *obj)
+{
+    if (obj->spi == &SPI0_PL022_DEV) {
+        return SPI_0;
+    } else if (obj->spi == &SPI1_PL022_DEV) {
+        return SPI_1;
+    } else if (obj->spi == &SPI2_PL022_DEV) {
+        return SPI_2;
+    } else if (obj->spi == &SPI3_PL022_DEV) {
+        return SPI_3;
+    } else if (obj->spi == &SPI4_PL022_DEV) {
+        return SPI_4;
+    } else {
+        error("SPI object is not initialized");
+        return (SPI_NC);
+    }
 }
 
 int spi_slave_read(spi_t *obj)
 {
-    return obj->spi->DR;
+    while(spi_slave_receive(obj) == 0) {};
+    return spi_pl022_slave_read(obj->spi);
 }
 
 void spi_slave_write(spi_t *obj, int value)
 {
-    while (ssp_writeable(obj) == 0);
-    obj->spi->DR = value;
+    (void)spi_pl022_write(obj->spi, SPI_PL022_SLAVE_SELECT, &value);
 }
 
 int spi_busy(spi_t *obj)
 {
-    return ssp_busy(obj);
+    int32_t status = spi_pl022_get_status(obj->spi);
+    return (status & SPI_PL022_SSPSR_BSY_MSK);
 }

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/spi_def.h	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,174 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- * ----------------------------------------------------------------
- * File:     spi_def.h
- * Release:  Version 2.0
- * ----------------------------------------------------------------
- *
- *            SSP interface Support
- *            =====================
- */
-
-#define SSPCS_BASE          (0x4002804C)  // SSP chip select register
-#define SSP_BASE            (0x40020000)  // SSP Prime Cell
-
-#define SSPCR0              ((volatile unsigned int *)(SSP_BASE + 0x00))
-#define SSPCR1              ((volatile unsigned int *)(SSP_BASE + 0x04))
-#define SSPDR               ((volatile unsigned int *)(SSP_BASE + 0x08))
-#define SSPSR               ((volatile unsigned int *)(SSP_BASE + 0x0C))
-#define SSPCPSR             ((volatile unsigned int *)(SSP_BASE + 0x10))
-#define SSPIMSC             ((volatile unsigned int *)(SSP_BASE + 0x14))
-#define SSPRIS              ((volatile unsigned int *)(SSP_BASE + 0x18))
-#define SSPMIS              ((volatile unsigned int *)(SSP_BASE + 0x1C))
-#define SSPICR              ((volatile unsigned int *)(SSP_BASE + 0x20))
-#define SSPDMACR            ((volatile unsigned int *)(SSP_BASE + 0x24))
-#define SSPCS               ((volatile unsigned int *)(SSPCS_BASE))
-
-// SSPCR0 Control register 0
-#define SSPCR0_SCR_DFLT     0x0300      // Serial Clock Rate (divide), default set at 3
-#define SSPCR0_SPH          0x0080      // SSPCLKOUT phase
-#define SSPCR0_SPO          0x0040      // SSPCLKOUT polarity
-#define SSPCR0_FRF_MOT      0x0000      // Frame format, Motorola
-#define SSPCR0_DSS_8        0x0007      // Data packet size, 8bits
-#define SSPCR0_DSS_16       0x000F      // Data packet size, 16bits
-
-// SSPCR1 Control register 1
-#define SSPCR1_SOD          0x0008      // Slave Output mode Disable
-#define SSPCR1_MS           0x0004      // Master or Slave mode
-#define SSPCR1_SSE          0x0002      // Serial port enable
-#define SSPCR1_LBM          0x0001      // Loop Back Mode
-
-// SSPSR Status register
-#define SSPSR_BSY           0x0010      // Busy
-#define SSPSR_RFF           0x0008      // Receive  FIFO full
-#define SSPSR_RNE           0x0004      // Receive  FIFO not empty
-#define SSPSR_TNF           0x0002      // Transmit FIFO not full
-#define SSPSR_TFE           0x0001      // Transmit FIFO empty
-
-// SSPCPSR Clock prescale register
-#define SSPCPSR_DFLT        0x0008      // Clock prescale (use with SCR), default set at 8
-
-// SSPIMSC Interrupt mask set and clear register
-#define SSPIMSC_TXIM        0x0008      // Transmit FIFO not Masked
-#define SSPIMSC_RXIM        0x0004      // Receive  FIFO not Masked
-#define SSPIMSC_RTIM        0x0002      // Receive timeout not Masked
-#define SSPIMSC_RORIM       0x0001      // Receive overrun not Masked
-
-// SSPRIS Raw interrupt status register
-#define SSPRIS_TXRIS        0x0008      // Raw Transmit interrupt flag
-#define SSPRIS_RXRIS        0x0004      // Raw Receive  interrupt flag
-#define SSPRIS_RTRIS        0x0002      // Raw Timemout interrupt flag
-#define SSPRIS_RORRIS       0x0001      // Raw Overrun  interrupt flag
-
-// SSPMIS Masked interrupt status register
-#define SSPMIS_TXMIS        0x0008      // Masked Transmit interrupt flag
-#define SSPMIS_RXMIS        0x0004      // Masked Receive  interrupt flag
-#define SSPMIS_RTMIS        0x0002      // Masked Timemout interrupt flag
-#define SSPMIS_RORMIS       0x0001      // Masked Overrun  interrupt flag
-
-// SSPICR Interrupt clear register
-#define SSPICR_RTIC         0x0002      // Clears Timeout interrupt flag
-#define SSPICR_RORIC        0x0001      // Clears Overrun interrupt flag
-
-// SSPDMACR DMA control register
-#define SSPDMACR_TXDMAE     0x0002      // Enable Transmit FIFO DMA
-#define SSPDMACR_RXDMAE     0x0001      // Enable Receive  FIFO DMA
-
-// SPICS register (0=Chip Select low)
-#define SSPCS_nCS1          0x0002      // nCS1  (SPI_nSS)
-
-// SPI defaults
-#define SSPMAXTIME          1000        // Maximum time to wait for SSP (10*10uS)
-
-// EEPROM instruction set
-#define EEWRSR              0x0001      // Write status
-#define EEWRITE             0x0002      // Write data
-#define EEREAD              0x0003      // Read data
-#define EEWDI               0x0004      // Write disable
-#define EEWREN              0x0006      // Write enable
-#define EERDSR              0x0005      // Read status
-
-// EEPROM status register flags
-#define EERDSR_WIP          0x0001      // Write in process
-#define EERDSR_WEL          0x0002      // Write enable latch
-#define EERDSR_BP0          0x0004      // Block protect 0
-#define EERDSR_BP1          0x0008      // Block protect 1
-#define EERDSR_WPEN         0x0080      // Write protect enable
-
- /* ----------------------------------------------------------------
- *
- *            Color LCD Support
- *            =================
- */
-
-// Color LCD Controller Internal Register addresses
-#define LSSPCS_BASE          (0x4002804C)  // LSSP chip select register
-#define LSSP_BASE            (0x40021000)  // LSSP Prime Cell
-
-#define LSSPCR0              ((volatile unsigned int *)(LSSP_BASE + 0x00))
-#define LSSPCR1              ((volatile unsigned int *)(LSSP_BASE + 0x04))
-#define LSSPDR               ((volatile unsigned int *)(LSSP_BASE + 0x08))
-#define LSSPSR               ((volatile unsigned int *)(LSSP_BASE + 0x0C))
-#define LSSPCPSR             ((volatile unsigned int *)(LSSP_BASE + 0x10))
-#define LSSPIMSC             ((volatile unsigned int *)(LSSP_BASE + 0x14))
-#define LSSPRIS              ((volatile unsigned int *)(LSSP_BASE + 0x18))
-#define LSSPMIS              ((volatile unsigned int *)(LSSP_BASE + 0x1C))
-#define LSSPICR              ((volatile unsigned int *)(LSSP_BASE + 0x20))
-#define LSSPDMACR            ((volatile unsigned int *)(LSSP_BASE + 0x24))
-#define LSSPCS               ((volatile unsigned int *)(LSSPCS_BASE))
-
-// LSSPCR0 Control register 0
-#define LSSPCR0_SCR_DFLT    0x0100      // Serial Clock Rate (divide), CLK/(CPSR*(1+SCR))
-#define LSSPCR0_SPH         0x0080      // LSSPCLKOUT phase
-#define LSSPCR0_SPO         0x0040      // LSSPCLKOUT polarity
-#define LSSPCR0_FRF_MOT     0x0000      // Frame format, Motorola
-#define LSSPCR0_DSS_8       0x0007      // Data packet size, 8bits
-#define LSSPCR0_DSS_16      0x000F      // Data packet size, 16bits
-
-// LSSPCR1 Control register 1
-#define LSSPCR1_SOD         0x0008      // Slave Output mode Disable
-#define LSSPCR1_MS          0x0004      // Master or Slave mode
-#define LSSPCR1_SSE         0x0002      // Serial port enable
-#define LSSPCR1_LBM         0x0001      // Loop Back Mode
-
-// LSSPSR Status register
-#define LSSPSR_BSY          0x0010      // Busy
-#define LSSPSR_RFF          0x0008      // Receive  FIFO full
-#define LSSPSR_RNE          0x0004      // Receive  FIFO not empty
-#define LSSPSR_TNF          0x0002      // Transmit FIFO not full
-#define LSSPSR_TFE          0x0001      // Transmit FIFO empty
-
-// LSSPCPSR Clock prescale register
-#define LSSPCPSR_DFLT       0x0002      // Clock prescale (use with SCR)
-
-// SPICS register
-#define LSSPCS_nCS0         0x0001      // nCS0      (CLCD_CS)
-#define LSSPCS_nCS2         0x0004      // nCS2      (CLCD_T_CS)
-#define LCD_RESET           0x0008      // RESET     (CLCD_RESET)
-#define LCD_RS              0x0010      // RS        (CLCD_RS)
-#define LCD_RD              0x0020      // RD        (CLCD_RD)
-#define LCD_BL              0x0040      // Backlight (CLCD_BL_CTRL)
-
-// SPI defaults
-#define LSSPMAXTIME         10000       // Maximum time to wait for LSSP (10*10uS)
-#define LSPI_START          (0x70)      // Start byte for SPI transfer
-#define LSPI_RD             (0x01)      // WR bit 1 within start
-#define LSPI_WR             (0x00)      // WR bit 0 within start
-#define LSPI_DATA           (0x02)      // RS bit 1 within start byte
-#define LSPI_INDEX          (0x00)      // RS bit 0 within start byte
-
-// Screen size
-#define LCD_WIDTH           320         // Screen Width (in pixels)
-#define LCD_HEIGHT          240         // Screen Height (in pixels)

--- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
+ * Copyright (c) 2017-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -14,125 +14,98 @@
  * limitations under the License.
  */
 
-/* This file is derivative of us_ticker.c from BEETLE */
+/**
+ * Elapsed time measure and interval timer in micro-secundum,
+ * servicing \ref us_ticker_api.h, using CMSDK Timer0 \ref CMSDK_TIMER0_DEV.
+ */
 
-#include <stddef.h>
-#include "cmsis.h"
+#include "cmsdk_ticker.h"
 #include "us_ticker_api.h"
-#include "PeripheralNames.h"
+#include "platform_devices.h"
 
-#define TIMER_MAX_VALUE  0
+/**
+ * \brief Convert clocks to us
+ *
+ * \param[in] tick Number of clocks
+ *
+ * \return Number of usec, relative to the timer frequency,
+ *         that a given ammount of ticks equates to.
+ */
+static uint32_t convert_tick_to_us(uint32_t tick)
+{
+    return (tick / (SystemCoreClock / SEC_TO_USEC_MULTIPLIER));
+}
 
-/* Private data */
-struct us_ticker_drv_data_t {
-    uint32_t inited;          /* us ticker initialized */
-    uint32_t overflow_delta;  /* us ticker overflow */
-    uint32_t overflow_limit;  /* us ticker overflow limit */
+/**
+ * \brief Convert us to clock ticks
+ *
+ * \param[in] us Time to convert to clock ticks
+ *
+ * \return Number of clock ticks relative to the timer frequency,
+ *         that a given period of usec equates to.
+ */
+static uint32_t convert_us_to_tick(uint32_t us)
+{
+    return (us * (SystemCoreClock / SEC_TO_USEC_MULTIPLIER));
+}
+
+static const struct tick_cfg_t cfg =
+{
+    .timer_driver = &CMSDK_TIMER0_DEV,
+    .irq_n = TIMER0_IRQn,
+    .interval_callback = &us_ticker_irq_handler,
+    .convert_tick_to_time = &convert_tick_to_us,
+    .convert_time_to_tick = &convert_us_to_tick
 };
 
-static struct us_ticker_drv_data_t us_ticker_drv_data = {
-    .inited = 0,
-    .overflow_delta = 0,
-    .overflow_limit = 0
+static struct tick_data_t data =
+{
+    .is_initialized = false,
+    .cumulated_time = 0,
+    .max_interval_time = 0,
+    .reload_time = 0,
+    .interval_callback_enabled = false,
+    .previous_cumulated_time = 0,
+    .previous_elapsed = 0
 };
 
-
-void __us_ticker_irq_handler(void)
+static struct tick_drv_data_t timer_data =
 {
-    Timer_ClearInterrupt(TIMER1);
-    /*
-     * For each overflow event adds the timer max represented value to
-     * the delta. This allows the us_ticker to keep track of the elapsed
-     * time:
-     * elapsed_time = (num_overflow * overflow_limit) + current_time
-     */
-    us_ticker_drv_data.overflow_delta += us_ticker_drv_data.overflow_limit;
-}
+    .cfg = &cfg,
+    .data = &data
+};
 
 void us_ticker_init(void)
 {
-    uint32_t us_ticker_irqn0 = 0;
-    uint32_t us_ticker_irqn1 = 0;
-
-    if (us_ticker_drv_data.inited) {
-        return;
-    }
-
-    us_ticker_drv_data.inited = 1;
-
-    /* Initialize Timer 0 */
-    Timer_Initialize(TIMER0, TIMER_MAX_VALUE);
-    /* Enable Timer 0 */
-    Timer_Enable(TIMER0);
-
-    /* Initialize Timer 1 */
-    Timer_Initialize(TIMER1, TIMER_MAX_VALUE);
-    /* Enable Timer 1 */
-    Timer_Enable(TIMER1);
-
-    /* Timer 0 get IRQn */
-    us_ticker_irqn0 = Timer_GetIRQn(TIMER0);
-    NVIC_SetVector((IRQn_Type)us_ticker_irqn0, (uint32_t)us_ticker_irq_handler);
-    NVIC_EnableIRQ((IRQn_Type)us_ticker_irqn0);
-
-    /* Timer 1 get IRQn */
-    us_ticker_irqn1 = Timer_GetIRQn(TIMER1);
-    NVIC_SetVector((IRQn_Type)us_ticker_irqn1, (uint32_t)__us_ticker_irq_handler);
-    NVIC_EnableIRQ((IRQn_Type)us_ticker_irqn1);
-
-    /* Timer set interrupt on TIMER1 */
-    Timer_SetInterrupt(TIMER1, TIMER_DEFAULT_RELOAD);
-
-    /*
-     * Set us_ticker Overflow limit. The us_ticker overflow limit is required
-     * to calculated the return value of the us_ticker read function in us
-     * on 32bit.
-     * A 32bit us value cannot be represented directly in the Timer Load
-     * register if it is greater than (0xFFFFFFFF ticks)/TIMER_DIVIDER_US.
-     */
-    us_ticker_drv_data.overflow_limit = Timer_GetReloadValue(TIMER1);
+    cmsdk_ticker_init(&timer_data);
 }
 
 uint32_t us_ticker_read()
 {
-    uint32_t return_value = 0;
-
-    if (!us_ticker_drv_data.inited) {
-        us_ticker_init();
-    }
-
-    return_value = us_ticker_drv_data.overflow_delta + Timer_Read(TIMER1);
-
-    return return_value;
+    return cmsdk_ticker_read(&timer_data);
 }
 
 void us_ticker_set_interrupt(timestamp_t timestamp)
 {
-    uint32_t delta = 0;
-
-    if (!us_ticker_drv_data.inited) {
-        us_ticker_init();
-    }
+    cmsdk_ticker_set_interrupt(&timer_data, timestamp);
+}
 
-    delta = timestamp - us_ticker_read();
+void us_ticker_disable_interrupt(void)
+{
+    cmsdk_ticker_disable_interrupt(&timer_data);
+}
 
-    /* If the event was not in the past enable interrupt */
-    Timer_SetInterrupt(TIMER0, delta);
-
+void us_ticker_clear_interrupt(void)
+{
+    cmsdk_ticker_clear_interrupt(&timer_data);
 }
 
 void us_ticker_fire_interrupt(void)
 {
-    uint32_t us_ticker_irqn1 = Timer_GetIRQn(TIMER1);
-    NVIC_SetPendingIRQ((IRQn_Type)us_ticker_irqn1);
+    cmsdk_ticker_fire_interrupt(&timer_data);
 }
 
-void us_ticker_disable_interrupt(void)
+void TIMER0_IRQHandler(void)
 {
-    Timer_DisableInterrupt(TIMER0);
+    cmsdk_ticker_irq_handler(&timer_data);
 }
-
-void us_ticker_clear_interrupt(void)
-{
-    Timer_ClearInterrupt(TIMER0);
-}

--- a/targets/TARGET_ARM_SSG/mbed_rtx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ARM_SSG/mbed_rtx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* mbed Microcontroller Library
- * Copyright (c) 2016-2017 ARM Limited
+ * Copyright (c) 2016-2018 ARM Limited
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -17,12 +17,20 @@
 #ifndef MBED_MBED_RTX_H
 #define MBED_MBED_RTX_H
 
-#if defined(TARGET_BEETLE) || defined(TARGET_CM3DS_MPS2)
+#if defined(TARGET_BEETLE)
 
 #ifndef INITIAL_SP
 #define INITIAL_SP              (0x20020000UL)
 #endif
 
+#elif defined(TARGET_CM3DS_MPS2)
+
+#include "memory_zones.h"
+
+#ifndef INITIAL_SP
+#define INITIAL_SP              (ZBT_SSRAM23_START + ZBT_SSRAM23_SIZE)
 #endif
 
-#endif  // MBED_MBED_RTX_H
+#endif /* defined(TARGET_...) */
+
+#endif  /* MBED_MBED_RTX_H */

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/flash_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -76,7 +76,7 @@
 };
 
 static const flash_target_config_t flash_target_config = {
-    .page_size   = 0x800,
+    .page_size   = 0x8,                       // minimal programmable unit size
     .flash_start = 0x0,
     .flash_size  = 0x00040000,
     .sectors     = sectors_info,

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/api/us_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2010-2017 Analog Devices, Inc.
+ * Copyright (c) 2010-2018 Analog Devices, Inc.
  *
  * All rights reserved.
  *
@@ -206,7 +206,10 @@
         adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, &tmr2Config);
         adi_tmr_Enable(ADI_TMR_DEVICE_GP2, true);
     } else {
-        us_ticker_irq_handler();
+        tmr2Config.nLoad        = 65535u;
+        tmr2Config.nAsyncLoad   = 65535u;
+        adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, &tmr2Config);
+        adi_tmr_Enable(ADI_TMR_DEVICE_GP2, true);
     }
 }
 
@@ -231,7 +234,11 @@
 
     if (largecnt < 65536u) {
         adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false);
-        event_timer();
+        if (largecnt) {
+            event_timer();
+        } else {
+            us_ticker_irq_handler();
+        }
     }
 }
 
@@ -328,6 +335,7 @@
      *
      */
     calc_event_counts(timestamp);             // use timestamp to calculate largecnt to control number of timer interrupts
+    tmr2Config.ePrescaler   = ADI_TMR_PRESCALER_256;   // TMR2 at 26MHz/256
     event_timer();                            // uses largecnt to initiate timer interrupts
 }
 
@@ -339,7 +347,9 @@
  */
 void us_ticker_fire_interrupt(void)
 {
-    NVIC_SetPendingIRQ(TMR2_EVT_IRQn);
+    largecnt = 1;                              // set a minimal interval so interrupt fire immediately
+    tmr2Config.ePrescaler   = ADI_TMR_PRESCALER_1;   // TMR2 at 26MHz/1
+    event_timer();                             // enable the timer and interrupt
 }
 
 

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/flash_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -74,7 +74,7 @@
 };
 
 static const flash_target_config_t flash_target_config = {
-    .page_size   = 0x800,
+    .page_size   = 0x8,                       // minimal programmable unit size
     .flash_start = 0x0,
     .flash_size  = 0x0007F000,
     .sectors     = sectors_info,

--- a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/api/us_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /*******************************************************************************
- * Copyright (c) 2010-2017 Analog Devices, Inc.
+ * Copyright (c) 2010-2018 Analog Devices, Inc.
  *
  * All rights reserved.
  *
@@ -116,7 +116,7 @@
          * thereby clearing any TMR1 pend's.  This have no effect if this routine is called with interrupts globally disabled.
          */
 
-        NVIC_DisableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);		// Prevent Upper_count increment
+        NVIC_DisableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);     // Prevent Upper_count increment
         tmrpend0 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);
         // Check if there is a pending interrupt for timer 1
 
@@ -128,27 +128,27 @@
 
         tmrcnt1 = adi_tmr_registers[ADI_TMR_DEVICE_GP1]->CURCNT;    // read both timers manually
 
-        totaltmr0 = tmrcnt0;        								// expand to u32 bits
-        totaltmr1 = tmrcnt1;        								// expand to u32 bits
+        totaltmr0 = tmrcnt0;                                        // expand to u32 bits
+        totaltmr1 = tmrcnt1;                                        // expand to u32 bits
 
         tmrcnt0 &= 0xff00u;
         tmrcnt1 <<= 8;
 
         __DMB();
 
-        uc1 = *ucptr;												// Read Upper_count
+        uc1 = *ucptr;                                               // Read Upper_count
 
         tmrpend1 = NVIC_GetPendingIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);
         // Check for a pending interrupt again.  Only leave loop if they match
 
-        NVIC_EnableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);		// enable interrupt on every loop to allow TMR1 interrupt to run
+        NVIC_EnableIRQ(adi_tmr_interrupt[ADI_TMR_DEVICE_GP1]);      // enable interrupt on every loop to allow TMR1 interrupt to run
     } while ((tmrcnt0 != tmrcnt1) || (tmrpend0 != tmrpend1));
 
     totaltmr1 <<= 8;                 // Timer1 runs 256x slower
     totaltmr1 += totaltmr0 & 0xffu;  // Use last 8 bits of Timer0 as it runs faster
     // totaltmr1 now contain 24 bits of significance
 
-    if (tmrpend0) {					 // If an interrupt is pending, then increment local copy of upper count
+    if (tmrpend0) {                  // If an interrupt is pending, then increment local copy of upper count
         uc1++;
     }
 
@@ -158,7 +158,7 @@
     // Divide Uc by 26 (26MHz converted to 1MHz) todo scale for other clock freqs
 
     Uc *= 1290555u;                  // Divide total(1/26) << 25
-    Uc >>= 25;						 // shift back.  Fixed point avoid use of floating point divide.
+    Uc >>= 25;                       // shift back.  Fixed point avoid use of floating point divide.
     // Compiler does this inline using shifts and adds.
 
     return Uc;
@@ -205,7 +205,10 @@
         adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, tmr2Config);
         adi_tmr_Enable(ADI_TMR_DEVICE_GP2, true);
     } else {
-        us_ticker_irq_handler();
+        tmr2Config.nLoad        = 65535u;
+        tmr2Config.nAsyncLoad   = 65535u;
+        adi_tmr_ConfigTimer(ADI_TMR_DEVICE_GP2, tmr2Config);
+        adi_tmr_Enable(ADI_TMR_DEVICE_GP2, true);
     }
 }
 
@@ -229,7 +232,11 @@
 
     if (largecnt < 65536u) {
         adi_tmr_Enable(ADI_TMR_DEVICE_GP2, false);
-        event_timer();
+        if (largecnt) {
+            event_timer();
+        } else {
+            us_ticker_irq_handler();
+        }
     }
 }
 
@@ -326,7 +333,8 @@
      *
      */
     calc_event_counts(timestamp);             // use timestamp to calculate largecnt to control number of timer interrupts
-    event_timer();							  // uses largecnt to initiate timer interrupts
+    tmr2Config.ePrescaler   = ADI_TMR_PRESCALER_256;   // TMR2 at 26MHz/256
+    event_timer();                            // uses largecnt to initiate timer interrupts
 }
 
 /** Set pending interrupt that should be fired right away.
@@ -337,7 +345,9 @@
  */
 void us_ticker_fire_interrupt(void)
 {
-    NVIC_SetPendingIRQ(TMR2_EVT_IRQn);
+    largecnt = 1;                              // set a minimal interval so interrupt fire immediately
+    tmr2Config.ePrescaler   = ADI_TMR_PRESCALER_1;   // TMR2 at 26MHz/1
+    event_timer();                             // enable the timer and interrupt
 }
 
 

--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMD21/reset.h	Thu Apr 19 17:12:19 2018 +0100
@@ -84,18 +84,6 @@
  */
 
 /**
- * \brief Reset the MCU.
- *
- * Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources,
- * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).
- *
- */
-static inline void system_reset(void)
-{
-    NVIC_SystemReset();
-}
-
-/**
  * \brief Return the reset cause.
  *
  * Retrieves the cause of the last system reset.

--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAML21/reset.h	Thu Apr 19 17:12:19 2018 +0100
@@ -122,18 +122,6 @@
  */
 
 /**
- * \brief Reset the MCU.
- *
- * Resets the MCU and all associated peripherals and registers, except RTC,
- * OSC32KCTRL, RSTC, GCLK (if WRTLOCK is set), and I/O retention state of PM.
- *
- */
-static inline void system_reset(void)
-{
-    NVIC_SystemReset();
-}
-
-/**
  * \brief Get the reset cause.
  *
  * Retrieves the cause of the last system reset.

--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/system/reset/TARGET_SAMR21/reset.h	Thu Apr 19 17:12:19 2018 +0100
@@ -84,18 +84,6 @@
  */
 
 /**
- * \brief Reset the MCU.
- *
- * Resets the MCU and all associated peripherals and registers, except RTC, all 32KHz sources,
- * WDT (if ALWAYSON is set) and GCLK (if WRTLOCK is set).
- *
- */
-static inline void system_reset(void)
-{
-    NVIC_SystemReset();
-}
-
-/**
  * \brief Return the reset cause.
  *
  * Retrieves the cause of the last system reset.

--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/drivers/pmc/sleep.c	Thu Apr 19 17:12:19 2018 +0100
@@ -45,7 +45,7 @@
  */
 
 #include <compiler.h>
-#include "mbed_sleep.h"
+#include "mbed_power_mgmt.h"
 
 /* SAM3 and SAM4 series */
 #if (SAM3S || SAM3N || SAM3XA || SAM3U || SAM4S || SAM4E || SAM4N || SAM4C || \

--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM4/rtc_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM4/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -71,7 +71,11 @@
     timeinfo.tm_year = (ul_year - 1900);
 
     /* Convert to timestamp */
-    time_t t = _rtc_mktime(&timeinfo);
+    time_t t;
+    if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
+        return 0;
+    }
+
     return t;
 }
 
@@ -81,8 +85,9 @@
         /* Initialize the RTC is not yet initialized */
         rtc_init();
     }
+
     struct tm timeinfo;
-    if (_rtc_localtime(t, &timeinfo) == false) {
+    if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
         return;
     }
     uint32_t ul_hour, ul_minute, ul_second;

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/peripheral_clock_defines.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/peripheral_clock_defines.h	Thu Apr 19 17:12:19 2018 +0100
@@ -36,7 +36,7 @@
 /* Array for I2C module clocks */
 #define I2C_CLOCK_FREQS                                 \
     {                                              \
-        I2C0_CLK_SRC, I2C1_CLK_SRC, I2C2_CLK_SRC   \
+        I2C0_CLK_SRC, I2C1_CLK_SRC, I2C2_CLK_SRC, I2C3_CLK_SRC   \
     }
 
 /* Array for DSPI module clocks */

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_FRDM/mbed_overrides.c	Thu Apr 19 17:12:19 2018 +0100
@@ -39,3 +39,9 @@
     gpio_t gpio;
     gpio_init_in(&gpio, PTA4);
 }
+
+// Set the UART clock source
+void serial_clock_init(void)
+{
+    CLOCK_SetLpuartClock(2U);
+}

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/TARGET_USENSE/mbed_overrides.c	Thu Apr 19 17:12:19 2018 +0100
@@ -53,4 +53,10 @@
     /* Enable the RTC oscillator */
     RTC->CR |= RTC_CR_OSCE_MASK;
 }
-#endif
\ No newline at end of file
+#endif
+
+// Set the UART clock source
+void serial_clock_init(void)
+{
+    CLOCK_SetLpuartClock(2U);
+}

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/peripheral_clock_defines.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/peripheral_clock_defines.h	Thu Apr 19 17:12:19 2018 +0100
@@ -33,12 +33,6 @@
 
 #include "fsl_clock.h"
 
-/* Array for LPUART module clocks */
-#define LPUART_CLOCK_FREQS                         \
-    {                                              \
-        kCLOCK_Osc0ErClk, kCLOCK_Osc0ErClk, kCLOCK_Osc0ErClk   \
-    }
-
 /* Array for I2C module clocks */
 #define I2C_CLOCK_FREQS               \
     {                                 \

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/serial_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/serial_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -34,8 +34,8 @@
 static uart_irq_handler irq_handler;
 /* Array of UART peripheral base address. */
 static LPUART_Type *const uart_addrs[] = LPUART_BASE_PTRS;
-/* Array of LPUART bus clock frequencies */
-static clock_name_t const uart_clocks[] = LPUART_CLOCK_FREQS;
+/* LPUART bus clock frequency */
+static uint32_t lpuart_src_freq;
 
 int stdio_uart_inited = 0;
 serial_t stdio_uart;
@@ -47,10 +47,11 @@
     obj->index = pinmap_merge(uart_tx, uart_rx);
     MBED_ASSERT((int)obj->index != NC);
 
+    /* Set the UART clock source */
+    serial_clock_init();
+
     // since the LPuart initialization depends very much on the source clock and its
     // frequency, we do a check here and retrieve the frequency accordingly
-    // The CLOCK_SetLpuartSrc() is already done during clock init.
-    uint32_t lpuart_src_freq;
     switch (SIM->SOPT2 & SIM_SOPT2_LPUARTSRC_MASK) {
         case SIM_SOPT2_LPUARTSRC(3U): {
             lpuart_src_freq = CLOCK_GetInternalRefClkFreq();
@@ -65,9 +66,9 @@
             break;
         }
         default: {
-    /* Set the LPUART clock source */
-            CLOCK_SetLpuartClock(1U);
-            lpuart_src_freq = CLOCK_GetFreq(uart_clocks[obj->index]);
+            /* Set the LPUART clock source */
+            CLOCK_SetLpuartClock(2U);
+            lpuart_src_freq = CLOCK_GetOsc0ErClkFreq();
             break;
         }
     }
@@ -106,7 +107,7 @@
 
 void serial_baud(serial_t *obj, int baudrate)
 {
-    LPUART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, CLOCK_GetFreq(uart_clocks[obj->index]));
+    LPUART_SetBaudRate(uart_addrs[obj->index], (uint32_t)baudrate, lpuart_src_freq);
 }
 
 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)

--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/i2c_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -36,6 +36,9 @@
 {
     uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
     uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
+    PORT_Type *port_addrs[] = PORT_BASE_PTRS;
+    PORT_Type *base = port_addrs[sda >> GPIO_PORT_SHIFT];
+
     obj->instance = pinmap_merge(i2c_sda, i2c_scl);
     obj->next_repeated_start = 0;
     MBED_ASSERT((int)obj->instance != NC);
@@ -49,10 +52,11 @@
     pinmap_pinout(sda, PinMap_I2C_SDA);
     pinmap_pinout(scl, PinMap_I2C_SCL);
 
+    /* Enable internal pullup resistor */
+    base->PCR[sda & 0xFF] |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK);
+    base->PCR[scl & 0xFF] |= (PORT_PCR_PE_MASK | PORT_PCR_PS_MASK);
+
 #if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
-    PORT_Type *port_addrs[] = PORT_BASE_PTRS;
-    PORT_Type *base = port_addrs[sda >> GPIO_PORT_SHIFT];
-
     base->PCR[sda & 0xFF] |= PORT_PCR_ODE_MASK;
     base->PCR[scl & 0xFF] |= PORT_PCR_ODE_MASK;
 #endif
@@ -63,12 +67,14 @@
     I2C_Type *base = i2c_addrs[obj->instance];
     uint32_t statusFlags = I2C_MasterGetStatusFlags(base);
 
-    /* Return an error if the bus is already in use. */
+    /* Check if the bus is already in use. */
     if (statusFlags & kI2C_BusBusyFlag) {
-        return 1;
+        /* Send a repeat START signal. */
+        base->C1 |= I2C_C1_RSTA_MASK;
+    } else {
+        /* Send the START signal. */
+        base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK;
     }
-    /* Send the START signal. */
-    base->C1 |= I2C_C1_MST_MASK | I2C_C1_TX_MASK;
 
 #if defined(FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING) && FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING
     while (!(base->S2 & I2C_S2_EMPTY_MASK))
@@ -81,7 +87,6 @@
 
 int i2c_stop(i2c_t *obj)
 {
-    obj->next_repeated_start = 0;
     if (I2C_MasterStop(i2c_addrs[obj->instance]) != kStatus_Success) {
         return 1;
     }
@@ -179,39 +184,64 @@
 {
     uint8_t data;
     I2C_Type *base = i2c_addrs[obj->instance];
-    i2c_master_transfer_t master_xfer;
+
+    /* Setup the I2C peripheral to receive data. */
+    base->C1 &= ~(I2C_C1_TX_MASK | I2C_C1_TXAK_MASK);
+
+    if (last) {
+        base->C1 |= I2C_C1_TXAK_MASK; // NACK
+    }
+
+    data = (base->D & 0xFF);
 
-    memset(&master_xfer, 0, sizeof(master_xfer));
-    master_xfer.slaveAddress = i2c_address;
-    master_xfer.direction = kI2C_Read;
-    master_xfer.data = &data;
-    master_xfer.dataSize = 1;
+    /* Change direction to Tx to avoid extra clocks. */
+    base->C1 |= I2C_C1_TX_MASK;
 
-    /* The below function will issue a STOP signal at the end of the transfer.
-     * This is required by the hardware in order to receive the last byte
-     */
-    if (I2C_MasterTransferBlocking(base, &master_xfer) != kStatus_Success) {
-        return I2C_ERROR_NO_SLAVE;
+    /* Wait until data transfer complete. */
+    while (!(base->S & kI2C_IntPendingFlag))
+    {
     }
+
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
+
     return data;
 }
 
 int i2c_byte_write(i2c_t *obj, int data)
 {
-    status_t ret_value;
-#if FSL_I2C_DRIVER_VERSION > MAKE_VERSION(2, 0, 1)
-    ret_value = I2C_MasterWriteBlocking(i2c_addrs[obj->instance], (uint8_t *)(&data), 1, kI2C_TransferNoStopFlag);
-#else
-    ret_value = I2C_MasterWriteBlocking(i2c_addrs[obj->instance], (uint8_t *)(&data), 1);
-#endif
+    int ret_value = 1;
+    uint8_t statusFlags = 0;
+    I2C_Type *base = i2c_addrs[obj->instance];
+
+    /* Setup the I2C peripheral to transmit data. */
+    base->C1 |= I2C_C1_TX_MASK;
+
+    /* Send a byte of data. */
+    base->D = data;
+
+    /* Wait until data transfer complete. */
+    while (!(base->S & kI2C_IntPendingFlag)) {
+    }
+
+    statusFlags = base->S;
 
-    if (ret_value == kStatus_Success) {
-        return 1;
-    } else if (ret_value == kStatus_I2C_Nak) {
-        return 0;
-    } else {
-        return 2;
+    /* Clear the IICIF flag. */
+    base->S = kI2C_IntPendingFlag;
+
+    /* Check if arbitration lost */
+    if (statusFlags & kI2C_ArbitrationLostFlag) {
+        base->S = kI2C_ArbitrationLostFlag;
+        ret_value = 2;
     }
+
+    /* Check if no acknowledgement (NAK) */
+    if (statusFlags & kI2C_ReceiveNakFlag) {
+        base->S = kI2C_ReceiveNakFlag;
+        ret_value = 0;
+    }
+
+    return ret_value;
 }
 
 

--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/PeripheralNames.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/PeripheralNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -45,8 +45,14 @@
 extern "C" {
 #endif
 
+#ifndef STDIO_UART_TX
 #define STDIO_UART_TX     TX_PIN_NUMBER
+#endif
+
+#ifndef STDIO_UART_RX
 #define STDIO_UART_RX     RX_PIN_NUMBER
+#endif
+
 #define STDIO_UART        UART_0
 
 typedef enum {

--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/PeripheralNames.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/PeripheralNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -45,8 +45,14 @@
 extern "C" {
 #endif
 
+#ifndef STDIO_UART_TX
 #define STDIO_UART_TX     TX_PIN_NUMBER
+#endif
+
+#ifndef STDIO_UART_RX
 #define STDIO_UART_RX     RX_PIN_NUMBER
+#endif
+
 #define STDIO_UART        UART_0
 
 typedef enum

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/itm_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(DEVICE_ITM)
+
+#include "hal/itm_api.h"
+
+#include "nrf.h"
+#include "nrf5x_lf_clk_helper.h"
+
+/* SWO frequency: 4000 kHz */
+void itm_init(void)
+{
+    /* Enable SWO trace functionality */
+    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+    NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+
+    /* set SWO clock speed to 4 MHz */
+    NRF_CLOCK->TRACECONFIG = (NRF_CLOCK->TRACECONFIG & ~CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk) | 
+                             (CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos);
+
+    /* set SWO pin */
+    NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | 
+                          (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | 
+                          (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+
+    /* set prescaler */
+    TPI->ACPR = 0;
+}
+
+#endif

--- a/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/nordic_critical.c	Thu Apr 19 17:12:19 2018 +0100
@@ -19,13 +19,13 @@
 #include "app_util_platform.h"
 
 #if defined(SOFTDEVICE_PRESENT)
-static volatile uint32_t nordic_cr_nested = 0;
+static volatile bool state_saved = false;
 
 static void nordic_nvic_critical_region_enter(void);
 static void nordic_nvic_critical_region_exit(void);
 #endif
 
-void core_util_critical_section_enter()
+void hal_critical_section_enter()
 {
 #ifdef NRF52
     ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get())
@@ -39,7 +39,7 @@
 #endif
 }
 
-void core_util_critical_section_exit()
+void hal_critical_section_exit()
 {
 #ifdef NRF52
     ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get())
@@ -53,6 +53,13 @@
 #endif
 }
 
+
+bool hal_in_critical_section(void)
+{
+    return (state_saved != 0);
+}
+
+
 #if defined(SOFTDEVICE_PRESENT)
 /**@brief Enters critical region.
  *
@@ -63,7 +70,7 @@
 {
     int was_masked = __sd_nvic_irq_disable();
 
-    if (nordic_cr_nested == 0) {
+    if (state_saved == false) {
             nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 );
             NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0;
 #ifdef NRF52
@@ -72,7 +79,7 @@
 #endif
     }
 
-    nordic_cr_nested++;
+    state_saved = true;
 
     if (!was_masked) {
         __sd_nvic_irq_enable();
@@ -86,17 +93,15 @@
  */
 static inline void nordic_nvic_critical_region_exit(void)
 {
-    nordic_cr_nested--;
+    state_saved = false;
 
-    if (nordic_cr_nested == 0) {
-        int was_masked = __sd_nvic_irq_disable();
-        NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0];
+    int was_masked = __sd_nvic_irq_disable();
+    NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0];
 #ifdef NRF52
-        NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1];
+    NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1];
 #endif
-        if (!was_masked) {
-        __sd_nvic_irq_enable();
-        }
+    if (!was_masked) {
+    __sd_nvic_irq_enable();
     }
 }
 #endif

--- a/targets/TARGET_NUVOTON/TARGET_M451/flash_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M451/flash_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -65,7 +65,8 @@
 };
 
 static const flash_target_config_t flash_target_config = {
-    .page_size  = 0x800,    // 2 KB
+    .page_size  = 4,        // 4 bytes
+                            // Here page_size is program unit, which is different than FMC definition.
     .flash_start = 0x0,
     .flash_size = 0x40000,  // 256 KB
     .sectors = sectors_info,

--- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -47,6 +47,9 @@
 #define TMR_CMP_MIN         2
 #define TMR_CMP_MAX         0xFFFFFFu
 
+/* NOTE: When system clock is higher than timer clock, we need to add 3 engine clock
+ *       (recommended by designer) delay to wait for above timer control to take effect. */
+
 void lp_ticker_init(void)
 {
     if (ticker_inited) {
@@ -63,8 +66,10 @@
     // Enable IP clock
     CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
 
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
     // Configure clock
-    uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
     uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
     MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
@@ -72,19 +77,28 @@
     MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
     // Continuous mode
     // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
+    timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    timer_base->CMP = cmp_timer;
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 
     // Set vector
     NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
 
     NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
 
-    TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+    TIMER_EnableInt(timer_base);
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    TIMER_EnableWakeup(timer_base);
     wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-    TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+
+    TIMER_Start(timer_base);
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    /* Wait for timer to start counting and raise active flag */
+    while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
 }
 
 timestamp_t lp_ticker_read()
@@ -93,7 +107,7 @@
         lp_ticker_init();
     }
 
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     return  (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
 }
@@ -108,27 +122,27 @@
      * This behavior is not what we want. To fix it, we could configure new CMP value
      * without stopping counting first.
      */
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of 
      *       (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
     uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
     cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+
     timer_base->CMP = cmp_timer;
-
-    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
     wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-    TIMER_Start(timer_base);
 }
 
 void lp_ticker_disable_interrupt(void)
 {
     TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 }
 
 void lp_ticker_clear_interrupt(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 }
 
 void lp_ticker_fire_interrupt(void)
@@ -150,8 +164,11 @@
 static void tmr1_vec(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
     TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
     // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
     lp_ticker_irq_handler();
 }

--- a/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M451/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -13,7 +13,7 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
- 
+
 #include "rtc_api.h"
 
 #if DEVICE_RTC
@@ -24,8 +24,65 @@
 #include "nu_miscutil.h"
 #include "mbed_mktime.h"
 
-#define YEAR0       1900
-//#define EPOCH_YR    1970
+/* Micro seconds per second */
+#define NU_US_PER_SEC               1000000
+/* Timer clock per second
+ *
+ * NOTE: This dependents on real hardware.
+ */
+#define NU_RTCCLK_PER_SEC           ((CLK->CLKSEL3 & CLK_CLKSEL3_SC0SEL_Msk) ? __LIRC : __LXT)
+
+/* Strategy for implementation of RTC HAL
+ *
+ * H/W RTC just supports year range 2000~2099, which cannot fully cover POSIX time (starting since 2970)
+ * and date time of struct TM (starting since 1900).
+ *
+ * To conquer the difficulty, we don't use H/W RTC to keep real date time. Instead, we use it to keep
+ * elapsed time in seconds since one reference time point. The strategy would be:
+ *
+ * 1. Choose DATETIME_HWRTC_ORIGIN (00:00:00 UTC, Saturday, 1 January 2000) as reference time point of H/W RTC.
+ * 2. t_hwrtc_origin = DATETIME_HWRTC_ORIGIN in POSIX time
+ * 3. t_hwrtc_elapsed = t_hwrtc_origin + elapsed time since t_hwrtc_origin
+ * 4. t_write = POSIX time set by rtc_write().
+ * 5. t_present = rtc_read() = t_write + (t_hwrtc_elapsed - t_hwrtc_origin)
+ *
+ * 1900
+ * |---------------------------------------------------------------------------------|
+ *           1970    t_write           t_present
+ * |---------|-------|-----------------|---------------------------------------------|
+ * 
+ * 2000 
+ * |-----------------|---------------------------------------------------------------|
+ * t_hwrtc_origin    t_hwrtc_elapsed
+ *
+ */
+/* Start year of struct TM*/
+#define NU_TM_YEAR0         1900
+/* Start year of POSIX time (set_time()/time()) */
+#define NU_POSIX_YEAR0      1970
+/* Start year of H/W RTC */
+#define NU_HWRTC_YEAR0      2000
+
+/* RTC H/W origin time: 00:00:00 UTC, Saturday, 1 January 2000 */
+static const S_RTC_TIME_DATA_T DATETIME_HWRTC_ORIGIN = {
+    2000,           /* Year value, range between 2000 ~ 2099 */
+    1,              /* Month value, range between 1 ~ 12 */
+    1,              /* Day value, range between 1 ~ 31 */
+    RTC_SATURDAY,   /* Day of the week */
+    0,              /* Hour value, range between 0 ~ 23 */
+    0,              /* Minute value, range between 0 ~ 59 */
+    0,              /* Second value, range between 0 ~ 59 */
+    RTC_CLOCK_24,   /* 12-Hour (RTC_CLOCK_12) / 24-Hour (RTC_CLOCK_24) */
+    0               /* RTC_AM / RTC_PM (used only for 12-Hour) */
+};
+/* t_hwrtc_origin initialized or not? */
+static bool t_hwrtc_origin_inited = 0;
+/* POSIX time of DATETIME_HWRTC_ORIGIN (since 00:00:00 UTC, Thursday, 1 January 1970) */
+static time_t t_hwrtc_origin = 0;
+/* POSIX time set by rtc_write() */
+static time_t t_write = 0;
+/* Convert date time from H/W RTC to struct TM */
+static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc);
 
 static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
 
@@ -34,8 +91,11 @@
     if (rtc_isenabled()) {
         return;
     }
-    
+
     RTC_Open(NULL);
+
+    /* POSIX time origin (00:00:00 UTC, Thursday, 1 January 1970) */
+    rtc_write(0);
 }
 
 void rtc_free(void)
@@ -50,11 +110,62 @@
         // Enable IP clock
         CLK_EnableModuleClock(rtc_modinit.clkidx);
     }
-    
+
     // NOTE: Check RTC Init Active flag to support crossing reset cycle.
     return  !! (RTC->INIT & RTC_INIT_ACTIVE_Msk);
 }
 
+time_t rtc_read(void)
+{
+    /* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
+     *       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
+     */
+    if (! rtc_isenabled()) {
+        rtc_init();
+    }
+
+    /* Used for intermediary between date time of H/W RTC and POSIX time */
+    struct tm datetime_tm;
+
+    if (! t_hwrtc_origin_inited) {
+        t_hwrtc_origin_inited = 1;
+        
+        /* Convert date time from H/W RTC to struct TM */     
+        rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &DATETIME_HWRTC_ORIGIN);
+        /* Convert date time of struct TM to POSIX time */
+        if (! _rtc_maketime(&datetime_tm, &t_hwrtc_origin, RTC_FULL_LEAP_YEAR_SUPPORT)) {
+            return 0;
+        }
+    }
+
+    S_RTC_TIME_DATA_T hwrtc_datetime_2K_present;
+    RTC_GetDateAndTime(&hwrtc_datetime_2K_present);
+    /* Convert date time from H/W RTC to struct TM */
+    rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &hwrtc_datetime_2K_present);
+    /* Convert date time of struct TM to POSIX time */
+    time_t t_hwrtc_elapsed;
+    if (! _rtc_maketime(&datetime_tm, &t_hwrtc_elapsed, RTC_FULL_LEAP_YEAR_SUPPORT)) {
+        return 0;
+    }
+
+    /* Present time in POSIX time */
+    time_t t_present = t_write + (t_hwrtc_elapsed - t_hwrtc_origin);
+    return t_present;
+}
+
+void rtc_write(time_t t)
+{
+    if (! rtc_isenabled()) {
+        rtc_init();
+    }
+
+    t_write = t;
+
+    RTC_SetDateAndTime((S_RTC_TIME_DATA_T *) &DATETIME_HWRTC_ORIGIN);
+    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+    wait_us((NU_US_PER_SEC / NU_RTCCLK_PER_SEC) * 3);
+}
+
 /*
  struct tm
    tm_sec      seconds after the minute 0-61
@@ -67,66 +178,18 @@
    tm_yday     days since January 1 0-365
    tm_isdst    Daylight Saving Time flag
 */
-
-time_t rtc_read(void)
+static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc)
 {
-    // NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
-    //       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
-    if (! rtc_isenabled()) {
-        rtc_init();
-    }
-    
-    S_RTC_TIME_DATA_T rtc_datetime;
-    RTC_GetDateAndTime(&rtc_datetime);
-    
-    struct tm timeinfo;
-
-    // Convert struct tm to S_RTC_TIME_DATA_T
-    timeinfo.tm_year = rtc_datetime.u32Year - YEAR0;
-    timeinfo.tm_mon  = rtc_datetime.u32Month - 1;
-    timeinfo.tm_mday = rtc_datetime.u32Day;
-    timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
-    timeinfo.tm_hour = rtc_datetime.u32Hour;
-    if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) {
-        timeinfo.tm_hour += 12;
+    datetime_tm->tm_year = datetime_hwrtc->u32Year - NU_TM_YEAR0;
+    datetime_tm->tm_mon  = datetime_hwrtc->u32Month - 1;
+    datetime_tm->tm_mday = datetime_hwrtc->u32Day;
+    datetime_tm->tm_wday = datetime_hwrtc->u32DayOfWeek;
+    datetime_tm->tm_hour = datetime_hwrtc->u32Hour;
+    if (datetime_hwrtc->u32TimeScale == RTC_CLOCK_12 && datetime_hwrtc->u32AmPm == RTC_PM) {
+        datetime_tm->tm_hour += 12;
     }
-    timeinfo.tm_min  = rtc_datetime.u32Minute;
-    timeinfo.tm_sec  = rtc_datetime.u32Second;
-
-    // Convert to timestamp
-    time_t t = _rtc_mktime(&timeinfo);
-
-    return t;
-}
-
-void rtc_write(time_t t)
-{
-    if (! rtc_isenabled()) {
-        rtc_init();
-    }
-    
-    // Convert timestamp to struct tm
-    struct tm timeinfo;
-    if (_rtc_localtime(t, &timeinfo) == false) {
-        return;
-    }
-
-    S_RTC_TIME_DATA_T rtc_datetime;
-    
-    // Convert S_RTC_TIME_DATA_T to struct tm
-    rtc_datetime.u32Year        = timeinfo.tm_year + YEAR0;
-    rtc_datetime.u32Month       = timeinfo.tm_mon + 1;
-    rtc_datetime.u32Day         = timeinfo.tm_mday;
-    rtc_datetime.u32DayOfWeek   = timeinfo.tm_wday;
-    rtc_datetime.u32Hour        = timeinfo.tm_hour;
-    rtc_datetime.u32Minute      = timeinfo.tm_min;
-    rtc_datetime.u32Second      = timeinfo.tm_sec;
-    rtc_datetime.u32TimeScale   = RTC_CLOCK_24;
-    
-    // NOTE: Timing issue with write to RTC registers. This delay is empirical, not rational.
-    RTC_SetDateAndTime(&rtc_datetime);
-    //nu_nop(6000);
-    wait_us(100);
+    datetime_tm->tm_min  = datetime_hwrtc->u32Minute;
+    datetime_tm->tm_sec  = datetime_hwrtc->u32Second;
 }
 
 #endif

--- a/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M451/serial_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -503,6 +503,10 @@
         // Register DMA event handler
         dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
         serial_tx_enable_interrupt(obj, handler, 1);
+        /* We needn't actually enable UART INT to go UART ISR -> handler.
+         * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
+         * with serial_tx/rx_enable_interrupt having set up this call path. */
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
         ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk;  // Start DMA transfer
     }
     
@@ -566,6 +570,10 @@
         // Register DMA event handler
         dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
         serial_rx_enable_interrupt(obj, handler, 1);
+        /* We needn't actually enable UART INT to go UART ISR -> handler.
+         * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
+         * with serial_tx/rx_enable_interrupt having set up this call path. */
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
         ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk;  // Start DMA transfer
     }
 }

--- a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -58,23 +58,28 @@
     // Enable IP clock
     CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
 
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
     // Timer for normal counter
-    uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
     uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
     MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
     uint32_t cmp_timer = TMR_CMP_MAX;
     MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
     // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
+    timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
+    timer_base->CMP = cmp_timer;
 
     NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
 
     NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
 
-    TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    TIMER_EnableInt(timer_base);
+
+    TIMER_Start(timer_base);
+    /* Wait for timer to start counting and raise active flag */
+    while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
 }
 
 uint32_t us_ticker_read()
@@ -83,7 +88,7 @@
         us_ticker_init();
     }
 
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     return  (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
 }
@@ -98,7 +103,7 @@
      * This behavior is not what we want. To fix it, we could configure new CMP value
      * without stopping counting first.
      */
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of 
      *       (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */

--- a/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PinNames.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PinNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -84,34 +84,34 @@
     A0 = PB_6,
     A1 = PB_7,
     A2 = PB_8,
-    A3 = PB_3,
-    A4 = PB_4,
-    A5 = PB_5,
+    A3 = PB_9,
+    A4 = PB_0,
+    A5 = PB_1,
 
-    D0 = PH_9,
-    D1 = PH_8,
-    D2 = PB_9,
-    D3 = PF_11,
-    D4 = PG_4,
-    D5 = PC_11,
-    D6 = PC_12,
-    D7 = PC_13,
+    D0 = PB_2,
+    D1 = PB_3,
+    D2 = PC_9,
+    D3 = PC_10,
+    D4 = PC_11,
+    D5 = PC_12,
+    D6 = PE_4,
+    D7 = PE_5,
     D8 = PA_5,
     D9 = PA_4,
     D10 = PA_3,
     D11 = PA_0,
     D12 = PA_1,
     D13 = PA_2,
-    D14 = PG_3,
-    D15 = PG_2,
+    D14 = PG_1,
+    D15 = PG_0,
 
     I2C_SCL = D15,
     I2C_SDA = D14,
     
     // Note: board-specific
     // UART naming
-    USBTX = PD_3,
-    USBRX = PD_2,
+    USBTX = PB_13,
+    USBRX = PB_12,
     STDIO_UART_TX   = USBTX,
     STDIO_UART_RX   = USBRX,
     SERIAL_TX = USBTX,
@@ -125,8 +125,8 @@
     LED3 = LED_GREEN,
     LED4 = LED1,    // No real LED. Just for passing ATS.
     // Button naming
-    SW2 = PC_10,
-    SW3 = PC_9,
+    SW2 = PG_15,
+    SW3 = PF_11,
     
 } PinName;
 

--- a/targets/TARGET_NUVOTON/TARGET_M480/flash_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/flash_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -69,7 +69,8 @@
 };
 
 static const flash_target_config_t flash_target_config = {
-    .page_size  = 0x200,    // 512 bytes
+    .page_size  = 4,        // 4 bytes
+                            // Here page_size is program unit, which is different than FMC definition.
     .flash_start = 0x0,
     .flash_size = 0x80000,  // 512 KB
     .sectors = sectors_info,

--- a/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -47,6 +47,9 @@
 #define TMR_CMP_MIN         2
 #define TMR_CMP_MAX         0xFFFFFFu
 
+/* NOTE: When system clock is higher than timer clock, we need to add 3 engine clock
+ *       (recommended by designer) delay to wait for above timer control to take effect. */
+
 void lp_ticker_init(void)
 {
     if (ticker_inited) {
@@ -63,8 +66,10 @@
     // Enable IP clock
     CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
 
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
     // Configure clock
-    uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
     uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
     MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
@@ -72,19 +77,28 @@
     MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
     // Continuous mode
     // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
+    timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    timer_base->CMP = cmp_timer;
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 
     // Set vector
     NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
 
     NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
 
-    TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+    TIMER_EnableInt(timer_base);
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    TIMER_EnableWakeup(timer_base);
     wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-    TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+
+    TIMER_Start(timer_base);
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    /* Wait for timer to start counting and raise active flag */
+    while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
 }
 
 timestamp_t lp_ticker_read()
@@ -93,7 +107,7 @@
         lp_ticker_init();
     }
 
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     return  (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
 }
@@ -108,27 +122,27 @@
      * This behavior is not what we want. To fix it, we could configure new CMP value
      * without stopping counting first.
      */
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of 
      *       (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
     uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
     cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+
     timer_base->CMP = cmp_timer;
-
-    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
     wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-    TIMER_Start(timer_base);
 }
 
 void lp_ticker_disable_interrupt(void)
 {
     TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 }
 
 void lp_ticker_clear_interrupt(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 }
 
 void lp_ticker_fire_interrupt(void)
@@ -150,8 +164,11 @@
 static void tmr1_vec(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
     TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
     // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
     lp_ticker_irq_handler();
 }

--- a/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -24,8 +24,65 @@
 #include "nu_miscutil.h"
 #include "mbed_mktime.h"
 
-#define YEAR0       1900
-//#define EPOCH_YR    1970
+/* Micro seconds per second */
+#define NU_US_PER_SEC               1000000
+/* Timer clock per second
+ *
+ * NOTE: This dependents on real hardware.
+ */
+#define NU_RTCCLK_PER_SEC           ((CLK->CLKSEL3 & CLK_CLKSEL3_SC0SEL_Msk) ? __LIRC : __LXT)
+
+/* Strategy for implementation of RTC HAL
+ *
+ * H/W RTC just supports year range 2000~2099, which cannot fully cover POSIX time (starting since 2970)
+ * and date time of struct TM (starting since 1900).
+ *
+ * To conquer the difficulty, we don't use H/W RTC to keep real date time. Instead, we use it to keep
+ * elapsed time in seconds since one reference time point. The strategy would be:
+ *
+ * 1. Choose DATETIME_HWRTC_ORIGIN (00:00:00 UTC, Saturday, 1 January 2000) as reference time point of H/W RTC.
+ * 2. t_hwrtc_origin = DATETIME_HWRTC_ORIGIN in POSIX time
+ * 3. t_hwrtc_elapsed = t_hwrtc_origin + elapsed time since t_hwrtc_origin
+ * 4. t_write = POSIX time set by rtc_write().
+ * 5. t_present = rtc_read() = t_write + (t_hwrtc_elapsed - t_hwrtc_origin)
+ *
+ * 1900
+ * |---------------------------------------------------------------------------------|
+ *           1970    t_write           t_present
+ * |---------|-------|-----------------|---------------------------------------------|
+ * 
+ * 2000 
+ * |-----------------|---------------------------------------------------------------|
+ * t_hwrtc_origin    t_hwrtc_elapsed
+ *
+ */
+/* Start year of struct TM*/
+#define NU_TM_YEAR0         1900
+/* Start year of POSIX time (set_time()/time()) */
+#define NU_POSIX_YEAR0      1970
+/* Start year of H/W RTC */
+#define NU_HWRTC_YEAR0      2000
+
+/* RTC H/W origin time: 00:00:00 UTC, Saturday, 1 January 2000 */
+static const S_RTC_TIME_DATA_T DATETIME_HWRTC_ORIGIN = {
+    2000,           /* Year value, range between 2000 ~ 2099 */
+    1,              /* Month value, range between 1 ~ 12 */
+    1,              /* Day value, range between 1 ~ 31 */
+    RTC_SATURDAY,   /* Day of the week */
+    0,              /* Hour value, range between 0 ~ 23 */
+    0,              /* Minute value, range between 0 ~ 59 */
+    0,              /* Second value, range between 0 ~ 59 */
+    RTC_CLOCK_24,   /* 12-Hour (RTC_CLOCK_12) / 24-Hour (RTC_CLOCK_24) */
+    0               /* RTC_AM / RTC_PM (used only for 12-Hour) */
+};
+/* t_hwrtc_origin initialized or not? */
+static bool t_hwrtc_origin_inited = 0;
+/* POSIX time of DATETIME_HWRTC_ORIGIN (since 00:00:00 UTC, Thursday, 1 January 1970) */
+static time_t t_hwrtc_origin = 0;
+/* POSIX time set by rtc_write() */
+static time_t t_write = 0;
+/* Convert date time from H/W RTC to struct TM */
+static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc);
 
 static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
 
@@ -36,6 +93,9 @@
     }
 
     RTC_Open(NULL);
+
+    /* POSIX time origin (00:00:00 UTC, Thursday, 1 January 1970) */
+    rtc_write(0);
 }
 
 void rtc_free(void)
@@ -54,6 +114,58 @@
     // NOTE: Check RTC Init Active flag to support crossing reset cycle.
     return !! (RTC->INIT & RTC_INIT_ACTIVE_Msk);
 }
+time_t rtc_read(void)
+{
+    /* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
+     *       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
+     *       NUC472/M453: Known issue
+     *       M487: Fixed
+     */
+    if (! rtc_isenabled()) {
+        rtc_init();
+    }
+
+    /* Used for intermediary between date time of H/W RTC and POSIX time */
+    struct tm datetime_tm;
+
+    if (! t_hwrtc_origin_inited) {
+        t_hwrtc_origin_inited = 1;
+        
+        /* Convert date time from H/W RTC to struct TM */     
+        rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &DATETIME_HWRTC_ORIGIN);
+        /* Convert date time of struct TM to POSIX time */
+        if (! _rtc_maketime(&datetime_tm, &t_hwrtc_origin, RTC_FULL_LEAP_YEAR_SUPPORT)) {
+            return 0;
+        }
+    }
+
+    S_RTC_TIME_DATA_T hwrtc_datetime_2K_present;
+    RTC_GetDateAndTime(&hwrtc_datetime_2K_present);
+    /* Convert date time from H/W RTC to struct TM */
+    rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &hwrtc_datetime_2K_present);
+    /* Convert date time of struct TM to POSIX time */
+    time_t t_hwrtc_elapsed;
+    if (! _rtc_maketime(&datetime_tm, &t_hwrtc_elapsed, RTC_FULL_LEAP_YEAR_SUPPORT)) {
+        return 0;
+    }
+
+    /* Present time in POSIX time */
+    time_t t_present = t_write + (t_hwrtc_elapsed - t_hwrtc_origin);
+    return t_present;
+}
+
+void rtc_write(time_t t)
+{
+    if (! rtc_isenabled()) {
+        rtc_init();
+    }
+
+    t_write = t;
+
+    RTC_SetDateAndTime((S_RTC_TIME_DATA_T *) &DATETIME_HWRTC_ORIGIN);
+    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+    wait_us((NU_US_PER_SEC / NU_RTCCLK_PER_SEC) * 3);
+}
 
 /*
  struct tm
@@ -67,67 +179,18 @@
    tm_yday     days since January 1 0-365
    tm_isdst    Daylight Saving Time flag
 */
-
-time_t rtc_read(void)
+static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc)
 {
-    // NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
-    //       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
-    //       NUC472/M453: Known issue
-    //       M487: Fixed
-    if (! rtc_isenabled()) {
-        rtc_init();
-    }
-
-    S_RTC_TIME_DATA_T rtc_datetime;
-    RTC_GetDateAndTime(&rtc_datetime);
-
-    struct tm timeinfo;
-
-    // Convert struct tm to S_RTC_TIME_DATA_T
-    timeinfo.tm_year = rtc_datetime.u32Year - YEAR0;
-    timeinfo.tm_mon  = rtc_datetime.u32Month - 1;
-    timeinfo.tm_mday = rtc_datetime.u32Day;
-    timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
-    timeinfo.tm_hour = rtc_datetime.u32Hour;
-    if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) {
-        timeinfo.tm_hour += 12;
+    datetime_tm->tm_year = datetime_hwrtc->u32Year - NU_TM_YEAR0;
+    datetime_tm->tm_mon  = datetime_hwrtc->u32Month - 1;
+    datetime_tm->tm_mday = datetime_hwrtc->u32Day;
+    datetime_tm->tm_wday = datetime_hwrtc->u32DayOfWeek;
+    datetime_tm->tm_hour = datetime_hwrtc->u32Hour;
+    if (datetime_hwrtc->u32TimeScale == RTC_CLOCK_12 && datetime_hwrtc->u32AmPm == RTC_PM) {
+        datetime_tm->tm_hour += 12;
     }
-    timeinfo.tm_min  = rtc_datetime.u32Minute;
-    timeinfo.tm_sec  = rtc_datetime.u32Second;
-
-    // Convert to timestamp
-    time_t t = _rtc_mktime(&timeinfo);
-
-    return t;
-}
-
-void rtc_write(time_t t)
-{
-    if (! rtc_isenabled()) {
-        rtc_init();
-    }
-
-    // Convert timestamp to struct tm
-    struct tm timeinfo;
-    if (_rtc_localtime(t, &timeinfo) == false) {
-        return;
-    }
-
-    S_RTC_TIME_DATA_T rtc_datetime;
-
-    // Convert S_RTC_TIME_DATA_T to struct tm
-    rtc_datetime.u32Year        = timeinfo.tm_year + YEAR0;
-    rtc_datetime.u32Month       = timeinfo.tm_mon + 1;
-    rtc_datetime.u32Day         = timeinfo.tm_mday;
-    rtc_datetime.u32DayOfWeek   = timeinfo.tm_wday;
-    rtc_datetime.u32Hour        = timeinfo.tm_hour;
-    rtc_datetime.u32Minute      = timeinfo.tm_min;
-    rtc_datetime.u32Second      = timeinfo.tm_sec;
-    rtc_datetime.u32TimeScale   = RTC_CLOCK_24;
-
-    // NOTE: Timing issue with write to RTC registers. This delay is empirical, not rational.
-    RTC_SetDateAndTime(&rtc_datetime);
-    wait_us(100);
+    datetime_tm->tm_min  = datetime_hwrtc->u32Minute;
+    datetime_tm->tm_sec  = datetime_hwrtc->u32Second;
 }
 
 #endif

--- a/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/serial_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -561,6 +561,10 @@
         // Register DMA event handler
         dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
         serial_tx_enable_interrupt(obj, handler, 1);
+        /* We needn't actually enable UART INT to go UART ISR -> handler.
+         * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
+         * with serial_tx/rx_enable_interrupt having set up this call path. */
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
         ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk;  // Start DMA transfer
     }
 
@@ -622,6 +626,10 @@
         // Register DMA event handler
         dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
         serial_rx_enable_interrupt(obj, handler, 1);
+        /* We needn't actually enable UART INT to go UART ISR -> handler.
+         * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
+         * with serial_tx/rx_enable_interrupt having set up this call path. */
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
         ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk;  // Start DMA transfer
     }
 }

--- a/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -58,23 +58,28 @@
     // Enable IP clock
     CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
 
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
     // Timer for normal counter
-    uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
     uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
     MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
     uint32_t cmp_timer = TMR_CMP_MAX;
     MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
     // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
+    timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
+    timer_base->CMP = cmp_timer;
 
     NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
 
     NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
 
-    TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    TIMER_EnableInt(timer_base);
+
+    TIMER_Start(timer_base);
+    /* Wait for timer to start counting and raise active flag */
+    while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
 }
 
 uint32_t us_ticker_read()
@@ -83,7 +88,7 @@
         us_ticker_init();
     }
 
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     return  (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
 }
@@ -98,7 +103,7 @@
      * This behavior is not what we want. To fix it, we could configure new CMP value
      * without stopping counting first.
      */
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of 
      *       (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */

--- a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -49,6 +49,9 @@
 #define TMR_CMP_MIN         2
 #define TMR_CMP_MAX         0xFFFFFFu
 
+/* NOTE: When system clock is higher than timer clock, we need to add 3 engine clock
+ *       (recommended by designer) delay to wait for above timer control to take effect. */
+
 void lp_ticker_init(void)
 {
     if (ticker_inited) {
@@ -65,28 +68,41 @@
     // Enable IP clock
     CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
 
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
     // Configure clock
-    uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
     uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
     MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
     uint32_t cmp_timer = TMR_CMP_MAX;
     MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
     // Continuous mode
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE;
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->PRECNT = prescale_timer;
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMPR = cmp_timer;
+    timer_base->CTL = TIMER_CONTINUOUS_MODE;
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    timer_base->PRECNT = prescale_timer;
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    timer_base->CMPR = cmp_timer;
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 
     // Set vector
     NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
 
     NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
 
-    TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+    TIMER_EnableInt(timer_base);
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    TIMER_EnableWakeup(timer_base);
     wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-    TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+
+    TIMER_Start(timer_base);
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    /* Wait for timer to start counting and raise active flag */
+    while(! (timer_base->CTL & TIMER_CTL_TMR_ACT_Msk));
 }
 
 timestamp_t lp_ticker_read()
@@ -95,7 +111,7 @@
         lp_ticker_init();
     }
 
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     return  (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
 }
@@ -110,27 +126,27 @@
      * This behavior is not what we want. To fix it, we could configure new CMP value
      * without stopping counting first.
      */
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of 
      *       (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
     uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
     cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+
     timer_base->CMPR = cmp_timer;
-
-    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
     wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-    TIMER_Start(timer_base);
 }
 
 void lp_ticker_disable_interrupt(void)
 {
     TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 }
 
 void lp_ticker_clear_interrupt(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 }
 
 void lp_ticker_fire_interrupt(void)
@@ -152,8 +168,11 @@
 void TMR1_IRQHandler(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
     TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
     // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
     lp_ticker_irq_handler();
 }

--- a/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -13,7 +13,7 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
- 
+
 #include "rtc_api.h"
 
 #if DEVICE_RTC
@@ -24,8 +24,65 @@
 #include "nu_miscutil.h"
 #include "mbed_mktime.h"
 
-#define YEAR0           1900
+/* Micro seconds per second */
+#define NU_US_PER_SEC               1000000
+/* Timer clock per second
+ *
+ * NOTE: This dependents on real hardware.
+ */
+#define NU_RTCCLK_PER_SEC           (__LXT)
 
+/* Strategy for implementation of RTC HAL
+ *
+ * H/W RTC just supports year range 2000~2099, which cannot fully cover POSIX time (starting since 2970)
+ * and date time of struct TM (starting since 1900).
+ *
+ * To conquer the difficulty, we don't use H/W RTC to keep real date time. Instead, we use it to keep
+ * elapsed time in seconds since one reference time point. The strategy would be:
+ *
+ * 1. Choose DATETIME_HWRTC_ORIGIN (00:00:00 UTC, Saturday, 1 January 2000) as reference time point of H/W RTC.
+ * 2. t_hwrtc_origin = DATETIME_HWRTC_ORIGIN in POSIX time
+ * 3. t_hwrtc_elapsed = t_hwrtc_origin + elapsed time since t_hwrtc_origin
+ * 4. t_write = POSIX time set by rtc_write().
+ * 5. t_present = rtc_read() = t_write + (t_hwrtc_elapsed - t_hwrtc_origin)
+ *
+ * 1900
+ * |---------------------------------------------------------------------------------|
+ *           1970    t_write           t_present
+ * |---------|-------|-----------------|---------------------------------------------|
+ * 
+ * 2000 
+ * |-----------------|---------------------------------------------------------------|
+ * t_hwrtc_origin    t_hwrtc_elapsed
+ *
+ */
+/* Start year of struct TM*/
+#define NU_TM_YEAR0         1900
+/* Start year of POSIX time (set_time()/time()) */
+#define NU_POSIX_YEAR0      1970
+/* Start year of H/W RTC */
+#define NU_HWRTC_YEAR0      2000
+
+/* RTC H/W origin time: 00:00:00 UTC, Saturday, 1 January 2000 */
+static const S_RTC_TIME_DATA_T DATETIME_HWRTC_ORIGIN = {
+    2000,           /* Year value, range between 2000 ~ 2099 */
+    1,              /* Month value, range between 1 ~ 12 */
+    1,              /* Day value, range between 1 ~ 31 */
+    RTC_SATURDAY,   /* Day of the week */
+    0,              /* Hour value, range between 0 ~ 23 */
+    0,              /* Minute value, range between 0 ~ 59 */
+    0,              /* Second value, range between 0 ~ 59 */
+    RTC_CLOCK_24,   /* 12-Hour (RTC_CLOCK_12) / 24-Hour (RTC_CLOCK_24) */
+    0               /* RTC_AM / RTC_PM (used only for 12-Hour) */
+};
+/* t_hwrtc_origin initialized or not? */
+static bool t_hwrtc_origin_inited = 0;
+/* POSIX time of DATETIME_HWRTC_ORIGIN (since 00:00:00 UTC, Thursday, 1 January 1970) */
+static time_t t_hwrtc_origin = 0;
+/* POSIX time set by rtc_write() */
+static time_t t_write = 0;
+/* Convert date time from H/W RTC to struct TM */
+static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc);
 
 static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
 
@@ -34,8 +91,11 @@
     if (rtc_isenabled()) {
         return;
     }
-    
+
     RTC_Open(NULL);
+
+    /* POSIX time origin (00:00:00 UTC, Thursday, 1 January 1970) */
+    rtc_write(0);
 }
 
 void rtc_free(void)
@@ -50,11 +110,62 @@
         // Enable IP clock
         CLK_EnableModuleClock(rtc_modinit.clkidx);
     }
-    
+
     // NOTE: Check RTC Init Active flag to support crossing reset cycle.
     return !! (RTC->INIR & RTC_INIR_ACTIVE_Msk);
 }
 
+time_t rtc_read(void)
+{
+    /* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
+     *       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
+     */
+    if (! rtc_isenabled()) {
+        rtc_init();
+    }
+
+    /* Used for intermediary between date time of H/W RTC and POSIX time */
+    struct tm datetime_tm;
+
+    if (! t_hwrtc_origin_inited) {
+        t_hwrtc_origin_inited = 1;
+        
+        /* Convert date time from H/W RTC to struct TM */     
+        rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &DATETIME_HWRTC_ORIGIN);
+        /* Convert date time of struct TM to POSIX time */
+        if (! _rtc_maketime(&datetime_tm, &t_hwrtc_origin, RTC_FULL_LEAP_YEAR_SUPPORT)) {
+            return 0;
+        }
+    }
+
+    S_RTC_TIME_DATA_T hwrtc_datetime_2K_present;
+    RTC_GetDateAndTime(&hwrtc_datetime_2K_present);
+    /* Convert date time from H/W RTC to struct TM */
+    rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &hwrtc_datetime_2K_present);
+    /* Convert date time of struct TM to POSIX time */
+    time_t t_hwrtc_elapsed;
+    if (! _rtc_maketime(&datetime_tm, &t_hwrtc_elapsed, RTC_FULL_LEAP_YEAR_SUPPORT)) {
+        return 0;
+    }
+
+    /* Present time in POSIX time */
+    time_t t_present = t_write + (t_hwrtc_elapsed - t_hwrtc_origin);
+    return t_present;
+}
+
+void rtc_write(time_t t)
+{
+    if (! rtc_isenabled()) {
+        rtc_init();
+    }
+
+    t_write = t;
+
+    RTC_SetDateAndTime((S_RTC_TIME_DATA_T *) &DATETIME_HWRTC_ORIGIN);
+    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+    wait_us((NU_US_PER_SEC / NU_RTCCLK_PER_SEC) * 3);
+}
+
 /*
  struct tm
    tm_sec      seconds after the minute 0-61
@@ -67,65 +178,19 @@
    tm_yday     days since January 1 0-365
    tm_isdst    Daylight Saving Time flag
 */
-
-time_t rtc_read(void)
+static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc)
 {
-    // NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
-    //       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
-    if (! rtc_isenabled()) {
-        rtc_init();
-    }
-    
-    S_RTC_TIME_DATA_T rtc_datetime;
-    RTC_GetDateAndTime(&rtc_datetime);
-    
-    struct tm timeinfo;
-
-    // Convert struct tm to S_RTC_TIME_DATA_T
-    timeinfo.tm_year = rtc_datetime.u32Year - YEAR0;
-    timeinfo.tm_mon  = rtc_datetime.u32Month - 1;
-    timeinfo.tm_mday = rtc_datetime.u32Day;
-    timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
-    timeinfo.tm_hour = rtc_datetime.u32Hour;
-    if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) {
-        timeinfo.tm_hour += 12;
+    datetime_tm->tm_year = datetime_hwrtc->u32Year - NU_TM_YEAR0;
+    datetime_tm->tm_mon  = datetime_hwrtc->u32Month - 1;
+    datetime_tm->tm_mday = datetime_hwrtc->u32Day;
+    datetime_tm->tm_wday = datetime_hwrtc->u32DayOfWeek;
+    datetime_tm->tm_hour = datetime_hwrtc->u32Hour;
+    if (datetime_hwrtc->u32TimeScale == RTC_CLOCK_12 && datetime_hwrtc->u32AmPm == RTC_PM) {
+        datetime_tm->tm_hour += 12;
     }
-    timeinfo.tm_min  = rtc_datetime.u32Minute;
-    timeinfo.tm_sec  = rtc_datetime.u32Second;
-
-    // Convert to timestamp
-    time_t t = _rtc_mktime(&timeinfo);
-
-    return t;
-}
-
-void rtc_write(time_t t)
-{
-    if (! rtc_isenabled()) {
-        rtc_init();
-    }
-    
-    // Convert timestamp to struct tm
-    struct tm timeinfo;
-    if (_rtc_localtime(t, &timeinfo) == false) {
-        return;
-    }
-
-    S_RTC_TIME_DATA_T rtc_datetime;
-    
-    // Convert S_RTC_TIME_DATA_T to struct tm
-    rtc_datetime.u32Year        = timeinfo.tm_year + YEAR0;
-    rtc_datetime.u32Month       = timeinfo.tm_mon + 1;
-    rtc_datetime.u32Day         = timeinfo.tm_mday;
-    rtc_datetime.u32DayOfWeek   = timeinfo.tm_wday;
-    rtc_datetime.u32Hour        = timeinfo.tm_hour;
-    rtc_datetime.u32Minute      = timeinfo.tm_min;
-    rtc_datetime.u32Second      = timeinfo.tm_sec;
-    rtc_datetime.u32TimeScale   = RTC_CLOCK_24;
-    
-    RTC_SetDateAndTime(&rtc_datetime);
-    // Wait 3 cycles of engine clock to ensure previous CTL write action is finish
-    wait_us(30 * 3);
+    datetime_tm->tm_min  = datetime_hwrtc->u32Minute;
+    datetime_tm->tm_sec  = datetime_hwrtc->u32Second;
 }
 
 #endif
+

--- a/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/serial_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -458,6 +458,10 @@
         // Register DMA event handler
         dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
         serial_tx_enable_interrupt(obj, handler, 1);
+        /* We needn't actually enable UART INT to go UART ISR -> handler.
+         * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
+         * with serial_tx/rx_enable_interrupt having set up this call path. */
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_IER_THRE_IE_Msk);
         PDMA_Trigger(obj->serial.dma_chn_id_tx);
         ((UART_T *) NU_MODBASE(obj->serial.uart))->CTL |= UART_CTL_DMA_TX_EN_Msk;   // Start DMA transfer
     }
@@ -514,6 +518,10 @@
         // Register DMA event handler
         dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
         serial_rx_enable_interrupt(obj, handler, 1);
+        /* We needn't actually enable UART INT to go UART ISR -> handler.
+         * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
+         * with serial_tx/rx_enable_interrupt having set up this call path. */
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_IER_RDA_IE_Msk | UART_IER_RTO_IE_Msk));
         PDMA_Trigger(obj->serial.dma_chn_id_rx);
         ((UART_T *) NU_MODBASE(obj->serial.uart))->CTL |= UART_CTL_DMA_RX_EN_Msk;   // Start DMA transfer
     }

--- a/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -60,23 +60,28 @@
     // Enable IP clock
     CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
 
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
     // Timer for normal counter
-    uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
     uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
     MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
     uint32_t cmp_timer = TMR_CMP_MAX;
     MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE;
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->PRECNT = prescale_timer;
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMPR = cmp_timer;
+    timer_base->CTL = TIMER_CONTINUOUS_MODE;
+    timer_base->PRECNT = prescale_timer;
+    timer_base->CMPR = cmp_timer;
 
     NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
 
     NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
 
-    TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    TIMER_EnableInt(timer_base);
+
+    TIMER_Start(timer_base);
+    /* Wait for timer to start counting and raise active flag */
+    while(! (timer_base->CTL & TIMER_CTL_TMR_ACT_Msk));
 }
 
 uint32_t us_ticker_read()
@@ -85,7 +90,7 @@
         us_ticker_init();
     }
 
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     return  (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
 }
@@ -100,7 +105,7 @@
      * This behavior is not what we want. To fix it, we could configure new CMP value
      * without stopping counting first.
      */
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of 
      *       (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/flash_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/flash_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -67,7 +67,8 @@
 };
 
 static const flash_target_config_t flash_target_config = {
-    .page_size  = 0x800,    // 2 KB
+    .page_size  = 4,        // 4 bytes
+                            // Here page_size is program unit, which is different than FMC definition.
     .flash_start = 0x0,
     .flash_size = 0x80000,  // 512 KB
     .sectors = sectors_info,

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -47,6 +47,9 @@
 #define TMR_CMP_MIN         2
 #define TMR_CMP_MAX         0xFFFFFFu
 
+/* NOTE: When system clock is higher than timer clock, we need to add 3 engine clock
+ *       (recommended by designer) delay to wait for above timer control to take effect. */
+
 void lp_ticker_init(void)
 {
     if (ticker_inited) {
@@ -63,27 +66,38 @@
     // Enable IP clock
     CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
 
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
     // Configure clock
-    uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
     uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
     MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
     uint32_t cmp_timer = TMR_CMP_MAX;
     MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
     // Continuous mode
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk;
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
+    timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk;
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    timer_base->CMP = cmp_timer;
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 
     // Set vector
     NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
 
     NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
 
-    TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+    TIMER_EnableInt(timer_base);
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    TIMER_EnableWakeup(timer_base);
     wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-    TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+
+    TIMER_Start(timer_base);
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
+    /* Wait for timer to start counting and raise active flag */
+    while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
 }
 
 timestamp_t lp_ticker_read()
@@ -92,7 +106,7 @@
         lp_ticker_init();
     }
 
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     return  (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
 }
@@ -107,27 +121,27 @@
      * This behavior is not what we want. To fix it, we could configure new CMP value
      * without stopping counting first.
      */
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of 
      *       (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
     uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
     cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+
     timer_base->CMP = cmp_timer;
-
-    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
     wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
-    TIMER_Start(timer_base);
 }
 
 void lp_ticker_disable_interrupt(void)
 {
     TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 }
 
 void lp_ticker_clear_interrupt(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
 }
 
 void lp_ticker_fire_interrupt(void)
@@ -149,8 +163,11 @@
 static void tmr1_vec(void)
 {
     TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
     TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    
+    wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+
     // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
     lp_ticker_irq_handler();
 }

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -13,7 +13,7 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
- 
+
 #include "rtc_api.h"
 
 #if DEVICE_RTC
@@ -24,8 +24,65 @@
 #include "nu_miscutil.h"
 #include "mbed_mktime.h"
 
-#define YEAR0       1900
-//#define EPOCH_YR    1970
+/* Micro seconds per second */
+#define NU_US_PER_SEC               1000000
+/* Timer clock per second
+ *
+ * NOTE: This dependents on real hardware.
+ */
+#define NU_RTCCLK_PER_SEC           (__LXT)
+
+/* Strategy for implementation of RTC HAL
+ *
+ * H/W RTC just supports year range 2000~2099, which cannot fully cover POSIX time (starting since 2970)
+ * and date time of struct TM (starting since 1900).
+ *
+ * To conquer the difficulty, we don't use H/W RTC to keep real date time. Instead, we use it to keep
+ * elapsed time in seconds since one reference time point. The strategy would be:
+ *
+ * 1. Choose DATETIME_HWRTC_ORIGIN (00:00:00 UTC, Saturday, 1 January 2000) as reference time point of H/W RTC.
+ * 2. t_hwrtc_origin = DATETIME_HWRTC_ORIGIN in POSIX time
+ * 3. t_hwrtc_elapsed = t_hwrtc_origin + elapsed time since t_hwrtc_origin
+ * 4. t_write = POSIX time set by rtc_write().
+ * 5. t_present = rtc_read() = t_write + (t_hwrtc_elapsed - t_hwrtc_origin)
+ *
+ * 1900
+ * |---------------------------------------------------------------------------------|
+ *           1970    t_write           t_present
+ * |---------|-------|-----------------|---------------------------------------------|
+ * 
+ * 2000 
+ * |-----------------|---------------------------------------------------------------|
+ * t_hwrtc_origin    t_hwrtc_elapsed
+ *
+ */
+/* Start year of struct TM*/
+#define NU_TM_YEAR0         1900
+/* Start year of POSIX time (set_time()/time()) */
+#define NU_POSIX_YEAR0      1970
+/* Start year of H/W RTC */
+#define NU_HWRTC_YEAR0      2000
+
+/* RTC H/W origin time: 00:00:00 UTC, Saturday, 1 January 2000 */
+static const S_RTC_TIME_DATA_T DATETIME_HWRTC_ORIGIN = {
+    2000,           /* Year value, range between 2000 ~ 2099 */
+    1,              /* Month value, range between 1 ~ 12 */
+    1,              /* Day value, range between 1 ~ 31 */
+    RTC_SATURDAY,   /* Day of the week */
+    0,              /* Hour value, range between 0 ~ 23 */
+    0,              /* Minute value, range between 0 ~ 59 */
+    0,              /* Second value, range between 0 ~ 59 */
+    RTC_CLOCK_24,   /* 12-Hour (RTC_CLOCK_12) / 24-Hour (RTC_CLOCK_24) */
+    0               /* RTC_AM / RTC_PM (used only for 12-Hour) */
+};
+/* t_hwrtc_origin initialized or not? */
+static bool t_hwrtc_origin_inited = 0;
+/* POSIX time of DATETIME_HWRTC_ORIGIN (since 00:00:00 UTC, Thursday, 1 January 1970) */
+static time_t t_hwrtc_origin = 0;
+/* POSIX time set by rtc_write() */
+static time_t t_write = 0;
+/* Convert date time from H/W RTC to struct TM */
+static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc);
 
 static const struct nu_modinit_s rtc_modinit = {RTC_0, RTC_MODULE, 0, 0, 0, RTC_IRQn, NULL};
 
@@ -34,8 +91,11 @@
     if (rtc_isenabled()) {
         return;
     }
-    
+
     RTC_Open(NULL);
+
+    /* POSIX time origin (00:00:00 UTC, Thursday, 1 January 1970) */
+    rtc_write(0);
 }
 
 void rtc_free(void)
@@ -55,6 +115,57 @@
     return !! (RTC->INIT & RTC_INIT_INIT_Active_Msk);
 }
 
+time_t rtc_read(void)
+{
+    /* NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
+     *       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
+     */
+    if (! rtc_isenabled()) {
+        rtc_init();
+    }
+
+    /* Used for intermediary between date time of H/W RTC and POSIX time */
+    struct tm datetime_tm;
+
+    if (! t_hwrtc_origin_inited) {
+        t_hwrtc_origin_inited = 1;
+        
+        /* Convert date time from H/W RTC to struct TM */     
+        rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &DATETIME_HWRTC_ORIGIN);
+        /* Convert date time of struct TM to POSIX time */
+        if (! _rtc_maketime(&datetime_tm, &t_hwrtc_origin, RTC_FULL_LEAP_YEAR_SUPPORT)) {
+            return 0;
+        }
+    }
+
+    S_RTC_TIME_DATA_T hwrtc_datetime_2K_present;
+    RTC_GetDateAndTime(&hwrtc_datetime_2K_present);
+    /* Convert date time from H/W RTC to struct TM */
+    rtc_convert_datetime_hwrtc_to_tm(&datetime_tm, &hwrtc_datetime_2K_present);
+    /* Convert date time of struct TM to POSIX time */
+    time_t t_hwrtc_elapsed;
+    if (! _rtc_maketime(&datetime_tm, &t_hwrtc_elapsed, RTC_FULL_LEAP_YEAR_SUPPORT)) {
+        return 0;
+    }
+
+    /* Present time in POSIX time */
+    time_t t_present = t_write + (t_hwrtc_elapsed - t_hwrtc_origin);
+    return t_present;
+}
+
+void rtc_write(time_t t)
+{
+    if (! rtc_isenabled()) {
+        rtc_init();
+    }
+
+    t_write = t;
+
+    RTC_SetDateAndTime((S_RTC_TIME_DATA_T *) &DATETIME_HWRTC_ORIGIN);
+    /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+    wait_us((NU_US_PER_SEC / NU_RTCCLK_PER_SEC) * 3);
+}
+
 /*
  struct tm
    tm_sec      seconds after the minute 0-61
@@ -67,66 +178,18 @@
    tm_yday     days since January 1 0-365
    tm_isdst    Daylight Saving Time flag
 */
-
-time_t rtc_read(void)
+static void rtc_convert_datetime_hwrtc_to_tm(struct tm *datetime_tm, const S_RTC_TIME_DATA_T *datetime_hwrtc)
 {
-    // NOTE: After boot, RTC time registers are not synced immediately, about 1 sec latency.
-    //       RTC time got (through RTC_GetDateAndTime()) in this sec would be last-synced and incorrect.
-    if (! rtc_isenabled()) {
-        rtc_init();
-    }
-    
-    S_RTC_TIME_DATA_T rtc_datetime;
-    RTC_GetDateAndTime(&rtc_datetime);
-    
-    struct tm timeinfo;
-
-    // Convert struct tm to S_RTC_TIME_DATA_T
-    timeinfo.tm_year = rtc_datetime.u32Year - YEAR0;
-    timeinfo.tm_mon  = rtc_datetime.u32Month - 1;
-    timeinfo.tm_mday = rtc_datetime.u32Day;
-    timeinfo.tm_wday = rtc_datetime.u32DayOfWeek;
-    timeinfo.tm_hour = rtc_datetime.u32Hour;
-    if (rtc_datetime.u32TimeScale == RTC_CLOCK_12 && rtc_datetime.u32AmPm == RTC_PM) {
-        timeinfo.tm_hour += 12;
+    datetime_tm->tm_year = datetime_hwrtc->u32Year - NU_TM_YEAR0;
+    datetime_tm->tm_mon  = datetime_hwrtc->u32Month - 1;
+    datetime_tm->tm_mday = datetime_hwrtc->u32Day;
+    datetime_tm->tm_wday = datetime_hwrtc->u32DayOfWeek;
+    datetime_tm->tm_hour = datetime_hwrtc->u32Hour;
+    if (datetime_hwrtc->u32TimeScale == RTC_CLOCK_12 && datetime_hwrtc->u32AmPm == RTC_PM) {
+        datetime_tm->tm_hour += 12;
     }
-    timeinfo.tm_min  = rtc_datetime.u32Minute;
-    timeinfo.tm_sec  = rtc_datetime.u32Second;
-
-    // Convert to timestamp
-    time_t t = _rtc_mktime(&timeinfo);
-
-    return t;
-}
-
-void rtc_write(time_t t)
-{
-    if (! rtc_isenabled()) {
-        rtc_init();
-    }
-    
-    // Convert timestamp to struct tm
-    struct tm timeinfo;
-    if (_rtc_localtime(t, &timeinfo) == false) {
-        return;
-    }
-
-    S_RTC_TIME_DATA_T rtc_datetime;
-    
-    // Convert S_RTC_TIME_DATA_T to struct tm
-    rtc_datetime.u32Year        = timeinfo.tm_year + YEAR0;
-    rtc_datetime.u32Month       = timeinfo.tm_mon + 1;
-    rtc_datetime.u32Day         = timeinfo.tm_mday;
-    rtc_datetime.u32DayOfWeek   = timeinfo.tm_wday;
-    rtc_datetime.u32Hour        = timeinfo.tm_hour;
-    rtc_datetime.u32Minute      = timeinfo.tm_min;
-    rtc_datetime.u32Second      = timeinfo.tm_sec;
-    rtc_datetime.u32TimeScale   = RTC_CLOCK_24;
-    
-    // NOTE: Timing issue with write to RTC registers. This delay is empirical, not rational.
-    RTC_SetDateAndTime(&rtc_datetime);
-    //nu_nop(6000);
-    wait_us(100);
+    datetime_tm->tm_min  = datetime_hwrtc->u32Minute;
+    datetime_tm->tm_sec  = datetime_hwrtc->u32Second;
 }
 
 #endif

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -543,6 +543,10 @@
         // Register DMA event handler
         dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
         serial_tx_enable_interrupt(obj, handler, 1);
+        /* We needn't actually enable UART INT to go UART ISR -> handler.
+         * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
+         * with serial_tx/rx_enable_interrupt having set up this call path. */
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
         ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk;  // Start DMA transfer
     }
     
@@ -604,6 +608,10 @@
         // Register DMA event handler
         dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
         serial_rx_enable_interrupt(obj, handler, 1);
+        /* We needn't actually enable UART INT to go UART ISR -> handler.
+         * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
+         * with serial_tx/rx_enable_interrupt having set up this call path. */
+        UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
         ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk;  // Start DMA transfer
     }
 }

--- a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -58,22 +58,27 @@
     // Enable IP clock
     CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
 
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
     // Timer for normal counter
-    uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    uint32_t clk_timer = TIMER_GetModuleClock(timer_base);
     uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
     MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
     MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
     uint32_t cmp_timer = TMR_CMP_MAX;
     MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk;
-    ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
+    timer_base->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk;
+    timer_base->CMP = cmp_timer;
 
     NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
 
     NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
 
-    TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
-    TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+    TIMER_EnableInt(timer_base);
+
+    TIMER_Start(timer_base);
+    /* Wait for timer to start counting and raise active flag */
+    while(! (timer_base->CTL & TIMER_CTL_ACTSTS_Msk));
 }
 
 uint32_t us_ticker_read()
@@ -82,7 +87,7 @@
         us_ticker_init();
     }
 
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     return  (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
 }
@@ -97,7 +102,7 @@
      * This behavior is not what we want. To fix it, we could configure new CMP value
      * without stopping counting first.
      */
-    TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+    TIMER_T *timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
 
     /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of 
      *       (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */

--- a/targets/TARGET_NUVOTON/nu_timer.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NUVOTON/nu_timer.h	Thu Apr 19 17:12:19 2018 +0100
@@ -20,7 +20,7 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include "cmsis.h"
-#include "mbed_sleep.h"
+#include "mbed_power_mgmt.h"
 #include "mbed_critical.h"
 #include "ticker_api.h"
 #include "us_ticker_api.h"

--- a/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_LPC176X/device/flash_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -112,42 +112,64 @@
         const uint8_t *data, uint32_t size)
 {
     unsigned long n;
-    // always malloc outside critical section
-    uint8_t *alignedData = malloc(size);
+    const uint32_t copySize = 1024; // should be 256|512|1024|4096
+    uint8_t *alignedData, *source;
+
+    alignedData = 0;
+    source = (uint8_t *)data;
+
+    // check word boundary
+    if (((uint32_t)data % 4) != 0) {
+        // always malloc outside critical section
+        alignedData = malloc(copySize);
+        if (alignedData == 0) {
+            return (1);
+        }
+    }
 
     n = GetSecNum(address); // Get Sector Number
 
     core_util_critical_section_enter();
-    IAP.cmd = 50;// Prepare Sector for Write
-    IAP.par[0] = n;// Start Sector
-    IAP.par[1] = n;// End Sector
-    IAP_Call (&IAP.cmd, &IAP.stat);// Call IAP Command
-    if (IAP.stat) {
-        return (1); // Command Failed
+
+    while (size) {
+        if (((uint32_t)data % 4) != 0) {
+            memcpy(alignedData, source, copySize);
+            source = alignedData;
+        }
+
+        /*
+        Prepare_Sector_for_Write command must be exected before
+        Copy_RAM_to_Flash command.
+        */
+        IAP.cmd = 50;    // Prepare Sector for Write
+        IAP.par[0] = n;  // Start Sector
+        IAP.par[1] = n;  // End Sector
+        IAP_Call (&IAP.cmd, &IAP.stat); // Call IAP Command
+        if (IAP.stat) {
+            return (1); // Command Failed
+        }
+
+        IAP.cmd = 51; // Copy RAM to Flash
+        IAP.par[0] = address; // Destination Flash Address
+        IAP.par[1] = (unsigned long)source; // Source RAM Address        
+        IAP.par[2] = copySize; // number of bytes to be written
+        IAP.par[3] = CCLK; // CCLK in kHz
+        IAP_Call (&IAP.cmd, &IAP.stat); // Call IAP Command
+        if (IAP.stat) {
+            return (1); // Command Failed
+        }
+
+        source += copySize;
+        size -= copySize;
+        address += copySize;
     }
 
-    IAP.cmd = 51; // Copy RAM to Flash
-    IAP.par[0] = address;// Destination Flash Address
-
-    if ((unsigned long)data%4==0) { // Word boundary
-        IAP.par[1] = (unsigned long)data;// Source RAM Address
-    } else {
-        memcpy(alignedData,data,size);
-        IAP.par[1] = (unsigned long)alignedData; // Source RAM Address
-    }
-
-    IAP.par[2] = 1024; // Fixed Page Size
-    IAP.par[3] = CCLK;// CCLK in kHz
-    IAP_Call (&IAP.cmd, &IAP.stat);// Call IAP Command
     core_util_critical_section_exit();
 
-    if(alignedData !=0) { // We allocated our own memory
+    if(alignedData != 0) { // We allocated our own memory
         free(alignedData);
     }
 
-    if (IAP.stat) {
-        return (1); // Command Failed
-    }
     return (0); // Finished without Errors
 }
 

--- a/targets/TARGET_NXP/TARGET_LPC176X/rtc_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_LPC176X/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -89,7 +89,10 @@
     timeinfo.tm_year = LPC_RTC->YEAR - 1900;
     
     // Convert to timestamp
-    time_t t = _rtc_mktime(&timeinfo);
+    time_t t;
+    if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
+        return 0;
+    }
     
     return t;
 }
@@ -97,10 +100,10 @@
 void rtc_write(time_t t) {
     // Convert the time in to a tm
     struct tm timeinfo;
-    if (_rtc_localtime(t, &timeinfo) == false) {
+    if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
         return;
     }
-    
+
     // Pause clock, and clear counter register (clears us count)
     LPC_RTC->CCR |= 2;
     

--- a/targets/TARGET_NXP/TARGET_LPC408X/rtc_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_LPC408X/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -88,7 +88,10 @@
     timeinfo.tm_year = LPC_RTC->YEAR - 1900;
     
     // Convert to timestamp
-    time_t t = _rtc_mktime(&timeinfo);
+    time_t t;
+    if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
+        return 0;
+    }
     
     return t;
 }
@@ -96,10 +99,10 @@
 void rtc_write(time_t t) {
     // Convert the time in to a tm
     struct tm timeinfo;
-    if (_rtc_localtime(t, &timeinfo) == false) {
+    if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
         return;
     }
-    
+
     // Pause clock, and clear counter register (clears us count)
     LPC_RTC->CCR |= 2;
     

--- a/targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_LPC43XX/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -102,7 +102,10 @@
     timeinfo.tm_year = LPC_RTC->TIME[RTC_TIMETYPE_YEAR] - 1900;
     
     // Convert to timestamp
-    time_t t = _rtc_mktime(&timeinfo);
+    time_t t;
+    if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
+        return 0;
+    }
     
     return t;
 }
@@ -110,10 +113,10 @@
 void rtc_write(time_t t) {
     // Convert the time in to a tm
     struct tm timeinfo;
-    if (_rtc_localtime(t, &timeinfo) == false) {
+    if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
         return;
     }
-    
+
     // Pause clock, and clear counter register (clears us count)
     LPC_RTC->CCR |= 2;
     

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/flash_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,129 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "flash_api.h"
+#include "mbed_critical.h"
+
+#if DEVICE_FLASH
+
+#include "fsl_flashiap.h"
+
+int32_t flash_init(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    uint32_t n;
+    uint32_t status;
+    int32_t ret = -1;
+
+    /* We need to prevent flash accesses during erase operation */
+    core_util_critical_section_enter();
+
+    n = address / FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES;   // Get Sector Number
+
+    status = FLASHIAP_PrepareSectorForWrite(n, n);
+    if (status == kStatus_FLASHIAP_Success) {
+        status = FLASHIAP_EraseSector(n, n, SystemCoreClock);
+        if (status == kStatus_FLASHIAP_Success) {
+            ret = 0;
+        }
+    }
+
+    core_util_critical_section_exit();
+
+    return ret;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+    uint32_t n;
+    uint32_t sector_number;
+
+    uint32_t status;
+    int32_t ret = -1;
+    uint8_t buf[FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES];
+
+    if (address == 0) {                              // Check for Vector Table
+        n = *((unsigned long *)(data + 0)) +
+            *((unsigned long *)(data + 1)) +
+            *((unsigned long *)(data + 2)) +
+            *((unsigned long *)(data + 3)) +
+            *((unsigned long *)(data + 4)) +
+            *((unsigned long *)(data + 5)) +
+            *((unsigned long *)(data + 6));
+        *((unsigned long *)(data + 7)) = 0 - n;  // Signature at Reserved Vector
+    }
+
+    /* Copy into a local buffer to ensure address is word-aligned */
+    memcpy(&buf, data, FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES);
+
+    /* We need to prevent flash accesses during program operation */
+    core_util_critical_section_enter();
+
+    sector_number = address / FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES;  // Get Sector Number
+
+    status = FLASHIAP_PrepareSectorForWrite(sector_number, sector_number);
+    if (status == kStatus_FLASHIAP_Success) {
+        status = FLASHIAP_CopyRamToFlash(address, (uint32_t *)&buf,
+                                        FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES, SystemCoreClock);
+        if (status == kStatus_FLASHIAP_Success) {
+            ret = 0;
+        }
+    }
+
+    core_util_critical_section_exit();
+
+    return ret;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    uint32_t sectorsize = MBED_FLASH_INVALID_SIZE;
+    uint32_t devicesize = FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES;
+    uint32_t startaddr = 0;
+
+    if ((address >= startaddr) && (address < (startaddr + devicesize))) {
+        sectorsize = FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES;
+    }
+
+    return sectorsize;
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    uint32_t startaddr = 0;
+
+    return startaddr;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+    return FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES;
+}
+
+#endif

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/objects.h	Thu Apr 19 17:12:19 2018 +0100
@@ -58,6 +58,12 @@
     uint8_t bits;
 };
 
+#if DEVICE_FLASH
+struct flash_s {
+    uint8_t dummy;
+};
+#endif
+
 #include "gpio_object.h"
 
 #ifdef __cplusplus

--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/PinNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -217,7 +217,8 @@
     PullUp_47K  = 2,
     PullUp_100K = 3,
     PullUp_22K  = 4,
-    PullDefault = PullUp_47K
+    PullDefault = PullUp_47K,
+    PullUp = PullUp_47K
 } PinMode;
 
 #ifdef __cplusplus

--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/exceptions.c	Thu Apr 19 17:12:19 2018 +0100
@@ -68,12 +68,6 @@
     while (1) {};
 }
 
-/** Hardware fault interrupt handler */
-void HardFault_Handler(void)
-{
-    while (1) {};
-}
-
 /*************************************************************************************************
 *                                                                                                *
 *  Functions                                                                                     *

--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/sleep.c	Thu Apr 19 17:12:19 2018 +0100
@@ -31,7 +31,7 @@
  *
  */
 #if DEVICE_SLEEP
-#include "mbed_sleep.h"
+#include "mbed_power_mgmt.h"
 #include "sleep_api.h"
 #include "cmsis_nvic.h"
 

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/iodefines/iodefine_typedef.h	Thu Apr 19 17:12:19 2018 +0100
@@ -54,7 +54,9 @@
 typedef enum iodefine_byte_select_t
 {
     R_IO_L = 0, R_IO_H = 1,
-    R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3
+    R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3,
+    L = 0, H = 1,
+    LL= 0, LH = 1, HL = 2, HH = 3
 } iodefine_byte_select_t;
 
 

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,3 +1,19 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
 #ifndef RESERVED_PINS_H
 #define RESERVED_PINS_H
 

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h	Thu Apr 19 17:12:19 2018 +0100
@@ -26,23 +26,12 @@
 #endif
 /* <-Take measures about optimization problems of web compiler */
 
-
-
-
-
-
-
-
-
-
+#define TRANSACTION_QUEUE_SIZE_SPI 16
 
 #define DEVICE_ID_LENGTH       32
 #define DEVICE_MAC_OFFSET      20
 
-
-
-
-
 #include "objects.h"
+#include "dma_api.h"
 
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c	Thu Apr 19 17:12:19 2018 +0100
@@ -47,7 +47,9 @@
 
 #define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
 
+#if (defined(TARGET_DEBUG) || !defined(RUN_FROM_SDRAM))
 #define CS2_SDRAM
+#endif
 
 /******************************************************************************
 Imported global variables and functions (from other files)

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/VKRZA1H.sct	Thu Apr 19 17:12:19 2018 +0100
@@ -1,42 +1,62 @@
+#! armcc -E -I"../"
+;**************************************************
+; Copyright (c) 2017 ARM Ltd.  All rights reserved.
+;**************************************************
 
+; Scatter-file for RTX Example on Versatile Express
 
-LOAD_TTB    0x20000000 0x00004000 ; Page 0 of On-Chip Data Retention RAM
+; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
+
+#include "mbed_config.h"
+#include "mem_VK_RZ_A1H.h"
+
+LOAD_TTB    __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
 {
     TTB     +0 EMPTY 0x4000            
     { }                           ; Level-1 Translation Table for MMU
 }
 
-SDRAM       0x08000000 0x02000000 ; 32MB External SDRAM region
+SFLASH __ROM_BASE __ROM_SIZE       ; load region size_region
 {
-}
+  VECTORS __VECTOR_BASE FIXED
+  {
+    * (RESET, +FIRST)         ; Vector table and other startup code
+    * (InRoot$$Sections)      ; All (library) code that must be in a root region
+    * (+RO-CODE)              ; Application RO code (.text)
+  }
 
-SFLASH_DUAL 0x18020000 (32*1024*1024-2*64*1024)
-{
-    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-    ; S-Flash ROM : Executable cached region
-    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+  RO_DATA    +0
+  { * (+RO-DATA) }              ; Application RO data (.constdata)
+
+  RW_DATA    __DATA_BASE
+  { * (+RW) }                   ; Application RW data (.data)
 
-    VECTORS 0x18020000 FIXED
-    {
-        * (RESET, +FIRST)         ; Vector table and other (assembler) startup code
-        * (InRoot$$Sections)      ; All (library) code that must be in a root region
-        * (+RO-CODE)              ; Application RO code (.text)
-    }
+  RW_IRAM1    +0 ALIGN 0x10
+  { * (+ZI) }                   ; Application ZI data (.bss)
+
+  ARM_LIB_HEAP  +0
+  { * (HEAP) }                  ; Application heap area (HEAP)
 
-    RO_DATA    +0
-    { * (+RO-DATA) }              ; Application RO data (.constdata)
+  ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE      ; Stack region growing down
+  { }
 
-    RW_DATA    0x20020000
-    { * (+RW) }                   ; Application RW data (.data)
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+  ; RAM-NC : Internal non-cached RAM region
+  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
-    ZI_DATA    +0 ALIGN 0x400
-    { * (+ZI) }                   ; Application ZI data (.bss)
-
-    RW_DATA_NC 0x60900000 0x00100000
+  RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE
     { * (NC_DATA) }              ; Application RW data Non cached area
 
     ZI_DATA_NC +0
     { * (NC_BSS) }               ; Application ZI data Non cached area
 }
 
-
+#ifndef RUN_FROM_SDRAM
+SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region
+{
+}
+#else
+SRAM 0x200A0000 0x00960000 ; 9.5MB Internal SRAM region (0.5MB SDCARD Bootloader !!!)
+{
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/mem_VK_RZ_A1H.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,95 @@
+/**************************************************************************//**
+ * @file     mem_VK_RZ_A1H.h
+ * @brief    Memory base and size definitions (used in scatter file)
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __MEM_VK_RZ_A1H_H
+#define __MEM_VK_RZ_A1H_H
+
+/*----------------------------------------------------------------------------
+  User Stack & Heap size definition
+ *----------------------------------------------------------------------------*/
+/*
+//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+*/
+
+/*--------------------- ROM Configuration ------------------------------------
+//
+// <h> ROM Configuration
+//   <o0> ROM Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> ROM Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#ifdef RUN_FROM_SDRAM
+ #define __ROM_BASE       0x08000000
+ #define __ROM_SIZE       0x02000000
+ #define __VECTOR_BASE    0x08000000
+ #define __DATA_BASE	  +0 ALIGN 0x100000
+#elif defined (RUN_FROM_SRAM)
+ #define __ROM_BASE       0x200A0000
+ #define __ROM_SIZE       0x00960000
+ #define __VECTOR_BASE    0x200A0000
+ #define __DATA_BASE	  +0 ALIGN 0x100000 NOCOMPRESS
+#else
+ #define __ROM_BASE       0x18020000
+ #define __ROM_SIZE       0x01FE0000
+ #define __VECTOR_BASE    0x18020000
+ #define __DATA_BASE	  0x20020000
+#endif
+
+/*--------------------- RAM Configuration -----------------------------------
+ *----------------------------------------------------------------------------*/
+#ifdef RUN_FROM_SDRAM
+#define __RAM_BASE       0x08000000
+#define __RAM_SIZE       0x02000000
+#define __NC_RAM_SIZE    0x00200000
+#else
+#define __RAM_BASE       0x20000000
+#define __RAM_SIZE       0x00A00000
+#define __NC_RAM_SIZE    0x00100000
+#endif
+#define __NM_RAM_SIZE    (__RAM_SIZE - __NC_RAM_SIZE)
+#define __DATA_NC_BASE   (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
+
+#define __UND_STACK_SIZE 0x00000100
+#define __SVC_STACK_SIZE 0x00008000
+#define __ABT_STACK_SIZE 0x00000100
+#define __FIQ_STACK_SIZE 0x00000100
+#define __IRQ_STACK_SIZE 0x0000F000
+#define __STACK_SIZE     (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------------- TTB Configuration ------------------------------------
+//
+// <h> TTB Configuration
+//   <o0> TTB Base Address <0x0-0xFFFFFFFF:8>
+//   <o1> TTB Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+ *----------------------------------------------------------------------------*/
+#define __TTB_BASE       0x20000000
+#define __TTB_SIZE       0x00004000
+
+#endif /* __MEM_VK_RZ_A1H_H */

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VKRZA1H.S	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,454 +0,0 @@
-;/*****************************************************************************
-; * @file:    startup_VKRZA1H.s
-; * @purpose: CMSIS Cortex-A9 Core Device Startup File 
-; *           for the Renesas RZA1H Device Series
-; * @version: V1.02, modified for mbed
-; * @date:    27. July 2009, modified 3rd Aug 2009
-; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-; *
-; * Copyright (C) 2009 ARM Limited. All rights reserved.
-; * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
-; * processor based microcontrollers.  This file can be freely distributed 
-; * within development tools that are supporting such ARM based processors. 
-; *
-; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
-; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
-; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
-; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
-; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
-; *
-; *****************************************************************************/
-
-GICI_BASE       EQU     0xe8202000
-ICCIAR_OFFSET   EQU     0x0000000C
-ICCEOIR_OFFSET  EQU     0x00000010
-ICCHPIR_OFFSET  EQU     0x00000018
-
-GICD_BASE       EQU     0xe8201000
-ICDISER0_OFFSET EQU     0x00000100
-ICDICER0_OFFSET EQU     0x00000180
-ICDISPR0_OFFSET EQU     0x00000200
-ICDABR0_OFFSET  EQU     0x00000300
-ICDIPR0_OFFSET  EQU     0x00000400
-
-Mode_USR        EQU     0x10
-Mode_FIQ        EQU     0x11
-Mode_IRQ        EQU     0x12
-Mode_SVC        EQU     0x13
-Mode_ABT        EQU     0x17
-Mode_UND        EQU     0x1B
-Mode_SYS        EQU     0x1F
-
-I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
-F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled
-T_Bit           EQU     0x20            ; when T bit is set, core is in Thumb state
-
-GIC_ERRATA_CHECK_1     EQU     0x000003FE
-GIC_ERRATA_CHECK_2     EQU     0x000003FF
-
-
-Sect_Normal     EQU     0x00005c06 ;outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
-Sect_Normal_Cod EQU     0x0000dc06 ;outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
-Sect_Normal_RO  EQU     0x0000dc16 ;as Sect_Normal_Cod, but not executable
-Sect_Normal_RW  EQU     0x00005c16 ;as Sect_Normal_Cod, but writeable and not executable
-Sect_SO         EQU     0x00000c12 ;strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
-Sect_Device_RO  EQU     0x00008c12 ;device, non-shareable, non-executable, ro, domain 0, base addr 0
-Sect_Device_RW  EQU     0x00000c12 ;as Sect_Device_RO, but writeable
-Sect_Fault      EQU     0x00000000 ;this translation will fault (the bottom 2 bits are important, the rest are ignored)
-
-RAM_BASE        EQU     0x80000000
-VRAM_BASE       EQU     0x18000000
-SRAM_BASE       EQU     0x2e000000
-ETHERNET        EQU     0x1a000000
-CS3_PERIPHERAL_BASE EQU 0x1c000000
-
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes, per mode) <0x0-0xFFFFFFFF:8>
-; </h>
-
-UND_Stack_Size  EQU     0x00000100
-SVC_Stack_Size  EQU     0x00008000
-ABT_Stack_Size  EQU     0x00000100
-FIQ_Stack_Size  EQU     0x00000100
-IRQ_Stack_Size  EQU     0x00008000
-USR_Stack_Size  EQU     0x00004000
-
-ISR_Stack_Size  EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
-                         FIQ_Stack_Size + IRQ_Stack_Size)
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   USR_Stack_Size
-__initial_sp    SPACE   ISR_Stack_Size
-
-Stack_Top
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00080000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-
-                PRESERVE8
-                ARM
-
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, CODE, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       LDR     PC, Reset_Addr            ; Address of Reset Handler
-                LDR     PC, Undef_Addr            ; Address of Undef Handler
-                LDR     PC, SVC_Addr              ; Address of SVC Handler
-                LDR     PC, PAbt_Addr             ; Address of Prefetch Abort Handler
-                LDR     PC, DAbt_Addr             ; Address of Data Abort Handler
-                NOP                               ; Reserved Vector
-                LDR     PC, IRQ_Addr              ; Address of IRQ Handler
-                LDR     PC, FIQ_Addr              ; Address of FIQ Handler
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-Reset_Addr      DCD     Reset_Handler
-Undef_Addr      DCD     Undef_Handler
-SVC_Addr        DCD     SVC_Handler
-PAbt_Addr       DCD     PAbt_Handler
-DAbt_Addr       DCD     DAbt_Handler
-IRQ_Addr        DCD     IRQ_Handler
-FIQ_Addr        DCD     FIQ_Handler
-
-                AREA    |.text|, CODE, READONLY
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  InitMemorySubsystem
-                IMPORT  __main
-                IMPORT  RZ_A1_SetSramWriteEnable
-
-                ; Put any cores other than 0 to sleep
-                MRC     p15, 0, R0, c0, c0, 5     ; Read MPIDR
-                ANDS    R0, R0, #3
-goToSleep
-                WFINE
-                BNE     goToSleep
-
-; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
-; Enables Full Access i.e. in both privileged and non privileged modes
-                MRC     p15, 0, r0, c1, c0, 2       ; Read Coprocessor Access Control Register (CPACR)
-                ORR     r0, r0, #(0xF << 20)        ; Enable access to CP 10 & 11
-                MCR     p15, 0, r0, c1, c0, 2       ; Write Coprocessor Access Control Register (CPACR)
-                ISB
-
-; Switch on the VFP and NEON hardware
-                MOV     r0, #0x40000000
-                VMSR    FPEXC, r0                   ; Write FPEXC register, EN bit set
-
-                MRC     p15, 0, R0, c1, c0, 0       ; Read CP15 System Control register
-                BIC     R0, R0, #(0x1 << 12)        ; Clear I bit 12 to disable I Cache
-                BIC     R0, R0, #(0x1 <<  2)        ; Clear C bit  2 to disable D Cache
-                BIC     R0, R0, #0x1                ; Clear M bit  0 to disable MMU
-                BIC     R0, R0, #(0x1 << 11)        ; Clear Z bit 11 to disable branch prediction
-                BIC     R0, R0, #(0x1 << 13)        ; Clear V bit 13 to disable hivecs
-                MCR     p15, 0, R0, c1, c0, 0       ; Write value back to CP15 System Control register
-                ISB
-
-; Set Vector Base Address Register (VBAR) to point to this application's vector table
-                LDR     R0, =__Vectors
-                MCR     p15, 0, R0, c12, c0, 0
-
-;  Setup Stack for each exceptional mode
-                LDR     R0, =Stack_Top
-
-;  Enter Undefined Instruction Mode and set its Stack Pointer
-                MSR     CPSR_C, #Mode_UND:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-                SUB     R0, R0, #UND_Stack_Size
-
-;  Enter Abort Mode and set its Stack Pointer
-                MSR     CPSR_C, #Mode_ABT:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-                SUB     R0, R0, #ABT_Stack_Size
-
-;  Enter FIQ Mode and set its Stack Pointer
-                MSR     CPSR_C, #Mode_FIQ:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-                SUB     R0, R0, #FIQ_Stack_Size
-
-;  Enter IRQ Mode and set its Stack Pointer
-                MSR     CPSR_C, #Mode_IRQ:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-                SUB     R0, R0, #IRQ_Stack_Size
-
-;  Enter Supervisor Mode and set its Stack Pointer
-                MSR     CPSR_C, #Mode_SVC:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-
-;  Enter System Mode to complete initialization and enter kernel
-                MSR     CPSR_C, #Mode_SYS:OR:I_Bit:OR:F_Bit
-                MOV     SP, R0
-
-                ISB
-
-                LDR     R0, =RZ_A1_SetSramWriteEnable
-                BLX     R0
-
-                IMPORT  create_translation_table
-                BL      create_translation_table
-
-;  USR/SYS stack pointer will be set during kernel init
-
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =InitMemorySubsystem
-                BLX     R0
-                LDR     R0, =__main
-                BLX     R0
-
-                ENDP
-
-Undef_Handler\
-                PROC
-                EXPORT  Undef_Handler             [WEAK]
-                IMPORT  CUndefHandler
-                SRSFD   SP!, #Mode_UND
-                PUSH    {R0-R4, R12}              ; Save APCS corruptible registers to UND mode stack
-
-                MRS     R0, SPSR
-                TST     R0, #T_Bit                ; Check mode
-                MOVEQ   R1, #4                    ; R1 = 4 ARM mode
-                MOVNE   R1, #2                    ; R1 = 2 Thumb mode
-                SUB     R0, LR, R1
-                LDREQ   R0, [R0]                  ; ARM mode - R0 points to offending instruction
-                BEQ     undef_cont
-
-                ;Thumb instruction
-                ;Determine if it is a 32-bit Thumb instruction
-                LDRH    R0, [R0]
-                MOV     R2, #0x1c
-                CMP     R2, R0, LSR #11
-                BHS     undef_cont                ;16-bit Thumb instruction
-
-                ;32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction.
-                LDRH    R2, [LR]
-                ORR     R0, R2, R0, LSL #16
-undef_cont
-                MOV     R2, LR                    ; Set LR to third argument
-                
-;               AND     R12, SP, #4               ; Ensure stack is 8-byte aligned
-                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               ; Adjust stack
-                PUSH    {R12, LR}                 ; Store stack adjustment and dummy LR
-
-                ;R0 Offending instruction
-                ;R1 =2 (Thumb) or =4 (ARM)
-                BL      CUndefHandler
-
-                POP     {R12, LR}                 ; Get stack adjustment & discard dummy LR
-                ADD     SP, SP, R12               ; Unadjust stack
-
-                LDR     LR, [SP, #24]             ; Restore stacked LR and possibly adjust for retry
-                SUB     LR, LR, R0
-                LDR     R0, [SP, #28]             ; Restore stacked SPSR
-                MSR     SPSR_CXSF, R0
-                POP     {R0-R4, R12}              ; Restore stacked APCS registers
-                ADD     SP, SP, #8                ; Adjust SP for already-restored banked registers
-                MOVS    PC, LR
-                ENDP
-
-PAbt_Handler\
-                PROC
-                EXPORT  PAbt_Handler              [WEAK]
-                IMPORT  CPAbtHandler
-                SUB     LR, LR, #4                ; Pre-adjust LR
-                SRSFD   SP!, #Mode_ABT            ; Save LR and SPRS to ABT mode stack
-                PUSH    {R0-R4, R12}              ; Save APCS corruptible registers to ABT mode stack
-                MRC     p15, 0, R0, c5, c0, 1     ; IFSR
-                MRC     p15, 0, R1, c6, c0, 2     ; IFAR
-
-                MOV     R2, LR                    ; Set LR to third argument
-
-;               AND     R12, SP, #4               ; Ensure stack is 8-byte aligned
-                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               ; Adjust stack
-                PUSH    {R12, LR}                 ; Store stack adjustment and dummy LR
-
-                BL      CPAbtHandler
-
-                POP     {R12, LR}                 ; Get stack adjustment & discard dummy LR
-                ADD     SP, SP, R12               ; Unadjust stack
-
-                POP     {R0-R4, R12}              ; Restore stack APCS registers
-                RFEFD   SP!                       ; Return from exception
-                ENDP
-
-
-DAbt_Handler\
-                PROC
-                EXPORT  DAbt_Handler              [WEAK]
-                IMPORT  CDAbtHandler
-                SUB     LR, LR, #8                ; Pre-adjust LR
-                SRSFD   SP!, #Mode_ABT            ; Save LR and SPRS to ABT mode stack
-                PUSH    {R0-R4, R12}              ; Save APCS corruptible registers to ABT mode stack
-                CLREX                             ; State of exclusive monitors unknown after taken data abort
-                MRC     p15, 0, R0, c5, c0, 0     ; DFSR
-                MRC     p15, 0, R1, c6, c0, 0     ; DFAR
-
-                MOV     R2, LR                    ; Set LR to third argument
-
-;               AND     R12, SP, #4               ; Ensure stack is 8-byte aligned
-                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               ; Adjust stack
-                PUSH    {R12, LR}                 ; Store stack adjustment and dummy LR
-
-                BL      CDAbtHandler
-
-                POP     {R12, LR}                 ; Get stack adjustment & discard dummy LR
-                ADD     SP, SP, R12               ; Unadjust stack
-
-                POP     {R0-R4, R12}              ; Restore stacked APCS registers
-                RFEFD   SP!                       ; Return from exception
-                ENDP
-
-FIQ_Handler\
-                PROC
-                EXPORT  FIQ_Handler               [WEAK]
-                ;; An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
-                ;; so if a real FIQ Handler is implemented, this will be needed before returning:
-                ;; LDR     R1, =GICI_BASE
-                ;; LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
-                B       .
-                ENDP
-
-SVC_Handler\
-                PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-
-IRQ_Handler\
-                PROC
-                EXPORT  IRQ_Handler                [WEAK]
-                IMPORT  IRQCount
-                IMPORT  IRQTable
-                IMPORT  IRQNestLevel
-
-                ;prologue
-                SUB     LR, LR, #4                  ; Pre-adjust LR
-                SRSFD   SP!, #Mode_SVC              ; Save LR_IRQ and SPRS_IRQ to SVC mode stack
-                CPS     #Mode_SVC                   ; Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL
-                PUSH    {R0-R3, R12}                ; Save remaining APCS corruptible registers to SVC stack
-
-;               AND     R1, SP, #4                  ; Ensure stack is 8-byte aligned
-                MOV     R3, SP                    ; Ensure stack is 8-byte aligned
-                AND     R1, R3, #4
-                SUB     SP, SP, R1                  ; Adjust stack
-                PUSH    {R1, LR}                    ; Store stack adjustment and LR_SVC to SVC stack
-
-                LDR     R0, =IRQNestLevel           ; Get address of nesting counter
-                LDR     R1, [R0]
-                ADD     R1, R1, #1                  ; Increment nesting counter
-                STR     R1, [R0]
-
-                ;identify and acknowledge interrupt
-                LDR     R1, =GICI_BASE
-                LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
-                LDR     R0, [R1, #ICCIAR_OFFSET]    ; Read ICCIAR (GIC CPU Interface register)
-                DSB                                 ; Ensure that interrupt acknowledge completes before re-enabling interrupts
-
-                ; Workaround GIC 390 errata 733075
-                ; If the ID is not 0, then service the interrupt as normal.
-                ; If the ID is 0 and active, then service interrupt ID 0 as normal.
-                ; If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
-                ;   with a dummy write to ICDIPR0.  This interrupt should be treated as spurious and not serviced.
-                ;
-                LDR     R2, =GICD_BASE
-                LDR     R3, =GIC_ERRATA_CHECK_1
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                LDR     R3, =GIC_ERRATA_CHECK_2
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                CMP     R0, #0
-                BNE     int_active					; If the ID is not 0, then service the interrupt
-                LDR     R3, [R2, #ICDABR0_OFFSET]   ; Get the interrupt state
-                TST     R3, #1
-                BNE     int_active                  ; If active, then service the interrupt
-unlock_cpu
-                LDR     R3, [R2, #ICDIPR0_OFFSET]   ; Not active, so unlock the CPU interface
-                STR     R3, [R2, #ICDIPR0_OFFSET]   ;   with a dummy write
-                DSB                                 ; Ensure the write completes before continuing
-                B       ret_irq                     ; Do not service the spurious interrupt
-                ; End workaround
-
-int_active
-                LDR     R2, =IRQCount               ; Read number of IRQs
-                LDR     R2, [R2]
-                CMP     R0, R2                      ; Clean up and return if no handler
-                BHS     ret_irq                     ; In a single-processor system, spurious interrupt ID 1023 does not need any special handling
-                LDR     R2, =IRQTable               ; Get address of handler
-                LDR     R2, [R2, R0, LSL #2]
-                CMP     R2, #0                      ; Clean up and return if handler address is 0
-                BEQ     ret_irq
-                PUSH    {R0,R1}
-
-                CPSIE   i                           ; Now safe to re-enable interrupts
-                BLX     R2                          ; Call handler. R0 will be IRQ number
-                CPSID   i                           ; Disable interrupts again
-
-                ;write EOIR (GIC CPU Interface register)
-                POP     {R0,R1}
-                DSB                                 ; Ensure that interrupt source is cleared before we write the EOIR
-ret_irq
-                ;epilogue
-                STR     R0, [R1, #ICCEOIR_OFFSET]
-
-                LDR     R0, =IRQNestLevel           ; Get address of nesting counter
-                LDR     R1, [R0]
-                SUB     R1, R1, #1                  ; Decrement nesting counter
-                STR     R1, [R0]
-
-                POP     {R1, LR}                    ; Get stack adjustment and restore LR_SVC
-                ADD     SP, SP, R1                  ; Unadjust stack
-
-                POP     {R0-R3,R12}                 ; Restore stacked APCS registers
-                RFEFD   SP!                         ; Return from exception
-                ENDP
-
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-                
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-__user_initial_stackheap
-
-                LDR     R0, =  Heap_Mem
-                LDR     R1, =(Stack_Mem + USR_Stack_Size)
-                LDR     R2, = (Heap_Mem +  Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-
-                ENDIF
-
-
-                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,162 @@
+/******************************************************************************
+ * @file     startup_RZ_A1H_H.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "VKRZA1H.h"
+#include "mem_VK_RZ_A1H.h"
+
+/*----------------------------------------------------------------------------
+  Definitions
+ *----------------------------------------------------------------------------*/
+#define USR_MODE 0x10            // User mode
+#define FIQ_MODE 0x11            // Fast Interrupt Request mode
+#define IRQ_MODE 0x12            // Interrupt Request mode
+#define SVC_MODE 0x13            // Supervisor mode
+#define ABT_MODE 0x17            // Abort mode
+#define UND_MODE 0x1B            // Undefined Instruction mode
+#define SYS_MODE 0x1F            // System mode
+
+/*----------------------------------------------------------------------------
+  Internal References
+ *----------------------------------------------------------------------------*/
+void Vectors       (void) __attribute__ ((section("RESET")));
+void Reset_Handler(void);
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Handler
+ *----------------------------------------------------------------------------*/
+void Undef_Handler (void) __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void PAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void DAbt_Handler  (void) __attribute__ ((weak, alias("Default_Handler")));
+void IRQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+void FIQ_Handler   (void) __attribute__ ((weak, alias("Default_Handler")));
+
+/*----------------------------------------------------------------------------
+  Exception / Interrupt Vector Table
+ *----------------------------------------------------------------------------*/
+__ASM void Vectors(void) {
+  IMPORT Undef_Handler
+  IMPORT SVC_Handler
+  IMPORT PAbt_Handler
+  IMPORT DAbt_Handler
+  IMPORT IRQ_Handler
+  IMPORT FIQ_Handler
+  LDR    PC, =Reset_Handler
+  LDR    PC, =Undef_Handler
+  LDR    PC, =SVC_Handler
+  LDR    PC, =PAbt_Handler
+  LDR    PC, =DAbt_Handler
+  NOP
+  LDR    PC, =IRQ_Handler
+  LDR    PC, =FIQ_Handler
+}
+
+/*----------------------------------------------------------------------------
+  Reset Handler called on controller reset
+ *----------------------------------------------------------------------------*/
+__ASM void Reset_Handler(void) {
+
+  // Mask interrupts
+  CPSID   if                           
+
+  // Put any cores other than 0 to sleep
+  MRC     p15, 0, R0, c0, c0, 5       // Read MPIDR
+  ANDS    R0, R0, #3
+goToSleep
+  WFINE
+  BNE     goToSleep
+
+  // Reset SCTLR Settings
+  MRC     p15, 0, R0, c1, c0, 0       // Read CP15 System Control register
+  BIC     R0, R0, #(0x1 << 12)        // Clear I bit 12 to disable I Cache
+  BIC     R0, R0, #(0x1 <<  2)        // Clear C bit  2 to disable D Cache
+  BIC     R0, R0, #0x1                // Clear M bit  0 to disable MMU
+  BIC     R0, R0, #(0x1 << 11)        // Clear Z bit 11 to disable branch prediction
+  BIC     R0, R0, #(0x1 << 13)        // Clear V bit 13 to disable hivecs
+  MCR     p15, 0, R0, c1, c0, 0       // Write value back to CP15 System Control register
+  ISB
+
+  // Configure ACTLR
+  MRC     p15, 0, r0, c1, c0, 1       // Read CP15 Auxiliary Control Register
+  ORR     r0, r0, #(1 <<  1)          // Enable L2 prefetch hint (UNK/WI since r4p1)
+  MCR     p15, 0, r0, c1, c0, 1       // Write CP15 Auxiliary Control Register
+
+  // Set Vector Base Address Register (VBAR) to point to this application's vector table
+  LDR    R0, =Vectors
+  MCR    p15, 0, R0, c12, c0, 0
+
+  // Setup Stack for each exceptional mode
+  IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+  LDR    R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+  //Enter Undefined Instruction Mode and set its Stack Pointer 
+  CPS    #UND_MODE
+  MOV    SP, R0
+  SUB    R0, R0, #__UND_STACK_SIZE
+
+  // Enter Abort Mode and set its Stack Pointer 
+  CPS    #ABT_MODE
+  MOV    SP, R0
+  SUB    R0, R0, #__ABT_STACK_SIZE
+
+  // Enter FIQ Mode and set its Stack Pointer 
+  CPS    #FIQ_MODE
+  MOV    SP, R0
+  SUB    R0, R0, #__FIQ_STACK_SIZE
+
+  // Enter IRQ Mode and set its Stack Pointer 
+  CPS    #IRQ_MODE
+  MOV    SP, R0
+  SUB    R0, R0, #__IRQ_STACK_SIZE
+
+  // Enter Supervisor Mode and set its Stack Pointer 
+  CPS    #SVC_MODE
+  MOV    SP, R0
+  SUB    R0, R0, #__SVC_STACK_SIZE
+
+  // Enter System Mode to complete initialization and enter kernel 
+  CPS    #SYS_MODE
+  MOV    SP, R0
+
+  // Call SystemInit
+  IMPORT SystemInit
+  BL     SystemInit
+
+  // Unmask interrupts
+  CPSIE  if
+
+  // Call __main
+  IMPORT __main
+  BL     __main
+}
+
+/*----------------------------------------------------------------------------
+  Default Handler for Exceptions / Interrupts
+ *----------------------------------------------------------------------------*/
+void Default_Handler(void) {
+	while(1);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library - stackheap
+ * Setup a fixed single stack/heap memory model, 
+ * between the top of the RW/ZI region and the stackpointer
+ *******************************************************************************
+ * Copyright (c) 2017 ARM Limited.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+#include <arm_compat.h>
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$ARM_LIB_HEAP$$Base[];
+extern char Image$$ARM_LIB_STACK$$Base[];
+
+extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
+    uint32_t sp_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base;
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld	Thu Apr 19 17:12:19 2018 +0100
@@ -1,15 +1,40 @@
 /* Linker script for mbed VK_RZ_A1H */
 
 /* Linker script to configure memory regions. */
+/*
+#ifdef RUN_FROM_SDRAM
+MEMORY
+{
+  L_TTB (rw)  : ORIGIN = 0x20000000, LENGTH = 0x00004000
+  RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x01E00000
+  RAM_NC (rwx) : ORIGIN = 0x49E00000, LENGTH = 0x00200000
+  SRAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00960000
+}
+REGION_ALIAS("SFLASH", RAM);
+TTBOFFSET = 1M;
+
+#elif defined (RUN_FROM_SRAM)
+MEMORY
+{
+  L_TTB (rw)  : ORIGIN = 0x20000000, LENGTH = 0x00004000 
+  RAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00860000
+  RAM_NC (rwx) : ORIGIN = 0x60900000, LENGTH = 0x00100000
+  SDRAM  (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000
+}
+REGION_ALIAS("SFLASH", RAM);
+TTBOFFSET = 1M;
+#else
+*/
 MEMORY
 {
   ROM   (rx)  : ORIGIN = 0x00000000, LENGTH = 0x02000000
-  SFLASH_DUAL (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000 
+  SFLASH (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000 
   L_TTB (rw)  : ORIGIN = 0x20000000, LENGTH = 0x00004000 
-  RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x00700000
+  RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x008E0000
   RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000
   SDRAM  (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000
 }
+/*#endif*/
 
 /* Linker script to place sections and symbol values. Should be used together
  * with other linker script that defines memory regions FLASH and RAM.
@@ -45,8 +70,7 @@
     {
 
         Image$$VECTORS$$Base = .;
-        *(.isr_vector)
-        Image$$VECTORS$$Limit = .;
+        KEEP(*(.isr_vector))
         *(SVC_TABLE)
         *(.text*)
 
@@ -66,24 +90,25 @@
         *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
         *(SORT(.dtors.*))
         *(.dtors)
+        Image$$VECTORS$$Limit = .;
 
         Image$$RO_DATA$$Base = .;
         *(.rodata*)
         Image$$RO_DATA$$Limit = .;
 
         KEEP(*(.eh_frame*))
-    } > SFLASH_DUAL
+    } > SFLASH
 
     .ARM.extab : 
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > SFLASH_DUAL
+    } > SFLASH
 
     __exidx_start = .;
     .ARM.exidx :
     {
         *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > SFLASH_DUAL
+    } > SFLASH
     __exidx_end = .;
 
 
@@ -98,7 +123,7 @@
         LONG (__nc_data_start)
         LONG (__nc_data_end - __nc_data_start)
         __copy_table_end__ = .;
-    } > SFLASH_DUAL
+    } > SFLASH
 
     .zero.table :
     {
@@ -109,7 +134,7 @@
         LONG (__nc_bss_start)
         LONG (__nc_bss_end - __nc_bss_start)
         __zero_table_end__ = .;
-    } > SFLASH_DUAL
+    } > SFLASH
 
     __etext = .;
         
@@ -155,34 +180,42 @@
 
     } > RAM
 
-    
-    .bss ALIGN(0x400):
+    .bss ALIGN(0x10):
     {
-        Image$$ZI_DATA$$Base = .;
+        Image$$RW_IRAM1$$Base = .;
         __bss_start__ = .;
         *(.bss*)
         *(COMMON)
         __bss_end__ = .;
-        Image$$ZI_DATA$$Limit = .;
+        Image$$RW_IRAM1$$Limit = .;
     } > RAM
 
-    
     .heap :
     {
         __end__ = .;
         end = __end__;
         *(.heap*)
-        __HeapLimit = .;
     } > RAM
 
     /* .stack_dummy section doesn't contains any symbols. It is only
      * used for linker to calculate size of stack sections, and assign
      * values to stack symbols later */
-    .stack_dummy :
+    .stack_dummy (COPY):
     {
-        *(.stack)
+        *(.stack*)
     } > RAM
 
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    __HeapLimit = __StackLimit;
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+
     __etext2 = __etext + SIZEOF(.data);
     .nc_data : AT (__etext2)
     {
@@ -205,15 +238,4 @@
         __nc_bss_end = .;
         Image$$ZI_DATA_NC$$Limit = .;
     } > RAM_NC
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-
-
 }

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S	Thu Apr 19 17:12:19 2018 +0100
@@ -19,26 +19,6 @@
     .extern _start
  
 @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
-    .equ    USR_MODE        ,   0x10
-    .equ    FIQ_MODE        ,   0x11
-    .equ    IRQ_MODE        ,   0x12
-    .equ    SVC_MODE        ,   0x13
-    .equ    ABT_MODE        ,   0x17
-    .equ    UND_MODE        ,   0x1b
-    .equ    SYS_MODE        ,   0x1f
-    .equ    Thum_bit        ,   0x20            @ CPSR/SPSR Thumb bit
-
-    .equ    GICI_BASE       ,   0xe8202000
-    .equ    ICCIAR_OFFSET   ,   0x0000000C
-    .equ    ICCEOIR_OFFSET  ,   0x00000010
-    .equ    ICCHPIR_OFFSET  ,   0x00000018
-    .equ    GICD_BASE       ,   0xe8201000
-    .equ    ICDISER0_OFFSET ,   0x00000100
-    .equ    ICDICER0_OFFSET ,   0x00000180
-    .equ    ICDISPR0_OFFSET ,   0x00000200
-    .equ    ICDABR0_OFFSET  ,   0x00000300
-    .equ    ICDIPR0_OFFSET  ,   0x00000400
-
     .equ    Mode_USR        ,   0x10
     .equ    Mode_FIQ        ,   0x11
     .equ    Mode_IRQ        ,   0x12
@@ -51,33 +31,13 @@
     .equ    F_Bit           ,   0x40            @ when F bit is set, FIQ is disabled 
     .equ    T_Bit           ,   0x20            @ when T bit is set, core is in Thumb state 
 
-    .equ    GIC_ERRATA_CHECK_1, 0x000003FE 
-    .equ    GIC_ERRATA_CHECK_2, 0x000003FF 
-
-    .equ    Sect_Normal     , 0x00005c06        @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0 
-    .equ    Sect_Normal_Cod , 0x0000dc06        @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0 
-    .equ    Sect_Normal_RO  , 0x0000dc16        @ as Sect_Normal_Cod, but not executable 
-    .equ    Sect_Normal_RW  , 0x00005c16        @ as Sect_Normal_Cod, but writeable and not executable 
-    .equ    Sect_SO         , 0x00000c12        @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0 
-    .equ    Sect_Device_RO  , 0x00008c12        @ device, non-shareable, non-executable, ro, domain 0, base addr 0 
-    .equ    Sect_Device_RW  , 0x00000c12        @ as Sect_Device_RO, but writeable 
-    .equ    Sect_Fault      , 0x00000000        @ this translation will fault (the bottom 2 bits are important, the rest are ignored) 
-
-    .equ    RAM_BASE        , 0x80000000
-    .equ    VRAM_BASE       , 0x18000000
-    .equ    SRAM_BASE       , 0x2e000000
-    .equ    ETHERNET        , 0x1a000000
-    .equ    CS3_PERIPHERAL_BASE, 0x1c000000
-
-
 @ Stack Configuration
 
     .EQU    UND_Stack_Size  , 0x00000100
     .EQU    SVC_Stack_Size  , 0x00008000
     .EQU    ABT_Stack_Size  , 0x00000100
     .EQU    FIQ_Stack_Size  , 0x00000100
-    .EQU    IRQ_Stack_Size  , 0x00008000
-    .EQU    USR_Stack_Size  , 0x00004000
+    .EQU    IRQ_Stack_Size  , 0x0000F000
 
     .EQU    ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
 
@@ -88,7 +48,6 @@
 __StackLimit:
     .space    ISR_Stack_Size
 __initial_sp:
-    .space    USR_Stack_Size
     .size __StackLimit, . - __StackLimit
 __StackTop:
     .size __StackTop, . - __StackTop
@@ -139,25 +98,17 @@
     .globl          Reset_Handler
     .type          Reset_Handler, %function
 Reset_Handler:
+    @ Mask interrupts
+    CPSID   if                           
+
     @ Put any cores other than 0 to sleep
     mrc     p15, 0, r0, c0, c0, 5   @ Read MPIDR
     ands    r0, r0, #3
-
 goToSleep:
     wfine
     bne     goToSleep
 
-@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. 
-@ Enables Full Access i.e. in both privileged and non privileged modes 
-    mrc     p15, 0, r0, c1, c0, 2       @ Read Coprocessor Access Control Register (CPACR) 
-    orr     r0, r0, #(0xF << 20)        @ Enable access to CP 10 & 11 
-    mcr     p15, 0, r0, c1, c0, 2       @ Write Coprocessor Access Control Register (CPACR) 
-    isb
-
-@ Switch on the VFP and NEON hardware 
-    mov     r0, #0x40000000
-    vmsr    fpexc, r0                   @ Write FPEXC register, EN bit set 
-
+    @ Reset SCTLR Settings
     mrc     p15, 0, r0, c1, c0, 0       @ Read CP15 System Control register 
     bic     r0, r0, #(0x1 << 12)        @ Clear I bit 12 to disable I Cache 
     bic     r0, r0, #(0x1 <<  2)        @ Clear C bit  2 to disable D Cache 
@@ -167,13 +118,17 @@
     mcr     p15, 0, r0, c1, c0, 0       @ Write value back to CP15 System Control register 
     isb
 
+    @ Configure ACTLR
+    MRC     p15, 0, r0, c1, c0, 1       @ Read CP15 Auxiliary Control Register
+    ORR     r0, r0, #(1 <<  1)          @ Enable L2 prefetch hint (UNK/WI since r4p1)
+    MCR     p15, 0, r0, c1, c0, 1       @ Write CP15 Auxiliary Control Register
+
 @ Set Vector Base Address Register (VBAR) to point to this application's vector table
     ldr     r0, =__isr_vector
     mcr     p15, 0, r0, c12, c0, 0
  
 @ Setup Stack for each exceptional mode 
-/*    ldr     r0, =__StackTop  */
-    ldr     r0, =(__StackTop - USR_Stack_Size)
+    ldr     r0, =__StackTop
 
 @ Enter Undefined Instruction Mode and set its Stack Pointer 
     msr     cpsr_c, #(Mode_UND | I_Bit | F_Bit)
@@ -203,23 +158,12 @@
     msr     cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
     mov     sp, r0 
 
-    isb
-    ldr     r0, =RZ_A1_SetSramWriteEnable
-    blx     r0
-
-    .extern  create_translation_table
-    bl      create_translation_table 
-
 @  USR/SYS stack pointer will be set during kernel init
     ldr     r0, =SystemInit
     blx     r0
-    ldr     r0, =InitMemorySubsystem
-    blx     r0
 
-@ fp_init
-    mov      r0, #0x3000000
-    vmsr     fpscr, r0
-
+    @ Unmask interrupts
+    CPSIE  if
 
 @ data sections copy
     ldr     r4, =__copy_table_start__
@@ -269,227 +213,12 @@
     ldr     r0, =_start
     bx      r0
 
-    ldr     r0, sf_boot     @ dummy to keep boot loader area
-loop_here:
-    b       loop_here
-
-sf_boot: 
-    .word   0x18020000
-
     .pool
     .size Reset_Handler, . - Reset_Handler
 
 
     .text
 
-Undef_Handler:
-                .global Undef_Handler
-                .func   Undef_Handler
-                .extern CUndefHandler
-                SRSDB   SP!, #Mode_UND
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to UND mode stack */
-
-                MRS     R0, SPSR
-                TST     R0, #T_Bit                /* Check mode */
-                MOVEQ   R1, #4                    /* R1 = 4 ARM mode */
-                MOVNE   R1, #2                    /* R1 = 2 Thumb mode */
-                SUB     R0, LR, R1
-                LDREQ   R0, [R0]                  /* ARM mode - R0 points to offending instruction */
-                BEQ     undef_cont
-
-                /* Thumb instruction */
-                /* Determine if it is a 32-bit Thumb instruction */
-                LDRH    R0, [R0]
-                MOV     R2, #0x1c
-                CMP     R2, R0, LSR #11
-                BHS     undef_cont                /* 16-bit Thumb instruction */
-
-                /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
-                LDRH    R2, [LR]
-                ORR     R0, R2, R0, LSL #16
-undef_cont:
-                MOV     R2, LR                    /* Set LR to third argument */
-                
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                /* R0 Offending instruction */
-                /* R1 =2 (Thumb) or =4 (ARM) */
-                BL      CUndefHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                LDR     LR, [SP, #24]             /* Restore stacked LR and possibly adjust for retry */
-                SUB     LR, LR, R0
-                LDR     R0, [SP, #28]             /* Restore stacked SPSR */
-                MSR     SPSR_cxsf, R0
-                POP     {R0-R4, R12}              /* Restore stacked APCS registers */
-                ADD     SP, SP, #8                /* Adjust SP for already-restored banked registers */
-                MOVS    PC, LR
-                .endfunc
- 
-PAbt_Handler:
-                .global PAbt_Handler
-                .func   PAbt_Handler
-                .extern CPAbtHandler
-                SUB     LR, LR, #4                /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
-                MRC     p15, 0, R0, c5, c0, 1     /* IFSR */
-                MRC     p15, 0, R1, c6, c0, 2     /* IFAR */
-
-                MOV     R2, LR                    /* Set LR to third argument */
-
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                BL      CPAbtHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                POP     {R0-R4, R12}              /* Restore stack APCS registers */
-                RFEFD   SP!                       /* Return from exception */
-                .endfunc
-
-DAbt_Handler:
-                .global DAbt_Handler
-                .func   DAbt_Handler
-                .extern CDAbtHandler
-                SUB     LR, LR, #8                /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
-                CLREX                             /* State of exclusive monitors unknown after taken data abort */
-                MRC     p15, 0, R0, c5, c0, 0     /* DFSR */
-                MRC     p15, 0, R1, c6, c0, 0     /* DFAR */
-
-                MOV     R2, LR                    /* Set LR to third argument */
-
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                BL      CDAbtHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                POP     {R0-R4, R12}              /* Restore stacked APCS registers */
-                RFEFD   SP!                       /* Return from exception */
-                .endfunc
- 
-FIQ_Handler:
-                .global FIQ_Handler
-                .func   FIQ_Handler
-                /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
-                 * so if a real FIQ Handler is implemented, this will be needed before returning:
-                 */
-                /* LDR     R1, =GICI_BASE
-                   LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
-                 */
-                B       .
-                .endfunc
- 
-                .extern SVC_Handler                 /* refer RTX function */
-
-IRQ_Handler: 
-                .global IRQ_Handler
-                .func   IRQ_Handler
-                .extern IRQCount
-                .extern IRQTable
-                .extern IRQNestLevel
-
-                /* prologue */
-                SUB     LR, LR, #4                  /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_SVC              /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
-                CPS     #Mode_SVC                   /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
-                PUSH    {R0-R3, R12}                /* Save remaining APCS corruptible registers to SVC stack */
-
-/*              AND     R1, SP, #4 */               /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                      /* Ensure stack is 8-byte aligned */
-                AND     R1, R3, #4
-                SUB     SP, SP, R1                  /* Adjust stack */
-                PUSH    {R1, LR}                    /* Store stack adjustment and LR_SVC to SVC stack */
-
-                LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
-                LDR     R1, [R0]
-                ADD     R1, R1, #1                  /* Increment nesting counter */
-                STR     R1, [R0]
-
-                /* identify and acknowledge interrupt */
-                LDR     R1, =GICI_BASE
-                LDR     R0, [R1, #ICCHPIR_OFFSET]   /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
-                LDR     R0, [R1, #ICCIAR_OFFSET]    /* Read ICCIAR (GIC CPU Interface register) */
-                DSB                                 /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
-
-                /* Workaround GIC 390 errata 733075
-                 * If the ID is not 0, then service the interrupt as normal.
-                 * If the ID is 0 and active, then service interrupt ID 0 as normal.
-                 * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
-                 *   with a dummy write to ICDIPR0.  This interrupt should be treated as spurious and not serviced.
-                 */
-                LDR     R2, =GICD_BASE
-                LDR     R3, =GIC_ERRATA_CHECK_1
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                LDR     R3, =GIC_ERRATA_CHECK_2
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                CMP     R0, #0
-                BNE     int_active                  /* If the ID is not 0, then service the interrupt */
-                LDR     R3, [R2, #ICDABR0_OFFSET]   /* Get the interrupt state */
-                TST     R3, #1
-                BNE     int_active                  /* If active, then service the interrupt */
-unlock_cpu:
-                LDR     R3, [R2, #ICDIPR0_OFFSET]   /* Not active, so unlock the CPU interface */
-                STR     R3, [R2, #ICDIPR0_OFFSET]   /*   with a dummy write */
-                DSB                                 /* Ensure the write completes before continuing */
-                B       ret_irq                     /* Do not service the spurious interrupt */
-                /* End workaround */
-
-int_active:
-                LDR     R2, =IRQCount               /* Read number of IRQs */
-                LDR     R2, [R2]
-                CMP     R0, R2                      /* Clean up and return if no handler */
-                BHS     ret_irq                     /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
-                LDR     R2, =IRQTable               /* Get address of handler */
-                LDR     R2, [R2, R0, LSL #2]
-                CMP     R2, #0                      /* Clean up and return if handler address is 0 */
-                BEQ     ret_irq
-                PUSH    {R0,R1}
-
-                CPSIE   i                           /* Now safe to re-enable interrupts */
-                BLX     R2                          /* Call handler. R0 will be IRQ number */
-                CPSID   i                           /* Disable interrupts again */
-
-                /* write EOIR (GIC CPU Interface register) */
-                POP     {R0,R1}
-                DSB                                 /* Ensure that interrupt source is cleared before we write the EOIR */
-ret_irq:
-                /* epilogue */
-                STR     R0, [R1, #ICCEOIR_OFFSET]
-
-                LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
-                LDR     R1, [R0]
-                SUB     R1, R1, #1                  /* Decrement nesting counter */
-                STR     R1, [R0]
-
-                POP     {R1, LR}                    /* Get stack adjustment and restore LR_SVC */
-                ADD     SP, SP, R1                  /* Unadjust stack */
-
-                POP     {R0-R3,R12}                 /* Restore stacked APCS registers */
-                RFEFD   SP!                         /* Return from exception */
-                .endfunc
-
 /*    Macro to define default handlers. Default handler
  *    will be weak symbol and just dead loops. They can be
  *    overwritten by other handlers */
@@ -503,30 +232,11 @@
                 .size    \handler_name, . - \handler_name
                 .endm
 
+                def_default_handler    Undef_Handler
                 def_default_handler    SVC_Handler
-
-
-/* User Initial Stack & Heap */
-
-                .ifdef __MICROLIB
-                
-                .global __initial_sp
-                .global __heap_base
-                .global __heap_limit
-
-                .else
-
-                .extern __use_two_region_memory
-                .global __user_initial_stackheap
-__user_initial_stackheap:
-
-                LDR     R0, =  __HeapBase
-                LDR     R1, =(__StackTop)
-                LDR     R2, = (__HeapBase +  Heap_Size)
-                LDR     R3, = (__StackTop - USR_Stack_Size)
-                BX      LR
-
-                .endif
-
+                def_default_handler    PAbt_Handler
+                def_default_handler    DAbt_Handler
+                def_default_handler    IRQ_Handler
+                def_default_handler    FIQ_Handler
 
                 .END

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf	Thu Apr 19 17:12:19 2018 +0100
@@ -41,6 +41,7 @@
 define region MirrorRAM_region    = mem:[from __ICFEDIT_region_MirrorRAM_start__    to __ICFEDIT_region_MirrorRAM_end__];
 define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
 
+define block ROM_FIXED_ORDER with fixed order { ro code, ro data };
 define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
 define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
 define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
@@ -51,11 +52,11 @@
 
 initialize by copy { readwrite };
 do not initialize  { section .noinit };
-do not initialize  { section MMU_TT };
+do not initialize  { section .retram };
 
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
-place in ROM_region     { readonly };
+place in ROM_region     { readonly, block ROM_FIXED_ORDER };
 place in RAM_region     { readwrite,
                           block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
                           block UND_STACK, block ABT_STACK, block HEAP };

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S	Thu Apr 19 17:12:19 2018 +0100
@@ -29,30 +29,21 @@
 
         SECTION .intvec:CODE:NOROOT(2)
 
-        PUBLIC  __vector_core_a9
-        PUBWEAK __iar_program_start
-        PUBLIC  Undefined_Handler
-        EXTERN  SWI_Handler
-        PUBLIC  Prefetch_Handler
-        PUBLIC  Abort_Handler
-        PUBLIC  IRQ_Handler
+        PUBLIC  __vector_table
+        PUBLIC  __RST_Handler
+        EXTERN  Undef_Handler
+        EXTERN  SVC_Handler
+        EXTERN  PAbt_Handler
+        EXTERN  DAbt_Handler
+        EXTERN  IRQ_Handler
         PUBLIC  FIQ_Handler
-        EXTERN  VbarInit
-        EXTERN  SetLowVectors
-        EXTERN  init_TTB
-        EXTERN  enable_mmu
-        EXTERN  Peripheral_BasicInit
-        EXTERN  initsct
-        EXTERN  PowerON_Reset
-        PUBLIC  FPUEnable
-        
 
         DATA
 
 __iar_init$$done:               ; The vector table is not needed
                                 ; until after copy initialization is done
 
-__vector_core_a9:               ; Make this a DATA label, so that stack usage
+__vector_table:                 ; Make this a DATA label, so that stack usage
                                 ; analysis doesn't consider it an uncalled fun
 
         ARM
@@ -71,11 +62,11 @@
 
         DATA
 
-Reset_Addr:     DCD   __iar_program_start
-Undefined_Addr: DCD   Undefined_Handler
-SWI_Addr:       DCD   SWI_Handler
-Prefetch_Addr:  DCD   Prefetch_Handler
-Abort_Addr:     DCD   Abort_Handler
+Reset_Addr:     DCD   __RST_Handler
+Undefined_Addr: DCD   Undef_Handler
+SWI_Addr:       DCD   SVC_Handler
+Prefetch_Addr:  DCD   PAbt_Handler
+Abort_Addr:     DCD   DAbt_Handler
 IRQ_Addr:       DCD   IRQ_Handler
 FIQ_Addr:       DCD   FIQ_Handler
 
@@ -90,21 +81,20 @@
 
 
         SECTION .text:CODE:NOROOT(2)
-        EXTERN  RZ_A1_SetSramWriteEnable
-        EXTERN  create_translation_table
         EXTERN  SystemInit
-        EXTERN  InitMemorySubsystem
-        EXTERN  __cmain
-        REQUIRE __vector_core_a9
+        EXTERN  __iar_program_start
+        REQUIRE __vector_table
         EXTWEAK __iar_init_core
         EXTWEAK __iar_init_vfp
 
 
         ARM
 
-__iar_program_start:
+__RST_Handler:
 ?cstartup:
 
+;;;    @ Mask interrupts
+    CPSID   if   
 
 ;;;    @ Put any cores other than 0 to sleep
     mrc     p15, 0, r0, c0, c0, 5   ;;; @ Read MPIDR
@@ -114,19 +104,7 @@
     wfine
     bne     goToSleep
 
-
-//@ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11. 
-//@ Enables Full Access i.e. in both privileged and non privileged modes 
-    mrc     p15, 0, r0, c1, c0, 2       ;@ Read Coprocessor Access Control Register (CPACR) 
-    orr     r0, r0, #(0xF << 20)        ;@ Enable access to CP 10 & 11 
-    mcr     p15, 0, r0, c1, c0, 2       ;@ Write Coprocessor Access Control Register (CPACR) 
-    isb
-   
-   
-;; Switch on the VFP and NEON hardware 
-    mov     r0, #0x40000000
-    vmsr    fpexc, r0                   ;@ Write FPEXC register, EN bit set 
-
+;;;    @ Reset SCTLR Settings
     mrc     p15, 0, r0, c1, c0, 0       ;@ Read CP15 System Control register 
     bic     r0, r0, #(0x1 << 12)        ;@ Clear I bit 12 to disable I Cache 
     bic     r0, r0, #(0x1 <<  2)        ;@ Clear C bit  2 to disable D Cache 
@@ -136,9 +114,13 @@
     mcr     p15, 0, r0, c1, c0, 0       ;@ Write value back to CP15 System Control register 
     isb
   
+;;;    @ Configure ACTLR
+    MRC     p15, 0, r0, c1, c0, 1       ;@ Read CP15 Auxiliary Control Register
+    ORR     r0, r0, #(1 <<  1)          ;@ Enable L2 prefetch hint (UNK/WI since r4p1)
+    MCR     p15, 0, r0, c1, c0, 1       ;@ Write CP15 Auxiliary Control Register
   
 ;; Set Vector Base Address Register (VBAR) to point to this application's vector table
-    ldr     r0, =__vector_core_a9
+    ldr     r0, =__vector_table
     mcr     p15, 0, r0, c12, c0, 0
     
     
@@ -169,20 +151,6 @@
 #define UND_MODE 0x1B            ; Undefined Instruction mode
 #define SYS_MODE 0x1F            ; System mode
 
-#define Mode_SVC  0x13
-#define Mode_ABT  0x17
-#define Mode_UND  0x1B
-#define GICI_BASE 0xe8202000
-#define ICCIAR_OFFSET   0x0000000C
-#define ICCEOIR_OFFSET  0x00000010
-#define ICCHPIR_OFFSET  0x00000018
-#define GICD_BASE       0xe8201000
-#define GIC_ERRATA_CHECK_1 0x000003FE 
-#define GIC_ERRATA_CHECK_2 0x000003FF 
-#define ICDABR0_OFFSET  0x00000300
-#define ICDIPR0_OFFSET  0x00000400
-#define T_Bit           0x20     ; when T bit is set, core is in Thumb state 
-
         MRS     r0, cpsr                ; Original PSR value
 
         ;; Set up the SVC stack pointer.        
@@ -235,271 +203,16 @@
         BIC     sp,sp,#0x7              ; Make sure SP is 8 aligned
 
 ;;;
-
-    isb
-    ldr     r0, =RZ_A1_SetSramWriteEnable
-    blx     r0
-
-    bl      create_translation_table 
-
 ;  USR/SYS stack pointer will be set during kernel init
     ldr     r0, =SystemInit
     blx     r0
-    ldr     r0, =InitMemorySubsystem
-    blx     r0
-
-; fp_init
-    mov      r0, #0x3000000
-    vmsr     fpscr, r0
-    
-    
 
 ;;; Continue to __cmain for C-level initialization.
 
-          FUNCALL __iar_program_start, __cmain
-        B       __cmain
-
-
-    ldr     r0, sf_boot     ;@ dummy to keep boot loader area
-loop_here:
-    b       loop_here
-
-sf_boot: 
-    DC32   0x00000001
-
-Undefined_Handler:
-                EXTERN CUndefHandler
-                SRSDB   SP!, #Mode_UND
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to UND mode stack */
-
-                MRS     R0, SPSR
-                TST     R0, #T_Bit                /* Check mode */
-                MOVEQ   R1, #4                    /* R1 = 4 ARM mode */
-                MOVNE   R1, #2                    /* R1 = 2 Thumb mode */
-                SUB     R0, LR, R1
-                LDREQ   R0, [R0]                  /* ARM mode - R0 points to offending instruction */
-                BEQ     undef_cont
-
-                /* Thumb instruction */
-                /* Determine if it is a 32-bit Thumb instruction */
-                LDRH    R0, [R0]
-                MOV     R2, #0x1c
-                CMP     R2, R0, LSR #11
-                BHS     undef_cont                /* 16-bit Thumb instruction */
-
-                /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
-                LDRH    R2, [LR]
-                ORR     R0, R2, R0, LSL #16
-undef_cont:
-                MOV     R2, LR                    /* Set LR to third argument */
-                
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                /* R0 Offending instruction */
-                /* R1 =2 (Thumb) or =4 (ARM) */
-                BL      CUndefHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                LDR     LR, [SP, #24]             /* Restore stacked LR and possibly adjust for retry */
-                SUB     LR, LR, R0
-                LDR     R0, [SP, #28]             /* Restore stacked SPSR */
-                MSR     SPSR_cxsf, R0
-                POP     {R0-R4, R12}              /* Restore stacked APCS registers */
-                ADD     SP, SP, #8                /* Adjust SP for already-restored banked registers */
-                MOVS    PC, LR
- 
-Prefetch_Handler:
-                EXTERN CPAbtHandler
-                SUB     LR, LR, #4                /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
-                MRC     p15, 0, R0, c5, c0, 1     /* IFSR */
-                MRC     p15, 0, R1, c6, c0, 2     /* IFAR */
-
-                MOV     R2, LR                    /* Set LR to third argument */
-
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                BL      CPAbtHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                POP     {R0-R4, R12}              /* Restore stack APCS registers */
-                RFEFD   SP!                       /* Return from exception */
-
-Abort_Handler:
-                EXTERN CDAbtHandler
-                SUB     LR, LR, #8                /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_ABT            /* Save LR and SPRS to ABT mode stack */
-                PUSH    {R0-R4, R12}              /* Save APCS corruptible registers to ABT mode stack */
-                CLREX                             /* State of exclusive monitors unknown after taken data abort */
-                MRC     p15, 0, R0, c5, c0, 0     /* DFSR */
-                MRC     p15, 0, R1, c6, c0, 0     /* DFAR */
-
-                MOV     R2, LR                    /* Set LR to third argument */
-
-/*              AND     R12, SP, #4 */            /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                    /* Ensure stack is 8-byte aligned */
-                AND     R12, R3, #4
-                SUB     SP, SP, R12               /* Adjust stack */
-                PUSH    {R12, LR}                 /* Store stack adjustment and dummy LR */
-
-                BL      CDAbtHandler
-
-                POP     {R12, LR}                 /* Get stack adjustment & discard dummy LR */
-                ADD     SP, SP, R12               /* Unadjust stack */
-
-                POP     {R0-R4, R12}              /* Restore stacked APCS registers */
-                RFEFD   SP!                       /* Return from exception */
+          FUNCALL __RST_Handler, __iar_program_start
+        B       __iar_program_start
 
 FIQ_Handler:
-    /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
-     * so if a real FIQ Handler is implemented, this will be needed before returning:
-     */
-    /* LDR     R1, =GICI_BASE
-    LDR     R0, [R1, #ICCHPIR_OFFSET]   ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
-     */
     B       .
  
-    EXTERN SVC_Handler                 /* refer RTX function */
-
-IRQ_Handler: 
-                EXTERN IRQCount
-                EXTERN IRQTable
-                EXTERN IRQNestLevel
-
-                /* prologue */
-                SUB     LR, LR, #4                  /* Pre-adjust LR */
-                SRSDB   SP!, #Mode_SVC              /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
-                CPS     #Mode_SVC                   /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
-                PUSH    {R0-R3, R12}                /* Save remaining APCS corruptible registers to SVC stack */
-
-/*              AND     R1, SP, #4 */               /* Ensure stack is 8-byte aligned */
-                MOV     R3, SP                      /* Ensure stack is 8-byte aligned */
-                AND     R1, R3, #4
-                SUB     SP, SP, R1                  /* Adjust stack */
-                PUSH    {R1, LR}                    /* Store stack adjustment and LR_SVC to SVC stack */
-
-                LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
-                LDR     R1, [R0]
-                ADD     R1, R1, #1                  /* Increment nesting counter */
-                STR     R1, [R0]
-
-                /* identify and acknowledge interrupt */
-                LDR     R1, =GICI_BASE
-                LDR     R0, [R1, #ICCHPIR_OFFSET]   /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
-                LDR     R0, [R1, #ICCIAR_OFFSET]    /* Read ICCIAR (GIC CPU Interface register) */
-                DSB                                 /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
-
-                /* Workaround GIC 390 errata 733075
-                 * If the ID is not 0, then service the interrupt as normal.
-                 * If the ID is 0 and active, then service interrupt ID 0 as normal.
-                 * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
-                 *   with a dummy write to ICDIPR0.  This interrupt should be treated as spurious and not serviced.
-                 */
-                LDR     R2, =GICD_BASE
-                LDR     R3, =GIC_ERRATA_CHECK_1
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                LDR     R3, =GIC_ERRATA_CHECK_2
-                CMP     R0, R3
-                BEQ     unlock_cpu
-                CMP     R0, #0
-                BNE     int_active                  /* If the ID is not 0, then service the interrupt */
-                LDR     R3, [R2, #ICDABR0_OFFSET]   /* Get the interrupt state */
-                TST     R3, #1
-                BNE     int_active                  /* If active, then service the interrupt */
-unlock_cpu:
-                LDR     R3, [R2, #ICDIPR0_OFFSET]   /* Not active, so unlock the CPU interface */
-                STR     R3, [R2, #ICDIPR0_OFFSET]   /*   with a dummy write */
-                DSB                                 /* Ensure the write completes before continuing */
-                B       ret_irq                     /* Do not service the spurious interrupt */
-                /* End workaround */
-
-int_active:
-                LDR     R2, =IRQCount               /* Read number of IRQs */
-                LDR     R2, [R2]
-                CMP     R0, R2                      /* Clean up and return if no handler */
-                BHS     ret_irq                     /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
-                LDR     R2, =IRQTable               /* Get address of handler */
-                LDR     R2, [R2, R0, LSL #2]
-                CMP     R2, #0                      /* Clean up and return if handler address is 0 */
-                BEQ     ret_irq
-                PUSH    {R0,R1}
-
-                CPSIE   i                           /* Now safe to re-enable interrupts */
-                BLX     R2                          /* Call handler. R0 will be IRQ number */
-                CPSID   i                           /* Disable interrupts again */
-
-                /* write EOIR (GIC CPU Interface register) */
-                POP     {R0,R1}
-                DSB                                 /* Ensure that interrupt source is cleared before we write the EOIR */
-ret_irq:
-                /* epilogue */
-                STR     R0, [R1, #ICCEOIR_OFFSET]
-
-                LDR     R0, =IRQNestLevel           /* Get address of nesting counter */
-                LDR     R1, [R0]
-                SUB     R1, R1, #1                  /* Decrement nesting counter */
-                STR     R1, [R0]
-
-                POP     {R1, LR}                    /* Get stack adjustment and restore LR_SVC */
-                ADD     SP, SP, R1                  /* Unadjust stack */
-
-                POP     {R0-R3,R12}                 /* Restore stacked APCS registers */
-                RFEFD   SP!                         /* Return from exception */
-;;;
-;;; Add more initialization here
-;;;
-FPUEnable:
-        ARM
-
-        //Permit access to VFP registers by modifying CPACR
-        MRC     p15,0,R1,c1,c0,2
-        ORR     R1,R1,#0x00F00000
-        MCR     p15,0,R1,c1,c0,2
-
-        //Enable VFP
-        VMRS    R1,FPEXC
-        ORR     R1,R1,#0x40000000
-        VMSR    FPEXC,R1
-
-        //Initialise VFP registers to 0
-        MOV     R2,#0
-        VMOV    D0, R2,R2
-        VMOV    D1, R2,R2
-        VMOV    D2, R2,R2
-        VMOV    D3, R2,R2
-        VMOV    D4, R2,R2
-        VMOV    D5, R2,R2
-        VMOV    D6, R2,R2
-        VMOV    D7, R2,R2
-        VMOV    D8, R2,R2
-        VMOV    D9, R2,R2
-        VMOV    D10,R2,R2
-        VMOV    D11,R2,R2
-        VMOV    D12,R2,R2
-        VMOV    D13,R2,R2
-        VMOV    D14,R2,R2
-        VMOV    D15,R2,R2
-
-        //Initialise FPSCR to a known state
-        VMRS    R2,FPSCR
-        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-        AND     R2,R2,R3
-        VMSR    FPSCR,R2
-
-        BX      LR
-
   END

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,1075 +1,1 @@
-/*******************************************************************************
-* DISCLAIMER
-* This software is supplied by Renesas Electronics Corporation and is only
-* intended for use with Renesas products. No other uses are authorized. This
-* software is owned by Renesas Electronics Corporation and is protected under
-* all applicable laws, including copyright laws.
-* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
-* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
-* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
-* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
-* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
-* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
-* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
-* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
-* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
-* Renesas reserves the right, without notice, to make changes to this software
-* and to discontinue the availability of this software. By using this software,
-* you agree to the additional terms and conditions found by accessing the
-* following link:
-* http://www.renesas.com/disclaimer
-* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
-*******************************************************************************/
-/**************************************************************************//**
- * @file     VKRZA1H.h
- * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File for 
- *           Renesas RZA1H Device Series
- * @version
- * @date     19 Sept 2013
- *
- * @note
- *
- ******************************************************************************/
-
-#ifndef __VKRZA1H_H__
-#define __VKRZA1H_H__
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* -------------------------  Interrupt Number Definition  ------------------------ */
-
-typedef enum IRQn
-{
-/******  SGI Interrupts Numbers                 ****************************************/
-  SGI0_IRQn           =  0,
-  SGI1_IRQn           =  1,
-  SGI2_IRQn           =  2,
-  SGI3_IRQn           =  3,
-  SGI4_IRQn           =  4,
-  SGI5_IRQn           =  5,
-  SGI6_IRQn           =  6,
-  SGI7_IRQn           =  7,
-  SGI8_IRQn           =  8,
-  SGI9_IRQn           =  9,
-  SGI10_IRQn          = 10,
-  SGI11_IRQn          = 11,
-  SGI12_IRQn          = 12,
-  SGI13_IRQn          = 13,
-  SGI14_IRQn          = 14,
-  SGI15_IRQn          = 15,
-
-/******  Cortex-A9 Processor Exceptions Numbers ****************************************/
-  /* 16 - 578 */
-  PMUIRQ0_IRQn         = 16,
-  COMMRX0_IRQn         = 17,
-  COMMTX0_IRQn         = 18,
-  CTIIRQ0_IRQn         = 19,
-
-  IRQ0_IRQn            = 32,
-  IRQ1_IRQn            = 33,
-  IRQ2_IRQn            = 34,
-  IRQ3_IRQn            = 35,
-  IRQ4_IRQn            = 36,
-  IRQ5_IRQn            = 37,
-  IRQ6_IRQn            = 38,
-  IRQ7_IRQn            = 39,
-
-  PL310ERR_IRQn        = 40,
-
-  DMAINT0_IRQn         = 41,        /*!< DMAC Interrupt         */
-  DMAINT1_IRQn         = 42,        /*!< DMAC Interrupt         */
-  DMAINT2_IRQn         = 43,        /*!< DMAC Interrupt         */
-  DMAINT3_IRQn         = 44,        /*!< DMAC Interrupt         */
-  DMAINT4_IRQn         = 45,        /*!< DMAC Interrupt         */
-  DMAINT5_IRQn         = 46,        /*!< DMAC Interrupt         */
-  DMAINT6_IRQn         = 47,        /*!< DMAC Interrupt         */
-  DMAINT7_IRQn         = 48,        /*!< DMAC Interrupt         */
-  DMAINT8_IRQn         = 49,        /*!< DMAC Interrupt         */
-  DMAINT9_IRQn         = 50,        /*!< DMAC Interrupt         */
-  DMAINT10_IRQn        = 51,        /*!< DMAC Interrupt         */
-  DMAINT11_IRQn        = 52,        /*!< DMAC Interrupt         */
-  DMAINT12_IRQn        = 53,        /*!< DMAC Interrupt         */
-  DMAINT13_IRQn        = 54,        /*!< DMAC Interrupt         */
-  DMAINT14_IRQn        = 55,        /*!< DMAC Interrupt         */
-  DMAINT15_IRQn        = 56,        /*!< DMAC Interrupt         */
-  DMAERR_IRQn          = 57,        /*!< DMAC Interrupt         */
-
-  /* 58-72 Reserved */
-
-  USBI0_IRQn           = 73,
-  USBI1_IRQn           = 74,
-
-  S0_VI_VSYNC0_IRQn    = 75,
-  S0_LO_VSYNC0_IRQn    = 76,
-  S0_VSYNCERR0_IRQn    = 77,
-  GR3_VLINE0_IRQn      = 78,
-  S0_VFIELD0_IRQn      = 79,
-  IV1_VBUFERR0_IRQn    = 80,
-  IV3_VBUFERR0_IRQn    = 81,
-  IV5_VBUFERR0_IRQn    = 82,
-  IV6_VBUFERR0_IRQn    = 83,
-  S0_WLINE0_IRQn       = 84,
-  S1_VI_VSYNC0_IRQn    = 85,
-  S1_LO_VSYNC0_IRQn    = 86,
-  S1_VSYNCERR0_IRQn    = 87,
-  S1_VFIELD0_IRQn      = 88,
-  IV2_VBUFERR0_IRQn    = 89,
-  IV4_VBUFERR0_IRQn    = 90,
-  S1_WLINE0_IRQn       = 91,
-  OIR_VI_VSYNC0_IRQn   = 92,
-  OIR_LO_VSYNC0_IRQn   = 93,
-  OIR_VSYNCERR0_IRQn   = 94,
-  OIR_VFIELD0_IRQn     = 95,
-  IV7_VBUFERR0_IRQn    = 96,
-  IV8_VBUFERR0_IRQn    = 97,
-  /* 98 Reserved */
-  S0_VI_VSYNC1_IRQn    = 99,
-  S0_LO_VSYNC1_IRQn    = 100,
-  S0_VSYNCERR1_IRQn    = 101,
-  GR3_VLINE1_IRQn      = 102,
-  S0_VFIELD1_IRQn      = 103,
-  IV1_VBUFERR1_IRQn    = 104,
-  IV3_VBUFERR1_IRQn    = 105,
-  IV5_VBUFERR1_IRQn    = 106,
-  IV6_VBUFERR1_IRQn    = 107,
-  S0_WLINE1_IRQn       = 108,
-  S1_VI_VSYNC1_IRQn    = 109,
-  S1_LO_VSYNC1_IRQn    = 110,
-  S1_VSYNCERR1_IRQn    = 111,
-  S1_VFIELD1_IRQn      = 112,
-  IV2_VBUFERR1_IRQn    = 113,
-  IV4_VBUFERR1_IRQn    = 114,
-  S1_WLINE1_IRQn       = 115,
-  OIR_VI_VSYNC1_IRQn   = 116,
-  OIR_LO_VSYNC1_IRQn   = 117,
-  OIR_VSYNCERR1_IRQn   = 118,
-  OIR_VFIELD1_IRQn     = 119,
-  IV7_VBUFERR1_IRQn    = 120,
-  IV8_VBUFERR1_IRQn    = 121,
-  /* Reserved = 122 */
-
-  IMRDI_IRQn           = 123,
-  IMR2I0_IRQn          = 124,
-  IMR2I1_IRQn          = 125,
-
-  JEDI_IRQn            = 126,
-  JDTI_IRQn            = 127,
-
-  CMP0_IRQn            = 128,
-  CMP1_IRQn            = 129,
-
-  INT0_IRQn            = 130,
-  INT1_IRQn            = 131,
-  INT2_IRQn            = 132,
-  INT3_IRQn            = 133,
-
-  OSTMI0TINT_IRQn      = 134,       /*!< OSTM Interrupt         */
-  OSTMI1TINT_IRQn      = 135,       /*!< OSTM Interrupt         */
-
-  CMI_IRQn             = 136,
-  WTOUT_IRQn           = 137,
-
-  ITI_IRQn             = 138,
-
-  TGI0A_IRQn           = 139,
-  TGI0B_IRQn           = 140,
-  TGI0C_IRQn           = 141,
-  TGI0D_IRQn           = 142,
-  TGI0V_IRQn           = 143,
-  TGI0E_IRQn           = 144,
-  TGI0F_IRQn           = 145,
-  TGI1A_IRQn           = 146,
-  TGI1B_IRQn           = 147,
-  TGI1V_IRQn           = 148,
-  TGI1U_IRQn           = 149,
-  TGI2A_IRQn           = 150,
-  TGI2B_IRQn           = 151,
-  TGI2V_IRQn           = 152,
-  TGI2U_IRQn           = 153,
-  TGI3A_IRQn           = 154,
-  TGI3B_IRQn           = 155,
-  TGI3C_IRQn           = 156,
-  TGI3D_IRQn           = 157,
-  TGI3V_IRQn           = 158,
-  TGI4A_IRQn           = 159,
-  TGI4B_IRQn           = 160,
-  TGI4C_IRQn           = 161,
-  TGI4D_IRQn           = 162,
-  TGI4V_IRQn           = 163,
-
-  CMI1_IRQn            = 164,
-  CMI2_IRQn            = 165,
-
-  SGDEI0_IRQn          = 166,
-  SGDEI1_IRQn          = 167,
-  SGDEI2_IRQn          = 168,
-  SGDEI3_IRQn          = 169,
-
-  ADI_IRQn             = 170,
-  LMTI_IRQn            = 171,
-
-  SSII0_IRQn           = 172,       /*!< SSIF Interrupt         */
-  SSIRXI0_IRQn         = 173,       /*!< SSIF Interrupt         */
-  SSITXI0_IRQn         = 174,       /*!< SSIF Interrupt         */
-  SSII1_IRQn           = 175,       /*!< SSIF Interrupt         */
-  SSIRXI1_IRQn         = 176,       /*!< SSIF Interrupt         */
-  SSITXI1_IRQn         = 177,       /*!< SSIF Interrupt         */
-  SSII2_IRQn           = 178,       /*!< SSIF Interrupt         */
-  SSIRTI2_IRQn         = 179,       /*!< SSIF Interrupt         */
-  SSII3_IRQn           = 180,       /*!< SSIF Interrupt         */
-  SSIRXI3_IRQn         = 181,       /*!< SSIF Interrupt         */
-  SSITXI3_IRQn         = 182,       /*!< SSIF Interrupt         */
-  SSII4_IRQn           = 183,       /*!< SSIF Interrupt         */
-  SSIRTI4_IRQn         = 184,       /*!< SSIF Interrupt         */
-  SSII5_IRQn           = 185,       /*!< SSIF Interrupt         */
-  SSIRXI5_IRQn         = 186,       /*!< SSIF Interrupt         */
-  SSITXI5_IRQn         = 187,       /*!< SSIF Interrupt         */
-
-  SPDIFI_IRQn          = 188,
-
-  INTIICTEI0_IRQn      = 189,       /*!< RIIC Interrupt         */
-  INTIICRI0_IRQn       = 190,       /*!< RIIC Interrupt         */
-  INTIICTI0_IRQn       = 191,       /*!< RIIC Interrupt         */
-  INTIICSPI0_IRQn      = 192,       /*!< RIIC Interrupt         */
-  INTIICSTI0_IRQn      = 193,       /*!< RIIC Interrupt         */
-  INTIICNAKI0_IRQn     = 194,       /*!< RIIC Interrupt         */
-  INTIICALI0_IRQn      = 195,       /*!< RIIC Interrupt         */
-  INTIICTMOI0_IRQn     = 196,       /*!< RIIC Interrupt         */
-  INTIICTEI1_IRQn      = 197,       /*!< RIIC Interrupt         */
-  INTIICRI1_IRQn       = 198,       /*!< RIIC Interrupt         */
-  INTIICTI1_IRQn       = 199,       /*!< RIIC Interrupt         */
-  INTIICSPI1_IRQn      = 200,       /*!< RIIC Interrupt         */
-  INTIICSTI1_IRQn      = 201,       /*!< RIIC Interrupt         */
-  INTIICNAKI1_IRQn     = 202,       /*!< RIIC Interrupt         */
-  INTIICALI1_IRQn      = 203,       /*!< RIIC Interrupt         */
-  INTIICTMOI1_IRQn     = 204,       /*!< RIIC Interrupt         */
-  INTIICTEI2_IRQn      = 205,       /*!< RIIC Interrupt         */
-  INTIICRI2_IRQn       = 206,       /*!< RIIC Interrupt         */
-  INTIICTI2_IRQn       = 207,       /*!< RIIC Interrupt         */
-  INTIICSPI2_IRQn      = 208,       /*!< RIIC Interrupt         */
-  INTIICSTI2_IRQn      = 209,       /*!< RIIC Interrupt         */
-  INTIICNAKI2_IRQn     = 210,       /*!< RIIC Interrupt         */
-  INTIICALI2_IRQn      = 211,       /*!< RIIC Interrupt         */
-  INTIICTMOI2_IRQn     = 212,       /*!< RIIC Interrupt         */
-  INTIICTEI3_IRQn      = 213,       /*!< RIIC Interrupt         */
-  INTIICRI3_IRQn       = 214,       /*!< RIIC Interrupt         */
-  INTIICTI3_IRQn       = 215,       /*!< RIIC Interrupt         */
-  INTIICSPI3_IRQn      = 216,       /*!< RIIC Interrupt         */
-  INTIICSTI3_IRQn      = 217,       /*!< RIIC Interrupt         */
-  INTIICNAKI3_IRQn     = 218,       /*!< RIIC Interrupt         */
-  INTIICALI3_IRQn      = 219,       /*!< RIIC Interrupt         */
-  INTIICTMOI3_IRQn     = 220,       /*!< RIIC Interrupt         */
-
-  SCIFBRI0_IRQn        = 221,       /*!< SCIF Interrupt         */
-  SCIFERI0_IRQn        = 222,       /*!< SCIF Interrupt         */
-  SCIFRXI0_IRQn        = 223,       /*!< SCIF Interrupt         */
-  SCIFTXI0_IRQn        = 224,       /*!< SCIF Interrupt         */
-  SCIFBRI1_IRQn        = 225,       /*!< SCIF Interrupt         */
-  SCIFERI1_IRQn        = 226,       /*!< SCIF Interrupt         */
-  SCIFRXI1_IRQn        = 227,       /*!< SCIF Interrupt         */
-  SCIFTXI1_IRQn        = 228,       /*!< SCIF Interrupt         */
-  SCIFBRI2_IRQn        = 229,       /*!< SCIF Interrupt         */
-  SCIFERI2_IRQn        = 230,       /*!< SCIF Interrupt         */
-  SCIFRXI2_IRQn        = 231,       /*!< SCIF Interrupt         */
-  SCIFTXI2_IRQn        = 232,       /*!< SCIF Interrupt         */
-  SCIFBRI3_IRQn        = 233,       /*!< SCIF Interrupt         */
-  SCIFERI3_IRQn        = 234,       /*!< SCIF Interrupt         */
-  SCIFRXI3_IRQn        = 235,       /*!< SCIF Interrupt         */
-  SCIFTXI3_IRQn        = 236,       /*!< SCIF Interrupt         */
-  SCIFBRI4_IRQn        = 237,       /*!< SCIF Interrupt         */
-  SCIFERI4_IRQn        = 238,       /*!< SCIF Interrupt         */
-  SCIFRXI4_IRQn        = 239,       /*!< SCIF Interrupt         */
-  SCIFTXI4_IRQn        = 240,       /*!< SCIF Interrupt         */
-  SCIFBRI5_IRQn        = 241,       /*!< SCIF Interrupt         */
-  SCIFERI5_IRQn        = 242,       /*!< SCIF Interrupt         */
-  SCIFRXI5_IRQn        = 243,       /*!< SCIF Interrupt         */
-  SCIFTXI5_IRQn        = 244,       /*!< SCIF Interrupt         */
-  SCIFBRI6_IRQn        = 245,       /*!< SCIF Interrupt         */
-  SCIFERI6_IRQn        = 246,       /*!< SCIF Interrupt         */
-  SCIFRXI6_IRQn        = 247,       /*!< SCIF Interrupt         */
-  SCIFTXI6_IRQn        = 248,       /*!< SCIF Interrupt         */
-  SCIFBRI7_IRQn        = 249,       /*!< SCIF Interrupt         */
-  SCIFERI7_IRQn        = 250,       /*!< SCIF Interrupt         */
-  SCIFRXI7_IRQn        = 251,       /*!< SCIF Interrupt         */
-  SCIFTXI7_IRQn        = 252,       /*!< SCIF Interrupt         */
-
-  INTRCANGERR_IRQn     = 253,
-  INTRCANGRECC_IRQn    = 254,
-  INTRCAN0REC_IRQn     = 255,
-  INTRCAN0ERR_IRQn     = 256,
-  INTRCAN0TRX_IRQn     = 257,
-  INTRCAN1REC_IRQn     = 258,
-  INTRCAN1ERR_IRQn     = 259,
-  INTRCAN1TRX_IRQn     = 260,
-  INTRCAN2REC_IRQn     = 261,
-  INTRCAN2ERR_IRQn     = 262,
-  INTRCAN2TRX_IRQn     = 263,
-  INTRCAN3REC_IRQn     = 264,
-  INTRCAN3ERR_IRQn     = 265,
-  INTRCAN3TRX_IRQn     = 266,
-  INTRCAN4REC_IRQn     = 267,
-  INTRCAN4ERR_IRQn     = 268,
-  INTRCAN4TRX_IRQn     = 269,
-
-  RSPISPEI0_IRQn       = 270,       /*!< RSPI Interrupt         */
-  RSPISPRI0_IRQn       = 271,       /*!< RSPI Interrupt         */
-  RSPISPTI0_IRQn       = 272,       /*!< RSPI Interrupt         */
-  RSPISPEI1_IRQn       = 273,       /*!< RSPI Interrupt         */
-  RSPISPRI1_IRQn       = 274,       /*!< RSPI Interrupt         */
-  RSPISPTI1_IRQn       = 275,       /*!< RSPI Interrupt         */
-  RSPISPEI2_IRQn       = 276,       /*!< RSPI Interrupt         */
-  RSPISPRI2_IRQn       = 277,       /*!< RSPI Interrupt         */
-  RSPISPTI2_IRQn       = 278,       /*!< RSPI Interrupt         */
-  RSPISPEI3_IRQn       = 279,       /*!< RSPI Interrupt         */
-  RSPISPRI3_IRQn       = 280,       /*!< RSPI Interrupt         */
-  RSPISPTI3_IRQn       = 281,       /*!< RSPI Interrupt         */
-  RSPISPEI4_IRQn       = 282,       /*!< RSPI Interrupt         */
-  RSPISPRI4_IRQn       = 283,       /*!< RSPI Interrupt         */
-  RSPISPTI4_IRQn       = 284,       /*!< RSPI Interrupt         */
-
-  IEBBTD_IRQn          = 285,
-  IEBBTERR_IRQn        = 286,
-  IEBBTSTA_IRQn        = 287,
-  IEBBTV_IRQn          = 288,
-
-  ISY_IRQn             = 289,
-  IERR_IRQn            = 290,
-  ITARG_IRQn           = 291,
-  ISEC_IRQn            = 292,
-  IBUF_IRQn            = 293,
-  IREADY_IRQn          = 294,
-
-  STERB_IRQn           = 295,
-  FLTENDI_IRQn         = 296,
-  FLTREQ0I_IRQn        = 297,
-  FLTREQ1I_IRQn        = 298,
-
-  MMC0_IRQn            = 299,
-  MMC1_IRQn            = 300,
-  MMC2_IRQn            = 301,
-
-  SCHI0_3_IRQn         = 302,
-  SDHI0_0_IRQn         = 303,
-  SDHI0_1_IRQn         = 304,
-  SCHI1_3_IRQn         = 305,
-  SDHI1_0_IRQn         = 306,
-  SDHI1_1_IRQn         = 307,
-
-  ARM_IRQn             = 308,
-  PRD_IRQn             = 309,
-  CUP_IRQn             = 310,
-
-  SCUAI0_IRQn          = 311,
-  SCUAI1_IRQn          = 312,
-  SCUFDI0_IRQn         = 313,
-  SCUFDI1_IRQn         = 314,
-  SCUFDI2_IRQn         = 315,
-  SCUFDI3_IRQn         = 316,
-  SCUFUI0_IRQn         = 317,
-  SCUFUI1_IRQn         = 318,
-  SCUFUI2_IRQn         = 319,
-  SCUFUI3_IRQn         = 320,
-  SCUDVI0_IRQn         = 321,
-  SCUDVI1_IRQn         = 322,
-  SCUDVI2_IRQn         = 323,
-  SCUDVI3_IRQn         = 324,
-
-  MLB_CINT_IRQn        = 325,
-  MLB_SINT_IRQn        = 326,
-
-  DRC10_IRQn           = 327,
-  DRC11_IRQn           = 328,
-
-  /* 329-330 Reserved  */
-
-  LINI0_INT_T_IRQn     = 331,
-  LINI0_INT_R_IRQn     = 332,
-  LINI0_INT_S_IRQn     = 333,
-  LINI0_INT_M_IRQn     = 334,
-  LINI1_INT_T_IRQn     = 335,
-  LINI1_INT_R_IRQn     = 336,
-  LINI1_INT_S_IRQn     = 337,
-  LINI1_INT_M_IRQn     = 338,
-
-  /* 339-346 Reserved */
-
-  SCIERI0_IRQn         = 347,
-  SCIRXI0_IRQn         = 348,
-  SCITXI0_IRQn         = 349,
-  SCITEI0_IRQn         = 350,
-  SCIERI1_IRQn         = 351,
-  SCIRXI1_IRQn         = 352,
-  SCITXI1_IRQn         = 353,
-  SCITEI1_IRQn         = 354,
-
-  AVBI_DATA            = 355,
-  AVBI_ERROR           = 356,
-  AVBI_MANAGE          = 357,
-  AVBI_MAC             = 358,
-
-  ETHERI_IRQn          = 359,
-
-  /* 360-363 Reserved */
-
-  CEUI_IRQn            = 364,
-
-  /* 365-380 Reserved */
-
-
-  H2XMLB_ERRINT_IRQn   = 381,
-  H2XIC1_ERRINT_IRQn   = 382,
-  X2HPERI1_ERRINT_IRQn = 383,
-  X2HPERR2_ERRINT_IRQn = 384,
-  X2HPERR34_ERRINT_IRQn= 385,
-  X2HPERR5_ERRINT_IRQn = 386,
-  X2HPERR67_ERRINT_IRQn= 387,
-  X2HDBGR_ERRINT_IRQn  = 388,
-  X2HBSC_ERRINT_IRQn   = 389,   
-  X2HSPI1_ERRINT_IRQn  = 390,   
-  X2HSPI2_ERRINT_IRQn  = 391,   
-  PRRI_IRQn            = 392,
-
-  IFEI0_IRQn           = 393,
-  OFFI0_IRQn           = 394,
-  PFVEI0_IRQn          = 395,
-  IFEI1_IRQn           = 396,
-  OFFI1_IRQn           = 397,
-  PFVEI1_IRQn          = 398,
-
-  /* 399-415 Reserved */
-  TINT0_IRQn           = 416,
-  TINT1_IRQn           = 417,
-  TINT2_IRQn           = 418,
-  TINT3_IRQn           = 419,
-  TINT4_IRQn           = 420,
-  TINT5_IRQn           = 421,
-  TINT6_IRQn           = 422,
-  TINT7_IRQn           = 423,
-  TINT8_IRQn           = 424,
-  TINT9_IRQn           = 425,
-  TINT10_IRQn          = 426,
-  TINT11_IRQn          = 427,
-  TINT12_IRQn          = 428,
-  TINT13_IRQn          = 429,
-  TINT14_IRQn          = 430,
-  TINT15_IRQn          = 431,
-  TINT16_IRQn          = 432,
-  TINT17_IRQn          = 433,
-  TINT18_IRQn          = 434,
-  TINT19_IRQn          = 435,
-  TINT20_IRQn          = 436,
-  TINT21_IRQn          = 437,
-  TINT22_IRQn          = 438,
-  TINT23_IRQn          = 439,
-  TINT24_IRQn          = 440,
-  TINT25_IRQn          = 441,
-  TINT26_IRQn          = 442,
-  TINT27_IRQn          = 443,
-  TINT28_IRQn          = 444,
-  TINT29_IRQn          = 445,
-  TINT30_IRQn          = 446,
-  TINT31_IRQn          = 447,
-  TINT32_IRQn          = 448,
-  TINT33_IRQn          = 449,
-  TINT34_IRQn          = 450,
-  TINT35_IRQn          = 451,
-  TINT36_IRQn          = 452,
-  TINT37_IRQn          = 453,
-  TINT38_IRQn          = 454,
-  TINT39_IRQn          = 455,
-  TINT40_IRQn          = 456,
-  TINT41_IRQn          = 457,
-  TINT42_IRQn          = 458,
-  TINT43_IRQn          = 459,
-  TINT44_IRQn          = 460,
-  TINT45_IRQn          = 461,
-  TINT46_IRQn          = 462,
-  TINT47_IRQn          = 463,
-  TINT48_IRQn          = 464,
-  TINT49_IRQn          = 465,
-  TINT50_IRQn          = 466,
-  TINT51_IRQn          = 467,
-  TINT52_IRQn          = 468,
-  TINT53_IRQn          = 469,
-  TINT54_IRQn          = 470,
-  TINT55_IRQn          = 471,
-  TINT56_IRQn          = 472,
-  TINT57_IRQn          = 473,
-  TINT58_IRQn          = 474,
-  TINT59_IRQn          = 475,
-  TINT60_IRQn          = 476,
-  TINT61_IRQn          = 477,
-  TINT62_IRQn          = 478,
-  TINT63_IRQn          = 479,
-  TINT64_IRQn          = 480,
-  TINT65_IRQn          = 481,
-  TINT66_IRQn          = 482,
-  TINT67_IRQn          = 483,
-  TINT68_IRQn          = 484,
-  TINT69_IRQn          = 485,
-  TINT70_IRQn          = 486,
-  TINT71_IRQn          = 487,
-  TINT72_IRQn          = 488,
-  TINT73_IRQn          = 489,
-  TINT74_IRQn          = 490,
-  TINT75_IRQn          = 491,
-  TINT76_IRQn          = 492,
-  TINT77_IRQn          = 493,
-  TINT78_IRQn          = 494,
-  TINT79_IRQn          = 495,
-  TINT80_IRQn          = 496,
-  TINT81_IRQn          = 497,
-  TINT82_IRQn          = 498,
-  TINT83_IRQn          = 499,
-  TINT84_IRQn          = 500,
-  TINT85_IRQn          = 501,
-  TINT86_IRQn          = 502,
-  TINT87_IRQn          = 503,
-  TINT88_IRQn          = 504,
-  TINT89_IRQn          = 505,
-  TINT90_IRQn          = 506,
-  TINT91_IRQn          = 507,
-  TINT92_IRQn          = 508,
-  TINT93_IRQn          = 509,
-  TINT94_IRQn          = 510,
-  TINT95_IRQn          = 511,
-  TINT96_IRQn          = 512,
-  TINT97_IRQn          = 513,
-  TINT98_IRQn          = 514,
-  TINT99_IRQn          = 515,
-  TINT100_IRQn         = 516,
-  TINT101_IRQn         = 517,
-  TINT102_IRQn         = 518,
-  TINT103_IRQn         = 519,
-  TINT104_IRQn         = 520,
-  TINT105_IRQn         = 521,
-  TINT106_IRQn         = 522,
-  TINT107_IRQn         = 523,
-  TINT108_IRQn         = 524,
-  TINT109_IRQn         = 525,
-  TINT110_IRQn         = 526,
-  TINT111_IRQn         = 527,
-  TINT112_IRQn         = 528,
-  TINT113_IRQn         = 529,
-  TINT114_IRQn         = 530,
-  TINT115_IRQn         = 531,
-  TINT116_IRQn         = 532,
-  TINT117_IRQn         = 533,
-  TINT118_IRQn         = 534,
-  TINT119_IRQn         = 535,
-  TINT120_IRQn         = 536,
-  TINT121_IRQn         = 537,
-  TINT122_IRQn         = 538,
-  TINT123_IRQn         = 539,
-  TINT124_IRQn         = 540,
-  TINT125_IRQn         = 541,
-  TINT126_IRQn         = 542,
-  TINT127_IRQn         = 543,
-  TINT128_IRQn         = 544,
-  TINT129_IRQn         = 545,
-  TINT130_IRQn         = 546,
-  TINT131_IRQn         = 547,
-  TINT132_IRQn         = 548,
-  TINT133_IRQn         = 549,
-  TINT134_IRQn         = 550,
-  TINT135_IRQn         = 551,
-  TINT136_IRQn         = 552,
-  TINT137_IRQn         = 553,
-  TINT138_IRQn         = 554,
-  TINT139_IRQn         = 555,
-  TINT140_IRQn         = 556,
-  TINT141_IRQn         = 557,
-  TINT142_IRQn         = 558,
-  TINT143_IRQn         = 559,
-  TINT144_IRQn         = 560,
-  TINT145_IRQn         = 561,
-  TINT146_IRQn         = 562,
-  TINT147_IRQn         = 563,
-  TINT148_IRQn         = 564,
-  TINT149_IRQn         = 565,
-  TINT150_IRQn         = 566,
-  TINT151_IRQn         = 567,
-  TINT152_IRQn         = 568,
-  TINT153_IRQn         = 569,
-  TINT154_IRQn         = 570,
-  TINT155_IRQn         = 571,
-  TINT156_IRQn         = 572,
-  TINT157_IRQn         = 573,
-  TINT158_IRQn         = 574,
-  TINT159_IRQn         = 575,
-  TINT160_IRQn         = 576,
-  TINT161_IRQn         = 577,
-  TINT162_IRQn         = 578,
-  TINT163_IRQn         = 579,
-  TINT164_IRQn         = 580,
-  TINT165_IRQn         = 581,
-  TINT166_IRQn         = 582,
-  TINT167_IRQn         = 583,
-  TINT168_IRQn         = 584,
-  TINT169_IRQn         = 585,
-  TINT170_IRQn         = 586
-
-} IRQn_Type;
-
-#define Renesas_RZ_A1_IRQ_MAX  TINT170_IRQn
-
-/* --------  Configuration of the Cortex-A9 Processor and Core Peripherals  ------- */
-#define __CA9_REV                 0x0000    /*!< Core revision r0                                */
-
-#define __MPU_PRESENT             1         /*!< MPU present or not                               */
-
-#define __FPU_PRESENT             1         /*!< FPU present or not                               */
-
-#define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
-#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
-
-#include "core_ca.h"
-#include "system_VKRZA1H.h"
-#include "iodefine.h"
-
-/******************************************************************************/
-/*                Device Specific Peripheral Section                          */
-/******************************************************************************/
-/** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
-  Renesas_RZ_A1 Device Specific Peripheral registers structures
-  @{
-*/
-
-#if defined ( __CC_ARM   )
-#pragma anon_unions
-#endif
-
-#include "pl310.h"
-#include "gic.h"
-#include "nvic_wrapper.h"
-#include "cmsis_nvic.h"
-
-#include "ostm_iodefine.h"
-#include "gpio_iodefine.h"
-#include "cpg_iodefine.h"
-#include "l2c_iodefine.h"
-
-#if defined ( __CC_ARM   )
-#pragma no_anon_unions
-#endif
-
-/*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
-
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-/** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
-  @{
-*/
-
-/* R7S72100 CPU board  */
-#define Renesas_RZ_A1_NORFLASH_BASE0               (0x00000000UL)                        /*!< (FLASH0    ) Base Address */
-#define Renesas_RZ_A1_NORFLASH_BASE1               (0x04000000UL)                        /*!< (FLASH1    ) Base Address */
-#define Renesas_RZ_A1_SDRAM_BASE0                  (0x08000000UL)                        /*!< (SDRAM0    ) Base Address */
-#define Renesas_RZ_A1_SDRAM_BASE1                  (0x0C000000UL)                        /*!< (SDRAM1    ) Base Address */
-#define Renesas_RZ_A1_USER_AREA0                   (0x10000000UL)                        /*!< (USER0     ) Base Address */
-#define Renesas_RZ_A1_USER_AREA1                   (0x14000000UL)                        /*!< (USER1     ) Base Address */
-#define Renesas_RZ_A1_SPI_IO0                      (0x18000000UL)                        /*!< (SPI_IO0   ) Base Address */
-#define Renesas_RZ_A1_SPI_IO1                      (0x1C000000UL)                        /*!< (SPI_IO1   ) Base Address */
-#define Renesas_RZ_A1_ONCHIP_SRAM_BASE             (0x20000000UL)                        /*!< (SRAM_OC   ) Base Address */
-#define Renesas_RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
-#define Renesas_RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
-#define Renesas_RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
-#define Renesas_RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
-#define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE         (0xe8201000UL)                        /*!< (GIC DIST  ) Base Address */
-#define Renesas_RZ_A1_GIC_INTERFACE_BASE           (0xe8202000UL)                        /*!< (GIC CPU IF) Base Address */
-#define Renesas_RZ_A1_PL310_BASE                   (0x3ffff000UL)                        /*!< (PL310     ) Base Address */
-#define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE          (0x60000000UL)                        /*!< (SRAM_OC   ) Base Address */
-
-//Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
-//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
-#define section_normal(descriptor_l1, region)     region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = NON_SECURE; \
-                                   region.xn_t = EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-#define section_normal_nc(descriptor_l1, region)     region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
-#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = NON_SECURE; \
-                                   region.xn_t = EXECUTE; \
-                                   region.priv_t = READ; \
-                                   region.user_t = READ; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-//Sect_Normal_RO. Sect_Normal_Cod, but not executable
-#define section_normal_ro(descriptor_l1, region)  region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = NON_SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = READ; \
-                                   region.user_t = READ; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-#ifdef __RAM_DEBUG__
-//Sect_Normal_RWX. Sect_Normal_Cod, but writeable
-#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = NON_SECURE; \
-                                   region.xn_t = EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-#else
-//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
-#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = WB_WA; \
-                                   region.outer_norm_t = WB_WA; \
-                                   region.mem_t = NORMAL; \
-                                   region.sec_t = NON_SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-#endif
-
-//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
-#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = STRONGLY_ORDERED; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
-#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = STRONGLY_ORDERED; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = READ; \
-                                   region.user_t = READ; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-
-//Sect_Device_RW. Sect_Device_RO, but writeable
-#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = STRONGLY_ORDERED; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_section_descriptor(&descriptor_l1, region);
-//Page_4k_Device_RW.  Shared device, not executable, rw, domain 0
-#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = SHARED_DEVICE; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
-
-//Page_64k_Device_RW.  Shared device, not executable, rw, domain 0
-#define page64k_device_rw(descriptor_l1, descriptor_l2, region)  region.rg_t = PAGE_64k; \
-                                   region.domain = 0x0; \
-                                   region.e_t = ECC_DISABLED; \
-                                   region.g_t = GLOBAL; \
-                                   region.inner_norm_t = NON_CACHEABLE; \
-                                   region.outer_norm_t = NON_CACHEABLE; \
-                                   region.mem_t = SHARED_DEVICE; \
-                                   region.sec_t = SECURE; \
-                                   region.xn_t = NON_EXECUTE; \
-                                   region.priv_t = RW; \
-                                   region.user_t = RW; \
-                                   region.sh_t = NON_SHARED; \
-                                   __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
-
-/*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
-
-/******************************************************************************/
-/*                         Clock Settings                                     */
-/******************************************************************************/
-/** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
-  @{
-*/
-
-/*
- * Clock Mode 0 settings
- * SW1-4(MD_CLK):ON
- * SW1-5(MD_CLKS):ON
- * FRQCR=0x1035
- *   CLKEN2    = 0b - unstable
- *   CLKEN[1:0]=01b - Output, Low, Low
- *   IFC[1:0]  =00b - CPU clock is 1/1 PLL clock
- * FRQCR2=0x0001
- *   GFC[1:0]  =01b - Graphic clock is 2/3 bus clock
- */
-#define CM0_RENESAS_RZ_A1_CLKIN  ( 13333333u)
-#define CM0_RENESAS_RZ_A1_CLKO   ( 66666666u)
-#define CM0_RENESAS_RZ_A1_I_CLK  (400000000u)
-#define CM0_RENESAS_RZ_A1_G_CLK  (266666666u)
-#define CM0_RENESAS_RZ_A1_B_CLK  (133333333u)
-#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
-#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
-
-/*
- * Clock Mode 1 settings
- * SW1-4(MD_CLK):OFF
- * SW1-5(MD_CLKS):ON
- * FRQCR=0x1335
- *   CLKEN2    = 0b - unstable
- *   CLKEN[1:0]=01b - Output, Low, Low
- *   IFC[1:0]  =11b - CPU clock is 1/3 PLL clock
- * FRQCR2=0x0003
- *   GFC[1:0]  =11b - graphic clock is 1/3 bus clock
- */
-#define CM1_RENESAS_RZ_A1_CLKIN  ( 48000000u)
-#define CM1_RENESAS_RZ_A1_CLKO   ( 64000000u)
-#define CM1_RENESAS_RZ_A1_I_CLK  (128000000u)
-#define CM1_RENESAS_RZ_A1_G_CLK  (128000000u)
-#define CM1_RENESAS_RZ_A1_B_CLK  (128000000u)
-#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
-#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
-
-/*@}*/ /* end of group Renesas_RZ_A1_Clocks */
-
-/******************************************************************************/
-/*                         CPG   Settings                                     */
-/******************************************************************************/
-/** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
-  @{
-*/
-
-#define CPG_FRQCR_SHIFT_CKOEN2  (14)
-#define CPG_FRQCR_BIT_CKOEN2    (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
-#define CPG_FRQCR_SHIFT_CKOEN0  (12)
-#define CPG_FRQCR_BITS_CKOEN0   (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
-#define CPG_FRQCR_SHIFT_IFC     (8)
-#define CPG_FRQCR_BITS_IFC      (0x3 << CPG_FRQCR_SHIFT_IFC)
-
-#define CPG_FRQCR2_SHIFT_GFC    (0)
-#define CPG_FRQCR2_BITS_GFC     (0x3 << CPG_FRQCR2_SHIFT_GFC)
-
-
-#define CPG_STBCR1_BIT_STBY     (0x80u)
-#define CPG_STBCR1_BIT_DEEP     (0x40u)
-#define CPG_STBCR2_BIT_HIZ      (0x80u)
-#define CPG_STBCR2_BIT_MSTP20   (0x01u) /* CoreSight */
-#define CPG_STBCR3_BIT_MSTP37   (0x80u) /* IEBus */
-#define CPG_STBCR3_BIT_MSTP36   (0x40u) /* IrDA */
-#define CPG_STBCR3_BIT_MSTP35   (0x20u) /* LIN0 */
-#define CPG_STBCR3_BIT_MSTP34   (0x10u) /* LIN1 */
-#define CPG_STBCR3_BIT_MSTP33   (0x08u) /* Multi-Function Timer */
-#define CPG_STBCR3_BIT_MSTP32   (0x04u) /* CAN */
-#define CPG_STBCR3_BIT_MSTP30   (0x01u) /* Motor Control PWM Timer */
-#define CPG_STBCR4_BIT_MSTP47   (0x80u) /* SCIF0 */
-#define CPG_STBCR4_BIT_MSTP46   (0x40u) /* SCIF1 */
-#define CPG_STBCR4_BIT_MSTP45   (0x20u) /* SCIF2 */
-#define CPG_STBCR4_BIT_MSTP44   (0x10u) /* SCIF3 */
-#define CPG_STBCR4_BIT_MSTP43   (0x08u) /* SCIF4 */
-#define CPG_STBCR4_BIT_MSTP42   (0x04u) /* SCIF5 */
-#define CPG_STBCR4_BIT_MSTP41   (0x02u) /* SCIF6 */
-#define CPG_STBCR4_BIT_MSTP40   (0x01u) /* SCIF7 */
-#define CPG_STBCR5_BIT_MSTP57   (0x80u) /* SCI0 */
-#define CPG_STBCR5_BIT_MSTP56   (0x40u) /* SCI1 */
-#define CPG_STBCR5_BIT_MSTP55   (0x20u) /* Sound Generator0 */
-#define CPG_STBCR5_BIT_MSTP54   (0x10u) /* Sound Generator1 */
-#define CPG_STBCR5_BIT_MSTP53   (0x08u) /* Sound Generator2 */
-#define CPG_STBCR5_BIT_MSTP52   (0x04u) /* Sound Generator3 */
-#define CPG_STBCR5_BIT_MSTP51   (0x02u) /* OSTM0 */
-#define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
-#define CPG_STBCR6_BIT_MSTP67   (0x80u) /* General A/D Comvertor */
-#define CPG_STBCR6_BIT_MSTP66   (0x40u) /* Capture Engine */
-#define CPG_STBCR6_BIT_MSTP65   (0x20u) /* Display out comparison0 */
-#define CPG_STBCR6_BIT_MSTP64   (0x10u) /* Display out comparison1 */   
-#define CPG_STBCR6_BIT_MSTP63   (0x08u) /* Dynamic Range Compalator0 */
-#define CPG_STBCR6_BIT_MSTP62   (0x04u) /* Dynamic Range Compalator1 */
-#define CPG_STBCR6_BIT_MSTP61   (0x02u) /* JPEG Decoder */
-#define CPG_STBCR6_BIT_MSTP60   (0x01u) /* Realtime Clock */
-#define CPG_STBCR7_BIT_MSTP77   (0x80u) /* Video Decoder0 */
-#define CPG_STBCR7_BIT_MSTP76   (0x40u) /* Video Decoder1 */
-#define CPG_STBCR7_BIT_MSTP74   (0x10u) /* Ether */
-#define CPG_STBCR7_BIT_MSTP73   (0x04u) /* NAND Flash Memory Controller */
-#define CPG_STBCR7_BIT_MSTP71   (0x02u) /* USB0 */
-#define CPG_STBCR7_BIT_MSTP70   (0x01u) /* USB1 */
-#define CPG_STBCR8_BIT_MSTP87   (0x80u) /* IMR-LS2_0 */
-#define CPG_STBCR8_BIT_MSTP86   (0x40u) /* IMR-LS2_1 */
-#define CPG_STBCR8_BIT_MSTP85   (0x20u) /* IMR-LSD */
-#define CPG_STBCR8_BIT_MSTP84   (0x10u) /* MMC Host Interface */
-#define CPG_STBCR8_BIT_MSTP83   (0x08u) /* MediaLB */
-#define CPG_STBCR8_BIT_MSTP81   (0x02u) /* SCUX */
-#define CPG_STBCR9_BIT_MSTP97   (0x80u) /* RIIC0 */
-#define CPG_STBCR9_BIT_MSTP96   (0x40u) /* RIIC1 */
-#define CPG_STBCR9_BIT_MSTP95   (0x20u) /* RIIC2 */
-#define CPG_STBCR9_BIT_MSTP94   (0x10u) /* RIIC3 */
-#define CPG_STBCR9_BIT_MSTP93   (0x08u) /* SPI Multi I/O Bus Controller0 */
-#define CPG_STBCR9_BIT_MSTP92   (0x04u) /* SPI Multi I/O Bus Controller1 */
-#define CPG_STBCR9_BIT_MSTP91   (0x02u) /* VDC5_0 */
-#define CPG_STBCR9_BIT_MSTP90   (0x01u) /* VDC5_1 */
-#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
-#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
-#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
-#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
-#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
-#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
-#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
-#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
-#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
-#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
-#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
-#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
-#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
-#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
-#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
-#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
-#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
-#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
-#define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
-#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
-#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
-#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
-#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
-#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
-#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
-#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
-#define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
-#define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
-#define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
-#define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
-#define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
-#define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
-#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
-#define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
-#define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
-#define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
-#define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
-#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
-#define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
-#define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
-#define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
-#define CPG_SYSCR1_BIT_VRAME4   (0x10u) /* VRAM E Page4 */
-#define CPG_SYSCR1_BIT_VRAME3   (0x08u) /* VRAM E Page3 */
-#define CPG_SYSCR1_BIT_VRAME2   (0x04u) /* VRAM E Page2 */
-#define CPG_SYSCR1_BIT_VRAME1   (0x02u) /* VRAM E Page1 */
-#define CPG_SYSCR1_BIT_VRAME0   (0x01u) /* VRAM E Page0 */
-#define CPG_SYSCR2_BIT_VRAMWE4  (0x10u) /* VRAM WE Page4 */
-#define CPG_SYSCR2_BIT_VRAMWE3  (0x08u) /* VRAM WE Page3 */
-#define CPG_SYSCR2_BIT_VRAMWE2  (0x04u) /* VRAM WE Page2 */
-#define CPG_SYSCR2_BIT_VRAMWE1  (0x02u) /* VRAM WE Page1 */
-#define CPG_SYSCR2_BIT_VRAMWE0  (0x01u) /* VRAM WE Page0 */
-#define CPG_SYSCR3_BIT_RRAMWE3  (0x08u) /* RRAM WE Page3 */
-#define CPG_SYSCR3_BIT_RRAMWE2  (0x04u) /* RRAM WE Page2 */
-#define CPG_SYSCR3_BIT_RRAMWE1  (0x02u) /* RRAM WE Page1 */
-#define CPG_SYSCR3_BIT_RRAMWE0  (0x01u) /* RRAM WE Page0 */
-
-/*@}*/ /* end of group Renesas_RZ_A1_CPG */
-
-/******************************************************************************/
-/*                        GPIO   Settings                                     */
-/******************************************************************************/
-/** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
-  @{
-*/
-
-#define GPIO_BIT_N0  (1u <<  0)
-#define GPIO_BIT_N1  (1u <<  1)
-#define GPIO_BIT_N2  (1u <<  2)
-#define GPIO_BIT_N3  (1u <<  3)
-#define GPIO_BIT_N4  (1u <<  4)
-#define GPIO_BIT_N5  (1u <<  5)
-#define GPIO_BIT_N6  (1u <<  6)
-#define GPIO_BIT_N7  (1u <<  7)
-#define GPIO_BIT_N8  (1u <<  8)
-#define GPIO_BIT_N9  (1u <<  9)
-#define GPIO_BIT_N10 (1u << 10)
-#define GPIO_BIT_N11 (1u << 11)
-#define GPIO_BIT_N12 (1u << 12)
-#define GPIO_BIT_N13 (1u << 13)
-#define GPIO_BIT_N14 (1u << 14)
-#define GPIO_BIT_N15 (1u << 15)
-
-
-#define MD_BOOT10_MASK    (0x3)
-
-#define MD_BOOT10_BM0     (0x0)
-#define MD_BOOT10_BM1     (0x2)
-#define MD_BOOT10_BM3     (0x1)
-#define MD_BOOT10_BM4_5   (0x3)
-
-#define MD_CLK        (1u << 2)
-#define MD_CLKS       (1u << 3)
-
-/*@}*/ /* end of group Renesas_RZ_A1_GPIO */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  // __VKRZA1H_H__
+#include "VK_RZ_A1H.h"

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h	Thu Apr 19 17:12:19 2018 +0100
@@ -8,5 +8,6 @@
 #define MBED_CMSIS_H
 
 #include "VKRZA1H.h"
+#include "cmsis_nvic.h"
 
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c	Thu Apr 19 17:12:19 2018 +0100
@@ -29,14 +29,15 @@
  *******************************************************************************
  */
 #include "VKRZA1H.h"
+#include "irq_ctrl.h"
 
-extern IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
     InterruptHandlerRegister(IRQn, (IRQHandler)vector);
 }
 
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t vectors = (uint32_t)IRQTable[IRQn];
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn);
     return vectors;
 }

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.c	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,305 +0,0 @@
-/**************************************************************************//**
- * @file     gic.c
- * @brief    Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date     19 Sept 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#include "VKRZA1H.h"
-
-#define GICDistributor      ((GICDistributor_Type      *)     Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE ) /*!< GIC Distributor configuration struct */
-#define GICInterface        ((GICInterface_Type        *)     Renesas_RZ_A1_GIC_INTERFACE_BASE )   /*!< GIC Interface configuration struct */
-
-/* Globals for use of post-scatterloading code that must access GIC */
-const uint32_t GICDistributor_BASE = Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE;
-const uint32_t GICInterface_BASE = Renesas_RZ_A1_GIC_INTERFACE_BASE;
-
-void GIC_EnableDistributor(void)
-{
-    GICDistributor->ICDDCR |= 1; //enable distributor
-}
-
-void GIC_DisableDistributor(void)
-{
-    GICDistributor->ICDDCR &=~1; //disable distributor
-}
-
-uint32_t GIC_DistributorInfo(void)
-{
-    return (uint32_t)(GICDistributor->ICDICTR);
-}
-
-uint32_t GIC_DistributorImplementer(void)
-{
-    return (uint32_t)(GICDistributor->ICDIIDR);
-}
-
-void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
-{
-    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
-    field += IRQn % 4;
-    *field = (uint8_t)cpu_target & 0xf;
-}
-
-void GIC_SetICDICFR (const uint32_t *ICDICFRn)
-{
-    uint32_t i, num_irq;
-
-    //Get the maximum number of interrupts that the GIC supports
-    num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
-
-    for (i = 0; i < (num_irq/16); i++)
-    {
-        GICDistributor->ICDISPR[i] = *ICDICFRn++;
-    }
-}
-
-uint32_t GIC_GetTarget(IRQn_Type IRQn)
-{
-    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPTR[IRQn / 4]);
-    field += IRQn % 4;
-    return ((uint32_t)*field & 0xf);
-}
-
-void GIC_EnableInterface(void)
-{
-    GICInterface->ICCICR |= 1; //enable interface
-}
-
-void GIC_DisableInterface(void)
-{
-    GICInterface->ICCICR &=~1; //disable distributor
-}
-
-IRQn_Type GIC_AcknowledgePending(void)
-{
-    return (IRQn_Type)(GICInterface->ICCIAR);
-}
-
-void GIC_EndInterrupt(IRQn_Type IRQn)
-{
-    GICInterface->ICCEOIR = IRQn;
-}
-
-void GIC_EnableIRQ(IRQn_Type IRQn)
-{
-    GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-void GIC_DisableIRQ(IRQn_Type IRQn)
-{
-    GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-void GIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-    GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-void GIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-    GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
-}
-
-void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
-{
-    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDICFR[IRQn / 16]);
-    int  bit_shift = (IRQn % 16)<<1;
-    uint8_t save_byte;
-
-    field += (bit_shift / 8);
-    bit_shift %= 8;
-
-    save_byte = *field;
-    save_byte &= ((uint8_t)~(3u << bit_shift));
-
-    *field = save_byte | ((uint8_t)((edge_level<<1) | model)<< bit_shift);
-}
-
-void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
-    field += (IRQn % 4);
-    *field = (uint8_t)priority;
-}
-
-uint32_t GIC_GetPriority(IRQn_Type IRQn)
-{
-    volatile uint8_t* field = (volatile uint8_t*)&(GICDistributor->ICDIPR[IRQn / 4]);
-    field += (IRQn % 4);
-    return (uint32_t)*field;
-}
-
-void GIC_InterfacePriorityMask(uint32_t priority)
-{
-    GICInterface->ICCPMR = priority & 0xff; //set priority mask
-}
-
-void GIC_SetBinaryPoint(uint32_t binary_point)
-{
-    GICInterface->ICCBPR = binary_point & 0x07; //set binary point
-}
-
-uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
-{
-    return (uint32_t)GICInterface->ICCBPR;
-}
-
-uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
-{
-    uint32_t pending, active;
-
-    active = ((GICDistributor->ICDABR[IRQn / 32])  >> (IRQn % 32)) & 0x1;
-    pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
-
-    return ((active<<1) | pending);
-}
-
-void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
-{
-    GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) | ((target_list & 0xff) << 16) | (IRQn & 0xf);
-}
-
-void GIC_DistInit(void)
-{
-    //IRQn_Type i;
-    uint32_t i;
-    uint32_t num_irq = 0;
-    uint32_t priority_field;
-
-    //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
-    //configuring all of the interrupts as Secure.
-
-    //Disable interrupt forwarding
-    GIC_DisableDistributor();
-    //Get the maximum number of interrupts that the GIC supports
-    num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
-
-    /* Priority level is implementation defined.
-     To determine the number of priority bits implemented write 0xFF to an ICDIPR
-     priority field and read back the value stored.*/
-    GIC_SetPriority((IRQn_Type)0, 0xff);
-    priority_field = GIC_GetPriority((IRQn_Type)0);
-
-    for (i = 32; i < num_irq; i++)
-    {
-        //Disable all SPI the interrupts
-        GIC_DisableIRQ((IRQn_Type)i);
-        //Set level-sensitive and N-N model
-        //GIC_SetLevelModel(i, 0, 0);
-        //Set priority
-        GIC_SetPriority((IRQn_Type)i, priority_field/2);
-        //Set target list to "all cpus"
-        GIC_SetTarget((IRQn_Type)i, 0xff);
-    }
-    /* Set level-edge and 1-N model */
-    /* GICDistributor->ICDICFR[ 0] is read only */
-    GICDistributor->ICDICFR[ 1] = 0x00000055;
-    GICDistributor->ICDICFR[ 2] = 0xFFFD5555;
-    GICDistributor->ICDICFR[ 3] = 0x555FFFFF;
-    GICDistributor->ICDICFR[ 4] = 0x55555555;
-    GICDistributor->ICDICFR[ 5] = 0x55555555;
-    GICDistributor->ICDICFR[ 6] = 0x55555555;
-    GICDistributor->ICDICFR[ 7] = 0x55555555;
-    GICDistributor->ICDICFR[ 8] = 0x5555F555;
-    GICDistributor->ICDICFR[ 9] = 0x55555555;
-    GICDistributor->ICDICFR[10] = 0x55555555;
-    GICDistributor->ICDICFR[11] = 0xF5555555;
-    GICDistributor->ICDICFR[12] = 0xF555F555;
-    GICDistributor->ICDICFR[13] = 0x5555F555;
-    GICDistributor->ICDICFR[14] = 0x55555555;
-    GICDistributor->ICDICFR[15] = 0x55555555;
-    GICDistributor->ICDICFR[16] = 0x55555555;
-    GICDistributor->ICDICFR[17] = 0xFD555555;
-    GICDistributor->ICDICFR[18] = 0x55555557;
-    GICDistributor->ICDICFR[19] = 0x55555555;
-    GICDistributor->ICDICFR[20] = 0xFFD55555;
-    GICDistributor->ICDICFR[21] = 0x5F55557F;
-    GICDistributor->ICDICFR[22] = 0xFD55555F;
-    GICDistributor->ICDICFR[23] = 0x55555557;
-    GICDistributor->ICDICFR[24] = 0x55555555;
-    GICDistributor->ICDICFR[25] = 0x55555555;
-    GICDistributor->ICDICFR[26] = 0x55555555;
-    GICDistributor->ICDICFR[27] = 0x55555555;
-    GICDistributor->ICDICFR[28] = 0x55555555;
-    GICDistributor->ICDICFR[29] = 0x55555555;
-    GICDistributor->ICDICFR[30] = 0x55555555;
-    GICDistributor->ICDICFR[31] = 0x55555555;
-    GICDistributor->ICDICFR[32] = 0x55555555;
-    GICDistributor->ICDICFR[33] = 0x55555555;
-
-    //Enable distributor
-    GIC_EnableDistributor();
-}
-
-void GIC_CPUInterfaceInit(void)
-{
-    IRQn_Type i;
-    uint32_t priority_field;
-
-    //A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
-    //configuring all of the interrupts as Secure.
-
-    //Disable interrupt forwarding
-    GIC_DisableInterface();
-
-    /* Priority level is implementation defined.
-     To determine the number of priority bits implemented write 0xFF to an ICDIPR
-     priority field and read back the value stored.*/
-    GIC_SetPriority((IRQn_Type)0, 0xff);
-    priority_field = GIC_GetPriority((IRQn_Type)0);
-
-    //SGI and PPI
-    for (i = (IRQn_Type)0; i < 32; i++)
-    {
-        //Set level-sensitive and N-N model for PPI
-        //if(i > 15)
-            //GIC_SetLevelModel(i, 0, 0);
-        //Disable SGI and PPI interrupts
-        GIC_DisableIRQ(i);
-        //Set priority
-        GIC_SetPriority(i, priority_field/2);
-    }
-    //Enable interface
-    GIC_EnableInterface();
-    //Set binary point to 0
-    GIC_SetBinaryPoint(0);
-    //Set priority mask
-    GIC_InterfacePriorityMask(0xff);
-}
-
-void GIC_Enable(void)
-{
-    GIC_DistInit();
-    GIC_CPUInterfaceInit(); //per CPU
-}
-

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/gic.h	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,316 +0,0 @@
-/**************************************************************************//**
- * @file     gic.h
- * @brief    Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
- * @version
- * @date     29 August 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#ifndef GIC_H_
-#define GIC_H_
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/** \brief  Structure type to access the Generic Interrupt Controller Distributor (GICD)
- */
-typedef struct
-{
-  __IO uint32_t ICDDCR;
-  __I  uint32_t ICDICTR;
-  __I  uint32_t ICDIIDR;
-       uint32_t RESERVED0[29];
-  __IO uint32_t ICDISR[32];
-  __IO uint32_t ICDISER[32];
-  __IO uint32_t ICDICER[32];
-  __IO uint32_t ICDISPR[32];
-  __IO uint32_t ICDICPR[32];
-  __I  uint32_t ICDABR[32];
-       uint32_t RESERVED1[32];
-  __IO uint32_t ICDIPR[256];
-  __IO uint32_t ICDIPTR[256];
-  __IO uint32_t ICDICFR[64];
-       uint32_t RESERVED2[128];
-  __IO uint32_t ICDSGIR;
-}  GICDistributor_Type;
-
-/** \brief  Structure type to access the Controller Interface (GICC)
- */
-typedef struct
-{
-  __IO uint32_t ICCICR;          // +0x000 - RW - CPU Interface Control Register
-  __IO uint32_t ICCPMR;          // +0x004 - RW - Interrupt Priority Mask Register
-  __IO uint32_t ICCBPR;          // +0x008 - RW - Binary Point Register
-  __I  uint32_t ICCIAR;          // +0x00C - RO - Interrupt Acknowledge Register
-  __IO uint32_t ICCEOIR;         // +0x010 - WO - End of Interrupt Register
-  __I  uint32_t ICCRPR;          // +0x014 - RO - Running Priority Register
-  __I  uint32_t ICCHPIR;         // +0x018 - RO - Highest Pending Interrupt Register
-  __IO uint32_t ICCABPR;         // +0x01C - RW - Aliased Binary Point Register
-
-       uint32_t RESERVED[55];
-
-  __I  uint32_t ICCIIDR;         // +0x0FC - RO - CPU Interface Identification Register
-}  GICInterface_Type;
-
-/*@} end of GICD */
-
-/* ##########################   GIC functions  #################################### */
-/**  \brief      Functions that manage interrupts via the GIC.
-  @{
- */
-
-/** \brief  Enable DistributorGICInterface->ICCICR |= 1; //enable interface
-
-   Enables the forwarding of pending interrupts to the CPU interfaces.
-
- */
-void GIC_EnableDistributor(void);
-
-/** \brief  Disable Distributor
-
-   Disables the forwarding of pending interrupts to the CPU interfaces.
-
- */
-void GIC_DisableDistributor(void);
-
-/** \brief  Provides information about the configuration of the GIC.
-   Provides information about the configuration of the GIC.
-   - whether the GIC implements the Security Extensions
-   - the maximum number of interrupt IDs that the GIC supports
-   - the number of CPU interfaces implemented
-   - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
-
-   \return Distributor Information.
- */
-uint32_t GIC_DistributorInfo(void);
-
-/** \brief  Distributor Implementer Identification Register.
-
-   Distributor Implementer Identification Register
-
-   \return Implementer Information.
- */
-uint32_t GIC_DistributorImplementer(void);
-
-/** \brief  Set list of processors that the interrupt is sent to if it is asserted.
-
-    The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
-    This field stores the list of processors that the interrupt is sent to if it is asserted.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]    target  CPU target
- */
-void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
-
-/** \brief  Get list of processors that the interrupt is sent to if it is asserted.
-
-    The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
-    This field stores the list of processors that the interrupt is sent to if it is asserted.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]    target  CPU target
-*/
-uint32_t GIC_GetTarget(IRQn_Type IRQn);
-
-/** \brief  Enable Interface
-
-   Enables the signalling of interrupts to the target processors.
-
- */
-void GIC_EnableInterface(void);
-
-/** \brief  Disable Interface
-
-   Disables the signalling of interrupts to the target processors.
-
- */
-void GIC_DisableInterface(void);
-
-/** \brief  Acknowledge Interrupt
-
-    The function acknowledges the highest priority pending interrupt and returns its IRQ number.
-
-    \return             Interrupt number
- */
-IRQn_Type GIC_AcknowledgePending(void);
-
-/** \brief  End Interrupt
-
-    The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
-
-    \param [in]   IRQn  Interrupt number.
- */
-void GIC_EndInterrupt(IRQn_Type IRQn);
-
-
-/** \brief  Enable Interrupt
-
-    Set-enable bit for each interrupt supported by the GIC.
-
-    \param [in]      IRQn  External interrupt number.
- */
-void GIC_EnableIRQ(IRQn_Type IRQn);
-
-/** \brief  Disable Interrupt
-
-    Clear-enable bit for each interrupt supported by the GIC.
-
-    \param [in]      IRQn  Number of the external interrupt to disable
- */
-void GIC_DisableIRQ(IRQn_Type IRQn);
-
-/** \brief  Set Pending Interrupt
-
-    Set-pending bit for each interrupt supported by the GIC.
-
-    \param [in]      IRQn  Interrupt number.
- */
-void GIC_SetPendingIRQ(IRQn_Type IRQn);
-
-/** \brief  Clear Pending Interrupt
-
-    Clear-pending bit for each interrupt supported by the GIC
-
-    \param [in]      IRQn  Number of the interrupt for clear pending
- */
-void GIC_ClearPendingIRQ(IRQn_Type IRQn);
-
-/** \brief  Int_config field for each interrupt supported by the GIC.
-
-    This field identifies whether the corresponding interrupt is:
-    (1) edge-triggered or (0) level-sensitive
-    (1) 1-N model or (0) N-N model
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in] edge_level (1) edge-triggered or (0) level-sensitive
-    \param [in] model      (1) 1-N model or (0) N-N model
- */
-void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt.
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority.
- */
-uint32_t GIC_GetPriority(IRQn_Type IRQn);
-
-/** \brief  CPU Interface Priority Mask Register
-
-    The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
-    value indicated by this field, the interface signals the interrupt to the processor.
-
-    \param [in]   Mask.
- */
-void GIC_InterfacePriorityMask(uint32_t priority);
-
-/** \brief  Set the binary point.
-
-     Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
-
-    \param [in]   Mask.
- */
-void GIC_SetBinaryPoint(uint32_t binary_point);
-
-/** \brief  Get the binary point.
-
-     Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
-
-    \return  Binary point.
- */
-uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
-
-/** \brief  Get Interrupt state.
-
-     Get the interrupt state, whether pending and/or active
-
-    \return  0 - inactive, 1 - pending, 2 - active, 3 - pending and active
- */
-uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
-
-/** \brief  Send Software Generated interrupt
-
-    Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
-GIC_InterfacePriorityMask
-    \param [in]   IRQn         The Interrupt ID of the SGI.
-    \param [in]   target_list  CPUTargetList
-    \param [in]   filter_list  TargetListFilter
- */
-void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
-
-/** \brief  API call to initialise the interrupt distributor
-
-   API call to initialise the interrupt distributor
-
- */
-void GIC_DistInit(void);
-
-/** \brief  API call to initialise the CPU interface
-
-   API call to initialise the CPU interface
-
- */
-void GIC_CPUInterfaceInit(void);
-
-/** \brief  API call to set the Interrupt Configuration Registers
-
-   API call to initialise the Interrupt Configuration Registers
-
- */
-void GIC_SetICDICFR (const uint32_t *ICDICFRn);
-
-/** \brief  API call to  Enable the GIC
-
-   API call to  Enable the GIC
-
- */
-void GIC_Enable(void);
-
-#endif /* GIC_H_ */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,922 @@
+/******************************************************************************
+ * @file     VK_RZ_A1H.h
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File 
+ * @version  V1.00
+ * @data     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __VK_RZ_A1H_H__
+#define __VK_RZ_A1H_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+/******  SGI Interrupts Numbers                 ****************************************/
+  SGI0_IRQn            =  0,
+  SGI1_IRQn            =  1,
+  SGI2_IRQn            =  2,
+  SGI3_IRQn            =  3,
+  SGI4_IRQn            =  4,
+  SGI5_IRQn            =  5,
+  SGI6_IRQn            =  6,
+  SGI7_IRQn            =  7,
+  SGI8_IRQn            =  8,
+  SGI9_IRQn            =  9,
+  SGI10_IRQn           = 10,
+  SGI11_IRQn           = 11,
+  SGI12_IRQn           = 12,
+  SGI13_IRQn           = 13,
+  SGI14_IRQn           = 14,
+  SGI15_IRQn           = 15,
+
+/******  Cortex-A9 Processor Exceptions Numbers ****************************************/
+  /* 16 - 578 */
+  PMUIRQ0_IRQn         = 16,
+  COMMRX0_IRQn         = 17,
+  COMMTX0_IRQn         = 18,
+  CTIIRQ0_IRQn         = 19,
+
+  IRQ0_IRQn            = 32,
+  IRQ1_IRQn            = 33,
+  IRQ2_IRQn            = 34,
+  IRQ3_IRQn            = 35,
+  IRQ4_IRQn            = 36,
+  IRQ5_IRQn            = 37,
+  IRQ6_IRQn            = 38,
+  IRQ7_IRQn            = 39,
+
+  PL310ERR_IRQn        = 40,
+
+  DMAINT0_IRQn         = 41,        /*!< DMAC Interrupt         */
+  DMAINT1_IRQn         = 42,        /*!< DMAC Interrupt         */
+  DMAINT2_IRQn         = 43,        /*!< DMAC Interrupt         */
+  DMAINT3_IRQn         = 44,        /*!< DMAC Interrupt         */
+  DMAINT4_IRQn         = 45,        /*!< DMAC Interrupt         */
+  DMAINT5_IRQn         = 46,        /*!< DMAC Interrupt         */
+  DMAINT6_IRQn         = 47,        /*!< DMAC Interrupt         */
+  DMAINT7_IRQn         = 48,        /*!< DMAC Interrupt         */
+  DMAINT8_IRQn         = 49,        /*!< DMAC Interrupt         */
+  DMAINT9_IRQn         = 50,        /*!< DMAC Interrupt         */
+  DMAINT10_IRQn        = 51,        /*!< DMAC Interrupt         */
+  DMAINT11_IRQn        = 52,        /*!< DMAC Interrupt         */
+  DMAINT12_IRQn        = 53,        /*!< DMAC Interrupt         */
+  DMAINT13_IRQn        = 54,        /*!< DMAC Interrupt         */
+  DMAINT14_IRQn        = 55,        /*!< DMAC Interrupt         */
+  DMAINT15_IRQn        = 56,        /*!< DMAC Interrupt         */
+  DMAERR_IRQn          = 57,        /*!< DMAC Interrupt         */
+
+  /* 58-72 Reserved */
+
+  USBI0_IRQn           = 73,
+  USBI1_IRQn           = 74,
+
+  S0_VI_VSYNC0_IRQn    = 75,
+  S0_LO_VSYNC0_IRQn    = 76,
+  S0_VSYNCERR0_IRQn    = 77,
+  GR3_VLINE0_IRQn      = 78,
+  S0_VFIELD0_IRQn      = 79,
+  IV1_VBUFERR0_IRQn    = 80,
+  IV3_VBUFERR0_IRQn    = 81,
+  IV5_VBUFERR0_IRQn    = 82,
+  IV6_VBUFERR0_IRQn    = 83,
+  S0_WLINE0_IRQn       = 84,
+  S1_VI_VSYNC0_IRQn    = 85,
+  S1_LO_VSYNC0_IRQn    = 86,
+  S1_VSYNCERR0_IRQn    = 87,
+  S1_VFIELD0_IRQn      = 88,
+  IV2_VBUFERR0_IRQn    = 89,
+  IV4_VBUFERR0_IRQn    = 90,
+  S1_WLINE0_IRQn       = 91,
+  OIR_VI_VSYNC0_IRQn   = 92,
+  OIR_LO_VSYNC0_IRQn   = 93,
+  OIR_VSYNCERR0_IRQn   = 94,
+  OIR_VFIELD0_IRQn     = 95,
+  IV7_VBUFERR0_IRQn    = 96,
+  IV8_VBUFERR0_IRQn    = 97,
+  /* 98 Reserved */
+  S0_VI_VSYNC1_IRQn    = 99,
+  S0_LO_VSYNC1_IRQn    = 100,
+  S0_VSYNCERR1_IRQn    = 101,
+  GR3_VLINE1_IRQn      = 102,
+  S0_VFIELD1_IRQn      = 103,
+  IV1_VBUFERR1_IRQn    = 104,
+  IV3_VBUFERR1_IRQn    = 105,
+  IV5_VBUFERR1_IRQn    = 106,
+  IV6_VBUFERR1_IRQn    = 107,
+  S0_WLINE1_IRQn       = 108,
+  S1_VI_VSYNC1_IRQn    = 109,
+  S1_LO_VSYNC1_IRQn    = 110,
+  S1_VSYNCERR1_IRQn    = 111,
+  S1_VFIELD1_IRQn      = 112,
+  IV2_VBUFERR1_IRQn    = 113,
+  IV4_VBUFERR1_IRQn    = 114,
+  S1_WLINE1_IRQn       = 115,
+  OIR_VI_VSYNC1_IRQn   = 116,
+  OIR_LO_VSYNC1_IRQn   = 117,
+  OIR_VSYNCERR1_IRQn   = 118,
+  OIR_VFIELD1_IRQn     = 119,
+  IV7_VBUFERR1_IRQn    = 120,
+  IV8_VBUFERR1_IRQn    = 121,
+  /* Reserved = 122 */
+
+  IMRDI_IRQn           = 123,
+  IMR2I0_IRQn          = 124,
+  IMR2I1_IRQn          = 125,
+
+  JEDI_IRQn            = 126,
+  JDTI_IRQn            = 127,
+
+  CMP0_IRQn            = 128,
+  CMP1_IRQn            = 129,
+
+  INT0_IRQn            = 130,
+  INT1_IRQn            = 131,
+  INT2_IRQn            = 132,
+  INT3_IRQn            = 133,
+
+  OSTMI0TINT_IRQn      = 134,       /*!< OSTM Interrupt         */
+  OSTMI1TINT_IRQn      = 135,       /*!< OSTM Interrupt         */
+
+  CMI_IRQn             = 136,
+  WTOUT_IRQn           = 137,
+
+  ITI_IRQn             = 138,
+
+  TGI0A_IRQn           = 139,
+  TGI0B_IRQn           = 140,
+  TGI0C_IRQn           = 141,
+  TGI0D_IRQn           = 142,
+  TGI0V_IRQn           = 143,
+  TGI0E_IRQn           = 144,
+  TGI0F_IRQn           = 145,
+  TGI1A_IRQn           = 146,
+  TGI1B_IRQn           = 147,
+  TGI1V_IRQn           = 148,
+  TGI1U_IRQn           = 149,
+  TGI2A_IRQn           = 150,
+  TGI2B_IRQn           = 151,
+  TGI2V_IRQn           = 152,
+  TGI2U_IRQn           = 153,
+  TGI3A_IRQn           = 154,
+  TGI3B_IRQn           = 155,
+  TGI3C_IRQn           = 156,
+  TGI3D_IRQn           = 157,
+  TGI3V_IRQn           = 158,
+  TGI4A_IRQn           = 159,
+  TGI4B_IRQn           = 160,
+  TGI4C_IRQn           = 161,
+  TGI4D_IRQn           = 162,
+  TGI4V_IRQn           = 163,
+
+  CMI1_IRQn            = 164,
+  CMI2_IRQn            = 165,
+
+  SGDEI0_IRQn          = 166,
+  SGDEI1_IRQn          = 167,
+  SGDEI2_IRQn          = 168,
+  SGDEI3_IRQn          = 169,
+
+  ADI_IRQn             = 170,
+  LMTI_IRQn            = 171,
+
+  SSII0_IRQn           = 172,       /*!< SSIF Interrupt         */
+  SSIRXI0_IRQn         = 173,       /*!< SSIF Interrupt         */
+  SSITXI0_IRQn         = 174,       /*!< SSIF Interrupt         */
+  SSII1_IRQn           = 175,       /*!< SSIF Interrupt         */
+  SSIRXI1_IRQn         = 176,       /*!< SSIF Interrupt         */
+  SSITXI1_IRQn         = 177,       /*!< SSIF Interrupt         */
+  SSII2_IRQn           = 178,       /*!< SSIF Interrupt         */
+  SSIRTI2_IRQn         = 179,       /*!< SSIF Interrupt         */
+  SSII3_IRQn           = 180,       /*!< SSIF Interrupt         */
+  SSIRXI3_IRQn         = 181,       /*!< SSIF Interrupt         */
+  SSITXI3_IRQn         = 182,       /*!< SSIF Interrupt         */
+  SSII4_IRQn           = 183,       /*!< SSIF Interrupt         */
+  SSIRTI4_IRQn         = 184,       /*!< SSIF Interrupt         */
+  SSII5_IRQn           = 185,       /*!< SSIF Interrupt         */
+  SSIRXI5_IRQn         = 186,       /*!< SSIF Interrupt         */
+  SSITXI5_IRQn         = 187,       /*!< SSIF Interrupt         */
+
+  SPDIFI_IRQn          = 188,
+
+  INTIICTEI0_IRQn      = 189,       /*!< RIIC Interrupt         */
+  INTIICRI0_IRQn       = 190,       /*!< RIIC Interrupt         */
+  INTIICTI0_IRQn       = 191,       /*!< RIIC Interrupt         */
+  INTIICSPI0_IRQn      = 192,       /*!< RIIC Interrupt         */
+  INTIICSTI0_IRQn      = 193,       /*!< RIIC Interrupt         */
+  INTIICNAKI0_IRQn     = 194,       /*!< RIIC Interrupt         */
+  INTIICALI0_IRQn      = 195,       /*!< RIIC Interrupt         */
+  INTIICTMOI0_IRQn     = 196,       /*!< RIIC Interrupt         */
+  INTIICTEI1_IRQn      = 197,       /*!< RIIC Interrupt         */
+  INTIICRI1_IRQn       = 198,       /*!< RIIC Interrupt         */
+  INTIICTI1_IRQn       = 199,       /*!< RIIC Interrupt         */
+  INTIICSPI1_IRQn      = 200,       /*!< RIIC Interrupt         */
+  INTIICSTI1_IRQn      = 201,       /*!< RIIC Interrupt         */
+  INTIICNAKI1_IRQn     = 202,       /*!< RIIC Interrupt         */
+  INTIICALI1_IRQn      = 203,       /*!< RIIC Interrupt         */
+  INTIICTMOI1_IRQn     = 204,       /*!< RIIC Interrupt         */
+  INTIICTEI2_IRQn      = 205,       /*!< RIIC Interrupt         */
+  INTIICRI2_IRQn       = 206,       /*!< RIIC Interrupt         */
+  INTIICTI2_IRQn       = 207,       /*!< RIIC Interrupt         */
+  INTIICSPI2_IRQn      = 208,       /*!< RIIC Interrupt         */
+  INTIICSTI2_IRQn      = 209,       /*!< RIIC Interrupt         */
+  INTIICNAKI2_IRQn     = 210,       /*!< RIIC Interrupt         */
+  INTIICALI2_IRQn      = 211,       /*!< RIIC Interrupt         */
+  INTIICTMOI2_IRQn     = 212,       /*!< RIIC Interrupt         */
+  INTIICTEI3_IRQn      = 213,       /*!< RIIC Interrupt         */
+  INTIICRI3_IRQn       = 214,       /*!< RIIC Interrupt         */
+  INTIICTI3_IRQn       = 215,       /*!< RIIC Interrupt         */
+  INTIICSPI3_IRQn      = 216,       /*!< RIIC Interrupt         */
+  INTIICSTI3_IRQn      = 217,       /*!< RIIC Interrupt         */
+  INTIICNAKI3_IRQn     = 218,       /*!< RIIC Interrupt         */
+  INTIICALI3_IRQn      = 219,       /*!< RIIC Interrupt         */
+  INTIICTMOI3_IRQn     = 220,       /*!< RIIC Interrupt         */
+
+  SCIFBRI0_IRQn        = 221,       /*!< SCIF Interrupt         */
+  SCIFERI0_IRQn        = 222,       /*!< SCIF Interrupt         */
+  SCIFRXI0_IRQn        = 223,       /*!< SCIF Interrupt         */
+  SCIFTXI0_IRQn        = 224,       /*!< SCIF Interrupt         */
+  SCIFBRI1_IRQn        = 225,       /*!< SCIF Interrupt         */
+  SCIFERI1_IRQn        = 226,       /*!< SCIF Interrupt         */
+  SCIFRXI1_IRQn        = 227,       /*!< SCIF Interrupt         */
+  SCIFTXI1_IRQn        = 228,       /*!< SCIF Interrupt         */
+  SCIFBRI2_IRQn        = 229,       /*!< SCIF Interrupt         */
+  SCIFERI2_IRQn        = 230,       /*!< SCIF Interrupt         */
+  SCIFRXI2_IRQn        = 231,       /*!< SCIF Interrupt         */
+  SCIFTXI2_IRQn        = 232,       /*!< SCIF Interrupt         */
+  SCIFBRI3_IRQn        = 233,       /*!< SCIF Interrupt         */
+  SCIFERI3_IRQn        = 234,       /*!< SCIF Interrupt         */
+  SCIFRXI3_IRQn        = 235,       /*!< SCIF Interrupt         */
+  SCIFTXI3_IRQn        = 236,       /*!< SCIF Interrupt         */
+  SCIFBRI4_IRQn        = 237,       /*!< SCIF Interrupt         */
+  SCIFERI4_IRQn        = 238,       /*!< SCIF Interrupt         */
+  SCIFRXI4_IRQn        = 239,       /*!< SCIF Interrupt         */
+  SCIFTXI4_IRQn        = 240,       /*!< SCIF Interrupt         */
+  SCIFBRI5_IRQn        = 241,       /*!< SCIF Interrupt         */
+  SCIFERI5_IRQn        = 242,       /*!< SCIF Interrupt         */
+  SCIFRXI5_IRQn        = 243,       /*!< SCIF Interrupt         */
+  SCIFTXI5_IRQn        = 244,       /*!< SCIF Interrupt         */
+  SCIFBRI6_IRQn        = 245,       /*!< SCIF Interrupt         */
+  SCIFERI6_IRQn        = 246,       /*!< SCIF Interrupt         */
+  SCIFRXI6_IRQn        = 247,       /*!< SCIF Interrupt         */
+  SCIFTXI6_IRQn        = 248,       /*!< SCIF Interrupt         */
+  SCIFBRI7_IRQn        = 249,       /*!< SCIF Interrupt         */
+  SCIFERI7_IRQn        = 250,       /*!< SCIF Interrupt         */
+  SCIFRXI7_IRQn        = 251,       /*!< SCIF Interrupt         */
+  SCIFTXI7_IRQn        = 252,       /*!< SCIF Interrupt         */
+
+  INTRCANGERR_IRQn     = 253,
+  INTRCANGRECC_IRQn    = 254,
+  INTRCAN0REC_IRQn     = 255,
+  INTRCAN0ERR_IRQn     = 256,
+  INTRCAN0TRX_IRQn     = 257,
+  INTRCAN1REC_IRQn     = 258,
+  INTRCAN1ERR_IRQn     = 259,
+  INTRCAN1TRX_IRQn     = 260,
+  INTRCAN2REC_IRQn     = 261,
+  INTRCAN2ERR_IRQn     = 262,
+  INTRCAN2TRX_IRQn     = 263,
+  INTRCAN3REC_IRQn     = 264,
+  INTRCAN3ERR_IRQn     = 265,
+  INTRCAN3TRX_IRQn     = 266,
+  INTRCAN4REC_IRQn     = 267,
+  INTRCAN4ERR_IRQn     = 268,
+  INTRCAN4TRX_IRQn     = 269,
+
+  RSPISPEI0_IRQn       = 270,       /*!< RSPI Interrupt         */
+  RSPISPRI0_IRQn       = 271,       /*!< RSPI Interrupt         */
+  RSPISPTI0_IRQn       = 272,       /*!< RSPI Interrupt         */
+  RSPISPEI1_IRQn       = 273,       /*!< RSPI Interrupt         */
+  RSPISPRI1_IRQn       = 274,       /*!< RSPI Interrupt         */
+  RSPISPTI1_IRQn       = 275,       /*!< RSPI Interrupt         */
+  RSPISPEI2_IRQn       = 276,       /*!< RSPI Interrupt         */
+  RSPISPRI2_IRQn       = 277,       /*!< RSPI Interrupt         */
+  RSPISPTI2_IRQn       = 278,       /*!< RSPI Interrupt         */
+  RSPISPEI3_IRQn       = 279,       /*!< RSPI Interrupt         */
+  RSPISPRI3_IRQn       = 280,       /*!< RSPI Interrupt         */
+  RSPISPTI3_IRQn       = 281,       /*!< RSPI Interrupt         */
+  RSPISPEI4_IRQn       = 282,       /*!< RSPI Interrupt         */
+  RSPISPRI4_IRQn       = 283,       /*!< RSPI Interrupt         */
+  RSPISPTI4_IRQn       = 284,       /*!< RSPI Interrupt         */
+
+  IEBBTD_IRQn          = 285,
+  IEBBTERR_IRQn        = 286,
+  IEBBTSTA_IRQn        = 287,
+  IEBBTV_IRQn          = 288,
+
+  ISY_IRQn             = 289,
+  IERR_IRQn            = 290,
+  ITARG_IRQn           = 291,
+  ISEC_IRQn            = 292,
+  IBUF_IRQn            = 293,
+  IREADY_IRQn          = 294,
+
+  STERB_IRQn           = 295,
+  FLTENDI_IRQn         = 296,
+  FLTREQ0I_IRQn        = 297,
+  FLTREQ1I_IRQn        = 298,
+
+  MMC0_IRQn            = 299,
+  MMC1_IRQn            = 300,
+  MMC2_IRQn            = 301,
+
+  SCHI0_3_IRQn         = 302,
+  SDHI0_0_IRQn         = 303,
+  SDHI0_1_IRQn         = 304,
+  SCHI1_3_IRQn         = 305,
+  SDHI1_0_IRQn         = 306,
+  SDHI1_1_IRQn         = 307,
+
+  ARM_IRQn             = 308,
+  PRD_IRQn             = 309,
+  CUP_IRQn             = 310,
+
+  SCUAI0_IRQn          = 311,
+  SCUAI1_IRQn          = 312,
+  SCUFDI0_IRQn         = 313,
+  SCUFDI1_IRQn         = 314,
+  SCUFDI2_IRQn         = 315,
+  SCUFDI3_IRQn         = 316,
+  SCUFUI0_IRQn         = 317,
+  SCUFUI1_IRQn         = 318,
+  SCUFUI2_IRQn         = 319,
+  SCUFUI3_IRQn         = 320,
+  SCUDVI0_IRQn         = 321,
+  SCUDVI1_IRQn         = 322,
+  SCUDVI2_IRQn         = 323,
+  SCUDVI3_IRQn         = 324,
+
+  MLB_CINT_IRQn        = 325,
+  MLB_SINT_IRQn        = 326,
+
+  DRC10_IRQn           = 327,
+  DRC11_IRQn           = 328,
+
+  /* 329-330 Reserved  */
+
+  LINI0_INT_T_IRQn     = 331,
+  LINI0_INT_R_IRQn     = 332,
+  LINI0_INT_S_IRQn     = 333,
+  LINI0_INT_M_IRQn     = 334,
+  LINI1_INT_T_IRQn     = 335,
+  LINI1_INT_R_IRQn     = 336,
+  LINI1_INT_S_IRQn     = 337,
+  LINI1_INT_M_IRQn     = 338,
+
+  /* 339-346 Reserved */
+
+  SCIERI0_IRQn         = 347,
+  SCIRXI0_IRQn         = 348,
+  SCITXI0_IRQn         = 349,
+  SCITEI0_IRQn         = 350,
+  SCIERI1_IRQn         = 351,
+  SCIRXI1_IRQn         = 352,
+  SCITXI1_IRQn         = 353,
+  SCITEI1_IRQn         = 354,
+
+  AVBI_DATA            = 355,
+  AVBI_ERROR           = 356,
+  AVBI_MANAGE          = 357,
+  AVBI_MAC             = 358,
+
+  ETHERI_IRQn          = 359,
+
+  /* 360-363 Reserved */
+
+  CEUI_IRQn            = 364,
+
+  /* 365-380 Reserved */
+
+  H2XMLB_ERRINT_IRQn   = 381,
+  H2XIC1_ERRINT_IRQn   = 382,
+  X2HPERI1_ERRINT_IRQn = 383,
+  X2HPERR2_ERRINT_IRQn = 384,
+  X2HPERR34_ERRINT_IRQn= 385,
+  X2HPERR5_ERRINT_IRQn = 386,
+  X2HPERR67_ERRINT_IRQn= 387,
+  X2HDBGR_ERRINT_IRQn  = 388,
+  X2HBSC_ERRINT_IRQn   = 389,   
+  X2HSPI1_ERRINT_IRQn  = 390,   
+  X2HSPI2_ERRINT_IRQn  = 391,   
+  PRRI_IRQn            = 392,
+
+  IFEI0_IRQn           = 393,
+  OFFI0_IRQn           = 394,
+  PFVEI0_IRQn          = 395,
+  IFEI1_IRQn           = 396,
+  OFFI1_IRQn           = 397,
+  PFVEI1_IRQn          = 398,
+
+  /* 399-415 Reserved */
+
+  TINT0_IRQn           = 416,
+  TINT1_IRQn           = 417,
+  TINT2_IRQn           = 418,
+  TINT3_IRQn           = 419,
+  TINT4_IRQn           = 420,
+  TINT5_IRQn           = 421,
+  TINT6_IRQn           = 422,
+  TINT7_IRQn           = 423,
+  TINT8_IRQn           = 424,
+  TINT9_IRQn           = 425,
+  TINT10_IRQn          = 426,
+  TINT11_IRQn          = 427,
+  TINT12_IRQn          = 428,
+  TINT13_IRQn          = 429,
+  TINT14_IRQn          = 430,
+  TINT15_IRQn          = 431,
+  TINT16_IRQn          = 432,
+  TINT17_IRQn          = 433,
+  TINT18_IRQn          = 434,
+  TINT19_IRQn          = 435,
+  TINT20_IRQn          = 436,
+  TINT21_IRQn          = 437,
+  TINT22_IRQn          = 438,
+  TINT23_IRQn          = 439,
+  TINT24_IRQn          = 440,
+  TINT25_IRQn          = 441,
+  TINT26_IRQn          = 442,
+  TINT27_IRQn          = 443,
+  TINT28_IRQn          = 444,
+  TINT29_IRQn          = 445,
+  TINT30_IRQn          = 446,
+  TINT31_IRQn          = 447,
+  TINT32_IRQn          = 448,
+  TINT33_IRQn          = 449,
+  TINT34_IRQn          = 450,
+  TINT35_IRQn          = 451,
+  TINT36_IRQn          = 452,
+  TINT37_IRQn          = 453,
+  TINT38_IRQn          = 454,
+  TINT39_IRQn          = 455,
+  TINT40_IRQn          = 456,
+  TINT41_IRQn          = 457,
+  TINT42_IRQn          = 458,
+  TINT43_IRQn          = 459,
+  TINT44_IRQn          = 460,
+  TINT45_IRQn          = 461,
+  TINT46_IRQn          = 462,
+  TINT47_IRQn          = 463,
+  TINT48_IRQn          = 464,
+  TINT49_IRQn          = 465,
+  TINT50_IRQn          = 466,
+  TINT51_IRQn          = 467,
+  TINT52_IRQn          = 468,
+  TINT53_IRQn          = 469,
+  TINT54_IRQn          = 470,
+  TINT55_IRQn          = 471,
+  TINT56_IRQn          = 472,
+  TINT57_IRQn          = 473,
+  TINT58_IRQn          = 474,
+  TINT59_IRQn          = 475,
+  TINT60_IRQn          = 476,
+  TINT61_IRQn          = 477,
+  TINT62_IRQn          = 478,
+  TINT63_IRQn          = 479,
+  TINT64_IRQn          = 480,
+  TINT65_IRQn          = 481,
+  TINT66_IRQn          = 482,
+  TINT67_IRQn          = 483,
+  TINT68_IRQn          = 484,
+  TINT69_IRQn          = 485,
+  TINT70_IRQn          = 486,
+  TINT71_IRQn          = 487,
+  TINT72_IRQn          = 488,
+  TINT73_IRQn          = 489,
+  TINT74_IRQn          = 490,
+  TINT75_IRQn          = 491,
+  TINT76_IRQn          = 492,
+  TINT77_IRQn          = 493,
+  TINT78_IRQn          = 494,
+  TINT79_IRQn          = 495,
+  TINT80_IRQn          = 496,
+  TINT81_IRQn          = 497,
+  TINT82_IRQn          = 498,
+  TINT83_IRQn          = 499,
+  TINT84_IRQn          = 500,
+  TINT85_IRQn          = 501,
+  TINT86_IRQn          = 502,
+  TINT87_IRQn          = 503,
+  TINT88_IRQn          = 504,
+  TINT89_IRQn          = 505,
+  TINT90_IRQn          = 506,
+  TINT91_IRQn          = 507,
+  TINT92_IRQn          = 508,
+  TINT93_IRQn          = 509,
+  TINT94_IRQn          = 510,
+  TINT95_IRQn          = 511,
+  TINT96_IRQn          = 512,
+  TINT97_IRQn          = 513,
+  TINT98_IRQn          = 514,
+  TINT99_IRQn          = 515,
+  TINT100_IRQn         = 516,
+  TINT101_IRQn         = 517,
+  TINT102_IRQn         = 518,
+  TINT103_IRQn         = 519,
+  TINT104_IRQn         = 520,
+  TINT105_IRQn         = 521,
+  TINT106_IRQn         = 522,
+  TINT107_IRQn         = 523,
+  TINT108_IRQn         = 524,
+  TINT109_IRQn         = 525,
+  TINT110_IRQn         = 526,
+  TINT111_IRQn         = 527,
+  TINT112_IRQn         = 528,
+  TINT113_IRQn         = 529,
+  TINT114_IRQn         = 530,
+  TINT115_IRQn         = 531,
+  TINT116_IRQn         = 532,
+  TINT117_IRQn         = 533,
+  TINT118_IRQn         = 534,
+  TINT119_IRQn         = 535,
+  TINT120_IRQn         = 536,
+  TINT121_IRQn         = 537,
+  TINT122_IRQn         = 538,
+  TINT123_IRQn         = 539,
+  TINT124_IRQn         = 540,
+  TINT125_IRQn         = 541,
+  TINT126_IRQn         = 542,
+  TINT127_IRQn         = 543,
+  TINT128_IRQn         = 544,
+  TINT129_IRQn         = 545,
+  TINT130_IRQn         = 546,
+  TINT131_IRQn         = 547,
+  TINT132_IRQn         = 548,
+  TINT133_IRQn         = 549,
+  TINT134_IRQn         = 550,
+  TINT135_IRQn         = 551,
+  TINT136_IRQn         = 552,
+  TINT137_IRQn         = 553,
+  TINT138_IRQn         = 554,
+  TINT139_IRQn         = 555,
+  TINT140_IRQn         = 556,
+  TINT141_IRQn         = 557,
+  TINT142_IRQn         = 558,
+  TINT143_IRQn         = 559,
+  TINT144_IRQn         = 560,
+  TINT145_IRQn         = 561,
+  TINT146_IRQn         = 562,
+  TINT147_IRQn         = 563,
+  TINT148_IRQn         = 564,
+  TINT149_IRQn         = 565,
+  TINT150_IRQn         = 566,
+  TINT151_IRQn         = 567,
+  TINT152_IRQn         = 568,
+  TINT153_IRQn         = 569,
+  TINT154_IRQn         = 570,
+  TINT155_IRQn         = 571,
+  TINT156_IRQn         = 572,
+  TINT157_IRQn         = 573,
+  TINT158_IRQn         = 574,
+  TINT159_IRQn         = 575,
+  TINT160_IRQn         = 576,
+  TINT161_IRQn         = 577,
+  TINT162_IRQn         = 578,
+  TINT163_IRQn         = 579,
+  TINT164_IRQn         = 580,
+  TINT165_IRQn         = 581,
+  TINT166_IRQn         = 582,
+  TINT167_IRQn         = 583,
+  TINT168_IRQn         = 584,
+  TINT169_IRQn         = 585,
+  TINT170_IRQn         = 586
+
+} IRQn_Type;
+
+#define RZ_A1_IRQ_MAX  TINT170_IRQn
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+
+#define RZ_A1_NORFLASH_BASE0               (0x00000000UL)                        /*!< (FLASH0    ) Base Address */
+#define RZ_A1_NORFLASH_BASE1               (0x04000000UL)                        /*!< (FLASH1    ) Base Address */
+#define RZ_A1_SDRAM_BASE0                  (0x08000000UL)                        /*!< (SDRAM0    ) Base Address */
+#define RZ_A1_SDRAM_BASE1                  (0x0C000000UL)                        /*!< (SDRAM1    ) Base Address */
+#define RZ_A1_USER_AREA0                   (0x10000000UL)                        /*!< (USER0     ) Base Address */
+#define RZ_A1_USER_AREA1                   (0x14000000UL)                        /*!< (USER1     ) Base Address */
+#define RZ_A1_SPI_IO0                      (0x18000000UL)                        /*!< (SPI_IO0   ) Base Address */
+#define RZ_A1_SPI_IO1                      (0x1C000000UL)                        /*!< (SPI_IO1   ) Base Address */
+#define RZ_A1_ONCHIP_SRAM_BASE             (0x20000000UL)                        /*!< (SRAM_OC   ) Base Address */
+#define RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
+#define RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
+#define RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
+#define RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
+#define RZ_A1_GIC_DISTRIBUTOR_BASE         (0xe8201000UL)                        /*!< (GIC DIST  ) Base Address */
+#define RZ_A1_GIC_INTERFACE_BASE           (0xe8202000UL)                        /*!< (GIC CPU IF) Base Address */
+#define RZ_A1_PL310_BASE                   (0x3ffff000UL)                        /*!< (PL310     ) Base Address */
+#define RZ_A1_ONCHIP_SRAM_NC_BASE          (0x60000000UL)                        /*!< (SRAM_OC   ) Base Address */
+#define RZ_A1_PRIVATE_TIMER                (0x00000600UL + 0x82000000UL)         /*!< (PTIM      ) Base Address */
+#define GIC_DISTRIBUTOR_BASE               RZ_A1_GIC_DISTRIBUTOR_BASE
+#define GIC_INTERFACE_BASE                 RZ_A1_GIC_INTERFACE_BASE
+#define L2C_310_BASE                       RZ_A1_PL310_BASE
+#define TIMER_BASE                         RZ_A1_PRIVATE_TIMER
+
+/* --------  Configuration of the Cortex-A9 Processor and Core Peripherals  ------- */
+#define __CA_REV        0x0000U    /*!< Core revision r0p0                          */
+#define __CORTEX_A           9U    /*!< Cortex-A9 Core                              */
+#if (__FPU_PRESENT != 1)
+#undef __FPU_PRESENT
+#define __FPU_PRESENT        1U    /* FPU present                                   */
+#endif
+#define __GIC_PRESENT        1U    /* GIC present                                   */
+#define __TIM_PRESENT        0U    /* TIM present                                   */
+#define __L2C_PRESENT        1U    /* L2C present                                   */
+
+#include "core_ca.h"
+#include "nvic_wrapper.h"
+#include <system_VK_RZ_A1H.h>
+#include "iodefine.h"
+
+/******************************************************************************/
+/*                         Clock Settings                                     */
+/******************************************************************************/
+/*
+ * Clock Mode 0 settings
+ * SW1-4(MD_CLK):ON
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1035
+ *   CLKEN2    = 0b - unstable
+ *   CLKEN[1:0]=01b - Output, Low, Low
+ *   IFC[1:0]  =00b - CPU clock is 1/1 PLL clock
+ * FRQCR2=0x0001
+ *   GFC[1:0]  =01b - Graphic clock is 2/3 bus clock
+ */
+#define CM0_RENESAS_RZ_A1_CLKIN  ( 13333333u)
+#define CM0_RENESAS_RZ_A1_CLKO   ( 66666666u)
+#define CM0_RENESAS_RZ_A1_I_CLK  (400000000u)
+#define CM0_RENESAS_RZ_A1_G_CLK  (266666666u)
+#define CM0_RENESAS_RZ_A1_B_CLK  (133333333u)
+#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
+#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
+
+/*
+ * Clock Mode 1 settings
+ * SW1-4(MD_CLK):OFF
+ * SW1-5(MD_CLKS):ON
+ * FRQCR=0x1335
+ *   CLKEN2    = 0b - unstable
+ *   CLKEN[1:0]=01b - Output, Low, Low
+ *   IFC[1:0]  =11b - CPU clock is 1/3 PLL clock
+ * FRQCR2=0x0003
+ *   GFC[1:0]  =11b - graphic clock is 1/3 bus clock
+ */
+#define CM1_RENESAS_RZ_A1_CLKIN  ( 48000000u)
+#define CM1_RENESAS_RZ_A1_CLKO   ( 64000000u)
+#define CM1_RENESAS_RZ_A1_I_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_G_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_B_CLK  (128000000u)
+#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
+#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
+
+/******************************************************************************/
+/*                         CPG   Settings                                     */
+/******************************************************************************/
+#define CPG_FRQCR_SHIFT_CKOEN2  (14)
+#define CPG_FRQCR_BIT_CKOEN2    (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
+#define CPG_FRQCR_SHIFT_CKOEN0  (12)
+#define CPG_FRQCR_BITS_CKOEN0   (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
+#define CPG_FRQCR_SHIFT_IFC     (8)
+#define CPG_FRQCR_BITS_IFC      (0x3 << CPG_FRQCR_SHIFT_IFC)
+
+#define CPG_FRQCR2_SHIFT_GFC    (0)
+#define CPG_FRQCR2_BITS_GFC     (0x3 << CPG_FRQCR2_SHIFT_GFC)
+
+
+#define CPG_STBCR1_BIT_STBY     (0x80u)
+#define CPG_STBCR1_BIT_DEEP     (0x40u)
+#define CPG_STBCR2_BIT_HIZ      (0x80u)
+#define CPG_STBCR2_BIT_MSTP20   (0x01u) /* CoreSight */
+#define CPG_STBCR3_BIT_MSTP37   (0x80u) /* IEBus */
+#define CPG_STBCR3_BIT_MSTP36   (0x40u) /* IrDA */
+#define CPG_STBCR3_BIT_MSTP35   (0x20u) /* LIN0 */
+#define CPG_STBCR3_BIT_MSTP34   (0x10u) /* LIN1 */
+#define CPG_STBCR3_BIT_MSTP33   (0x08u) /* Multi-Function Timer */
+#define CPG_STBCR3_BIT_MSTP32   (0x04u) /* CAN */
+#define CPG_STBCR3_BIT_MSTP31   (0x02u) /* A/D converter (analog voltage) */
+#define CPG_STBCR3_BIT_MSTP30   (0x01u) /* Motor Control PWM Timer */
+#define CPG_STBCR4_BIT_MSTP47   (0x80u) /* SCIF0 */
+#define CPG_STBCR4_BIT_MSTP46   (0x40u) /* SCIF1 */
+#define CPG_STBCR4_BIT_MSTP45   (0x20u) /* SCIF2 */
+#define CPG_STBCR4_BIT_MSTP44   (0x10u) /* SCIF3 */
+#define CPG_STBCR4_BIT_MSTP43   (0x08u) /* SCIF4 */
+#define CPG_STBCR4_BIT_MSTP42   (0x04u) /* SCIF5 */
+#define CPG_STBCR4_BIT_MSTP41   (0x02u) /* SCIF6 */
+#define CPG_STBCR4_BIT_MSTP40   (0x01u) /* SCIF7 */
+#define CPG_STBCR5_BIT_MSTP57   (0x80u) /* SCI0 */
+#define CPG_STBCR5_BIT_MSTP56   (0x40u) /* SCI1 */
+#define CPG_STBCR5_BIT_MSTP55   (0x20u) /* Sound Generator0 */
+#define CPG_STBCR5_BIT_MSTP54   (0x10u) /* Sound Generator1 */
+#define CPG_STBCR5_BIT_MSTP53   (0x08u) /* Sound Generator2 */
+#define CPG_STBCR5_BIT_MSTP52   (0x04u) /* Sound Generator3 */
+#define CPG_STBCR5_BIT_MSTP51   (0x02u) /* OSTM0 */
+#define CPG_STBCR5_BIT_MSTP50   (0x01u) /* OSTM1 */
+#define CPG_STBCR6_BIT_MSTP67   (0x80u) /* A/D converter (clock) */
+#define CPG_STBCR6_BIT_MSTP66   (0x40u) /* Capture Engine */
+#define CPG_STBCR6_BIT_MSTP65   (0x20u) /* Display out comparison0 */
+#define CPG_STBCR6_BIT_MSTP64   (0x10u) /* Display out comparison1 */   
+#define CPG_STBCR6_BIT_MSTP63   (0x08u) /* Dynamic Range compression0 */
+#define CPG_STBCR6_BIT_MSTP62   (0x04u) /* Dynamic Range compression1 */
+#define CPG_STBCR6_BIT_MSTP61   (0x02u) /* JPEG Decoder */
+#define CPG_STBCR6_BIT_MSTP60   (0x01u) /* Realtime Clock */
+#define CPG_STBCR7_BIT_MSTP77   (0x80u) /* Video Decoder0 */
+#define CPG_STBCR7_BIT_MSTP76   (0x40u) /* Video Decoder1 */
+#define CPG_STBCR7_BIT_MSTP74   (0x10u) /* Ethernet */
+#define CPG_STBCR7_BIT_MSTP73   (0x04u) /* NAND Flash Memory Controller */
+#define CPG_STBCR7_BIT_MSTP71   (0x02u) /* USB0 */
+#define CPG_STBCR7_BIT_MSTP70   (0x01u) /* USB1 */
+#define CPG_STBCR8_BIT_MSTP87   (0x80u) /* IMR-LS2_0 */
+#define CPG_STBCR8_BIT_MSTP86   (0x40u) /* IMR-LS2_1 */
+#define CPG_STBCR8_BIT_MSTP85   (0x20u) /* IMR-LSD */
+#define CPG_STBCR8_BIT_MSTP84   (0x10u) /* MMC Host Interface */
+#define CPG_STBCR8_BIT_MSTP83   (0x08u) /* MediaLB */
+#define CPG_STBCR8_BIT_MSTP82   (0x04u) /* EthernetAVB */
+#define CPG_STBCR8_BIT_MSTP81   (0x02u) /* SCUX */
+#define CPG_STBCR9_BIT_MSTP97   (0x80u) /* RIIC0 */
+#define CPG_STBCR9_BIT_MSTP96   (0x40u) /* RIIC1 */
+#define CPG_STBCR9_BIT_MSTP95   (0x20u) /* RIIC2 */
+#define CPG_STBCR9_BIT_MSTP94   (0x10u) /* RIIC3 */
+#define CPG_STBCR9_BIT_MSTP93   (0x08u) /* SPI Multi I/O Bus Controller0 */
+#define CPG_STBCR9_BIT_MSTP92   (0x04u) /* SPI Multi I/O Bus Controller1 */
+#define CPG_STBCR9_BIT_MSTP91   (0x02u) /* VDC5_0 */
+#define CPG_STBCR9_BIT_MSTP90   (0x01u) /* VDC5_1 */
+#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
+#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
+#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
+#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
+#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
+#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
+#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
+#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
+#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
+#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
+#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
+#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
+#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
+#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
+#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
+#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
+#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
+#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
+#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */
+#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */
+#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
+#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
+#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
+#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
+#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
+#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
+#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
+#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
+#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
+#define CPG_SYSCR1_BIT_VRAME4   (0x10u) /* VRAM E Page4 */
+#define CPG_SYSCR1_BIT_VRAME3   (0x08u) /* VRAM E Page3 */
+#define CPG_SYSCR1_BIT_VRAME2   (0x04u) /* VRAM E Page2 */
+#define CPG_SYSCR1_BIT_VRAME1   (0x02u) /* VRAM E Page1 */
+#define CPG_SYSCR1_BIT_VRAME0   (0x01u) /* VRAM E Page0 */
+#define CPG_SYSCR2_BIT_VRAMWE4  (0x10u) /* VRAM WE Page4 */
+#define CPG_SYSCR2_BIT_VRAMWE3  (0x08u) /* VRAM WE Page3 */
+#define CPG_SYSCR2_BIT_VRAMWE2  (0x04u) /* VRAM WE Page2 */
+#define CPG_SYSCR2_BIT_VRAMWE1  (0x02u) /* VRAM WE Page1 */
+#define CPG_SYSCR2_BIT_VRAMWE0  (0x01u) /* VRAM WE Page0 */
+#define CPG_SYSCR3_BIT_RRAMWE3  (0x08u) /* RRAM WE Page3 */
+#define CPG_SYSCR3_BIT_RRAMWE2  (0x04u) /* RRAM WE Page2 */
+#define CPG_SYSCR3_BIT_RRAMWE1  (0x02u) /* RRAM WE Page1 */
+#define CPG_SYSCR3_BIT_RRAMWE0  (0x01u) /* RRAM WE Page0 */
+#define CPG_CPUSTS_BIT_ISBUSY   (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */
+#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */
+#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */
+#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */
+#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */
+#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */
+#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */
+#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */
+#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */
+#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */
+#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */
+#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */
+#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */
+#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */
+#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */
+#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */
+#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */
+#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */
+#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */
+#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */
+#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */
+#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */
+#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */
+#define CPG_RRAMKP_BIT_RRAMKP3  (0x08u) /* RRAM KP Page3 */
+#define CPG_RRAMKP_BIT_RRAMKP2  (0x04u) /* RRAM KP Page2 */
+#define CPG_RRAMKP_BIT_RRAMKP1  (0x02u) /* RRAM KP Page1 */
+#define CPG_RRAMKP_BIT_RRAMKP0  (0x01u) /* RRAM KP Page0 */
+#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */
+#define CPG_DSCTR_BIT_RAMBOOT   (0x40u) /* Selection of Method after Returning from Deep Standby Mode */
+#define CPG_DSSSR_BIT_P6_2      (0x4000u) /* P6_2 */
+#define CPG_DSSSR_BIT_P3_9      (0x2000u) /* P3_9 */
+#define CPG_DSSSR_BIT_P3_1      (0x1000u) /* P3_1 */
+#define CPG_DSSSR_BIT_P2_12     (0x0800u) /* P2_12 */
+#define CPG_DSSSR_BIT_P8_7      (0x0400u) /* P8_7 */
+#define CPG_DSSSR_BIT_P3_3      (0x0200u) /* P3_3 */
+#define CPG_DSSSR_BIT_NMI       (0x0100u) /* NMI */
+#define CPG_DSSSR_BIT_RTCAR     (0x0040u) /* RTCAR */
+#define CPG_DSSSR_BIT_P6_4      (0x0020u) /* P6_4 */
+#define CPG_DSSSR_BIT_P5_9      (0x0010u) /* P5_9 */
+#define CPG_DSSSR_BIT_P7_8      (0x0008u) /* P7_8 */
+#define CPG_DSSSR_BIT_P2_15     (0x0004u) /* P2_15 */
+#define CPG_DSSSR_BIT_P9_1      (0x0002u) /* P9_1 */
+#define CPG_DSSSR_BIT_P8_2      (0x0001u) /* P8_2 */
+#define CPG_DSESR_BIT_P6_2E     (0x4000u) /* P6_2 */
+#define CPG_DSESR_BIT_P3_9E     (0x2000u) /* P3_9 */
+#define CPG_DSESR_BIT_P3_1E     (0x1000u) /* P3_1 */
+#define CPG_DSESR_BIT_P2_12E    (0x0800u) /* P2_12 */
+#define CPG_DSESR_BIT_P8_7E     (0x0400u) /* P8_7 */
+#define CPG_DSESR_BIT_P3_3E     (0x0200u) /* P3_3 */
+#define CPG_DSESR_BIT_NMIE      (0x0100u) /* NMI */
+#define CPG_DSESR_BIT_P6_4E     (0x0020u) /* P6_4 */
+#define CPG_DSESR_BIT_P5_9E     (0x0010u) /* P5_9 */
+#define CPG_DSESR_BIT_P7_8E     (0x0008u) /* P7_8 */
+#define CPG_DSESR_BIT_P2_15E    (0x0004u) /* P2_15 */
+#define CPG_DSESR_BIT_P9_1E     (0x0002u) /* P9_1 */
+#define CPG_DSESR_BIT_P8_2E     (0x0001u) /* P8_2 */
+#define CPG_DSFR_BIT_IOKEEP     (0x8000u) /* Release of Pin State Retention */
+#define CPG_DSFR_BIT_P6_2F      (0x4000u) /* P6_2 */
+#define CPG_DSFR_BIT_P3_9F      (0x2000u) /* P3_9 */
+#define CPG_DSFR_BIT_P3_1F      (0x1000u) /* P3_1 */
+#define CPG_DSFR_BIT_P2_12F     (0x0800u) /* P2_12 */
+#define CPG_DSFR_BIT_P8_7F      (0x0400u) /* P8_7 */
+#define CPG_DSFR_BIT_P3_3F      (0x0200u) /* P3_3 */
+#define CPG_DSFR_BIT_NMIF       (0x0100u) /* NMI */
+#define CPG_DSFR_BIT_RTCARF     (0x0040u) /* RTCAR */
+#define CPG_DSFR_BIT_P6_4F      (0x0020u) /* P6_4 */
+#define CPG_DSFR_BIT_P5_9F      (0x0010u) /* P5_9 */
+#define CPG_DSFR_BIT_P7_8F      (0x0008u) /* P7_8 */
+#define CPG_DSFR_BIT_P2_15F     (0x0004u) /* P2_15 */
+#define CPG_DSFR_BIT_P9_1F      (0x0002u) /* P9_1 */
+#define CPG_DSFR_BIT_P8_2F      (0x0001u) /* P8_2 */
+#define CPG_XTALCTR_BIT_GAIN1   (0x02u)   /* RTC_X3, RTC_X4 */
+#define CPG_XTALCTR_BIT_GAIN0   (0x01u)   /* EXTAL, XTAL */
+
+/******************************************************************************/
+/*                        GPIO   Settings                                     */
+/******************************************************************************/
+#define GPIO_BIT_N0  (1u <<  0)
+#define GPIO_BIT_N1  (1u <<  1)
+#define GPIO_BIT_N2  (1u <<  2)
+#define GPIO_BIT_N3  (1u <<  3)
+#define GPIO_BIT_N4  (1u <<  4)
+#define GPIO_BIT_N5  (1u <<  5)
+#define GPIO_BIT_N6  (1u <<  6)
+#define GPIO_BIT_N7  (1u <<  7)
+#define GPIO_BIT_N8  (1u <<  8)
+#define GPIO_BIT_N9  (1u <<  9)
+#define GPIO_BIT_N10 (1u << 10)
+#define GPIO_BIT_N11 (1u << 11)
+#define GPIO_BIT_N12 (1u << 12)
+#define GPIO_BIT_N13 (1u << 13)
+#define GPIO_BIT_N14 (1u << 14)
+#define GPIO_BIT_N15 (1u << 15)
+
+#define MD_BOOT10_MASK    (0x3)
+
+#define MD_BOOT10_BM0     (0x0)
+#define MD_BOOT10_BM1     (0x2)
+#define MD_BOOT10_BM3     (0x1)
+#define MD_BOOT10_BM4_5   (0x3)
+
+#define MD_CLK        (1u << 2)
+#define MD_CLKS       (1u << 3)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  // __VK_RZ_A1H_H__

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,119 +18,56 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
-#ifndef R7S72100_IODEFINE_H
-#define R7S72100_IODEFINE_H
-#define IODEFINE_H_VERSION  100
-
-enum iodefine_byte_select_t
-{
-    L = 0, H = 1,
-    LL= 0, LH = 1, HL = 2, HH = 3
-};
+#ifndef R7S721000_IODEFINE_H
+#define R7S721000_IODEFINE_H
 
-/***********************************************************************
-  <<< [iodefine_reg32_t] >>> 
-- Padding : sizeof(iodefine_reg32_t) == 4
-- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
--                     &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
-- Endian : Independent (Same as CPU endian as register endian)
-- Bit-Order : Independent
-************************************************************************/
-/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
-/* ->SEC M1.10.1 : Not magic number */
-union iodefine_reg32_t
-{
-    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
-    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
-    volatile uint8_t   UINT8[4];                                /*  8-bit Access    */
-};
-/* <-SEC M1.10.1 */
-/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
-
-/***********************************************************************
-  <<< [iodefine_reg32_16_t] >>> 
-- Padding : sizeof(iodefine_reg32_16_t) == 4
-- Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
-- Endian : Independent (Same as CPU endian as register endian)
-- Bit-Order : Independent
-************************************************************************/
-/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
-/* ->SEC M1.10.1 : Not magic number */
-union iodefine_reg32_16_t
-{
-    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
-    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
-};
-/* <-SEC M1.10.1 */
-/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+#include "iodefines/iodefine_typedef.h"                         /* (V2.00h) */
 
-/***********************************************************************
-  <<< [iodefine_reg16_8_t] >>> 
-- Padding : sizeof(iodefine_reg16_8_t) == 2
-- Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
-- Endian : Independent (Same as CPU endian as register endian)
-- Bit-Order : Independent
-************************************************************************/
-/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
-/* ->SEC M1.10.1 : Not magic number */
-union iodefine_reg16_8_t
-{
-    volatile uint16_t  UINT16;                                  /*  16-bit Access   */
-    volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
-};
-/* <-SEC M1.10.1 */
-/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
-
-
-
-
-
-
-#include "adc_iodefine.h"                             /* (V1.00a) */
-#include "bsc_iodefine.h"                             /* (V1.00a) */
-#include "ceu_iodefine.h"                             /* (V1.00a) */
-#include "cpg_iodefine.h"                             /* (V1.00a) */
-#include "disc_iodefine.h"                            /* (V1.00a) */
-#include "dmac_iodefine.h"                            /* (V1.00a) */
-#include "dvdec_iodefine.h"                           /* (V1.00a) */
-#include "ether_iodefine.h"                           /* (V1.00a) */
-#include "flctl_iodefine.h"                           /* (V1.00a) */
-#include "gpio_iodefine.h"                            /* (V1.00a) */
-#include "ieb_iodefine.h"                             /* (V1.00a) */
-#include "inb_iodefine.h"                             /* (V1.00a) */
-#include "intc_iodefine.h"                            /* (V1.00a) */
-#include "irda_iodefine.h"                            /* (V1.00a) */
-#include "jcu_iodefine.h"                             /* (V1.00a) */
-#include "l2c_iodefine.h"                             /* (V1.00a) */
-#include "lin_iodefine.h"                             /* (V1.00a) */
-#include "lvds_iodefine.h"                            /* (V1.00a) */
-#include "mlb_iodefine.h"                             /* (V1.00a) */
-#include "mmc_iodefine.h"                             /* (V1.00a) */
-#include "mtu2_iodefine.h"                            /* (V1.00a) */
-#include "ostm_iodefine.h"                            /* (V1.00a) */
-#include "pfv_iodefine.h"                             /* (V1.00a) */
-#include "pwm_iodefine.h"                             /* (V1.00a) */
-#include "riic_iodefine.h"                            /* (V1.00a) */
-#include "romdec_iodefine.h"                          /* (V1.00a) */
-#include "rscan0_iodefine.h"                          /* (V1.00a) */
-#include "rspi_iodefine.h"                            /* (V1.00a) */
-#include "rtc_iodefine.h"                             /* (V1.00a) */
-#include "scif_iodefine.h"                            /* (V1.00a) */
-#include "scim_iodefine.h"                            /* (V1.00a) */
-#include "scux_iodefine.h"                            /* (V1.00a) */
-#include "sdg_iodefine.h"                             /* (V1.00a) */
-#include "spdif_iodefine.h"                           /* (V1.00a) */
-#include "spibsc_iodefine.h"                          /* (V1.00a) */
-#include "ssif_iodefine.h"                            /* (V1.00a) */
-#include "usb20_iodefine.h"                           /* (V1.00a) */
-#include "vdc5_iodefine.h"                            /* (V1.00a) */
-#include "wdt_iodefine.h"                             /* (V1.00a) */
+#include "iodefines/adc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/bsc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/ceu_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/cpg_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/disc_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/dmac_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/dvdec_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/ether_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/flctl_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/gpio_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/ieb_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/inb_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/intc_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/irda_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/jcu_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/l2c_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/lin_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/lvds_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/mlb_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/mmc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/mtu2_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/ostm_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/pfv_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/pwm_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/riic_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/romdec_iodefine.h"                          /* (V2.00h) */
+#include "iodefines/rscan0_iodefine.h"                          /* (V2.00h) */
+#include "iodefines/rspi_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/rtc_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/scif_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/scim_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/scux_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/sdg_iodefine.h"                             /* (V2.00h) */
+#include "iodefines/spdif_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/spibsc_iodefine.h"                          /* (V2.00h) */
+#include "iodefines/ssif_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/usb20_iodefine.h"                           /* (V2.00h) */
+#include "iodefines/vdc5_iodefine.h"                            /* (V2.00h) */
+#include "iodefines/wdt_iodefine.h"                             /* (V2.00h) */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/adc_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,56 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : adc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef ADC_IODEFINE_H
 #define ADC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_adc
-{                                                          /* ADC              */
+#define ADC     (*(struct st_adc     *)0xE8005800uL) /* ADC */
+
+
+#define ADCADDRA (ADC.ADDRA)
+#define ADCADDRB (ADC.ADDRB)
+#define ADCADDRC (ADC.ADDRC)
+#define ADCADDRD (ADC.ADDRD)
+#define ADCADDRE (ADC.ADDRE)
+#define ADCADDRF (ADC.ADDRF)
+#define ADCADDRG (ADC.ADDRG)
+#define ADCADDRH (ADC.ADDRH)
+#define ADCADCMPHA (ADC.ADCMPHA)
+#define ADCADCMPLA (ADC.ADCMPLA)
+#define ADCADCMPHB (ADC.ADCMPHB)
+#define ADCADCMPLB (ADC.ADCMPLB)
+#define ADCADCMPHC (ADC.ADCMPHC)
+#define ADCADCMPLC (ADC.ADCMPLC)
+#define ADCADCMPHD (ADC.ADCMPHD)
+#define ADCADCMPLD (ADC.ADCMPLD)
+#define ADCADCMPHE (ADC.ADCMPHE)
+#define ADCADCMPLE (ADC.ADCMPLE)
+#define ADCADCMPHF (ADC.ADCMPHF)
+#define ADCADCMPLF (ADC.ADCMPLF)
+#define ADCADCMPHG (ADC.ADCMPHG)
+#define ADCADCMPLG (ADC.ADCMPLG)
+#define ADCADCMPHH (ADC.ADCMPHH)
+#define ADCADCMPLH (ADC.ADCMPLH)
+#define ADCADCSR (ADC.ADCSR)
+#define ADCADCMPER (ADC.ADCMPER)
+#define ADCADCMPSR (ADC.ADCMPSR)
+
+
+typedef struct st_adc
+{
+                                                           /* ADC              */
     volatile uint16_t ADDRA;                                  /*  ADDRA           */
     volatile uint16_t ADDRB;                                  /*  ADDRB           */
     volatile uint16_t ADDRC;                                  /*  ADDRC           */
@@ -61,38 +97,11 @@
     volatile uint16_t ADCSR;                                  /*  ADCSR           */
     volatile uint16_t ADCMPER;                                /*  ADCMPER         */
     volatile uint16_t ADCMPSR;                                /*  ADCMPSR         */
-};
-
-
-#define ADC     (*(struct st_adc     *)0xE8005800uL) /* ADC */
+} r_io_adc_t;
 
 
-#define ADCADDRA ADC.ADDRA
-#define ADCADDRB ADC.ADDRB
-#define ADCADDRC ADC.ADDRC
-#define ADCADDRD ADC.ADDRD
-#define ADCADDRE ADC.ADDRE
-#define ADCADDRF ADC.ADDRF
-#define ADCADDRG ADC.ADDRG
-#define ADCADDRH ADC.ADDRH
-#define ADCADCMPHA ADC.ADCMPHA
-#define ADCADCMPLA ADC.ADCMPLA
-#define ADCADCMPHB ADC.ADCMPHB
-#define ADCADCMPLB ADC.ADCMPLB
-#define ADCADCMPHC ADC.ADCMPHC
-#define ADCADCMPLC ADC.ADCMPLC
-#define ADCADCMPHD ADC.ADCMPHD
-#define ADCADCMPLD ADC.ADCMPLD
-#define ADCADCMPHE ADC.ADCMPHE
-#define ADCADCMPLE ADC.ADCMPLE
-#define ADCADCMPHF ADC.ADCMPHF
-#define ADCADCMPLF ADC.ADCMPLF
-#define ADCADCMPHG ADC.ADCMPHG
-#define ADCADCMPLG ADC.ADCMPLG
-#define ADCADCMPHH ADC.ADCMPHH
-#define ADCADCMPLH ADC.ADCMPLH
-#define ADCADCSR ADC.ADCSR
-#define ADCADCMPER ADC.ADCMPER
-#define ADCADCMPSR ADC.ADCMPSR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/bsc_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,22 +18,61 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : bsc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef BSC_IODEFINE_H
 #define BSC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_bsc
-{                                                          /* BSC              */
+#define BSC     (*(struct st_bsc     *)0x3FFFC000uL) /* BSC */
+
+
+#define BSCCMNCR (BSC.CMNCR)
+#define BSCCS0BCR (BSC.CS0BCR)
+#define BSCCS1BCR (BSC.CS1BCR)
+#define BSCCS2BCR (BSC.CS2BCR)
+#define BSCCS3BCR (BSC.CS3BCR)
+#define BSCCS4BCR (BSC.CS4BCR)
+#define BSCCS5BCR (BSC.CS5BCR)
+#define BSCCS0WCR (BSC.CS0WCR)
+#define BSCCS1WCR (BSC.CS1WCR)
+#define BSCCS2WCR (BSC.CS2WCR)
+#define BSCCS3WCR (BSC.CS3WCR)
+#define BSCCS4WCR (BSC.CS4WCR)
+#define BSCCS5WCR (BSC.CS5WCR)
+#define BSCSDCR (BSC.SDCR)
+#define BSCRTCSR (BSC.RTCSR)
+#define BSCRTCNT (BSC.RTCNT)
+#define BSCRTCOR (BSC.RTCOR)
+#define BSCTOSCOR0 (BSC.TOSCOR0)
+#define BSCTOSCOR1 (BSC.TOSCOR1)
+#define BSCTOSCOR2 (BSC.TOSCOR2)
+#define BSCTOSCOR3 (BSC.TOSCOR3)
+#define BSCTOSCOR4 (BSC.TOSCOR4)
+#define BSCTOSCOR5 (BSC.TOSCOR5)
+#define BSCTOSTR (BSC.TOSTR)
+#define BSCTOENR (BSC.TOENR)
+
+#define BSC_CSnBCR_COUNT (6)
+#define BSC_CSnWCR_COUNT (6)
+#define BSC_TOSCORn_COUNT (6)
+
+
+typedef struct st_bsc
+{
+                                                           /* BSC              */
     volatile uint32_t  CMNCR;                                  /*  CMNCR           */
-#define BSC_CSnBCR_COUNT 6
+
+/* #define BSC_CSnBCR_COUNT (6) */
     volatile uint32_t  CS0BCR;                                 /*  CS0BCR          */
     volatile uint32_t  CS1BCR;                                 /*  CS1BCR          */
     volatile uint32_t  CS2BCR;                                 /*  CS2BCR          */
@@ -41,7 +80,8 @@
     volatile uint32_t  CS4BCR;                                 /*  CS4BCR          */
     volatile uint32_t  CS5BCR;                                 /*  CS5BCR          */
     volatile uint8_t   dummy4[12];                             /*                  */
-#define BSC_CSnWCR_COUNT 6
+
+/* #define BSC_CSnWCR_COUNT (6) */
     volatile uint32_t  CS0WCR;                                 /*  CS0WCR          */
     volatile uint32_t  CS1WCR;                                 /*  CS1WCR          */
     volatile uint32_t  CS2WCR;                                 /*  CS2WCR          */
@@ -54,7 +94,8 @@
     volatile uint32_t  RTCNT;                                  /*  RTCNT           */
     volatile uint32_t  RTCOR;                                  /*  RTCOR           */
     volatile uint8_t   dummy6[4];                              /*                  */
-#define BSC_TOSCORn_COUNT 6
+
+/* #define BSC_TOSCORn_COUNT (6) */
     volatile uint32_t  TOSCOR0;                                /*  TOSCOR0         */
     volatile uint32_t  TOSCOR1;                                /*  TOSCOR1         */
     volatile uint32_t  TOSCOR2;                                /*  TOSCOR2         */
@@ -64,36 +105,11 @@
     volatile uint8_t   dummy7[8];                              /*                  */
     volatile uint32_t  TOSTR;                                  /*  TOSTR           */
     volatile uint32_t  TOENR;                                  /*  TOENR           */
-};
-
-
-#define BSC     (*(struct st_bsc     *)0x3FFFC000uL) /* BSC */
+} r_io_bsc_t;
 
 
-#define BSCCMNCR BSC.CMNCR
-#define BSCCS0BCR BSC.CS0BCR
-#define BSCCS1BCR BSC.CS1BCR
-#define BSCCS2BCR BSC.CS2BCR
-#define BSCCS3BCR BSC.CS3BCR
-#define BSCCS4BCR BSC.CS4BCR
-#define BSCCS5BCR BSC.CS5BCR
-#define BSCCS0WCR BSC.CS0WCR
-#define BSCCS1WCR BSC.CS1WCR
-#define BSCCS2WCR BSC.CS2WCR
-#define BSCCS3WCR BSC.CS3WCR
-#define BSCCS4WCR BSC.CS4WCR
-#define BSCCS5WCR BSC.CS5WCR
-#define BSCSDCR BSC.SDCR
-#define BSCRTCSR BSC.RTCSR
-#define BSCRTCNT BSC.RTCNT
-#define BSCRTCOR BSC.RTCOR
-#define BSCTOSCOR0 BSC.TOSCOR0
-#define BSCTOSCOR1 BSC.TOSCOR1
-#define BSCTOSCOR2 BSC.TOSCOR2
-#define BSCTOSCOR3 BSC.TOSCOR3
-#define BSCTOSCOR4 BSC.TOSCOR4
-#define BSCTOSCOR5 BSC.TOSCOR5
-#define BSCTOSTR BSC.TOSTR
-#define BSCTOENR BSC.TOENR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ceu_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,108 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : ceu_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef CEU_IODEFINE_H
 #define CEU_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_ceu
-{                                                          /* CEU              */
+#define CEU     (*(struct st_ceu     *)0xE8210000uL) /* CEU */
+
+
+/* Start of channel array defines of CEU */
+
+/* Channel array defines of CEUn */
+/*(Sample) value = CEUn[ channel ]->CAMOR; */
+#define CEUn_COUNT  (3)
+#define CEUn_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    (volatile struct st_ceu_n*)&CEU_A, \
+    (volatile struct st_ceu_n*)&CEU_B, \
+    (volatile struct st_ceu_n*)&CEU_M \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CEU_A   (*(struct st_ceu_n *)&CEU.CAPSR)                 /* CEU_A */
+#define CEU_B   (*(struct st_ceu_n *)&CEU.dummy3111)             /* CEU_B */
+#define CEU_M   (*(struct st_ceu_n *)&CEU.dummy3151)             /* CEU_M */
+
+/* End of channel array defines of CEU */
+
+
+#define CEUCAPSR (CEU.CAPSR)
+#define CEUCAPCR (CEU.CAPCR)
+#define CEUCAMCR (CEU.CAMCR)
+#define CEUCMCYR (CEU.CMCYR)
+#define CEUCAMOR_A (CEU.CAMOR_A)
+#define CEUCAPWR_A (CEU.CAPWR_A)
+#define CEUCAIFR (CEU.CAIFR)
+#define CEUCRCNTR (CEU.CRCNTR)
+#define CEUCRCMPR (CEU.CRCMPR)
+#define CEUCFLCR_A (CEU.CFLCR_A)
+#define CEUCFSZR_A (CEU.CFSZR_A)
+#define CEUCDWDR_A (CEU.CDWDR_A)
+#define CEUCDAYR_A (CEU.CDAYR_A)
+#define CEUCDACR_A (CEU.CDACR_A)
+#define CEUCDBYR_A (CEU.CDBYR_A)
+#define CEUCDBCR_A (CEU.CDBCR_A)
+#define CEUCBDSR_A (CEU.CBDSR_A)
+#define CEUCFWCR (CEU.CFWCR)
+#define CEUCLFCR_A (CEU.CLFCR_A)
+#define CEUCDOCR_A (CEU.CDOCR_A)
+#define CEUCEIER (CEU.CEIER)
+#define CEUCETCR (CEU.CETCR)
+#define CEUCSTSR (CEU.CSTSR)
+#define CEUCDSSR (CEU.CDSSR)
+#define CEUCDAYR2_A (CEU.CDAYR2_A)
+#define CEUCDACR2_A (CEU.CDACR2_A)
+#define CEUCDBYR2_A (CEU.CDBYR2_A)
+#define CEUCDBCR2_A (CEU.CDBCR2_A)
+#define CEUCAMOR_B (CEU.CAMOR_B)
+#define CEUCAPWR_B (CEU.CAPWR_B)
+#define CEUCFLCR_B (CEU.CFLCR_B)
+#define CEUCFSZR_B (CEU.CFSZR_B)
+#define CEUCDWDR_B (CEU.CDWDR_B)
+#define CEUCDAYR_B (CEU.CDAYR_B)
+#define CEUCDACR_B (CEU.CDACR_B)
+#define CEUCDBYR_B (CEU.CDBYR_B)
+#define CEUCDBCR_B (CEU.CDBCR_B)
+#define CEUCBDSR_B (CEU.CBDSR_B)
+#define CEUCLFCR_B (CEU.CLFCR_B)
+#define CEUCDOCR_B (CEU.CDOCR_B)
+#define CEUCDAYR2_B (CEU.CDAYR2_B)
+#define CEUCDACR2_B (CEU.CDACR2_B)
+#define CEUCDBYR2_B (CEU.CDBYR2_B)
+#define CEUCDBCR2_B (CEU.CDBCR2_B)
+#define CEUCAMOR_M (CEU.CAMOR_M)
+#define CEUCAPWR_M (CEU.CAPWR_M)
+#define CEUCFLCR_M (CEU.CFLCR_M)
+#define CEUCFSZR_M (CEU.CFSZR_M)
+#define CEUCDWDR_M (CEU.CDWDR_M)
+#define CEUCDAYR_M (CEU.CDAYR_M)
+#define CEUCDACR_M (CEU.CDACR_M)
+#define CEUCDBYR_M (CEU.CDBYR_M)
+#define CEUCDBCR_M (CEU.CDBCR_M)
+#define CEUCBDSR_M (CEU.CBDSR_M)
+#define CEUCLFCR_M (CEU.CLFCR_M)
+#define CEUCDOCR_M (CEU.CDOCR_M)
+#define CEUCDAYR2_M (CEU.CDAYR2_M)
+#define CEUCDACR2_M (CEU.CDACR2_M)
+#define CEUCDBYR2_M (CEU.CDBYR2_M)
+#define CEUCDBCR2_M (CEU.CDBCR2_M)
+
+
+typedef struct st_ceu
+{
+                                                           /* CEU              */
+
 /* start of struct st_ceu_n */
     volatile uint32_t  CAPSR;                                  /*  CAPSR           */
     volatile uint32_t  CAPCR;                                  /*  CAPCR           */
@@ -67,8 +155,10 @@
     volatile uint32_t  CDACR2_A;                               /*  CDACR2_A        */
     volatile uint32_t  CDBYR2_A;                               /*  CDBYR2_A        */
     volatile uint32_t  CDBCR2_A;                               /*  CDBCR2_A        */
+
 /* end of struct st_ceu_n */
     volatile uint8_t   dummy3110[3936];                        /*                  */
+
 /* start of struct st_ceu_n */
     volatile uint8_t   dummy3111[4];                           /*                  */
     volatile uint8_t   dummy3112[4];                           /*                  */
@@ -104,8 +194,10 @@
     volatile uint32_t  CDACR2_B;                               /*  CDACR2_B        */
     volatile uint32_t  CDBYR2_B;                               /*  CDBYR2_B        */
     volatile uint32_t  CDBCR2_B;                               /*  CDBCR2_B        */
+
 /* end of struct st_ceu_n */
     volatile uint8_t   dummy3150[3936];                        /*                  */
+
 /* start of struct st_ceu_n */
     volatile uint8_t   dummy3151[4];                           /*                  */
     volatile uint8_t   dummy3152[4];                           /*                  */
@@ -141,12 +233,14 @@
     volatile uint32_t  CDACR2_M;                               /*  CDACR2_M        */
     volatile uint32_t  CDBYR2_M;                               /*  CDBYR2_M        */
     volatile uint32_t  CDBCR2_M;                               /*  CDBCR2_M        */
+
 /* end of struct st_ceu_n */
-};
+} r_io_ceu_t;
 
 
-struct st_ceu_n
+typedef struct st_ceu_n
 {
+ 
     volatile uint32_t  not_common1;                            /*                  */
     volatile uint32_t  not_common2;                            /*                  */
     volatile uint32_t  not_common3;                            /*                  */
@@ -181,89 +275,21 @@
     volatile uint32_t  CDACR2;                                 /*  CDACR2          */
     volatile uint32_t  CDBYR2;                                 /*  CDBYR2          */
     volatile uint32_t  CDBCR2;                                 /*  CDBCR2          */
-};
-
-
-#define CEU     (*(struct st_ceu     *)0xE8210000uL) /* CEU */
-
-
-/* Start of channnel array defines of CEU */
-
-/* Channnel array defines of CEUn */
-/*(Sample) value = CEUn[ channel ]->CAMOR; */
-#define CEUn_COUNT  3
-#define CEUn_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    (volatile struct st_ceu_n*)&CEU_A, \
-    (volatile struct st_ceu_n*)&CEU_B, \
-    (volatile struct st_ceu_n*)&CEU_M \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define CEU_A   (*(struct st_ceu_n *)&CEU.CAPSR)                 /* CEU_A */
-#define CEU_B   (*(struct st_ceu_n *)&CEU.dummy3111)             /* CEU_B */
-#define CEU_M   (*(struct st_ceu_n *)&CEU.dummy3151)             /* CEU_M */
-
-/* End of channnel array defines of CEU */
+} r_io_ceu_n_t;
 
 
-#define CEUCAPSR CEU.CAPSR
-#define CEUCAPCR CEU.CAPCR
-#define CEUCAMCR CEU.CAMCR
-#define CEUCMCYR CEU.CMCYR
-#define CEUCAMOR_A CEU.CAMOR_A
-#define CEUCAPWR_A CEU.CAPWR_A
-#define CEUCAIFR CEU.CAIFR
-#define CEUCRCNTR CEU.CRCNTR
-#define CEUCRCMPR CEU.CRCMPR
-#define CEUCFLCR_A CEU.CFLCR_A
-#define CEUCFSZR_A CEU.CFSZR_A
-#define CEUCDWDR_A CEU.CDWDR_A
-#define CEUCDAYR_A CEU.CDAYR_A
-#define CEUCDACR_A CEU.CDACR_A
-#define CEUCDBYR_A CEU.CDBYR_A
-#define CEUCDBCR_A CEU.CDBCR_A
-#define CEUCBDSR_A CEU.CBDSR_A
-#define CEUCFWCR CEU.CFWCR
-#define CEUCLFCR_A CEU.CLFCR_A
-#define CEUCDOCR_A CEU.CDOCR_A
-#define CEUCEIER CEU.CEIER
-#define CEUCETCR CEU.CETCR
-#define CEUCSTSR CEU.CSTSR
-#define CEUCDSSR CEU.CDSSR
-#define CEUCDAYR2_A CEU.CDAYR2_A
-#define CEUCDACR2_A CEU.CDACR2_A
-#define CEUCDBYR2_A CEU.CDBYR2_A
-#define CEUCDBCR2_A CEU.CDBCR2_A
-#define CEUCAMOR_B CEU.CAMOR_B
-#define CEUCAPWR_B CEU.CAPWR_B
-#define CEUCFLCR_B CEU.CFLCR_B
-#define CEUCFSZR_B CEU.CFSZR_B
-#define CEUCDWDR_B CEU.CDWDR_B
-#define CEUCDAYR_B CEU.CDAYR_B
-#define CEUCDACR_B CEU.CDACR_B
-#define CEUCDBYR_B CEU.CDBYR_B
-#define CEUCDBCR_B CEU.CDBCR_B
-#define CEUCBDSR_B CEU.CBDSR_B
-#define CEUCLFCR_B CEU.CLFCR_B
-#define CEUCDOCR_B CEU.CDOCR_B
-#define CEUCDAYR2_B CEU.CDAYR2_B
-#define CEUCDACR2_B CEU.CDACR2_B
-#define CEUCDBYR2_B CEU.CDBYR2_B
-#define CEUCDBCR2_B CEU.CDBCR2_B
-#define CEUCAMOR_M CEU.CAMOR_M
-#define CEUCAPWR_M CEU.CAPWR_M
-#define CEUCFLCR_M CEU.CFLCR_M
-#define CEUCFSZR_M CEU.CFSZR_M
-#define CEUCDWDR_M CEU.CDWDR_M
-#define CEUCDAYR_M CEU.CDAYR_M
-#define CEUCDACR_M CEU.CDACR_M
-#define CEUCDBYR_M CEU.CDBYR_M
-#define CEUCDBCR_M CEU.CDBCR_M
-#define CEUCBDSR_M CEU.CBDSR_M
-#define CEUCLFCR_M CEU.CLFCR_M
-#define CEUCDOCR_M CEU.CDOCR_M
-#define CEUCDAYR2_M CEU.CDAYR2_M
-#define CEUCDACR2_M CEU.CDACR2_M
-#define CEUCDBYR2_M CEU.CDBYR2_M
-#define CEUCDBCR2_M CEU.CDBCR2_M
+/* Channel array defines of CEUn (2)*/
+#ifdef  DECLARE_CEUn_CHANNELS
+volatile struct st_ceu_n*  CEUn[ CEUn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CEUn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CEUn_CHANNELS */
+/* End of channel array defines of CEUn (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/cpg_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,109 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : cpg_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef CPG_IODEFINE_H
 #define CPG_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_cpg
-{                                                          /* CPG              */
+#define CPG     (*(struct st_cpg     *)0xFCFE0010uL) /* CPG */
+
+
+/* Start of channel array defines of CPG */
+
+/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
+#define CPG_FROM_SWRSTCR1_ARRAY_COUNT  (3)
+#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
+#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
+#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
+
+
+/* Channel array defines of CPG_FROM_STBCR3_ARRAY */
+/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
+#define CPG_FROM_STBCR3_ARRAY_COUNT  (10)
+#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
+    &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
+#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
+#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
+#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
+#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
+#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
+#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
+#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
+#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
+#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
+
+
+/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */
+/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
+#define CPG_FROM_SYSCR1_ARRAY_COUNT  (3)
+#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
+#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
+#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
+
+/* End of channel array defines of CPG */
+
+
+#define CPGFRQCR (CPG.FRQCR)
+#define CPGFRQCR2 (CPG.FRQCR2)
+#define CPGCPUSTS (CPG.CPUSTS)
+#define CPGSTBCR1 (CPG.STBCR1)
+#define CPGSTBCR2 (CPG.STBCR2)
+#define CPGSTBREQ1 (CPG.STBREQ1)
+#define CPGSTBREQ2 (CPG.STBREQ2)
+#define CPGSTBACK1 (CPG.STBACK1)
+#define CPGSTBACK2 (CPG.STBACK2)
+#define CPGSYSCR1 (CPG.SYSCR1)
+#define CPGSYSCR2 (CPG.SYSCR2)
+#define CPGSYSCR3 (CPG.SYSCR3)
+#define CPGSTBCR3 (CPG.STBCR3)
+#define CPGSTBCR4 (CPG.STBCR4)
+#define CPGSTBCR5 (CPG.STBCR5)
+#define CPGSTBCR6 (CPG.STBCR6)
+#define CPGSTBCR7 (CPG.STBCR7)
+#define CPGSTBCR8 (CPG.STBCR8)
+#define CPGSTBCR9 (CPG.STBCR9)
+#define CPGSTBCR10 (CPG.STBCR10)
+#define CPGSTBCR11 (CPG.STBCR11)
+#define CPGSTBCR12 (CPG.STBCR12)
+#define CPGSWRSTCR1 (CPG.SWRSTCR1)
+#define CPGSWRSTCR2 (CPG.SWRSTCR2)
+#define CPGSWRSTCR3 (CPG.SWRSTCR3)
+#define CPGSTBCR13 (CPG.STBCR13)
+#define CPGRRAMKP (CPG.RRAMKP)
+#define CPGDSCTR (CPG.DSCTR)
+#define CPGDSSSR (CPG.DSSSR)
+#define CPGDSESR (CPG.DSESR)
+#define CPGDSFR (CPG.DSFR)
+#define CPGXTALCTR (CPG.XTALCTR)
+
+
+typedef struct st_cpg
+{
+                                                           /* CPG              */
     volatile uint16_t FRQCR;                                  /*  FRQCR           */
     volatile uint8_t   dummy319[2];                            /*                  */
     volatile uint16_t FRQCR2;                                 /*  FRQCR2          */
@@ -50,71 +139,103 @@
     volatile uint8_t   dummy326[3];                            /*                  */
     volatile uint8_t   STBACK2;                                /*  STBACK2         */
     volatile uint8_t   dummy327[955];                          /*                  */
+
 /* start of struct st_cpg_from_syscr1 */
     volatile uint8_t   SYSCR1;                                 /*  SYSCR1          */
     volatile uint8_t   dummy328[3];                            /*                  */
+
 /* end of struct st_cpg_from_syscr1 */
+
 /* start of struct st_cpg_from_syscr1 */
     volatile uint8_t   SYSCR2;                                 /*  SYSCR2          */
     volatile uint8_t   dummy329[3];                            /*                  */
+
 /* end of struct st_cpg_from_syscr1 */
+
 /* start of struct st_cpg_from_syscr1 */
     volatile uint8_t   SYSCR3;                                 /*  SYSCR3          */
     volatile uint8_t   dummy3300[3];                           /*                  */
+
 /* end of struct st_cpg_from_syscr1 */
     volatile uint8_t   dummy3301[20];                          /*                  */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR3;                                 /*  STBCR3          */
     volatile uint8_t   dummy331[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR4;                                 /*  STBCR4          */
     volatile uint8_t   dummy332[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR5;                                 /*  STBCR5          */
     volatile uint8_t   dummy333[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR6;                                 /*  STBCR6          */
     volatile uint8_t   dummy334[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR7;                                 /*  STBCR7          */
     volatile uint8_t   dummy335[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR8;                                 /*  STBCR8          */
     volatile uint8_t   dummy336[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR9;                                 /*  STBCR9          */
     volatile uint8_t   dummy337[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR10;                                /*  STBCR10         */
     volatile uint8_t   dummy338[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR11;                                /*  STBCR11         */
     volatile uint8_t   dummy339[3];                            /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
+
 /* start of struct st_cpg_from_stbcr3 */
     volatile uint8_t   STBCR12;                                /*  STBCR12         */
     volatile uint8_t   dummy3400[3];                           /*                  */
+
 /* end of struct st_cpg_from_stbcr3 */
     volatile uint8_t   dummy3401[24];                          /*                  */
+
 /* start of struct st_cpg_from_swrstcr1 */
     volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
     volatile uint8_t   dummy341[3];                            /*                  */
+
 /* end of struct st_cpg_from_swrstcr1 */
+
 /* start of struct st_cpg_from_swrstcr1 */
     volatile uint8_t   SWRSTCR2;                               /*  SWRSTCR2        */
     volatile uint8_t   dummy342[3];                            /*                  */
+
 /* end of struct st_cpg_from_swrstcr1 */
+
 /* start of struct st_cpg_from_swrstcr1 */
     volatile uint8_t   SWRSTCR3;                               /*  SWRSTCR3        */
     volatile uint8_t   dummy3430[3];                           /*                  */
+
 /* end of struct st_cpg_from_swrstcr1 */
     volatile uint8_t   dummy3431[4];                           /*                  */
     volatile uint8_t   STBCR13;                                /*  STBCR13         */
@@ -128,112 +249,59 @@
     volatile uint16_t DSFR;                                   /*  DSFR            */
     volatile uint8_t   dummy347[6];                            /*                  */
     volatile uint8_t   XTALCTR;                                /*  XTALCTR         */
-};
+} r_io_cpg_t;
 
 
-struct st_cpg_from_syscr1
+typedef struct st_cpg_from_syscr1
 {
+ 
     volatile uint8_t   SYSCR1;                                 /*  SYSCR1          */
     volatile uint8_t   dummy1[3];                              /*                  */
-};
-
-
-struct st_cpg_from_stbcr3
-{
-    volatile uint8_t   STBCR3;                                 /*  STBCR3          */
-    volatile uint8_t   dummy1[3];                              /*                  */
-};
+} r_io_cpg_from_syscr1_t;
 
 
-struct st_cpg_from_swrstcr1
+typedef struct st_cpg_from_stbcr3
 {
-    volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
+ 
+    volatile uint8_t   STBCR3;                                 /*  STBCR3          */
     volatile uint8_t   dummy1[3];                              /*                  */
-};
-
-
-#define CPG     (*(struct st_cpg     *)0xFCFE0010uL) /* CPG */
+} r_io_cpg_from_stbcr3_t;
 
 
-/* Start of channnel array defines of CPG */
-
-/* Channnel array defines of CPG_FROM_SWRSTCR1_ARRAY */
-/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
-#define CPG_FROM_SWRSTCR1_ARRAY_COUNT  3
-#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
-#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
-#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
+typedef struct st_cpg_from_swrstcr1
+{
+ 
+    volatile uint8_t   SWRSTCR1;                               /*  SWRSTCR1        */
+    volatile uint8_t   dummy1[3];                              /*                  */
+} r_io_cpg_from_swrstcr1_t;
 
 
-/* Channnel array defines of CPG_FROM_STBCR3_ARRAY */
-/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
-#define CPG_FROM_STBCR3_ARRAY_COUNT  10
-#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
-    &CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
-#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
-#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
-#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
-#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
-#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
-#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
-#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
-#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
-#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
+/* Channel array defines of CPG (2)*/
+#ifdef  DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS
+volatile struct st_cpg_from_swrstcr1*  CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */
 
+#ifdef  DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS
+volatile struct st_cpg_from_stbcr3*  CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */
 
-/* Channnel array defines of CPG_FROM_SYSCR1_ARRAY */
-/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
-#define CPG_FROM_SYSCR1_ARRAY_COUNT  3
-#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
-#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
-#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
-
-/* End of channnel array defines of CPG */
+#ifdef  DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS
+volatile struct st_cpg_from_syscr1*  CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */
+/* End of channel array defines of CPG (2)*/
 
 
-#define CPGFRQCR CPG.FRQCR
-#define CPGFRQCR2 CPG.FRQCR2
-#define CPGCPUSTS CPG.CPUSTS
-#define CPGSTBCR1 CPG.STBCR1
-#define CPGSTBCR2 CPG.STBCR2
-#define CPGSTBREQ1 CPG.STBREQ1
-#define CPGSTBREQ2 CPG.STBREQ2
-#define CPGSTBACK1 CPG.STBACK1
-#define CPGSTBACK2 CPG.STBACK2
-#define CPGSYSCR1 CPG.SYSCR1
-#define CPGSYSCR2 CPG.SYSCR2
-#define CPGSYSCR3 CPG.SYSCR3
-#define CPGSTBCR3 CPG.STBCR3
-#define CPGSTBCR4 CPG.STBCR4
-#define CPGSTBCR5 CPG.STBCR5
-#define CPGSTBCR6 CPG.STBCR6
-#define CPGSTBCR7 CPG.STBCR7
-#define CPGSTBCR8 CPG.STBCR8
-#define CPGSTBCR9 CPG.STBCR9
-#define CPGSTBCR10 CPG.STBCR10
-#define CPGSTBCR11 CPG.STBCR11
-#define CPGSTBCR12 CPG.STBCR12
-#define CPGSWRSTCR1 CPG.SWRSTCR1
-#define CPGSWRSTCR2 CPG.SWRSTCR2
-#define CPGSWRSTCR3 CPG.SWRSTCR3
-#define CPGSTBCR13 CPG.STBCR13
-#define CPGRRAMKP CPG.RRAMKP
-#define CPGDSCTR CPG.DSCTR
-#define CPGDSSSR CPG.DSSSR
-#define CPGDSESR CPG.DSESR
-#define CPGDSFR CPG.DSFR
-#define CPGXTALCTR CPG.XTALCTR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/disc_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,67 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : disc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef DISC_IODEFINE_H
 #define DISC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_disc
-{                                                          /* DISC             */
+#define DISC0   (*(struct st_disc    *)0xFCFFA800uL) /* DISC0 */
+#define DISC1   (*(struct st_disc    *)0xFCFFB000uL) /* DISC1 */
+
+
+/* Start of channel array defines of DISC */
+
+/* Channel array defines of DISC */
+/*(Sample) value = DISC[ channel ]->DOCMCR; */
+#define DISC_COUNT  (2)
+#define DISC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DISC0, &DISC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of DISC */
+
+
+#define DISC0DOCMCR (DISC0.DOCMCR)
+#define DISC0DOCMSTR (DISC0.DOCMSTR)
+#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR)
+#define DISC0DOCMIENR (DISC0.DOCMIENR)
+#define DISC0DOCMPMR (DISC0.DOCMPMR)
+#define DISC0DOCMECRCR (DISC0.DOCMECRCR)
+#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR)
+#define DISC0DOCMSPXR (DISC0.DOCMSPXR)
+#define DISC0DOCMSPYR (DISC0.DOCMSPYR)
+#define DISC0DOCMSZXR (DISC0.DOCMSZXR)
+#define DISC0DOCMSZYR (DISC0.DOCMSZYR)
+#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR)
+#define DISC1DOCMCR (DISC1.DOCMCR)
+#define DISC1DOCMSTR (DISC1.DOCMSTR)
+#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR)
+#define DISC1DOCMIENR (DISC1.DOCMIENR)
+#define DISC1DOCMPMR (DISC1.DOCMPMR)
+#define DISC1DOCMECRCR (DISC1.DOCMECRCR)
+#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR)
+#define DISC1DOCMSPXR (DISC1.DOCMSPXR)
+#define DISC1DOCMSPYR (DISC1.DOCMSPYR)
+#define DISC1DOCMSZXR (DISC1.DOCMSZXR)
+#define DISC1DOCMSZYR (DISC1.DOCMSZYR)
+#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR)
+
+
+typedef struct st_disc
+{
+                                                           /* DISC             */
     volatile uint32_t  DOCMCR;                                 /*  DOCMCR          */
     volatile uint32_t  DOCMSTR;                                /*  DOCMSTR         */
     volatile uint32_t  DOCMCLSTR;                              /*  DOCMCLSTR       */
@@ -45,49 +92,21 @@
     volatile uint32_t  DOCMSZXR;                               /*  DOCMSZXR        */
     volatile uint32_t  DOCMSZYR;                               /*  DOCMSZYR        */
     volatile uint32_t  DOCMCRCIR;                              /*  DOCMCRCIR       */
-};
-
-
-#define DISC0   (*(struct st_disc    *)0xFCFFA800uL) /* DISC0 */
-#define DISC1   (*(struct st_disc    *)0xFCFFB000uL) /* DISC1 */
-
-
-/* Start of channnel array defines of DISC */
-
-/* Channnel array defines of DISC */
-/*(Sample) value = DISC[ channel ]->DOCMCR; */
-#define DISC_COUNT  2
-#define DISC_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &DISC0, &DISC1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of DISC */
+} r_io_disc_t;
 
 
-#define DISC0DOCMCR DISC0.DOCMCR
-#define DISC0DOCMSTR DISC0.DOCMSTR
-#define DISC0DOCMCLSTR DISC0.DOCMCLSTR
-#define DISC0DOCMIENR DISC0.DOCMIENR
-#define DISC0DOCMPMR DISC0.DOCMPMR
-#define DISC0DOCMECRCR DISC0.DOCMECRCR
-#define DISC0DOCMCCRCR DISC0.DOCMCCRCR
-#define DISC0DOCMSPXR DISC0.DOCMSPXR
-#define DISC0DOCMSPYR DISC0.DOCMSPYR
-#define DISC0DOCMSZXR DISC0.DOCMSZXR
-#define DISC0DOCMSZYR DISC0.DOCMSZYR
-#define DISC0DOCMCRCIR DISC0.DOCMCRCIR
-#define DISC1DOCMCR DISC1.DOCMCR
-#define DISC1DOCMSTR DISC1.DOCMSTR
-#define DISC1DOCMCLSTR DISC1.DOCMCLSTR
-#define DISC1DOCMIENR DISC1.DOCMIENR
-#define DISC1DOCMPMR DISC1.DOCMPMR
-#define DISC1DOCMECRCR DISC1.DOCMECRCR
-#define DISC1DOCMCCRCR DISC1.DOCMCCRCR
-#define DISC1DOCMSPXR DISC1.DOCMSPXR
-#define DISC1DOCMSPYR DISC1.DOCMSPYR
-#define DISC1DOCMSZXR DISC1.DOCMSZXR
-#define DISC1DOCMSZYR DISC1.DOCMSZYR
-#define DISC1DOCMCRCIR DISC1.DOCMCRCIR
+/* Channel array defines of DISC (2)*/
+#ifdef  DECLARE_DISC_CHANNELS
+volatile struct st_disc*  DISC[ DISC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DISC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DISC_CHANNELS */
+/* End of channel array defines of DISC (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dmac_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,383 +18,48 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : dmac_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef DMAC_IODEFINE_H
 #define DMAC_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_dmac
-{                                                          /* DMAC             */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_0;                                 /*  N0SA_0          */
-    volatile uint32_t  N0DA_0;                                 /*  N0DA_0          */
-    volatile uint32_t  N0TB_0;                                 /*  N0TB_0          */
-    volatile uint32_t  N1SA_0;                                 /*  N1SA_0          */
-    volatile uint32_t  N1DA_0;                                 /*  N1DA_0          */
-    volatile uint32_t  N1TB_0;                                 /*  N1TB_0          */
-    volatile uint32_t  CRSA_0;                                 /*  CRSA_0          */
-    volatile uint32_t  CRDA_0;                                 /*  CRDA_0          */
-    volatile uint32_t  CRTB_0;                                 /*  CRTB_0          */
-    volatile uint32_t  CHSTAT_0;                               /*  CHSTAT_0        */
-    volatile uint32_t  CHCTRL_0;                               /*  CHCTRL_0        */
-    volatile uint32_t  CHCFG_0;                                /*  CHCFG_0         */
-    volatile uint32_t  CHITVL_0;                               /*  CHITVL_0        */
-    volatile uint32_t  CHEXT_0;                                /*  CHEXT_0         */
-    volatile uint32_t  NXLA_0;                                 /*  NXLA_0          */
-    volatile uint32_t  CRLA_0;                                 /*  CRLA_0          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_1;                                 /*  N0SA_1          */
-    volatile uint32_t  N0DA_1;                                 /*  N0DA_1          */
-    volatile uint32_t  N0TB_1;                                 /*  N0TB_1          */
-    volatile uint32_t  N1SA_1;                                 /*  N1SA_1          */
-    volatile uint32_t  N1DA_1;                                 /*  N1DA_1          */
-    volatile uint32_t  N1TB_1;                                 /*  N1TB_1          */
-    volatile uint32_t  CRSA_1;                                 /*  CRSA_1          */
-    volatile uint32_t  CRDA_1;                                 /*  CRDA_1          */
-    volatile uint32_t  CRTB_1;                                 /*  CRTB_1          */
-    volatile uint32_t  CHSTAT_1;                               /*  CHSTAT_1        */
-    volatile uint32_t  CHCTRL_1;                               /*  CHCTRL_1        */
-    volatile uint32_t  CHCFG_1;                                /*  CHCFG_1         */
-    volatile uint32_t  CHITVL_1;                               /*  CHITVL_1        */
-    volatile uint32_t  CHEXT_1;                                /*  CHEXT_1         */
-    volatile uint32_t  NXLA_1;                                 /*  NXLA_1          */
-    volatile uint32_t  CRLA_1;                                 /*  CRLA_1          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_2;                                 /*  N0SA_2          */
-    volatile uint32_t  N0DA_2;                                 /*  N0DA_2          */
-    volatile uint32_t  N0TB_2;                                 /*  N0TB_2          */
-    volatile uint32_t  N1SA_2;                                 /*  N1SA_2          */
-    volatile uint32_t  N1DA_2;                                 /*  N1DA_2          */
-    volatile uint32_t  N1TB_2;                                 /*  N1TB_2          */
-    volatile uint32_t  CRSA_2;                                 /*  CRSA_2          */
-    volatile uint32_t  CRDA_2;                                 /*  CRDA_2          */
-    volatile uint32_t  CRTB_2;                                 /*  CRTB_2          */
-    volatile uint32_t  CHSTAT_2;                               /*  CHSTAT_2        */
-    volatile uint32_t  CHCTRL_2;                               /*  CHCTRL_2        */
-    volatile uint32_t  CHCFG_2;                                /*  CHCFG_2         */
-    volatile uint32_t  CHITVL_2;                               /*  CHITVL_2        */
-    volatile uint32_t  CHEXT_2;                                /*  CHEXT_2         */
-    volatile uint32_t  NXLA_2;                                 /*  NXLA_2          */
-    volatile uint32_t  CRLA_2;                                 /*  CRLA_2          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_3;                                 /*  N0SA_3          */
-    volatile uint32_t  N0DA_3;                                 /*  N0DA_3          */
-    volatile uint32_t  N0TB_3;                                 /*  N0TB_3          */
-    volatile uint32_t  N1SA_3;                                 /*  N1SA_3          */
-    volatile uint32_t  N1DA_3;                                 /*  N1DA_3          */
-    volatile uint32_t  N1TB_3;                                 /*  N1TB_3          */
-    volatile uint32_t  CRSA_3;                                 /*  CRSA_3          */
-    volatile uint32_t  CRDA_3;                                 /*  CRDA_3          */
-    volatile uint32_t  CRTB_3;                                 /*  CRTB_3          */
-    volatile uint32_t  CHSTAT_3;                               /*  CHSTAT_3        */
-    volatile uint32_t  CHCTRL_3;                               /*  CHCTRL_3        */
-    volatile uint32_t  CHCFG_3;                                /*  CHCFG_3         */
-    volatile uint32_t  CHITVL_3;                               /*  CHITVL_3        */
-    volatile uint32_t  CHEXT_3;                                /*  CHEXT_3         */
-    volatile uint32_t  NXLA_3;                                 /*  NXLA_3          */
-    volatile uint32_t  CRLA_3;                                 /*  CRLA_3          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_4;                                 /*  N0SA_4          */
-    volatile uint32_t  N0DA_4;                                 /*  N0DA_4          */
-    volatile uint32_t  N0TB_4;                                 /*  N0TB_4          */
-    volatile uint32_t  N1SA_4;                                 /*  N1SA_4          */
-    volatile uint32_t  N1DA_4;                                 /*  N1DA_4          */
-    volatile uint32_t  N1TB_4;                                 /*  N1TB_4          */
-    volatile uint32_t  CRSA_4;                                 /*  CRSA_4          */
-    volatile uint32_t  CRDA_4;                                 /*  CRDA_4          */
-    volatile uint32_t  CRTB_4;                                 /*  CRTB_4          */
-    volatile uint32_t  CHSTAT_4;                               /*  CHSTAT_4        */
-    volatile uint32_t  CHCTRL_4;                               /*  CHCTRL_4        */
-    volatile uint32_t  CHCFG_4;                                /*  CHCFG_4         */
-    volatile uint32_t  CHITVL_4;                               /*  CHITVL_4        */
-    volatile uint32_t  CHEXT_4;                                /*  CHEXT_4         */
-    volatile uint32_t  NXLA_4;                                 /*  NXLA_4          */
-    volatile uint32_t  CRLA_4;                                 /*  CRLA_4          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_5;                                 /*  N0SA_5          */
-    volatile uint32_t  N0DA_5;                                 /*  N0DA_5          */
-    volatile uint32_t  N0TB_5;                                 /*  N0TB_5          */
-    volatile uint32_t  N1SA_5;                                 /*  N1SA_5          */
-    volatile uint32_t  N1DA_5;                                 /*  N1DA_5          */
-    volatile uint32_t  N1TB_5;                                 /*  N1TB_5          */
-    volatile uint32_t  CRSA_5;                                 /*  CRSA_5          */
-    volatile uint32_t  CRDA_5;                                 /*  CRDA_5          */
-    volatile uint32_t  CRTB_5;                                 /*  CRTB_5          */
-    volatile uint32_t  CHSTAT_5;                               /*  CHSTAT_5        */
-    volatile uint32_t  CHCTRL_5;                               /*  CHCTRL_5        */
-    volatile uint32_t  CHCFG_5;                                /*  CHCFG_5         */
-    volatile uint32_t  CHITVL_5;                               /*  CHITVL_5        */
-    volatile uint32_t  CHEXT_5;                                /*  CHEXT_5         */
-    volatile uint32_t  NXLA_5;                                 /*  NXLA_5          */
-    volatile uint32_t  CRLA_5;                                 /*  CRLA_5          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_6;                                 /*  N0SA_6          */
-    volatile uint32_t  N0DA_6;                                 /*  N0DA_6          */
-    volatile uint32_t  N0TB_6;                                 /*  N0TB_6          */
-    volatile uint32_t  N1SA_6;                                 /*  N1SA_6          */
-    volatile uint32_t  N1DA_6;                                 /*  N1DA_6          */
-    volatile uint32_t  N1TB_6;                                 /*  N1TB_6          */
-    volatile uint32_t  CRSA_6;                                 /*  CRSA_6          */
-    volatile uint32_t  CRDA_6;                                 /*  CRDA_6          */
-    volatile uint32_t  CRTB_6;                                 /*  CRTB_6          */
-    volatile uint32_t  CHSTAT_6;                               /*  CHSTAT_6        */
-    volatile uint32_t  CHCTRL_6;                               /*  CHCTRL_6        */
-    volatile uint32_t  CHCFG_6;                                /*  CHCFG_6         */
-    volatile uint32_t  CHITVL_6;                               /*  CHITVL_6        */
-    volatile uint32_t  CHEXT_6;                                /*  CHEXT_6         */
-    volatile uint32_t  NXLA_6;                                 /*  NXLA_6          */
-    volatile uint32_t  CRLA_6;                                 /*  CRLA_6          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_7;                                 /*  N0SA_7          */
-    volatile uint32_t  N0DA_7;                                 /*  N0DA_7          */
-    volatile uint32_t  N0TB_7;                                 /*  N0TB_7          */
-    volatile uint32_t  N1SA_7;                                 /*  N1SA_7          */
-    volatile uint32_t  N1DA_7;                                 /*  N1DA_7          */
-    volatile uint32_t  N1TB_7;                                 /*  N1TB_7          */
-    volatile uint32_t  CRSA_7;                                 /*  CRSA_7          */
-    volatile uint32_t  CRDA_7;                                 /*  CRDA_7          */
-    volatile uint32_t  CRTB_7;                                 /*  CRTB_7          */
-    volatile uint32_t  CHSTAT_7;                               /*  CHSTAT_7        */
-    volatile uint32_t  CHCTRL_7;                               /*  CHCTRL_7        */
-    volatile uint32_t  CHCFG_7;                                /*  CHCFG_7         */
-    volatile uint32_t  CHITVL_7;                               /*  CHITVL_7        */
-    volatile uint32_t  CHEXT_7;                                /*  CHEXT_7         */
-    volatile uint32_t  NXLA_7;                                 /*  NXLA_7          */
-    volatile uint32_t  CRLA_7;                                 /*  CRLA_7          */
-/* end of struct st_dmac_n */
-    volatile uint8_t   dummy187[256];                          /*                  */
-/* start of struct st_dmaccommon_n */
-    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
-    volatile uint8_t   dummy188[12];                           /*                  */
-    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
-    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
-    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
-    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
-    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
-/* end of struct st_dmaccommon_n */
-    volatile uint8_t   dummy189[220];                          /*                  */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_8;                                 /*  N0SA_8          */
-    volatile uint32_t  N0DA_8;                                 /*  N0DA_8          */
-    volatile uint32_t  N0TB_8;                                 /*  N0TB_8          */
-    volatile uint32_t  N1SA_8;                                 /*  N1SA_8          */
-    volatile uint32_t  N1DA_8;                                 /*  N1DA_8          */
-    volatile uint32_t  N1TB_8;                                 /*  N1TB_8          */
-    volatile uint32_t  CRSA_8;                                 /*  CRSA_8          */
-    volatile uint32_t  CRDA_8;                                 /*  CRDA_8          */
-    volatile uint32_t  CRTB_8;                                 /*  CRTB_8          */
-    volatile uint32_t  CHSTAT_8;                               /*  CHSTAT_8        */
-    volatile uint32_t  CHCTRL_8;                               /*  CHCTRL_8        */
-    volatile uint32_t  CHCFG_8;                                /*  CHCFG_8         */
-    volatile uint32_t  CHITVL_8;                               /*  CHITVL_8        */
-    volatile uint32_t  CHEXT_8;                                /*  CHEXT_8         */
-    volatile uint32_t  NXLA_8;                                 /*  NXLA_8          */
-    volatile uint32_t  CRLA_8;                                 /*  CRLA_8          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_9;                                 /*  N0SA_9          */
-    volatile uint32_t  N0DA_9;                                 /*  N0DA_9          */
-    volatile uint32_t  N0TB_9;                                 /*  N0TB_9          */
-    volatile uint32_t  N1SA_9;                                 /*  N1SA_9          */
-    volatile uint32_t  N1DA_9;                                 /*  N1DA_9          */
-    volatile uint32_t  N1TB_9;                                 /*  N1TB_9          */
-    volatile uint32_t  CRSA_9;                                 /*  CRSA_9          */
-    volatile uint32_t  CRDA_9;                                 /*  CRDA_9          */
-    volatile uint32_t  CRTB_9;                                 /*  CRTB_9          */
-    volatile uint32_t  CHSTAT_9;                               /*  CHSTAT_9        */
-    volatile uint32_t  CHCTRL_9;                               /*  CHCTRL_9        */
-    volatile uint32_t  CHCFG_9;                                /*  CHCFG_9         */
-    volatile uint32_t  CHITVL_9;                               /*  CHITVL_9        */
-    volatile uint32_t  CHEXT_9;                                /*  CHEXT_9         */
-    volatile uint32_t  NXLA_9;                                 /*  NXLA_9          */
-    volatile uint32_t  CRLA_9;                                 /*  CRLA_9          */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_10;                                /*  N0SA_10         */
-    volatile uint32_t  N0DA_10;                                /*  N0DA_10         */
-    volatile uint32_t  N0TB_10;                                /*  N0TB_10         */
-    volatile uint32_t  N1SA_10;                                /*  N1SA_10         */
-    volatile uint32_t  N1DA_10;                                /*  N1DA_10         */
-    volatile uint32_t  N1TB_10;                                /*  N1TB_10         */
-    volatile uint32_t  CRSA_10;                                /*  CRSA_10         */
-    volatile uint32_t  CRDA_10;                                /*  CRDA_10         */
-    volatile uint32_t  CRTB_10;                                /*  CRTB_10         */
-    volatile uint32_t  CHSTAT_10;                              /*  CHSTAT_10       */
-    volatile uint32_t  CHCTRL_10;                              /*  CHCTRL_10       */
-    volatile uint32_t  CHCFG_10;                               /*  CHCFG_10        */
-    volatile uint32_t  CHITVL_10;                              /*  CHITVL_10       */
-    volatile uint32_t  CHEXT_10;                               /*  CHEXT_10        */
-    volatile uint32_t  NXLA_10;                                /*  NXLA_10         */
-    volatile uint32_t  CRLA_10;                                /*  CRLA_10         */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_11;                                /*  N0SA_11         */
-    volatile uint32_t  N0DA_11;                                /*  N0DA_11         */
-    volatile uint32_t  N0TB_11;                                /*  N0TB_11         */
-    volatile uint32_t  N1SA_11;                                /*  N1SA_11         */
-    volatile uint32_t  N1DA_11;                                /*  N1DA_11         */
-    volatile uint32_t  N1TB_11;                                /*  N1TB_11         */
-    volatile uint32_t  CRSA_11;                                /*  CRSA_11         */
-    volatile uint32_t  CRDA_11;                                /*  CRDA_11         */
-    volatile uint32_t  CRTB_11;                                /*  CRTB_11         */
-    volatile uint32_t  CHSTAT_11;                              /*  CHSTAT_11       */
-    volatile uint32_t  CHCTRL_11;                              /*  CHCTRL_11       */
-    volatile uint32_t  CHCFG_11;                               /*  CHCFG_11        */
-    volatile uint32_t  CHITVL_11;                              /*  CHITVL_11       */
-    volatile uint32_t  CHEXT_11;                               /*  CHEXT_11        */
-    volatile uint32_t  NXLA_11;                                /*  NXLA_11         */
-    volatile uint32_t  CRLA_11;                                /*  CRLA_11         */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_12;                                /*  N0SA_12         */
-    volatile uint32_t  N0DA_12;                                /*  N0DA_12         */
-    volatile uint32_t  N0TB_12;                                /*  N0TB_12         */
-    volatile uint32_t  N1SA_12;                                /*  N1SA_12         */
-    volatile uint32_t  N1DA_12;                                /*  N1DA_12         */
-    volatile uint32_t  N1TB_12;                                /*  N1TB_12         */
-    volatile uint32_t  CRSA_12;                                /*  CRSA_12         */
-    volatile uint32_t  CRDA_12;                                /*  CRDA_12         */
-    volatile uint32_t  CRTB_12;                                /*  CRTB_12         */
-    volatile uint32_t  CHSTAT_12;                              /*  CHSTAT_12       */
-    volatile uint32_t  CHCTRL_12;                              /*  CHCTRL_12       */
-    volatile uint32_t  CHCFG_12;                               /*  CHCFG_12        */
-    volatile uint32_t  CHITVL_12;                              /*  CHITVL_12       */
-    volatile uint32_t  CHEXT_12;                               /*  CHEXT_12        */
-    volatile uint32_t  NXLA_12;                                /*  NXLA_12         */
-    volatile uint32_t  CRLA_12;                                /*  CRLA_12         */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_13;                                /*  N0SA_13         */
-    volatile uint32_t  N0DA_13;                                /*  N0DA_13         */
-    volatile uint32_t  N0TB_13;                                /*  N0TB_13         */
-    volatile uint32_t  N1SA_13;                                /*  N1SA_13         */
-    volatile uint32_t  N1DA_13;                                /*  N1DA_13         */
-    volatile uint32_t  N1TB_13;                                /*  N1TB_13         */
-    volatile uint32_t  CRSA_13;                                /*  CRSA_13         */
-    volatile uint32_t  CRDA_13;                                /*  CRDA_13         */
-    volatile uint32_t  CRTB_13;                                /*  CRTB_13         */
-    volatile uint32_t  CHSTAT_13;                              /*  CHSTAT_13       */
-    volatile uint32_t  CHCTRL_13;                              /*  CHCTRL_13       */
-    volatile uint32_t  CHCFG_13;                               /*  CHCFG_13        */
-    volatile uint32_t  CHITVL_13;                              /*  CHITVL_13       */
-    volatile uint32_t  CHEXT_13;                               /*  CHEXT_13        */
-    volatile uint32_t  NXLA_13;                                /*  NXLA_13         */
-    volatile uint32_t  CRLA_13;                                /*  CRLA_13         */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_14;                                /*  N0SA_14         */
-    volatile uint32_t  N0DA_14;                                /*  N0DA_14         */
-    volatile uint32_t  N0TB_14;                                /*  N0TB_14         */
-    volatile uint32_t  N1SA_14;                                /*  N1SA_14         */
-    volatile uint32_t  N1DA_14;                                /*  N1DA_14         */
-    volatile uint32_t  N1TB_14;                                /*  N1TB_14         */
-    volatile uint32_t  CRSA_14;                                /*  CRSA_14         */
-    volatile uint32_t  CRDA_14;                                /*  CRDA_14         */
-    volatile uint32_t  CRTB_14;                                /*  CRTB_14         */
-    volatile uint32_t  CHSTAT_14;                              /*  CHSTAT_14       */
-    volatile uint32_t  CHCTRL_14;                              /*  CHCTRL_14       */
-    volatile uint32_t  CHCFG_14;                               /*  CHCFG_14        */
-    volatile uint32_t  CHITVL_14;                              /*  CHITVL_14       */
-    volatile uint32_t  CHEXT_14;                               /*  CHEXT_14        */
-    volatile uint32_t  NXLA_14;                                /*  NXLA_14         */
-    volatile uint32_t  CRLA_14;                                /*  CRLA_14         */
-/* end of struct st_dmac_n */
-/* start of struct st_dmac_n */
-    volatile uint32_t  N0SA_15;                                /*  N0SA_15         */
-    volatile uint32_t  N0DA_15;                                /*  N0DA_15         */
-    volatile uint32_t  N0TB_15;                                /*  N0TB_15         */
-    volatile uint32_t  N1SA_15;                                /*  N1SA_15         */
-    volatile uint32_t  N1DA_15;                                /*  N1DA_15         */
-    volatile uint32_t  N1TB_15;                                /*  N1TB_15         */
-    volatile uint32_t  CRSA_15;                                /*  CRSA_15         */
-    volatile uint32_t  CRDA_15;                                /*  CRDA_15         */
-    volatile uint32_t  CRTB_15;                                /*  CRTB_15         */
-    volatile uint32_t  CHSTAT_15;                              /*  CHSTAT_15       */
-    volatile uint32_t  CHCTRL_15;                              /*  CHCTRL_15       */
-    volatile uint32_t  CHCFG_15;                               /*  CHCFG_15        */
-    volatile uint32_t  CHITVL_15;                              /*  CHITVL_15       */
-    volatile uint32_t  CHEXT_15;                               /*  CHEXT_15        */
-    volatile uint32_t  NXLA_15;                                /*  NXLA_15         */
-    volatile uint32_t  CRLA_15;                                /*  CRLA_15         */
-/* end of struct st_dmac_n */
-    volatile uint8_t   dummy190[256];                          /*                  */
-/* start of struct st_dmaccommon_n */
-    volatile uint32_t  DCTRL_8_15;                             /*  DCTRL_8_15      */
-    volatile uint8_t   dummy191[12];                           /*                  */
-    volatile uint32_t  DSTAT_EN_8_15;                          /*  DSTAT_EN_8_15   */
-    volatile uint32_t  DSTAT_ER_8_15;                          /*  DSTAT_ER_8_15   */
-    volatile uint32_t  DSTAT_END_8_15;                         /*  DSTAT_END_8_15  */
-    volatile uint32_t  DSTAT_TC_8_15;                          /*  DSTAT_TC_8_15   */
-    volatile uint32_t  DSTAT_SUS_8_15;                         /*  DSTAT_SUS_8_15  */
-/* end of struct st_dmaccommon_n */
-    volatile uint8_t   dummy192[350095580];                    /*                  */
-    volatile uint32_t  DMARS0;                                 /*  DMARS0          */
-    volatile uint32_t  DMARS1;                                 /*  DMARS1          */
-    volatile uint32_t  DMARS2;                                 /*  DMARS2          */
-    volatile uint32_t  DMARS3;                                 /*  DMARS3          */
-    volatile uint32_t  DMARS4;                                 /*  DMARS4          */
-    volatile uint32_t  DMARS5;                                 /*  DMARS5          */
-    volatile uint32_t  DMARS6;                                 /*  DMARS6          */
-    volatile uint32_t  DMARS7;                                 /*  DMARS7          */
-};
 
 
-struct st_dmaccommon_n
-{
-    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
-    volatile uint8_t   dummy1[12];                             /*                  */
-    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
-    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
-    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
-    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
-    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
-};
+/* Channel array defines of DMACmm */
+#define DMACmm_COUNT  (8)
+#define DMACmm_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define DMAC01    (*(struct st_dmars_mm *)&DMAC.DMARS0)  /* DMAC0-1   */
+#define DMAC23    (*(struct st_dmars_mm *)&DMAC.DMARS1)  /* DMAC2-3   */
+#define DMAC45    (*(struct st_dmars_mm *)&DMAC.DMARS2)  /* DMAC4-5   */
+#define DMAC67    (*(struct st_dmars_mm *)&DMAC.DMARS3)  /* DMAC6-7   */
+#define DMAC89    (*(struct st_dmars_mm *)&DMAC.DMARS4)  /* DMAC8-9   */
+#define DMAC1011  (*(struct st_dmars_mm *)&DMAC.DMARS5)  /* DMAC10-11 */
+#define DMAC1213  (*(struct st_dmars_mm *)&DMAC.DMARS6)  /* DMAC12-13 */
+#define DMAC1415  (*(struct st_dmars_mm *)&DMAC.DMARS7)  /* DMAC14-15 */
 
 
-struct st_dmac_n
-{
-    volatile uint32_t  N0SA_n;                                 /*  N0SA_n          */
-    volatile uint32_t  N0DA_n;                                 /*  N0DA_n          */
-    volatile uint32_t  N0TB_n;                                 /*  N0TB_n          */
-    volatile uint32_t  N1SA_n;                                 /*  N1SA_n          */
-    volatile uint32_t  N1DA_n;                                 /*  N1DA_n          */
-    volatile uint32_t  N1TB_n;                                 /*  N1TB_n          */
-    volatile uint32_t  CRSA_n;                                 /*  CRSA_n          */
-    volatile uint32_t  CRDA_n;                                 /*  CRDA_n          */
-    volatile uint32_t  CRTB_n;                                 /*  CRTB_n          */
-    volatile uint32_t  CHSTAT_n;                               /*  CHSTAT_n        */
-    volatile uint32_t  CHCTRL_n;                               /*  CHCTRL_n        */
-    volatile uint32_t  CHCFG_n;                                /*  CHCFG_n         */
-    volatile uint32_t  CHITVL_n;                               /*  CHITVL_n        */
-    volatile uint32_t  CHEXT_n;                                /*  CHEXT_n         */
-    volatile uint32_t  NXLA_n;                                 /*  NXLA_n          */
-    volatile uint32_t  CRLA_n;                                 /*  CRLA_n          */
-};
-
-
+/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
 #define DMAC    (*(struct st_dmac    *)0xE8200000uL) /* DMAC */
 
 
-/* Start of channnel array defines of DMAC */
+/* Start of channel array defines of DMAC */
 
-/* Channnel array defines of DMACn */
+/* Channel array defines of DMACn */
 /*(Sample) value = DMACn[ channel ]->N0SA_n; */
-#define DMACn_COUNT  16
+#define DMACn_COUNT  (16)
 #define DMACn_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \
@@ -418,9 +83,9 @@
 #define DMAC15  (*(struct st_dmac_n *)&DMAC.N0SA_15)             /* DMAC15 */
 
 
-/* Channnel array defines of DMACnn */
+/* Channel array defines of DMACnn */
 /*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
-#define DMACnn_COUNT  2
+#define DMACnn_COUNT  (2)
 #define DMACnn_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &DMAC07, &DMAC815 \
@@ -428,306 +93,715 @@
 #define DMAC07  (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7)     /* DMAC07 */
 #define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15)    /* DMAC815 */
 
+/* End of channel array defines of DMAC */
 
-/* Channnel array defines of DMACmm */
-/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
-struct st_dmars_mm
+
+#define DMACN0SA_0 (DMAC.N0SA_0)
+#define DMACN0DA_0 (DMAC.N0DA_0)
+#define DMACN0TB_0 (DMAC.N0TB_0)
+#define DMACN1SA_0 (DMAC.N1SA_0)
+#define DMACN1DA_0 (DMAC.N1DA_0)
+#define DMACN1TB_0 (DMAC.N1TB_0)
+#define DMACCRSA_0 (DMAC.CRSA_0)
+#define DMACCRDA_0 (DMAC.CRDA_0)
+#define DMACCRTB_0 (DMAC.CRTB_0)
+#define DMACCHSTAT_0 (DMAC.CHSTAT_0)
+#define DMACCHCTRL_0 (DMAC.CHCTRL_0)
+#define DMACCHCFG_0 (DMAC.CHCFG_0)
+#define DMACCHITVL_0 (DMAC.CHITVL_0)
+#define DMACCHEXT_0 (DMAC.CHEXT_0)
+#define DMACNXLA_0 (DMAC.NXLA_0)
+#define DMACCRLA_0 (DMAC.CRLA_0)
+#define DMACN0SA_1 (DMAC.N0SA_1)
+#define DMACN0DA_1 (DMAC.N0DA_1)
+#define DMACN0TB_1 (DMAC.N0TB_1)
+#define DMACN1SA_1 (DMAC.N1SA_1)
+#define DMACN1DA_1 (DMAC.N1DA_1)
+#define DMACN1TB_1 (DMAC.N1TB_1)
+#define DMACCRSA_1 (DMAC.CRSA_1)
+#define DMACCRDA_1 (DMAC.CRDA_1)
+#define DMACCRTB_1 (DMAC.CRTB_1)
+#define DMACCHSTAT_1 (DMAC.CHSTAT_1)
+#define DMACCHCTRL_1 (DMAC.CHCTRL_1)
+#define DMACCHCFG_1 (DMAC.CHCFG_1)
+#define DMACCHITVL_1 (DMAC.CHITVL_1)
+#define DMACCHEXT_1 (DMAC.CHEXT_1)
+#define DMACNXLA_1 (DMAC.NXLA_1)
+#define DMACCRLA_1 (DMAC.CRLA_1)
+#define DMACN0SA_2 (DMAC.N0SA_2)
+#define DMACN0DA_2 (DMAC.N0DA_2)
+#define DMACN0TB_2 (DMAC.N0TB_2)
+#define DMACN1SA_2 (DMAC.N1SA_2)
+#define DMACN1DA_2 (DMAC.N1DA_2)
+#define DMACN1TB_2 (DMAC.N1TB_2)
+#define DMACCRSA_2 (DMAC.CRSA_2)
+#define DMACCRDA_2 (DMAC.CRDA_2)
+#define DMACCRTB_2 (DMAC.CRTB_2)
+#define DMACCHSTAT_2 (DMAC.CHSTAT_2)
+#define DMACCHCTRL_2 (DMAC.CHCTRL_2)
+#define DMACCHCFG_2 (DMAC.CHCFG_2)
+#define DMACCHITVL_2 (DMAC.CHITVL_2)
+#define DMACCHEXT_2 (DMAC.CHEXT_2)
+#define DMACNXLA_2 (DMAC.NXLA_2)
+#define DMACCRLA_2 (DMAC.CRLA_2)
+#define DMACN0SA_3 (DMAC.N0SA_3)
+#define DMACN0DA_3 (DMAC.N0DA_3)
+#define DMACN0TB_3 (DMAC.N0TB_3)
+#define DMACN1SA_3 (DMAC.N1SA_3)
+#define DMACN1DA_3 (DMAC.N1DA_3)
+#define DMACN1TB_3 (DMAC.N1TB_3)
+#define DMACCRSA_3 (DMAC.CRSA_3)
+#define DMACCRDA_3 (DMAC.CRDA_3)
+#define DMACCRTB_3 (DMAC.CRTB_3)
+#define DMACCHSTAT_3 (DMAC.CHSTAT_3)
+#define DMACCHCTRL_3 (DMAC.CHCTRL_3)
+#define DMACCHCFG_3 (DMAC.CHCFG_3)
+#define DMACCHITVL_3 (DMAC.CHITVL_3)
+#define DMACCHEXT_3 (DMAC.CHEXT_3)
+#define DMACNXLA_3 (DMAC.NXLA_3)
+#define DMACCRLA_3 (DMAC.CRLA_3)
+#define DMACN0SA_4 (DMAC.N0SA_4)
+#define DMACN0DA_4 (DMAC.N0DA_4)
+#define DMACN0TB_4 (DMAC.N0TB_4)
+#define DMACN1SA_4 (DMAC.N1SA_4)
+#define DMACN1DA_4 (DMAC.N1DA_4)
+#define DMACN1TB_4 (DMAC.N1TB_4)
+#define DMACCRSA_4 (DMAC.CRSA_4)
+#define DMACCRDA_4 (DMAC.CRDA_4)
+#define DMACCRTB_4 (DMAC.CRTB_4)
+#define DMACCHSTAT_4 (DMAC.CHSTAT_4)
+#define DMACCHCTRL_4 (DMAC.CHCTRL_4)
+#define DMACCHCFG_4 (DMAC.CHCFG_4)
+#define DMACCHITVL_4 (DMAC.CHITVL_4)
+#define DMACCHEXT_4 (DMAC.CHEXT_4)
+#define DMACNXLA_4 (DMAC.NXLA_4)
+#define DMACCRLA_4 (DMAC.CRLA_4)
+#define DMACN0SA_5 (DMAC.N0SA_5)
+#define DMACN0DA_5 (DMAC.N0DA_5)
+#define DMACN0TB_5 (DMAC.N0TB_5)
+#define DMACN1SA_5 (DMAC.N1SA_5)
+#define DMACN1DA_5 (DMAC.N1DA_5)
+#define DMACN1TB_5 (DMAC.N1TB_5)
+#define DMACCRSA_5 (DMAC.CRSA_5)
+#define DMACCRDA_5 (DMAC.CRDA_5)
+#define DMACCRTB_5 (DMAC.CRTB_5)
+#define DMACCHSTAT_5 (DMAC.CHSTAT_5)
+#define DMACCHCTRL_5 (DMAC.CHCTRL_5)
+#define DMACCHCFG_5 (DMAC.CHCFG_5)
+#define DMACCHITVL_5 (DMAC.CHITVL_5)
+#define DMACCHEXT_5 (DMAC.CHEXT_5)
+#define DMACNXLA_5 (DMAC.NXLA_5)
+#define DMACCRLA_5 (DMAC.CRLA_5)
+#define DMACN0SA_6 (DMAC.N0SA_6)
+#define DMACN0DA_6 (DMAC.N0DA_6)
+#define DMACN0TB_6 (DMAC.N0TB_6)
+#define DMACN1SA_6 (DMAC.N1SA_6)
+#define DMACN1DA_6 (DMAC.N1DA_6)
+#define DMACN1TB_6 (DMAC.N1TB_6)
+#define DMACCRSA_6 (DMAC.CRSA_6)
+#define DMACCRDA_6 (DMAC.CRDA_6)
+#define DMACCRTB_6 (DMAC.CRTB_6)
+#define DMACCHSTAT_6 (DMAC.CHSTAT_6)
+#define DMACCHCTRL_6 (DMAC.CHCTRL_6)
+#define DMACCHCFG_6 (DMAC.CHCFG_6)
+#define DMACCHITVL_6 (DMAC.CHITVL_6)
+#define DMACCHEXT_6 (DMAC.CHEXT_6)
+#define DMACNXLA_6 (DMAC.NXLA_6)
+#define DMACCRLA_6 (DMAC.CRLA_6)
+#define DMACN0SA_7 (DMAC.N0SA_7)
+#define DMACN0DA_7 (DMAC.N0DA_7)
+#define DMACN0TB_7 (DMAC.N0TB_7)
+#define DMACN1SA_7 (DMAC.N1SA_7)
+#define DMACN1DA_7 (DMAC.N1DA_7)
+#define DMACN1TB_7 (DMAC.N1TB_7)
+#define DMACCRSA_7 (DMAC.CRSA_7)
+#define DMACCRDA_7 (DMAC.CRDA_7)
+#define DMACCRTB_7 (DMAC.CRTB_7)
+#define DMACCHSTAT_7 (DMAC.CHSTAT_7)
+#define DMACCHCTRL_7 (DMAC.CHCTRL_7)
+#define DMACCHCFG_7 (DMAC.CHCFG_7)
+#define DMACCHITVL_7 (DMAC.CHITVL_7)
+#define DMACCHEXT_7 (DMAC.CHEXT_7)
+#define DMACNXLA_7 (DMAC.NXLA_7)
+#define DMACCRLA_7 (DMAC.CRLA_7)
+#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7)
+#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7)
+#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7)
+#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7)
+#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7)
+#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7)
+#define DMACN0SA_8 (DMAC.N0SA_8)
+#define DMACN0DA_8 (DMAC.N0DA_8)
+#define DMACN0TB_8 (DMAC.N0TB_8)
+#define DMACN1SA_8 (DMAC.N1SA_8)
+#define DMACN1DA_8 (DMAC.N1DA_8)
+#define DMACN1TB_8 (DMAC.N1TB_8)
+#define DMACCRSA_8 (DMAC.CRSA_8)
+#define DMACCRDA_8 (DMAC.CRDA_8)
+#define DMACCRTB_8 (DMAC.CRTB_8)
+#define DMACCHSTAT_8 (DMAC.CHSTAT_8)
+#define DMACCHCTRL_8 (DMAC.CHCTRL_8)
+#define DMACCHCFG_8 (DMAC.CHCFG_8)
+#define DMACCHITVL_8 (DMAC.CHITVL_8)
+#define DMACCHEXT_8 (DMAC.CHEXT_8)
+#define DMACNXLA_8 (DMAC.NXLA_8)
+#define DMACCRLA_8 (DMAC.CRLA_8)
+#define DMACN0SA_9 (DMAC.N0SA_9)
+#define DMACN0DA_9 (DMAC.N0DA_9)
+#define DMACN0TB_9 (DMAC.N0TB_9)
+#define DMACN1SA_9 (DMAC.N1SA_9)
+#define DMACN1DA_9 (DMAC.N1DA_9)
+#define DMACN1TB_9 (DMAC.N1TB_9)
+#define DMACCRSA_9 (DMAC.CRSA_9)
+#define DMACCRDA_9 (DMAC.CRDA_9)
+#define DMACCRTB_9 (DMAC.CRTB_9)
+#define DMACCHSTAT_9 (DMAC.CHSTAT_9)
+#define DMACCHCTRL_9 (DMAC.CHCTRL_9)
+#define DMACCHCFG_9 (DMAC.CHCFG_9)
+#define DMACCHITVL_9 (DMAC.CHITVL_9)
+#define DMACCHEXT_9 (DMAC.CHEXT_9)
+#define DMACNXLA_9 (DMAC.NXLA_9)
+#define DMACCRLA_9 (DMAC.CRLA_9)
+#define DMACN0SA_10 (DMAC.N0SA_10)
+#define DMACN0DA_10 (DMAC.N0DA_10)
+#define DMACN0TB_10 (DMAC.N0TB_10)
+#define DMACN1SA_10 (DMAC.N1SA_10)
+#define DMACN1DA_10 (DMAC.N1DA_10)
+#define DMACN1TB_10 (DMAC.N1TB_10)
+#define DMACCRSA_10 (DMAC.CRSA_10)
+#define DMACCRDA_10 (DMAC.CRDA_10)
+#define DMACCRTB_10 (DMAC.CRTB_10)
+#define DMACCHSTAT_10 (DMAC.CHSTAT_10)
+#define DMACCHCTRL_10 (DMAC.CHCTRL_10)
+#define DMACCHCFG_10 (DMAC.CHCFG_10)
+#define DMACCHITVL_10 (DMAC.CHITVL_10)
+#define DMACCHEXT_10 (DMAC.CHEXT_10)
+#define DMACNXLA_10 (DMAC.NXLA_10)
+#define DMACCRLA_10 (DMAC.CRLA_10)
+#define DMACN0SA_11 (DMAC.N0SA_11)
+#define DMACN0DA_11 (DMAC.N0DA_11)
+#define DMACN0TB_11 (DMAC.N0TB_11)
+#define DMACN1SA_11 (DMAC.N1SA_11)
+#define DMACN1DA_11 (DMAC.N1DA_11)
+#define DMACN1TB_11 (DMAC.N1TB_11)
+#define DMACCRSA_11 (DMAC.CRSA_11)
+#define DMACCRDA_11 (DMAC.CRDA_11)
+#define DMACCRTB_11 (DMAC.CRTB_11)
+#define DMACCHSTAT_11 (DMAC.CHSTAT_11)
+#define DMACCHCTRL_11 (DMAC.CHCTRL_11)
+#define DMACCHCFG_11 (DMAC.CHCFG_11)
+#define DMACCHITVL_11 (DMAC.CHITVL_11)
+#define DMACCHEXT_11 (DMAC.CHEXT_11)
+#define DMACNXLA_11 (DMAC.NXLA_11)
+#define DMACCRLA_11 (DMAC.CRLA_11)
+#define DMACN0SA_12 (DMAC.N0SA_12)
+#define DMACN0DA_12 (DMAC.N0DA_12)
+#define DMACN0TB_12 (DMAC.N0TB_12)
+#define DMACN1SA_12 (DMAC.N1SA_12)
+#define DMACN1DA_12 (DMAC.N1DA_12)
+#define DMACN1TB_12 (DMAC.N1TB_12)
+#define DMACCRSA_12 (DMAC.CRSA_12)
+#define DMACCRDA_12 (DMAC.CRDA_12)
+#define DMACCRTB_12 (DMAC.CRTB_12)
+#define DMACCHSTAT_12 (DMAC.CHSTAT_12)
+#define DMACCHCTRL_12 (DMAC.CHCTRL_12)
+#define DMACCHCFG_12 (DMAC.CHCFG_12)
+#define DMACCHITVL_12 (DMAC.CHITVL_12)
+#define DMACCHEXT_12 (DMAC.CHEXT_12)
+#define DMACNXLA_12 (DMAC.NXLA_12)
+#define DMACCRLA_12 (DMAC.CRLA_12)
+#define DMACN0SA_13 (DMAC.N0SA_13)
+#define DMACN0DA_13 (DMAC.N0DA_13)
+#define DMACN0TB_13 (DMAC.N0TB_13)
+#define DMACN1SA_13 (DMAC.N1SA_13)
+#define DMACN1DA_13 (DMAC.N1DA_13)
+#define DMACN1TB_13 (DMAC.N1TB_13)
+#define DMACCRSA_13 (DMAC.CRSA_13)
+#define DMACCRDA_13 (DMAC.CRDA_13)
+#define DMACCRTB_13 (DMAC.CRTB_13)
+#define DMACCHSTAT_13 (DMAC.CHSTAT_13)
+#define DMACCHCTRL_13 (DMAC.CHCTRL_13)
+#define DMACCHCFG_13 (DMAC.CHCFG_13)
+#define DMACCHITVL_13 (DMAC.CHITVL_13)
+#define DMACCHEXT_13 (DMAC.CHEXT_13)
+#define DMACNXLA_13 (DMAC.NXLA_13)
+#define DMACCRLA_13 (DMAC.CRLA_13)
+#define DMACN0SA_14 (DMAC.N0SA_14)
+#define DMACN0DA_14 (DMAC.N0DA_14)
+#define DMACN0TB_14 (DMAC.N0TB_14)
+#define DMACN1SA_14 (DMAC.N1SA_14)
+#define DMACN1DA_14 (DMAC.N1DA_14)
+#define DMACN1TB_14 (DMAC.N1TB_14)
+#define DMACCRSA_14 (DMAC.CRSA_14)
+#define DMACCRDA_14 (DMAC.CRDA_14)
+#define DMACCRTB_14 (DMAC.CRTB_14)
+#define DMACCHSTAT_14 (DMAC.CHSTAT_14)
+#define DMACCHCTRL_14 (DMAC.CHCTRL_14)
+#define DMACCHCFG_14 (DMAC.CHCFG_14)
+#define DMACCHITVL_14 (DMAC.CHITVL_14)
+#define DMACCHEXT_14 (DMAC.CHEXT_14)
+#define DMACNXLA_14 (DMAC.NXLA_14)
+#define DMACCRLA_14 (DMAC.CRLA_14)
+#define DMACN0SA_15 (DMAC.N0SA_15)
+#define DMACN0DA_15 (DMAC.N0DA_15)
+#define DMACN0TB_15 (DMAC.N0TB_15)
+#define DMACN1SA_15 (DMAC.N1SA_15)
+#define DMACN1DA_15 (DMAC.N1DA_15)
+#define DMACN1TB_15 (DMAC.N1TB_15)
+#define DMACCRSA_15 (DMAC.CRSA_15)
+#define DMACCRDA_15 (DMAC.CRDA_15)
+#define DMACCRTB_15 (DMAC.CRTB_15)
+#define DMACCHSTAT_15 (DMAC.CHSTAT_15)
+#define DMACCHCTRL_15 (DMAC.CHCTRL_15)
+#define DMACCHCFG_15 (DMAC.CHCFG_15)
+#define DMACCHITVL_15 (DMAC.CHITVL_15)
+#define DMACCHEXT_15 (DMAC.CHEXT_15)
+#define DMACNXLA_15 (DMAC.NXLA_15)
+#define DMACCRLA_15 (DMAC.CRLA_15)
+#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15)
+#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15)
+#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15)
+#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15)
+#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15)
+#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15)
+#define DMACDMARS0 (DMAC.DMARS0)
+#define DMACDMARS1 (DMAC.DMARS1)
+#define DMACDMARS2 (DMAC.DMARS2)
+#define DMACDMARS3 (DMAC.DMARS3)
+#define DMACDMARS4 (DMAC.DMARS4)
+#define DMACDMARS5 (DMAC.DMARS5)
+#define DMACDMARS6 (DMAC.DMARS6)
+#define DMACDMARS7 (DMAC.DMARS7)
+
+
+typedef struct st_dmars_mm
 {
-    uint32_t       DMARS;                                        /*  DMARS     */
-};
-#define DMACmm_COUNT  8
-#define DMACmm_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define DMAC01    (*(struct st_dmars_mm *)&DMAC.DMARS0)  /* DMAC0-1   */
-#define DMAC23    (*(struct st_dmars_mm *)&DMAC.DMARS1)  /* DMAC2-3   */
-#define DMAC45    (*(struct st_dmars_mm *)&DMAC.DMARS2)  /* DMAC4-5   */
-#define DMAC67    (*(struct st_dmars_mm *)&DMAC.DMARS3)  /* DMAC6-7   */
-#define DMAC89    (*(struct st_dmars_mm *)&DMAC.DMARS4)  /* DMAC8-9   */
-#define DMAC1011  (*(struct st_dmars_mm *)&DMAC.DMARS5)  /* DMAC10-11 */
-#define DMAC1213  (*(struct st_dmars_mm *)&DMAC.DMARS6)  /* DMAC12-13 */
-#define DMAC1415  (*(struct st_dmars_mm *)&DMAC.DMARS7)  /* DMAC14-15 */
-
-/* End of channnel array defines of DMAC */
+ 
+    volatile uint32_t  DMARS;                                    /*  DMARS     */
+} r_io_dmars_mm_t;
 
 
-#define DMACN0SA_0 DMAC.N0SA_0
-#define DMACN0DA_0 DMAC.N0DA_0
-#define DMACN0TB_0 DMAC.N0TB_0
-#define DMACN1SA_0 DMAC.N1SA_0
-#define DMACN1DA_0 DMAC.N1DA_0
-#define DMACN1TB_0 DMAC.N1TB_0
-#define DMACCRSA_0 DMAC.CRSA_0
-#define DMACCRDA_0 DMAC.CRDA_0
-#define DMACCRTB_0 DMAC.CRTB_0
-#define DMACCHSTAT_0 DMAC.CHSTAT_0
-#define DMACCHCTRL_0 DMAC.CHCTRL_0
-#define DMACCHCFG_0 DMAC.CHCFG_0
-#define DMACCHITVL_0 DMAC.CHITVL_0
-#define DMACCHEXT_0 DMAC.CHEXT_0
-#define DMACNXLA_0 DMAC.NXLA_0
-#define DMACCRLA_0 DMAC.CRLA_0
-#define DMACN0SA_1 DMAC.N0SA_1
-#define DMACN0DA_1 DMAC.N0DA_1
-#define DMACN0TB_1 DMAC.N0TB_1
-#define DMACN1SA_1 DMAC.N1SA_1
-#define DMACN1DA_1 DMAC.N1DA_1
-#define DMACN1TB_1 DMAC.N1TB_1
-#define DMACCRSA_1 DMAC.CRSA_1
-#define DMACCRDA_1 DMAC.CRDA_1
-#define DMACCRTB_1 DMAC.CRTB_1
-#define DMACCHSTAT_1 DMAC.CHSTAT_1
-#define DMACCHCTRL_1 DMAC.CHCTRL_1
-#define DMACCHCFG_1 DMAC.CHCFG_1
-#define DMACCHITVL_1 DMAC.CHITVL_1
-#define DMACCHEXT_1 DMAC.CHEXT_1
-#define DMACNXLA_1 DMAC.NXLA_1
-#define DMACCRLA_1 DMAC.CRLA_1
-#define DMACN0SA_2 DMAC.N0SA_2
-#define DMACN0DA_2 DMAC.N0DA_2
-#define DMACN0TB_2 DMAC.N0TB_2
-#define DMACN1SA_2 DMAC.N1SA_2
-#define DMACN1DA_2 DMAC.N1DA_2
-#define DMACN1TB_2 DMAC.N1TB_2
-#define DMACCRSA_2 DMAC.CRSA_2
-#define DMACCRDA_2 DMAC.CRDA_2
-#define DMACCRTB_2 DMAC.CRTB_2
-#define DMACCHSTAT_2 DMAC.CHSTAT_2
-#define DMACCHCTRL_2 DMAC.CHCTRL_2
-#define DMACCHCFG_2 DMAC.CHCFG_2
-#define DMACCHITVL_2 DMAC.CHITVL_2
-#define DMACCHEXT_2 DMAC.CHEXT_2
-#define DMACNXLA_2 DMAC.NXLA_2
-#define DMACCRLA_2 DMAC.CRLA_2
-#define DMACN0SA_3 DMAC.N0SA_3
-#define DMACN0DA_3 DMAC.N0DA_3
-#define DMACN0TB_3 DMAC.N0TB_3
-#define DMACN1SA_3 DMAC.N1SA_3
-#define DMACN1DA_3 DMAC.N1DA_3
-#define DMACN1TB_3 DMAC.N1TB_3
-#define DMACCRSA_3 DMAC.CRSA_3
-#define DMACCRDA_3 DMAC.CRDA_3
-#define DMACCRTB_3 DMAC.CRTB_3
-#define DMACCHSTAT_3 DMAC.CHSTAT_3
-#define DMACCHCTRL_3 DMAC.CHCTRL_3
-#define DMACCHCFG_3 DMAC.CHCFG_3
-#define DMACCHITVL_3 DMAC.CHITVL_3
-#define DMACCHEXT_3 DMAC.CHEXT_3
-#define DMACNXLA_3 DMAC.NXLA_3
-#define DMACCRLA_3 DMAC.CRLA_3
-#define DMACN0SA_4 DMAC.N0SA_4
-#define DMACN0DA_4 DMAC.N0DA_4
-#define DMACN0TB_4 DMAC.N0TB_4
-#define DMACN1SA_4 DMAC.N1SA_4
-#define DMACN1DA_4 DMAC.N1DA_4
-#define DMACN1TB_4 DMAC.N1TB_4
-#define DMACCRSA_4 DMAC.CRSA_4
-#define DMACCRDA_4 DMAC.CRDA_4
-#define DMACCRTB_4 DMAC.CRTB_4
-#define DMACCHSTAT_4 DMAC.CHSTAT_4
-#define DMACCHCTRL_4 DMAC.CHCTRL_4
-#define DMACCHCFG_4 DMAC.CHCFG_4
-#define DMACCHITVL_4 DMAC.CHITVL_4
-#define DMACCHEXT_4 DMAC.CHEXT_4
-#define DMACNXLA_4 DMAC.NXLA_4
-#define DMACCRLA_4 DMAC.CRLA_4
-#define DMACN0SA_5 DMAC.N0SA_5
-#define DMACN0DA_5 DMAC.N0DA_5
-#define DMACN0TB_5 DMAC.N0TB_5
-#define DMACN1SA_5 DMAC.N1SA_5
-#define DMACN1DA_5 DMAC.N1DA_5
-#define DMACN1TB_5 DMAC.N1TB_5
-#define DMACCRSA_5 DMAC.CRSA_5
-#define DMACCRDA_5 DMAC.CRDA_5
-#define DMACCRTB_5 DMAC.CRTB_5
-#define DMACCHSTAT_5 DMAC.CHSTAT_5
-#define DMACCHCTRL_5 DMAC.CHCTRL_5
-#define DMACCHCFG_5 DMAC.CHCFG_5
-#define DMACCHITVL_5 DMAC.CHITVL_5
-#define DMACCHEXT_5 DMAC.CHEXT_5
-#define DMACNXLA_5 DMAC.NXLA_5
-#define DMACCRLA_5 DMAC.CRLA_5
-#define DMACN0SA_6 DMAC.N0SA_6
-#define DMACN0DA_6 DMAC.N0DA_6
-#define DMACN0TB_6 DMAC.N0TB_6
-#define DMACN1SA_6 DMAC.N1SA_6
-#define DMACN1DA_6 DMAC.N1DA_6
-#define DMACN1TB_6 DMAC.N1TB_6
-#define DMACCRSA_6 DMAC.CRSA_6
-#define DMACCRDA_6 DMAC.CRDA_6
-#define DMACCRTB_6 DMAC.CRTB_6
-#define DMACCHSTAT_6 DMAC.CHSTAT_6
-#define DMACCHCTRL_6 DMAC.CHCTRL_6
-#define DMACCHCFG_6 DMAC.CHCFG_6
-#define DMACCHITVL_6 DMAC.CHITVL_6
-#define DMACCHEXT_6 DMAC.CHEXT_6
-#define DMACNXLA_6 DMAC.NXLA_6
-#define DMACCRLA_6 DMAC.CRLA_6
-#define DMACN0SA_7 DMAC.N0SA_7
-#define DMACN0DA_7 DMAC.N0DA_7
-#define DMACN0TB_7 DMAC.N0TB_7
-#define DMACN1SA_7 DMAC.N1SA_7
-#define DMACN1DA_7 DMAC.N1DA_7
-#define DMACN1TB_7 DMAC.N1TB_7
-#define DMACCRSA_7 DMAC.CRSA_7
-#define DMACCRDA_7 DMAC.CRDA_7
-#define DMACCRTB_7 DMAC.CRTB_7
-#define DMACCHSTAT_7 DMAC.CHSTAT_7
-#define DMACCHCTRL_7 DMAC.CHCTRL_7
-#define DMACCHCFG_7 DMAC.CHCFG_7
-#define DMACCHITVL_7 DMAC.CHITVL_7
-#define DMACCHEXT_7 DMAC.CHEXT_7
-#define DMACNXLA_7 DMAC.NXLA_7
-#define DMACCRLA_7 DMAC.CRLA_7
-#define DMACDCTRL_0_7 DMAC.DCTRL_0_7
-#define DMACDSTAT_EN_0_7 DMAC.DSTAT_EN_0_7
-#define DMACDSTAT_ER_0_7 DMAC.DSTAT_ER_0_7
-#define DMACDSTAT_END_0_7 DMAC.DSTAT_END_0_7
-#define DMACDSTAT_TC_0_7 DMAC.DSTAT_TC_0_7
-#define DMACDSTAT_SUS_0_7 DMAC.DSTAT_SUS_0_7
-#define DMACN0SA_8 DMAC.N0SA_8
-#define DMACN0DA_8 DMAC.N0DA_8
-#define DMACN0TB_8 DMAC.N0TB_8
-#define DMACN1SA_8 DMAC.N1SA_8
-#define DMACN1DA_8 DMAC.N1DA_8
-#define DMACN1TB_8 DMAC.N1TB_8
-#define DMACCRSA_8 DMAC.CRSA_8
-#define DMACCRDA_8 DMAC.CRDA_8
-#define DMACCRTB_8 DMAC.CRTB_8
-#define DMACCHSTAT_8 DMAC.CHSTAT_8
-#define DMACCHCTRL_8 DMAC.CHCTRL_8
-#define DMACCHCFG_8 DMAC.CHCFG_8
-#define DMACCHITVL_8 DMAC.CHITVL_8
-#define DMACCHEXT_8 DMAC.CHEXT_8
-#define DMACNXLA_8 DMAC.NXLA_8
-#define DMACCRLA_8 DMAC.CRLA_8
-#define DMACN0SA_9 DMAC.N0SA_9
-#define DMACN0DA_9 DMAC.N0DA_9
-#define DMACN0TB_9 DMAC.N0TB_9
-#define DMACN1SA_9 DMAC.N1SA_9
-#define DMACN1DA_9 DMAC.N1DA_9
-#define DMACN1TB_9 DMAC.N1TB_9
-#define DMACCRSA_9 DMAC.CRSA_9
-#define DMACCRDA_9 DMAC.CRDA_9
-#define DMACCRTB_9 DMAC.CRTB_9
-#define DMACCHSTAT_9 DMAC.CHSTAT_9
-#define DMACCHCTRL_9 DMAC.CHCTRL_9
-#define DMACCHCFG_9 DMAC.CHCFG_9
-#define DMACCHITVL_9 DMAC.CHITVL_9
-#define DMACCHEXT_9 DMAC.CHEXT_9
-#define DMACNXLA_9 DMAC.NXLA_9
-#define DMACCRLA_9 DMAC.CRLA_9
-#define DMACN0SA_10 DMAC.N0SA_10
-#define DMACN0DA_10 DMAC.N0DA_10
-#define DMACN0TB_10 DMAC.N0TB_10
-#define DMACN1SA_10 DMAC.N1SA_10
-#define DMACN1DA_10 DMAC.N1DA_10
-#define DMACN1TB_10 DMAC.N1TB_10
-#define DMACCRSA_10 DMAC.CRSA_10
-#define DMACCRDA_10 DMAC.CRDA_10
-#define DMACCRTB_10 DMAC.CRTB_10
-#define DMACCHSTAT_10 DMAC.CHSTAT_10
-#define DMACCHCTRL_10 DMAC.CHCTRL_10
-#define DMACCHCFG_10 DMAC.CHCFG_10
-#define DMACCHITVL_10 DMAC.CHITVL_10
-#define DMACCHEXT_10 DMAC.CHEXT_10
-#define DMACNXLA_10 DMAC.NXLA_10
-#define DMACCRLA_10 DMAC.CRLA_10
-#define DMACN0SA_11 DMAC.N0SA_11
-#define DMACN0DA_11 DMAC.N0DA_11
-#define DMACN0TB_11 DMAC.N0TB_11
-#define DMACN1SA_11 DMAC.N1SA_11
-#define DMACN1DA_11 DMAC.N1DA_11
-#define DMACN1TB_11 DMAC.N1TB_11
-#define DMACCRSA_11 DMAC.CRSA_11
-#define DMACCRDA_11 DMAC.CRDA_11
-#define DMACCRTB_11 DMAC.CRTB_11
-#define DMACCHSTAT_11 DMAC.CHSTAT_11
-#define DMACCHCTRL_11 DMAC.CHCTRL_11
-#define DMACCHCFG_11 DMAC.CHCFG_11
-#define DMACCHITVL_11 DMAC.CHITVL_11
-#define DMACCHEXT_11 DMAC.CHEXT_11
-#define DMACNXLA_11 DMAC.NXLA_11
-#define DMACCRLA_11 DMAC.CRLA_11
-#define DMACN0SA_12 DMAC.N0SA_12
-#define DMACN0DA_12 DMAC.N0DA_12
-#define DMACN0TB_12 DMAC.N0TB_12
-#define DMACN1SA_12 DMAC.N1SA_12
-#define DMACN1DA_12 DMAC.N1DA_12
-#define DMACN1TB_12 DMAC.N1TB_12
-#define DMACCRSA_12 DMAC.CRSA_12
-#define DMACCRDA_12 DMAC.CRDA_12
-#define DMACCRTB_12 DMAC.CRTB_12
-#define DMACCHSTAT_12 DMAC.CHSTAT_12
-#define DMACCHCTRL_12 DMAC.CHCTRL_12
-#define DMACCHCFG_12 DMAC.CHCFG_12
-#define DMACCHITVL_12 DMAC.CHITVL_12
-#define DMACCHEXT_12 DMAC.CHEXT_12
-#define DMACNXLA_12 DMAC.NXLA_12
-#define DMACCRLA_12 DMAC.CRLA_12
-#define DMACN0SA_13 DMAC.N0SA_13
-#define DMACN0DA_13 DMAC.N0DA_13
-#define DMACN0TB_13 DMAC.N0TB_13
-#define DMACN1SA_13 DMAC.N1SA_13
-#define DMACN1DA_13 DMAC.N1DA_13
-#define DMACN1TB_13 DMAC.N1TB_13
-#define DMACCRSA_13 DMAC.CRSA_13
-#define DMACCRDA_13 DMAC.CRDA_13
-#define DMACCRTB_13 DMAC.CRTB_13
-#define DMACCHSTAT_13 DMAC.CHSTAT_13
-#define DMACCHCTRL_13 DMAC.CHCTRL_13
-#define DMACCHCFG_13 DMAC.CHCFG_13
-#define DMACCHITVL_13 DMAC.CHITVL_13
-#define DMACCHEXT_13 DMAC.CHEXT_13
-#define DMACNXLA_13 DMAC.NXLA_13
-#define DMACCRLA_13 DMAC.CRLA_13
-#define DMACN0SA_14 DMAC.N0SA_14
-#define DMACN0DA_14 DMAC.N0DA_14
-#define DMACN0TB_14 DMAC.N0TB_14
-#define DMACN1SA_14 DMAC.N1SA_14
-#define DMACN1DA_14 DMAC.N1DA_14
-#define DMACN1TB_14 DMAC.N1TB_14
-#define DMACCRSA_14 DMAC.CRSA_14
-#define DMACCRDA_14 DMAC.CRDA_14
-#define DMACCRTB_14 DMAC.CRTB_14
-#define DMACCHSTAT_14 DMAC.CHSTAT_14
-#define DMACCHCTRL_14 DMAC.CHCTRL_14
-#define DMACCHCFG_14 DMAC.CHCFG_14
-#define DMACCHITVL_14 DMAC.CHITVL_14
-#define DMACCHEXT_14 DMAC.CHEXT_14
-#define DMACNXLA_14 DMAC.NXLA_14
-#define DMACCRLA_14 DMAC.CRLA_14
-#define DMACN0SA_15 DMAC.N0SA_15
-#define DMACN0DA_15 DMAC.N0DA_15
-#define DMACN0TB_15 DMAC.N0TB_15
-#define DMACN1SA_15 DMAC.N1SA_15
-#define DMACN1DA_15 DMAC.N1DA_15
-#define DMACN1TB_15 DMAC.N1TB_15
-#define DMACCRSA_15 DMAC.CRSA_15
-#define DMACCRDA_15 DMAC.CRDA_15
-#define DMACCRTB_15 DMAC.CRTB_15
-#define DMACCHSTAT_15 DMAC.CHSTAT_15
-#define DMACCHCTRL_15 DMAC.CHCTRL_15
-#define DMACCHCFG_15 DMAC.CHCFG_15
-#define DMACCHITVL_15 DMAC.CHITVL_15
-#define DMACCHEXT_15 DMAC.CHEXT_15
-#define DMACNXLA_15 DMAC.NXLA_15
-#define DMACCRLA_15 DMAC.CRLA_15
-#define DMACDCTRL_8_15 DMAC.DCTRL_8_15
-#define DMACDSTAT_EN_8_15 DMAC.DSTAT_EN_8_15
-#define DMACDSTAT_ER_8_15 DMAC.DSTAT_ER_8_15
-#define DMACDSTAT_END_8_15 DMAC.DSTAT_END_8_15
-#define DMACDSTAT_TC_8_15 DMAC.DSTAT_TC_8_15
-#define DMACDSTAT_SUS_8_15 DMAC.DSTAT_SUS_8_15
-#define DMACDMARS0 DMAC.DMARS0
-#define DMACDMARS1 DMAC.DMARS1
-#define DMACDMARS2 DMAC.DMARS2
-#define DMACDMARS3 DMAC.DMARS3
-#define DMACDMARS4 DMAC.DMARS4
-#define DMACDMARS5 DMAC.DMARS5
-#define DMACDMARS6 DMAC.DMARS6
-#define DMACDMARS7 DMAC.DMARS7
+typedef struct st_dmac
+{
+                                                           /* DMAC             */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_0;                                 /*  N0SA_0          */
+    volatile uint32_t  N0DA_0;                                 /*  N0DA_0          */
+    volatile uint32_t  N0TB_0;                                 /*  N0TB_0          */
+    volatile uint32_t  N1SA_0;                                 /*  N1SA_0          */
+    volatile uint32_t  N1DA_0;                                 /*  N1DA_0          */
+    volatile uint32_t  N1TB_0;                                 /*  N1TB_0          */
+    volatile uint32_t  CRSA_0;                                 /*  CRSA_0          */
+    volatile uint32_t  CRDA_0;                                 /*  CRDA_0          */
+    volatile uint32_t  CRTB_0;                                 /*  CRTB_0          */
+    volatile uint32_t  CHSTAT_0;                               /*  CHSTAT_0        */
+    volatile uint32_t  CHCTRL_0;                               /*  CHCTRL_0        */
+    volatile uint32_t  CHCFG_0;                                /*  CHCFG_0         */
+    volatile uint32_t  CHITVL_0;                               /*  CHITVL_0        */
+    volatile uint32_t  CHEXT_0;                                /*  CHEXT_0         */
+    volatile uint32_t  NXLA_0;                                 /*  NXLA_0          */
+    volatile uint32_t  CRLA_0;                                 /*  CRLA_0          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_1;                                 /*  N0SA_1          */
+    volatile uint32_t  N0DA_1;                                 /*  N0DA_1          */
+    volatile uint32_t  N0TB_1;                                 /*  N0TB_1          */
+    volatile uint32_t  N1SA_1;                                 /*  N1SA_1          */
+    volatile uint32_t  N1DA_1;                                 /*  N1DA_1          */
+    volatile uint32_t  N1TB_1;                                 /*  N1TB_1          */
+    volatile uint32_t  CRSA_1;                                 /*  CRSA_1          */
+    volatile uint32_t  CRDA_1;                                 /*  CRDA_1          */
+    volatile uint32_t  CRTB_1;                                 /*  CRTB_1          */
+    volatile uint32_t  CHSTAT_1;                               /*  CHSTAT_1        */
+    volatile uint32_t  CHCTRL_1;                               /*  CHCTRL_1        */
+    volatile uint32_t  CHCFG_1;                                /*  CHCFG_1         */
+    volatile uint32_t  CHITVL_1;                               /*  CHITVL_1        */
+    volatile uint32_t  CHEXT_1;                                /*  CHEXT_1         */
+    volatile uint32_t  NXLA_1;                                 /*  NXLA_1          */
+    volatile uint32_t  CRLA_1;                                 /*  CRLA_1          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_2;                                 /*  N0SA_2          */
+    volatile uint32_t  N0DA_2;                                 /*  N0DA_2          */
+    volatile uint32_t  N0TB_2;                                 /*  N0TB_2          */
+    volatile uint32_t  N1SA_2;                                 /*  N1SA_2          */
+    volatile uint32_t  N1DA_2;                                 /*  N1DA_2          */
+    volatile uint32_t  N1TB_2;                                 /*  N1TB_2          */
+    volatile uint32_t  CRSA_2;                                 /*  CRSA_2          */
+    volatile uint32_t  CRDA_2;                                 /*  CRDA_2          */
+    volatile uint32_t  CRTB_2;                                 /*  CRTB_2          */
+    volatile uint32_t  CHSTAT_2;                               /*  CHSTAT_2        */
+    volatile uint32_t  CHCTRL_2;                               /*  CHCTRL_2        */
+    volatile uint32_t  CHCFG_2;                                /*  CHCFG_2         */
+    volatile uint32_t  CHITVL_2;                               /*  CHITVL_2        */
+    volatile uint32_t  CHEXT_2;                                /*  CHEXT_2         */
+    volatile uint32_t  NXLA_2;                                 /*  NXLA_2          */
+    volatile uint32_t  CRLA_2;                                 /*  CRLA_2          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_3;                                 /*  N0SA_3          */
+    volatile uint32_t  N0DA_3;                                 /*  N0DA_3          */
+    volatile uint32_t  N0TB_3;                                 /*  N0TB_3          */
+    volatile uint32_t  N1SA_3;                                 /*  N1SA_3          */
+    volatile uint32_t  N1DA_3;                                 /*  N1DA_3          */
+    volatile uint32_t  N1TB_3;                                 /*  N1TB_3          */
+    volatile uint32_t  CRSA_3;                                 /*  CRSA_3          */
+    volatile uint32_t  CRDA_3;                                 /*  CRDA_3          */
+    volatile uint32_t  CRTB_3;                                 /*  CRTB_3          */
+    volatile uint32_t  CHSTAT_3;                               /*  CHSTAT_3        */
+    volatile uint32_t  CHCTRL_3;                               /*  CHCTRL_3        */
+    volatile uint32_t  CHCFG_3;                                /*  CHCFG_3         */
+    volatile uint32_t  CHITVL_3;                               /*  CHITVL_3        */
+    volatile uint32_t  CHEXT_3;                                /*  CHEXT_3         */
+    volatile uint32_t  NXLA_3;                                 /*  NXLA_3          */
+    volatile uint32_t  CRLA_3;                                 /*  CRLA_3          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_4;                                 /*  N0SA_4          */
+    volatile uint32_t  N0DA_4;                                 /*  N0DA_4          */
+    volatile uint32_t  N0TB_4;                                 /*  N0TB_4          */
+    volatile uint32_t  N1SA_4;                                 /*  N1SA_4          */
+    volatile uint32_t  N1DA_4;                                 /*  N1DA_4          */
+    volatile uint32_t  N1TB_4;                                 /*  N1TB_4          */
+    volatile uint32_t  CRSA_4;                                 /*  CRSA_4          */
+    volatile uint32_t  CRDA_4;                                 /*  CRDA_4          */
+    volatile uint32_t  CRTB_4;                                 /*  CRTB_4          */
+    volatile uint32_t  CHSTAT_4;                               /*  CHSTAT_4        */
+    volatile uint32_t  CHCTRL_4;                               /*  CHCTRL_4        */
+    volatile uint32_t  CHCFG_4;                                /*  CHCFG_4         */
+    volatile uint32_t  CHITVL_4;                               /*  CHITVL_4        */
+    volatile uint32_t  CHEXT_4;                                /*  CHEXT_4         */
+    volatile uint32_t  NXLA_4;                                 /*  NXLA_4          */
+    volatile uint32_t  CRLA_4;                                 /*  CRLA_4          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_5;                                 /*  N0SA_5          */
+    volatile uint32_t  N0DA_5;                                 /*  N0DA_5          */
+    volatile uint32_t  N0TB_5;                                 /*  N0TB_5          */
+    volatile uint32_t  N1SA_5;                                 /*  N1SA_5          */
+    volatile uint32_t  N1DA_5;                                 /*  N1DA_5          */
+    volatile uint32_t  N1TB_5;                                 /*  N1TB_5          */
+    volatile uint32_t  CRSA_5;                                 /*  CRSA_5          */
+    volatile uint32_t  CRDA_5;                                 /*  CRDA_5          */
+    volatile uint32_t  CRTB_5;                                 /*  CRTB_5          */
+    volatile uint32_t  CHSTAT_5;                               /*  CHSTAT_5        */
+    volatile uint32_t  CHCTRL_5;                               /*  CHCTRL_5        */
+    volatile uint32_t  CHCFG_5;                                /*  CHCFG_5         */
+    volatile uint32_t  CHITVL_5;                               /*  CHITVL_5        */
+    volatile uint32_t  CHEXT_5;                                /*  CHEXT_5         */
+    volatile uint32_t  NXLA_5;                                 /*  NXLA_5          */
+    volatile uint32_t  CRLA_5;                                 /*  CRLA_5          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_6;                                 /*  N0SA_6          */
+    volatile uint32_t  N0DA_6;                                 /*  N0DA_6          */
+    volatile uint32_t  N0TB_6;                                 /*  N0TB_6          */
+    volatile uint32_t  N1SA_6;                                 /*  N1SA_6          */
+    volatile uint32_t  N1DA_6;                                 /*  N1DA_6          */
+    volatile uint32_t  N1TB_6;                                 /*  N1TB_6          */
+    volatile uint32_t  CRSA_6;                                 /*  CRSA_6          */
+    volatile uint32_t  CRDA_6;                                 /*  CRDA_6          */
+    volatile uint32_t  CRTB_6;                                 /*  CRTB_6          */
+    volatile uint32_t  CHSTAT_6;                               /*  CHSTAT_6        */
+    volatile uint32_t  CHCTRL_6;                               /*  CHCTRL_6        */
+    volatile uint32_t  CHCFG_6;                                /*  CHCFG_6         */
+    volatile uint32_t  CHITVL_6;                               /*  CHITVL_6        */
+    volatile uint32_t  CHEXT_6;                                /*  CHEXT_6         */
+    volatile uint32_t  NXLA_6;                                 /*  NXLA_6          */
+    volatile uint32_t  CRLA_6;                                 /*  CRLA_6          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_7;                                 /*  N0SA_7          */
+    volatile uint32_t  N0DA_7;                                 /*  N0DA_7          */
+    volatile uint32_t  N0TB_7;                                 /*  N0TB_7          */
+    volatile uint32_t  N1SA_7;                                 /*  N1SA_7          */
+    volatile uint32_t  N1DA_7;                                 /*  N1DA_7          */
+    volatile uint32_t  N1TB_7;                                 /*  N1TB_7          */
+    volatile uint32_t  CRSA_7;                                 /*  CRSA_7          */
+    volatile uint32_t  CRDA_7;                                 /*  CRDA_7          */
+    volatile uint32_t  CRTB_7;                                 /*  CRTB_7          */
+    volatile uint32_t  CHSTAT_7;                               /*  CHSTAT_7        */
+    volatile uint32_t  CHCTRL_7;                               /*  CHCTRL_7        */
+    volatile uint32_t  CHCFG_7;                                /*  CHCFG_7         */
+    volatile uint32_t  CHITVL_7;                               /*  CHITVL_7        */
+    volatile uint32_t  CHEXT_7;                                /*  CHEXT_7         */
+    volatile uint32_t  NXLA_7;                                 /*  NXLA_7          */
+    volatile uint32_t  CRLA_7;                                 /*  CRLA_7          */
+
+/* end of struct st_dmac_n */
+    volatile uint8_t   dummy187[256];                          /*                  */
+
+/* start of struct st_dmaccommon_n */
+    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
+    volatile uint8_t   dummy188[12];                           /*                  */
+    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
+    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
+    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
+    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
+    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
+
+/* end of struct st_dmaccommon_n */
+    volatile uint8_t   dummy189[220];                          /*                  */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_8;                                 /*  N0SA_8          */
+    volatile uint32_t  N0DA_8;                                 /*  N0DA_8          */
+    volatile uint32_t  N0TB_8;                                 /*  N0TB_8          */
+    volatile uint32_t  N1SA_8;                                 /*  N1SA_8          */
+    volatile uint32_t  N1DA_8;                                 /*  N1DA_8          */
+    volatile uint32_t  N1TB_8;                                 /*  N1TB_8          */
+    volatile uint32_t  CRSA_8;                                 /*  CRSA_8          */
+    volatile uint32_t  CRDA_8;                                 /*  CRDA_8          */
+    volatile uint32_t  CRTB_8;                                 /*  CRTB_8          */
+    volatile uint32_t  CHSTAT_8;                               /*  CHSTAT_8        */
+    volatile uint32_t  CHCTRL_8;                               /*  CHCTRL_8        */
+    volatile uint32_t  CHCFG_8;                                /*  CHCFG_8         */
+    volatile uint32_t  CHITVL_8;                               /*  CHITVL_8        */
+    volatile uint32_t  CHEXT_8;                                /*  CHEXT_8         */
+    volatile uint32_t  NXLA_8;                                 /*  NXLA_8          */
+    volatile uint32_t  CRLA_8;                                 /*  CRLA_8          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_9;                                 /*  N0SA_9          */
+    volatile uint32_t  N0DA_9;                                 /*  N0DA_9          */
+    volatile uint32_t  N0TB_9;                                 /*  N0TB_9          */
+    volatile uint32_t  N1SA_9;                                 /*  N1SA_9          */
+    volatile uint32_t  N1DA_9;                                 /*  N1DA_9          */
+    volatile uint32_t  N1TB_9;                                 /*  N1TB_9          */
+    volatile uint32_t  CRSA_9;                                 /*  CRSA_9          */
+    volatile uint32_t  CRDA_9;                                 /*  CRDA_9          */
+    volatile uint32_t  CRTB_9;                                 /*  CRTB_9          */
+    volatile uint32_t  CHSTAT_9;                               /*  CHSTAT_9        */
+    volatile uint32_t  CHCTRL_9;                               /*  CHCTRL_9        */
+    volatile uint32_t  CHCFG_9;                                /*  CHCFG_9         */
+    volatile uint32_t  CHITVL_9;                               /*  CHITVL_9        */
+    volatile uint32_t  CHEXT_9;                                /*  CHEXT_9         */
+    volatile uint32_t  NXLA_9;                                 /*  NXLA_9          */
+    volatile uint32_t  CRLA_9;                                 /*  CRLA_9          */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_10;                                /*  N0SA_10         */
+    volatile uint32_t  N0DA_10;                                /*  N0DA_10         */
+    volatile uint32_t  N0TB_10;                                /*  N0TB_10         */
+    volatile uint32_t  N1SA_10;                                /*  N1SA_10         */
+    volatile uint32_t  N1DA_10;                                /*  N1DA_10         */
+    volatile uint32_t  N1TB_10;                                /*  N1TB_10         */
+    volatile uint32_t  CRSA_10;                                /*  CRSA_10         */
+    volatile uint32_t  CRDA_10;                                /*  CRDA_10         */
+    volatile uint32_t  CRTB_10;                                /*  CRTB_10         */
+    volatile uint32_t  CHSTAT_10;                              /*  CHSTAT_10       */
+    volatile uint32_t  CHCTRL_10;                              /*  CHCTRL_10       */
+    volatile uint32_t  CHCFG_10;                               /*  CHCFG_10        */
+    volatile uint32_t  CHITVL_10;                              /*  CHITVL_10       */
+    volatile uint32_t  CHEXT_10;                               /*  CHEXT_10        */
+    volatile uint32_t  NXLA_10;                                /*  NXLA_10         */
+    volatile uint32_t  CRLA_10;                                /*  CRLA_10         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_11;                                /*  N0SA_11         */
+    volatile uint32_t  N0DA_11;                                /*  N0DA_11         */
+    volatile uint32_t  N0TB_11;                                /*  N0TB_11         */
+    volatile uint32_t  N1SA_11;                                /*  N1SA_11         */
+    volatile uint32_t  N1DA_11;                                /*  N1DA_11         */
+    volatile uint32_t  N1TB_11;                                /*  N1TB_11         */
+    volatile uint32_t  CRSA_11;                                /*  CRSA_11         */
+    volatile uint32_t  CRDA_11;                                /*  CRDA_11         */
+    volatile uint32_t  CRTB_11;                                /*  CRTB_11         */
+    volatile uint32_t  CHSTAT_11;                              /*  CHSTAT_11       */
+    volatile uint32_t  CHCTRL_11;                              /*  CHCTRL_11       */
+    volatile uint32_t  CHCFG_11;                               /*  CHCFG_11        */
+    volatile uint32_t  CHITVL_11;                              /*  CHITVL_11       */
+    volatile uint32_t  CHEXT_11;                               /*  CHEXT_11        */
+    volatile uint32_t  NXLA_11;                                /*  NXLA_11         */
+    volatile uint32_t  CRLA_11;                                /*  CRLA_11         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_12;                                /*  N0SA_12         */
+    volatile uint32_t  N0DA_12;                                /*  N0DA_12         */
+    volatile uint32_t  N0TB_12;                                /*  N0TB_12         */
+    volatile uint32_t  N1SA_12;                                /*  N1SA_12         */
+    volatile uint32_t  N1DA_12;                                /*  N1DA_12         */
+    volatile uint32_t  N1TB_12;                                /*  N1TB_12         */
+    volatile uint32_t  CRSA_12;                                /*  CRSA_12         */
+    volatile uint32_t  CRDA_12;                                /*  CRDA_12         */
+    volatile uint32_t  CRTB_12;                                /*  CRTB_12         */
+    volatile uint32_t  CHSTAT_12;                              /*  CHSTAT_12       */
+    volatile uint32_t  CHCTRL_12;                              /*  CHCTRL_12       */
+    volatile uint32_t  CHCFG_12;                               /*  CHCFG_12        */
+    volatile uint32_t  CHITVL_12;                              /*  CHITVL_12       */
+    volatile uint32_t  CHEXT_12;                               /*  CHEXT_12        */
+    volatile uint32_t  NXLA_12;                                /*  NXLA_12         */
+    volatile uint32_t  CRLA_12;                                /*  CRLA_12         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_13;                                /*  N0SA_13         */
+    volatile uint32_t  N0DA_13;                                /*  N0DA_13         */
+    volatile uint32_t  N0TB_13;                                /*  N0TB_13         */
+    volatile uint32_t  N1SA_13;                                /*  N1SA_13         */
+    volatile uint32_t  N1DA_13;                                /*  N1DA_13         */
+    volatile uint32_t  N1TB_13;                                /*  N1TB_13         */
+    volatile uint32_t  CRSA_13;                                /*  CRSA_13         */
+    volatile uint32_t  CRDA_13;                                /*  CRDA_13         */
+    volatile uint32_t  CRTB_13;                                /*  CRTB_13         */
+    volatile uint32_t  CHSTAT_13;                              /*  CHSTAT_13       */
+    volatile uint32_t  CHCTRL_13;                              /*  CHCTRL_13       */
+    volatile uint32_t  CHCFG_13;                               /*  CHCFG_13        */
+    volatile uint32_t  CHITVL_13;                              /*  CHITVL_13       */
+    volatile uint32_t  CHEXT_13;                               /*  CHEXT_13        */
+    volatile uint32_t  NXLA_13;                                /*  NXLA_13         */
+    volatile uint32_t  CRLA_13;                                /*  CRLA_13         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_14;                                /*  N0SA_14         */
+    volatile uint32_t  N0DA_14;                                /*  N0DA_14         */
+    volatile uint32_t  N0TB_14;                                /*  N0TB_14         */
+    volatile uint32_t  N1SA_14;                                /*  N1SA_14         */
+    volatile uint32_t  N1DA_14;                                /*  N1DA_14         */
+    volatile uint32_t  N1TB_14;                                /*  N1TB_14         */
+    volatile uint32_t  CRSA_14;                                /*  CRSA_14         */
+    volatile uint32_t  CRDA_14;                                /*  CRDA_14         */
+    volatile uint32_t  CRTB_14;                                /*  CRTB_14         */
+    volatile uint32_t  CHSTAT_14;                              /*  CHSTAT_14       */
+    volatile uint32_t  CHCTRL_14;                              /*  CHCTRL_14       */
+    volatile uint32_t  CHCFG_14;                               /*  CHCFG_14        */
+    volatile uint32_t  CHITVL_14;                              /*  CHITVL_14       */
+    volatile uint32_t  CHEXT_14;                               /*  CHEXT_14        */
+    volatile uint32_t  NXLA_14;                                /*  NXLA_14         */
+    volatile uint32_t  CRLA_14;                                /*  CRLA_14         */
+
+/* end of struct st_dmac_n */
+
+/* start of struct st_dmac_n */
+    volatile uint32_t  N0SA_15;                                /*  N0SA_15         */
+    volatile uint32_t  N0DA_15;                                /*  N0DA_15         */
+    volatile uint32_t  N0TB_15;                                /*  N0TB_15         */
+    volatile uint32_t  N1SA_15;                                /*  N1SA_15         */
+    volatile uint32_t  N1DA_15;                                /*  N1DA_15         */
+    volatile uint32_t  N1TB_15;                                /*  N1TB_15         */
+    volatile uint32_t  CRSA_15;                                /*  CRSA_15         */
+    volatile uint32_t  CRDA_15;                                /*  CRDA_15         */
+    volatile uint32_t  CRTB_15;                                /*  CRTB_15         */
+    volatile uint32_t  CHSTAT_15;                              /*  CHSTAT_15       */
+    volatile uint32_t  CHCTRL_15;                              /*  CHCTRL_15       */
+    volatile uint32_t  CHCFG_15;                               /*  CHCFG_15        */
+    volatile uint32_t  CHITVL_15;                              /*  CHITVL_15       */
+    volatile uint32_t  CHEXT_15;                               /*  CHEXT_15        */
+    volatile uint32_t  NXLA_15;                                /*  NXLA_15         */
+    volatile uint32_t  CRLA_15;                                /*  CRLA_15         */
+
+/* end of struct st_dmac_n */
+    volatile uint8_t   dummy190[256];                          /*                  */
+
+/* start of struct st_dmaccommon_n */
+    volatile uint32_t  DCTRL_8_15;                             /*  DCTRL_8_15      */
+    volatile uint8_t   dummy191[12];                           /*                  */
+    volatile uint32_t  DSTAT_EN_8_15;                          /*  DSTAT_EN_8_15   */
+    volatile uint32_t  DSTAT_ER_8_15;                          /*  DSTAT_ER_8_15   */
+    volatile uint32_t  DSTAT_END_8_15;                         /*  DSTAT_END_8_15  */
+    volatile uint32_t  DSTAT_TC_8_15;                          /*  DSTAT_TC_8_15   */
+    volatile uint32_t  DSTAT_SUS_8_15;                         /*  DSTAT_SUS_8_15  */
+
+/* end of struct st_dmaccommon_n */
+    volatile uint8_t   dummy192[350095580];                    /*                  */
+    volatile uint32_t  DMARS0;                                 /*  DMARS0          */
+    volatile uint32_t  DMARS1;                                 /*  DMARS1          */
+    volatile uint32_t  DMARS2;                                 /*  DMARS2          */
+    volatile uint32_t  DMARS3;                                 /*  DMARS3          */
+    volatile uint32_t  DMARS4;                                 /*  DMARS4          */
+    volatile uint32_t  DMARS5;                                 /*  DMARS5          */
+    volatile uint32_t  DMARS6;                                 /*  DMARS6          */
+    volatile uint32_t  DMARS7;                                 /*  DMARS7          */
+} r_io_dmac_t;
+
+
+typedef struct st_dmaccommon_n
+{
+ 
+    volatile uint32_t  DCTRL_0_7;                              /*  DCTRL_0_7       */
+    volatile uint8_t   dummy1[12];                             /*                  */
+    volatile uint32_t  DSTAT_EN_0_7;                           /*  DSTAT_EN_0_7    */
+    volatile uint32_t  DSTAT_ER_0_7;                           /*  DSTAT_ER_0_7    */
+    volatile uint32_t  DSTAT_END_0_7;                          /*  DSTAT_END_0_7   */
+    volatile uint32_t  DSTAT_TC_0_7;                           /*  DSTAT_TC_0_7    */
+    volatile uint32_t  DSTAT_SUS_0_7;                          /*  DSTAT_SUS_0_7   */
+} r_io_dmaccommon_n_t;
+
+
+typedef struct st_dmac_n
+{
+ 
+    volatile uint32_t  N0SA_n;                                 /*  N0SA_n          */
+    volatile uint32_t  N0DA_n;                                 /*  N0DA_n          */
+    volatile uint32_t  N0TB_n;                                 /*  N0TB_n          */
+    volatile uint32_t  N1SA_n;                                 /*  N1SA_n          */
+    volatile uint32_t  N1DA_n;                                 /*  N1DA_n          */
+    volatile uint32_t  N1TB_n;                                 /*  N1TB_n          */
+    volatile uint32_t  CRSA_n;                                 /*  CRSA_n          */
+    volatile uint32_t  CRDA_n;                                 /*  CRDA_n          */
+    volatile uint32_t  CRTB_n;                                 /*  CRTB_n          */
+    volatile uint32_t  CHSTAT_n;                               /*  CHSTAT_n        */
+    volatile uint32_t  CHCTRL_n;                               /*  CHCTRL_n        */
+    volatile uint32_t  CHCFG_n;                                /*  CHCFG_n         */
+    volatile uint32_t  CHITVL_n;                               /*  CHITVL_n        */
+    volatile uint32_t  CHEXT_n;                                /*  CHEXT_n         */
+    volatile uint32_t  NXLA_n;                                 /*  NXLA_n          */
+    volatile uint32_t  CRLA_n;                                 /*  CRLA_n          */
+} r_io_dmac_n_t;
+
+
+/* Channel array defines of DMAC (2)*/
+#ifdef  DECLARE_DMACmm_CHANNELS
+volatile struct st_dmars_mm*  DMACmm[ DMACmm_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DMACmm_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DMACmm_CHANNELS */
+
+#ifdef  DECLARE_DMACn_CHANNELS
+volatile struct st_dmac_n*  DMACn[ DMACn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DMACn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DMACn_CHANNELS */
+
+#ifdef  DECLARE_DMACnn_CHANNELS
+volatile struct st_dmaccommon_n*  DMACnn[ DMACnn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DMACnn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DMACnn_CHANNELS */
+/* End of channel array defines of DMAC (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,40 +18,289 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : dvdec_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef DVDEC_IODEFINE_H
 #define DVDEC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_dvdec
-{                                                          /* DVDEC            */
+#define DVDEC1  (*(struct st_dvdec   *)0xFCFFA008uL) /* DVDEC1 */
+#define DVDEC0  (*(struct st_dvdec   *)0xFCFFB808uL) /* DVDEC0 */
+
+
+/* Start of channel array defines of DVDEC */
+
+/* Channel array defines of DVDEC */
+/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
+#define DVDEC_COUNT  (2)
+#define DVDEC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &DVDEC0, &DVDEC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of DVDEC */
+
+
+#define ADCCR1_1 (DVDEC1.ADCCR1)
+#define TGCR1_1 (DVDEC1.TGCR1)
+#define TGCR2_1 (DVDEC1.TGCR2)
+#define TGCR3_1 (DVDEC1.TGCR3)
+#define SYNSCR1_1 (DVDEC1.SYNSCR1)
+#define SYNSCR2_1 (DVDEC1.SYNSCR2)
+#define SYNSCR3_1 (DVDEC1.SYNSCR3)
+#define SYNSCR4_1 (DVDEC1.SYNSCR4)
+#define SYNSCR5_1 (DVDEC1.SYNSCR5)
+#define HAFCCR1_1 (DVDEC1.HAFCCR1)
+#define HAFCCR2_1 (DVDEC1.HAFCCR2)
+#define HAFCCR3_1 (DVDEC1.HAFCCR3)
+#define VCDWCR1_1 (DVDEC1.VCDWCR1)
+#define DCPCR1_1 (DVDEC1.DCPCR1)
+#define DCPCR2_1 (DVDEC1.DCPCR2)
+#define DCPCR3_1 (DVDEC1.DCPCR3)
+#define DCPCR4_1 (DVDEC1.DCPCR4)
+#define DCPCR5_1 (DVDEC1.DCPCR5)
+#define DCPCR6_1 (DVDEC1.DCPCR6)
+#define DCPCR7_1 (DVDEC1.DCPCR7)
+#define DCPCR8_1 (DVDEC1.DCPCR8)
+#define NSDCR_1 (DVDEC1.NSDCR)
+#define BTLCR_1 (DVDEC1.BTLCR)
+#define BTGPCR_1 (DVDEC1.BTGPCR)
+#define ACCCR1_1 (DVDEC1.ACCCR1)
+#define ACCCR2_1 (DVDEC1.ACCCR2)
+#define ACCCR3_1 (DVDEC1.ACCCR3)
+#define TINTCR_1 (DVDEC1.TINTCR)
+#define YCDCR_1 (DVDEC1.YCDCR)
+#define AGCCR1_1 (DVDEC1.AGCCR1)
+#define AGCCR2_1 (DVDEC1.AGCCR2)
+#define PKLIMITCR_1 (DVDEC1.PKLIMITCR)
+#define RGORCR1_1 (DVDEC1.RGORCR1)
+#define RGORCR2_1 (DVDEC1.RGORCR2)
+#define RGORCR3_1 (DVDEC1.RGORCR3)
+#define RGORCR4_1 (DVDEC1.RGORCR4)
+#define RGORCR5_1 (DVDEC1.RGORCR5)
+#define RGORCR6_1 (DVDEC1.RGORCR6)
+#define RGORCR7_1 (DVDEC1.RGORCR7)
+#define AFCPFCR_1 (DVDEC1.AFCPFCR)
+#define RUPDCR_1 (DVDEC1.RUPDCR)
+#define VSYNCSR_1 (DVDEC1.VSYNCSR)
+#define HSYNCSR_1 (DVDEC1.HSYNCSR)
+#define DCPSR1_1 (DVDEC1.DCPSR1)
+#define DCPSR2_1 (DVDEC1.DCPSR2)
+#define NSDSR_1 (DVDEC1.NSDSR)
+#define CROMASR1_1 (DVDEC1.CROMASR1)
+#define CROMASR2_1 (DVDEC1.CROMASR2)
+#define SYNCSSR_1 (DVDEC1.SYNCSSR)
+#define AGCCSR1_1 (DVDEC1.AGCCSR1)
+#define AGCCSR2_1 (DVDEC1.AGCCSR2)
+#define YCSCR3_1 (DVDEC1.YCSCR3)
+#define YCSCR4_1 (DVDEC1.YCSCR4)
+#define YCSCR5_1 (DVDEC1.YCSCR5)
+#define YCSCR6_1 (DVDEC1.YCSCR6)
+#define YCSCR7_1 (DVDEC1.YCSCR7)
+#define YCSCR8_1 (DVDEC1.YCSCR8)
+#define YCSCR9_1 (DVDEC1.YCSCR9)
+#define YCSCR11_1 (DVDEC1.YCSCR11)
+#define YCSCR12_1 (DVDEC1.YCSCR12)
+#define DCPCR9_1 (DVDEC1.DCPCR9)
+#define YCTWA_F0_1 (DVDEC1.YCTWA_F0)
+#define YCTWA_F1_1 (DVDEC1.YCTWA_F1)
+#define YCTWA_F2_1 (DVDEC1.YCTWA_F2)
+#define YCTWA_F3_1 (DVDEC1.YCTWA_F3)
+#define YCTWA_F4_1 (DVDEC1.YCTWA_F4)
+#define YCTWA_F5_1 (DVDEC1.YCTWA_F5)
+#define YCTWA_F6_1 (DVDEC1.YCTWA_F6)
+#define YCTWA_F7_1 (DVDEC1.YCTWA_F7)
+#define YCTWA_F8_1 (DVDEC1.YCTWA_F8)
+#define YCTWB_F0_1 (DVDEC1.YCTWB_F0)
+#define YCTWB_F1_1 (DVDEC1.YCTWB_F1)
+#define YCTWB_F2_1 (DVDEC1.YCTWB_F2)
+#define YCTWB_F3_1 (DVDEC1.YCTWB_F3)
+#define YCTWB_F4_1 (DVDEC1.YCTWB_F4)
+#define YCTWB_F5_1 (DVDEC1.YCTWB_F5)
+#define YCTWB_F6_1 (DVDEC1.YCTWB_F6)
+#define YCTWB_F7_1 (DVDEC1.YCTWB_F7)
+#define YCTWB_F8_1 (DVDEC1.YCTWB_F8)
+#define YCTNA_F0_1 (DVDEC1.YCTNA_F0)
+#define YCTNA_F1_1 (DVDEC1.YCTNA_F1)
+#define YCTNA_F2_1 (DVDEC1.YCTNA_F2)
+#define YCTNA_F3_1 (DVDEC1.YCTNA_F3)
+#define YCTNA_F4_1 (DVDEC1.YCTNA_F4)
+#define YCTNA_F5_1 (DVDEC1.YCTNA_F5)
+#define YCTNA_F6_1 (DVDEC1.YCTNA_F6)
+#define YCTNA_F7_1 (DVDEC1.YCTNA_F7)
+#define YCTNA_F8_1 (DVDEC1.YCTNA_F8)
+#define YCTNB_F0_1 (DVDEC1.YCTNB_F0)
+#define YCTNB_F1_1 (DVDEC1.YCTNB_F1)
+#define YCTNB_F2_1 (DVDEC1.YCTNB_F2)
+#define YCTNB_F3_1 (DVDEC1.YCTNB_F3)
+#define YCTNB_F4_1 (DVDEC1.YCTNB_F4)
+#define YCTNB_F5_1 (DVDEC1.YCTNB_F5)
+#define YCTNB_F6_1 (DVDEC1.YCTNB_F6)
+#define YCTNB_F7_1 (DVDEC1.YCTNB_F7)
+#define YCTNB_F8_1 (DVDEC1.YCTNB_F8)
+#define YGAINCR_1 (DVDEC1.YGAINCR)
+#define CBGAINCR_1 (DVDEC1.CBGAINCR)
+#define CRGAINCR_1 (DVDEC1.CRGAINCR)
+#define PGA_UPDATE_1 (DVDEC1.PGA_UPDATE)
+#define PGACR_1 (DVDEC1.PGACR)
+#define ADCCR2_1 (DVDEC1.ADCCR2)
+#define ADCCR1_0 (DVDEC0.ADCCR1)
+#define TGCR1_0 (DVDEC0.TGCR1)
+#define TGCR2_0 (DVDEC0.TGCR2)
+#define TGCR3_0 (DVDEC0.TGCR3)
+#define SYNSCR1_0 (DVDEC0.SYNSCR1)
+#define SYNSCR2_0 (DVDEC0.SYNSCR2)
+#define SYNSCR3_0 (DVDEC0.SYNSCR3)
+#define SYNSCR4_0 (DVDEC0.SYNSCR4)
+#define SYNSCR5_0 (DVDEC0.SYNSCR5)
+#define HAFCCR1_0 (DVDEC0.HAFCCR1)
+#define HAFCCR2_0 (DVDEC0.HAFCCR2)
+#define HAFCCR3_0 (DVDEC0.HAFCCR3)
+#define VCDWCR1_0 (DVDEC0.VCDWCR1)
+#define DCPCR1_0 (DVDEC0.DCPCR1)
+#define DCPCR2_0 (DVDEC0.DCPCR2)
+#define DCPCR3_0 (DVDEC0.DCPCR3)
+#define DCPCR4_0 (DVDEC0.DCPCR4)
+#define DCPCR5_0 (DVDEC0.DCPCR5)
+#define DCPCR6_0 (DVDEC0.DCPCR6)
+#define DCPCR7_0 (DVDEC0.DCPCR7)
+#define DCPCR8_0 (DVDEC0.DCPCR8)
+#define NSDCR_0 (DVDEC0.NSDCR)
+#define BTLCR_0 (DVDEC0.BTLCR)
+#define BTGPCR_0 (DVDEC0.BTGPCR)
+#define ACCCR1_0 (DVDEC0.ACCCR1)
+#define ACCCR2_0 (DVDEC0.ACCCR2)
+#define ACCCR3_0 (DVDEC0.ACCCR3)
+#define TINTCR_0 (DVDEC0.TINTCR)
+#define YCDCR_0 (DVDEC0.YCDCR)
+#define AGCCR1_0 (DVDEC0.AGCCR1)
+#define AGCCR2_0 (DVDEC0.AGCCR2)
+#define PKLIMITCR_0 (DVDEC0.PKLIMITCR)
+#define RGORCR1_0 (DVDEC0.RGORCR1)
+#define RGORCR2_0 (DVDEC0.RGORCR2)
+#define RGORCR3_0 (DVDEC0.RGORCR3)
+#define RGORCR4_0 (DVDEC0.RGORCR4)
+#define RGORCR5_0 (DVDEC0.RGORCR5)
+#define RGORCR6_0 (DVDEC0.RGORCR6)
+#define RGORCR7_0 (DVDEC0.RGORCR7)
+#define AFCPFCR_0 (DVDEC0.AFCPFCR)
+#define RUPDCR_0 (DVDEC0.RUPDCR)
+#define VSYNCSR_0 (DVDEC0.VSYNCSR)
+#define HSYNCSR_0 (DVDEC0.HSYNCSR)
+#define DCPSR1_0 (DVDEC0.DCPSR1)
+#define DCPSR2_0 (DVDEC0.DCPSR2)
+#define NSDSR_0 (DVDEC0.NSDSR)
+#define CROMASR1_0 (DVDEC0.CROMASR1)
+#define CROMASR2_0 (DVDEC0.CROMASR2)
+#define SYNCSSR_0 (DVDEC0.SYNCSSR)
+#define AGCCSR1_0 (DVDEC0.AGCCSR1)
+#define AGCCSR2_0 (DVDEC0.AGCCSR2)
+#define YCSCR3_0 (DVDEC0.YCSCR3)
+#define YCSCR4_0 (DVDEC0.YCSCR4)
+#define YCSCR5_0 (DVDEC0.YCSCR5)
+#define YCSCR6_0 (DVDEC0.YCSCR6)
+#define YCSCR7_0 (DVDEC0.YCSCR7)
+#define YCSCR8_0 (DVDEC0.YCSCR8)
+#define YCSCR9_0 (DVDEC0.YCSCR9)
+#define YCSCR11_0 (DVDEC0.YCSCR11)
+#define YCSCR12_0 (DVDEC0.YCSCR12)
+#define DCPCR9_0 (DVDEC0.DCPCR9)
+#define YCTWA_F0_0 (DVDEC0.YCTWA_F0)
+#define YCTWA_F1_0 (DVDEC0.YCTWA_F1)
+#define YCTWA_F2_0 (DVDEC0.YCTWA_F2)
+#define YCTWA_F3_0 (DVDEC0.YCTWA_F3)
+#define YCTWA_F4_0 (DVDEC0.YCTWA_F4)
+#define YCTWA_F5_0 (DVDEC0.YCTWA_F5)
+#define YCTWA_F6_0 (DVDEC0.YCTWA_F6)
+#define YCTWA_F7_0 (DVDEC0.YCTWA_F7)
+#define YCTWA_F8_0 (DVDEC0.YCTWA_F8)
+#define YCTWB_F0_0 (DVDEC0.YCTWB_F0)
+#define YCTWB_F1_0 (DVDEC0.YCTWB_F1)
+#define YCTWB_F2_0 (DVDEC0.YCTWB_F2)
+#define YCTWB_F3_0 (DVDEC0.YCTWB_F3)
+#define YCTWB_F4_0 (DVDEC0.YCTWB_F4)
+#define YCTWB_F5_0 (DVDEC0.YCTWB_F5)
+#define YCTWB_F6_0 (DVDEC0.YCTWB_F6)
+#define YCTWB_F7_0 (DVDEC0.YCTWB_F7)
+#define YCTWB_F8_0 (DVDEC0.YCTWB_F8)
+#define YCTNA_F0_0 (DVDEC0.YCTNA_F0)
+#define YCTNA_F1_0 (DVDEC0.YCTNA_F1)
+#define YCTNA_F2_0 (DVDEC0.YCTNA_F2)
+#define YCTNA_F3_0 (DVDEC0.YCTNA_F3)
+#define YCTNA_F4_0 (DVDEC0.YCTNA_F4)
+#define YCTNA_F5_0 (DVDEC0.YCTNA_F5)
+#define YCTNA_F6_0 (DVDEC0.YCTNA_F6)
+#define YCTNA_F7_0 (DVDEC0.YCTNA_F7)
+#define YCTNA_F8_0 (DVDEC0.YCTNA_F8)
+#define YCTNB_F0_0 (DVDEC0.YCTNB_F0)
+#define YCTNB_F1_0 (DVDEC0.YCTNB_F1)
+#define YCTNB_F2_0 (DVDEC0.YCTNB_F2)
+#define YCTNB_F3_0 (DVDEC0.YCTNB_F3)
+#define YCTNB_F4_0 (DVDEC0.YCTNB_F4)
+#define YCTNB_F5_0 (DVDEC0.YCTNB_F5)
+#define YCTNB_F6_0 (DVDEC0.YCTNB_F6)
+#define YCTNB_F7_0 (DVDEC0.YCTNB_F7)
+#define YCTNB_F8_0 (DVDEC0.YCTNB_F8)
+#define YGAINCR_0 (DVDEC0.YGAINCR)
+#define CBGAINCR_0 (DVDEC0.CBGAINCR)
+#define CRGAINCR_0 (DVDEC0.CRGAINCR)
+#define PGA_UPDATE_0 (DVDEC0.PGA_UPDATE)
+#define PGACR_0 (DVDEC0.PGACR)
+#define ADCCR2_0 (DVDEC0.ADCCR2)
+
+#define DVDEC_TGCRn_COUNT (3)
+#define DVDEC_SYNSCRn_COUNT (5)
+#define DVDEC_HAFCCRn_COUNT (3)
+#define DVDEC_DCPCRn_COUNT (8)
+#define DVDEC_ACCCRn_COUNT (3)
+#define DVDEC_AGCCRn_COUNT (2)
+#define DVDEC_RGORCRn_COUNT (7)
+#define DVDEC_DCPSRn_COUNT (2)
+#define DVDEC_CROMASRn_COUNT (2)
+#define DVDEC_AGCCSRn_COUNT (2)
+#define DVDEC_YCSCRn_COUNT (7)
+#define DVDEC_YCTWA_Fn_COUNT (9)
+#define DVDEC_YCTWB_Fn_COUNT (9)
+#define DVDEC_YCTNA_Fn_COUNT (9)
+#define DVDEC_YCTNB_Fn_COUNT (9)
+
+
+typedef struct st_dvdec
+{
+                                                           /* DVDEC            */
     volatile uint16_t ADCCR1;                                 /*  ADCCR1          */
     volatile uint8_t   dummy1[4];                              /*                  */
-#define DVDEC_TGCRn_COUNT 3
+
+/* #define DVDEC_TGCRn_COUNT (3) */
     volatile uint16_t TGCR1;                                  /*  TGCR1           */
     volatile uint16_t TGCR2;                                  /*  TGCR2           */
     volatile uint16_t TGCR3;                                  /*  TGCR3           */
     volatile uint8_t   dummy2[6];                              /*                  */
-#define DVDEC_SYNSCRn_COUNT 5
+
+/* #define DVDEC_SYNSCRn_COUNT (5) */
     volatile uint16_t SYNSCR1;                                /*  SYNSCR1         */
     volatile uint16_t SYNSCR2;                                /*  SYNSCR2         */
     volatile uint16_t SYNSCR3;                                /*  SYNSCR3         */
     volatile uint16_t SYNSCR4;                                /*  SYNSCR4         */
     volatile uint16_t SYNSCR5;                                /*  SYNSCR5         */
-#define DVDEC_HAFCCRn_COUNT 3
+
+/* #define DVDEC_HAFCCRn_COUNT (3) */
     volatile uint16_t HAFCCR1;                                /*  HAFCCR1         */
     volatile uint16_t HAFCCR2;                                /*  HAFCCR2         */
     volatile uint16_t HAFCCR3;                                /*  HAFCCR3         */
     volatile uint16_t VCDWCR1;                                /*  VCDWCR1         */
     volatile uint8_t   dummy3[4];                              /*                  */
-#define DVDEC_DCPCRn_COUNT 8
+
+/* #define DVDEC_DCPCRn_COUNT (8) */
     volatile uint16_t DCPCR1;                                 /*  DCPCR1          */
     volatile uint16_t DCPCR2;                                 /*  DCPCR2          */
     volatile uint16_t DCPCR3;                                 /*  DCPCR3          */
@@ -63,17 +312,20 @@
     volatile uint16_t NSDCR;                                  /*  NSDCR           */
     volatile uint16_t BTLCR;                                  /*  BTLCR           */
     volatile uint16_t BTGPCR;                                 /*  BTGPCR          */
-#define DVDEC_ACCCRn_COUNT 3
+
+/* #define DVDEC_ACCCRn_COUNT (3) */
     volatile uint16_t ACCCR1;                                 /*  ACCCR1          */
     volatile uint16_t ACCCR2;                                 /*  ACCCR2          */
     volatile uint16_t ACCCR3;                                 /*  ACCCR3          */
     volatile uint16_t TINTCR;                                 /*  TINTCR          */
     volatile uint16_t YCDCR;                                  /*  YCDCR           */
-#define DVDEC_AGCCRn_COUNT 2
+
+/* #define DVDEC_AGCCRn_COUNT (2) */
     volatile uint16_t AGCCR1;                                 /*  AGCCR1          */
     volatile uint16_t AGCCR2;                                 /*  AGCCR2          */
     volatile uint16_t PKLIMITCR;                              /*  PKLIMITCR       */
-#define DVDEC_RGORCRn_COUNT 7
+
+/* #define DVDEC_RGORCRn_COUNT (7) */
     volatile uint16_t RGORCR1;                                /*  RGORCR1         */
     volatile uint16_t RGORCR2;                                /*  RGORCR2         */
     volatile uint16_t RGORCR3;                                /*  RGORCR3         */
@@ -86,20 +338,24 @@
     volatile uint16_t RUPDCR;                                 /*  RUPDCR          */
     volatile uint16_t VSYNCSR;                                /*  VSYNCSR         */
     volatile uint16_t HSYNCSR;                                /*  HSYNCSR         */
-#define DVDEC_DCPSRn_COUNT 2
+
+/* #define DVDEC_DCPSRn_COUNT (2) */
     volatile uint16_t DCPSR1;                                 /*  DCPSR1          */
     volatile uint16_t DCPSR2;                                 /*  DCPSR2          */
     volatile uint8_t   dummy5[4];                              /*                  */
     volatile uint16_t NSDSR;                                  /*  NSDSR           */
-#define DVDEC_CROMASRn_COUNT 2
+
+/* #define DVDEC_CROMASRn_COUNT (2) */
     volatile uint16_t CROMASR1;                               /*  CROMASR1        */
     volatile uint16_t CROMASR2;                               /*  CROMASR2        */
     volatile uint16_t SYNCSSR;                                /*  SYNCSSR         */
-#define DVDEC_AGCCSRn_COUNT 2
+
+/* #define DVDEC_AGCCSRn_COUNT (2) */
     volatile uint16_t AGCCSR1;                                /*  AGCCSR1         */
     volatile uint16_t AGCCSR2;                                /*  AGCCSR2         */
     volatile uint8_t   dummy6[108];                            /*                  */
-#define DVDEC_YCSCRn_COUNT 7
+
+/* #define DVDEC_YCSCRn_COUNT (7) */
     volatile uint16_t YCSCR3;                                 /*  YCSCR3          */
     volatile uint16_t YCSCR4;                                 /*  YCSCR4          */
     volatile uint16_t YCSCR5;                                 /*  YCSCR5          */
@@ -113,7 +369,8 @@
     volatile uint8_t   dummy8[104];                            /*                  */
     volatile uint16_t DCPCR9;                                 /*  DCPCR9          */
     volatile uint8_t   dummy9[16];                             /*                  */
-#define DVDEC_YCTWA_Fn_COUNT 9
+
+/* #define DVDEC_YCTWA_Fn_COUNT (9) */
     volatile uint16_t YCTWA_F0;                               /*  YCTWA_F0        */
     volatile uint16_t YCTWA_F1;                               /*  YCTWA_F1        */
     volatile uint16_t YCTWA_F2;                               /*  YCTWA_F2        */
@@ -123,7 +380,8 @@
     volatile uint16_t YCTWA_F6;                               /*  YCTWA_F6        */
     volatile uint16_t YCTWA_F7;                               /*  YCTWA_F7        */
     volatile uint16_t YCTWA_F8;                               /*  YCTWA_F8        */
-#define DVDEC_YCTWB_Fn_COUNT 9
+
+/* #define DVDEC_YCTWB_Fn_COUNT (9) */
     volatile uint16_t YCTWB_F0;                               /*  YCTWB_F0        */
     volatile uint16_t YCTWB_F1;                               /*  YCTWB_F1        */
     volatile uint16_t YCTWB_F2;                               /*  YCTWB_F2        */
@@ -133,7 +391,8 @@
     volatile uint16_t YCTWB_F6;                               /*  YCTWB_F6        */
     volatile uint16_t YCTWB_F7;                               /*  YCTWB_F7        */
     volatile uint16_t YCTWB_F8;                               /*  YCTWB_F8        */
-#define DVDEC_YCTNA_Fn_COUNT 9
+
+/* #define DVDEC_YCTNA_Fn_COUNT (9) */
     volatile uint16_t YCTNA_F0;                               /*  YCTNA_F0        */
     volatile uint16_t YCTNA_F1;                               /*  YCTNA_F1        */
     volatile uint16_t YCTNA_F2;                               /*  YCTNA_F2        */
@@ -143,7 +402,8 @@
     volatile uint16_t YCTNA_F6;                               /*  YCTNA_F6        */
     volatile uint16_t YCTNA_F7;                               /*  YCTNA_F7        */
     volatile uint16_t YCTNA_F8;                               /*  YCTNA_F8        */
-#define DVDEC_YCTNB_Fn_COUNT 9
+
+/* #define DVDEC_YCTNB_Fn_COUNT (9) */
     volatile uint16_t YCTNB_F0;                               /*  YCTNB_F0        */
     volatile uint16_t YCTNB_F1;                               /*  YCTNB_F1        */
     volatile uint16_t YCTNB_F2;                               /*  YCTNB_F2        */
@@ -161,231 +421,21 @@
     volatile uint16_t PGA_UPDATE;                             /*  PGA_UPDATE      */
     volatile uint16_t PGACR;                                  /*  PGACR           */
     volatile uint16_t ADCCR2;                                 /*  ADCCR2          */
-};
-
-
-#define DVDEC1  (*(struct st_dvdec   *)0xFCFFA008uL) /* DVDEC1 */
-#define DVDEC0  (*(struct st_dvdec   *)0xFCFFB808uL) /* DVDEC0 */
-
-
-/* Start of channnel array defines of DVDEC */
-
-/* Channnel array defines of DVDEC */
-/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
-#define DVDEC_COUNT  2
-#define DVDEC_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &DVDEC0, &DVDEC1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of DVDEC */
+} r_io_dvdec_t;
 
 
-#define ADCCR1_1 DVDEC1.ADCCR1
-#define TGCR1_1 DVDEC1.TGCR1
-#define TGCR2_1 DVDEC1.TGCR2
-#define TGCR3_1 DVDEC1.TGCR3
-#define SYNSCR1_1 DVDEC1.SYNSCR1
-#define SYNSCR2_1 DVDEC1.SYNSCR2
-#define SYNSCR3_1 DVDEC1.SYNSCR3
-#define SYNSCR4_1 DVDEC1.SYNSCR4
-#define SYNSCR5_1 DVDEC1.SYNSCR5
-#define HAFCCR1_1 DVDEC1.HAFCCR1
-#define HAFCCR2_1 DVDEC1.HAFCCR2
-#define HAFCCR3_1 DVDEC1.HAFCCR3
-#define VCDWCR1_1 DVDEC1.VCDWCR1
-#define DCPCR1_1 DVDEC1.DCPCR1
-#define DCPCR2_1 DVDEC1.DCPCR2
-#define DCPCR3_1 DVDEC1.DCPCR3
-#define DCPCR4_1 DVDEC1.DCPCR4
-#define DCPCR5_1 DVDEC1.DCPCR5
-#define DCPCR6_1 DVDEC1.DCPCR6
-#define DCPCR7_1 DVDEC1.DCPCR7
-#define DCPCR8_1 DVDEC1.DCPCR8
-#define NSDCR_1 DVDEC1.NSDCR
-#define BTLCR_1 DVDEC1.BTLCR
-#define BTGPCR_1 DVDEC1.BTGPCR
-#define ACCCR1_1 DVDEC1.ACCCR1
-#define ACCCR2_1 DVDEC1.ACCCR2
-#define ACCCR3_1 DVDEC1.ACCCR3
-#define TINTCR_1 DVDEC1.TINTCR
-#define YCDCR_1 DVDEC1.YCDCR
-#define AGCCR1_1 DVDEC1.AGCCR1
-#define AGCCR2_1 DVDEC1.AGCCR2
-#define PKLIMITCR_1 DVDEC1.PKLIMITCR
-#define RGORCR1_1 DVDEC1.RGORCR1
-#define RGORCR2_1 DVDEC1.RGORCR2
-#define RGORCR3_1 DVDEC1.RGORCR3
-#define RGORCR4_1 DVDEC1.RGORCR4
-#define RGORCR5_1 DVDEC1.RGORCR5
-#define RGORCR6_1 DVDEC1.RGORCR6
-#define RGORCR7_1 DVDEC1.RGORCR7
-#define AFCPFCR_1 DVDEC1.AFCPFCR
-#define RUPDCR_1 DVDEC1.RUPDCR
-#define VSYNCSR_1 DVDEC1.VSYNCSR
-#define HSYNCSR_1 DVDEC1.HSYNCSR
-#define DCPSR1_1 DVDEC1.DCPSR1
-#define DCPSR2_1 DVDEC1.DCPSR2
-#define NSDSR_1 DVDEC1.NSDSR
-#define CROMASR1_1 DVDEC1.CROMASR1
-#define CROMASR2_1 DVDEC1.CROMASR2
-#define SYNCSSR_1 DVDEC1.SYNCSSR
-#define AGCCSR1_1 DVDEC1.AGCCSR1
-#define AGCCSR2_1 DVDEC1.AGCCSR2
-#define YCSCR3_1 DVDEC1.YCSCR3
-#define YCSCR4_1 DVDEC1.YCSCR4
-#define YCSCR5_1 DVDEC1.YCSCR5
-#define YCSCR6_1 DVDEC1.YCSCR6
-#define YCSCR7_1 DVDEC1.YCSCR7
-#define YCSCR8_1 DVDEC1.YCSCR8
-#define YCSCR9_1 DVDEC1.YCSCR9
-#define YCSCR11_1 DVDEC1.YCSCR11
-#define YCSCR12_1 DVDEC1.YCSCR12
-#define DCPCR9_1 DVDEC1.DCPCR9
-#define YCTWA_F0_1 DVDEC1.YCTWA_F0
-#define YCTWA_F1_1 DVDEC1.YCTWA_F1
-#define YCTWA_F2_1 DVDEC1.YCTWA_F2
-#define YCTWA_F3_1 DVDEC1.YCTWA_F3
-#define YCTWA_F4_1 DVDEC1.YCTWA_F4
-#define YCTWA_F5_1 DVDEC1.YCTWA_F5
-#define YCTWA_F6_1 DVDEC1.YCTWA_F6
-#define YCTWA_F7_1 DVDEC1.YCTWA_F7
-#define YCTWA_F8_1 DVDEC1.YCTWA_F8
-#define YCTWB_F0_1 DVDEC1.YCTWB_F0
-#define YCTWB_F1_1 DVDEC1.YCTWB_F1
-#define YCTWB_F2_1 DVDEC1.YCTWB_F2
-#define YCTWB_F3_1 DVDEC1.YCTWB_F3
-#define YCTWB_F4_1 DVDEC1.YCTWB_F4
-#define YCTWB_F5_1 DVDEC1.YCTWB_F5
-#define YCTWB_F6_1 DVDEC1.YCTWB_F6
-#define YCTWB_F7_1 DVDEC1.YCTWB_F7
-#define YCTWB_F8_1 DVDEC1.YCTWB_F8
-#define YCTNA_F0_1 DVDEC1.YCTNA_F0
-#define YCTNA_F1_1 DVDEC1.YCTNA_F1
-#define YCTNA_F2_1 DVDEC1.YCTNA_F2
-#define YCTNA_F3_1 DVDEC1.YCTNA_F3
-#define YCTNA_F4_1 DVDEC1.YCTNA_F4
-#define YCTNA_F5_1 DVDEC1.YCTNA_F5
-#define YCTNA_F6_1 DVDEC1.YCTNA_F6
-#define YCTNA_F7_1 DVDEC1.YCTNA_F7
-#define YCTNA_F8_1 DVDEC1.YCTNA_F8
-#define YCTNB_F0_1 DVDEC1.YCTNB_F0
-#define YCTNB_F1_1 DVDEC1.YCTNB_F1
-#define YCTNB_F2_1 DVDEC1.YCTNB_F2
-#define YCTNB_F3_1 DVDEC1.YCTNB_F3
-#define YCTNB_F4_1 DVDEC1.YCTNB_F4
-#define YCTNB_F5_1 DVDEC1.YCTNB_F5
-#define YCTNB_F6_1 DVDEC1.YCTNB_F6
-#define YCTNB_F7_1 DVDEC1.YCTNB_F7
-#define YCTNB_F8_1 DVDEC1.YCTNB_F8
-#define YGAINCR_1 DVDEC1.YGAINCR
-#define CBGAINCR_1 DVDEC1.CBGAINCR
-#define CRGAINCR_1 DVDEC1.CRGAINCR
-#define PGA_UPDATE_1 DVDEC1.PGA_UPDATE
-#define PGACR_1 DVDEC1.PGACR
-#define ADCCR2_1 DVDEC1.ADCCR2
-#define ADCCR1_0 DVDEC0.ADCCR1
-#define TGCR1_0 DVDEC0.TGCR1
-#define TGCR2_0 DVDEC0.TGCR2
-#define TGCR3_0 DVDEC0.TGCR3
-#define SYNSCR1_0 DVDEC0.SYNSCR1
-#define SYNSCR2_0 DVDEC0.SYNSCR2
-#define SYNSCR3_0 DVDEC0.SYNSCR3
-#define SYNSCR4_0 DVDEC0.SYNSCR4
-#define SYNSCR5_0 DVDEC0.SYNSCR5
-#define HAFCCR1_0 DVDEC0.HAFCCR1
-#define HAFCCR2_0 DVDEC0.HAFCCR2
-#define HAFCCR3_0 DVDEC0.HAFCCR3
-#define VCDWCR1_0 DVDEC0.VCDWCR1
-#define DCPCR1_0 DVDEC0.DCPCR1
-#define DCPCR2_0 DVDEC0.DCPCR2
-#define DCPCR3_0 DVDEC0.DCPCR3
-#define DCPCR4_0 DVDEC0.DCPCR4
-#define DCPCR5_0 DVDEC0.DCPCR5
-#define DCPCR6_0 DVDEC0.DCPCR6
-#define DCPCR7_0 DVDEC0.DCPCR7
-#define DCPCR8_0 DVDEC0.DCPCR8
-#define NSDCR_0 DVDEC0.NSDCR
-#define BTLCR_0 DVDEC0.BTLCR
-#define BTGPCR_0 DVDEC0.BTGPCR
-#define ACCCR1_0 DVDEC0.ACCCR1
-#define ACCCR2_0 DVDEC0.ACCCR2
-#define ACCCR3_0 DVDEC0.ACCCR3
-#define TINTCR_0 DVDEC0.TINTCR
-#define YCDCR_0 DVDEC0.YCDCR
-#define AGCCR1_0 DVDEC0.AGCCR1
-#define AGCCR2_0 DVDEC0.AGCCR2
-#define PKLIMITCR_0 DVDEC0.PKLIMITCR
-#define RGORCR1_0 DVDEC0.RGORCR1
-#define RGORCR2_0 DVDEC0.RGORCR2
-#define RGORCR3_0 DVDEC0.RGORCR3
-#define RGORCR4_0 DVDEC0.RGORCR4
-#define RGORCR5_0 DVDEC0.RGORCR5
-#define RGORCR6_0 DVDEC0.RGORCR6
-#define RGORCR7_0 DVDEC0.RGORCR7
-#define AFCPFCR_0 DVDEC0.AFCPFCR
-#define RUPDCR_0 DVDEC0.RUPDCR
-#define VSYNCSR_0 DVDEC0.VSYNCSR
-#define HSYNCSR_0 DVDEC0.HSYNCSR
-#define DCPSR1_0 DVDEC0.DCPSR1
-#define DCPSR2_0 DVDEC0.DCPSR2
-#define NSDSR_0 DVDEC0.NSDSR
-#define CROMASR1_0 DVDEC0.CROMASR1
-#define CROMASR2_0 DVDEC0.CROMASR2
-#define SYNCSSR_0 DVDEC0.SYNCSSR
-#define AGCCSR1_0 DVDEC0.AGCCSR1
-#define AGCCSR2_0 DVDEC0.AGCCSR2
-#define YCSCR3_0 DVDEC0.YCSCR3
-#define YCSCR4_0 DVDEC0.YCSCR4
-#define YCSCR5_0 DVDEC0.YCSCR5
-#define YCSCR6_0 DVDEC0.YCSCR6
-#define YCSCR7_0 DVDEC0.YCSCR7
-#define YCSCR8_0 DVDEC0.YCSCR8
-#define YCSCR9_0 DVDEC0.YCSCR9
-#define YCSCR11_0 DVDEC0.YCSCR11
-#define YCSCR12_0 DVDEC0.YCSCR12
-#define DCPCR9_0 DVDEC0.DCPCR9
-#define YCTWA_F0_0 DVDEC0.YCTWA_F0
-#define YCTWA_F1_0 DVDEC0.YCTWA_F1
-#define YCTWA_F2_0 DVDEC0.YCTWA_F2
-#define YCTWA_F3_0 DVDEC0.YCTWA_F3
-#define YCTWA_F4_0 DVDEC0.YCTWA_F4
-#define YCTWA_F5_0 DVDEC0.YCTWA_F5
-#define YCTWA_F6_0 DVDEC0.YCTWA_F6
-#define YCTWA_F7_0 DVDEC0.YCTWA_F7
-#define YCTWA_F8_0 DVDEC0.YCTWA_F8
-#define YCTWB_F0_0 DVDEC0.YCTWB_F0
-#define YCTWB_F1_0 DVDEC0.YCTWB_F1
-#define YCTWB_F2_0 DVDEC0.YCTWB_F2
-#define YCTWB_F3_0 DVDEC0.YCTWB_F3
-#define YCTWB_F4_0 DVDEC0.YCTWB_F4
-#define YCTWB_F5_0 DVDEC0.YCTWB_F5
-#define YCTWB_F6_0 DVDEC0.YCTWB_F6
-#define YCTWB_F7_0 DVDEC0.YCTWB_F7
-#define YCTWB_F8_0 DVDEC0.YCTWB_F8
-#define YCTNA_F0_0 DVDEC0.YCTNA_F0
-#define YCTNA_F1_0 DVDEC0.YCTNA_F1
-#define YCTNA_F2_0 DVDEC0.YCTNA_F2
-#define YCTNA_F3_0 DVDEC0.YCTNA_F3
-#define YCTNA_F4_0 DVDEC0.YCTNA_F4
-#define YCTNA_F5_0 DVDEC0.YCTNA_F5
-#define YCTNA_F6_0 DVDEC0.YCTNA_F6
-#define YCTNA_F7_0 DVDEC0.YCTNA_F7
-#define YCTNA_F8_0 DVDEC0.YCTNA_F8
-#define YCTNB_F0_0 DVDEC0.YCTNB_F0
-#define YCTNB_F1_0 DVDEC0.YCTNB_F1
-#define YCTNB_F2_0 DVDEC0.YCTNB_F2
-#define YCTNB_F3_0 DVDEC0.YCTNB_F3
-#define YCTNB_F4_0 DVDEC0.YCTNB_F4
-#define YCTNB_F5_0 DVDEC0.YCTNB_F5
-#define YCTNB_F6_0 DVDEC0.YCTNB_F6
-#define YCTNB_F7_0 DVDEC0.YCTNB_F7
-#define YCTNB_F8_0 DVDEC0.YCTNB_F8
-#define YGAINCR_0 DVDEC0.YGAINCR
-#define CBGAINCR_0 DVDEC0.CBGAINCR
-#define CRGAINCR_0 DVDEC0.CRGAINCR
-#define PGA_UPDATE_0 DVDEC0.PGA_UPDATE
-#define PGACR_0 DVDEC0.PGACR
-#define ADCCR2_0 DVDEC0.ADCCR2
+/* Channel array defines of DVDEC (2)*/
+#ifdef  DECLARE_DVDEC_CHANNELS
+volatile struct st_dvdec*  DVDEC[ DVDEC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    DVDEC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_DVDEC_CHANNELS */
+/* End of channel array defines of DVDEC (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,21 +18,192 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : ether_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef ETHER_IODEFINE_H
 #define ETHER_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_ether
-{                                                          /* ETHER            */
+#define ETHER   (*(struct st_ether   *)0xE8203000uL) /* ETHER */
+
+
+/* Start of channel array defines of ETHER */
+
+/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
+/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
+#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT  (32)
+#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
+    &ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
+    &ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
+    &ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
+#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
+#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
+#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
+#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
+#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
+#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
+#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
+#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
+#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
+#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
+#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
+#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
+#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
+#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
+#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
+#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
+#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
+#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
+#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
+#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
+#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
+#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
+#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
+#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
+#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
+#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
+#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
+#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
+#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
+#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
+#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
+
+/* End of channel array defines of ETHER */
+
+
+#define ETHEREDSR0 (ETHER.EDSR0)
+#define ETHERTDLAR0 (ETHER.TDLAR0)
+#define ETHERTDFAR0 (ETHER.TDFAR0)
+#define ETHERTDFXR0 (ETHER.TDFXR0)
+#define ETHERTDFFR0 (ETHER.TDFFR0)
+#define ETHERRDLAR0 (ETHER.RDLAR0)
+#define ETHERRDFAR0 (ETHER.RDFAR0)
+#define ETHERRDFXR0 (ETHER.RDFXR0)
+#define ETHERRDFFR0 (ETHER.RDFFR0)
+#define ETHEREDMR0 (ETHER.EDMR0)
+#define ETHEREDTRR0 (ETHER.EDTRR0)
+#define ETHEREDRRR0 (ETHER.EDRRR0)
+#define ETHEREESR0 (ETHER.EESR0)
+#define ETHEREESIPR0 (ETHER.EESIPR0)
+#define ETHERTRSCER0 (ETHER.TRSCER0)
+#define ETHERRMFCR0 (ETHER.RMFCR0)
+#define ETHERTFTR0 (ETHER.TFTR0)
+#define ETHERFDR0 (ETHER.FDR0)
+#define ETHERRMCR0 (ETHER.RMCR0)
+#define ETHERRPADIR0 (ETHER.RPADIR0)
+#define ETHERFCFTR0 (ETHER.FCFTR0)
+#define ETHERCSMR (ETHER.CSMR)
+#define ETHERCSSBM (ETHER.CSSBM)
+#define ETHERCSSMR (ETHER.CSSMR)
+#define ETHERECMR0 (ETHER.ECMR0)
+#define ETHERRFLR0 (ETHER.RFLR0)
+#define ETHERECSR0 (ETHER.ECSR0)
+#define ETHERECSIPR0 (ETHER.ECSIPR0)
+#define ETHERPIR0 (ETHER.PIR0)
+#define ETHERAPR0 (ETHER.APR0)
+#define ETHERMPR0 (ETHER.MPR0)
+#define ETHERPFTCR0 (ETHER.PFTCR0)
+#define ETHERPFRCR0 (ETHER.PFRCR0)
+#define ETHERTPAUSER0 (ETHER.TPAUSER0)
+#define ETHERMAHR0 (ETHER.MAHR0)
+#define ETHERMALR0 (ETHER.MALR0)
+#define ETHERCEFCR0 (ETHER.CEFCR0)
+#define ETHERFRECR0 (ETHER.FRECR0)
+#define ETHERTSFRCR0 (ETHER.TSFRCR0)
+#define ETHERTLFRCR0 (ETHER.TLFRCR0)
+#define ETHERRFCR0 (ETHER.RFCR0)
+#define ETHERMAFCR0 (ETHER.MAFCR0)
+#define ETHERARSTR (ETHER.ARSTR)
+#define ETHERTSU_CTRST (ETHER.TSU_CTRST)
+#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0)
+#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY)
+#define ETHERTSU_TEN (ETHER.TSU_TEN)
+#define ETHERTXNLCR0 (ETHER.TXNLCR0)
+#define ETHERTXALCR0 (ETHER.TXALCR0)
+#define ETHERRXNLCR0 (ETHER.RXNLCR0)
+#define ETHERRXALCR0 (ETHER.RXALCR0)
+#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0)
+#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0)
+#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1)
+#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1)
+#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2)
+#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2)
+#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3)
+#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3)
+#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4)
+#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4)
+#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5)
+#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5)
+#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6)
+#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6)
+#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7)
+#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7)
+#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8)
+#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8)
+#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9)
+#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9)
+#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10)
+#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10)
+#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11)
+#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11)
+#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12)
+#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12)
+#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13)
+#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13)
+#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14)
+#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14)
+#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15)
+#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15)
+#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16)
+#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16)
+#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17)
+#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17)
+#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18)
+#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18)
+#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19)
+#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19)
+#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20)
+#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20)
+#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21)
+#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21)
+#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22)
+#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22)
+#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23)
+#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23)
+#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24)
+#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24)
+#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25)
+#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25)
+#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26)
+#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26)
+#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27)
+#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27)
+#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28)
+#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28)
+#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29)
+#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29)
+#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30)
+#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30)
+#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31)
+#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31)
+
+
+typedef struct st_ether
+{
+                                                           /* ETHER            */
     volatile uint32_t  EDSR0;                                  /*  EDSR0           */
     volatile uint8_t   dummy207[12];                           /*                  */
     volatile uint32_t  TDLAR0;                                 /*  TDLAR0          */
@@ -118,310 +289,221 @@
     volatile uint32_t  RXNLCR0;                                /*  RXNLCR0         */
     volatile uint32_t  RXALCR0;                                /*  RXALCR0         */
     volatile uint8_t   dummy240[112];                          /*                  */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
     volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH1;                              /*  TSU_ADRH1       */
     volatile uint32_t  TSU_ADRL1;                              /*  TSU_ADRL1       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH2;                              /*  TSU_ADRH2       */
     volatile uint32_t  TSU_ADRL2;                              /*  TSU_ADRL2       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH3;                              /*  TSU_ADRH3       */
     volatile uint32_t  TSU_ADRL3;                              /*  TSU_ADRL3       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH4;                              /*  TSU_ADRH4       */
     volatile uint32_t  TSU_ADRL4;                              /*  TSU_ADRL4       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH5;                              /*  TSU_ADRH5       */
     volatile uint32_t  TSU_ADRL5;                              /*  TSU_ADRL5       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH6;                              /*  TSU_ADRH6       */
     volatile uint32_t  TSU_ADRL6;                              /*  TSU_ADRL6       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH7;                              /*  TSU_ADRH7       */
     volatile uint32_t  TSU_ADRL7;                              /*  TSU_ADRL7       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH8;                              /*  TSU_ADRH8       */
     volatile uint32_t  TSU_ADRL8;                              /*  TSU_ADRL8       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH9;                              /*  TSU_ADRH9       */
     volatile uint32_t  TSU_ADRL9;                              /*  TSU_ADRL9       */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH10;                             /*  TSU_ADRH10      */
     volatile uint32_t  TSU_ADRL10;                             /*  TSU_ADRL10      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH11;                             /*  TSU_ADRH11      */
     volatile uint32_t  TSU_ADRL11;                             /*  TSU_ADRL11      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH12;                             /*  TSU_ADRH12      */
     volatile uint32_t  TSU_ADRL12;                             /*  TSU_ADRL12      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH13;                             /*  TSU_ADRH13      */
     volatile uint32_t  TSU_ADRL13;                             /*  TSU_ADRL13      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH14;                             /*  TSU_ADRH14      */
     volatile uint32_t  TSU_ADRL14;                             /*  TSU_ADRL14      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH15;                             /*  TSU_ADRH15      */
     volatile uint32_t  TSU_ADRL15;                             /*  TSU_ADRL15      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH16;                             /*  TSU_ADRH16      */
     volatile uint32_t  TSU_ADRL16;                             /*  TSU_ADRL16      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH17;                             /*  TSU_ADRH17      */
     volatile uint32_t  TSU_ADRL17;                             /*  TSU_ADRL17      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH18;                             /*  TSU_ADRH18      */
     volatile uint32_t  TSU_ADRL18;                             /*  TSU_ADRL18      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH19;                             /*  TSU_ADRH19      */
     volatile uint32_t  TSU_ADRL19;                             /*  TSU_ADRL19      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH20;                             /*  TSU_ADRH20      */
     volatile uint32_t  TSU_ADRL20;                             /*  TSU_ADRL20      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH21;                             /*  TSU_ADRH21      */
     volatile uint32_t  TSU_ADRL21;                             /*  TSU_ADRL21      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH22;                             /*  TSU_ADRH22      */
     volatile uint32_t  TSU_ADRL22;                             /*  TSU_ADRL22      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH23;                             /*  TSU_ADRH23      */
     volatile uint32_t  TSU_ADRL23;                             /*  TSU_ADRL23      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH24;                             /*  TSU_ADRH24      */
     volatile uint32_t  TSU_ADRL24;                             /*  TSU_ADRL24      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH25;                             /*  TSU_ADRH25      */
     volatile uint32_t  TSU_ADRL25;                             /*  TSU_ADRL25      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH26;                             /*  TSU_ADRH26      */
     volatile uint32_t  TSU_ADRL26;                             /*  TSU_ADRL26      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH27;                             /*  TSU_ADRH27      */
     volatile uint32_t  TSU_ADRL27;                             /*  TSU_ADRL27      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH28;                             /*  TSU_ADRH28      */
     volatile uint32_t  TSU_ADRL28;                             /*  TSU_ADRL28      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH29;                             /*  TSU_ADRH29      */
     volatile uint32_t  TSU_ADRL29;                             /*  TSU_ADRL29      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH30;                             /*  TSU_ADRH30      */
     volatile uint32_t  TSU_ADRL30;                             /*  TSU_ADRL30      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
+
 /* start of struct st_ether_from_tsu_adrh0 */
     volatile uint32_t  TSU_ADRH31;                             /*  TSU_ADRH31      */
     volatile uint32_t  TSU_ADRL31;                             /*  TSU_ADRL31      */
+
 /* end of struct st_ether_from_tsu_adrh0 */
-};
-
-
-struct st_ether_from_tsu_adrh0
-{
-    volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
-    volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
-};
-
-
-#define ETHER   (*(struct st_ether   *)0xE8203000uL) /* ETHER */
+} r_io_ether_t;
 
 
-/* Start of channnel array defines of ETHER */
-
-/* Channnel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
-/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
-#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT  32
-#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
-    &ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
-    &ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
-    &ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
-#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
-#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
-#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
-#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
-#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
-#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
-#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
-#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
-#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
-#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
-#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
-#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
-#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
-#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
-#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
-#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
-#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
-#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
-#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
-#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
-#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
-#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
-#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
-#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
-#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
-#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
-#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
-#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
-#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
-#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
-#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
-
-/* End of channnel array defines of ETHER */
+typedef struct st_ether_from_tsu_adrh0
+{
+ 
+    volatile uint32_t  TSU_ADRH0;                              /*  TSU_ADRH0       */
+    volatile uint32_t  TSU_ADRL0;                              /*  TSU_ADRL0       */
+} r_io_ether_from_tsu_adrh0_t;
 
 
-#define ETHEREDSR0 ETHER.EDSR0
-#define ETHERTDLAR0 ETHER.TDLAR0
-#define ETHERTDFAR0 ETHER.TDFAR0
-#define ETHERTDFXR0 ETHER.TDFXR0
-#define ETHERTDFFR0 ETHER.TDFFR0
-#define ETHERRDLAR0 ETHER.RDLAR0
-#define ETHERRDFAR0 ETHER.RDFAR0
-#define ETHERRDFXR0 ETHER.RDFXR0
-#define ETHERRDFFR0 ETHER.RDFFR0
-#define ETHEREDMR0 ETHER.EDMR0
-#define ETHEREDTRR0 ETHER.EDTRR0
-#define ETHEREDRRR0 ETHER.EDRRR0
-#define ETHEREESR0 ETHER.EESR0
-#define ETHEREESIPR0 ETHER.EESIPR0
-#define ETHERTRSCER0 ETHER.TRSCER0
-#define ETHERRMFCR0 ETHER.RMFCR0
-#define ETHERTFTR0 ETHER.TFTR0
-#define ETHERFDR0 ETHER.FDR0
-#define ETHERRMCR0 ETHER.RMCR0
-#define ETHERRPADIR0 ETHER.RPADIR0
-#define ETHERFCFTR0 ETHER.FCFTR0
-#define ETHERCSMR ETHER.CSMR
-#define ETHERCSSBM ETHER.CSSBM
-#define ETHERCSSMR ETHER.CSSMR
-#define ETHERECMR0 ETHER.ECMR0
-#define ETHERRFLR0 ETHER.RFLR0
-#define ETHERECSR0 ETHER.ECSR0
-#define ETHERECSIPR0 ETHER.ECSIPR0
-#define ETHERPIR0 ETHER.PIR0
-#define ETHERAPR0 ETHER.APR0
-#define ETHERMPR0 ETHER.MPR0
-#define ETHERPFTCR0 ETHER.PFTCR0
-#define ETHERPFRCR0 ETHER.PFRCR0
-#define ETHERTPAUSER0 ETHER.TPAUSER0
-#define ETHERMAHR0 ETHER.MAHR0
-#define ETHERMALR0 ETHER.MALR0
-#define ETHERCEFCR0 ETHER.CEFCR0
-#define ETHERFRECR0 ETHER.FRECR0
-#define ETHERTSFRCR0 ETHER.TSFRCR0
-#define ETHERTLFRCR0 ETHER.TLFRCR0
-#define ETHERRFCR0 ETHER.RFCR0
-#define ETHERMAFCR0 ETHER.MAFCR0
-#define ETHERARSTR ETHER.ARSTR
-#define ETHERTSU_CTRST ETHER.TSU_CTRST
-#define ETHERTSU_VTAG0 ETHER.TSU_VTAG0
-#define ETHERTSU_ADSBSY ETHER.TSU_ADSBSY
-#define ETHERTSU_TEN ETHER.TSU_TEN
-#define ETHERTXNLCR0 ETHER.TXNLCR0
-#define ETHERTXALCR0 ETHER.TXALCR0
-#define ETHERRXNLCR0 ETHER.RXNLCR0
-#define ETHERRXALCR0 ETHER.RXALCR0
-#define ETHERTSU_ADRH0 ETHER.TSU_ADRH0
-#define ETHERTSU_ADRL0 ETHER.TSU_ADRL0
-#define ETHERTSU_ADRH1 ETHER.TSU_ADRH1
-#define ETHERTSU_ADRL1 ETHER.TSU_ADRL1
-#define ETHERTSU_ADRH2 ETHER.TSU_ADRH2
-#define ETHERTSU_ADRL2 ETHER.TSU_ADRL2
-#define ETHERTSU_ADRH3 ETHER.TSU_ADRH3
-#define ETHERTSU_ADRL3 ETHER.TSU_ADRL3
-#define ETHERTSU_ADRH4 ETHER.TSU_ADRH4
-#define ETHERTSU_ADRL4 ETHER.TSU_ADRL4
-#define ETHERTSU_ADRH5 ETHER.TSU_ADRH5
-#define ETHERTSU_ADRL5 ETHER.TSU_ADRL5
-#define ETHERTSU_ADRH6 ETHER.TSU_ADRH6
-#define ETHERTSU_ADRL6 ETHER.TSU_ADRL6
-#define ETHERTSU_ADRH7 ETHER.TSU_ADRH7
-#define ETHERTSU_ADRL7 ETHER.TSU_ADRL7
-#define ETHERTSU_ADRH8 ETHER.TSU_ADRH8
-#define ETHERTSU_ADRL8 ETHER.TSU_ADRL8
-#define ETHERTSU_ADRH9 ETHER.TSU_ADRH9
-#define ETHERTSU_ADRL9 ETHER.TSU_ADRL9
-#define ETHERTSU_ADRH10 ETHER.TSU_ADRH10
-#define ETHERTSU_ADRL10 ETHER.TSU_ADRL10
-#define ETHERTSU_ADRH11 ETHER.TSU_ADRH11
-#define ETHERTSU_ADRL11 ETHER.TSU_ADRL11
-#define ETHERTSU_ADRH12 ETHER.TSU_ADRH12
-#define ETHERTSU_ADRL12 ETHER.TSU_ADRL12
-#define ETHERTSU_ADRH13 ETHER.TSU_ADRH13
-#define ETHERTSU_ADRL13 ETHER.TSU_ADRL13
-#define ETHERTSU_ADRH14 ETHER.TSU_ADRH14
-#define ETHERTSU_ADRL14 ETHER.TSU_ADRL14
-#define ETHERTSU_ADRH15 ETHER.TSU_ADRH15
-#define ETHERTSU_ADRL15 ETHER.TSU_ADRL15
-#define ETHERTSU_ADRH16 ETHER.TSU_ADRH16
-#define ETHERTSU_ADRL16 ETHER.TSU_ADRL16
-#define ETHERTSU_ADRH17 ETHER.TSU_ADRH17
-#define ETHERTSU_ADRL17 ETHER.TSU_ADRL17
-#define ETHERTSU_ADRH18 ETHER.TSU_ADRH18
-#define ETHERTSU_ADRL18 ETHER.TSU_ADRL18
-#define ETHERTSU_ADRH19 ETHER.TSU_ADRH19
-#define ETHERTSU_ADRL19 ETHER.TSU_ADRL19
-#define ETHERTSU_ADRH20 ETHER.TSU_ADRH20
-#define ETHERTSU_ADRL20 ETHER.TSU_ADRL20
-#define ETHERTSU_ADRH21 ETHER.TSU_ADRH21
-#define ETHERTSU_ADRL21 ETHER.TSU_ADRL21
-#define ETHERTSU_ADRH22 ETHER.TSU_ADRH22
-#define ETHERTSU_ADRL22 ETHER.TSU_ADRL22
-#define ETHERTSU_ADRH23 ETHER.TSU_ADRH23
-#define ETHERTSU_ADRL23 ETHER.TSU_ADRL23
-#define ETHERTSU_ADRH24 ETHER.TSU_ADRH24
-#define ETHERTSU_ADRL24 ETHER.TSU_ADRL24
-#define ETHERTSU_ADRH25 ETHER.TSU_ADRH25
-#define ETHERTSU_ADRL25 ETHER.TSU_ADRL25
-#define ETHERTSU_ADRH26 ETHER.TSU_ADRH26
-#define ETHERTSU_ADRL26 ETHER.TSU_ADRL26
-#define ETHERTSU_ADRH27 ETHER.TSU_ADRH27
-#define ETHERTSU_ADRL27 ETHER.TSU_ADRL27
-#define ETHERTSU_ADRH28 ETHER.TSU_ADRH28
-#define ETHERTSU_ADRL28 ETHER.TSU_ADRL28
-#define ETHERTSU_ADRH29 ETHER.TSU_ADRH29
-#define ETHERTSU_ADRL29 ETHER.TSU_ADRL29
-#define ETHERTSU_ADRH30 ETHER.TSU_ADRH30
-#define ETHERTSU_ADRL30 ETHER.TSU_ADRL30
-#define ETHERTSU_ADRH31 ETHER.TSU_ADRH31
-#define ETHERTSU_ADRL31 ETHER.TSU_ADRL31
+/* Channel array defines of ETHER (2)*/
+#ifdef  DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS
+volatile struct st_ether_from_tsu_adrh0*  ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */
+/* End of channel array defines of ETHER (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/flctl_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,41 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : flctl_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef FLCTL_IODEFINE_H
 #define FLCTL_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_flctl
-{                                                          /* FLCTL            */
+#define FLCTL   (*(struct st_flctl   *)0xFCFF4000uL) /* FLCTL */
+
+
+#define FLCTLFLCMNCR (FLCTL.FLCMNCR)
+#define FLCTLFLCMDCR (FLCTL.FLCMDCR)
+#define FLCTLFLCMCDR (FLCTL.FLCMCDR)
+#define FLCTLFLADR (FLCTL.FLADR)
+#define FLCTLFLDATAR (FLCTL.FLDATAR)
+#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR)
+#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR)
+#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR)
+#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT)
+#define FLCTLFLTRCR (FLCTL.FLTRCR)
+#define FLCTLFLADR2 (FLCTL.FLADR2)
+#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO)
+
+
+typedef struct st_flctl
+{
+                                                           /* FLCTL            */
     volatile uint32_t  FLCMNCR;                                /*  FLCMNCR         */
     volatile uint32_t  FLCMDCR;                                /*  FLCMDCR         */
     volatile uint32_t  FLCMCDR;                                /*  FLCMCDR         */
@@ -47,26 +68,11 @@
     volatile uint32_t  FLADR2;                                 /*  FLADR2          */
     volatile uint8_t   dummy557[16];                           /*                  */
     volatile uint32_t  FLDTFIFO;                               /*  FLDTFIFO        */
-    volatile uint8_t   dummy558[12];                           /*                  */
-    volatile uint32_t  FLECFIFO;                               /*  FLECFIFO        */
-};
-
-
-#define FLCTL   (*(struct st_flctl   *)0xFCFF4000uL) /* FLCTL */
+} r_io_flctl_t;
 
 
-#define FLCTLFLCMNCR FLCTL.FLCMNCR
-#define FLCTLFLCMDCR FLCTL.FLCMDCR
-#define FLCTLFLCMCDR FLCTL.FLCMCDR
-#define FLCTLFLADR FLCTL.FLADR
-#define FLCTLFLDATAR FLCTL.FLDATAR
-#define FLCTLFLDTCNTR FLCTL.FLDTCNTR
-#define FLCTLFLINTDMACR FLCTL.FLINTDMACR
-#define FLCTLFLBSYTMR FLCTL.FLBSYTMR
-#define FLCTLFLBSYCNT FLCTL.FLBSYCNT
-#define FLCTLFLTRCR FLCTL.FLTRCR
-#define FLCTLFLADR2 FLCTL.FLADR2
-#define FLCTLFLDTFIFO FLCTL.FLDTFIFO
-#define FLCTLFLECFIFO FLCTL.FLECFIFO
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/gpio_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,662 +18,29 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : gpio_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef GPIO_IODEFINE_H
 #define GPIO_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_gpio
-{                                                          /* GPIO             */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P1;                                     /*  P1              */
-    volatile uint8_t   dummy348[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P2;                                     /*  P2              */
-    volatile uint8_t   dummy349[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P3;                                     /*  P3              */
-    volatile uint8_t   dummy350[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P4;                                     /*  P4              */
-    volatile uint8_t   dummy351[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P5;                                     /*  P5              */
-    volatile uint8_t   dummy352[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P6;                                     /*  P6              */
-    volatile uint8_t   dummy353[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P7;                                     /*  P7              */
-    volatile uint8_t   dummy354[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P8;                                     /*  P8              */
-    volatile uint8_t   dummy355[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P9;                                     /*  P9              */
-    volatile uint8_t   dummy356[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P10;                                    /*  P10             */
-    volatile uint8_t   dummy357[2];                            /*                  */
-/* end of struct st_gpio_from_p1 */
-/* start of struct st_gpio_from_p1 */
-    volatile uint16_t P11;                                    /*  P11             */
-    volatile uint8_t   dummy3580[2];                           /*                  */
-/* end of struct st_gpio_from_p1 */
-    volatile uint8_t   dummy3581[212];                         /*                  */
-#define GPIO_PSRn_COUNT 11
-    volatile uint32_t  PSR1;                                   /*  PSR1            */
-    volatile uint32_t  PSR2;                                   /*  PSR2            */
-    volatile uint32_t  PSR3;                                   /*  PSR3            */
-    volatile uint32_t  PSR4;                                   /*  PSR4            */
-    volatile uint32_t  PSR5;                                   /*  PSR5            */
-    volatile uint32_t  PSR6;                                   /*  PSR6            */
-    volatile uint32_t  PSR7;                                   /*  PSR7            */
-    volatile uint32_t  PSR8;                                   /*  PSR8            */
-    volatile uint32_t  PSR9;                                   /*  PSR9            */
-    volatile uint32_t  PSR10;                                  /*  PSR10           */
-    volatile uint32_t  PSR11;                                  /*  PSR11           */
-    volatile uint8_t   dummy359[208];                          /*                  */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR0;                                   /*  PPR0            */
-    volatile uint8_t   dummy360[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR1;                                   /*  PPR1            */
-    volatile uint8_t   dummy361[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR2;                                   /*  PPR2            */
-    volatile uint8_t   dummy362[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR3;                                   /*  PPR3            */
-    volatile uint8_t   dummy363[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR4;                                   /*  PPR4            */
-    volatile uint8_t   dummy364[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR5;                                   /*  PPR5            */
-    volatile uint8_t   dummy365[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR6;                                   /*  PPR6            */
-    volatile uint8_t   dummy366[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR7;                                   /*  PPR7            */
-    volatile uint8_t   dummy367[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR8;                                   /*  PPR8            */
-    volatile uint8_t   dummy368[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR9;                                   /*  PPR9            */
-    volatile uint8_t   dummy369[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR10;                                  /*  PPR10           */
-    volatile uint8_t   dummy370[2];                            /*                  */
-/* end of struct st_gpio_from_ppr0 */
-/* start of struct st_gpio_from_ppr0 */
-    volatile uint16_t PPR11;                                  /*  PPR11           */
-    volatile uint8_t   dummy3710[2];                           /*                  */
-/* end of struct st_gpio_from_ppr0 */
-    volatile uint8_t   dummy3711[212];                         /*                  */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM1;                                    /*  PM1             */
-    volatile uint8_t   dummy372[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM2;                                    /*  PM2             */
-    volatile uint8_t   dummy373[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM3;                                    /*  PM3             */
-    volatile uint8_t   dummy374[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM4;                                    /*  PM4             */
-    volatile uint8_t   dummy375[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM5;                                    /*  PM5             */
-    volatile uint8_t   dummy376[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM6;                                    /*  PM6             */
-    volatile uint8_t   dummy377[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM7;                                    /*  PM7             */
-    volatile uint8_t   dummy378[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM8;                                    /*  PM8             */
-    volatile uint8_t   dummy379[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM9;                                    /*  PM9             */
-    volatile uint8_t   dummy380[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM10;                                   /*  PM10            */
-    volatile uint8_t   dummy381[2];                            /*                  */
-/* end of struct st_gpio_from_pm1 */
-/* start of struct st_gpio_from_pm1 */
-    volatile uint16_t PM11;                                   /*  PM11            */
-    volatile uint8_t   dummy3820[2];                           /*                  */
-/* end of struct st_gpio_from_pm1 */
-    volatile uint8_t   dummy3821[208];                         /*                  */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC0;                                   /*  PMC0            */
-    volatile uint8_t   dummy383[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC1;                                   /*  PMC1            */
-    volatile uint8_t   dummy384[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC2;                                   /*  PMC2            */
-    volatile uint8_t   dummy385[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC3;                                   /*  PMC3            */
-    volatile uint8_t   dummy386[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC4;                                   /*  PMC4            */
-    volatile uint8_t   dummy387[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC5;                                   /*  PMC5            */
-    volatile uint8_t   dummy388[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC6;                                   /*  PMC6            */
-    volatile uint8_t   dummy389[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC7;                                   /*  PMC7            */
-    volatile uint8_t   dummy390[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC8;                                   /*  PMC8            */
-    volatile uint8_t   dummy391[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC9;                                   /*  PMC9            */
-    volatile uint8_t   dummy392[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC10;                                  /*  PMC10           */
-    volatile uint8_t   dummy393[2];                            /*                  */
-/* end of struct st_gpio_from_pmc0 */
-/* start of struct st_gpio_from_pmc0 */
-    volatile uint16_t PMC11;                                  /*  PMC11           */
-    volatile uint8_t   dummy3940[2];                           /*                  */
-/* end of struct st_gpio_from_pmc0 */
-    volatile uint8_t   dummy3941[212];                         /*                  */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC1;                                   /*  PFC1            */
-    volatile uint8_t   dummy395[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC2;                                   /*  PFC2            */
-    volatile uint8_t   dummy396[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC3;                                   /*  PFC3            */
-    volatile uint8_t   dummy397[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC4;                                   /*  PFC4            */
-    volatile uint8_t   dummy398[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC5;                                   /*  PFC5            */
-    volatile uint8_t   dummy399[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC6;                                   /*  PFC6            */
-    volatile uint8_t   dummy400[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC7;                                   /*  PFC7            */
-    volatile uint8_t   dummy401[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC8;                                   /*  PFC8            */
-    volatile uint8_t   dummy402[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC9;                                   /*  PFC9            */
-    volatile uint8_t   dummy403[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC10;                                  /*  PFC10           */
-    volatile uint8_t   dummy404[2];                            /*                  */
-/* end of struct st_gpio_from_pfc1 */
-/* start of struct st_gpio_from_pfc1 */
-    volatile uint16_t PFC11;                                  /*  PFC11           */
-    volatile uint8_t   dummy4050[2];                           /*                  */
-/* end of struct st_gpio_from_pfc1 */
-    volatile uint8_t   dummy4051[212];                         /*                  */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE1;                                  /*  PFCE1           */
-    volatile uint8_t   dummy406[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE2;                                  /*  PFCE2           */
-    volatile uint8_t   dummy407[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE3;                                  /*  PFCE3           */
-    volatile uint8_t   dummy408[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE4;                                  /*  PFCE4           */
-    volatile uint8_t   dummy409[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE5;                                  /*  PFCE5           */
-    volatile uint8_t   dummy410[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE6;                                  /*  PFCE6           */
-    volatile uint8_t   dummy411[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE7;                                  /*  PFCE7           */
-    volatile uint8_t   dummy412[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE8;                                  /*  PFCE8           */
-    volatile uint8_t   dummy413[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE9;                                  /*  PFCE9           */
-    volatile uint8_t   dummy414[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE10;                                 /*  PFCE10          */
-    volatile uint8_t   dummy415[2];                            /*                  */
-/* end of struct st_gpio_from_pfce1 */
-/* start of struct st_gpio_from_pfce1 */
-    volatile uint16_t PFCE11;                                 /*  PFCE11          */
-    volatile uint8_t   dummy4160[2];                           /*                  */
-/* end of struct st_gpio_from_pfce1 */
-    volatile uint8_t   dummy4161[212];                         /*                  */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT1;                                  /*  PNOT1           */
-    volatile uint8_t   dummy417[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT2;                                  /*  PNOT2           */
-    volatile uint8_t   dummy418[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT3;                                  /*  PNOT3           */
-    volatile uint8_t   dummy419[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT4;                                  /*  PNOT4           */
-    volatile uint8_t   dummy420[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT5;                                  /*  PNOT5           */
-    volatile uint8_t   dummy421[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT6;                                  /*  PNOT6           */
-    volatile uint8_t   dummy422[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT7;                                  /*  PNOT7           */
-    volatile uint8_t   dummy423[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT8;                                  /*  PNOT8           */
-    volatile uint8_t   dummy424[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT9;                                  /*  PNOT9           */
-    volatile uint8_t   dummy425[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT10;                                 /*  PNOT10          */
-    volatile uint8_t   dummy426[2];                            /*                  */
-/* end of struct st_gpio_from_pnot1 */
-/* start of struct st_gpio_from_pnot1 */
-    volatile uint16_t PNOT11;                                 /*  PNOT11          */
-    volatile uint8_t   dummy4270[2];                           /*                  */
-/* end of struct st_gpio_from_pnot1 */
-    volatile uint8_t   dummy4271[212];                         /*                  */
-#define GPIO_PMSRn_COUNT 11
-    volatile uint32_t  PMSR1;                                  /*  PMSR1           */
-    volatile uint32_t  PMSR2;                                  /*  PMSR2           */
-    volatile uint32_t  PMSR3;                                  /*  PMSR3           */
-    volatile uint32_t  PMSR4;                                  /*  PMSR4           */
-    volatile uint32_t  PMSR5;                                  /*  PMSR5           */
-    volatile uint32_t  PMSR6;                                  /*  PMSR6           */
-    volatile uint32_t  PMSR7;                                  /*  PMSR7           */
-    volatile uint32_t  PMSR8;                                  /*  PMSR8           */
-    volatile uint32_t  PMSR9;                                  /*  PMSR9           */
-    volatile uint32_t  PMSR10;                                 /*  PMSR10          */
-    volatile uint32_t  PMSR11;                                 /*  PMSR11          */
-    volatile uint8_t   dummy428[208];                          /*                  */
-#define GPIO_PMCSRn_COUNT 12
-    volatile uint32_t  PMCSR0;                                 /*  PMCSR0          */
-    volatile uint32_t  PMCSR1;                                 /*  PMCSR1          */
-    volatile uint32_t  PMCSR2;                                 /*  PMCSR2          */
-    volatile uint32_t  PMCSR3;                                 /*  PMCSR3          */
-    volatile uint32_t  PMCSR4;                                 /*  PMCSR4          */
-    volatile uint32_t  PMCSR5;                                 /*  PMCSR5          */
-    volatile uint32_t  PMCSR6;                                 /*  PMCSR6          */
-    volatile uint32_t  PMCSR7;                                 /*  PMCSR7          */
-    volatile uint32_t  PMCSR8;                                 /*  PMCSR8          */
-    volatile uint32_t  PMCSR9;                                 /*  PMCSR9          */
-    volatile uint32_t  PMCSR10;                                /*  PMCSR10         */
-    volatile uint32_t  PMCSR11;                                /*  PMCSR11         */
-    volatile uint8_t   dummy429[212];                          /*                  */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
-    volatile uint8_t   dummy430[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE2;                                 /*  PFCAE2          */
-    volatile uint8_t   dummy431[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE3;                                 /*  PFCAE3          */
-    volatile uint8_t   dummy432[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE4;                                 /*  PFCAE4          */
-    volatile uint8_t   dummy433[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE5;                                 /*  PFCAE5          */
-    volatile uint8_t   dummy434[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE6;                                 /*  PFCAE6          */
-    volatile uint8_t   dummy435[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE7;                                 /*  PFCAE7          */
-    volatile uint8_t   dummy436[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE8;                                 /*  PFCAE8          */
-    volatile uint8_t   dummy437[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE9;                                 /*  PFCAE9          */
-    volatile uint8_t   dummy438[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE10;                                /*  PFCAE10         */
-    volatile uint8_t   dummy439[2];                            /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-/* start of struct st_gpio_from_pfcae1 */
-    volatile uint16_t PFCAE11;                                /*  PFCAE11         */
-    volatile uint8_t   dummy4400[2];                           /*                  */
-/* end of struct st_gpio_from_pfcae1 */
-    volatile uint8_t   dummy4401[464];                         /*                  */
-    volatile uint32_t  SNCR;                                   /*  SNCR            */
-    volatile uint8_t   dummy441[13308];                        /*                  */
-    volatile uint16_t PIBC0;                                  /*  PIBC0           */
-    volatile uint8_t   dummy442[2];                            /*                  */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC1;                                  /*  PIBC1           */
-    volatile uint8_t   dummy443[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC2;                                  /*  PIBC2           */
-    volatile uint8_t   dummy444[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC3;                                  /*  PIBC3           */
-    volatile uint8_t   dummy445[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC4;                                  /*  PIBC4           */
-    volatile uint8_t   dummy446[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC5;                                  /*  PIBC5           */
-    volatile uint8_t   dummy447[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC6;                                  /*  PIBC6           */
-    volatile uint8_t   dummy448[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC7;                                  /*  PIBC7           */
-    volatile uint8_t   dummy449[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC8;                                  /*  PIBC8           */
-    volatile uint8_t   dummy450[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC9;                                  /*  PIBC9           */
-    volatile uint8_t   dummy451[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC10;                                 /*  PIBC10          */
-    volatile uint8_t   dummy452[2];                            /*                  */
-/* end of struct st_gpio_from_pibc1 */
-/* start of struct st_gpio_from_pibc1 */
-    volatile uint16_t PIBC11;                                 /*  PIBC11          */
-    volatile uint8_t   dummy4530[2];                           /*                  */
-/* end of struct st_gpio_from_pibc1 */
-    volatile uint8_t   dummy4531[212];                         /*                  */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC1;                                  /*  PBDC1           */
-    volatile uint8_t   dummy454[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC2;                                  /*  PBDC2           */
-    volatile uint8_t   dummy455[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC3;                                  /*  PBDC3           */
-    volatile uint8_t   dummy456[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC4;                                  /*  PBDC4           */
-    volatile uint8_t   dummy457[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC5;                                  /*  PBDC5           */
-    volatile uint8_t   dummy458[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC6;                                  /*  PBDC6           */
-    volatile uint8_t   dummy459[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC7;                                  /*  PBDC7           */
-    volatile uint8_t   dummy460[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC8;                                  /*  PBDC8           */
-    volatile uint8_t   dummy461[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC9;                                  /*  PBDC9           */
-    volatile uint8_t   dummy462[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC10;                                 /*  PBDC10          */
-    volatile uint8_t   dummy463[2];                            /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-/* start of struct st_gpio_from_pbdc1 */
-    volatile uint16_t PBDC11;                                 /*  PBDC11          */
-    volatile uint8_t   dummy4640[2];                           /*                  */
-/* end of struct st_gpio_from_pbdc1 */
-    volatile uint8_t   dummy4641[212];                         /*                  */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC1;                                  /*  PIPC1           */
-    volatile uint8_t   dummy465[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC2;                                  /*  PIPC2           */
-    volatile uint8_t   dummy466[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC3;                                  /*  PIPC3           */
-    volatile uint8_t   dummy467[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC4;                                  /*  PIPC4           */
-    volatile uint8_t   dummy468[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC5;                                  /*  PIPC5           */
-    volatile uint8_t   dummy469[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC6;                                  /*  PIPC6           */
-    volatile uint8_t   dummy470[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC7;                                  /*  PIPC7           */
-    volatile uint8_t   dummy471[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC8;                                  /*  PIPC8           */
-    volatile uint8_t   dummy472[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC9;                                  /*  PIPC9           */
-    volatile uint8_t   dummy473[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC10;                                 /*  PIPC10          */
-    volatile uint8_t   dummy474[2];                            /*                  */
-/* end of struct st_gpio_from_pipc1 */
-/* start of struct st_gpio_from_pipc1 */
-    volatile uint16_t PIPC11;                                 /*  PIPC11          */
-    volatile uint8_t   dummy4750[2];                           /*                  */
-/* end of struct st_gpio_from_pipc1 */
-    volatile uint8_t   dummy4751[2288];                        /*                  */
-    volatile uint16_t JPPR0;                                  /*  JPPR0           */
-    volatile uint8_t   dummy476[30];                           /*                  */
-    volatile uint16_t JPMC0;                                  /*  JPMC0           */
-    volatile uint8_t   dummy477[78];                           /*                  */
-    volatile uint32_t  JPMCSR0;                                /*  JPMCSR0         */
-    volatile uint8_t   dummy478[876];                          /*                  */
-    volatile uint16_t JPIBC0;                                 /*  JPIBC0          */
-};
-
-
-struct st_gpio_from_p1
-{
-    volatile uint16_t P1;                                     /*  P1              */
-    volatile uint8_t   dummy1[3];                              /*                  */
-};
-
-
-struct st_gpio_from_ppr0
-{
-    volatile uint16_t PPR0;                                   /*  PPR0            */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pm1
-{
-    volatile uint16_t PM1;                                    /*  PM1             */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pmc0
-{
-    volatile uint16_t PMC0;                                   /*  PMC0            */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pfc1
-{
-    volatile uint16_t PFC1;                                   /*  PFC1            */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pfce1
-{
-    volatile uint16_t PFCE1;                                  /*  PFCE1           */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pnot1
-{
-    volatile uint16_t PNOT1;                                  /*  PNOT1           */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pfcae1
-{
-    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pibc1
-{
-    volatile uint16_t PIBC1;                                  /*  PIBC1           */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pbdc1
-{
-    volatile uint16_t PBDC1;                                  /*  PBDC1           */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
-struct st_gpio_from_pipc1
-{
-    volatile uint16_t PIPC1;                                  /*  PIPC1           */
-    volatile uint8_t   dummy1[2];                              /*                  */
-};
-
-
 #define GPIO    (*(struct st_gpio    *)0xFCFE3004uL) /* GPIO */
 
-/* Start of channnel array defines of GPIO */
+
+/* Start of channel array defines of GPIO */
 
-/* Channnel array defines of GPIO_FROM_PIPC1_ARRAY */
+/* Channel array defines of GPIO_FROM_PIPC1_ARRAY */
 /*(Sample) value = GPIO_FROM_PIPC1_ARRAY[ channel ]->PIPC1; */
-#define GPIO_FROM_PIPC1_ARRAY_COUNT  11
+#define GPIO_FROM_PIPC1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PIPC1, &GPIO_FROM_PIPC2, &GPIO_FROM_PIPC3, &GPIO_FROM_PIPC4, &GPIO_FROM_PIPC5, &GPIO_FROM_PIPC6, &GPIO_FROM_PIPC7, &GPIO_FROM_PIPC8, \
@@ -692,9 +59,9 @@
 #define GPIO_FROM_PIPC11 (*(struct st_gpio_from_pipc1 *)&GPIO.PIPC11) /* GPIO_FROM_PIPC11 */
 
 
-/* Channnel array defines of GPIO_FROM_PBDC1_ARRAY */
+/* Channel array defines of GPIO_FROM_PBDC1_ARRAY */
 /*(Sample) value = GPIO_FROM_PBDC1_ARRAY[ channel ]->PBDC1; */
-#define GPIO_FROM_PBDC1_ARRAY_COUNT  11
+#define GPIO_FROM_PBDC1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PBDC1, &GPIO_FROM_PBDC2, &GPIO_FROM_PBDC3, &GPIO_FROM_PBDC4, &GPIO_FROM_PBDC5, &GPIO_FROM_PBDC6, &GPIO_FROM_PBDC7, &GPIO_FROM_PBDC8, \
@@ -713,14 +80,15 @@
 #define GPIO_FROM_PBDC11 (*(struct st_gpio_from_pbdc1 *)&GPIO.PBDC11) /* GPIO_FROM_PBDC11 */
 
 
-/* Channnel array defines of GPIO_FROM_PIBC1_ARRAY */
+/* Channel array defines of GPIO_FROM_PIBC1_ARRAY */
 /*(Sample) value = GPIO_FROM_PIBC1_ARRAY[ channel ]->PIBC1; */
-#define GPIO_FROM_PIBC1_ARRAY_COUNT  11
+#define GPIO_FROM_PIBC1_ARRAY_COUNT  (12)
 #define GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, &GPIO_FROM_PIBC8, \
-    &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
+    &GPIO_FROM_PIBC0, &GPIO_FROM_PIBC1, &GPIO_FROM_PIBC2, &GPIO_FROM_PIBC3, &GPIO_FROM_PIBC4, &GPIO_FROM_PIBC5, &GPIO_FROM_PIBC6, &GPIO_FROM_PIBC7, \
+    &GPIO_FROM_PIBC8, &GPIO_FROM_PIBC9, &GPIO_FROM_PIBC10, &GPIO_FROM_PIBC11 \
 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define GPIO_FROM_PIBC0 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC0) /* GPIO_FROM_PIBC0 */
 #define GPIO_FROM_PIBC1 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC1) /* GPIO_FROM_PIBC1 */
 #define GPIO_FROM_PIBC2 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC2) /* GPIO_FROM_PIBC2 */
 #define GPIO_FROM_PIBC3 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC3) /* GPIO_FROM_PIBC3 */
@@ -734,9 +102,9 @@
 #define GPIO_FROM_PIBC11 (*(struct st_gpio_from_pibc1 *)&GPIO.PIBC11) /* GPIO_FROM_PIBC11 */
 
 
-/* Channnel array defines of GPIO_FROM_PFCAE1_ARRAY */
+/* Channel array defines of GPIO_FROM_PFCAE1_ARRAY */
 /*(Sample) value = GPIO_FROM_PFCAE1_ARRAY[ channel ]->PFCAE1; */
-#define GPIO_FROM_PFCAE1_ARRAY_COUNT  11
+#define GPIO_FROM_PFCAE1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PFCAE1, &GPIO_FROM_PFCAE2, &GPIO_FROM_PFCAE3, &GPIO_FROM_PFCAE4, &GPIO_FROM_PFCAE5, &GPIO_FROM_PFCAE6, &GPIO_FROM_PFCAE7, &GPIO_FROM_PFCAE8, \
@@ -755,9 +123,9 @@
 #define GPIO_FROM_PFCAE11 (*(struct st_gpio_from_pfcae1 *)&GPIO.PFCAE11) /* GPIO_FROM_PFCAE11 */
 
 
-/* Channnel array defines of GPIO_FROM_PNOT1_ARRAY */
+/* Channel array defines of GPIO_FROM_PNOT1_ARRAY */
 /*(Sample) value = GPIO_FROM_PNOT1_ARRAY[ channel ]->PNOT1; */
-#define GPIO_FROM_PNOT1_ARRAY_COUNT  11
+#define GPIO_FROM_PNOT1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PNOT1, &GPIO_FROM_PNOT2, &GPIO_FROM_PNOT3, &GPIO_FROM_PNOT4, &GPIO_FROM_PNOT5, &GPIO_FROM_PNOT6, &GPIO_FROM_PNOT7, &GPIO_FROM_PNOT8, \
@@ -776,9 +144,9 @@
 #define GPIO_FROM_PNOT11 (*(struct st_gpio_from_pnot1 *)&GPIO.PNOT11) /* GPIO_FROM_PNOT11 */
 
 
-/* Channnel array defines of GPIO_FROM_PFCE1_ARRAY */
+/* Channel array defines of GPIO_FROM_PFCE1_ARRAY */
 /*(Sample) value = GPIO_FROM_PFCE1_ARRAY[ channel ]->PFCE1; */
-#define GPIO_FROM_PFCE1_ARRAY_COUNT  11
+#define GPIO_FROM_PFCE1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PFCE1, &GPIO_FROM_PFCE2, &GPIO_FROM_PFCE3, &GPIO_FROM_PFCE4, &GPIO_FROM_PFCE5, &GPIO_FROM_PFCE6, &GPIO_FROM_PFCE7, &GPIO_FROM_PFCE8, \
@@ -797,9 +165,9 @@
 #define GPIO_FROM_PFCE11 (*(struct st_gpio_from_pfce1 *)&GPIO.PFCE11) /* GPIO_FROM_PFCE11 */
 
 
-/* Channnel array defines of GPIO_FROM_PFC1_ARRAY */
+/* Channel array defines of GPIO_FROM_PFC1_ARRAY */
 /*(Sample) value = GPIO_FROM_PFC1_ARRAY[ channel ]->PFC1; */
-#define GPIO_FROM_PFC1_ARRAY_COUNT  11
+#define GPIO_FROM_PFC1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PFC1, &GPIO_FROM_PFC2, &GPIO_FROM_PFC3, &GPIO_FROM_PFC4, &GPIO_FROM_PFC5, &GPIO_FROM_PFC6, &GPIO_FROM_PFC7, &GPIO_FROM_PFC8, \
@@ -818,9 +186,9 @@
 #define GPIO_FROM_PFC11 (*(struct st_gpio_from_pfc1 *)&GPIO.PFC11) /* GPIO_FROM_PFC11 */
 
 
-/* Channnel array defines of GPIO_FROM_PMC0_ARRAY */
+/* Channel array defines of GPIO_FROM_PMC0_ARRAY */
 /*(Sample) value = GPIO_FROM_PMC0_ARRAY[ channel ]->PMC0; */
-#define GPIO_FROM_PMC0_ARRAY_COUNT  12
+#define GPIO_FROM_PMC0_ARRAY_COUNT  (12)
 #define GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PMC0, &GPIO_FROM_PMC1, &GPIO_FROM_PMC2, &GPIO_FROM_PMC3, &GPIO_FROM_PMC4, &GPIO_FROM_PMC5, &GPIO_FROM_PMC6, &GPIO_FROM_PMC7, \
@@ -840,9 +208,9 @@
 #define GPIO_FROM_PMC11 (*(struct st_gpio_from_pmc0 *)&GPIO.PMC11) /* GPIO_FROM_PMC11 */
 
 
-/* Channnel array defines of GPIO_FROM_PM1_ARRAY */
+/* Channel array defines of GPIO_FROM_PM1_ARRAY */
 /*(Sample) value = GPIO_FROM_PM1_ARRAY[ channel ]->PM1; */
-#define GPIO_FROM_PM1_ARRAY_COUNT  11
+#define GPIO_FROM_PM1_ARRAY_COUNT  (11)
 #define GPIO_FROM_PM1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PM1, &GPIO_FROM_PM2, &GPIO_FROM_PM3, &GPIO_FROM_PM4, &GPIO_FROM_PM5, &GPIO_FROM_PM6, &GPIO_FROM_PM7, &GPIO_FROM_PM8, \
@@ -861,9 +229,9 @@
 #define GPIO_FROM_PM11 (*(struct st_gpio_from_pm1 *)&GPIO.PM11)  /* GPIO_FROM_PM11 */
 
 
-/* Channnel array defines of GPIO_FROM_PPR0_ARRAY */
+/* Channel array defines of GPIO_FROM_PPR0_ARRAY */
 /*(Sample) value = GPIO_FROM_PPR0_ARRAY[ channel ]->PPR0; */
-#define GPIO_FROM_PPR0_ARRAY_COUNT  12
+#define GPIO_FROM_PPR0_ARRAY_COUNT  (12)
 #define GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_PPR0, &GPIO_FROM_PPR1, &GPIO_FROM_PPR2, &GPIO_FROM_PPR3, &GPIO_FROM_PPR4, &GPIO_FROM_PPR5, &GPIO_FROM_PPR6, &GPIO_FROM_PPR7, \
@@ -883,9 +251,9 @@
 #define GPIO_FROM_PPR11 (*(struct st_gpio_from_ppr0 *)&GPIO.PPR11) /* GPIO_FROM_PPR11 */
 
 
-/* Channnel array defines of GPIO_FROM_P1_ARRAY */
+/* Channel array defines of GPIO_FROM_P1_ARRAY */
 /*(Sample) value = GPIO_FROM_P1_ARRAY[ channel ]->P1; */
-#define GPIO_FROM_P1_ARRAY_COUNT  11
+#define GPIO_FROM_P1_ARRAY_COUNT  (11)
 #define GPIO_FROM_P1_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &GPIO_FROM_P1, &GPIO_FROM_P2, &GPIO_FROM_P3, &GPIO_FROM_P4, &GPIO_FROM_P5, &GPIO_FROM_P6, &GPIO_FROM_P7, &GPIO_FROM_P8, \
@@ -903,172 +271,1161 @@
 #define GPIO_FROM_P10 (*(struct st_gpio_from_p1 *)&GPIO.P10)     /* GPIO_FROM_P10 */
 #define GPIO_FROM_P11 (*(struct st_gpio_from_p1 *)&GPIO.P11)     /* GPIO_FROM_P11 */
 
-/* End of channnel array defines of GPIO */
+/* End of channel array defines of GPIO */
+
+
+#define GPIOP1 (GPIO.P1)
+#define GPIOP2 (GPIO.P2)
+#define GPIOP3 (GPIO.P3)
+#define GPIOP4 (GPIO.P4)
+#define GPIOP5 (GPIO.P5)
+#define GPIOP6 (GPIO.P6)
+#define GPIOP7 (GPIO.P7)
+#define GPIOP8 (GPIO.P8)
+#define GPIOP9 (GPIO.P9)
+#define GPIOP10 (GPIO.P10)
+#define GPIOP11 (GPIO.P11)
+#define GPIOPSR1 (GPIO.PSR1)
+#define GPIOPSR2 (GPIO.PSR2)
+#define GPIOPSR3 (GPIO.PSR3)
+#define GPIOPSR4 (GPIO.PSR4)
+#define GPIOPSR5 (GPIO.PSR5)
+#define GPIOPSR6 (GPIO.PSR6)
+#define GPIOPSR7 (GPIO.PSR7)
+#define GPIOPSR8 (GPIO.PSR8)
+#define GPIOPSR9 (GPIO.PSR9)
+#define GPIOPSR10 (GPIO.PSR10)
+#define GPIOPSR11 (GPIO.PSR11)
+#define GPIOPPR0 (GPIO.PPR0)
+#define GPIOPPR1 (GPIO.PPR1)
+#define GPIOPPR2 (GPIO.PPR2)
+#define GPIOPPR3 (GPIO.PPR3)
+#define GPIOPPR4 (GPIO.PPR4)
+#define GPIOPPR5 (GPIO.PPR5)
+#define GPIOPPR6 (GPIO.PPR6)
+#define GPIOPPR7 (GPIO.PPR7)
+#define GPIOPPR8 (GPIO.PPR8)
+#define GPIOPPR9 (GPIO.PPR9)
+#define GPIOPPR10 (GPIO.PPR10)
+#define GPIOPPR11 (GPIO.PPR11)
+#define GPIOPM1 (GPIO.PM1)
+#define GPIOPM2 (GPIO.PM2)
+#define GPIOPM3 (GPIO.PM3)
+#define GPIOPM4 (GPIO.PM4)
+#define GPIOPM5 (GPIO.PM5)
+#define GPIOPM6 (GPIO.PM6)
+#define GPIOPM7 (GPIO.PM7)
+#define GPIOPM8 (GPIO.PM8)
+#define GPIOPM9 (GPIO.PM9)
+#define GPIOPM10 (GPIO.PM10)
+#define GPIOPM11 (GPIO.PM11)
+#define GPIOPMC0 (GPIO.PMC0)
+#define GPIOPMC1 (GPIO.PMC1)
+#define GPIOPMC2 (GPIO.PMC2)
+#define GPIOPMC3 (GPIO.PMC3)
+#define GPIOPMC4 (GPIO.PMC4)
+#define GPIOPMC5 (GPIO.PMC5)
+#define GPIOPMC6 (GPIO.PMC6)
+#define GPIOPMC7 (GPIO.PMC7)
+#define GPIOPMC8 (GPIO.PMC8)
+#define GPIOPMC9 (GPIO.PMC9)
+#define GPIOPMC10 (GPIO.PMC10)
+#define GPIOPMC11 (GPIO.PMC11)
+#define GPIOPFC1 (GPIO.PFC1)
+#define GPIOPFC2 (GPIO.PFC2)
+#define GPIOPFC3 (GPIO.PFC3)
+#define GPIOPFC4 (GPIO.PFC4)
+#define GPIOPFC5 (GPIO.PFC5)
+#define GPIOPFC6 (GPIO.PFC6)
+#define GPIOPFC7 (GPIO.PFC7)
+#define GPIOPFC8 (GPIO.PFC8)
+#define GPIOPFC9 (GPIO.PFC9)
+#define GPIOPFC10 (GPIO.PFC10)
+#define GPIOPFC11 (GPIO.PFC11)
+#define GPIOPFCE1 (GPIO.PFCE1)
+#define GPIOPFCE2 (GPIO.PFCE2)
+#define GPIOPFCE3 (GPIO.PFCE3)
+#define GPIOPFCE4 (GPIO.PFCE4)
+#define GPIOPFCE5 (GPIO.PFCE5)
+#define GPIOPFCE6 (GPIO.PFCE6)
+#define GPIOPFCE7 (GPIO.PFCE7)
+#define GPIOPFCE8 (GPIO.PFCE8)
+#define GPIOPFCE9 (GPIO.PFCE9)
+#define GPIOPFCE10 (GPIO.PFCE10)
+#define GPIOPFCE11 (GPIO.PFCE11)
+#define GPIOPNOT1 (GPIO.PNOT1)
+#define GPIOPNOT2 (GPIO.PNOT2)
+#define GPIOPNOT3 (GPIO.PNOT3)
+#define GPIOPNOT4 (GPIO.PNOT4)
+#define GPIOPNOT5 (GPIO.PNOT5)
+#define GPIOPNOT6 (GPIO.PNOT6)
+#define GPIOPNOT7 (GPIO.PNOT7)
+#define GPIOPNOT8 (GPIO.PNOT8)
+#define GPIOPNOT9 (GPIO.PNOT9)
+#define GPIOPNOT10 (GPIO.PNOT10)
+#define GPIOPNOT11 (GPIO.PNOT11)
+#define GPIOPMSR1 (GPIO.PMSR1)
+#define GPIOPMSR2 (GPIO.PMSR2)
+#define GPIOPMSR3 (GPIO.PMSR3)
+#define GPIOPMSR4 (GPIO.PMSR4)
+#define GPIOPMSR5 (GPIO.PMSR5)
+#define GPIOPMSR6 (GPIO.PMSR6)
+#define GPIOPMSR7 (GPIO.PMSR7)
+#define GPIOPMSR8 (GPIO.PMSR8)
+#define GPIOPMSR9 (GPIO.PMSR9)
+#define GPIOPMSR10 (GPIO.PMSR10)
+#define GPIOPMSR11 (GPIO.PMSR11)
+#define GPIOPMCSR0 (GPIO.PMCSR0)
+#define GPIOPMCSR1 (GPIO.PMCSR1)
+#define GPIOPMCSR2 (GPIO.PMCSR2)
+#define GPIOPMCSR3 (GPIO.PMCSR3)
+#define GPIOPMCSR4 (GPIO.PMCSR4)
+#define GPIOPMCSR5 (GPIO.PMCSR5)
+#define GPIOPMCSR6 (GPIO.PMCSR6)
+#define GPIOPMCSR7 (GPIO.PMCSR7)
+#define GPIOPMCSR8 (GPIO.PMCSR8)
+#define GPIOPMCSR9 (GPIO.PMCSR9)
+#define GPIOPMCSR10 (GPIO.PMCSR10)
+#define GPIOPMCSR11 (GPIO.PMCSR11)
+#define GPIOPFCAE1 (GPIO.PFCAE1)
+#define GPIOPFCAE2 (GPIO.PFCAE2)
+#define GPIOPFCAE3 (GPIO.PFCAE3)
+#define GPIOPFCAE4 (GPIO.PFCAE4)
+#define GPIOPFCAE5 (GPIO.PFCAE5)
+#define GPIOPFCAE6 (GPIO.PFCAE6)
+#define GPIOPFCAE7 (GPIO.PFCAE7)
+#define GPIOPFCAE8 (GPIO.PFCAE8)
+#define GPIOPFCAE9 (GPIO.PFCAE9)
+#define GPIOPFCAE10 (GPIO.PFCAE10)
+#define GPIOPFCAE11 (GPIO.PFCAE11)
+#define GPIOSNCR (GPIO.SNCR)
+#define GPIOPIBC0 (GPIO.PIBC0)
+#define GPIOPIBC1 (GPIO.PIBC1)
+#define GPIOPIBC2 (GPIO.PIBC2)
+#define GPIOPIBC3 (GPIO.PIBC3)
+#define GPIOPIBC4 (GPIO.PIBC4)
+#define GPIOPIBC5 (GPIO.PIBC5)
+#define GPIOPIBC6 (GPIO.PIBC6)
+#define GPIOPIBC7 (GPIO.PIBC7)
+#define GPIOPIBC8 (GPIO.PIBC8)
+#define GPIOPIBC9 (GPIO.PIBC9)
+#define GPIOPIBC10 (GPIO.PIBC10)
+#define GPIOPIBC11 (GPIO.PIBC11)
+#define GPIOPBDC1 (GPIO.PBDC1)
+#define GPIOPBDC2 (GPIO.PBDC2)
+#define GPIOPBDC3 (GPIO.PBDC3)
+#define GPIOPBDC4 (GPIO.PBDC4)
+#define GPIOPBDC5 (GPIO.PBDC5)
+#define GPIOPBDC6 (GPIO.PBDC6)
+#define GPIOPBDC7 (GPIO.PBDC7)
+#define GPIOPBDC8 (GPIO.PBDC8)
+#define GPIOPBDC9 (GPIO.PBDC9)
+#define GPIOPBDC10 (GPIO.PBDC10)
+#define GPIOPBDC11 (GPIO.PBDC11)
+#define GPIOPIPC1 (GPIO.PIPC1)
+#define GPIOPIPC2 (GPIO.PIPC2)
+#define GPIOPIPC3 (GPIO.PIPC3)
+#define GPIOPIPC4 (GPIO.PIPC4)
+#define GPIOPIPC5 (GPIO.PIPC5)
+#define GPIOPIPC6 (GPIO.PIPC6)
+#define GPIOPIPC7 (GPIO.PIPC7)
+#define GPIOPIPC8 (GPIO.PIPC8)
+#define GPIOPIPC9 (GPIO.PIPC9)
+#define GPIOPIPC10 (GPIO.PIPC10)
+#define GPIOPIPC11 (GPIO.PIPC11)
+#define GPIOJPPR0 (GPIO.JPPR0)
+#define GPIOJPMC0 (GPIO.JPMC0)
+#define GPIOJPMCSR0 (GPIO.JPMCSR0)
+#define GPIOJPIBC0 (GPIO.JPIBC0)
+
+#define GPIO_PSRn_COUNT (11)
+#define GPIO_PMSRn_COUNT (11)
+#define GPIO_PMCSRn_COUNT (12)
 
 
-#define GPIOP1 GPIO.P1
-#define GPIOP2 GPIO.P2
-#define GPIOP3 GPIO.P3
-#define GPIOP4 GPIO.P4
-#define GPIOP5 GPIO.P5
-#define GPIOP6 GPIO.P6
-#define GPIOP7 GPIO.P7
-#define GPIOP8 GPIO.P8
-#define GPIOP9 GPIO.P9
-#define GPIOP10 GPIO.P10
-#define GPIOP11 GPIO.P11
-#define GPIOPSR1 GPIO.PSR1
-#define GPIOPSR2 GPIO.PSR2
-#define GPIOPSR3 GPIO.PSR3
-#define GPIOPSR4 GPIO.PSR4
-#define GPIOPSR5 GPIO.PSR5
-#define GPIOPSR6 GPIO.PSR6
-#define GPIOPSR7 GPIO.PSR7
-#define GPIOPSR8 GPIO.PSR8
-#define GPIOPSR9 GPIO.PSR9
-#define GPIOPSR10 GPIO.PSR10
-#define GPIOPSR11 GPIO.PSR11
-#define GPIOPPR0 GPIO.PPR0
-#define GPIOPPR1 GPIO.PPR1
-#define GPIOPPR2 GPIO.PPR2
-#define GPIOPPR3 GPIO.PPR3
-#define GPIOPPR4 GPIO.PPR4
-#define GPIOPPR5 GPIO.PPR5
-#define GPIOPPR6 GPIO.PPR6
-#define GPIOPPR7 GPIO.PPR7
-#define GPIOPPR8 GPIO.PPR8
-#define GPIOPPR9 GPIO.PPR9
-#define GPIOPPR10 GPIO.PPR10
-#define GPIOPPR11 GPIO.PPR11
-#define GPIOPM1 GPIO.PM1
-#define GPIOPM2 GPIO.PM2
-#define GPIOPM3 GPIO.PM3
-#define GPIOPM4 GPIO.PM4
-#define GPIOPM5 GPIO.PM5
-#define GPIOPM6 GPIO.PM6
-#define GPIOPM7 GPIO.PM7
-#define GPIOPM8 GPIO.PM8
-#define GPIOPM9 GPIO.PM9
-#define GPIOPM10 GPIO.PM10
-#define GPIOPM11 GPIO.PM11
-#define GPIOPMC0 GPIO.PMC0
-#define GPIOPMC1 GPIO.PMC1
-#define GPIOPMC2 GPIO.PMC2
-#define GPIOPMC3 GPIO.PMC3
-#define GPIOPMC4 GPIO.PMC4
-#define GPIOPMC5 GPIO.PMC5
-#define GPIOPMC6 GPIO.PMC6
-#define GPIOPMC7 GPIO.PMC7
-#define GPIOPMC8 GPIO.PMC8
-#define GPIOPMC9 GPIO.PMC9
-#define GPIOPMC10 GPIO.PMC10
-#define GPIOPMC11 GPIO.PMC11
-#define GPIOPFC1 GPIO.PFC1
-#define GPIOPFC2 GPIO.PFC2
-#define GPIOPFC3 GPIO.PFC3
-#define GPIOPFC4 GPIO.PFC4
-#define GPIOPFC5 GPIO.PFC5
-#define GPIOPFC6 GPIO.PFC6
-#define GPIOPFC7 GPIO.PFC7
-#define GPIOPFC8 GPIO.PFC8
-#define GPIOPFC9 GPIO.PFC9
-#define GPIOPFC10 GPIO.PFC10
-#define GPIOPFC11 GPIO.PFC11
-#define GPIOPFCE1 GPIO.PFCE1
-#define GPIOPFCE2 GPIO.PFCE2
-#define GPIOPFCE3 GPIO.PFCE3
-#define GPIOPFCE4 GPIO.PFCE4
-#define GPIOPFCE5 GPIO.PFCE5
-#define GPIOPFCE6 GPIO.PFCE6
-#define GPIOPFCE7 GPIO.PFCE7
-#define GPIOPFCE8 GPIO.PFCE8
-#define GPIOPFCE9 GPIO.PFCE9
-#define GPIOPFCE10 GPIO.PFCE10
-#define GPIOPFCE11 GPIO.PFCE11
-#define GPIOPNOT1 GPIO.PNOT1
-#define GPIOPNOT2 GPIO.PNOT2
-#define GPIOPNOT3 GPIO.PNOT3
-#define GPIOPNOT4 GPIO.PNOT4
-#define GPIOPNOT5 GPIO.PNOT5
-#define GPIOPNOT6 GPIO.PNOT6
-#define GPIOPNOT7 GPIO.PNOT7
-#define GPIOPNOT8 GPIO.PNOT8
-#define GPIOPNOT9 GPIO.PNOT9
-#define GPIOPNOT10 GPIO.PNOT10
-#define GPIOPNOT11 GPIO.PNOT11
-#define GPIOPMSR1 GPIO.PMSR1
-#define GPIOPMSR2 GPIO.PMSR2
-#define GPIOPMSR3 GPIO.PMSR3
-#define GPIOPMSR4 GPIO.PMSR4
-#define GPIOPMSR5 GPIO.PMSR5
-#define GPIOPMSR6 GPIO.PMSR6
-#define GPIOPMSR7 GPIO.PMSR7
-#define GPIOPMSR8 GPIO.PMSR8
-#define GPIOPMSR9 GPIO.PMSR9
-#define GPIOPMSR10 GPIO.PMSR10
-#define GPIOPMSR11 GPIO.PMSR11
-#define GPIOPMCSR0 GPIO.PMCSR0
-#define GPIOPMCSR1 GPIO.PMCSR1
-#define GPIOPMCSR2 GPIO.PMCSR2
-#define GPIOPMCSR3 GPIO.PMCSR3
-#define GPIOPMCSR4 GPIO.PMCSR4
-#define GPIOPMCSR5 GPIO.PMCSR5
-#define GPIOPMCSR6 GPIO.PMCSR6
-#define GPIOPMCSR7 GPIO.PMCSR7
-#define GPIOPMCSR8 GPIO.PMCSR8
-#define GPIOPMCSR9 GPIO.PMCSR9
-#define GPIOPMCSR10 GPIO.PMCSR10
-#define GPIOPMCSR11 GPIO.PMCSR11
-#define GPIOPFCAE1 GPIO.PFCAE1
-#define GPIOPFCAE2 GPIO.PFCAE2
-#define GPIOPFCAE3 GPIO.PFCAE3
-#define GPIOPFCAE4 GPIO.PFCAE4
-#define GPIOPFCAE5 GPIO.PFCAE5
-#define GPIOPFCAE6 GPIO.PFCAE6
-#define GPIOPFCAE7 GPIO.PFCAE7
-#define GPIOPFCAE8 GPIO.PFCAE8
-#define GPIOPFCAE9 GPIO.PFCAE9
-#define GPIOPFCAE10 GPIO.PFCAE10
-#define GPIOPFCAE11 GPIO.PFCAE11
-#define GPIOSNCR GPIO.SNCR
-#define GPIOPIBC0 GPIO.PIBC0
-#define GPIOPIBC1 GPIO.PIBC1
-#define GPIOPIBC2 GPIO.PIBC2
-#define GPIOPIBC3 GPIO.PIBC3
-#define GPIOPIBC4 GPIO.PIBC4
-#define GPIOPIBC5 GPIO.PIBC5
-#define GPIOPIBC6 GPIO.PIBC6
-#define GPIOPIBC7 GPIO.PIBC7
-#define GPIOPIBC8 GPIO.PIBC8
-#define GPIOPIBC9 GPIO.PIBC9
-#define GPIOPIBC10 GPIO.PIBC10
-#define GPIOPIBC11 GPIO.PIBC11
-#define GPIOPBDC1 GPIO.PBDC1
-#define GPIOPBDC2 GPIO.PBDC2
-#define GPIOPBDC3 GPIO.PBDC3
-#define GPIOPBDC4 GPIO.PBDC4
-#define GPIOPBDC5 GPIO.PBDC5
-#define GPIOPBDC6 GPIO.PBDC6
-#define GPIOPBDC7 GPIO.PBDC7
-#define GPIOPBDC8 GPIO.PBDC8
-#define GPIOPBDC9 GPIO.PBDC9
-#define GPIOPBDC10 GPIO.PBDC10
-#define GPIOPBDC11 GPIO.PBDC11
-#define GPIOPIPC1 GPIO.PIPC1
-#define GPIOPIPC2 GPIO.PIPC2
-#define GPIOPIPC3 GPIO.PIPC3
-#define GPIOPIPC4 GPIO.PIPC4
-#define GPIOPIPC5 GPIO.PIPC5
-#define GPIOPIPC6 GPIO.PIPC6
-#define GPIOPIPC7 GPIO.PIPC7
-#define GPIOPIPC8 GPIO.PIPC8
-#define GPIOPIPC9 GPIO.PIPC9
-#define GPIOPIPC10 GPIO.PIPC10
-#define GPIOPIPC11 GPIO.PIPC11
-#define GPIOJPPR0 GPIO.JPPR0
-#define GPIOJPMC0 GPIO.JPMC0
-#define GPIOJPMCSR0 GPIO.JPMCSR0
-#define GPIOJPIBC0 GPIO.JPIBC0
+typedef struct st_gpio
+{
+                                                           /* GPIO             */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P1;                                     /*  P1              */
+    volatile uint8_t   dummy348[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P2;                                     /*  P2              */
+    volatile uint8_t   dummy349[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P3;                                     /*  P3              */
+    volatile uint8_t   dummy350[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P4;                                     /*  P4              */
+    volatile uint8_t   dummy351[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P5;                                     /*  P5              */
+    volatile uint8_t   dummy352[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P6;                                     /*  P6              */
+    volatile uint8_t   dummy353[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P7;                                     /*  P7              */
+    volatile uint8_t   dummy354[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P8;                                     /*  P8              */
+    volatile uint8_t   dummy355[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P9;                                     /*  P9              */
+    volatile uint8_t   dummy356[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P10;                                    /*  P10             */
+    volatile uint8_t   dummy357[2];                            /*                  */
+
+/* end of struct st_gpio_from_p1 */
+
+/* start of struct st_gpio_from_p1 */
+    volatile uint16_t P11;                                    /*  P11             */
+    volatile uint8_t   dummy3580[2];                           /*                  */
+
+/* end of struct st_gpio_from_p1 */
+    volatile uint8_t   dummy3581[212];                         /*                  */
+
+/* #define GPIO_PSRn_COUNT (11) */
+    volatile uint32_t  PSR1;                                   /*  PSR1            */
+    volatile uint32_t  PSR2;                                   /*  PSR2            */
+    volatile uint32_t  PSR3;                                   /*  PSR3            */
+    volatile uint32_t  PSR4;                                   /*  PSR4            */
+    volatile uint32_t  PSR5;                                   /*  PSR5            */
+    volatile uint32_t  PSR6;                                   /*  PSR6            */
+    volatile uint32_t  PSR7;                                   /*  PSR7            */
+    volatile uint32_t  PSR8;                                   /*  PSR8            */
+    volatile uint32_t  PSR9;                                   /*  PSR9            */
+    volatile uint32_t  PSR10;                                  /*  PSR10           */
+    volatile uint32_t  PSR11;                                  /*  PSR11           */
+    volatile uint8_t   dummy359[208];                          /*                  */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR0;                                   /*  PPR0            */
+    volatile uint8_t   dummy360[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR1;                                   /*  PPR1            */
+    volatile uint8_t   dummy361[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR2;                                   /*  PPR2            */
+    volatile uint8_t   dummy362[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR3;                                   /*  PPR3            */
+    volatile uint8_t   dummy363[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR4;                                   /*  PPR4            */
+    volatile uint8_t   dummy364[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR5;                                   /*  PPR5            */
+    volatile uint8_t   dummy365[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR6;                                   /*  PPR6            */
+    volatile uint8_t   dummy366[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR7;                                   /*  PPR7            */
+    volatile uint8_t   dummy367[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR8;                                   /*  PPR8            */
+    volatile uint8_t   dummy368[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR9;                                   /*  PPR9            */
+    volatile uint8_t   dummy369[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR10;                                  /*  PPR10           */
+    volatile uint8_t   dummy370[2];                            /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+
+/* start of struct st_gpio_from_ppr0 */
+    volatile uint16_t PPR11;                                  /*  PPR11           */
+    volatile uint8_t   dummy3710[2];                           /*                  */
+
+/* end of struct st_gpio_from_ppr0 */
+    volatile uint8_t   dummy3711[212];                         /*                  */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM1;                                    /*  PM1             */
+    volatile uint8_t   dummy372[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM2;                                    /*  PM2             */
+    volatile uint8_t   dummy373[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM3;                                    /*  PM3             */
+    volatile uint8_t   dummy374[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM4;                                    /*  PM4             */
+    volatile uint8_t   dummy375[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM5;                                    /*  PM5             */
+    volatile uint8_t   dummy376[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM6;                                    /*  PM6             */
+    volatile uint8_t   dummy377[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM7;                                    /*  PM7             */
+    volatile uint8_t   dummy378[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM8;                                    /*  PM8             */
+    volatile uint8_t   dummy379[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM9;                                    /*  PM9             */
+    volatile uint8_t   dummy380[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM10;                                   /*  PM10            */
+    volatile uint8_t   dummy381[2];                            /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+
+/* start of struct st_gpio_from_pm1 */
+    volatile uint16_t PM11;                                   /*  PM11            */
+    volatile uint8_t   dummy3820[2];                           /*                  */
+
+/* end of struct st_gpio_from_pm1 */
+    volatile uint8_t   dummy3821[208];                         /*                  */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC0;                                   /*  PMC0            */
+    volatile uint8_t   dummy383[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC1;                                   /*  PMC1            */
+    volatile uint8_t   dummy384[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC2;                                   /*  PMC2            */
+    volatile uint8_t   dummy385[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC3;                                   /*  PMC3            */
+    volatile uint8_t   dummy386[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC4;                                   /*  PMC4            */
+    volatile uint8_t   dummy387[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC5;                                   /*  PMC5            */
+    volatile uint8_t   dummy388[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC6;                                   /*  PMC6            */
+    volatile uint8_t   dummy389[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC7;                                   /*  PMC7            */
+    volatile uint8_t   dummy390[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC8;                                   /*  PMC8            */
+    volatile uint8_t   dummy391[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC9;                                   /*  PMC9            */
+    volatile uint8_t   dummy392[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC10;                                  /*  PMC10           */
+    volatile uint8_t   dummy393[2];                            /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+
+/* start of struct st_gpio_from_pmc0 */
+    volatile uint16_t PMC11;                                  /*  PMC11           */
+    volatile uint8_t   dummy3940[2];                           /*                  */
+
+/* end of struct st_gpio_from_pmc0 */
+    volatile uint8_t   dummy3941[212];                         /*                  */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC1;                                   /*  PFC1            */
+    volatile uint8_t   dummy395[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC2;                                   /*  PFC2            */
+    volatile uint8_t   dummy396[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC3;                                   /*  PFC3            */
+    volatile uint8_t   dummy397[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC4;                                   /*  PFC4            */
+    volatile uint8_t   dummy398[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC5;                                   /*  PFC5            */
+    volatile uint8_t   dummy399[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC6;                                   /*  PFC6            */
+    volatile uint8_t   dummy400[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC7;                                   /*  PFC7            */
+    volatile uint8_t   dummy401[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC8;                                   /*  PFC8            */
+    volatile uint8_t   dummy402[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC9;                                   /*  PFC9            */
+    volatile uint8_t   dummy403[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC10;                                  /*  PFC10           */
+    volatile uint8_t   dummy404[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+
+/* start of struct st_gpio_from_pfc1 */
+    volatile uint16_t PFC11;                                  /*  PFC11           */
+    volatile uint8_t   dummy4050[2];                           /*                  */
+
+/* end of struct st_gpio_from_pfc1 */
+    volatile uint8_t   dummy4051[212];                         /*                  */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE1;                                  /*  PFCE1           */
+    volatile uint8_t   dummy406[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE2;                                  /*  PFCE2           */
+    volatile uint8_t   dummy407[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE3;                                  /*  PFCE3           */
+    volatile uint8_t   dummy408[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE4;                                  /*  PFCE4           */
+    volatile uint8_t   dummy409[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE5;                                  /*  PFCE5           */
+    volatile uint8_t   dummy410[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE6;                                  /*  PFCE6           */
+    volatile uint8_t   dummy411[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE7;                                  /*  PFCE7           */
+    volatile uint8_t   dummy412[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE8;                                  /*  PFCE8           */
+    volatile uint8_t   dummy413[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE9;                                  /*  PFCE9           */
+    volatile uint8_t   dummy414[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE10;                                 /*  PFCE10          */
+    volatile uint8_t   dummy415[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+
+/* start of struct st_gpio_from_pfce1 */
+    volatile uint16_t PFCE11;                                 /*  PFCE11          */
+    volatile uint8_t   dummy4160[2];                           /*                  */
+
+/* end of struct st_gpio_from_pfce1 */
+    volatile uint8_t   dummy4161[212];                         /*                  */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT1;                                  /*  PNOT1           */
+    volatile uint8_t   dummy417[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT2;                                  /*  PNOT2           */
+    volatile uint8_t   dummy418[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT3;                                  /*  PNOT3           */
+    volatile uint8_t   dummy419[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT4;                                  /*  PNOT4           */
+    volatile uint8_t   dummy420[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT5;                                  /*  PNOT5           */
+    volatile uint8_t   dummy421[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT6;                                  /*  PNOT6           */
+    volatile uint8_t   dummy422[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT7;                                  /*  PNOT7           */
+    volatile uint8_t   dummy423[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT8;                                  /*  PNOT8           */
+    volatile uint8_t   dummy424[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT9;                                  /*  PNOT9           */
+    volatile uint8_t   dummy425[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT10;                                 /*  PNOT10          */
+    volatile uint8_t   dummy426[2];                            /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+
+/* start of struct st_gpio_from_pnot1 */
+    volatile uint16_t PNOT11;                                 /*  PNOT11          */
+    volatile uint8_t   dummy4270[2];                           /*                  */
+
+/* end of struct st_gpio_from_pnot1 */
+    volatile uint8_t   dummy4271[212];                         /*                  */
+
+/* #define GPIO_PMSRn_COUNT (11) */
+    volatile uint32_t  PMSR1;                                  /*  PMSR1           */
+    volatile uint32_t  PMSR2;                                  /*  PMSR2           */
+    volatile uint32_t  PMSR3;                                  /*  PMSR3           */
+    volatile uint32_t  PMSR4;                                  /*  PMSR4           */
+    volatile uint32_t  PMSR5;                                  /*  PMSR5           */
+    volatile uint32_t  PMSR6;                                  /*  PMSR6           */
+    volatile uint32_t  PMSR7;                                  /*  PMSR7           */
+    volatile uint32_t  PMSR8;                                  /*  PMSR8           */
+    volatile uint32_t  PMSR9;                                  /*  PMSR9           */
+    volatile uint32_t  PMSR10;                                 /*  PMSR10          */
+    volatile uint32_t  PMSR11;                                 /*  PMSR11          */
+    volatile uint8_t   dummy428[208];                          /*                  */
+
+/* #define GPIO_PMCSRn_COUNT (12) */
+    volatile uint32_t  PMCSR0;                                 /*  PMCSR0          */
+    volatile uint32_t  PMCSR1;                                 /*  PMCSR1          */
+    volatile uint32_t  PMCSR2;                                 /*  PMCSR2          */
+    volatile uint32_t  PMCSR3;                                 /*  PMCSR3          */
+    volatile uint32_t  PMCSR4;                                 /*  PMCSR4          */
+    volatile uint32_t  PMCSR5;                                 /*  PMCSR5          */
+    volatile uint32_t  PMCSR6;                                 /*  PMCSR6          */
+    volatile uint32_t  PMCSR7;                                 /*  PMCSR7          */
+    volatile uint32_t  PMCSR8;                                 /*  PMCSR8          */
+    volatile uint32_t  PMCSR9;                                 /*  PMCSR9          */
+    volatile uint32_t  PMCSR10;                                /*  PMCSR10         */
+    volatile uint32_t  PMCSR11;                                /*  PMCSR11         */
+    volatile uint8_t   dummy429[212];                          /*                  */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
+    volatile uint8_t   dummy430[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE2;                                 /*  PFCAE2          */
+    volatile uint8_t   dummy431[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE3;                                 /*  PFCAE3          */
+    volatile uint8_t   dummy432[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE4;                                 /*  PFCAE4          */
+    volatile uint8_t   dummy433[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE5;                                 /*  PFCAE5          */
+    volatile uint8_t   dummy434[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE6;                                 /*  PFCAE6          */
+    volatile uint8_t   dummy435[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE7;                                 /*  PFCAE7          */
+    volatile uint8_t   dummy436[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE8;                                 /*  PFCAE8          */
+    volatile uint8_t   dummy437[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE9;                                 /*  PFCAE9          */
+    volatile uint8_t   dummy438[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE10;                                /*  PFCAE10         */
+    volatile uint8_t   dummy439[2];                            /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+
+/* start of struct st_gpio_from_pfcae1 */
+    volatile uint16_t PFCAE11;                                /*  PFCAE11         */
+    volatile uint8_t   dummy4400[2];                           /*                  */
+
+/* end of struct st_gpio_from_pfcae1 */
+    volatile uint8_t   dummy4401[464];                         /*                  */
+    volatile uint32_t  SNCR;                                   /*  SNCR            */
+    volatile uint8_t   dummy441[13308];                        /*                  */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC0;                                  /*  PIBC0           */
+    volatile uint8_t   dummy442[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC1;                                  /*  PIBC1           */
+    volatile uint8_t   dummy443[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC2;                                  /*  PIBC2           */
+    volatile uint8_t   dummy444[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC3;                                  /*  PIBC3           */
+    volatile uint8_t   dummy445[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC4;                                  /*  PIBC4           */
+    volatile uint8_t   dummy446[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC5;                                  /*  PIBC5           */
+    volatile uint8_t   dummy447[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC6;                                  /*  PIBC6           */
+    volatile uint8_t   dummy448[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC7;                                  /*  PIBC7           */
+    volatile uint8_t   dummy449[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC8;                                  /*  PIBC8           */
+    volatile uint8_t   dummy450[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC9;                                  /*  PIBC9           */
+    volatile uint8_t   dummy451[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC10;                                 /*  PIBC10          */
+    volatile uint8_t   dummy452[2];                            /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+
+/* start of struct st_gpio_from_pibc1 */
+    volatile uint16_t PIBC11;                                 /*  PIBC11          */
+    volatile uint8_t   dummy4530[2];                           /*                  */
+
+/* end of struct st_gpio_from_pibc1 */
+    volatile uint8_t   dummy4531[212];                         /*                  */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC1;                                  /*  PBDC1           */
+    volatile uint8_t   dummy454[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC2;                                  /*  PBDC2           */
+    volatile uint8_t   dummy455[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC3;                                  /*  PBDC3           */
+    volatile uint8_t   dummy456[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC4;                                  /*  PBDC4           */
+    volatile uint8_t   dummy457[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC5;                                  /*  PBDC5           */
+    volatile uint8_t   dummy458[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC6;                                  /*  PBDC6           */
+    volatile uint8_t   dummy459[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC7;                                  /*  PBDC7           */
+    volatile uint8_t   dummy460[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC8;                                  /*  PBDC8           */
+    volatile uint8_t   dummy461[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC9;                                  /*  PBDC9           */
+    volatile uint8_t   dummy462[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC10;                                 /*  PBDC10          */
+    volatile uint8_t   dummy463[2];                            /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+
+/* start of struct st_gpio_from_pbdc1 */
+    volatile uint16_t PBDC11;                                 /*  PBDC11          */
+    volatile uint8_t   dummy4640[2];                           /*                  */
+
+/* end of struct st_gpio_from_pbdc1 */
+    volatile uint8_t   dummy4641[212];                         /*                  */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC1;                                  /*  PIPC1           */
+    volatile uint8_t   dummy465[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC2;                                  /*  PIPC2           */
+    volatile uint8_t   dummy466[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC3;                                  /*  PIPC3           */
+    volatile uint8_t   dummy467[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC4;                                  /*  PIPC4           */
+    volatile uint8_t   dummy468[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC5;                                  /*  PIPC5           */
+    volatile uint8_t   dummy469[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC6;                                  /*  PIPC6           */
+    volatile uint8_t   dummy470[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC7;                                  /*  PIPC7           */
+    volatile uint8_t   dummy471[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC8;                                  /*  PIPC8           */
+    volatile uint8_t   dummy472[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC9;                                  /*  PIPC9           */
+    volatile uint8_t   dummy473[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC10;                                 /*  PIPC10          */
+    volatile uint8_t   dummy474[2];                            /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+
+/* start of struct st_gpio_from_pipc1 */
+    volatile uint16_t PIPC11;                                 /*  PIPC11          */
+    volatile uint8_t   dummy4750[2];                           /*                  */
+
+/* end of struct st_gpio_from_pipc1 */
+    volatile uint8_t   dummy4751[2288];                        /*                  */
+    volatile uint16_t JPPR0;                                  /*  JPPR0           */
+    volatile uint8_t   dummy476[30];                           /*                  */
+    volatile uint16_t JPMC0;                                  /*  JPMC0           */
+    volatile uint8_t   dummy477[78];                           /*                  */
+    volatile uint32_t  JPMCSR0;                                /*  JPMCSR0         */
+    volatile uint8_t   dummy478[876];                          /*                  */
+    volatile uint16_t JPIBC0;                                 /*  JPIBC0          */
+} r_io_gpio_t;
+
+
+typedef struct st_gpio_from_p1
+{
+ 
+    volatile uint16_t P1;                                     /*  P1              */
+    volatile uint8_t   dummy1[3];                              /*                  */
+} r_io_gpio_from_p1_t;
+
+
+typedef struct st_gpio_from_ppr0
+{
+ 
+    volatile uint16_t PPR0;                                   /*  PPR0            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_ppr0_t;
+
+
+typedef struct st_gpio_from_pm1
+{
+ 
+    volatile uint16_t PM1;                                    /*  PM1             */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pm1_t;
+
+
+typedef struct st_gpio_from_pmc0
+{
+ 
+    volatile uint16_t PMC0;                                   /*  PMC0            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pmc0_t;
+
+
+typedef struct st_gpio_from_pfc1
+{
+ 
+    volatile uint16_t PFC1;                                   /*  PFC1            */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pfc1_t;
+
+
+typedef struct st_gpio_from_pfce1
+{
+ 
+    volatile uint16_t PFCE1;                                  /*  PFCE1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pfce1_t;
+
+
+typedef struct st_gpio_from_pnot1
+{
+ 
+    volatile uint16_t PNOT1;                                  /*  PNOT1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pnot1_t;
+
+
+typedef struct st_gpio_from_pfcae1
+{
+ 
+    volatile uint16_t PFCAE1;                                 /*  PFCAE1          */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pfcae1_t;
+
+
+typedef struct st_gpio_from_pibc1
+{
+ 
+    volatile uint16_t PIBC1;                                  /*  PIBC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pibc1_t;
+
+
+typedef struct st_gpio_from_pbdc1
+{
+ 
+    volatile uint16_t PBDC1;                                  /*  PBDC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pbdc1_t;
+
+
+typedef struct st_gpio_from_pipc1
+{
+ 
+    volatile uint16_t PIPC1;                                  /*  PIPC1           */
+    volatile uint8_t   dummy1[2];                              /*                  */
+} r_io_gpio_from_pipc1_t;
+
+
+/* Channel array defines of GPIO (2)*/
+#ifdef  DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pipc1*  GPIO_FROM_PIPC1_ARRAY[ GPIO_FROM_PIPC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PIPC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PIPC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pbdc1*  GPIO_FROM_PBDC1_ARRAY[ GPIO_FROM_PBDC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PBDC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PBDC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pibc1*  GPIO_FROM_PIBC1_ARRAY[ GPIO_FROM_PIBC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PIBC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PIBC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pfcae1*  GPIO_FROM_PFCAE1_ARRAY[ GPIO_FROM_PFCAE1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PFCAE1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PFCAE1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pnot1*  GPIO_FROM_PNOT1_ARRAY[ GPIO_FROM_PNOT1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PNOT1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PNOT1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pfce1*  GPIO_FROM_PFCE1_ARRAY[ GPIO_FROM_PFCE1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PFCE1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PFCE1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pfc1*  GPIO_FROM_PFC1_ARRAY[ GPIO_FROM_PFC1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PFC1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PFC1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS
+volatile struct st_gpio_from_pmc0*  GPIO_FROM_PMC0_ARRAY[ GPIO_FROM_PMC0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PMC0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PMC0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS
+volatile struct st_gpio_from_pm1*  GPIO_FROM_PM1_ARRAY[ GPIO_FROM_PM1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PM1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PM1_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS
+volatile struct st_gpio_from_ppr0*  GPIO_FROM_PPR0_ARRAY[ GPIO_FROM_PPR0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_PPR0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_PPR0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS
+volatile struct st_gpio_from_p1*  GPIO_FROM_P1_ARRAY[ GPIO_FROM_P1_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    GPIO_FROM_P1_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_GPIO_FROM_P1_ARRAY_CHANNELS */
+/* End of channel array defines of GPIO (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ieb_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,55 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : ieb_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef IEB_IODEFINE_H
 #define IEB_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_ieb
-{                                                          /* IEB              */
+#define IEB     (*(struct st_ieb     *)0xFCFEF000uL) /* IEB */
+
+
+#define IEBB0BCR (IEB.B0BCR)
+#define IEBB0PSR (IEB.B0PSR)
+#define IEBB0UAR (IEB.B0UAR)
+#define IEBB0SAR (IEB.B0SAR)
+#define IEBB0PAR (IEB.B0PAR)
+#define IEBB0RSA (IEB.B0RSA)
+#define IEBB0CDR (IEB.B0CDR)
+#define IEBB0TCD (IEB.B0TCD)
+#define IEBB0RCD (IEB.B0RCD)
+#define IEBB0DLR (IEB.B0DLR)
+#define IEBB0TDL (IEB.B0TDL)
+#define IEBB0RDL (IEB.B0RDL)
+#define IEBB0CKS (IEB.B0CKS)
+#define IEBB0TMS (IEB.B0TMS)
+#define IEBB0PCR (IEB.B0PCR)
+#define IEBB0BSR (IEB.B0BSR)
+#define IEBB0SSR (IEB.B0SSR)
+#define IEBB0USR (IEB.B0USR)
+#define IEBB0ISR (IEB.B0ISR)
+#define IEBB0ESR (IEB.B0ESR)
+#define IEBB0FSR (IEB.B0FSR)
+#define IEBB0SCR (IEB.B0SCR)
+#define IEBB0CCR (IEB.B0CCR)
+#define IEBB0STC0 (IEB.B0STC0)
+#define IEBB0STC1 (IEB.B0STC1)
+#define IEBB0DR (IEB.B0DR)
+
+
+typedef struct st_ieb
+{
+                                                           /* IEB              */
     volatile uint8_t   B0BCR;                                  /*  B0BCR           */
     volatile uint8_t   dummy495[3];                            /*                  */
     volatile uint8_t   B0PSR;                                  /*  B0PSR           */
@@ -83,37 +118,11 @@
     volatile uint8_t   B0STC1;                                 /*  B0STC1          */
     volatile uint8_t   dummy519[3];                            /*                  */
     volatile uint8_t   B0DR;                                   /*  B0DR            */
-};
-
-
-#define IEB     (*(struct st_ieb     *)0xFCFEF000uL) /* IEB */
+} r_io_ieb_t;
 
 
-#define IEBB0BCR IEB.B0BCR
-#define IEBB0PSR IEB.B0PSR
-#define IEBB0UAR IEB.B0UAR
-#define IEBB0SAR IEB.B0SAR
-#define IEBB0PAR IEB.B0PAR
-#define IEBB0RSA IEB.B0RSA
-#define IEBB0CDR IEB.B0CDR
-#define IEBB0TCD IEB.B0TCD
-#define IEBB0RCD IEB.B0RCD
-#define IEBB0DLR IEB.B0DLR
-#define IEBB0TDL IEB.B0TDL
-#define IEBB0RDL IEB.B0RDL
-#define IEBB0CKS IEB.B0CKS
-#define IEBB0TMS IEB.B0TMS
-#define IEBB0PCR IEB.B0PCR
-#define IEBB0BSR IEB.B0BSR
-#define IEBB0SSR IEB.B0SSR
-#define IEBB0USR IEB.B0USR
-#define IEBB0ISR IEB.B0ISR
-#define IEBB0ESR IEB.B0ESR
-#define IEBB0FSR IEB.B0FSR
-#define IEBB0SCR IEB.B0SCR
-#define IEBB0CCR IEB.B0CCR
-#define IEBB0STC0 IEB.B0STC0
-#define IEBB0STC1 IEB.B0STC1
-#define IEBB0DR IEB.B0DR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/inb_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,21 +18,61 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : inb_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef INB_IODEFINE_H
 #define INB_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
-struct st_inb
-{                                                          /* INB              */
+#define INB     (*(struct st_inb     *)0xFCFE1A00uL) /* INB */
+
+
+#define INBRMPR (INB.RMPR)
+#define INBAXIBUSCTL0 (INB.AXIBUSCTL0)
+#define INBAXIBUSCTL1 (INB.AXIBUSCTL1)
+#define INBAXIBUSCTL2 (INB.AXIBUSCTL2)
+#define INBAXIBUSCTL3 (INB.AXIBUSCTL3)
+#define INBAXIBUSCTL4 (INB.AXIBUSCTL4)
+#define INBAXIBUSCTL5 (INB.AXIBUSCTL5)
+#define INBAXIBUSCTL6 (INB.AXIBUSCTL6)
+#define INBAXIBUSCTL7 (INB.AXIBUSCTL7)
+#define INBAXIBUSCTL8 (INB.AXIBUSCTL8)
+#define INBAXIBUSCTL9 (INB.AXIBUSCTL9)
+#define INBAXIBUSCTL10 (INB.AXIBUSCTL10)
+#define INBAXIRERRCTL0 (INB.AXIRERRCTL0)
+#define INBAXIRERRCTL1 (INB.AXIRERRCTL1)
+#define INBAXIRERRCTL2 (INB.AXIRERRCTL2)
+#define INBAXIRERRCTL3 (INB.AXIRERRCTL3)
+#define INBAXIRERRST0 (INB.AXIRERRST0)
+#define INBAXIRERRST1 (INB.AXIRERRST1)
+#define INBAXIRERRST2 (INB.AXIRERRST2)
+#define INBAXIRERRST3 (INB.AXIRERRST3)
+#define INBAXIRERRCLR0 (INB.AXIRERRCLR0)
+#define INBAXIRERRCLR1 (INB.AXIRERRCLR1)
+#define INBAXIRERRCLR2 (INB.AXIRERRCLR2)
+#define INBAXIRERRCLR3 (INB.AXIRERRCLR3)
+
+#define INB_AXIBUSCTLn_COUNT (11)
+#define INB_AXIRERRCTLn_COUNT (4)
+#define INB_AXIRERRSTn_COUNT (4)
+#define INB_AXIRERRCLRn_COUNT (4)
+
+
+typedef struct st_inb
+{
+                                                           /* INB              */
     volatile uint32_t  RMPR;                                   /*  RMPR            */
-#define INB_AXIBUSCTLn_COUNT 11
+
+/* #define INB_AXIBUSCTLn_COUNT (11) */
     volatile uint32_t  AXIBUSCTL0;                             /*  AXIBUSCTL0      */
     volatile uint32_t  AXIBUSCTL1;                             /*  AXIBUSCTL1      */
     volatile uint32_t  AXIBUSCTL2;                             /*  AXIBUSCTL2      */
@@ -44,49 +84,29 @@
     volatile uint32_t  AXIBUSCTL8;                             /*  AXIBUSCTL8      */
     volatile uint32_t  AXIBUSCTL9;                             /*  AXIBUSCTL9      */
     volatile uint32_t  AXIBUSCTL10;                            /*  AXIBUSCTL10     */
-#define INB_AXIRERRCTLn_COUNT 4
+
+/* #define INB_AXIRERRCTLn_COUNT (4) */
     volatile uint32_t  AXIRERRCTL0;                            /*  AXIRERRCTL0     */
     volatile uint32_t  AXIRERRCTL1;                            /*  AXIRERRCTL1     */
     volatile uint32_t  AXIRERRCTL2;                            /*  AXIRERRCTL2     */
     volatile uint32_t  AXIRERRCTL3;                            /*  AXIRERRCTL3     */
-#define INB_AXIRERRSTn_COUNT 4
+
+/* #define INB_AXIRERRSTn_COUNT (4) */
     volatile uint32_t  AXIRERRST0;                             /*  AXIRERRST0      */
     volatile uint32_t  AXIRERRST1;                             /*  AXIRERRST1      */
     volatile uint32_t  AXIRERRST2;                             /*  AXIRERRST2      */
     volatile uint32_t  AXIRERRST3;                             /*  AXIRERRST3      */
-#define INB_AXIRERRCLRn_COUNT 4
+
+/* #define INB_AXIRERRCLRn_COUNT (4) */
     volatile uint32_t  AXIRERRCLR0;                            /*  AXIRERRCLR0     */
     volatile uint32_t  AXIRERRCLR1;                            /*  AXIRERRCLR1     */
     volatile uint32_t  AXIRERRCLR2;                            /*  AXIRERRCLR2     */
     volatile uint32_t  AXIRERRCLR3;                            /*  AXIRERRCLR3     */
-};
-
-
-#define INB     (*(struct st_inb     *)0xFCFE1A00uL) /* INB */
+} r_io_inb_t;
 
 
-#define INBRMPR INB.RMPR
-#define INBAXIBUSCTL0 INB.AXIBUSCTL0
-#define INBAXIBUSCTL1 INB.AXIBUSCTL1
-#define INBAXIBUSCTL2 INB.AXIBUSCTL2
-#define INBAXIBUSCTL3 INB.AXIBUSCTL3
-#define INBAXIBUSCTL4 INB.AXIBUSCTL4
-#define INBAXIBUSCTL5 INB.AXIBUSCTL5
-#define INBAXIBUSCTL6 INB.AXIBUSCTL6
-#define INBAXIBUSCTL7 INB.AXIBUSCTL7
-#define INBAXIBUSCTL8 INB.AXIBUSCTL8
-#define INBAXIBUSCTL9 INB.AXIBUSCTL9
-#define INBAXIBUSCTL10 INB.AXIBUSCTL10
-#define INBAXIRERRCTL0 INB.AXIRERRCTL0
-#define INBAXIRERRCTL1 INB.AXIRERRCTL1
-#define INBAXIRERRCTL2 INB.AXIRERRCTL2
-#define INBAXIRERRCTL3 INB.AXIRERRCTL3
-#define INBAXIRERRST0 INB.AXIRERRST0
-#define INBAXIRERRST1 INB.AXIRERRST1
-#define INBAXIRERRST2 INB.AXIRERRST2
-#define INBAXIRERRST3 INB.AXIRERRST3
-#define INBAXIRERRCLR0 INB.AXIRERRCLR0
-#define INBAXIRERRCLR1 INB.AXIRERRCLR1
-#define INBAXIRERRCLR2 INB.AXIRERRCLR2
-#define INBAXIRERRCLR3 INB.AXIRERRCLR3
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/intc_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,26 +18,525 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : intc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef INTC_IODEFINE_H
 #define INTC_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_intc
-{                                                          /* INTC             */
+#define INTC    (*(struct st_intc    *)0xE8201000uL) /* INTC */
+
+
+#define INTCICDDCR (INTC.ICDDCR)
+#define INTCICDICTR (INTC.ICDICTR)
+#define INTCICDIIDR (INTC.ICDIIDR)
+#define INTCICDISR0 (INTC.ICDISR0)
+#define INTCICDISR1 (INTC.ICDISR1)
+#define INTCICDISR2 (INTC.ICDISR2)
+#define INTCICDISR3 (INTC.ICDISR3)
+#define INTCICDISR4 (INTC.ICDISR4)
+#define INTCICDISR5 (INTC.ICDISR5)
+#define INTCICDISR6 (INTC.ICDISR6)
+#define INTCICDISR7 (INTC.ICDISR7)
+#define INTCICDISR8 (INTC.ICDISR8)
+#define INTCICDISR9 (INTC.ICDISR9)
+#define INTCICDISR10 (INTC.ICDISR10)
+#define INTCICDISR11 (INTC.ICDISR11)
+#define INTCICDISR12 (INTC.ICDISR12)
+#define INTCICDISR13 (INTC.ICDISR13)
+#define INTCICDISR14 (INTC.ICDISR14)
+#define INTCICDISR15 (INTC.ICDISR15)
+#define INTCICDISR16 (INTC.ICDISR16)
+#define INTCICDISR17 (INTC.ICDISR17)
+#define INTCICDISR18 (INTC.ICDISR18)
+#define INTCICDISER0 (INTC.ICDISER0)
+#define INTCICDISER1 (INTC.ICDISER1)
+#define INTCICDISER2 (INTC.ICDISER2)
+#define INTCICDISER3 (INTC.ICDISER3)
+#define INTCICDISER4 (INTC.ICDISER4)
+#define INTCICDISER5 (INTC.ICDISER5)
+#define INTCICDISER6 (INTC.ICDISER6)
+#define INTCICDISER7 (INTC.ICDISER7)
+#define INTCICDISER8 (INTC.ICDISER8)
+#define INTCICDISER9 (INTC.ICDISER9)
+#define INTCICDISER10 (INTC.ICDISER10)
+#define INTCICDISER11 (INTC.ICDISER11)
+#define INTCICDISER12 (INTC.ICDISER12)
+#define INTCICDISER13 (INTC.ICDISER13)
+#define INTCICDISER14 (INTC.ICDISER14)
+#define INTCICDISER15 (INTC.ICDISER15)
+#define INTCICDISER16 (INTC.ICDISER16)
+#define INTCICDISER17 (INTC.ICDISER17)
+#define INTCICDISER18 (INTC.ICDISER18)
+#define INTCICDICER0 (INTC.ICDICER0)
+#define INTCICDICER1 (INTC.ICDICER1)
+#define INTCICDICER2 (INTC.ICDICER2)
+#define INTCICDICER3 (INTC.ICDICER3)
+#define INTCICDICER4 (INTC.ICDICER4)
+#define INTCICDICER5 (INTC.ICDICER5)
+#define INTCICDICER6 (INTC.ICDICER6)
+#define INTCICDICER7 (INTC.ICDICER7)
+#define INTCICDICER8 (INTC.ICDICER8)
+#define INTCICDICER9 (INTC.ICDICER9)
+#define INTCICDICER10 (INTC.ICDICER10)
+#define INTCICDICER11 (INTC.ICDICER11)
+#define INTCICDICER12 (INTC.ICDICER12)
+#define INTCICDICER13 (INTC.ICDICER13)
+#define INTCICDICER14 (INTC.ICDICER14)
+#define INTCICDICER15 (INTC.ICDICER15)
+#define INTCICDICER16 (INTC.ICDICER16)
+#define INTCICDICER17 (INTC.ICDICER17)
+#define INTCICDICER18 (INTC.ICDICER18)
+#define INTCICDISPR0 (INTC.ICDISPR0)
+#define INTCICDISPR1 (INTC.ICDISPR1)
+#define INTCICDISPR2 (INTC.ICDISPR2)
+#define INTCICDISPR3 (INTC.ICDISPR3)
+#define INTCICDISPR4 (INTC.ICDISPR4)
+#define INTCICDISPR5 (INTC.ICDISPR5)
+#define INTCICDISPR6 (INTC.ICDISPR6)
+#define INTCICDISPR7 (INTC.ICDISPR7)
+#define INTCICDISPR8 (INTC.ICDISPR8)
+#define INTCICDISPR9 (INTC.ICDISPR9)
+#define INTCICDISPR10 (INTC.ICDISPR10)
+#define INTCICDISPR11 (INTC.ICDISPR11)
+#define INTCICDISPR12 (INTC.ICDISPR12)
+#define INTCICDISPR13 (INTC.ICDISPR13)
+#define INTCICDISPR14 (INTC.ICDISPR14)
+#define INTCICDISPR15 (INTC.ICDISPR15)
+#define INTCICDISPR16 (INTC.ICDISPR16)
+#define INTCICDISPR17 (INTC.ICDISPR17)
+#define INTCICDISPR18 (INTC.ICDISPR18)
+#define INTCICDICPR0 (INTC.ICDICPR0)
+#define INTCICDICPR1 (INTC.ICDICPR1)
+#define INTCICDICPR2 (INTC.ICDICPR2)
+#define INTCICDICPR3 (INTC.ICDICPR3)
+#define INTCICDICPR4 (INTC.ICDICPR4)
+#define INTCICDICPR5 (INTC.ICDICPR5)
+#define INTCICDICPR6 (INTC.ICDICPR6)
+#define INTCICDICPR7 (INTC.ICDICPR7)
+#define INTCICDICPR8 (INTC.ICDICPR8)
+#define INTCICDICPR9 (INTC.ICDICPR9)
+#define INTCICDICPR10 (INTC.ICDICPR10)
+#define INTCICDICPR11 (INTC.ICDICPR11)
+#define INTCICDICPR12 (INTC.ICDICPR12)
+#define INTCICDICPR13 (INTC.ICDICPR13)
+#define INTCICDICPR14 (INTC.ICDICPR14)
+#define INTCICDICPR15 (INTC.ICDICPR15)
+#define INTCICDICPR16 (INTC.ICDICPR16)
+#define INTCICDICPR17 (INTC.ICDICPR17)
+#define INTCICDICPR18 (INTC.ICDICPR18)
+#define INTCICDABR0 (INTC.ICDABR0)
+#define INTCICDABR1 (INTC.ICDABR1)
+#define INTCICDABR2 (INTC.ICDABR2)
+#define INTCICDABR3 (INTC.ICDABR3)
+#define INTCICDABR4 (INTC.ICDABR4)
+#define INTCICDABR5 (INTC.ICDABR5)
+#define INTCICDABR6 (INTC.ICDABR6)
+#define INTCICDABR7 (INTC.ICDABR7)
+#define INTCICDABR8 (INTC.ICDABR8)
+#define INTCICDABR9 (INTC.ICDABR9)
+#define INTCICDABR10 (INTC.ICDABR10)
+#define INTCICDABR11 (INTC.ICDABR11)
+#define INTCICDABR12 (INTC.ICDABR12)
+#define INTCICDABR13 (INTC.ICDABR13)
+#define INTCICDABR14 (INTC.ICDABR14)
+#define INTCICDABR15 (INTC.ICDABR15)
+#define INTCICDABR16 (INTC.ICDABR16)
+#define INTCICDABR17 (INTC.ICDABR17)
+#define INTCICDABR18 (INTC.ICDABR18)
+#define INTCICDIPR0 (INTC.ICDIPR0)
+#define INTCICDIPR1 (INTC.ICDIPR1)
+#define INTCICDIPR2 (INTC.ICDIPR2)
+#define INTCICDIPR3 (INTC.ICDIPR3)
+#define INTCICDIPR4 (INTC.ICDIPR4)
+#define INTCICDIPR5 (INTC.ICDIPR5)
+#define INTCICDIPR6 (INTC.ICDIPR6)
+#define INTCICDIPR7 (INTC.ICDIPR7)
+#define INTCICDIPR8 (INTC.ICDIPR8)
+#define INTCICDIPR9 (INTC.ICDIPR9)
+#define INTCICDIPR10 (INTC.ICDIPR10)
+#define INTCICDIPR11 (INTC.ICDIPR11)
+#define INTCICDIPR12 (INTC.ICDIPR12)
+#define INTCICDIPR13 (INTC.ICDIPR13)
+#define INTCICDIPR14 (INTC.ICDIPR14)
+#define INTCICDIPR15 (INTC.ICDIPR15)
+#define INTCICDIPR16 (INTC.ICDIPR16)
+#define INTCICDIPR17 (INTC.ICDIPR17)
+#define INTCICDIPR18 (INTC.ICDIPR18)
+#define INTCICDIPR19 (INTC.ICDIPR19)
+#define INTCICDIPR20 (INTC.ICDIPR20)
+#define INTCICDIPR21 (INTC.ICDIPR21)
+#define INTCICDIPR22 (INTC.ICDIPR22)
+#define INTCICDIPR23 (INTC.ICDIPR23)
+#define INTCICDIPR24 (INTC.ICDIPR24)
+#define INTCICDIPR25 (INTC.ICDIPR25)
+#define INTCICDIPR26 (INTC.ICDIPR26)
+#define INTCICDIPR27 (INTC.ICDIPR27)
+#define INTCICDIPR28 (INTC.ICDIPR28)
+#define INTCICDIPR29 (INTC.ICDIPR29)
+#define INTCICDIPR30 (INTC.ICDIPR30)
+#define INTCICDIPR31 (INTC.ICDIPR31)
+#define INTCICDIPR32 (INTC.ICDIPR32)
+#define INTCICDIPR33 (INTC.ICDIPR33)
+#define INTCICDIPR34 (INTC.ICDIPR34)
+#define INTCICDIPR35 (INTC.ICDIPR35)
+#define INTCICDIPR36 (INTC.ICDIPR36)
+#define INTCICDIPR37 (INTC.ICDIPR37)
+#define INTCICDIPR38 (INTC.ICDIPR38)
+#define INTCICDIPR39 (INTC.ICDIPR39)
+#define INTCICDIPR40 (INTC.ICDIPR40)
+#define INTCICDIPR41 (INTC.ICDIPR41)
+#define INTCICDIPR42 (INTC.ICDIPR42)
+#define INTCICDIPR43 (INTC.ICDIPR43)
+#define INTCICDIPR44 (INTC.ICDIPR44)
+#define INTCICDIPR45 (INTC.ICDIPR45)
+#define INTCICDIPR46 (INTC.ICDIPR46)
+#define INTCICDIPR47 (INTC.ICDIPR47)
+#define INTCICDIPR48 (INTC.ICDIPR48)
+#define INTCICDIPR49 (INTC.ICDIPR49)
+#define INTCICDIPR50 (INTC.ICDIPR50)
+#define INTCICDIPR51 (INTC.ICDIPR51)
+#define INTCICDIPR52 (INTC.ICDIPR52)
+#define INTCICDIPR53 (INTC.ICDIPR53)
+#define INTCICDIPR54 (INTC.ICDIPR54)
+#define INTCICDIPR55 (INTC.ICDIPR55)
+#define INTCICDIPR56 (INTC.ICDIPR56)
+#define INTCICDIPR57 (INTC.ICDIPR57)
+#define INTCICDIPR58 (INTC.ICDIPR58)
+#define INTCICDIPR59 (INTC.ICDIPR59)
+#define INTCICDIPR60 (INTC.ICDIPR60)
+#define INTCICDIPR61 (INTC.ICDIPR61)
+#define INTCICDIPR62 (INTC.ICDIPR62)
+#define INTCICDIPR63 (INTC.ICDIPR63)
+#define INTCICDIPR64 (INTC.ICDIPR64)
+#define INTCICDIPR65 (INTC.ICDIPR65)
+#define INTCICDIPR66 (INTC.ICDIPR66)
+#define INTCICDIPR67 (INTC.ICDIPR67)
+#define INTCICDIPR68 (INTC.ICDIPR68)
+#define INTCICDIPR69 (INTC.ICDIPR69)
+#define INTCICDIPR70 (INTC.ICDIPR70)
+#define INTCICDIPR71 (INTC.ICDIPR71)
+#define INTCICDIPR72 (INTC.ICDIPR72)
+#define INTCICDIPR73 (INTC.ICDIPR73)
+#define INTCICDIPR74 (INTC.ICDIPR74)
+#define INTCICDIPR75 (INTC.ICDIPR75)
+#define INTCICDIPR76 (INTC.ICDIPR76)
+#define INTCICDIPR77 (INTC.ICDIPR77)
+#define INTCICDIPR78 (INTC.ICDIPR78)
+#define INTCICDIPR79 (INTC.ICDIPR79)
+#define INTCICDIPR80 (INTC.ICDIPR80)
+#define INTCICDIPR81 (INTC.ICDIPR81)
+#define INTCICDIPR82 (INTC.ICDIPR82)
+#define INTCICDIPR83 (INTC.ICDIPR83)
+#define INTCICDIPR84 (INTC.ICDIPR84)
+#define INTCICDIPR85 (INTC.ICDIPR85)
+#define INTCICDIPR86 (INTC.ICDIPR86)
+#define INTCICDIPR87 (INTC.ICDIPR87)
+#define INTCICDIPR88 (INTC.ICDIPR88)
+#define INTCICDIPR89 (INTC.ICDIPR89)
+#define INTCICDIPR90 (INTC.ICDIPR90)
+#define INTCICDIPR91 (INTC.ICDIPR91)
+#define INTCICDIPR92 (INTC.ICDIPR92)
+#define INTCICDIPR93 (INTC.ICDIPR93)
+#define INTCICDIPR94 (INTC.ICDIPR94)
+#define INTCICDIPR95 (INTC.ICDIPR95)
+#define INTCICDIPR96 (INTC.ICDIPR96)
+#define INTCICDIPR97 (INTC.ICDIPR97)
+#define INTCICDIPR98 (INTC.ICDIPR98)
+#define INTCICDIPR99 (INTC.ICDIPR99)
+#define INTCICDIPR100 (INTC.ICDIPR100)
+#define INTCICDIPR101 (INTC.ICDIPR101)
+#define INTCICDIPR102 (INTC.ICDIPR102)
+#define INTCICDIPR103 (INTC.ICDIPR103)
+#define INTCICDIPR104 (INTC.ICDIPR104)
+#define INTCICDIPR105 (INTC.ICDIPR105)
+#define INTCICDIPR106 (INTC.ICDIPR106)
+#define INTCICDIPR107 (INTC.ICDIPR107)
+#define INTCICDIPR108 (INTC.ICDIPR108)
+#define INTCICDIPR109 (INTC.ICDIPR109)
+#define INTCICDIPR110 (INTC.ICDIPR110)
+#define INTCICDIPR111 (INTC.ICDIPR111)
+#define INTCICDIPR112 (INTC.ICDIPR112)
+#define INTCICDIPR113 (INTC.ICDIPR113)
+#define INTCICDIPR114 (INTC.ICDIPR114)
+#define INTCICDIPR115 (INTC.ICDIPR115)
+#define INTCICDIPR116 (INTC.ICDIPR116)
+#define INTCICDIPR117 (INTC.ICDIPR117)
+#define INTCICDIPR118 (INTC.ICDIPR118)
+#define INTCICDIPR119 (INTC.ICDIPR119)
+#define INTCICDIPR120 (INTC.ICDIPR120)
+#define INTCICDIPR121 (INTC.ICDIPR121)
+#define INTCICDIPR122 (INTC.ICDIPR122)
+#define INTCICDIPR123 (INTC.ICDIPR123)
+#define INTCICDIPR124 (INTC.ICDIPR124)
+#define INTCICDIPR125 (INTC.ICDIPR125)
+#define INTCICDIPR126 (INTC.ICDIPR126)
+#define INTCICDIPR127 (INTC.ICDIPR127)
+#define INTCICDIPR128 (INTC.ICDIPR128)
+#define INTCICDIPR129 (INTC.ICDIPR129)
+#define INTCICDIPR130 (INTC.ICDIPR130)
+#define INTCICDIPR131 (INTC.ICDIPR131)
+#define INTCICDIPR132 (INTC.ICDIPR132)
+#define INTCICDIPR133 (INTC.ICDIPR133)
+#define INTCICDIPR134 (INTC.ICDIPR134)
+#define INTCICDIPR135 (INTC.ICDIPR135)
+#define INTCICDIPR136 (INTC.ICDIPR136)
+#define INTCICDIPR137 (INTC.ICDIPR137)
+#define INTCICDIPR138 (INTC.ICDIPR138)
+#define INTCICDIPR139 (INTC.ICDIPR139)
+#define INTCICDIPR140 (INTC.ICDIPR140)
+#define INTCICDIPR141 (INTC.ICDIPR141)
+#define INTCICDIPR142 (INTC.ICDIPR142)
+#define INTCICDIPR143 (INTC.ICDIPR143)
+#define INTCICDIPR144 (INTC.ICDIPR144)
+#define INTCICDIPR145 (INTC.ICDIPR145)
+#define INTCICDIPR146 (INTC.ICDIPR146)
+#define INTCICDIPTR0 (INTC.ICDIPTR0)
+#define INTCICDIPTR1 (INTC.ICDIPTR1)
+#define INTCICDIPTR2 (INTC.ICDIPTR2)
+#define INTCICDIPTR3 (INTC.ICDIPTR3)
+#define INTCICDIPTR4 (INTC.ICDIPTR4)
+#define INTCICDIPTR5 (INTC.ICDIPTR5)
+#define INTCICDIPTR6 (INTC.ICDIPTR6)
+#define INTCICDIPTR7 (INTC.ICDIPTR7)
+#define INTCICDIPTR8 (INTC.ICDIPTR8)
+#define INTCICDIPTR9 (INTC.ICDIPTR9)
+#define INTCICDIPTR10 (INTC.ICDIPTR10)
+#define INTCICDIPTR11 (INTC.ICDIPTR11)
+#define INTCICDIPTR12 (INTC.ICDIPTR12)
+#define INTCICDIPTR13 (INTC.ICDIPTR13)
+#define INTCICDIPTR14 (INTC.ICDIPTR14)
+#define INTCICDIPTR15 (INTC.ICDIPTR15)
+#define INTCICDIPTR16 (INTC.ICDIPTR16)
+#define INTCICDIPTR17 (INTC.ICDIPTR17)
+#define INTCICDIPTR18 (INTC.ICDIPTR18)
+#define INTCICDIPTR19 (INTC.ICDIPTR19)
+#define INTCICDIPTR20 (INTC.ICDIPTR20)
+#define INTCICDIPTR21 (INTC.ICDIPTR21)
+#define INTCICDIPTR22 (INTC.ICDIPTR22)
+#define INTCICDIPTR23 (INTC.ICDIPTR23)
+#define INTCICDIPTR24 (INTC.ICDIPTR24)
+#define INTCICDIPTR25 (INTC.ICDIPTR25)
+#define INTCICDIPTR26 (INTC.ICDIPTR26)
+#define INTCICDIPTR27 (INTC.ICDIPTR27)
+#define INTCICDIPTR28 (INTC.ICDIPTR28)
+#define INTCICDIPTR29 (INTC.ICDIPTR29)
+#define INTCICDIPTR30 (INTC.ICDIPTR30)
+#define INTCICDIPTR31 (INTC.ICDIPTR31)
+#define INTCICDIPTR32 (INTC.ICDIPTR32)
+#define INTCICDIPTR33 (INTC.ICDIPTR33)
+#define INTCICDIPTR34 (INTC.ICDIPTR34)
+#define INTCICDIPTR35 (INTC.ICDIPTR35)
+#define INTCICDIPTR36 (INTC.ICDIPTR36)
+#define INTCICDIPTR37 (INTC.ICDIPTR37)
+#define INTCICDIPTR38 (INTC.ICDIPTR38)
+#define INTCICDIPTR39 (INTC.ICDIPTR39)
+#define INTCICDIPTR40 (INTC.ICDIPTR40)
+#define INTCICDIPTR41 (INTC.ICDIPTR41)
+#define INTCICDIPTR42 (INTC.ICDIPTR42)
+#define INTCICDIPTR43 (INTC.ICDIPTR43)
+#define INTCICDIPTR44 (INTC.ICDIPTR44)
+#define INTCICDIPTR45 (INTC.ICDIPTR45)
+#define INTCICDIPTR46 (INTC.ICDIPTR46)
+#define INTCICDIPTR47 (INTC.ICDIPTR47)
+#define INTCICDIPTR48 (INTC.ICDIPTR48)
+#define INTCICDIPTR49 (INTC.ICDIPTR49)
+#define INTCICDIPTR50 (INTC.ICDIPTR50)
+#define INTCICDIPTR51 (INTC.ICDIPTR51)
+#define INTCICDIPTR52 (INTC.ICDIPTR52)
+#define INTCICDIPTR53 (INTC.ICDIPTR53)
+#define INTCICDIPTR54 (INTC.ICDIPTR54)
+#define INTCICDIPTR55 (INTC.ICDIPTR55)
+#define INTCICDIPTR56 (INTC.ICDIPTR56)
+#define INTCICDIPTR57 (INTC.ICDIPTR57)
+#define INTCICDIPTR58 (INTC.ICDIPTR58)
+#define INTCICDIPTR59 (INTC.ICDIPTR59)
+#define INTCICDIPTR60 (INTC.ICDIPTR60)
+#define INTCICDIPTR61 (INTC.ICDIPTR61)
+#define INTCICDIPTR62 (INTC.ICDIPTR62)
+#define INTCICDIPTR63 (INTC.ICDIPTR63)
+#define INTCICDIPTR64 (INTC.ICDIPTR64)
+#define INTCICDIPTR65 (INTC.ICDIPTR65)
+#define INTCICDIPTR66 (INTC.ICDIPTR66)
+#define INTCICDIPTR67 (INTC.ICDIPTR67)
+#define INTCICDIPTR68 (INTC.ICDIPTR68)
+#define INTCICDIPTR69 (INTC.ICDIPTR69)
+#define INTCICDIPTR70 (INTC.ICDIPTR70)
+#define INTCICDIPTR71 (INTC.ICDIPTR71)
+#define INTCICDIPTR72 (INTC.ICDIPTR72)
+#define INTCICDIPTR73 (INTC.ICDIPTR73)
+#define INTCICDIPTR74 (INTC.ICDIPTR74)
+#define INTCICDIPTR75 (INTC.ICDIPTR75)
+#define INTCICDIPTR76 (INTC.ICDIPTR76)
+#define INTCICDIPTR77 (INTC.ICDIPTR77)
+#define INTCICDIPTR78 (INTC.ICDIPTR78)
+#define INTCICDIPTR79 (INTC.ICDIPTR79)
+#define INTCICDIPTR80 (INTC.ICDIPTR80)
+#define INTCICDIPTR81 (INTC.ICDIPTR81)
+#define INTCICDIPTR82 (INTC.ICDIPTR82)
+#define INTCICDIPTR83 (INTC.ICDIPTR83)
+#define INTCICDIPTR84 (INTC.ICDIPTR84)
+#define INTCICDIPTR85 (INTC.ICDIPTR85)
+#define INTCICDIPTR86 (INTC.ICDIPTR86)
+#define INTCICDIPTR87 (INTC.ICDIPTR87)
+#define INTCICDIPTR88 (INTC.ICDIPTR88)
+#define INTCICDIPTR89 (INTC.ICDIPTR89)
+#define INTCICDIPTR90 (INTC.ICDIPTR90)
+#define INTCICDIPTR91 (INTC.ICDIPTR91)
+#define INTCICDIPTR92 (INTC.ICDIPTR92)
+#define INTCICDIPTR93 (INTC.ICDIPTR93)
+#define INTCICDIPTR94 (INTC.ICDIPTR94)
+#define INTCICDIPTR95 (INTC.ICDIPTR95)
+#define INTCICDIPTR96 (INTC.ICDIPTR96)
+#define INTCICDIPTR97 (INTC.ICDIPTR97)
+#define INTCICDIPTR98 (INTC.ICDIPTR98)
+#define INTCICDIPTR99 (INTC.ICDIPTR99)
+#define INTCICDIPTR100 (INTC.ICDIPTR100)
+#define INTCICDIPTR101 (INTC.ICDIPTR101)
+#define INTCICDIPTR102 (INTC.ICDIPTR102)
+#define INTCICDIPTR103 (INTC.ICDIPTR103)
+#define INTCICDIPTR104 (INTC.ICDIPTR104)
+#define INTCICDIPTR105 (INTC.ICDIPTR105)
+#define INTCICDIPTR106 (INTC.ICDIPTR106)
+#define INTCICDIPTR107 (INTC.ICDIPTR107)
+#define INTCICDIPTR108 (INTC.ICDIPTR108)
+#define INTCICDIPTR109 (INTC.ICDIPTR109)
+#define INTCICDIPTR110 (INTC.ICDIPTR110)
+#define INTCICDIPTR111 (INTC.ICDIPTR111)
+#define INTCICDIPTR112 (INTC.ICDIPTR112)
+#define INTCICDIPTR113 (INTC.ICDIPTR113)
+#define INTCICDIPTR114 (INTC.ICDIPTR114)
+#define INTCICDIPTR115 (INTC.ICDIPTR115)
+#define INTCICDIPTR116 (INTC.ICDIPTR116)
+#define INTCICDIPTR117 (INTC.ICDIPTR117)
+#define INTCICDIPTR118 (INTC.ICDIPTR118)
+#define INTCICDIPTR119 (INTC.ICDIPTR119)
+#define INTCICDIPTR120 (INTC.ICDIPTR120)
+#define INTCICDIPTR121 (INTC.ICDIPTR121)
+#define INTCICDIPTR122 (INTC.ICDIPTR122)
+#define INTCICDIPTR123 (INTC.ICDIPTR123)
+#define INTCICDIPTR124 (INTC.ICDIPTR124)
+#define INTCICDIPTR125 (INTC.ICDIPTR125)
+#define INTCICDIPTR126 (INTC.ICDIPTR126)
+#define INTCICDIPTR127 (INTC.ICDIPTR127)
+#define INTCICDIPTR128 (INTC.ICDIPTR128)
+#define INTCICDIPTR129 (INTC.ICDIPTR129)
+#define INTCICDIPTR130 (INTC.ICDIPTR130)
+#define INTCICDIPTR131 (INTC.ICDIPTR131)
+#define INTCICDIPTR132 (INTC.ICDIPTR132)
+#define INTCICDIPTR133 (INTC.ICDIPTR133)
+#define INTCICDIPTR134 (INTC.ICDIPTR134)
+#define INTCICDIPTR135 (INTC.ICDIPTR135)
+#define INTCICDIPTR136 (INTC.ICDIPTR136)
+#define INTCICDIPTR137 (INTC.ICDIPTR137)
+#define INTCICDIPTR138 (INTC.ICDIPTR138)
+#define INTCICDIPTR139 (INTC.ICDIPTR139)
+#define INTCICDIPTR140 (INTC.ICDIPTR140)
+#define INTCICDIPTR141 (INTC.ICDIPTR141)
+#define INTCICDIPTR142 (INTC.ICDIPTR142)
+#define INTCICDIPTR143 (INTC.ICDIPTR143)
+#define INTCICDIPTR144 (INTC.ICDIPTR144)
+#define INTCICDIPTR145 (INTC.ICDIPTR145)
+#define INTCICDIPTR146 (INTC.ICDIPTR146)
+#define INTCICDICFR0 (INTC.ICDICFR0)
+#define INTCICDICFR1 (INTC.ICDICFR1)
+#define INTCICDICFR2 (INTC.ICDICFR2)
+#define INTCICDICFR3 (INTC.ICDICFR3)
+#define INTCICDICFR4 (INTC.ICDICFR4)
+#define INTCICDICFR5 (INTC.ICDICFR5)
+#define INTCICDICFR6 (INTC.ICDICFR6)
+#define INTCICDICFR7 (INTC.ICDICFR7)
+#define INTCICDICFR8 (INTC.ICDICFR8)
+#define INTCICDICFR9 (INTC.ICDICFR9)
+#define INTCICDICFR10 (INTC.ICDICFR10)
+#define INTCICDICFR11 (INTC.ICDICFR11)
+#define INTCICDICFR12 (INTC.ICDICFR12)
+#define INTCICDICFR13 (INTC.ICDICFR13)
+#define INTCICDICFR14 (INTC.ICDICFR14)
+#define INTCICDICFR15 (INTC.ICDICFR15)
+#define INTCICDICFR16 (INTC.ICDICFR16)
+#define INTCICDICFR17 (INTC.ICDICFR17)
+#define INTCICDICFR18 (INTC.ICDICFR18)
+#define INTCICDICFR19 (INTC.ICDICFR19)
+#define INTCICDICFR20 (INTC.ICDICFR20)
+#define INTCICDICFR21 (INTC.ICDICFR21)
+#define INTCICDICFR22 (INTC.ICDICFR22)
+#define INTCICDICFR23 (INTC.ICDICFR23)
+#define INTCICDICFR24 (INTC.ICDICFR24)
+#define INTCICDICFR25 (INTC.ICDICFR25)
+#define INTCICDICFR26 (INTC.ICDICFR26)
+#define INTCICDICFR27 (INTC.ICDICFR27)
+#define INTCICDICFR28 (INTC.ICDICFR28)
+#define INTCICDICFR29 (INTC.ICDICFR29)
+#define INTCICDICFR30 (INTC.ICDICFR30)
+#define INTCICDICFR31 (INTC.ICDICFR31)
+#define INTCICDICFR32 (INTC.ICDICFR32)
+#define INTCICDICFR33 (INTC.ICDICFR33)
+#define INTCICDICFR34 (INTC.ICDICFR34)
+#define INTCICDICFR35 (INTC.ICDICFR35)
+#define INTCICDICFR36 (INTC.ICDICFR36)
+#define INTCPPI_STATUS (INTC.PPI_STATUS)
+#define INTCSPI_STATUS0 (INTC.SPI_STATUS0)
+#define INTCSPI_STATUS1 (INTC.SPI_STATUS1)
+#define INTCSPI_STATUS2 (INTC.SPI_STATUS2)
+#define INTCSPI_STATUS3 (INTC.SPI_STATUS3)
+#define INTCSPI_STATUS4 (INTC.SPI_STATUS4)
+#define INTCSPI_STATUS5 (INTC.SPI_STATUS5)
+#define INTCSPI_STATUS6 (INTC.SPI_STATUS6)
+#define INTCSPI_STATUS7 (INTC.SPI_STATUS7)
+#define INTCSPI_STATUS8 (INTC.SPI_STATUS8)
+#define INTCSPI_STATUS9 (INTC.SPI_STATUS9)
+#define INTCSPI_STATUS10 (INTC.SPI_STATUS10)
+#define INTCSPI_STATUS11 (INTC.SPI_STATUS11)
+#define INTCSPI_STATUS12 (INTC.SPI_STATUS12)
+#define INTCSPI_STATUS13 (INTC.SPI_STATUS13)
+#define INTCSPI_STATUS14 (INTC.SPI_STATUS14)
+#define INTCSPI_STATUS15 (INTC.SPI_STATUS15)
+#define INTCSPI_STATUS16 (INTC.SPI_STATUS16)
+#define INTCICDSGIR (INTC.ICDSGIR)
+#define INTCICCICR (INTC.ICCICR)
+#define INTCICCPMR (INTC.ICCPMR)
+#define INTCICCBPR (INTC.ICCBPR)
+#define INTCICCIAR (INTC.ICCIAR)
+#define INTCICCEOIR (INTC.ICCEOIR)
+#define INTCICCRPR (INTC.ICCRPR)
+#define INTCICCHPIR (INTC.ICCHPIR)
+#define INTCICCABPR (INTC.ICCABPR)
+#define INTCICCIIDR (INTC.ICCIIDR)
+#define INTCICR0 (INTC.ICR0)
+#define INTCICR1 (INTC.ICR1)
+#define INTCIRQRR (INTC.IRQRR)
+
+#define INTC_ICDISR0_COUNT (19)
+#define INTC_ICDISER0_COUNT (19)
+#define INTC_ICDICER0_COUNT (19)
+#define INTC_ICDISPR0_COUNT (19)
+#define INTC_ICDICPR0_COUNT (19)
+#define INTC_ICDABR0_COUNT (19)
+#define INTC_ICDIPR0_COUNT (147)
+#define INTC_ICDIPTR0_COUNT (147)
+#define INTC_ICDICFR0_COUNT (37)
+#define INTC_SPI_STATUS0_COUNT (17)
+
+
+typedef struct st_intc
+{
+                                                           /* INTC             */
     volatile uint32_t  ICDDCR;                                 /*  ICDDCR          */
     volatile uint32_t  ICDICTR;                                /*  ICDICTR         */
     volatile uint32_t  ICDIIDR;                                /*  ICDIIDR         */
     volatile uint8_t   dummy193[116];                          /*                  */
-#define INTC_ICDISR0_COUNT 19
+
+/* #define INTC_ICDISR0_COUNT (19) */
     volatile uint32_t  ICDISR0;                                /*  ICDISR0         */
     volatile uint32_t  ICDISR1;                                /*  ICDISR1         */
     volatile uint32_t  ICDISR2;                                /*  ICDISR2         */
@@ -58,7 +557,8 @@
     volatile uint32_t  ICDISR17;                               /*  ICDISR17        */
     volatile uint32_t  ICDISR18;                               /*  ICDISR18        */
     volatile uint8_t   dummy194[52];                           /*                  */
-#define INTC_ICDISER0_COUNT 19
+
+/* #define INTC_ICDISER0_COUNT (19) */
     volatile uint32_t  ICDISER0;                               /*  ICDISER0        */
     volatile uint32_t  ICDISER1;                               /*  ICDISER1        */
     volatile uint32_t  ICDISER2;                               /*  ICDISER2        */
@@ -79,7 +579,8 @@
     volatile uint32_t  ICDISER17;                              /*  ICDISER17       */
     volatile uint32_t  ICDISER18;                              /*  ICDISER18       */
     volatile uint8_t   dummy195[52];                           /*                  */
-#define INTC_ICDICER0_COUNT 19
+
+/* #define INTC_ICDICER0_COUNT (19) */
     volatile uint32_t  ICDICER0;                               /*  ICDICER0        */
     volatile uint32_t  ICDICER1;                               /*  ICDICER1        */
     volatile uint32_t  ICDICER2;                               /*  ICDICER2        */
@@ -100,7 +601,8 @@
     volatile uint32_t  ICDICER17;                              /*  ICDICER17       */
     volatile uint32_t  ICDICER18;                              /*  ICDICER18       */
     volatile uint8_t   dummy196[52];                           /*                  */
-#define INTC_ICDISPR0_COUNT 19
+
+/* #define INTC_ICDISPR0_COUNT (19) */
     volatile uint32_t  ICDISPR0;                               /*  ICDISPR0        */
     volatile uint32_t  ICDISPR1;                               /*  ICDISPR1        */
     volatile uint32_t  ICDISPR2;                               /*  ICDISPR2        */
@@ -121,7 +623,8 @@
     volatile uint32_t  ICDISPR17;                              /*  ICDISPR17       */
     volatile uint32_t  ICDISPR18;                              /*  ICDISPR18       */
     volatile uint8_t   dummy197[52];                           /*                  */
-#define INTC_ICDICPR0_COUNT 19
+
+/* #define INTC_ICDICPR0_COUNT (19) */
     volatile uint32_t  ICDICPR0;                               /*  ICDICPR0        */
     volatile uint32_t  ICDICPR1;                               /*  ICDICPR1        */
     volatile uint32_t  ICDICPR2;                               /*  ICDICPR2        */
@@ -142,7 +645,8 @@
     volatile uint32_t  ICDICPR17;                              /*  ICDICPR17       */
     volatile uint32_t  ICDICPR18;                              /*  ICDICPR18       */
     volatile uint8_t   dummy198[52];                           /*                  */
-#define INTC_ICDABR0_COUNT 19
+
+/* #define INTC_ICDABR0_COUNT (19) */
     volatile uint32_t  ICDABR0;                                /*  ICDABR0         */
     volatile uint32_t  ICDABR1;                                /*  ICDABR1         */
     volatile uint32_t  ICDABR2;                                /*  ICDABR2         */
@@ -163,7 +667,8 @@
     volatile uint32_t  ICDABR17;                               /*  ICDABR17        */
     volatile uint32_t  ICDABR18;                               /*  ICDABR18        */
     volatile uint8_t   dummy199[180];                          /*                  */
-#define INTC_ICDIPR0_COUNT 147
+
+/* #define INTC_ICDIPR0_COUNT (147) */
     volatile uint32_t  ICDIPR0;                                /*  ICDIPR0         */
     volatile uint32_t  ICDIPR1;                                /*  ICDIPR1         */
     volatile uint32_t  ICDIPR2;                                /*  ICDIPR2         */
@@ -312,7 +817,8 @@
     volatile uint32_t  ICDIPR145;                              /*  ICDIPR145       */
     volatile uint32_t  ICDIPR146;                              /*  ICDIPR146       */
     volatile uint8_t   dummy200[436];                          /*                  */
-#define INTC_ICDIPTR0_COUNT 147
+
+/* #define INTC_ICDIPTR0_COUNT (147) */
     volatile uint32_t  ICDIPTR0;                               /*  ICDIPTR0        */
     volatile uint32_t  ICDIPTR1;                               /*  ICDIPTR1        */
     volatile uint32_t  ICDIPTR2;                               /*  ICDIPTR2        */
@@ -461,7 +967,8 @@
     volatile uint32_t  ICDIPTR145;                             /*  ICDIPTR145      */
     volatile uint32_t  ICDIPTR146;                             /*  ICDIPTR146      */
     volatile uint8_t   dummy201[436];                          /*                  */
-#define INTC_ICDICFR0_COUNT 37
+
+/* #define INTC_ICDICFR0_COUNT (37) */
     volatile uint32_t  ICDICFR0;                               /*  ICDICFR0        */
     volatile uint32_t  ICDICFR1;                               /*  ICDICFR1        */
     volatile uint32_t  ICDICFR2;                               /*  ICDICFR2        */
@@ -501,7 +1008,8 @@
     volatile uint32_t  ICDICFR36;                              /*  ICDICFR36       */
     volatile uint8_t   dummy202[108];                          /*                  */
     volatile uint32_t  PPI_STATUS;                             /*  PPI_STATUS      */
-#define INTC_SPI_STATUS0_COUNT 17
+
+/* #define INTC_SPI_STATUS0_COUNT (17) */
     volatile uint32_t  SPI_STATUS0;                            /*  SPI_STATUS0     */
     volatile uint32_t  SPI_STATUS1;                            /*  SPI_STATUS1     */
     volatile uint32_t  SPI_STATUS2;                            /*  SPI_STATUS2     */
@@ -536,491 +1044,11 @@
     volatile uint16_t ICR0;                                   /*  ICR0            */
     volatile uint16_t ICR1;                                   /*  ICR1            */
     volatile uint16_t IRQRR;                                  /*  IRQRR           */
-};
-
-
-#define INTC    (*(struct st_intc    *)0xE8201000uL) /* INTC */
+} r_io_intc_t;
 
 
-#define INTCICDDCR INTC.ICDDCR
-#define INTCICDICTR INTC.ICDICTR
-#define INTCICDIIDR INTC.ICDIIDR
-#define INTCICDISR0 INTC.ICDISR0
-#define INTCICDISR1 INTC.ICDISR1
-#define INTCICDISR2 INTC.ICDISR2
-#define INTCICDISR3 INTC.ICDISR3
-#define INTCICDISR4 INTC.ICDISR4
-#define INTCICDISR5 INTC.ICDISR5
-#define INTCICDISR6 INTC.ICDISR6
-#define INTCICDISR7 INTC.ICDISR7
-#define INTCICDISR8 INTC.ICDISR8
-#define INTCICDISR9 INTC.ICDISR9
-#define INTCICDISR10 INTC.ICDISR10
-#define INTCICDISR11 INTC.ICDISR11
-#define INTCICDISR12 INTC.ICDISR12
-#define INTCICDISR13 INTC.ICDISR13
-#define INTCICDISR14 INTC.ICDISR14
-#define INTCICDISR15 INTC.ICDISR15
-#define INTCICDISR16 INTC.ICDISR16
-#define INTCICDISR17 INTC.ICDISR17
-#define INTCICDISR18 INTC.ICDISR18
-#define INTCICDISER0 INTC.ICDISER0
-#define INTCICDISER1 INTC.ICDISER1
-#define INTCICDISER2 INTC.ICDISER2
-#define INTCICDISER3 INTC.ICDISER3
-#define INTCICDISER4 INTC.ICDISER4
-#define INTCICDISER5 INTC.ICDISER5
-#define INTCICDISER6 INTC.ICDISER6
-#define INTCICDISER7 INTC.ICDISER7
-#define INTCICDISER8 INTC.ICDISER8
-#define INTCICDISER9 INTC.ICDISER9
-#define INTCICDISER10 INTC.ICDISER10
-#define INTCICDISER11 INTC.ICDISER11
-#define INTCICDISER12 INTC.ICDISER12
-#define INTCICDISER13 INTC.ICDISER13
-#define INTCICDISER14 INTC.ICDISER14
-#define INTCICDISER15 INTC.ICDISER15
-#define INTCICDISER16 INTC.ICDISER16
-#define INTCICDISER17 INTC.ICDISER17
-#define INTCICDISER18 INTC.ICDISER18
-#define INTCICDICER0 INTC.ICDICER0
-#define INTCICDICER1 INTC.ICDICER1
-#define INTCICDICER2 INTC.ICDICER2
-#define INTCICDICER3 INTC.ICDICER3
-#define INTCICDICER4 INTC.ICDICER4
-#define INTCICDICER5 INTC.ICDICER5
-#define INTCICDICER6 INTC.ICDICER6
-#define INTCICDICER7 INTC.ICDICER7
-#define INTCICDICER8 INTC.ICDICER8
-#define INTCICDICER9 INTC.ICDICER9
-#define INTCICDICER10 INTC.ICDICER10
-#define INTCICDICER11 INTC.ICDICER11
-#define INTCICDICER12 INTC.ICDICER12
-#define INTCICDICER13 INTC.ICDICER13
-#define INTCICDICER14 INTC.ICDICER14
-#define INTCICDICER15 INTC.ICDICER15
-#define INTCICDICER16 INTC.ICDICER16
-#define INTCICDICER17 INTC.ICDICER17
-#define INTCICDICER18 INTC.ICDICER18
-#define INTCICDISPR0 INTC.ICDISPR0
-#define INTCICDISPR1 INTC.ICDISPR1
-#define INTCICDISPR2 INTC.ICDISPR2
-#define INTCICDISPR3 INTC.ICDISPR3
-#define INTCICDISPR4 INTC.ICDISPR4
-#define INTCICDISPR5 INTC.ICDISPR5
-#define INTCICDISPR6 INTC.ICDISPR6
-#define INTCICDISPR7 INTC.ICDISPR7
-#define INTCICDISPR8 INTC.ICDISPR8
-#define INTCICDISPR9 INTC.ICDISPR9
-#define INTCICDISPR10 INTC.ICDISPR10
-#define INTCICDISPR11 INTC.ICDISPR11
-#define INTCICDISPR12 INTC.ICDISPR12
-#define INTCICDISPR13 INTC.ICDISPR13
-#define INTCICDISPR14 INTC.ICDISPR14
-#define INTCICDISPR15 INTC.ICDISPR15
-#define INTCICDISPR16 INTC.ICDISPR16
-#define INTCICDISPR17 INTC.ICDISPR17
-#define INTCICDISPR18 INTC.ICDISPR18
-#define INTCICDICPR0 INTC.ICDICPR0
-#define INTCICDICPR1 INTC.ICDICPR1
-#define INTCICDICPR2 INTC.ICDICPR2
-#define INTCICDICPR3 INTC.ICDICPR3
-#define INTCICDICPR4 INTC.ICDICPR4
-#define INTCICDICPR5 INTC.ICDICPR5
-#define INTCICDICPR6 INTC.ICDICPR6
-#define INTCICDICPR7 INTC.ICDICPR7
-#define INTCICDICPR8 INTC.ICDICPR8
-#define INTCICDICPR9 INTC.ICDICPR9
-#define INTCICDICPR10 INTC.ICDICPR10
-#define INTCICDICPR11 INTC.ICDICPR11
-#define INTCICDICPR12 INTC.ICDICPR12
-#define INTCICDICPR13 INTC.ICDICPR13
-#define INTCICDICPR14 INTC.ICDICPR14
-#define INTCICDICPR15 INTC.ICDICPR15
-#define INTCICDICPR16 INTC.ICDICPR16
-#define INTCICDICPR17 INTC.ICDICPR17
-#define INTCICDICPR18 INTC.ICDICPR18
-#define INTCICDABR0 INTC.ICDABR0
-#define INTCICDABR1 INTC.ICDABR1
-#define INTCICDABR2 INTC.ICDABR2
-#define INTCICDABR3 INTC.ICDABR3
-#define INTCICDABR4 INTC.ICDABR4
-#define INTCICDABR5 INTC.ICDABR5
-#define INTCICDABR6 INTC.ICDABR6
-#define INTCICDABR7 INTC.ICDABR7
-#define INTCICDABR8 INTC.ICDABR8
-#define INTCICDABR9 INTC.ICDABR9
-#define INTCICDABR10 INTC.ICDABR10
-#define INTCICDABR11 INTC.ICDABR11
-#define INTCICDABR12 INTC.ICDABR12
-#define INTCICDABR13 INTC.ICDABR13
-#define INTCICDABR14 INTC.ICDABR14
-#define INTCICDABR15 INTC.ICDABR15
-#define INTCICDABR16 INTC.ICDABR16
-#define INTCICDABR17 INTC.ICDABR17
-#define INTCICDABR18 INTC.ICDABR18
-#define INTCICDIPR0 INTC.ICDIPR0
-#define INTCICDIPR1 INTC.ICDIPR1
-#define INTCICDIPR2 INTC.ICDIPR2
-#define INTCICDIPR3 INTC.ICDIPR3
-#define INTCICDIPR4 INTC.ICDIPR4
-#define INTCICDIPR5 INTC.ICDIPR5
-#define INTCICDIPR6 INTC.ICDIPR6
-#define INTCICDIPR7 INTC.ICDIPR7
-#define INTCICDIPR8 INTC.ICDIPR8
-#define INTCICDIPR9 INTC.ICDIPR9
-#define INTCICDIPR10 INTC.ICDIPR10
-#define INTCICDIPR11 INTC.ICDIPR11
-#define INTCICDIPR12 INTC.ICDIPR12
-#define INTCICDIPR13 INTC.ICDIPR13
-#define INTCICDIPR14 INTC.ICDIPR14
-#define INTCICDIPR15 INTC.ICDIPR15
-#define INTCICDIPR16 INTC.ICDIPR16
-#define INTCICDIPR17 INTC.ICDIPR17
-#define INTCICDIPR18 INTC.ICDIPR18
-#define INTCICDIPR19 INTC.ICDIPR19
-#define INTCICDIPR20 INTC.ICDIPR20
-#define INTCICDIPR21 INTC.ICDIPR21
-#define INTCICDIPR22 INTC.ICDIPR22
-#define INTCICDIPR23 INTC.ICDIPR23
-#define INTCICDIPR24 INTC.ICDIPR24
-#define INTCICDIPR25 INTC.ICDIPR25
-#define INTCICDIPR26 INTC.ICDIPR26
-#define INTCICDIPR27 INTC.ICDIPR27
-#define INTCICDIPR28 INTC.ICDIPR28
-#define INTCICDIPR29 INTC.ICDIPR29
-#define INTCICDIPR30 INTC.ICDIPR30
-#define INTCICDIPR31 INTC.ICDIPR31
-#define INTCICDIPR32 INTC.ICDIPR32
-#define INTCICDIPR33 INTC.ICDIPR33
-#define INTCICDIPR34 INTC.ICDIPR34
-#define INTCICDIPR35 INTC.ICDIPR35
-#define INTCICDIPR36 INTC.ICDIPR36
-#define INTCICDIPR37 INTC.ICDIPR37
-#define INTCICDIPR38 INTC.ICDIPR38
-#define INTCICDIPR39 INTC.ICDIPR39
-#define INTCICDIPR40 INTC.ICDIPR40
-#define INTCICDIPR41 INTC.ICDIPR41
-#define INTCICDIPR42 INTC.ICDIPR42
-#define INTCICDIPR43 INTC.ICDIPR43
-#define INTCICDIPR44 INTC.ICDIPR44
-#define INTCICDIPR45 INTC.ICDIPR45
-#define INTCICDIPR46 INTC.ICDIPR46
-#define INTCICDIPR47 INTC.ICDIPR47
-#define INTCICDIPR48 INTC.ICDIPR48
-#define INTCICDIPR49 INTC.ICDIPR49
-#define INTCICDIPR50 INTC.ICDIPR50
-#define INTCICDIPR51 INTC.ICDIPR51
-#define INTCICDIPR52 INTC.ICDIPR52
-#define INTCICDIPR53 INTC.ICDIPR53
-#define INTCICDIPR54 INTC.ICDIPR54
-#define INTCICDIPR55 INTC.ICDIPR55
-#define INTCICDIPR56 INTC.ICDIPR56
-#define INTCICDIPR57 INTC.ICDIPR57
-#define INTCICDIPR58 INTC.ICDIPR58
-#define INTCICDIPR59 INTC.ICDIPR59
-#define INTCICDIPR60 INTC.ICDIPR60
-#define INTCICDIPR61 INTC.ICDIPR61
-#define INTCICDIPR62 INTC.ICDIPR62
-#define INTCICDIPR63 INTC.ICDIPR63
-#define INTCICDIPR64 INTC.ICDIPR64
-#define INTCICDIPR65 INTC.ICDIPR65
-#define INTCICDIPR66 INTC.ICDIPR66
-#define INTCICDIPR67 INTC.ICDIPR67
-#define INTCICDIPR68 INTC.ICDIPR68
-#define INTCICDIPR69 INTC.ICDIPR69
-#define INTCICDIPR70 INTC.ICDIPR70
-#define INTCICDIPR71 INTC.ICDIPR71
-#define INTCICDIPR72 INTC.ICDIPR72
-#define INTCICDIPR73 INTC.ICDIPR73
-#define INTCICDIPR74 INTC.ICDIPR74
-#define INTCICDIPR75 INTC.ICDIPR75
-#define INTCICDIPR76 INTC.ICDIPR76
-#define INTCICDIPR77 INTC.ICDIPR77
-#define INTCICDIPR78 INTC.ICDIPR78
-#define INTCICDIPR79 INTC.ICDIPR79
-#define INTCICDIPR80 INTC.ICDIPR80
-#define INTCICDIPR81 INTC.ICDIPR81
-#define INTCICDIPR82 INTC.ICDIPR82
-#define INTCICDIPR83 INTC.ICDIPR83
-#define INTCICDIPR84 INTC.ICDIPR84
-#define INTCICDIPR85 INTC.ICDIPR85
-#define INTCICDIPR86 INTC.ICDIPR86
-#define INTCICDIPR87 INTC.ICDIPR87
-#define INTCICDIPR88 INTC.ICDIPR88
-#define INTCICDIPR89 INTC.ICDIPR89
-#define INTCICDIPR90 INTC.ICDIPR90
-#define INTCICDIPR91 INTC.ICDIPR91
-#define INTCICDIPR92 INTC.ICDIPR92
-#define INTCICDIPR93 INTC.ICDIPR93
-#define INTCICDIPR94 INTC.ICDIPR94
-#define INTCICDIPR95 INTC.ICDIPR95
-#define INTCICDIPR96 INTC.ICDIPR96
-#define INTCICDIPR97 INTC.ICDIPR97
-#define INTCICDIPR98 INTC.ICDIPR98
-#define INTCICDIPR99 INTC.ICDIPR99
-#define INTCICDIPR100 INTC.ICDIPR100
-#define INTCICDIPR101 INTC.ICDIPR101
-#define INTCICDIPR102 INTC.ICDIPR102
-#define INTCICDIPR103 INTC.ICDIPR103
-#define INTCICDIPR104 INTC.ICDIPR104
-#define INTCICDIPR105 INTC.ICDIPR105
-#define INTCICDIPR106 INTC.ICDIPR106
-#define INTCICDIPR107 INTC.ICDIPR107
-#define INTCICDIPR108 INTC.ICDIPR108
-#define INTCICDIPR109 INTC.ICDIPR109
-#define INTCICDIPR110 INTC.ICDIPR110
-#define INTCICDIPR111 INTC.ICDIPR111
-#define INTCICDIPR112 INTC.ICDIPR112
-#define INTCICDIPR113 INTC.ICDIPR113
-#define INTCICDIPR114 INTC.ICDIPR114
-#define INTCICDIPR115 INTC.ICDIPR115
-#define INTCICDIPR116 INTC.ICDIPR116
-#define INTCICDIPR117 INTC.ICDIPR117
-#define INTCICDIPR118 INTC.ICDIPR118
-#define INTCICDIPR119 INTC.ICDIPR119
-#define INTCICDIPR120 INTC.ICDIPR120
-#define INTCICDIPR121 INTC.ICDIPR121
-#define INTCICDIPR122 INTC.ICDIPR122
-#define INTCICDIPR123 INTC.ICDIPR123
-#define INTCICDIPR124 INTC.ICDIPR124
-#define INTCICDIPR125 INTC.ICDIPR125
-#define INTCICDIPR126 INTC.ICDIPR126
-#define INTCICDIPR127 INTC.ICDIPR127
-#define INTCICDIPR128 INTC.ICDIPR128
-#define INTCICDIPR129 INTC.ICDIPR129
-#define INTCICDIPR130 INTC.ICDIPR130
-#define INTCICDIPR131 INTC.ICDIPR131
-#define INTCICDIPR132 INTC.ICDIPR132
-#define INTCICDIPR133 INTC.ICDIPR133
-#define INTCICDIPR134 INTC.ICDIPR134
-#define INTCICDIPR135 INTC.ICDIPR135
-#define INTCICDIPR136 INTC.ICDIPR136
-#define INTCICDIPR137 INTC.ICDIPR137
-#define INTCICDIPR138 INTC.ICDIPR138
-#define INTCICDIPR139 INTC.ICDIPR139
-#define INTCICDIPR140 INTC.ICDIPR140
-#define INTCICDIPR141 INTC.ICDIPR141
-#define INTCICDIPR142 INTC.ICDIPR142
-#define INTCICDIPR143 INTC.ICDIPR143
-#define INTCICDIPR144 INTC.ICDIPR144
-#define INTCICDIPR145 INTC.ICDIPR145
-#define INTCICDIPR146 INTC.ICDIPR146
-#define INTCICDIPTR0 INTC.ICDIPTR0
-#define INTCICDIPTR1 INTC.ICDIPTR1
-#define INTCICDIPTR2 INTC.ICDIPTR2
-#define INTCICDIPTR3 INTC.ICDIPTR3
-#define INTCICDIPTR4 INTC.ICDIPTR4
-#define INTCICDIPTR5 INTC.ICDIPTR5
-#define INTCICDIPTR6 INTC.ICDIPTR6
-#define INTCICDIPTR7 INTC.ICDIPTR7
-#define INTCICDIPTR8 INTC.ICDIPTR8
-#define INTCICDIPTR9 INTC.ICDIPTR9
-#define INTCICDIPTR10 INTC.ICDIPTR10
-#define INTCICDIPTR11 INTC.ICDIPTR11
-#define INTCICDIPTR12 INTC.ICDIPTR12
-#define INTCICDIPTR13 INTC.ICDIPTR13
-#define INTCICDIPTR14 INTC.ICDIPTR14
-#define INTCICDIPTR15 INTC.ICDIPTR15
-#define INTCICDIPTR16 INTC.ICDIPTR16
-#define INTCICDIPTR17 INTC.ICDIPTR17
-#define INTCICDIPTR18 INTC.ICDIPTR18
-#define INTCICDIPTR19 INTC.ICDIPTR19
-#define INTCICDIPTR20 INTC.ICDIPTR20
-#define INTCICDIPTR21 INTC.ICDIPTR21
-#define INTCICDIPTR22 INTC.ICDIPTR22
-#define INTCICDIPTR23 INTC.ICDIPTR23
-#define INTCICDIPTR24 INTC.ICDIPTR24
-#define INTCICDIPTR25 INTC.ICDIPTR25
-#define INTCICDIPTR26 INTC.ICDIPTR26
-#define INTCICDIPTR27 INTC.ICDIPTR27
-#define INTCICDIPTR28 INTC.ICDIPTR28
-#define INTCICDIPTR29 INTC.ICDIPTR29
-#define INTCICDIPTR30 INTC.ICDIPTR30
-#define INTCICDIPTR31 INTC.ICDIPTR31
-#define INTCICDIPTR32 INTC.ICDIPTR32
-#define INTCICDIPTR33 INTC.ICDIPTR33
-#define INTCICDIPTR34 INTC.ICDIPTR34
-#define INTCICDIPTR35 INTC.ICDIPTR35
-#define INTCICDIPTR36 INTC.ICDIPTR36
-#define INTCICDIPTR37 INTC.ICDIPTR37
-#define INTCICDIPTR38 INTC.ICDIPTR38
-#define INTCICDIPTR39 INTC.ICDIPTR39
-#define INTCICDIPTR40 INTC.ICDIPTR40
-#define INTCICDIPTR41 INTC.ICDIPTR41
-#define INTCICDIPTR42 INTC.ICDIPTR42
-#define INTCICDIPTR43 INTC.ICDIPTR43
-#define INTCICDIPTR44 INTC.ICDIPTR44
-#define INTCICDIPTR45 INTC.ICDIPTR45
-#define INTCICDIPTR46 INTC.ICDIPTR46
-#define INTCICDIPTR47 INTC.ICDIPTR47
-#define INTCICDIPTR48 INTC.ICDIPTR48
-#define INTCICDIPTR49 INTC.ICDIPTR49
-#define INTCICDIPTR50 INTC.ICDIPTR50
-#define INTCICDIPTR51 INTC.ICDIPTR51
-#define INTCICDIPTR52 INTC.ICDIPTR52
-#define INTCICDIPTR53 INTC.ICDIPTR53
-#define INTCICDIPTR54 INTC.ICDIPTR54
-#define INTCICDIPTR55 INTC.ICDIPTR55
-#define INTCICDIPTR56 INTC.ICDIPTR56
-#define INTCICDIPTR57 INTC.ICDIPTR57
-#define INTCICDIPTR58 INTC.ICDIPTR58
-#define INTCICDIPTR59 INTC.ICDIPTR59
-#define INTCICDIPTR60 INTC.ICDIPTR60
-#define INTCICDIPTR61 INTC.ICDIPTR61
-#define INTCICDIPTR62 INTC.ICDIPTR62
-#define INTCICDIPTR63 INTC.ICDIPTR63
-#define INTCICDIPTR64 INTC.ICDIPTR64
-#define INTCICDIPTR65 INTC.ICDIPTR65
-#define INTCICDIPTR66 INTC.ICDIPTR66
-#define INTCICDIPTR67 INTC.ICDIPTR67
-#define INTCICDIPTR68 INTC.ICDIPTR68
-#define INTCICDIPTR69 INTC.ICDIPTR69
-#define INTCICDIPTR70 INTC.ICDIPTR70
-#define INTCICDIPTR71 INTC.ICDIPTR71
-#define INTCICDIPTR72 INTC.ICDIPTR72
-#define INTCICDIPTR73 INTC.ICDIPTR73
-#define INTCICDIPTR74 INTC.ICDIPTR74
-#define INTCICDIPTR75 INTC.ICDIPTR75
-#define INTCICDIPTR76 INTC.ICDIPTR76
-#define INTCICDIPTR77 INTC.ICDIPTR77
-#define INTCICDIPTR78 INTC.ICDIPTR78
-#define INTCICDIPTR79 INTC.ICDIPTR79
-#define INTCICDIPTR80 INTC.ICDIPTR80
-#define INTCICDIPTR81 INTC.ICDIPTR81
-#define INTCICDIPTR82 INTC.ICDIPTR82
-#define INTCICDIPTR83 INTC.ICDIPTR83
-#define INTCICDIPTR84 INTC.ICDIPTR84
-#define INTCICDIPTR85 INTC.ICDIPTR85
-#define INTCICDIPTR86 INTC.ICDIPTR86
-#define INTCICDIPTR87 INTC.ICDIPTR87
-#define INTCICDIPTR88 INTC.ICDIPTR88
-#define INTCICDIPTR89 INTC.ICDIPTR89
-#define INTCICDIPTR90 INTC.ICDIPTR90
-#define INTCICDIPTR91 INTC.ICDIPTR91
-#define INTCICDIPTR92 INTC.ICDIPTR92
-#define INTCICDIPTR93 INTC.ICDIPTR93
-#define INTCICDIPTR94 INTC.ICDIPTR94
-#define INTCICDIPTR95 INTC.ICDIPTR95
-#define INTCICDIPTR96 INTC.ICDIPTR96
-#define INTCICDIPTR97 INTC.ICDIPTR97
-#define INTCICDIPTR98 INTC.ICDIPTR98
-#define INTCICDIPTR99 INTC.ICDIPTR99
-#define INTCICDIPTR100 INTC.ICDIPTR100
-#define INTCICDIPTR101 INTC.ICDIPTR101
-#define INTCICDIPTR102 INTC.ICDIPTR102
-#define INTCICDIPTR103 INTC.ICDIPTR103
-#define INTCICDIPTR104 INTC.ICDIPTR104
-#define INTCICDIPTR105 INTC.ICDIPTR105
-#define INTCICDIPTR106 INTC.ICDIPTR106
-#define INTCICDIPTR107 INTC.ICDIPTR107
-#define INTCICDIPTR108 INTC.ICDIPTR108
-#define INTCICDIPTR109 INTC.ICDIPTR109
-#define INTCICDIPTR110 INTC.ICDIPTR110
-#define INTCICDIPTR111 INTC.ICDIPTR111
-#define INTCICDIPTR112 INTC.ICDIPTR112
-#define INTCICDIPTR113 INTC.ICDIPTR113
-#define INTCICDIPTR114 INTC.ICDIPTR114
-#define INTCICDIPTR115 INTC.ICDIPTR115
-#define INTCICDIPTR116 INTC.ICDIPTR116
-#define INTCICDIPTR117 INTC.ICDIPTR117
-#define INTCICDIPTR118 INTC.ICDIPTR118
-#define INTCICDIPTR119 INTC.ICDIPTR119
-#define INTCICDIPTR120 INTC.ICDIPTR120
-#define INTCICDIPTR121 INTC.ICDIPTR121
-#define INTCICDIPTR122 INTC.ICDIPTR122
-#define INTCICDIPTR123 INTC.ICDIPTR123
-#define INTCICDIPTR124 INTC.ICDIPTR124
-#define INTCICDIPTR125 INTC.ICDIPTR125
-#define INTCICDIPTR126 INTC.ICDIPTR126
-#define INTCICDIPTR127 INTC.ICDIPTR127
-#define INTCICDIPTR128 INTC.ICDIPTR128
-#define INTCICDIPTR129 INTC.ICDIPTR129
-#define INTCICDIPTR130 INTC.ICDIPTR130
-#define INTCICDIPTR131 INTC.ICDIPTR131
-#define INTCICDIPTR132 INTC.ICDIPTR132
-#define INTCICDIPTR133 INTC.ICDIPTR133
-#define INTCICDIPTR134 INTC.ICDIPTR134
-#define INTCICDIPTR135 INTC.ICDIPTR135
-#define INTCICDIPTR136 INTC.ICDIPTR136
-#define INTCICDIPTR137 INTC.ICDIPTR137
-#define INTCICDIPTR138 INTC.ICDIPTR138
-#define INTCICDIPTR139 INTC.ICDIPTR139
-#define INTCICDIPTR140 INTC.ICDIPTR140
-#define INTCICDIPTR141 INTC.ICDIPTR141
-#define INTCICDIPTR142 INTC.ICDIPTR142
-#define INTCICDIPTR143 INTC.ICDIPTR143
-#define INTCICDIPTR144 INTC.ICDIPTR144
-#define INTCICDIPTR145 INTC.ICDIPTR145
-#define INTCICDIPTR146 INTC.ICDIPTR146
-#define INTCICDICFR0 INTC.ICDICFR0
-#define INTCICDICFR1 INTC.ICDICFR1
-#define INTCICDICFR2 INTC.ICDICFR2
-#define INTCICDICFR3 INTC.ICDICFR3
-#define INTCICDICFR4 INTC.ICDICFR4
-#define INTCICDICFR5 INTC.ICDICFR5
-#define INTCICDICFR6 INTC.ICDICFR6
-#define INTCICDICFR7 INTC.ICDICFR7
-#define INTCICDICFR8 INTC.ICDICFR8
-#define INTCICDICFR9 INTC.ICDICFR9
-#define INTCICDICFR10 INTC.ICDICFR10
-#define INTCICDICFR11 INTC.ICDICFR11
-#define INTCICDICFR12 INTC.ICDICFR12
-#define INTCICDICFR13 INTC.ICDICFR13
-#define INTCICDICFR14 INTC.ICDICFR14
-#define INTCICDICFR15 INTC.ICDICFR15
-#define INTCICDICFR16 INTC.ICDICFR16
-#define INTCICDICFR17 INTC.ICDICFR17
-#define INTCICDICFR18 INTC.ICDICFR18
-#define INTCICDICFR19 INTC.ICDICFR19
-#define INTCICDICFR20 INTC.ICDICFR20
-#define INTCICDICFR21 INTC.ICDICFR21
-#define INTCICDICFR22 INTC.ICDICFR22
-#define INTCICDICFR23 INTC.ICDICFR23
-#define INTCICDICFR24 INTC.ICDICFR24
-#define INTCICDICFR25 INTC.ICDICFR25
-#define INTCICDICFR26 INTC.ICDICFR26
-#define INTCICDICFR27 INTC.ICDICFR27
-#define INTCICDICFR28 INTC.ICDICFR28
-#define INTCICDICFR29 INTC.ICDICFR29
-#define INTCICDICFR30 INTC.ICDICFR30
-#define INTCICDICFR31 INTC.ICDICFR31
-#define INTCICDICFR32 INTC.ICDICFR32
-#define INTCICDICFR33 INTC.ICDICFR33
-#define INTCICDICFR34 INTC.ICDICFR34
-#define INTCICDICFR35 INTC.ICDICFR35
-#define INTCICDICFR36 INTC.ICDICFR36
-#define INTCPPI_STATUS INTC.PPI_STATUS
-#define INTCSPI_STATUS0 INTC.SPI_STATUS0
-#define INTCSPI_STATUS1 INTC.SPI_STATUS1
-#define INTCSPI_STATUS2 INTC.SPI_STATUS2
-#define INTCSPI_STATUS3 INTC.SPI_STATUS3
-#define INTCSPI_STATUS4 INTC.SPI_STATUS4
-#define INTCSPI_STATUS5 INTC.SPI_STATUS5
-#define INTCSPI_STATUS6 INTC.SPI_STATUS6
-#define INTCSPI_STATUS7 INTC.SPI_STATUS7
-#define INTCSPI_STATUS8 INTC.SPI_STATUS8
-#define INTCSPI_STATUS9 INTC.SPI_STATUS9
-#define INTCSPI_STATUS10 INTC.SPI_STATUS10
-#define INTCSPI_STATUS11 INTC.SPI_STATUS11
-#define INTCSPI_STATUS12 INTC.SPI_STATUS12
-#define INTCSPI_STATUS13 INTC.SPI_STATUS13
-#define INTCSPI_STATUS14 INTC.SPI_STATUS14
-#define INTCSPI_STATUS15 INTC.SPI_STATUS15
-#define INTCSPI_STATUS16 INTC.SPI_STATUS16
-#define INTCICDSGIR INTC.ICDSGIR
-#define INTCICCICR INTC.ICCICR
-#define INTCICCPMR INTC.ICCPMR
-#define INTCICCBPR INTC.ICCBPR
-#define INTCICCIAR INTC.ICCIAR
-#define INTCICCEOIR INTC.ICCEOIR
-#define INTCICCRPR INTC.ICCRPR
-#define INTCICCHPIR INTC.ICCHPIR
-#define INTCICCABPR INTC.ICCABPR
-#define INTCICCIIDR INTC.ICCIIDR
-#define INTCICR0 INTC.ICR0
-#define INTCICR1 INTC.ICR1
-#define INTCIRQRR INTC.IRQRR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/iodefine_typedef.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,118 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer*
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : iodefine_typedef.h
+* $Rev: $
+* $Date::                           $
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
+******************************************************************************/
+#ifndef IODEFINE_TYPEDEF_H
+#define IODEFINE_TYPEDEF_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
+
+/* Shared types and macros for iodefine.h */
+
+/***********************************************************************
+* Macro: IODEFINE_H_VERSION
+************************************************************************/
+#define IODEFINE_H_VERSION  (200)
+
+
+/***********************************************************************
+* Enum: iodefine_byte_select_t
+*
+*   R_IO_L - Low 16bit or Low 8 bit
+*   R_IO_H - High 16bit or Low 8 bit
+*   R_IO_LL - Low 8 bit
+*   R_IO_LH - Middle Low 8 bit
+*   R_IO_HL - Middle High 8 bit
+*   R_IO_HH - High 8 bit
+************************************************************************/
+typedef enum iodefine_byte_select_t
+{
+    R_IO_L = 0, R_IO_H = 1,
+    R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3,
+    L = 0, H = 1,
+    LL= 0, LH = 1, HL = 2, HH = 3
+} iodefine_byte_select_t;
+
+
+/***********************************************************************
+* Type: iodefine_reg32_t
+*   32/16/8 bit access register
+*
+* - Padding : sizeof(iodefine_reg32_t) == 4
+* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+*                       &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
+* - Endian : Independent (Same as CPU endian as register endian)
+* - Bit-Order : Independent
+************************************************************************/
+typedef union iodefine_reg32_t
+{
+    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
+    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
+    volatile uint8_t   UINT8[4];                                /*  8-bit Access    */
+} iodefine_reg32_t;
+
+
+/***********************************************************************
+* Type: iodefine_reg32_16_t
+*   32/16 bit access register
+* 
+* - Padding : sizeof(iodefine_reg32_16_t) == 4
+* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
+* - Endian : Independent (Same as CPU endian as register endian)
+* - Bit-Order : Independent
+************************************************************************/
+typedef union iodefine_reg32_16_t
+{
+    volatile uint32_t  UINT32;                                  /*  32-bit Access   */
+    volatile uint16_t  UINT16[2];                               /*  16-bit Access   */
+} iodefine_reg32_16_t;
+
+
+/***********************************************************************
+* Type: iodefine_reg16_8_t
+*   16/8 bit access register
+* 
+* - Padding : sizeof(iodefine_reg16_8_t) == 2
+* - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
+* - Endian : Independent (Same as CPU endian as register endian)
+* - Bit-Order : Independent
+************************************************************************/
+typedef union iodefine_reg16_8_t
+{
+    volatile uint16_t  UINT16;                                  /*  16-bit Access   */
+    volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
+} iodefine_reg16_8_t;
+
+
+/* End of shared types and macros for iodefine.h */
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
+#endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/irda_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,25 +18,36 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : irda_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef IRDA_IODEFINE_H
 #define IRDA_IODEFINE_H
-
-struct st_irda
-{                                                          /* IRDA             */
-    volatile uint8_t   IRCR;                                   /*  IRCR            */
-};
-
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
 #define IRDA    (*(struct st_irda    *)0xE8014000uL) /* IRDA */
 
 
-#define IRDAIRCR IRDA.IRCR
+#define IRDAIRCR (IRDA.IRCR)
+
+
+typedef struct st_irda
+{
+                                                           /* IRDA             */
+    volatile uint8_t   IRCR;                                   /*  IRCR            */
+} r_io_irda_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/jcu_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,88 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : jcu_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef JCU_IODEFINE_H
 #define JCU_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_jcu
-{                                                          /* JCU              */
+#define JCU     (*(struct st_jcu     *)0xE8017000uL) /* JCU */
+
+
+/* Start of channel array defines of JCU */
+
+/* Channel array defines of JCU_JCQTBL0 */
+/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
+#define JCU_JCQTBL0_COUNT  (4)
+#define JCU_JCQTBL0_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
+#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
+#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
+#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
+
+/* End of channel array defines of JCU */
+
+
+#define JCUJCMOD (JCU.JCMOD)
+#define JCUJCCMD (JCU.JCCMD)
+#define JCUJCQTN (JCU.JCQTN)
+#define JCUJCHTN (JCU.JCHTN)
+#define JCUJCDRIU (JCU.JCDRIU)
+#define JCUJCDRID (JCU.JCDRID)
+#define JCUJCVSZU (JCU.JCVSZU)
+#define JCUJCVSZD (JCU.JCVSZD)
+#define JCUJCHSZU (JCU.JCHSZU)
+#define JCUJCHSZD (JCU.JCHSZD)
+#define JCUJCDTCU (JCU.JCDTCU)
+#define JCUJCDTCM (JCU.JCDTCM)
+#define JCUJCDTCD (JCU.JCDTCD)
+#define JCUJINTE0 (JCU.JINTE0)
+#define JCUJINTS0 (JCU.JINTS0)
+#define JCUJCDERR (JCU.JCDERR)
+#define JCUJCRST (JCU.JCRST)
+#define JCUJIFECNT (JCU.JIFECNT)
+#define JCUJIFESA (JCU.JIFESA)
+#define JCUJIFESOFST (JCU.JIFESOFST)
+#define JCUJIFEDA (JCU.JIFEDA)
+#define JCUJIFESLC (JCU.JIFESLC)
+#define JCUJIFEDDC (JCU.JIFEDDC)
+#define JCUJIFDCNT (JCU.JIFDCNT)
+#define JCUJIFDSA (JCU.JIFDSA)
+#define JCUJIFDDOFST (JCU.JIFDDOFST)
+#define JCUJIFDDA (JCU.JIFDDA)
+#define JCUJIFDSDC (JCU.JIFDSDC)
+#define JCUJIFDDLC (JCU.JIFDDLC)
+#define JCUJIFDADT (JCU.JIFDADT)
+#define JCUJINTE1 (JCU.JINTE1)
+#define JCUJINTS1 (JCU.JINTS1)
+#define JCUJIFESVSZ (JCU.JIFESVSZ)
+#define JCUJIFESHSZ (JCU.JIFESHSZ)
+#define JCUJCQTBL0 (JCU.JCQTBL0)
+#define JCUJCQTBL1 (JCU.JCQTBL1)
+#define JCUJCQTBL2 (JCU.JCQTBL2)
+#define JCUJCQTBL3 (JCU.JCQTBL3)
+#define JCUJCHTBD0 (JCU.JCHTBD0)
+#define JCUJCHTBA0 (JCU.JCHTBA0)
+#define JCUJCHTBD1 (JCU.JCHTBD1)
+#define JCUJCHTBA1 (JCU.JCHTBA1)
+
+
+typedef struct st_jcu
+{
+                                                           /* JCU              */
     volatile uint8_t   JCMOD;                                  /*  JCMOD           */
     volatile uint8_t   JCCMD;                                  /*  JCCMD           */
     volatile uint8_t   dummy145[1];                            /*                  */
@@ -70,21 +138,29 @@
     volatile uint32_t  JIFESVSZ;                               /*  JIFESVSZ        */
     volatile uint32_t  JIFESHSZ;                               /*  JIFESHSZ        */
     volatile uint8_t   dummy148[100];                          /*                  */
+
 /* start of struct st_jcu_from_jcqtbl0 */
     volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
     volatile uint8_t   dummy149[63];                           /*                  */
+
 /* end of struct st_jcu_from_jcqtbl0 */
+
 /* start of struct st_jcu_from_jcqtbl0 */
     volatile uint8_t   JCQTBL1;                                /*  JCQTBL1         */
     volatile uint8_t   dummy150[63];                           /*                  */
+
 /* end of struct st_jcu_from_jcqtbl0 */
+
 /* start of struct st_jcu_from_jcqtbl0 */
     volatile uint8_t   JCQTBL2;                                /*  JCQTBL2         */
     volatile uint8_t   dummy151[63];                           /*                  */
+
 /* end of struct st_jcu_from_jcqtbl0 */
+
 /* start of struct st_jcu_from_jcqtbl0 */
     volatile uint8_t   JCQTBL3;                                /*  JCQTBL3         */
     volatile uint8_t   dummy152[63];                           /*                  */
+
 /* end of struct st_jcu_from_jcqtbl0 */
     volatile uint8_t   JCHTBD0;                                /*  JCHTBD0         */
     volatile uint8_t   dummy153[31];                           /*                  */
@@ -93,77 +169,29 @@
     volatile uint8_t   JCHTBD1;                                /*  JCHTBD1         */
     volatile uint8_t   dummy155[31];                           /*                  */
     volatile uint8_t   JCHTBA1;                                /*  JCHTBA1         */
-};
-
-
-struct st_jcu_from_jcqtbl0
-{
-    volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
-    volatile uint8_t   dummy1[63];                             /*                  */
-};
-
-
-#define JCU     (*(struct st_jcu     *)0xE8017000uL) /* JCU */
+} r_io_jcu_t;
 
 
-/* Start of channnel array defines of JCU */
-
-/* Channnel array defines of JCU_JCQTBL0 */
-/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
-#define JCU_JCQTBL0_COUNT  4
-#define JCU_JCQTBL0_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
-#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
-#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
-#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
-
-/* End of channnel array defines of JCU */
+typedef struct st_jcu_from_jcqtbl0
+{
+ 
+    volatile uint8_t   JCQTBL0;                                /*  JCQTBL0         */
+    volatile uint8_t   dummy1[63];                             /*                  */
+} r_io_jcu_from_jcqtbl0_t;
 
 
-#define JCUJCMOD JCU.JCMOD
-#define JCUJCCMD JCU.JCCMD
-#define JCUJCQTN JCU.JCQTN
-#define JCUJCHTN JCU.JCHTN
-#define JCUJCDRIU JCU.JCDRIU
-#define JCUJCDRID JCU.JCDRID
-#define JCUJCVSZU JCU.JCVSZU
-#define JCUJCVSZD JCU.JCVSZD
-#define JCUJCHSZU JCU.JCHSZU
-#define JCUJCHSZD JCU.JCHSZD
-#define JCUJCDTCU JCU.JCDTCU
-#define JCUJCDTCM JCU.JCDTCM
-#define JCUJCDTCD JCU.JCDTCD
-#define JCUJINTE0 JCU.JINTE0
-#define JCUJINTS0 JCU.JINTS0
-#define JCUJCDERR JCU.JCDERR
-#define JCUJCRST JCU.JCRST
-#define JCUJIFECNT JCU.JIFECNT
-#define JCUJIFESA JCU.JIFESA
-#define JCUJIFESOFST JCU.JIFESOFST
-#define JCUJIFEDA JCU.JIFEDA
-#define JCUJIFESLC JCU.JIFESLC
-#define JCUJIFEDDC JCU.JIFEDDC
-#define JCUJIFDCNT JCU.JIFDCNT
-#define JCUJIFDSA JCU.JIFDSA
-#define JCUJIFDDOFST JCU.JIFDDOFST
-#define JCUJIFDDA JCU.JIFDDA
-#define JCUJIFDSDC JCU.JIFDSDC
-#define JCUJIFDDLC JCU.JIFDDLC
-#define JCUJIFDADT JCU.JIFDADT
-#define JCUJINTE1 JCU.JINTE1
-#define JCUJINTS1 JCU.JINTS1
-#define JCUJIFESVSZ JCU.JIFESVSZ
-#define JCUJIFESHSZ JCU.JIFESHSZ
-#define JCUJCQTBL0 JCU.JCQTBL0
-#define JCUJCQTBL1 JCU.JCQTBL1
-#define JCUJCQTBL2 JCU.JCQTBL2
-#define JCUJCQTBL3 JCU.JCQTBL3
-#define JCUJCHTBD0 JCU.JCHTBD0
-#define JCUJCHTBA0 JCU.JCHTBA0
-#define JCUJCHTBD1 JCU.JCHTBD1
-#define JCUJCHTBA1 JCU.JCHTBA1
+/* Channel array defines of JCU (2)*/
+#ifdef  DECLARE_JCU_JCQTBL0_CHANNELS
+volatile struct st_jcu_from_jcqtbl0*  JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    JCU_JCQTBL0_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_JCU_JCQTBL0_CHANNELS */
+/* End of channel array defines of JCU (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/l2c_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,97 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : l2c_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef L2C_IODEFINE_H
 #define L2C_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_l2c
-{                                                          /* L2C              */
+#define L2C     (*(struct st_l2c     *)0x3FFFF000uL) /* L2C */
+
+
+/* Start of channel array defines of L2C */
+
+/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
+/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT  (8)
+#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
+#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
+#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
+#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
+#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
+#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
+#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
+#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
+
+/* End of channel array defines of L2C */
+
+
+#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID)
+#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE)
+#define L2CREG1_CONTROL (L2C.REG1_CONTROL)
+#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL)
+#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL)
+#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL)
+#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL)
+#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG)
+#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG)
+#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1)
+#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0)
+#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK)
+#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS)
+#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS)
+#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR)
+#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC)
+#define L2CREG7_INV_PA (L2C.REG7_INV_PA)
+#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY)
+#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA)
+#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX)
+#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY)
+#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA)
+#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX)
+#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY)
+#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0)
+#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0)
+#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1)
+#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1)
+#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2)
+#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2)
+#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3)
+#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3)
+#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4)
+#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4)
+#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5)
+#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5)
+#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6)
+#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6)
+#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7)
+#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7)
+#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN)
+#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY)
+#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START)
+#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END)
+#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL)
+#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL)
+#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL)
+
+
+typedef struct st_l2c
+{
+                                                           /* L2C              */
     volatile uint32_t  REG0_CACHE_ID;                          /*  REG0_CACHE_ID   */
     volatile uint32_t  REG0_CACHE_TYPE;                        /*  REG0_CACHE_TYPE */
     volatile uint8_t   dummy8[248];                            /*                  */
@@ -66,37 +143,53 @@
     volatile uint32_t  REG7_CLEAN_INV_INDEX;                   /*  REG7_CLEAN_INV_INDEX */
     volatile uint32_t  REG7_CLEAN_INV_WAY;                     /*  REG7_CLEAN_INV_WAY */
     volatile uint8_t   dummy17[256];                           /*                  */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
     volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN1;                       /*  REG9_D_LOCKDOWN1 */
     volatile uint32_t  REG9_I_LOCKDOWN1;                       /*  REG9_I_LOCKDOWN1 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN2;                       /*  REG9_D_LOCKDOWN2 */
     volatile uint32_t  REG9_I_LOCKDOWN2;                       /*  REG9_I_LOCKDOWN2 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN3;                       /*  REG9_D_LOCKDOWN3 */
     volatile uint32_t  REG9_I_LOCKDOWN3;                       /*  REG9_I_LOCKDOWN3 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN4;                       /*  REG9_D_LOCKDOWN4 */
     volatile uint32_t  REG9_I_LOCKDOWN4;                       /*  REG9_I_LOCKDOWN4 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN5;                       /*  REG9_D_LOCKDOWN5 */
     volatile uint32_t  REG9_I_LOCKDOWN5;                       /*  REG9_I_LOCKDOWN5 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN6;                       /*  REG9_D_LOCKDOWN6 */
     volatile uint32_t  REG9_I_LOCKDOWN6;                       /*  REG9_I_LOCKDOWN6 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
+
 /* start of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint32_t  REG9_D_LOCKDOWN7;                       /*  REG9_D_LOCKDOWN7 */
     volatile uint32_t  REG9_I_LOCKDOWN7;                       /*  REG9_I_LOCKDOWN7 */
+
 /* end of struct st_l2c_from_reg9_d_lockdown0 */
     volatile uint8_t   dummy18[16];                            /*                  */
     volatile uint32_t  REG9_LOCK_LINE_EN;                      /*  REG9_LOCK_LINE_EN */
@@ -110,86 +203,29 @@
     volatile uint32_t  REG15_PREFETCH_CTRL;                    /*  REG15_PREFETCH_CTRL */
     volatile uint8_t   dummy22[28];                            /*                  */
     volatile uint32_t  REG15_POWER_CTRL;                       /*  REG15_POWER_CTRL */
-};
-
-
-struct st_l2c_from_reg9_d_lockdown0
-{
-    volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
-    volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
-};
-
-
-#define L2C     (*(struct st_l2c     *)0x3FFFF000uL) /* L2C */
+} r_io_l2c_t;
 
 
-/* Start of channnel array defines of L2C */
-
-/* Channnel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
-/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
-#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT  8
-#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
-#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
-#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
-#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
-#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
-#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
-#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
-#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
-
-/* End of channnel array defines of L2C */
+typedef struct st_l2c_from_reg9_d_lockdown0
+{
+ 
+    volatile uint32_t  REG9_D_LOCKDOWN0;                       /*  REG9_D_LOCKDOWN0 */
+    volatile uint32_t  REG9_I_LOCKDOWN0;                       /*  REG9_I_LOCKDOWN0 */
+} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */;
 
 
-#define L2CREG0_CACHE_ID L2C.REG0_CACHE_ID
-#define L2CREG0_CACHE_TYPE L2C.REG0_CACHE_TYPE
-#define L2CREG1_CONTROL L2C.REG1_CONTROL
-#define L2CREG1_AUX_CONTROL L2C.REG1_AUX_CONTROL
-#define L2CREG1_TAG_RAM_CONTROL L2C.REG1_TAG_RAM_CONTROL
-#define L2CREG1_DATA_RAM_CONTROL L2C.REG1_DATA_RAM_CONTROL
-#define L2CREG2_EV_COUNTER_CTRL L2C.REG2_EV_COUNTER_CTRL
-#define L2CREG2_EV_COUNTER1_CFG L2C.REG2_EV_COUNTER1_CFG
-#define L2CREG2_EV_COUNTER0_CFG L2C.REG2_EV_COUNTER0_CFG
-#define L2CREG2_EV_COUNTER1 L2C.REG2_EV_COUNTER1
-#define L2CREG2_EV_COUNTER0 L2C.REG2_EV_COUNTER0
-#define L2CREG2_INT_MASK L2C.REG2_INT_MASK
-#define L2CREG2_INT_MASK_STATUS L2C.REG2_INT_MASK_STATUS
-#define L2CREG2_INT_RAW_STATUS L2C.REG2_INT_RAW_STATUS
-#define L2CREG2_INT_CLEAR L2C.REG2_INT_CLEAR
-#define L2CREG7_CACHE_SYNC L2C.REG7_CACHE_SYNC
-#define L2CREG7_INV_PA L2C.REG7_INV_PA
-#define L2CREG7_INV_WAY L2C.REG7_INV_WAY
-#define L2CREG7_CLEAN_PA L2C.REG7_CLEAN_PA
-#define L2CREG7_CLEAN_INDEX L2C.REG7_CLEAN_INDEX
-#define L2CREG7_CLEAN_WAY L2C.REG7_CLEAN_WAY
-#define L2CREG7_CLEAN_INV_PA L2C.REG7_CLEAN_INV_PA
-#define L2CREG7_CLEAN_INV_INDEX L2C.REG7_CLEAN_INV_INDEX
-#define L2CREG7_CLEAN_INV_WAY L2C.REG7_CLEAN_INV_WAY
-#define L2CREG9_D_LOCKDOWN0 L2C.REG9_D_LOCKDOWN0
-#define L2CREG9_I_LOCKDOWN0 L2C.REG9_I_LOCKDOWN0
-#define L2CREG9_D_LOCKDOWN1 L2C.REG9_D_LOCKDOWN1
-#define L2CREG9_I_LOCKDOWN1 L2C.REG9_I_LOCKDOWN1
-#define L2CREG9_D_LOCKDOWN2 L2C.REG9_D_LOCKDOWN2
-#define L2CREG9_I_LOCKDOWN2 L2C.REG9_I_LOCKDOWN2
-#define L2CREG9_D_LOCKDOWN3 L2C.REG9_D_LOCKDOWN3
-#define L2CREG9_I_LOCKDOWN3 L2C.REG9_I_LOCKDOWN3
-#define L2CREG9_D_LOCKDOWN4 L2C.REG9_D_LOCKDOWN4
-#define L2CREG9_I_LOCKDOWN4 L2C.REG9_I_LOCKDOWN4
-#define L2CREG9_D_LOCKDOWN5 L2C.REG9_D_LOCKDOWN5
-#define L2CREG9_I_LOCKDOWN5 L2C.REG9_I_LOCKDOWN5
-#define L2CREG9_D_LOCKDOWN6 L2C.REG9_D_LOCKDOWN6
-#define L2CREG9_I_LOCKDOWN6 L2C.REG9_I_LOCKDOWN6
-#define L2CREG9_D_LOCKDOWN7 L2C.REG9_D_LOCKDOWN7
-#define L2CREG9_I_LOCKDOWN7 L2C.REG9_I_LOCKDOWN7
-#define L2CREG9_LOCK_LINE_EN L2C.REG9_LOCK_LINE_EN
-#define L2CREG9_UNLOCK_WAY L2C.REG9_UNLOCK_WAY
-#define L2CREG12_ADDR_FILTERING_START L2C.REG12_ADDR_FILTERING_START
-#define L2CREG12_ADDR_FILTERING_END L2C.REG12_ADDR_FILTERING_END
-#define L2CREG15_DEBUG_CTRL L2C.REG15_DEBUG_CTRL
-#define L2CREG15_PREFETCH_CTRL L2C.REG15_PREFETCH_CTRL
-#define L2CREG15_POWER_CTRL L2C.REG15_POWER_CTRL
+/* Channel array defines of L2C (2)*/
+#ifdef  DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS
+volatile struct st_l2c_from_reg9_d_lockdown0*  L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */
+/* End of channel array defines of L2C (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lin_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,25 +18,101 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : lin_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef LIN_IODEFINE_H
 #define LIN_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_lin
-{                                                          /* LIN              */
+#define LIN0    (*(struct st_lin     *)0xFCFE9000uL) /* LIN0 */
+#define LIN1    (*(struct st_lin     *)0xFCFE9800uL) /* LIN1 */
+
+
+/* Start of channel array defines of LIN */
+
+/* Channel array defines of LIN */
+/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
+#define LIN_COUNT  (2)
+#define LIN_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &LIN0, &LIN1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of LIN */
+
+
+#define LIN0RLN30LWBR (LIN0.RLN3nLWBR)
+#define LIN0RLN30LBRP0 (LIN0.RLN3nLBRP0)
+#define LIN0RLN30LBRP1 (LIN0.RLN3nLBRP1)
+#define LIN0RLN30LSTC (LIN0.RLN3nLSTC)
+#define LIN0RLN30LMD (LIN0.RLN3nLMD)
+#define LIN0RLN30LBFC (LIN0.RLN3nLBFC)
+#define LIN0RLN30LSC (LIN0.RLN3nLSC)
+#define LIN0RLN30LWUP (LIN0.RLN3nLWUP)
+#define LIN0RLN30LIE (LIN0.RLN3nLIE)
+#define LIN0RLN30LEDE (LIN0.RLN3nLEDE)
+#define LIN0RLN30LCUC (LIN0.RLN3nLCUC)
+#define LIN0RLN30LTRC (LIN0.RLN3nLTRC)
+#define LIN0RLN30LMST (LIN0.RLN3nLMST)
+#define LIN0RLN30LST (LIN0.RLN3nLST)
+#define LIN0RLN30LEST (LIN0.RLN3nLEST)
+#define LIN0RLN30LDFC (LIN0.RLN3nLDFC)
+#define LIN0RLN30LIDB (LIN0.RLN3nLIDB)
+#define LIN0RLN30LCBR (LIN0.RLN3nLCBR)
+#define LIN0RLN30LDBR1 (LIN0.RLN3nLDBR1)
+#define LIN0RLN30LDBR2 (LIN0.RLN3nLDBR2)
+#define LIN0RLN30LDBR3 (LIN0.RLN3nLDBR3)
+#define LIN0RLN30LDBR4 (LIN0.RLN3nLDBR4)
+#define LIN0RLN30LDBR5 (LIN0.RLN3nLDBR5)
+#define LIN0RLN30LDBR6 (LIN0.RLN3nLDBR6)
+#define LIN0RLN30LDBR7 (LIN0.RLN3nLDBR7)
+#define LIN0RLN30LDBR8 (LIN0.RLN3nLDBR8)
+#define LIN1RLN31LWBR (LIN1.RLN3nLWBR)
+#define LIN1RLN31LBRP0 (LIN1.RLN3nLBRP0)
+#define LIN1RLN31LBRP1 (LIN1.RLN3nLBRP1)
+#define LIN1RLN31LSTC (LIN1.RLN3nLSTC)
+#define LIN1RLN31LMD (LIN1.RLN3nLMD)
+#define LIN1RLN31LBFC (LIN1.RLN3nLBFC)
+#define LIN1RLN31LSC (LIN1.RLN3nLSC)
+#define LIN1RLN31LWUP (LIN1.RLN3nLWUP)
+#define LIN1RLN31LIE (LIN1.RLN3nLIE)
+#define LIN1RLN31LEDE (LIN1.RLN3nLEDE)
+#define LIN1RLN31LCUC (LIN1.RLN3nLCUC)
+#define LIN1RLN31LTRC (LIN1.RLN3nLTRC)
+#define LIN1RLN31LMST (LIN1.RLN3nLMST)
+#define LIN1RLN31LST (LIN1.RLN3nLST)
+#define LIN1RLN31LEST (LIN1.RLN3nLEST)
+#define LIN1RLN31LDFC (LIN1.RLN3nLDFC)
+#define LIN1RLN31LIDB (LIN1.RLN3nLIDB)
+#define LIN1RLN31LCBR (LIN1.RLN3nLCBR)
+#define LIN1RLN31LDBR1 (LIN1.RLN3nLDBR1)
+#define LIN1RLN31LDBR2 (LIN1.RLN3nLDBR2)
+#define LIN1RLN31LDBR3 (LIN1.RLN3nLDBR3)
+#define LIN1RLN31LDBR4 (LIN1.RLN3nLDBR4)
+#define LIN1RLN31LDBR5 (LIN1.RLN3nLDBR5)
+#define LIN1RLN31LDBR6 (LIN1.RLN3nLDBR6)
+#define LIN1RLN31LDBR7 (LIN1.RLN3nLDBR7)
+#define LIN1RLN31LDBR8 (LIN1.RLN3nLDBR8)
+
+#define LIN_LDBn_COUNT (8)
+
+
+typedef struct st_lin
+{
+                                                           /* LIN              */
     volatile uint8_t   dummy1[1];                              /*                  */
     volatile uint8_t   RLN3nLWBR;                              /*  RLN3nLWBR       */
-    union iodefine_reg16_8_t  RLN3nLBRP01;                     /*  RLN3nLBRP01 */
-    
+    volatile uint8_t   RLN3nLBRP0;                             /*  RLN3nLBRP0      */
+    volatile uint8_t   RLN3nLBRP1;                             /*  RLN3nLBRP1      */
     volatile uint8_t   RLN3nLSTC;                              /*  RLN3nLSTC       */
     volatile uint8_t   dummy2[3];                              /*                  */
     volatile uint8_t   RLN3nLMD;                               /*  RLN3nLMD        */
@@ -54,8 +130,9 @@
     volatile uint8_t   RLN3nLDFC;                              /*  RLN3nLDFC       */
     volatile uint8_t   RLN3nLIDB;                              /*  RLN3nLIDB       */
     volatile uint8_t   RLN3nLCBR;                              /*  RLN3nLCBR       */
-    volatile uint8_t   RLN3nLUDB0;                             /*  RLN3nLUDB0      */
-#define LIN_LDBn_COUNT 8
+    volatile uint8_t   dummy4[1];                              /*                  */
+
+/* #define LIN_LDBn_COUNT (8) */
     volatile uint8_t   RLN3nLDBR1;                             /*  RLN3nLDBR1      */
     volatile uint8_t   RLN3nLDBR2;                             /*  RLN3nLDBR2      */
     volatile uint8_t   RLN3nLDBR3;                             /*  RLN3nLDBR3      */
@@ -64,111 +141,21 @@
     volatile uint8_t   RLN3nLDBR6;                             /*  RLN3nLDBR6      */
     volatile uint8_t   RLN3nLDBR7;                             /*  RLN3nLDBR7      */
     volatile uint8_t   RLN3nLDBR8;                             /*  RLN3nLDBR8      */
-    volatile uint8_t   RLN3nLUOER;                             /*  RLN3nLUOER      */
-    volatile uint8_t   RLN3nLUOR1;                             /*  RLN3nLUOR1      */
-    volatile uint8_t   dummy4[2];                              /*                  */
-    union iodefine_reg16_8_t  RLN3nLUTDR;                      /*  RLN3nLUTDR  */
-    union iodefine_reg16_8_t  RLN3nLURDR;                      /*  RLN3nLURDR  */
-    union iodefine_reg16_8_t  RLN3nLUWTDR;                     /*  RLN3nLUWTDR */
-    
-};
-
-
-#define LIN0    (*(struct st_lin     *)0xFCFE9000uL) /* LIN0 */
-#define LIN1    (*(struct st_lin     *)0xFCFE9800uL) /* LIN1 */
-
-
-/* Start of channnel array defines of LIN */
-
-/* Channnel array defines of LIN */
-/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
-#define LIN_COUNT  2
-#define LIN_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &LIN0, &LIN1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of LIN */
+} r_io_lin_t;
 
 
-#define LIN0RLN30LWBR LIN0.RLN3nLWBR
-#define LIN0RLN30LBRP01 LIN0.RLN3nLBRP01.UINT16
-#define LIN0RLN30LBRP0 LIN0.RLN3nLBRP01.UINT8[L]
-#define LIN0RLN30LBRP1 LIN0.RLN3nLBRP01.UINT8[H]
-#define LIN0RLN30LSTC LIN0.RLN3nLSTC
-#define LIN0RLN30LMD LIN0.RLN3nLMD
-#define LIN0RLN30LBFC LIN0.RLN3nLBFC
-#define LIN0RLN30LSC LIN0.RLN3nLSC
-#define LIN0RLN30LWUP LIN0.RLN3nLWUP
-#define LIN0RLN30LIE LIN0.RLN3nLIE
-#define LIN0RLN30LEDE LIN0.RLN3nLEDE
-#define LIN0RLN30LCUC LIN0.RLN3nLCUC
-#define LIN0RLN30LTRC LIN0.RLN3nLTRC
-#define LIN0RLN30LMST LIN0.RLN3nLMST
-#define LIN0RLN30LST LIN0.RLN3nLST
-#define LIN0RLN30LEST LIN0.RLN3nLEST
-#define LIN0RLN30LDFC LIN0.RLN3nLDFC
-#define LIN0RLN30LIDB LIN0.RLN3nLIDB
-#define LIN0RLN30LCBR LIN0.RLN3nLCBR
-#define LIN0RLN30LUDB0 LIN0.RLN3nLUDB0
-#define LIN0RLN30LDBR1 LIN0.RLN3nLDBR1
-#define LIN0RLN30LDBR2 LIN0.RLN3nLDBR2
-#define LIN0RLN30LDBR3 LIN0.RLN3nLDBR3
-#define LIN0RLN30LDBR4 LIN0.RLN3nLDBR4
-#define LIN0RLN30LDBR5 LIN0.RLN3nLDBR5
-#define LIN0RLN30LDBR6 LIN0.RLN3nLDBR6
-#define LIN0RLN30LDBR7 LIN0.RLN3nLDBR7
-#define LIN0RLN30LDBR8 LIN0.RLN3nLDBR8
-#define LIN0RLN30LUOER LIN0.RLN3nLUOER
-#define LIN0RLN30LUOR1 LIN0.RLN3nLUOR1
-#define LIN0RLN30LUTDR LIN0.RLN3nLUTDR.UINT16
-#define LIN0RLN30LUTDRL LIN0.RLN3nLUTDR.UINT8[L]
-#define LIN0RLN30LUTDRH LIN0.RLN3nLUTDR.UINT8[H]
-#define LIN0RLN30LURDR LIN0.RLN3nLURDR.UINT16
-#define LIN0RLN30LURDRL LIN0.RLN3nLURDR.UINT8[L]
-#define LIN0RLN30LURDRH LIN0.RLN3nLURDR.UINT8[H]
-#define LIN0RLN30LUWTDR LIN0.RLN3nLUWTDR.UINT16
-#define LIN0RLN30LUWTDRL LIN0.RLN3nLUWTDR.UINT8[L]
-#define LIN0RLN30LUWTDRH LIN0.RLN3nLUWTDR.UINT8[H]
-#define LIN1RLN31LWBR LIN1.RLN3nLWBR
-#define LIN1RLN31LBRP01 LIN1.RLN3nLBRP01.UINT16
-#define LIN1RLN31LBRP0 LIN1.RLN3nLBRP01.UINT8[L]
-#define LIN1RLN31LBRP1 LIN1.RLN3nLBRP01.UINT8[H]
-#define LIN1RLN31LSTC LIN1.RLN3nLSTC
-#define LIN1RLN31LMD LIN1.RLN3nLMD
-#define LIN1RLN31LBFC LIN1.RLN3nLBFC
-#define LIN1RLN31LSC LIN1.RLN3nLSC
-#define LIN1RLN31LWUP LIN1.RLN3nLWUP
-#define LIN1RLN31LIE LIN1.RLN3nLIE
-#define LIN1RLN31LEDE LIN1.RLN3nLEDE
-#define LIN1RLN31LCUC LIN1.RLN3nLCUC
-#define LIN1RLN31LTRC LIN1.RLN3nLTRC
-#define LIN1RLN31LMST LIN1.RLN3nLMST
-#define LIN1RLN31LST LIN1.RLN3nLST
-#define LIN1RLN31LEST LIN1.RLN3nLEST
-#define LIN1RLN31LDFC LIN1.RLN3nLDFC
-#define LIN1RLN31LIDB LIN1.RLN3nLIDB
-#define LIN1RLN31LCBR LIN1.RLN3nLCBR
-#define LIN1RLN31LUDB0 LIN1.RLN3nLUDB0
-#define LIN1RLN31LDBR1 LIN1.RLN3nLDBR1
-#define LIN1RLN31LDBR2 LIN1.RLN3nLDBR2
-#define LIN1RLN31LDBR3 LIN1.RLN3nLDBR3
-#define LIN1RLN31LDBR4 LIN1.RLN3nLDBR4
-#define LIN1RLN31LDBR5 LIN1.RLN3nLDBR5
-#define LIN1RLN31LDBR6 LIN1.RLN3nLDBR6
-#define LIN1RLN31LDBR7 LIN1.RLN3nLDBR7
-#define LIN1RLN31LDBR8 LIN1.RLN3nLDBR8
-#define LIN1RLN31LUOER LIN1.RLN3nLUOER
-#define LIN1RLN31LUOR1 LIN1.RLN3nLUOR1
-#define LIN1RLN31LUTDR LIN1.RLN3nLUTDR.UINT16
-#define LIN1RLN31LUTDRL LIN1.RLN3nLUTDR.UINT8[L]
-#define LIN1RLN31LUTDRH LIN1.RLN3nLUTDR.UINT8[H]
-#define LIN1RLN31LURDR LIN1.RLN3nLURDR.UINT16
-#define LIN1RLN31LURDRL LIN1.RLN3nLURDR.UINT8[L]
-#define LIN1RLN31LURDRH LIN1.RLN3nLURDR.UINT8[H]
-#define LIN1RLN31LUWTDR LIN1.RLN3nLUWTDR.UINT16
-#define LIN1RLN31LUWTDRL LIN1.RLN3nLUWTDR.UINT8[L]
-#define LIN1RLN31LUWTDRH LIN1.RLN3nLUWTDR.UINT8[H]
+/* Channel array defines of LIN (2)*/
+#ifdef  DECLARE_LIN_CHANNELS
+volatile struct st_lin*  LIN[ LIN_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    LIN_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_LIN_CHANNELS */
+/* End of channel array defines of LIN (2)*/
+
+
 /* <-SEC M1.10.1 */
 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/lvds_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,34 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : lvds_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.01a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef LVDS_IODEFINE_H
 #define LVDS_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_lvds
-{                                                          /* LVDS             */
+#define LVDS    (*(struct st_lvds    *)0xFCFF7A30uL) /* LVDS */
+
+
+#define LVDSLVDS_UPDATE (LVDS.LVDS_UPDATE)
+#define LVDSLVDSFCL (LVDS.LVDSFCL)
+#define LVDSLCLKSELR (LVDS.LCLKSELR)
+#define LVDSLPLLSETR (LVDS.LPLLSETR)
+#define LVDSLPHYACC (LVDS.LPHYACC)
+
+
+typedef struct st_lvds
+{
+                                                           /* LVDS             */
     volatile uint32_t  LVDS_UPDATE;                            /*  LVDS_UPDATE     */
     volatile uint32_t  LVDSFCL;                                /*  LVDSFCL         */
     volatile uint8_t   dummy608[24];                           /*                  */
@@ -39,16 +53,11 @@
     volatile uint32_t  LPLLSETR;                               /*  LPLLSETR        */
     volatile uint8_t   dummy609[4];                            /*                  */
     volatile uint32_t  LPHYACC;                                /*  LPHYACC         */
-};
-
-
-#define LVDS    (*(struct st_lvds    *)0xFCFF7A30uL) /* LVDS */
+} r_io_lvds_t;
 
 
-#define LVDSLVDS_UPDATE LVDS.LVDS_UPDATE
-#define LVDSLVDSFCL LVDS.LVDSFCL
-#define LVDSLCLKSELR LVDS.LCLKSELR
-#define LVDSLPLLSETR LVDS.LPLLSETR
-#define LVDSLPHYACC LVDS.LPHYACC
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mlb_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,273 +18,29 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : mlb_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef MLB_IODEFINE_H
 #define MLB_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
 /* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_mlb
-{                                                          /* MLB              */
-    volatile uint32_t  DCCR;                                   /*  DCCR            */
-    volatile uint32_t  SSCR;                                   /*  SSCR            */
-    volatile uint32_t  SDCR;                                   /*  SDCR            */
-    volatile uint32_t  SMCR;                                   /*  SMCR            */
-    volatile uint8_t   dummy156[12];                           /*                  */
-    volatile uint32_t  VCCR;                                   /*  VCCR            */
-    volatile uint32_t  SBCR;                                   /*  SBCR            */
-    volatile uint32_t  ABCR;                                   /*  ABCR            */
-    volatile uint32_t  CBCR;                                   /*  CBCR            */
-    volatile uint32_t  IBCR;                                   /*  IBCR            */
-    volatile uint32_t  CICR;                                   /*  CICR            */
-    volatile uint8_t   dummy157[12];                           /*                  */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR0;                                  /*  CECR0           */
-    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
-    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
-    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR1;                                  /*  CECR1           */
-    volatile uint32_t  CSCR1;                                  /*  CSCR1           */
-    volatile uint32_t  CCBCR1;                                 /*  CCBCR1          */
-    volatile uint32_t  CNBCR1;                                 /*  CNBCR1          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR2;                                  /*  CECR2           */
-    volatile uint32_t  CSCR2;                                  /*  CSCR2           */
-    volatile uint32_t  CCBCR2;                                 /*  CCBCR2          */
-    volatile uint32_t  CNBCR2;                                 /*  CNBCR2          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR3;                                  /*  CECR3           */
-    volatile uint32_t  CSCR3;                                  /*  CSCR3           */
-    volatile uint32_t  CCBCR3;                                 /*  CCBCR3          */
-    volatile uint32_t  CNBCR3;                                 /*  CNBCR3          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR4;                                  /*  CECR4           */
-    volatile uint32_t  CSCR4;                                  /*  CSCR4           */
-    volatile uint32_t  CCBCR4;                                 /*  CCBCR4          */
-    volatile uint32_t  CNBCR4;                                 /*  CNBCR4          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR5;                                  /*  CECR5           */
-    volatile uint32_t  CSCR5;                                  /*  CSCR5           */
-    volatile uint32_t  CCBCR5;                                 /*  CCBCR5          */
-    volatile uint32_t  CNBCR5;                                 /*  CNBCR5          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR6;                                  /*  CECR6           */
-    volatile uint32_t  CSCR6;                                  /*  CSCR6           */
-    volatile uint32_t  CCBCR6;                                 /*  CCBCR6          */
-    volatile uint32_t  CNBCR6;                                 /*  CNBCR6          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR7;                                  /*  CECR7           */
-    volatile uint32_t  CSCR7;                                  /*  CSCR7           */
-    volatile uint32_t  CCBCR7;                                 /*  CCBCR7          */
-    volatile uint32_t  CNBCR7;                                 /*  CNBCR7          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR8;                                  /*  CECR8           */
-    volatile uint32_t  CSCR8;                                  /*  CSCR8           */
-    volatile uint32_t  CCBCR8;                                 /*  CCBCR8          */
-    volatile uint32_t  CNBCR8;                                 /*  CNBCR8          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR9;                                  /*  CECR9           */
-    volatile uint32_t  CSCR9;                                  /*  CSCR9           */
-    volatile uint32_t  CCBCR9;                                 /*  CCBCR9          */
-    volatile uint32_t  CNBCR9;                                 /*  CNBCR9          */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR10;                                 /*  CECR10          */
-    volatile uint32_t  CSCR10;                                 /*  CSCR10          */
-    volatile uint32_t  CCBCR10;                                /*  CCBCR10         */
-    volatile uint32_t  CNBCR10;                                /*  CNBCR10         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR11;                                 /*  CECR11          */
-    volatile uint32_t  CSCR11;                                 /*  CSCR11          */
-    volatile uint32_t  CCBCR11;                                /*  CCBCR11         */
-    volatile uint32_t  CNBCR11;                                /*  CNBCR11         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR12;                                 /*  CECR12          */
-    volatile uint32_t  CSCR12;                                 /*  CSCR12          */
-    volatile uint32_t  CCBCR12;                                /*  CCBCR12         */
-    volatile uint32_t  CNBCR12;                                /*  CNBCR12         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR13;                                 /*  CECR13          */
-    volatile uint32_t  CSCR13;                                 /*  CSCR13          */
-    volatile uint32_t  CCBCR13;                                /*  CCBCR13         */
-    volatile uint32_t  CNBCR13;                                /*  CNBCR13         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR14;                                 /*  CECR14          */
-    volatile uint32_t  CSCR14;                                 /*  CSCR14          */
-    volatile uint32_t  CCBCR14;                                /*  CCBCR14         */
-    volatile uint32_t  CNBCR14;                                /*  CNBCR14         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR15;                                 /*  CECR15          */
-    volatile uint32_t  CSCR15;                                 /*  CSCR15          */
-    volatile uint32_t  CCBCR15;                                /*  CCBCR15         */
-    volatile uint32_t  CNBCR15;                                /*  CNBCR15         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR16;                                 /*  CECR16          */
-    volatile uint32_t  CSCR16;                                 /*  CSCR16          */
-    volatile uint32_t  CCBCR16;                                /*  CCBCR16         */
-    volatile uint32_t  CNBCR16;                                /*  CNBCR16         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR17;                                 /*  CECR17          */
-    volatile uint32_t  CSCR17;                                 /*  CSCR17          */
-    volatile uint32_t  CCBCR17;                                /*  CCBCR17         */
-    volatile uint32_t  CNBCR17;                                /*  CNBCR17         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR18;                                 /*  CECR18          */
-    volatile uint32_t  CSCR18;                                 /*  CSCR18          */
-    volatile uint32_t  CCBCR18;                                /*  CCBCR18         */
-    volatile uint32_t  CNBCR18;                                /*  CNBCR18         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR19;                                 /*  CECR19          */
-    volatile uint32_t  CSCR19;                                 /*  CSCR19          */
-    volatile uint32_t  CCBCR19;                                /*  CCBCR19         */
-    volatile uint32_t  CNBCR19;                                /*  CNBCR19         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR20;                                 /*  CECR20          */
-    volatile uint32_t  CSCR20;                                 /*  CSCR20          */
-    volatile uint32_t  CCBCR20;                                /*  CCBCR20         */
-    volatile uint32_t  CNBCR20;                                /*  CNBCR20         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR21;                                 /*  CECR21          */
-    volatile uint32_t  CSCR21;                                 /*  CSCR21          */
-    volatile uint32_t  CCBCR21;                                /*  CCBCR21         */
-    volatile uint32_t  CNBCR21;                                /*  CNBCR21         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR22;                                 /*  CECR22          */
-    volatile uint32_t  CSCR22;                                 /*  CSCR22          */
-    volatile uint32_t  CCBCR22;                                /*  CCBCR22         */
-    volatile uint32_t  CNBCR22;                                /*  CNBCR22         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR23;                                 /*  CECR23          */
-    volatile uint32_t  CSCR23;                                 /*  CSCR23          */
-    volatile uint32_t  CCBCR23;                                /*  CCBCR23         */
-    volatile uint32_t  CNBCR23;                                /*  CNBCR23         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR24;                                 /*  CECR24          */
-    volatile uint32_t  CSCR24;                                 /*  CSCR24          */
-    volatile uint32_t  CCBCR24;                                /*  CCBCR24         */
-    volatile uint32_t  CNBCR24;                                /*  CNBCR24         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR25;                                 /*  CECR25          */
-    volatile uint32_t  CSCR25;                                 /*  CSCR25          */
-    volatile uint32_t  CCBCR25;                                /*  CCBCR25         */
-    volatile uint32_t  CNBCR25;                                /*  CNBCR25         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR26;                                 /*  CECR26          */
-    volatile uint32_t  CSCR26;                                 /*  CSCR26          */
-    volatile uint32_t  CCBCR26;                                /*  CCBCR26         */
-    volatile uint32_t  CNBCR26;                                /*  CNBCR26         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR27;                                 /*  CECR27          */
-    volatile uint32_t  CSCR27;                                 /*  CSCR27          */
-    volatile uint32_t  CCBCR27;                                /*  CCBCR27         */
-    volatile uint32_t  CNBCR27;                                /*  CNBCR27         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR28;                                 /*  CECR28          */
-    volatile uint32_t  CSCR28;                                 /*  CSCR28          */
-    volatile uint32_t  CCBCR28;                                /*  CCBCR28         */
-    volatile uint32_t  CNBCR28;                                /*  CNBCR28         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR29;                                 /*  CECR29          */
-    volatile uint32_t  CSCR29;                                 /*  CSCR29          */
-    volatile uint32_t  CCBCR29;                                /*  CCBCR29         */
-    volatile uint32_t  CNBCR29;                                /*  CNBCR29         */
-/* end of struct st_mlb_from_cecr0 */
-/* start of struct st_mlb_from_cecr0 */
-    volatile uint32_t  CECR30;                                 /*  CECR30          */
-    volatile uint32_t  CSCR30;                                 /*  CSCR30          */
-    volatile uint32_t  CCBCR30;                                /*  CCBCR30         */
-    volatile uint32_t  CNBCR30;                                /*  CNBCR30         */
-/* end of struct st_mlb_from_cecr0 */
-    volatile uint8_t   dummy158[80];                           /*                  */
-#define MLB_LCBCR0_COUNT 31
-    volatile uint32_t  LCBCR0;                                 /*  LCBCR0          */
-    volatile uint32_t  LCBCR1;                                 /*  LCBCR1          */
-    volatile uint32_t  LCBCR2;                                 /*  LCBCR2          */
-    volatile uint32_t  LCBCR3;                                 /*  LCBCR3          */
-    volatile uint32_t  LCBCR4;                                 /*  LCBCR4          */
-    volatile uint32_t  LCBCR5;                                 /*  LCBCR5          */
-    volatile uint32_t  LCBCR6;                                 /*  LCBCR6          */
-    volatile uint32_t  LCBCR7;                                 /*  LCBCR7          */
-    volatile uint32_t  LCBCR8;                                 /*  LCBCR8          */
-    volatile uint32_t  LCBCR9;                                 /*  LCBCR9          */
-    volatile uint32_t  LCBCR10;                                /*  LCBCR10         */
-    volatile uint32_t  LCBCR11;                                /*  LCBCR11         */
-    volatile uint32_t  LCBCR12;                                /*  LCBCR12         */
-    volatile uint32_t  LCBCR13;                                /*  LCBCR13         */
-    volatile uint32_t  LCBCR14;                                /*  LCBCR14         */
-    volatile uint32_t  LCBCR15;                                /*  LCBCR15         */
-    volatile uint32_t  LCBCR16;                                /*  LCBCR16         */
-    volatile uint32_t  LCBCR17;                                /*  LCBCR17         */
-    volatile uint32_t  LCBCR18;                                /*  LCBCR18         */
-    volatile uint32_t  LCBCR19;                                /*  LCBCR19         */
-    volatile uint32_t  LCBCR20;                                /*  LCBCR20         */
-    volatile uint32_t  LCBCR21;                                /*  LCBCR21         */
-    volatile uint32_t  LCBCR22;                                /*  LCBCR22         */
-    volatile uint32_t  LCBCR23;                                /*  LCBCR23         */
-    volatile uint32_t  LCBCR24;                                /*  LCBCR24         */
-    volatile uint32_t  LCBCR25;                                /*  LCBCR25         */
-    volatile uint32_t  LCBCR26;                                /*  LCBCR26         */
-    volatile uint32_t  LCBCR27;                                /*  LCBCR27         */
-    volatile uint32_t  LCBCR28;                                /*  LCBCR28         */
-    volatile uint32_t  LCBCR29;                                /*  LCBCR29         */
-    volatile uint32_t  LCBCR30;                                /*  LCBCR30         */
-};
-
-
-struct st_mlb_from_cecr0
-{
-    volatile uint32_t  CECR0;                                  /*  CECR0           */
-    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
-    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
-    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
-};
-
-
 #define MLB     (*(struct st_mlb     *)0xE8034000uL) /* MLB */
 
 
-/* Start of channnel array defines of MLB */
+/* Start of channel array defines of MLB */
 
-/* Channnel array defines of MLB_FROM_CECR0_ARRAY */
+/* Channel array defines of MLB_FROM_CECR0_ARRAY */
 /*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */
-#define MLB_FROM_CECR0_ARRAY_COUNT  31
+#define MLB_FROM_CECR0_ARRAY_COUNT  (31)
 #define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \
@@ -324,175 +80,500 @@
 #define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */
 #define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */
 
-/* End of channnel array defines of MLB */
+/* End of channel array defines of MLB */
+
+
+#define MLBDCCR (MLB.DCCR)
+#define MLBSSCR (MLB.SSCR)
+#define MLBSDCR (MLB.SDCR)
+#define MLBSMCR (MLB.SMCR)
+#define MLBVCCR (MLB.VCCR)
+#define MLBSBCR (MLB.SBCR)
+#define MLBABCR (MLB.ABCR)
+#define MLBCBCR (MLB.CBCR)
+#define MLBIBCR (MLB.IBCR)
+#define MLBCICR (MLB.CICR)
+#define MLBCECR0 (MLB.CECR0)
+#define MLBCSCR0 (MLB.CSCR0)
+#define MLBCCBCR0 (MLB.CCBCR0)
+#define MLBCNBCR0 (MLB.CNBCR0)
+#define MLBCECR1 (MLB.CECR1)
+#define MLBCSCR1 (MLB.CSCR1)
+#define MLBCCBCR1 (MLB.CCBCR1)
+#define MLBCNBCR1 (MLB.CNBCR1)
+#define MLBCECR2 (MLB.CECR2)
+#define MLBCSCR2 (MLB.CSCR2)
+#define MLBCCBCR2 (MLB.CCBCR2)
+#define MLBCNBCR2 (MLB.CNBCR2)
+#define MLBCECR3 (MLB.CECR3)
+#define MLBCSCR3 (MLB.CSCR3)
+#define MLBCCBCR3 (MLB.CCBCR3)
+#define MLBCNBCR3 (MLB.CNBCR3)
+#define MLBCECR4 (MLB.CECR4)
+#define MLBCSCR4 (MLB.CSCR4)
+#define MLBCCBCR4 (MLB.CCBCR4)
+#define MLBCNBCR4 (MLB.CNBCR4)
+#define MLBCECR5 (MLB.CECR5)
+#define MLBCSCR5 (MLB.CSCR5)
+#define MLBCCBCR5 (MLB.CCBCR5)
+#define MLBCNBCR5 (MLB.CNBCR5)
+#define MLBCECR6 (MLB.CECR6)
+#define MLBCSCR6 (MLB.CSCR6)
+#define MLBCCBCR6 (MLB.CCBCR6)
+#define MLBCNBCR6 (MLB.CNBCR6)
+#define MLBCECR7 (MLB.CECR7)
+#define MLBCSCR7 (MLB.CSCR7)
+#define MLBCCBCR7 (MLB.CCBCR7)
+#define MLBCNBCR7 (MLB.CNBCR7)
+#define MLBCECR8 (MLB.CECR8)
+#define MLBCSCR8 (MLB.CSCR8)
+#define MLBCCBCR8 (MLB.CCBCR8)
+#define MLBCNBCR8 (MLB.CNBCR8)
+#define MLBCECR9 (MLB.CECR9)
+#define MLBCSCR9 (MLB.CSCR9)
+#define MLBCCBCR9 (MLB.CCBCR9)
+#define MLBCNBCR9 (MLB.CNBCR9)
+#define MLBCECR10 (MLB.CECR10)
+#define MLBCSCR10 (MLB.CSCR10)
+#define MLBCCBCR10 (MLB.CCBCR10)
+#define MLBCNBCR10 (MLB.CNBCR10)
+#define MLBCECR11 (MLB.CECR11)
+#define MLBCSCR11 (MLB.CSCR11)
+#define MLBCCBCR11 (MLB.CCBCR11)
+#define MLBCNBCR11 (MLB.CNBCR11)
+#define MLBCECR12 (MLB.CECR12)
+#define MLBCSCR12 (MLB.CSCR12)
+#define MLBCCBCR12 (MLB.CCBCR12)
+#define MLBCNBCR12 (MLB.CNBCR12)
+#define MLBCECR13 (MLB.CECR13)
+#define MLBCSCR13 (MLB.CSCR13)
+#define MLBCCBCR13 (MLB.CCBCR13)
+#define MLBCNBCR13 (MLB.CNBCR13)
+#define MLBCECR14 (MLB.CECR14)
+#define MLBCSCR14 (MLB.CSCR14)
+#define MLBCCBCR14 (MLB.CCBCR14)
+#define MLBCNBCR14 (MLB.CNBCR14)
+#define MLBCECR15 (MLB.CECR15)
+#define MLBCSCR15 (MLB.CSCR15)
+#define MLBCCBCR15 (MLB.CCBCR15)
+#define MLBCNBCR15 (MLB.CNBCR15)
+#define MLBCECR16 (MLB.CECR16)
+#define MLBCSCR16 (MLB.CSCR16)
+#define MLBCCBCR16 (MLB.CCBCR16)
+#define MLBCNBCR16 (MLB.CNBCR16)
+#define MLBCECR17 (MLB.CECR17)
+#define MLBCSCR17 (MLB.CSCR17)
+#define MLBCCBCR17 (MLB.CCBCR17)
+#define MLBCNBCR17 (MLB.CNBCR17)
+#define MLBCECR18 (MLB.CECR18)
+#define MLBCSCR18 (MLB.CSCR18)
+#define MLBCCBCR18 (MLB.CCBCR18)
+#define MLBCNBCR18 (MLB.CNBCR18)
+#define MLBCECR19 (MLB.CECR19)
+#define MLBCSCR19 (MLB.CSCR19)
+#define MLBCCBCR19 (MLB.CCBCR19)
+#define MLBCNBCR19 (MLB.CNBCR19)
+#define MLBCECR20 (MLB.CECR20)
+#define MLBCSCR20 (MLB.CSCR20)
+#define MLBCCBCR20 (MLB.CCBCR20)
+#define MLBCNBCR20 (MLB.CNBCR20)
+#define MLBCECR21 (MLB.CECR21)
+#define MLBCSCR21 (MLB.CSCR21)
+#define MLBCCBCR21 (MLB.CCBCR21)
+#define MLBCNBCR21 (MLB.CNBCR21)
+#define MLBCECR22 (MLB.CECR22)
+#define MLBCSCR22 (MLB.CSCR22)
+#define MLBCCBCR22 (MLB.CCBCR22)
+#define MLBCNBCR22 (MLB.CNBCR22)
+#define MLBCECR23 (MLB.CECR23)
+#define MLBCSCR23 (MLB.CSCR23)
+#define MLBCCBCR23 (MLB.CCBCR23)
+#define MLBCNBCR23 (MLB.CNBCR23)
+#define MLBCECR24 (MLB.CECR24)
+#define MLBCSCR24 (MLB.CSCR24)
+#define MLBCCBCR24 (MLB.CCBCR24)
+#define MLBCNBCR24 (MLB.CNBCR24)
+#define MLBCECR25 (MLB.CECR25)
+#define MLBCSCR25 (MLB.CSCR25)
+#define MLBCCBCR25 (MLB.CCBCR25)
+#define MLBCNBCR25 (MLB.CNBCR25)
+#define MLBCECR26 (MLB.CECR26)
+#define MLBCSCR26 (MLB.CSCR26)
+#define MLBCCBCR26 (MLB.CCBCR26)
+#define MLBCNBCR26 (MLB.CNBCR26)
+#define MLBCECR27 (MLB.CECR27)
+#define MLBCSCR27 (MLB.CSCR27)
+#define MLBCCBCR27 (MLB.CCBCR27)
+#define MLBCNBCR27 (MLB.CNBCR27)
+#define MLBCECR28 (MLB.CECR28)
+#define MLBCSCR28 (MLB.CSCR28)
+#define MLBCCBCR28 (MLB.CCBCR28)
+#define MLBCNBCR28 (MLB.CNBCR28)
+#define MLBCECR29 (MLB.CECR29)
+#define MLBCSCR29 (MLB.CSCR29)
+#define MLBCCBCR29 (MLB.CCBCR29)
+#define MLBCNBCR29 (MLB.CNBCR29)
+#define MLBCECR30 (MLB.CECR30)
+#define MLBCSCR30 (MLB.CSCR30)
+#define MLBCCBCR30 (MLB.CCBCR30)
+#define MLBCNBCR30 (MLB.CNBCR30)
+#define MLBLCBCR0 (MLB.LCBCR0)
+#define MLBLCBCR1 (MLB.LCBCR1)
+#define MLBLCBCR2 (MLB.LCBCR2)
+#define MLBLCBCR3 (MLB.LCBCR3)
+#define MLBLCBCR4 (MLB.LCBCR4)
+#define MLBLCBCR5 (MLB.LCBCR5)
+#define MLBLCBCR6 (MLB.LCBCR6)
+#define MLBLCBCR7 (MLB.LCBCR7)
+#define MLBLCBCR8 (MLB.LCBCR8)
+#define MLBLCBCR9 (MLB.LCBCR9)
+#define MLBLCBCR10 (MLB.LCBCR10)
+#define MLBLCBCR11 (MLB.LCBCR11)
+#define MLBLCBCR12 (MLB.LCBCR12)
+#define MLBLCBCR13 (MLB.LCBCR13)
+#define MLBLCBCR14 (MLB.LCBCR14)
+#define MLBLCBCR15 (MLB.LCBCR15)
+#define MLBLCBCR16 (MLB.LCBCR16)
+#define MLBLCBCR17 (MLB.LCBCR17)
+#define MLBLCBCR18 (MLB.LCBCR18)
+#define MLBLCBCR19 (MLB.LCBCR19)
+#define MLBLCBCR20 (MLB.LCBCR20)
+#define MLBLCBCR21 (MLB.LCBCR21)
+#define MLBLCBCR22 (MLB.LCBCR22)
+#define MLBLCBCR23 (MLB.LCBCR23)
+#define MLBLCBCR24 (MLB.LCBCR24)
+#define MLBLCBCR25 (MLB.LCBCR25)
+#define MLBLCBCR26 (MLB.LCBCR26)
+#define MLBLCBCR27 (MLB.LCBCR27)
+#define MLBLCBCR28 (MLB.LCBCR28)
+#define MLBLCBCR29 (MLB.LCBCR29)
+#define MLBLCBCR30 (MLB.LCBCR30)
+
+#define MLB_LCBCR0_COUNT (31)
 
 
-#define MLBDCCR MLB.DCCR
-#define MLBSSCR MLB.SSCR
-#define MLBSDCR MLB.SDCR
-#define MLBSMCR MLB.SMCR
-#define MLBVCCR MLB.VCCR
-#define MLBSBCR MLB.SBCR
-#define MLBABCR MLB.ABCR
-#define MLBCBCR MLB.CBCR
-#define MLBIBCR MLB.IBCR
-#define MLBCICR MLB.CICR
-#define MLBCECR0 MLB.CECR0
-#define MLBCSCR0 MLB.CSCR0
-#define MLBCCBCR0 MLB.CCBCR0
-#define MLBCNBCR0 MLB.CNBCR0
-#define MLBCECR1 MLB.CECR1
-#define MLBCSCR1 MLB.CSCR1
-#define MLBCCBCR1 MLB.CCBCR1
-#define MLBCNBCR1 MLB.CNBCR1
-#define MLBCECR2 MLB.CECR2
-#define MLBCSCR2 MLB.CSCR2
-#define MLBCCBCR2 MLB.CCBCR2
-#define MLBCNBCR2 MLB.CNBCR2
-#define MLBCECR3 MLB.CECR3
-#define MLBCSCR3 MLB.CSCR3
-#define MLBCCBCR3 MLB.CCBCR3
-#define MLBCNBCR3 MLB.CNBCR3
-#define MLBCECR4 MLB.CECR4
-#define MLBCSCR4 MLB.CSCR4
-#define MLBCCBCR4 MLB.CCBCR4
-#define MLBCNBCR4 MLB.CNBCR4
-#define MLBCECR5 MLB.CECR5
-#define MLBCSCR5 MLB.CSCR5
-#define MLBCCBCR5 MLB.CCBCR5
-#define MLBCNBCR5 MLB.CNBCR5
-#define MLBCECR6 MLB.CECR6
-#define MLBCSCR6 MLB.CSCR6
-#define MLBCCBCR6 MLB.CCBCR6
-#define MLBCNBCR6 MLB.CNBCR6
-#define MLBCECR7 MLB.CECR7
-#define MLBCSCR7 MLB.CSCR7
-#define MLBCCBCR7 MLB.CCBCR7
-#define MLBCNBCR7 MLB.CNBCR7
-#define MLBCECR8 MLB.CECR8
-#define MLBCSCR8 MLB.CSCR8
-#define MLBCCBCR8 MLB.CCBCR8
-#define MLBCNBCR8 MLB.CNBCR8
-#define MLBCECR9 MLB.CECR9
-#define MLBCSCR9 MLB.CSCR9
-#define MLBCCBCR9 MLB.CCBCR9
-#define MLBCNBCR9 MLB.CNBCR9
-#define MLBCECR10 MLB.CECR10
-#define MLBCSCR10 MLB.CSCR10
-#define MLBCCBCR10 MLB.CCBCR10
-#define MLBCNBCR10 MLB.CNBCR10
-#define MLBCECR11 MLB.CECR11
-#define MLBCSCR11 MLB.CSCR11
-#define MLBCCBCR11 MLB.CCBCR11
-#define MLBCNBCR11 MLB.CNBCR11
-#define MLBCECR12 MLB.CECR12
-#define MLBCSCR12 MLB.CSCR12
-#define MLBCCBCR12 MLB.CCBCR12
-#define MLBCNBCR12 MLB.CNBCR12
-#define MLBCECR13 MLB.CECR13
-#define MLBCSCR13 MLB.CSCR13
-#define MLBCCBCR13 MLB.CCBCR13
-#define MLBCNBCR13 MLB.CNBCR13
-#define MLBCECR14 MLB.CECR14
-#define MLBCSCR14 MLB.CSCR14
-#define MLBCCBCR14 MLB.CCBCR14
-#define MLBCNBCR14 MLB.CNBCR14
-#define MLBCECR15 MLB.CECR15
-#define MLBCSCR15 MLB.CSCR15
-#define MLBCCBCR15 MLB.CCBCR15
-#define MLBCNBCR15 MLB.CNBCR15
-#define MLBCECR16 MLB.CECR16
-#define MLBCSCR16 MLB.CSCR16
-#define MLBCCBCR16 MLB.CCBCR16
-#define MLBCNBCR16 MLB.CNBCR16
-#define MLBCECR17 MLB.CECR17
-#define MLBCSCR17 MLB.CSCR17
-#define MLBCCBCR17 MLB.CCBCR17
-#define MLBCNBCR17 MLB.CNBCR17
-#define MLBCECR18 MLB.CECR18
-#define MLBCSCR18 MLB.CSCR18
-#define MLBCCBCR18 MLB.CCBCR18
-#define MLBCNBCR18 MLB.CNBCR18
-#define MLBCECR19 MLB.CECR19
-#define MLBCSCR19 MLB.CSCR19
-#define MLBCCBCR19 MLB.CCBCR19
-#define MLBCNBCR19 MLB.CNBCR19
-#define MLBCECR20 MLB.CECR20
-#define MLBCSCR20 MLB.CSCR20
-#define MLBCCBCR20 MLB.CCBCR20
-#define MLBCNBCR20 MLB.CNBCR20
-#define MLBCECR21 MLB.CECR21
-#define MLBCSCR21 MLB.CSCR21
-#define MLBCCBCR21 MLB.CCBCR21
-#define MLBCNBCR21 MLB.CNBCR21
-#define MLBCECR22 MLB.CECR22
-#define MLBCSCR22 MLB.CSCR22
-#define MLBCCBCR22 MLB.CCBCR22
-#define MLBCNBCR22 MLB.CNBCR22
-#define MLBCECR23 MLB.CECR23
-#define MLBCSCR23 MLB.CSCR23
-#define MLBCCBCR23 MLB.CCBCR23
-#define MLBCNBCR23 MLB.CNBCR23
-#define MLBCECR24 MLB.CECR24
-#define MLBCSCR24 MLB.CSCR24
-#define MLBCCBCR24 MLB.CCBCR24
-#define MLBCNBCR24 MLB.CNBCR24
-#define MLBCECR25 MLB.CECR25
-#define MLBCSCR25 MLB.CSCR25
-#define MLBCCBCR25 MLB.CCBCR25
-#define MLBCNBCR25 MLB.CNBCR25
-#define MLBCECR26 MLB.CECR26
-#define MLBCSCR26 MLB.CSCR26
-#define MLBCCBCR26 MLB.CCBCR26
-#define MLBCNBCR26 MLB.CNBCR26
-#define MLBCECR27 MLB.CECR27
-#define MLBCSCR27 MLB.CSCR27
-#define MLBCCBCR27 MLB.CCBCR27
-#define MLBCNBCR27 MLB.CNBCR27
-#define MLBCECR28 MLB.CECR28
-#define MLBCSCR28 MLB.CSCR28
-#define MLBCCBCR28 MLB.CCBCR28
-#define MLBCNBCR28 MLB.CNBCR28
-#define MLBCECR29 MLB.CECR29
-#define MLBCSCR29 MLB.CSCR29
-#define MLBCCBCR29 MLB.CCBCR29
-#define MLBCNBCR29 MLB.CNBCR29
-#define MLBCECR30 MLB.CECR30
-#define MLBCSCR30 MLB.CSCR30
-#define MLBCCBCR30 MLB.CCBCR30
-#define MLBCNBCR30 MLB.CNBCR30
-#define MLBLCBCR0 MLB.LCBCR0
-#define MLBLCBCR1 MLB.LCBCR1
-#define MLBLCBCR2 MLB.LCBCR2
-#define MLBLCBCR3 MLB.LCBCR3
-#define MLBLCBCR4 MLB.LCBCR4
-#define MLBLCBCR5 MLB.LCBCR5
-#define MLBLCBCR6 MLB.LCBCR6
-#define MLBLCBCR7 MLB.LCBCR7
-#define MLBLCBCR8 MLB.LCBCR8
-#define MLBLCBCR9 MLB.LCBCR9
-#define MLBLCBCR10 MLB.LCBCR10
-#define MLBLCBCR11 MLB.LCBCR11
-#define MLBLCBCR12 MLB.LCBCR12
-#define MLBLCBCR13 MLB.LCBCR13
-#define MLBLCBCR14 MLB.LCBCR14
-#define MLBLCBCR15 MLB.LCBCR15
-#define MLBLCBCR16 MLB.LCBCR16
-#define MLBLCBCR17 MLB.LCBCR17
-#define MLBLCBCR18 MLB.LCBCR18
-#define MLBLCBCR19 MLB.LCBCR19
-#define MLBLCBCR20 MLB.LCBCR20
-#define MLBLCBCR21 MLB.LCBCR21
-#define MLBLCBCR22 MLB.LCBCR22
-#define MLBLCBCR23 MLB.LCBCR23
-#define MLBLCBCR24 MLB.LCBCR24
-#define MLBLCBCR25 MLB.LCBCR25
-#define MLBLCBCR26 MLB.LCBCR26
-#define MLBLCBCR27 MLB.LCBCR27
-#define MLBLCBCR28 MLB.LCBCR28
-#define MLBLCBCR29 MLB.LCBCR29
-#define MLBLCBCR30 MLB.LCBCR30
+typedef struct st_mlb
+{
+                                                           /* MLB              */
+    volatile uint32_t  DCCR;                                   /*  DCCR            */
+    volatile uint32_t  SSCR;                                   /*  SSCR            */
+    volatile uint32_t  SDCR;                                   /*  SDCR            */
+    volatile uint32_t  SMCR;                                   /*  SMCR            */
+    volatile uint8_t   dummy156[12];                           /*                  */
+    volatile uint32_t  VCCR;                                   /*  VCCR            */
+    volatile uint32_t  SBCR;                                   /*  SBCR            */
+    volatile uint32_t  ABCR;                                   /*  ABCR            */
+    volatile uint32_t  CBCR;                                   /*  CBCR            */
+    volatile uint32_t  IBCR;                                   /*  IBCR            */
+    volatile uint32_t  CICR;                                   /*  CICR            */
+    volatile uint8_t   dummy157[12];                           /*                  */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR0;                                  /*  CECR0           */
+    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
+    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
+    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR1;                                  /*  CECR1           */
+    volatile uint32_t  CSCR1;                                  /*  CSCR1           */
+    volatile uint32_t  CCBCR1;                                 /*  CCBCR1          */
+    volatile uint32_t  CNBCR1;                                 /*  CNBCR1          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR2;                                  /*  CECR2           */
+    volatile uint32_t  CSCR2;                                  /*  CSCR2           */
+    volatile uint32_t  CCBCR2;                                 /*  CCBCR2          */
+    volatile uint32_t  CNBCR2;                                 /*  CNBCR2          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR3;                                  /*  CECR3           */
+    volatile uint32_t  CSCR3;                                  /*  CSCR3           */
+    volatile uint32_t  CCBCR3;                                 /*  CCBCR3          */
+    volatile uint32_t  CNBCR3;                                 /*  CNBCR3          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR4;                                  /*  CECR4           */
+    volatile uint32_t  CSCR4;                                  /*  CSCR4           */
+    volatile uint32_t  CCBCR4;                                 /*  CCBCR4          */
+    volatile uint32_t  CNBCR4;                                 /*  CNBCR4          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR5;                                  /*  CECR5           */
+    volatile uint32_t  CSCR5;                                  /*  CSCR5           */
+    volatile uint32_t  CCBCR5;                                 /*  CCBCR5          */
+    volatile uint32_t  CNBCR5;                                 /*  CNBCR5          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR6;                                  /*  CECR6           */
+    volatile uint32_t  CSCR6;                                  /*  CSCR6           */
+    volatile uint32_t  CCBCR6;                                 /*  CCBCR6          */
+    volatile uint32_t  CNBCR6;                                 /*  CNBCR6          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR7;                                  /*  CECR7           */
+    volatile uint32_t  CSCR7;                                  /*  CSCR7           */
+    volatile uint32_t  CCBCR7;                                 /*  CCBCR7          */
+    volatile uint32_t  CNBCR7;                                 /*  CNBCR7          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR8;                                  /*  CECR8           */
+    volatile uint32_t  CSCR8;                                  /*  CSCR8           */
+    volatile uint32_t  CCBCR8;                                 /*  CCBCR8          */
+    volatile uint32_t  CNBCR8;                                 /*  CNBCR8          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR9;                                  /*  CECR9           */
+    volatile uint32_t  CSCR9;                                  /*  CSCR9           */
+    volatile uint32_t  CCBCR9;                                 /*  CCBCR9          */
+    volatile uint32_t  CNBCR9;                                 /*  CNBCR9          */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR10;                                 /*  CECR10          */
+    volatile uint32_t  CSCR10;                                 /*  CSCR10          */
+    volatile uint32_t  CCBCR10;                                /*  CCBCR10         */
+    volatile uint32_t  CNBCR10;                                /*  CNBCR10         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR11;                                 /*  CECR11          */
+    volatile uint32_t  CSCR11;                                 /*  CSCR11          */
+    volatile uint32_t  CCBCR11;                                /*  CCBCR11         */
+    volatile uint32_t  CNBCR11;                                /*  CNBCR11         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR12;                                 /*  CECR12          */
+    volatile uint32_t  CSCR12;                                 /*  CSCR12          */
+    volatile uint32_t  CCBCR12;                                /*  CCBCR12         */
+    volatile uint32_t  CNBCR12;                                /*  CNBCR12         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR13;                                 /*  CECR13          */
+    volatile uint32_t  CSCR13;                                 /*  CSCR13          */
+    volatile uint32_t  CCBCR13;                                /*  CCBCR13         */
+    volatile uint32_t  CNBCR13;                                /*  CNBCR13         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR14;                                 /*  CECR14          */
+    volatile uint32_t  CSCR14;                                 /*  CSCR14          */
+    volatile uint32_t  CCBCR14;                                /*  CCBCR14         */
+    volatile uint32_t  CNBCR14;                                /*  CNBCR14         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR15;                                 /*  CECR15          */
+    volatile uint32_t  CSCR15;                                 /*  CSCR15          */
+    volatile uint32_t  CCBCR15;                                /*  CCBCR15         */
+    volatile uint32_t  CNBCR15;                                /*  CNBCR15         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR16;                                 /*  CECR16          */
+    volatile uint32_t  CSCR16;                                 /*  CSCR16          */
+    volatile uint32_t  CCBCR16;                                /*  CCBCR16         */
+    volatile uint32_t  CNBCR16;                                /*  CNBCR16         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR17;                                 /*  CECR17          */
+    volatile uint32_t  CSCR17;                                 /*  CSCR17          */
+    volatile uint32_t  CCBCR17;                                /*  CCBCR17         */
+    volatile uint32_t  CNBCR17;                                /*  CNBCR17         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR18;                                 /*  CECR18          */
+    volatile uint32_t  CSCR18;                                 /*  CSCR18          */
+    volatile uint32_t  CCBCR18;                                /*  CCBCR18         */
+    volatile uint32_t  CNBCR18;                                /*  CNBCR18         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR19;                                 /*  CECR19          */
+    volatile uint32_t  CSCR19;                                 /*  CSCR19          */
+    volatile uint32_t  CCBCR19;                                /*  CCBCR19         */
+    volatile uint32_t  CNBCR19;                                /*  CNBCR19         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR20;                                 /*  CECR20          */
+    volatile uint32_t  CSCR20;                                 /*  CSCR20          */
+    volatile uint32_t  CCBCR20;                                /*  CCBCR20         */
+    volatile uint32_t  CNBCR20;                                /*  CNBCR20         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR21;                                 /*  CECR21          */
+    volatile uint32_t  CSCR21;                                 /*  CSCR21          */
+    volatile uint32_t  CCBCR21;                                /*  CCBCR21         */
+    volatile uint32_t  CNBCR21;                                /*  CNBCR21         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR22;                                 /*  CECR22          */
+    volatile uint32_t  CSCR22;                                 /*  CSCR22          */
+    volatile uint32_t  CCBCR22;                                /*  CCBCR22         */
+    volatile uint32_t  CNBCR22;                                /*  CNBCR22         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR23;                                 /*  CECR23          */
+    volatile uint32_t  CSCR23;                                 /*  CSCR23          */
+    volatile uint32_t  CCBCR23;                                /*  CCBCR23         */
+    volatile uint32_t  CNBCR23;                                /*  CNBCR23         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR24;                                 /*  CECR24          */
+    volatile uint32_t  CSCR24;                                 /*  CSCR24          */
+    volatile uint32_t  CCBCR24;                                /*  CCBCR24         */
+    volatile uint32_t  CNBCR24;                                /*  CNBCR24         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR25;                                 /*  CECR25          */
+    volatile uint32_t  CSCR25;                                 /*  CSCR25          */
+    volatile uint32_t  CCBCR25;                                /*  CCBCR25         */
+    volatile uint32_t  CNBCR25;                                /*  CNBCR25         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR26;                                 /*  CECR26          */
+    volatile uint32_t  CSCR26;                                 /*  CSCR26          */
+    volatile uint32_t  CCBCR26;                                /*  CCBCR26         */
+    volatile uint32_t  CNBCR26;                                /*  CNBCR26         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR27;                                 /*  CECR27          */
+    volatile uint32_t  CSCR27;                                 /*  CSCR27          */
+    volatile uint32_t  CCBCR27;                                /*  CCBCR27         */
+    volatile uint32_t  CNBCR27;                                /*  CNBCR27         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR28;                                 /*  CECR28          */
+    volatile uint32_t  CSCR28;                                 /*  CSCR28          */
+    volatile uint32_t  CCBCR28;                                /*  CCBCR28         */
+    volatile uint32_t  CNBCR28;                                /*  CNBCR28         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR29;                                 /*  CECR29          */
+    volatile uint32_t  CSCR29;                                 /*  CSCR29          */
+    volatile uint32_t  CCBCR29;                                /*  CCBCR29         */
+    volatile uint32_t  CNBCR29;                                /*  CNBCR29         */
+
+/* end of struct st_mlb_from_cecr0 */
+
+/* start of struct st_mlb_from_cecr0 */
+    volatile uint32_t  CECR30;                                 /*  CECR30          */
+    volatile uint32_t  CSCR30;                                 /*  CSCR30          */
+    volatile uint32_t  CCBCR30;                                /*  CCBCR30         */
+    volatile uint32_t  CNBCR30;                                /*  CNBCR30         */
+
+/* end of struct st_mlb_from_cecr0 */
+    volatile uint8_t   dummy158[80];                           /*                  */
+
+/* #define MLB_LCBCR0_COUNT (31) */
+    volatile uint32_t  LCBCR0;                                 /*  LCBCR0          */
+    volatile uint32_t  LCBCR1;                                 /*  LCBCR1          */
+    volatile uint32_t  LCBCR2;                                 /*  LCBCR2          */
+    volatile uint32_t  LCBCR3;                                 /*  LCBCR3          */
+    volatile uint32_t  LCBCR4;                                 /*  LCBCR4          */
+    volatile uint32_t  LCBCR5;                                 /*  LCBCR5          */
+    volatile uint32_t  LCBCR6;                                 /*  LCBCR6          */
+    volatile uint32_t  LCBCR7;                                 /*  LCBCR7          */
+    volatile uint32_t  LCBCR8;                                 /*  LCBCR8          */
+    volatile uint32_t  LCBCR9;                                 /*  LCBCR9          */
+    volatile uint32_t  LCBCR10;                                /*  LCBCR10         */
+    volatile uint32_t  LCBCR11;                                /*  LCBCR11         */
+    volatile uint32_t  LCBCR12;                                /*  LCBCR12         */
+    volatile uint32_t  LCBCR13;                                /*  LCBCR13         */
+    volatile uint32_t  LCBCR14;                                /*  LCBCR14         */
+    volatile uint32_t  LCBCR15;                                /*  LCBCR15         */
+    volatile uint32_t  LCBCR16;                                /*  LCBCR16         */
+    volatile uint32_t  LCBCR17;                                /*  LCBCR17         */
+    volatile uint32_t  LCBCR18;                                /*  LCBCR18         */
+    volatile uint32_t  LCBCR19;                                /*  LCBCR19         */
+    volatile uint32_t  LCBCR20;                                /*  LCBCR20         */
+    volatile uint32_t  LCBCR21;                                /*  LCBCR21         */
+    volatile uint32_t  LCBCR22;                                /*  LCBCR22         */
+    volatile uint32_t  LCBCR23;                                /*  LCBCR23         */
+    volatile uint32_t  LCBCR24;                                /*  LCBCR24         */
+    volatile uint32_t  LCBCR25;                                /*  LCBCR25         */
+    volatile uint32_t  LCBCR26;                                /*  LCBCR26         */
+    volatile uint32_t  LCBCR27;                                /*  LCBCR27         */
+    volatile uint32_t  LCBCR28;                                /*  LCBCR28         */
+    volatile uint32_t  LCBCR29;                                /*  LCBCR29         */
+    volatile uint32_t  LCBCR30;                                /*  LCBCR30         */
+} r_io_mlb_t;
+
+
+typedef struct st_mlb_from_cecr0
+{
+ 
+    volatile uint32_t  CECR0;                                  /*  CECR0           */
+    volatile uint32_t  CSCR0;                                  /*  CSCR0           */
+    volatile uint32_t  CCBCR0;                                 /*  CCBCR0          */
+    volatile uint32_t  CNBCR0;                                 /*  CNBCR0          */
+} r_io_mlb_from_cecr0_t;
+
+
+/* Channel array defines of MLB (2)*/
+#ifdef  DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS
+volatile struct st_mlb_from_cecr0*  MLB_FROM_CECR0_ARRAY[ MLB_FROM_CECR0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    MLB_FROM_CECR0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS */
+/* End of channel array defines of MLB (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
 /* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mmc_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,53 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : mmc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef MMC_IODEFINE_H
 #define MMC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_mmc
-{                                                          /* MMC              */
+#define MMC     (*(struct st_mmc     *)0xE804C800uL) /* MMC */
+
+
+#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH)
+#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL)
+#define MMCCE_ARG (MMC.CE_ARG)
+#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12)
+#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL)
+#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET)
+#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL)
+#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC)
+#define MMCCE_RESP3 (MMC.CE_RESP3)
+#define MMCCE_RESP2 (MMC.CE_RESP2)
+#define MMCCE_RESP1 (MMC.CE_RESP1)
+#define MMCCE_RESP0 (MMC.CE_RESP0)
+#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12)
+#define MMCCE_DATA (MMC.CE_DATA)
+#define MMCCE_INT (MMC.CE_INT)
+#define MMCCE_INT_EN (MMC.CE_INT_EN)
+#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1)
+#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2)
+#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE)
+#define MMCCE_DETECT (MMC.CE_DETECT)
+#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE)
+#define MMCCE_VERSION (MMC.CE_VERSION)
+
+#define MMC_CE_RESPn_COUNT (4)
+
+
+typedef struct st_mmc
+{
+                                                           /* MMC              */
     volatile uint16_t CE_CMD_SETH;                      /*  CE_CMD_SETH */
     volatile uint16_t CE_CMD_SETL;                      /*  CE_CMD_SETL */
     volatile uint8_t   dummy182[4];                            /*                  */
@@ -41,7 +74,8 @@
     volatile uint32_t  CE_BLOCK_SET;                           /*  CE_BLOCK_SET    */
     volatile uint32_t  CE_CLK_CTRL;                            /*  CE_CLK_CTRL     */
     volatile uint32_t  CE_BUF_ACC;                             /*  CE_BUF_ACC      */
-#define MMC_CE_RESPn_COUNT 4
+
+/* #define MMC_CE_RESPn_COUNT (4) */
     volatile uint32_t  CE_RESP3;                               /*  CE_RESP3        */
     volatile uint32_t  CE_RESP2;                               /*  CE_RESP2        */
     volatile uint32_t  CE_RESP1;                               /*  CE_RESP1        */
@@ -60,33 +94,11 @@
     volatile uint32_t  CE_ADD_MODE;                            /*  CE_ADD_MODE     */
     volatile uint8_t   dummy186[4];                            /*                  */
     volatile uint32_t  CE_VERSION;                             /*  CE_VERSION      */
-};
-
-
-#define MMC     (*(struct st_mmc     *)0xE804C800uL) /* MMC */
+} r_io_mmc_t;
 
 
-#define MMCCE_CMD_SETH MMC.CE_CMD_SETH
-#define MMCCE_CMD_SETL MMC.CE_CMD_SETL
-#define MMCCE_ARG MMC.CE_ARG
-#define MMCCE_ARG_CMD12 MMC.CE_ARG_CMD12
-#define MMCCE_CMD_CTRL MMC.CE_CMD_CTRL
-#define MMCCE_BLOCK_SET MMC.CE_BLOCK_SET
-#define MMCCE_CLK_CTRL MMC.CE_CLK_CTRL
-#define MMCCE_BUF_ACC MMC.CE_BUF_ACC
-#define MMCCE_RESP3 MMC.CE_RESP3
-#define MMCCE_RESP2 MMC.CE_RESP2
-#define MMCCE_RESP1 MMC.CE_RESP1
-#define MMCCE_RESP0 MMC.CE_RESP0
-#define MMCCE_RESP_CMD12 MMC.CE_RESP_CMD12
-#define MMCCE_DATA MMC.CE_DATA
-#define MMCCE_INT MMC.CE_INT
-#define MMCCE_INT_EN MMC.CE_INT_EN
-#define MMCCE_HOST_STS1 MMC.CE_HOST_STS1
-#define MMCCE_HOST_STS2 MMC.CE_HOST_STS2
-#define MMCCE_DMA_MODE MMC.CE_DMA_MODE
-#define MMCCE_DETECT MMC.CE_DETECT
-#define MMCCE_ADD_MODE MMC.CE_ADD_MODE
-#define MMCCE_VERSION MMC.CE_VERSION
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/mtu2_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,108 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : mtu2_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef MTU2_IODEFINE_H
 #define MTU2_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_mtu2
-{                                                          /* MTU2             */
+#define MTU2    (*(struct st_mtu2    *)0xFCFF0000uL) /* MTU2 */
+
+
+#define MTU2TCR_2 (MTU2.TCR_2)
+#define MTU2TMDR_2 (MTU2.TMDR_2)
+#define MTU2TIOR_2 (MTU2.TIOR_2)
+#define MTU2TIER_2 (MTU2.TIER_2)
+#define MTU2TSR_2 (MTU2.TSR_2)
+#define MTU2TCNT_2 (MTU2.TCNT_2)
+#define MTU2TGRA_2 (MTU2.TGRA_2)
+#define MTU2TGRB_2 (MTU2.TGRB_2)
+#define MTU2TCR_3 (MTU2.TCR_3)
+#define MTU2TCR_4 (MTU2.TCR_4)
+#define MTU2TMDR_3 (MTU2.TMDR_3)
+#define MTU2TMDR_4 (MTU2.TMDR_4)
+#define MTU2TIORH_3 (MTU2.TIORH_3)
+#define MTU2TIORL_3 (MTU2.TIORL_3)
+#define MTU2TIORH_4 (MTU2.TIORH_4)
+#define MTU2TIORL_4 (MTU2.TIORL_4)
+#define MTU2TIER_3 (MTU2.TIER_3)
+#define MTU2TIER_4 (MTU2.TIER_4)
+#define MTU2TOER (MTU2.TOER)
+#define MTU2TGCR (MTU2.TGCR)
+#define MTU2TOCR1 (MTU2.TOCR1)
+#define MTU2TOCR2 (MTU2.TOCR2)
+#define MTU2TCNT_3 (MTU2.TCNT_3)
+#define MTU2TCNT_4 (MTU2.TCNT_4)
+#define MTU2TCDR (MTU2.TCDR)
+#define MTU2TDDR (MTU2.TDDR)
+#define MTU2TGRA_3 (MTU2.TGRA_3)
+#define MTU2TGRB_3 (MTU2.TGRB_3)
+#define MTU2TGRA_4 (MTU2.TGRA_4)
+#define MTU2TGRB_4 (MTU2.TGRB_4)
+#define MTU2TCNTS (MTU2.TCNTS)
+#define MTU2TCBR (MTU2.TCBR)
+#define MTU2TGRC_3 (MTU2.TGRC_3)
+#define MTU2TGRD_3 (MTU2.TGRD_3)
+#define MTU2TGRC_4 (MTU2.TGRC_4)
+#define MTU2TGRD_4 (MTU2.TGRD_4)
+#define MTU2TSR_3 (MTU2.TSR_3)
+#define MTU2TSR_4 (MTU2.TSR_4)
+#define MTU2TITCR (MTU2.TITCR)
+#define MTU2TITCNT (MTU2.TITCNT)
+#define MTU2TBTER (MTU2.TBTER)
+#define MTU2TDER (MTU2.TDER)
+#define MTU2TOLBR (MTU2.TOLBR)
+#define MTU2TBTM_3 (MTU2.TBTM_3)
+#define MTU2TBTM_4 (MTU2.TBTM_4)
+#define MTU2TADCR (MTU2.TADCR)
+#define MTU2TADCORA_4 (MTU2.TADCORA_4)
+#define MTU2TADCORB_4 (MTU2.TADCORB_4)
+#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4)
+#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4)
+#define MTU2TWCR (MTU2.TWCR)
+#define MTU2TSTR (MTU2.TSTR)
+#define MTU2TSYR (MTU2.TSYR)
+#define MTU2TRWER (MTU2.TRWER)
+#define MTU2TCR_0 (MTU2.TCR_0)
+#define MTU2TMDR_0 (MTU2.TMDR_0)
+#define MTU2TIORH_0 (MTU2.TIORH_0)
+#define MTU2TIORL_0 (MTU2.TIORL_0)
+#define MTU2TIER_0 (MTU2.TIER_0)
+#define MTU2TSR_0 (MTU2.TSR_0)
+#define MTU2TCNT_0 (MTU2.TCNT_0)
+#define MTU2TGRA_0 (MTU2.TGRA_0)
+#define MTU2TGRB_0 (MTU2.TGRB_0)
+#define MTU2TGRC_0 (MTU2.TGRC_0)
+#define MTU2TGRD_0 (MTU2.TGRD_0)
+#define MTU2TGRE_0 (MTU2.TGRE_0)
+#define MTU2TGRF_0 (MTU2.TGRF_0)
+#define MTU2TIER2_0 (MTU2.TIER2_0)
+#define MTU2TSR2_0 (MTU2.TSR2_0)
+#define MTU2TBTM_0 (MTU2.TBTM_0)
+#define MTU2TCR_1 (MTU2.TCR_1)
+#define MTU2TMDR_1 (MTU2.TMDR_1)
+#define MTU2TIOR_1 (MTU2.TIOR_1)
+#define MTU2TIER_1 (MTU2.TIER_1)
+#define MTU2TSR_1 (MTU2.TSR_1)
+#define MTU2TCNT_1 (MTU2.TCNT_1)
+#define MTU2TGRA_1 (MTU2.TGRA_1)
+#define MTU2TGRB_1 (MTU2.TGRB_1)
+#define MTU2TICCR (MTU2.TICCR)
+
+
+typedef struct st_mtu2
+{
+                                                           /* MTU2             */
     volatile uint8_t   TCR_2;                                  /*  TCR_2           */
     volatile uint8_t   TMDR_2;                                 /*  TMDR_2          */
     volatile uint8_t   TIOR_2;                                 /*  TIOR_2          */
@@ -128,90 +216,11 @@
     volatile uint16_t TGRB_1;                                 /*  TGRB_1          */
     volatile uint8_t   dummy536[4];                            /*                  */
     volatile uint8_t   TICCR;                                  /*  TICCR           */
-};
-
-
-#define MTU2    (*(struct st_mtu2    *)0xFCFF0000uL) /* MTU2 */
+} r_io_mtu2_t;
 
 
-#define MTU2TCR_2 MTU2.TCR_2
-#define MTU2TMDR_2 MTU2.TMDR_2
-#define MTU2TIOR_2 MTU2.TIOR_2
-#define MTU2TIER_2 MTU2.TIER_2
-#define MTU2TSR_2 MTU2.TSR_2
-#define MTU2TCNT_2 MTU2.TCNT_2
-#define MTU2TGRA_2 MTU2.TGRA_2
-#define MTU2TGRB_2 MTU2.TGRB_2
-#define MTU2TCR_3 MTU2.TCR_3
-#define MTU2TCR_4 MTU2.TCR_4
-#define MTU2TMDR_3 MTU2.TMDR_3
-#define MTU2TMDR_4 MTU2.TMDR_4
-#define MTU2TIORH_3 MTU2.TIORH_3
-#define MTU2TIORL_3 MTU2.TIORL_3
-#define MTU2TIORH_4 MTU2.TIORH_4
-#define MTU2TIORL_4 MTU2.TIORL_4
-#define MTU2TIER_3 MTU2.TIER_3
-#define MTU2TIER_4 MTU2.TIER_4
-#define MTU2TOER MTU2.TOER
-#define MTU2TGCR MTU2.TGCR
-#define MTU2TOCR1 MTU2.TOCR1
-#define MTU2TOCR2 MTU2.TOCR2
-#define MTU2TCNT_3 MTU2.TCNT_3
-#define MTU2TCNT_4 MTU2.TCNT_4
-#define MTU2TCDR MTU2.TCDR
-#define MTU2TDDR MTU2.TDDR
-#define MTU2TGRA_3 MTU2.TGRA_3
-#define MTU2TGRB_3 MTU2.TGRB_3
-#define MTU2TGRA_4 MTU2.TGRA_4
-#define MTU2TGRB_4 MTU2.TGRB_4
-#define MTU2TCNTS MTU2.TCNTS
-#define MTU2TCBR MTU2.TCBR
-#define MTU2TGRC_3 MTU2.TGRC_3
-#define MTU2TGRD_3 MTU2.TGRD_3
-#define MTU2TGRC_4 MTU2.TGRC_4
-#define MTU2TGRD_4 MTU2.TGRD_4
-#define MTU2TSR_3 MTU2.TSR_3
-#define MTU2TSR_4 MTU2.TSR_4
-#define MTU2TITCR MTU2.TITCR
-#define MTU2TITCNT MTU2.TITCNT
-#define MTU2TBTER MTU2.TBTER
-#define MTU2TDER MTU2.TDER
-#define MTU2TOLBR MTU2.TOLBR
-#define MTU2TBTM_3 MTU2.TBTM_3
-#define MTU2TBTM_4 MTU2.TBTM_4
-#define MTU2TADCR MTU2.TADCR
-#define MTU2TADCORA_4 MTU2.TADCORA_4
-#define MTU2TADCORB_4 MTU2.TADCORB_4
-#define MTU2TADCOBRA_4 MTU2.TADCOBRA_4
-#define MTU2TADCOBRB_4 MTU2.TADCOBRB_4
-#define MTU2TWCR MTU2.TWCR
-#define MTU2TSTR MTU2.TSTR
-#define MTU2TSYR MTU2.TSYR
-#define MTU2TRWER MTU2.TRWER
-#define MTU2TCR_0 MTU2.TCR_0
-#define MTU2TMDR_0 MTU2.TMDR_0
-#define MTU2TIORH_0 MTU2.TIORH_0
-#define MTU2TIORL_0 MTU2.TIORL_0
-#define MTU2TIER_0 MTU2.TIER_0
-#define MTU2TSR_0 MTU2.TSR_0
-#define MTU2TCNT_0 MTU2.TCNT_0
-#define MTU2TGRA_0 MTU2.TGRA_0
-#define MTU2TGRB_0 MTU2.TGRB_0
-#define MTU2TGRC_0 MTU2.TGRC_0
-#define MTU2TGRD_0 MTU2.TGRD_0
-#define MTU2TGRE_0 MTU2.TGRE_0
-#define MTU2TGRF_0 MTU2.TGRF_0
-#define MTU2TIER2_0 MTU2.TIER2_0
-#define MTU2TSR2_0 MTU2.TSR2_0
-#define MTU2TBTM_0 MTU2.TBTM_0
-#define MTU2TCR_1 MTU2.TCR_1
-#define MTU2TMDR_1 MTU2.TMDR_1
-#define MTU2TIOR_1 MTU2.TIOR_1
-#define MTU2TIER_1 MTU2.TIER_1
-#define MTU2TSR_1 MTU2.TSR_1
-#define MTU2TCNT_1 MTU2.TCNT_1
-#define MTU2TGRA_1 MTU2.TGRA_1
-#define MTU2TGRB_1 MTU2.TGRB_1
-#define MTU2TICCR MTU2.TICCR
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ostm_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,55 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : ostm_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef OSTM_IODEFINE_H
 #define OSTM_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_ostm
-{                                                          /* OSTM             */
+#define OSTM0   (*(struct st_ostm    *)0xFCFEC000uL) /* OSTM0 */
+#define OSTM1   (*(struct st_ostm    *)0xFCFEC400uL) /* OSTM1 */
+
+
+/* Start of channel array defines of OSTM */
+
+/* Channel array defines of OSTM */
+/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
+#define OSTM_COUNT  (2)
+#define OSTM_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &OSTM0, &OSTM1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of OSTM */
+
+
+#define OSTM0CMP (OSTM0.OSTMnCMP)
+#define OSTM0CNT (OSTM0.OSTMnCNT)
+#define OSTM0TE (OSTM0.OSTMnTE)
+#define OSTM0TS (OSTM0.OSTMnTS)
+#define OSTM0TT (OSTM0.OSTMnTT)
+#define OSTM0CTL (OSTM0.OSTMnCTL)
+#define OSTM1CMP (OSTM1.OSTMnCMP)
+#define OSTM1CNT (OSTM1.OSTMnCNT)
+#define OSTM1TE (OSTM1.OSTMnTE)
+#define OSTM1TS (OSTM1.OSTMnTS)
+#define OSTM1TT (OSTM1.OSTMnTT)
+#define OSTM1CTL (OSTM1.OSTMnCTL)
+
+
+typedef struct st_ostm
+{
+                                                           /* OSTM             */
     volatile uint32_t  OSTMnCMP;                               /*  OSTMnCMP        */
     volatile uint32_t  OSTMnCNT;                               /*  OSTMnCNT        */
     volatile uint8_t   dummy1[8];                              /*                  */
@@ -42,37 +77,21 @@
     volatile uint8_t   OSTMnTT;                                /*  OSTMnTT         */
     volatile uint8_t   dummy4[7];                              /*                  */
     volatile uint8_t   OSTMnCTL;                               /*  OSTMnCTL        */
-};
-
-
-#define OSTM0   (*(struct st_ostm    *)0xFCFEC000uL) /* OSTM0 */
-#define OSTM1   (*(struct st_ostm    *)0xFCFEC400uL) /* OSTM1 */
+} r_io_ostm_t;
 
 
-/* Start of channnel array defines of OSTM */
-
-/* Channnel array defines of OSTM */
-/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
-#define OSTM_COUNT  2
-#define OSTM_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &OSTM0, &OSTM1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of OSTM */
+/* Channel array defines of OSTM (2)*/
+#ifdef  DECLARE_OSTM_CHANNELS
+volatile struct st_ostm*  OSTM[ OSTM_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    OSTM_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_OSTM_CHANNELS */
+/* End of channel array defines of OSTM (2)*/
 
 
-#define OSTM0CMP OSTM0.OSTMnCMP
-#define OSTM0CNT OSTM0.OSTMnCNT
-#define OSTM0TE OSTM0.OSTMnTE
-#define OSTM0TS OSTM0.OSTMnTS
-#define OSTM0TT OSTM0.OSTMnTT
-#define OSTM0CTL OSTM0.OSTMnCTL
-#define OSTM1CMP OSTM1.OSTMnCMP
-#define OSTM1CNT OSTM1.OSTMnCNT
-#define OSTM1TE OSTM1.OSTMnTE
-#define OSTM1TS OSTM1.OSTMnTS
-#define OSTM1TT OSTM1.OSTMnTT
-#define OSTM1CTL OSTM1.OSTMnCTL
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pfv_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,25 +18,112 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : pfv_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef PFV_IODEFINE_H
 #define PFV_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_pfv
-{                                                          /* PFV              */
+#define PFV0    (*(struct st_pfv     *)0xE8205000uL) /* PFV0 */
+#define PFV1    (*(struct st_pfv     *)0xE8205800uL) /* PFV1 */
+
+
+/* Start of channel array defines of PFV */
+
+/* Channel array defines of PFV */
+/*(Sample) value = PFV[ channel ]->PFVCR; */
+#define PFV_COUNT  (2)
+#define PFV_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &PFV0, &PFV1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of PFV */
+
+
+#define PFV0PFVCR (PFV0.PFVCR)
+#define PFV0PFVICR (PFV0.PFVICR)
+#define PFV0PFVISR (PFV0.PFVISR)
+#define PFV0PFVID0 (PFV0.PFVID0)
+#define PFV0PFVID1 (PFV0.PFVID1)
+#define PFV0PFVID2 (PFV0.PFVID2)
+#define PFV0PFVID3 (PFV0.PFVID3)
+#define PFV0PFVID4 (PFV0.PFVID4)
+#define PFV0PFVID5 (PFV0.PFVID5)
+#define PFV0PFVID6 (PFV0.PFVID6)
+#define PFV0PFVID7 (PFV0.PFVID7)
+#define PFV0PFVOD0 (PFV0.PFVOD0)
+#define PFV0PFVOD1 (PFV0.PFVOD1)
+#define PFV0PFVOD2 (PFV0.PFVOD2)
+#define PFV0PFVOD3 (PFV0.PFVOD3)
+#define PFV0PFVOD4 (PFV0.PFVOD4)
+#define PFV0PFVOD5 (PFV0.PFVOD5)
+#define PFV0PFVOD6 (PFV0.PFVOD6)
+#define PFV0PFVOD7 (PFV0.PFVOD7)
+#define PFV0PFVIFSR (PFV0.PFVIFSR)
+#define PFV0PFVOFSR (PFV0.PFVOFSR)
+#define PFV0PFVACR (PFV0.PFVACR)
+#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE)
+#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0)
+#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1)
+#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0)
+#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1)
+#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0)
+#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1)
+#define PFV0PFVSZR (PFV0.PFVSZR)
+#define PFV1PFVCR (PFV1.PFVCR)
+#define PFV1PFVICR (PFV1.PFVICR)
+#define PFV1PFVISR (PFV1.PFVISR)
+#define PFV1PFVID0 (PFV1.PFVID0)
+#define PFV1PFVID1 (PFV1.PFVID1)
+#define PFV1PFVID2 (PFV1.PFVID2)
+#define PFV1PFVID3 (PFV1.PFVID3)
+#define PFV1PFVID4 (PFV1.PFVID4)
+#define PFV1PFVID5 (PFV1.PFVID5)
+#define PFV1PFVID6 (PFV1.PFVID6)
+#define PFV1PFVID7 (PFV1.PFVID7)
+#define PFV1PFVOD0 (PFV1.PFVOD0)
+#define PFV1PFVOD1 (PFV1.PFVOD1)
+#define PFV1PFVOD2 (PFV1.PFVOD2)
+#define PFV1PFVOD3 (PFV1.PFVOD3)
+#define PFV1PFVOD4 (PFV1.PFVOD4)
+#define PFV1PFVOD5 (PFV1.PFVOD5)
+#define PFV1PFVOD6 (PFV1.PFVOD6)
+#define PFV1PFVOD7 (PFV1.PFVOD7)
+#define PFV1PFVIFSR (PFV1.PFVIFSR)
+#define PFV1PFVOFSR (PFV1.PFVOFSR)
+#define PFV1PFVACR (PFV1.PFVACR)
+#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE)
+#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0)
+#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1)
+#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0)
+#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1)
+#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0)
+#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1)
+#define PFV1PFVSZR (PFV1.PFVSZR)
+
+#define PFVID_COUNT (8)
+#define PFVOD_COUNT (8)
+
+
+typedef struct st_pfv
+{
+                                                           /* PFV              */
     volatile uint32_t  PFVCR;                                  /*  PFVCR           */
     volatile uint32_t  PFVICR;                                 /*  PFVICR          */
     volatile uint32_t  PFVISR;                                 /*  PFVISR          */
     volatile uint8_t   dummy1[20];                             /*                  */
-#define PFVID_COUNT 8
+
+/* #define PFVID_COUNT (8) */
     volatile uint32_t  PFVID0;                                 /*  PFVID0          */
     volatile uint32_t  PFVID1;                                 /*  PFVID1          */
     volatile uint32_t  PFVID2;                                 /*  PFVID2          */
@@ -45,7 +132,8 @@
     volatile uint32_t  PFVID5;                                 /*  PFVID5          */
     volatile uint32_t  PFVID6;                                 /*  PFVID6          */
     volatile uint32_t  PFVID7;                                 /*  PFVID7          */
-#define PFVOD_COUNT 8
+
+/* #define PFVOD_COUNT (8) */
     volatile uint32_t  PFVOD0;                                 /*  PFVOD0          */
     volatile uint32_t  PFVOD1;                                 /*  PFVOD1          */
     volatile uint32_t  PFVOD2;                                 /*  PFVOD2          */
@@ -66,85 +154,21 @@
     volatile uint32_t  PFV_MTX_CRR_ADJ0;                       /*  PFV_MTX_CRR_ADJ0 */
     volatile uint32_t  PFV_MTX_CRR_ADJ1;                       /*  PFV_MTX_CRR_ADJ1 */
     volatile uint32_t  PFVSZR;                                 /*  PFVSZR          */
-};
-
-
-#define PFV0    (*(struct st_pfv     *)0xE8205000uL) /* PFV0 */
-#define PFV1    (*(struct st_pfv     *)0xE8205800uL) /* PFV1 */
-
-
-/* Start of channnel array defines of PFV */
-
-/* Channnel array defines of PFV */
-/*(Sample) value = PFV[ channel ]->PFVCR; */
-#define PFV_COUNT  2
-#define PFV_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &PFV0, &PFV1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of PFV */
+} r_io_pfv_t;
 
 
-#define PFV0PFVCR PFV0.PFVCR
-#define PFV0PFVICR PFV0.PFVICR
-#define PFV0PFVISR PFV0.PFVISR
-#define PFV0PFVID0 PFV0.PFVID0
-#define PFV0PFVID1 PFV0.PFVID1
-#define PFV0PFVID2 PFV0.PFVID2
-#define PFV0PFVID3 PFV0.PFVID3
-#define PFV0PFVID4 PFV0.PFVID4
-#define PFV0PFVID5 PFV0.PFVID5
-#define PFV0PFVID6 PFV0.PFVID6
-#define PFV0PFVID7 PFV0.PFVID7
-#define PFV0PFVOD0 PFV0.PFVOD0
-#define PFV0PFVOD1 PFV0.PFVOD1
-#define PFV0PFVOD2 PFV0.PFVOD2
-#define PFV0PFVOD3 PFV0.PFVOD3
-#define PFV0PFVOD4 PFV0.PFVOD4
-#define PFV0PFVOD5 PFV0.PFVOD5
-#define PFV0PFVOD6 PFV0.PFVOD6
-#define PFV0PFVOD7 PFV0.PFVOD7
-#define PFV0PFVIFSR PFV0.PFVIFSR
-#define PFV0PFVOFSR PFV0.PFVOFSR
-#define PFV0PFVACR PFV0.PFVACR
-#define PFV0PFV_MTX_MODE PFV0.PFV_MTX_MODE
-#define PFV0PFV_MTX_YG_ADJ0 PFV0.PFV_MTX_YG_ADJ0
-#define PFV0PFV_MTX_YG_ADJ1 PFV0.PFV_MTX_YG_ADJ1
-#define PFV0PFV_MTX_CBB_ADJ0 PFV0.PFV_MTX_CBB_ADJ0
-#define PFV0PFV_MTX_CBB_ADJ1 PFV0.PFV_MTX_CBB_ADJ1
-#define PFV0PFV_MTX_CRR_ADJ0 PFV0.PFV_MTX_CRR_ADJ0
-#define PFV0PFV_MTX_CRR_ADJ1 PFV0.PFV_MTX_CRR_ADJ1
-#define PFV0PFVSZR PFV0.PFVSZR
-#define PFV1PFVCR PFV1.PFVCR
-#define PFV1PFVICR PFV1.PFVICR
-#define PFV1PFVISR PFV1.PFVISR
-#define PFV1PFVID0 PFV1.PFVID0
-#define PFV1PFVID1 PFV1.PFVID1
-#define PFV1PFVID2 PFV1.PFVID2
-#define PFV1PFVID3 PFV1.PFVID3
-#define PFV1PFVID4 PFV1.PFVID4
-#define PFV1PFVID5 PFV1.PFVID5
-#define PFV1PFVID6 PFV1.PFVID6
-#define PFV1PFVID7 PFV1.PFVID7
-#define PFV1PFVOD0 PFV1.PFVOD0
-#define PFV1PFVOD1 PFV1.PFVOD1
-#define PFV1PFVOD2 PFV1.PFVOD2
-#define PFV1PFVOD3 PFV1.PFVOD3
-#define PFV1PFVOD4 PFV1.PFVOD4
-#define PFV1PFVOD5 PFV1.PFVOD5
-#define PFV1PFVOD6 PFV1.PFVOD6
-#define PFV1PFVOD7 PFV1.PFVOD7
-#define PFV1PFVIFSR PFV1.PFVIFSR
-#define PFV1PFVOFSR PFV1.PFVOFSR
-#define PFV1PFVACR PFV1.PFVACR
-#define PFV1PFV_MTX_MODE PFV1.PFV_MTX_MODE
-#define PFV1PFV_MTX_YG_ADJ0 PFV1.PFV_MTX_YG_ADJ0
-#define PFV1PFV_MTX_YG_ADJ1 PFV1.PFV_MTX_YG_ADJ1
-#define PFV1PFV_MTX_CBB_ADJ0 PFV1.PFV_MTX_CBB_ADJ0
-#define PFV1PFV_MTX_CBB_ADJ1 PFV1.PFV_MTX_CBB_ADJ1
-#define PFV1PFV_MTX_CRR_ADJ0 PFV1.PFV_MTX_CRR_ADJ0
-#define PFV1PFV_MTX_CRR_ADJ1 PFV1.PFV_MTX_CRR_ADJ1
-#define PFV1PFVSZR PFV1.PFVSZR
+/* Channel array defines of PFV (2)*/
+#ifdef  DECLARE_PFV_CHANNELS
+volatile struct st_pfv*  PFV[ PFV_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    PFV_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_PFV_CHANNELS */
+/* End of channel array defines of PFV (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/pwm_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,83 +18,29 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : pwm_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef PWM_IODEFINE_H
 #define PWM_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
 /* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-union reg16_8_t
-{
-    volatile uint16_t  UINT16;                                  /*  16-bit Access   */
-    volatile uint8_t   UINT8[2];                                /*  8-bit Access    */
-};
-
-struct st_pwm
-{                                                          /* PWM              */
-    volatile uint8_t   dummy559[2];                            /*                  */
-    union reg16_8_t  PWBTCR;                          /*  PWBTCR      */
-    
-    volatile uint8_t   dummy560[216];                          /*                  */
-    
-/* start of struct st_pwm_common */
-    union reg16_8_t  PWCR_1;                          /*  PWCR_1      */
-    
-    volatile uint8_t   dummy561[2];                            /*                  */
-    union reg16_8_t  PWPR_1;                          /*  PWPR_1      */
-    
-    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
-    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
-    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
-    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
-    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
-/* end of struct st_pwm_common */
-    
-/* start of struct st_pwm_common */
-    union reg16_8_t  PWCR_2;                          /*  PWCR_2      */
-    
-    volatile uint8_t   dummy562[2];                            /*                  */
-    union reg16_8_t  PWPR_2;                          /*  PWPR_2      */
-    
-    volatile uint16_t PWCYR_2;                                /*  PWCYR_2         */
-    volatile uint16_t PWBFR_2A;                               /*  PWBFR_2A        */
-    volatile uint16_t PWBFR_2C;                               /*  PWBFR_2C        */
-    volatile uint16_t PWBFR_2E;                               /*  PWBFR_2E        */
-    volatile uint16_t PWBFR_2G;                               /*  PWBFR_2G        */
-/* end of struct st_pwm_common */
-};
-
-
-struct st_pwm_common
-{
-    union reg16_8_t  PWCR_1;                          /*  PWCR_1      */
-    
-    volatile uint8_t   dummy572[2];                            /*                  */
-    union reg16_8_t  PWPR_1;                          /*  PWPR_1      */
-    
-    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
-    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
-    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
-    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
-    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
-};
-
-
 #define PWM     (*(struct st_pwm     *)0xFCFF5004uL) /* PWM */
 
 
-/* Start of channnel array defines of PWM */
+/* Start of channel array defines of PWM */
 
-/* Channnel array defines of PWMn */
-/*(Sample) value = PWMn[ channel ]->PWCR_1.UINT16; */
-#define PWMn_COUNT  2
+/* Channel array defines of PWMn */
+/*(Sample) value = PWMn[ channel ]->PWCR_1; */
+#define PWMn_COUNT  (2)
 #define PWMn_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &PWM1, &PWM2 \
@@ -102,34 +48,88 @@
 #define PWM1    (*(struct st_pwm_common *)&PWM.PWCR_1)           /* PWM1 */
 #define PWM2    (*(struct st_pwm_common *)&PWM.PWCR_2)           /* PWM2 */
 
-/* End of channnel array defines of PWM */
+/* End of channel array defines of PWM */
+
+
+#define PWMPWBTCR (PWM.PWBTCR)
+#define PWMPWCR_1 (PWM.PWCR_1)
+#define PWMPWPR_1 (PWM.PWPR_1)
+#define PWMPWCYR_1 (PWM.PWCYR_1)
+#define PWMPWBFR_1A (PWM.PWBFR_1A)
+#define PWMPWBFR_1C (PWM.PWBFR_1C)
+#define PWMPWBFR_1E (PWM.PWBFR_1E)
+#define PWMPWBFR_1G (PWM.PWBFR_1G)
+#define PWMPWCR_2 (PWM.PWCR_2)
+#define PWMPWPR_2 (PWM.PWPR_2)
+#define PWMPWCYR_2 (PWM.PWCYR_2)
+#define PWMPWBFR_2A (PWM.PWBFR_2A)
+#define PWMPWBFR_2C (PWM.PWBFR_2C)
+#define PWMPWBFR_2E (PWM.PWBFR_2E)
+#define PWMPWBFR_2G (PWM.PWBFR_2G)
 
 
-#define PWMPWBTCR PWM.PWBTCR.UINT16
-#define PWMPWBTCR_BYTE_L PWM.PWBTCR.UINT8[0]
-#define PWMPWBTCR_BYTE_H PWM.PWBTCR.UINT8[1]
-#define PWMPWCR_1 PWM.PWCR_1.UINT16
-#define PWMPWCR_1_BYTE_L PWM.PWCR_1.UINT8[0]
-#define PWMPWCR_1_BYTE_H PWM.PWCR_1.UINT8[1]
-#define PWMPWPR_1 PWM.PWPR_1.UINT16
-#define PWMPWPR_1_BYTE_L PWM.PWPR_1.UINT8[0]
-#define PWMPWPR_1_BYTE_H PWM.PWPR_1.UINT8[1]
-#define PWMPWCYR_1 PWM.PWCYR_1
-#define PWMPWBFR_1A PWM.PWBFR_1A
-#define PWMPWBFR_1C PWM.PWBFR_1C
-#define PWMPWBFR_1E PWM.PWBFR_1E
-#define PWMPWBFR_1G PWM.PWBFR_1G
-#define PWMPWCR_2 PWM.PWCR_2.UINT16
-#define PWMPWCR_2_BYTE_L PWM.PWCR_2.UINT8[0]
-#define PWMPWCR_2_BYTE_H PWM.PWCR_2.UINT8[1]
-#define PWMPWPR_2 PWM.PWPR_2.UINT16
-#define PWMPWPR_2_BYTE_L PWM.PWPR_2.UINT8[0]
-#define PWMPWPR_2_BYTE_H PWM.PWPR_2.UINT8[1]
-#define PWMPWCYR_2 PWM.PWCYR_2
-#define PWMPWBFR_2A PWM.PWBFR_2A
-#define PWMPWBFR_2C PWM.PWBFR_2C
-#define PWMPWBFR_2E PWM.PWBFR_2E
-#define PWMPWBFR_2G PWM.PWBFR_2G
+typedef struct st_pwm
+{
+                                                           /* PWM              */
+    volatile uint8_t   dummy559[2];                            /*                  */
+    volatile uint8_t   PWBTCR;                                 /*  PWBTCR          */
+    volatile uint8_t   dummy560[217];                          /*                  */
+
+/* start of struct st_pwm_common */
+    volatile uint8_t   PWCR_1;                                 /*  PWCR_1          */
+    volatile uint8_t   dummy561[3];                            /*                  */
+    volatile uint8_t   PWPR_1;                                 /*  PWPR_1          */
+    volatile uint8_t   dummy562[1];                            /*                  */
+    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
+    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
+    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
+    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
+    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
+
+/* end of struct st_pwm_common */
+
+/* start of struct st_pwm_common */
+    volatile uint8_t   PWCR_2;                                 /*  PWCR_2          */
+    volatile uint8_t   dummy563[3];                            /*                  */
+    volatile uint8_t   PWPR_2;                                 /*  PWPR_2          */
+    volatile uint8_t   dummy564[1];                            /*                  */
+    volatile uint16_t PWCYR_2;                                /*  PWCYR_2         */
+    volatile uint16_t PWBFR_2A;                               /*  PWBFR_2A        */
+    volatile uint16_t PWBFR_2C;                               /*  PWBFR_2C        */
+    volatile uint16_t PWBFR_2E;                               /*  PWBFR_2E        */
+    volatile uint16_t PWBFR_2G;                               /*  PWBFR_2G        */
+
+/* end of struct st_pwm_common */
+} r_io_pwm_t;
+
+
+typedef struct st_pwm_common
+{
+ 
+    volatile uint8_t   PWCR_1;                                 /*  PWCR_1          */
+    volatile uint8_t   dummy562[3];                            /*                  */
+    volatile uint8_t   PWPR_1;                                 /*  PWPR_1          */
+    volatile uint8_t   dummy563[1];                            /*                  */
+    volatile uint16_t PWCYR_1;                                /*  PWCYR_1         */
+    volatile uint16_t PWBFR_1A;                               /*  PWBFR_1A        */
+    volatile uint16_t PWBFR_1C;                               /*  PWBFR_1C        */
+    volatile uint16_t PWBFR_1E;                               /*  PWBFR_1E        */
+    volatile uint16_t PWBFR_1G;                               /*  PWBFR_1G        */
+} r_io_pwm_common_t;
+
+
+/* Channel array defines of PWMn (2)*/
+#ifdef  DECLARE_PWMn_CHANNELS
+volatile struct st_pwm_common*  PWMn[ PWMn_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    PWMn_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_PWMn_CHANNELS */
+/* End of channel array defines of PWMn (2)*/
+
+
 /* <-SEC M1.10.1 */
 /* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/riic_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,45 +18,20 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : riic_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef RIIC_IODEFINE_H
 #define RIIC_IODEFINE_H
-
-#include "reg32_t.h"
-
-struct st_riic
-{                                                          /* RIIC             */
-#define RIICnCRm_COUNT 2
-    union reg32_t  RIICnCR1;                      /*  RIICnCR1        */
-    union reg32_t  RIICnCR2;                      /*  RIICnCR2        */
-#define RIICnMRm_COUNT 3
-    union reg32_t  RIICnMR1;                      /*  RIICnMR1        */
-    union reg32_t  RIICnMR2;                      /*  RIICnMR2        */
-    union reg32_t  RIICnMR3;                      /*  RIICnMR3        */
-    union reg32_t  RIICnFER;                      /*  RIICnFER        */
-    union reg32_t  RIICnSER;                      /*  RIICnSER        */
-    union reg32_t  RIICnIER;                      /*  RIICnIER        */
-#define RIICnSRm_COUNT 2
-    union reg32_t  RIICnSR1;                      /*  RIICnSR1        */
-    union reg32_t  RIICnSR2;                      /*  RIICnSR2        */
-#define RIICnSARm_COUNT 3
-    union reg32_t  RIICnSAR0;                     /*  RIICnSAR0       */
-    union reg32_t  RIICnSAR1;                     /*  RIICnSAR1       */
-    union reg32_t  RIICnSAR2;                     /*  RIICnSAR2       */
-    union reg32_t  RIICnBRL;                      /*  RIICnBRL        */
-    union reg32_t  RIICnBRH;                      /*  RIICnBRH        */
-    union reg32_t  RIICnDRT;                      /*  RIICnDRT        */
-    union reg32_t  RIICnDRR;                      /*  RIICnDRR        */
-    
-};
-
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
 #define RIIC0   (*(struct st_riic    *)0xFCFEE000uL) /* RIIC0 */
 #define RIIC1   (*(struct st_riic    *)0xFCFEE400uL) /* RIIC1 */
@@ -64,493 +39,546 @@
 #define RIIC3   (*(struct st_riic    *)0xFCFEEC00uL) /* RIIC3 */
 
 
-/* Start of channnel array defines of RIIC */
+/* Start of channel array defines of RIIC */
 
-/* Channnel array defines of RIIC */
+/* Channel array defines of RIIC */
 /*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */
-#define RIIC_COUNT  4
+#define RIIC_COUNT  (4)
 #define RIIC_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RIIC0, &RIIC1, &RIIC2, &RIIC3 \
 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
 
-/* End of channnel array defines of RIIC */
+/* End of channel array defines of RIIC */
 
 
-#define RIIC0CR1 RIIC0.RIICnCR1.UINT32
-#define RIIC0CR1L RIIC0.RIICnCR1.UINT16[L]
-#define RIIC0CR1LL RIIC0.RIICnCR1.UINT8[LL]
-#define RIIC0CR1LH RIIC0.RIICnCR1.UINT8[LH]
-#define RIIC0CR1H RIIC0.RIICnCR1.UINT16[H]
-#define RIIC0CR1HL RIIC0.RIICnCR1.UINT8[HL]
-#define RIIC0CR1HH RIIC0.RIICnCR1.UINT8[HH]
-#define RIIC0CR2 RIIC0.RIICnCR2.UINT32
-#define RIIC0CR2L RIIC0.RIICnCR2.UINT16[L]
-#define RIIC0CR2LL RIIC0.RIICnCR2.UINT8[LL]
-#define RIIC0CR2LH RIIC0.RIICnCR2.UINT8[LH]
-#define RIIC0CR2H RIIC0.RIICnCR2.UINT16[H]
-#define RIIC0CR2HL RIIC0.RIICnCR2.UINT8[HL]
-#define RIIC0CR2HH RIIC0.RIICnCR2.UINT8[HH]
-#define RIIC0MR1 RIIC0.RIICnMR1.UINT32
-#define RIIC0MR1L RIIC0.RIICnMR1.UINT16[L]
-#define RIIC0MR1LL RIIC0.RIICnMR1.UINT8[LL]
-#define RIIC0MR1LH RIIC0.RIICnMR1.UINT8[LH]
-#define RIIC0MR1H RIIC0.RIICnMR1.UINT16[H]
-#define RIIC0MR1HL RIIC0.RIICnMR1.UINT8[HL]
-#define RIIC0MR1HH RIIC0.RIICnMR1.UINT8[HH]
-#define RIIC0MR2 RIIC0.RIICnMR2.UINT32
-#define RIIC0MR2L RIIC0.RIICnMR2.UINT16[L]
-#define RIIC0MR2LL RIIC0.RIICnMR2.UINT8[LL]
-#define RIIC0MR2LH RIIC0.RIICnMR2.UINT8[LH]
-#define RIIC0MR2H RIIC0.RIICnMR2.UINT16[H]
-#define RIIC0MR2HL RIIC0.RIICnMR2.UINT8[HL]
-#define RIIC0MR2HH RIIC0.RIICnMR2.UINT8[HH]
-#define RIIC0MR3 RIIC0.RIICnMR3.UINT32
-#define RIIC0MR3L RIIC0.RIICnMR3.UINT16[L]
-#define RIIC0MR3LL RIIC0.RIICnMR3.UINT8[LL]
-#define RIIC0MR3LH RIIC0.RIICnMR3.UINT8[LH]
-#define RIIC0MR3H RIIC0.RIICnMR3.UINT16[H]
-#define RIIC0MR3HL RIIC0.RIICnMR3.UINT8[HL]
-#define RIIC0MR3HH RIIC0.RIICnMR3.UINT8[HH]
-#define RIIC0FER RIIC0.RIICnFER.UINT32
-#define RIIC0FERL RIIC0.RIICnFER.UINT16[L]
-#define RIIC0FERLL RIIC0.RIICnFER.UINT8[LL]
-#define RIIC0FERLH RIIC0.RIICnFER.UINT8[LH]
-#define RIIC0FERH RIIC0.RIICnFER.UINT16[H]
-#define RIIC0FERHL RIIC0.RIICnFER.UINT8[HL]
-#define RIIC0FERHH RIIC0.RIICnFER.UINT8[HH]
-#define RIIC0SER RIIC0.RIICnSER.UINT32
-#define RIIC0SERL RIIC0.RIICnSER.UINT16[L]
-#define RIIC0SERLL RIIC0.RIICnSER.UINT8[LL]
-#define RIIC0SERLH RIIC0.RIICnSER.UINT8[LH]
-#define RIIC0SERH RIIC0.RIICnSER.UINT16[H]
-#define RIIC0SERHL RIIC0.RIICnSER.UINT8[HL]
-#define RIIC0SERHH RIIC0.RIICnSER.UINT8[HH]
-#define RIIC0IER RIIC0.RIICnIER.UINT32
-#define RIIC0IERL RIIC0.RIICnIER.UINT16[L]
-#define RIIC0IERLL RIIC0.RIICnIER.UINT8[LL]
-#define RIIC0IERLH RIIC0.RIICnIER.UINT8[LH]
-#define RIIC0IERH RIIC0.RIICnIER.UINT16[H]
-#define RIIC0IERHL RIIC0.RIICnIER.UINT8[HL]
-#define RIIC0IERHH RIIC0.RIICnIER.UINT8[HH]
-#define RIIC0SR1 RIIC0.RIICnSR1.UINT32
-#define RIIC0SR1L RIIC0.RIICnSR1.UINT16[L]
-#define RIIC0SR1LL RIIC0.RIICnSR1.UINT8[LL]
-#define RIIC0SR1LH RIIC0.RIICnSR1.UINT8[LH]
-#define RIIC0SR1H RIIC0.RIICnSR1.UINT16[H]
-#define RIIC0SR1HL RIIC0.RIICnSR1.UINT8[HL]
-#define RIIC0SR1HH RIIC0.RIICnSR1.UINT8[HH]
-#define RIIC0SR2 RIIC0.RIICnSR2.UINT32
-#define RIIC0SR2L RIIC0.RIICnSR2.UINT16[L]
-#define RIIC0SR2LL RIIC0.RIICnSR2.UINT8[LL]
-#define RIIC0SR2LH RIIC0.RIICnSR2.UINT8[LH]
-#define RIIC0SR2H RIIC0.RIICnSR2.UINT16[H]
-#define RIIC0SR2HL RIIC0.RIICnSR2.UINT8[HL]
-#define RIIC0SR2HH RIIC0.RIICnSR2.UINT8[HH]
-#define RIIC0SAR0 RIIC0.RIICnSAR0.UINT32
-#define RIIC0SAR0L RIIC0.RIICnSAR0.UINT16[L]
-#define RIIC0SAR0LL RIIC0.RIICnSAR0.UINT8[LL]
-#define RIIC0SAR0LH RIIC0.RIICnSAR0.UINT8[LH]
-#define RIIC0SAR0H RIIC0.RIICnSAR0.UINT16[H]
-#define RIIC0SAR0HL RIIC0.RIICnSAR0.UINT8[HL]
-#define RIIC0SAR0HH RIIC0.RIICnSAR0.UINT8[HH]
-#define RIIC0SAR1 RIIC0.RIICnSAR1.UINT32
-#define RIIC0SAR1L RIIC0.RIICnSAR1.UINT16[L]
-#define RIIC0SAR1LL RIIC0.RIICnSAR1.UINT8[LL]
-#define RIIC0SAR1LH RIIC0.RIICnSAR1.UINT8[LH]
-#define RIIC0SAR1H RIIC0.RIICnSAR1.UINT16[H]
-#define RIIC0SAR1HL RIIC0.RIICnSAR1.UINT8[HL]
-#define RIIC0SAR1HH RIIC0.RIICnSAR1.UINT8[HH]
-#define RIIC0SAR2 RIIC0.RIICnSAR2.UINT32
-#define RIIC0SAR2L RIIC0.RIICnSAR2.UINT16[L]
-#define RIIC0SAR2LL RIIC0.RIICnSAR2.UINT8[LL]
-#define RIIC0SAR2LH RIIC0.RIICnSAR2.UINT8[LH]
-#define RIIC0SAR2H RIIC0.RIICnSAR2.UINT16[H]
-#define RIIC0SAR2HL RIIC0.RIICnSAR2.UINT8[HL]
-#define RIIC0SAR2HH RIIC0.RIICnSAR2.UINT8[HH]
-#define RIIC0BRL RIIC0.RIICnBRL.UINT32
-#define RIIC0BRLL RIIC0.RIICnBRL.UINT16[L]
-#define RIIC0BRLLL RIIC0.RIICnBRL.UINT8[LL]
-#define RIIC0BRLLH RIIC0.RIICnBRL.UINT8[LH]
-#define RIIC0BRLH RIIC0.RIICnBRL.UINT16[H]
-#define RIIC0BRLHL RIIC0.RIICnBRL.UINT8[HL]
-#define RIIC0BRLHH RIIC0.RIICnBRL.UINT8[HH]
-#define RIIC0BRH RIIC0.RIICnBRH.UINT32
-#define RIIC0BRHL RIIC0.RIICnBRH.UINT16[L]
-#define RIIC0BRHLL RIIC0.RIICnBRH.UINT8[LL]
-#define RIIC0BRHLH RIIC0.RIICnBRH.UINT8[LH]
-#define RIIC0BRHH RIIC0.RIICnBRH.UINT16[H]
-#define RIIC0BRHHL RIIC0.RIICnBRH.UINT8[HL]
-#define RIIC0BRHHH RIIC0.RIICnBRH.UINT8[HH]
-#define RIIC0DRT RIIC0.RIICnDRT.UINT32
-#define RIIC0DRTL RIIC0.RIICnDRT.UINT16[L]
-#define RIIC0DRTLL RIIC0.RIICnDRT.UINT8[LL]
-#define RIIC0DRTLH RIIC0.RIICnDRT.UINT8[LH]
-#define RIIC0DRTH RIIC0.RIICnDRT.UINT16[H]
-#define RIIC0DRTHL RIIC0.RIICnDRT.UINT8[HL]
-#define RIIC0DRTHH RIIC0.RIICnDRT.UINT8[HH]
-#define RIIC0DRR RIIC0.RIICnDRR.UINT32
-#define RIIC0DRRL RIIC0.RIICnDRR.UINT16[L]
-#define RIIC0DRRLL RIIC0.RIICnDRR.UINT8[LL]
-#define RIIC0DRRLH RIIC0.RIICnDRR.UINT8[LH]
-#define RIIC0DRRH RIIC0.RIICnDRR.UINT16[H]
-#define RIIC0DRRHL RIIC0.RIICnDRR.UINT8[HL]
-#define RIIC0DRRHH RIIC0.RIICnDRR.UINT8[HH]
-#define RIIC1CR1 RIIC1.RIICnCR1.UINT32
-#define RIIC1CR1L RIIC1.RIICnCR1.UINT16[L]
-#define RIIC1CR1LL RIIC1.RIICnCR1.UINT8[LL]
-#define RIIC1CR1LH RIIC1.RIICnCR1.UINT8[LH]
-#define RIIC1CR1H RIIC1.RIICnCR1.UINT16[H]
-#define RIIC1CR1HL RIIC1.RIICnCR1.UINT8[HL]
-#define RIIC1CR1HH RIIC1.RIICnCR1.UINT8[HH]
-#define RIIC1CR2 RIIC1.RIICnCR2.UINT32
-#define RIIC1CR2L RIIC1.RIICnCR2.UINT16[L]
-#define RIIC1CR2LL RIIC1.RIICnCR2.UINT8[LL]
-#define RIIC1CR2LH RIIC1.RIICnCR2.UINT8[LH]
-#define RIIC1CR2H RIIC1.RIICnCR2.UINT16[H]
-#define RIIC1CR2HL RIIC1.RIICnCR2.UINT8[HL]
-#define RIIC1CR2HH RIIC1.RIICnCR2.UINT8[HH]
-#define RIIC1MR1 RIIC1.RIICnMR1.UINT32
-#define RIIC1MR1L RIIC1.RIICnMR1.UINT16[L]
-#define RIIC1MR1LL RIIC1.RIICnMR1.UINT8[LL]
-#define RIIC1MR1LH RIIC1.RIICnMR1.UINT8[LH]
-#define RIIC1MR1H RIIC1.RIICnMR1.UINT16[H]
-#define RIIC1MR1HL RIIC1.RIICnMR1.UINT8[HL]
-#define RIIC1MR1HH RIIC1.RIICnMR1.UINT8[HH]
-#define RIIC1MR2 RIIC1.RIICnMR2.UINT32
-#define RIIC1MR2L RIIC1.RIICnMR2.UINT16[L]
-#define RIIC1MR2LL RIIC1.RIICnMR2.UINT8[LL]
-#define RIIC1MR2LH RIIC1.RIICnMR2.UINT8[LH]
-#define RIIC1MR2H RIIC1.RIICnMR2.UINT16[H]
-#define RIIC1MR2HL RIIC1.RIICnMR2.UINT8[HL]
-#define RIIC1MR2HH RIIC1.RIICnMR2.UINT8[HH]
-#define RIIC1MR3 RIIC1.RIICnMR3.UINT32
-#define RIIC1MR3L RIIC1.RIICnMR3.UINT16[L]
-#define RIIC1MR3LL RIIC1.RIICnMR3.UINT8[LL]
-#define RIIC1MR3LH RIIC1.RIICnMR3.UINT8[LH]
-#define RIIC1MR3H RIIC1.RIICnMR3.UINT16[H]
-#define RIIC1MR3HL RIIC1.RIICnMR3.UINT8[HL]
-#define RIIC1MR3HH RIIC1.RIICnMR3.UINT8[HH]
-#define RIIC1FER RIIC1.RIICnFER.UINT32
-#define RIIC1FERL RIIC1.RIICnFER.UINT16[L]
-#define RIIC1FERLL RIIC1.RIICnFER.UINT8[LL]
-#define RIIC1FERLH RIIC1.RIICnFER.UINT8[LH]
-#define RIIC1FERH RIIC1.RIICnFER.UINT16[H]
-#define RIIC1FERHL RIIC1.RIICnFER.UINT8[HL]
-#define RIIC1FERHH RIIC1.RIICnFER.UINT8[HH]
-#define RIIC1SER RIIC1.RIICnSER.UINT32
-#define RIIC1SERL RIIC1.RIICnSER.UINT16[L]
-#define RIIC1SERLL RIIC1.RIICnSER.UINT8[LL]
-#define RIIC1SERLH RIIC1.RIICnSER.UINT8[LH]
-#define RIIC1SERH RIIC1.RIICnSER.UINT16[H]
-#define RIIC1SERHL RIIC1.RIICnSER.UINT8[HL]
-#define RIIC1SERHH RIIC1.RIICnSER.UINT8[HH]
-#define RIIC1IER RIIC1.RIICnIER.UINT32
-#define RIIC1IERL RIIC1.RIICnIER.UINT16[L]
-#define RIIC1IERLL RIIC1.RIICnIER.UINT8[LL]
-#define RIIC1IERLH RIIC1.RIICnIER.UINT8[LH]
-#define RIIC1IERH RIIC1.RIICnIER.UINT16[H]
-#define RIIC1IERHL RIIC1.RIICnIER.UINT8[HL]
-#define RIIC1IERHH RIIC1.RIICnIER.UINT8[HH]
-#define RIIC1SR1 RIIC1.RIICnSR1.UINT32
-#define RIIC1SR1L RIIC1.RIICnSR1.UINT16[L]
-#define RIIC1SR1LL RIIC1.RIICnSR1.UINT8[LL]
-#define RIIC1SR1LH RIIC1.RIICnSR1.UINT8[LH]
-#define RIIC1SR1H RIIC1.RIICnSR1.UINT16[H]
-#define RIIC1SR1HL RIIC1.RIICnSR1.UINT8[HL]
-#define RIIC1SR1HH RIIC1.RIICnSR1.UINT8[HH]
-#define RIIC1SR2 RIIC1.RIICnSR2.UINT32
-#define RIIC1SR2L RIIC1.RIICnSR2.UINT16[L]
-#define RIIC1SR2LL RIIC1.RIICnSR2.UINT8[LL]
-#define RIIC1SR2LH RIIC1.RIICnSR2.UINT8[LH]
-#define RIIC1SR2H RIIC1.RIICnSR2.UINT16[H]
-#define RIIC1SR2HL RIIC1.RIICnSR2.UINT8[HL]
-#define RIIC1SR2HH RIIC1.RIICnSR2.UINT8[HH]
-#define RIIC1SAR0 RIIC1.RIICnSAR0.UINT32
-#define RIIC1SAR0L RIIC1.RIICnSAR0.UINT16[L]
-#define RIIC1SAR0LL RIIC1.RIICnSAR0.UINT8[LL]
-#define RIIC1SAR0LH RIIC1.RIICnSAR0.UINT8[LH]
-#define RIIC1SAR0H RIIC1.RIICnSAR0.UINT16[H]
-#define RIIC1SAR0HL RIIC1.RIICnSAR0.UINT8[HL]
-#define RIIC1SAR0HH RIIC1.RIICnSAR0.UINT8[HH]
-#define RIIC1SAR1 RIIC1.RIICnSAR1.UINT32
-#define RIIC1SAR1L RIIC1.RIICnSAR1.UINT16[L]
-#define RIIC1SAR1LL RIIC1.RIICnSAR1.UINT8[LL]
-#define RIIC1SAR1LH RIIC1.RIICnSAR1.UINT8[LH]
-#define RIIC1SAR1H RIIC1.RIICnSAR1.UINT16[H]
-#define RIIC1SAR1HL RIIC1.RIICnSAR1.UINT8[HL]
-#define RIIC1SAR1HH RIIC1.RIICnSAR1.UINT8[HH]
-#define RIIC1SAR2 RIIC1.RIICnSAR2.UINT32
-#define RIIC1SAR2L RIIC1.RIICnSAR2.UINT16[L]
-#define RIIC1SAR2LL RIIC1.RIICnSAR2.UINT8[LL]
-#define RIIC1SAR2LH RIIC1.RIICnSAR2.UINT8[LH]
-#define RIIC1SAR2H RIIC1.RIICnSAR2.UINT16[H]
-#define RIIC1SAR2HL RIIC1.RIICnSAR2.UINT8[HL]
-#define RIIC1SAR2HH RIIC1.RIICnSAR2.UINT8[HH]
-#define RIIC1BRL RIIC1.RIICnBRL.UINT32
-#define RIIC1BRLL RIIC1.RIICnBRL.UINT16[L]
-#define RIIC1BRLLL RIIC1.RIICnBRL.UINT8[LL]
-#define RIIC1BRLLH RIIC1.RIICnBRL.UINT8[LH]
-#define RIIC1BRLH RIIC1.RIICnBRL.UINT16[H]
-#define RIIC1BRLHL RIIC1.RIICnBRL.UINT8[HL]
-#define RIIC1BRLHH RIIC1.RIICnBRL.UINT8[HH]
-#define RIIC1BRH RIIC1.RIICnBRH.UINT32
-#define RIIC1BRHL RIIC1.RIICnBRH.UINT16[L]
-#define RIIC1BRHLL RIIC1.RIICnBRH.UINT8[LL]
-#define RIIC1BRHLH RIIC1.RIICnBRH.UINT8[LH]
-#define RIIC1BRHH RIIC1.RIICnBRH.UINT16[H]
-#define RIIC1BRHHL RIIC1.RIICnBRH.UINT8[HL]
-#define RIIC1BRHHH RIIC1.RIICnBRH.UINT8[HH]
-#define RIIC1DRT RIIC1.RIICnDRT.UINT32
-#define RIIC1DRTL RIIC1.RIICnDRT.UINT16[L]
-#define RIIC1DRTLL RIIC1.RIICnDRT.UINT8[LL]
-#define RIIC1DRTLH RIIC1.RIICnDRT.UINT8[LH]
-#define RIIC1DRTH RIIC1.RIICnDRT.UINT16[H]
-#define RIIC1DRTHL RIIC1.RIICnDRT.UINT8[HL]
-#define RIIC1DRTHH RIIC1.RIICnDRT.UINT8[HH]
-#define RIIC1DRR RIIC1.RIICnDRR.UINT32
-#define RIIC1DRRL RIIC1.RIICnDRR.UINT16[L]
-#define RIIC1DRRLL RIIC1.RIICnDRR.UINT8[LL]
-#define RIIC1DRRLH RIIC1.RIICnDRR.UINT8[LH]
-#define RIIC1DRRH RIIC1.RIICnDRR.UINT16[H]
-#define RIIC1DRRHL RIIC1.RIICnDRR.UINT8[HL]
-#define RIIC1DRRHH RIIC1.RIICnDRR.UINT8[HH]
-#define RIIC2CR1 RIIC2.RIICnCR1.UINT32
-#define RIIC2CR1L RIIC2.RIICnCR1.UINT16[L]
-#define RIIC2CR1LL RIIC2.RIICnCR1.UINT8[LL]
-#define RIIC2CR1LH RIIC2.RIICnCR1.UINT8[LH]
-#define RIIC2CR1H RIIC2.RIICnCR1.UINT16[H]
-#define RIIC2CR1HL RIIC2.RIICnCR1.UINT8[HL]
-#define RIIC2CR1HH RIIC2.RIICnCR1.UINT8[HH]
-#define RIIC2CR2 RIIC2.RIICnCR2.UINT32
-#define RIIC2CR2L RIIC2.RIICnCR2.UINT16[L]
-#define RIIC2CR2LL RIIC2.RIICnCR2.UINT8[LL]
-#define RIIC2CR2LH RIIC2.RIICnCR2.UINT8[LH]
-#define RIIC2CR2H RIIC2.RIICnCR2.UINT16[H]
-#define RIIC2CR2HL RIIC2.RIICnCR2.UINT8[HL]
-#define RIIC2CR2HH RIIC2.RIICnCR2.UINT8[HH]
-#define RIIC2MR1 RIIC2.RIICnMR1.UINT32
-#define RIIC2MR1L RIIC2.RIICnMR1.UINT16[L]
-#define RIIC2MR1LL RIIC2.RIICnMR1.UINT8[LL]
-#define RIIC2MR1LH RIIC2.RIICnMR1.UINT8[LH]
-#define RIIC2MR1H RIIC2.RIICnMR1.UINT16[H]
-#define RIIC2MR1HL RIIC2.RIICnMR1.UINT8[HL]
-#define RIIC2MR1HH RIIC2.RIICnMR1.UINT8[HH]
-#define RIIC2MR2 RIIC2.RIICnMR2.UINT32
-#define RIIC2MR2L RIIC2.RIICnMR2.UINT16[L]
-#define RIIC2MR2LL RIIC2.RIICnMR2.UINT8[LL]
-#define RIIC2MR2LH RIIC2.RIICnMR2.UINT8[LH]
-#define RIIC2MR2H RIIC2.RIICnMR2.UINT16[H]
-#define RIIC2MR2HL RIIC2.RIICnMR2.UINT8[HL]
-#define RIIC2MR2HH RIIC2.RIICnMR2.UINT8[HH]
-#define RIIC2MR3 RIIC2.RIICnMR3.UINT32
-#define RIIC2MR3L RIIC2.RIICnMR3.UINT16[L]
-#define RIIC2MR3LL RIIC2.RIICnMR3.UINT8[LL]
-#define RIIC2MR3LH RIIC2.RIICnMR3.UINT8[LH]
-#define RIIC2MR3H RIIC2.RIICnMR3.UINT16[H]
-#define RIIC2MR3HL RIIC2.RIICnMR3.UINT8[HL]
-#define RIIC2MR3HH RIIC2.RIICnMR3.UINT8[HH]
-#define RIIC2FER RIIC2.RIICnFER.UINT32
-#define RIIC2FERL RIIC2.RIICnFER.UINT16[L]
-#define RIIC2FERLL RIIC2.RIICnFER.UINT8[LL]
-#define RIIC2FERLH RIIC2.RIICnFER.UINT8[LH]
-#define RIIC2FERH RIIC2.RIICnFER.UINT16[H]
-#define RIIC2FERHL RIIC2.RIICnFER.UINT8[HL]
-#define RIIC2FERHH RIIC2.RIICnFER.UINT8[HH]
-#define RIIC2SER RIIC2.RIICnSER.UINT32
-#define RIIC2SERL RIIC2.RIICnSER.UINT16[L]
-#define RIIC2SERLL RIIC2.RIICnSER.UINT8[LL]
-#define RIIC2SERLH RIIC2.RIICnSER.UINT8[LH]
-#define RIIC2SERH RIIC2.RIICnSER.UINT16[H]
-#define RIIC2SERHL RIIC2.RIICnSER.UINT8[HL]
-#define RIIC2SERHH RIIC2.RIICnSER.UINT8[HH]
-#define RIIC2IER RIIC2.RIICnIER.UINT32
-#define RIIC2IERL RIIC2.RIICnIER.UINT16[L]
-#define RIIC2IERLL RIIC2.RIICnIER.UINT8[LL]
-#define RIIC2IERLH RIIC2.RIICnIER.UINT8[LH]
-#define RIIC2IERH RIIC2.RIICnIER.UINT16[H]
-#define RIIC2IERHL RIIC2.RIICnIER.UINT8[HL]
-#define RIIC2IERHH RIIC2.RIICnIER.UINT8[HH]
-#define RIIC2SR1 RIIC2.RIICnSR1.UINT32
-#define RIIC2SR1L RIIC2.RIICnSR1.UINT16[L]
-#define RIIC2SR1LL RIIC2.RIICnSR1.UINT8[LL]
-#define RIIC2SR1LH RIIC2.RIICnSR1.UINT8[LH]
-#define RIIC2SR1H RIIC2.RIICnSR1.UINT16[H]
-#define RIIC2SR1HL RIIC2.RIICnSR1.UINT8[HL]
-#define RIIC2SR1HH RIIC2.RIICnSR1.UINT8[HH]
-#define RIIC2SR2 RIIC2.RIICnSR2.UINT32
-#define RIIC2SR2L RIIC2.RIICnSR2.UINT16[L]
-#define RIIC2SR2LL RIIC2.RIICnSR2.UINT8[LL]
-#define RIIC2SR2LH RIIC2.RIICnSR2.UINT8[LH]
-#define RIIC2SR2H RIIC2.RIICnSR2.UINT16[H]
-#define RIIC2SR2HL RIIC2.RIICnSR2.UINT8[HL]
-#define RIIC2SR2HH RIIC2.RIICnSR2.UINT8[HH]
-#define RIIC2SAR0 RIIC2.RIICnSAR0.UINT32
-#define RIIC2SAR0L RIIC2.RIICnSAR0.UINT16[L]
-#define RIIC2SAR0LL RIIC2.RIICnSAR0.UINT8[LL]
-#define RIIC2SAR0LH RIIC2.RIICnSAR0.UINT8[LH]
-#define RIIC2SAR0H RIIC2.RIICnSAR0.UINT16[H]
-#define RIIC2SAR0HL RIIC2.RIICnSAR0.UINT8[HL]
-#define RIIC2SAR0HH RIIC2.RIICnSAR0.UINT8[HH]
-#define RIIC2SAR1 RIIC2.RIICnSAR1.UINT32
-#define RIIC2SAR1L RIIC2.RIICnSAR1.UINT16[L]
-#define RIIC2SAR1LL RIIC2.RIICnSAR1.UINT8[LL]
-#define RIIC2SAR1LH RIIC2.RIICnSAR1.UINT8[LH]
-#define RIIC2SAR1H RIIC2.RIICnSAR1.UINT16[H]
-#define RIIC2SAR1HL RIIC2.RIICnSAR1.UINT8[HL]
-#define RIIC2SAR1HH RIIC2.RIICnSAR1.UINT8[HH]
-#define RIIC2SAR2 RIIC2.RIICnSAR2.UINT32
-#define RIIC2SAR2L RIIC2.RIICnSAR2.UINT16[L]
-#define RIIC2SAR2LL RIIC2.RIICnSAR2.UINT8[LL]
-#define RIIC2SAR2LH RIIC2.RIICnSAR2.UINT8[LH]
-#define RIIC2SAR2H RIIC2.RIICnSAR2.UINT16[H]
-#define RIIC2SAR2HL RIIC2.RIICnSAR2.UINT8[HL]
-#define RIIC2SAR2HH RIIC2.RIICnSAR2.UINT8[HH]
-#define RIIC2BRL RIIC2.RIICnBRL.UINT32
-#define RIIC2BRLL RIIC2.RIICnBRL.UINT16[L]
-#define RIIC2BRLLL RIIC2.RIICnBRL.UINT8[LL]
-#define RIIC2BRLLH RIIC2.RIICnBRL.UINT8[LH]
-#define RIIC2BRLH RIIC2.RIICnBRL.UINT16[H]
-#define RIIC2BRLHL RIIC2.RIICnBRL.UINT8[HL]
-#define RIIC2BRLHH RIIC2.RIICnBRL.UINT8[HH]
-#define RIIC2BRH RIIC2.RIICnBRH.UINT32
-#define RIIC2BRHL RIIC2.RIICnBRH.UINT16[L]
-#define RIIC2BRHLL RIIC2.RIICnBRH.UINT8[LL]
-#define RIIC2BRHLH RIIC2.RIICnBRH.UINT8[LH]
-#define RIIC2BRHH RIIC2.RIICnBRH.UINT16[H]
-#define RIIC2BRHHL RIIC2.RIICnBRH.UINT8[HL]
-#define RIIC2BRHHH RIIC2.RIICnBRH.UINT8[HH]
-#define RIIC2DRT RIIC2.RIICnDRT.UINT32
-#define RIIC2DRTL RIIC2.RIICnDRT.UINT16[L]
-#define RIIC2DRTLL RIIC2.RIICnDRT.UINT8[LL]
-#define RIIC2DRTLH RIIC2.RIICnDRT.UINT8[LH]
-#define RIIC2DRTH RIIC2.RIICnDRT.UINT16[H]
-#define RIIC2DRTHL RIIC2.RIICnDRT.UINT8[HL]
-#define RIIC2DRTHH RIIC2.RIICnDRT.UINT8[HH]
-#define RIIC2DRR RIIC2.RIICnDRR.UINT32
-#define RIIC2DRRL RIIC2.RIICnDRR.UINT16[L]
-#define RIIC2DRRLL RIIC2.RIICnDRR.UINT8[LL]
-#define RIIC2DRRLH RIIC2.RIICnDRR.UINT8[LH]
-#define RIIC2DRRH RIIC2.RIICnDRR.UINT16[H]
-#define RIIC2DRRHL RIIC2.RIICnDRR.UINT8[HL]
-#define RIIC2DRRHH RIIC2.RIICnDRR.UINT8[HH]
-#define RIIC3CR1 RIIC3.RIICnCR1.UINT32
-#define RIIC3CR1L RIIC3.RIICnCR1.UINT16[L]
-#define RIIC3CR1LL RIIC3.RIICnCR1.UINT8[LL]
-#define RIIC3CR1LH RIIC3.RIICnCR1.UINT8[LH]
-#define RIIC3CR1H RIIC3.RIICnCR1.UINT16[H]
-#define RIIC3CR1HL RIIC3.RIICnCR1.UINT8[HL]
-#define RIIC3CR1HH RIIC3.RIICnCR1.UINT8[HH]
-#define RIIC3CR2 RIIC3.RIICnCR2.UINT32
-#define RIIC3CR2L RIIC3.RIICnCR2.UINT16[L]
-#define RIIC3CR2LL RIIC3.RIICnCR2.UINT8[LL]
-#define RIIC3CR2LH RIIC3.RIICnCR2.UINT8[LH]
-#define RIIC3CR2H RIIC3.RIICnCR2.UINT16[H]
-#define RIIC3CR2HL RIIC3.RIICnCR2.UINT8[HL]
-#define RIIC3CR2HH RIIC3.RIICnCR2.UINT8[HH]
-#define RIIC3MR1 RIIC3.RIICnMR1.UINT32
-#define RIIC3MR1L RIIC3.RIICnMR1.UINT16[L]
-#define RIIC3MR1LL RIIC3.RIICnMR1.UINT8[LL]
-#define RIIC3MR1LH RIIC3.RIICnMR1.UINT8[LH]
-#define RIIC3MR1H RIIC3.RIICnMR1.UINT16[H]
-#define RIIC3MR1HL RIIC3.RIICnMR1.UINT8[HL]
-#define RIIC3MR1HH RIIC3.RIICnMR1.UINT8[HH]
-#define RIIC3MR2 RIIC3.RIICnMR2.UINT32
-#define RIIC3MR2L RIIC3.RIICnMR2.UINT16[L]
-#define RIIC3MR2LL RIIC3.RIICnMR2.UINT8[LL]
-#define RIIC3MR2LH RIIC3.RIICnMR2.UINT8[LH]
-#define RIIC3MR2H RIIC3.RIICnMR2.UINT16[H]
-#define RIIC3MR2HL RIIC3.RIICnMR2.UINT8[HL]
-#define RIIC3MR2HH RIIC3.RIICnMR2.UINT8[HH]
-#define RIIC3MR3 RIIC3.RIICnMR3.UINT32
-#define RIIC3MR3L RIIC3.RIICnMR3.UINT16[L]
-#define RIIC3MR3LL RIIC3.RIICnMR3.UINT8[LL]
-#define RIIC3MR3LH RIIC3.RIICnMR3.UINT8[LH]
-#define RIIC3MR3H RIIC3.RIICnMR3.UINT16[H]
-#define RIIC3MR3HL RIIC3.RIICnMR3.UINT8[HL]
-#define RIIC3MR3HH RIIC3.RIICnMR3.UINT8[HH]
-#define RIIC3FER RIIC3.RIICnFER.UINT32
-#define RIIC3FERL RIIC3.RIICnFER.UINT16[L]
-#define RIIC3FERLL RIIC3.RIICnFER.UINT8[LL]
-#define RIIC3FERLH RIIC3.RIICnFER.UINT8[LH]
-#define RIIC3FERH RIIC3.RIICnFER.UINT16[H]
-#define RIIC3FERHL RIIC3.RIICnFER.UINT8[HL]
-#define RIIC3FERHH RIIC3.RIICnFER.UINT8[HH]
-#define RIIC3SER RIIC3.RIICnSER.UINT32
-#define RIIC3SERL RIIC3.RIICnSER.UINT16[L]
-#define RIIC3SERLL RIIC3.RIICnSER.UINT8[LL]
-#define RIIC3SERLH RIIC3.RIICnSER.UINT8[LH]
-#define RIIC3SERH RIIC3.RIICnSER.UINT16[H]
-#define RIIC3SERHL RIIC3.RIICnSER.UINT8[HL]
-#define RIIC3SERHH RIIC3.RIICnSER.UINT8[HH]
-#define RIIC3IER RIIC3.RIICnIER.UINT32
-#define RIIC3IERL RIIC3.RIICnIER.UINT16[L]
-#define RIIC3IERLL RIIC3.RIICnIER.UINT8[LL]
-#define RIIC3IERLH RIIC3.RIICnIER.UINT8[LH]
-#define RIIC3IERH RIIC3.RIICnIER.UINT16[H]
-#define RIIC3IERHL RIIC3.RIICnIER.UINT8[HL]
-#define RIIC3IERHH RIIC3.RIICnIER.UINT8[HH]
-#define RIIC3SR1 RIIC3.RIICnSR1.UINT32
-#define RIIC3SR1L RIIC3.RIICnSR1.UINT16[L]
-#define RIIC3SR1LL RIIC3.RIICnSR1.UINT8[LL]
-#define RIIC3SR1LH RIIC3.RIICnSR1.UINT8[LH]
-#define RIIC3SR1H RIIC3.RIICnSR1.UINT16[H]
-#define RIIC3SR1HL RIIC3.RIICnSR1.UINT8[HL]
-#define RIIC3SR1HH RIIC3.RIICnSR1.UINT8[HH]
-#define RIIC3SR2 RIIC3.RIICnSR2.UINT32
-#define RIIC3SR2L RIIC3.RIICnSR2.UINT16[L]
-#define RIIC3SR2LL RIIC3.RIICnSR2.UINT8[LL]
-#define RIIC3SR2LH RIIC3.RIICnSR2.UINT8[LH]
-#define RIIC3SR2H RIIC3.RIICnSR2.UINT16[H]
-#define RIIC3SR2HL RIIC3.RIICnSR2.UINT8[HL]
-#define RIIC3SR2HH RIIC3.RIICnSR2.UINT8[HH]
-#define RIIC3SAR0 RIIC3.RIICnSAR0.UINT32
-#define RIIC3SAR0L RIIC3.RIICnSAR0.UINT16[L]
-#define RIIC3SAR0LL RIIC3.RIICnSAR0.UINT8[LL]
-#define RIIC3SAR0LH RIIC3.RIICnSAR0.UINT8[LH]
-#define RIIC3SAR0H RIIC3.RIICnSAR0.UINT16[H]
-#define RIIC3SAR0HL RIIC3.RIICnSAR0.UINT8[HL]
-#define RIIC3SAR0HH RIIC3.RIICnSAR0.UINT8[HH]
-#define RIIC3SAR1 RIIC3.RIICnSAR1.UINT32
-#define RIIC3SAR1L RIIC3.RIICnSAR1.UINT16[L]
-#define RIIC3SAR1LL RIIC3.RIICnSAR1.UINT8[LL]
-#define RIIC3SAR1LH RIIC3.RIICnSAR1.UINT8[LH]
-#define RIIC3SAR1H RIIC3.RIICnSAR1.UINT16[H]
-#define RIIC3SAR1HL RIIC3.RIICnSAR1.UINT8[HL]
-#define RIIC3SAR1HH RIIC3.RIICnSAR1.UINT8[HH]
-#define RIIC3SAR2 RIIC3.RIICnSAR2.UINT32
-#define RIIC3SAR2L RIIC3.RIICnSAR2.UINT16[L]
-#define RIIC3SAR2LL RIIC3.RIICnSAR2.UINT8[LL]
-#define RIIC3SAR2LH RIIC3.RIICnSAR2.UINT8[LH]
-#define RIIC3SAR2H RIIC3.RIICnSAR2.UINT16[H]
-#define RIIC3SAR2HL RIIC3.RIICnSAR2.UINT8[HL]
-#define RIIC3SAR2HH RIIC3.RIICnSAR2.UINT8[HH]
-#define RIIC3BRL RIIC3.RIICnBRL.UINT32
-#define RIIC3BRLL RIIC3.RIICnBRL.UINT16[L]
-#define RIIC3BRLLL RIIC3.RIICnBRL.UINT8[LL]
-#define RIIC3BRLLH RIIC3.RIICnBRL.UINT8[LH]
-#define RIIC3BRLH RIIC3.RIICnBRL.UINT16[H]
-#define RIIC3BRLHL RIIC3.RIICnBRL.UINT8[HL]
-#define RIIC3BRLHH RIIC3.RIICnBRL.UINT8[HH]
-#define RIIC3BRH RIIC3.RIICnBRH.UINT32
-#define RIIC3BRHL RIIC3.RIICnBRH.UINT16[L]
-#define RIIC3BRHLL RIIC3.RIICnBRH.UINT8[LL]
-#define RIIC3BRHLH RIIC3.RIICnBRH.UINT8[LH]
-#define RIIC3BRHH RIIC3.RIICnBRH.UINT16[H]
-#define RIIC3BRHHL RIIC3.RIICnBRH.UINT8[HL]
-#define RIIC3BRHHH RIIC3.RIICnBRH.UINT8[HH]
-#define RIIC3DRT RIIC3.RIICnDRT.UINT32
-#define RIIC3DRTL RIIC3.RIICnDRT.UINT16[L]
-#define RIIC3DRTLL RIIC3.RIICnDRT.UINT8[LL]
-#define RIIC3DRTLH RIIC3.RIICnDRT.UINT8[LH]
-#define RIIC3DRTH RIIC3.RIICnDRT.UINT16[H]
-#define RIIC3DRTHL RIIC3.RIICnDRT.UINT8[HL]
-#define RIIC3DRTHH RIIC3.RIICnDRT.UINT8[HH]
-#define RIIC3DRR RIIC3.RIICnDRR.UINT32
-#define RIIC3DRRL RIIC3.RIICnDRR.UINT16[L]
-#define RIIC3DRRLL RIIC3.RIICnDRR.UINT8[LL]
-#define RIIC3DRRLH RIIC3.RIICnDRR.UINT8[LH]
-#define RIIC3DRRH RIIC3.RIICnDRR.UINT16[H]
-#define RIIC3DRRHL RIIC3.RIICnDRR.UINT8[HL]
-#define RIIC3DRRHH RIIC3.RIICnDRR.UINT8[HH]
+#define RIIC0CR1 (RIIC0.RIICnCR1.UINT32)
+#define RIIC0CR1L (RIIC0.RIICnCR1.UINT16[R_IO_L])
+#define RIIC0CR1LL (RIIC0.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC0CR1LH (RIIC0.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC0CR1H (RIIC0.RIICnCR1.UINT16[R_IO_H])
+#define RIIC0CR1HL (RIIC0.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC0CR1HH (RIIC0.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC0CR2 (RIIC0.RIICnCR2.UINT32)
+#define RIIC0CR2L (RIIC0.RIICnCR2.UINT16[R_IO_L])
+#define RIIC0CR2LL (RIIC0.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC0CR2LH (RIIC0.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC0CR2H (RIIC0.RIICnCR2.UINT16[R_IO_H])
+#define RIIC0CR2HL (RIIC0.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC0CR2HH (RIIC0.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC0MR1 (RIIC0.RIICnMR1.UINT32)
+#define RIIC0MR1L (RIIC0.RIICnMR1.UINT16[R_IO_L])
+#define RIIC0MR1LL (RIIC0.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC0MR1LH (RIIC0.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC0MR1H (RIIC0.RIICnMR1.UINT16[R_IO_H])
+#define RIIC0MR1HL (RIIC0.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC0MR1HH (RIIC0.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC0MR2 (RIIC0.RIICnMR2.UINT32)
+#define RIIC0MR2L (RIIC0.RIICnMR2.UINT16[R_IO_L])
+#define RIIC0MR2LL (RIIC0.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC0MR2LH (RIIC0.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC0MR2H (RIIC0.RIICnMR2.UINT16[R_IO_H])
+#define RIIC0MR2HL (RIIC0.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC0MR2HH (RIIC0.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC0MR3 (RIIC0.RIICnMR3.UINT32)
+#define RIIC0MR3L (RIIC0.RIICnMR3.UINT16[R_IO_L])
+#define RIIC0MR3LL (RIIC0.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC0MR3LH (RIIC0.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC0MR3H (RIIC0.RIICnMR3.UINT16[R_IO_H])
+#define RIIC0MR3HL (RIIC0.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC0MR3HH (RIIC0.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC0FER (RIIC0.RIICnFER.UINT32)
+#define RIIC0FERL (RIIC0.RIICnFER.UINT16[R_IO_L])
+#define RIIC0FERLL (RIIC0.RIICnFER.UINT8[R_IO_LL])
+#define RIIC0FERLH (RIIC0.RIICnFER.UINT8[R_IO_LH])
+#define RIIC0FERH (RIIC0.RIICnFER.UINT16[R_IO_H])
+#define RIIC0FERHL (RIIC0.RIICnFER.UINT8[R_IO_HL])
+#define RIIC0FERHH (RIIC0.RIICnFER.UINT8[R_IO_HH])
+#define RIIC0SER (RIIC0.RIICnSER.UINT32)
+#define RIIC0SERL (RIIC0.RIICnSER.UINT16[R_IO_L])
+#define RIIC0SERLL (RIIC0.RIICnSER.UINT8[R_IO_LL])
+#define RIIC0SERLH (RIIC0.RIICnSER.UINT8[R_IO_LH])
+#define RIIC0SERH (RIIC0.RIICnSER.UINT16[R_IO_H])
+#define RIIC0SERHL (RIIC0.RIICnSER.UINT8[R_IO_HL])
+#define RIIC0SERHH (RIIC0.RIICnSER.UINT8[R_IO_HH])
+#define RIIC0IER (RIIC0.RIICnIER.UINT32)
+#define RIIC0IERL (RIIC0.RIICnIER.UINT16[R_IO_L])
+#define RIIC0IERLL (RIIC0.RIICnIER.UINT8[R_IO_LL])
+#define RIIC0IERLH (RIIC0.RIICnIER.UINT8[R_IO_LH])
+#define RIIC0IERH (RIIC0.RIICnIER.UINT16[R_IO_H])
+#define RIIC0IERHL (RIIC0.RIICnIER.UINT8[R_IO_HL])
+#define RIIC0IERHH (RIIC0.RIICnIER.UINT8[R_IO_HH])
+#define RIIC0SR1 (RIIC0.RIICnSR1.UINT32)
+#define RIIC0SR1L (RIIC0.RIICnSR1.UINT16[R_IO_L])
+#define RIIC0SR1LL (RIIC0.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC0SR1LH (RIIC0.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC0SR1H (RIIC0.RIICnSR1.UINT16[R_IO_H])
+#define RIIC0SR1HL (RIIC0.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC0SR1HH (RIIC0.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC0SR2 (RIIC0.RIICnSR2.UINT32)
+#define RIIC0SR2L (RIIC0.RIICnSR2.UINT16[R_IO_L])
+#define RIIC0SR2LL (RIIC0.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC0SR2LH (RIIC0.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC0SR2H (RIIC0.RIICnSR2.UINT16[R_IO_H])
+#define RIIC0SR2HL (RIIC0.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC0SR2HH (RIIC0.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC0SAR0 (RIIC0.RIICnSAR0.UINT32)
+#define RIIC0SAR0L (RIIC0.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC0SAR0LL (RIIC0.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC0SAR0LH (RIIC0.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC0SAR0H (RIIC0.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC0SAR0HL (RIIC0.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC0SAR0HH (RIIC0.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC0SAR1 (RIIC0.RIICnSAR1.UINT32)
+#define RIIC0SAR1L (RIIC0.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC0SAR1LL (RIIC0.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC0SAR1LH (RIIC0.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC0SAR1H (RIIC0.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC0SAR1HL (RIIC0.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC0SAR1HH (RIIC0.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC0SAR2 (RIIC0.RIICnSAR2.UINT32)
+#define RIIC0SAR2L (RIIC0.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC0SAR2LL (RIIC0.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC0SAR2LH (RIIC0.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC0SAR2H (RIIC0.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC0SAR2HL (RIIC0.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC0SAR2HH (RIIC0.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC0BRL (RIIC0.RIICnBRL.UINT32)
+#define RIIC0BRLL (RIIC0.RIICnBRL.UINT16[R_IO_L])
+#define RIIC0BRLLL (RIIC0.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC0BRLLH (RIIC0.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC0BRLH (RIIC0.RIICnBRL.UINT16[R_IO_H])
+#define RIIC0BRLHL (RIIC0.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC0BRLHH (RIIC0.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC0BRH (RIIC0.RIICnBRH.UINT32)
+#define RIIC0BRHL (RIIC0.RIICnBRH.UINT16[R_IO_L])
+#define RIIC0BRHLL (RIIC0.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC0BRHLH (RIIC0.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC0BRHH (RIIC0.RIICnBRH.UINT16[R_IO_H])
+#define RIIC0BRHHL (RIIC0.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC0BRHHH (RIIC0.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC0DRT (RIIC0.RIICnDRT.UINT32)
+#define RIIC0DRTL (RIIC0.RIICnDRT.UINT16[R_IO_L])
+#define RIIC0DRTLL (RIIC0.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC0DRTLH (RIIC0.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC0DRTH (RIIC0.RIICnDRT.UINT16[R_IO_H])
+#define RIIC0DRTHL (RIIC0.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC0DRTHH (RIIC0.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC0DRR (RIIC0.RIICnDRR.UINT32)
+#define RIIC0DRRL (RIIC0.RIICnDRR.UINT16[R_IO_L])
+#define RIIC0DRRLL (RIIC0.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC0DRRLH (RIIC0.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC0DRRH (RIIC0.RIICnDRR.UINT16[R_IO_H])
+#define RIIC0DRRHL (RIIC0.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC0DRRHH (RIIC0.RIICnDRR.UINT8[R_IO_HH])
+#define RIIC1CR1 (RIIC1.RIICnCR1.UINT32)
+#define RIIC1CR1L (RIIC1.RIICnCR1.UINT16[R_IO_L])
+#define RIIC1CR1LL (RIIC1.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC1CR1LH (RIIC1.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC1CR1H (RIIC1.RIICnCR1.UINT16[R_IO_H])
+#define RIIC1CR1HL (RIIC1.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC1CR1HH (RIIC1.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC1CR2 (RIIC1.RIICnCR2.UINT32)
+#define RIIC1CR2L (RIIC1.RIICnCR2.UINT16[R_IO_L])
+#define RIIC1CR2LL (RIIC1.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC1CR2LH (RIIC1.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC1CR2H (RIIC1.RIICnCR2.UINT16[R_IO_H])
+#define RIIC1CR2HL (RIIC1.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC1CR2HH (RIIC1.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC1MR1 (RIIC1.RIICnMR1.UINT32)
+#define RIIC1MR1L (RIIC1.RIICnMR1.UINT16[R_IO_L])
+#define RIIC1MR1LL (RIIC1.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC1MR1LH (RIIC1.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC1MR1H (RIIC1.RIICnMR1.UINT16[R_IO_H])
+#define RIIC1MR1HL (RIIC1.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC1MR1HH (RIIC1.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC1MR2 (RIIC1.RIICnMR2.UINT32)
+#define RIIC1MR2L (RIIC1.RIICnMR2.UINT16[R_IO_L])
+#define RIIC1MR2LL (RIIC1.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC1MR2LH (RIIC1.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC1MR2H (RIIC1.RIICnMR2.UINT16[R_IO_H])
+#define RIIC1MR2HL (RIIC1.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC1MR2HH (RIIC1.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC1MR3 (RIIC1.RIICnMR3.UINT32)
+#define RIIC1MR3L (RIIC1.RIICnMR3.UINT16[R_IO_L])
+#define RIIC1MR3LL (RIIC1.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC1MR3LH (RIIC1.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC1MR3H (RIIC1.RIICnMR3.UINT16[R_IO_H])
+#define RIIC1MR3HL (RIIC1.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC1MR3HH (RIIC1.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC1FER (RIIC1.RIICnFER.UINT32)
+#define RIIC1FERL (RIIC1.RIICnFER.UINT16[R_IO_L])
+#define RIIC1FERLL (RIIC1.RIICnFER.UINT8[R_IO_LL])
+#define RIIC1FERLH (RIIC1.RIICnFER.UINT8[R_IO_LH])
+#define RIIC1FERH (RIIC1.RIICnFER.UINT16[R_IO_H])
+#define RIIC1FERHL (RIIC1.RIICnFER.UINT8[R_IO_HL])
+#define RIIC1FERHH (RIIC1.RIICnFER.UINT8[R_IO_HH])
+#define RIIC1SER (RIIC1.RIICnSER.UINT32)
+#define RIIC1SERL (RIIC1.RIICnSER.UINT16[R_IO_L])
+#define RIIC1SERLL (RIIC1.RIICnSER.UINT8[R_IO_LL])
+#define RIIC1SERLH (RIIC1.RIICnSER.UINT8[R_IO_LH])
+#define RIIC1SERH (RIIC1.RIICnSER.UINT16[R_IO_H])
+#define RIIC1SERHL (RIIC1.RIICnSER.UINT8[R_IO_HL])
+#define RIIC1SERHH (RIIC1.RIICnSER.UINT8[R_IO_HH])
+#define RIIC1IER (RIIC1.RIICnIER.UINT32)
+#define RIIC1IERL (RIIC1.RIICnIER.UINT16[R_IO_L])
+#define RIIC1IERLL (RIIC1.RIICnIER.UINT8[R_IO_LL])
+#define RIIC1IERLH (RIIC1.RIICnIER.UINT8[R_IO_LH])
+#define RIIC1IERH (RIIC1.RIICnIER.UINT16[R_IO_H])
+#define RIIC1IERHL (RIIC1.RIICnIER.UINT8[R_IO_HL])
+#define RIIC1IERHH (RIIC1.RIICnIER.UINT8[R_IO_HH])
+#define RIIC1SR1 (RIIC1.RIICnSR1.UINT32)
+#define RIIC1SR1L (RIIC1.RIICnSR1.UINT16[R_IO_L])
+#define RIIC1SR1LL (RIIC1.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC1SR1LH (RIIC1.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC1SR1H (RIIC1.RIICnSR1.UINT16[R_IO_H])
+#define RIIC1SR1HL (RIIC1.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC1SR1HH (RIIC1.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC1SR2 (RIIC1.RIICnSR2.UINT32)
+#define RIIC1SR2L (RIIC1.RIICnSR2.UINT16[R_IO_L])
+#define RIIC1SR2LL (RIIC1.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC1SR2LH (RIIC1.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC1SR2H (RIIC1.RIICnSR2.UINT16[R_IO_H])
+#define RIIC1SR2HL (RIIC1.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC1SR2HH (RIIC1.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC1SAR0 (RIIC1.RIICnSAR0.UINT32)
+#define RIIC1SAR0L (RIIC1.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC1SAR0LL (RIIC1.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC1SAR0LH (RIIC1.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC1SAR0H (RIIC1.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC1SAR0HL (RIIC1.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC1SAR0HH (RIIC1.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC1SAR1 (RIIC1.RIICnSAR1.UINT32)
+#define RIIC1SAR1L (RIIC1.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC1SAR1LL (RIIC1.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC1SAR1LH (RIIC1.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC1SAR1H (RIIC1.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC1SAR1HL (RIIC1.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC1SAR1HH (RIIC1.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC1SAR2 (RIIC1.RIICnSAR2.UINT32)
+#define RIIC1SAR2L (RIIC1.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC1SAR2LL (RIIC1.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC1SAR2LH (RIIC1.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC1SAR2H (RIIC1.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC1SAR2HL (RIIC1.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC1SAR2HH (RIIC1.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC1BRL (RIIC1.RIICnBRL.UINT32)
+#define RIIC1BRLL (RIIC1.RIICnBRL.UINT16[R_IO_L])
+#define RIIC1BRLLL (RIIC1.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC1BRLLH (RIIC1.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC1BRLH (RIIC1.RIICnBRL.UINT16[R_IO_H])
+#define RIIC1BRLHL (RIIC1.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC1BRLHH (RIIC1.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC1BRH (RIIC1.RIICnBRH.UINT32)
+#define RIIC1BRHL (RIIC1.RIICnBRH.UINT16[R_IO_L])
+#define RIIC1BRHLL (RIIC1.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC1BRHLH (RIIC1.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC1BRHH (RIIC1.RIICnBRH.UINT16[R_IO_H])
+#define RIIC1BRHHL (RIIC1.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC1BRHHH (RIIC1.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC1DRT (RIIC1.RIICnDRT.UINT32)
+#define RIIC1DRTL (RIIC1.RIICnDRT.UINT16[R_IO_L])
+#define RIIC1DRTLL (RIIC1.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC1DRTLH (RIIC1.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC1DRTH (RIIC1.RIICnDRT.UINT16[R_IO_H])
+#define RIIC1DRTHL (RIIC1.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC1DRTHH (RIIC1.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC1DRR (RIIC1.RIICnDRR.UINT32)
+#define RIIC1DRRL (RIIC1.RIICnDRR.UINT16[R_IO_L])
+#define RIIC1DRRLL (RIIC1.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC1DRRLH (RIIC1.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC1DRRH (RIIC1.RIICnDRR.UINT16[R_IO_H])
+#define RIIC1DRRHL (RIIC1.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC1DRRHH (RIIC1.RIICnDRR.UINT8[R_IO_HH])
+#define RIIC2CR1 (RIIC2.RIICnCR1.UINT32)
+#define RIIC2CR1L (RIIC2.RIICnCR1.UINT16[R_IO_L])
+#define RIIC2CR1LL (RIIC2.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC2CR1LH (RIIC2.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC2CR1H (RIIC2.RIICnCR1.UINT16[R_IO_H])
+#define RIIC2CR1HL (RIIC2.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC2CR1HH (RIIC2.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC2CR2 (RIIC2.RIICnCR2.UINT32)
+#define RIIC2CR2L (RIIC2.RIICnCR2.UINT16[R_IO_L])
+#define RIIC2CR2LL (RIIC2.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC2CR2LH (RIIC2.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC2CR2H (RIIC2.RIICnCR2.UINT16[R_IO_H])
+#define RIIC2CR2HL (RIIC2.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC2CR2HH (RIIC2.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC2MR1 (RIIC2.RIICnMR1.UINT32)
+#define RIIC2MR1L (RIIC2.RIICnMR1.UINT16[R_IO_L])
+#define RIIC2MR1LL (RIIC2.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC2MR1LH (RIIC2.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC2MR1H (RIIC2.RIICnMR1.UINT16[R_IO_H])
+#define RIIC2MR1HL (RIIC2.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC2MR1HH (RIIC2.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC2MR2 (RIIC2.RIICnMR2.UINT32)
+#define RIIC2MR2L (RIIC2.RIICnMR2.UINT16[R_IO_L])
+#define RIIC2MR2LL (RIIC2.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC2MR2LH (RIIC2.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC2MR2H (RIIC2.RIICnMR2.UINT16[R_IO_H])
+#define RIIC2MR2HL (RIIC2.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC2MR2HH (RIIC2.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC2MR3 (RIIC2.RIICnMR3.UINT32)
+#define RIIC2MR3L (RIIC2.RIICnMR3.UINT16[R_IO_L])
+#define RIIC2MR3LL (RIIC2.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC2MR3LH (RIIC2.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC2MR3H (RIIC2.RIICnMR3.UINT16[R_IO_H])
+#define RIIC2MR3HL (RIIC2.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC2MR3HH (RIIC2.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC2FER (RIIC2.RIICnFER.UINT32)
+#define RIIC2FERL (RIIC2.RIICnFER.UINT16[R_IO_L])
+#define RIIC2FERLL (RIIC2.RIICnFER.UINT8[R_IO_LL])
+#define RIIC2FERLH (RIIC2.RIICnFER.UINT8[R_IO_LH])
+#define RIIC2FERH (RIIC2.RIICnFER.UINT16[R_IO_H])
+#define RIIC2FERHL (RIIC2.RIICnFER.UINT8[R_IO_HL])
+#define RIIC2FERHH (RIIC2.RIICnFER.UINT8[R_IO_HH])
+#define RIIC2SER (RIIC2.RIICnSER.UINT32)
+#define RIIC2SERL (RIIC2.RIICnSER.UINT16[R_IO_L])
+#define RIIC2SERLL (RIIC2.RIICnSER.UINT8[R_IO_LL])
+#define RIIC2SERLH (RIIC2.RIICnSER.UINT8[R_IO_LH])
+#define RIIC2SERH (RIIC2.RIICnSER.UINT16[R_IO_H])
+#define RIIC2SERHL (RIIC2.RIICnSER.UINT8[R_IO_HL])
+#define RIIC2SERHH (RIIC2.RIICnSER.UINT8[R_IO_HH])
+#define RIIC2IER (RIIC2.RIICnIER.UINT32)
+#define RIIC2IERL (RIIC2.RIICnIER.UINT16[R_IO_L])
+#define RIIC2IERLL (RIIC2.RIICnIER.UINT8[R_IO_LL])
+#define RIIC2IERLH (RIIC2.RIICnIER.UINT8[R_IO_LH])
+#define RIIC2IERH (RIIC2.RIICnIER.UINT16[R_IO_H])
+#define RIIC2IERHL (RIIC2.RIICnIER.UINT8[R_IO_HL])
+#define RIIC2IERHH (RIIC2.RIICnIER.UINT8[R_IO_HH])
+#define RIIC2SR1 (RIIC2.RIICnSR1.UINT32)
+#define RIIC2SR1L (RIIC2.RIICnSR1.UINT16[R_IO_L])
+#define RIIC2SR1LL (RIIC2.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC2SR1LH (RIIC2.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC2SR1H (RIIC2.RIICnSR1.UINT16[R_IO_H])
+#define RIIC2SR1HL (RIIC2.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC2SR1HH (RIIC2.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC2SR2 (RIIC2.RIICnSR2.UINT32)
+#define RIIC2SR2L (RIIC2.RIICnSR2.UINT16[R_IO_L])
+#define RIIC2SR2LL (RIIC2.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC2SR2LH (RIIC2.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC2SR2H (RIIC2.RIICnSR2.UINT16[R_IO_H])
+#define RIIC2SR2HL (RIIC2.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC2SR2HH (RIIC2.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC2SAR0 (RIIC2.RIICnSAR0.UINT32)
+#define RIIC2SAR0L (RIIC2.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC2SAR0LL (RIIC2.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC2SAR0LH (RIIC2.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC2SAR0H (RIIC2.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC2SAR0HL (RIIC2.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC2SAR0HH (RIIC2.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC2SAR1 (RIIC2.RIICnSAR1.UINT32)
+#define RIIC2SAR1L (RIIC2.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC2SAR1LL (RIIC2.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC2SAR1LH (RIIC2.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC2SAR1H (RIIC2.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC2SAR1HL (RIIC2.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC2SAR1HH (RIIC2.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC2SAR2 (RIIC2.RIICnSAR2.UINT32)
+#define RIIC2SAR2L (RIIC2.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC2SAR2LL (RIIC2.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC2SAR2LH (RIIC2.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC2SAR2H (RIIC2.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC2SAR2HL (RIIC2.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC2SAR2HH (RIIC2.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC2BRL (RIIC2.RIICnBRL.UINT32)
+#define RIIC2BRLL (RIIC2.RIICnBRL.UINT16[R_IO_L])
+#define RIIC2BRLLL (RIIC2.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC2BRLLH (RIIC2.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC2BRLH (RIIC2.RIICnBRL.UINT16[R_IO_H])
+#define RIIC2BRLHL (RIIC2.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC2BRLHH (RIIC2.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC2BRH (RIIC2.RIICnBRH.UINT32)
+#define RIIC2BRHL (RIIC2.RIICnBRH.UINT16[R_IO_L])
+#define RIIC2BRHLL (RIIC2.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC2BRHLH (RIIC2.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC2BRHH (RIIC2.RIICnBRH.UINT16[R_IO_H])
+#define RIIC2BRHHL (RIIC2.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC2BRHHH (RIIC2.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC2DRT (RIIC2.RIICnDRT.UINT32)
+#define RIIC2DRTL (RIIC2.RIICnDRT.UINT16[R_IO_L])
+#define RIIC2DRTLL (RIIC2.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC2DRTLH (RIIC2.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC2DRTH (RIIC2.RIICnDRT.UINT16[R_IO_H])
+#define RIIC2DRTHL (RIIC2.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC2DRTHH (RIIC2.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC2DRR (RIIC2.RIICnDRR.UINT32)
+#define RIIC2DRRL (RIIC2.RIICnDRR.UINT16[R_IO_L])
+#define RIIC2DRRLL (RIIC2.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC2DRRLH (RIIC2.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC2DRRH (RIIC2.RIICnDRR.UINT16[R_IO_H])
+#define RIIC2DRRHL (RIIC2.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC2DRRHH (RIIC2.RIICnDRR.UINT8[R_IO_HH])
+#define RIIC3CR1 (RIIC3.RIICnCR1.UINT32)
+#define RIIC3CR1L (RIIC3.RIICnCR1.UINT16[R_IO_L])
+#define RIIC3CR1LL (RIIC3.RIICnCR1.UINT8[R_IO_LL])
+#define RIIC3CR1LH (RIIC3.RIICnCR1.UINT8[R_IO_LH])
+#define RIIC3CR1H (RIIC3.RIICnCR1.UINT16[R_IO_H])
+#define RIIC3CR1HL (RIIC3.RIICnCR1.UINT8[R_IO_HL])
+#define RIIC3CR1HH (RIIC3.RIICnCR1.UINT8[R_IO_HH])
+#define RIIC3CR2 (RIIC3.RIICnCR2.UINT32)
+#define RIIC3CR2L (RIIC3.RIICnCR2.UINT16[R_IO_L])
+#define RIIC3CR2LL (RIIC3.RIICnCR2.UINT8[R_IO_LL])
+#define RIIC3CR2LH (RIIC3.RIICnCR2.UINT8[R_IO_LH])
+#define RIIC3CR2H (RIIC3.RIICnCR2.UINT16[R_IO_H])
+#define RIIC3CR2HL (RIIC3.RIICnCR2.UINT8[R_IO_HL])
+#define RIIC3CR2HH (RIIC3.RIICnCR2.UINT8[R_IO_HH])
+#define RIIC3MR1 (RIIC3.RIICnMR1.UINT32)
+#define RIIC3MR1L (RIIC3.RIICnMR1.UINT16[R_IO_L])
+#define RIIC3MR1LL (RIIC3.RIICnMR1.UINT8[R_IO_LL])
+#define RIIC3MR1LH (RIIC3.RIICnMR1.UINT8[R_IO_LH])
+#define RIIC3MR1H (RIIC3.RIICnMR1.UINT16[R_IO_H])
+#define RIIC3MR1HL (RIIC3.RIICnMR1.UINT8[R_IO_HL])
+#define RIIC3MR1HH (RIIC3.RIICnMR1.UINT8[R_IO_HH])
+#define RIIC3MR2 (RIIC3.RIICnMR2.UINT32)
+#define RIIC3MR2L (RIIC3.RIICnMR2.UINT16[R_IO_L])
+#define RIIC3MR2LL (RIIC3.RIICnMR2.UINT8[R_IO_LL])
+#define RIIC3MR2LH (RIIC3.RIICnMR2.UINT8[R_IO_LH])
+#define RIIC3MR2H (RIIC3.RIICnMR2.UINT16[R_IO_H])
+#define RIIC3MR2HL (RIIC3.RIICnMR2.UINT8[R_IO_HL])
+#define RIIC3MR2HH (RIIC3.RIICnMR2.UINT8[R_IO_HH])
+#define RIIC3MR3 (RIIC3.RIICnMR3.UINT32)
+#define RIIC3MR3L (RIIC3.RIICnMR3.UINT16[R_IO_L])
+#define RIIC3MR3LL (RIIC3.RIICnMR3.UINT8[R_IO_LL])
+#define RIIC3MR3LH (RIIC3.RIICnMR3.UINT8[R_IO_LH])
+#define RIIC3MR3H (RIIC3.RIICnMR3.UINT16[R_IO_H])
+#define RIIC3MR3HL (RIIC3.RIICnMR3.UINT8[R_IO_HL])
+#define RIIC3MR3HH (RIIC3.RIICnMR3.UINT8[R_IO_HH])
+#define RIIC3FER (RIIC3.RIICnFER.UINT32)
+#define RIIC3FERL (RIIC3.RIICnFER.UINT16[R_IO_L])
+#define RIIC3FERLL (RIIC3.RIICnFER.UINT8[R_IO_LL])
+#define RIIC3FERLH (RIIC3.RIICnFER.UINT8[R_IO_LH])
+#define RIIC3FERH (RIIC3.RIICnFER.UINT16[R_IO_H])
+#define RIIC3FERHL (RIIC3.RIICnFER.UINT8[R_IO_HL])
+#define RIIC3FERHH (RIIC3.RIICnFER.UINT8[R_IO_HH])
+#define RIIC3SER (RIIC3.RIICnSER.UINT32)
+#define RIIC3SERL (RIIC3.RIICnSER.UINT16[R_IO_L])
+#define RIIC3SERLL (RIIC3.RIICnSER.UINT8[R_IO_LL])
+#define RIIC3SERLH (RIIC3.RIICnSER.UINT8[R_IO_LH])
+#define RIIC3SERH (RIIC3.RIICnSER.UINT16[R_IO_H])
+#define RIIC3SERHL (RIIC3.RIICnSER.UINT8[R_IO_HL])
+#define RIIC3SERHH (RIIC3.RIICnSER.UINT8[R_IO_HH])
+#define RIIC3IER (RIIC3.RIICnIER.UINT32)
+#define RIIC3IERL (RIIC3.RIICnIER.UINT16[R_IO_L])
+#define RIIC3IERLL (RIIC3.RIICnIER.UINT8[R_IO_LL])
+#define RIIC3IERLH (RIIC3.RIICnIER.UINT8[R_IO_LH])
+#define RIIC3IERH (RIIC3.RIICnIER.UINT16[R_IO_H])
+#define RIIC3IERHL (RIIC3.RIICnIER.UINT8[R_IO_HL])
+#define RIIC3IERHH (RIIC3.RIICnIER.UINT8[R_IO_HH])
+#define RIIC3SR1 (RIIC3.RIICnSR1.UINT32)
+#define RIIC3SR1L (RIIC3.RIICnSR1.UINT16[R_IO_L])
+#define RIIC3SR1LL (RIIC3.RIICnSR1.UINT8[R_IO_LL])
+#define RIIC3SR1LH (RIIC3.RIICnSR1.UINT8[R_IO_LH])
+#define RIIC3SR1H (RIIC3.RIICnSR1.UINT16[R_IO_H])
+#define RIIC3SR1HL (RIIC3.RIICnSR1.UINT8[R_IO_HL])
+#define RIIC3SR1HH (RIIC3.RIICnSR1.UINT8[R_IO_HH])
+#define RIIC3SR2 (RIIC3.RIICnSR2.UINT32)
+#define RIIC3SR2L (RIIC3.RIICnSR2.UINT16[R_IO_L])
+#define RIIC3SR2LL (RIIC3.RIICnSR2.UINT8[R_IO_LL])
+#define RIIC3SR2LH (RIIC3.RIICnSR2.UINT8[R_IO_LH])
+#define RIIC3SR2H (RIIC3.RIICnSR2.UINT16[R_IO_H])
+#define RIIC3SR2HL (RIIC3.RIICnSR2.UINT8[R_IO_HL])
+#define RIIC3SR2HH (RIIC3.RIICnSR2.UINT8[R_IO_HH])
+#define RIIC3SAR0 (RIIC3.RIICnSAR0.UINT32)
+#define RIIC3SAR0L (RIIC3.RIICnSAR0.UINT16[R_IO_L])
+#define RIIC3SAR0LL (RIIC3.RIICnSAR0.UINT8[R_IO_LL])
+#define RIIC3SAR0LH (RIIC3.RIICnSAR0.UINT8[R_IO_LH])
+#define RIIC3SAR0H (RIIC3.RIICnSAR0.UINT16[R_IO_H])
+#define RIIC3SAR0HL (RIIC3.RIICnSAR0.UINT8[R_IO_HL])
+#define RIIC3SAR0HH (RIIC3.RIICnSAR0.UINT8[R_IO_HH])
+#define RIIC3SAR1 (RIIC3.RIICnSAR1.UINT32)
+#define RIIC3SAR1L (RIIC3.RIICnSAR1.UINT16[R_IO_L])
+#define RIIC3SAR1LL (RIIC3.RIICnSAR1.UINT8[R_IO_LL])
+#define RIIC3SAR1LH (RIIC3.RIICnSAR1.UINT8[R_IO_LH])
+#define RIIC3SAR1H (RIIC3.RIICnSAR1.UINT16[R_IO_H])
+#define RIIC3SAR1HL (RIIC3.RIICnSAR1.UINT8[R_IO_HL])
+#define RIIC3SAR1HH (RIIC3.RIICnSAR1.UINT8[R_IO_HH])
+#define RIIC3SAR2 (RIIC3.RIICnSAR2.UINT32)
+#define RIIC3SAR2L (RIIC3.RIICnSAR2.UINT16[R_IO_L])
+#define RIIC3SAR2LL (RIIC3.RIICnSAR2.UINT8[R_IO_LL])
+#define RIIC3SAR2LH (RIIC3.RIICnSAR2.UINT8[R_IO_LH])
+#define RIIC3SAR2H (RIIC3.RIICnSAR2.UINT16[R_IO_H])
+#define RIIC3SAR2HL (RIIC3.RIICnSAR2.UINT8[R_IO_HL])
+#define RIIC3SAR2HH (RIIC3.RIICnSAR2.UINT8[R_IO_HH])
+#define RIIC3BRL (RIIC3.RIICnBRL.UINT32)
+#define RIIC3BRLL (RIIC3.RIICnBRL.UINT16[R_IO_L])
+#define RIIC3BRLLL (RIIC3.RIICnBRL.UINT8[R_IO_LL])
+#define RIIC3BRLLH (RIIC3.RIICnBRL.UINT8[R_IO_LH])
+#define RIIC3BRLH (RIIC3.RIICnBRL.UINT16[R_IO_H])
+#define RIIC3BRLHL (RIIC3.RIICnBRL.UINT8[R_IO_HL])
+#define RIIC3BRLHH (RIIC3.RIICnBRL.UINT8[R_IO_HH])
+#define RIIC3BRH (RIIC3.RIICnBRH.UINT32)
+#define RIIC3BRHL (RIIC3.RIICnBRH.UINT16[R_IO_L])
+#define RIIC3BRHLL (RIIC3.RIICnBRH.UINT8[R_IO_LL])
+#define RIIC3BRHLH (RIIC3.RIICnBRH.UINT8[R_IO_LH])
+#define RIIC3BRHH (RIIC3.RIICnBRH.UINT16[R_IO_H])
+#define RIIC3BRHHL (RIIC3.RIICnBRH.UINT8[R_IO_HL])
+#define RIIC3BRHHH (RIIC3.RIICnBRH.UINT8[R_IO_HH])
+#define RIIC3DRT (RIIC3.RIICnDRT.UINT32)
+#define RIIC3DRTL (RIIC3.RIICnDRT.UINT16[R_IO_L])
+#define RIIC3DRTLL (RIIC3.RIICnDRT.UINT8[R_IO_LL])
+#define RIIC3DRTLH (RIIC3.RIICnDRT.UINT8[R_IO_LH])
+#define RIIC3DRTH (RIIC3.RIICnDRT.UINT16[R_IO_H])
+#define RIIC3DRTHL (RIIC3.RIICnDRT.UINT8[R_IO_HL])
+#define RIIC3DRTHH (RIIC3.RIICnDRT.UINT8[R_IO_HH])
+#define RIIC3DRR (RIIC3.RIICnDRR.UINT32)
+#define RIIC3DRRL (RIIC3.RIICnDRR.UINT16[R_IO_L])
+#define RIIC3DRRLL (RIIC3.RIICnDRR.UINT8[R_IO_LL])
+#define RIIC3DRRLH (RIIC3.RIICnDRR.UINT8[R_IO_LH])
+#define RIIC3DRRH (RIIC3.RIICnDRR.UINT16[R_IO_H])
+#define RIIC3DRRHL (RIIC3.RIICnDRR.UINT8[R_IO_HL])
+#define RIIC3DRRHH (RIIC3.RIICnDRR.UINT8[R_IO_HH])
+
+#define RIICnCRm_COUNT (2)
+#define RIICnMRm_COUNT (3)
+#define RIICnSRm_COUNT (2)
+#define RIICnSARm_COUNT (3)
+
+
+typedef struct st_riic
+{
+                                                           /* RIIC             */
+
+/* #define RIICnCRm_COUNT (2) */
+    union iodefine_reg32_t  RIICnCR1;                      /*  RIICnCR1        */
+    union iodefine_reg32_t  RIICnCR2;                      /*  RIICnCR2        */
+
+/* #define RIICnMRm_COUNT (3) */
+    union iodefine_reg32_t  RIICnMR1;                      /*  RIICnMR1        */
+    union iodefine_reg32_t  RIICnMR2;                      /*  RIICnMR2        */
+    union iodefine_reg32_t  RIICnMR3;                      /*  RIICnMR3        */
+    union iodefine_reg32_t  RIICnFER;                      /*  RIICnFER        */
+    union iodefine_reg32_t  RIICnSER;                      /*  RIICnSER        */
+    union iodefine_reg32_t  RIICnIER;                      /*  RIICnIER        */
+
+/* #define RIICnSRm_COUNT (2) */
+    union iodefine_reg32_t  RIICnSR1;                      /*  RIICnSR1        */
+    union iodefine_reg32_t  RIICnSR2;                      /*  RIICnSR2        */
+
+/* #define RIICnSARm_COUNT (3) */
+    union iodefine_reg32_t  RIICnSAR0;                     /*  RIICnSAR0       */
+    union iodefine_reg32_t  RIICnSAR1;                     /*  RIICnSAR1       */
+    union iodefine_reg32_t  RIICnSAR2;                     /*  RIICnSAR2       */
+    union iodefine_reg32_t  RIICnBRL;                      /*  RIICnBRL        */
+    union iodefine_reg32_t  RIICnBRH;                      /*  RIICnBRH        */
+    union iodefine_reg32_t  RIICnDRT;                      /*  RIICnDRT        */
+    union iodefine_reg32_t  RIICnDRR;                      /*  RIICnDRR        */
+    
+} r_io_riic_t;
+
+
+/* Channel array defines of RIIC (2)*/
+#ifdef  DECLARE_RIIC_CHANNELS
+volatile struct st_riic*  RIIC[ RIIC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RIIC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RIIC_CHANNELS */
+/* End of channel array defines of RIIC (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,30 +18,104 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : romdec_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef ROMDEC_IODEFINE_H
 #define ROMDEC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_romdec
-{                                                          /* ROMDEC           */
+#define ROMDEC  (*(struct st_romdec  *)0xE8005000uL) /* ROMDEC */
+
+
+#define ROMDECCROMEN (ROMDEC.CROMEN)
+#define ROMDECCROMSY0 (ROMDEC.CROMSY0)
+#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0)
+#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1)
+#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3)
+#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4)
+#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5)
+#define ROMDECCROMST0 (ROMDEC.CROMST0)
+#define ROMDECCROMST1 (ROMDEC.CROMST1)
+#define ROMDECCROMST3 (ROMDEC.CROMST3)
+#define ROMDECCROMST4 (ROMDEC.CROMST4)
+#define ROMDECCROMST5 (ROMDEC.CROMST5)
+#define ROMDECCROMST6 (ROMDEC.CROMST6)
+#define ROMDECCBUFST0 (ROMDEC.CBUFST0)
+#define ROMDECCBUFST1 (ROMDEC.CBUFST1)
+#define ROMDECCBUFST2 (ROMDEC.CBUFST2)
+#define ROMDECHEAD00 (ROMDEC.HEAD00)
+#define ROMDECHEAD01 (ROMDEC.HEAD01)
+#define ROMDECHEAD02 (ROMDEC.HEAD02)
+#define ROMDECHEAD03 (ROMDEC.HEAD03)
+#define ROMDECSHEAD00 (ROMDEC.SHEAD00)
+#define ROMDECSHEAD01 (ROMDEC.SHEAD01)
+#define ROMDECSHEAD02 (ROMDEC.SHEAD02)
+#define ROMDECSHEAD03 (ROMDEC.SHEAD03)
+#define ROMDECSHEAD04 (ROMDEC.SHEAD04)
+#define ROMDECSHEAD05 (ROMDEC.SHEAD05)
+#define ROMDECSHEAD06 (ROMDEC.SHEAD06)
+#define ROMDECSHEAD07 (ROMDEC.SHEAD07)
+#define ROMDECHEAD20 (ROMDEC.HEAD20)
+#define ROMDECHEAD21 (ROMDEC.HEAD21)
+#define ROMDECHEAD22 (ROMDEC.HEAD22)
+#define ROMDECHEAD23 (ROMDEC.HEAD23)
+#define ROMDECSHEAD20 (ROMDEC.SHEAD20)
+#define ROMDECSHEAD21 (ROMDEC.SHEAD21)
+#define ROMDECSHEAD22 (ROMDEC.SHEAD22)
+#define ROMDECSHEAD23 (ROMDEC.SHEAD23)
+#define ROMDECSHEAD24 (ROMDEC.SHEAD24)
+#define ROMDECSHEAD25 (ROMDEC.SHEAD25)
+#define ROMDECSHEAD26 (ROMDEC.SHEAD26)
+#define ROMDECSHEAD27 (ROMDEC.SHEAD27)
+#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0)
+#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1)
+#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2)
+#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3)
+#define ROMDECCROMST0M (ROMDEC.CROMST0M)
+#define ROMDECROMDECRST (ROMDEC.ROMDECRST)
+#define ROMDECRSTSTAT (ROMDEC.RSTSTAT)
+#define ROMDECSSI (ROMDEC.SSI)
+#define ROMDECINTHOLD (ROMDEC.INTHOLD)
+#define ROMDECINHINT (ROMDEC.INHINT)
+#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0)
+#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2)
+#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0)
+
+#define ROMDEC_CROMCTL0_COUNT (2)
+#define ROMDEC_CROMST0_COUNT (2)
+#define ROMDEC_CBUFST0_COUNT (3)
+#define ROMDEC_HEAD00_COUNT (4)
+#define ROMDEC_SHEAD00_COUNT (8)
+#define ROMDEC_HEAD20_COUNT (4)
+#define ROMDEC_SHEAD20_COUNT (8)
+#define ROMDEC_CBUFCTL0_COUNT (4)
+#define ROMDEC_STRMDIN0_COUNT (2)
+
+
+typedef struct st_romdec
+{
+                                                           /* ROMDEC           */
     volatile uint8_t   CROMEN;                                 /*  CROMEN          */
     volatile uint8_t   CROMSY0;                                /*  CROMSY0         */
-#define ROMDEC_CROMCTL0_COUNT 2
+
+/* #define ROMDEC_CROMCTL0_COUNT (2) */
     volatile uint8_t   CROMCTL0;                               /*  CROMCTL0        */
     volatile uint8_t   CROMCTL1;                               /*  CROMCTL1        */
     volatile uint8_t   dummy23[1];                             /*                  */
     volatile uint8_t   CROMCTL3;                               /*  CROMCTL3        */
     volatile uint8_t   CROMCTL4;                               /*  CROMCTL4        */
     volatile uint8_t   CROMCTL5;                               /*  CROMCTL5        */
-#define ROMDEC_CROMST0_COUNT 2
+
+/* #define ROMDEC_CROMST0_COUNT (2) */
     volatile uint8_t   CROMST0;                                /*  CROMST0         */
     volatile uint8_t   CROMST1;                                /*  CROMST1         */
     volatile uint8_t   dummy24[1];                             /*                  */
@@ -50,17 +124,20 @@
     volatile uint8_t   CROMST5;                                /*  CROMST5         */
     volatile uint8_t   CROMST6;                                /*  CROMST6         */
     volatile uint8_t   dummy25[5];                             /*                  */
-#define ROMDEC_CBUFST0_COUNT 3
+
+/* #define ROMDEC_CBUFST0_COUNT (3) */
     volatile uint8_t   CBUFST0;                                /*  CBUFST0         */
     volatile uint8_t   CBUFST1;                                /*  CBUFST1         */
     volatile uint8_t   CBUFST2;                                /*  CBUFST2         */
     volatile uint8_t   dummy26[1];                             /*                  */
-#define ROMDEC_HEAD00_COUNT 4
+
+/* #define ROMDEC_HEAD00_COUNT (4) */
     volatile uint8_t   HEAD00;                                 /*  HEAD00          */
     volatile uint8_t   HEAD01;                                 /*  HEAD01          */
     volatile uint8_t   HEAD02;                                 /*  HEAD02          */
     volatile uint8_t   HEAD03;                                 /*  HEAD03          */
-#define ROMDEC_SHEAD00_COUNT 8
+
+/* #define ROMDEC_SHEAD00_COUNT (8) */
     volatile uint8_t   SHEAD00;                                /*  SHEAD00         */
     volatile uint8_t   SHEAD01;                                /*  SHEAD01         */
     volatile uint8_t   SHEAD02;                                /*  SHEAD02         */
@@ -69,12 +146,14 @@
     volatile uint8_t   SHEAD05;                                /*  SHEAD05         */
     volatile uint8_t   SHEAD06;                                /*  SHEAD06         */
     volatile uint8_t   SHEAD07;                                /*  SHEAD07         */
-#define ROMDEC_HEAD20_COUNT 4
+
+/* #define ROMDEC_HEAD20_COUNT (4) */
     volatile uint8_t   HEAD20;                                 /*  HEAD20          */
     volatile uint8_t   HEAD21;                                 /*  HEAD21          */
     volatile uint8_t   HEAD22;                                 /*  HEAD22          */
     volatile uint8_t   HEAD23;                                 /*  HEAD23          */
-#define ROMDEC_SHEAD20_COUNT 8
+
+/* #define ROMDEC_SHEAD20_COUNT (8) */
     volatile uint8_t   SHEAD20;                                /*  SHEAD20         */
     volatile uint8_t   SHEAD21;                                /*  SHEAD21         */
     volatile uint8_t   SHEAD22;                                /*  SHEAD22         */
@@ -84,7 +163,8 @@
     volatile uint8_t   SHEAD26;                                /*  SHEAD26         */
     volatile uint8_t   SHEAD27;                                /*  SHEAD27         */
     volatile uint8_t   dummy27[16];                            /*                  */
-#define ROMDEC_CBUFCTL0_COUNT 4
+
+/* #define ROMDEC_CBUFCTL0_COUNT (4) */
     volatile uint8_t   CBUFCTL0;                               /*  CBUFCTL0        */
     volatile uint8_t   CBUFCTL1;                               /*  CBUFCTL1        */
     volatile uint8_t   CBUFCTL2;                               /*  CBUFCTL2        */
@@ -99,68 +179,16 @@
     volatile uint8_t   INTHOLD;                                /*  INTHOLD         */
     volatile uint8_t   INHINT;                                 /*  INHINT          */
     volatile uint8_t   dummy31[246];                           /*                  */
-#define ROMDEC_STRMDIN0_COUNT 2
+
+/* #define ROMDEC_STRMDIN0_COUNT (2) */
     volatile uint16_t STRMDIN0;                               /*  STRMDIN0        */
     volatile uint16_t STRMDIN2;                               /*  STRMDIN2        */
     volatile uint16_t STRMDOUT0;                              /*  STRMDOUT0       */
-};
-
-
-#define ROMDEC  (*(struct st_romdec  *)0xE8005000uL) /* ROMDEC */
+} r_io_romdec_t;
 
 
-#define ROMDECCROMEN ROMDEC.CROMEN
-#define ROMDECCROMSY0 ROMDEC.CROMSY0
-#define ROMDECCROMCTL0 ROMDEC.CROMCTL0
-#define ROMDECCROMCTL1 ROMDEC.CROMCTL1
-#define ROMDECCROMCTL3 ROMDEC.CROMCTL3
-#define ROMDECCROMCTL4 ROMDEC.CROMCTL4
-#define ROMDECCROMCTL5 ROMDEC.CROMCTL5
-#define ROMDECCROMST0 ROMDEC.CROMST0
-#define ROMDECCROMST1 ROMDEC.CROMST1
-#define ROMDECCROMST3 ROMDEC.CROMST3
-#define ROMDECCROMST4 ROMDEC.CROMST4
-#define ROMDECCROMST5 ROMDEC.CROMST5
-#define ROMDECCROMST6 ROMDEC.CROMST6
-#define ROMDECCBUFST0 ROMDEC.CBUFST0
-#define ROMDECCBUFST1 ROMDEC.CBUFST1
-#define ROMDECCBUFST2 ROMDEC.CBUFST2
-#define ROMDECHEAD00 ROMDEC.HEAD00
-#define ROMDECHEAD01 ROMDEC.HEAD01
-#define ROMDECHEAD02 ROMDEC.HEAD02
-#define ROMDECHEAD03 ROMDEC.HEAD03
-#define ROMDECSHEAD00 ROMDEC.SHEAD00
-#define ROMDECSHEAD01 ROMDEC.SHEAD01
-#define ROMDECSHEAD02 ROMDEC.SHEAD02
-#define ROMDECSHEAD03 ROMDEC.SHEAD03
-#define ROMDECSHEAD04 ROMDEC.SHEAD04
-#define ROMDECSHEAD05 ROMDEC.SHEAD05
-#define ROMDECSHEAD06 ROMDEC.SHEAD06
-#define ROMDECSHEAD07 ROMDEC.SHEAD07
-#define ROMDECHEAD20 ROMDEC.HEAD20
-#define ROMDECHEAD21 ROMDEC.HEAD21
-#define ROMDECHEAD22 ROMDEC.HEAD22
-#define ROMDECHEAD23 ROMDEC.HEAD23
-#define ROMDECSHEAD20 ROMDEC.SHEAD20
-#define ROMDECSHEAD21 ROMDEC.SHEAD21
-#define ROMDECSHEAD22 ROMDEC.SHEAD22
-#define ROMDECSHEAD23 ROMDEC.SHEAD23
-#define ROMDECSHEAD24 ROMDEC.SHEAD24
-#define ROMDECSHEAD25 ROMDEC.SHEAD25
-#define ROMDECSHEAD26 ROMDEC.SHEAD26
-#define ROMDECSHEAD27 ROMDEC.SHEAD27
-#define ROMDECCBUFCTL0 ROMDEC.CBUFCTL0
-#define ROMDECCBUFCTL1 ROMDEC.CBUFCTL1
-#define ROMDECCBUFCTL2 ROMDEC.CBUFCTL2
-#define ROMDECCBUFCTL3 ROMDEC.CBUFCTL3
-#define ROMDECCROMST0M ROMDEC.CROMST0M
-#define ROMDECROMDECRST ROMDEC.ROMDECRST
-#define ROMDECRSTSTAT ROMDEC.RSTSTAT
-#define ROMDECSSI ROMDEC.SSI
-#define ROMDECINTHOLD ROMDEC.INTHOLD
-#define ROMDECINHINT ROMDEC.INHINT
-#define ROMDECSTRMDIN0 ROMDEC.STRMDIN0
-#define ROMDECSTRMDIN2 ROMDEC.STRMDIN2
-#define ROMDECSTRMDOUT0 ROMDEC.STRMDOUT0
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rscan0_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,1886 +18,30 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : rscan0_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef RSCAN0_IODEFINE_H
 #define RSCAN0_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
 /* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_rscan0
-{                                                          /* RSCAN0           */
-/* start of struct st_rscan_from_rscan0cncfg */
-    union iodefine_reg32_t  C0CFG;                         /*  C0CFG           */
-    union iodefine_reg32_t  C0CTR;                         /*  C0CTR           */
-    union iodefine_reg32_t  C0STS;                         /*  C0STS           */
-    union iodefine_reg32_t  C0ERFL;                        /*  C0ERFL          */
-/* end of struct st_rscan_from_rscan0cncfg */
-    
-/* start of struct st_rscan_from_rscan0cncfg */
-    union iodefine_reg32_t  C1CFG;                         /*  C1CFG           */
-    union iodefine_reg32_t  C1CTR;                         /*  C1CTR           */
-    union iodefine_reg32_t  C1STS;                         /*  C1STS           */
-    union iodefine_reg32_t  C1ERFL;                        /*  C1ERFL          */
-/* end of struct st_rscan_from_rscan0cncfg */
-    
-/* start of struct st_rscan_from_rscan0cncfg */
-    union iodefine_reg32_t  C2CFG;                         /*  C2CFG           */
-    union iodefine_reg32_t  C2CTR;                         /*  C2CTR           */
-    union iodefine_reg32_t  C2STS;                         /*  C2STS           */
-    union iodefine_reg32_t  C2ERFL;                        /*  C2ERFL          */
-/* end of struct st_rscan_from_rscan0cncfg */
-    
-/* start of struct st_rscan_from_rscan0cncfg */
-    union iodefine_reg32_t  C3CFG;                         /*  C3CFG           */
-    union iodefine_reg32_t  C3CTR;                         /*  C3CTR           */
-    union iodefine_reg32_t  C3STS;                         /*  C3STS           */
-    union iodefine_reg32_t  C3ERFL;                        /*  C3ERFL          */
-/* end of struct st_rscan_from_rscan0cncfg */
-    
-/* start of struct st_rscan_from_rscan0cncfg */
-    union iodefine_reg32_t  C4CFG;                         /*  C4CFG           */
-    union iodefine_reg32_t  C4CTR;                         /*  C4CTR           */
-    union iodefine_reg32_t  C4STS;                         /*  C4STS           */
-    union iodefine_reg32_t  C4ERFL;                        /*  C4ERFL          */
-/* end of struct st_rscan_from_rscan0cncfg */
-    
-    volatile uint8_t   dummy159[52];                           /*                  */
-    union iodefine_reg32_t  GCFG;                          /*  GCFG            */
-    union iodefine_reg32_t  GCTR;                          /*  GCTR            */
-    union iodefine_reg32_t  GSTS;                          /*  GSTS            */
-    union iodefine_reg32_t  GERFL;                         /*  GERFL           */
-    union iodefine_reg32_16_t  GTSC;                       /*  GTSC            */
-    union iodefine_reg32_t  GAFLECTR;                      /*  GAFLECTR        */
-#define RSCAN0_GAFLCFG0_COUNT 2
-    union iodefine_reg32_t  GAFLCFG0;                      /*  GAFLCFG0        */
-    union iodefine_reg32_t  GAFLCFG1;                      /*  GAFLCFG1        */
-    union iodefine_reg32_t  RMNB;                          /*  RMNB            */
-#define RSCAN0_RMND0_COUNT 3
-    union iodefine_reg32_t  RMND0;                         /*  RMND0           */
-    union iodefine_reg32_t  RMND1;                         /*  RMND1           */
-    union iodefine_reg32_t  RMND2;                         /*  RMND2           */
-    
-    volatile uint8_t   dummy160[4];                            /*                  */
-#define RSCAN0_RFCC0_COUNT 8
-    union iodefine_reg32_t  RFCC0;                         /*  RFCC0           */
-    union iodefine_reg32_t  RFCC1;                         /*  RFCC1           */
-    union iodefine_reg32_t  RFCC2;                         /*  RFCC2           */
-    union iodefine_reg32_t  RFCC3;                         /*  RFCC3           */
-    union iodefine_reg32_t  RFCC4;                         /*  RFCC4           */
-    union iodefine_reg32_t  RFCC5;                         /*  RFCC5           */
-    union iodefine_reg32_t  RFCC6;                         /*  RFCC6           */
-    union iodefine_reg32_t  RFCC7;                         /*  RFCC7           */
-#define RSCAN0_RFSTS0_COUNT 8
-    union iodefine_reg32_t  RFSTS0;                        /*  RFSTS0          */
-    union iodefine_reg32_t  RFSTS1;                        /*  RFSTS1          */
-    union iodefine_reg32_t  RFSTS2;                        /*  RFSTS2          */
-    union iodefine_reg32_t  RFSTS3;                        /*  RFSTS3          */
-    union iodefine_reg32_t  RFSTS4;                        /*  RFSTS4          */
-    union iodefine_reg32_t  RFSTS5;                        /*  RFSTS5          */
-    union iodefine_reg32_t  RFSTS6;                        /*  RFSTS6          */
-    union iodefine_reg32_t  RFSTS7;                        /*  RFSTS7          */
-#define RSCAN0_RFPCTR0_COUNT 8
-    union iodefine_reg32_t  RFPCTR0;                       /*  RFPCTR0         */
-    union iodefine_reg32_t  RFPCTR1;                       /*  RFPCTR1         */
-    union iodefine_reg32_t  RFPCTR2;                       /*  RFPCTR2         */
-    union iodefine_reg32_t  RFPCTR3;                       /*  RFPCTR3         */
-    union iodefine_reg32_t  RFPCTR4;                       /*  RFPCTR4         */
-    union iodefine_reg32_t  RFPCTR5;                       /*  RFPCTR5         */
-    union iodefine_reg32_t  RFPCTR6;                       /*  RFPCTR6         */
-    union iodefine_reg32_t  RFPCTR7;                       /*  RFPCTR7         */
-#define RSCAN0_CFCC0_COUNT 15
-    union iodefine_reg32_t  CFCC0;                         /*  CFCC0           */
-    union iodefine_reg32_t  CFCC1;                         /*  CFCC1           */
-    union iodefine_reg32_t  CFCC2;                         /*  CFCC2           */
-    union iodefine_reg32_t  CFCC3;                         /*  CFCC3           */
-    union iodefine_reg32_t  CFCC4;                         /*  CFCC4           */
-    union iodefine_reg32_t  CFCC5;                         /*  CFCC5           */
-    union iodefine_reg32_t  CFCC6;                         /*  CFCC6           */
-    union iodefine_reg32_t  CFCC7;                         /*  CFCC7           */
-    union iodefine_reg32_t  CFCC8;                         /*  CFCC8           */
-    union iodefine_reg32_t  CFCC9;                         /*  CFCC9           */
-    union iodefine_reg32_t  CFCC10;                        /*  CFCC10          */
-    union iodefine_reg32_t  CFCC11;                        /*  CFCC11          */
-    union iodefine_reg32_t  CFCC12;                        /*  CFCC12          */
-    union iodefine_reg32_t  CFCC13;                        /*  CFCC13          */
-    union iodefine_reg32_t  CFCC14;                        /*  CFCC14          */
-    
-    volatile uint8_t   dummy161[36];                           /*                  */
-#define RSCAN0_CFSTS0_COUNT 15
-    union iodefine_reg32_t  CFSTS0;                        /*  CFSTS0          */
-    union iodefine_reg32_t  CFSTS1;                        /*  CFSTS1          */
-    union iodefine_reg32_t  CFSTS2;                        /*  CFSTS2          */
-    union iodefine_reg32_t  CFSTS3;                        /*  CFSTS3          */
-    union iodefine_reg32_t  CFSTS4;                        /*  CFSTS4          */
-    union iodefine_reg32_t  CFSTS5;                        /*  CFSTS5          */
-    union iodefine_reg32_t  CFSTS6;                        /*  CFSTS6          */
-    union iodefine_reg32_t  CFSTS7;                        /*  CFSTS7          */
-    union iodefine_reg32_t  CFSTS8;                        /*  CFSTS8          */
-    union iodefine_reg32_t  CFSTS9;                        /*  CFSTS9          */
-    union iodefine_reg32_t  CFSTS10;                       /*  CFSTS10         */
-    union iodefine_reg32_t  CFSTS11;                       /*  CFSTS11         */
-    union iodefine_reg32_t  CFSTS12;                       /*  CFSTS12         */
-    union iodefine_reg32_t  CFSTS13;                       /*  CFSTS13         */
-    union iodefine_reg32_t  CFSTS14;                       /*  CFSTS14         */
-    
-    volatile uint8_t   dummy162[36];                           /*                  */
-#define RSCAN0_CFPCTR0_COUNT 15
-    union iodefine_reg32_t  CFPCTR0;                       /*  CFPCTR0         */
-    union iodefine_reg32_t  CFPCTR1;                       /*  CFPCTR1         */
-    union iodefine_reg32_t  CFPCTR2;                       /*  CFPCTR2         */
-    union iodefine_reg32_t  CFPCTR3;                       /*  CFPCTR3         */
-    union iodefine_reg32_t  CFPCTR4;                       /*  CFPCTR4         */
-    union iodefine_reg32_t  CFPCTR5;                       /*  CFPCTR5         */
-    union iodefine_reg32_t  CFPCTR6;                       /*  CFPCTR6         */
-    union iodefine_reg32_t  CFPCTR7;                       /*  CFPCTR7         */
-    union iodefine_reg32_t  CFPCTR8;                       /*  CFPCTR8         */
-    union iodefine_reg32_t  CFPCTR9;                       /*  CFPCTR9         */
-    union iodefine_reg32_t  CFPCTR10;                      /*  CFPCTR10        */
-    union iodefine_reg32_t  CFPCTR11;                      /*  CFPCTR11        */
-    union iodefine_reg32_t  CFPCTR12;                      /*  CFPCTR12        */
-    union iodefine_reg32_t  CFPCTR13;                      /*  CFPCTR13        */
-    union iodefine_reg32_t  CFPCTR14;                      /*  CFPCTR14        */
-    
-    volatile uint8_t   dummy163[36];                           /*                  */
-    union iodefine_reg32_t  FESTS;                         /*  FESTS           */
-    union iodefine_reg32_t  FFSTS;                         /*  FFSTS           */
-    union iodefine_reg32_t  FMSTS;                         /*  FMSTS           */
-    union iodefine_reg32_t  RFISTS;                        /*  RFISTS          */
-    union iodefine_reg32_t  CFRISTS;                       /*  CFRISTS         */
-    union iodefine_reg32_t  CFTISTS;                       /*  CFTISTS         */
-    
-#define RSCAN0_TMC0_COUNT 80
-    volatile uint8_t   TMC0;                                   /*  TMC0            */
-    volatile uint8_t   TMC1;                                   /*  TMC1            */
-    volatile uint8_t   TMC2;                                   /*  TMC2            */
-    volatile uint8_t   TMC3;                                   /*  TMC3            */
-    volatile uint8_t   TMC4;                                   /*  TMC4            */
-    volatile uint8_t   TMC5;                                   /*  TMC5            */
-    volatile uint8_t   TMC6;                                   /*  TMC6            */
-    volatile uint8_t   TMC7;                                   /*  TMC7            */
-    volatile uint8_t   TMC8;                                   /*  TMC8            */
-    volatile uint8_t   TMC9;                                   /*  TMC9            */
-    volatile uint8_t   TMC10;                                  /*  TMC10           */
-    volatile uint8_t   TMC11;                                  /*  TMC11           */
-    volatile uint8_t   TMC12;                                  /*  TMC12           */
-    volatile uint8_t   TMC13;                                  /*  TMC13           */
-    volatile uint8_t   TMC14;                                  /*  TMC14           */
-    volatile uint8_t   TMC15;                                  /*  TMC15           */
-    volatile uint8_t   TMC16;                                  /*  TMC16           */
-    volatile uint8_t   TMC17;                                  /*  TMC17           */
-    volatile uint8_t   TMC18;                                  /*  TMC18           */
-    volatile uint8_t   TMC19;                                  /*  TMC19           */
-    volatile uint8_t   TMC20;                                  /*  TMC20           */
-    volatile uint8_t   TMC21;                                  /*  TMC21           */
-    volatile uint8_t   TMC22;                                  /*  TMC22           */
-    volatile uint8_t   TMC23;                                  /*  TMC23           */
-    volatile uint8_t   TMC24;                                  /*  TMC24           */
-    volatile uint8_t   TMC25;                                  /*  TMC25           */
-    volatile uint8_t   TMC26;                                  /*  TMC26           */
-    volatile uint8_t   TMC27;                                  /*  TMC27           */
-    volatile uint8_t   TMC28;                                  /*  TMC28           */
-    volatile uint8_t   TMC29;                                  /*  TMC29           */
-    volatile uint8_t   TMC30;                                  /*  TMC30           */
-    volatile uint8_t   TMC31;                                  /*  TMC31           */
-    volatile uint8_t   TMC32;                                  /*  TMC32           */
-    volatile uint8_t   TMC33;                                  /*  TMC33           */
-    volatile uint8_t   TMC34;                                  /*  TMC34           */
-    volatile uint8_t   TMC35;                                  /*  TMC35           */
-    volatile uint8_t   TMC36;                                  /*  TMC36           */
-    volatile uint8_t   TMC37;                                  /*  TMC37           */
-    volatile uint8_t   TMC38;                                  /*  TMC38           */
-    volatile uint8_t   TMC39;                                  /*  TMC39           */
-    volatile uint8_t   TMC40;                                  /*  TMC40           */
-    volatile uint8_t   TMC41;                                  /*  TMC41           */
-    volatile uint8_t   TMC42;                                  /*  TMC42           */
-    volatile uint8_t   TMC43;                                  /*  TMC43           */
-    volatile uint8_t   TMC44;                                  /*  TMC44           */
-    volatile uint8_t   TMC45;                                  /*  TMC45           */
-    volatile uint8_t   TMC46;                                  /*  TMC46           */
-    volatile uint8_t   TMC47;                                  /*  TMC47           */
-    volatile uint8_t   TMC48;                                  /*  TMC48           */
-    volatile uint8_t   TMC49;                                  /*  TMC49           */
-    volatile uint8_t   TMC50;                                  /*  TMC50           */
-    volatile uint8_t   TMC51;                                  /*  TMC51           */
-    volatile uint8_t   TMC52;                                  /*  TMC52           */
-    volatile uint8_t   TMC53;                                  /*  TMC53           */
-    volatile uint8_t   TMC54;                                  /*  TMC54           */
-    volatile uint8_t   TMC55;                                  /*  TMC55           */
-    volatile uint8_t   TMC56;                                  /*  TMC56           */
-    volatile uint8_t   TMC57;                                  /*  TMC57           */
-    volatile uint8_t   TMC58;                                  /*  TMC58           */
-    volatile uint8_t   TMC59;                                  /*  TMC59           */
-    volatile uint8_t   TMC60;                                  /*  TMC60           */
-    volatile uint8_t   TMC61;                                  /*  TMC61           */
-    volatile uint8_t   TMC62;                                  /*  TMC62           */
-    volatile uint8_t   TMC63;                                  /*  TMC63           */
-    volatile uint8_t   TMC64;                                  /*  TMC64           */
-    volatile uint8_t   TMC65;                                  /*  TMC65           */
-    volatile uint8_t   TMC66;                                  /*  TMC66           */
-    volatile uint8_t   TMC67;                                  /*  TMC67           */
-    volatile uint8_t   TMC68;                                  /*  TMC68           */
-    volatile uint8_t   TMC69;                                  /*  TMC69           */
-    volatile uint8_t   TMC70;                                  /*  TMC70           */
-    volatile uint8_t   TMC71;                                  /*  TMC71           */
-    volatile uint8_t   TMC72;                                  /*  TMC72           */
-    volatile uint8_t   TMC73;                                  /*  TMC73           */
-    volatile uint8_t   TMC74;                                  /*  TMC74           */
-    volatile uint8_t   TMC75;                                  /*  TMC75           */
-    volatile uint8_t   TMC76;                                  /*  TMC76           */
-    volatile uint8_t   TMC77;                                  /*  TMC77           */
-    volatile uint8_t   TMC78;                                  /*  TMC78           */
-    volatile uint8_t   TMC79;                                  /*  TMC79           */
-    volatile uint8_t   dummy164[48];                           /*                  */
-#define RSCAN0_TMSTS0_COUNT 80
-    volatile uint8_t   TMSTS0;                                 /*  TMSTS0          */
-    volatile uint8_t   TMSTS1;                                 /*  TMSTS1          */
-    volatile uint8_t   TMSTS2;                                 /*  TMSTS2          */
-    volatile uint8_t   TMSTS3;                                 /*  TMSTS3          */
-    volatile uint8_t   TMSTS4;                                 /*  TMSTS4          */
-    volatile uint8_t   TMSTS5;                                 /*  TMSTS5          */
-    volatile uint8_t   TMSTS6;                                 /*  TMSTS6          */
-    volatile uint8_t   TMSTS7;                                 /*  TMSTS7          */
-    volatile uint8_t   TMSTS8;                                 /*  TMSTS8          */
-    volatile uint8_t   TMSTS9;                                 /*  TMSTS9          */
-    volatile uint8_t   TMSTS10;                                /*  TMSTS10         */
-    volatile uint8_t   TMSTS11;                                /*  TMSTS11         */
-    volatile uint8_t   TMSTS12;                                /*  TMSTS12         */
-    volatile uint8_t   TMSTS13;                                /*  TMSTS13         */
-    volatile uint8_t   TMSTS14;                                /*  TMSTS14         */
-    volatile uint8_t   TMSTS15;                                /*  TMSTS15         */
-    volatile uint8_t   TMSTS16;                                /*  TMSTS16         */
-    volatile uint8_t   TMSTS17;                                /*  TMSTS17         */
-    volatile uint8_t   TMSTS18;                                /*  TMSTS18         */
-    volatile uint8_t   TMSTS19;                                /*  TMSTS19         */
-    volatile uint8_t   TMSTS20;                                /*  TMSTS20         */
-    volatile uint8_t   TMSTS21;                                /*  TMSTS21         */
-    volatile uint8_t   TMSTS22;                                /*  TMSTS22         */
-    volatile uint8_t   TMSTS23;                                /*  TMSTS23         */
-    volatile uint8_t   TMSTS24;                                /*  TMSTS24         */
-    volatile uint8_t   TMSTS25;                                /*  TMSTS25         */
-    volatile uint8_t   TMSTS26;                                /*  TMSTS26         */
-    volatile uint8_t   TMSTS27;                                /*  TMSTS27         */
-    volatile uint8_t   TMSTS28;                                /*  TMSTS28         */
-    volatile uint8_t   TMSTS29;                                /*  TMSTS29         */
-    volatile uint8_t   TMSTS30;                                /*  TMSTS30         */
-    volatile uint8_t   TMSTS31;                                /*  TMSTS31         */
-    volatile uint8_t   TMSTS32;                                /*  TMSTS32         */
-    volatile uint8_t   TMSTS33;                                /*  TMSTS33         */
-    volatile uint8_t   TMSTS34;                                /*  TMSTS34         */
-    volatile uint8_t   TMSTS35;                                /*  TMSTS35         */
-    volatile uint8_t   TMSTS36;                                /*  TMSTS36         */
-    volatile uint8_t   TMSTS37;                                /*  TMSTS37         */
-    volatile uint8_t   TMSTS38;                                /*  TMSTS38         */
-    volatile uint8_t   TMSTS39;                                /*  TMSTS39         */
-    volatile uint8_t   TMSTS40;                                /*  TMSTS40         */
-    volatile uint8_t   TMSTS41;                                /*  TMSTS41         */
-    volatile uint8_t   TMSTS42;                                /*  TMSTS42         */
-    volatile uint8_t   TMSTS43;                                /*  TMSTS43         */
-    volatile uint8_t   TMSTS44;                                /*  TMSTS44         */
-    volatile uint8_t   TMSTS45;                                /*  TMSTS45         */
-    volatile uint8_t   TMSTS46;                                /*  TMSTS46         */
-    volatile uint8_t   TMSTS47;                                /*  TMSTS47         */
-    volatile uint8_t   TMSTS48;                                /*  TMSTS48         */
-    volatile uint8_t   TMSTS49;                                /*  TMSTS49         */
-    volatile uint8_t   TMSTS50;                                /*  TMSTS50         */
-    volatile uint8_t   TMSTS51;                                /*  TMSTS51         */
-    volatile uint8_t   TMSTS52;                                /*  TMSTS52         */
-    volatile uint8_t   TMSTS53;                                /*  TMSTS53         */
-    volatile uint8_t   TMSTS54;                                /*  TMSTS54         */
-    volatile uint8_t   TMSTS55;                                /*  TMSTS55         */
-    volatile uint8_t   TMSTS56;                                /*  TMSTS56         */
-    volatile uint8_t   TMSTS57;                                /*  TMSTS57         */
-    volatile uint8_t   TMSTS58;                                /*  TMSTS58         */
-    volatile uint8_t   TMSTS59;                                /*  TMSTS59         */
-    volatile uint8_t   TMSTS60;                                /*  TMSTS60         */
-    volatile uint8_t   TMSTS61;                                /*  TMSTS61         */
-    volatile uint8_t   TMSTS62;                                /*  TMSTS62         */
-    volatile uint8_t   TMSTS63;                                /*  TMSTS63         */
-    volatile uint8_t   TMSTS64;                                /*  TMSTS64         */
-    volatile uint8_t   TMSTS65;                                /*  TMSTS65         */
-    volatile uint8_t   TMSTS66;                                /*  TMSTS66         */
-    volatile uint8_t   TMSTS67;                                /*  TMSTS67         */
-    volatile uint8_t   TMSTS68;                                /*  TMSTS68         */
-    volatile uint8_t   TMSTS69;                                /*  TMSTS69         */
-    volatile uint8_t   TMSTS70;                                /*  TMSTS70         */
-    volatile uint8_t   TMSTS71;                                /*  TMSTS71         */
-    volatile uint8_t   TMSTS72;                                /*  TMSTS72         */
-    volatile uint8_t   TMSTS73;                                /*  TMSTS73         */
-    volatile uint8_t   TMSTS74;                                /*  TMSTS74         */
-    volatile uint8_t   TMSTS75;                                /*  TMSTS75         */
-    volatile uint8_t   TMSTS76;                                /*  TMSTS76         */
-    volatile uint8_t   TMSTS77;                                /*  TMSTS77         */
-    volatile uint8_t   TMSTS78;                                /*  TMSTS78         */
-    volatile uint8_t   TMSTS79;                                /*  TMSTS79         */
-    volatile uint8_t   dummy165[48];                           /*                  */
-#define RSCAN0_TMTRSTS0_COUNT 3
-    union iodefine_reg32_t  TMTRSTS0;                      /*  TMTRSTS0        */
-    union iodefine_reg32_t  TMTRSTS1;                      /*  TMTRSTS1        */
-    union iodefine_reg32_t  TMTRSTS2;                      /*  TMTRSTS2        */
-    
-    volatile uint8_t   dummy166[4];                            /*                  */
-#define RSCAN0_TMTARSTS0_COUNT 3
-    union iodefine_reg32_t  TMTARSTS0;                     /*  TMTARSTS0       */
-    union iodefine_reg32_t  TMTARSTS1;                     /*  TMTARSTS1       */
-    union iodefine_reg32_t  TMTARSTS2;                     /*  TMTARSTS2       */
-    
-    volatile uint8_t   dummy167[4];                            /*                  */
-#define RSCAN0_TMTCSTS0_COUNT 3
-    union iodefine_reg32_t  TMTCSTS0;                      /*  TMTCSTS0        */
-    union iodefine_reg32_t  TMTCSTS1;                      /*  TMTCSTS1        */
-    union iodefine_reg32_t  TMTCSTS2;                      /*  TMTCSTS2        */
-    
-    volatile uint8_t   dummy168[4];                            /*                  */
-#define RSCAN0_TMTASTS0_COUNT 3
-    union iodefine_reg32_t  TMTASTS0;                      /*  TMTASTS0        */
-    union iodefine_reg32_t  TMTASTS1;                      /*  TMTASTS1        */
-    union iodefine_reg32_t  TMTASTS2;                      /*  TMTASTS2        */
-    
-    volatile uint8_t   dummy169[4];                            /*                  */
-#define RSCAN0_TMIEC0_COUNT 3
-    union iodefine_reg32_t  TMIEC0;                        /*  TMIEC0          */
-    union iodefine_reg32_t  TMIEC1;                        /*  TMIEC1          */
-    union iodefine_reg32_t  TMIEC2;                        /*  TMIEC2          */
-    
-    volatile uint8_t   dummy170[4];                            /*                  */
-#define RSCAN0_TXQCC0_COUNT 5
-    union iodefine_reg32_t  TXQCC0;                        /*  TXQCC0          */
-    union iodefine_reg32_t  TXQCC1;                        /*  TXQCC1          */
-    union iodefine_reg32_t  TXQCC2;                        /*  TXQCC2          */
-    union iodefine_reg32_t  TXQCC3;                        /*  TXQCC3          */
-    union iodefine_reg32_t  TXQCC4;                        /*  TXQCC4          */
-    
-    volatile uint8_t   dummy171[12];                           /*                  */
-#define RSCAN0_TXQSTS0_COUNT 5
-    union iodefine_reg32_t  TXQSTS0;                       /*  TXQSTS0         */
-    union iodefine_reg32_t  TXQSTS1;                       /*  TXQSTS1         */
-    union iodefine_reg32_t  TXQSTS2;                       /*  TXQSTS2         */
-    union iodefine_reg32_t  TXQSTS3;                       /*  TXQSTS3         */
-    union iodefine_reg32_t  TXQSTS4;                       /*  TXQSTS4         */
-    
-    volatile uint8_t   dummy172[12];                           /*                  */
-#define RSCAN0_TXQPCTR0_COUNT 5
-    union iodefine_reg32_t  TXQPCTR0;                      /*  TXQPCTR0        */
-    union iodefine_reg32_t  TXQPCTR1;                      /*  TXQPCTR1        */
-    union iodefine_reg32_t  TXQPCTR2;                      /*  TXQPCTR2        */
-    union iodefine_reg32_t  TXQPCTR3;                      /*  TXQPCTR3        */
-    union iodefine_reg32_t  TXQPCTR4;                      /*  TXQPCTR4        */
-    
-    volatile uint8_t   dummy173[12];                           /*                  */
-#define RSCAN0_THLCC0_COUNT 5
-    union iodefine_reg32_t  THLCC0;                        /*  THLCC0          */
-    union iodefine_reg32_t  THLCC1;                        /*  THLCC1          */
-    union iodefine_reg32_t  THLCC2;                        /*  THLCC2          */
-    union iodefine_reg32_t  THLCC3;                        /*  THLCC3          */
-    union iodefine_reg32_t  THLCC4;                        /*  THLCC4          */
-    
-    volatile uint8_t   dummy174[12];                           /*                  */
-#define RSCAN0_THLSTS0_COUNT 5
-    union iodefine_reg32_t  THLSTS0;                       /*  THLSTS0         */
-    union iodefine_reg32_t  THLSTS1;                       /*  THLSTS1         */
-    union iodefine_reg32_t  THLSTS2;                       /*  THLSTS2         */
-    union iodefine_reg32_t  THLSTS3;                       /*  THLSTS3         */
-    union iodefine_reg32_t  THLSTS4;                       /*  THLSTS4         */
-    
-    volatile uint8_t   dummy175[12];                           /*                  */
-#define RSCAN0_THLPCTR0_COUNT 5
-    union iodefine_reg32_t  THLPCTR0;                      /*  THLPCTR0        */
-    union iodefine_reg32_t  THLPCTR1;                      /*  THLPCTR1        */
-    union iodefine_reg32_t  THLPCTR2;                      /*  THLPCTR2        */
-    union iodefine_reg32_t  THLPCTR3;                      /*  THLPCTR3        */
-    union iodefine_reg32_t  THLPCTR4;                      /*  THLPCTR4        */
-    
-    volatile uint8_t   dummy176[12];                           /*                  */
-#define RSCAN0_GTINTSTS0_COUNT 2
-    union iodefine_reg32_t  GTINTSTS0;                     /*  GTINTSTS0       */
-    union iodefine_reg32_t  GTINTSTS1;                     /*  GTINTSTS1       */
-    union iodefine_reg32_t  GTSTCFG;                       /*  GTSTCFG         */
-    union iodefine_reg32_t  GTSTCTR;                       /*  GTSTCTR         */
-    
-    volatile uint8_t   dummy177[12];                           /*                  */
-    union iodefine_reg32_16_t  GLOCKK;                     /*  GLOCKK          */
-    
-    volatile uint8_t   dummy178[128];                          /*                  */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID0;                       /*  GAFLID0         */
-    union iodefine_reg32_t  GAFLM0;                        /*  GAFLM0          */
-    union iodefine_reg32_t  GAFLP00;                       /*  GAFLP00         */
-    union iodefine_reg32_t  GAFLP10;                       /*  GAFLP10         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID1;                       /*  GAFLID1         */
-    union iodefine_reg32_t  GAFLM1;                        /*  GAFLM1          */
-    union iodefine_reg32_t  GAFLP01;                       /*  GAFLP01         */
-    union iodefine_reg32_t  GAFLP11;                       /*  GAFLP11         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID2;                       /*  GAFLID2         */
-    union iodefine_reg32_t  GAFLM2;                        /*  GAFLM2          */
-    union iodefine_reg32_t  GAFLP02;                       /*  GAFLP02         */
-    union iodefine_reg32_t  GAFLP12;                       /*  GAFLP12         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID3;                       /*  GAFLID3         */
-    union iodefine_reg32_t  GAFLM3;                        /*  GAFLM3          */
-    union iodefine_reg32_t  GAFLP03;                       /*  GAFLP03         */
-    union iodefine_reg32_t  GAFLP13;                       /*  GAFLP13         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID4;                       /*  GAFLID4         */
-    union iodefine_reg32_t  GAFLM4;                        /*  GAFLM4          */
-    union iodefine_reg32_t  GAFLP04;                       /*  GAFLP04         */
-    union iodefine_reg32_t  GAFLP14;                       /*  GAFLP14         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID5;                       /*  GAFLID5         */
-    union iodefine_reg32_t  GAFLM5;                        /*  GAFLM5          */
-    union iodefine_reg32_t  GAFLP05;                       /*  GAFLP05         */
-    union iodefine_reg32_t  GAFLP15;                       /*  GAFLP15         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID6;                       /*  GAFLID6         */
-    union iodefine_reg32_t  GAFLM6;                        /*  GAFLM6          */
-    union iodefine_reg32_t  GAFLP06;                       /*  GAFLP06         */
-    union iodefine_reg32_t  GAFLP16;                       /*  GAFLP16         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID7;                       /*  GAFLID7         */
-    union iodefine_reg32_t  GAFLM7;                        /*  GAFLM7          */
-    union iodefine_reg32_t  GAFLP07;                       /*  GAFLP07         */
-    union iodefine_reg32_t  GAFLP17;                       /*  GAFLP17         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID8;                       /*  GAFLID8         */
-    union iodefine_reg32_t  GAFLM8;                        /*  GAFLM8          */
-    union iodefine_reg32_t  GAFLP08;                       /*  GAFLP08         */
-    union iodefine_reg32_t  GAFLP18;                       /*  GAFLP18         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID9;                       /*  GAFLID9         */
-    union iodefine_reg32_t  GAFLM9;                        /*  GAFLM9          */
-    union iodefine_reg32_t  GAFLP09;                       /*  GAFLP09         */
-    union iodefine_reg32_t  GAFLP19;                       /*  GAFLP19         */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID10;                      /*  GAFLID10        */
-    union iodefine_reg32_t  GAFLM10;                       /*  GAFLM10         */
-    union iodefine_reg32_t  GAFLP010;                      /*  GAFLP010        */
-    union iodefine_reg32_t  GAFLP110;                      /*  GAFLP110        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID11;                      /*  GAFLID11        */
-    union iodefine_reg32_t  GAFLM11;                       /*  GAFLM11         */
-    union iodefine_reg32_t  GAFLP011;                      /*  GAFLP011        */
-    union iodefine_reg32_t  GAFLP111;                      /*  GAFLP111        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID12;                      /*  GAFLID12        */
-    union iodefine_reg32_t  GAFLM12;                       /*  GAFLM12         */
-    union iodefine_reg32_t  GAFLP012;                      /*  GAFLP012        */
-    union iodefine_reg32_t  GAFLP112;                      /*  GAFLP112        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID13;                      /*  GAFLID13        */
-    union iodefine_reg32_t  GAFLM13;                       /*  GAFLM13         */
-    union iodefine_reg32_t  GAFLP013;                      /*  GAFLP013        */
-    union iodefine_reg32_t  GAFLP113;                      /*  GAFLP113        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID14;                      /*  GAFLID14        */
-    union iodefine_reg32_t  GAFLM14;                       /*  GAFLM14         */
-    union iodefine_reg32_t  GAFLP014;                      /*  GAFLP014        */
-    union iodefine_reg32_t  GAFLP114;                      /*  GAFLP114        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0gaflidj */
-    union iodefine_reg32_t  GAFLID15;                      /*  GAFLID15        */
-    union iodefine_reg32_t  GAFLM15;                       /*  GAFLM15         */
-    union iodefine_reg32_t  GAFLP015;                      /*  GAFLP015        */
-    union iodefine_reg32_t  GAFLP115;                      /*  GAFLP115        */
-/* end of struct st_rscan_from_rscan0gaflidj */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID0;                         /*  RMID0           */
-    union iodefine_reg32_t  RMPTR0;                        /*  RMPTR0          */
-    union iodefine_reg32_t  RMDF00;                        /*  RMDF00          */
-    union iodefine_reg32_t  RMDF10;                        /*  RMDF10          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID1;                         /*  RMID1           */
-    union iodefine_reg32_t  RMPTR1;                        /*  RMPTR1          */
-    union iodefine_reg32_t  RMDF01;                        /*  RMDF01          */
-    union iodefine_reg32_t  RMDF11;                        /*  RMDF11          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID2;                         /*  RMID2           */
-    union iodefine_reg32_t  RMPTR2;                        /*  RMPTR2          */
-    union iodefine_reg32_t  RMDF02;                        /*  RMDF02          */
-    union iodefine_reg32_t  RMDF12;                        /*  RMDF12          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID3;                         /*  RMID3           */
-    union iodefine_reg32_t  RMPTR3;                        /*  RMPTR3          */
-    union iodefine_reg32_t  RMDF03;                        /*  RMDF03          */
-    union iodefine_reg32_t  RMDF13;                        /*  RMDF13          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID4;                         /*  RMID4           */
-    union iodefine_reg32_t  RMPTR4;                        /*  RMPTR4          */
-    union iodefine_reg32_t  RMDF04;                        /*  RMDF04          */
-    union iodefine_reg32_t  RMDF14;                        /*  RMDF14          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID5;                         /*  RMID5           */
-    union iodefine_reg32_t  RMPTR5;                        /*  RMPTR5          */
-    union iodefine_reg32_t  RMDF05;                        /*  RMDF05          */
-    union iodefine_reg32_t  RMDF15;                        /*  RMDF15          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID6;                         /*  RMID6           */
-    union iodefine_reg32_t  RMPTR6;                        /*  RMPTR6          */
-    union iodefine_reg32_t  RMDF06;                        /*  RMDF06          */
-    union iodefine_reg32_t  RMDF16;                        /*  RMDF16          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID7;                         /*  RMID7           */
-    union iodefine_reg32_t  RMPTR7;                        /*  RMPTR7          */
-    union iodefine_reg32_t  RMDF07;                        /*  RMDF07          */
-    union iodefine_reg32_t  RMDF17;                        /*  RMDF17          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID8;                         /*  RMID8           */
-    union iodefine_reg32_t  RMPTR8;                        /*  RMPTR8          */
-    union iodefine_reg32_t  RMDF08;                        /*  RMDF08          */
-    union iodefine_reg32_t  RMDF18;                        /*  RMDF18          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID9;                         /*  RMID9           */
-    union iodefine_reg32_t  RMPTR9;                        /*  RMPTR9          */
-    union iodefine_reg32_t  RMDF09;                        /*  RMDF09          */
-    union iodefine_reg32_t  RMDF19;                        /*  RMDF19          */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID10;                        /*  RMID10          */
-    union iodefine_reg32_t  RMPTR10;                       /*  RMPTR10         */
-    union iodefine_reg32_t  RMDF010;                       /*  RMDF010         */
-    union iodefine_reg32_t  RMDF110;                       /*  RMDF110         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID11;                        /*  RMID11          */
-    union iodefine_reg32_t  RMPTR11;                       /*  RMPTR11         */
-    union iodefine_reg32_t  RMDF011;                       /*  RMDF011         */
-    union iodefine_reg32_t  RMDF111;                       /*  RMDF111         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID12;                        /*  RMID12          */
-    union iodefine_reg32_t  RMPTR12;                       /*  RMPTR12         */
-    union iodefine_reg32_t  RMDF012;                       /*  RMDF012         */
-    union iodefine_reg32_t  RMDF112;                       /*  RMDF112         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID13;                        /*  RMID13          */
-    union iodefine_reg32_t  RMPTR13;                       /*  RMPTR13         */
-    union iodefine_reg32_t  RMDF013;                       /*  RMDF013         */
-    union iodefine_reg32_t  RMDF113;                       /*  RMDF113         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID14;                        /*  RMID14          */
-    union iodefine_reg32_t  RMPTR14;                       /*  RMPTR14         */
-    union iodefine_reg32_t  RMDF014;                       /*  RMDF014         */
-    union iodefine_reg32_t  RMDF114;                       /*  RMDF114         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID15;                        /*  RMID15          */
-    union iodefine_reg32_t  RMPTR15;                       /*  RMPTR15         */
-    union iodefine_reg32_t  RMDF015;                       /*  RMDF015         */
-    union iodefine_reg32_t  RMDF115;                       /*  RMDF115         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID16;                        /*  RMID16          */
-    union iodefine_reg32_t  RMPTR16;                       /*  RMPTR16         */
-    union iodefine_reg32_t  RMDF016;                       /*  RMDF016         */
-    union iodefine_reg32_t  RMDF116;                       /*  RMDF116         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID17;                        /*  RMID17          */
-    union iodefine_reg32_t  RMPTR17;                       /*  RMPTR17         */
-    union iodefine_reg32_t  RMDF017;                       /*  RMDF017         */
-    union iodefine_reg32_t  RMDF117;                       /*  RMDF117         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID18;                        /*  RMID18          */
-    union iodefine_reg32_t  RMPTR18;                       /*  RMPTR18         */
-    union iodefine_reg32_t  RMDF018;                       /*  RMDF018         */
-    union iodefine_reg32_t  RMDF118;                       /*  RMDF118         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID19;                        /*  RMID19          */
-    union iodefine_reg32_t  RMPTR19;                       /*  RMPTR19         */
-    union iodefine_reg32_t  RMDF019;                       /*  RMDF019         */
-    union iodefine_reg32_t  RMDF119;                       /*  RMDF119         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID20;                        /*  RMID20          */
-    union iodefine_reg32_t  RMPTR20;                       /*  RMPTR20         */
-    union iodefine_reg32_t  RMDF020;                       /*  RMDF020         */
-    union iodefine_reg32_t  RMDF120;                       /*  RMDF120         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID21;                        /*  RMID21          */
-    union iodefine_reg32_t  RMPTR21;                       /*  RMPTR21         */
-    union iodefine_reg32_t  RMDF021;                       /*  RMDF021         */
-    union iodefine_reg32_t  RMDF121;                       /*  RMDF121         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID22;                        /*  RMID22          */
-    union iodefine_reg32_t  RMPTR22;                       /*  RMPTR22         */
-    union iodefine_reg32_t  RMDF022;                       /*  RMDF022         */
-    union iodefine_reg32_t  RMDF122;                       /*  RMDF122         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID23;                        /*  RMID23          */
-    union iodefine_reg32_t  RMPTR23;                       /*  RMPTR23         */
-    union iodefine_reg32_t  RMDF023;                       /*  RMDF023         */
-    union iodefine_reg32_t  RMDF123;                       /*  RMDF123         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID24;                        /*  RMID24          */
-    union iodefine_reg32_t  RMPTR24;                       /*  RMPTR24         */
-    union iodefine_reg32_t  RMDF024;                       /*  RMDF024         */
-    union iodefine_reg32_t  RMDF124;                       /*  RMDF124         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID25;                        /*  RMID25          */
-    union iodefine_reg32_t  RMPTR25;                       /*  RMPTR25         */
-    union iodefine_reg32_t  RMDF025;                       /*  RMDF025         */
-    union iodefine_reg32_t  RMDF125;                       /*  RMDF125         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID26;                        /*  RMID26          */
-    union iodefine_reg32_t  RMPTR26;                       /*  RMPTR26         */
-    union iodefine_reg32_t  RMDF026;                       /*  RMDF026         */
-    union iodefine_reg32_t  RMDF126;                       /*  RMDF126         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID27;                        /*  RMID27          */
-    union iodefine_reg32_t  RMPTR27;                       /*  RMPTR27         */
-    union iodefine_reg32_t  RMDF027;                       /*  RMDF027         */
-    union iodefine_reg32_t  RMDF127;                       /*  RMDF127         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID28;                        /*  RMID28          */
-    union iodefine_reg32_t  RMPTR28;                       /*  RMPTR28         */
-    union iodefine_reg32_t  RMDF028;                       /*  RMDF028         */
-    union iodefine_reg32_t  RMDF128;                       /*  RMDF128         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID29;                        /*  RMID29          */
-    union iodefine_reg32_t  RMPTR29;                       /*  RMPTR29         */
-    union iodefine_reg32_t  RMDF029;                       /*  RMDF029         */
-    union iodefine_reg32_t  RMDF129;                       /*  RMDF129         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID30;                        /*  RMID30          */
-    union iodefine_reg32_t  RMPTR30;                       /*  RMPTR30         */
-    union iodefine_reg32_t  RMDF030;                       /*  RMDF030         */
-    union iodefine_reg32_t  RMDF130;                       /*  RMDF130         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID31;                        /*  RMID31          */
-    union iodefine_reg32_t  RMPTR31;                       /*  RMPTR31         */
-    union iodefine_reg32_t  RMDF031;                       /*  RMDF031         */
-    union iodefine_reg32_t  RMDF131;                       /*  RMDF131         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID32;                        /*  RMID32          */
-    union iodefine_reg32_t  RMPTR32;                       /*  RMPTR32         */
-    union iodefine_reg32_t  RMDF032;                       /*  RMDF032         */
-    union iodefine_reg32_t  RMDF132;                       /*  RMDF132         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID33;                        /*  RMID33          */
-    union iodefine_reg32_t  RMPTR33;                       /*  RMPTR33         */
-    union iodefine_reg32_t  RMDF033;                       /*  RMDF033         */
-    union iodefine_reg32_t  RMDF133;                       /*  RMDF133         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID34;                        /*  RMID34          */
-    union iodefine_reg32_t  RMPTR34;                       /*  RMPTR34         */
-    union iodefine_reg32_t  RMDF034;                       /*  RMDF034         */
-    union iodefine_reg32_t  RMDF134;                       /*  RMDF134         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID35;                        /*  RMID35          */
-    union iodefine_reg32_t  RMPTR35;                       /*  RMPTR35         */
-    union iodefine_reg32_t  RMDF035;                       /*  RMDF035         */
-    union iodefine_reg32_t  RMDF135;                       /*  RMDF135         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID36;                        /*  RMID36          */
-    union iodefine_reg32_t  RMPTR36;                       /*  RMPTR36         */
-    union iodefine_reg32_t  RMDF036;                       /*  RMDF036         */
-    union iodefine_reg32_t  RMDF136;                       /*  RMDF136         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID37;                        /*  RMID37          */
-    union iodefine_reg32_t  RMPTR37;                       /*  RMPTR37         */
-    union iodefine_reg32_t  RMDF037;                       /*  RMDF037         */
-    union iodefine_reg32_t  RMDF137;                       /*  RMDF137         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID38;                        /*  RMID38          */
-    union iodefine_reg32_t  RMPTR38;                       /*  RMPTR38         */
-    union iodefine_reg32_t  RMDF038;                       /*  RMDF038         */
-    union iodefine_reg32_t  RMDF138;                       /*  RMDF138         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID39;                        /*  RMID39          */
-    union iodefine_reg32_t  RMPTR39;                       /*  RMPTR39         */
-    union iodefine_reg32_t  RMDF039;                       /*  RMDF039         */
-    union iodefine_reg32_t  RMDF139;                       /*  RMDF139         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID40;                        /*  RMID40          */
-    union iodefine_reg32_t  RMPTR40;                       /*  RMPTR40         */
-    union iodefine_reg32_t  RMDF040;                       /*  RMDF040         */
-    union iodefine_reg32_t  RMDF140;                       /*  RMDF140         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID41;                        /*  RMID41          */
-    union iodefine_reg32_t  RMPTR41;                       /*  RMPTR41         */
-    union iodefine_reg32_t  RMDF041;                       /*  RMDF041         */
-    union iodefine_reg32_t  RMDF141;                       /*  RMDF141         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID42;                        /*  RMID42          */
-    union iodefine_reg32_t  RMPTR42;                       /*  RMPTR42         */
-    union iodefine_reg32_t  RMDF042;                       /*  RMDF042         */
-    union iodefine_reg32_t  RMDF142;                       /*  RMDF142         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID43;                        /*  RMID43          */
-    union iodefine_reg32_t  RMPTR43;                       /*  RMPTR43         */
-    union iodefine_reg32_t  RMDF043;                       /*  RMDF043         */
-    union iodefine_reg32_t  RMDF143;                       /*  RMDF143         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID44;                        /*  RMID44          */
-    union iodefine_reg32_t  RMPTR44;                       /*  RMPTR44         */
-    union iodefine_reg32_t  RMDF044;                       /*  RMDF044         */
-    union iodefine_reg32_t  RMDF144;                       /*  RMDF144         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID45;                        /*  RMID45          */
-    union iodefine_reg32_t  RMPTR45;                       /*  RMPTR45         */
-    union iodefine_reg32_t  RMDF045;                       /*  RMDF045         */
-    union iodefine_reg32_t  RMDF145;                       /*  RMDF145         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID46;                        /*  RMID46          */
-    union iodefine_reg32_t  RMPTR46;                       /*  RMPTR46         */
-    union iodefine_reg32_t  RMDF046;                       /*  RMDF046         */
-    union iodefine_reg32_t  RMDF146;                       /*  RMDF146         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID47;                        /*  RMID47          */
-    union iodefine_reg32_t  RMPTR47;                       /*  RMPTR47         */
-    union iodefine_reg32_t  RMDF047;                       /*  RMDF047         */
-    union iodefine_reg32_t  RMDF147;                       /*  RMDF147         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID48;                        /*  RMID48          */
-    union iodefine_reg32_t  RMPTR48;                       /*  RMPTR48         */
-    union iodefine_reg32_t  RMDF048;                       /*  RMDF048         */
-    union iodefine_reg32_t  RMDF148;                       /*  RMDF148         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID49;                        /*  RMID49          */
-    union iodefine_reg32_t  RMPTR49;                       /*  RMPTR49         */
-    union iodefine_reg32_t  RMDF049;                       /*  RMDF049         */
-    union iodefine_reg32_t  RMDF149;                       /*  RMDF149         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID50;                        /*  RMID50          */
-    union iodefine_reg32_t  RMPTR50;                       /*  RMPTR50         */
-    union iodefine_reg32_t  RMDF050;                       /*  RMDF050         */
-    union iodefine_reg32_t  RMDF150;                       /*  RMDF150         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID51;                        /*  RMID51          */
-    union iodefine_reg32_t  RMPTR51;                       /*  RMPTR51         */
-    union iodefine_reg32_t  RMDF051;                       /*  RMDF051         */
-    union iodefine_reg32_t  RMDF151;                       /*  RMDF151         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID52;                        /*  RMID52          */
-    union iodefine_reg32_t  RMPTR52;                       /*  RMPTR52         */
-    union iodefine_reg32_t  RMDF052;                       /*  RMDF052         */
-    union iodefine_reg32_t  RMDF152;                       /*  RMDF152         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID53;                        /*  RMID53          */
-    union iodefine_reg32_t  RMPTR53;                       /*  RMPTR53         */
-    union iodefine_reg32_t  RMDF053;                       /*  RMDF053         */
-    union iodefine_reg32_t  RMDF153;                       /*  RMDF153         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID54;                        /*  RMID54          */
-    union iodefine_reg32_t  RMPTR54;                       /*  RMPTR54         */
-    union iodefine_reg32_t  RMDF054;                       /*  RMDF054         */
-    union iodefine_reg32_t  RMDF154;                       /*  RMDF154         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID55;                        /*  RMID55          */
-    union iodefine_reg32_t  RMPTR55;                       /*  RMPTR55         */
-    union iodefine_reg32_t  RMDF055;                       /*  RMDF055         */
-    union iodefine_reg32_t  RMDF155;                       /*  RMDF155         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID56;                        /*  RMID56          */
-    union iodefine_reg32_t  RMPTR56;                       /*  RMPTR56         */
-    union iodefine_reg32_t  RMDF056;                       /*  RMDF056         */
-    union iodefine_reg32_t  RMDF156;                       /*  RMDF156         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID57;                        /*  RMID57          */
-    union iodefine_reg32_t  RMPTR57;                       /*  RMPTR57         */
-    union iodefine_reg32_t  RMDF057;                       /*  RMDF057         */
-    union iodefine_reg32_t  RMDF157;                       /*  RMDF157         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID58;                        /*  RMID58          */
-    union iodefine_reg32_t  RMPTR58;                       /*  RMPTR58         */
-    union iodefine_reg32_t  RMDF058;                       /*  RMDF058         */
-    union iodefine_reg32_t  RMDF158;                       /*  RMDF158         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID59;                        /*  RMID59          */
-    union iodefine_reg32_t  RMPTR59;                       /*  RMPTR59         */
-    union iodefine_reg32_t  RMDF059;                       /*  RMDF059         */
-    union iodefine_reg32_t  RMDF159;                       /*  RMDF159         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID60;                        /*  RMID60          */
-    union iodefine_reg32_t  RMPTR60;                       /*  RMPTR60         */
-    union iodefine_reg32_t  RMDF060;                       /*  RMDF060         */
-    union iodefine_reg32_t  RMDF160;                       /*  RMDF160         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID61;                        /*  RMID61          */
-    union iodefine_reg32_t  RMPTR61;                       /*  RMPTR61         */
-    union iodefine_reg32_t  RMDF061;                       /*  RMDF061         */
-    union iodefine_reg32_t  RMDF161;                       /*  RMDF161         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID62;                        /*  RMID62          */
-    union iodefine_reg32_t  RMPTR62;                       /*  RMPTR62         */
-    union iodefine_reg32_t  RMDF062;                       /*  RMDF062         */
-    union iodefine_reg32_t  RMDF162;                       /*  RMDF162         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID63;                        /*  RMID63          */
-    union iodefine_reg32_t  RMPTR63;                       /*  RMPTR63         */
-    union iodefine_reg32_t  RMDF063;                       /*  RMDF063         */
-    union iodefine_reg32_t  RMDF163;                       /*  RMDF163         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID64;                        /*  RMID64          */
-    union iodefine_reg32_t  RMPTR64;                       /*  RMPTR64         */
-    union iodefine_reg32_t  RMDF064;                       /*  RMDF064         */
-    union iodefine_reg32_t  RMDF164;                       /*  RMDF164         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID65;                        /*  RMID65          */
-    union iodefine_reg32_t  RMPTR65;                       /*  RMPTR65         */
-    union iodefine_reg32_t  RMDF065;                       /*  RMDF065         */
-    union iodefine_reg32_t  RMDF165;                       /*  RMDF165         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID66;                        /*  RMID66          */
-    union iodefine_reg32_t  RMPTR66;                       /*  RMPTR66         */
-    union iodefine_reg32_t  RMDF066;                       /*  RMDF066         */
-    union iodefine_reg32_t  RMDF166;                       /*  RMDF166         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID67;                        /*  RMID67          */
-    union iodefine_reg32_t  RMPTR67;                       /*  RMPTR67         */
-    union iodefine_reg32_t  RMDF067;                       /*  RMDF067         */
-    union iodefine_reg32_t  RMDF167;                       /*  RMDF167         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID68;                        /*  RMID68          */
-    union iodefine_reg32_t  RMPTR68;                       /*  RMPTR68         */
-    union iodefine_reg32_t  RMDF068;                       /*  RMDF068         */
-    union iodefine_reg32_t  RMDF168;                       /*  RMDF168         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID69;                        /*  RMID69          */
-    union iodefine_reg32_t  RMPTR69;                       /*  RMPTR69         */
-    union iodefine_reg32_t  RMDF069;                       /*  RMDF069         */
-    union iodefine_reg32_t  RMDF169;                       /*  RMDF169         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID70;                        /*  RMID70          */
-    union iodefine_reg32_t  RMPTR70;                       /*  RMPTR70         */
-    union iodefine_reg32_t  RMDF070;                       /*  RMDF070         */
-    union iodefine_reg32_t  RMDF170;                       /*  RMDF170         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID71;                        /*  RMID71          */
-    union iodefine_reg32_t  RMPTR71;                       /*  RMPTR71         */
-    union iodefine_reg32_t  RMDF071;                       /*  RMDF071         */
-    union iodefine_reg32_t  RMDF171;                       /*  RMDF171         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID72;                        /*  RMID72          */
-    union iodefine_reg32_t  RMPTR72;                       /*  RMPTR72         */
-    union iodefine_reg32_t  RMDF072;                       /*  RMDF072         */
-    union iodefine_reg32_t  RMDF172;                       /*  RMDF172         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID73;                        /*  RMID73          */
-    union iodefine_reg32_t  RMPTR73;                       /*  RMPTR73         */
-    union iodefine_reg32_t  RMDF073;                       /*  RMDF073         */
-    union iodefine_reg32_t  RMDF173;                       /*  RMDF173         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID74;                        /*  RMID74          */
-    union iodefine_reg32_t  RMPTR74;                       /*  RMPTR74         */
-    union iodefine_reg32_t  RMDF074;                       /*  RMDF074         */
-    union iodefine_reg32_t  RMDF174;                       /*  RMDF174         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID75;                        /*  RMID75          */
-    union iodefine_reg32_t  RMPTR75;                       /*  RMPTR75         */
-    union iodefine_reg32_t  RMDF075;                       /*  RMDF075         */
-    union iodefine_reg32_t  RMDF175;                       /*  RMDF175         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID76;                        /*  RMID76          */
-    union iodefine_reg32_t  RMPTR76;                       /*  RMPTR76         */
-    union iodefine_reg32_t  RMDF076;                       /*  RMDF076         */
-    union iodefine_reg32_t  RMDF176;                       /*  RMDF176         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID77;                        /*  RMID77          */
-    union iodefine_reg32_t  RMPTR77;                       /*  RMPTR77         */
-    union iodefine_reg32_t  RMDF077;                       /*  RMDF077         */
-    union iodefine_reg32_t  RMDF177;                       /*  RMDF177         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID78;                        /*  RMID78          */
-    union iodefine_reg32_t  RMPTR78;                       /*  RMPTR78         */
-    union iodefine_reg32_t  RMDF078;                       /*  RMDF078         */
-    union iodefine_reg32_t  RMDF178;                       /*  RMDF178         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-/* start of struct st_rscan_from_rscan0rmidp */
-    union iodefine_reg32_t  RMID79;                        /*  RMID79          */
-    union iodefine_reg32_t  RMPTR79;                       /*  RMPTR79         */
-    union iodefine_reg32_t  RMDF079;                       /*  RMDF079         */
-    union iodefine_reg32_t  RMDF179;                       /*  RMDF179         */
-/* end of struct st_rscan_from_rscan0rmidp */
-    
-    volatile uint8_t   dummy179[768];                          /*                  */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID0;                         /*  RFID0           */
-    union iodefine_reg32_t  RFPTR0;                        /*  RFPTR0          */
-    union iodefine_reg32_t  RFDF00;                        /*  RFDF00          */
-    union iodefine_reg32_t  RFDF10;                        /*  RFDF10          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID1;                         /*  RFID1           */
-    union iodefine_reg32_t  RFPTR1;                        /*  RFPTR1          */
-    union iodefine_reg32_t  RFDF01;                        /*  RFDF01          */
-    union iodefine_reg32_t  RFDF11;                        /*  RFDF11          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID2;                         /*  RFID2           */
-    union iodefine_reg32_t  RFPTR2;                        /*  RFPTR2          */
-    union iodefine_reg32_t  RFDF02;                        /*  RFDF02          */
-    union iodefine_reg32_t  RFDF12;                        /*  RFDF12          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID3;                         /*  RFID3           */
-    union iodefine_reg32_t  RFPTR3;                        /*  RFPTR3          */
-    union iodefine_reg32_t  RFDF03;                        /*  RFDF03          */
-    union iodefine_reg32_t  RFDF13;                        /*  RFDF13          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID4;                         /*  RFID4           */
-    union iodefine_reg32_t  RFPTR4;                        /*  RFPTR4          */
-    union iodefine_reg32_t  RFDF04;                        /*  RFDF04          */
-    union iodefine_reg32_t  RFDF14;                        /*  RFDF14          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID5;                         /*  RFID5           */
-    union iodefine_reg32_t  RFPTR5;                        /*  RFPTR5          */
-    union iodefine_reg32_t  RFDF05;                        /*  RFDF05          */
-    union iodefine_reg32_t  RFDF15;                        /*  RFDF15          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID6;                         /*  RFID6           */
-    union iodefine_reg32_t  RFPTR6;                        /*  RFPTR6          */
-    union iodefine_reg32_t  RFDF06;                        /*  RFDF06          */
-    union iodefine_reg32_t  RFDF16;                        /*  RFDF16          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0rfidm */
-    union iodefine_reg32_t  RFID7;                         /*  RFID7           */
-    union iodefine_reg32_t  RFPTR7;                        /*  RFPTR7          */
-    union iodefine_reg32_t  RFDF07;                        /*  RFDF07          */
-    union iodefine_reg32_t  RFDF17;                        /*  RFDF17          */
-/* end of struct st_rscan_from_rscan0rfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID0;                         /*  CFID0           */
-    union iodefine_reg32_t  CFPTR0;                        /*  CFPTR0          */
-    union iodefine_reg32_t  CFDF00;                        /*  CFDF00          */
-    union iodefine_reg32_t  CFDF10;                        /*  CFDF10          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID1;                         /*  CFID1           */
-    union iodefine_reg32_t  CFPTR1;                        /*  CFPTR1          */
-    union iodefine_reg32_t  CFDF01;                        /*  CFDF01          */
-    union iodefine_reg32_t  CFDF11;                        /*  CFDF11          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID2;                         /*  CFID2           */
-    union iodefine_reg32_t  CFPTR2;                        /*  CFPTR2          */
-    union iodefine_reg32_t  CFDF02;                        /*  CFDF02          */
-    union iodefine_reg32_t  CFDF12;                        /*  CFDF12          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID3;                         /*  CFID3           */
-    union iodefine_reg32_t  CFPTR3;                        /*  CFPTR3          */
-    union iodefine_reg32_t  CFDF03;                        /*  CFDF03          */
-    union iodefine_reg32_t  CFDF13;                        /*  CFDF13          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID4;                         /*  CFID4           */
-    union iodefine_reg32_t  CFPTR4;                        /*  CFPTR4          */
-    union iodefine_reg32_t  CFDF04;                        /*  CFDF04          */
-    union iodefine_reg32_t  CFDF14;                        /*  CFDF14          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID5;                         /*  CFID5           */
-    union iodefine_reg32_t  CFPTR5;                        /*  CFPTR5          */
-    union iodefine_reg32_t  CFDF05;                        /*  CFDF05          */
-    union iodefine_reg32_t  CFDF15;                        /*  CFDF15          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID6;                         /*  CFID6           */
-    union iodefine_reg32_t  CFPTR6;                        /*  CFPTR6          */
-    union iodefine_reg32_t  CFDF06;                        /*  CFDF06          */
-    union iodefine_reg32_t  CFDF16;                        /*  CFDF16          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID7;                         /*  CFID7           */
-    union iodefine_reg32_t  CFPTR7;                        /*  CFPTR7          */
-    union iodefine_reg32_t  CFDF07;                        /*  CFDF07          */
-    union iodefine_reg32_t  CFDF17;                        /*  CFDF17          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID8;                         /*  CFID8           */
-    union iodefine_reg32_t  CFPTR8;                        /*  CFPTR8          */
-    union iodefine_reg32_t  CFDF08;                        /*  CFDF08          */
-    union iodefine_reg32_t  CFDF18;                        /*  CFDF18          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID9;                         /*  CFID9           */
-    union iodefine_reg32_t  CFPTR9;                        /*  CFPTR9          */
-    union iodefine_reg32_t  CFDF09;                        /*  CFDF09          */
-    union iodefine_reg32_t  CFDF19;                        /*  CFDF19          */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID10;                        /*  CFID10          */
-    union iodefine_reg32_t  CFPTR10;                       /*  CFPTR10         */
-    union iodefine_reg32_t  CFDF010;                       /*  CFDF010         */
-    union iodefine_reg32_t  CFDF110;                       /*  CFDF110         */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID11;                        /*  CFID11          */
-    union iodefine_reg32_t  CFPTR11;                       /*  CFPTR11         */
-    union iodefine_reg32_t  CFDF011;                       /*  CFDF011         */
-    union iodefine_reg32_t  CFDF111;                       /*  CFDF111         */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID12;                        /*  CFID12          */
-    union iodefine_reg32_t  CFPTR12;                       /*  CFPTR12         */
-    union iodefine_reg32_t  CFDF012;                       /*  CFDF012         */
-    union iodefine_reg32_t  CFDF112;                       /*  CFDF112         */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID13;                        /*  CFID13          */
-    union iodefine_reg32_t  CFPTR13;                       /*  CFPTR13         */
-    union iodefine_reg32_t  CFDF013;                       /*  CFDF013         */
-    union iodefine_reg32_t  CFDF113;                       /*  CFDF113         */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-/* start of struct st_rscan_from_rscan0cfidm */
-    union iodefine_reg32_t  CFID14;                        /*  CFID14          */
-    union iodefine_reg32_t  CFPTR14;                       /*  CFPTR14         */
-    union iodefine_reg32_t  CFDF014;                       /*  CFDF014         */
-    union iodefine_reg32_t  CFDF114;                       /*  CFDF114         */
-/* end of struct st_rscan_from_rscan0cfidm */
-    
-    volatile uint8_t   dummy180[144];                          /*                  */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID0;                         /*  TMID0           */
-    union iodefine_reg32_t  TMPTR0;                        /*  TMPTR0          */
-    union iodefine_reg32_t  TMDF00;                        /*  TMDF00          */
-    union iodefine_reg32_t  TMDF10;                        /*  TMDF10          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID1;                         /*  TMID1           */
-    union iodefine_reg32_t  TMPTR1;                        /*  TMPTR1          */
-    union iodefine_reg32_t  TMDF01;                        /*  TMDF01          */
-    union iodefine_reg32_t  TMDF11;                        /*  TMDF11          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID2;                         /*  TMID2           */
-    union iodefine_reg32_t  TMPTR2;                        /*  TMPTR2          */
-    union iodefine_reg32_t  TMDF02;                        /*  TMDF02          */
-    union iodefine_reg32_t  TMDF12;                        /*  TMDF12          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID3;                         /*  TMID3           */
-    union iodefine_reg32_t  TMPTR3;                        /*  TMPTR3          */
-    union iodefine_reg32_t  TMDF03;                        /*  TMDF03          */
-    union iodefine_reg32_t  TMDF13;                        /*  TMDF13          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID4;                         /*  TMID4           */
-    union iodefine_reg32_t  TMPTR4;                        /*  TMPTR4          */
-    union iodefine_reg32_t  TMDF04;                        /*  TMDF04          */
-    union iodefine_reg32_t  TMDF14;                        /*  TMDF14          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID5;                         /*  TMID5           */
-    union iodefine_reg32_t  TMPTR5;                        /*  TMPTR5          */
-    union iodefine_reg32_t  TMDF05;                        /*  TMDF05          */
-    union iodefine_reg32_t  TMDF15;                        /*  TMDF15          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID6;                         /*  TMID6           */
-    union iodefine_reg32_t  TMPTR6;                        /*  TMPTR6          */
-    union iodefine_reg32_t  TMDF06;                        /*  TMDF06          */
-    union iodefine_reg32_t  TMDF16;                        /*  TMDF16          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID7;                         /*  TMID7           */
-    union iodefine_reg32_t  TMPTR7;                        /*  TMPTR7          */
-    union iodefine_reg32_t  TMDF07;                        /*  TMDF07          */
-    union iodefine_reg32_t  TMDF17;                        /*  TMDF17          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID8;                         /*  TMID8           */
-    union iodefine_reg32_t  TMPTR8;                        /*  TMPTR8          */
-    union iodefine_reg32_t  TMDF08;                        /*  TMDF08          */
-    union iodefine_reg32_t  TMDF18;                        /*  TMDF18          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID9;                         /*  TMID9           */
-    union iodefine_reg32_t  TMPTR9;                        /*  TMPTR9          */
-    union iodefine_reg32_t  TMDF09;                        /*  TMDF09          */
-    union iodefine_reg32_t  TMDF19;                        /*  TMDF19          */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID10;                        /*  TMID10          */
-    union iodefine_reg32_t  TMPTR10;                       /*  TMPTR10         */
-    union iodefine_reg32_t  TMDF010;                       /*  TMDF010         */
-    union iodefine_reg32_t  TMDF110;                       /*  TMDF110         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID11;                        /*  TMID11          */
-    union iodefine_reg32_t  TMPTR11;                       /*  TMPTR11         */
-    union iodefine_reg32_t  TMDF011;                       /*  TMDF011         */
-    union iodefine_reg32_t  TMDF111;                       /*  TMDF111         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID12;                        /*  TMID12          */
-    union iodefine_reg32_t  TMPTR12;                       /*  TMPTR12         */
-    union iodefine_reg32_t  TMDF012;                       /*  TMDF012         */
-    union iodefine_reg32_t  TMDF112;                       /*  TMDF112         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID13;                        /*  TMID13          */
-    union iodefine_reg32_t  TMPTR13;                       /*  TMPTR13         */
-    union iodefine_reg32_t  TMDF013;                       /*  TMDF013         */
-    union iodefine_reg32_t  TMDF113;                       /*  TMDF113         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID14;                        /*  TMID14          */
-    union iodefine_reg32_t  TMPTR14;                       /*  TMPTR14         */
-    union iodefine_reg32_t  TMDF014;                       /*  TMDF014         */
-    union iodefine_reg32_t  TMDF114;                       /*  TMDF114         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID15;                        /*  TMID15          */
-    union iodefine_reg32_t  TMPTR15;                       /*  TMPTR15         */
-    union iodefine_reg32_t  TMDF015;                       /*  TMDF015         */
-    union iodefine_reg32_t  TMDF115;                       /*  TMDF115         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID16;                        /*  TMID16          */
-    union iodefine_reg32_t  TMPTR16;                       /*  TMPTR16         */
-    union iodefine_reg32_t  TMDF016;                       /*  TMDF016         */
-    union iodefine_reg32_t  TMDF116;                       /*  TMDF116         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID17;                        /*  TMID17          */
-    union iodefine_reg32_t  TMPTR17;                       /*  TMPTR17         */
-    union iodefine_reg32_t  TMDF017;                       /*  TMDF017         */
-    union iodefine_reg32_t  TMDF117;                       /*  TMDF117         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID18;                        /*  TMID18          */
-    union iodefine_reg32_t  TMPTR18;                       /*  TMPTR18         */
-    union iodefine_reg32_t  TMDF018;                       /*  TMDF018         */
-    union iodefine_reg32_t  TMDF118;                       /*  TMDF118         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID19;                        /*  TMID19          */
-    union iodefine_reg32_t  TMPTR19;                       /*  TMPTR19         */
-    union iodefine_reg32_t  TMDF019;                       /*  TMDF019         */
-    union iodefine_reg32_t  TMDF119;                       /*  TMDF119         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID20;                        /*  TMID20          */
-    union iodefine_reg32_t  TMPTR20;                       /*  TMPTR20         */
-    union iodefine_reg32_t  TMDF020;                       /*  TMDF020         */
-    union iodefine_reg32_t  TMDF120;                       /*  TMDF120         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID21;                        /*  TMID21          */
-    union iodefine_reg32_t  TMPTR21;                       /*  TMPTR21         */
-    union iodefine_reg32_t  TMDF021;                       /*  TMDF021         */
-    union iodefine_reg32_t  TMDF121;                       /*  TMDF121         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID22;                        /*  TMID22          */
-    union iodefine_reg32_t  TMPTR22;                       /*  TMPTR22         */
-    union iodefine_reg32_t  TMDF022;                       /*  TMDF022         */
-    union iodefine_reg32_t  TMDF122;                       /*  TMDF122         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID23;                        /*  TMID23          */
-    union iodefine_reg32_t  TMPTR23;                       /*  TMPTR23         */
-    union iodefine_reg32_t  TMDF023;                       /*  TMDF023         */
-    union iodefine_reg32_t  TMDF123;                       /*  TMDF123         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID24;                        /*  TMID24          */
-    union iodefine_reg32_t  TMPTR24;                       /*  TMPTR24         */
-    union iodefine_reg32_t  TMDF024;                       /*  TMDF024         */
-    union iodefine_reg32_t  TMDF124;                       /*  TMDF124         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID25;                        /*  TMID25          */
-    union iodefine_reg32_t  TMPTR25;                       /*  TMPTR25         */
-    union iodefine_reg32_t  TMDF025;                       /*  TMDF025         */
-    union iodefine_reg32_t  TMDF125;                       /*  TMDF125         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID26;                        /*  TMID26          */
-    union iodefine_reg32_t  TMPTR26;                       /*  TMPTR26         */
-    union iodefine_reg32_t  TMDF026;                       /*  TMDF026         */
-    union iodefine_reg32_t  TMDF126;                       /*  TMDF126         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID27;                        /*  TMID27          */
-    union iodefine_reg32_t  TMPTR27;                       /*  TMPTR27         */
-    union iodefine_reg32_t  TMDF027;                       /*  TMDF027         */
-    union iodefine_reg32_t  TMDF127;                       /*  TMDF127         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID28;                        /*  TMID28          */
-    union iodefine_reg32_t  TMPTR28;                       /*  TMPTR28         */
-    union iodefine_reg32_t  TMDF028;                       /*  TMDF028         */
-    union iodefine_reg32_t  TMDF128;                       /*  TMDF128         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID29;                        /*  TMID29          */
-    union iodefine_reg32_t  TMPTR29;                       /*  TMPTR29         */
-    union iodefine_reg32_t  TMDF029;                       /*  TMDF029         */
-    union iodefine_reg32_t  TMDF129;                       /*  TMDF129         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID30;                        /*  TMID30          */
-    union iodefine_reg32_t  TMPTR30;                       /*  TMPTR30         */
-    union iodefine_reg32_t  TMDF030;                       /*  TMDF030         */
-    union iodefine_reg32_t  TMDF130;                       /*  TMDF130         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID31;                        /*  TMID31          */
-    union iodefine_reg32_t  TMPTR31;                       /*  TMPTR31         */
-    union iodefine_reg32_t  TMDF031;                       /*  TMDF031         */
-    union iodefine_reg32_t  TMDF131;                       /*  TMDF131         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID32;                        /*  TMID32          */
-    union iodefine_reg32_t  TMPTR32;                       /*  TMPTR32         */
-    union iodefine_reg32_t  TMDF032;                       /*  TMDF032         */
-    union iodefine_reg32_t  TMDF132;                       /*  TMDF132         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID33;                        /*  TMID33          */
-    union iodefine_reg32_t  TMPTR33;                       /*  TMPTR33         */
-    union iodefine_reg32_t  TMDF033;                       /*  TMDF033         */
-    union iodefine_reg32_t  TMDF133;                       /*  TMDF133         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID34;                        /*  TMID34          */
-    union iodefine_reg32_t  TMPTR34;                       /*  TMPTR34         */
-    union iodefine_reg32_t  TMDF034;                       /*  TMDF034         */
-    union iodefine_reg32_t  TMDF134;                       /*  TMDF134         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID35;                        /*  TMID35          */
-    union iodefine_reg32_t  TMPTR35;                       /*  TMPTR35         */
-    union iodefine_reg32_t  TMDF035;                       /*  TMDF035         */
-    union iodefine_reg32_t  TMDF135;                       /*  TMDF135         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID36;                        /*  TMID36          */
-    union iodefine_reg32_t  TMPTR36;                       /*  TMPTR36         */
-    union iodefine_reg32_t  TMDF036;                       /*  TMDF036         */
-    union iodefine_reg32_t  TMDF136;                       /*  TMDF136         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID37;                        /*  TMID37          */
-    union iodefine_reg32_t  TMPTR37;                       /*  TMPTR37         */
-    union iodefine_reg32_t  TMDF037;                       /*  TMDF037         */
-    union iodefine_reg32_t  TMDF137;                       /*  TMDF137         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID38;                        /*  TMID38          */
-    union iodefine_reg32_t  TMPTR38;                       /*  TMPTR38         */
-    union iodefine_reg32_t  TMDF038;                       /*  TMDF038         */
-    union iodefine_reg32_t  TMDF138;                       /*  TMDF138         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID39;                        /*  TMID39          */
-    union iodefine_reg32_t  TMPTR39;                       /*  TMPTR39         */
-    union iodefine_reg32_t  TMDF039;                       /*  TMDF039         */
-    union iodefine_reg32_t  TMDF139;                       /*  TMDF139         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID40;                        /*  TMID40          */
-    union iodefine_reg32_t  TMPTR40;                       /*  TMPTR40         */
-    union iodefine_reg32_t  TMDF040;                       /*  TMDF040         */
-    union iodefine_reg32_t  TMDF140;                       /*  TMDF140         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID41;                        /*  TMID41          */
-    union iodefine_reg32_t  TMPTR41;                       /*  TMPTR41         */
-    union iodefine_reg32_t  TMDF041;                       /*  TMDF041         */
-    union iodefine_reg32_t  TMDF141;                       /*  TMDF141         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID42;                        /*  TMID42          */
-    union iodefine_reg32_t  TMPTR42;                       /*  TMPTR42         */
-    union iodefine_reg32_t  TMDF042;                       /*  TMDF042         */
-    union iodefine_reg32_t  TMDF142;                       /*  TMDF142         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID43;                        /*  TMID43          */
-    union iodefine_reg32_t  TMPTR43;                       /*  TMPTR43         */
-    union iodefine_reg32_t  TMDF043;                       /*  TMDF043         */
-    union iodefine_reg32_t  TMDF143;                       /*  TMDF143         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID44;                        /*  TMID44          */
-    union iodefine_reg32_t  TMPTR44;                       /*  TMPTR44         */
-    union iodefine_reg32_t  TMDF044;                       /*  TMDF044         */
-    union iodefine_reg32_t  TMDF144;                       /*  TMDF144         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID45;                        /*  TMID45          */
-    union iodefine_reg32_t  TMPTR45;                       /*  TMPTR45         */
-    union iodefine_reg32_t  TMDF045;                       /*  TMDF045         */
-    union iodefine_reg32_t  TMDF145;                       /*  TMDF145         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID46;                        /*  TMID46          */
-    union iodefine_reg32_t  TMPTR46;                       /*  TMPTR46         */
-    union iodefine_reg32_t  TMDF046;                       /*  TMDF046         */
-    union iodefine_reg32_t  TMDF146;                       /*  TMDF146         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID47;                        /*  TMID47          */
-    union iodefine_reg32_t  TMPTR47;                       /*  TMPTR47         */
-    union iodefine_reg32_t  TMDF047;                       /*  TMDF047         */
-    union iodefine_reg32_t  TMDF147;                       /*  TMDF147         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID48;                        /*  TMID48          */
-    union iodefine_reg32_t  TMPTR48;                       /*  TMPTR48         */
-    union iodefine_reg32_t  TMDF048;                       /*  TMDF048         */
-    union iodefine_reg32_t  TMDF148;                       /*  TMDF148         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID49;                        /*  TMID49          */
-    union iodefine_reg32_t  TMPTR49;                       /*  TMPTR49         */
-    union iodefine_reg32_t  TMDF049;                       /*  TMDF049         */
-    union iodefine_reg32_t  TMDF149;                       /*  TMDF149         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID50;                        /*  TMID50          */
-    union iodefine_reg32_t  TMPTR50;                       /*  TMPTR50         */
-    union iodefine_reg32_t  TMDF050;                       /*  TMDF050         */
-    union iodefine_reg32_t  TMDF150;                       /*  TMDF150         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID51;                        /*  TMID51          */
-    union iodefine_reg32_t  TMPTR51;                       /*  TMPTR51         */
-    union iodefine_reg32_t  TMDF051;                       /*  TMDF051         */
-    union iodefine_reg32_t  TMDF151;                       /*  TMDF151         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID52;                        /*  TMID52          */
-    union iodefine_reg32_t  TMPTR52;                       /*  TMPTR52         */
-    union iodefine_reg32_t  TMDF052;                       /*  TMDF052         */
-    union iodefine_reg32_t  TMDF152;                       /*  TMDF152         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID53;                        /*  TMID53          */
-    union iodefine_reg32_t  TMPTR53;                       /*  TMPTR53         */
-    union iodefine_reg32_t  TMDF053;                       /*  TMDF053         */
-    union iodefine_reg32_t  TMDF153;                       /*  TMDF153         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID54;                        /*  TMID54          */
-    union iodefine_reg32_t  TMPTR54;                       /*  TMPTR54         */
-    union iodefine_reg32_t  TMDF054;                       /*  TMDF054         */
-    union iodefine_reg32_t  TMDF154;                       /*  TMDF154         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID55;                        /*  TMID55          */
-    union iodefine_reg32_t  TMPTR55;                       /*  TMPTR55         */
-    union iodefine_reg32_t  TMDF055;                       /*  TMDF055         */
-    union iodefine_reg32_t  TMDF155;                       /*  TMDF155         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID56;                        /*  TMID56          */
-    union iodefine_reg32_t  TMPTR56;                       /*  TMPTR56         */
-    union iodefine_reg32_t  TMDF056;                       /*  TMDF056         */
-    union iodefine_reg32_t  TMDF156;                       /*  TMDF156         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID57;                        /*  TMID57          */
-    union iodefine_reg32_t  TMPTR57;                       /*  TMPTR57         */
-    union iodefine_reg32_t  TMDF057;                       /*  TMDF057         */
-    union iodefine_reg32_t  TMDF157;                       /*  TMDF157         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID58;                        /*  TMID58          */
-    union iodefine_reg32_t  TMPTR58;                       /*  TMPTR58         */
-    union iodefine_reg32_t  TMDF058;                       /*  TMDF058         */
-    union iodefine_reg32_t  TMDF158;                       /*  TMDF158         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID59;                        /*  TMID59          */
-    union iodefine_reg32_t  TMPTR59;                       /*  TMPTR59         */
-    union iodefine_reg32_t  TMDF059;                       /*  TMDF059         */
-    union iodefine_reg32_t  TMDF159;                       /*  TMDF159         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID60;                        /*  TMID60          */
-    union iodefine_reg32_t  TMPTR60;                       /*  TMPTR60         */
-    union iodefine_reg32_t  TMDF060;                       /*  TMDF060         */
-    union iodefine_reg32_t  TMDF160;                       /*  TMDF160         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID61;                        /*  TMID61          */
-    union iodefine_reg32_t  TMPTR61;                       /*  TMPTR61         */
-    union iodefine_reg32_t  TMDF061;                       /*  TMDF061         */
-    union iodefine_reg32_t  TMDF161;                       /*  TMDF161         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID62;                        /*  TMID62          */
-    union iodefine_reg32_t  TMPTR62;                       /*  TMPTR62         */
-    union iodefine_reg32_t  TMDF062;                       /*  TMDF062         */
-    union iodefine_reg32_t  TMDF162;                       /*  TMDF162         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID63;                        /*  TMID63          */
-    union iodefine_reg32_t  TMPTR63;                       /*  TMPTR63         */
-    union iodefine_reg32_t  TMDF063;                       /*  TMDF063         */
-    union iodefine_reg32_t  TMDF163;                       /*  TMDF163         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID64;                        /*  TMID64          */
-    union iodefine_reg32_t  TMPTR64;                       /*  TMPTR64         */
-    union iodefine_reg32_t  TMDF064;                       /*  TMDF064         */
-    union iodefine_reg32_t  TMDF164;                       /*  TMDF164         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID65;                        /*  TMID65          */
-    union iodefine_reg32_t  TMPTR65;                       /*  TMPTR65         */
-    union iodefine_reg32_t  TMDF065;                       /*  TMDF065         */
-    union iodefine_reg32_t  TMDF165;                       /*  TMDF165         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID66;                        /*  TMID66          */
-    union iodefine_reg32_t  TMPTR66;                       /*  TMPTR66         */
-    union iodefine_reg32_t  TMDF066;                       /*  TMDF066         */
-    union iodefine_reg32_t  TMDF166;                       /*  TMDF166         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID67;                        /*  TMID67          */
-    union iodefine_reg32_t  TMPTR67;                       /*  TMPTR67         */
-    union iodefine_reg32_t  TMDF067;                       /*  TMDF067         */
-    union iodefine_reg32_t  TMDF167;                       /*  TMDF167         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID68;                        /*  TMID68          */
-    union iodefine_reg32_t  TMPTR68;                       /*  TMPTR68         */
-    union iodefine_reg32_t  TMDF068;                       /*  TMDF068         */
-    union iodefine_reg32_t  TMDF168;                       /*  TMDF168         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID69;                        /*  TMID69          */
-    union iodefine_reg32_t  TMPTR69;                       /*  TMPTR69         */
-    union iodefine_reg32_t  TMDF069;                       /*  TMDF069         */
-    union iodefine_reg32_t  TMDF169;                       /*  TMDF169         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID70;                        /*  TMID70          */
-    union iodefine_reg32_t  TMPTR70;                       /*  TMPTR70         */
-    union iodefine_reg32_t  TMDF070;                       /*  TMDF070         */
-    union iodefine_reg32_t  TMDF170;                       /*  TMDF170         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID71;                        /*  TMID71          */
-    union iodefine_reg32_t  TMPTR71;                       /*  TMPTR71         */
-    union iodefine_reg32_t  TMDF071;                       /*  TMDF071         */
-    union iodefine_reg32_t  TMDF171;                       /*  TMDF171         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID72;                        /*  TMID72          */
-    union iodefine_reg32_t  TMPTR72;                       /*  TMPTR72         */
-    union iodefine_reg32_t  TMDF072;                       /*  TMDF072         */
-    union iodefine_reg32_t  TMDF172;                       /*  TMDF172         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID73;                        /*  TMID73          */
-    union iodefine_reg32_t  TMPTR73;                       /*  TMPTR73         */
-    union iodefine_reg32_t  TMDF073;                       /*  TMDF073         */
-    union iodefine_reg32_t  TMDF173;                       /*  TMDF173         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID74;                        /*  TMID74          */
-    union iodefine_reg32_t  TMPTR74;                       /*  TMPTR74         */
-    union iodefine_reg32_t  TMDF074;                       /*  TMDF074         */
-    union iodefine_reg32_t  TMDF174;                       /*  TMDF174         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID75;                        /*  TMID75          */
-    union iodefine_reg32_t  TMPTR75;                       /*  TMPTR75         */
-    union iodefine_reg32_t  TMDF075;                       /*  TMDF075         */
-    union iodefine_reg32_t  TMDF175;                       /*  TMDF175         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID76;                        /*  TMID76          */
-    union iodefine_reg32_t  TMPTR76;                       /*  TMPTR76         */
-    union iodefine_reg32_t  TMDF076;                       /*  TMDF076         */
-    union iodefine_reg32_t  TMDF176;                       /*  TMDF176         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID77;                        /*  TMID77          */
-    union iodefine_reg32_t  TMPTR77;                       /*  TMPTR77         */
-    union iodefine_reg32_t  TMDF077;                       /*  TMDF077         */
-    union iodefine_reg32_t  TMDF177;                       /*  TMDF177         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID78;                        /*  TMID78          */
-    union iodefine_reg32_t  TMPTR78;                       /*  TMPTR78         */
-    union iodefine_reg32_t  TMDF078;                       /*  TMDF078         */
-    union iodefine_reg32_t  TMDF178;                       /*  TMDF178         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-/* start of struct st_rscan_from_rscan0tmidp */
-    union iodefine_reg32_t  TMID79;                        /*  TMID79          */
-    union iodefine_reg32_t  TMPTR79;                       /*  TMPTR79         */
-    union iodefine_reg32_t  TMDF079;                       /*  TMDF079         */
-    union iodefine_reg32_t  TMDF179;                       /*  TMDF179         */
-/* end of struct st_rscan_from_rscan0tmidp */
-    
-    volatile uint8_t   dummy181[768];                          /*                  */
-#define RSCAN0_THLACC0_COUNT 5
-    union iodefine_reg32_t  THLACC0;                       /*  THLACC0         */
-    union iodefine_reg32_t  THLACC1;                       /*  THLACC1         */
-    union iodefine_reg32_t  THLACC2;                       /*  THLACC2         */
-    union iodefine_reg32_t  THLACC3;                       /*  THLACC3         */
-    union iodefine_reg32_t  THLACC4;                       /*  THLACC4         */
-    
-};
-
-
-struct st_rscan_from_rscan0cncfg
-{
-    union iodefine_reg32_t  CnCFG;                         /*  CnCFG           */
-    union iodefine_reg32_t  CnCTR;                         /*  CnCTR           */
-    union iodefine_reg32_t  CnSTS;                         /*  CnSTS           */
-    union iodefine_reg32_t  CnERFL;                        /*  CnERFL          */
-};
-
-
-struct st_rscan_from_rscan0gaflidj
-{
-    union iodefine_reg32_t  GAFLIDj;                       /*  GAFLIDj         */
-    union iodefine_reg32_t  GAFLMj;                        /*  GAFLMj          */
-    union iodefine_reg32_t  GAFLP0j;                       /*  GAFLP0j         */
-    union iodefine_reg32_t  GAFLP1j;                       /*  GAFLP1j         */
-};
-
-
-struct st_rscan_from_rscan0rmidp
-{
-    union iodefine_reg32_t  RMIDp;                         /*  RMIDp           */
-    union iodefine_reg32_t  RMPTRp;                        /*  RMPTRp          */
-    union iodefine_reg32_t  RMDF0p;                        /*  RMDF0p          */
-    union iodefine_reg32_t  RMDF1p;                        /*  RMDF1p          */
-};
-
-
-struct st_rscan_from_rscan0rfidm
-{
-    union iodefine_reg32_t  RFIDm;                         /*  RFIDm           */
-    union iodefine_reg32_t  RFPTRm;                        /*  RFPTRm          */
-    union iodefine_reg32_t  RFDF0m;                        /*  RFDF0m          */
-    union iodefine_reg32_t  RFDF1m;                        /*  RFDF1m          */
-};
-
-
-struct st_rscan_from_rscan0tmidp
-{
-    union iodefine_reg32_t  TMIDp;                         /*  TMIDp           */
-    union iodefine_reg32_t  TMPTRp;                        /*  TMPTRp          */
-    union iodefine_reg32_t  TMDF0p;                        /*  TMDF0p          */
-    union iodefine_reg32_t  TMDF1p;                        /*  TMDF1p          */
-};
-
-
-struct st_rscan_from_rscan0cfidm
-{
-    union iodefine_reg32_t  CFIDm;                         /*  CFIDm           */
-    union iodefine_reg32_t  CFPTRm;                        /*  CFPTRm          */
-    union iodefine_reg32_t  CFDF0m;                        /*  CFDF0m          */
-    union iodefine_reg32_t  CFDF1m;                        /*  CFDF1m          */
-};
-
-
 #define RSCAN0  (*(struct st_rscan0  *)0xE803A000uL) /* RSCAN0 */
 
 
-/* Start of channnel array defines of RSCAN0 */
-
-/* Channnel array defines of RSCAN_FROM_RSCAN0CFIDm */
-/*(Sample) value = RSCAN_FROM_RSCAN0CFIDm[ channel ]->CFIDm.UINT32; */
-#define RSCAN_FROM_RSCAN0CFIDm_COUNT  15
-#define RSCAN_FROM_RSCAN0CFIDm_ADDRESS_LIST \
+/* Start of channel array defines of RSCAN0 */
+
+/* Channel array defines of RSCAN_FROM_RSCAN0_CFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0_CFIDm[ channel ]->CFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0_CFIDm_COUNT  (15)
+#define RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0CFID0, &RSCAN_FROM_RSCAN0CFID1, &RSCAN_FROM_RSCAN0CFID2, &RSCAN_FROM_RSCAN0CFID3, &RSCAN_FROM_RSCAN0CFID4, &RSCAN_FROM_RSCAN0CFID5, &RSCAN_FROM_RSCAN0CFID6, &RSCAN_FROM_RSCAN0CFID7, \
     &RSCAN_FROM_RSCAN0CFID8, &RSCAN_FROM_RSCAN0CFID9, &RSCAN_FROM_RSCAN0CFID10, &RSCAN_FROM_RSCAN0CFID11, &RSCAN_FROM_RSCAN0CFID12, &RSCAN_FROM_RSCAN0CFID13, &RSCAN_FROM_RSCAN0CFID14 \
@@ -1919,10 +63,10 @@
 #define RSCAN_FROM_RSCAN0CFID14 (*(struct st_rscan_from_rscan0cfidm *)&RSCAN0.CFID14) /* RSCAN_FROM_RSCAN0CFID14 */
 
 
-/* Channnel array defines of RSCAN_FROM_RSCAN0TMIDp */
-/*(Sample) value = RSCAN_FROM_RSCAN0TMIDp[ channel ]->TMIDp.UINT32; */
-#define RSCAN_FROM_RSCAN0TMIDp_COUNT  80
-#define RSCAN_FROM_RSCAN0TMIDp_ADDRESS_LIST \
+/* Channel array defines of RSCAN_FROM_RSCAN0_TMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0_TMIDp[ channel ]->TMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0_TMIDp_COUNT  (80)
+#define RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0TMID0, &RSCAN_FROM_RSCAN0TMID1, &RSCAN_FROM_RSCAN0TMID2, &RSCAN_FROM_RSCAN0TMID3, &RSCAN_FROM_RSCAN0TMID4, &RSCAN_FROM_RSCAN0TMID5, &RSCAN_FROM_RSCAN0TMID6, &RSCAN_FROM_RSCAN0TMID7, \
     &RSCAN_FROM_RSCAN0TMID8, &RSCAN_FROM_RSCAN0TMID9, &RSCAN_FROM_RSCAN0TMID10, &RSCAN_FROM_RSCAN0TMID11, &RSCAN_FROM_RSCAN0TMID12, &RSCAN_FROM_RSCAN0TMID13, &RSCAN_FROM_RSCAN0TMID14, &RSCAN_FROM_RSCAN0TMID15, \
@@ -2017,10 +161,10 @@
 #define RSCAN_FROM_RSCAN0TMID79 (*(struct st_rscan_from_rscan0tmidp *)&RSCAN0.TMID79) /* RSCAN_FROM_RSCAN0TMID79 */
 
 
-/* Channnel array defines of RSCAN_FROM_RSCAN0RFIDm */
-/*(Sample) value = RSCAN_FROM_RSCAN0RFIDm[ channel ]->RFIDm.UINT32; */
-#define RSCAN_FROM_RSCAN0RFIDm_COUNT  8
-#define RSCAN_FROM_RSCAN0RFIDm_ADDRESS_LIST \
+/* Channel array defines of RSCAN_FROM_RSCAN0_RFIDm */
+/*(Sample) value = RSCAN_FROM_RSCAN0_RFIDm[ channel ]->RFIDm.UINT32; */
+#define RSCAN_FROM_RSCAN0_RFIDm_COUNT  (8)
+#define RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0RFID0, &RSCAN_FROM_RSCAN0RFID1, &RSCAN_FROM_RSCAN0RFID2, &RSCAN_FROM_RSCAN0RFID3, &RSCAN_FROM_RSCAN0RFID4, &RSCAN_FROM_RSCAN0RFID5, &RSCAN_FROM_RSCAN0RFID6, &RSCAN_FROM_RSCAN0RFID7 \
 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
@@ -2034,10 +178,10 @@
 #define RSCAN_FROM_RSCAN0RFID7 (*(struct st_rscan_from_rscan0rfidm *)&RSCAN0.RFID7) /* RSCAN_FROM_RSCAN0RFID7 */
 
 
-/* Channnel array defines of RSCAN_FROM_RSCAN0RMIDp */
-/*(Sample) value = RSCAN_FROM_RSCAN0RMIDp[ channel ]->RMIDp.UINT32; */
-#define RSCAN_FROM_RSCAN0RMIDp_COUNT  80
-#define RSCAN_FROM_RSCAN0RMIDp_ADDRESS_LIST \
+/* Channel array defines of RSCAN_FROM_RSCAN0_RMIDp */
+/*(Sample) value = RSCAN_FROM_RSCAN0_RMIDp[ channel ]->RMIDp.UINT32; */
+#define RSCAN_FROM_RSCAN0_RMIDp_COUNT  (80)
+#define RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0RMID0, &RSCAN_FROM_RSCAN0RMID1, &RSCAN_FROM_RSCAN0RMID2, &RSCAN_FROM_RSCAN0RMID3, &RSCAN_FROM_RSCAN0RMID4, &RSCAN_FROM_RSCAN0RMID5, &RSCAN_FROM_RSCAN0RMID6, &RSCAN_FROM_RSCAN0RMID7, \
     &RSCAN_FROM_RSCAN0RMID8, &RSCAN_FROM_RSCAN0RMID9, &RSCAN_FROM_RSCAN0RMID10, &RSCAN_FROM_RSCAN0RMID11, &RSCAN_FROM_RSCAN0RMID12, &RSCAN_FROM_RSCAN0RMID13, &RSCAN_FROM_RSCAN0RMID14, &RSCAN_FROM_RSCAN0RMID15, \
@@ -2132,10 +276,10 @@
 #define RSCAN_FROM_RSCAN0RMID79 (*(struct st_rscan_from_rscan0rmidp *)&RSCAN0.RMID79) /* RSCAN_FROM_RSCAN0RMID79 */
 
 
-/* Channnel array defines of RSCAN_FROM_RSCAN0GAFLIDj */
-/*(Sample) value = RSCAN_FROM_RSCAN0GAFLIDj[ channel ]->GAFLIDj.UINT32; */
-#define RSCAN_FROM_RSCAN0GAFLIDj_COUNT  16
-#define RSCAN_FROM_RSCAN0GAFLIDj_ADDRESS_LIST \
+/* Channel array defines of RSCAN_FROM_RSCAN0_GAFLIDj */
+/*(Sample) value = RSCAN_FROM_RSCAN0_GAFLIDj[ channel ]->GAFLIDj.UINT32; */
+#define RSCAN_FROM_RSCAN0_GAFLIDj_COUNT  (16)
+#define RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0GAFLID0, &RSCAN_FROM_RSCAN0GAFLID1, &RSCAN_FROM_RSCAN0GAFLID2, &RSCAN_FROM_RSCAN0GAFLID3, &RSCAN_FROM_RSCAN0GAFLID4, &RSCAN_FROM_RSCAN0GAFLID5, &RSCAN_FROM_RSCAN0GAFLID6, &RSCAN_FROM_RSCAN0GAFLID7, \
     &RSCAN_FROM_RSCAN0GAFLID8, &RSCAN_FROM_RSCAN0GAFLID9, &RSCAN_FROM_RSCAN0GAFLID10, &RSCAN_FROM_RSCAN0GAFLID11, &RSCAN_FROM_RSCAN0GAFLID12, &RSCAN_FROM_RSCAN0GAFLID13, &RSCAN_FROM_RSCAN0GAFLID14, &RSCAN_FROM_RSCAN0GAFLID15 \
@@ -2158,10 +302,10 @@
 #define RSCAN_FROM_RSCAN0GAFLID15 (*(struct st_rscan_from_rscan0gaflidj *)&RSCAN0.GAFLID15) /* RSCAN_FROM_RSCAN0GAFLID15 */
 
 
-/* Channnel array defines of RSCAN_FROM_RSCAN0CnCFG */
-/*(Sample) value = RSCAN_FROM_RSCAN0CnCFG[ channel ]->CnCFG.UINT32; */
-#define RSCAN_FROM_RSCAN0CnCFG_COUNT  5
-#define RSCAN_FROM_RSCAN0CnCFG_ADDRESS_LIST \
+/* Channel array defines of RSCAN_FROM_RSCAN0_CnCFG */
+/*(Sample) value = RSCAN_FROM_RSCAN0_CnCFG[ channel ]->CnCFG.UINT32; */
+#define RSCAN_FROM_RSCAN0_CnCFG_COUNT  (5)
+#define RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &RSCAN_FROM_RSCAN0C0CFG, &RSCAN_FROM_RSCAN0C1CFG, &RSCAN_FROM_RSCAN0C2CFG, &RSCAN_FROM_RSCAN0C3CFG, &RSCAN_FROM_RSCAN0C4CFG \
 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
@@ -2171,6868 +315,9032 @@
 #define RSCAN_FROM_RSCAN0C3CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C3CFG) /* RSCAN_FROM_RSCAN0C3CFG */
 #define RSCAN_FROM_RSCAN0C4CFG (*(struct st_rscan_from_rscan0cncfg *)&RSCAN0.C4CFG) /* RSCAN_FROM_RSCAN0C4CFG */
 
-/* End of channnel array defines of RSCAN0 */
-
-
-#define RSCAN0C0CFG RSCAN0.C0CFG.UINT32
-#define RSCAN0C0CFGL RSCAN0.C0CFG.UINT16[L]
-#define RSCAN0C0CFGLL RSCAN0.C0CFG.UINT8[LL]
-#define RSCAN0C0CFGLH RSCAN0.C0CFG.UINT8[LH]
-#define RSCAN0C0CFGH RSCAN0.C0CFG.UINT16[H]
-#define RSCAN0C0CFGHL RSCAN0.C0CFG.UINT8[HL]
-#define RSCAN0C0CFGHH RSCAN0.C0CFG.UINT8[HH]
-#define RSCAN0C0CTR RSCAN0.C0CTR.UINT32
-#define RSCAN0C0CTRL RSCAN0.C0CTR.UINT16[L]
-#define RSCAN0C0CTRLL RSCAN0.C0CTR.UINT8[LL]
-#define RSCAN0C0CTRLH RSCAN0.C0CTR.UINT8[LH]
-#define RSCAN0C0CTRH RSCAN0.C0CTR.UINT16[H]
-#define RSCAN0C0CTRHL RSCAN0.C0CTR.UINT8[HL]
-#define RSCAN0C0CTRHH RSCAN0.C0CTR.UINT8[HH]
-#define RSCAN0C0STS RSCAN0.C0STS.UINT32
-#define RSCAN0C0STSL RSCAN0.C0STS.UINT16[L]
-#define RSCAN0C0STSLL RSCAN0.C0STS.UINT8[LL]
-#define RSCAN0C0STSLH RSCAN0.C0STS.UINT8[LH]
-#define RSCAN0C0STSH RSCAN0.C0STS.UINT16[H]
-#define RSCAN0C0STSHL RSCAN0.C0STS.UINT8[HL]
-#define RSCAN0C0STSHH RSCAN0.C0STS.UINT8[HH]
-#define RSCAN0C0ERFL RSCAN0.C0ERFL.UINT32
-#define RSCAN0C0ERFLL RSCAN0.C0ERFL.UINT16[L]
-#define RSCAN0C0ERFLLL RSCAN0.C0ERFL.UINT8[LL]
-#define RSCAN0C0ERFLLH RSCAN0.C0ERFL.UINT8[LH]
-#define RSCAN0C0ERFLH RSCAN0.C0ERFL.UINT16[H]
-#define RSCAN0C0ERFLHL RSCAN0.C0ERFL.UINT8[HL]
-#define RSCAN0C0ERFLHH RSCAN0.C0ERFL.UINT8[HH]
-#define RSCAN0C1CFG RSCAN0.C1CFG.UINT32
-#define RSCAN0C1CFGL RSCAN0.C1CFG.UINT16[L]
-#define RSCAN0C1CFGLL RSCAN0.C1CFG.UINT8[LL]
-#define RSCAN0C1CFGLH RSCAN0.C1CFG.UINT8[LH]
-#define RSCAN0C1CFGH RSCAN0.C1CFG.UINT16[H]
-#define RSCAN0C1CFGHL RSCAN0.C1CFG.UINT8[HL]
-#define RSCAN0C1CFGHH RSCAN0.C1CFG.UINT8[HH]
-#define RSCAN0C1CTR RSCAN0.C1CTR.UINT32
-#define RSCAN0C1CTRL RSCAN0.C1CTR.UINT16[L]
-#define RSCAN0C1CTRLL RSCAN0.C1CTR.UINT8[LL]
-#define RSCAN0C1CTRLH RSCAN0.C1CTR.UINT8[LH]
-#define RSCAN0C1CTRH RSCAN0.C1CTR.UINT16[H]
-#define RSCAN0C1CTRHL RSCAN0.C1CTR.UINT8[HL]
-#define RSCAN0C1CTRHH RSCAN0.C1CTR.UINT8[HH]
-#define RSCAN0C1STS RSCAN0.C1STS.UINT32
-#define RSCAN0C1STSL RSCAN0.C1STS.UINT16[L]
-#define RSCAN0C1STSLL RSCAN0.C1STS.UINT8[LL]
-#define RSCAN0C1STSLH RSCAN0.C1STS.UINT8[LH]
-#define RSCAN0C1STSH RSCAN0.C1STS.UINT16[H]
-#define RSCAN0C1STSHL RSCAN0.C1STS.UINT8[HL]
-#define RSCAN0C1STSHH RSCAN0.C1STS.UINT8[HH]
-#define RSCAN0C1ERFL RSCAN0.C1ERFL.UINT32
-#define RSCAN0C1ERFLL RSCAN0.C1ERFL.UINT16[L]
-#define RSCAN0C1ERFLLL RSCAN0.C1ERFL.UINT8[LL]
-#define RSCAN0C1ERFLLH RSCAN0.C1ERFL.UINT8[LH]
-#define RSCAN0C1ERFLH RSCAN0.C1ERFL.UINT16[H]
-#define RSCAN0C1ERFLHL RSCAN0.C1ERFL.UINT8[HL]
-#define RSCAN0C1ERFLHH RSCAN0.C1ERFL.UINT8[HH]
-#define RSCAN0C2CFG RSCAN0.C2CFG.UINT32
-#define RSCAN0C2CFGL RSCAN0.C2CFG.UINT16[L]
-#define RSCAN0C2CFGLL RSCAN0.C2CFG.UINT8[LL]
-#define RSCAN0C2CFGLH RSCAN0.C2CFG.UINT8[LH]
-#define RSCAN0C2CFGH RSCAN0.C2CFG.UINT16[H]
-#define RSCAN0C2CFGHL RSCAN0.C2CFG.UINT8[HL]
-#define RSCAN0C2CFGHH RSCAN0.C2CFG.UINT8[HH]
-#define RSCAN0C2CTR RSCAN0.C2CTR.UINT32
-#define RSCAN0C2CTRL RSCAN0.C2CTR.UINT16[L]
-#define RSCAN0C2CTRLL RSCAN0.C2CTR.UINT8[LL]
-#define RSCAN0C2CTRLH RSCAN0.C2CTR.UINT8[LH]
-#define RSCAN0C2CTRH RSCAN0.C2CTR.UINT16[H]
-#define RSCAN0C2CTRHL RSCAN0.C2CTR.UINT8[HL]
-#define RSCAN0C2CTRHH RSCAN0.C2CTR.UINT8[HH]
-#define RSCAN0C2STS RSCAN0.C2STS.UINT32
-#define RSCAN0C2STSL RSCAN0.C2STS.UINT16[L]
-#define RSCAN0C2STSLL RSCAN0.C2STS.UINT8[LL]
-#define RSCAN0C2STSLH RSCAN0.C2STS.UINT8[LH]
-#define RSCAN0C2STSH RSCAN0.C2STS.UINT16[H]
-#define RSCAN0C2STSHL RSCAN0.C2STS.UINT8[HL]
-#define RSCAN0C2STSHH RSCAN0.C2STS.UINT8[HH]
-#define RSCAN0C2ERFL RSCAN0.C2ERFL.UINT32
-#define RSCAN0C2ERFLL RSCAN0.C2ERFL.UINT16[L]
-#define RSCAN0C2ERFLLL RSCAN0.C2ERFL.UINT8[LL]
-#define RSCAN0C2ERFLLH RSCAN0.C2ERFL.UINT8[LH]
-#define RSCAN0C2ERFLH RSCAN0.C2ERFL.UINT16[H]
-#define RSCAN0C2ERFLHL RSCAN0.C2ERFL.UINT8[HL]
-#define RSCAN0C2ERFLHH RSCAN0.C2ERFL.UINT8[HH]
-#define RSCAN0C3CFG RSCAN0.C3CFG.UINT32
-#define RSCAN0C3CFGL RSCAN0.C3CFG.UINT16[L]
-#define RSCAN0C3CFGLL RSCAN0.C3CFG.UINT8[LL]
-#define RSCAN0C3CFGLH RSCAN0.C3CFG.UINT8[LH]
-#define RSCAN0C3CFGH RSCAN0.C3CFG.UINT16[H]
-#define RSCAN0C3CFGHL RSCAN0.C3CFG.UINT8[HL]
-#define RSCAN0C3CFGHH RSCAN0.C3CFG.UINT8[HH]
-#define RSCAN0C3CTR RSCAN0.C3CTR.UINT32
-#define RSCAN0C3CTRL RSCAN0.C3CTR.UINT16[L]
-#define RSCAN0C3CTRLL RSCAN0.C3CTR.UINT8[LL]
-#define RSCAN0C3CTRLH RSCAN0.C3CTR.UINT8[LH]
-#define RSCAN0C3CTRH RSCAN0.C3CTR.UINT16[H]
-#define RSCAN0C3CTRHL RSCAN0.C3CTR.UINT8[HL]
-#define RSCAN0C3CTRHH RSCAN0.C3CTR.UINT8[HH]
-#define RSCAN0C3STS RSCAN0.C3STS.UINT32
-#define RSCAN0C3STSL RSCAN0.C3STS.UINT16[L]
-#define RSCAN0C3STSLL RSCAN0.C3STS.UINT8[LL]
-#define RSCAN0C3STSLH RSCAN0.C3STS.UINT8[LH]
-#define RSCAN0C3STSH RSCAN0.C3STS.UINT16[H]
-#define RSCAN0C3STSHL RSCAN0.C3STS.UINT8[HL]
-#define RSCAN0C3STSHH RSCAN0.C3STS.UINT8[HH]
-#define RSCAN0C3ERFL RSCAN0.C3ERFL.UINT32
-#define RSCAN0C3ERFLL RSCAN0.C3ERFL.UINT16[L]
-#define RSCAN0C3ERFLLL RSCAN0.C3ERFL.UINT8[LL]
-#define RSCAN0C3ERFLLH RSCAN0.C3ERFL.UINT8[LH]
-#define RSCAN0C3ERFLH RSCAN0.C3ERFL.UINT16[H]
-#define RSCAN0C3ERFLHL RSCAN0.C3ERFL.UINT8[HL]
-#define RSCAN0C3ERFLHH RSCAN0.C3ERFL.UINT8[HH]
-#define RSCAN0C4CFG RSCAN0.C4CFG.UINT32
-#define RSCAN0C4CFGL RSCAN0.C4CFG.UINT16[L]
-#define RSCAN0C4CFGLL RSCAN0.C4CFG.UINT8[LL]
-#define RSCAN0C4CFGLH RSCAN0.C4CFG.UINT8[LH]
-#define RSCAN0C4CFGH RSCAN0.C4CFG.UINT16[H]
-#define RSCAN0C4CFGHL RSCAN0.C4CFG.UINT8[HL]
-#define RSCAN0C4CFGHH RSCAN0.C4CFG.UINT8[HH]
-#define RSCAN0C4CTR RSCAN0.C4CTR.UINT32
-#define RSCAN0C4CTRL RSCAN0.C4CTR.UINT16[L]
-#define RSCAN0C4CTRLL RSCAN0.C4CTR.UINT8[LL]
-#define RSCAN0C4CTRLH RSCAN0.C4CTR.UINT8[LH]
-#define RSCAN0C4CTRH RSCAN0.C4CTR.UINT16[H]
-#define RSCAN0C4CTRHL RSCAN0.C4CTR.UINT8[HL]
-#define RSCAN0C4CTRHH RSCAN0.C4CTR.UINT8[HH]
-#define RSCAN0C4STS RSCAN0.C4STS.UINT32
-#define RSCAN0C4STSL RSCAN0.C4STS.UINT16[L]
-#define RSCAN0C4STSLL RSCAN0.C4STS.UINT8[LL]
-#define RSCAN0C4STSLH RSCAN0.C4STS.UINT8[LH]
-#define RSCAN0C4STSH RSCAN0.C4STS.UINT16[H]
-#define RSCAN0C4STSHL RSCAN0.C4STS.UINT8[HL]
-#define RSCAN0C4STSHH RSCAN0.C4STS.UINT8[HH]
-#define RSCAN0C4ERFL RSCAN0.C4ERFL.UINT32
-#define RSCAN0C4ERFLL RSCAN0.C4ERFL.UINT16[L]
-#define RSCAN0C4ERFLLL RSCAN0.C4ERFL.UINT8[LL]
-#define RSCAN0C4ERFLLH RSCAN0.C4ERFL.UINT8[LH]
-#define RSCAN0C4ERFLH RSCAN0.C4ERFL.UINT16[H]
-#define RSCAN0C4ERFLHL RSCAN0.C4ERFL.UINT8[HL]
-#define RSCAN0C4ERFLHH RSCAN0.C4ERFL.UINT8[HH]
-#define RSCAN0GCFG RSCAN0.GCFG.UINT32
-#define RSCAN0GCFGL RSCAN0.GCFG.UINT16[L]
-#define RSCAN0GCFGLL RSCAN0.GCFG.UINT8[LL]
-#define RSCAN0GCFGLH RSCAN0.GCFG.UINT8[LH]
-#define RSCAN0GCFGH RSCAN0.GCFG.UINT16[H]
-#define RSCAN0GCFGHL RSCAN0.GCFG.UINT8[HL]
-#define RSCAN0GCFGHH RSCAN0.GCFG.UINT8[HH]
-#define RSCAN0GCTR RSCAN0.GCTR.UINT32
-#define RSCAN0GCTRL RSCAN0.GCTR.UINT16[L]
-#define RSCAN0GCTRLL RSCAN0.GCTR.UINT8[LL]
-#define RSCAN0GCTRLH RSCAN0.GCTR.UINT8[LH]
-#define RSCAN0GCTRH RSCAN0.GCTR.UINT16[H]
-#define RSCAN0GCTRHL RSCAN0.GCTR.UINT8[HL]
-#define RSCAN0GCTRHH RSCAN0.GCTR.UINT8[HH]
-#define RSCAN0GSTS RSCAN0.GSTS.UINT32
-#define RSCAN0GSTSL RSCAN0.GSTS.UINT16[L]
-#define RSCAN0GSTSLL RSCAN0.GSTS.UINT8[LL]
-#define RSCAN0GSTSLH RSCAN0.GSTS.UINT8[LH]
-#define RSCAN0GSTSH RSCAN0.GSTS.UINT16[H]
-#define RSCAN0GSTSHL RSCAN0.GSTS.UINT8[HL]
-#define RSCAN0GSTSHH RSCAN0.GSTS.UINT8[HH]
-#define RSCAN0GERFL RSCAN0.GERFL.UINT32
-#define RSCAN0GERFLL RSCAN0.GERFL.UINT16[L]
-#define RSCAN0GERFLLL RSCAN0.GERFL.UINT8[LL]
-#define RSCAN0GERFLLH RSCAN0.GERFL.UINT8[LH]
-#define RSCAN0GERFLH RSCAN0.GERFL.UINT16[H]
-#define RSCAN0GERFLHL RSCAN0.GERFL.UINT8[HL]
-#define RSCAN0GERFLHH RSCAN0.GERFL.UINT8[HH]
-#define RSCAN0GTSC RSCAN0.GTSC.UINT32
-#define RSCAN0GTSCL RSCAN0.GTSC.UINT16[L]
-#define RSCAN0GTSCH RSCAN0.GTSC.UINT16[H]
-#define RSCAN0GAFLECTR RSCAN0.GAFLECTR.UINT32
-#define RSCAN0GAFLECTRL RSCAN0.GAFLECTR.UINT16[L]
-#define RSCAN0GAFLECTRLL RSCAN0.GAFLECTR.UINT8[LL]
-#define RSCAN0GAFLECTRLH RSCAN0.GAFLECTR.UINT8[LH]
-#define RSCAN0GAFLECTRH RSCAN0.GAFLECTR.UINT16[H]
-#define RSCAN0GAFLECTRHL RSCAN0.GAFLECTR.UINT8[HL]
-#define RSCAN0GAFLECTRHH RSCAN0.GAFLECTR.UINT8[HH]
-#define RSCAN0GAFLCFG0 RSCAN0.GAFLCFG0.UINT32
-#define RSCAN0GAFLCFG0L RSCAN0.GAFLCFG0.UINT16[L]
-#define RSCAN0GAFLCFG0LL RSCAN0.GAFLCFG0.UINT8[LL]
-#define RSCAN0GAFLCFG0LH RSCAN0.GAFLCFG0.UINT8[LH]
-#define RSCAN0GAFLCFG0H RSCAN0.GAFLCFG0.UINT16[H]
-#define RSCAN0GAFLCFG0HL RSCAN0.GAFLCFG0.UINT8[HL]
-#define RSCAN0GAFLCFG0HH RSCAN0.GAFLCFG0.UINT8[HH]
-#define RSCAN0GAFLCFG1 RSCAN0.GAFLCFG1.UINT32
-#define RSCAN0GAFLCFG1L RSCAN0.GAFLCFG1.UINT16[L]
-#define RSCAN0GAFLCFG1LL RSCAN0.GAFLCFG1.UINT8[LL]
-#define RSCAN0GAFLCFG1LH RSCAN0.GAFLCFG1.UINT8[LH]
-#define RSCAN0GAFLCFG1H RSCAN0.GAFLCFG1.UINT16[H]
-#define RSCAN0GAFLCFG1HL RSCAN0.GAFLCFG1.UINT8[HL]
-#define RSCAN0GAFLCFG1HH RSCAN0.GAFLCFG1.UINT8[HH]
-#define RSCAN0RMNB RSCAN0.RMNB.UINT32
-#define RSCAN0RMNBL RSCAN0.RMNB.UINT16[L]
-#define RSCAN0RMNBLL RSCAN0.RMNB.UINT8[LL]
-#define RSCAN0RMNBLH RSCAN0.RMNB.UINT8[LH]
-#define RSCAN0RMNBH RSCAN0.RMNB.UINT16[H]
-#define RSCAN0RMNBHL RSCAN0.RMNB.UINT8[HL]
-#define RSCAN0RMNBHH RSCAN0.RMNB.UINT8[HH]
-#define RSCAN0RMND0 RSCAN0.RMND0.UINT32
-#define RSCAN0RMND0L RSCAN0.RMND0.UINT16[L]
-#define RSCAN0RMND0LL RSCAN0.RMND0.UINT8[LL]
-#define RSCAN0RMND0LH RSCAN0.RMND0.UINT8[LH]
-#define RSCAN0RMND0H RSCAN0.RMND0.UINT16[H]
-#define RSCAN0RMND0HL RSCAN0.RMND0.UINT8[HL]
-#define RSCAN0RMND0HH RSCAN0.RMND0.UINT8[HH]
-#define RSCAN0RMND1 RSCAN0.RMND1.UINT32
-#define RSCAN0RMND1L RSCAN0.RMND1.UINT16[L]
-#define RSCAN0RMND1LL RSCAN0.RMND1.UINT8[LL]
-#define RSCAN0RMND1LH RSCAN0.RMND1.UINT8[LH]
-#define RSCAN0RMND1H RSCAN0.RMND1.UINT16[H]
-#define RSCAN0RMND1HL RSCAN0.RMND1.UINT8[HL]
-#define RSCAN0RMND1HH RSCAN0.RMND1.UINT8[HH]
-#define RSCAN0RMND2 RSCAN0.RMND2.UINT32
-#define RSCAN0RMND2L RSCAN0.RMND2.UINT16[L]
-#define RSCAN0RMND2LL RSCAN0.RMND2.UINT8[LL]
-#define RSCAN0RMND2LH RSCAN0.RMND2.UINT8[LH]
-#define RSCAN0RMND2H RSCAN0.RMND2.UINT16[H]
-#define RSCAN0RMND2HL RSCAN0.RMND2.UINT8[HL]
-#define RSCAN0RMND2HH RSCAN0.RMND2.UINT8[HH]
-#define RSCAN0RFCC0 RSCAN0.RFCC0.UINT32
-#define RSCAN0RFCC0L RSCAN0.RFCC0.UINT16[L]
-#define RSCAN0RFCC0LL RSCAN0.RFCC0.UINT8[LL]
-#define RSCAN0RFCC0LH RSCAN0.RFCC0.UINT8[LH]
-#define RSCAN0RFCC0H RSCAN0.RFCC0.UINT16[H]
-#define RSCAN0RFCC0HL RSCAN0.RFCC0.UINT8[HL]
-#define RSCAN0RFCC0HH RSCAN0.RFCC0.UINT8[HH]
-#define RSCAN0RFCC1 RSCAN0.RFCC1.UINT32
-#define RSCAN0RFCC1L RSCAN0.RFCC1.UINT16[L]
-#define RSCAN0RFCC1LL RSCAN0.RFCC1.UINT8[LL]
-#define RSCAN0RFCC1LH RSCAN0.RFCC1.UINT8[LH]
-#define RSCAN0RFCC1H RSCAN0.RFCC1.UINT16[H]
-#define RSCAN0RFCC1HL RSCAN0.RFCC1.UINT8[HL]
-#define RSCAN0RFCC1HH RSCAN0.RFCC1.UINT8[HH]
-#define RSCAN0RFCC2 RSCAN0.RFCC2.UINT32
-#define RSCAN0RFCC2L RSCAN0.RFCC2.UINT16[L]
-#define RSCAN0RFCC2LL RSCAN0.RFCC2.UINT8[LL]
-#define RSCAN0RFCC2LH RSCAN0.RFCC2.UINT8[LH]
-#define RSCAN0RFCC2H RSCAN0.RFCC2.UINT16[H]
-#define RSCAN0RFCC2HL RSCAN0.RFCC2.UINT8[HL]
-#define RSCAN0RFCC2HH RSCAN0.RFCC2.UINT8[HH]
-#define RSCAN0RFCC3 RSCAN0.RFCC3.UINT32
-#define RSCAN0RFCC3L RSCAN0.RFCC3.UINT16[L]
-#define RSCAN0RFCC3LL RSCAN0.RFCC3.UINT8[LL]
-#define RSCAN0RFCC3LH RSCAN0.RFCC3.UINT8[LH]
-#define RSCAN0RFCC3H RSCAN0.RFCC3.UINT16[H]
-#define RSCAN0RFCC3HL RSCAN0.RFCC3.UINT8[HL]
-#define RSCAN0RFCC3HH RSCAN0.RFCC3.UINT8[HH]
-#define RSCAN0RFCC4 RSCAN0.RFCC4.UINT32
-#define RSCAN0RFCC4L RSCAN0.RFCC4.UINT16[L]
-#define RSCAN0RFCC4LL RSCAN0.RFCC4.UINT8[LL]
-#define RSCAN0RFCC4LH RSCAN0.RFCC4.UINT8[LH]
-#define RSCAN0RFCC4H RSCAN0.RFCC4.UINT16[H]
-#define RSCAN0RFCC4HL RSCAN0.RFCC4.UINT8[HL]
-#define RSCAN0RFCC4HH RSCAN0.RFCC4.UINT8[HH]
-#define RSCAN0RFCC5 RSCAN0.RFCC5.UINT32
-#define RSCAN0RFCC5L RSCAN0.RFCC5.UINT16[L]
-#define RSCAN0RFCC5LL RSCAN0.RFCC5.UINT8[LL]
-#define RSCAN0RFCC5LH RSCAN0.RFCC5.UINT8[LH]
-#define RSCAN0RFCC5H RSCAN0.RFCC5.UINT16[H]
-#define RSCAN0RFCC5HL RSCAN0.RFCC5.UINT8[HL]
-#define RSCAN0RFCC5HH RSCAN0.RFCC5.UINT8[HH]
-#define RSCAN0RFCC6 RSCAN0.RFCC6.UINT32
-#define RSCAN0RFCC6L RSCAN0.RFCC6.UINT16[L]
-#define RSCAN0RFCC6LL RSCAN0.RFCC6.UINT8[LL]
-#define RSCAN0RFCC6LH RSCAN0.RFCC6.UINT8[LH]
-#define RSCAN0RFCC6H RSCAN0.RFCC6.UINT16[H]
-#define RSCAN0RFCC6HL RSCAN0.RFCC6.UINT8[HL]
-#define RSCAN0RFCC6HH RSCAN0.RFCC6.UINT8[HH]
-#define RSCAN0RFCC7 RSCAN0.RFCC7.UINT32
-#define RSCAN0RFCC7L RSCAN0.RFCC7.UINT16[L]
-#define RSCAN0RFCC7LL RSCAN0.RFCC7.UINT8[LL]
-#define RSCAN0RFCC7LH RSCAN0.RFCC7.UINT8[LH]
-#define RSCAN0RFCC7H RSCAN0.RFCC7.UINT16[H]
-#define RSCAN0RFCC7HL RSCAN0.RFCC7.UINT8[HL]
-#define RSCAN0RFCC7HH RSCAN0.RFCC7.UINT8[HH]
-#define RSCAN0RFSTS0 RSCAN0.RFSTS0.UINT32
-#define RSCAN0RFSTS0L RSCAN0.RFSTS0.UINT16[L]
-#define RSCAN0RFSTS0LL RSCAN0.RFSTS0.UINT8[LL]
-#define RSCAN0RFSTS0LH RSCAN0.RFSTS0.UINT8[LH]
-#define RSCAN0RFSTS0H RSCAN0.RFSTS0.UINT16[H]
-#define RSCAN0RFSTS0HL RSCAN0.RFSTS0.UINT8[HL]
-#define RSCAN0RFSTS0HH RSCAN0.RFSTS0.UINT8[HH]
-#define RSCAN0RFSTS1 RSCAN0.RFSTS1.UINT32
-#define RSCAN0RFSTS1L RSCAN0.RFSTS1.UINT16[L]
-#define RSCAN0RFSTS1LL RSCAN0.RFSTS1.UINT8[LL]
-#define RSCAN0RFSTS1LH RSCAN0.RFSTS1.UINT8[LH]
-#define RSCAN0RFSTS1H RSCAN0.RFSTS1.UINT16[H]
-#define RSCAN0RFSTS1HL RSCAN0.RFSTS1.UINT8[HL]
-#define RSCAN0RFSTS1HH RSCAN0.RFSTS1.UINT8[HH]
-#define RSCAN0RFSTS2 RSCAN0.RFSTS2.UINT32
-#define RSCAN0RFSTS2L RSCAN0.RFSTS2.UINT16[L]
-#define RSCAN0RFSTS2LL RSCAN0.RFSTS2.UINT8[LL]
-#define RSCAN0RFSTS2LH RSCAN0.RFSTS2.UINT8[LH]
-#define RSCAN0RFSTS2H RSCAN0.RFSTS2.UINT16[H]
-#define RSCAN0RFSTS2HL RSCAN0.RFSTS2.UINT8[HL]
-#define RSCAN0RFSTS2HH RSCAN0.RFSTS2.UINT8[HH]
-#define RSCAN0RFSTS3 RSCAN0.RFSTS3.UINT32
-#define RSCAN0RFSTS3L RSCAN0.RFSTS3.UINT16[L]
-#define RSCAN0RFSTS3LL RSCAN0.RFSTS3.UINT8[LL]
-#define RSCAN0RFSTS3LH RSCAN0.RFSTS3.UINT8[LH]
-#define RSCAN0RFSTS3H RSCAN0.RFSTS3.UINT16[H]
-#define RSCAN0RFSTS3HL RSCAN0.RFSTS3.UINT8[HL]
-#define RSCAN0RFSTS3HH RSCAN0.RFSTS3.UINT8[HH]
-#define RSCAN0RFSTS4 RSCAN0.RFSTS4.UINT32
-#define RSCAN0RFSTS4L RSCAN0.RFSTS4.UINT16[L]
-#define RSCAN0RFSTS4LL RSCAN0.RFSTS4.UINT8[LL]
-#define RSCAN0RFSTS4LH RSCAN0.RFSTS4.UINT8[LH]
-#define RSCAN0RFSTS4H RSCAN0.RFSTS4.UINT16[H]
-#define RSCAN0RFSTS4HL RSCAN0.RFSTS4.UINT8[HL]
-#define RSCAN0RFSTS4HH RSCAN0.RFSTS4.UINT8[HH]
-#define RSCAN0RFSTS5 RSCAN0.RFSTS5.UINT32
-#define RSCAN0RFSTS5L RSCAN0.RFSTS5.UINT16[L]
-#define RSCAN0RFSTS5LL RSCAN0.RFSTS5.UINT8[LL]
-#define RSCAN0RFSTS5LH RSCAN0.RFSTS5.UINT8[LH]
-#define RSCAN0RFSTS5H RSCAN0.RFSTS5.UINT16[H]
-#define RSCAN0RFSTS5HL RSCAN0.RFSTS5.UINT8[HL]
-#define RSCAN0RFSTS5HH RSCAN0.RFSTS5.UINT8[HH]
-#define RSCAN0RFSTS6 RSCAN0.RFSTS6.UINT32
-#define RSCAN0RFSTS6L RSCAN0.RFSTS6.UINT16[L]
-#define RSCAN0RFSTS6LL RSCAN0.RFSTS6.UINT8[LL]
-#define RSCAN0RFSTS6LH RSCAN0.RFSTS6.UINT8[LH]
-#define RSCAN0RFSTS6H RSCAN0.RFSTS6.UINT16[H]
-#define RSCAN0RFSTS6HL RSCAN0.RFSTS6.UINT8[HL]
-#define RSCAN0RFSTS6HH RSCAN0.RFSTS6.UINT8[HH]
-#define RSCAN0RFSTS7 RSCAN0.RFSTS7.UINT32
-#define RSCAN0RFSTS7L RSCAN0.RFSTS7.UINT16[L]
-#define RSCAN0RFSTS7LL RSCAN0.RFSTS7.UINT8[LL]
-#define RSCAN0RFSTS7LH RSCAN0.RFSTS7.UINT8[LH]
-#define RSCAN0RFSTS7H RSCAN0.RFSTS7.UINT16[H]
-#define RSCAN0RFSTS7HL RSCAN0.RFSTS7.UINT8[HL]
-#define RSCAN0RFSTS7HH RSCAN0.RFSTS7.UINT8[HH]
-#define RSCAN0RFPCTR0 RSCAN0.RFPCTR0.UINT32
-#define RSCAN0RFPCTR0L RSCAN0.RFPCTR0.UINT16[L]
-#define RSCAN0RFPCTR0LL RSCAN0.RFPCTR0.UINT8[LL]
-#define RSCAN0RFPCTR0LH RSCAN0.RFPCTR0.UINT8[LH]
-#define RSCAN0RFPCTR0H RSCAN0.RFPCTR0.UINT16[H]
-#define RSCAN0RFPCTR0HL RSCAN0.RFPCTR0.UINT8[HL]
-#define RSCAN0RFPCTR0HH RSCAN0.RFPCTR0.UINT8[HH]
-#define RSCAN0RFPCTR1 RSCAN0.RFPCTR1.UINT32
-#define RSCAN0RFPCTR1L RSCAN0.RFPCTR1.UINT16[L]
-#define RSCAN0RFPCTR1LL RSCAN0.RFPCTR1.UINT8[LL]
-#define RSCAN0RFPCTR1LH RSCAN0.RFPCTR1.UINT8[LH]
-#define RSCAN0RFPCTR1H RSCAN0.RFPCTR1.UINT16[H]
-#define RSCAN0RFPCTR1HL RSCAN0.RFPCTR1.UINT8[HL]
-#define RSCAN0RFPCTR1HH RSCAN0.RFPCTR1.UINT8[HH]
-#define RSCAN0RFPCTR2 RSCAN0.RFPCTR2.UINT32
-#define RSCAN0RFPCTR2L RSCAN0.RFPCTR2.UINT16[L]
-#define RSCAN0RFPCTR2LL RSCAN0.RFPCTR2.UINT8[LL]
-#define RSCAN0RFPCTR2LH RSCAN0.RFPCTR2.UINT8[LH]
-#define RSCAN0RFPCTR2H RSCAN0.RFPCTR2.UINT16[H]
-#define RSCAN0RFPCTR2HL RSCAN0.RFPCTR2.UINT8[HL]
-#define RSCAN0RFPCTR2HH RSCAN0.RFPCTR2.UINT8[HH]
-#define RSCAN0RFPCTR3 RSCAN0.RFPCTR3.UINT32
-#define RSCAN0RFPCTR3L RSCAN0.RFPCTR3.UINT16[L]
-#define RSCAN0RFPCTR3LL RSCAN0.RFPCTR3.UINT8[LL]
-#define RSCAN0RFPCTR3LH RSCAN0.RFPCTR3.UINT8[LH]
-#define RSCAN0RFPCTR3H RSCAN0.RFPCTR3.UINT16[H]
-#define RSCAN0RFPCTR3HL RSCAN0.RFPCTR3.UINT8[HL]
-#define RSCAN0RFPCTR3HH RSCAN0.RFPCTR3.UINT8[HH]
-#define RSCAN0RFPCTR4 RSCAN0.RFPCTR4.UINT32
-#define RSCAN0RFPCTR4L RSCAN0.RFPCTR4.UINT16[L]
-#define RSCAN0RFPCTR4LL RSCAN0.RFPCTR4.UINT8[LL]
-#define RSCAN0RFPCTR4LH RSCAN0.RFPCTR4.UINT8[LH]
-#define RSCAN0RFPCTR4H RSCAN0.RFPCTR4.UINT16[H]
-#define RSCAN0RFPCTR4HL RSCAN0.RFPCTR4.UINT8[HL]
-#define RSCAN0RFPCTR4HH RSCAN0.RFPCTR4.UINT8[HH]
-#define RSCAN0RFPCTR5 RSCAN0.RFPCTR5.UINT32
-#define RSCAN0RFPCTR5L RSCAN0.RFPCTR5.UINT16[L]
-#define RSCAN0RFPCTR5LL RSCAN0.RFPCTR5.UINT8[LL]
-#define RSCAN0RFPCTR5LH RSCAN0.RFPCTR5.UINT8[LH]
-#define RSCAN0RFPCTR5H RSCAN0.RFPCTR5.UINT16[H]
-#define RSCAN0RFPCTR5HL RSCAN0.RFPCTR5.UINT8[HL]
-#define RSCAN0RFPCTR5HH RSCAN0.RFPCTR5.UINT8[HH]
-#define RSCAN0RFPCTR6 RSCAN0.RFPCTR6.UINT32
-#define RSCAN0RFPCTR6L RSCAN0.RFPCTR6.UINT16[L]
-#define RSCAN0RFPCTR6LL RSCAN0.RFPCTR6.UINT8[LL]
-#define RSCAN0RFPCTR6LH RSCAN0.RFPCTR6.UINT8[LH]
-#define RSCAN0RFPCTR6H RSCAN0.RFPCTR6.UINT16[H]
-#define RSCAN0RFPCTR6HL RSCAN0.RFPCTR6.UINT8[HL]
-#define RSCAN0RFPCTR6HH RSCAN0.RFPCTR6.UINT8[HH]
-#define RSCAN0RFPCTR7 RSCAN0.RFPCTR7.UINT32
-#define RSCAN0RFPCTR7L RSCAN0.RFPCTR7.UINT16[L]
-#define RSCAN0RFPCTR7LL RSCAN0.RFPCTR7.UINT8[LL]
-#define RSCAN0RFPCTR7LH RSCAN0.RFPCTR7.UINT8[LH]
-#define RSCAN0RFPCTR7H RSCAN0.RFPCTR7.UINT16[H]
-#define RSCAN0RFPCTR7HL RSCAN0.RFPCTR7.UINT8[HL]
-#define RSCAN0RFPCTR7HH RSCAN0.RFPCTR7.UINT8[HH]
-#define RSCAN0CFCC0 RSCAN0.CFCC0.UINT32
-#define RSCAN0CFCC0L RSCAN0.CFCC0.UINT16[L]
-#define RSCAN0CFCC0LL RSCAN0.CFCC0.UINT8[LL]
-#define RSCAN0CFCC0LH RSCAN0.CFCC0.UINT8[LH]
-#define RSCAN0CFCC0H RSCAN0.CFCC0.UINT16[H]
-#define RSCAN0CFCC0HL RSCAN0.CFCC0.UINT8[HL]
-#define RSCAN0CFCC0HH RSCAN0.CFCC0.UINT8[HH]
-#define RSCAN0CFCC1 RSCAN0.CFCC1.UINT32
-#define RSCAN0CFCC1L RSCAN0.CFCC1.UINT16[L]
-#define RSCAN0CFCC1LL RSCAN0.CFCC1.UINT8[LL]
-#define RSCAN0CFCC1LH RSCAN0.CFCC1.UINT8[LH]
-#define RSCAN0CFCC1H RSCAN0.CFCC1.UINT16[H]
-#define RSCAN0CFCC1HL RSCAN0.CFCC1.UINT8[HL]
-#define RSCAN0CFCC1HH RSCAN0.CFCC1.UINT8[HH]
-#define RSCAN0CFCC2 RSCAN0.CFCC2.UINT32
-#define RSCAN0CFCC2L RSCAN0.CFCC2.UINT16[L]
-#define RSCAN0CFCC2LL RSCAN0.CFCC2.UINT8[LL]
-#define RSCAN0CFCC2LH RSCAN0.CFCC2.UINT8[LH]
-#define RSCAN0CFCC2H RSCAN0.CFCC2.UINT16[H]
-#define RSCAN0CFCC2HL RSCAN0.CFCC2.UINT8[HL]
-#define RSCAN0CFCC2HH RSCAN0.CFCC2.UINT8[HH]
-#define RSCAN0CFCC3 RSCAN0.CFCC3.UINT32
-#define RSCAN0CFCC3L RSCAN0.CFCC3.UINT16[L]
-#define RSCAN0CFCC3LL RSCAN0.CFCC3.UINT8[LL]
-#define RSCAN0CFCC3LH RSCAN0.CFCC3.UINT8[LH]
-#define RSCAN0CFCC3H RSCAN0.CFCC3.UINT16[H]
-#define RSCAN0CFCC3HL RSCAN0.CFCC3.UINT8[HL]
-#define RSCAN0CFCC3HH RSCAN0.CFCC3.UINT8[HH]
-#define RSCAN0CFCC4 RSCAN0.CFCC4.UINT32
-#define RSCAN0CFCC4L RSCAN0.CFCC4.UINT16[L]
-#define RSCAN0CFCC4LL RSCAN0.CFCC4.UINT8[LL]
-#define RSCAN0CFCC4LH RSCAN0.CFCC4.UINT8[LH]
-#define RSCAN0CFCC4H RSCAN0.CFCC4.UINT16[H]
-#define RSCAN0CFCC4HL RSCAN0.CFCC4.UINT8[HL]
-#define RSCAN0CFCC4HH RSCAN0.CFCC4.UINT8[HH]
-#define RSCAN0CFCC5 RSCAN0.CFCC5.UINT32
-#define RSCAN0CFCC5L RSCAN0.CFCC5.UINT16[L]
-#define RSCAN0CFCC5LL RSCAN0.CFCC5.UINT8[LL]
-#define RSCAN0CFCC5LH RSCAN0.CFCC5.UINT8[LH]
-#define RSCAN0CFCC5H RSCAN0.CFCC5.UINT16[H]
-#define RSCAN0CFCC5HL RSCAN0.CFCC5.UINT8[HL]
-#define RSCAN0CFCC5HH RSCAN0.CFCC5.UINT8[HH]
-#define RSCAN0CFCC6 RSCAN0.CFCC6.UINT32
-#define RSCAN0CFCC6L RSCAN0.CFCC6.UINT16[L]
-#define RSCAN0CFCC6LL RSCAN0.CFCC6.UINT8[LL]
-#define RSCAN0CFCC6LH RSCAN0.CFCC6.UINT8[LH]
-#define RSCAN0CFCC6H RSCAN0.CFCC6.UINT16[H]
-#define RSCAN0CFCC6HL RSCAN0.CFCC6.UINT8[HL]
-#define RSCAN0CFCC6HH RSCAN0.CFCC6.UINT8[HH]
-#define RSCAN0CFCC7 RSCAN0.CFCC7.UINT32
-#define RSCAN0CFCC7L RSCAN0.CFCC7.UINT16[L]
-#define RSCAN0CFCC7LL RSCAN0.CFCC7.UINT8[LL]
-#define RSCAN0CFCC7LH RSCAN0.CFCC7.UINT8[LH]
-#define RSCAN0CFCC7H RSCAN0.CFCC7.UINT16[H]
-#define RSCAN0CFCC7HL RSCAN0.CFCC7.UINT8[HL]
-#define RSCAN0CFCC7HH RSCAN0.CFCC7.UINT8[HH]
-#define RSCAN0CFCC8 RSCAN0.CFCC8.UINT32
-#define RSCAN0CFCC8L RSCAN0.CFCC8.UINT16[L]
-#define RSCAN0CFCC8LL RSCAN0.CFCC8.UINT8[LL]
-#define RSCAN0CFCC8LH RSCAN0.CFCC8.UINT8[LH]
-#define RSCAN0CFCC8H RSCAN0.CFCC8.UINT16[H]
-#define RSCAN0CFCC8HL RSCAN0.CFCC8.UINT8[HL]
-#define RSCAN0CFCC8HH RSCAN0.CFCC8.UINT8[HH]
-#define RSCAN0CFCC9 RSCAN0.CFCC9.UINT32
-#define RSCAN0CFCC9L RSCAN0.CFCC9.UINT16[L]
-#define RSCAN0CFCC9LL RSCAN0.CFCC9.UINT8[LL]
-#define RSCAN0CFCC9LH RSCAN0.CFCC9.UINT8[LH]
-#define RSCAN0CFCC9H RSCAN0.CFCC9.UINT16[H]
-#define RSCAN0CFCC9HL RSCAN0.CFCC9.UINT8[HL]
-#define RSCAN0CFCC9HH RSCAN0.CFCC9.UINT8[HH]
-#define RSCAN0CFCC10 RSCAN0.CFCC10.UINT32
-#define RSCAN0CFCC10L RSCAN0.CFCC10.UINT16[L]
-#define RSCAN0CFCC10LL RSCAN0.CFCC10.UINT8[LL]
-#define RSCAN0CFCC10LH RSCAN0.CFCC10.UINT8[LH]
-#define RSCAN0CFCC10H RSCAN0.CFCC10.UINT16[H]
-#define RSCAN0CFCC10HL RSCAN0.CFCC10.UINT8[HL]
-#define RSCAN0CFCC10HH RSCAN0.CFCC10.UINT8[HH]
-#define RSCAN0CFCC11 RSCAN0.CFCC11.UINT32
-#define RSCAN0CFCC11L RSCAN0.CFCC11.UINT16[L]
-#define RSCAN0CFCC11LL RSCAN0.CFCC11.UINT8[LL]
-#define RSCAN0CFCC11LH RSCAN0.CFCC11.UINT8[LH]
-#define RSCAN0CFCC11H RSCAN0.CFCC11.UINT16[H]
-#define RSCAN0CFCC11HL RSCAN0.CFCC11.UINT8[HL]
-#define RSCAN0CFCC11HH RSCAN0.CFCC11.UINT8[HH]
-#define RSCAN0CFCC12 RSCAN0.CFCC12.UINT32
-#define RSCAN0CFCC12L RSCAN0.CFCC12.UINT16[L]
-#define RSCAN0CFCC12LL RSCAN0.CFCC12.UINT8[LL]
-#define RSCAN0CFCC12LH RSCAN0.CFCC12.UINT8[LH]
-#define RSCAN0CFCC12H RSCAN0.CFCC12.UINT16[H]
-#define RSCAN0CFCC12HL RSCAN0.CFCC12.UINT8[HL]
-#define RSCAN0CFCC12HH RSCAN0.CFCC12.UINT8[HH]
-#define RSCAN0CFCC13 RSCAN0.CFCC13.UINT32
-#define RSCAN0CFCC13L RSCAN0.CFCC13.UINT16[L]
-#define RSCAN0CFCC13LL RSCAN0.CFCC13.UINT8[LL]
-#define RSCAN0CFCC13LH RSCAN0.CFCC13.UINT8[LH]
-#define RSCAN0CFCC13H RSCAN0.CFCC13.UINT16[H]
-#define RSCAN0CFCC13HL RSCAN0.CFCC13.UINT8[HL]
-#define RSCAN0CFCC13HH RSCAN0.CFCC13.UINT8[HH]
-#define RSCAN0CFCC14 RSCAN0.CFCC14.UINT32
-#define RSCAN0CFCC14L RSCAN0.CFCC14.UINT16[L]
-#define RSCAN0CFCC14LL RSCAN0.CFCC14.UINT8[LL]
-#define RSCAN0CFCC14LH RSCAN0.CFCC14.UINT8[LH]
-#define RSCAN0CFCC14H RSCAN0.CFCC14.UINT16[H]
-#define RSCAN0CFCC14HL RSCAN0.CFCC14.UINT8[HL]
-#define RSCAN0CFCC14HH RSCAN0.CFCC14.UINT8[HH]
-#define RSCAN0CFSTS0 RSCAN0.CFSTS0.UINT32
-#define RSCAN0CFSTS0L RSCAN0.CFSTS0.UINT16[L]
-#define RSCAN0CFSTS0LL RSCAN0.CFSTS0.UINT8[LL]
-#define RSCAN0CFSTS0LH RSCAN0.CFSTS0.UINT8[LH]
-#define RSCAN0CFSTS0H RSCAN0.CFSTS0.UINT16[H]
-#define RSCAN0CFSTS0HL RSCAN0.CFSTS0.UINT8[HL]
-#define RSCAN0CFSTS0HH RSCAN0.CFSTS0.UINT8[HH]
-#define RSCAN0CFSTS1 RSCAN0.CFSTS1.UINT32
-#define RSCAN0CFSTS1L RSCAN0.CFSTS1.UINT16[L]
-#define RSCAN0CFSTS1LL RSCAN0.CFSTS1.UINT8[LL]
-#define RSCAN0CFSTS1LH RSCAN0.CFSTS1.UINT8[LH]
-#define RSCAN0CFSTS1H RSCAN0.CFSTS1.UINT16[H]
-#define RSCAN0CFSTS1HL RSCAN0.CFSTS1.UINT8[HL]
-#define RSCAN0CFSTS1HH RSCAN0.CFSTS1.UINT8[HH]
-#define RSCAN0CFSTS2 RSCAN0.CFSTS2.UINT32
-#define RSCAN0CFSTS2L RSCAN0.CFSTS2.UINT16[L]
-#define RSCAN0CFSTS2LL RSCAN0.CFSTS2.UINT8[LL]
-#define RSCAN0CFSTS2LH RSCAN0.CFSTS2.UINT8[LH]
-#define RSCAN0CFSTS2H RSCAN0.CFSTS2.UINT16[H]
-#define RSCAN0CFSTS2HL RSCAN0.CFSTS2.UINT8[HL]
-#define RSCAN0CFSTS2HH RSCAN0.CFSTS2.UINT8[HH]
-#define RSCAN0CFSTS3 RSCAN0.CFSTS3.UINT32
-#define RSCAN0CFSTS3L RSCAN0.CFSTS3.UINT16[L]
-#define RSCAN0CFSTS3LL RSCAN0.CFSTS3.UINT8[LL]
-#define RSCAN0CFSTS3LH RSCAN0.CFSTS3.UINT8[LH]
-#define RSCAN0CFSTS3H RSCAN0.CFSTS3.UINT16[H]
-#define RSCAN0CFSTS3HL RSCAN0.CFSTS3.UINT8[HL]
-#define RSCAN0CFSTS3HH RSCAN0.CFSTS3.UINT8[HH]
-#define RSCAN0CFSTS4 RSCAN0.CFSTS4.UINT32
-#define RSCAN0CFSTS4L RSCAN0.CFSTS4.UINT16[L]
-#define RSCAN0CFSTS4LL RSCAN0.CFSTS4.UINT8[LL]
-#define RSCAN0CFSTS4LH RSCAN0.CFSTS4.UINT8[LH]
-#define RSCAN0CFSTS4H RSCAN0.CFSTS4.UINT16[H]
-#define RSCAN0CFSTS4HL RSCAN0.CFSTS4.UINT8[HL]
-#define RSCAN0CFSTS4HH RSCAN0.CFSTS4.UINT8[HH]
-#define RSCAN0CFSTS5 RSCAN0.CFSTS5.UINT32
-#define RSCAN0CFSTS5L RSCAN0.CFSTS5.UINT16[L]
-#define RSCAN0CFSTS5LL RSCAN0.CFSTS5.UINT8[LL]
-#define RSCAN0CFSTS5LH RSCAN0.CFSTS5.UINT8[LH]
-#define RSCAN0CFSTS5H RSCAN0.CFSTS5.UINT16[H]
-#define RSCAN0CFSTS5HL RSCAN0.CFSTS5.UINT8[HL]
-#define RSCAN0CFSTS5HH RSCAN0.CFSTS5.UINT8[HH]
-#define RSCAN0CFSTS6 RSCAN0.CFSTS6.UINT32
-#define RSCAN0CFSTS6L RSCAN0.CFSTS6.UINT16[L]
-#define RSCAN0CFSTS6LL RSCAN0.CFSTS6.UINT8[LL]
-#define RSCAN0CFSTS6LH RSCAN0.CFSTS6.UINT8[LH]
-#define RSCAN0CFSTS6H RSCAN0.CFSTS6.UINT16[H]
-#define RSCAN0CFSTS6HL RSCAN0.CFSTS6.UINT8[HL]
-#define RSCAN0CFSTS6HH RSCAN0.CFSTS6.UINT8[HH]
-#define RSCAN0CFSTS7 RSCAN0.CFSTS7.UINT32
-#define RSCAN0CFSTS7L RSCAN0.CFSTS7.UINT16[L]
-#define RSCAN0CFSTS7LL RSCAN0.CFSTS7.UINT8[LL]
-#define RSCAN0CFSTS7LH RSCAN0.CFSTS7.UINT8[LH]
-#define RSCAN0CFSTS7H RSCAN0.CFSTS7.UINT16[H]
-#define RSCAN0CFSTS7HL RSCAN0.CFSTS7.UINT8[HL]
-#define RSCAN0CFSTS7HH RSCAN0.CFSTS7.UINT8[HH]
-#define RSCAN0CFSTS8 RSCAN0.CFSTS8.UINT32
-#define RSCAN0CFSTS8L RSCAN0.CFSTS8.UINT16[L]
-#define RSCAN0CFSTS8LL RSCAN0.CFSTS8.UINT8[LL]
-#define RSCAN0CFSTS8LH RSCAN0.CFSTS8.UINT8[LH]
-#define RSCAN0CFSTS8H RSCAN0.CFSTS8.UINT16[H]
-#define RSCAN0CFSTS8HL RSCAN0.CFSTS8.UINT8[HL]
-#define RSCAN0CFSTS8HH RSCAN0.CFSTS8.UINT8[HH]
-#define RSCAN0CFSTS9 RSCAN0.CFSTS9.UINT32
-#define RSCAN0CFSTS9L RSCAN0.CFSTS9.UINT16[L]
-#define RSCAN0CFSTS9LL RSCAN0.CFSTS9.UINT8[LL]
-#define RSCAN0CFSTS9LH RSCAN0.CFSTS9.UINT8[LH]
-#define RSCAN0CFSTS9H RSCAN0.CFSTS9.UINT16[H]
-#define RSCAN0CFSTS9HL RSCAN0.CFSTS9.UINT8[HL]
-#define RSCAN0CFSTS9HH RSCAN0.CFSTS9.UINT8[HH]
-#define RSCAN0CFSTS10 RSCAN0.CFSTS10.UINT32
-#define RSCAN0CFSTS10L RSCAN0.CFSTS10.UINT16[L]
-#define RSCAN0CFSTS10LL RSCAN0.CFSTS10.UINT8[LL]
-#define RSCAN0CFSTS10LH RSCAN0.CFSTS10.UINT8[LH]
-#define RSCAN0CFSTS10H RSCAN0.CFSTS10.UINT16[H]
-#define RSCAN0CFSTS10HL RSCAN0.CFSTS10.UINT8[HL]
-#define RSCAN0CFSTS10HH RSCAN0.CFSTS10.UINT8[HH]
-#define RSCAN0CFSTS11 RSCAN0.CFSTS11.UINT32
-#define RSCAN0CFSTS11L RSCAN0.CFSTS11.UINT16[L]
-#define RSCAN0CFSTS11LL RSCAN0.CFSTS11.UINT8[LL]
-#define RSCAN0CFSTS11LH RSCAN0.CFSTS11.UINT8[LH]
-#define RSCAN0CFSTS11H RSCAN0.CFSTS11.UINT16[H]
-#define RSCAN0CFSTS11HL RSCAN0.CFSTS11.UINT8[HL]
-#define RSCAN0CFSTS11HH RSCAN0.CFSTS11.UINT8[HH]
-#define RSCAN0CFSTS12 RSCAN0.CFSTS12.UINT32
-#define RSCAN0CFSTS12L RSCAN0.CFSTS12.UINT16[L]
-#define RSCAN0CFSTS12LL RSCAN0.CFSTS12.UINT8[LL]
-#define RSCAN0CFSTS12LH RSCAN0.CFSTS12.UINT8[LH]
-#define RSCAN0CFSTS12H RSCAN0.CFSTS12.UINT16[H]
-#define RSCAN0CFSTS12HL RSCAN0.CFSTS12.UINT8[HL]
-#define RSCAN0CFSTS12HH RSCAN0.CFSTS12.UINT8[HH]
-#define RSCAN0CFSTS13 RSCAN0.CFSTS13.UINT32
-#define RSCAN0CFSTS13L RSCAN0.CFSTS13.UINT16[L]
-#define RSCAN0CFSTS13LL RSCAN0.CFSTS13.UINT8[LL]
-#define RSCAN0CFSTS13LH RSCAN0.CFSTS13.UINT8[LH]
-#define RSCAN0CFSTS13H RSCAN0.CFSTS13.UINT16[H]
-#define RSCAN0CFSTS13HL RSCAN0.CFSTS13.UINT8[HL]
-#define RSCAN0CFSTS13HH RSCAN0.CFSTS13.UINT8[HH]
-#define RSCAN0CFSTS14 RSCAN0.CFSTS14.UINT32
-#define RSCAN0CFSTS14L RSCAN0.CFSTS14.UINT16[L]
-#define RSCAN0CFSTS14LL RSCAN0.CFSTS14.UINT8[LL]
-#define RSCAN0CFSTS14LH RSCAN0.CFSTS14.UINT8[LH]
-#define RSCAN0CFSTS14H RSCAN0.CFSTS14.UINT16[H]
-#define RSCAN0CFSTS14HL RSCAN0.CFSTS14.UINT8[HL]
-#define RSCAN0CFSTS14HH RSCAN0.CFSTS14.UINT8[HH]
-#define RSCAN0CFPCTR0 RSCAN0.CFPCTR0.UINT32
-#define RSCAN0CFPCTR0L RSCAN0.CFPCTR0.UINT16[L]
-#define RSCAN0CFPCTR0LL RSCAN0.CFPCTR0.UINT8[LL]
-#define RSCAN0CFPCTR0LH RSCAN0.CFPCTR0.UINT8[LH]
-#define RSCAN0CFPCTR0H RSCAN0.CFPCTR0.UINT16[H]
-#define RSCAN0CFPCTR0HL RSCAN0.CFPCTR0.UINT8[HL]
-#define RSCAN0CFPCTR0HH RSCAN0.CFPCTR0.UINT8[HH]
-#define RSCAN0CFPCTR1 RSCAN0.CFPCTR1.UINT32
-#define RSCAN0CFPCTR1L RSCAN0.CFPCTR1.UINT16[L]
-#define RSCAN0CFPCTR1LL RSCAN0.CFPCTR1.UINT8[LL]
-#define RSCAN0CFPCTR1LH RSCAN0.CFPCTR1.UINT8[LH]
-#define RSCAN0CFPCTR1H RSCAN0.CFPCTR1.UINT16[H]
-#define RSCAN0CFPCTR1HL RSCAN0.CFPCTR1.UINT8[HL]
-#define RSCAN0CFPCTR1HH RSCAN0.CFPCTR1.UINT8[HH]
-#define RSCAN0CFPCTR2 RSCAN0.CFPCTR2.UINT32
-#define RSCAN0CFPCTR2L RSCAN0.CFPCTR2.UINT16[L]
-#define RSCAN0CFPCTR2LL RSCAN0.CFPCTR2.UINT8[LL]
-#define RSCAN0CFPCTR2LH RSCAN0.CFPCTR2.UINT8[LH]
-#define RSCAN0CFPCTR2H RSCAN0.CFPCTR2.UINT16[H]
-#define RSCAN0CFPCTR2HL RSCAN0.CFPCTR2.UINT8[HL]
-#define RSCAN0CFPCTR2HH RSCAN0.CFPCTR2.UINT8[HH]
-#define RSCAN0CFPCTR3 RSCAN0.CFPCTR3.UINT32
-#define RSCAN0CFPCTR3L RSCAN0.CFPCTR3.UINT16[L]
-#define RSCAN0CFPCTR3LL RSCAN0.CFPCTR3.UINT8[LL]
-#define RSCAN0CFPCTR3LH RSCAN0.CFPCTR3.UINT8[LH]
-#define RSCAN0CFPCTR3H RSCAN0.CFPCTR3.UINT16[H]
-#define RSCAN0CFPCTR3HL RSCAN0.CFPCTR3.UINT8[HL]
-#define RSCAN0CFPCTR3HH RSCAN0.CFPCTR3.UINT8[HH]
-#define RSCAN0CFPCTR4 RSCAN0.CFPCTR4.UINT32
-#define RSCAN0CFPCTR4L RSCAN0.CFPCTR4.UINT16[L]
-#define RSCAN0CFPCTR4LL RSCAN0.CFPCTR4.UINT8[LL]
-#define RSCAN0CFPCTR4LH RSCAN0.CFPCTR4.UINT8[LH]
-#define RSCAN0CFPCTR4H RSCAN0.CFPCTR4.UINT16[H]
-#define RSCAN0CFPCTR4HL RSCAN0.CFPCTR4.UINT8[HL]
-#define RSCAN0CFPCTR4HH RSCAN0.CFPCTR4.UINT8[HH]
-#define RSCAN0CFPCTR5 RSCAN0.CFPCTR5.UINT32
-#define RSCAN0CFPCTR5L RSCAN0.CFPCTR5.UINT16[L]
-#define RSCAN0CFPCTR5LL RSCAN0.CFPCTR5.UINT8[LL]
-#define RSCAN0CFPCTR5LH RSCAN0.CFPCTR5.UINT8[LH]
-#define RSCAN0CFPCTR5H RSCAN0.CFPCTR5.UINT16[H]
-#define RSCAN0CFPCTR5HL RSCAN0.CFPCTR5.UINT8[HL]
-#define RSCAN0CFPCTR5HH RSCAN0.CFPCTR5.UINT8[HH]
-#define RSCAN0CFPCTR6 RSCAN0.CFPCTR6.UINT32
-#define RSCAN0CFPCTR6L RSCAN0.CFPCTR6.UINT16[L]
-#define RSCAN0CFPCTR6LL RSCAN0.CFPCTR6.UINT8[LL]
-#define RSCAN0CFPCTR6LH RSCAN0.CFPCTR6.UINT8[LH]
-#define RSCAN0CFPCTR6H RSCAN0.CFPCTR6.UINT16[H]
-#define RSCAN0CFPCTR6HL RSCAN0.CFPCTR6.UINT8[HL]
-#define RSCAN0CFPCTR6HH RSCAN0.CFPCTR6.UINT8[HH]
-#define RSCAN0CFPCTR7 RSCAN0.CFPCTR7.UINT32
-#define RSCAN0CFPCTR7L RSCAN0.CFPCTR7.UINT16[L]
-#define RSCAN0CFPCTR7LL RSCAN0.CFPCTR7.UINT8[LL]
-#define RSCAN0CFPCTR7LH RSCAN0.CFPCTR7.UINT8[LH]
-#define RSCAN0CFPCTR7H RSCAN0.CFPCTR7.UINT16[H]
-#define RSCAN0CFPCTR7HL RSCAN0.CFPCTR7.UINT8[HL]
-#define RSCAN0CFPCTR7HH RSCAN0.CFPCTR7.UINT8[HH]
-#define RSCAN0CFPCTR8 RSCAN0.CFPCTR8.UINT32
-#define RSCAN0CFPCTR8L RSCAN0.CFPCTR8.UINT16[L]
-#define RSCAN0CFPCTR8LL RSCAN0.CFPCTR8.UINT8[LL]
-#define RSCAN0CFPCTR8LH RSCAN0.CFPCTR8.UINT8[LH]
-#define RSCAN0CFPCTR8H RSCAN0.CFPCTR8.UINT16[H]
-#define RSCAN0CFPCTR8HL RSCAN0.CFPCTR8.UINT8[HL]
-#define RSCAN0CFPCTR8HH RSCAN0.CFPCTR8.UINT8[HH]
-#define RSCAN0CFPCTR9 RSCAN0.CFPCTR9.UINT32
-#define RSCAN0CFPCTR9L RSCAN0.CFPCTR9.UINT16[L]
-#define RSCAN0CFPCTR9LL RSCAN0.CFPCTR9.UINT8[LL]
-#define RSCAN0CFPCTR9LH RSCAN0.CFPCTR9.UINT8[LH]
-#define RSCAN0CFPCTR9H RSCAN0.CFPCTR9.UINT16[H]
-#define RSCAN0CFPCTR9HL RSCAN0.CFPCTR9.UINT8[HL]
-#define RSCAN0CFPCTR9HH RSCAN0.CFPCTR9.UINT8[HH]
-#define RSCAN0CFPCTR10 RSCAN0.CFPCTR10.UINT32
-#define RSCAN0CFPCTR10L RSCAN0.CFPCTR10.UINT16[L]
-#define RSCAN0CFPCTR10LL RSCAN0.CFPCTR10.UINT8[LL]
-#define RSCAN0CFPCTR10LH RSCAN0.CFPCTR10.UINT8[LH]
-#define RSCAN0CFPCTR10H RSCAN0.CFPCTR10.UINT16[H]
-#define RSCAN0CFPCTR10HL RSCAN0.CFPCTR10.UINT8[HL]
-#define RSCAN0CFPCTR10HH RSCAN0.CFPCTR10.UINT8[HH]
-#define RSCAN0CFPCTR11 RSCAN0.CFPCTR11.UINT32
-#define RSCAN0CFPCTR11L RSCAN0.CFPCTR11.UINT16[L]
-#define RSCAN0CFPCTR11LL RSCAN0.CFPCTR11.UINT8[LL]
-#define RSCAN0CFPCTR11LH RSCAN0.CFPCTR11.UINT8[LH]
-#define RSCAN0CFPCTR11H RSCAN0.CFPCTR11.UINT16[H]
-#define RSCAN0CFPCTR11HL RSCAN0.CFPCTR11.UINT8[HL]
-#define RSCAN0CFPCTR11HH RSCAN0.CFPCTR11.UINT8[HH]
-#define RSCAN0CFPCTR12 RSCAN0.CFPCTR12.UINT32
-#define RSCAN0CFPCTR12L RSCAN0.CFPCTR12.UINT16[L]
-#define RSCAN0CFPCTR12LL RSCAN0.CFPCTR12.UINT8[LL]
-#define RSCAN0CFPCTR12LH RSCAN0.CFPCTR12.UINT8[LH]
-#define RSCAN0CFPCTR12H RSCAN0.CFPCTR12.UINT16[H]
-#define RSCAN0CFPCTR12HL RSCAN0.CFPCTR12.UINT8[HL]
-#define RSCAN0CFPCTR12HH RSCAN0.CFPCTR12.UINT8[HH]
-#define RSCAN0CFPCTR13 RSCAN0.CFPCTR13.UINT32
-#define RSCAN0CFPCTR13L RSCAN0.CFPCTR13.UINT16[L]
-#define RSCAN0CFPCTR13LL RSCAN0.CFPCTR13.UINT8[LL]
-#define RSCAN0CFPCTR13LH RSCAN0.CFPCTR13.UINT8[LH]
-#define RSCAN0CFPCTR13H RSCAN0.CFPCTR13.UINT16[H]
-#define RSCAN0CFPCTR13HL RSCAN0.CFPCTR13.UINT8[HL]
-#define RSCAN0CFPCTR13HH RSCAN0.CFPCTR13.UINT8[HH]
-#define RSCAN0CFPCTR14 RSCAN0.CFPCTR14.UINT32
-#define RSCAN0CFPCTR14L RSCAN0.CFPCTR14.UINT16[L]
-#define RSCAN0CFPCTR14LL RSCAN0.CFPCTR14.UINT8[LL]
-#define RSCAN0CFPCTR14LH RSCAN0.CFPCTR14.UINT8[LH]
-#define RSCAN0CFPCTR14H RSCAN0.CFPCTR14.UINT16[H]
-#define RSCAN0CFPCTR14HL RSCAN0.CFPCTR14.UINT8[HL]
-#define RSCAN0CFPCTR14HH RSCAN0.CFPCTR14.UINT8[HH]
-#define RSCAN0FESTS RSCAN0.FESTS.UINT32
-#define RSCAN0FESTSL RSCAN0.FESTS.UINT16[L]
-#define RSCAN0FESTSLL RSCAN0.FESTS.UINT8[LL]
-#define RSCAN0FESTSLH RSCAN0.FESTS.UINT8[LH]
-#define RSCAN0FESTSH RSCAN0.FESTS.UINT16[H]
-#define RSCAN0FESTSHL RSCAN0.FESTS.UINT8[HL]
-#define RSCAN0FESTSHH RSCAN0.FESTS.UINT8[HH]
-#define RSCAN0FFSTS RSCAN0.FFSTS.UINT32
-#define RSCAN0FFSTSL RSCAN0.FFSTS.UINT16[L]
-#define RSCAN0FFSTSLL RSCAN0.FFSTS.UINT8[LL]
-#define RSCAN0FFSTSLH RSCAN0.FFSTS.UINT8[LH]
-#define RSCAN0FFSTSH RSCAN0.FFSTS.UINT16[H]
-#define RSCAN0FFSTSHL RSCAN0.FFSTS.UINT8[HL]
-#define RSCAN0FFSTSHH RSCAN0.FFSTS.UINT8[HH]
-#define RSCAN0FMSTS RSCAN0.FMSTS.UINT32
-#define RSCAN0FMSTSL RSCAN0.FMSTS.UINT16[L]
-#define RSCAN0FMSTSLL RSCAN0.FMSTS.UINT8[LL]
-#define RSCAN0FMSTSLH RSCAN0.FMSTS.UINT8[LH]
-#define RSCAN0FMSTSH RSCAN0.FMSTS.UINT16[H]
-#define RSCAN0FMSTSHL RSCAN0.FMSTS.UINT8[HL]
-#define RSCAN0FMSTSHH RSCAN0.FMSTS.UINT8[HH]
-#define RSCAN0RFISTS RSCAN0.RFISTS.UINT32
-#define RSCAN0RFISTSL RSCAN0.RFISTS.UINT16[L]
-#define RSCAN0RFISTSLL RSCAN0.RFISTS.UINT8[LL]
-#define RSCAN0RFISTSLH RSCAN0.RFISTS.UINT8[LH]
-#define RSCAN0RFISTSH RSCAN0.RFISTS.UINT16[H]
-#define RSCAN0RFISTSHL RSCAN0.RFISTS.UINT8[HL]
-#define RSCAN0RFISTSHH RSCAN0.RFISTS.UINT8[HH]
-#define RSCAN0CFRISTS RSCAN0.CFRISTS.UINT32
-#define RSCAN0CFRISTSL RSCAN0.CFRISTS.UINT16[L]
-#define RSCAN0CFRISTSLL RSCAN0.CFRISTS.UINT8[LL]
-#define RSCAN0CFRISTSLH RSCAN0.CFRISTS.UINT8[LH]
-#define RSCAN0CFRISTSH RSCAN0.CFRISTS.UINT16[H]
-#define RSCAN0CFRISTSHL RSCAN0.CFRISTS.UINT8[HL]
-#define RSCAN0CFRISTSHH RSCAN0.CFRISTS.UINT8[HH]
-#define RSCAN0CFTISTS RSCAN0.CFTISTS.UINT32
-#define RSCAN0CFTISTSL RSCAN0.CFTISTS.UINT16[L]
-#define RSCAN0CFTISTSLL RSCAN0.CFTISTS.UINT8[LL]
-#define RSCAN0CFTISTSLH RSCAN0.CFTISTS.UINT8[LH]
-#define RSCAN0CFTISTSH RSCAN0.CFTISTS.UINT16[H]
-#define RSCAN0CFTISTSHL RSCAN0.CFTISTS.UINT8[HL]
-#define RSCAN0CFTISTSHH RSCAN0.CFTISTS.UINT8[HH]
-#define RSCAN0TMC0 RSCAN0.TMC0
-#define RSCAN0TMC1 RSCAN0.TMC1
-#define RSCAN0TMC2 RSCAN0.TMC2
-#define RSCAN0TMC3 RSCAN0.TMC3
-#define RSCAN0TMC4 RSCAN0.TMC4
-#define RSCAN0TMC5 RSCAN0.TMC5
-#define RSCAN0TMC6 RSCAN0.TMC6
-#define RSCAN0TMC7 RSCAN0.TMC7
-#define RSCAN0TMC8 RSCAN0.TMC8
-#define RSCAN0TMC9 RSCAN0.TMC9
-#define RSCAN0TMC10 RSCAN0.TMC10
-#define RSCAN0TMC11 RSCAN0.TMC11
-#define RSCAN0TMC12 RSCAN0.TMC12
-#define RSCAN0TMC13 RSCAN0.TMC13
-#define RSCAN0TMC14 RSCAN0.TMC14
-#define RSCAN0TMC15 RSCAN0.TMC15
-#define RSCAN0TMC16 RSCAN0.TMC16
-#define RSCAN0TMC17 RSCAN0.TMC17
-#define RSCAN0TMC18 RSCAN0.TMC18
-#define RSCAN0TMC19 RSCAN0.TMC19
-#define RSCAN0TMC20 RSCAN0.TMC20
-#define RSCAN0TMC21 RSCAN0.TMC21
-#define RSCAN0TMC22 RSCAN0.TMC22
-#define RSCAN0TMC23 RSCAN0.TMC23
-#define RSCAN0TMC24 RSCAN0.TMC24
-#define RSCAN0TMC25 RSCAN0.TMC25
-#define RSCAN0TMC26 RSCAN0.TMC26
-#define RSCAN0TMC27 RSCAN0.TMC27
-#define RSCAN0TMC28 RSCAN0.TMC28
-#define RSCAN0TMC29 RSCAN0.TMC29
-#define RSCAN0TMC30 RSCAN0.TMC30
-#define RSCAN0TMC31 RSCAN0.TMC31
-#define RSCAN0TMC32 RSCAN0.TMC32
-#define RSCAN0TMC33 RSCAN0.TMC33
-#define RSCAN0TMC34 RSCAN0.TMC34
-#define RSCAN0TMC35 RSCAN0.TMC35
-#define RSCAN0TMC36 RSCAN0.TMC36
-#define RSCAN0TMC37 RSCAN0.TMC37
-#define RSCAN0TMC38 RSCAN0.TMC38
-#define RSCAN0TMC39 RSCAN0.TMC39
-#define RSCAN0TMC40 RSCAN0.TMC40
-#define RSCAN0TMC41 RSCAN0.TMC41
-#define RSCAN0TMC42 RSCAN0.TMC42
-#define RSCAN0TMC43 RSCAN0.TMC43
-#define RSCAN0TMC44 RSCAN0.TMC44
-#define RSCAN0TMC45 RSCAN0.TMC45
-#define RSCAN0TMC46 RSCAN0.TMC46
-#define RSCAN0TMC47 RSCAN0.TMC47
-#define RSCAN0TMC48 RSCAN0.TMC48
-#define RSCAN0TMC49 RSCAN0.TMC49
-#define RSCAN0TMC50 RSCAN0.TMC50
-#define RSCAN0TMC51 RSCAN0.TMC51
-#define RSCAN0TMC52 RSCAN0.TMC52
-#define RSCAN0TMC53 RSCAN0.TMC53
-#define RSCAN0TMC54 RSCAN0.TMC54
-#define RSCAN0TMC55 RSCAN0.TMC55
-#define RSCAN0TMC56 RSCAN0.TMC56
-#define RSCAN0TMC57 RSCAN0.TMC57
-#define RSCAN0TMC58 RSCAN0.TMC58
-#define RSCAN0TMC59 RSCAN0.TMC59
-#define RSCAN0TMC60 RSCAN0.TMC60
-#define RSCAN0TMC61 RSCAN0.TMC61
-#define RSCAN0TMC62 RSCAN0.TMC62
-#define RSCAN0TMC63 RSCAN0.TMC63
-#define RSCAN0TMC64 RSCAN0.TMC64
-#define RSCAN0TMC65 RSCAN0.TMC65
-#define RSCAN0TMC66 RSCAN0.TMC66
-#define RSCAN0TMC67 RSCAN0.TMC67
-#define RSCAN0TMC68 RSCAN0.TMC68
-#define RSCAN0TMC69 RSCAN0.TMC69
-#define RSCAN0TMC70 RSCAN0.TMC70
-#define RSCAN0TMC71 RSCAN0.TMC71
-#define RSCAN0TMC72 RSCAN0.TMC72
-#define RSCAN0TMC73 RSCAN0.TMC73
-#define RSCAN0TMC74 RSCAN0.TMC74
-#define RSCAN0TMC75 RSCAN0.TMC75
-#define RSCAN0TMC76 RSCAN0.TMC76
-#define RSCAN0TMC77 RSCAN0.TMC77
-#define RSCAN0TMC78 RSCAN0.TMC78
-#define RSCAN0TMC79 RSCAN0.TMC79
-#define RSCAN0TMSTS0 RSCAN0.TMSTS0
-#define RSCAN0TMSTS1 RSCAN0.TMSTS1
-#define RSCAN0TMSTS2 RSCAN0.TMSTS2
-#define RSCAN0TMSTS3 RSCAN0.TMSTS3
-#define RSCAN0TMSTS4 RSCAN0.TMSTS4
-#define RSCAN0TMSTS5 RSCAN0.TMSTS5
-#define RSCAN0TMSTS6 RSCAN0.TMSTS6
-#define RSCAN0TMSTS7 RSCAN0.TMSTS7
-#define RSCAN0TMSTS8 RSCAN0.TMSTS8
-#define RSCAN0TMSTS9 RSCAN0.TMSTS9
-#define RSCAN0TMSTS10 RSCAN0.TMSTS10
-#define RSCAN0TMSTS11 RSCAN0.TMSTS11
-#define RSCAN0TMSTS12 RSCAN0.TMSTS12
-#define RSCAN0TMSTS13 RSCAN0.TMSTS13
-#define RSCAN0TMSTS14 RSCAN0.TMSTS14
-#define RSCAN0TMSTS15 RSCAN0.TMSTS15
-#define RSCAN0TMSTS16 RSCAN0.TMSTS16
-#define RSCAN0TMSTS17 RSCAN0.TMSTS17
-#define RSCAN0TMSTS18 RSCAN0.TMSTS18
-#define RSCAN0TMSTS19 RSCAN0.TMSTS19
-#define RSCAN0TMSTS20 RSCAN0.TMSTS20
-#define RSCAN0TMSTS21 RSCAN0.TMSTS21
-#define RSCAN0TMSTS22 RSCAN0.TMSTS22
-#define RSCAN0TMSTS23 RSCAN0.TMSTS23
-#define RSCAN0TMSTS24 RSCAN0.TMSTS24
-#define RSCAN0TMSTS25 RSCAN0.TMSTS25
-#define RSCAN0TMSTS26 RSCAN0.TMSTS26
-#define RSCAN0TMSTS27 RSCAN0.TMSTS27
-#define RSCAN0TMSTS28 RSCAN0.TMSTS28
-#define RSCAN0TMSTS29 RSCAN0.TMSTS29
-#define RSCAN0TMSTS30 RSCAN0.TMSTS30
-#define RSCAN0TMSTS31 RSCAN0.TMSTS31
-#define RSCAN0TMSTS32 RSCAN0.TMSTS32
-#define RSCAN0TMSTS33 RSCAN0.TMSTS33
-#define RSCAN0TMSTS34 RSCAN0.TMSTS34
-#define RSCAN0TMSTS35 RSCAN0.TMSTS35
-#define RSCAN0TMSTS36 RSCAN0.TMSTS36
-#define RSCAN0TMSTS37 RSCAN0.TMSTS37
-#define RSCAN0TMSTS38 RSCAN0.TMSTS38
-#define RSCAN0TMSTS39 RSCAN0.TMSTS39
-#define RSCAN0TMSTS40 RSCAN0.TMSTS40
-#define RSCAN0TMSTS41 RSCAN0.TMSTS41
-#define RSCAN0TMSTS42 RSCAN0.TMSTS42
-#define RSCAN0TMSTS43 RSCAN0.TMSTS43
-#define RSCAN0TMSTS44 RSCAN0.TMSTS44
-#define RSCAN0TMSTS45 RSCAN0.TMSTS45
-#define RSCAN0TMSTS46 RSCAN0.TMSTS46
-#define RSCAN0TMSTS47 RSCAN0.TMSTS47
-#define RSCAN0TMSTS48 RSCAN0.TMSTS48
-#define RSCAN0TMSTS49 RSCAN0.TMSTS49
-#define RSCAN0TMSTS50 RSCAN0.TMSTS50
-#define RSCAN0TMSTS51 RSCAN0.TMSTS51
-#define RSCAN0TMSTS52 RSCAN0.TMSTS52
-#define RSCAN0TMSTS53 RSCAN0.TMSTS53
-#define RSCAN0TMSTS54 RSCAN0.TMSTS54
-#define RSCAN0TMSTS55 RSCAN0.TMSTS55
-#define RSCAN0TMSTS56 RSCAN0.TMSTS56
-#define RSCAN0TMSTS57 RSCAN0.TMSTS57
-#define RSCAN0TMSTS58 RSCAN0.TMSTS58
-#define RSCAN0TMSTS59 RSCAN0.TMSTS59
-#define RSCAN0TMSTS60 RSCAN0.TMSTS60
-#define RSCAN0TMSTS61 RSCAN0.TMSTS61
-#define RSCAN0TMSTS62 RSCAN0.TMSTS62
-#define RSCAN0TMSTS63 RSCAN0.TMSTS63
-#define RSCAN0TMSTS64 RSCAN0.TMSTS64
-#define RSCAN0TMSTS65 RSCAN0.TMSTS65
-#define RSCAN0TMSTS66 RSCAN0.TMSTS66
-#define RSCAN0TMSTS67 RSCAN0.TMSTS67
-#define RSCAN0TMSTS68 RSCAN0.TMSTS68
-#define RSCAN0TMSTS69 RSCAN0.TMSTS69
-#define RSCAN0TMSTS70 RSCAN0.TMSTS70
-#define RSCAN0TMSTS71 RSCAN0.TMSTS71
-#define RSCAN0TMSTS72 RSCAN0.TMSTS72
-#define RSCAN0TMSTS73 RSCAN0.TMSTS73
-#define RSCAN0TMSTS74 RSCAN0.TMSTS74
-#define RSCAN0TMSTS75 RSCAN0.TMSTS75
-#define RSCAN0TMSTS76 RSCAN0.TMSTS76
-#define RSCAN0TMSTS77 RSCAN0.TMSTS77
-#define RSCAN0TMSTS78 RSCAN0.TMSTS78
-#define RSCAN0TMSTS79 RSCAN0.TMSTS79
-#define RSCAN0TMTRSTS0 RSCAN0.TMTRSTS0.UINT32
-#define RSCAN0TMTRSTS0L RSCAN0.TMTRSTS0.UINT16[L]
-#define RSCAN0TMTRSTS0LL RSCAN0.TMTRSTS0.UINT8[LL]
-#define RSCAN0TMTRSTS0LH RSCAN0.TMTRSTS0.UINT8[LH]
-#define RSCAN0TMTRSTS0H RSCAN0.TMTRSTS0.UINT16[H]
-#define RSCAN0TMTRSTS0HL RSCAN0.TMTRSTS0.UINT8[HL]
-#define RSCAN0TMTRSTS0HH RSCAN0.TMTRSTS0.UINT8[HH]
-#define RSCAN0TMTRSTS1 RSCAN0.TMTRSTS1.UINT32
-#define RSCAN0TMTRSTS1L RSCAN0.TMTRSTS1.UINT16[L]
-#define RSCAN0TMTRSTS1LL RSCAN0.TMTRSTS1.UINT8[LL]
-#define RSCAN0TMTRSTS1LH RSCAN0.TMTRSTS1.UINT8[LH]
-#define RSCAN0TMTRSTS1H RSCAN0.TMTRSTS1.UINT16[H]
-#define RSCAN0TMTRSTS1HL RSCAN0.TMTRSTS1.UINT8[HL]
-#define RSCAN0TMTRSTS1HH RSCAN0.TMTRSTS1.UINT8[HH]
-#define RSCAN0TMTRSTS2 RSCAN0.TMTRSTS2.UINT32
-#define RSCAN0TMTRSTS2L RSCAN0.TMTRSTS2.UINT16[L]
-#define RSCAN0TMTRSTS2LL RSCAN0.TMTRSTS2.UINT8[LL]
-#define RSCAN0TMTRSTS2LH RSCAN0.TMTRSTS2.UINT8[LH]
-#define RSCAN0TMTRSTS2H RSCAN0.TMTRSTS2.UINT16[H]
-#define RSCAN0TMTRSTS2HL RSCAN0.TMTRSTS2.UINT8[HL]
-#define RSCAN0TMTRSTS2HH RSCAN0.TMTRSTS2.UINT8[HH]
-#define RSCAN0TMTARSTS0 RSCAN0.TMTARSTS0.UINT32
-#define RSCAN0TMTARSTS0L RSCAN0.TMTARSTS0.UINT16[L]
-#define RSCAN0TMTARSTS0LL RSCAN0.TMTARSTS0.UINT8[LL]
-#define RSCAN0TMTARSTS0LH RSCAN0.TMTARSTS0.UINT8[LH]
-#define RSCAN0TMTARSTS0H RSCAN0.TMTARSTS0.UINT16[H]
-#define RSCAN0TMTARSTS0HL RSCAN0.TMTARSTS0.UINT8[HL]
-#define RSCAN0TMTARSTS0HH RSCAN0.TMTARSTS0.UINT8[HH]
-#define RSCAN0TMTARSTS1 RSCAN0.TMTARSTS1.UINT32
-#define RSCAN0TMTARSTS1L RSCAN0.TMTARSTS1.UINT16[L]
-#define RSCAN0TMTARSTS1LL RSCAN0.TMTARSTS1.UINT8[LL]
-#define RSCAN0TMTARSTS1LH RSCAN0.TMTARSTS1.UINT8[LH]
-#define RSCAN0TMTARSTS1H RSCAN0.TMTARSTS1.UINT16[H]
-#define RSCAN0TMTARSTS1HL RSCAN0.TMTARSTS1.UINT8[HL]
-#define RSCAN0TMTARSTS1HH RSCAN0.TMTARSTS1.UINT8[HH]
-#define RSCAN0TMTARSTS2 RSCAN0.TMTARSTS2.UINT32
-#define RSCAN0TMTARSTS2L RSCAN0.TMTARSTS2.UINT16[L]
-#define RSCAN0TMTARSTS2LL RSCAN0.TMTARSTS2.UINT8[LL]
-#define RSCAN0TMTARSTS2LH RSCAN0.TMTARSTS2.UINT8[LH]
-#define RSCAN0TMTARSTS2H RSCAN0.TMTARSTS2.UINT16[H]
-#define RSCAN0TMTARSTS2HL RSCAN0.TMTARSTS2.UINT8[HL]
-#define RSCAN0TMTARSTS2HH RSCAN0.TMTARSTS2.UINT8[HH]
-#define RSCAN0TMTCSTS0 RSCAN0.TMTCSTS0.UINT32
-#define RSCAN0TMTCSTS0L RSCAN0.TMTCSTS0.UINT16[L]
-#define RSCAN0TMTCSTS0LL RSCAN0.TMTCSTS0.UINT8[LL]
-#define RSCAN0TMTCSTS0LH RSCAN0.TMTCSTS0.UINT8[LH]
-#define RSCAN0TMTCSTS0H RSCAN0.TMTCSTS0.UINT16[H]
-#define RSCAN0TMTCSTS0HL RSCAN0.TMTCSTS0.UINT8[HL]
-#define RSCAN0TMTCSTS0HH RSCAN0.TMTCSTS0.UINT8[HH]
-#define RSCAN0TMTCSTS1 RSCAN0.TMTCSTS1.UINT32
-#define RSCAN0TMTCSTS1L RSCAN0.TMTCSTS1.UINT16[L]
-#define RSCAN0TMTCSTS1LL RSCAN0.TMTCSTS1.UINT8[LL]
-#define RSCAN0TMTCSTS1LH RSCAN0.TMTCSTS1.UINT8[LH]
-#define RSCAN0TMTCSTS1H RSCAN0.TMTCSTS1.UINT16[H]
-#define RSCAN0TMTCSTS1HL RSCAN0.TMTCSTS1.UINT8[HL]
-#define RSCAN0TMTCSTS1HH RSCAN0.TMTCSTS1.UINT8[HH]
-#define RSCAN0TMTCSTS2 RSCAN0.TMTCSTS2.UINT32
-#define RSCAN0TMTCSTS2L RSCAN0.TMTCSTS2.UINT16[L]
-#define RSCAN0TMTCSTS2LL RSCAN0.TMTCSTS2.UINT8[LL]
-#define RSCAN0TMTCSTS2LH RSCAN0.TMTCSTS2.UINT8[LH]
-#define RSCAN0TMTCSTS2H RSCAN0.TMTCSTS2.UINT16[H]
-#define RSCAN0TMTCSTS2HL RSCAN0.TMTCSTS2.UINT8[HL]
-#define RSCAN0TMTCSTS2HH RSCAN0.TMTCSTS2.UINT8[HH]
-#define RSCAN0TMTASTS0 RSCAN0.TMTASTS0.UINT32
-#define RSCAN0TMTASTS0L RSCAN0.TMTASTS0.UINT16[L]
-#define RSCAN0TMTASTS0LL RSCAN0.TMTASTS0.UINT8[LL]
-#define RSCAN0TMTASTS0LH RSCAN0.TMTASTS0.UINT8[LH]
-#define RSCAN0TMTASTS0H RSCAN0.TMTASTS0.UINT16[H]
-#define RSCAN0TMTASTS0HL RSCAN0.TMTASTS0.UINT8[HL]
-#define RSCAN0TMTASTS0HH RSCAN0.TMTASTS0.UINT8[HH]
-#define RSCAN0TMTASTS1 RSCAN0.TMTASTS1.UINT32
-#define RSCAN0TMTASTS1L RSCAN0.TMTASTS1.UINT16[L]
-#define RSCAN0TMTASTS1LL RSCAN0.TMTASTS1.UINT8[LL]
-#define RSCAN0TMTASTS1LH RSCAN0.TMTASTS1.UINT8[LH]
-#define RSCAN0TMTASTS1H RSCAN0.TMTASTS1.UINT16[H]
-#define RSCAN0TMTASTS1HL RSCAN0.TMTASTS1.UINT8[HL]
-#define RSCAN0TMTASTS1HH RSCAN0.TMTASTS1.UINT8[HH]
-#define RSCAN0TMTASTS2 RSCAN0.TMTASTS2.UINT32
-#define RSCAN0TMTASTS2L RSCAN0.TMTASTS2.UINT16[L]
-#define RSCAN0TMTASTS2LL RSCAN0.TMTASTS2.UINT8[LL]
-#define RSCAN0TMTASTS2LH RSCAN0.TMTASTS2.UINT8[LH]
-#define RSCAN0TMTASTS2H RSCAN0.TMTASTS2.UINT16[H]
-#define RSCAN0TMTASTS2HL RSCAN0.TMTASTS2.UINT8[HL]
-#define RSCAN0TMTASTS2HH RSCAN0.TMTASTS2.UINT8[HH]
-#define RSCAN0TMIEC0 RSCAN0.TMIEC0.UINT32
-#define RSCAN0TMIEC0L RSCAN0.TMIEC0.UINT16[L]
-#define RSCAN0TMIEC0LL RSCAN0.TMIEC0.UINT8[LL]
-#define RSCAN0TMIEC0LH RSCAN0.TMIEC0.UINT8[LH]
-#define RSCAN0TMIEC0H RSCAN0.TMIEC0.UINT16[H]
-#define RSCAN0TMIEC0HL RSCAN0.TMIEC0.UINT8[HL]
-#define RSCAN0TMIEC0HH RSCAN0.TMIEC0.UINT8[HH]
-#define RSCAN0TMIEC1 RSCAN0.TMIEC1.UINT32
-#define RSCAN0TMIEC1L RSCAN0.TMIEC1.UINT16[L]
-#define RSCAN0TMIEC1LL RSCAN0.TMIEC1.UINT8[LL]
-#define RSCAN0TMIEC1LH RSCAN0.TMIEC1.UINT8[LH]
-#define RSCAN0TMIEC1H RSCAN0.TMIEC1.UINT16[H]
-#define RSCAN0TMIEC1HL RSCAN0.TMIEC1.UINT8[HL]
-#define RSCAN0TMIEC1HH RSCAN0.TMIEC1.UINT8[HH]
-#define RSCAN0TMIEC2 RSCAN0.TMIEC2.UINT32
-#define RSCAN0TMIEC2L RSCAN0.TMIEC2.UINT16[L]
-#define RSCAN0TMIEC2LL RSCAN0.TMIEC2.UINT8[LL]
-#define RSCAN0TMIEC2LH RSCAN0.TMIEC2.UINT8[LH]
-#define RSCAN0TMIEC2H RSCAN0.TMIEC2.UINT16[H]
-#define RSCAN0TMIEC2HL RSCAN0.TMIEC2.UINT8[HL]
-#define RSCAN0TMIEC2HH RSCAN0.TMIEC2.UINT8[HH]
-#define RSCAN0TXQCC0 RSCAN0.TXQCC0.UINT32
-#define RSCAN0TXQCC0L RSCAN0.TXQCC0.UINT16[L]
-#define RSCAN0TXQCC0LL RSCAN0.TXQCC0.UINT8[LL]
-#define RSCAN0TXQCC0LH RSCAN0.TXQCC0.UINT8[LH]
-#define RSCAN0TXQCC0H RSCAN0.TXQCC0.UINT16[H]
-#define RSCAN0TXQCC0HL RSCAN0.TXQCC0.UINT8[HL]
-#define RSCAN0TXQCC0HH RSCAN0.TXQCC0.UINT8[HH]
-#define RSCAN0TXQCC1 RSCAN0.TXQCC1.UINT32
-#define RSCAN0TXQCC1L RSCAN0.TXQCC1.UINT16[L]
-#define RSCAN0TXQCC1LL RSCAN0.TXQCC1.UINT8[LL]
-#define RSCAN0TXQCC1LH RSCAN0.TXQCC1.UINT8[LH]
-#define RSCAN0TXQCC1H RSCAN0.TXQCC1.UINT16[H]
-#define RSCAN0TXQCC1HL RSCAN0.TXQCC1.UINT8[HL]
-#define RSCAN0TXQCC1HH RSCAN0.TXQCC1.UINT8[HH]
-#define RSCAN0TXQCC2 RSCAN0.TXQCC2.UINT32
-#define RSCAN0TXQCC2L RSCAN0.TXQCC2.UINT16[L]
-#define RSCAN0TXQCC2LL RSCAN0.TXQCC2.UINT8[LL]
-#define RSCAN0TXQCC2LH RSCAN0.TXQCC2.UINT8[LH]
-#define RSCAN0TXQCC2H RSCAN0.TXQCC2.UINT16[H]
-#define RSCAN0TXQCC2HL RSCAN0.TXQCC2.UINT8[HL]
-#define RSCAN0TXQCC2HH RSCAN0.TXQCC2.UINT8[HH]
-#define RSCAN0TXQCC3 RSCAN0.TXQCC3.UINT32
-#define RSCAN0TXQCC3L RSCAN0.TXQCC3.UINT16[L]
-#define RSCAN0TXQCC3LL RSCAN0.TXQCC3.UINT8[LL]
-#define RSCAN0TXQCC3LH RSCAN0.TXQCC3.UINT8[LH]
-#define RSCAN0TXQCC3H RSCAN0.TXQCC3.UINT16[H]
-#define RSCAN0TXQCC3HL RSCAN0.TXQCC3.UINT8[HL]
-#define RSCAN0TXQCC3HH RSCAN0.TXQCC3.UINT8[HH]
-#define RSCAN0TXQCC4 RSCAN0.TXQCC4.UINT32
-#define RSCAN0TXQCC4L RSCAN0.TXQCC4.UINT16[L]
-#define RSCAN0TXQCC4LL RSCAN0.TXQCC4.UINT8[LL]
-#define RSCAN0TXQCC4LH RSCAN0.TXQCC4.UINT8[LH]
-#define RSCAN0TXQCC4H RSCAN0.TXQCC4.UINT16[H]
-#define RSCAN0TXQCC4HL RSCAN0.TXQCC4.UINT8[HL]
-#define RSCAN0TXQCC4HH RSCAN0.TXQCC4.UINT8[HH]
-#define RSCAN0TXQSTS0 RSCAN0.TXQSTS0.UINT32
-#define RSCAN0TXQSTS0L RSCAN0.TXQSTS0.UINT16[L]
-#define RSCAN0TXQSTS0LL RSCAN0.TXQSTS0.UINT8[LL]
-#define RSCAN0TXQSTS0LH RSCAN0.TXQSTS0.UINT8[LH]
-#define RSCAN0TXQSTS0H RSCAN0.TXQSTS0.UINT16[H]
-#define RSCAN0TXQSTS0HL RSCAN0.TXQSTS0.UINT8[HL]
-#define RSCAN0TXQSTS0HH RSCAN0.TXQSTS0.UINT8[HH]
-#define RSCAN0TXQSTS1 RSCAN0.TXQSTS1.UINT32
-#define RSCAN0TXQSTS1L RSCAN0.TXQSTS1.UINT16[L]
-#define RSCAN0TXQSTS1LL RSCAN0.TXQSTS1.UINT8[LL]
-#define RSCAN0TXQSTS1LH RSCAN0.TXQSTS1.UINT8[LH]
-#define RSCAN0TXQSTS1H RSCAN0.TXQSTS1.UINT16[H]
-#define RSCAN0TXQSTS1HL RSCAN0.TXQSTS1.UINT8[HL]
-#define RSCAN0TXQSTS1HH RSCAN0.TXQSTS1.UINT8[HH]
-#define RSCAN0TXQSTS2 RSCAN0.TXQSTS2.UINT32
-#define RSCAN0TXQSTS2L RSCAN0.TXQSTS2.UINT16[L]
-#define RSCAN0TXQSTS2LL RSCAN0.TXQSTS2.UINT8[LL]
-#define RSCAN0TXQSTS2LH RSCAN0.TXQSTS2.UINT8[LH]
-#define RSCAN0TXQSTS2H RSCAN0.TXQSTS2.UINT16[H]
-#define RSCAN0TXQSTS2HL RSCAN0.TXQSTS2.UINT8[HL]
-#define RSCAN0TXQSTS2HH RSCAN0.TXQSTS2.UINT8[HH]
-#define RSCAN0TXQSTS3 RSCAN0.TXQSTS3.UINT32
-#define RSCAN0TXQSTS3L RSCAN0.TXQSTS3.UINT16[L]
-#define RSCAN0TXQSTS3LL RSCAN0.TXQSTS3.UINT8[LL]
-#define RSCAN0TXQSTS3LH RSCAN0.TXQSTS3.UINT8[LH]
-#define RSCAN0TXQSTS3H RSCAN0.TXQSTS3.UINT16[H]
-#define RSCAN0TXQSTS3HL RSCAN0.TXQSTS3.UINT8[HL]
-#define RSCAN0TXQSTS3HH RSCAN0.TXQSTS3.UINT8[HH]
-#define RSCAN0TXQSTS4 RSCAN0.TXQSTS4.UINT32
-#define RSCAN0TXQSTS4L RSCAN0.TXQSTS4.UINT16[L]
-#define RSCAN0TXQSTS4LL RSCAN0.TXQSTS4.UINT8[LL]
-#define RSCAN0TXQSTS4LH RSCAN0.TXQSTS4.UINT8[LH]
-#define RSCAN0TXQSTS4H RSCAN0.TXQSTS4.UINT16[H]
-#define RSCAN0TXQSTS4HL RSCAN0.TXQSTS4.UINT8[HL]
-#define RSCAN0TXQSTS4HH RSCAN0.TXQSTS4.UINT8[HH]
-#define RSCAN0TXQPCTR0 RSCAN0.TXQPCTR0.UINT32
-#define RSCAN0TXQPCTR0L RSCAN0.TXQPCTR0.UINT16[L]
-#define RSCAN0TXQPCTR0LL RSCAN0.TXQPCTR0.UINT8[LL]
-#define RSCAN0TXQPCTR0LH RSCAN0.TXQPCTR0.UINT8[LH]
-#define RSCAN0TXQPCTR0H RSCAN0.TXQPCTR0.UINT16[H]
-#define RSCAN0TXQPCTR0HL RSCAN0.TXQPCTR0.UINT8[HL]
-#define RSCAN0TXQPCTR0HH RSCAN0.TXQPCTR0.UINT8[HH]
-#define RSCAN0TXQPCTR1 RSCAN0.TXQPCTR1.UINT32
-#define RSCAN0TXQPCTR1L RSCAN0.TXQPCTR1.UINT16[L]
-#define RSCAN0TXQPCTR1LL RSCAN0.TXQPCTR1.UINT8[LL]
-#define RSCAN0TXQPCTR1LH RSCAN0.TXQPCTR1.UINT8[LH]
-#define RSCAN0TXQPCTR1H RSCAN0.TXQPCTR1.UINT16[H]
-#define RSCAN0TXQPCTR1HL RSCAN0.TXQPCTR1.UINT8[HL]
-#define RSCAN0TXQPCTR1HH RSCAN0.TXQPCTR1.UINT8[HH]
-#define RSCAN0TXQPCTR2 RSCAN0.TXQPCTR2.UINT32
-#define RSCAN0TXQPCTR2L RSCAN0.TXQPCTR2.UINT16[L]
-#define RSCAN0TXQPCTR2LL RSCAN0.TXQPCTR2.UINT8[LL]
-#define RSCAN0TXQPCTR2LH RSCAN0.TXQPCTR2.UINT8[LH]
-#define RSCAN0TXQPCTR2H RSCAN0.TXQPCTR2.UINT16[H]
-#define RSCAN0TXQPCTR2HL RSCAN0.TXQPCTR2.UINT8[HL]
-#define RSCAN0TXQPCTR2HH RSCAN0.TXQPCTR2.UINT8[HH]
-#define RSCAN0TXQPCTR3 RSCAN0.TXQPCTR3.UINT32
-#define RSCAN0TXQPCTR3L RSCAN0.TXQPCTR3.UINT16[L]
-#define RSCAN0TXQPCTR3LL RSCAN0.TXQPCTR3.UINT8[LL]
-#define RSCAN0TXQPCTR3LH RSCAN0.TXQPCTR3.UINT8[LH]
-#define RSCAN0TXQPCTR3H RSCAN0.TXQPCTR3.UINT16[H]
-#define RSCAN0TXQPCTR3HL RSCAN0.TXQPCTR3.UINT8[HL]
-#define RSCAN0TXQPCTR3HH RSCAN0.TXQPCTR3.UINT8[HH]
-#define RSCAN0TXQPCTR4 RSCAN0.TXQPCTR4.UINT32
-#define RSCAN0TXQPCTR4L RSCAN0.TXQPCTR4.UINT16[L]
-#define RSCAN0TXQPCTR4LL RSCAN0.TXQPCTR4.UINT8[LL]
-#define RSCAN0TXQPCTR4LH RSCAN0.TXQPCTR4.UINT8[LH]
-#define RSCAN0TXQPCTR4H RSCAN0.TXQPCTR4.UINT16[H]
-#define RSCAN0TXQPCTR4HL RSCAN0.TXQPCTR4.UINT8[HL]
-#define RSCAN0TXQPCTR4HH RSCAN0.TXQPCTR4.UINT8[HH]
-#define RSCAN0THLCC0 RSCAN0.THLCC0.UINT32
-#define RSCAN0THLCC0L RSCAN0.THLCC0.UINT16[L]
-#define RSCAN0THLCC0LL RSCAN0.THLCC0.UINT8[LL]
-#define RSCAN0THLCC0LH RSCAN0.THLCC0.UINT8[LH]
-#define RSCAN0THLCC0H RSCAN0.THLCC0.UINT16[H]
-#define RSCAN0THLCC0HL RSCAN0.THLCC0.UINT8[HL]
-#define RSCAN0THLCC0HH RSCAN0.THLCC0.UINT8[HH]
-#define RSCAN0THLCC1 RSCAN0.THLCC1.UINT32
-#define RSCAN0THLCC1L RSCAN0.THLCC1.UINT16[L]
-#define RSCAN0THLCC1LL RSCAN0.THLCC1.UINT8[LL]
-#define RSCAN0THLCC1LH RSCAN0.THLCC1.UINT8[LH]
-#define RSCAN0THLCC1H RSCAN0.THLCC1.UINT16[H]
-#define RSCAN0THLCC1HL RSCAN0.THLCC1.UINT8[HL]
-#define RSCAN0THLCC1HH RSCAN0.THLCC1.UINT8[HH]
-#define RSCAN0THLCC2 RSCAN0.THLCC2.UINT32
-#define RSCAN0THLCC2L RSCAN0.THLCC2.UINT16[L]
-#define RSCAN0THLCC2LL RSCAN0.THLCC2.UINT8[LL]
-#define RSCAN0THLCC2LH RSCAN0.THLCC2.UINT8[LH]
-#define RSCAN0THLCC2H RSCAN0.THLCC2.UINT16[H]
-#define RSCAN0THLCC2HL RSCAN0.THLCC2.UINT8[HL]
-#define RSCAN0THLCC2HH RSCAN0.THLCC2.UINT8[HH]
-#define RSCAN0THLCC3 RSCAN0.THLCC3.UINT32
-#define RSCAN0THLCC3L RSCAN0.THLCC3.UINT16[L]
-#define RSCAN0THLCC3LL RSCAN0.THLCC3.UINT8[LL]
-#define RSCAN0THLCC3LH RSCAN0.THLCC3.UINT8[LH]
-#define RSCAN0THLCC3H RSCAN0.THLCC3.UINT16[H]
-#define RSCAN0THLCC3HL RSCAN0.THLCC3.UINT8[HL]
-#define RSCAN0THLCC3HH RSCAN0.THLCC3.UINT8[HH]
-#define RSCAN0THLCC4 RSCAN0.THLCC4.UINT32
-#define RSCAN0THLCC4L RSCAN0.THLCC4.UINT16[L]
-#define RSCAN0THLCC4LL RSCAN0.THLCC4.UINT8[LL]
-#define RSCAN0THLCC4LH RSCAN0.THLCC4.UINT8[LH]
-#define RSCAN0THLCC4H RSCAN0.THLCC4.UINT16[H]
-#define RSCAN0THLCC4HL RSCAN0.THLCC4.UINT8[HL]
-#define RSCAN0THLCC4HH RSCAN0.THLCC4.UINT8[HH]
-#define RSCAN0THLSTS0 RSCAN0.THLSTS0.UINT32
-#define RSCAN0THLSTS0L RSCAN0.THLSTS0.UINT16[L]
-#define RSCAN0THLSTS0LL RSCAN0.THLSTS0.UINT8[LL]
-#define RSCAN0THLSTS0LH RSCAN0.THLSTS0.UINT8[LH]
-#define RSCAN0THLSTS0H RSCAN0.THLSTS0.UINT16[H]
-#define RSCAN0THLSTS0HL RSCAN0.THLSTS0.UINT8[HL]
-#define RSCAN0THLSTS0HH RSCAN0.THLSTS0.UINT8[HH]
-#define RSCAN0THLSTS1 RSCAN0.THLSTS1.UINT32
-#define RSCAN0THLSTS1L RSCAN0.THLSTS1.UINT16[L]
-#define RSCAN0THLSTS1LL RSCAN0.THLSTS1.UINT8[LL]
-#define RSCAN0THLSTS1LH RSCAN0.THLSTS1.UINT8[LH]
-#define RSCAN0THLSTS1H RSCAN0.THLSTS1.UINT16[H]
-#define RSCAN0THLSTS1HL RSCAN0.THLSTS1.UINT8[HL]
-#define RSCAN0THLSTS1HH RSCAN0.THLSTS1.UINT8[HH]
-#define RSCAN0THLSTS2 RSCAN0.THLSTS2.UINT32
-#define RSCAN0THLSTS2L RSCAN0.THLSTS2.UINT16[L]
-#define RSCAN0THLSTS2LL RSCAN0.THLSTS2.UINT8[LL]
-#define RSCAN0THLSTS2LH RSCAN0.THLSTS2.UINT8[LH]
-#define RSCAN0THLSTS2H RSCAN0.THLSTS2.UINT16[H]
-#define RSCAN0THLSTS2HL RSCAN0.THLSTS2.UINT8[HL]
-#define RSCAN0THLSTS2HH RSCAN0.THLSTS2.UINT8[HH]
-#define RSCAN0THLSTS3 RSCAN0.THLSTS3.UINT32
-#define RSCAN0THLSTS3L RSCAN0.THLSTS3.UINT16[L]
-#define RSCAN0THLSTS3LL RSCAN0.THLSTS3.UINT8[LL]
-#define RSCAN0THLSTS3LH RSCAN0.THLSTS3.UINT8[LH]
-#define RSCAN0THLSTS3H RSCAN0.THLSTS3.UINT16[H]
-#define RSCAN0THLSTS3HL RSCAN0.THLSTS3.UINT8[HL]
-#define RSCAN0THLSTS3HH RSCAN0.THLSTS3.UINT8[HH]
-#define RSCAN0THLSTS4 RSCAN0.THLSTS4.UINT32
-#define RSCAN0THLSTS4L RSCAN0.THLSTS4.UINT16[L]
-#define RSCAN0THLSTS4LL RSCAN0.THLSTS4.UINT8[LL]
-#define RSCAN0THLSTS4LH RSCAN0.THLSTS4.UINT8[LH]
-#define RSCAN0THLSTS4H RSCAN0.THLSTS4.UINT16[H]
-#define RSCAN0THLSTS4HL RSCAN0.THLSTS4.UINT8[HL]
-#define RSCAN0THLSTS4HH RSCAN0.THLSTS4.UINT8[HH]
-#define RSCAN0THLPCTR0 RSCAN0.THLPCTR0.UINT32
-#define RSCAN0THLPCTR0L RSCAN0.THLPCTR0.UINT16[L]
-#define RSCAN0THLPCTR0LL RSCAN0.THLPCTR0.UINT8[LL]
-#define RSCAN0THLPCTR0LH RSCAN0.THLPCTR0.UINT8[LH]
-#define RSCAN0THLPCTR0H RSCAN0.THLPCTR0.UINT16[H]
-#define RSCAN0THLPCTR0HL RSCAN0.THLPCTR0.UINT8[HL]
-#define RSCAN0THLPCTR0HH RSCAN0.THLPCTR0.UINT8[HH]
-#define RSCAN0THLPCTR1 RSCAN0.THLPCTR1.UINT32
-#define RSCAN0THLPCTR1L RSCAN0.THLPCTR1.UINT16[L]
-#define RSCAN0THLPCTR1LL RSCAN0.THLPCTR1.UINT8[LL]
-#define RSCAN0THLPCTR1LH RSCAN0.THLPCTR1.UINT8[LH]
-#define RSCAN0THLPCTR1H RSCAN0.THLPCTR1.UINT16[H]
-#define RSCAN0THLPCTR1HL RSCAN0.THLPCTR1.UINT8[HL]
-#define RSCAN0THLPCTR1HH RSCAN0.THLPCTR1.UINT8[HH]
-#define RSCAN0THLPCTR2 RSCAN0.THLPCTR2.UINT32
-#define RSCAN0THLPCTR2L RSCAN0.THLPCTR2.UINT16[L]
-#define RSCAN0THLPCTR2LL RSCAN0.THLPCTR2.UINT8[LL]
-#define RSCAN0THLPCTR2LH RSCAN0.THLPCTR2.UINT8[LH]
-#define RSCAN0THLPCTR2H RSCAN0.THLPCTR2.UINT16[H]
-#define RSCAN0THLPCTR2HL RSCAN0.THLPCTR2.UINT8[HL]
-#define RSCAN0THLPCTR2HH RSCAN0.THLPCTR2.UINT8[HH]
-#define RSCAN0THLPCTR3 RSCAN0.THLPCTR3.UINT32
-#define RSCAN0THLPCTR3L RSCAN0.THLPCTR3.UINT16[L]
-#define RSCAN0THLPCTR3LL RSCAN0.THLPCTR3.UINT8[LL]
-#define RSCAN0THLPCTR3LH RSCAN0.THLPCTR3.UINT8[LH]
-#define RSCAN0THLPCTR3H RSCAN0.THLPCTR3.UINT16[H]
-#define RSCAN0THLPCTR3HL RSCAN0.THLPCTR3.UINT8[HL]
-#define RSCAN0THLPCTR3HH RSCAN0.THLPCTR3.UINT8[HH]
-#define RSCAN0THLPCTR4 RSCAN0.THLPCTR4.UINT32
-#define RSCAN0THLPCTR4L RSCAN0.THLPCTR4.UINT16[L]
-#define RSCAN0THLPCTR4LL RSCAN0.THLPCTR4.UINT8[LL]
-#define RSCAN0THLPCTR4LH RSCAN0.THLPCTR4.UINT8[LH]
-#define RSCAN0THLPCTR4H RSCAN0.THLPCTR4.UINT16[H]
-#define RSCAN0THLPCTR4HL RSCAN0.THLPCTR4.UINT8[HL]
-#define RSCAN0THLPCTR4HH RSCAN0.THLPCTR4.UINT8[HH]
-#define RSCAN0GTINTSTS0 RSCAN0.GTINTSTS0.UINT32
-#define RSCAN0GTINTSTS0L RSCAN0.GTINTSTS0.UINT16[L]
-#define RSCAN0GTINTSTS0LL RSCAN0.GTINTSTS0.UINT8[LL]
-#define RSCAN0GTINTSTS0LH RSCAN0.GTINTSTS0.UINT8[LH]
-#define RSCAN0GTINTSTS0H RSCAN0.GTINTSTS0.UINT16[H]
-#define RSCAN0GTINTSTS0HL RSCAN0.GTINTSTS0.UINT8[HL]
-#define RSCAN0GTINTSTS0HH RSCAN0.GTINTSTS0.UINT8[HH]
-#define RSCAN0GTINTSTS1 RSCAN0.GTINTSTS1.UINT32
-#define RSCAN0GTINTSTS1L RSCAN0.GTINTSTS1.UINT16[L]
-#define RSCAN0GTINTSTS1LL RSCAN0.GTINTSTS1.UINT8[LL]
-#define RSCAN0GTINTSTS1LH RSCAN0.GTINTSTS1.UINT8[LH]
-#define RSCAN0GTINTSTS1H RSCAN0.GTINTSTS1.UINT16[H]
-#define RSCAN0GTINTSTS1HL RSCAN0.GTINTSTS1.UINT8[HL]
-#define RSCAN0GTINTSTS1HH RSCAN0.GTINTSTS1.UINT8[HH]
-#define RSCAN0GTSTCFG RSCAN0.GTSTCFG.UINT32
-#define RSCAN0GTSTCFGL RSCAN0.GTSTCFG.UINT16[L]
-#define RSCAN0GTSTCFGLL RSCAN0.GTSTCFG.UINT8[LL]
-#define RSCAN0GTSTCFGLH RSCAN0.GTSTCFG.UINT8[LH]
-#define RSCAN0GTSTCFGH RSCAN0.GTSTCFG.UINT16[H]
-#define RSCAN0GTSTCFGHL RSCAN0.GTSTCFG.UINT8[HL]
-#define RSCAN0GTSTCFGHH RSCAN0.GTSTCFG.UINT8[HH]
-#define RSCAN0GTSTCTR RSCAN0.GTSTCTR.UINT32
-#define RSCAN0GTSTCTRL RSCAN0.GTSTCTR.UINT16[L]
-#define RSCAN0GTSTCTRLL RSCAN0.GTSTCTR.UINT8[LL]
-#define RSCAN0GTSTCTRLH RSCAN0.GTSTCTR.UINT8[LH]
-#define RSCAN0GTSTCTRH RSCAN0.GTSTCTR.UINT16[H]
-#define RSCAN0GTSTCTRHL RSCAN0.GTSTCTR.UINT8[HL]
-#define RSCAN0GTSTCTRHH RSCAN0.GTSTCTR.UINT8[HH]
-#define RSCAN0GLOCKK RSCAN0.GLOCKK.UINT32
-#define RSCAN0GLOCKKL RSCAN0.GLOCKK.UINT16[L]
-#define RSCAN0GLOCKKH RSCAN0.GLOCKK.UINT16[H]
-#define RSCAN0GAFLID0 RSCAN0.GAFLID0.UINT32
-#define RSCAN0GAFLID0L RSCAN0.GAFLID0.UINT16[L]
-#define RSCAN0GAFLID0LL RSCAN0.GAFLID0.UINT8[LL]
-#define RSCAN0GAFLID0LH RSCAN0.GAFLID0.UINT8[LH]
-#define RSCAN0GAFLID0H RSCAN0.GAFLID0.UINT16[H]
-#define RSCAN0GAFLID0HL RSCAN0.GAFLID0.UINT8[HL]
-#define RSCAN0GAFLID0HH RSCAN0.GAFLID0.UINT8[HH]
-#define RSCAN0GAFLM0 RSCAN0.GAFLM0.UINT32
-#define RSCAN0GAFLM0L RSCAN0.GAFLM0.UINT16[L]
-#define RSCAN0GAFLM0LL RSCAN0.GAFLM0.UINT8[LL]
-#define RSCAN0GAFLM0LH RSCAN0.GAFLM0.UINT8[LH]
-#define RSCAN0GAFLM0H RSCAN0.GAFLM0.UINT16[H]
-#define RSCAN0GAFLM0HL RSCAN0.GAFLM0.UINT8[HL]
-#define RSCAN0GAFLM0HH RSCAN0.GAFLM0.UINT8[HH]
-#define RSCAN0GAFLP00 RSCAN0.GAFLP00.UINT32
-#define RSCAN0GAFLP00L RSCAN0.GAFLP00.UINT16[L]
-#define RSCAN0GAFLP00LL RSCAN0.GAFLP00.UINT8[LL]
-#define RSCAN0GAFLP00LH RSCAN0.GAFLP00.UINT8[LH]
-#define RSCAN0GAFLP00H RSCAN0.GAFLP00.UINT16[H]
-#define RSCAN0GAFLP00HL RSCAN0.GAFLP00.UINT8[HL]
-#define RSCAN0GAFLP00HH RSCAN0.GAFLP00.UINT8[HH]
-#define RSCAN0GAFLP10 RSCAN0.GAFLP10.UINT32
-#define RSCAN0GAFLP10L RSCAN0.GAFLP10.UINT16[L]
-#define RSCAN0GAFLP10LL RSCAN0.GAFLP10.UINT8[LL]
-#define RSCAN0GAFLP10LH RSCAN0.GAFLP10.UINT8[LH]
-#define RSCAN0GAFLP10H RSCAN0.GAFLP10.UINT16[H]
-#define RSCAN0GAFLP10HL RSCAN0.GAFLP10.UINT8[HL]
-#define RSCAN0GAFLP10HH RSCAN0.GAFLP10.UINT8[HH]
-#define RSCAN0GAFLID1 RSCAN0.GAFLID1.UINT32
-#define RSCAN0GAFLID1L RSCAN0.GAFLID1.UINT16[L]
-#define RSCAN0GAFLID1LL RSCAN0.GAFLID1.UINT8[LL]
-#define RSCAN0GAFLID1LH RSCAN0.GAFLID1.UINT8[LH]
-#define RSCAN0GAFLID1H RSCAN0.GAFLID1.UINT16[H]
-#define RSCAN0GAFLID1HL RSCAN0.GAFLID1.UINT8[HL]
-#define RSCAN0GAFLID1HH RSCAN0.GAFLID1.UINT8[HH]
-#define RSCAN0GAFLM1 RSCAN0.GAFLM1.UINT32
-#define RSCAN0GAFLM1L RSCAN0.GAFLM1.UINT16[L]
-#define RSCAN0GAFLM1LL RSCAN0.GAFLM1.UINT8[LL]
-#define RSCAN0GAFLM1LH RSCAN0.GAFLM1.UINT8[LH]
-#define RSCAN0GAFLM1H RSCAN0.GAFLM1.UINT16[H]
-#define RSCAN0GAFLM1HL RSCAN0.GAFLM1.UINT8[HL]
-#define RSCAN0GAFLM1HH RSCAN0.GAFLM1.UINT8[HH]
-#define RSCAN0GAFLP01 RSCAN0.GAFLP01.UINT32
-#define RSCAN0GAFLP01L RSCAN0.GAFLP01.UINT16[L]
-#define RSCAN0GAFLP01LL RSCAN0.GAFLP01.UINT8[LL]
-#define RSCAN0GAFLP01LH RSCAN0.GAFLP01.UINT8[LH]
-#define RSCAN0GAFLP01H RSCAN0.GAFLP01.UINT16[H]
-#define RSCAN0GAFLP01HL RSCAN0.GAFLP01.UINT8[HL]
-#define RSCAN0GAFLP01HH RSCAN0.GAFLP01.UINT8[HH]
-#define RSCAN0GAFLP11 RSCAN0.GAFLP11.UINT32
-#define RSCAN0GAFLP11L RSCAN0.GAFLP11.UINT16[L]
-#define RSCAN0GAFLP11LL RSCAN0.GAFLP11.UINT8[LL]
-#define RSCAN0GAFLP11LH RSCAN0.GAFLP11.UINT8[LH]
-#define RSCAN0GAFLP11H RSCAN0.GAFLP11.UINT16[H]
-#define RSCAN0GAFLP11HL RSCAN0.GAFLP11.UINT8[HL]
-#define RSCAN0GAFLP11HH RSCAN0.GAFLP11.UINT8[HH]
-#define RSCAN0GAFLID2 RSCAN0.GAFLID2.UINT32
-#define RSCAN0GAFLID2L RSCAN0.GAFLID2.UINT16[L]
-#define RSCAN0GAFLID2LL RSCAN0.GAFLID2.UINT8[LL]
-#define RSCAN0GAFLID2LH RSCAN0.GAFLID2.UINT8[LH]
-#define RSCAN0GAFLID2H RSCAN0.GAFLID2.UINT16[H]
-#define RSCAN0GAFLID2HL RSCAN0.GAFLID2.UINT8[HL]
-#define RSCAN0GAFLID2HH RSCAN0.GAFLID2.UINT8[HH]
-#define RSCAN0GAFLM2 RSCAN0.GAFLM2.UINT32
-#define RSCAN0GAFLM2L RSCAN0.GAFLM2.UINT16[L]
-#define RSCAN0GAFLM2LL RSCAN0.GAFLM2.UINT8[LL]
-#define RSCAN0GAFLM2LH RSCAN0.GAFLM2.UINT8[LH]
-#define RSCAN0GAFLM2H RSCAN0.GAFLM2.UINT16[H]
-#define RSCAN0GAFLM2HL RSCAN0.GAFLM2.UINT8[HL]
-#define RSCAN0GAFLM2HH RSCAN0.GAFLM2.UINT8[HH]
-#define RSCAN0GAFLP02 RSCAN0.GAFLP02.UINT32
-#define RSCAN0GAFLP02L RSCAN0.GAFLP02.UINT16[L]
-#define RSCAN0GAFLP02LL RSCAN0.GAFLP02.UINT8[LL]
-#define RSCAN0GAFLP02LH RSCAN0.GAFLP02.UINT8[LH]
-#define RSCAN0GAFLP02H RSCAN0.GAFLP02.UINT16[H]
-#define RSCAN0GAFLP02HL RSCAN0.GAFLP02.UINT8[HL]
-#define RSCAN0GAFLP02HH RSCAN0.GAFLP02.UINT8[HH]
-#define RSCAN0GAFLP12 RSCAN0.GAFLP12.UINT32
-#define RSCAN0GAFLP12L RSCAN0.GAFLP12.UINT16[L]
-#define RSCAN0GAFLP12LL RSCAN0.GAFLP12.UINT8[LL]
-#define RSCAN0GAFLP12LH RSCAN0.GAFLP12.UINT8[LH]
-#define RSCAN0GAFLP12H RSCAN0.GAFLP12.UINT16[H]
-#define RSCAN0GAFLP12HL RSCAN0.GAFLP12.UINT8[HL]
-#define RSCAN0GAFLP12HH RSCAN0.GAFLP12.UINT8[HH]
-#define RSCAN0GAFLID3 RSCAN0.GAFLID3.UINT32
-#define RSCAN0GAFLID3L RSCAN0.GAFLID3.UINT16[L]
-#define RSCAN0GAFLID3LL RSCAN0.GAFLID3.UINT8[LL]
-#define RSCAN0GAFLID3LH RSCAN0.GAFLID3.UINT8[LH]
-#define RSCAN0GAFLID3H RSCAN0.GAFLID3.UINT16[H]
-#define RSCAN0GAFLID3HL RSCAN0.GAFLID3.UINT8[HL]
-#define RSCAN0GAFLID3HH RSCAN0.GAFLID3.UINT8[HH]
-#define RSCAN0GAFLM3 RSCAN0.GAFLM3.UINT32
-#define RSCAN0GAFLM3L RSCAN0.GAFLM3.UINT16[L]
-#define RSCAN0GAFLM3LL RSCAN0.GAFLM3.UINT8[LL]
-#define RSCAN0GAFLM3LH RSCAN0.GAFLM3.UINT8[LH]
-#define RSCAN0GAFLM3H RSCAN0.GAFLM3.UINT16[H]
-#define RSCAN0GAFLM3HL RSCAN0.GAFLM3.UINT8[HL]
-#define RSCAN0GAFLM3HH RSCAN0.GAFLM3.UINT8[HH]
-#define RSCAN0GAFLP03 RSCAN0.GAFLP03.UINT32
-#define RSCAN0GAFLP03L RSCAN0.GAFLP03.UINT16[L]
-#define RSCAN0GAFLP03LL RSCAN0.GAFLP03.UINT8[LL]
-#define RSCAN0GAFLP03LH RSCAN0.GAFLP03.UINT8[LH]
-#define RSCAN0GAFLP03H RSCAN0.GAFLP03.UINT16[H]
-#define RSCAN0GAFLP03HL RSCAN0.GAFLP03.UINT8[HL]
-#define RSCAN0GAFLP03HH RSCAN0.GAFLP03.UINT8[HH]
-#define RSCAN0GAFLP13 RSCAN0.GAFLP13.UINT32
-#define RSCAN0GAFLP13L RSCAN0.GAFLP13.UINT16[L]
-#define RSCAN0GAFLP13LL RSCAN0.GAFLP13.UINT8[LL]
-#define RSCAN0GAFLP13LH RSCAN0.GAFLP13.UINT8[LH]
-#define RSCAN0GAFLP13H RSCAN0.GAFLP13.UINT16[H]
-#define RSCAN0GAFLP13HL RSCAN0.GAFLP13.UINT8[HL]
-#define RSCAN0GAFLP13HH RSCAN0.GAFLP13.UINT8[HH]
-#define RSCAN0GAFLID4 RSCAN0.GAFLID4.UINT32
-#define RSCAN0GAFLID4L RSCAN0.GAFLID4.UINT16[L]
-#define RSCAN0GAFLID4LL RSCAN0.GAFLID4.UINT8[LL]
-#define RSCAN0GAFLID4LH RSCAN0.GAFLID4.UINT8[LH]
-#define RSCAN0GAFLID4H RSCAN0.GAFLID4.UINT16[H]
-#define RSCAN0GAFLID4HL RSCAN0.GAFLID4.UINT8[HL]
-#define RSCAN0GAFLID4HH RSCAN0.GAFLID4.UINT8[HH]
-#define RSCAN0GAFLM4 RSCAN0.GAFLM4.UINT32
-#define RSCAN0GAFLM4L RSCAN0.GAFLM4.UINT16[L]
-#define RSCAN0GAFLM4LL RSCAN0.GAFLM4.UINT8[LL]
-#define RSCAN0GAFLM4LH RSCAN0.GAFLM4.UINT8[LH]
-#define RSCAN0GAFLM4H RSCAN0.GAFLM4.UINT16[H]
-#define RSCAN0GAFLM4HL RSCAN0.GAFLM4.UINT8[HL]
-#define RSCAN0GAFLM4HH RSCAN0.GAFLM4.UINT8[HH]
-#define RSCAN0GAFLP04 RSCAN0.GAFLP04.UINT32
-#define RSCAN0GAFLP04L RSCAN0.GAFLP04.UINT16[L]
-#define RSCAN0GAFLP04LL RSCAN0.GAFLP04.UINT8[LL]
-#define RSCAN0GAFLP04LH RSCAN0.GAFLP04.UINT8[LH]
-#define RSCAN0GAFLP04H RSCAN0.GAFLP04.UINT16[H]
-#define RSCAN0GAFLP04HL RSCAN0.GAFLP04.UINT8[HL]
-#define RSCAN0GAFLP04HH RSCAN0.GAFLP04.UINT8[HH]
-#define RSCAN0GAFLP14 RSCAN0.GAFLP14.UINT32
-#define RSCAN0GAFLP14L RSCAN0.GAFLP14.UINT16[L]
-#define RSCAN0GAFLP14LL RSCAN0.GAFLP14.UINT8[LL]
-#define RSCAN0GAFLP14LH RSCAN0.GAFLP14.UINT8[LH]
-#define RSCAN0GAFLP14H RSCAN0.GAFLP14.UINT16[H]
-#define RSCAN0GAFLP14HL RSCAN0.GAFLP14.UINT8[HL]
-#define RSCAN0GAFLP14HH RSCAN0.GAFLP14.UINT8[HH]
-#define RSCAN0GAFLID5 RSCAN0.GAFLID5.UINT32
-#define RSCAN0GAFLID5L RSCAN0.GAFLID5.UINT16[L]
-#define RSCAN0GAFLID5LL RSCAN0.GAFLID5.UINT8[LL]
-#define RSCAN0GAFLID5LH RSCAN0.GAFLID5.UINT8[LH]
-#define RSCAN0GAFLID5H RSCAN0.GAFLID5.UINT16[H]
-#define RSCAN0GAFLID5HL RSCAN0.GAFLID5.UINT8[HL]
-#define RSCAN0GAFLID5HH RSCAN0.GAFLID5.UINT8[HH]
-#define RSCAN0GAFLM5 RSCAN0.GAFLM5.UINT32
-#define RSCAN0GAFLM5L RSCAN0.GAFLM5.UINT16[L]
-#define RSCAN0GAFLM5LL RSCAN0.GAFLM5.UINT8[LL]
-#define RSCAN0GAFLM5LH RSCAN0.GAFLM5.UINT8[LH]
-#define RSCAN0GAFLM5H RSCAN0.GAFLM5.UINT16[H]
-#define RSCAN0GAFLM5HL RSCAN0.GAFLM5.UINT8[HL]
-#define RSCAN0GAFLM5HH RSCAN0.GAFLM5.UINT8[HH]
-#define RSCAN0GAFLP05 RSCAN0.GAFLP05.UINT32
-#define RSCAN0GAFLP05L RSCAN0.GAFLP05.UINT16[L]
-#define RSCAN0GAFLP05LL RSCAN0.GAFLP05.UINT8[LL]
-#define RSCAN0GAFLP05LH RSCAN0.GAFLP05.UINT8[LH]
-#define RSCAN0GAFLP05H RSCAN0.GAFLP05.UINT16[H]
-#define RSCAN0GAFLP05HL RSCAN0.GAFLP05.UINT8[HL]
-#define RSCAN0GAFLP05HH RSCAN0.GAFLP05.UINT8[HH]
-#define RSCAN0GAFLP15 RSCAN0.GAFLP15.UINT32
-#define RSCAN0GAFLP15L RSCAN0.GAFLP15.UINT16[L]
-#define RSCAN0GAFLP15LL RSCAN0.GAFLP15.UINT8[LL]
-#define RSCAN0GAFLP15LH RSCAN0.GAFLP15.UINT8[LH]
-#define RSCAN0GAFLP15H RSCAN0.GAFLP15.UINT16[H]
-#define RSCAN0GAFLP15HL RSCAN0.GAFLP15.UINT8[HL]
-#define RSCAN0GAFLP15HH RSCAN0.GAFLP15.UINT8[HH]
-#define RSCAN0GAFLID6 RSCAN0.GAFLID6.UINT32
-#define RSCAN0GAFLID6L RSCAN0.GAFLID6.UINT16[L]
-#define RSCAN0GAFLID6LL RSCAN0.GAFLID6.UINT8[LL]
-#define RSCAN0GAFLID6LH RSCAN0.GAFLID6.UINT8[LH]
-#define RSCAN0GAFLID6H RSCAN0.GAFLID6.UINT16[H]
-#define RSCAN0GAFLID6HL RSCAN0.GAFLID6.UINT8[HL]
-#define RSCAN0GAFLID6HH RSCAN0.GAFLID6.UINT8[HH]
-#define RSCAN0GAFLM6 RSCAN0.GAFLM6.UINT32
-#define RSCAN0GAFLM6L RSCAN0.GAFLM6.UINT16[L]
-#define RSCAN0GAFLM6LL RSCAN0.GAFLM6.UINT8[LL]
-#define RSCAN0GAFLM6LH RSCAN0.GAFLM6.UINT8[LH]
-#define RSCAN0GAFLM6H RSCAN0.GAFLM6.UINT16[H]
-#define RSCAN0GAFLM6HL RSCAN0.GAFLM6.UINT8[HL]
-#define RSCAN0GAFLM6HH RSCAN0.GAFLM6.UINT8[HH]
-#define RSCAN0GAFLP06 RSCAN0.GAFLP06.UINT32
-#define RSCAN0GAFLP06L RSCAN0.GAFLP06.UINT16[L]
-#define RSCAN0GAFLP06LL RSCAN0.GAFLP06.UINT8[LL]
-#define RSCAN0GAFLP06LH RSCAN0.GAFLP06.UINT8[LH]
-#define RSCAN0GAFLP06H RSCAN0.GAFLP06.UINT16[H]
-#define RSCAN0GAFLP06HL RSCAN0.GAFLP06.UINT8[HL]
-#define RSCAN0GAFLP06HH RSCAN0.GAFLP06.UINT8[HH]
-#define RSCAN0GAFLP16 RSCAN0.GAFLP16.UINT32
-#define RSCAN0GAFLP16L RSCAN0.GAFLP16.UINT16[L]
-#define RSCAN0GAFLP16LL RSCAN0.GAFLP16.UINT8[LL]
-#define RSCAN0GAFLP16LH RSCAN0.GAFLP16.UINT8[LH]
-#define RSCAN0GAFLP16H RSCAN0.GAFLP16.UINT16[H]
-#define RSCAN0GAFLP16HL RSCAN0.GAFLP16.UINT8[HL]
-#define RSCAN0GAFLP16HH RSCAN0.GAFLP16.UINT8[HH]
-#define RSCAN0GAFLID7 RSCAN0.GAFLID7.UINT32
-#define RSCAN0GAFLID7L RSCAN0.GAFLID7.UINT16[L]
-#define RSCAN0GAFLID7LL RSCAN0.GAFLID7.UINT8[LL]
-#define RSCAN0GAFLID7LH RSCAN0.GAFLID7.UINT8[LH]
-#define RSCAN0GAFLID7H RSCAN0.GAFLID7.UINT16[H]
-#define RSCAN0GAFLID7HL RSCAN0.GAFLID7.UINT8[HL]
-#define RSCAN0GAFLID7HH RSCAN0.GAFLID7.UINT8[HH]
-#define RSCAN0GAFLM7 RSCAN0.GAFLM7.UINT32
-#define RSCAN0GAFLM7L RSCAN0.GAFLM7.UINT16[L]
-#define RSCAN0GAFLM7LL RSCAN0.GAFLM7.UINT8[LL]
-#define RSCAN0GAFLM7LH RSCAN0.GAFLM7.UINT8[LH]
-#define RSCAN0GAFLM7H RSCAN0.GAFLM7.UINT16[H]
-#define RSCAN0GAFLM7HL RSCAN0.GAFLM7.UINT8[HL]
-#define RSCAN0GAFLM7HH RSCAN0.GAFLM7.UINT8[HH]
-#define RSCAN0GAFLP07 RSCAN0.GAFLP07.UINT32
-#define RSCAN0GAFLP07L RSCAN0.GAFLP07.UINT16[L]
-#define RSCAN0GAFLP07LL RSCAN0.GAFLP07.UINT8[LL]
-#define RSCAN0GAFLP07LH RSCAN0.GAFLP07.UINT8[LH]
-#define RSCAN0GAFLP07H RSCAN0.GAFLP07.UINT16[H]
-#define RSCAN0GAFLP07HL RSCAN0.GAFLP07.UINT8[HL]
-#define RSCAN0GAFLP07HH RSCAN0.GAFLP07.UINT8[HH]
-#define RSCAN0GAFLP17 RSCAN0.GAFLP17.UINT32
-#define RSCAN0GAFLP17L RSCAN0.GAFLP17.UINT16[L]
-#define RSCAN0GAFLP17LL RSCAN0.GAFLP17.UINT8[LL]
-#define RSCAN0GAFLP17LH RSCAN0.GAFLP17.UINT8[LH]
-#define RSCAN0GAFLP17H RSCAN0.GAFLP17.UINT16[H]
-#define RSCAN0GAFLP17HL RSCAN0.GAFLP17.UINT8[HL]
-#define RSCAN0GAFLP17HH RSCAN0.GAFLP17.UINT8[HH]
-#define RSCAN0GAFLID8 RSCAN0.GAFLID8.UINT32
-#define RSCAN0GAFLID8L RSCAN0.GAFLID8.UINT16[L]
-#define RSCAN0GAFLID8LL RSCAN0.GAFLID8.UINT8[LL]
-#define RSCAN0GAFLID8LH RSCAN0.GAFLID8.UINT8[LH]
-#define RSCAN0GAFLID8H RSCAN0.GAFLID8.UINT16[H]
-#define RSCAN0GAFLID8HL RSCAN0.GAFLID8.UINT8[HL]
-#define RSCAN0GAFLID8HH RSCAN0.GAFLID8.UINT8[HH]
-#define RSCAN0GAFLM8 RSCAN0.GAFLM8.UINT32
-#define RSCAN0GAFLM8L RSCAN0.GAFLM8.UINT16[L]
-#define RSCAN0GAFLM8LL RSCAN0.GAFLM8.UINT8[LL]
-#define RSCAN0GAFLM8LH RSCAN0.GAFLM8.UINT8[LH]
-#define RSCAN0GAFLM8H RSCAN0.GAFLM8.UINT16[H]
-#define RSCAN0GAFLM8HL RSCAN0.GAFLM8.UINT8[HL]
-#define RSCAN0GAFLM8HH RSCAN0.GAFLM8.UINT8[HH]
-#define RSCAN0GAFLP08 RSCAN0.GAFLP08.UINT32
-#define RSCAN0GAFLP08L RSCAN0.GAFLP08.UINT16[L]
-#define RSCAN0GAFLP08LL RSCAN0.GAFLP08.UINT8[LL]
-#define RSCAN0GAFLP08LH RSCAN0.GAFLP08.UINT8[LH]
-#define RSCAN0GAFLP08H RSCAN0.GAFLP08.UINT16[H]
-#define RSCAN0GAFLP08HL RSCAN0.GAFLP08.UINT8[HL]
-#define RSCAN0GAFLP08HH RSCAN0.GAFLP08.UINT8[HH]
-#define RSCAN0GAFLP18 RSCAN0.GAFLP18.UINT32
-#define RSCAN0GAFLP18L RSCAN0.GAFLP18.UINT16[L]
-#define RSCAN0GAFLP18LL RSCAN0.GAFLP18.UINT8[LL]
-#define RSCAN0GAFLP18LH RSCAN0.GAFLP18.UINT8[LH]
-#define RSCAN0GAFLP18H RSCAN0.GAFLP18.UINT16[H]
-#define RSCAN0GAFLP18HL RSCAN0.GAFLP18.UINT8[HL]
-#define RSCAN0GAFLP18HH RSCAN0.GAFLP18.UINT8[HH]
-#define RSCAN0GAFLID9 RSCAN0.GAFLID9.UINT32
-#define RSCAN0GAFLID9L RSCAN0.GAFLID9.UINT16[L]
-#define RSCAN0GAFLID9LL RSCAN0.GAFLID9.UINT8[LL]
-#define RSCAN0GAFLID9LH RSCAN0.GAFLID9.UINT8[LH]
-#define RSCAN0GAFLID9H RSCAN0.GAFLID9.UINT16[H]
-#define RSCAN0GAFLID9HL RSCAN0.GAFLID9.UINT8[HL]
-#define RSCAN0GAFLID9HH RSCAN0.GAFLID9.UINT8[HH]
-#define RSCAN0GAFLM9 RSCAN0.GAFLM9.UINT32
-#define RSCAN0GAFLM9L RSCAN0.GAFLM9.UINT16[L]
-#define RSCAN0GAFLM9LL RSCAN0.GAFLM9.UINT8[LL]
-#define RSCAN0GAFLM9LH RSCAN0.GAFLM9.UINT8[LH]
-#define RSCAN0GAFLM9H RSCAN0.GAFLM9.UINT16[H]
-#define RSCAN0GAFLM9HL RSCAN0.GAFLM9.UINT8[HL]
-#define RSCAN0GAFLM9HH RSCAN0.GAFLM9.UINT8[HH]
-#define RSCAN0GAFLP09 RSCAN0.GAFLP09.UINT32
-#define RSCAN0GAFLP09L RSCAN0.GAFLP09.UINT16[L]
-#define RSCAN0GAFLP09LL RSCAN0.GAFLP09.UINT8[LL]
-#define RSCAN0GAFLP09LH RSCAN0.GAFLP09.UINT8[LH]
-#define RSCAN0GAFLP09H RSCAN0.GAFLP09.UINT16[H]
-#define RSCAN0GAFLP09HL RSCAN0.GAFLP09.UINT8[HL]
-#define RSCAN0GAFLP09HH RSCAN0.GAFLP09.UINT8[HH]
-#define RSCAN0GAFLP19 RSCAN0.GAFLP19.UINT32
-#define RSCAN0GAFLP19L RSCAN0.GAFLP19.UINT16[L]
-#define RSCAN0GAFLP19LL RSCAN0.GAFLP19.UINT8[LL]
-#define RSCAN0GAFLP19LH RSCAN0.GAFLP19.UINT8[LH]
-#define RSCAN0GAFLP19H RSCAN0.GAFLP19.UINT16[H]
-#define RSCAN0GAFLP19HL RSCAN0.GAFLP19.UINT8[HL]
-#define RSCAN0GAFLP19HH RSCAN0.GAFLP19.UINT8[HH]
-#define RSCAN0GAFLID10 RSCAN0.GAFLID10.UINT32
-#define RSCAN0GAFLID10L RSCAN0.GAFLID10.UINT16[L]
-#define RSCAN0GAFLID10LL RSCAN0.GAFLID10.UINT8[LL]
-#define RSCAN0GAFLID10LH RSCAN0.GAFLID10.UINT8[LH]
-#define RSCAN0GAFLID10H RSCAN0.GAFLID10.UINT16[H]
-#define RSCAN0GAFLID10HL RSCAN0.GAFLID10.UINT8[HL]
-#define RSCAN0GAFLID10HH RSCAN0.GAFLID10.UINT8[HH]
-#define RSCAN0GAFLM10 RSCAN0.GAFLM10.UINT32
-#define RSCAN0GAFLM10L RSCAN0.GAFLM10.UINT16[L]
-#define RSCAN0GAFLM10LL RSCAN0.GAFLM10.UINT8[LL]
-#define RSCAN0GAFLM10LH RSCAN0.GAFLM10.UINT8[LH]
-#define RSCAN0GAFLM10H RSCAN0.GAFLM10.UINT16[H]
-#define RSCAN0GAFLM10HL RSCAN0.GAFLM10.UINT8[HL]
-#define RSCAN0GAFLM10HH RSCAN0.GAFLM10.UINT8[HH]
-#define RSCAN0GAFLP010 RSCAN0.GAFLP010.UINT32
-#define RSCAN0GAFLP010L RSCAN0.GAFLP010.UINT16[L]
-#define RSCAN0GAFLP010LL RSCAN0.GAFLP010.UINT8[LL]
-#define RSCAN0GAFLP010LH RSCAN0.GAFLP010.UINT8[LH]
-#define RSCAN0GAFLP010H RSCAN0.GAFLP010.UINT16[H]
-#define RSCAN0GAFLP010HL RSCAN0.GAFLP010.UINT8[HL]
-#define RSCAN0GAFLP010HH RSCAN0.GAFLP010.UINT8[HH]
-#define RSCAN0GAFLP110 RSCAN0.GAFLP110.UINT32
-#define RSCAN0GAFLP110L RSCAN0.GAFLP110.UINT16[L]
-#define RSCAN0GAFLP110LL RSCAN0.GAFLP110.UINT8[LL]
-#define RSCAN0GAFLP110LH RSCAN0.GAFLP110.UINT8[LH]
-#define RSCAN0GAFLP110H RSCAN0.GAFLP110.UINT16[H]
-#define RSCAN0GAFLP110HL RSCAN0.GAFLP110.UINT8[HL]
-#define RSCAN0GAFLP110HH RSCAN0.GAFLP110.UINT8[HH]
-#define RSCAN0GAFLID11 RSCAN0.GAFLID11.UINT32
-#define RSCAN0GAFLID11L RSCAN0.GAFLID11.UINT16[L]
-#define RSCAN0GAFLID11LL RSCAN0.GAFLID11.UINT8[LL]
-#define RSCAN0GAFLID11LH RSCAN0.GAFLID11.UINT8[LH]
-#define RSCAN0GAFLID11H RSCAN0.GAFLID11.UINT16[H]
-#define RSCAN0GAFLID11HL RSCAN0.GAFLID11.UINT8[HL]
-#define RSCAN0GAFLID11HH RSCAN0.GAFLID11.UINT8[HH]
-#define RSCAN0GAFLM11 RSCAN0.GAFLM11.UINT32
-#define RSCAN0GAFLM11L RSCAN0.GAFLM11.UINT16[L]
-#define RSCAN0GAFLM11LL RSCAN0.GAFLM11.UINT8[LL]
-#define RSCAN0GAFLM11LH RSCAN0.GAFLM11.UINT8[LH]
-#define RSCAN0GAFLM11H RSCAN0.GAFLM11.UINT16[H]
-#define RSCAN0GAFLM11HL RSCAN0.GAFLM11.UINT8[HL]
-#define RSCAN0GAFLM11HH RSCAN0.GAFLM11.UINT8[HH]
-#define RSCAN0GAFLP011 RSCAN0.GAFLP011.UINT32
-#define RSCAN0GAFLP011L RSCAN0.GAFLP011.UINT16[L]
-#define RSCAN0GAFLP011LL RSCAN0.GAFLP011.UINT8[LL]
-#define RSCAN0GAFLP011LH RSCAN0.GAFLP011.UINT8[LH]
-#define RSCAN0GAFLP011H RSCAN0.GAFLP011.UINT16[H]
-#define RSCAN0GAFLP011HL RSCAN0.GAFLP011.UINT8[HL]
-#define RSCAN0GAFLP011HH RSCAN0.GAFLP011.UINT8[HH]
-#define RSCAN0GAFLP111 RSCAN0.GAFLP111.UINT32
-#define RSCAN0GAFLP111L RSCAN0.GAFLP111.UINT16[L]
-#define RSCAN0GAFLP111LL RSCAN0.GAFLP111.UINT8[LL]
-#define RSCAN0GAFLP111LH RSCAN0.GAFLP111.UINT8[LH]
-#define RSCAN0GAFLP111H RSCAN0.GAFLP111.UINT16[H]
-#define RSCAN0GAFLP111HL RSCAN0.GAFLP111.UINT8[HL]
-#define RSCAN0GAFLP111HH RSCAN0.GAFLP111.UINT8[HH]
-#define RSCAN0GAFLID12 RSCAN0.GAFLID12.UINT32
-#define RSCAN0GAFLID12L RSCAN0.GAFLID12.UINT16[L]
-#define RSCAN0GAFLID12LL RSCAN0.GAFLID12.UINT8[LL]
-#define RSCAN0GAFLID12LH RSCAN0.GAFLID12.UINT8[LH]
-#define RSCAN0GAFLID12H RSCAN0.GAFLID12.UINT16[H]
-#define RSCAN0GAFLID12HL RSCAN0.GAFLID12.UINT8[HL]
-#define RSCAN0GAFLID12HH RSCAN0.GAFLID12.UINT8[HH]
-#define RSCAN0GAFLM12 RSCAN0.GAFLM12.UINT32
-#define RSCAN0GAFLM12L RSCAN0.GAFLM12.UINT16[L]
-#define RSCAN0GAFLM12LL RSCAN0.GAFLM12.UINT8[LL]
-#define RSCAN0GAFLM12LH RSCAN0.GAFLM12.UINT8[LH]
-#define RSCAN0GAFLM12H RSCAN0.GAFLM12.UINT16[H]
-#define RSCAN0GAFLM12HL RSCAN0.GAFLM12.UINT8[HL]
-#define RSCAN0GAFLM12HH RSCAN0.GAFLM12.UINT8[HH]
-#define RSCAN0GAFLP012 RSCAN0.GAFLP012.UINT32
-#define RSCAN0GAFLP012L RSCAN0.GAFLP012.UINT16[L]
-#define RSCAN0GAFLP012LL RSCAN0.GAFLP012.UINT8[LL]
-#define RSCAN0GAFLP012LH RSCAN0.GAFLP012.UINT8[LH]
-#define RSCAN0GAFLP012H RSCAN0.GAFLP012.UINT16[H]
-#define RSCAN0GAFLP012HL RSCAN0.GAFLP012.UINT8[HL]
-#define RSCAN0GAFLP012HH RSCAN0.GAFLP012.UINT8[HH]
-#define RSCAN0GAFLP112 RSCAN0.GAFLP112.UINT32
-#define RSCAN0GAFLP112L RSCAN0.GAFLP112.UINT16[L]
-#define RSCAN0GAFLP112LL RSCAN0.GAFLP112.UINT8[LL]
-#define RSCAN0GAFLP112LH RSCAN0.GAFLP112.UINT8[LH]
-#define RSCAN0GAFLP112H RSCAN0.GAFLP112.UINT16[H]
-#define RSCAN0GAFLP112HL RSCAN0.GAFLP112.UINT8[HL]
-#define RSCAN0GAFLP112HH RSCAN0.GAFLP112.UINT8[HH]
-#define RSCAN0GAFLID13 RSCAN0.GAFLID13.UINT32
-#define RSCAN0GAFLID13L RSCAN0.GAFLID13.UINT16[L]
-#define RSCAN0GAFLID13LL RSCAN0.GAFLID13.UINT8[LL]
-#define RSCAN0GAFLID13LH RSCAN0.GAFLID13.UINT8[LH]
-#define RSCAN0GAFLID13H RSCAN0.GAFLID13.UINT16[H]
-#define RSCAN0GAFLID13HL RSCAN0.GAFLID13.UINT8[HL]
-#define RSCAN0GAFLID13HH RSCAN0.GAFLID13.UINT8[HH]
-#define RSCAN0GAFLM13 RSCAN0.GAFLM13.UINT32
-#define RSCAN0GAFLM13L RSCAN0.GAFLM13.UINT16[L]
-#define RSCAN0GAFLM13LL RSCAN0.GAFLM13.UINT8[LL]
-#define RSCAN0GAFLM13LH RSCAN0.GAFLM13.UINT8[LH]
-#define RSCAN0GAFLM13H RSCAN0.GAFLM13.UINT16[H]
-#define RSCAN0GAFLM13HL RSCAN0.GAFLM13.UINT8[HL]
-#define RSCAN0GAFLM13HH RSCAN0.GAFLM13.UINT8[HH]
-#define RSCAN0GAFLP013 RSCAN0.GAFLP013.UINT32
-#define RSCAN0GAFLP013L RSCAN0.GAFLP013.UINT16[L]
-#define RSCAN0GAFLP013LL RSCAN0.GAFLP013.UINT8[LL]
-#define RSCAN0GAFLP013LH RSCAN0.GAFLP013.UINT8[LH]
-#define RSCAN0GAFLP013H RSCAN0.GAFLP013.UINT16[H]
-#define RSCAN0GAFLP013HL RSCAN0.GAFLP013.UINT8[HL]
-#define RSCAN0GAFLP013HH RSCAN0.GAFLP013.UINT8[HH]
-#define RSCAN0GAFLP113 RSCAN0.GAFLP113.UINT32
-#define RSCAN0GAFLP113L RSCAN0.GAFLP113.UINT16[L]
-#define RSCAN0GAFLP113LL RSCAN0.GAFLP113.UINT8[LL]
-#define RSCAN0GAFLP113LH RSCAN0.GAFLP113.UINT8[LH]
-#define RSCAN0GAFLP113H RSCAN0.GAFLP113.UINT16[H]
-#define RSCAN0GAFLP113HL RSCAN0.GAFLP113.UINT8[HL]
-#define RSCAN0GAFLP113HH RSCAN0.GAFLP113.UINT8[HH]
-#define RSCAN0GAFLID14 RSCAN0.GAFLID14.UINT32
-#define RSCAN0GAFLID14L RSCAN0.GAFLID14.UINT16[L]
-#define RSCAN0GAFLID14LL RSCAN0.GAFLID14.UINT8[LL]
-#define RSCAN0GAFLID14LH RSCAN0.GAFLID14.UINT8[LH]
-#define RSCAN0GAFLID14H RSCAN0.GAFLID14.UINT16[H]
-#define RSCAN0GAFLID14HL RSCAN0.GAFLID14.UINT8[HL]
-#define RSCAN0GAFLID14HH RSCAN0.GAFLID14.UINT8[HH]
-#define RSCAN0GAFLM14 RSCAN0.GAFLM14.UINT32
-#define RSCAN0GAFLM14L RSCAN0.GAFLM14.UINT16[L]
-#define RSCAN0GAFLM14LL RSCAN0.GAFLM14.UINT8[LL]
-#define RSCAN0GAFLM14LH RSCAN0.GAFLM14.UINT8[LH]
-#define RSCAN0GAFLM14H RSCAN0.GAFLM14.UINT16[H]
-#define RSCAN0GAFLM14HL RSCAN0.GAFLM14.UINT8[HL]
-#define RSCAN0GAFLM14HH RSCAN0.GAFLM14.UINT8[HH]
-#define RSCAN0GAFLP014 RSCAN0.GAFLP014.UINT32
-#define RSCAN0GAFLP014L RSCAN0.GAFLP014.UINT16[L]
-#define RSCAN0GAFLP014LL RSCAN0.GAFLP014.UINT8[LL]
-#define RSCAN0GAFLP014LH RSCAN0.GAFLP014.UINT8[LH]
-#define RSCAN0GAFLP014H RSCAN0.GAFLP014.UINT16[H]
-#define RSCAN0GAFLP014HL RSCAN0.GAFLP014.UINT8[HL]
-#define RSCAN0GAFLP014HH RSCAN0.GAFLP014.UINT8[HH]
-#define RSCAN0GAFLP114 RSCAN0.GAFLP114.UINT32
-#define RSCAN0GAFLP114L RSCAN0.GAFLP114.UINT16[L]
-#define RSCAN0GAFLP114LL RSCAN0.GAFLP114.UINT8[LL]
-#define RSCAN0GAFLP114LH RSCAN0.GAFLP114.UINT8[LH]
-#define RSCAN0GAFLP114H RSCAN0.GAFLP114.UINT16[H]
-#define RSCAN0GAFLP114HL RSCAN0.GAFLP114.UINT8[HL]
-#define RSCAN0GAFLP114HH RSCAN0.GAFLP114.UINT8[HH]
-#define RSCAN0GAFLID15 RSCAN0.GAFLID15.UINT32
-#define RSCAN0GAFLID15L RSCAN0.GAFLID15.UINT16[L]
-#define RSCAN0GAFLID15LL RSCAN0.GAFLID15.UINT8[LL]
-#define RSCAN0GAFLID15LH RSCAN0.GAFLID15.UINT8[LH]
-#define RSCAN0GAFLID15H RSCAN0.GAFLID15.UINT16[H]
-#define RSCAN0GAFLID15HL RSCAN0.GAFLID15.UINT8[HL]
-#define RSCAN0GAFLID15HH RSCAN0.GAFLID15.UINT8[HH]
-#define RSCAN0GAFLM15 RSCAN0.GAFLM15.UINT32
-#define RSCAN0GAFLM15L RSCAN0.GAFLM15.UINT16[L]
-#define RSCAN0GAFLM15LL RSCAN0.GAFLM15.UINT8[LL]
-#define RSCAN0GAFLM15LH RSCAN0.GAFLM15.UINT8[LH]
-#define RSCAN0GAFLM15H RSCAN0.GAFLM15.UINT16[H]
-#define RSCAN0GAFLM15HL RSCAN0.GAFLM15.UINT8[HL]
-#define RSCAN0GAFLM15HH RSCAN0.GAFLM15.UINT8[HH]
-#define RSCAN0GAFLP015 RSCAN0.GAFLP015.UINT32
-#define RSCAN0GAFLP015L RSCAN0.GAFLP015.UINT16[L]
-#define RSCAN0GAFLP015LL RSCAN0.GAFLP015.UINT8[LL]
-#define RSCAN0GAFLP015LH RSCAN0.GAFLP015.UINT8[LH]
-#define RSCAN0GAFLP015H RSCAN0.GAFLP015.UINT16[H]
-#define RSCAN0GAFLP015HL RSCAN0.GAFLP015.UINT8[HL]
-#define RSCAN0GAFLP015HH RSCAN0.GAFLP015.UINT8[HH]
-#define RSCAN0GAFLP115 RSCAN0.GAFLP115.UINT32
-#define RSCAN0GAFLP115L RSCAN0.GAFLP115.UINT16[L]
-#define RSCAN0GAFLP115LL RSCAN0.GAFLP115.UINT8[LL]
-#define RSCAN0GAFLP115LH RSCAN0.GAFLP115.UINT8[LH]
-#define RSCAN0GAFLP115H RSCAN0.GAFLP115.UINT16[H]
-#define RSCAN0GAFLP115HL RSCAN0.GAFLP115.UINT8[HL]
-#define RSCAN0GAFLP115HH RSCAN0.GAFLP115.UINT8[HH]
-#define RSCAN0RMID0 RSCAN0.RMID0.UINT32
-#define RSCAN0RMID0L RSCAN0.RMID0.UINT16[L]
-#define RSCAN0RMID0LL RSCAN0.RMID0.UINT8[LL]
-#define RSCAN0RMID0LH RSCAN0.RMID0.UINT8[LH]
-#define RSCAN0RMID0H RSCAN0.RMID0.UINT16[H]
-#define RSCAN0RMID0HL RSCAN0.RMID0.UINT8[HL]
-#define RSCAN0RMID0HH RSCAN0.RMID0.UINT8[HH]
-#define RSCAN0RMPTR0 RSCAN0.RMPTR0.UINT32
-#define RSCAN0RMPTR0L RSCAN0.RMPTR0.UINT16[L]
-#define RSCAN0RMPTR0LL RSCAN0.RMPTR0.UINT8[LL]
-#define RSCAN0RMPTR0LH RSCAN0.RMPTR0.UINT8[LH]
-#define RSCAN0RMPTR0H RSCAN0.RMPTR0.UINT16[H]
-#define RSCAN0RMPTR0HL RSCAN0.RMPTR0.UINT8[HL]
-#define RSCAN0RMPTR0HH RSCAN0.RMPTR0.UINT8[HH]
-#define RSCAN0RMDF00 RSCAN0.RMDF00.UINT32
-#define RSCAN0RMDF00L RSCAN0.RMDF00.UINT16[L]
-#define RSCAN0RMDF00LL RSCAN0.RMDF00.UINT8[LL]
-#define RSCAN0RMDF00LH RSCAN0.RMDF00.UINT8[LH]
-#define RSCAN0RMDF00H RSCAN0.RMDF00.UINT16[H]
-#define RSCAN0RMDF00HL RSCAN0.RMDF00.UINT8[HL]
-#define RSCAN0RMDF00HH RSCAN0.RMDF00.UINT8[HH]
-#define RSCAN0RMDF10 RSCAN0.RMDF10.UINT32
-#define RSCAN0RMDF10L RSCAN0.RMDF10.UINT16[L]
-#define RSCAN0RMDF10LL RSCAN0.RMDF10.UINT8[LL]
-#define RSCAN0RMDF10LH RSCAN0.RMDF10.UINT8[LH]
-#define RSCAN0RMDF10H RSCAN0.RMDF10.UINT16[H]
-#define RSCAN0RMDF10HL RSCAN0.RMDF10.UINT8[HL]
-#define RSCAN0RMDF10HH RSCAN0.RMDF10.UINT8[HH]
-#define RSCAN0RMID1 RSCAN0.RMID1.UINT32
-#define RSCAN0RMID1L RSCAN0.RMID1.UINT16[L]
-#define RSCAN0RMID1LL RSCAN0.RMID1.UINT8[LL]
-#define RSCAN0RMID1LH RSCAN0.RMID1.UINT8[LH]
-#define RSCAN0RMID1H RSCAN0.RMID1.UINT16[H]
-#define RSCAN0RMID1HL RSCAN0.RMID1.UINT8[HL]
-#define RSCAN0RMID1HH RSCAN0.RMID1.UINT8[HH]
-#define RSCAN0RMPTR1 RSCAN0.RMPTR1.UINT32
-#define RSCAN0RMPTR1L RSCAN0.RMPTR1.UINT16[L]
-#define RSCAN0RMPTR1LL RSCAN0.RMPTR1.UINT8[LL]
-#define RSCAN0RMPTR1LH RSCAN0.RMPTR1.UINT8[LH]
-#define RSCAN0RMPTR1H RSCAN0.RMPTR1.UINT16[H]
-#define RSCAN0RMPTR1HL RSCAN0.RMPTR1.UINT8[HL]
-#define RSCAN0RMPTR1HH RSCAN0.RMPTR1.UINT8[HH]
-#define RSCAN0RMDF01 RSCAN0.RMDF01.UINT32
-#define RSCAN0RMDF01L RSCAN0.RMDF01.UINT16[L]
-#define RSCAN0RMDF01LL RSCAN0.RMDF01.UINT8[LL]
-#define RSCAN0RMDF01LH RSCAN0.RMDF01.UINT8[LH]
-#define RSCAN0RMDF01H RSCAN0.RMDF01.UINT16[H]
-#define RSCAN0RMDF01HL RSCAN0.RMDF01.UINT8[HL]
-#define RSCAN0RMDF01HH RSCAN0.RMDF01.UINT8[HH]
-#define RSCAN0RMDF11 RSCAN0.RMDF11.UINT32
-#define RSCAN0RMDF11L RSCAN0.RMDF11.UINT16[L]
-#define RSCAN0RMDF11LL RSCAN0.RMDF11.UINT8[LL]
-#define RSCAN0RMDF11LH RSCAN0.RMDF11.UINT8[LH]
-#define RSCAN0RMDF11H RSCAN0.RMDF11.UINT16[H]
-#define RSCAN0RMDF11HL RSCAN0.RMDF11.UINT8[HL]
-#define RSCAN0RMDF11HH RSCAN0.RMDF11.UINT8[HH]
-#define RSCAN0RMID2 RSCAN0.RMID2.UINT32
-#define RSCAN0RMID2L RSCAN0.RMID2.UINT16[L]
-#define RSCAN0RMID2LL RSCAN0.RMID2.UINT8[LL]
-#define RSCAN0RMID2LH RSCAN0.RMID2.UINT8[LH]
-#define RSCAN0RMID2H RSCAN0.RMID2.UINT16[H]
-#define RSCAN0RMID2HL RSCAN0.RMID2.UINT8[HL]
-#define RSCAN0RMID2HH RSCAN0.RMID2.UINT8[HH]
-#define RSCAN0RMPTR2 RSCAN0.RMPTR2.UINT32
-#define RSCAN0RMPTR2L RSCAN0.RMPTR2.UINT16[L]
-#define RSCAN0RMPTR2LL RSCAN0.RMPTR2.UINT8[LL]
-#define RSCAN0RMPTR2LH RSCAN0.RMPTR2.UINT8[LH]
-#define RSCAN0RMPTR2H RSCAN0.RMPTR2.UINT16[H]
-#define RSCAN0RMPTR2HL RSCAN0.RMPTR2.UINT8[HL]
-#define RSCAN0RMPTR2HH RSCAN0.RMPTR2.UINT8[HH]
-#define RSCAN0RMDF02 RSCAN0.RMDF02.UINT32
-#define RSCAN0RMDF02L RSCAN0.RMDF02.UINT16[L]
-#define RSCAN0RMDF02LL RSCAN0.RMDF02.UINT8[LL]
-#define RSCAN0RMDF02LH RSCAN0.RMDF02.UINT8[LH]
-#define RSCAN0RMDF02H RSCAN0.RMDF02.UINT16[H]
-#define RSCAN0RMDF02HL RSCAN0.RMDF02.UINT8[HL]
-#define RSCAN0RMDF02HH RSCAN0.RMDF02.UINT8[HH]
-#define RSCAN0RMDF12 RSCAN0.RMDF12.UINT32
-#define RSCAN0RMDF12L RSCAN0.RMDF12.UINT16[L]
-#define RSCAN0RMDF12LL RSCAN0.RMDF12.UINT8[LL]
-#define RSCAN0RMDF12LH RSCAN0.RMDF12.UINT8[LH]
-#define RSCAN0RMDF12H RSCAN0.RMDF12.UINT16[H]
-#define RSCAN0RMDF12HL RSCAN0.RMDF12.UINT8[HL]
-#define RSCAN0RMDF12HH RSCAN0.RMDF12.UINT8[HH]
-#define RSCAN0RMID3 RSCAN0.RMID3.UINT32
-#define RSCAN0RMID3L RSCAN0.RMID3.UINT16[L]
-#define RSCAN0RMID3LL RSCAN0.RMID3.UINT8[LL]
-#define RSCAN0RMID3LH RSCAN0.RMID3.UINT8[LH]
-#define RSCAN0RMID3H RSCAN0.RMID3.UINT16[H]
-#define RSCAN0RMID3HL RSCAN0.RMID3.UINT8[HL]
-#define RSCAN0RMID3HH RSCAN0.RMID3.UINT8[HH]
-#define RSCAN0RMPTR3 RSCAN0.RMPTR3.UINT32
-#define RSCAN0RMPTR3L RSCAN0.RMPTR3.UINT16[L]
-#define RSCAN0RMPTR3LL RSCAN0.RMPTR3.UINT8[LL]
-#define RSCAN0RMPTR3LH RSCAN0.RMPTR3.UINT8[LH]
-#define RSCAN0RMPTR3H RSCAN0.RMPTR3.UINT16[H]
-#define RSCAN0RMPTR3HL RSCAN0.RMPTR3.UINT8[HL]
-#define RSCAN0RMPTR3HH RSCAN0.RMPTR3.UINT8[HH]
-#define RSCAN0RMDF03 RSCAN0.RMDF03.UINT32
-#define RSCAN0RMDF03L RSCAN0.RMDF03.UINT16[L]
-#define RSCAN0RMDF03LL RSCAN0.RMDF03.UINT8[LL]
-#define RSCAN0RMDF03LH RSCAN0.RMDF03.UINT8[LH]
-#define RSCAN0RMDF03H RSCAN0.RMDF03.UINT16[H]
-#define RSCAN0RMDF03HL RSCAN0.RMDF03.UINT8[HL]
-#define RSCAN0RMDF03HH RSCAN0.RMDF03.UINT8[HH]
-#define RSCAN0RMDF13 RSCAN0.RMDF13.UINT32
-#define RSCAN0RMDF13L RSCAN0.RMDF13.UINT16[L]
-#define RSCAN0RMDF13LL RSCAN0.RMDF13.UINT8[LL]
-#define RSCAN0RMDF13LH RSCAN0.RMDF13.UINT8[LH]
-#define RSCAN0RMDF13H RSCAN0.RMDF13.UINT16[H]
-#define RSCAN0RMDF13HL RSCAN0.RMDF13.UINT8[HL]
-#define RSCAN0RMDF13HH RSCAN0.RMDF13.UINT8[HH]
-#define RSCAN0RMID4 RSCAN0.RMID4.UINT32
-#define RSCAN0RMID4L RSCAN0.RMID4.UINT16[L]
-#define RSCAN0RMID4LL RSCAN0.RMID4.UINT8[LL]
-#define RSCAN0RMID4LH RSCAN0.RMID4.UINT8[LH]
-#define RSCAN0RMID4H RSCAN0.RMID4.UINT16[H]
-#define RSCAN0RMID4HL RSCAN0.RMID4.UINT8[HL]
-#define RSCAN0RMID4HH RSCAN0.RMID4.UINT8[HH]
-#define RSCAN0RMPTR4 RSCAN0.RMPTR4.UINT32
-#define RSCAN0RMPTR4L RSCAN0.RMPTR4.UINT16[L]
-#define RSCAN0RMPTR4LL RSCAN0.RMPTR4.UINT8[LL]
-#define RSCAN0RMPTR4LH RSCAN0.RMPTR4.UINT8[LH]
-#define RSCAN0RMPTR4H RSCAN0.RMPTR4.UINT16[H]
-#define RSCAN0RMPTR4HL RSCAN0.RMPTR4.UINT8[HL]
-#define RSCAN0RMPTR4HH RSCAN0.RMPTR4.UINT8[HH]
-#define RSCAN0RMDF04 RSCAN0.RMDF04.UINT32
-#define RSCAN0RMDF04L RSCAN0.RMDF04.UINT16[L]
-#define RSCAN0RMDF04LL RSCAN0.RMDF04.UINT8[LL]
-#define RSCAN0RMDF04LH RSCAN0.RMDF04.UINT8[LH]
-#define RSCAN0RMDF04H RSCAN0.RMDF04.UINT16[H]
-#define RSCAN0RMDF04HL RSCAN0.RMDF04.UINT8[HL]
-#define RSCAN0RMDF04HH RSCAN0.RMDF04.UINT8[HH]
-#define RSCAN0RMDF14 RSCAN0.RMDF14.UINT32
-#define RSCAN0RMDF14L RSCAN0.RMDF14.UINT16[L]
-#define RSCAN0RMDF14LL RSCAN0.RMDF14.UINT8[LL]
-#define RSCAN0RMDF14LH RSCAN0.RMDF14.UINT8[LH]
-#define RSCAN0RMDF14H RSCAN0.RMDF14.UINT16[H]
-#define RSCAN0RMDF14HL RSCAN0.RMDF14.UINT8[HL]
-#define RSCAN0RMDF14HH RSCAN0.RMDF14.UINT8[HH]
-#define RSCAN0RMID5 RSCAN0.RMID5.UINT32
-#define RSCAN0RMID5L RSCAN0.RMID5.UINT16[L]
-#define RSCAN0RMID5LL RSCAN0.RMID5.UINT8[LL]
-#define RSCAN0RMID5LH RSCAN0.RMID5.UINT8[LH]
-#define RSCAN0RMID5H RSCAN0.RMID5.UINT16[H]
-#define RSCAN0RMID5HL RSCAN0.RMID5.UINT8[HL]
-#define RSCAN0RMID5HH RSCAN0.RMID5.UINT8[HH]
-#define RSCAN0RMPTR5 RSCAN0.RMPTR5.UINT32
-#define RSCAN0RMPTR5L RSCAN0.RMPTR5.UINT16[L]
-#define RSCAN0RMPTR5LL RSCAN0.RMPTR5.UINT8[LL]
-#define RSCAN0RMPTR5LH RSCAN0.RMPTR5.UINT8[LH]
-#define RSCAN0RMPTR5H RSCAN0.RMPTR5.UINT16[H]
-#define RSCAN0RMPTR5HL RSCAN0.RMPTR5.UINT8[HL]
-#define RSCAN0RMPTR5HH RSCAN0.RMPTR5.UINT8[HH]
-#define RSCAN0RMDF05 RSCAN0.RMDF05.UINT32
-#define RSCAN0RMDF05L RSCAN0.RMDF05.UINT16[L]
-#define RSCAN0RMDF05LL RSCAN0.RMDF05.UINT8[LL]
-#define RSCAN0RMDF05LH RSCAN0.RMDF05.UINT8[LH]
-#define RSCAN0RMDF05H RSCAN0.RMDF05.UINT16[H]
-#define RSCAN0RMDF05HL RSCAN0.RMDF05.UINT8[HL]
-#define RSCAN0RMDF05HH RSCAN0.RMDF05.UINT8[HH]
-#define RSCAN0RMDF15 RSCAN0.RMDF15.UINT32
-#define RSCAN0RMDF15L RSCAN0.RMDF15.UINT16[L]
-#define RSCAN0RMDF15LL RSCAN0.RMDF15.UINT8[LL]
-#define RSCAN0RMDF15LH RSCAN0.RMDF15.UINT8[LH]
-#define RSCAN0RMDF15H RSCAN0.RMDF15.UINT16[H]
-#define RSCAN0RMDF15HL RSCAN0.RMDF15.UINT8[HL]
-#define RSCAN0RMDF15HH RSCAN0.RMDF15.UINT8[HH]
-#define RSCAN0RMID6 RSCAN0.RMID6.UINT32
-#define RSCAN0RMID6L RSCAN0.RMID6.UINT16[L]
-#define RSCAN0RMID6LL RSCAN0.RMID6.UINT8[LL]
-#define RSCAN0RMID6LH RSCAN0.RMID6.UINT8[LH]
-#define RSCAN0RMID6H RSCAN0.RMID6.UINT16[H]
-#define RSCAN0RMID6HL RSCAN0.RMID6.UINT8[HL]
-#define RSCAN0RMID6HH RSCAN0.RMID6.UINT8[HH]
-#define RSCAN0RMPTR6 RSCAN0.RMPTR6.UINT32
-#define RSCAN0RMPTR6L RSCAN0.RMPTR6.UINT16[L]
-#define RSCAN0RMPTR6LL RSCAN0.RMPTR6.UINT8[LL]
-#define RSCAN0RMPTR6LH RSCAN0.RMPTR6.UINT8[LH]
-#define RSCAN0RMPTR6H RSCAN0.RMPTR6.UINT16[H]
-#define RSCAN0RMPTR6HL RSCAN0.RMPTR6.UINT8[HL]
-#define RSCAN0RMPTR6HH RSCAN0.RMPTR6.UINT8[HH]
-#define RSCAN0RMDF06 RSCAN0.RMDF06.UINT32
-#define RSCAN0RMDF06L RSCAN0.RMDF06.UINT16[L]
-#define RSCAN0RMDF06LL RSCAN0.RMDF06.UINT8[LL]
-#define RSCAN0RMDF06LH RSCAN0.RMDF06.UINT8[LH]
-#define RSCAN0RMDF06H RSCAN0.RMDF06.UINT16[H]
-#define RSCAN0RMDF06HL RSCAN0.RMDF06.UINT8[HL]
-#define RSCAN0RMDF06HH RSCAN0.RMDF06.UINT8[HH]
-#define RSCAN0RMDF16 RSCAN0.RMDF16.UINT32
-#define RSCAN0RMDF16L RSCAN0.RMDF16.UINT16[L]
-#define RSCAN0RMDF16LL RSCAN0.RMDF16.UINT8[LL]
-#define RSCAN0RMDF16LH RSCAN0.RMDF16.UINT8[LH]
-#define RSCAN0RMDF16H RSCAN0.RMDF16.UINT16[H]
-#define RSCAN0RMDF16HL RSCAN0.RMDF16.UINT8[HL]
-#define RSCAN0RMDF16HH RSCAN0.RMDF16.UINT8[HH]
-#define RSCAN0RMID7 RSCAN0.RMID7.UINT32
-#define RSCAN0RMID7L RSCAN0.RMID7.UINT16[L]
-#define RSCAN0RMID7LL RSCAN0.RMID7.UINT8[LL]
-#define RSCAN0RMID7LH RSCAN0.RMID7.UINT8[LH]
-#define RSCAN0RMID7H RSCAN0.RMID7.UINT16[H]
-#define RSCAN0RMID7HL RSCAN0.RMID7.UINT8[HL]
-#define RSCAN0RMID7HH RSCAN0.RMID7.UINT8[HH]
-#define RSCAN0RMPTR7 RSCAN0.RMPTR7.UINT32
-#define RSCAN0RMPTR7L RSCAN0.RMPTR7.UINT16[L]
-#define RSCAN0RMPTR7LL RSCAN0.RMPTR7.UINT8[LL]
-#define RSCAN0RMPTR7LH RSCAN0.RMPTR7.UINT8[LH]
-#define RSCAN0RMPTR7H RSCAN0.RMPTR7.UINT16[H]
-#define RSCAN0RMPTR7HL RSCAN0.RMPTR7.UINT8[HL]
-#define RSCAN0RMPTR7HH RSCAN0.RMPTR7.UINT8[HH]
-#define RSCAN0RMDF07 RSCAN0.RMDF07.UINT32
-#define RSCAN0RMDF07L RSCAN0.RMDF07.UINT16[L]
-#define RSCAN0RMDF07LL RSCAN0.RMDF07.UINT8[LL]
-#define RSCAN0RMDF07LH RSCAN0.RMDF07.UINT8[LH]
-#define RSCAN0RMDF07H RSCAN0.RMDF07.UINT16[H]
-#define RSCAN0RMDF07HL RSCAN0.RMDF07.UINT8[HL]
-#define RSCAN0RMDF07HH RSCAN0.RMDF07.UINT8[HH]
-#define RSCAN0RMDF17 RSCAN0.RMDF17.UINT32
-#define RSCAN0RMDF17L RSCAN0.RMDF17.UINT16[L]
-#define RSCAN0RMDF17LL RSCAN0.RMDF17.UINT8[LL]
-#define RSCAN0RMDF17LH RSCAN0.RMDF17.UINT8[LH]
-#define RSCAN0RMDF17H RSCAN0.RMDF17.UINT16[H]
-#define RSCAN0RMDF17HL RSCAN0.RMDF17.UINT8[HL]
-#define RSCAN0RMDF17HH RSCAN0.RMDF17.UINT8[HH]
-#define RSCAN0RMID8 RSCAN0.RMID8.UINT32
-#define RSCAN0RMID8L RSCAN0.RMID8.UINT16[L]
-#define RSCAN0RMID8LL RSCAN0.RMID8.UINT8[LL]
-#define RSCAN0RMID8LH RSCAN0.RMID8.UINT8[LH]
-#define RSCAN0RMID8H RSCAN0.RMID8.UINT16[H]
-#define RSCAN0RMID8HL RSCAN0.RMID8.UINT8[HL]
-#define RSCAN0RMID8HH RSCAN0.RMID8.UINT8[HH]
-#define RSCAN0RMPTR8 RSCAN0.RMPTR8.UINT32
-#define RSCAN0RMPTR8L RSCAN0.RMPTR8.UINT16[L]
-#define RSCAN0RMPTR8LL RSCAN0.RMPTR8.UINT8[LL]
-#define RSCAN0RMPTR8LH RSCAN0.RMPTR8.UINT8[LH]
-#define RSCAN0RMPTR8H RSCAN0.RMPTR8.UINT16[H]
-#define RSCAN0RMPTR8HL RSCAN0.RMPTR8.UINT8[HL]
-#define RSCAN0RMPTR8HH RSCAN0.RMPTR8.UINT8[HH]
-#define RSCAN0RMDF08 RSCAN0.RMDF08.UINT32
-#define RSCAN0RMDF08L RSCAN0.RMDF08.UINT16[L]
-#define RSCAN0RMDF08LL RSCAN0.RMDF08.UINT8[LL]
-#define RSCAN0RMDF08LH RSCAN0.RMDF08.UINT8[LH]
-#define RSCAN0RMDF08H RSCAN0.RMDF08.UINT16[H]
-#define RSCAN0RMDF08HL RSCAN0.RMDF08.UINT8[HL]
-#define RSCAN0RMDF08HH RSCAN0.RMDF08.UINT8[HH]
-#define RSCAN0RMDF18 RSCAN0.RMDF18.UINT32
-#define RSCAN0RMDF18L RSCAN0.RMDF18.UINT16[L]
-#define RSCAN0RMDF18LL RSCAN0.RMDF18.UINT8[LL]
-#define RSCAN0RMDF18LH RSCAN0.RMDF18.UINT8[LH]
-#define RSCAN0RMDF18H RSCAN0.RMDF18.UINT16[H]
-#define RSCAN0RMDF18HL RSCAN0.RMDF18.UINT8[HL]
-#define RSCAN0RMDF18HH RSCAN0.RMDF18.UINT8[HH]
-#define RSCAN0RMID9 RSCAN0.RMID9.UINT32
-#define RSCAN0RMID9L RSCAN0.RMID9.UINT16[L]
-#define RSCAN0RMID9LL RSCAN0.RMID9.UINT8[LL]
-#define RSCAN0RMID9LH RSCAN0.RMID9.UINT8[LH]
-#define RSCAN0RMID9H RSCAN0.RMID9.UINT16[H]
-#define RSCAN0RMID9HL RSCAN0.RMID9.UINT8[HL]
-#define RSCAN0RMID9HH RSCAN0.RMID9.UINT8[HH]
-#define RSCAN0RMPTR9 RSCAN0.RMPTR9.UINT32
-#define RSCAN0RMPTR9L RSCAN0.RMPTR9.UINT16[L]
-#define RSCAN0RMPTR9LL RSCAN0.RMPTR9.UINT8[LL]
-#define RSCAN0RMPTR9LH RSCAN0.RMPTR9.UINT8[LH]
-#define RSCAN0RMPTR9H RSCAN0.RMPTR9.UINT16[H]
-#define RSCAN0RMPTR9HL RSCAN0.RMPTR9.UINT8[HL]
-#define RSCAN0RMPTR9HH RSCAN0.RMPTR9.UINT8[HH]
-#define RSCAN0RMDF09 RSCAN0.RMDF09.UINT32
-#define RSCAN0RMDF09L RSCAN0.RMDF09.UINT16[L]
-#define RSCAN0RMDF09LL RSCAN0.RMDF09.UINT8[LL]
-#define RSCAN0RMDF09LH RSCAN0.RMDF09.UINT8[LH]
-#define RSCAN0RMDF09H RSCAN0.RMDF09.UINT16[H]
-#define RSCAN0RMDF09HL RSCAN0.RMDF09.UINT8[HL]
-#define RSCAN0RMDF09HH RSCAN0.RMDF09.UINT8[HH]
-#define RSCAN0RMDF19 RSCAN0.RMDF19.UINT32
-#define RSCAN0RMDF19L RSCAN0.RMDF19.UINT16[L]
-#define RSCAN0RMDF19LL RSCAN0.RMDF19.UINT8[LL]
-#define RSCAN0RMDF19LH RSCAN0.RMDF19.UINT8[LH]
-#define RSCAN0RMDF19H RSCAN0.RMDF19.UINT16[H]
-#define RSCAN0RMDF19HL RSCAN0.RMDF19.UINT8[HL]
-#define RSCAN0RMDF19HH RSCAN0.RMDF19.UINT8[HH]
-#define RSCAN0RMID10 RSCAN0.RMID10.UINT32
-#define RSCAN0RMID10L RSCAN0.RMID10.UINT16[L]
-#define RSCAN0RMID10LL RSCAN0.RMID10.UINT8[LL]
-#define RSCAN0RMID10LH RSCAN0.RMID10.UINT8[LH]
-#define RSCAN0RMID10H RSCAN0.RMID10.UINT16[H]
-#define RSCAN0RMID10HL RSCAN0.RMID10.UINT8[HL]
-#define RSCAN0RMID10HH RSCAN0.RMID10.UINT8[HH]
-#define RSCAN0RMPTR10 RSCAN0.RMPTR10.UINT32
-#define RSCAN0RMPTR10L RSCAN0.RMPTR10.UINT16[L]
-#define RSCAN0RMPTR10LL RSCAN0.RMPTR10.UINT8[LL]
-#define RSCAN0RMPTR10LH RSCAN0.RMPTR10.UINT8[LH]
-#define RSCAN0RMPTR10H RSCAN0.RMPTR10.UINT16[H]
-#define RSCAN0RMPTR10HL RSCAN0.RMPTR10.UINT8[HL]
-#define RSCAN0RMPTR10HH RSCAN0.RMPTR10.UINT8[HH]
-#define RSCAN0RMDF010 RSCAN0.RMDF010.UINT32
-#define RSCAN0RMDF010L RSCAN0.RMDF010.UINT16[L]
-#define RSCAN0RMDF010LL RSCAN0.RMDF010.UINT8[LL]
-#define RSCAN0RMDF010LH RSCAN0.RMDF010.UINT8[LH]
-#define RSCAN0RMDF010H RSCAN0.RMDF010.UINT16[H]
-#define RSCAN0RMDF010HL RSCAN0.RMDF010.UINT8[HL]
-#define RSCAN0RMDF010HH RSCAN0.RMDF010.UINT8[HH]
-#define RSCAN0RMDF110 RSCAN0.RMDF110.UINT32
-#define RSCAN0RMDF110L RSCAN0.RMDF110.UINT16[L]
-#define RSCAN0RMDF110LL RSCAN0.RMDF110.UINT8[LL]
-#define RSCAN0RMDF110LH RSCAN0.RMDF110.UINT8[LH]
-#define RSCAN0RMDF110H RSCAN0.RMDF110.UINT16[H]
-#define RSCAN0RMDF110HL RSCAN0.RMDF110.UINT8[HL]
-#define RSCAN0RMDF110HH RSCAN0.RMDF110.UINT8[HH]
-#define RSCAN0RMID11 RSCAN0.RMID11.UINT32
-#define RSCAN0RMID11L RSCAN0.RMID11.UINT16[L]
-#define RSCAN0RMID11LL RSCAN0.RMID11.UINT8[LL]
-#define RSCAN0RMID11LH RSCAN0.RMID11.UINT8[LH]
-#define RSCAN0RMID11H RSCAN0.RMID11.UINT16[H]
-#define RSCAN0RMID11HL RSCAN0.RMID11.UINT8[HL]
-#define RSCAN0RMID11HH RSCAN0.RMID11.UINT8[HH]
-#define RSCAN0RMPTR11 RSCAN0.RMPTR11.UINT32
-#define RSCAN0RMPTR11L RSCAN0.RMPTR11.UINT16[L]
-#define RSCAN0RMPTR11LL RSCAN0.RMPTR11.UINT8[LL]
-#define RSCAN0RMPTR11LH RSCAN0.RMPTR11.UINT8[LH]
-#define RSCAN0RMPTR11H RSCAN0.RMPTR11.UINT16[H]
-#define RSCAN0RMPTR11HL RSCAN0.RMPTR11.UINT8[HL]
-#define RSCAN0RMPTR11HH RSCAN0.RMPTR11.UINT8[HH]
-#define RSCAN0RMDF011 RSCAN0.RMDF011.UINT32
-#define RSCAN0RMDF011L RSCAN0.RMDF011.UINT16[L]
-#define RSCAN0RMDF011LL RSCAN0.RMDF011.UINT8[LL]
-#define RSCAN0RMDF011LH RSCAN0.RMDF011.UINT8[LH]
-#define RSCAN0RMDF011H RSCAN0.RMDF011.UINT16[H]
-#define RSCAN0RMDF011HL RSCAN0.RMDF011.UINT8[HL]
-#define RSCAN0RMDF011HH RSCAN0.RMDF011.UINT8[HH]
-#define RSCAN0RMDF111 RSCAN0.RMDF111.UINT32
-#define RSCAN0RMDF111L RSCAN0.RMDF111.UINT16[L]
-#define RSCAN0RMDF111LL RSCAN0.RMDF111.UINT8[LL]
-#define RSCAN0RMDF111LH RSCAN0.RMDF111.UINT8[LH]
-#define RSCAN0RMDF111H RSCAN0.RMDF111.UINT16[H]
-#define RSCAN0RMDF111HL RSCAN0.RMDF111.UINT8[HL]
-#define RSCAN0RMDF111HH RSCAN0.RMDF111.UINT8[HH]
-#define RSCAN0RMID12 RSCAN0.RMID12.UINT32
-#define RSCAN0RMID12L RSCAN0.RMID12.UINT16[L]
-#define RSCAN0RMID12LL RSCAN0.RMID12.UINT8[LL]
-#define RSCAN0RMID12LH RSCAN0.RMID12.UINT8[LH]
-#define RSCAN0RMID12H RSCAN0.RMID12.UINT16[H]
-#define RSCAN0RMID12HL RSCAN0.RMID12.UINT8[HL]
-#define RSCAN0RMID12HH RSCAN0.RMID12.UINT8[HH]
-#define RSCAN0RMPTR12 RSCAN0.RMPTR12.UINT32
-#define RSCAN0RMPTR12L RSCAN0.RMPTR12.UINT16[L]
-#define RSCAN0RMPTR12LL RSCAN0.RMPTR12.UINT8[LL]
-#define RSCAN0RMPTR12LH RSCAN0.RMPTR12.UINT8[LH]
-#define RSCAN0RMPTR12H RSCAN0.RMPTR12.UINT16[H]
-#define RSCAN0RMPTR12HL RSCAN0.RMPTR12.UINT8[HL]
-#define RSCAN0RMPTR12HH RSCAN0.RMPTR12.UINT8[HH]
-#define RSCAN0RMDF012 RSCAN0.RMDF012.UINT32
-#define RSCAN0RMDF012L RSCAN0.RMDF012.UINT16[L]
-#define RSCAN0RMDF012LL RSCAN0.RMDF012.UINT8[LL]
-#define RSCAN0RMDF012LH RSCAN0.RMDF012.UINT8[LH]
-#define RSCAN0RMDF012H RSCAN0.RMDF012.UINT16[H]
-#define RSCAN0RMDF012HL RSCAN0.RMDF012.UINT8[HL]
-#define RSCAN0RMDF012HH RSCAN0.RMDF012.UINT8[HH]
-#define RSCAN0RMDF112 RSCAN0.RMDF112.UINT32
-#define RSCAN0RMDF112L RSCAN0.RMDF112.UINT16[L]
-#define RSCAN0RMDF112LL RSCAN0.RMDF112.UINT8[LL]
-#define RSCAN0RMDF112LH RSCAN0.RMDF112.UINT8[LH]
-#define RSCAN0RMDF112H RSCAN0.RMDF112.UINT16[H]
-#define RSCAN0RMDF112HL RSCAN0.RMDF112.UINT8[HL]
-#define RSCAN0RMDF112HH RSCAN0.RMDF112.UINT8[HH]
-#define RSCAN0RMID13 RSCAN0.RMID13.UINT32
-#define RSCAN0RMID13L RSCAN0.RMID13.UINT16[L]
-#define RSCAN0RMID13LL RSCAN0.RMID13.UINT8[LL]
-#define RSCAN0RMID13LH RSCAN0.RMID13.UINT8[LH]
-#define RSCAN0RMID13H RSCAN0.RMID13.UINT16[H]
-#define RSCAN0RMID13HL RSCAN0.RMID13.UINT8[HL]
-#define RSCAN0RMID13HH RSCAN0.RMID13.UINT8[HH]
-#define RSCAN0RMPTR13 RSCAN0.RMPTR13.UINT32
-#define RSCAN0RMPTR13L RSCAN0.RMPTR13.UINT16[L]
-#define RSCAN0RMPTR13LL RSCAN0.RMPTR13.UINT8[LL]
-#define RSCAN0RMPTR13LH RSCAN0.RMPTR13.UINT8[LH]
-#define RSCAN0RMPTR13H RSCAN0.RMPTR13.UINT16[H]
-#define RSCAN0RMPTR13HL RSCAN0.RMPTR13.UINT8[HL]
-#define RSCAN0RMPTR13HH RSCAN0.RMPTR13.UINT8[HH]
-#define RSCAN0RMDF013 RSCAN0.RMDF013.UINT32
-#define RSCAN0RMDF013L RSCAN0.RMDF013.UINT16[L]
-#define RSCAN0RMDF013LL RSCAN0.RMDF013.UINT8[LL]
-#define RSCAN0RMDF013LH RSCAN0.RMDF013.UINT8[LH]
-#define RSCAN0RMDF013H RSCAN0.RMDF013.UINT16[H]
-#define RSCAN0RMDF013HL RSCAN0.RMDF013.UINT8[HL]
-#define RSCAN0RMDF013HH RSCAN0.RMDF013.UINT8[HH]
-#define RSCAN0RMDF113 RSCAN0.RMDF113.UINT32
-#define RSCAN0RMDF113L RSCAN0.RMDF113.UINT16[L]
-#define RSCAN0RMDF113LL RSCAN0.RMDF113.UINT8[LL]
-#define RSCAN0RMDF113LH RSCAN0.RMDF113.UINT8[LH]
-#define RSCAN0RMDF113H RSCAN0.RMDF113.UINT16[H]
-#define RSCAN0RMDF113HL RSCAN0.RMDF113.UINT8[HL]
-#define RSCAN0RMDF113HH RSCAN0.RMDF113.UINT8[HH]
-#define RSCAN0RMID14 RSCAN0.RMID14.UINT32
-#define RSCAN0RMID14L RSCAN0.RMID14.UINT16[L]
-#define RSCAN0RMID14LL RSCAN0.RMID14.UINT8[LL]
-#define RSCAN0RMID14LH RSCAN0.RMID14.UINT8[LH]
-#define RSCAN0RMID14H RSCAN0.RMID14.UINT16[H]
-#define RSCAN0RMID14HL RSCAN0.RMID14.UINT8[HL]
-#define RSCAN0RMID14HH RSCAN0.RMID14.UINT8[HH]
-#define RSCAN0RMPTR14 RSCAN0.RMPTR14.UINT32
-#define RSCAN0RMPTR14L RSCAN0.RMPTR14.UINT16[L]
-#define RSCAN0RMPTR14LL RSCAN0.RMPTR14.UINT8[LL]
-#define RSCAN0RMPTR14LH RSCAN0.RMPTR14.UINT8[LH]
-#define RSCAN0RMPTR14H RSCAN0.RMPTR14.UINT16[H]
-#define RSCAN0RMPTR14HL RSCAN0.RMPTR14.UINT8[HL]
-#define RSCAN0RMPTR14HH RSCAN0.RMPTR14.UINT8[HH]
-#define RSCAN0RMDF014 RSCAN0.RMDF014.UINT32
-#define RSCAN0RMDF014L RSCAN0.RMDF014.UINT16[L]
-#define RSCAN0RMDF014LL RSCAN0.RMDF014.UINT8[LL]
-#define RSCAN0RMDF014LH RSCAN0.RMDF014.UINT8[LH]
-#define RSCAN0RMDF014H RSCAN0.RMDF014.UINT16[H]
-#define RSCAN0RMDF014HL RSCAN0.RMDF014.UINT8[HL]
-#define RSCAN0RMDF014HH RSCAN0.RMDF014.UINT8[HH]
-#define RSCAN0RMDF114 RSCAN0.RMDF114.UINT32
-#define RSCAN0RMDF114L RSCAN0.RMDF114.UINT16[L]
-#define RSCAN0RMDF114LL RSCAN0.RMDF114.UINT8[LL]
-#define RSCAN0RMDF114LH RSCAN0.RMDF114.UINT8[LH]
-#define RSCAN0RMDF114H RSCAN0.RMDF114.UINT16[H]
-#define RSCAN0RMDF114HL RSCAN0.RMDF114.UINT8[HL]
-#define RSCAN0RMDF114HH RSCAN0.RMDF114.UINT8[HH]
-#define RSCAN0RMID15 RSCAN0.RMID15.UINT32
-#define RSCAN0RMID15L RSCAN0.RMID15.UINT16[L]
-#define RSCAN0RMID15LL RSCAN0.RMID15.UINT8[LL]
-#define RSCAN0RMID15LH RSCAN0.RMID15.UINT8[LH]
-#define RSCAN0RMID15H RSCAN0.RMID15.UINT16[H]
-#define RSCAN0RMID15HL RSCAN0.RMID15.UINT8[HL]
-#define RSCAN0RMID15HH RSCAN0.RMID15.UINT8[HH]
-#define RSCAN0RMPTR15 RSCAN0.RMPTR15.UINT32
-#define RSCAN0RMPTR15L RSCAN0.RMPTR15.UINT16[L]
-#define RSCAN0RMPTR15LL RSCAN0.RMPTR15.UINT8[LL]
-#define RSCAN0RMPTR15LH RSCAN0.RMPTR15.UINT8[LH]
-#define RSCAN0RMPTR15H RSCAN0.RMPTR15.UINT16[H]
-#define RSCAN0RMPTR15HL RSCAN0.RMPTR15.UINT8[HL]
-#define RSCAN0RMPTR15HH RSCAN0.RMPTR15.UINT8[HH]
-#define RSCAN0RMDF015 RSCAN0.RMDF015.UINT32
-#define RSCAN0RMDF015L RSCAN0.RMDF015.UINT16[L]
-#define RSCAN0RMDF015LL RSCAN0.RMDF015.UINT8[LL]
-#define RSCAN0RMDF015LH RSCAN0.RMDF015.UINT8[LH]
-#define RSCAN0RMDF015H RSCAN0.RMDF015.UINT16[H]
-#define RSCAN0RMDF015HL RSCAN0.RMDF015.UINT8[HL]
-#define RSCAN0RMDF015HH RSCAN0.RMDF015.UINT8[HH]
-#define RSCAN0RMDF115 RSCAN0.RMDF115.UINT32
-#define RSCAN0RMDF115L RSCAN0.RMDF115.UINT16[L]
-#define RSCAN0RMDF115LL RSCAN0.RMDF115.UINT8[LL]
-#define RSCAN0RMDF115LH RSCAN0.RMDF115.UINT8[LH]
-#define RSCAN0RMDF115H RSCAN0.RMDF115.UINT16[H]
-#define RSCAN0RMDF115HL RSCAN0.RMDF115.UINT8[HL]
-#define RSCAN0RMDF115HH RSCAN0.RMDF115.UINT8[HH]
-#define RSCAN0RMID16 RSCAN0.RMID16.UINT32
-#define RSCAN0RMID16L RSCAN0.RMID16.UINT16[L]
-#define RSCAN0RMID16LL RSCAN0.RMID16.UINT8[LL]
-#define RSCAN0RMID16LH RSCAN0.RMID16.UINT8[LH]
-#define RSCAN0RMID16H RSCAN0.RMID16.UINT16[H]
-#define RSCAN0RMID16HL RSCAN0.RMID16.UINT8[HL]
-#define RSCAN0RMID16HH RSCAN0.RMID16.UINT8[HH]
-#define RSCAN0RMPTR16 RSCAN0.RMPTR16.UINT32
-#define RSCAN0RMPTR16L RSCAN0.RMPTR16.UINT16[L]
-#define RSCAN0RMPTR16LL RSCAN0.RMPTR16.UINT8[LL]
-#define RSCAN0RMPTR16LH RSCAN0.RMPTR16.UINT8[LH]
-#define RSCAN0RMPTR16H RSCAN0.RMPTR16.UINT16[H]
-#define RSCAN0RMPTR16HL RSCAN0.RMPTR16.UINT8[HL]
-#define RSCAN0RMPTR16HH RSCAN0.RMPTR16.UINT8[HH]
-#define RSCAN0RMDF016 RSCAN0.RMDF016.UINT32
-#define RSCAN0RMDF016L RSCAN0.RMDF016.UINT16[L]
-#define RSCAN0RMDF016LL RSCAN0.RMDF016.UINT8[LL]
-#define RSCAN0RMDF016LH RSCAN0.RMDF016.UINT8[LH]
-#define RSCAN0RMDF016H RSCAN0.RMDF016.UINT16[H]
-#define RSCAN0RMDF016HL RSCAN0.RMDF016.UINT8[HL]
-#define RSCAN0RMDF016HH RSCAN0.RMDF016.UINT8[HH]
-#define RSCAN0RMDF116 RSCAN0.RMDF116.UINT32
-#define RSCAN0RMDF116L RSCAN0.RMDF116.UINT16[L]
-#define RSCAN0RMDF116LL RSCAN0.RMDF116.UINT8[LL]
-#define RSCAN0RMDF116LH RSCAN0.RMDF116.UINT8[LH]
-#define RSCAN0RMDF116H RSCAN0.RMDF116.UINT16[H]
-#define RSCAN0RMDF116HL RSCAN0.RMDF116.UINT8[HL]
-#define RSCAN0RMDF116HH RSCAN0.RMDF116.UINT8[HH]
-#define RSCAN0RMID17 RSCAN0.RMID17.UINT32
-#define RSCAN0RMID17L RSCAN0.RMID17.UINT16[L]
-#define RSCAN0RMID17LL RSCAN0.RMID17.UINT8[LL]
-#define RSCAN0RMID17LH RSCAN0.RMID17.UINT8[LH]
-#define RSCAN0RMID17H RSCAN0.RMID17.UINT16[H]
-#define RSCAN0RMID17HL RSCAN0.RMID17.UINT8[HL]
-#define RSCAN0RMID17HH RSCAN0.RMID17.UINT8[HH]
-#define RSCAN0RMPTR17 RSCAN0.RMPTR17.UINT32
-#define RSCAN0RMPTR17L RSCAN0.RMPTR17.UINT16[L]
-#define RSCAN0RMPTR17LL RSCAN0.RMPTR17.UINT8[LL]
-#define RSCAN0RMPTR17LH RSCAN0.RMPTR17.UINT8[LH]
-#define RSCAN0RMPTR17H RSCAN0.RMPTR17.UINT16[H]
-#define RSCAN0RMPTR17HL RSCAN0.RMPTR17.UINT8[HL]
-#define RSCAN0RMPTR17HH RSCAN0.RMPTR17.UINT8[HH]
-#define RSCAN0RMDF017 RSCAN0.RMDF017.UINT32
-#define RSCAN0RMDF017L RSCAN0.RMDF017.UINT16[L]
-#define RSCAN0RMDF017LL RSCAN0.RMDF017.UINT8[LL]
-#define RSCAN0RMDF017LH RSCAN0.RMDF017.UINT8[LH]
-#define RSCAN0RMDF017H RSCAN0.RMDF017.UINT16[H]
-#define RSCAN0RMDF017HL RSCAN0.RMDF017.UINT8[HL]
-#define RSCAN0RMDF017HH RSCAN0.RMDF017.UINT8[HH]
-#define RSCAN0RMDF117 RSCAN0.RMDF117.UINT32
-#define RSCAN0RMDF117L RSCAN0.RMDF117.UINT16[L]
-#define RSCAN0RMDF117LL RSCAN0.RMDF117.UINT8[LL]
-#define RSCAN0RMDF117LH RSCAN0.RMDF117.UINT8[LH]
-#define RSCAN0RMDF117H RSCAN0.RMDF117.UINT16[H]
-#define RSCAN0RMDF117HL RSCAN0.RMDF117.UINT8[HL]
-#define RSCAN0RMDF117HH RSCAN0.RMDF117.UINT8[HH]
-#define RSCAN0RMID18 RSCAN0.RMID18.UINT32
-#define RSCAN0RMID18L RSCAN0.RMID18.UINT16[L]
-#define RSCAN0RMID18LL RSCAN0.RMID18.UINT8[LL]
-#define RSCAN0RMID18LH RSCAN0.RMID18.UINT8[LH]
-#define RSCAN0RMID18H RSCAN0.RMID18.UINT16[H]
-#define RSCAN0RMID18HL RSCAN0.RMID18.UINT8[HL]
-#define RSCAN0RMID18HH RSCAN0.RMID18.UINT8[HH]
-#define RSCAN0RMPTR18 RSCAN0.RMPTR18.UINT32
-#define RSCAN0RMPTR18L RSCAN0.RMPTR18.UINT16[L]
-#define RSCAN0RMPTR18LL RSCAN0.RMPTR18.UINT8[LL]
-#define RSCAN0RMPTR18LH RSCAN0.RMPTR18.UINT8[LH]
-#define RSCAN0RMPTR18H RSCAN0.RMPTR18.UINT16[H]
-#define RSCAN0RMPTR18HL RSCAN0.RMPTR18.UINT8[HL]
-#define RSCAN0RMPTR18HH RSCAN0.RMPTR18.UINT8[HH]
-#define RSCAN0RMDF018 RSCAN0.RMDF018.UINT32
-#define RSCAN0RMDF018L RSCAN0.RMDF018.UINT16[L]
-#define RSCAN0RMDF018LL RSCAN0.RMDF018.UINT8[LL]
-#define RSCAN0RMDF018LH RSCAN0.RMDF018.UINT8[LH]
-#define RSCAN0RMDF018H RSCAN0.RMDF018.UINT16[H]
-#define RSCAN0RMDF018HL RSCAN0.RMDF018.UINT8[HL]
-#define RSCAN0RMDF018HH RSCAN0.RMDF018.UINT8[HH]
-#define RSCAN0RMDF118 RSCAN0.RMDF118.UINT32
-#define RSCAN0RMDF118L RSCAN0.RMDF118.UINT16[L]
-#define RSCAN0RMDF118LL RSCAN0.RMDF118.UINT8[LL]
-#define RSCAN0RMDF118LH RSCAN0.RMDF118.UINT8[LH]
-#define RSCAN0RMDF118H RSCAN0.RMDF118.UINT16[H]
-#define RSCAN0RMDF118HL RSCAN0.RMDF118.UINT8[HL]
-#define RSCAN0RMDF118HH RSCAN0.RMDF118.UINT8[HH]
-#define RSCAN0RMID19 RSCAN0.RMID19.UINT32
-#define RSCAN0RMID19L RSCAN0.RMID19.UINT16[L]
-#define RSCAN0RMID19LL RSCAN0.RMID19.UINT8[LL]
-#define RSCAN0RMID19LH RSCAN0.RMID19.UINT8[LH]
-#define RSCAN0RMID19H RSCAN0.RMID19.UINT16[H]
-#define RSCAN0RMID19HL RSCAN0.RMID19.UINT8[HL]
-#define RSCAN0RMID19HH RSCAN0.RMID19.UINT8[HH]
-#define RSCAN0RMPTR19 RSCAN0.RMPTR19.UINT32
-#define RSCAN0RMPTR19L RSCAN0.RMPTR19.UINT16[L]
-#define RSCAN0RMPTR19LL RSCAN0.RMPTR19.UINT8[LL]
-#define RSCAN0RMPTR19LH RSCAN0.RMPTR19.UINT8[LH]
-#define RSCAN0RMPTR19H RSCAN0.RMPTR19.UINT16[H]
-#define RSCAN0RMPTR19HL RSCAN0.RMPTR19.UINT8[HL]
-#define RSCAN0RMPTR19HH RSCAN0.RMPTR19.UINT8[HH]
-#define RSCAN0RMDF019 RSCAN0.RMDF019.UINT32
-#define RSCAN0RMDF019L RSCAN0.RMDF019.UINT16[L]
-#define RSCAN0RMDF019LL RSCAN0.RMDF019.UINT8[LL]
-#define RSCAN0RMDF019LH RSCAN0.RMDF019.UINT8[LH]
-#define RSCAN0RMDF019H RSCAN0.RMDF019.UINT16[H]
-#define RSCAN0RMDF019HL RSCAN0.RMDF019.UINT8[HL]
-#define RSCAN0RMDF019HH RSCAN0.RMDF019.UINT8[HH]
-#define RSCAN0RMDF119 RSCAN0.RMDF119.UINT32
-#define RSCAN0RMDF119L RSCAN0.RMDF119.UINT16[L]
-#define RSCAN0RMDF119LL RSCAN0.RMDF119.UINT8[LL]
-#define RSCAN0RMDF119LH RSCAN0.RMDF119.UINT8[LH]
-#define RSCAN0RMDF119H RSCAN0.RMDF119.UINT16[H]
-#define RSCAN0RMDF119HL RSCAN0.RMDF119.UINT8[HL]
-#define RSCAN0RMDF119HH RSCAN0.RMDF119.UINT8[HH]
-#define RSCAN0RMID20 RSCAN0.RMID20.UINT32
-#define RSCAN0RMID20L RSCAN0.RMID20.UINT16[L]
-#define RSCAN0RMID20LL RSCAN0.RMID20.UINT8[LL]
-#define RSCAN0RMID20LH RSCAN0.RMID20.UINT8[LH]
-#define RSCAN0RMID20H RSCAN0.RMID20.UINT16[H]
-#define RSCAN0RMID20HL RSCAN0.RMID20.UINT8[HL]
-#define RSCAN0RMID20HH RSCAN0.RMID20.UINT8[HH]
-#define RSCAN0RMPTR20 RSCAN0.RMPTR20.UINT32
-#define RSCAN0RMPTR20L RSCAN0.RMPTR20.UINT16[L]
-#define RSCAN0RMPTR20LL RSCAN0.RMPTR20.UINT8[LL]
-#define RSCAN0RMPTR20LH RSCAN0.RMPTR20.UINT8[LH]
-#define RSCAN0RMPTR20H RSCAN0.RMPTR20.UINT16[H]
-#define RSCAN0RMPTR20HL RSCAN0.RMPTR20.UINT8[HL]
-#define RSCAN0RMPTR20HH RSCAN0.RMPTR20.UINT8[HH]
-#define RSCAN0RMDF020 RSCAN0.RMDF020.UINT32
-#define RSCAN0RMDF020L RSCAN0.RMDF020.UINT16[L]
-#define RSCAN0RMDF020LL RSCAN0.RMDF020.UINT8[LL]
-#define RSCAN0RMDF020LH RSCAN0.RMDF020.UINT8[LH]
-#define RSCAN0RMDF020H RSCAN0.RMDF020.UINT16[H]
-#define RSCAN0RMDF020HL RSCAN0.RMDF020.UINT8[HL]
-#define RSCAN0RMDF020HH RSCAN0.RMDF020.UINT8[HH]
-#define RSCAN0RMDF120 RSCAN0.RMDF120.UINT32
-#define RSCAN0RMDF120L RSCAN0.RMDF120.UINT16[L]
-#define RSCAN0RMDF120LL RSCAN0.RMDF120.UINT8[LL]
-#define RSCAN0RMDF120LH RSCAN0.RMDF120.UINT8[LH]
-#define RSCAN0RMDF120H RSCAN0.RMDF120.UINT16[H]
-#define RSCAN0RMDF120HL RSCAN0.RMDF120.UINT8[HL]
-#define RSCAN0RMDF120HH RSCAN0.RMDF120.UINT8[HH]
-#define RSCAN0RMID21 RSCAN0.RMID21.UINT32
-#define RSCAN0RMID21L RSCAN0.RMID21.UINT16[L]
-#define RSCAN0RMID21LL RSCAN0.RMID21.UINT8[LL]
-#define RSCAN0RMID21LH RSCAN0.RMID21.UINT8[LH]
-#define RSCAN0RMID21H RSCAN0.RMID21.UINT16[H]
-#define RSCAN0RMID21HL RSCAN0.RMID21.UINT8[HL]
-#define RSCAN0RMID21HH RSCAN0.RMID21.UINT8[HH]
-#define RSCAN0RMPTR21 RSCAN0.RMPTR21.UINT32
-#define RSCAN0RMPTR21L RSCAN0.RMPTR21.UINT16[L]
-#define RSCAN0RMPTR21LL RSCAN0.RMPTR21.UINT8[LL]
-#define RSCAN0RMPTR21LH RSCAN0.RMPTR21.UINT8[LH]
-#define RSCAN0RMPTR21H RSCAN0.RMPTR21.UINT16[H]
-#define RSCAN0RMPTR21HL RSCAN0.RMPTR21.UINT8[HL]
-#define RSCAN0RMPTR21HH RSCAN0.RMPTR21.UINT8[HH]
-#define RSCAN0RMDF021 RSCAN0.RMDF021.UINT32
-#define RSCAN0RMDF021L RSCAN0.RMDF021.UINT16[L]
-#define RSCAN0RMDF021LL RSCAN0.RMDF021.UINT8[LL]
-#define RSCAN0RMDF021LH RSCAN0.RMDF021.UINT8[LH]
-#define RSCAN0RMDF021H RSCAN0.RMDF021.UINT16[H]
-#define RSCAN0RMDF021HL RSCAN0.RMDF021.UINT8[HL]
-#define RSCAN0RMDF021HH RSCAN0.RMDF021.UINT8[HH]
-#define RSCAN0RMDF121 RSCAN0.RMDF121.UINT32
-#define RSCAN0RMDF121L RSCAN0.RMDF121.UINT16[L]
-#define RSCAN0RMDF121LL RSCAN0.RMDF121.UINT8[LL]
-#define RSCAN0RMDF121LH RSCAN0.RMDF121.UINT8[LH]
-#define RSCAN0RMDF121H RSCAN0.RMDF121.UINT16[H]
-#define RSCAN0RMDF121HL RSCAN0.RMDF121.UINT8[HL]
-#define RSCAN0RMDF121HH RSCAN0.RMDF121.UINT8[HH]
-#define RSCAN0RMID22 RSCAN0.RMID22.UINT32
-#define RSCAN0RMID22L RSCAN0.RMID22.UINT16[L]
-#define RSCAN0RMID22LL RSCAN0.RMID22.UINT8[LL]
-#define RSCAN0RMID22LH RSCAN0.RMID22.UINT8[LH]
-#define RSCAN0RMID22H RSCAN0.RMID22.UINT16[H]
-#define RSCAN0RMID22HL RSCAN0.RMID22.UINT8[HL]
-#define RSCAN0RMID22HH RSCAN0.RMID22.UINT8[HH]
-#define RSCAN0RMPTR22 RSCAN0.RMPTR22.UINT32
-#define RSCAN0RMPTR22L RSCAN0.RMPTR22.UINT16[L]
-#define RSCAN0RMPTR22LL RSCAN0.RMPTR22.UINT8[LL]
-#define RSCAN0RMPTR22LH RSCAN0.RMPTR22.UINT8[LH]
-#define RSCAN0RMPTR22H RSCAN0.RMPTR22.UINT16[H]
-#define RSCAN0RMPTR22HL RSCAN0.RMPTR22.UINT8[HL]
-#define RSCAN0RMPTR22HH RSCAN0.RMPTR22.UINT8[HH]
-#define RSCAN0RMDF022 RSCAN0.RMDF022.UINT32
-#define RSCAN0RMDF022L RSCAN0.RMDF022.UINT16[L]
-#define RSCAN0RMDF022LL RSCAN0.RMDF022.UINT8[LL]
-#define RSCAN0RMDF022LH RSCAN0.RMDF022.UINT8[LH]
-#define RSCAN0RMDF022H RSCAN0.RMDF022.UINT16[H]
-#define RSCAN0RMDF022HL RSCAN0.RMDF022.UINT8[HL]
-#define RSCAN0RMDF022HH RSCAN0.RMDF022.UINT8[HH]
-#define RSCAN0RMDF122 RSCAN0.RMDF122.UINT32
-#define RSCAN0RMDF122L RSCAN0.RMDF122.UINT16[L]
-#define RSCAN0RMDF122LL RSCAN0.RMDF122.UINT8[LL]
-#define RSCAN0RMDF122LH RSCAN0.RMDF122.UINT8[LH]
-#define RSCAN0RMDF122H RSCAN0.RMDF122.UINT16[H]
-#define RSCAN0RMDF122HL RSCAN0.RMDF122.UINT8[HL]
-#define RSCAN0RMDF122HH RSCAN0.RMDF122.UINT8[HH]
-#define RSCAN0RMID23 RSCAN0.RMID23.UINT32
-#define RSCAN0RMID23L RSCAN0.RMID23.UINT16[L]
-#define RSCAN0RMID23LL RSCAN0.RMID23.UINT8[LL]
-#define RSCAN0RMID23LH RSCAN0.RMID23.UINT8[LH]
-#define RSCAN0RMID23H RSCAN0.RMID23.UINT16[H]
-#define RSCAN0RMID23HL RSCAN0.RMID23.UINT8[HL]
-#define RSCAN0RMID23HH RSCAN0.RMID23.UINT8[HH]
-#define RSCAN0RMPTR23 RSCAN0.RMPTR23.UINT32
-#define RSCAN0RMPTR23L RSCAN0.RMPTR23.UINT16[L]
-#define RSCAN0RMPTR23LL RSCAN0.RMPTR23.UINT8[LL]
-#define RSCAN0RMPTR23LH RSCAN0.RMPTR23.UINT8[LH]
-#define RSCAN0RMPTR23H RSCAN0.RMPTR23.UINT16[H]
-#define RSCAN0RMPTR23HL RSCAN0.RMPTR23.UINT8[HL]
-#define RSCAN0RMPTR23HH RSCAN0.RMPTR23.UINT8[HH]
-#define RSCAN0RMDF023 RSCAN0.RMDF023.UINT32
-#define RSCAN0RMDF023L RSCAN0.RMDF023.UINT16[L]
-#define RSCAN0RMDF023LL RSCAN0.RMDF023.UINT8[LL]
-#define RSCAN0RMDF023LH RSCAN0.RMDF023.UINT8[LH]
-#define RSCAN0RMDF023H RSCAN0.RMDF023.UINT16[H]
-#define RSCAN0RMDF023HL RSCAN0.RMDF023.UINT8[HL]
-#define RSCAN0RMDF023HH RSCAN0.RMDF023.UINT8[HH]
-#define RSCAN0RMDF123 RSCAN0.RMDF123.UINT32
-#define RSCAN0RMDF123L RSCAN0.RMDF123.UINT16[L]
-#define RSCAN0RMDF123LL RSCAN0.RMDF123.UINT8[LL]
-#define RSCAN0RMDF123LH RSCAN0.RMDF123.UINT8[LH]
-#define RSCAN0RMDF123H RSCAN0.RMDF123.UINT16[H]
-#define RSCAN0RMDF123HL RSCAN0.RMDF123.UINT8[HL]
-#define RSCAN0RMDF123HH RSCAN0.RMDF123.UINT8[HH]
-#define RSCAN0RMID24 RSCAN0.RMID24.UINT32
-#define RSCAN0RMID24L RSCAN0.RMID24.UINT16[L]
-#define RSCAN0RMID24LL RSCAN0.RMID24.UINT8[LL]
-#define RSCAN0RMID24LH RSCAN0.RMID24.UINT8[LH]
-#define RSCAN0RMID24H RSCAN0.RMID24.UINT16[H]
-#define RSCAN0RMID24HL RSCAN0.RMID24.UINT8[HL]
-#define RSCAN0RMID24HH RSCAN0.RMID24.UINT8[HH]
-#define RSCAN0RMPTR24 RSCAN0.RMPTR24.UINT32
-#define RSCAN0RMPTR24L RSCAN0.RMPTR24.UINT16[L]
-#define RSCAN0RMPTR24LL RSCAN0.RMPTR24.UINT8[LL]
-#define RSCAN0RMPTR24LH RSCAN0.RMPTR24.UINT8[LH]
-#define RSCAN0RMPTR24H RSCAN0.RMPTR24.UINT16[H]
-#define RSCAN0RMPTR24HL RSCAN0.RMPTR24.UINT8[HL]
-#define RSCAN0RMPTR24HH RSCAN0.RMPTR24.UINT8[HH]
-#define RSCAN0RMDF024 RSCAN0.RMDF024.UINT32
-#define RSCAN0RMDF024L RSCAN0.RMDF024.UINT16[L]
-#define RSCAN0RMDF024LL RSCAN0.RMDF024.UINT8[LL]
-#define RSCAN0RMDF024LH RSCAN0.RMDF024.UINT8[LH]
-#define RSCAN0RMDF024H RSCAN0.RMDF024.UINT16[H]
-#define RSCAN0RMDF024HL RSCAN0.RMDF024.UINT8[HL]
-#define RSCAN0RMDF024HH RSCAN0.RMDF024.UINT8[HH]
-#define RSCAN0RMDF124 RSCAN0.RMDF124.UINT32
-#define RSCAN0RMDF124L RSCAN0.RMDF124.UINT16[L]
-#define RSCAN0RMDF124LL RSCAN0.RMDF124.UINT8[LL]
-#define RSCAN0RMDF124LH RSCAN0.RMDF124.UINT8[LH]
-#define RSCAN0RMDF124H RSCAN0.RMDF124.UINT16[H]
-#define RSCAN0RMDF124HL RSCAN0.RMDF124.UINT8[HL]
-#define RSCAN0RMDF124HH RSCAN0.RMDF124.UINT8[HH]
-#define RSCAN0RMID25 RSCAN0.RMID25.UINT32
-#define RSCAN0RMID25L RSCAN0.RMID25.UINT16[L]
-#define RSCAN0RMID25LL RSCAN0.RMID25.UINT8[LL]
-#define RSCAN0RMID25LH RSCAN0.RMID25.UINT8[LH]
-#define RSCAN0RMID25H RSCAN0.RMID25.UINT16[H]
-#define RSCAN0RMID25HL RSCAN0.RMID25.UINT8[HL]
-#define RSCAN0RMID25HH RSCAN0.RMID25.UINT8[HH]
-#define RSCAN0RMPTR25 RSCAN0.RMPTR25.UINT32
-#define RSCAN0RMPTR25L RSCAN0.RMPTR25.UINT16[L]
-#define RSCAN0RMPTR25LL RSCAN0.RMPTR25.UINT8[LL]
-#define RSCAN0RMPTR25LH RSCAN0.RMPTR25.UINT8[LH]
-#define RSCAN0RMPTR25H RSCAN0.RMPTR25.UINT16[H]
-#define RSCAN0RMPTR25HL RSCAN0.RMPTR25.UINT8[HL]
-#define RSCAN0RMPTR25HH RSCAN0.RMPTR25.UINT8[HH]
-#define RSCAN0RMDF025 RSCAN0.RMDF025.UINT32
-#define RSCAN0RMDF025L RSCAN0.RMDF025.UINT16[L]
-#define RSCAN0RMDF025LL RSCAN0.RMDF025.UINT8[LL]
-#define RSCAN0RMDF025LH RSCAN0.RMDF025.UINT8[LH]
-#define RSCAN0RMDF025H RSCAN0.RMDF025.UINT16[H]
-#define RSCAN0RMDF025HL RSCAN0.RMDF025.UINT8[HL]
-#define RSCAN0RMDF025HH RSCAN0.RMDF025.UINT8[HH]
-#define RSCAN0RMDF125 RSCAN0.RMDF125.UINT32
-#define RSCAN0RMDF125L RSCAN0.RMDF125.UINT16[L]
-#define RSCAN0RMDF125LL RSCAN0.RMDF125.UINT8[LL]
-#define RSCAN0RMDF125LH RSCAN0.RMDF125.UINT8[LH]
-#define RSCAN0RMDF125H RSCAN0.RMDF125.UINT16[H]
-#define RSCAN0RMDF125HL RSCAN0.RMDF125.UINT8[HL]
-#define RSCAN0RMDF125HH RSCAN0.RMDF125.UINT8[HH]
-#define RSCAN0RMID26 RSCAN0.RMID26.UINT32
-#define RSCAN0RMID26L RSCAN0.RMID26.UINT16[L]
-#define RSCAN0RMID26LL RSCAN0.RMID26.UINT8[LL]
-#define RSCAN0RMID26LH RSCAN0.RMID26.UINT8[LH]
-#define RSCAN0RMID26H RSCAN0.RMID26.UINT16[H]
-#define RSCAN0RMID26HL RSCAN0.RMID26.UINT8[HL]
-#define RSCAN0RMID26HH RSCAN0.RMID26.UINT8[HH]
-#define RSCAN0RMPTR26 RSCAN0.RMPTR26.UINT32
-#define RSCAN0RMPTR26L RSCAN0.RMPTR26.UINT16[L]
-#define RSCAN0RMPTR26LL RSCAN0.RMPTR26.UINT8[LL]
-#define RSCAN0RMPTR26LH RSCAN0.RMPTR26.UINT8[LH]
-#define RSCAN0RMPTR26H RSCAN0.RMPTR26.UINT16[H]
-#define RSCAN0RMPTR26HL RSCAN0.RMPTR26.UINT8[HL]
-#define RSCAN0RMPTR26HH RSCAN0.RMPTR26.UINT8[HH]
-#define RSCAN0RMDF026 RSCAN0.RMDF026.UINT32
-#define RSCAN0RMDF026L RSCAN0.RMDF026.UINT16[L]
-#define RSCAN0RMDF026LL RSCAN0.RMDF026.UINT8[LL]
-#define RSCAN0RMDF026LH RSCAN0.RMDF026.UINT8[LH]
-#define RSCAN0RMDF026H RSCAN0.RMDF026.UINT16[H]
-#define RSCAN0RMDF026HL RSCAN0.RMDF026.UINT8[HL]
-#define RSCAN0RMDF026HH RSCAN0.RMDF026.UINT8[HH]
-#define RSCAN0RMDF126 RSCAN0.RMDF126.UINT32
-#define RSCAN0RMDF126L RSCAN0.RMDF126.UINT16[L]
-#define RSCAN0RMDF126LL RSCAN0.RMDF126.UINT8[LL]
-#define RSCAN0RMDF126LH RSCAN0.RMDF126.UINT8[LH]
-#define RSCAN0RMDF126H RSCAN0.RMDF126.UINT16[H]
-#define RSCAN0RMDF126HL RSCAN0.RMDF126.UINT8[HL]
-#define RSCAN0RMDF126HH RSCAN0.RMDF126.UINT8[HH]
-#define RSCAN0RMID27 RSCAN0.RMID27.UINT32
-#define RSCAN0RMID27L RSCAN0.RMID27.UINT16[L]
-#define RSCAN0RMID27LL RSCAN0.RMID27.UINT8[LL]
-#define RSCAN0RMID27LH RSCAN0.RMID27.UINT8[LH]
-#define RSCAN0RMID27H RSCAN0.RMID27.UINT16[H]
-#define RSCAN0RMID27HL RSCAN0.RMID27.UINT8[HL]
-#define RSCAN0RMID27HH RSCAN0.RMID27.UINT8[HH]
-#define RSCAN0RMPTR27 RSCAN0.RMPTR27.UINT32
-#define RSCAN0RMPTR27L RSCAN0.RMPTR27.UINT16[L]
-#define RSCAN0RMPTR27LL RSCAN0.RMPTR27.UINT8[LL]
-#define RSCAN0RMPTR27LH RSCAN0.RMPTR27.UINT8[LH]
-#define RSCAN0RMPTR27H RSCAN0.RMPTR27.UINT16[H]
-#define RSCAN0RMPTR27HL RSCAN0.RMPTR27.UINT8[HL]
-#define RSCAN0RMPTR27HH RSCAN0.RMPTR27.UINT8[HH]
-#define RSCAN0RMDF027 RSCAN0.RMDF027.UINT32
-#define RSCAN0RMDF027L RSCAN0.RMDF027.UINT16[L]
-#define RSCAN0RMDF027LL RSCAN0.RMDF027.UINT8[LL]
-#define RSCAN0RMDF027LH RSCAN0.RMDF027.UINT8[LH]
-#define RSCAN0RMDF027H RSCAN0.RMDF027.UINT16[H]
-#define RSCAN0RMDF027HL RSCAN0.RMDF027.UINT8[HL]
-#define RSCAN0RMDF027HH RSCAN0.RMDF027.UINT8[HH]
-#define RSCAN0RMDF127 RSCAN0.RMDF127.UINT32
-#define RSCAN0RMDF127L RSCAN0.RMDF127.UINT16[L]
-#define RSCAN0RMDF127LL RSCAN0.RMDF127.UINT8[LL]
-#define RSCAN0RMDF127LH RSCAN0.RMDF127.UINT8[LH]
-#define RSCAN0RMDF127H RSCAN0.RMDF127.UINT16[H]
-#define RSCAN0RMDF127HL RSCAN0.RMDF127.UINT8[HL]
-#define RSCAN0RMDF127HH RSCAN0.RMDF127.UINT8[HH]
-#define RSCAN0RMID28 RSCAN0.RMID28.UINT32
-#define RSCAN0RMID28L RSCAN0.RMID28.UINT16[L]
-#define RSCAN0RMID28LL RSCAN0.RMID28.UINT8[LL]
-#define RSCAN0RMID28LH RSCAN0.RMID28.UINT8[LH]
-#define RSCAN0RMID28H RSCAN0.RMID28.UINT16[H]
-#define RSCAN0RMID28HL RSCAN0.RMID28.UINT8[HL]
-#define RSCAN0RMID28HH RSCAN0.RMID28.UINT8[HH]
-#define RSCAN0RMPTR28 RSCAN0.RMPTR28.UINT32
-#define RSCAN0RMPTR28L RSCAN0.RMPTR28.UINT16[L]
-#define RSCAN0RMPTR28LL RSCAN0.RMPTR28.UINT8[LL]
-#define RSCAN0RMPTR28LH RSCAN0.RMPTR28.UINT8[LH]
-#define RSCAN0RMPTR28H RSCAN0.RMPTR28.UINT16[H]
-#define RSCAN0RMPTR28HL RSCAN0.RMPTR28.UINT8[HL]
-#define RSCAN0RMPTR28HH RSCAN0.RMPTR28.UINT8[HH]
-#define RSCAN0RMDF028 RSCAN0.RMDF028.UINT32
-#define RSCAN0RMDF028L RSCAN0.RMDF028.UINT16[L]
-#define RSCAN0RMDF028LL RSCAN0.RMDF028.UINT8[LL]
-#define RSCAN0RMDF028LH RSCAN0.RMDF028.UINT8[LH]
-#define RSCAN0RMDF028H RSCAN0.RMDF028.UINT16[H]
-#define RSCAN0RMDF028HL RSCAN0.RMDF028.UINT8[HL]
-#define RSCAN0RMDF028HH RSCAN0.RMDF028.UINT8[HH]
-#define RSCAN0RMDF128 RSCAN0.RMDF128.UINT32
-#define RSCAN0RMDF128L RSCAN0.RMDF128.UINT16[L]
-#define RSCAN0RMDF128LL RSCAN0.RMDF128.UINT8[LL]
-#define RSCAN0RMDF128LH RSCAN0.RMDF128.UINT8[LH]
-#define RSCAN0RMDF128H RSCAN0.RMDF128.UINT16[H]
-#define RSCAN0RMDF128HL RSCAN0.RMDF128.UINT8[HL]
-#define RSCAN0RMDF128HH RSCAN0.RMDF128.UINT8[HH]
-#define RSCAN0RMID29 RSCAN0.RMID29.UINT32
-#define RSCAN0RMID29L RSCAN0.RMID29.UINT16[L]
-#define RSCAN0RMID29LL RSCAN0.RMID29.UINT8[LL]
-#define RSCAN0RMID29LH RSCAN0.RMID29.UINT8[LH]
-#define RSCAN0RMID29H RSCAN0.RMID29.UINT16[H]
-#define RSCAN0RMID29HL RSCAN0.RMID29.UINT8[HL]
-#define RSCAN0RMID29HH RSCAN0.RMID29.UINT8[HH]
-#define RSCAN0RMPTR29 RSCAN0.RMPTR29.UINT32
-#define RSCAN0RMPTR29L RSCAN0.RMPTR29.UINT16[L]
-#define RSCAN0RMPTR29LL RSCAN0.RMPTR29.UINT8[LL]
-#define RSCAN0RMPTR29LH RSCAN0.RMPTR29.UINT8[LH]
-#define RSCAN0RMPTR29H RSCAN0.RMPTR29.UINT16[H]
-#define RSCAN0RMPTR29HL RSCAN0.RMPTR29.UINT8[HL]
-#define RSCAN0RMPTR29HH RSCAN0.RMPTR29.UINT8[HH]
-#define RSCAN0RMDF029 RSCAN0.RMDF029.UINT32
-#define RSCAN0RMDF029L RSCAN0.RMDF029.UINT16[L]
-#define RSCAN0RMDF029LL RSCAN0.RMDF029.UINT8[LL]
-#define RSCAN0RMDF029LH RSCAN0.RMDF029.UINT8[LH]
-#define RSCAN0RMDF029H RSCAN0.RMDF029.UINT16[H]
-#define RSCAN0RMDF029HL RSCAN0.RMDF029.UINT8[HL]
-#define RSCAN0RMDF029HH RSCAN0.RMDF029.UINT8[HH]
-#define RSCAN0RMDF129 RSCAN0.RMDF129.UINT32
-#define RSCAN0RMDF129L RSCAN0.RMDF129.UINT16[L]
-#define RSCAN0RMDF129LL RSCAN0.RMDF129.UINT8[LL]
-#define RSCAN0RMDF129LH RSCAN0.RMDF129.UINT8[LH]
-#define RSCAN0RMDF129H RSCAN0.RMDF129.UINT16[H]
-#define RSCAN0RMDF129HL RSCAN0.RMDF129.UINT8[HL]
-#define RSCAN0RMDF129HH RSCAN0.RMDF129.UINT8[HH]
-#define RSCAN0RMID30 RSCAN0.RMID30.UINT32
-#define RSCAN0RMID30L RSCAN0.RMID30.UINT16[L]
-#define RSCAN0RMID30LL RSCAN0.RMID30.UINT8[LL]
-#define RSCAN0RMID30LH RSCAN0.RMID30.UINT8[LH]
-#define RSCAN0RMID30H RSCAN0.RMID30.UINT16[H]
-#define RSCAN0RMID30HL RSCAN0.RMID30.UINT8[HL]
-#define RSCAN0RMID30HH RSCAN0.RMID30.UINT8[HH]
-#define RSCAN0RMPTR30 RSCAN0.RMPTR30.UINT32
-#define RSCAN0RMPTR30L RSCAN0.RMPTR30.UINT16[L]
-#define RSCAN0RMPTR30LL RSCAN0.RMPTR30.UINT8[LL]
-#define RSCAN0RMPTR30LH RSCAN0.RMPTR30.UINT8[LH]
-#define RSCAN0RMPTR30H RSCAN0.RMPTR30.UINT16[H]
-#define RSCAN0RMPTR30HL RSCAN0.RMPTR30.UINT8[HL]
-#define RSCAN0RMPTR30HH RSCAN0.RMPTR30.UINT8[HH]
-#define RSCAN0RMDF030 RSCAN0.RMDF030.UINT32
-#define RSCAN0RMDF030L RSCAN0.RMDF030.UINT16[L]
-#define RSCAN0RMDF030LL RSCAN0.RMDF030.UINT8[LL]
-#define RSCAN0RMDF030LH RSCAN0.RMDF030.UINT8[LH]
-#define RSCAN0RMDF030H RSCAN0.RMDF030.UINT16[H]
-#define RSCAN0RMDF030HL RSCAN0.RMDF030.UINT8[HL]
-#define RSCAN0RMDF030HH RSCAN0.RMDF030.UINT8[HH]
-#define RSCAN0RMDF130 RSCAN0.RMDF130.UINT32
-#define RSCAN0RMDF130L RSCAN0.RMDF130.UINT16[L]
-#define RSCAN0RMDF130LL RSCAN0.RMDF130.UINT8[LL]
-#define RSCAN0RMDF130LH RSCAN0.RMDF130.UINT8[LH]
-#define RSCAN0RMDF130H RSCAN0.RMDF130.UINT16[H]
-#define RSCAN0RMDF130HL RSCAN0.RMDF130.UINT8[HL]
-#define RSCAN0RMDF130HH RSCAN0.RMDF130.UINT8[HH]
-#define RSCAN0RMID31 RSCAN0.RMID31.UINT32
-#define RSCAN0RMID31L RSCAN0.RMID31.UINT16[L]
-#define RSCAN0RMID31LL RSCAN0.RMID31.UINT8[LL]
-#define RSCAN0RMID31LH RSCAN0.RMID31.UINT8[LH]
-#define RSCAN0RMID31H RSCAN0.RMID31.UINT16[H]
-#define RSCAN0RMID31HL RSCAN0.RMID31.UINT8[HL]
-#define RSCAN0RMID31HH RSCAN0.RMID31.UINT8[HH]
-#define RSCAN0RMPTR31 RSCAN0.RMPTR31.UINT32
-#define RSCAN0RMPTR31L RSCAN0.RMPTR31.UINT16[L]
-#define RSCAN0RMPTR31LL RSCAN0.RMPTR31.UINT8[LL]
-#define RSCAN0RMPTR31LH RSCAN0.RMPTR31.UINT8[LH]
-#define RSCAN0RMPTR31H RSCAN0.RMPTR31.UINT16[H]
-#define RSCAN0RMPTR31HL RSCAN0.RMPTR31.UINT8[HL]
-#define RSCAN0RMPTR31HH RSCAN0.RMPTR31.UINT8[HH]
-#define RSCAN0RMDF031 RSCAN0.RMDF031.UINT32
-#define RSCAN0RMDF031L RSCAN0.RMDF031.UINT16[L]
-#define RSCAN0RMDF031LL RSCAN0.RMDF031.UINT8[LL]
-#define RSCAN0RMDF031LH RSCAN0.RMDF031.UINT8[LH]
-#define RSCAN0RMDF031H RSCAN0.RMDF031.UINT16[H]
-#define RSCAN0RMDF031HL RSCAN0.RMDF031.UINT8[HL]
-#define RSCAN0RMDF031HH RSCAN0.RMDF031.UINT8[HH]
-#define RSCAN0RMDF131 RSCAN0.RMDF131.UINT32
-#define RSCAN0RMDF131L RSCAN0.RMDF131.UINT16[L]
-#define RSCAN0RMDF131LL RSCAN0.RMDF131.UINT8[LL]
-#define RSCAN0RMDF131LH RSCAN0.RMDF131.UINT8[LH]
-#define RSCAN0RMDF131H RSCAN0.RMDF131.UINT16[H]
-#define RSCAN0RMDF131HL RSCAN0.RMDF131.UINT8[HL]
-#define RSCAN0RMDF131HH RSCAN0.RMDF131.UINT8[HH]
-#define RSCAN0RMID32 RSCAN0.RMID32.UINT32
-#define RSCAN0RMID32L RSCAN0.RMID32.UINT16[L]
-#define RSCAN0RMID32LL RSCAN0.RMID32.UINT8[LL]
-#define RSCAN0RMID32LH RSCAN0.RMID32.UINT8[LH]
-#define RSCAN0RMID32H RSCAN0.RMID32.UINT16[H]
-#define RSCAN0RMID32HL RSCAN0.RMID32.UINT8[HL]
-#define RSCAN0RMID32HH RSCAN0.RMID32.UINT8[HH]
-#define RSCAN0RMPTR32 RSCAN0.RMPTR32.UINT32
-#define RSCAN0RMPTR32L RSCAN0.RMPTR32.UINT16[L]
-#define RSCAN0RMPTR32LL RSCAN0.RMPTR32.UINT8[LL]
-#define RSCAN0RMPTR32LH RSCAN0.RMPTR32.UINT8[LH]
-#define RSCAN0RMPTR32H RSCAN0.RMPTR32.UINT16[H]
-#define RSCAN0RMPTR32HL RSCAN0.RMPTR32.UINT8[HL]
-#define RSCAN0RMPTR32HH RSCAN0.RMPTR32.UINT8[HH]
-#define RSCAN0RMDF032 RSCAN0.RMDF032.UINT32
-#define RSCAN0RMDF032L RSCAN0.RMDF032.UINT16[L]
-#define RSCAN0RMDF032LL RSCAN0.RMDF032.UINT8[LL]
-#define RSCAN0RMDF032LH RSCAN0.RMDF032.UINT8[LH]
-#define RSCAN0RMDF032H RSCAN0.RMDF032.UINT16[H]
-#define RSCAN0RMDF032HL RSCAN0.RMDF032.UINT8[HL]
-#define RSCAN0RMDF032HH RSCAN0.RMDF032.UINT8[HH]
-#define RSCAN0RMDF132 RSCAN0.RMDF132.UINT32
-#define RSCAN0RMDF132L RSCAN0.RMDF132.UINT16[L]
-#define RSCAN0RMDF132LL RSCAN0.RMDF132.UINT8[LL]
-#define RSCAN0RMDF132LH RSCAN0.RMDF132.UINT8[LH]
-#define RSCAN0RMDF132H RSCAN0.RMDF132.UINT16[H]
-#define RSCAN0RMDF132HL RSCAN0.RMDF132.UINT8[HL]
-#define RSCAN0RMDF132HH RSCAN0.RMDF132.UINT8[HH]
-#define RSCAN0RMID33 RSCAN0.RMID33.UINT32
-#define RSCAN0RMID33L RSCAN0.RMID33.UINT16[L]
-#define RSCAN0RMID33LL RSCAN0.RMID33.UINT8[LL]
-#define RSCAN0RMID33LH RSCAN0.RMID33.UINT8[LH]
-#define RSCAN0RMID33H RSCAN0.RMID33.UINT16[H]
-#define RSCAN0RMID33HL RSCAN0.RMID33.UINT8[HL]
-#define RSCAN0RMID33HH RSCAN0.RMID33.UINT8[HH]
-#define RSCAN0RMPTR33 RSCAN0.RMPTR33.UINT32
-#define RSCAN0RMPTR33L RSCAN0.RMPTR33.UINT16[L]
-#define RSCAN0RMPTR33LL RSCAN0.RMPTR33.UINT8[LL]
-#define RSCAN0RMPTR33LH RSCAN0.RMPTR33.UINT8[LH]
-#define RSCAN0RMPTR33H RSCAN0.RMPTR33.UINT16[H]
-#define RSCAN0RMPTR33HL RSCAN0.RMPTR33.UINT8[HL]
-#define RSCAN0RMPTR33HH RSCAN0.RMPTR33.UINT8[HH]
-#define RSCAN0RMDF033 RSCAN0.RMDF033.UINT32
-#define RSCAN0RMDF033L RSCAN0.RMDF033.UINT16[L]
-#define RSCAN0RMDF033LL RSCAN0.RMDF033.UINT8[LL]
-#define RSCAN0RMDF033LH RSCAN0.RMDF033.UINT8[LH]
-#define RSCAN0RMDF033H RSCAN0.RMDF033.UINT16[H]
-#define RSCAN0RMDF033HL RSCAN0.RMDF033.UINT8[HL]
-#define RSCAN0RMDF033HH RSCAN0.RMDF033.UINT8[HH]
-#define RSCAN0RMDF133 RSCAN0.RMDF133.UINT32
-#define RSCAN0RMDF133L RSCAN0.RMDF133.UINT16[L]
-#define RSCAN0RMDF133LL RSCAN0.RMDF133.UINT8[LL]
-#define RSCAN0RMDF133LH RSCAN0.RMDF133.UINT8[LH]
-#define RSCAN0RMDF133H RSCAN0.RMDF133.UINT16[H]
-#define RSCAN0RMDF133HL RSCAN0.RMDF133.UINT8[HL]
-#define RSCAN0RMDF133HH RSCAN0.RMDF133.UINT8[HH]
-#define RSCAN0RMID34 RSCAN0.RMID34.UINT32
-#define RSCAN0RMID34L RSCAN0.RMID34.UINT16[L]
-#define RSCAN0RMID34LL RSCAN0.RMID34.UINT8[LL]
-#define RSCAN0RMID34LH RSCAN0.RMID34.UINT8[LH]
-#define RSCAN0RMID34H RSCAN0.RMID34.UINT16[H]
-#define RSCAN0RMID34HL RSCAN0.RMID34.UINT8[HL]
-#define RSCAN0RMID34HH RSCAN0.RMID34.UINT8[HH]
-#define RSCAN0RMPTR34 RSCAN0.RMPTR34.UINT32
-#define RSCAN0RMPTR34L RSCAN0.RMPTR34.UINT16[L]
-#define RSCAN0RMPTR34LL RSCAN0.RMPTR34.UINT8[LL]
-#define RSCAN0RMPTR34LH RSCAN0.RMPTR34.UINT8[LH]
-#define RSCAN0RMPTR34H RSCAN0.RMPTR34.UINT16[H]
-#define RSCAN0RMPTR34HL RSCAN0.RMPTR34.UINT8[HL]
-#define RSCAN0RMPTR34HH RSCAN0.RMPTR34.UINT8[HH]
-#define RSCAN0RMDF034 RSCAN0.RMDF034.UINT32
-#define RSCAN0RMDF034L RSCAN0.RMDF034.UINT16[L]
-#define RSCAN0RMDF034LL RSCAN0.RMDF034.UINT8[LL]
-#define RSCAN0RMDF034LH RSCAN0.RMDF034.UINT8[LH]
-#define RSCAN0RMDF034H RSCAN0.RMDF034.UINT16[H]
-#define RSCAN0RMDF034HL RSCAN0.RMDF034.UINT8[HL]
-#define RSCAN0RMDF034HH RSCAN0.RMDF034.UINT8[HH]
-#define RSCAN0RMDF134 RSCAN0.RMDF134.UINT32
-#define RSCAN0RMDF134L RSCAN0.RMDF134.UINT16[L]
-#define RSCAN0RMDF134LL RSCAN0.RMDF134.UINT8[LL]
-#define RSCAN0RMDF134LH RSCAN0.RMDF134.UINT8[LH]
-#define RSCAN0RMDF134H RSCAN0.RMDF134.UINT16[H]
-#define RSCAN0RMDF134HL RSCAN0.RMDF134.UINT8[HL]
-#define RSCAN0RMDF134HH RSCAN0.RMDF134.UINT8[HH]
-#define RSCAN0RMID35 RSCAN0.RMID35.UINT32
-#define RSCAN0RMID35L RSCAN0.RMID35.UINT16[L]
-#define RSCAN0RMID35LL RSCAN0.RMID35.UINT8[LL]
-#define RSCAN0RMID35LH RSCAN0.RMID35.UINT8[LH]
-#define RSCAN0RMID35H RSCAN0.RMID35.UINT16[H]
-#define RSCAN0RMID35HL RSCAN0.RMID35.UINT8[HL]
-#define RSCAN0RMID35HH RSCAN0.RMID35.UINT8[HH]
-#define RSCAN0RMPTR35 RSCAN0.RMPTR35.UINT32
-#define RSCAN0RMPTR35L RSCAN0.RMPTR35.UINT16[L]
-#define RSCAN0RMPTR35LL RSCAN0.RMPTR35.UINT8[LL]
-#define RSCAN0RMPTR35LH RSCAN0.RMPTR35.UINT8[LH]
-#define RSCAN0RMPTR35H RSCAN0.RMPTR35.UINT16[H]
-#define RSCAN0RMPTR35HL RSCAN0.RMPTR35.UINT8[HL]
-#define RSCAN0RMPTR35HH RSCAN0.RMPTR35.UINT8[HH]
-#define RSCAN0RMDF035 RSCAN0.RMDF035.UINT32
-#define RSCAN0RMDF035L RSCAN0.RMDF035.UINT16[L]
-#define RSCAN0RMDF035LL RSCAN0.RMDF035.UINT8[LL]
-#define RSCAN0RMDF035LH RSCAN0.RMDF035.UINT8[LH]
-#define RSCAN0RMDF035H RSCAN0.RMDF035.UINT16[H]
-#define RSCAN0RMDF035HL RSCAN0.RMDF035.UINT8[HL]
-#define RSCAN0RMDF035HH RSCAN0.RMDF035.UINT8[HH]
-#define RSCAN0RMDF135 RSCAN0.RMDF135.UINT32
-#define RSCAN0RMDF135L RSCAN0.RMDF135.UINT16[L]
-#define RSCAN0RMDF135LL RSCAN0.RMDF135.UINT8[LL]
-#define RSCAN0RMDF135LH RSCAN0.RMDF135.UINT8[LH]
-#define RSCAN0RMDF135H RSCAN0.RMDF135.UINT16[H]
-#define RSCAN0RMDF135HL RSCAN0.RMDF135.UINT8[HL]
-#define RSCAN0RMDF135HH RSCAN0.RMDF135.UINT8[HH]
-#define RSCAN0RMID36 RSCAN0.RMID36.UINT32
-#define RSCAN0RMID36L RSCAN0.RMID36.UINT16[L]
-#define RSCAN0RMID36LL RSCAN0.RMID36.UINT8[LL]
-#define RSCAN0RMID36LH RSCAN0.RMID36.UINT8[LH]
-#define RSCAN0RMID36H RSCAN0.RMID36.UINT16[H]
-#define RSCAN0RMID36HL RSCAN0.RMID36.UINT8[HL]
-#define RSCAN0RMID36HH RSCAN0.RMID36.UINT8[HH]
-#define RSCAN0RMPTR36 RSCAN0.RMPTR36.UINT32
-#define RSCAN0RMPTR36L RSCAN0.RMPTR36.UINT16[L]
-#define RSCAN0RMPTR36LL RSCAN0.RMPTR36.UINT8[LL]
-#define RSCAN0RMPTR36LH RSCAN0.RMPTR36.UINT8[LH]
-#define RSCAN0RMPTR36H RSCAN0.RMPTR36.UINT16[H]
-#define RSCAN0RMPTR36HL RSCAN0.RMPTR36.UINT8[HL]
-#define RSCAN0RMPTR36HH RSCAN0.RMPTR36.UINT8[HH]
-#define RSCAN0RMDF036 RSCAN0.RMDF036.UINT32
-#define RSCAN0RMDF036L RSCAN0.RMDF036.UINT16[L]
-#define RSCAN0RMDF036LL RSCAN0.RMDF036.UINT8[LL]
-#define RSCAN0RMDF036LH RSCAN0.RMDF036.UINT8[LH]
-#define RSCAN0RMDF036H RSCAN0.RMDF036.UINT16[H]
-#define RSCAN0RMDF036HL RSCAN0.RMDF036.UINT8[HL]
-#define RSCAN0RMDF036HH RSCAN0.RMDF036.UINT8[HH]
-#define RSCAN0RMDF136 RSCAN0.RMDF136.UINT32
-#define RSCAN0RMDF136L RSCAN0.RMDF136.UINT16[L]
-#define RSCAN0RMDF136LL RSCAN0.RMDF136.UINT8[LL]
-#define RSCAN0RMDF136LH RSCAN0.RMDF136.UINT8[LH]
-#define RSCAN0RMDF136H RSCAN0.RMDF136.UINT16[H]
-#define RSCAN0RMDF136HL RSCAN0.RMDF136.UINT8[HL]
-#define RSCAN0RMDF136HH RSCAN0.RMDF136.UINT8[HH]
-#define RSCAN0RMID37 RSCAN0.RMID37.UINT32
-#define RSCAN0RMID37L RSCAN0.RMID37.UINT16[L]
-#define RSCAN0RMID37LL RSCAN0.RMID37.UINT8[LL]
-#define RSCAN0RMID37LH RSCAN0.RMID37.UINT8[LH]
-#define RSCAN0RMID37H RSCAN0.RMID37.UINT16[H]
-#define RSCAN0RMID37HL RSCAN0.RMID37.UINT8[HL]
-#define RSCAN0RMID37HH RSCAN0.RMID37.UINT8[HH]
-#define RSCAN0RMPTR37 RSCAN0.RMPTR37.UINT32
-#define RSCAN0RMPTR37L RSCAN0.RMPTR37.UINT16[L]
-#define RSCAN0RMPTR37LL RSCAN0.RMPTR37.UINT8[LL]
-#define RSCAN0RMPTR37LH RSCAN0.RMPTR37.UINT8[LH]
-#define RSCAN0RMPTR37H RSCAN0.RMPTR37.UINT16[H]
-#define RSCAN0RMPTR37HL RSCAN0.RMPTR37.UINT8[HL]
-#define RSCAN0RMPTR37HH RSCAN0.RMPTR37.UINT8[HH]
-#define RSCAN0RMDF037 RSCAN0.RMDF037.UINT32
-#define RSCAN0RMDF037L RSCAN0.RMDF037.UINT16[L]
-#define RSCAN0RMDF037LL RSCAN0.RMDF037.UINT8[LL]
-#define RSCAN0RMDF037LH RSCAN0.RMDF037.UINT8[LH]
-#define RSCAN0RMDF037H RSCAN0.RMDF037.UINT16[H]
-#define RSCAN0RMDF037HL RSCAN0.RMDF037.UINT8[HL]
-#define RSCAN0RMDF037HH RSCAN0.RMDF037.UINT8[HH]
-#define RSCAN0RMDF137 RSCAN0.RMDF137.UINT32
-#define RSCAN0RMDF137L RSCAN0.RMDF137.UINT16[L]
-#define RSCAN0RMDF137LL RSCAN0.RMDF137.UINT8[LL]
-#define RSCAN0RMDF137LH RSCAN0.RMDF137.UINT8[LH]
-#define RSCAN0RMDF137H RSCAN0.RMDF137.UINT16[H]
-#define RSCAN0RMDF137HL RSCAN0.RMDF137.UINT8[HL]
-#define RSCAN0RMDF137HH RSCAN0.RMDF137.UINT8[HH]
-#define RSCAN0RMID38 RSCAN0.RMID38.UINT32
-#define RSCAN0RMID38L RSCAN0.RMID38.UINT16[L]
-#define RSCAN0RMID38LL RSCAN0.RMID38.UINT8[LL]
-#define RSCAN0RMID38LH RSCAN0.RMID38.UINT8[LH]
-#define RSCAN0RMID38H RSCAN0.RMID38.UINT16[H]
-#define RSCAN0RMID38HL RSCAN0.RMID38.UINT8[HL]
-#define RSCAN0RMID38HH RSCAN0.RMID38.UINT8[HH]
-#define RSCAN0RMPTR38 RSCAN0.RMPTR38.UINT32
-#define RSCAN0RMPTR38L RSCAN0.RMPTR38.UINT16[L]
-#define RSCAN0RMPTR38LL RSCAN0.RMPTR38.UINT8[LL]
-#define RSCAN0RMPTR38LH RSCAN0.RMPTR38.UINT8[LH]
-#define RSCAN0RMPTR38H RSCAN0.RMPTR38.UINT16[H]
-#define RSCAN0RMPTR38HL RSCAN0.RMPTR38.UINT8[HL]
-#define RSCAN0RMPTR38HH RSCAN0.RMPTR38.UINT8[HH]
-#define RSCAN0RMDF038 RSCAN0.RMDF038.UINT32
-#define RSCAN0RMDF038L RSCAN0.RMDF038.UINT16[L]
-#define RSCAN0RMDF038LL RSCAN0.RMDF038.UINT8[LL]
-#define RSCAN0RMDF038LH RSCAN0.RMDF038.UINT8[LH]
-#define RSCAN0RMDF038H RSCAN0.RMDF038.UINT16[H]
-#define RSCAN0RMDF038HL RSCAN0.RMDF038.UINT8[HL]
-#define RSCAN0RMDF038HH RSCAN0.RMDF038.UINT8[HH]
-#define RSCAN0RMDF138 RSCAN0.RMDF138.UINT32
-#define RSCAN0RMDF138L RSCAN0.RMDF138.UINT16[L]
-#define RSCAN0RMDF138LL RSCAN0.RMDF138.UINT8[LL]
-#define RSCAN0RMDF138LH RSCAN0.RMDF138.UINT8[LH]
-#define RSCAN0RMDF138H RSCAN0.RMDF138.UINT16[H]
-#define RSCAN0RMDF138HL RSCAN0.RMDF138.UINT8[HL]
-#define RSCAN0RMDF138HH RSCAN0.RMDF138.UINT8[HH]
-#define RSCAN0RMID39 RSCAN0.RMID39.UINT32
-#define RSCAN0RMID39L RSCAN0.RMID39.UINT16[L]
-#define RSCAN0RMID39LL RSCAN0.RMID39.UINT8[LL]
-#define RSCAN0RMID39LH RSCAN0.RMID39.UINT8[LH]
-#define RSCAN0RMID39H RSCAN0.RMID39.UINT16[H]
-#define RSCAN0RMID39HL RSCAN0.RMID39.UINT8[HL]
-#define RSCAN0RMID39HH RSCAN0.RMID39.UINT8[HH]
-#define RSCAN0RMPTR39 RSCAN0.RMPTR39.UINT32
-#define RSCAN0RMPTR39L RSCAN0.RMPTR39.UINT16[L]
-#define RSCAN0RMPTR39LL RSCAN0.RMPTR39.UINT8[LL]
-#define RSCAN0RMPTR39LH RSCAN0.RMPTR39.UINT8[LH]
-#define RSCAN0RMPTR39H RSCAN0.RMPTR39.UINT16[H]
-#define RSCAN0RMPTR39HL RSCAN0.RMPTR39.UINT8[HL]
-#define RSCAN0RMPTR39HH RSCAN0.RMPTR39.UINT8[HH]
-#define RSCAN0RMDF039 RSCAN0.RMDF039.UINT32
-#define RSCAN0RMDF039L RSCAN0.RMDF039.UINT16[L]
-#define RSCAN0RMDF039LL RSCAN0.RMDF039.UINT8[LL]
-#define RSCAN0RMDF039LH RSCAN0.RMDF039.UINT8[LH]
-#define RSCAN0RMDF039H RSCAN0.RMDF039.UINT16[H]
-#define RSCAN0RMDF039HL RSCAN0.RMDF039.UINT8[HL]
-#define RSCAN0RMDF039HH RSCAN0.RMDF039.UINT8[HH]
-#define RSCAN0RMDF139 RSCAN0.RMDF139.UINT32
-#define RSCAN0RMDF139L RSCAN0.RMDF139.UINT16[L]
-#define RSCAN0RMDF139LL RSCAN0.RMDF139.UINT8[LL]
-#define RSCAN0RMDF139LH RSCAN0.RMDF139.UINT8[LH]
-#define RSCAN0RMDF139H RSCAN0.RMDF139.UINT16[H]
-#define RSCAN0RMDF139HL RSCAN0.RMDF139.UINT8[HL]
-#define RSCAN0RMDF139HH RSCAN0.RMDF139.UINT8[HH]
-#define RSCAN0RMID40 RSCAN0.RMID40.UINT32
-#define RSCAN0RMID40L RSCAN0.RMID40.UINT16[L]
-#define RSCAN0RMID40LL RSCAN0.RMID40.UINT8[LL]
-#define RSCAN0RMID40LH RSCAN0.RMID40.UINT8[LH]
-#define RSCAN0RMID40H RSCAN0.RMID40.UINT16[H]
-#define RSCAN0RMID40HL RSCAN0.RMID40.UINT8[HL]
-#define RSCAN0RMID40HH RSCAN0.RMID40.UINT8[HH]
-#define RSCAN0RMPTR40 RSCAN0.RMPTR40.UINT32
-#define RSCAN0RMPTR40L RSCAN0.RMPTR40.UINT16[L]
-#define RSCAN0RMPTR40LL RSCAN0.RMPTR40.UINT8[LL]
-#define RSCAN0RMPTR40LH RSCAN0.RMPTR40.UINT8[LH]
-#define RSCAN0RMPTR40H RSCAN0.RMPTR40.UINT16[H]
-#define RSCAN0RMPTR40HL RSCAN0.RMPTR40.UINT8[HL]
-#define RSCAN0RMPTR40HH RSCAN0.RMPTR40.UINT8[HH]
-#define RSCAN0RMDF040 RSCAN0.RMDF040.UINT32
-#define RSCAN0RMDF040L RSCAN0.RMDF040.UINT16[L]
-#define RSCAN0RMDF040LL RSCAN0.RMDF040.UINT8[LL]
-#define RSCAN0RMDF040LH RSCAN0.RMDF040.UINT8[LH]
-#define RSCAN0RMDF040H RSCAN0.RMDF040.UINT16[H]
-#define RSCAN0RMDF040HL RSCAN0.RMDF040.UINT8[HL]
-#define RSCAN0RMDF040HH RSCAN0.RMDF040.UINT8[HH]
-#define RSCAN0RMDF140 RSCAN0.RMDF140.UINT32
-#define RSCAN0RMDF140L RSCAN0.RMDF140.UINT16[L]
-#define RSCAN0RMDF140LL RSCAN0.RMDF140.UINT8[LL]
-#define RSCAN0RMDF140LH RSCAN0.RMDF140.UINT8[LH]
-#define RSCAN0RMDF140H RSCAN0.RMDF140.UINT16[H]
-#define RSCAN0RMDF140HL RSCAN0.RMDF140.UINT8[HL]
-#define RSCAN0RMDF140HH RSCAN0.RMDF140.UINT8[HH]
-#define RSCAN0RMID41 RSCAN0.RMID41.UINT32
-#define RSCAN0RMID41L RSCAN0.RMID41.UINT16[L]
-#define RSCAN0RMID41LL RSCAN0.RMID41.UINT8[LL]
-#define RSCAN0RMID41LH RSCAN0.RMID41.UINT8[LH]
-#define RSCAN0RMID41H RSCAN0.RMID41.UINT16[H]
-#define RSCAN0RMID41HL RSCAN0.RMID41.UINT8[HL]
-#define RSCAN0RMID41HH RSCAN0.RMID41.UINT8[HH]
-#define RSCAN0RMPTR41 RSCAN0.RMPTR41.UINT32
-#define RSCAN0RMPTR41L RSCAN0.RMPTR41.UINT16[L]
-#define RSCAN0RMPTR41LL RSCAN0.RMPTR41.UINT8[LL]
-#define RSCAN0RMPTR41LH RSCAN0.RMPTR41.UINT8[LH]
-#define RSCAN0RMPTR41H RSCAN0.RMPTR41.UINT16[H]
-#define RSCAN0RMPTR41HL RSCAN0.RMPTR41.UINT8[HL]
-#define RSCAN0RMPTR41HH RSCAN0.RMPTR41.UINT8[HH]
-#define RSCAN0RMDF041 RSCAN0.RMDF041.UINT32
-#define RSCAN0RMDF041L RSCAN0.RMDF041.UINT16[L]
-#define RSCAN0RMDF041LL RSCAN0.RMDF041.UINT8[LL]
-#define RSCAN0RMDF041LH RSCAN0.RMDF041.UINT8[LH]
-#define RSCAN0RMDF041H RSCAN0.RMDF041.UINT16[H]
-#define RSCAN0RMDF041HL RSCAN0.RMDF041.UINT8[HL]
-#define RSCAN0RMDF041HH RSCAN0.RMDF041.UINT8[HH]
-#define RSCAN0RMDF141 RSCAN0.RMDF141.UINT32
-#define RSCAN0RMDF141L RSCAN0.RMDF141.UINT16[L]
-#define RSCAN0RMDF141LL RSCAN0.RMDF141.UINT8[LL]
-#define RSCAN0RMDF141LH RSCAN0.RMDF141.UINT8[LH]
-#define RSCAN0RMDF141H RSCAN0.RMDF141.UINT16[H]
-#define RSCAN0RMDF141HL RSCAN0.RMDF141.UINT8[HL]
-#define RSCAN0RMDF141HH RSCAN0.RMDF141.UINT8[HH]
-#define RSCAN0RMID42 RSCAN0.RMID42.UINT32
-#define RSCAN0RMID42L RSCAN0.RMID42.UINT16[L]
-#define RSCAN0RMID42LL RSCAN0.RMID42.UINT8[LL]
-#define RSCAN0RMID42LH RSCAN0.RMID42.UINT8[LH]
-#define RSCAN0RMID42H RSCAN0.RMID42.UINT16[H]
-#define RSCAN0RMID42HL RSCAN0.RMID42.UINT8[HL]
-#define RSCAN0RMID42HH RSCAN0.RMID42.UINT8[HH]
-#define RSCAN0RMPTR42 RSCAN0.RMPTR42.UINT32
-#define RSCAN0RMPTR42L RSCAN0.RMPTR42.UINT16[L]
-#define RSCAN0RMPTR42LL RSCAN0.RMPTR42.UINT8[LL]
-#define RSCAN0RMPTR42LH RSCAN0.RMPTR42.UINT8[LH]
-#define RSCAN0RMPTR42H RSCAN0.RMPTR42.UINT16[H]
-#define RSCAN0RMPTR42HL RSCAN0.RMPTR42.UINT8[HL]
-#define RSCAN0RMPTR42HH RSCAN0.RMPTR42.UINT8[HH]
-#define RSCAN0RMDF042 RSCAN0.RMDF042.UINT32
-#define RSCAN0RMDF042L RSCAN0.RMDF042.UINT16[L]
-#define RSCAN0RMDF042LL RSCAN0.RMDF042.UINT8[LL]
-#define RSCAN0RMDF042LH RSCAN0.RMDF042.UINT8[LH]
-#define RSCAN0RMDF042H RSCAN0.RMDF042.UINT16[H]
-#define RSCAN0RMDF042HL RSCAN0.RMDF042.UINT8[HL]
-#define RSCAN0RMDF042HH RSCAN0.RMDF042.UINT8[HH]
-#define RSCAN0RMDF142 RSCAN0.RMDF142.UINT32
-#define RSCAN0RMDF142L RSCAN0.RMDF142.UINT16[L]
-#define RSCAN0RMDF142LL RSCAN0.RMDF142.UINT8[LL]
-#define RSCAN0RMDF142LH RSCAN0.RMDF142.UINT8[LH]
-#define RSCAN0RMDF142H RSCAN0.RMDF142.UINT16[H]
-#define RSCAN0RMDF142HL RSCAN0.RMDF142.UINT8[HL]
-#define RSCAN0RMDF142HH RSCAN0.RMDF142.UINT8[HH]
-#define RSCAN0RMID43 RSCAN0.RMID43.UINT32
-#define RSCAN0RMID43L RSCAN0.RMID43.UINT16[L]
-#define RSCAN0RMID43LL RSCAN0.RMID43.UINT8[LL]
-#define RSCAN0RMID43LH RSCAN0.RMID43.UINT8[LH]
-#define RSCAN0RMID43H RSCAN0.RMID43.UINT16[H]
-#define RSCAN0RMID43HL RSCAN0.RMID43.UINT8[HL]
-#define RSCAN0RMID43HH RSCAN0.RMID43.UINT8[HH]
-#define RSCAN0RMPTR43 RSCAN0.RMPTR43.UINT32
-#define RSCAN0RMPTR43L RSCAN0.RMPTR43.UINT16[L]
-#define RSCAN0RMPTR43LL RSCAN0.RMPTR43.UINT8[LL]
-#define RSCAN0RMPTR43LH RSCAN0.RMPTR43.UINT8[LH]
-#define RSCAN0RMPTR43H RSCAN0.RMPTR43.UINT16[H]
-#define RSCAN0RMPTR43HL RSCAN0.RMPTR43.UINT8[HL]
-#define RSCAN0RMPTR43HH RSCAN0.RMPTR43.UINT8[HH]
-#define RSCAN0RMDF043 RSCAN0.RMDF043.UINT32
-#define RSCAN0RMDF043L RSCAN0.RMDF043.UINT16[L]
-#define RSCAN0RMDF043LL RSCAN0.RMDF043.UINT8[LL]
-#define RSCAN0RMDF043LH RSCAN0.RMDF043.UINT8[LH]
-#define RSCAN0RMDF043H RSCAN0.RMDF043.UINT16[H]
-#define RSCAN0RMDF043HL RSCAN0.RMDF043.UINT8[HL]
-#define RSCAN0RMDF043HH RSCAN0.RMDF043.UINT8[HH]
-#define RSCAN0RMDF143 RSCAN0.RMDF143.UINT32
-#define RSCAN0RMDF143L RSCAN0.RMDF143.UINT16[L]
-#define RSCAN0RMDF143LL RSCAN0.RMDF143.UINT8[LL]
-#define RSCAN0RMDF143LH RSCAN0.RMDF143.UINT8[LH]
-#define RSCAN0RMDF143H RSCAN0.RMDF143.UINT16[H]
-#define RSCAN0RMDF143HL RSCAN0.RMDF143.UINT8[HL]
-#define RSCAN0RMDF143HH RSCAN0.RMDF143.UINT8[HH]
-#define RSCAN0RMID44 RSCAN0.RMID44.UINT32
-#define RSCAN0RMID44L RSCAN0.RMID44.UINT16[L]
-#define RSCAN0RMID44LL RSCAN0.RMID44.UINT8[LL]
-#define RSCAN0RMID44LH RSCAN0.RMID44.UINT8[LH]
-#define RSCAN0RMID44H RSCAN0.RMID44.UINT16[H]
-#define RSCAN0RMID44HL RSCAN0.RMID44.UINT8[HL]
-#define RSCAN0RMID44HH RSCAN0.RMID44.UINT8[HH]
-#define RSCAN0RMPTR44 RSCAN0.RMPTR44.UINT32
-#define RSCAN0RMPTR44L RSCAN0.RMPTR44.UINT16[L]
-#define RSCAN0RMPTR44LL RSCAN0.RMPTR44.UINT8[LL]
-#define RSCAN0RMPTR44LH RSCAN0.RMPTR44.UINT8[LH]
-#define RSCAN0RMPTR44H RSCAN0.RMPTR44.UINT16[H]
-#define RSCAN0RMPTR44HL RSCAN0.RMPTR44.UINT8[HL]
-#define RSCAN0RMPTR44HH RSCAN0.RMPTR44.UINT8[HH]
-#define RSCAN0RMDF044 RSCAN0.RMDF044.UINT32
-#define RSCAN0RMDF044L RSCAN0.RMDF044.UINT16[L]
-#define RSCAN0RMDF044LL RSCAN0.RMDF044.UINT8[LL]
-#define RSCAN0RMDF044LH RSCAN0.RMDF044.UINT8[LH]
-#define RSCAN0RMDF044H RSCAN0.RMDF044.UINT16[H]
-#define RSCAN0RMDF044HL RSCAN0.RMDF044.UINT8[HL]
-#define RSCAN0RMDF044HH RSCAN0.RMDF044.UINT8[HH]
-#define RSCAN0RMDF144 RSCAN0.RMDF144.UINT32
-#define RSCAN0RMDF144L RSCAN0.RMDF144.UINT16[L]
-#define RSCAN0RMDF144LL RSCAN0.RMDF144.UINT8[LL]
-#define RSCAN0RMDF144LH RSCAN0.RMDF144.UINT8[LH]
-#define RSCAN0RMDF144H RSCAN0.RMDF144.UINT16[H]
-#define RSCAN0RMDF144HL RSCAN0.RMDF144.UINT8[HL]
-#define RSCAN0RMDF144HH RSCAN0.RMDF144.UINT8[HH]
-#define RSCAN0RMID45 RSCAN0.RMID45.UINT32
-#define RSCAN0RMID45L RSCAN0.RMID45.UINT16[L]
-#define RSCAN0RMID45LL RSCAN0.RMID45.UINT8[LL]
-#define RSCAN0RMID45LH RSCAN0.RMID45.UINT8[LH]
-#define RSCAN0RMID45H RSCAN0.RMID45.UINT16[H]
-#define RSCAN0RMID45HL RSCAN0.RMID45.UINT8[HL]
-#define RSCAN0RMID45HH RSCAN0.RMID45.UINT8[HH]
-#define RSCAN0RMPTR45 RSCAN0.RMPTR45.UINT32
-#define RSCAN0RMPTR45L RSCAN0.RMPTR45.UINT16[L]
-#define RSCAN0RMPTR45LL RSCAN0.RMPTR45.UINT8[LL]
-#define RSCAN0RMPTR45LH RSCAN0.RMPTR45.UINT8[LH]
-#define RSCAN0RMPTR45H RSCAN0.RMPTR45.UINT16[H]
-#define RSCAN0RMPTR45HL RSCAN0.RMPTR45.UINT8[HL]
-#define RSCAN0RMPTR45HH RSCAN0.RMPTR45.UINT8[HH]
-#define RSCAN0RMDF045 RSCAN0.RMDF045.UINT32
-#define RSCAN0RMDF045L RSCAN0.RMDF045.UINT16[L]
-#define RSCAN0RMDF045LL RSCAN0.RMDF045.UINT8[LL]
-#define RSCAN0RMDF045LH RSCAN0.RMDF045.UINT8[LH]
-#define RSCAN0RMDF045H RSCAN0.RMDF045.UINT16[H]
-#define RSCAN0RMDF045HL RSCAN0.RMDF045.UINT8[HL]
-#define RSCAN0RMDF045HH RSCAN0.RMDF045.UINT8[HH]
-#define RSCAN0RMDF145 RSCAN0.RMDF145.UINT32
-#define RSCAN0RMDF145L RSCAN0.RMDF145.UINT16[L]
-#define RSCAN0RMDF145LL RSCAN0.RMDF145.UINT8[LL]
-#define RSCAN0RMDF145LH RSCAN0.RMDF145.UINT8[LH]
-#define RSCAN0RMDF145H RSCAN0.RMDF145.UINT16[H]
-#define RSCAN0RMDF145HL RSCAN0.RMDF145.UINT8[HL]
-#define RSCAN0RMDF145HH RSCAN0.RMDF145.UINT8[HH]
-#define RSCAN0RMID46 RSCAN0.RMID46.UINT32
-#define RSCAN0RMID46L RSCAN0.RMID46.UINT16[L]
-#define RSCAN0RMID46LL RSCAN0.RMID46.UINT8[LL]
-#define RSCAN0RMID46LH RSCAN0.RMID46.UINT8[LH]
-#define RSCAN0RMID46H RSCAN0.RMID46.UINT16[H]
-#define RSCAN0RMID46HL RSCAN0.RMID46.UINT8[HL]
-#define RSCAN0RMID46HH RSCAN0.RMID46.UINT8[HH]
-#define RSCAN0RMPTR46 RSCAN0.RMPTR46.UINT32
-#define RSCAN0RMPTR46L RSCAN0.RMPTR46.UINT16[L]
-#define RSCAN0RMPTR46LL RSCAN0.RMPTR46.UINT8[LL]
-#define RSCAN0RMPTR46LH RSCAN0.RMPTR46.UINT8[LH]
-#define RSCAN0RMPTR46H RSCAN0.RMPTR46.UINT16[H]
-#define RSCAN0RMPTR46HL RSCAN0.RMPTR46.UINT8[HL]
-#define RSCAN0RMPTR46HH RSCAN0.RMPTR46.UINT8[HH]
-#define RSCAN0RMDF046 RSCAN0.RMDF046.UINT32
-#define RSCAN0RMDF046L RSCAN0.RMDF046.UINT16[L]
-#define RSCAN0RMDF046LL RSCAN0.RMDF046.UINT8[LL]
-#define RSCAN0RMDF046LH RSCAN0.RMDF046.UINT8[LH]
-#define RSCAN0RMDF046H RSCAN0.RMDF046.UINT16[H]
-#define RSCAN0RMDF046HL RSCAN0.RMDF046.UINT8[HL]
-#define RSCAN0RMDF046HH RSCAN0.RMDF046.UINT8[HH]
-#define RSCAN0RMDF146 RSCAN0.RMDF146.UINT32
-#define RSCAN0RMDF146L RSCAN0.RMDF146.UINT16[L]
-#define RSCAN0RMDF146LL RSCAN0.RMDF146.UINT8[LL]
-#define RSCAN0RMDF146LH RSCAN0.RMDF146.UINT8[LH]
-#define RSCAN0RMDF146H RSCAN0.RMDF146.UINT16[H]
-#define RSCAN0RMDF146HL RSCAN0.RMDF146.UINT8[HL]
-#define RSCAN0RMDF146HH RSCAN0.RMDF146.UINT8[HH]
-#define RSCAN0RMID47 RSCAN0.RMID47.UINT32
-#define RSCAN0RMID47L RSCAN0.RMID47.UINT16[L]
-#define RSCAN0RMID47LL RSCAN0.RMID47.UINT8[LL]
-#define RSCAN0RMID47LH RSCAN0.RMID47.UINT8[LH]
-#define RSCAN0RMID47H RSCAN0.RMID47.UINT16[H]
-#define RSCAN0RMID47HL RSCAN0.RMID47.UINT8[HL]
-#define RSCAN0RMID47HH RSCAN0.RMID47.UINT8[HH]
-#define RSCAN0RMPTR47 RSCAN0.RMPTR47.UINT32
-#define RSCAN0RMPTR47L RSCAN0.RMPTR47.UINT16[L]
-#define RSCAN0RMPTR47LL RSCAN0.RMPTR47.UINT8[LL]
-#define RSCAN0RMPTR47LH RSCAN0.RMPTR47.UINT8[LH]
-#define RSCAN0RMPTR47H RSCAN0.RMPTR47.UINT16[H]
-#define RSCAN0RMPTR47HL RSCAN0.RMPTR47.UINT8[HL]
-#define RSCAN0RMPTR47HH RSCAN0.RMPTR47.UINT8[HH]
-#define RSCAN0RMDF047 RSCAN0.RMDF047.UINT32
-#define RSCAN0RMDF047L RSCAN0.RMDF047.UINT16[L]
-#define RSCAN0RMDF047LL RSCAN0.RMDF047.UINT8[LL]
-#define RSCAN0RMDF047LH RSCAN0.RMDF047.UINT8[LH]
-#define RSCAN0RMDF047H RSCAN0.RMDF047.UINT16[H]
-#define RSCAN0RMDF047HL RSCAN0.RMDF047.UINT8[HL]
-#define RSCAN0RMDF047HH RSCAN0.RMDF047.UINT8[HH]
-#define RSCAN0RMDF147 RSCAN0.RMDF147.UINT32
-#define RSCAN0RMDF147L RSCAN0.RMDF147.UINT16[L]
-#define RSCAN0RMDF147LL RSCAN0.RMDF147.UINT8[LL]
-#define RSCAN0RMDF147LH RSCAN0.RMDF147.UINT8[LH]
-#define RSCAN0RMDF147H RSCAN0.RMDF147.UINT16[H]
-#define RSCAN0RMDF147HL RSCAN0.RMDF147.UINT8[HL]
-#define RSCAN0RMDF147HH RSCAN0.RMDF147.UINT8[HH]
-#define RSCAN0RMID48 RSCAN0.RMID48.UINT32
-#define RSCAN0RMID48L RSCAN0.RMID48.UINT16[L]
-#define RSCAN0RMID48LL RSCAN0.RMID48.UINT8[LL]
-#define RSCAN0RMID48LH RSCAN0.RMID48.UINT8[LH]
-#define RSCAN0RMID48H RSCAN0.RMID48.UINT16[H]
-#define RSCAN0RMID48HL RSCAN0.RMID48.UINT8[HL]
-#define RSCAN0RMID48HH RSCAN0.RMID48.UINT8[HH]
-#define RSCAN0RMPTR48 RSCAN0.RMPTR48.UINT32
-#define RSCAN0RMPTR48L RSCAN0.RMPTR48.UINT16[L]
-#define RSCAN0RMPTR48LL RSCAN0.RMPTR48.UINT8[LL]
-#define RSCAN0RMPTR48LH RSCAN0.RMPTR48.UINT8[LH]
-#define RSCAN0RMPTR48H RSCAN0.RMPTR48.UINT16[H]
-#define RSCAN0RMPTR48HL RSCAN0.RMPTR48.UINT8[HL]
-#define RSCAN0RMPTR48HH RSCAN0.RMPTR48.UINT8[HH]
-#define RSCAN0RMDF048 RSCAN0.RMDF048.UINT32
-#define RSCAN0RMDF048L RSCAN0.RMDF048.UINT16[L]
-#define RSCAN0RMDF048LL RSCAN0.RMDF048.UINT8[LL]
-#define RSCAN0RMDF048LH RSCAN0.RMDF048.UINT8[LH]
-#define RSCAN0RMDF048H RSCAN0.RMDF048.UINT16[H]
-#define RSCAN0RMDF048HL RSCAN0.RMDF048.UINT8[HL]
-#define RSCAN0RMDF048HH RSCAN0.RMDF048.UINT8[HH]
-#define RSCAN0RMDF148 RSCAN0.RMDF148.UINT32
-#define RSCAN0RMDF148L RSCAN0.RMDF148.UINT16[L]
-#define RSCAN0RMDF148LL RSCAN0.RMDF148.UINT8[LL]
-#define RSCAN0RMDF148LH RSCAN0.RMDF148.UINT8[LH]
-#define RSCAN0RMDF148H RSCAN0.RMDF148.UINT16[H]
-#define RSCAN0RMDF148HL RSCAN0.RMDF148.UINT8[HL]
-#define RSCAN0RMDF148HH RSCAN0.RMDF148.UINT8[HH]
-#define RSCAN0RMID49 RSCAN0.RMID49.UINT32
-#define RSCAN0RMID49L RSCAN0.RMID49.UINT16[L]
-#define RSCAN0RMID49LL RSCAN0.RMID49.UINT8[LL]
-#define RSCAN0RMID49LH RSCAN0.RMID49.UINT8[LH]
-#define RSCAN0RMID49H RSCAN0.RMID49.UINT16[H]
-#define RSCAN0RMID49HL RSCAN0.RMID49.UINT8[HL]
-#define RSCAN0RMID49HH RSCAN0.RMID49.UINT8[HH]
-#define RSCAN0RMPTR49 RSCAN0.RMPTR49.UINT32
-#define RSCAN0RMPTR49L RSCAN0.RMPTR49.UINT16[L]
-#define RSCAN0RMPTR49LL RSCAN0.RMPTR49.UINT8[LL]
-#define RSCAN0RMPTR49LH RSCAN0.RMPTR49.UINT8[LH]
-#define RSCAN0RMPTR49H RSCAN0.RMPTR49.UINT16[H]
-#define RSCAN0RMPTR49HL RSCAN0.RMPTR49.UINT8[HL]
-#define RSCAN0RMPTR49HH RSCAN0.RMPTR49.UINT8[HH]
-#define RSCAN0RMDF049 RSCAN0.RMDF049.UINT32
-#define RSCAN0RMDF049L RSCAN0.RMDF049.UINT16[L]
-#define RSCAN0RMDF049LL RSCAN0.RMDF049.UINT8[LL]
-#define RSCAN0RMDF049LH RSCAN0.RMDF049.UINT8[LH]
-#define RSCAN0RMDF049H RSCAN0.RMDF049.UINT16[H]
-#define RSCAN0RMDF049HL RSCAN0.RMDF049.UINT8[HL]
-#define RSCAN0RMDF049HH RSCAN0.RMDF049.UINT8[HH]
-#define RSCAN0RMDF149 RSCAN0.RMDF149.UINT32
-#define RSCAN0RMDF149L RSCAN0.RMDF149.UINT16[L]
-#define RSCAN0RMDF149LL RSCAN0.RMDF149.UINT8[LL]
-#define RSCAN0RMDF149LH RSCAN0.RMDF149.UINT8[LH]
-#define RSCAN0RMDF149H RSCAN0.RMDF149.UINT16[H]
-#define RSCAN0RMDF149HL RSCAN0.RMDF149.UINT8[HL]
-#define RSCAN0RMDF149HH RSCAN0.RMDF149.UINT8[HH]
-#define RSCAN0RMID50 RSCAN0.RMID50.UINT32
-#define RSCAN0RMID50L RSCAN0.RMID50.UINT16[L]
-#define RSCAN0RMID50LL RSCAN0.RMID50.UINT8[LL]
-#define RSCAN0RMID50LH RSCAN0.RMID50.UINT8[LH]
-#define RSCAN0RMID50H RSCAN0.RMID50.UINT16[H]
-#define RSCAN0RMID50HL RSCAN0.RMID50.UINT8[HL]
-#define RSCAN0RMID50HH RSCAN0.RMID50.UINT8[HH]
-#define RSCAN0RMPTR50 RSCAN0.RMPTR50.UINT32
-#define RSCAN0RMPTR50L RSCAN0.RMPTR50.UINT16[L]
-#define RSCAN0RMPTR50LL RSCAN0.RMPTR50.UINT8[LL]
-#define RSCAN0RMPTR50LH RSCAN0.RMPTR50.UINT8[LH]
-#define RSCAN0RMPTR50H RSCAN0.RMPTR50.UINT16[H]
-#define RSCAN0RMPTR50HL RSCAN0.RMPTR50.UINT8[HL]
-#define RSCAN0RMPTR50HH RSCAN0.RMPTR50.UINT8[HH]
-#define RSCAN0RMDF050 RSCAN0.RMDF050.UINT32
-#define RSCAN0RMDF050L RSCAN0.RMDF050.UINT16[L]
-#define RSCAN0RMDF050LL RSCAN0.RMDF050.UINT8[LL]
-#define RSCAN0RMDF050LH RSCAN0.RMDF050.UINT8[LH]
-#define RSCAN0RMDF050H RSCAN0.RMDF050.UINT16[H]
-#define RSCAN0RMDF050HL RSCAN0.RMDF050.UINT8[HL]
-#define RSCAN0RMDF050HH RSCAN0.RMDF050.UINT8[HH]
-#define RSCAN0RMDF150 RSCAN0.RMDF150.UINT32
-#define RSCAN0RMDF150L RSCAN0.RMDF150.UINT16[L]
-#define RSCAN0RMDF150LL RSCAN0.RMDF150.UINT8[LL]
-#define RSCAN0RMDF150LH RSCAN0.RMDF150.UINT8[LH]
-#define RSCAN0RMDF150H RSCAN0.RMDF150.UINT16[H]
-#define RSCAN0RMDF150HL RSCAN0.RMDF150.UINT8[HL]
-#define RSCAN0RMDF150HH RSCAN0.RMDF150.UINT8[HH]
-#define RSCAN0RMID51 RSCAN0.RMID51.UINT32
-#define RSCAN0RMID51L RSCAN0.RMID51.UINT16[L]
-#define RSCAN0RMID51LL RSCAN0.RMID51.UINT8[LL]
-#define RSCAN0RMID51LH RSCAN0.RMID51.UINT8[LH]
-#define RSCAN0RMID51H RSCAN0.RMID51.UINT16[H]
-#define RSCAN0RMID51HL RSCAN0.RMID51.UINT8[HL]
-#define RSCAN0RMID51HH RSCAN0.RMID51.UINT8[HH]
-#define RSCAN0RMPTR51 RSCAN0.RMPTR51.UINT32
-#define RSCAN0RMPTR51L RSCAN0.RMPTR51.UINT16[L]
-#define RSCAN0RMPTR51LL RSCAN0.RMPTR51.UINT8[LL]
-#define RSCAN0RMPTR51LH RSCAN0.RMPTR51.UINT8[LH]
-#define RSCAN0RMPTR51H RSCAN0.RMPTR51.UINT16[H]
-#define RSCAN0RMPTR51HL RSCAN0.RMPTR51.UINT8[HL]
-#define RSCAN0RMPTR51HH RSCAN0.RMPTR51.UINT8[HH]
-#define RSCAN0RMDF051 RSCAN0.RMDF051.UINT32
-#define RSCAN0RMDF051L RSCAN0.RMDF051.UINT16[L]
-#define RSCAN0RMDF051LL RSCAN0.RMDF051.UINT8[LL]
-#define RSCAN0RMDF051LH RSCAN0.RMDF051.UINT8[LH]
-#define RSCAN0RMDF051H RSCAN0.RMDF051.UINT16[H]
-#define RSCAN0RMDF051HL RSCAN0.RMDF051.UINT8[HL]
-#define RSCAN0RMDF051HH RSCAN0.RMDF051.UINT8[HH]
-#define RSCAN0RMDF151 RSCAN0.RMDF151.UINT32
-#define RSCAN0RMDF151L RSCAN0.RMDF151.UINT16[L]
-#define RSCAN0RMDF151LL RSCAN0.RMDF151.UINT8[LL]
-#define RSCAN0RMDF151LH RSCAN0.RMDF151.UINT8[LH]
-#define RSCAN0RMDF151H RSCAN0.RMDF151.UINT16[H]
-#define RSCAN0RMDF151HL RSCAN0.RMDF151.UINT8[HL]
-#define RSCAN0RMDF151HH RSCAN0.RMDF151.UINT8[HH]
-#define RSCAN0RMID52 RSCAN0.RMID52.UINT32
-#define RSCAN0RMID52L RSCAN0.RMID52.UINT16[L]
-#define RSCAN0RMID52LL RSCAN0.RMID52.UINT8[LL]
-#define RSCAN0RMID52LH RSCAN0.RMID52.UINT8[LH]
-#define RSCAN0RMID52H RSCAN0.RMID52.UINT16[H]
-#define RSCAN0RMID52HL RSCAN0.RMID52.UINT8[HL]
-#define RSCAN0RMID52HH RSCAN0.RMID52.UINT8[HH]
-#define RSCAN0RMPTR52 RSCAN0.RMPTR52.UINT32
-#define RSCAN0RMPTR52L RSCAN0.RMPTR52.UINT16[L]
-#define RSCAN0RMPTR52LL RSCAN0.RMPTR52.UINT8[LL]
-#define RSCAN0RMPTR52LH RSCAN0.RMPTR52.UINT8[LH]
-#define RSCAN0RMPTR52H RSCAN0.RMPTR52.UINT16[H]
-#define RSCAN0RMPTR52HL RSCAN0.RMPTR52.UINT8[HL]
-#define RSCAN0RMPTR52HH RSCAN0.RMPTR52.UINT8[HH]
-#define RSCAN0RMDF052 RSCAN0.RMDF052.UINT32
-#define RSCAN0RMDF052L RSCAN0.RMDF052.UINT16[L]
-#define RSCAN0RMDF052LL RSCAN0.RMDF052.UINT8[LL]
-#define RSCAN0RMDF052LH RSCAN0.RMDF052.UINT8[LH]
-#define RSCAN0RMDF052H RSCAN0.RMDF052.UINT16[H]
-#define RSCAN0RMDF052HL RSCAN0.RMDF052.UINT8[HL]
-#define RSCAN0RMDF052HH RSCAN0.RMDF052.UINT8[HH]
-#define RSCAN0RMDF152 RSCAN0.RMDF152.UINT32
-#define RSCAN0RMDF152L RSCAN0.RMDF152.UINT16[L]
-#define RSCAN0RMDF152LL RSCAN0.RMDF152.UINT8[LL]
-#define RSCAN0RMDF152LH RSCAN0.RMDF152.UINT8[LH]
-#define RSCAN0RMDF152H RSCAN0.RMDF152.UINT16[H]
-#define RSCAN0RMDF152HL RSCAN0.RMDF152.UINT8[HL]
-#define RSCAN0RMDF152HH RSCAN0.RMDF152.UINT8[HH]
-#define RSCAN0RMID53 RSCAN0.RMID53.UINT32
-#define RSCAN0RMID53L RSCAN0.RMID53.UINT16[L]
-#define RSCAN0RMID53LL RSCAN0.RMID53.UINT8[LL]
-#define RSCAN0RMID53LH RSCAN0.RMID53.UINT8[LH]
-#define RSCAN0RMID53H RSCAN0.RMID53.UINT16[H]
-#define RSCAN0RMID53HL RSCAN0.RMID53.UINT8[HL]
-#define RSCAN0RMID53HH RSCAN0.RMID53.UINT8[HH]
-#define RSCAN0RMPTR53 RSCAN0.RMPTR53.UINT32
-#define RSCAN0RMPTR53L RSCAN0.RMPTR53.UINT16[L]
-#define RSCAN0RMPTR53LL RSCAN0.RMPTR53.UINT8[LL]
-#define RSCAN0RMPTR53LH RSCAN0.RMPTR53.UINT8[LH]
-#define RSCAN0RMPTR53H RSCAN0.RMPTR53.UINT16[H]
-#define RSCAN0RMPTR53HL RSCAN0.RMPTR53.UINT8[HL]
-#define RSCAN0RMPTR53HH RSCAN0.RMPTR53.UINT8[HH]
-#define RSCAN0RMDF053 RSCAN0.RMDF053.UINT32
-#define RSCAN0RMDF053L RSCAN0.RMDF053.UINT16[L]
-#define RSCAN0RMDF053LL RSCAN0.RMDF053.UINT8[LL]
-#define RSCAN0RMDF053LH RSCAN0.RMDF053.UINT8[LH]
-#define RSCAN0RMDF053H RSCAN0.RMDF053.UINT16[H]
-#define RSCAN0RMDF053HL RSCAN0.RMDF053.UINT8[HL]
-#define RSCAN0RMDF053HH RSCAN0.RMDF053.UINT8[HH]
-#define RSCAN0RMDF153 RSCAN0.RMDF153.UINT32
-#define RSCAN0RMDF153L RSCAN0.RMDF153.UINT16[L]
-#define RSCAN0RMDF153LL RSCAN0.RMDF153.UINT8[LL]
-#define RSCAN0RMDF153LH RSCAN0.RMDF153.UINT8[LH]
-#define RSCAN0RMDF153H RSCAN0.RMDF153.UINT16[H]
-#define RSCAN0RMDF153HL RSCAN0.RMDF153.UINT8[HL]
-#define RSCAN0RMDF153HH RSCAN0.RMDF153.UINT8[HH]
-#define RSCAN0RMID54 RSCAN0.RMID54.UINT32
-#define RSCAN0RMID54L RSCAN0.RMID54.UINT16[L]
-#define RSCAN0RMID54LL RSCAN0.RMID54.UINT8[LL]
-#define RSCAN0RMID54LH RSCAN0.RMID54.UINT8[LH]
-#define RSCAN0RMID54H RSCAN0.RMID54.UINT16[H]
-#define RSCAN0RMID54HL RSCAN0.RMID54.UINT8[HL]
-#define RSCAN0RMID54HH RSCAN0.RMID54.UINT8[HH]
-#define RSCAN0RMPTR54 RSCAN0.RMPTR54.UINT32
-#define RSCAN0RMPTR54L RSCAN0.RMPTR54.UINT16[L]
-#define RSCAN0RMPTR54LL RSCAN0.RMPTR54.UINT8[LL]
-#define RSCAN0RMPTR54LH RSCAN0.RMPTR54.UINT8[LH]
-#define RSCAN0RMPTR54H RSCAN0.RMPTR54.UINT16[H]
-#define RSCAN0RMPTR54HL RSCAN0.RMPTR54.UINT8[HL]
-#define RSCAN0RMPTR54HH RSCAN0.RMPTR54.UINT8[HH]
-#define RSCAN0RMDF054 RSCAN0.RMDF054.UINT32
-#define RSCAN0RMDF054L RSCAN0.RMDF054.UINT16[L]
-#define RSCAN0RMDF054LL RSCAN0.RMDF054.UINT8[LL]
-#define RSCAN0RMDF054LH RSCAN0.RMDF054.UINT8[LH]
-#define RSCAN0RMDF054H RSCAN0.RMDF054.UINT16[H]
-#define RSCAN0RMDF054HL RSCAN0.RMDF054.UINT8[HL]
-#define RSCAN0RMDF054HH RSCAN0.RMDF054.UINT8[HH]
-#define RSCAN0RMDF154 RSCAN0.RMDF154.UINT32
-#define RSCAN0RMDF154L RSCAN0.RMDF154.UINT16[L]
-#define RSCAN0RMDF154LL RSCAN0.RMDF154.UINT8[LL]
-#define RSCAN0RMDF154LH RSCAN0.RMDF154.UINT8[LH]
-#define RSCAN0RMDF154H RSCAN0.RMDF154.UINT16[H]
-#define RSCAN0RMDF154HL RSCAN0.RMDF154.UINT8[HL]
-#define RSCAN0RMDF154HH RSCAN0.RMDF154.UINT8[HH]
-#define RSCAN0RMID55 RSCAN0.RMID55.UINT32
-#define RSCAN0RMID55L RSCAN0.RMID55.UINT16[L]
-#define RSCAN0RMID55LL RSCAN0.RMID55.UINT8[LL]
-#define RSCAN0RMID55LH RSCAN0.RMID55.UINT8[LH]
-#define RSCAN0RMID55H RSCAN0.RMID55.UINT16[H]
-#define RSCAN0RMID55HL RSCAN0.RMID55.UINT8[HL]
-#define RSCAN0RMID55HH RSCAN0.RMID55.UINT8[HH]
-#define RSCAN0RMPTR55 RSCAN0.RMPTR55.UINT32
-#define RSCAN0RMPTR55L RSCAN0.RMPTR55.UINT16[L]
-#define RSCAN0RMPTR55LL RSCAN0.RMPTR55.UINT8[LL]
-#define RSCAN0RMPTR55LH RSCAN0.RMPTR55.UINT8[LH]
-#define RSCAN0RMPTR55H RSCAN0.RMPTR55.UINT16[H]
-#define RSCAN0RMPTR55HL RSCAN0.RMPTR55.UINT8[HL]
-#define RSCAN0RMPTR55HH RSCAN0.RMPTR55.UINT8[HH]
-#define RSCAN0RMDF055 RSCAN0.RMDF055.UINT32
-#define RSCAN0RMDF055L RSCAN0.RMDF055.UINT16[L]
-#define RSCAN0RMDF055LL RSCAN0.RMDF055.UINT8[LL]
-#define RSCAN0RMDF055LH RSCAN0.RMDF055.UINT8[LH]
-#define RSCAN0RMDF055H RSCAN0.RMDF055.UINT16[H]
-#define RSCAN0RMDF055HL RSCAN0.RMDF055.UINT8[HL]
-#define RSCAN0RMDF055HH RSCAN0.RMDF055.UINT8[HH]
-#define RSCAN0RMDF155 RSCAN0.RMDF155.UINT32
-#define RSCAN0RMDF155L RSCAN0.RMDF155.UINT16[L]
-#define RSCAN0RMDF155LL RSCAN0.RMDF155.UINT8[LL]
-#define RSCAN0RMDF155LH RSCAN0.RMDF155.UINT8[LH]
-#define RSCAN0RMDF155H RSCAN0.RMDF155.UINT16[H]
-#define RSCAN0RMDF155HL RSCAN0.RMDF155.UINT8[HL]
-#define RSCAN0RMDF155HH RSCAN0.RMDF155.UINT8[HH]
-#define RSCAN0RMID56 RSCAN0.RMID56.UINT32
-#define RSCAN0RMID56L RSCAN0.RMID56.UINT16[L]
-#define RSCAN0RMID56LL RSCAN0.RMID56.UINT8[LL]
-#define RSCAN0RMID56LH RSCAN0.RMID56.UINT8[LH]
-#define RSCAN0RMID56H RSCAN0.RMID56.UINT16[H]
-#define RSCAN0RMID56HL RSCAN0.RMID56.UINT8[HL]
-#define RSCAN0RMID56HH RSCAN0.RMID56.UINT8[HH]
-#define RSCAN0RMPTR56 RSCAN0.RMPTR56.UINT32
-#define RSCAN0RMPTR56L RSCAN0.RMPTR56.UINT16[L]
-#define RSCAN0RMPTR56LL RSCAN0.RMPTR56.UINT8[LL]
-#define RSCAN0RMPTR56LH RSCAN0.RMPTR56.UINT8[LH]
-#define RSCAN0RMPTR56H RSCAN0.RMPTR56.UINT16[H]
-#define RSCAN0RMPTR56HL RSCAN0.RMPTR56.UINT8[HL]
-#define RSCAN0RMPTR56HH RSCAN0.RMPTR56.UINT8[HH]
-#define RSCAN0RMDF056 RSCAN0.RMDF056.UINT32
-#define RSCAN0RMDF056L RSCAN0.RMDF056.UINT16[L]
-#define RSCAN0RMDF056LL RSCAN0.RMDF056.UINT8[LL]
-#define RSCAN0RMDF056LH RSCAN0.RMDF056.UINT8[LH]
-#define RSCAN0RMDF056H RSCAN0.RMDF056.UINT16[H]
-#define RSCAN0RMDF056HL RSCAN0.RMDF056.UINT8[HL]
-#define RSCAN0RMDF056HH RSCAN0.RMDF056.UINT8[HH]
-#define RSCAN0RMDF156 RSCAN0.RMDF156.UINT32
-#define RSCAN0RMDF156L RSCAN0.RMDF156.UINT16[L]
-#define RSCAN0RMDF156LL RSCAN0.RMDF156.UINT8[LL]
-#define RSCAN0RMDF156LH RSCAN0.RMDF156.UINT8[LH]
-#define RSCAN0RMDF156H RSCAN0.RMDF156.UINT16[H]
-#define RSCAN0RMDF156HL RSCAN0.RMDF156.UINT8[HL]
-#define RSCAN0RMDF156HH RSCAN0.RMDF156.UINT8[HH]
-#define RSCAN0RMID57 RSCAN0.RMID57.UINT32
-#define RSCAN0RMID57L RSCAN0.RMID57.UINT16[L]
-#define RSCAN0RMID57LL RSCAN0.RMID57.UINT8[LL]
-#define RSCAN0RMID57LH RSCAN0.RMID57.UINT8[LH]
-#define RSCAN0RMID57H RSCAN0.RMID57.UINT16[H]
-#define RSCAN0RMID57HL RSCAN0.RMID57.UINT8[HL]
-#define RSCAN0RMID57HH RSCAN0.RMID57.UINT8[HH]
-#define RSCAN0RMPTR57 RSCAN0.RMPTR57.UINT32
-#define RSCAN0RMPTR57L RSCAN0.RMPTR57.UINT16[L]
-#define RSCAN0RMPTR57LL RSCAN0.RMPTR57.UINT8[LL]
-#define RSCAN0RMPTR57LH RSCAN0.RMPTR57.UINT8[LH]
-#define RSCAN0RMPTR57H RSCAN0.RMPTR57.UINT16[H]
-#define RSCAN0RMPTR57HL RSCAN0.RMPTR57.UINT8[HL]
-#define RSCAN0RMPTR57HH RSCAN0.RMPTR57.UINT8[HH]
-#define RSCAN0RMDF057 RSCAN0.RMDF057.UINT32
-#define RSCAN0RMDF057L RSCAN0.RMDF057.UINT16[L]
-#define RSCAN0RMDF057LL RSCAN0.RMDF057.UINT8[LL]
-#define RSCAN0RMDF057LH RSCAN0.RMDF057.UINT8[LH]
-#define RSCAN0RMDF057H RSCAN0.RMDF057.UINT16[H]
-#define RSCAN0RMDF057HL RSCAN0.RMDF057.UINT8[HL]
-#define RSCAN0RMDF057HH RSCAN0.RMDF057.UINT8[HH]
-#define RSCAN0RMDF157 RSCAN0.RMDF157.UINT32
-#define RSCAN0RMDF157L RSCAN0.RMDF157.UINT16[L]
-#define RSCAN0RMDF157LL RSCAN0.RMDF157.UINT8[LL]
-#define RSCAN0RMDF157LH RSCAN0.RMDF157.UINT8[LH]
-#define RSCAN0RMDF157H RSCAN0.RMDF157.UINT16[H]
-#define RSCAN0RMDF157HL RSCAN0.RMDF157.UINT8[HL]
-#define RSCAN0RMDF157HH RSCAN0.RMDF157.UINT8[HH]
-#define RSCAN0RMID58 RSCAN0.RMID58.UINT32
-#define RSCAN0RMID58L RSCAN0.RMID58.UINT16[L]
-#define RSCAN0RMID58LL RSCAN0.RMID58.UINT8[LL]
-#define RSCAN0RMID58LH RSCAN0.RMID58.UINT8[LH]
-#define RSCAN0RMID58H RSCAN0.RMID58.UINT16[H]
-#define RSCAN0RMID58HL RSCAN0.RMID58.UINT8[HL]
-#define RSCAN0RMID58HH RSCAN0.RMID58.UINT8[HH]
-#define RSCAN0RMPTR58 RSCAN0.RMPTR58.UINT32
-#define RSCAN0RMPTR58L RSCAN0.RMPTR58.UINT16[L]
-#define RSCAN0RMPTR58LL RSCAN0.RMPTR58.UINT8[LL]
-#define RSCAN0RMPTR58LH RSCAN0.RMPTR58.UINT8[LH]
-#define RSCAN0RMPTR58H RSCAN0.RMPTR58.UINT16[H]
-#define RSCAN0RMPTR58HL RSCAN0.RMPTR58.UINT8[HL]
-#define RSCAN0RMPTR58HH RSCAN0.RMPTR58.UINT8[HH]
-#define RSCAN0RMDF058 RSCAN0.RMDF058.UINT32
-#define RSCAN0RMDF058L RSCAN0.RMDF058.UINT16[L]
-#define RSCAN0RMDF058LL RSCAN0.RMDF058.UINT8[LL]
-#define RSCAN0RMDF058LH RSCAN0.RMDF058.UINT8[LH]
-#define RSCAN0RMDF058H RSCAN0.RMDF058.UINT16[H]
-#define RSCAN0RMDF058HL RSCAN0.RMDF058.UINT8[HL]
-#define RSCAN0RMDF058HH RSCAN0.RMDF058.UINT8[HH]
-#define RSCAN0RMDF158 RSCAN0.RMDF158.UINT32
-#define RSCAN0RMDF158L RSCAN0.RMDF158.UINT16[L]
-#define RSCAN0RMDF158LL RSCAN0.RMDF158.UINT8[LL]
-#define RSCAN0RMDF158LH RSCAN0.RMDF158.UINT8[LH]
-#define RSCAN0RMDF158H RSCAN0.RMDF158.UINT16[H]
-#define RSCAN0RMDF158HL RSCAN0.RMDF158.UINT8[HL]
-#define RSCAN0RMDF158HH RSCAN0.RMDF158.UINT8[HH]
-#define RSCAN0RMID59 RSCAN0.RMID59.UINT32
-#define RSCAN0RMID59L RSCAN0.RMID59.UINT16[L]
-#define RSCAN0RMID59LL RSCAN0.RMID59.UINT8[LL]
-#define RSCAN0RMID59LH RSCAN0.RMID59.UINT8[LH]
-#define RSCAN0RMID59H RSCAN0.RMID59.UINT16[H]
-#define RSCAN0RMID59HL RSCAN0.RMID59.UINT8[HL]
-#define RSCAN0RMID59HH RSCAN0.RMID59.UINT8[HH]
-#define RSCAN0RMPTR59 RSCAN0.RMPTR59.UINT32
-#define RSCAN0RMPTR59L RSCAN0.RMPTR59.UINT16[L]
-#define RSCAN0RMPTR59LL RSCAN0.RMPTR59.UINT8[LL]
-#define RSCAN0RMPTR59LH RSCAN0.RMPTR59.UINT8[LH]
-#define RSCAN0RMPTR59H RSCAN0.RMPTR59.UINT16[H]
-#define RSCAN0RMPTR59HL RSCAN0.RMPTR59.UINT8[HL]
-#define RSCAN0RMPTR59HH RSCAN0.RMPTR59.UINT8[HH]
-#define RSCAN0RMDF059 RSCAN0.RMDF059.UINT32
-#define RSCAN0RMDF059L RSCAN0.RMDF059.UINT16[L]
-#define RSCAN0RMDF059LL RSCAN0.RMDF059.UINT8[LL]
-#define RSCAN0RMDF059LH RSCAN0.RMDF059.UINT8[LH]
-#define RSCAN0RMDF059H RSCAN0.RMDF059.UINT16[H]
-#define RSCAN0RMDF059HL RSCAN0.RMDF059.UINT8[HL]
-#define RSCAN0RMDF059HH RSCAN0.RMDF059.UINT8[HH]
-#define RSCAN0RMDF159 RSCAN0.RMDF159.UINT32
-#define RSCAN0RMDF159L RSCAN0.RMDF159.UINT16[L]
-#define RSCAN0RMDF159LL RSCAN0.RMDF159.UINT8[LL]
-#define RSCAN0RMDF159LH RSCAN0.RMDF159.UINT8[LH]
-#define RSCAN0RMDF159H RSCAN0.RMDF159.UINT16[H]
-#define RSCAN0RMDF159HL RSCAN0.RMDF159.UINT8[HL]
-#define RSCAN0RMDF159HH RSCAN0.RMDF159.UINT8[HH]
-#define RSCAN0RMID60 RSCAN0.RMID60.UINT32
-#define RSCAN0RMID60L RSCAN0.RMID60.UINT16[L]
-#define RSCAN0RMID60LL RSCAN0.RMID60.UINT8[LL]
-#define RSCAN0RMID60LH RSCAN0.RMID60.UINT8[LH]
-#define RSCAN0RMID60H RSCAN0.RMID60.UINT16[H]
-#define RSCAN0RMID60HL RSCAN0.RMID60.UINT8[HL]
-#define RSCAN0RMID60HH RSCAN0.RMID60.UINT8[HH]
-#define RSCAN0RMPTR60 RSCAN0.RMPTR60.UINT32
-#define RSCAN0RMPTR60L RSCAN0.RMPTR60.UINT16[L]
-#define RSCAN0RMPTR60LL RSCAN0.RMPTR60.UINT8[LL]
-#define RSCAN0RMPTR60LH RSCAN0.RMPTR60.UINT8[LH]
-#define RSCAN0RMPTR60H RSCAN0.RMPTR60.UINT16[H]
-#define RSCAN0RMPTR60HL RSCAN0.RMPTR60.UINT8[HL]
-#define RSCAN0RMPTR60HH RSCAN0.RMPTR60.UINT8[HH]
-#define RSCAN0RMDF060 RSCAN0.RMDF060.UINT32
-#define RSCAN0RMDF060L RSCAN0.RMDF060.UINT16[L]
-#define RSCAN0RMDF060LL RSCAN0.RMDF060.UINT8[LL]
-#define RSCAN0RMDF060LH RSCAN0.RMDF060.UINT8[LH]
-#define RSCAN0RMDF060H RSCAN0.RMDF060.UINT16[H]
-#define RSCAN0RMDF060HL RSCAN0.RMDF060.UINT8[HL]
-#define RSCAN0RMDF060HH RSCAN0.RMDF060.UINT8[HH]
-#define RSCAN0RMDF160 RSCAN0.RMDF160.UINT32
-#define RSCAN0RMDF160L RSCAN0.RMDF160.UINT16[L]
-#define RSCAN0RMDF160LL RSCAN0.RMDF160.UINT8[LL]
-#define RSCAN0RMDF160LH RSCAN0.RMDF160.UINT8[LH]
-#define RSCAN0RMDF160H RSCAN0.RMDF160.UINT16[H]
-#define RSCAN0RMDF160HL RSCAN0.RMDF160.UINT8[HL]
-#define RSCAN0RMDF160HH RSCAN0.RMDF160.UINT8[HH]
-#define RSCAN0RMID61 RSCAN0.RMID61.UINT32
-#define RSCAN0RMID61L RSCAN0.RMID61.UINT16[L]
-#define RSCAN0RMID61LL RSCAN0.RMID61.UINT8[LL]
-#define RSCAN0RMID61LH RSCAN0.RMID61.UINT8[LH]
-#define RSCAN0RMID61H RSCAN0.RMID61.UINT16[H]
-#define RSCAN0RMID61HL RSCAN0.RMID61.UINT8[HL]
-#define RSCAN0RMID61HH RSCAN0.RMID61.UINT8[HH]
-#define RSCAN0RMPTR61 RSCAN0.RMPTR61.UINT32
-#define RSCAN0RMPTR61L RSCAN0.RMPTR61.UINT16[L]
-#define RSCAN0RMPTR61LL RSCAN0.RMPTR61.UINT8[LL]
-#define RSCAN0RMPTR61LH RSCAN0.RMPTR61.UINT8[LH]
-#define RSCAN0RMPTR61H RSCAN0.RMPTR61.UINT16[H]
-#define RSCAN0RMPTR61HL RSCAN0.RMPTR61.UINT8[HL]
-#define RSCAN0RMPTR61HH RSCAN0.RMPTR61.UINT8[HH]
-#define RSCAN0RMDF061 RSCAN0.RMDF061.UINT32
-#define RSCAN0RMDF061L RSCAN0.RMDF061.UINT16[L]
-#define RSCAN0RMDF061LL RSCAN0.RMDF061.UINT8[LL]
-#define RSCAN0RMDF061LH RSCAN0.RMDF061.UINT8[LH]
-#define RSCAN0RMDF061H RSCAN0.RMDF061.UINT16[H]
-#define RSCAN0RMDF061HL RSCAN0.RMDF061.UINT8[HL]
-#define RSCAN0RMDF061HH RSCAN0.RMDF061.UINT8[HH]
-#define RSCAN0RMDF161 RSCAN0.RMDF161.UINT32
-#define RSCAN0RMDF161L RSCAN0.RMDF161.UINT16[L]
-#define RSCAN0RMDF161LL RSCAN0.RMDF161.UINT8[LL]
-#define RSCAN0RMDF161LH RSCAN0.RMDF161.UINT8[LH]
-#define RSCAN0RMDF161H RSCAN0.RMDF161.UINT16[H]
-#define RSCAN0RMDF161HL RSCAN0.RMDF161.UINT8[HL]
-#define RSCAN0RMDF161HH RSCAN0.RMDF161.UINT8[HH]
-#define RSCAN0RMID62 RSCAN0.RMID62.UINT32
-#define RSCAN0RMID62L RSCAN0.RMID62.UINT16[L]
-#define RSCAN0RMID62LL RSCAN0.RMID62.UINT8[LL]
-#define RSCAN0RMID62LH RSCAN0.RMID62.UINT8[LH]
-#define RSCAN0RMID62H RSCAN0.RMID62.UINT16[H]
-#define RSCAN0RMID62HL RSCAN0.RMID62.UINT8[HL]
-#define RSCAN0RMID62HH RSCAN0.RMID62.UINT8[HH]
-#define RSCAN0RMPTR62 RSCAN0.RMPTR62.UINT32
-#define RSCAN0RMPTR62L RSCAN0.RMPTR62.UINT16[L]
-#define RSCAN0RMPTR62LL RSCAN0.RMPTR62.UINT8[LL]
-#define RSCAN0RMPTR62LH RSCAN0.RMPTR62.UINT8[LH]
-#define RSCAN0RMPTR62H RSCAN0.RMPTR62.UINT16[H]
-#define RSCAN0RMPTR62HL RSCAN0.RMPTR62.UINT8[HL]
-#define RSCAN0RMPTR62HH RSCAN0.RMPTR62.UINT8[HH]
-#define RSCAN0RMDF062 RSCAN0.RMDF062.UINT32
-#define RSCAN0RMDF062L RSCAN0.RMDF062.UINT16[L]
-#define RSCAN0RMDF062LL RSCAN0.RMDF062.UINT8[LL]
-#define RSCAN0RMDF062LH RSCAN0.RMDF062.UINT8[LH]
-#define RSCAN0RMDF062H RSCAN0.RMDF062.UINT16[H]
-#define RSCAN0RMDF062HL RSCAN0.RMDF062.UINT8[HL]
-#define RSCAN0RMDF062HH RSCAN0.RMDF062.UINT8[HH]
-#define RSCAN0RMDF162 RSCAN0.RMDF162.UINT32
-#define RSCAN0RMDF162L RSCAN0.RMDF162.UINT16[L]
-#define RSCAN0RMDF162LL RSCAN0.RMDF162.UINT8[LL]
-#define RSCAN0RMDF162LH RSCAN0.RMDF162.UINT8[LH]
-#define RSCAN0RMDF162H RSCAN0.RMDF162.UINT16[H]
-#define RSCAN0RMDF162HL RSCAN0.RMDF162.UINT8[HL]
-#define RSCAN0RMDF162HH RSCAN0.RMDF162.UINT8[HH]
-#define RSCAN0RMID63 RSCAN0.RMID63.UINT32
-#define RSCAN0RMID63L RSCAN0.RMID63.UINT16[L]
-#define RSCAN0RMID63LL RSCAN0.RMID63.UINT8[LL]
-#define RSCAN0RMID63LH RSCAN0.RMID63.UINT8[LH]
-#define RSCAN0RMID63H RSCAN0.RMID63.UINT16[H]
-#define RSCAN0RMID63HL RSCAN0.RMID63.UINT8[HL]
-#define RSCAN0RMID63HH RSCAN0.RMID63.UINT8[HH]
-#define RSCAN0RMPTR63 RSCAN0.RMPTR63.UINT32
-#define RSCAN0RMPTR63L RSCAN0.RMPTR63.UINT16[L]
-#define RSCAN0RMPTR63LL RSCAN0.RMPTR63.UINT8[LL]
-#define RSCAN0RMPTR63LH RSCAN0.RMPTR63.UINT8[LH]
-#define RSCAN0RMPTR63H RSCAN0.RMPTR63.UINT16[H]
-#define RSCAN0RMPTR63HL RSCAN0.RMPTR63.UINT8[HL]
-#define RSCAN0RMPTR63HH RSCAN0.RMPTR63.UINT8[HH]
-#define RSCAN0RMDF063 RSCAN0.RMDF063.UINT32
-#define RSCAN0RMDF063L RSCAN0.RMDF063.UINT16[L]
-#define RSCAN0RMDF063LL RSCAN0.RMDF063.UINT8[LL]
-#define RSCAN0RMDF063LH RSCAN0.RMDF063.UINT8[LH]
-#define RSCAN0RMDF063H RSCAN0.RMDF063.UINT16[H]
-#define RSCAN0RMDF063HL RSCAN0.RMDF063.UINT8[HL]
-#define RSCAN0RMDF063HH RSCAN0.RMDF063.UINT8[HH]
-#define RSCAN0RMDF163 RSCAN0.RMDF163.UINT32
-#define RSCAN0RMDF163L RSCAN0.RMDF163.UINT16[L]
-#define RSCAN0RMDF163LL RSCAN0.RMDF163.UINT8[LL]
-#define RSCAN0RMDF163LH RSCAN0.RMDF163.UINT8[LH]
-#define RSCAN0RMDF163H RSCAN0.RMDF163.UINT16[H]
-#define RSCAN0RMDF163HL RSCAN0.RMDF163.UINT8[HL]
-#define RSCAN0RMDF163HH RSCAN0.RMDF163.UINT8[HH]
-#define RSCAN0RMID64 RSCAN0.RMID64.UINT32
-#define RSCAN0RMID64L RSCAN0.RMID64.UINT16[L]
-#define RSCAN0RMID64LL RSCAN0.RMID64.UINT8[LL]
-#define RSCAN0RMID64LH RSCAN0.RMID64.UINT8[LH]
-#define RSCAN0RMID64H RSCAN0.RMID64.UINT16[H]
-#define RSCAN0RMID64HL RSCAN0.RMID64.UINT8[HL]
-#define RSCAN0RMID64HH RSCAN0.RMID64.UINT8[HH]
-#define RSCAN0RMPTR64 RSCAN0.RMPTR64.UINT32
-#define RSCAN0RMPTR64L RSCAN0.RMPTR64.UINT16[L]
-#define RSCAN0RMPTR64LL RSCAN0.RMPTR64.UINT8[LL]
-#define RSCAN0RMPTR64LH RSCAN0.RMPTR64.UINT8[LH]
-#define RSCAN0RMPTR64H RSCAN0.RMPTR64.UINT16[H]
-#define RSCAN0RMPTR64HL RSCAN0.RMPTR64.UINT8[HL]
-#define RSCAN0RMPTR64HH RSCAN0.RMPTR64.UINT8[HH]
-#define RSCAN0RMDF064 RSCAN0.RMDF064.UINT32
-#define RSCAN0RMDF064L RSCAN0.RMDF064.UINT16[L]
-#define RSCAN0RMDF064LL RSCAN0.RMDF064.UINT8[LL]
-#define RSCAN0RMDF064LH RSCAN0.RMDF064.UINT8[LH]
-#define RSCAN0RMDF064H RSCAN0.RMDF064.UINT16[H]
-#define RSCAN0RMDF064HL RSCAN0.RMDF064.UINT8[HL]
-#define RSCAN0RMDF064HH RSCAN0.RMDF064.UINT8[HH]
-#define RSCAN0RMDF164 RSCAN0.RMDF164.UINT32
-#define RSCAN0RMDF164L RSCAN0.RMDF164.UINT16[L]
-#define RSCAN0RMDF164LL RSCAN0.RMDF164.UINT8[LL]
-#define RSCAN0RMDF164LH RSCAN0.RMDF164.UINT8[LH]
-#define RSCAN0RMDF164H RSCAN0.RMDF164.UINT16[H]
-#define RSCAN0RMDF164HL RSCAN0.RMDF164.UINT8[HL]
-#define RSCAN0RMDF164HH RSCAN0.RMDF164.UINT8[HH]
-#define RSCAN0RMID65 RSCAN0.RMID65.UINT32
-#define RSCAN0RMID65L RSCAN0.RMID65.UINT16[L]
-#define RSCAN0RMID65LL RSCAN0.RMID65.UINT8[LL]
-#define RSCAN0RMID65LH RSCAN0.RMID65.UINT8[LH]
-#define RSCAN0RMID65H RSCAN0.RMID65.UINT16[H]
-#define RSCAN0RMID65HL RSCAN0.RMID65.UINT8[HL]
-#define RSCAN0RMID65HH RSCAN0.RMID65.UINT8[HH]
-#define RSCAN0RMPTR65 RSCAN0.RMPTR65.UINT32
-#define RSCAN0RMPTR65L RSCAN0.RMPTR65.UINT16[L]
-#define RSCAN0RMPTR65LL RSCAN0.RMPTR65.UINT8[LL]
-#define RSCAN0RMPTR65LH RSCAN0.RMPTR65.UINT8[LH]
-#define RSCAN0RMPTR65H RSCAN0.RMPTR65.UINT16[H]
-#define RSCAN0RMPTR65HL RSCAN0.RMPTR65.UINT8[HL]
-#define RSCAN0RMPTR65HH RSCAN0.RMPTR65.UINT8[HH]
-#define RSCAN0RMDF065 RSCAN0.RMDF065.UINT32
-#define RSCAN0RMDF065L RSCAN0.RMDF065.UINT16[L]
-#define RSCAN0RMDF065LL RSCAN0.RMDF065.UINT8[LL]
-#define RSCAN0RMDF065LH RSCAN0.RMDF065.UINT8[LH]
-#define RSCAN0RMDF065H RSCAN0.RMDF065.UINT16[H]
-#define RSCAN0RMDF065HL RSCAN0.RMDF065.UINT8[HL]
-#define RSCAN0RMDF065HH RSCAN0.RMDF065.UINT8[HH]
-#define RSCAN0RMDF165 RSCAN0.RMDF165.UINT32
-#define RSCAN0RMDF165L RSCAN0.RMDF165.UINT16[L]
-#define RSCAN0RMDF165LL RSCAN0.RMDF165.UINT8[LL]
-#define RSCAN0RMDF165LH RSCAN0.RMDF165.UINT8[LH]
-#define RSCAN0RMDF165H RSCAN0.RMDF165.UINT16[H]
-#define RSCAN0RMDF165HL RSCAN0.RMDF165.UINT8[HL]
-#define RSCAN0RMDF165HH RSCAN0.RMDF165.UINT8[HH]
-#define RSCAN0RMID66 RSCAN0.RMID66.UINT32
-#define RSCAN0RMID66L RSCAN0.RMID66.UINT16[L]
-#define RSCAN0RMID66LL RSCAN0.RMID66.UINT8[LL]
-#define RSCAN0RMID66LH RSCAN0.RMID66.UINT8[LH]
-#define RSCAN0RMID66H RSCAN0.RMID66.UINT16[H]
-#define RSCAN0RMID66HL RSCAN0.RMID66.UINT8[HL]
-#define RSCAN0RMID66HH RSCAN0.RMID66.UINT8[HH]
-#define RSCAN0RMPTR66 RSCAN0.RMPTR66.UINT32
-#define RSCAN0RMPTR66L RSCAN0.RMPTR66.UINT16[L]
-#define RSCAN0RMPTR66LL RSCAN0.RMPTR66.UINT8[LL]
-#define RSCAN0RMPTR66LH RSCAN0.RMPTR66.UINT8[LH]
-#define RSCAN0RMPTR66H RSCAN0.RMPTR66.UINT16[H]
-#define RSCAN0RMPTR66HL RSCAN0.RMPTR66.UINT8[HL]
-#define RSCAN0RMPTR66HH RSCAN0.RMPTR66.UINT8[HH]
-#define RSCAN0RMDF066 RSCAN0.RMDF066.UINT32
-#define RSCAN0RMDF066L RSCAN0.RMDF066.UINT16[L]
-#define RSCAN0RMDF066LL RSCAN0.RMDF066.UINT8[LL]
-#define RSCAN0RMDF066LH RSCAN0.RMDF066.UINT8[LH]
-#define RSCAN0RMDF066H RSCAN0.RMDF066.UINT16[H]
-#define RSCAN0RMDF066HL RSCAN0.RMDF066.UINT8[HL]
-#define RSCAN0RMDF066HH RSCAN0.RMDF066.UINT8[HH]
-#define RSCAN0RMDF166 RSCAN0.RMDF166.UINT32
-#define RSCAN0RMDF166L RSCAN0.RMDF166.UINT16[L]
-#define RSCAN0RMDF166LL RSCAN0.RMDF166.UINT8[LL]
-#define RSCAN0RMDF166LH RSCAN0.RMDF166.UINT8[LH]
-#define RSCAN0RMDF166H RSCAN0.RMDF166.UINT16[H]
-#define RSCAN0RMDF166HL RSCAN0.RMDF166.UINT8[HL]
-#define RSCAN0RMDF166HH RSCAN0.RMDF166.UINT8[HH]
-#define RSCAN0RMID67 RSCAN0.RMID67.UINT32
-#define RSCAN0RMID67L RSCAN0.RMID67.UINT16[L]
-#define RSCAN0RMID67LL RSCAN0.RMID67.UINT8[LL]
-#define RSCAN0RMID67LH RSCAN0.RMID67.UINT8[LH]
-#define RSCAN0RMID67H RSCAN0.RMID67.UINT16[H]
-#define RSCAN0RMID67HL RSCAN0.RMID67.UINT8[HL]
-#define RSCAN0RMID67HH RSCAN0.RMID67.UINT8[HH]
-#define RSCAN0RMPTR67 RSCAN0.RMPTR67.UINT32
-#define RSCAN0RMPTR67L RSCAN0.RMPTR67.UINT16[L]
-#define RSCAN0RMPTR67LL RSCAN0.RMPTR67.UINT8[LL]
-#define RSCAN0RMPTR67LH RSCAN0.RMPTR67.UINT8[LH]
-#define RSCAN0RMPTR67H RSCAN0.RMPTR67.UINT16[H]
-#define RSCAN0RMPTR67HL RSCAN0.RMPTR67.UINT8[HL]
-#define RSCAN0RMPTR67HH RSCAN0.RMPTR67.UINT8[HH]
-#define RSCAN0RMDF067 RSCAN0.RMDF067.UINT32
-#define RSCAN0RMDF067L RSCAN0.RMDF067.UINT16[L]
-#define RSCAN0RMDF067LL RSCAN0.RMDF067.UINT8[LL]
-#define RSCAN0RMDF067LH RSCAN0.RMDF067.UINT8[LH]
-#define RSCAN0RMDF067H RSCAN0.RMDF067.UINT16[H]
-#define RSCAN0RMDF067HL RSCAN0.RMDF067.UINT8[HL]
-#define RSCAN0RMDF067HH RSCAN0.RMDF067.UINT8[HH]
-#define RSCAN0RMDF167 RSCAN0.RMDF167.UINT32
-#define RSCAN0RMDF167L RSCAN0.RMDF167.UINT16[L]
-#define RSCAN0RMDF167LL RSCAN0.RMDF167.UINT8[LL]
-#define RSCAN0RMDF167LH RSCAN0.RMDF167.UINT8[LH]
-#define RSCAN0RMDF167H RSCAN0.RMDF167.UINT16[H]
-#define RSCAN0RMDF167HL RSCAN0.RMDF167.UINT8[HL]
-#define RSCAN0RMDF167HH RSCAN0.RMDF167.UINT8[HH]
-#define RSCAN0RMID68 RSCAN0.RMID68.UINT32
-#define RSCAN0RMID68L RSCAN0.RMID68.UINT16[L]
-#define RSCAN0RMID68LL RSCAN0.RMID68.UINT8[LL]
-#define RSCAN0RMID68LH RSCAN0.RMID68.UINT8[LH]
-#define RSCAN0RMID68H RSCAN0.RMID68.UINT16[H]
-#define RSCAN0RMID68HL RSCAN0.RMID68.UINT8[HL]
-#define RSCAN0RMID68HH RSCAN0.RMID68.UINT8[HH]
-#define RSCAN0RMPTR68 RSCAN0.RMPTR68.UINT32
-#define RSCAN0RMPTR68L RSCAN0.RMPTR68.UINT16[L]
-#define RSCAN0RMPTR68LL RSCAN0.RMPTR68.UINT8[LL]
-#define RSCAN0RMPTR68LH RSCAN0.RMPTR68.UINT8[LH]
-#define RSCAN0RMPTR68H RSCAN0.RMPTR68.UINT16[H]
-#define RSCAN0RMPTR68HL RSCAN0.RMPTR68.UINT8[HL]
-#define RSCAN0RMPTR68HH RSCAN0.RMPTR68.UINT8[HH]
-#define RSCAN0RMDF068 RSCAN0.RMDF068.UINT32
-#define RSCAN0RMDF068L RSCAN0.RMDF068.UINT16[L]
-#define RSCAN0RMDF068LL RSCAN0.RMDF068.UINT8[LL]
-#define RSCAN0RMDF068LH RSCAN0.RMDF068.UINT8[LH]
-#define RSCAN0RMDF068H RSCAN0.RMDF068.UINT16[H]
-#define RSCAN0RMDF068HL RSCAN0.RMDF068.UINT8[HL]
-#define RSCAN0RMDF068HH RSCAN0.RMDF068.UINT8[HH]
-#define RSCAN0RMDF168 RSCAN0.RMDF168.UINT32
-#define RSCAN0RMDF168L RSCAN0.RMDF168.UINT16[L]
-#define RSCAN0RMDF168LL RSCAN0.RMDF168.UINT8[LL]
-#define RSCAN0RMDF168LH RSCAN0.RMDF168.UINT8[LH]
-#define RSCAN0RMDF168H RSCAN0.RMDF168.UINT16[H]
-#define RSCAN0RMDF168HL RSCAN0.RMDF168.UINT8[HL]
-#define RSCAN0RMDF168HH RSCAN0.RMDF168.UINT8[HH]
-#define RSCAN0RMID69 RSCAN0.RMID69.UINT32
-#define RSCAN0RMID69L RSCAN0.RMID69.UINT16[L]
-#define RSCAN0RMID69LL RSCAN0.RMID69.UINT8[LL]
-#define RSCAN0RMID69LH RSCAN0.RMID69.UINT8[LH]
-#define RSCAN0RMID69H RSCAN0.RMID69.UINT16[H]
-#define RSCAN0RMID69HL RSCAN0.RMID69.UINT8[HL]
-#define RSCAN0RMID69HH RSCAN0.RMID69.UINT8[HH]
-#define RSCAN0RMPTR69 RSCAN0.RMPTR69.UINT32
-#define RSCAN0RMPTR69L RSCAN0.RMPTR69.UINT16[L]
-#define RSCAN0RMPTR69LL RSCAN0.RMPTR69.UINT8[LL]
-#define RSCAN0RMPTR69LH RSCAN0.RMPTR69.UINT8[LH]
-#define RSCAN0RMPTR69H RSCAN0.RMPTR69.UINT16[H]
-#define RSCAN0RMPTR69HL RSCAN0.RMPTR69.UINT8[HL]
-#define RSCAN0RMPTR69HH RSCAN0.RMPTR69.UINT8[HH]
-#define RSCAN0RMDF069 RSCAN0.RMDF069.UINT32
-#define RSCAN0RMDF069L RSCAN0.RMDF069.UINT16[L]
-#define RSCAN0RMDF069LL RSCAN0.RMDF069.UINT8[LL]
-#define RSCAN0RMDF069LH RSCAN0.RMDF069.UINT8[LH]
-#define RSCAN0RMDF069H RSCAN0.RMDF069.UINT16[H]
-#define RSCAN0RMDF069HL RSCAN0.RMDF069.UINT8[HL]
-#define RSCAN0RMDF069HH RSCAN0.RMDF069.UINT8[HH]
-#define RSCAN0RMDF169 RSCAN0.RMDF169.UINT32
-#define RSCAN0RMDF169L RSCAN0.RMDF169.UINT16[L]
-#define RSCAN0RMDF169LL RSCAN0.RMDF169.UINT8[LL]
-#define RSCAN0RMDF169LH RSCAN0.RMDF169.UINT8[LH]
-#define RSCAN0RMDF169H RSCAN0.RMDF169.UINT16[H]
-#define RSCAN0RMDF169HL RSCAN0.RMDF169.UINT8[HL]
-#define RSCAN0RMDF169HH RSCAN0.RMDF169.UINT8[HH]
-#define RSCAN0RMID70 RSCAN0.RMID70.UINT32
-#define RSCAN0RMID70L RSCAN0.RMID70.UINT16[L]
-#define RSCAN0RMID70LL RSCAN0.RMID70.UINT8[LL]
-#define RSCAN0RMID70LH RSCAN0.RMID70.UINT8[LH]
-#define RSCAN0RMID70H RSCAN0.RMID70.UINT16[H]
-#define RSCAN0RMID70HL RSCAN0.RMID70.UINT8[HL]
-#define RSCAN0RMID70HH RSCAN0.RMID70.UINT8[HH]
-#define RSCAN0RMPTR70 RSCAN0.RMPTR70.UINT32
-#define RSCAN0RMPTR70L RSCAN0.RMPTR70.UINT16[L]
-#define RSCAN0RMPTR70LL RSCAN0.RMPTR70.UINT8[LL]
-#define RSCAN0RMPTR70LH RSCAN0.RMPTR70.UINT8[LH]
-#define RSCAN0RMPTR70H RSCAN0.RMPTR70.UINT16[H]
-#define RSCAN0RMPTR70HL RSCAN0.RMPTR70.UINT8[HL]
-#define RSCAN0RMPTR70HH RSCAN0.RMPTR70.UINT8[HH]
-#define RSCAN0RMDF070 RSCAN0.RMDF070.UINT32
-#define RSCAN0RMDF070L RSCAN0.RMDF070.UINT16[L]
-#define RSCAN0RMDF070LL RSCAN0.RMDF070.UINT8[LL]
-#define RSCAN0RMDF070LH RSCAN0.RMDF070.UINT8[LH]
-#define RSCAN0RMDF070H RSCAN0.RMDF070.UINT16[H]
-#define RSCAN0RMDF070HL RSCAN0.RMDF070.UINT8[HL]
-#define RSCAN0RMDF070HH RSCAN0.RMDF070.UINT8[HH]
-#define RSCAN0RMDF170 RSCAN0.RMDF170.UINT32
-#define RSCAN0RMDF170L RSCAN0.RMDF170.UINT16[L]
-#define RSCAN0RMDF170LL RSCAN0.RMDF170.UINT8[LL]
-#define RSCAN0RMDF170LH RSCAN0.RMDF170.UINT8[LH]
-#define RSCAN0RMDF170H RSCAN0.RMDF170.UINT16[H]
-#define RSCAN0RMDF170HL RSCAN0.RMDF170.UINT8[HL]
-#define RSCAN0RMDF170HH RSCAN0.RMDF170.UINT8[HH]
-#define RSCAN0RMID71 RSCAN0.RMID71.UINT32
-#define RSCAN0RMID71L RSCAN0.RMID71.UINT16[L]
-#define RSCAN0RMID71LL RSCAN0.RMID71.UINT8[LL]
-#define RSCAN0RMID71LH RSCAN0.RMID71.UINT8[LH]
-#define RSCAN0RMID71H RSCAN0.RMID71.UINT16[H]
-#define RSCAN0RMID71HL RSCAN0.RMID71.UINT8[HL]
-#define RSCAN0RMID71HH RSCAN0.RMID71.UINT8[HH]
-#define RSCAN0RMPTR71 RSCAN0.RMPTR71.UINT32
-#define RSCAN0RMPTR71L RSCAN0.RMPTR71.UINT16[L]
-#define RSCAN0RMPTR71LL RSCAN0.RMPTR71.UINT8[LL]
-#define RSCAN0RMPTR71LH RSCAN0.RMPTR71.UINT8[LH]
-#define RSCAN0RMPTR71H RSCAN0.RMPTR71.UINT16[H]
-#define RSCAN0RMPTR71HL RSCAN0.RMPTR71.UINT8[HL]
-#define RSCAN0RMPTR71HH RSCAN0.RMPTR71.UINT8[HH]
-#define RSCAN0RMDF071 RSCAN0.RMDF071.UINT32
-#define RSCAN0RMDF071L RSCAN0.RMDF071.UINT16[L]
-#define RSCAN0RMDF071LL RSCAN0.RMDF071.UINT8[LL]
-#define RSCAN0RMDF071LH RSCAN0.RMDF071.UINT8[LH]
-#define RSCAN0RMDF071H RSCAN0.RMDF071.UINT16[H]
-#define RSCAN0RMDF071HL RSCAN0.RMDF071.UINT8[HL]
-#define RSCAN0RMDF071HH RSCAN0.RMDF071.UINT8[HH]
-#define RSCAN0RMDF171 RSCAN0.RMDF171.UINT32
-#define RSCAN0RMDF171L RSCAN0.RMDF171.UINT16[L]
-#define RSCAN0RMDF171LL RSCAN0.RMDF171.UINT8[LL]
-#define RSCAN0RMDF171LH RSCAN0.RMDF171.UINT8[LH]
-#define RSCAN0RMDF171H RSCAN0.RMDF171.UINT16[H]
-#define RSCAN0RMDF171HL RSCAN0.RMDF171.UINT8[HL]
-#define RSCAN0RMDF171HH RSCAN0.RMDF171.UINT8[HH]
-#define RSCAN0RMID72 RSCAN0.RMID72.UINT32
-#define RSCAN0RMID72L RSCAN0.RMID72.UINT16[L]
-#define RSCAN0RMID72LL RSCAN0.RMID72.UINT8[LL]
-#define RSCAN0RMID72LH RSCAN0.RMID72.UINT8[LH]
-#define RSCAN0RMID72H RSCAN0.RMID72.UINT16[H]
-#define RSCAN0RMID72HL RSCAN0.RMID72.UINT8[HL]
-#define RSCAN0RMID72HH RSCAN0.RMID72.UINT8[HH]
-#define RSCAN0RMPTR72 RSCAN0.RMPTR72.UINT32
-#define RSCAN0RMPTR72L RSCAN0.RMPTR72.UINT16[L]
-#define RSCAN0RMPTR72LL RSCAN0.RMPTR72.UINT8[LL]
-#define RSCAN0RMPTR72LH RSCAN0.RMPTR72.UINT8[LH]
-#define RSCAN0RMPTR72H RSCAN0.RMPTR72.UINT16[H]
-#define RSCAN0RMPTR72HL RSCAN0.RMPTR72.UINT8[HL]
-#define RSCAN0RMPTR72HH RSCAN0.RMPTR72.UINT8[HH]
-#define RSCAN0RMDF072 RSCAN0.RMDF072.UINT32
-#define RSCAN0RMDF072L RSCAN0.RMDF072.UINT16[L]
-#define RSCAN0RMDF072LL RSCAN0.RMDF072.UINT8[LL]
-#define RSCAN0RMDF072LH RSCAN0.RMDF072.UINT8[LH]
-#define RSCAN0RMDF072H RSCAN0.RMDF072.UINT16[H]
-#define RSCAN0RMDF072HL RSCAN0.RMDF072.UINT8[HL]
-#define RSCAN0RMDF072HH RSCAN0.RMDF072.UINT8[HH]
-#define RSCAN0RMDF172 RSCAN0.RMDF172.UINT32
-#define RSCAN0RMDF172L RSCAN0.RMDF172.UINT16[L]
-#define RSCAN0RMDF172LL RSCAN0.RMDF172.UINT8[LL]
-#define RSCAN0RMDF172LH RSCAN0.RMDF172.UINT8[LH]
-#define RSCAN0RMDF172H RSCAN0.RMDF172.UINT16[H]
-#define RSCAN0RMDF172HL RSCAN0.RMDF172.UINT8[HL]
-#define RSCAN0RMDF172HH RSCAN0.RMDF172.UINT8[HH]
-#define RSCAN0RMID73 RSCAN0.RMID73.UINT32
-#define RSCAN0RMID73L RSCAN0.RMID73.UINT16[L]
-#define RSCAN0RMID73LL RSCAN0.RMID73.UINT8[LL]
-#define RSCAN0RMID73LH RSCAN0.RMID73.UINT8[LH]
-#define RSCAN0RMID73H RSCAN0.RMID73.UINT16[H]
-#define RSCAN0RMID73HL RSCAN0.RMID73.UINT8[HL]
-#define RSCAN0RMID73HH RSCAN0.RMID73.UINT8[HH]
-#define RSCAN0RMPTR73 RSCAN0.RMPTR73.UINT32
-#define RSCAN0RMPTR73L RSCAN0.RMPTR73.UINT16[L]
-#define RSCAN0RMPTR73LL RSCAN0.RMPTR73.UINT8[LL]
-#define RSCAN0RMPTR73LH RSCAN0.RMPTR73.UINT8[LH]
-#define RSCAN0RMPTR73H RSCAN0.RMPTR73.UINT16[H]
-#define RSCAN0RMPTR73HL RSCAN0.RMPTR73.UINT8[HL]
-#define RSCAN0RMPTR73HH RSCAN0.RMPTR73.UINT8[HH]
-#define RSCAN0RMDF073 RSCAN0.RMDF073.UINT32
-#define RSCAN0RMDF073L RSCAN0.RMDF073.UINT16[L]
-#define RSCAN0RMDF073LL RSCAN0.RMDF073.UINT8[LL]
-#define RSCAN0RMDF073LH RSCAN0.RMDF073.UINT8[LH]
-#define RSCAN0RMDF073H RSCAN0.RMDF073.UINT16[H]
-#define RSCAN0RMDF073HL RSCAN0.RMDF073.UINT8[HL]
-#define RSCAN0RMDF073HH RSCAN0.RMDF073.UINT8[HH]
-#define RSCAN0RMDF173 RSCAN0.RMDF173.UINT32
-#define RSCAN0RMDF173L RSCAN0.RMDF173.UINT16[L]
-#define RSCAN0RMDF173LL RSCAN0.RMDF173.UINT8[LL]
-#define RSCAN0RMDF173LH RSCAN0.RMDF173.UINT8[LH]
-#define RSCAN0RMDF173H RSCAN0.RMDF173.UINT16[H]
-#define RSCAN0RMDF173HL RSCAN0.RMDF173.UINT8[HL]
-#define RSCAN0RMDF173HH RSCAN0.RMDF173.UINT8[HH]
-#define RSCAN0RMID74 RSCAN0.RMID74.UINT32
-#define RSCAN0RMID74L RSCAN0.RMID74.UINT16[L]
-#define RSCAN0RMID74LL RSCAN0.RMID74.UINT8[LL]
-#define RSCAN0RMID74LH RSCAN0.RMID74.UINT8[LH]
-#define RSCAN0RMID74H RSCAN0.RMID74.UINT16[H]
-#define RSCAN0RMID74HL RSCAN0.RMID74.UINT8[HL]
-#define RSCAN0RMID74HH RSCAN0.RMID74.UINT8[HH]
-#define RSCAN0RMPTR74 RSCAN0.RMPTR74.UINT32
-#define RSCAN0RMPTR74L RSCAN0.RMPTR74.UINT16[L]
-#define RSCAN0RMPTR74LL RSCAN0.RMPTR74.UINT8[LL]
-#define RSCAN0RMPTR74LH RSCAN0.RMPTR74.UINT8[LH]
-#define RSCAN0RMPTR74H RSCAN0.RMPTR74.UINT16[H]
-#define RSCAN0RMPTR74HL RSCAN0.RMPTR74.UINT8[HL]
-#define RSCAN0RMPTR74HH RSCAN0.RMPTR74.UINT8[HH]
-#define RSCAN0RMDF074 RSCAN0.RMDF074.UINT32
-#define RSCAN0RMDF074L RSCAN0.RMDF074.UINT16[L]
-#define RSCAN0RMDF074LL RSCAN0.RMDF074.UINT8[LL]
-#define RSCAN0RMDF074LH RSCAN0.RMDF074.UINT8[LH]
-#define RSCAN0RMDF074H RSCAN0.RMDF074.UINT16[H]
-#define RSCAN0RMDF074HL RSCAN0.RMDF074.UINT8[HL]
-#define RSCAN0RMDF074HH RSCAN0.RMDF074.UINT8[HH]
-#define RSCAN0RMDF174 RSCAN0.RMDF174.UINT32
-#define RSCAN0RMDF174L RSCAN0.RMDF174.UINT16[L]
-#define RSCAN0RMDF174LL RSCAN0.RMDF174.UINT8[LL]
-#define RSCAN0RMDF174LH RSCAN0.RMDF174.UINT8[LH]
-#define RSCAN0RMDF174H RSCAN0.RMDF174.UINT16[H]
-#define RSCAN0RMDF174HL RSCAN0.RMDF174.UINT8[HL]
-#define RSCAN0RMDF174HH RSCAN0.RMDF174.UINT8[HH]
-#define RSCAN0RMID75 RSCAN0.RMID75.UINT32
-#define RSCAN0RMID75L RSCAN0.RMID75.UINT16[L]
-#define RSCAN0RMID75LL RSCAN0.RMID75.UINT8[LL]
-#define RSCAN0RMID75LH RSCAN0.RMID75.UINT8[LH]
-#define RSCAN0RMID75H RSCAN0.RMID75.UINT16[H]
-#define RSCAN0RMID75HL RSCAN0.RMID75.UINT8[HL]
-#define RSCAN0RMID75HH RSCAN0.RMID75.UINT8[HH]
-#define RSCAN0RMPTR75 RSCAN0.RMPTR75.UINT32
-#define RSCAN0RMPTR75L RSCAN0.RMPTR75.UINT16[L]
-#define RSCAN0RMPTR75LL RSCAN0.RMPTR75.UINT8[LL]
-#define RSCAN0RMPTR75LH RSCAN0.RMPTR75.UINT8[LH]
-#define RSCAN0RMPTR75H RSCAN0.RMPTR75.UINT16[H]
-#define RSCAN0RMPTR75HL RSCAN0.RMPTR75.UINT8[HL]
-#define RSCAN0RMPTR75HH RSCAN0.RMPTR75.UINT8[HH]
-#define RSCAN0RMDF075 RSCAN0.RMDF075.UINT32
-#define RSCAN0RMDF075L RSCAN0.RMDF075.UINT16[L]
-#define RSCAN0RMDF075LL RSCAN0.RMDF075.UINT8[LL]
-#define RSCAN0RMDF075LH RSCAN0.RMDF075.UINT8[LH]
-#define RSCAN0RMDF075H RSCAN0.RMDF075.UINT16[H]
-#define RSCAN0RMDF075HL RSCAN0.RMDF075.UINT8[HL]
-#define RSCAN0RMDF075HH RSCAN0.RMDF075.UINT8[HH]
-#define RSCAN0RMDF175 RSCAN0.RMDF175.UINT32
-#define RSCAN0RMDF175L RSCAN0.RMDF175.UINT16[L]
-#define RSCAN0RMDF175LL RSCAN0.RMDF175.UINT8[LL]
-#define RSCAN0RMDF175LH RSCAN0.RMDF175.UINT8[LH]
-#define RSCAN0RMDF175H RSCAN0.RMDF175.UINT16[H]
-#define RSCAN0RMDF175HL RSCAN0.RMDF175.UINT8[HL]
-#define RSCAN0RMDF175HH RSCAN0.RMDF175.UINT8[HH]
-#define RSCAN0RMID76 RSCAN0.RMID76.UINT32
-#define RSCAN0RMID76L RSCAN0.RMID76.UINT16[L]
-#define RSCAN0RMID76LL RSCAN0.RMID76.UINT8[LL]
-#define RSCAN0RMID76LH RSCAN0.RMID76.UINT8[LH]
-#define RSCAN0RMID76H RSCAN0.RMID76.UINT16[H]
-#define RSCAN0RMID76HL RSCAN0.RMID76.UINT8[HL]
-#define RSCAN0RMID76HH RSCAN0.RMID76.UINT8[HH]
-#define RSCAN0RMPTR76 RSCAN0.RMPTR76.UINT32
-#define RSCAN0RMPTR76L RSCAN0.RMPTR76.UINT16[L]
-#define RSCAN0RMPTR76LL RSCAN0.RMPTR76.UINT8[LL]
-#define RSCAN0RMPTR76LH RSCAN0.RMPTR76.UINT8[LH]
-#define RSCAN0RMPTR76H RSCAN0.RMPTR76.UINT16[H]
-#define RSCAN0RMPTR76HL RSCAN0.RMPTR76.UINT8[HL]
-#define RSCAN0RMPTR76HH RSCAN0.RMPTR76.UINT8[HH]
-#define RSCAN0RMDF076 RSCAN0.RMDF076.UINT32
-#define RSCAN0RMDF076L RSCAN0.RMDF076.UINT16[L]
-#define RSCAN0RMDF076LL RSCAN0.RMDF076.UINT8[LL]
-#define RSCAN0RMDF076LH RSCAN0.RMDF076.UINT8[LH]
-#define RSCAN0RMDF076H RSCAN0.RMDF076.UINT16[H]
-#define RSCAN0RMDF076HL RSCAN0.RMDF076.UINT8[HL]
-#define RSCAN0RMDF076HH RSCAN0.RMDF076.UINT8[HH]
-#define RSCAN0RMDF176 RSCAN0.RMDF176.UINT32
-#define RSCAN0RMDF176L RSCAN0.RMDF176.UINT16[L]
-#define RSCAN0RMDF176LL RSCAN0.RMDF176.UINT8[LL]
-#define RSCAN0RMDF176LH RSCAN0.RMDF176.UINT8[LH]
-#define RSCAN0RMDF176H RSCAN0.RMDF176.UINT16[H]
-#define RSCAN0RMDF176HL RSCAN0.RMDF176.UINT8[HL]
-#define RSCAN0RMDF176HH RSCAN0.RMDF176.UINT8[HH]
-#define RSCAN0RMID77 RSCAN0.RMID77.UINT32
-#define RSCAN0RMID77L RSCAN0.RMID77.UINT16[L]
-#define RSCAN0RMID77LL RSCAN0.RMID77.UINT8[LL]
-#define RSCAN0RMID77LH RSCAN0.RMID77.UINT8[LH]
-#define RSCAN0RMID77H RSCAN0.RMID77.UINT16[H]
-#define RSCAN0RMID77HL RSCAN0.RMID77.UINT8[HL]
-#define RSCAN0RMID77HH RSCAN0.RMID77.UINT8[HH]
-#define RSCAN0RMPTR77 RSCAN0.RMPTR77.UINT32
-#define RSCAN0RMPTR77L RSCAN0.RMPTR77.UINT16[L]
-#define RSCAN0RMPTR77LL RSCAN0.RMPTR77.UINT8[LL]
-#define RSCAN0RMPTR77LH RSCAN0.RMPTR77.UINT8[LH]
-#define RSCAN0RMPTR77H RSCAN0.RMPTR77.UINT16[H]
-#define RSCAN0RMPTR77HL RSCAN0.RMPTR77.UINT8[HL]
-#define RSCAN0RMPTR77HH RSCAN0.RMPTR77.UINT8[HH]
-#define RSCAN0RMDF077 RSCAN0.RMDF077.UINT32
-#define RSCAN0RMDF077L RSCAN0.RMDF077.UINT16[L]
-#define RSCAN0RMDF077LL RSCAN0.RMDF077.UINT8[LL]
-#define RSCAN0RMDF077LH RSCAN0.RMDF077.UINT8[LH]
-#define RSCAN0RMDF077H RSCAN0.RMDF077.UINT16[H]
-#define RSCAN0RMDF077HL RSCAN0.RMDF077.UINT8[HL]
-#define RSCAN0RMDF077HH RSCAN0.RMDF077.UINT8[HH]
-#define RSCAN0RMDF177 RSCAN0.RMDF177.UINT32
-#define RSCAN0RMDF177L RSCAN0.RMDF177.UINT16[L]
-#define RSCAN0RMDF177LL RSCAN0.RMDF177.UINT8[LL]
-#define RSCAN0RMDF177LH RSCAN0.RMDF177.UINT8[LH]
-#define RSCAN0RMDF177H RSCAN0.RMDF177.UINT16[H]
-#define RSCAN0RMDF177HL RSCAN0.RMDF177.UINT8[HL]
-#define RSCAN0RMDF177HH RSCAN0.RMDF177.UINT8[HH]
-#define RSCAN0RMID78 RSCAN0.RMID78.UINT32
-#define RSCAN0RMID78L RSCAN0.RMID78.UINT16[L]
-#define RSCAN0RMID78LL RSCAN0.RMID78.UINT8[LL]
-#define RSCAN0RMID78LH RSCAN0.RMID78.UINT8[LH]
-#define RSCAN0RMID78H RSCAN0.RMID78.UINT16[H]
-#define RSCAN0RMID78HL RSCAN0.RMID78.UINT8[HL]
-#define RSCAN0RMID78HH RSCAN0.RMID78.UINT8[HH]
-#define RSCAN0RMPTR78 RSCAN0.RMPTR78.UINT32
-#define RSCAN0RMPTR78L RSCAN0.RMPTR78.UINT16[L]
-#define RSCAN0RMPTR78LL RSCAN0.RMPTR78.UINT8[LL]
-#define RSCAN0RMPTR78LH RSCAN0.RMPTR78.UINT8[LH]
-#define RSCAN0RMPTR78H RSCAN0.RMPTR78.UINT16[H]
-#define RSCAN0RMPTR78HL RSCAN0.RMPTR78.UINT8[HL]
-#define RSCAN0RMPTR78HH RSCAN0.RMPTR78.UINT8[HH]
-#define RSCAN0RMDF078 RSCAN0.RMDF078.UINT32
-#define RSCAN0RMDF078L RSCAN0.RMDF078.UINT16[L]
-#define RSCAN0RMDF078LL RSCAN0.RMDF078.UINT8[LL]
-#define RSCAN0RMDF078LH RSCAN0.RMDF078.UINT8[LH]
-#define RSCAN0RMDF078H RSCAN0.RMDF078.UINT16[H]
-#define RSCAN0RMDF078HL RSCAN0.RMDF078.UINT8[HL]
-#define RSCAN0RMDF078HH RSCAN0.RMDF078.UINT8[HH]
-#define RSCAN0RMDF178 RSCAN0.RMDF178.UINT32
-#define RSCAN0RMDF178L RSCAN0.RMDF178.UINT16[L]
-#define RSCAN0RMDF178LL RSCAN0.RMDF178.UINT8[LL]
-#define RSCAN0RMDF178LH RSCAN0.RMDF178.UINT8[LH]
-#define RSCAN0RMDF178H RSCAN0.RMDF178.UINT16[H]
-#define RSCAN0RMDF178HL RSCAN0.RMDF178.UINT8[HL]
-#define RSCAN0RMDF178HH RSCAN0.RMDF178.UINT8[HH]
-#define RSCAN0RMID79 RSCAN0.RMID79.UINT32
-#define RSCAN0RMID79L RSCAN0.RMID79.UINT16[L]
-#define RSCAN0RMID79LL RSCAN0.RMID79.UINT8[LL]
-#define RSCAN0RMID79LH RSCAN0.RMID79.UINT8[LH]
-#define RSCAN0RMID79H RSCAN0.RMID79.UINT16[H]
-#define RSCAN0RMID79HL RSCAN0.RMID79.UINT8[HL]
-#define RSCAN0RMID79HH RSCAN0.RMID79.UINT8[HH]
-#define RSCAN0RMPTR79 RSCAN0.RMPTR79.UINT32
-#define RSCAN0RMPTR79L RSCAN0.RMPTR79.UINT16[L]
-#define RSCAN0RMPTR79LL RSCAN0.RMPTR79.UINT8[LL]
-#define RSCAN0RMPTR79LH RSCAN0.RMPTR79.UINT8[LH]
-#define RSCAN0RMPTR79H RSCAN0.RMPTR79.UINT16[H]
-#define RSCAN0RMPTR79HL RSCAN0.RMPTR79.UINT8[HL]
-#define RSCAN0RMPTR79HH RSCAN0.RMPTR79.UINT8[HH]
-#define RSCAN0RMDF079 RSCAN0.RMDF079.UINT32
-#define RSCAN0RMDF079L RSCAN0.RMDF079.UINT16[L]
-#define RSCAN0RMDF079LL RSCAN0.RMDF079.UINT8[LL]
-#define RSCAN0RMDF079LH RSCAN0.RMDF079.UINT8[LH]
-#define RSCAN0RMDF079H RSCAN0.RMDF079.UINT16[H]
-#define RSCAN0RMDF079HL RSCAN0.RMDF079.UINT8[HL]
-#define RSCAN0RMDF079HH RSCAN0.RMDF079.UINT8[HH]
-#define RSCAN0RMDF179 RSCAN0.RMDF179.UINT32
-#define RSCAN0RMDF179L RSCAN0.RMDF179.UINT16[L]
-#define RSCAN0RMDF179LL RSCAN0.RMDF179.UINT8[LL]
-#define RSCAN0RMDF179LH RSCAN0.RMDF179.UINT8[LH]
-#define RSCAN0RMDF179H RSCAN0.RMDF179.UINT16[H]
-#define RSCAN0RMDF179HL RSCAN0.RMDF179.UINT8[HL]
-#define RSCAN0RMDF179HH RSCAN0.RMDF179.UINT8[HH]
-#define RSCAN0RFID0 RSCAN0.RFID0.UINT32
-#define RSCAN0RFID0L RSCAN0.RFID0.UINT16[L]
-#define RSCAN0RFID0LL RSCAN0.RFID0.UINT8[LL]
-#define RSCAN0RFID0LH RSCAN0.RFID0.UINT8[LH]
-#define RSCAN0RFID0H RSCAN0.RFID0.UINT16[H]
-#define RSCAN0RFID0HL RSCAN0.RFID0.UINT8[HL]
-#define RSCAN0RFID0HH RSCAN0.RFID0.UINT8[HH]
-#define RSCAN0RFPTR0 RSCAN0.RFPTR0.UINT32
-#define RSCAN0RFPTR0L RSCAN0.RFPTR0.UINT16[L]
-#define RSCAN0RFPTR0LL RSCAN0.RFPTR0.UINT8[LL]
-#define RSCAN0RFPTR0LH RSCAN0.RFPTR0.UINT8[LH]
-#define RSCAN0RFPTR0H RSCAN0.RFPTR0.UINT16[H]
-#define RSCAN0RFPTR0HL RSCAN0.RFPTR0.UINT8[HL]
-#define RSCAN0RFPTR0HH RSCAN0.RFPTR0.UINT8[HH]
-#define RSCAN0RFDF00 RSCAN0.RFDF00.UINT32
-#define RSCAN0RFDF00L RSCAN0.RFDF00.UINT16[L]
-#define RSCAN0RFDF00LL RSCAN0.RFDF00.UINT8[LL]
-#define RSCAN0RFDF00LH RSCAN0.RFDF00.UINT8[LH]
-#define RSCAN0RFDF00H RSCAN0.RFDF00.UINT16[H]
-#define RSCAN0RFDF00HL RSCAN0.RFDF00.UINT8[HL]
-#define RSCAN0RFDF00HH RSCAN0.RFDF00.UINT8[HH]
-#define RSCAN0RFDF10 RSCAN0.RFDF10.UINT32
-#define RSCAN0RFDF10L RSCAN0.RFDF10.UINT16[L]
-#define RSCAN0RFDF10LL RSCAN0.RFDF10.UINT8[LL]
-#define RSCAN0RFDF10LH RSCAN0.RFDF10.UINT8[LH]
-#define RSCAN0RFDF10H RSCAN0.RFDF10.UINT16[H]
-#define RSCAN0RFDF10HL RSCAN0.RFDF10.UINT8[HL]
-#define RSCAN0RFDF10HH RSCAN0.RFDF10.UINT8[HH]
-#define RSCAN0RFID1 RSCAN0.RFID1.UINT32
-#define RSCAN0RFID1L RSCAN0.RFID1.UINT16[L]
-#define RSCAN0RFID1LL RSCAN0.RFID1.UINT8[LL]
-#define RSCAN0RFID1LH RSCAN0.RFID1.UINT8[LH]
-#define RSCAN0RFID1H RSCAN0.RFID1.UINT16[H]
-#define RSCAN0RFID1HL RSCAN0.RFID1.UINT8[HL]
-#define RSCAN0RFID1HH RSCAN0.RFID1.UINT8[HH]
-#define RSCAN0RFPTR1 RSCAN0.RFPTR1.UINT32
-#define RSCAN0RFPTR1L RSCAN0.RFPTR1.UINT16[L]
-#define RSCAN0RFPTR1LL RSCAN0.RFPTR1.UINT8[LL]
-#define RSCAN0RFPTR1LH RSCAN0.RFPTR1.UINT8[LH]
-#define RSCAN0RFPTR1H RSCAN0.RFPTR1.UINT16[H]
-#define RSCAN0RFPTR1HL RSCAN0.RFPTR1.UINT8[HL]
-#define RSCAN0RFPTR1HH RSCAN0.RFPTR1.UINT8[HH]
-#define RSCAN0RFDF01 RSCAN0.RFDF01.UINT32
-#define RSCAN0RFDF01L RSCAN0.RFDF01.UINT16[L]
-#define RSCAN0RFDF01LL RSCAN0.RFDF01.UINT8[LL]
-#define RSCAN0RFDF01LH RSCAN0.RFDF01.UINT8[LH]
-#define RSCAN0RFDF01H RSCAN0.RFDF01.UINT16[H]
-#define RSCAN0RFDF01HL RSCAN0.RFDF01.UINT8[HL]
-#define RSCAN0RFDF01HH RSCAN0.RFDF01.UINT8[HH]
-#define RSCAN0RFDF11 RSCAN0.RFDF11.UINT32
-#define RSCAN0RFDF11L RSCAN0.RFDF11.UINT16[L]
-#define RSCAN0RFDF11LL RSCAN0.RFDF11.UINT8[LL]
-#define RSCAN0RFDF11LH RSCAN0.RFDF11.UINT8[LH]
-#define RSCAN0RFDF11H RSCAN0.RFDF11.UINT16[H]
-#define RSCAN0RFDF11HL RSCAN0.RFDF11.UINT8[HL]
-#define RSCAN0RFDF11HH RSCAN0.RFDF11.UINT8[HH]
-#define RSCAN0RFID2 RSCAN0.RFID2.UINT32
-#define RSCAN0RFID2L RSCAN0.RFID2.UINT16[L]
-#define RSCAN0RFID2LL RSCAN0.RFID2.UINT8[LL]
-#define RSCAN0RFID2LH RSCAN0.RFID2.UINT8[LH]
-#define RSCAN0RFID2H RSCAN0.RFID2.UINT16[H]
-#define RSCAN0RFID2HL RSCAN0.RFID2.UINT8[HL]
-#define RSCAN0RFID2HH RSCAN0.RFID2.UINT8[HH]
-#define RSCAN0RFPTR2 RSCAN0.RFPTR2.UINT32
-#define RSCAN0RFPTR2L RSCAN0.RFPTR2.UINT16[L]
-#define RSCAN0RFPTR2LL RSCAN0.RFPTR2.UINT8[LL]
-#define RSCAN0RFPTR2LH RSCAN0.RFPTR2.UINT8[LH]
-#define RSCAN0RFPTR2H RSCAN0.RFPTR2.UINT16[H]
-#define RSCAN0RFPTR2HL RSCAN0.RFPTR2.UINT8[HL]
-#define RSCAN0RFPTR2HH RSCAN0.RFPTR2.UINT8[HH]
-#define RSCAN0RFDF02 RSCAN0.RFDF02.UINT32
-#define RSCAN0RFDF02L RSCAN0.RFDF02.UINT16[L]
-#define RSCAN0RFDF02LL RSCAN0.RFDF02.UINT8[LL]
-#define RSCAN0RFDF02LH RSCAN0.RFDF02.UINT8[LH]
-#define RSCAN0RFDF02H RSCAN0.RFDF02.UINT16[H]
-#define RSCAN0RFDF02HL RSCAN0.RFDF02.UINT8[HL]
-#define RSCAN0RFDF02HH RSCAN0.RFDF02.UINT8[HH]
-#define RSCAN0RFDF12 RSCAN0.RFDF12.UINT32
-#define RSCAN0RFDF12L RSCAN0.RFDF12.UINT16[L]
-#define RSCAN0RFDF12LL RSCAN0.RFDF12.UINT8[LL]
-#define RSCAN0RFDF12LH RSCAN0.RFDF12.UINT8[LH]
-#define RSCAN0RFDF12H RSCAN0.RFDF12.UINT16[H]
-#define RSCAN0RFDF12HL RSCAN0.RFDF12.UINT8[HL]
-#define RSCAN0RFDF12HH RSCAN0.RFDF12.UINT8[HH]
-#define RSCAN0RFID3 RSCAN0.RFID3.UINT32
-#define RSCAN0RFID3L RSCAN0.RFID3.UINT16[L]
-#define RSCAN0RFID3LL RSCAN0.RFID3.UINT8[LL]
-#define RSCAN0RFID3LH RSCAN0.RFID3.UINT8[LH]
-#define RSCAN0RFID3H RSCAN0.RFID3.UINT16[H]
-#define RSCAN0RFID3HL RSCAN0.RFID3.UINT8[HL]
-#define RSCAN0RFID3HH RSCAN0.RFID3.UINT8[HH]
-#define RSCAN0RFPTR3 RSCAN0.RFPTR3.UINT32
-#define RSCAN0RFPTR3L RSCAN0.RFPTR3.UINT16[L]
-#define RSCAN0RFPTR3LL RSCAN0.RFPTR3.UINT8[LL]
-#define RSCAN0RFPTR3LH RSCAN0.RFPTR3.UINT8[LH]
-#define RSCAN0RFPTR3H RSCAN0.RFPTR3.UINT16[H]
-#define RSCAN0RFPTR3HL RSCAN0.RFPTR3.UINT8[HL]
-#define RSCAN0RFPTR3HH RSCAN0.RFPTR3.UINT8[HH]
-#define RSCAN0RFDF03 RSCAN0.RFDF03.UINT32
-#define RSCAN0RFDF03L RSCAN0.RFDF03.UINT16[L]
-#define RSCAN0RFDF03LL RSCAN0.RFDF03.UINT8[LL]
-#define RSCAN0RFDF03LH RSCAN0.RFDF03.UINT8[LH]
-#define RSCAN0RFDF03H RSCAN0.RFDF03.UINT16[H]
-#define RSCAN0RFDF03HL RSCAN0.RFDF03.UINT8[HL]
-#define RSCAN0RFDF03HH RSCAN0.RFDF03.UINT8[HH]
-#define RSCAN0RFDF13 RSCAN0.RFDF13.UINT32
-#define RSCAN0RFDF13L RSCAN0.RFDF13.UINT16[L]
-#define RSCAN0RFDF13LL RSCAN0.RFDF13.UINT8[LL]
-#define RSCAN0RFDF13LH RSCAN0.RFDF13.UINT8[LH]
-#define RSCAN0RFDF13H RSCAN0.RFDF13.UINT16[H]
-#define RSCAN0RFDF13HL RSCAN0.RFDF13.UINT8[HL]
-#define RSCAN0RFDF13HH RSCAN0.RFDF13.UINT8[HH]
-#define RSCAN0RFID4 RSCAN0.RFID4.UINT32
-#define RSCAN0RFID4L RSCAN0.RFID4.UINT16[L]
-#define RSCAN0RFID4LL RSCAN0.RFID4.UINT8[LL]
-#define RSCAN0RFID4LH RSCAN0.RFID4.UINT8[LH]
-#define RSCAN0RFID4H RSCAN0.RFID4.UINT16[H]
-#define RSCAN0RFID4HL RSCAN0.RFID4.UINT8[HL]
-#define RSCAN0RFID4HH RSCAN0.RFID4.UINT8[HH]
-#define RSCAN0RFPTR4 RSCAN0.RFPTR4.UINT32
-#define RSCAN0RFPTR4L RSCAN0.RFPTR4.UINT16[L]
-#define RSCAN0RFPTR4LL RSCAN0.RFPTR4.UINT8[LL]
-#define RSCAN0RFPTR4LH RSCAN0.RFPTR4.UINT8[LH]
-#define RSCAN0RFPTR4H RSCAN0.RFPTR4.UINT16[H]
-#define RSCAN0RFPTR4HL RSCAN0.RFPTR4.UINT8[HL]
-#define RSCAN0RFPTR4HH RSCAN0.RFPTR4.UINT8[HH]
-#define RSCAN0RFDF04 RSCAN0.RFDF04.UINT32
-#define RSCAN0RFDF04L RSCAN0.RFDF04.UINT16[L]
-#define RSCAN0RFDF04LL RSCAN0.RFDF04.UINT8[LL]
-#define RSCAN0RFDF04LH RSCAN0.RFDF04.UINT8[LH]
-#define RSCAN0RFDF04H RSCAN0.RFDF04.UINT16[H]
-#define RSCAN0RFDF04HL RSCAN0.RFDF04.UINT8[HL]
-#define RSCAN0RFDF04HH RSCAN0.RFDF04.UINT8[HH]
-#define RSCAN0RFDF14 RSCAN0.RFDF14.UINT32
-#define RSCAN0RFDF14L RSCAN0.RFDF14.UINT16[L]
-#define RSCAN0RFDF14LL RSCAN0.RFDF14.UINT8[LL]
-#define RSCAN0RFDF14LH RSCAN0.RFDF14.UINT8[LH]
-#define RSCAN0RFDF14H RSCAN0.RFDF14.UINT16[H]
-#define RSCAN0RFDF14HL RSCAN0.RFDF14.UINT8[HL]
-#define RSCAN0RFDF14HH RSCAN0.RFDF14.UINT8[HH]
-#define RSCAN0RFID5 RSCAN0.RFID5.UINT32
-#define RSCAN0RFID5L RSCAN0.RFID5.UINT16[L]
-#define RSCAN0RFID5LL RSCAN0.RFID5.UINT8[LL]
-#define RSCAN0RFID5LH RSCAN0.RFID5.UINT8[LH]
-#define RSCAN0RFID5H RSCAN0.RFID5.UINT16[H]
-#define RSCAN0RFID5HL RSCAN0.RFID5.UINT8[HL]
-#define RSCAN0RFID5HH RSCAN0.RFID5.UINT8[HH]
-#define RSCAN0RFPTR5 RSCAN0.RFPTR5.UINT32
-#define RSCAN0RFPTR5L RSCAN0.RFPTR5.UINT16[L]
-#define RSCAN0RFPTR5LL RSCAN0.RFPTR5.UINT8[LL]
-#define RSCAN0RFPTR5LH RSCAN0.RFPTR5.UINT8[LH]
-#define RSCAN0RFPTR5H RSCAN0.RFPTR5.UINT16[H]
-#define RSCAN0RFPTR5HL RSCAN0.RFPTR5.UINT8[HL]
-#define RSCAN0RFPTR5HH RSCAN0.RFPTR5.UINT8[HH]
-#define RSCAN0RFDF05 RSCAN0.RFDF05.UINT32
-#define RSCAN0RFDF05L RSCAN0.RFDF05.UINT16[L]
-#define RSCAN0RFDF05LL RSCAN0.RFDF05.UINT8[LL]
-#define RSCAN0RFDF05LH RSCAN0.RFDF05.UINT8[LH]
-#define RSCAN0RFDF05H RSCAN0.RFDF05.UINT16[H]
-#define RSCAN0RFDF05HL RSCAN0.RFDF05.UINT8[HL]
-#define RSCAN0RFDF05HH RSCAN0.RFDF05.UINT8[HH]
-#define RSCAN0RFDF15 RSCAN0.RFDF15.UINT32
-#define RSCAN0RFDF15L RSCAN0.RFDF15.UINT16[L]
-#define RSCAN0RFDF15LL RSCAN0.RFDF15.UINT8[LL]
-#define RSCAN0RFDF15LH RSCAN0.RFDF15.UINT8[LH]
-#define RSCAN0RFDF15H RSCAN0.RFDF15.UINT16[H]
-#define RSCAN0RFDF15HL RSCAN0.RFDF15.UINT8[HL]
-#define RSCAN0RFDF15HH RSCAN0.RFDF15.UINT8[HH]
-#define RSCAN0RFID6 RSCAN0.RFID6.UINT32
-#define RSCAN0RFID6L RSCAN0.RFID6.UINT16[L]
-#define RSCAN0RFID6LL RSCAN0.RFID6.UINT8[LL]
-#define RSCAN0RFID6LH RSCAN0.RFID6.UINT8[LH]
-#define RSCAN0RFID6H RSCAN0.RFID6.UINT16[H]
-#define RSCAN0RFID6HL RSCAN0.RFID6.UINT8[HL]
-#define RSCAN0RFID6HH RSCAN0.RFID6.UINT8[HH]
-#define RSCAN0RFPTR6 RSCAN0.RFPTR6.UINT32
-#define RSCAN0RFPTR6L RSCAN0.RFPTR6.UINT16[L]
-#define RSCAN0RFPTR6LL RSCAN0.RFPTR6.UINT8[LL]
-#define RSCAN0RFPTR6LH RSCAN0.RFPTR6.UINT8[LH]
-#define RSCAN0RFPTR6H RSCAN0.RFPTR6.UINT16[H]
-#define RSCAN0RFPTR6HL RSCAN0.RFPTR6.UINT8[HL]
-#define RSCAN0RFPTR6HH RSCAN0.RFPTR6.UINT8[HH]
-#define RSCAN0RFDF06 RSCAN0.RFDF06.UINT32
-#define RSCAN0RFDF06L RSCAN0.RFDF06.UINT16[L]
-#define RSCAN0RFDF06LL RSCAN0.RFDF06.UINT8[LL]
-#define RSCAN0RFDF06LH RSCAN0.RFDF06.UINT8[LH]
-#define RSCAN0RFDF06H RSCAN0.RFDF06.UINT16[H]
-#define RSCAN0RFDF06HL RSCAN0.RFDF06.UINT8[HL]
-#define RSCAN0RFDF06HH RSCAN0.RFDF06.UINT8[HH]
-#define RSCAN0RFDF16 RSCAN0.RFDF16.UINT32
-#define RSCAN0RFDF16L RSCAN0.RFDF16.UINT16[L]
-#define RSCAN0RFDF16LL RSCAN0.RFDF16.UINT8[LL]
-#define RSCAN0RFDF16LH RSCAN0.RFDF16.UINT8[LH]
-#define RSCAN0RFDF16H RSCAN0.RFDF16.UINT16[H]
-#define RSCAN0RFDF16HL RSCAN0.RFDF16.UINT8[HL]
-#define RSCAN0RFDF16HH RSCAN0.RFDF16.UINT8[HH]
-#define RSCAN0RFID7 RSCAN0.RFID7.UINT32
-#define RSCAN0RFID7L RSCAN0.RFID7.UINT16[L]
-#define RSCAN0RFID7LL RSCAN0.RFID7.UINT8[LL]
-#define RSCAN0RFID7LH RSCAN0.RFID7.UINT8[LH]
-#define RSCAN0RFID7H RSCAN0.RFID7.UINT16[H]
-#define RSCAN0RFID7HL RSCAN0.RFID7.UINT8[HL]
-#define RSCAN0RFID7HH RSCAN0.RFID7.UINT8[HH]
-#define RSCAN0RFPTR7 RSCAN0.RFPTR7.UINT32
-#define RSCAN0RFPTR7L RSCAN0.RFPTR7.UINT16[L]
-#define RSCAN0RFPTR7LL RSCAN0.RFPTR7.UINT8[LL]
-#define RSCAN0RFPTR7LH RSCAN0.RFPTR7.UINT8[LH]
-#define RSCAN0RFPTR7H RSCAN0.RFPTR7.UINT16[H]
-#define RSCAN0RFPTR7HL RSCAN0.RFPTR7.UINT8[HL]
-#define RSCAN0RFPTR7HH RSCAN0.RFPTR7.UINT8[HH]
-#define RSCAN0RFDF07 RSCAN0.RFDF07.UINT32
-#define RSCAN0RFDF07L RSCAN0.RFDF07.UINT16[L]
-#define RSCAN0RFDF07LL RSCAN0.RFDF07.UINT8[LL]
-#define RSCAN0RFDF07LH RSCAN0.RFDF07.UINT8[LH]
-#define RSCAN0RFDF07H RSCAN0.RFDF07.UINT16[H]
-#define RSCAN0RFDF07HL RSCAN0.RFDF07.UINT8[HL]
-#define RSCAN0RFDF07HH RSCAN0.RFDF07.UINT8[HH]
-#define RSCAN0RFDF17 RSCAN0.RFDF17.UINT32
-#define RSCAN0RFDF17L RSCAN0.RFDF17.UINT16[L]
-#define RSCAN0RFDF17LL RSCAN0.RFDF17.UINT8[LL]
-#define RSCAN0RFDF17LH RSCAN0.RFDF17.UINT8[LH]
-#define RSCAN0RFDF17H RSCAN0.RFDF17.UINT16[H]
-#define RSCAN0RFDF17HL RSCAN0.RFDF17.UINT8[HL]
-#define RSCAN0RFDF17HH RSCAN0.RFDF17.UINT8[HH]
-#define RSCAN0CFID0 RSCAN0.CFID0.UINT32
-#define RSCAN0CFID0L RSCAN0.CFID0.UINT16[L]
-#define RSCAN0CFID0LL RSCAN0.CFID0.UINT8[LL]
-#define RSCAN0CFID0LH RSCAN0.CFID0.UINT8[LH]
-#define RSCAN0CFID0H RSCAN0.CFID0.UINT16[H]
-#define RSCAN0CFID0HL RSCAN0.CFID0.UINT8[HL]
-#define RSCAN0CFID0HH RSCAN0.CFID0.UINT8[HH]
-#define RSCAN0CFPTR0 RSCAN0.CFPTR0.UINT32
-#define RSCAN0CFPTR0L RSCAN0.CFPTR0.UINT16[L]
-#define RSCAN0CFPTR0LL RSCAN0.CFPTR0.UINT8[LL]
-#define RSCAN0CFPTR0LH RSCAN0.CFPTR0.UINT8[LH]
-#define RSCAN0CFPTR0H RSCAN0.CFPTR0.UINT16[H]
-#define RSCAN0CFPTR0HL RSCAN0.CFPTR0.UINT8[HL]
-#define RSCAN0CFPTR0HH RSCAN0.CFPTR0.UINT8[HH]
-#define RSCAN0CFDF00 RSCAN0.CFDF00.UINT32
-#define RSCAN0CFDF00L RSCAN0.CFDF00.UINT16[L]
-#define RSCAN0CFDF00LL RSCAN0.CFDF00.UINT8[LL]
-#define RSCAN0CFDF00LH RSCAN0.CFDF00.UINT8[LH]
-#define RSCAN0CFDF00H RSCAN0.CFDF00.UINT16[H]
-#define RSCAN0CFDF00HL RSCAN0.CFDF00.UINT8[HL]
-#define RSCAN0CFDF00HH RSCAN0.CFDF00.UINT8[HH]
-#define RSCAN0CFDF10 RSCAN0.CFDF10.UINT32
-#define RSCAN0CFDF10L RSCAN0.CFDF10.UINT16[L]
-#define RSCAN0CFDF10LL RSCAN0.CFDF10.UINT8[LL]
-#define RSCAN0CFDF10LH RSCAN0.CFDF10.UINT8[LH]
-#define RSCAN0CFDF10H RSCAN0.CFDF10.UINT16[H]
-#define RSCAN0CFDF10HL RSCAN0.CFDF10.UINT8[HL]
-#define RSCAN0CFDF10HH RSCAN0.CFDF10.UINT8[HH]
-#define RSCAN0CFID1 RSCAN0.CFID1.UINT32
-#define RSCAN0CFID1L RSCAN0.CFID1.UINT16[L]
-#define RSCAN0CFID1LL RSCAN0.CFID1.UINT8[LL]
-#define RSCAN0CFID1LH RSCAN0.CFID1.UINT8[LH]
-#define RSCAN0CFID1H RSCAN0.CFID1.UINT16[H]
-#define RSCAN0CFID1HL RSCAN0.CFID1.UINT8[HL]
-#define RSCAN0CFID1HH RSCAN0.CFID1.UINT8[HH]
-#define RSCAN0CFPTR1 RSCAN0.CFPTR1.UINT32
-#define RSCAN0CFPTR1L RSCAN0.CFPTR1.UINT16[L]
-#define RSCAN0CFPTR1LL RSCAN0.CFPTR1.UINT8[LL]
-#define RSCAN0CFPTR1LH RSCAN0.CFPTR1.UINT8[LH]
-#define RSCAN0CFPTR1H RSCAN0.CFPTR1.UINT16[H]
-#define RSCAN0CFPTR1HL RSCAN0.CFPTR1.UINT8[HL]
-#define RSCAN0CFPTR1HH RSCAN0.CFPTR1.UINT8[HH]
-#define RSCAN0CFDF01 RSCAN0.CFDF01.UINT32
-#define RSCAN0CFDF01L RSCAN0.CFDF01.UINT16[L]
-#define RSCAN0CFDF01LL RSCAN0.CFDF01.UINT8[LL]
-#define RSCAN0CFDF01LH RSCAN0.CFDF01.UINT8[LH]
-#define RSCAN0CFDF01H RSCAN0.CFDF01.UINT16[H]
-#define RSCAN0CFDF01HL RSCAN0.CFDF01.UINT8[HL]
-#define RSCAN0CFDF01HH RSCAN0.CFDF01.UINT8[HH]
-#define RSCAN0CFDF11 RSCAN0.CFDF11.UINT32
-#define RSCAN0CFDF11L RSCAN0.CFDF11.UINT16[L]
-#define RSCAN0CFDF11LL RSCAN0.CFDF11.UINT8[LL]
-#define RSCAN0CFDF11LH RSCAN0.CFDF11.UINT8[LH]
-#define RSCAN0CFDF11H RSCAN0.CFDF11.UINT16[H]
-#define RSCAN0CFDF11HL RSCAN0.CFDF11.UINT8[HL]
-#define RSCAN0CFDF11HH RSCAN0.CFDF11.UINT8[HH]
-#define RSCAN0CFID2 RSCAN0.CFID2.UINT32
-#define RSCAN0CFID2L RSCAN0.CFID2.UINT16[L]
-#define RSCAN0CFID2LL RSCAN0.CFID2.UINT8[LL]
-#define RSCAN0CFID2LH RSCAN0.CFID2.UINT8[LH]
-#define RSCAN0CFID2H RSCAN0.CFID2.UINT16[H]
-#define RSCAN0CFID2HL RSCAN0.CFID2.UINT8[HL]
-#define RSCAN0CFID2HH RSCAN0.CFID2.UINT8[HH]
-#define RSCAN0CFPTR2 RSCAN0.CFPTR2.UINT32
-#define RSCAN0CFPTR2L RSCAN0.CFPTR2.UINT16[L]
-#define RSCAN0CFPTR2LL RSCAN0.CFPTR2.UINT8[LL]
-#define RSCAN0CFPTR2LH RSCAN0.CFPTR2.UINT8[LH]
-#define RSCAN0CFPTR2H RSCAN0.CFPTR2.UINT16[H]
-#define RSCAN0CFPTR2HL RSCAN0.CFPTR2.UINT8[HL]
-#define RSCAN0CFPTR2HH RSCAN0.CFPTR2.UINT8[HH]
-#define RSCAN0CFDF02 RSCAN0.CFDF02.UINT32
-#define RSCAN0CFDF02L RSCAN0.CFDF02.UINT16[L]
-#define RSCAN0CFDF02LL RSCAN0.CFDF02.UINT8[LL]
-#define RSCAN0CFDF02LH RSCAN0.CFDF02.UINT8[LH]
-#define RSCAN0CFDF02H RSCAN0.CFDF02.UINT16[H]
-#define RSCAN0CFDF02HL RSCAN0.CFDF02.UINT8[HL]
-#define RSCAN0CFDF02HH RSCAN0.CFDF02.UINT8[HH]
-#define RSCAN0CFDF12 RSCAN0.CFDF12.UINT32
-#define RSCAN0CFDF12L RSCAN0.CFDF12.UINT16[L]
-#define RSCAN0CFDF12LL RSCAN0.CFDF12.UINT8[LL]
-#define RSCAN0CFDF12LH RSCAN0.CFDF12.UINT8[LH]
-#define RSCAN0CFDF12H RSCAN0.CFDF12.UINT16[H]
-#define RSCAN0CFDF12HL RSCAN0.CFDF12.UINT8[HL]
-#define RSCAN0CFDF12HH RSCAN0.CFDF12.UINT8[HH]
-#define RSCAN0CFID3 RSCAN0.CFID3.UINT32
-#define RSCAN0CFID3L RSCAN0.CFID3.UINT16[L]
-#define RSCAN0CFID3LL RSCAN0.CFID3.UINT8[LL]
-#define RSCAN0CFID3LH RSCAN0.CFID3.UINT8[LH]
-#define RSCAN0CFID3H RSCAN0.CFID3.UINT16[H]
-#define RSCAN0CFID3HL RSCAN0.CFID3.UINT8[HL]
-#define RSCAN0CFID3HH RSCAN0.CFID3.UINT8[HH]
-#define RSCAN0CFPTR3 RSCAN0.CFPTR3.UINT32
-#define RSCAN0CFPTR3L RSCAN0.CFPTR3.UINT16[L]
-#define RSCAN0CFPTR3LL RSCAN0.CFPTR3.UINT8[LL]
-#define RSCAN0CFPTR3LH RSCAN0.CFPTR3.UINT8[LH]
-#define RSCAN0CFPTR3H RSCAN0.CFPTR3.UINT16[H]
-#define RSCAN0CFPTR3HL RSCAN0.CFPTR3.UINT8[HL]
-#define RSCAN0CFPTR3HH RSCAN0.CFPTR3.UINT8[HH]
-#define RSCAN0CFDF03 RSCAN0.CFDF03.UINT32
-#define RSCAN0CFDF03L RSCAN0.CFDF03.UINT16[L]
-#define RSCAN0CFDF03LL RSCAN0.CFDF03.UINT8[LL]
-#define RSCAN0CFDF03LH RSCAN0.CFDF03.UINT8[LH]
-#define RSCAN0CFDF03H RSCAN0.CFDF03.UINT16[H]
-#define RSCAN0CFDF03HL RSCAN0.CFDF03.UINT8[HL]
-#define RSCAN0CFDF03HH RSCAN0.CFDF03.UINT8[HH]
-#define RSCAN0CFDF13 RSCAN0.CFDF13.UINT32
-#define RSCAN0CFDF13L RSCAN0.CFDF13.UINT16[L]
-#define RSCAN0CFDF13LL RSCAN0.CFDF13.UINT8[LL]
-#define RSCAN0CFDF13LH RSCAN0.CFDF13.UINT8[LH]
-#define RSCAN0CFDF13H RSCAN0.CFDF13.UINT16[H]
-#define RSCAN0CFDF13HL RSCAN0.CFDF13.UINT8[HL]
-#define RSCAN0CFDF13HH RSCAN0.CFDF13.UINT8[HH]
-#define RSCAN0CFID4 RSCAN0.CFID4.UINT32
-#define RSCAN0CFID4L RSCAN0.CFID4.UINT16[L]
-#define RSCAN0CFID4LL RSCAN0.CFID4.UINT8[LL]
-#define RSCAN0CFID4LH RSCAN0.CFID4.UINT8[LH]
-#define RSCAN0CFID4H RSCAN0.CFID4.UINT16[H]
-#define RSCAN0CFID4HL RSCAN0.CFID4.UINT8[HL]
-#define RSCAN0CFID4HH RSCAN0.CFID4.UINT8[HH]
-#define RSCAN0CFPTR4 RSCAN0.CFPTR4.UINT32
-#define RSCAN0CFPTR4L RSCAN0.CFPTR4.UINT16[L]
-#define RSCAN0CFPTR4LL RSCAN0.CFPTR4.UINT8[LL]
-#define RSCAN0CFPTR4LH RSCAN0.CFPTR4.UINT8[LH]
-#define RSCAN0CFPTR4H RSCAN0.CFPTR4.UINT16[H]
-#define RSCAN0CFPTR4HL RSCAN0.CFPTR4.UINT8[HL]
-#define RSCAN0CFPTR4HH RSCAN0.CFPTR4.UINT8[HH]
-#define RSCAN0CFDF04 RSCAN0.CFDF04.UINT32
-#define RSCAN0CFDF04L RSCAN0.CFDF04.UINT16[L]
-#define RSCAN0CFDF04LL RSCAN0.CFDF04.UINT8[LL]
-#define RSCAN0CFDF04LH RSCAN0.CFDF04.UINT8[LH]
-#define RSCAN0CFDF04H RSCAN0.CFDF04.UINT16[H]
-#define RSCAN0CFDF04HL RSCAN0.CFDF04.UINT8[HL]
-#define RSCAN0CFDF04HH RSCAN0.CFDF04.UINT8[HH]
-#define RSCAN0CFDF14 RSCAN0.CFDF14.UINT32
-#define RSCAN0CFDF14L RSCAN0.CFDF14.UINT16[L]
-#define RSCAN0CFDF14LL RSCAN0.CFDF14.UINT8[LL]
-#define RSCAN0CFDF14LH RSCAN0.CFDF14.UINT8[LH]
-#define RSCAN0CFDF14H RSCAN0.CFDF14.UINT16[H]
-#define RSCAN0CFDF14HL RSCAN0.CFDF14.UINT8[HL]
-#define RSCAN0CFDF14HH RSCAN0.CFDF14.UINT8[HH]
-#define RSCAN0CFID5 RSCAN0.CFID5.UINT32
-#define RSCAN0CFID5L RSCAN0.CFID5.UINT16[L]
-#define RSCAN0CFID5LL RSCAN0.CFID5.UINT8[LL]
-#define RSCAN0CFID5LH RSCAN0.CFID5.UINT8[LH]
-#define RSCAN0CFID5H RSCAN0.CFID5.UINT16[H]
-#define RSCAN0CFID5HL RSCAN0.CFID5.UINT8[HL]
-#define RSCAN0CFID5HH RSCAN0.CFID5.UINT8[HH]
-#define RSCAN0CFPTR5 RSCAN0.CFPTR5.UINT32
-#define RSCAN0CFPTR5L RSCAN0.CFPTR5.UINT16[L]
-#define RSCAN0CFPTR5LL RSCAN0.CFPTR5.UINT8[LL]
-#define RSCAN0CFPTR5LH RSCAN0.CFPTR5.UINT8[LH]
-#define RSCAN0CFPTR5H RSCAN0.CFPTR5.UINT16[H]
-#define RSCAN0CFPTR5HL RSCAN0.CFPTR5.UINT8[HL]
-#define RSCAN0CFPTR5HH RSCAN0.CFPTR5.UINT8[HH]
-#define RSCAN0CFDF05 RSCAN0.CFDF05.UINT32
-#define RSCAN0CFDF05L RSCAN0.CFDF05.UINT16[L]
-#define RSCAN0CFDF05LL RSCAN0.CFDF05.UINT8[LL]
-#define RSCAN0CFDF05LH RSCAN0.CFDF05.UINT8[LH]
-#define RSCAN0CFDF05H RSCAN0.CFDF05.UINT16[H]
-#define RSCAN0CFDF05HL RSCAN0.CFDF05.UINT8[HL]
-#define RSCAN0CFDF05HH RSCAN0.CFDF05.UINT8[HH]
-#define RSCAN0CFDF15 RSCAN0.CFDF15.UINT32
-#define RSCAN0CFDF15L RSCAN0.CFDF15.UINT16[L]
-#define RSCAN0CFDF15LL RSCAN0.CFDF15.UINT8[LL]
-#define RSCAN0CFDF15LH RSCAN0.CFDF15.UINT8[LH]
-#define RSCAN0CFDF15H RSCAN0.CFDF15.UINT16[H]
-#define RSCAN0CFDF15HL RSCAN0.CFDF15.UINT8[HL]
-#define RSCAN0CFDF15HH RSCAN0.CFDF15.UINT8[HH]
-#define RSCAN0CFID6 RSCAN0.CFID6.UINT32
-#define RSCAN0CFID6L RSCAN0.CFID6.UINT16[L]
-#define RSCAN0CFID6LL RSCAN0.CFID6.UINT8[LL]
-#define RSCAN0CFID6LH RSCAN0.CFID6.UINT8[LH]
-#define RSCAN0CFID6H RSCAN0.CFID6.UINT16[H]
-#define RSCAN0CFID6HL RSCAN0.CFID6.UINT8[HL]
-#define RSCAN0CFID6HH RSCAN0.CFID6.UINT8[HH]
-#define RSCAN0CFPTR6 RSCAN0.CFPTR6.UINT32
-#define RSCAN0CFPTR6L RSCAN0.CFPTR6.UINT16[L]
-#define RSCAN0CFPTR6LL RSCAN0.CFPTR6.UINT8[LL]
-#define RSCAN0CFPTR6LH RSCAN0.CFPTR6.UINT8[LH]
-#define RSCAN0CFPTR6H RSCAN0.CFPTR6.UINT16[H]
-#define RSCAN0CFPTR6HL RSCAN0.CFPTR6.UINT8[HL]
-#define RSCAN0CFPTR6HH RSCAN0.CFPTR6.UINT8[HH]
-#define RSCAN0CFDF06 RSCAN0.CFDF06.UINT32
-#define RSCAN0CFDF06L RSCAN0.CFDF06.UINT16[L]
-#define RSCAN0CFDF06LL RSCAN0.CFDF06.UINT8[LL]
-#define RSCAN0CFDF06LH RSCAN0.CFDF06.UINT8[LH]
-#define RSCAN0CFDF06H RSCAN0.CFDF06.UINT16[H]
-#define RSCAN0CFDF06HL RSCAN0.CFDF06.UINT8[HL]
-#define RSCAN0CFDF06HH RSCAN0.CFDF06.UINT8[HH]
-#define RSCAN0CFDF16 RSCAN0.CFDF16.UINT32
-#define RSCAN0CFDF16L RSCAN0.CFDF16.UINT16[L]
-#define RSCAN0CFDF16LL RSCAN0.CFDF16.UINT8[LL]
-#define RSCAN0CFDF16LH RSCAN0.CFDF16.UINT8[LH]
-#define RSCAN0CFDF16H RSCAN0.CFDF16.UINT16[H]
-#define RSCAN0CFDF16HL RSCAN0.CFDF16.UINT8[HL]
-#define RSCAN0CFDF16HH RSCAN0.CFDF16.UINT8[HH]
-#define RSCAN0CFID7 RSCAN0.CFID7.UINT32
-#define RSCAN0CFID7L RSCAN0.CFID7.UINT16[L]
-#define RSCAN0CFID7LL RSCAN0.CFID7.UINT8[LL]
-#define RSCAN0CFID7LH RSCAN0.CFID7.UINT8[LH]
-#define RSCAN0CFID7H RSCAN0.CFID7.UINT16[H]
-#define RSCAN0CFID7HL RSCAN0.CFID7.UINT8[HL]
-#define RSCAN0CFID7HH RSCAN0.CFID7.UINT8[HH]
-#define RSCAN0CFPTR7 RSCAN0.CFPTR7.UINT32
-#define RSCAN0CFPTR7L RSCAN0.CFPTR7.UINT16[L]
-#define RSCAN0CFPTR7LL RSCAN0.CFPTR7.UINT8[LL]
-#define RSCAN0CFPTR7LH RSCAN0.CFPTR7.UINT8[LH]
-#define RSCAN0CFPTR7H RSCAN0.CFPTR7.UINT16[H]
-#define RSCAN0CFPTR7HL RSCAN0.CFPTR7.UINT8[HL]
-#define RSCAN0CFPTR7HH RSCAN0.CFPTR7.UINT8[HH]
-#define RSCAN0CFDF07 RSCAN0.CFDF07.UINT32
-#define RSCAN0CFDF07L RSCAN0.CFDF07.UINT16[L]
-#define RSCAN0CFDF07LL RSCAN0.CFDF07.UINT8[LL]
-#define RSCAN0CFDF07LH RSCAN0.CFDF07.UINT8[LH]
-#define RSCAN0CFDF07H RSCAN0.CFDF07.UINT16[H]
-#define RSCAN0CFDF07HL RSCAN0.CFDF07.UINT8[HL]
-#define RSCAN0CFDF07HH RSCAN0.CFDF07.UINT8[HH]
-#define RSCAN0CFDF17 RSCAN0.CFDF17.UINT32
-#define RSCAN0CFDF17L RSCAN0.CFDF17.UINT16[L]
-#define RSCAN0CFDF17LL RSCAN0.CFDF17.UINT8[LL]
-#define RSCAN0CFDF17LH RSCAN0.CFDF17.UINT8[LH]
-#define RSCAN0CFDF17H RSCAN0.CFDF17.UINT16[H]
-#define RSCAN0CFDF17HL RSCAN0.CFDF17.UINT8[HL]
-#define RSCAN0CFDF17HH RSCAN0.CFDF17.UINT8[HH]
-#define RSCAN0CFID8 RSCAN0.CFID8.UINT32
-#define RSCAN0CFID8L RSCAN0.CFID8.UINT16[L]
-#define RSCAN0CFID8LL RSCAN0.CFID8.UINT8[LL]
-#define RSCAN0CFID8LH RSCAN0.CFID8.UINT8[LH]
-#define RSCAN0CFID8H RSCAN0.CFID8.UINT16[H]
-#define RSCAN0CFID8HL RSCAN0.CFID8.UINT8[HL]
-#define RSCAN0CFID8HH RSCAN0.CFID8.UINT8[HH]
-#define RSCAN0CFPTR8 RSCAN0.CFPTR8.UINT32
-#define RSCAN0CFPTR8L RSCAN0.CFPTR8.UINT16[L]
-#define RSCAN0CFPTR8LL RSCAN0.CFPTR8.UINT8[LL]
-#define RSCAN0CFPTR8LH RSCAN0.CFPTR8.UINT8[LH]
-#define RSCAN0CFPTR8H RSCAN0.CFPTR8.UINT16[H]
-#define RSCAN0CFPTR8HL RSCAN0.CFPTR8.UINT8[HL]
-#define RSCAN0CFPTR8HH RSCAN0.CFPTR8.UINT8[HH]
-#define RSCAN0CFDF08 RSCAN0.CFDF08.UINT32
-#define RSCAN0CFDF08L RSCAN0.CFDF08.UINT16[L]
-#define RSCAN0CFDF08LL RSCAN0.CFDF08.UINT8[LL]
-#define RSCAN0CFDF08LH RSCAN0.CFDF08.UINT8[LH]
-#define RSCAN0CFDF08H RSCAN0.CFDF08.UINT16[H]
-#define RSCAN0CFDF08HL RSCAN0.CFDF08.UINT8[HL]
-#define RSCAN0CFDF08HH RSCAN0.CFDF08.UINT8[HH]
-#define RSCAN0CFDF18 RSCAN0.CFDF18.UINT32
-#define RSCAN0CFDF18L RSCAN0.CFDF18.UINT16[L]
-#define RSCAN0CFDF18LL RSCAN0.CFDF18.UINT8[LL]
-#define RSCAN0CFDF18LH RSCAN0.CFDF18.UINT8[LH]
-#define RSCAN0CFDF18H RSCAN0.CFDF18.UINT16[H]
-#define RSCAN0CFDF18HL RSCAN0.CFDF18.UINT8[HL]
-#define RSCAN0CFDF18HH RSCAN0.CFDF18.UINT8[HH]
-#define RSCAN0CFID9 RSCAN0.CFID9.UINT32
-#define RSCAN0CFID9L RSCAN0.CFID9.UINT16[L]
-#define RSCAN0CFID9LL RSCAN0.CFID9.UINT8[LL]
-#define RSCAN0CFID9LH RSCAN0.CFID9.UINT8[LH]
-#define RSCAN0CFID9H RSCAN0.CFID9.UINT16[H]
-#define RSCAN0CFID9HL RSCAN0.CFID9.UINT8[HL]
-#define RSCAN0CFID9HH RSCAN0.CFID9.UINT8[HH]
-#define RSCAN0CFPTR9 RSCAN0.CFPTR9.UINT32
-#define RSCAN0CFPTR9L RSCAN0.CFPTR9.UINT16[L]
-#define RSCAN0CFPTR9LL RSCAN0.CFPTR9.UINT8[LL]
-#define RSCAN0CFPTR9LH RSCAN0.CFPTR9.UINT8[LH]
-#define RSCAN0CFPTR9H RSCAN0.CFPTR9.UINT16[H]
-#define RSCAN0CFPTR9HL RSCAN0.CFPTR9.UINT8[HL]
-#define RSCAN0CFPTR9HH RSCAN0.CFPTR9.UINT8[HH]
-#define RSCAN0CFDF09 RSCAN0.CFDF09.UINT32
-#define RSCAN0CFDF09L RSCAN0.CFDF09.UINT16[L]
-#define RSCAN0CFDF09LL RSCAN0.CFDF09.UINT8[LL]
-#define RSCAN0CFDF09LH RSCAN0.CFDF09.UINT8[LH]
-#define RSCAN0CFDF09H RSCAN0.CFDF09.UINT16[H]
-#define RSCAN0CFDF09HL RSCAN0.CFDF09.UINT8[HL]
-#define RSCAN0CFDF09HH RSCAN0.CFDF09.UINT8[HH]
-#define RSCAN0CFDF19 RSCAN0.CFDF19.UINT32
-#define RSCAN0CFDF19L RSCAN0.CFDF19.UINT16[L]
-#define RSCAN0CFDF19LL RSCAN0.CFDF19.UINT8[LL]
-#define RSCAN0CFDF19LH RSCAN0.CFDF19.UINT8[LH]
-#define RSCAN0CFDF19H RSCAN0.CFDF19.UINT16[H]
-#define RSCAN0CFDF19HL RSCAN0.CFDF19.UINT8[HL]
-#define RSCAN0CFDF19HH RSCAN0.CFDF19.UINT8[HH]
-#define RSCAN0CFID10 RSCAN0.CFID10.UINT32
-#define RSCAN0CFID10L RSCAN0.CFID10.UINT16[L]
-#define RSCAN0CFID10LL RSCAN0.CFID10.UINT8[LL]
-#define RSCAN0CFID10LH RSCAN0.CFID10.UINT8[LH]
-#define RSCAN0CFID10H RSCAN0.CFID10.UINT16[H]
-#define RSCAN0CFID10HL RSCAN0.CFID10.UINT8[HL]
-#define RSCAN0CFID10HH RSCAN0.CFID10.UINT8[HH]
-#define RSCAN0CFPTR10 RSCAN0.CFPTR10.UINT32
-#define RSCAN0CFPTR10L RSCAN0.CFPTR10.UINT16[L]
-#define RSCAN0CFPTR10LL RSCAN0.CFPTR10.UINT8[LL]
-#define RSCAN0CFPTR10LH RSCAN0.CFPTR10.UINT8[LH]
-#define RSCAN0CFPTR10H RSCAN0.CFPTR10.UINT16[H]
-#define RSCAN0CFPTR10HL RSCAN0.CFPTR10.UINT8[HL]
-#define RSCAN0CFPTR10HH RSCAN0.CFPTR10.UINT8[HH]
-#define RSCAN0CFDF010 RSCAN0.CFDF010.UINT32
-#define RSCAN0CFDF010L RSCAN0.CFDF010.UINT16[L]
-#define RSCAN0CFDF010LL RSCAN0.CFDF010.UINT8[LL]
-#define RSCAN0CFDF010LH RSCAN0.CFDF010.UINT8[LH]
-#define RSCAN0CFDF010H RSCAN0.CFDF010.UINT16[H]
-#define RSCAN0CFDF010HL RSCAN0.CFDF010.UINT8[HL]
-#define RSCAN0CFDF010HH RSCAN0.CFDF010.UINT8[HH]
-#define RSCAN0CFDF110 RSCAN0.CFDF110.UINT32
-#define RSCAN0CFDF110L RSCAN0.CFDF110.UINT16[L]
-#define RSCAN0CFDF110LL RSCAN0.CFDF110.UINT8[LL]
-#define RSCAN0CFDF110LH RSCAN0.CFDF110.UINT8[LH]
-#define RSCAN0CFDF110H RSCAN0.CFDF110.UINT16[H]
-#define RSCAN0CFDF110HL RSCAN0.CFDF110.UINT8[HL]
-#define RSCAN0CFDF110HH RSCAN0.CFDF110.UINT8[HH]
-#define RSCAN0CFID11 RSCAN0.CFID11.UINT32
-#define RSCAN0CFID11L RSCAN0.CFID11.UINT16[L]
-#define RSCAN0CFID11LL RSCAN0.CFID11.UINT8[LL]
-#define RSCAN0CFID11LH RSCAN0.CFID11.UINT8[LH]
-#define RSCAN0CFID11H RSCAN0.CFID11.UINT16[H]
-#define RSCAN0CFID11HL RSCAN0.CFID11.UINT8[HL]
-#define RSCAN0CFID11HH RSCAN0.CFID11.UINT8[HH]
-#define RSCAN0CFPTR11 RSCAN0.CFPTR11.UINT32
-#define RSCAN0CFPTR11L RSCAN0.CFPTR11.UINT16[L]
-#define RSCAN0CFPTR11LL RSCAN0.CFPTR11.UINT8[LL]
-#define RSCAN0CFPTR11LH RSCAN0.CFPTR11.UINT8[LH]
-#define RSCAN0CFPTR11H RSCAN0.CFPTR11.UINT16[H]
-#define RSCAN0CFPTR11HL RSCAN0.CFPTR11.UINT8[HL]
-#define RSCAN0CFPTR11HH RSCAN0.CFPTR11.UINT8[HH]
-#define RSCAN0CFDF011 RSCAN0.CFDF011.UINT32
-#define RSCAN0CFDF011L RSCAN0.CFDF011.UINT16[L]
-#define RSCAN0CFDF011LL RSCAN0.CFDF011.UINT8[LL]
-#define RSCAN0CFDF011LH RSCAN0.CFDF011.UINT8[LH]
-#define RSCAN0CFDF011H RSCAN0.CFDF011.UINT16[H]
-#define RSCAN0CFDF011HL RSCAN0.CFDF011.UINT8[HL]
-#define RSCAN0CFDF011HH RSCAN0.CFDF011.UINT8[HH]
-#define RSCAN0CFDF111 RSCAN0.CFDF111.UINT32
-#define RSCAN0CFDF111L RSCAN0.CFDF111.UINT16[L]
-#define RSCAN0CFDF111LL RSCAN0.CFDF111.UINT8[LL]
-#define RSCAN0CFDF111LH RSCAN0.CFDF111.UINT8[LH]
-#define RSCAN0CFDF111H RSCAN0.CFDF111.UINT16[H]
-#define RSCAN0CFDF111HL RSCAN0.CFDF111.UINT8[HL]
-#define RSCAN0CFDF111HH RSCAN0.CFDF111.UINT8[HH]
-#define RSCAN0CFID12 RSCAN0.CFID12.UINT32
-#define RSCAN0CFID12L RSCAN0.CFID12.UINT16[L]
-#define RSCAN0CFID12LL RSCAN0.CFID12.UINT8[LL]
-#define RSCAN0CFID12LH RSCAN0.CFID12.UINT8[LH]
-#define RSCAN0CFID12H RSCAN0.CFID12.UINT16[H]
-#define RSCAN0CFID12HL RSCAN0.CFID12.UINT8[HL]
-#define RSCAN0CFID12HH RSCAN0.CFID12.UINT8[HH]
-#define RSCAN0CFPTR12 RSCAN0.CFPTR12.UINT32
-#define RSCAN0CFPTR12L RSCAN0.CFPTR12.UINT16[L]
-#define RSCAN0CFPTR12LL RSCAN0.CFPTR12.UINT8[LL]
-#define RSCAN0CFPTR12LH RSCAN0.CFPTR12.UINT8[LH]
-#define RSCAN0CFPTR12H RSCAN0.CFPTR12.UINT16[H]
-#define RSCAN0CFPTR12HL RSCAN0.CFPTR12.UINT8[HL]
-#define RSCAN0CFPTR12HH RSCAN0.CFPTR12.UINT8[HH]
-#define RSCAN0CFDF012 RSCAN0.CFDF012.UINT32
-#define RSCAN0CFDF012L RSCAN0.CFDF012.UINT16[L]
-#define RSCAN0CFDF012LL RSCAN0.CFDF012.UINT8[LL]
-#define RSCAN0CFDF012LH RSCAN0.CFDF012.UINT8[LH]
-#define RSCAN0CFDF012H RSCAN0.CFDF012.UINT16[H]
-#define RSCAN0CFDF012HL RSCAN0.CFDF012.UINT8[HL]
-#define RSCAN0CFDF012HH RSCAN0.CFDF012.UINT8[HH]
-#define RSCAN0CFDF112 RSCAN0.CFDF112.UINT32
-#define RSCAN0CFDF112L RSCAN0.CFDF112.UINT16[L]
-#define RSCAN0CFDF112LL RSCAN0.CFDF112.UINT8[LL]
-#define RSCAN0CFDF112LH RSCAN0.CFDF112.UINT8[LH]
-#define RSCAN0CFDF112H RSCAN0.CFDF112.UINT16[H]
-#define RSCAN0CFDF112HL RSCAN0.CFDF112.UINT8[HL]
-#define RSCAN0CFDF112HH RSCAN0.CFDF112.UINT8[HH]
-#define RSCAN0CFID13 RSCAN0.CFID13.UINT32
-#define RSCAN0CFID13L RSCAN0.CFID13.UINT16[L]
-#define RSCAN0CFID13LL RSCAN0.CFID13.UINT8[LL]
-#define RSCAN0CFID13LH RSCAN0.CFID13.UINT8[LH]
-#define RSCAN0CFID13H RSCAN0.CFID13.UINT16[H]
-#define RSCAN0CFID13HL RSCAN0.CFID13.UINT8[HL]
-#define RSCAN0CFID13HH RSCAN0.CFID13.UINT8[HH]
-#define RSCAN0CFPTR13 RSCAN0.CFPTR13.UINT32
-#define RSCAN0CFPTR13L RSCAN0.CFPTR13.UINT16[L]
-#define RSCAN0CFPTR13LL RSCAN0.CFPTR13.UINT8[LL]
-#define RSCAN0CFPTR13LH RSCAN0.CFPTR13.UINT8[LH]
-#define RSCAN0CFPTR13H RSCAN0.CFPTR13.UINT16[H]
-#define RSCAN0CFPTR13HL RSCAN0.CFPTR13.UINT8[HL]
-#define RSCAN0CFPTR13HH RSCAN0.CFPTR13.UINT8[HH]
-#define RSCAN0CFDF013 RSCAN0.CFDF013.UINT32
-#define RSCAN0CFDF013L RSCAN0.CFDF013.UINT16[L]
-#define RSCAN0CFDF013LL RSCAN0.CFDF013.UINT8[LL]
-#define RSCAN0CFDF013LH RSCAN0.CFDF013.UINT8[LH]
-#define RSCAN0CFDF013H RSCAN0.CFDF013.UINT16[H]
-#define RSCAN0CFDF013HL RSCAN0.CFDF013.UINT8[HL]
-#define RSCAN0CFDF013HH RSCAN0.CFDF013.UINT8[HH]
-#define RSCAN0CFDF113 RSCAN0.CFDF113.UINT32
-#define RSCAN0CFDF113L RSCAN0.CFDF113.UINT16[L]
-#define RSCAN0CFDF113LL RSCAN0.CFDF113.UINT8[LL]
-#define RSCAN0CFDF113LH RSCAN0.CFDF113.UINT8[LH]
-#define RSCAN0CFDF113H RSCAN0.CFDF113.UINT16[H]
-#define RSCAN0CFDF113HL RSCAN0.CFDF113.UINT8[HL]
-#define RSCAN0CFDF113HH RSCAN0.CFDF113.UINT8[HH]
-#define RSCAN0CFID14 RSCAN0.CFID14.UINT32
-#define RSCAN0CFID14L RSCAN0.CFID14.UINT16[L]
-#define RSCAN0CFID14LL RSCAN0.CFID14.UINT8[LL]
-#define RSCAN0CFID14LH RSCAN0.CFID14.UINT8[LH]
-#define RSCAN0CFID14H RSCAN0.CFID14.UINT16[H]
-#define RSCAN0CFID14HL RSCAN0.CFID14.UINT8[HL]
-#define RSCAN0CFID14HH RSCAN0.CFID14.UINT8[HH]
-#define RSCAN0CFPTR14 RSCAN0.CFPTR14.UINT32
-#define RSCAN0CFPTR14L RSCAN0.CFPTR14.UINT16[L]
-#define RSCAN0CFPTR14LL RSCAN0.CFPTR14.UINT8[LL]
-#define RSCAN0CFPTR14LH RSCAN0.CFPTR14.UINT8[LH]
-#define RSCAN0CFPTR14H RSCAN0.CFPTR14.UINT16[H]
-#define RSCAN0CFPTR14HL RSCAN0.CFPTR14.UINT8[HL]
-#define RSCAN0CFPTR14HH RSCAN0.CFPTR14.UINT8[HH]
-#define RSCAN0CFDF014 RSCAN0.CFDF014.UINT32
-#define RSCAN0CFDF014L RSCAN0.CFDF014.UINT16[L]
-#define RSCAN0CFDF014LL RSCAN0.CFDF014.UINT8[LL]
-#define RSCAN0CFDF014LH RSCAN0.CFDF014.UINT8[LH]
-#define RSCAN0CFDF014H RSCAN0.CFDF014.UINT16[H]
-#define RSCAN0CFDF014HL RSCAN0.CFDF014.UINT8[HL]
-#define RSCAN0CFDF014HH RSCAN0.CFDF014.UINT8[HH]
-#define RSCAN0CFDF114 RSCAN0.CFDF114.UINT32
-#define RSCAN0CFDF114L RSCAN0.CFDF114.UINT16[L]
-#define RSCAN0CFDF114LL RSCAN0.CFDF114.UINT8[LL]
-#define RSCAN0CFDF114LH RSCAN0.CFDF114.UINT8[LH]
-#define RSCAN0CFDF114H RSCAN0.CFDF114.UINT16[H]
-#define RSCAN0CFDF114HL RSCAN0.CFDF114.UINT8[HL]
-#define RSCAN0CFDF114HH RSCAN0.CFDF114.UINT8[HH]
-#define RSCAN0TMID0 RSCAN0.TMID0.UINT32
-#define RSCAN0TMID0L RSCAN0.TMID0.UINT16[L]
-#define RSCAN0TMID0LL RSCAN0.TMID0.UINT8[LL]
-#define RSCAN0TMID0LH RSCAN0.TMID0.UINT8[LH]
-#define RSCAN0TMID0H RSCAN0.TMID0.UINT16[H]
-#define RSCAN0TMID0HL RSCAN0.TMID0.UINT8[HL]
-#define RSCAN0TMID0HH RSCAN0.TMID0.UINT8[HH]
-#define RSCAN0TMPTR0 RSCAN0.TMPTR0.UINT32
-#define RSCAN0TMPTR0L RSCAN0.TMPTR0.UINT16[L]
-#define RSCAN0TMPTR0LL RSCAN0.TMPTR0.UINT8[LL]
-#define RSCAN0TMPTR0LH RSCAN0.TMPTR0.UINT8[LH]
-#define RSCAN0TMPTR0H RSCAN0.TMPTR0.UINT16[H]
-#define RSCAN0TMPTR0HL RSCAN0.TMPTR0.UINT8[HL]
-#define RSCAN0TMPTR0HH RSCAN0.TMPTR0.UINT8[HH]
-#define RSCAN0TMDF00 RSCAN0.TMDF00.UINT32
-#define RSCAN0TMDF00L RSCAN0.TMDF00.UINT16[L]
-#define RSCAN0TMDF00LL RSCAN0.TMDF00.UINT8[LL]
-#define RSCAN0TMDF00LH RSCAN0.TMDF00.UINT8[LH]
-#define RSCAN0TMDF00H RSCAN0.TMDF00.UINT16[H]
-#define RSCAN0TMDF00HL RSCAN0.TMDF00.UINT8[HL]
-#define RSCAN0TMDF00HH RSCAN0.TMDF00.UINT8[HH]
-#define RSCAN0TMDF10 RSCAN0.TMDF10.UINT32
-#define RSCAN0TMDF10L RSCAN0.TMDF10.UINT16[L]
-#define RSCAN0TMDF10LL RSCAN0.TMDF10.UINT8[LL]
-#define RSCAN0TMDF10LH RSCAN0.TMDF10.UINT8[LH]
-#define RSCAN0TMDF10H RSCAN0.TMDF10.UINT16[H]
-#define RSCAN0TMDF10HL RSCAN0.TMDF10.UINT8[HL]
-#define RSCAN0TMDF10HH RSCAN0.TMDF10.UINT8[HH]
-#define RSCAN0TMID1 RSCAN0.TMID1.UINT32
-#define RSCAN0TMID1L RSCAN0.TMID1.UINT16[L]
-#define RSCAN0TMID1LL RSCAN0.TMID1.UINT8[LL]
-#define RSCAN0TMID1LH RSCAN0.TMID1.UINT8[LH]
-#define RSCAN0TMID1H RSCAN0.TMID1.UINT16[H]
-#define RSCAN0TMID1HL RSCAN0.TMID1.UINT8[HL]
-#define RSCAN0TMID1HH RSCAN0.TMID1.UINT8[HH]
-#define RSCAN0TMPTR1 RSCAN0.TMPTR1.UINT32
-#define RSCAN0TMPTR1L RSCAN0.TMPTR1.UINT16[L]
-#define RSCAN0TMPTR1LL RSCAN0.TMPTR1.UINT8[LL]
-#define RSCAN0TMPTR1LH RSCAN0.TMPTR1.UINT8[LH]
-#define RSCAN0TMPTR1H RSCAN0.TMPTR1.UINT16[H]
-#define RSCAN0TMPTR1HL RSCAN0.TMPTR1.UINT8[HL]
-#define RSCAN0TMPTR1HH RSCAN0.TMPTR1.UINT8[HH]
-#define RSCAN0TMDF01 RSCAN0.TMDF01.UINT32
-#define RSCAN0TMDF01L RSCAN0.TMDF01.UINT16[L]
-#define RSCAN0TMDF01LL RSCAN0.TMDF01.UINT8[LL]
-#define RSCAN0TMDF01LH RSCAN0.TMDF01.UINT8[LH]
-#define RSCAN0TMDF01H RSCAN0.TMDF01.UINT16[H]
-#define RSCAN0TMDF01HL RSCAN0.TMDF01.UINT8[HL]
-#define RSCAN0TMDF01HH RSCAN0.TMDF01.UINT8[HH]
-#define RSCAN0TMDF11 RSCAN0.TMDF11.UINT32
-#define RSCAN0TMDF11L RSCAN0.TMDF11.UINT16[L]
-#define RSCAN0TMDF11LL RSCAN0.TMDF11.UINT8[LL]
-#define RSCAN0TMDF11LH RSCAN0.TMDF11.UINT8[LH]
-#define RSCAN0TMDF11H RSCAN0.TMDF11.UINT16[H]
-#define RSCAN0TMDF11HL RSCAN0.TMDF11.UINT8[HL]
-#define RSCAN0TMDF11HH RSCAN0.TMDF11.UINT8[HH]
-#define RSCAN0TMID2 RSCAN0.TMID2.UINT32
-#define RSCAN0TMID2L RSCAN0.TMID2.UINT16[L]
-#define RSCAN0TMID2LL RSCAN0.TMID2.UINT8[LL]
-#define RSCAN0TMID2LH RSCAN0.TMID2.UINT8[LH]
-#define RSCAN0TMID2H RSCAN0.TMID2.UINT16[H]
-#define RSCAN0TMID2HL RSCAN0.TMID2.UINT8[HL]
-#define RSCAN0TMID2HH RSCAN0.TMID2.UINT8[HH]
-#define RSCAN0TMPTR2 RSCAN0.TMPTR2.UINT32
-#define RSCAN0TMPTR2L RSCAN0.TMPTR2.UINT16[L]
-#define RSCAN0TMPTR2LL RSCAN0.TMPTR2.UINT8[LL]
-#define RSCAN0TMPTR2LH RSCAN0.TMPTR2.UINT8[LH]
-#define RSCAN0TMPTR2H RSCAN0.TMPTR2.UINT16[H]
-#define RSCAN0TMPTR2HL RSCAN0.TMPTR2.UINT8[HL]
-#define RSCAN0TMPTR2HH RSCAN0.TMPTR2.UINT8[HH]
-#define RSCAN0TMDF02 RSCAN0.TMDF02.UINT32
-#define RSCAN0TMDF02L RSCAN0.TMDF02.UINT16[L]
-#define RSCAN0TMDF02LL RSCAN0.TMDF02.UINT8[LL]
-#define RSCAN0TMDF02LH RSCAN0.TMDF02.UINT8[LH]
-#define RSCAN0TMDF02H RSCAN0.TMDF02.UINT16[H]
-#define RSCAN0TMDF02HL RSCAN0.TMDF02.UINT8[HL]
-#define RSCAN0TMDF02HH RSCAN0.TMDF02.UINT8[HH]
-#define RSCAN0TMDF12 RSCAN0.TMDF12.UINT32
-#define RSCAN0TMDF12L RSCAN0.TMDF12.UINT16[L]
-#define RSCAN0TMDF12LL RSCAN0.TMDF12.UINT8[LL]
-#define RSCAN0TMDF12LH RSCAN0.TMDF12.UINT8[LH]
-#define RSCAN0TMDF12H RSCAN0.TMDF12.UINT16[H]
-#define RSCAN0TMDF12HL RSCAN0.TMDF12.UINT8[HL]
-#define RSCAN0TMDF12HH RSCAN0.TMDF12.UINT8[HH]
-#define RSCAN0TMID3 RSCAN0.TMID3.UINT32
-#define RSCAN0TMID3L RSCAN0.TMID3.UINT16[L]
-#define RSCAN0TMID3LL RSCAN0.TMID3.UINT8[LL]
-#define RSCAN0TMID3LH RSCAN0.TMID3.UINT8[LH]
-#define RSCAN0TMID3H RSCAN0.TMID3.UINT16[H]
-#define RSCAN0TMID3HL RSCAN0.TMID3.UINT8[HL]
-#define RSCAN0TMID3HH RSCAN0.TMID3.UINT8[HH]
-#define RSCAN0TMPTR3 RSCAN0.TMPTR3.UINT32
-#define RSCAN0TMPTR3L RSCAN0.TMPTR3.UINT16[L]
-#define RSCAN0TMPTR3LL RSCAN0.TMPTR3.UINT8[LL]
-#define RSCAN0TMPTR3LH RSCAN0.TMPTR3.UINT8[LH]
-#define RSCAN0TMPTR3H RSCAN0.TMPTR3.UINT16[H]
-#define RSCAN0TMPTR3HL RSCAN0.TMPTR3.UINT8[HL]
-#define RSCAN0TMPTR3HH RSCAN0.TMPTR3.UINT8[HH]
-#define RSCAN0TMDF03 RSCAN0.TMDF03.UINT32
-#define RSCAN0TMDF03L RSCAN0.TMDF03.UINT16[L]
-#define RSCAN0TMDF03LL RSCAN0.TMDF03.UINT8[LL]
-#define RSCAN0TMDF03LH RSCAN0.TMDF03.UINT8[LH]
-#define RSCAN0TMDF03H RSCAN0.TMDF03.UINT16[H]
-#define RSCAN0TMDF03HL RSCAN0.TMDF03.UINT8[HL]
-#define RSCAN0TMDF03HH RSCAN0.TMDF03.UINT8[HH]
-#define RSCAN0TMDF13 RSCAN0.TMDF13.UINT32
-#define RSCAN0TMDF13L RSCAN0.TMDF13.UINT16[L]
-#define RSCAN0TMDF13LL RSCAN0.TMDF13.UINT8[LL]
-#define RSCAN0TMDF13LH RSCAN0.TMDF13.UINT8[LH]
-#define RSCAN0TMDF13H RSCAN0.TMDF13.UINT16[H]
-#define RSCAN0TMDF13HL RSCAN0.TMDF13.UINT8[HL]
-#define RSCAN0TMDF13HH RSCAN0.TMDF13.UINT8[HH]
-#define RSCAN0TMID4 RSCAN0.TMID4.UINT32
-#define RSCAN0TMID4L RSCAN0.TMID4.UINT16[L]
-#define RSCAN0TMID4LL RSCAN0.TMID4.UINT8[LL]
-#define RSCAN0TMID4LH RSCAN0.TMID4.UINT8[LH]
-#define RSCAN0TMID4H RSCAN0.TMID4.UINT16[H]
-#define RSCAN0TMID4HL RSCAN0.TMID4.UINT8[HL]
-#define RSCAN0TMID4HH RSCAN0.TMID4.UINT8[HH]
-#define RSCAN0TMPTR4 RSCAN0.TMPTR4.UINT32
-#define RSCAN0TMPTR4L RSCAN0.TMPTR4.UINT16[L]
-#define RSCAN0TMPTR4LL RSCAN0.TMPTR4.UINT8[LL]
-#define RSCAN0TMPTR4LH RSCAN0.TMPTR4.UINT8[LH]
-#define RSCAN0TMPTR4H RSCAN0.TMPTR4.UINT16[H]
-#define RSCAN0TMPTR4HL RSCAN0.TMPTR4.UINT8[HL]
-#define RSCAN0TMPTR4HH RSCAN0.TMPTR4.UINT8[HH]
-#define RSCAN0TMDF04 RSCAN0.TMDF04.UINT32
-#define RSCAN0TMDF04L RSCAN0.TMDF04.UINT16[L]
-#define RSCAN0TMDF04LL RSCAN0.TMDF04.UINT8[LL]
-#define RSCAN0TMDF04LH RSCAN0.TMDF04.UINT8[LH]
-#define RSCAN0TMDF04H RSCAN0.TMDF04.UINT16[H]
-#define RSCAN0TMDF04HL RSCAN0.TMDF04.UINT8[HL]
-#define RSCAN0TMDF04HH RSCAN0.TMDF04.UINT8[HH]
-#define RSCAN0TMDF14 RSCAN0.TMDF14.UINT32
-#define RSCAN0TMDF14L RSCAN0.TMDF14.UINT16[L]
-#define RSCAN0TMDF14LL RSCAN0.TMDF14.UINT8[LL]
-#define RSCAN0TMDF14LH RSCAN0.TMDF14.UINT8[LH]
-#define RSCAN0TMDF14H RSCAN0.TMDF14.UINT16[H]
-#define RSCAN0TMDF14HL RSCAN0.TMDF14.UINT8[HL]
-#define RSCAN0TMDF14HH RSCAN0.TMDF14.UINT8[HH]
-#define RSCAN0TMID5 RSCAN0.TMID5.UINT32
-#define RSCAN0TMID5L RSCAN0.TMID5.UINT16[L]
-#define RSCAN0TMID5LL RSCAN0.TMID5.UINT8[LL]
-#define RSCAN0TMID5LH RSCAN0.TMID5.UINT8[LH]
-#define RSCAN0TMID5H RSCAN0.TMID5.UINT16[H]
-#define RSCAN0TMID5HL RSCAN0.TMID5.UINT8[HL]
-#define RSCAN0TMID5HH RSCAN0.TMID5.UINT8[HH]
-#define RSCAN0TMPTR5 RSCAN0.TMPTR5.UINT32
-#define RSCAN0TMPTR5L RSCAN0.TMPTR5.UINT16[L]
-#define RSCAN0TMPTR5LL RSCAN0.TMPTR5.UINT8[LL]
-#define RSCAN0TMPTR5LH RSCAN0.TMPTR5.UINT8[LH]
-#define RSCAN0TMPTR5H RSCAN0.TMPTR5.UINT16[H]
-#define RSCAN0TMPTR5HL RSCAN0.TMPTR5.UINT8[HL]
-#define RSCAN0TMPTR5HH RSCAN0.TMPTR5.UINT8[HH]
-#define RSCAN0TMDF05 RSCAN0.TMDF05.UINT32
-#define RSCAN0TMDF05L RSCAN0.TMDF05.UINT16[L]
-#define RSCAN0TMDF05LL RSCAN0.TMDF05.UINT8[LL]
-#define RSCAN0TMDF05LH RSCAN0.TMDF05.UINT8[LH]
-#define RSCAN0TMDF05H RSCAN0.TMDF05.UINT16[H]
-#define RSCAN0TMDF05HL RSCAN0.TMDF05.UINT8[HL]
-#define RSCAN0TMDF05HH RSCAN0.TMDF05.UINT8[HH]
-#define RSCAN0TMDF15 RSCAN0.TMDF15.UINT32
-#define RSCAN0TMDF15L RSCAN0.TMDF15.UINT16[L]
-#define RSCAN0TMDF15LL RSCAN0.TMDF15.UINT8[LL]
-#define RSCAN0TMDF15LH RSCAN0.TMDF15.UINT8[LH]
-#define RSCAN0TMDF15H RSCAN0.TMDF15.UINT16[H]
-#define RSCAN0TMDF15HL RSCAN0.TMDF15.UINT8[HL]
-#define RSCAN0TMDF15HH RSCAN0.TMDF15.UINT8[HH]
-#define RSCAN0TMID6 RSCAN0.TMID6.UINT32
-#define RSCAN0TMID6L RSCAN0.TMID6.UINT16[L]
-#define RSCAN0TMID6LL RSCAN0.TMID6.UINT8[LL]
-#define RSCAN0TMID6LH RSCAN0.TMID6.UINT8[LH]
-#define RSCAN0TMID6H RSCAN0.TMID6.UINT16[H]
-#define RSCAN0TMID6HL RSCAN0.TMID6.UINT8[HL]
-#define RSCAN0TMID6HH RSCAN0.TMID6.UINT8[HH]
-#define RSCAN0TMPTR6 RSCAN0.TMPTR6.UINT32
-#define RSCAN0TMPTR6L RSCAN0.TMPTR6.UINT16[L]
-#define RSCAN0TMPTR6LL RSCAN0.TMPTR6.UINT8[LL]
-#define RSCAN0TMPTR6LH RSCAN0.TMPTR6.UINT8[LH]
-#define RSCAN0TMPTR6H RSCAN0.TMPTR6.UINT16[H]
-#define RSCAN0TMPTR6HL RSCAN0.TMPTR6.UINT8[HL]
-#define RSCAN0TMPTR6HH RSCAN0.TMPTR6.UINT8[HH]
-#define RSCAN0TMDF06 RSCAN0.TMDF06.UINT32
-#define RSCAN0TMDF06L RSCAN0.TMDF06.UINT16[L]
-#define RSCAN0TMDF06LL RSCAN0.TMDF06.UINT8[LL]
-#define RSCAN0TMDF06LH RSCAN0.TMDF06.UINT8[LH]
-#define RSCAN0TMDF06H RSCAN0.TMDF06.UINT16[H]
-#define RSCAN0TMDF06HL RSCAN0.TMDF06.UINT8[HL]
-#define RSCAN0TMDF06HH RSCAN0.TMDF06.UINT8[HH]
-#define RSCAN0TMDF16 RSCAN0.TMDF16.UINT32
-#define RSCAN0TMDF16L RSCAN0.TMDF16.UINT16[L]
-#define RSCAN0TMDF16LL RSCAN0.TMDF16.UINT8[LL]
-#define RSCAN0TMDF16LH RSCAN0.TMDF16.UINT8[LH]
-#define RSCAN0TMDF16H RSCAN0.TMDF16.UINT16[H]
-#define RSCAN0TMDF16HL RSCAN0.TMDF16.UINT8[HL]
-#define RSCAN0TMDF16HH RSCAN0.TMDF16.UINT8[HH]
-#define RSCAN0TMID7 RSCAN0.TMID7.UINT32
-#define RSCAN0TMID7L RSCAN0.TMID7.UINT16[L]
-#define RSCAN0TMID7LL RSCAN0.TMID7.UINT8[LL]
-#define RSCAN0TMID7LH RSCAN0.TMID7.UINT8[LH]
-#define RSCAN0TMID7H RSCAN0.TMID7.UINT16[H]
-#define RSCAN0TMID7HL RSCAN0.TMID7.UINT8[HL]
-#define RSCAN0TMID7HH RSCAN0.TMID7.UINT8[HH]
-#define RSCAN0TMPTR7 RSCAN0.TMPTR7.UINT32
-#define RSCAN0TMPTR7L RSCAN0.TMPTR7.UINT16[L]
-#define RSCAN0TMPTR7LL RSCAN0.TMPTR7.UINT8[LL]
-#define RSCAN0TMPTR7LH RSCAN0.TMPTR7.UINT8[LH]
-#define RSCAN0TMPTR7H RSCAN0.TMPTR7.UINT16[H]
-#define RSCAN0TMPTR7HL RSCAN0.TMPTR7.UINT8[HL]
-#define RSCAN0TMPTR7HH RSCAN0.TMPTR7.UINT8[HH]
-#define RSCAN0TMDF07 RSCAN0.TMDF07.UINT32
-#define RSCAN0TMDF07L RSCAN0.TMDF07.UINT16[L]
-#define RSCAN0TMDF07LL RSCAN0.TMDF07.UINT8[LL]
-#define RSCAN0TMDF07LH RSCAN0.TMDF07.UINT8[LH]
-#define RSCAN0TMDF07H RSCAN0.TMDF07.UINT16[H]
-#define RSCAN0TMDF07HL RSCAN0.TMDF07.UINT8[HL]
-#define RSCAN0TMDF07HH RSCAN0.TMDF07.UINT8[HH]
-#define RSCAN0TMDF17 RSCAN0.TMDF17.UINT32
-#define RSCAN0TMDF17L RSCAN0.TMDF17.UINT16[L]
-#define RSCAN0TMDF17LL RSCAN0.TMDF17.UINT8[LL]
-#define RSCAN0TMDF17LH RSCAN0.TMDF17.UINT8[LH]
-#define RSCAN0TMDF17H RSCAN0.TMDF17.UINT16[H]
-#define RSCAN0TMDF17HL RSCAN0.TMDF17.UINT8[HL]
-#define RSCAN0TMDF17HH RSCAN0.TMDF17.UINT8[HH]
-#define RSCAN0TMID8 RSCAN0.TMID8.UINT32
-#define RSCAN0TMID8L RSCAN0.TMID8.UINT16[L]
-#define RSCAN0TMID8LL RSCAN0.TMID8.UINT8[LL]
-#define RSCAN0TMID8LH RSCAN0.TMID8.UINT8[LH]
-#define RSCAN0TMID8H RSCAN0.TMID8.UINT16[H]
-#define RSCAN0TMID8HL RSCAN0.TMID8.UINT8[HL]
-#define RSCAN0TMID8HH RSCAN0.TMID8.UINT8[HH]
-#define RSCAN0TMPTR8 RSCAN0.TMPTR8.UINT32
-#define RSCAN0TMPTR8L RSCAN0.TMPTR8.UINT16[L]
-#define RSCAN0TMPTR8LL RSCAN0.TMPTR8.UINT8[LL]
-#define RSCAN0TMPTR8LH RSCAN0.TMPTR8.UINT8[LH]
-#define RSCAN0TMPTR8H RSCAN0.TMPTR8.UINT16[H]
-#define RSCAN0TMPTR8HL RSCAN0.TMPTR8.UINT8[HL]
-#define RSCAN0TMPTR8HH RSCAN0.TMPTR8.UINT8[HH]
-#define RSCAN0TMDF08 RSCAN0.TMDF08.UINT32
-#define RSCAN0TMDF08L RSCAN0.TMDF08.UINT16[L]
-#define RSCAN0TMDF08LL RSCAN0.TMDF08.UINT8[LL]
-#define RSCAN0TMDF08LH RSCAN0.TMDF08.UINT8[LH]
-#define RSCAN0TMDF08H RSCAN0.TMDF08.UINT16[H]
-#define RSCAN0TMDF08HL RSCAN0.TMDF08.UINT8[HL]
-#define RSCAN0TMDF08HH RSCAN0.TMDF08.UINT8[HH]
-#define RSCAN0TMDF18 RSCAN0.TMDF18.UINT32
-#define RSCAN0TMDF18L RSCAN0.TMDF18.UINT16[L]
-#define RSCAN0TMDF18LL RSCAN0.TMDF18.UINT8[LL]
-#define RSCAN0TMDF18LH RSCAN0.TMDF18.UINT8[LH]
-#define RSCAN0TMDF18H RSCAN0.TMDF18.UINT16[H]
-#define RSCAN0TMDF18HL RSCAN0.TMDF18.UINT8[HL]
-#define RSCAN0TMDF18HH RSCAN0.TMDF18.UINT8[HH]
-#define RSCAN0TMID9 RSCAN0.TMID9.UINT32
-#define RSCAN0TMID9L RSCAN0.TMID9.UINT16[L]
-#define RSCAN0TMID9LL RSCAN0.TMID9.UINT8[LL]
-#define RSCAN0TMID9LH RSCAN0.TMID9.UINT8[LH]
-#define RSCAN0TMID9H RSCAN0.TMID9.UINT16[H]
-#define RSCAN0TMID9HL RSCAN0.TMID9.UINT8[HL]
-#define RSCAN0TMID9HH RSCAN0.TMID9.UINT8[HH]
-#define RSCAN0TMPTR9 RSCAN0.TMPTR9.UINT32
-#define RSCAN0TMPTR9L RSCAN0.TMPTR9.UINT16[L]
-#define RSCAN0TMPTR9LL RSCAN0.TMPTR9.UINT8[LL]
-#define RSCAN0TMPTR9LH RSCAN0.TMPTR9.UINT8[LH]
-#define RSCAN0TMPTR9H RSCAN0.TMPTR9.UINT16[H]
-#define RSCAN0TMPTR9HL RSCAN0.TMPTR9.UINT8[HL]
-#define RSCAN0TMPTR9HH RSCAN0.TMPTR9.UINT8[HH]
-#define RSCAN0TMDF09 RSCAN0.TMDF09.UINT32
-#define RSCAN0TMDF09L RSCAN0.TMDF09.UINT16[L]
-#define RSCAN0TMDF09LL RSCAN0.TMDF09.UINT8[LL]
-#define RSCAN0TMDF09LH RSCAN0.TMDF09.UINT8[LH]
-#define RSCAN0TMDF09H RSCAN0.TMDF09.UINT16[H]
-#define RSCAN0TMDF09HL RSCAN0.TMDF09.UINT8[HL]
-#define RSCAN0TMDF09HH RSCAN0.TMDF09.UINT8[HH]
-#define RSCAN0TMDF19 RSCAN0.TMDF19.UINT32
-#define RSCAN0TMDF19L RSCAN0.TMDF19.UINT16[L]
-#define RSCAN0TMDF19LL RSCAN0.TMDF19.UINT8[LL]
-#define RSCAN0TMDF19LH RSCAN0.TMDF19.UINT8[LH]
-#define RSCAN0TMDF19H RSCAN0.TMDF19.UINT16[H]
-#define RSCAN0TMDF19HL RSCAN0.TMDF19.UINT8[HL]
-#define RSCAN0TMDF19HH RSCAN0.TMDF19.UINT8[HH]
-#define RSCAN0TMID10 RSCAN0.TMID10.UINT32
-#define RSCAN0TMID10L RSCAN0.TMID10.UINT16[L]
-#define RSCAN0TMID10LL RSCAN0.TMID10.UINT8[LL]
-#define RSCAN0TMID10LH RSCAN0.TMID10.UINT8[LH]
-#define RSCAN0TMID10H RSCAN0.TMID10.UINT16[H]
-#define RSCAN0TMID10HL RSCAN0.TMID10.UINT8[HL]
-#define RSCAN0TMID10HH RSCAN0.TMID10.UINT8[HH]
-#define RSCAN0TMPTR10 RSCAN0.TMPTR10.UINT32
-#define RSCAN0TMPTR10L RSCAN0.TMPTR10.UINT16[L]
-#define RSCAN0TMPTR10LL RSCAN0.TMPTR10.UINT8[LL]
-#define RSCAN0TMPTR10LH RSCAN0.TMPTR10.UINT8[LH]
-#define RSCAN0TMPTR10H RSCAN0.TMPTR10.UINT16[H]
-#define RSCAN0TMPTR10HL RSCAN0.TMPTR10.UINT8[HL]
-#define RSCAN0TMPTR10HH RSCAN0.TMPTR10.UINT8[HH]
-#define RSCAN0TMDF010 RSCAN0.TMDF010.UINT32
-#define RSCAN0TMDF010L RSCAN0.TMDF010.UINT16[L]
-#define RSCAN0TMDF010LL RSCAN0.TMDF010.UINT8[LL]
-#define RSCAN0TMDF010LH RSCAN0.TMDF010.UINT8[LH]
-#define RSCAN0TMDF010H RSCAN0.TMDF010.UINT16[H]
-#define RSCAN0TMDF010HL RSCAN0.TMDF010.UINT8[HL]
-#define RSCAN0TMDF010HH RSCAN0.TMDF010.UINT8[HH]
-#define RSCAN0TMDF110 RSCAN0.TMDF110.UINT32
-#define RSCAN0TMDF110L RSCAN0.TMDF110.UINT16[L]
-#define RSCAN0TMDF110LL RSCAN0.TMDF110.UINT8[LL]
-#define RSCAN0TMDF110LH RSCAN0.TMDF110.UINT8[LH]
-#define RSCAN0TMDF110H RSCAN0.TMDF110.UINT16[H]
-#define RSCAN0TMDF110HL RSCAN0.TMDF110.UINT8[HL]
-#define RSCAN0TMDF110HH RSCAN0.TMDF110.UINT8[HH]
-#define RSCAN0TMID11 RSCAN0.TMID11.UINT32
-#define RSCAN0TMID11L RSCAN0.TMID11.UINT16[L]
-#define RSCAN0TMID11LL RSCAN0.TMID11.UINT8[LL]
-#define RSCAN0TMID11LH RSCAN0.TMID11.UINT8[LH]
-#define RSCAN0TMID11H RSCAN0.TMID11.UINT16[H]
-#define RSCAN0TMID11HL RSCAN0.TMID11.UINT8[HL]
-#define RSCAN0TMID11HH RSCAN0.TMID11.UINT8[HH]
-#define RSCAN0TMPTR11 RSCAN0.TMPTR11.UINT32
-#define RSCAN0TMPTR11L RSCAN0.TMPTR11.UINT16[L]
-#define RSCAN0TMPTR11LL RSCAN0.TMPTR11.UINT8[LL]
-#define RSCAN0TMPTR11LH RSCAN0.TMPTR11.UINT8[LH]
-#define RSCAN0TMPTR11H RSCAN0.TMPTR11.UINT16[H]
-#define RSCAN0TMPTR11HL RSCAN0.TMPTR11.UINT8[HL]
-#define RSCAN0TMPTR11HH RSCAN0.TMPTR11.UINT8[HH]
-#define RSCAN0TMDF011 RSCAN0.TMDF011.UINT32
-#define RSCAN0TMDF011L RSCAN0.TMDF011.UINT16[L]
-#define RSCAN0TMDF011LL RSCAN0.TMDF011.UINT8[LL]
-#define RSCAN0TMDF011LH RSCAN0.TMDF011.UINT8[LH]
-#define RSCAN0TMDF011H RSCAN0.TMDF011.UINT16[H]
-#define RSCAN0TMDF011HL RSCAN0.TMDF011.UINT8[HL]
-#define RSCAN0TMDF011HH RSCAN0.TMDF011.UINT8[HH]
-#define RSCAN0TMDF111 RSCAN0.TMDF111.UINT32
-#define RSCAN0TMDF111L RSCAN0.TMDF111.UINT16[L]
-#define RSCAN0TMDF111LL RSCAN0.TMDF111.UINT8[LL]
-#define RSCAN0TMDF111LH RSCAN0.TMDF111.UINT8[LH]
-#define RSCAN0TMDF111H RSCAN0.TMDF111.UINT16[H]
-#define RSCAN0TMDF111HL RSCAN0.TMDF111.UINT8[HL]
-#define RSCAN0TMDF111HH RSCAN0.TMDF111.UINT8[HH]
-#define RSCAN0TMID12 RSCAN0.TMID12.UINT32
-#define RSCAN0TMID12L RSCAN0.TMID12.UINT16[L]
-#define RSCAN0TMID12LL RSCAN0.TMID12.UINT8[LL]
-#define RSCAN0TMID12LH RSCAN0.TMID12.UINT8[LH]
-#define RSCAN0TMID12H RSCAN0.TMID12.UINT16[H]
-#define RSCAN0TMID12HL RSCAN0.TMID12.UINT8[HL]
-#define RSCAN0TMID12HH RSCAN0.TMID12.UINT8[HH]
-#define RSCAN0TMPTR12 RSCAN0.TMPTR12.UINT32
-#define RSCAN0TMPTR12L RSCAN0.TMPTR12.UINT16[L]
-#define RSCAN0TMPTR12LL RSCAN0.TMPTR12.UINT8[LL]
-#define RSCAN0TMPTR12LH RSCAN0.TMPTR12.UINT8[LH]
-#define RSCAN0TMPTR12H RSCAN0.TMPTR12.UINT16[H]
-#define RSCAN0TMPTR12HL RSCAN0.TMPTR12.UINT8[HL]
-#define RSCAN0TMPTR12HH RSCAN0.TMPTR12.UINT8[HH]
-#define RSCAN0TMDF012 RSCAN0.TMDF012.UINT32
-#define RSCAN0TMDF012L RSCAN0.TMDF012.UINT16[L]
-#define RSCAN0TMDF012LL RSCAN0.TMDF012.UINT8[LL]
-#define RSCAN0TMDF012LH RSCAN0.TMDF012.UINT8[LH]
-#define RSCAN0TMDF012H RSCAN0.TMDF012.UINT16[H]
-#define RSCAN0TMDF012HL RSCAN0.TMDF012.UINT8[HL]
-#define RSCAN0TMDF012HH RSCAN0.TMDF012.UINT8[HH]
-#define RSCAN0TMDF112 RSCAN0.TMDF112.UINT32
-#define RSCAN0TMDF112L RSCAN0.TMDF112.UINT16[L]
-#define RSCAN0TMDF112LL RSCAN0.TMDF112.UINT8[LL]
-#define RSCAN0TMDF112LH RSCAN0.TMDF112.UINT8[LH]
-#define RSCAN0TMDF112H RSCAN0.TMDF112.UINT16[H]
-#define RSCAN0TMDF112HL RSCAN0.TMDF112.UINT8[HL]
-#define RSCAN0TMDF112HH RSCAN0.TMDF112.UINT8[HH]
-#define RSCAN0TMID13 RSCAN0.TMID13.UINT32
-#define RSCAN0TMID13L RSCAN0.TMID13.UINT16[L]
-#define RSCAN0TMID13LL RSCAN0.TMID13.UINT8[LL]
-#define RSCAN0TMID13LH RSCAN0.TMID13.UINT8[LH]
-#define RSCAN0TMID13H RSCAN0.TMID13.UINT16[H]
-#define RSCAN0TMID13HL RSCAN0.TMID13.UINT8[HL]
-#define RSCAN0TMID13HH RSCAN0.TMID13.UINT8[HH]
-#define RSCAN0TMPTR13 RSCAN0.TMPTR13.UINT32
-#define RSCAN0TMPTR13L RSCAN0.TMPTR13.UINT16[L]
-#define RSCAN0TMPTR13LL RSCAN0.TMPTR13.UINT8[LL]
-#define RSCAN0TMPTR13LH RSCAN0.TMPTR13.UINT8[LH]
-#define RSCAN0TMPTR13H RSCAN0.TMPTR13.UINT16[H]
-#define RSCAN0TMPTR13HL RSCAN0.TMPTR13.UINT8[HL]
-#define RSCAN0TMPTR13HH RSCAN0.TMPTR13.UINT8[HH]
-#define RSCAN0TMDF013 RSCAN0.TMDF013.UINT32
-#define RSCAN0TMDF013L RSCAN0.TMDF013.UINT16[L]
-#define RSCAN0TMDF013LL RSCAN0.TMDF013.UINT8[LL]
-#define RSCAN0TMDF013LH RSCAN0.TMDF013.UINT8[LH]
-#define RSCAN0TMDF013H RSCAN0.TMDF013.UINT16[H]
-#define RSCAN0TMDF013HL RSCAN0.TMDF013.UINT8[HL]
-#define RSCAN0TMDF013HH RSCAN0.TMDF013.UINT8[HH]
-#define RSCAN0TMDF113 RSCAN0.TMDF113.UINT32
-#define RSCAN0TMDF113L RSCAN0.TMDF113.UINT16[L]
-#define RSCAN0TMDF113LL RSCAN0.TMDF113.UINT8[LL]
-#define RSCAN0TMDF113LH RSCAN0.TMDF113.UINT8[LH]
-#define RSCAN0TMDF113H RSCAN0.TMDF113.UINT16[H]
-#define RSCAN0TMDF113HL RSCAN0.TMDF113.UINT8[HL]
-#define RSCAN0TMDF113HH RSCAN0.TMDF113.UINT8[HH]
-#define RSCAN0TMID14 RSCAN0.TMID14.UINT32
-#define RSCAN0TMID14L RSCAN0.TMID14.UINT16[L]
-#define RSCAN0TMID14LL RSCAN0.TMID14.UINT8[LL]
-#define RSCAN0TMID14LH RSCAN0.TMID14.UINT8[LH]
-#define RSCAN0TMID14H RSCAN0.TMID14.UINT16[H]
-#define RSCAN0TMID14HL RSCAN0.TMID14.UINT8[HL]
-#define RSCAN0TMID14HH RSCAN0.TMID14.UINT8[HH]
-#define RSCAN0TMPTR14 RSCAN0.TMPTR14.UINT32
-#define RSCAN0TMPTR14L RSCAN0.TMPTR14.UINT16[L]
-#define RSCAN0TMPTR14LL RSCAN0.TMPTR14.UINT8[LL]
-#define RSCAN0TMPTR14LH RSCAN0.TMPTR14.UINT8[LH]
-#define RSCAN0TMPTR14H RSCAN0.TMPTR14.UINT16[H]
-#define RSCAN0TMPTR14HL RSCAN0.TMPTR14.UINT8[HL]
-#define RSCAN0TMPTR14HH RSCAN0.TMPTR14.UINT8[HH]
-#define RSCAN0TMDF014 RSCAN0.TMDF014.UINT32
-#define RSCAN0TMDF014L RSCAN0.TMDF014.UINT16[L]
-#define RSCAN0TMDF014LL RSCAN0.TMDF014.UINT8[LL]
-#define RSCAN0TMDF014LH RSCAN0.TMDF014.UINT8[LH]
-#define RSCAN0TMDF014H RSCAN0.TMDF014.UINT16[H]
-#define RSCAN0TMDF014HL RSCAN0.TMDF014.UINT8[HL]
-#define RSCAN0TMDF014HH RSCAN0.TMDF014.UINT8[HH]
-#define RSCAN0TMDF114 RSCAN0.TMDF114.UINT32
-#define RSCAN0TMDF114L RSCAN0.TMDF114.UINT16[L]
-#define RSCAN0TMDF114LL RSCAN0.TMDF114.UINT8[LL]
-#define RSCAN0TMDF114LH RSCAN0.TMDF114.UINT8[LH]
-#define RSCAN0TMDF114H RSCAN0.TMDF114.UINT16[H]
-#define RSCAN0TMDF114HL RSCAN0.TMDF114.UINT8[HL]
-#define RSCAN0TMDF114HH RSCAN0.TMDF114.UINT8[HH]
-#define RSCAN0TMID15 RSCAN0.TMID15.UINT32
-#define RSCAN0TMID15L RSCAN0.TMID15.UINT16[L]
-#define RSCAN0TMID15LL RSCAN0.TMID15.UINT8[LL]
-#define RSCAN0TMID15LH RSCAN0.TMID15.UINT8[LH]
-#define RSCAN0TMID15H RSCAN0.TMID15.UINT16[H]
-#define RSCAN0TMID15HL RSCAN0.TMID15.UINT8[HL]
-#define RSCAN0TMID15HH RSCAN0.TMID15.UINT8[HH]
-#define RSCAN0TMPTR15 RSCAN0.TMPTR15.UINT32
-#define RSCAN0TMPTR15L RSCAN0.TMPTR15.UINT16[L]
-#define RSCAN0TMPTR15LL RSCAN0.TMPTR15.UINT8[LL]
-#define RSCAN0TMPTR15LH RSCAN0.TMPTR15.UINT8[LH]
-#define RSCAN0TMPTR15H RSCAN0.TMPTR15.UINT16[H]
-#define RSCAN0TMPTR15HL RSCAN0.TMPTR15.UINT8[HL]
-#define RSCAN0TMPTR15HH RSCAN0.TMPTR15.UINT8[HH]
-#define RSCAN0TMDF015 RSCAN0.TMDF015.UINT32
-#define RSCAN0TMDF015L RSCAN0.TMDF015.UINT16[L]
-#define RSCAN0TMDF015LL RSCAN0.TMDF015.UINT8[LL]
-#define RSCAN0TMDF015LH RSCAN0.TMDF015.UINT8[LH]
-#define RSCAN0TMDF015H RSCAN0.TMDF015.UINT16[H]
-#define RSCAN0TMDF015HL RSCAN0.TMDF015.UINT8[HL]
-#define RSCAN0TMDF015HH RSCAN0.TMDF015.UINT8[HH]
-#define RSCAN0TMDF115 RSCAN0.TMDF115.UINT32
-#define RSCAN0TMDF115L RSCAN0.TMDF115.UINT16[L]
-#define RSCAN0TMDF115LL RSCAN0.TMDF115.UINT8[LL]
-#define RSCAN0TMDF115LH RSCAN0.TMDF115.UINT8[LH]
-#define RSCAN0TMDF115H RSCAN0.TMDF115.UINT16[H]
-#define RSCAN0TMDF115HL RSCAN0.TMDF115.UINT8[HL]
-#define RSCAN0TMDF115HH RSCAN0.TMDF115.UINT8[HH]
-#define RSCAN0TMID16 RSCAN0.TMID16.UINT32
-#define RSCAN0TMID16L RSCAN0.TMID16.UINT16[L]
-#define RSCAN0TMID16LL RSCAN0.TMID16.UINT8[LL]
-#define RSCAN0TMID16LH RSCAN0.TMID16.UINT8[LH]
-#define RSCAN0TMID16H RSCAN0.TMID16.UINT16[H]
-#define RSCAN0TMID16HL RSCAN0.TMID16.UINT8[HL]
-#define RSCAN0TMID16HH RSCAN0.TMID16.UINT8[HH]
-#define RSCAN0TMPTR16 RSCAN0.TMPTR16.UINT32
-#define RSCAN0TMPTR16L RSCAN0.TMPTR16.UINT16[L]
-#define RSCAN0TMPTR16LL RSCAN0.TMPTR16.UINT8[LL]
-#define RSCAN0TMPTR16LH RSCAN0.TMPTR16.UINT8[LH]
-#define RSCAN0TMPTR16H RSCAN0.TMPTR16.UINT16[H]
-#define RSCAN0TMPTR16HL RSCAN0.TMPTR16.UINT8[HL]
-#define RSCAN0TMPTR16HH RSCAN0.TMPTR16.UINT8[HH]
-#define RSCAN0TMDF016 RSCAN0.TMDF016.UINT32
-#define RSCAN0TMDF016L RSCAN0.TMDF016.UINT16[L]
-#define RSCAN0TMDF016LL RSCAN0.TMDF016.UINT8[LL]
-#define RSCAN0TMDF016LH RSCAN0.TMDF016.UINT8[LH]
-#define RSCAN0TMDF016H RSCAN0.TMDF016.UINT16[H]
-#define RSCAN0TMDF016HL RSCAN0.TMDF016.UINT8[HL]
-#define RSCAN0TMDF016HH RSCAN0.TMDF016.UINT8[HH]
-#define RSCAN0TMDF116 RSCAN0.TMDF116.UINT32
-#define RSCAN0TMDF116L RSCAN0.TMDF116.UINT16[L]
-#define RSCAN0TMDF116LL RSCAN0.TMDF116.UINT8[LL]
-#define RSCAN0TMDF116LH RSCAN0.TMDF116.UINT8[LH]
-#define RSCAN0TMDF116H RSCAN0.TMDF116.UINT16[H]
-#define RSCAN0TMDF116HL RSCAN0.TMDF116.UINT8[HL]
-#define RSCAN0TMDF116HH RSCAN0.TMDF116.UINT8[HH]
-#define RSCAN0TMID17 RSCAN0.TMID17.UINT32
-#define RSCAN0TMID17L RSCAN0.TMID17.UINT16[L]
-#define RSCAN0TMID17LL RSCAN0.TMID17.UINT8[LL]
-#define RSCAN0TMID17LH RSCAN0.TMID17.UINT8[LH]
-#define RSCAN0TMID17H RSCAN0.TMID17.UINT16[H]
-#define RSCAN0TMID17HL RSCAN0.TMID17.UINT8[HL]
-#define RSCAN0TMID17HH RSCAN0.TMID17.UINT8[HH]
-#define RSCAN0TMPTR17 RSCAN0.TMPTR17.UINT32
-#define RSCAN0TMPTR17L RSCAN0.TMPTR17.UINT16[L]
-#define RSCAN0TMPTR17LL RSCAN0.TMPTR17.UINT8[LL]
-#define RSCAN0TMPTR17LH RSCAN0.TMPTR17.UINT8[LH]
-#define RSCAN0TMPTR17H RSCAN0.TMPTR17.UINT16[H]
-#define RSCAN0TMPTR17HL RSCAN0.TMPTR17.UINT8[HL]
-#define RSCAN0TMPTR17HH RSCAN0.TMPTR17.UINT8[HH]
-#define RSCAN0TMDF017 RSCAN0.TMDF017.UINT32
-#define RSCAN0TMDF017L RSCAN0.TMDF017.UINT16[L]
-#define RSCAN0TMDF017LL RSCAN0.TMDF017.UINT8[LL]
-#define RSCAN0TMDF017LH RSCAN0.TMDF017.UINT8[LH]
-#define RSCAN0TMDF017H RSCAN0.TMDF017.UINT16[H]
-#define RSCAN0TMDF017HL RSCAN0.TMDF017.UINT8[HL]
-#define RSCAN0TMDF017HH RSCAN0.TMDF017.UINT8[HH]
-#define RSCAN0TMDF117 RSCAN0.TMDF117.UINT32
-#define RSCAN0TMDF117L RSCAN0.TMDF117.UINT16[L]
-#define RSCAN0TMDF117LL RSCAN0.TMDF117.UINT8[LL]
-#define RSCAN0TMDF117LH RSCAN0.TMDF117.UINT8[LH]
-#define RSCAN0TMDF117H RSCAN0.TMDF117.UINT16[H]
-#define RSCAN0TMDF117HL RSCAN0.TMDF117.UINT8[HL]
-#define RSCAN0TMDF117HH RSCAN0.TMDF117.UINT8[HH]
-#define RSCAN0TMID18 RSCAN0.TMID18.UINT32
-#define RSCAN0TMID18L RSCAN0.TMID18.UINT16[L]
-#define RSCAN0TMID18LL RSCAN0.TMID18.UINT8[LL]
-#define RSCAN0TMID18LH RSCAN0.TMID18.UINT8[LH]
-#define RSCAN0TMID18H RSCAN0.TMID18.UINT16[H]
-#define RSCAN0TMID18HL RSCAN0.TMID18.UINT8[HL]
-#define RSCAN0TMID18HH RSCAN0.TMID18.UINT8[HH]
-#define RSCAN0TMPTR18 RSCAN0.TMPTR18.UINT32
-#define RSCAN0TMPTR18L RSCAN0.TMPTR18.UINT16[L]
-#define RSCAN0TMPTR18LL RSCAN0.TMPTR18.UINT8[LL]
-#define RSCAN0TMPTR18LH RSCAN0.TMPTR18.UINT8[LH]
-#define RSCAN0TMPTR18H RSCAN0.TMPTR18.UINT16[H]
-#define RSCAN0TMPTR18HL RSCAN0.TMPTR18.UINT8[HL]
-#define RSCAN0TMPTR18HH RSCAN0.TMPTR18.UINT8[HH]
-#define RSCAN0TMDF018 RSCAN0.TMDF018.UINT32
-#define RSCAN0TMDF018L RSCAN0.TMDF018.UINT16[L]
-#define RSCAN0TMDF018LL RSCAN0.TMDF018.UINT8[LL]
-#define RSCAN0TMDF018LH RSCAN0.TMDF018.UINT8[LH]
-#define RSCAN0TMDF018H RSCAN0.TMDF018.UINT16[H]
-#define RSCAN0TMDF018HL RSCAN0.TMDF018.UINT8[HL]
-#define RSCAN0TMDF018HH RSCAN0.TMDF018.UINT8[HH]
-#define RSCAN0TMDF118 RSCAN0.TMDF118.UINT32
-#define RSCAN0TMDF118L RSCAN0.TMDF118.UINT16[L]
-#define RSCAN0TMDF118LL RSCAN0.TMDF118.UINT8[LL]
-#define RSCAN0TMDF118LH RSCAN0.TMDF118.UINT8[LH]
-#define RSCAN0TMDF118H RSCAN0.TMDF118.UINT16[H]
-#define RSCAN0TMDF118HL RSCAN0.TMDF118.UINT8[HL]
-#define RSCAN0TMDF118HH RSCAN0.TMDF118.UINT8[HH]
-#define RSCAN0TMID19 RSCAN0.TMID19.UINT32
-#define RSCAN0TMID19L RSCAN0.TMID19.UINT16[L]
-#define RSCAN0TMID19LL RSCAN0.TMID19.UINT8[LL]
-#define RSCAN0TMID19LH RSCAN0.TMID19.UINT8[LH]
-#define RSCAN0TMID19H RSCAN0.TMID19.UINT16[H]
-#define RSCAN0TMID19HL RSCAN0.TMID19.UINT8[HL]
-#define RSCAN0TMID19HH RSCAN0.TMID19.UINT8[HH]
-#define RSCAN0TMPTR19 RSCAN0.TMPTR19.UINT32
-#define RSCAN0TMPTR19L RSCAN0.TMPTR19.UINT16[L]
-#define RSCAN0TMPTR19LL RSCAN0.TMPTR19.UINT8[LL]
-#define RSCAN0TMPTR19LH RSCAN0.TMPTR19.UINT8[LH]
-#define RSCAN0TMPTR19H RSCAN0.TMPTR19.UINT16[H]
-#define RSCAN0TMPTR19HL RSCAN0.TMPTR19.UINT8[HL]
-#define RSCAN0TMPTR19HH RSCAN0.TMPTR19.UINT8[HH]
-#define RSCAN0TMDF019 RSCAN0.TMDF019.UINT32
-#define RSCAN0TMDF019L RSCAN0.TMDF019.UINT16[L]
-#define RSCAN0TMDF019LL RSCAN0.TMDF019.UINT8[LL]
-#define RSCAN0TMDF019LH RSCAN0.TMDF019.UINT8[LH]
-#define RSCAN0TMDF019H RSCAN0.TMDF019.UINT16[H]
-#define RSCAN0TMDF019HL RSCAN0.TMDF019.UINT8[HL]
-#define RSCAN0TMDF019HH RSCAN0.TMDF019.UINT8[HH]
-#define RSCAN0TMDF119 RSCAN0.TMDF119.UINT32
-#define RSCAN0TMDF119L RSCAN0.TMDF119.UINT16[L]
-#define RSCAN0TMDF119LL RSCAN0.TMDF119.UINT8[LL]
-#define RSCAN0TMDF119LH RSCAN0.TMDF119.UINT8[LH]
-#define RSCAN0TMDF119H RSCAN0.TMDF119.UINT16[H]
-#define RSCAN0TMDF119HL RSCAN0.TMDF119.UINT8[HL]
-#define RSCAN0TMDF119HH RSCAN0.TMDF119.UINT8[HH]
-#define RSCAN0TMID20 RSCAN0.TMID20.UINT32
-#define RSCAN0TMID20L RSCAN0.TMID20.UINT16[L]
-#define RSCAN0TMID20LL RSCAN0.TMID20.UINT8[LL]
-#define RSCAN0TMID20LH RSCAN0.TMID20.UINT8[LH]
-#define RSCAN0TMID20H RSCAN0.TMID20.UINT16[H]
-#define RSCAN0TMID20HL RSCAN0.TMID20.UINT8[HL]
-#define RSCAN0TMID20HH RSCAN0.TMID20.UINT8[HH]
-#define RSCAN0TMPTR20 RSCAN0.TMPTR20.UINT32
-#define RSCAN0TMPTR20L RSCAN0.TMPTR20.UINT16[L]
-#define RSCAN0TMPTR20LL RSCAN0.TMPTR20.UINT8[LL]
-#define RSCAN0TMPTR20LH RSCAN0.TMPTR20.UINT8[LH]
-#define RSCAN0TMPTR20H RSCAN0.TMPTR20.UINT16[H]
-#define RSCAN0TMPTR20HL RSCAN0.TMPTR20.UINT8[HL]
-#define RSCAN0TMPTR20HH RSCAN0.TMPTR20.UINT8[HH]
-#define RSCAN0TMDF020 RSCAN0.TMDF020.UINT32
-#define RSCAN0TMDF020L RSCAN0.TMDF020.UINT16[L]
-#define RSCAN0TMDF020LL RSCAN0.TMDF020.UINT8[LL]
-#define RSCAN0TMDF020LH RSCAN0.TMDF020.UINT8[LH]
-#define RSCAN0TMDF020H RSCAN0.TMDF020.UINT16[H]
-#define RSCAN0TMDF020HL RSCAN0.TMDF020.UINT8[HL]
-#define RSCAN0TMDF020HH RSCAN0.TMDF020.UINT8[HH]
-#define RSCAN0TMDF120 RSCAN0.TMDF120.UINT32
-#define RSCAN0TMDF120L RSCAN0.TMDF120.UINT16[L]
-#define RSCAN0TMDF120LL RSCAN0.TMDF120.UINT8[LL]
-#define RSCAN0TMDF120LH RSCAN0.TMDF120.UINT8[LH]
-#define RSCAN0TMDF120H RSCAN0.TMDF120.UINT16[H]
-#define RSCAN0TMDF120HL RSCAN0.TMDF120.UINT8[HL]
-#define RSCAN0TMDF120HH RSCAN0.TMDF120.UINT8[HH]
-#define RSCAN0TMID21 RSCAN0.TMID21.UINT32
-#define RSCAN0TMID21L RSCAN0.TMID21.UINT16[L]
-#define RSCAN0TMID21LL RSCAN0.TMID21.UINT8[LL]
-#define RSCAN0TMID21LH RSCAN0.TMID21.UINT8[LH]
-#define RSCAN0TMID21H RSCAN0.TMID21.UINT16[H]
-#define RSCAN0TMID21HL RSCAN0.TMID21.UINT8[HL]
-#define RSCAN0TMID21HH RSCAN0.TMID21.UINT8[HH]
-#define RSCAN0TMPTR21 RSCAN0.TMPTR21.UINT32
-#define RSCAN0TMPTR21L RSCAN0.TMPTR21.UINT16[L]
-#define RSCAN0TMPTR21LL RSCAN0.TMPTR21.UINT8[LL]
-#define RSCAN0TMPTR21LH RSCAN0.TMPTR21.UINT8[LH]
-#define RSCAN0TMPTR21H RSCAN0.TMPTR21.UINT16[H]
-#define RSCAN0TMPTR21HL RSCAN0.TMPTR21.UINT8[HL]
-#define RSCAN0TMPTR21HH RSCAN0.TMPTR21.UINT8[HH]
-#define RSCAN0TMDF021 RSCAN0.TMDF021.UINT32
-#define RSCAN0TMDF021L RSCAN0.TMDF021.UINT16[L]
-#define RSCAN0TMDF021LL RSCAN0.TMDF021.UINT8[LL]
-#define RSCAN0TMDF021LH RSCAN0.TMDF021.UINT8[LH]
-#define RSCAN0TMDF021H RSCAN0.TMDF021.UINT16[H]
-#define RSCAN0TMDF021HL RSCAN0.TMDF021.UINT8[HL]
-#define RSCAN0TMDF021HH RSCAN0.TMDF021.UINT8[HH]
-#define RSCAN0TMDF121 RSCAN0.TMDF121.UINT32
-#define RSCAN0TMDF121L RSCAN0.TMDF121.UINT16[L]
-#define RSCAN0TMDF121LL RSCAN0.TMDF121.UINT8[LL]
-#define RSCAN0TMDF121LH RSCAN0.TMDF121.UINT8[LH]
-#define RSCAN0TMDF121H RSCAN0.TMDF121.UINT16[H]
-#define RSCAN0TMDF121HL RSCAN0.TMDF121.UINT8[HL]
-#define RSCAN0TMDF121HH RSCAN0.TMDF121.UINT8[HH]
-#define RSCAN0TMID22 RSCAN0.TMID22.UINT32
-#define RSCAN0TMID22L RSCAN0.TMID22.UINT16[L]
-#define RSCAN0TMID22LL RSCAN0.TMID22.UINT8[LL]
-#define RSCAN0TMID22LH RSCAN0.TMID22.UINT8[LH]
-#define RSCAN0TMID22H RSCAN0.TMID22.UINT16[H]
-#define RSCAN0TMID22HL RSCAN0.TMID22.UINT8[HL]
-#define RSCAN0TMID22HH RSCAN0.TMID22.UINT8[HH]
-#define RSCAN0TMPTR22 RSCAN0.TMPTR22.UINT32
-#define RSCAN0TMPTR22L RSCAN0.TMPTR22.UINT16[L]
-#define RSCAN0TMPTR22LL RSCAN0.TMPTR22.UINT8[LL]
-#define RSCAN0TMPTR22LH RSCAN0.TMPTR22.UINT8[LH]
-#define RSCAN0TMPTR22H RSCAN0.TMPTR22.UINT16[H]
-#define RSCAN0TMPTR22HL RSCAN0.TMPTR22.UINT8[HL]
-#define RSCAN0TMPTR22HH RSCAN0.TMPTR22.UINT8[HH]
-#define RSCAN0TMDF022 RSCAN0.TMDF022.UINT32
-#define RSCAN0TMDF022L RSCAN0.TMDF022.UINT16[L]
-#define RSCAN0TMDF022LL RSCAN0.TMDF022.UINT8[LL]
-#define RSCAN0TMDF022LH RSCAN0.TMDF022.UINT8[LH]
-#define RSCAN0TMDF022H RSCAN0.TMDF022.UINT16[H]
-#define RSCAN0TMDF022HL RSCAN0.TMDF022.UINT8[HL]
-#define RSCAN0TMDF022HH RSCAN0.TMDF022.UINT8[HH]
-#define RSCAN0TMDF122 RSCAN0.TMDF122.UINT32
-#define RSCAN0TMDF122L RSCAN0.TMDF122.UINT16[L]
-#define RSCAN0TMDF122LL RSCAN0.TMDF122.UINT8[LL]
-#define RSCAN0TMDF122LH RSCAN0.TMDF122.UINT8[LH]
-#define RSCAN0TMDF122H RSCAN0.TMDF122.UINT16[H]
-#define RSCAN0TMDF122HL RSCAN0.TMDF122.UINT8[HL]
-#define RSCAN0TMDF122HH RSCAN0.TMDF122.UINT8[HH]
-#define RSCAN0TMID23 RSCAN0.TMID23.UINT32
-#define RSCAN0TMID23L RSCAN0.TMID23.UINT16[L]
-#define RSCAN0TMID23LL RSCAN0.TMID23.UINT8[LL]
-#define RSCAN0TMID23LH RSCAN0.TMID23.UINT8[LH]
-#define RSCAN0TMID23H RSCAN0.TMID23.UINT16[H]
-#define RSCAN0TMID23HL RSCAN0.TMID23.UINT8[HL]
-#define RSCAN0TMID23HH RSCAN0.TMID23.UINT8[HH]
-#define RSCAN0TMPTR23 RSCAN0.TMPTR23.UINT32
-#define RSCAN0TMPTR23L RSCAN0.TMPTR23.UINT16[L]
-#define RSCAN0TMPTR23LL RSCAN0.TMPTR23.UINT8[LL]
-#define RSCAN0TMPTR23LH RSCAN0.TMPTR23.UINT8[LH]
-#define RSCAN0TMPTR23H RSCAN0.TMPTR23.UINT16[H]
-#define RSCAN0TMPTR23HL RSCAN0.TMPTR23.UINT8[HL]
-#define RSCAN0TMPTR23HH RSCAN0.TMPTR23.UINT8[HH]
-#define RSCAN0TMDF023 RSCAN0.TMDF023.UINT32
-#define RSCAN0TMDF023L RSCAN0.TMDF023.UINT16[L]
-#define RSCAN0TMDF023LL RSCAN0.TMDF023.UINT8[LL]
-#define RSCAN0TMDF023LH RSCAN0.TMDF023.UINT8[LH]
-#define RSCAN0TMDF023H RSCAN0.TMDF023.UINT16[H]
-#define RSCAN0TMDF023HL RSCAN0.TMDF023.UINT8[HL]
-#define RSCAN0TMDF023HH RSCAN0.TMDF023.UINT8[HH]
-#define RSCAN0TMDF123 RSCAN0.TMDF123.UINT32
-#define RSCAN0TMDF123L RSCAN0.TMDF123.UINT16[L]
-#define RSCAN0TMDF123LL RSCAN0.TMDF123.UINT8[LL]
-#define RSCAN0TMDF123LH RSCAN0.TMDF123.UINT8[LH]
-#define RSCAN0TMDF123H RSCAN0.TMDF123.UINT16[H]
-#define RSCAN0TMDF123HL RSCAN0.TMDF123.UINT8[HL]
-#define RSCAN0TMDF123HH RSCAN0.TMDF123.UINT8[HH]
-#define RSCAN0TMID24 RSCAN0.TMID24.UINT32
-#define RSCAN0TMID24L RSCAN0.TMID24.UINT16[L]
-#define RSCAN0TMID24LL RSCAN0.TMID24.UINT8[LL]
-#define RSCAN0TMID24LH RSCAN0.TMID24.UINT8[LH]
-#define RSCAN0TMID24H RSCAN0.TMID24.UINT16[H]
-#define RSCAN0TMID24HL RSCAN0.TMID24.UINT8[HL]
-#define RSCAN0TMID24HH RSCAN0.TMID24.UINT8[HH]
-#define RSCAN0TMPTR24 RSCAN0.TMPTR24.UINT32
-#define RSCAN0TMPTR24L RSCAN0.TMPTR24.UINT16[L]
-#define RSCAN0TMPTR24LL RSCAN0.TMPTR24.UINT8[LL]
-#define RSCAN0TMPTR24LH RSCAN0.TMPTR24.UINT8[LH]
-#define RSCAN0TMPTR24H RSCAN0.TMPTR24.UINT16[H]
-#define RSCAN0TMPTR24HL RSCAN0.TMPTR24.UINT8[HL]
-#define RSCAN0TMPTR24HH RSCAN0.TMPTR24.UINT8[HH]
-#define RSCAN0TMDF024 RSCAN0.TMDF024.UINT32
-#define RSCAN0TMDF024L RSCAN0.TMDF024.UINT16[L]
-#define RSCAN0TMDF024LL RSCAN0.TMDF024.UINT8[LL]
-#define RSCAN0TMDF024LH RSCAN0.TMDF024.UINT8[LH]
-#define RSCAN0TMDF024H RSCAN0.TMDF024.UINT16[H]
-#define RSCAN0TMDF024HL RSCAN0.TMDF024.UINT8[HL]
-#define RSCAN0TMDF024HH RSCAN0.TMDF024.UINT8[HH]
-#define RSCAN0TMDF124 RSCAN0.TMDF124.UINT32
-#define RSCAN0TMDF124L RSCAN0.TMDF124.UINT16[L]
-#define RSCAN0TMDF124LL RSCAN0.TMDF124.UINT8[LL]
-#define RSCAN0TMDF124LH RSCAN0.TMDF124.UINT8[LH]
-#define RSCAN0TMDF124H RSCAN0.TMDF124.UINT16[H]
-#define RSCAN0TMDF124HL RSCAN0.TMDF124.UINT8[HL]
-#define RSCAN0TMDF124HH RSCAN0.TMDF124.UINT8[HH]
-#define RSCAN0TMID25 RSCAN0.TMID25.UINT32
-#define RSCAN0TMID25L RSCAN0.TMID25.UINT16[L]
-#define RSCAN0TMID25LL RSCAN0.TMID25.UINT8[LL]
-#define RSCAN0TMID25LH RSCAN0.TMID25.UINT8[LH]
-#define RSCAN0TMID25H RSCAN0.TMID25.UINT16[H]
-#define RSCAN0TMID25HL RSCAN0.TMID25.UINT8[HL]
-#define RSCAN0TMID25HH RSCAN0.TMID25.UINT8[HH]
-#define RSCAN0TMPTR25 RSCAN0.TMPTR25.UINT32
-#define RSCAN0TMPTR25L RSCAN0.TMPTR25.UINT16[L]
-#define RSCAN0TMPTR25LL RSCAN0.TMPTR25.UINT8[LL]
-#define RSCAN0TMPTR25LH RSCAN0.TMPTR25.UINT8[LH]
-#define RSCAN0TMPTR25H RSCAN0.TMPTR25.UINT16[H]
-#define RSCAN0TMPTR25HL RSCAN0.TMPTR25.UINT8[HL]
-#define RSCAN0TMPTR25HH RSCAN0.TMPTR25.UINT8[HH]
-#define RSCAN0TMDF025 RSCAN0.TMDF025.UINT32
-#define RSCAN0TMDF025L RSCAN0.TMDF025.UINT16[L]
-#define RSCAN0TMDF025LL RSCAN0.TMDF025.UINT8[LL]
-#define RSCAN0TMDF025LH RSCAN0.TMDF025.UINT8[LH]
-#define RSCAN0TMDF025H RSCAN0.TMDF025.UINT16[H]
-#define RSCAN0TMDF025HL RSCAN0.TMDF025.UINT8[HL]
-#define RSCAN0TMDF025HH RSCAN0.TMDF025.UINT8[HH]
-#define RSCAN0TMDF125 RSCAN0.TMDF125.UINT32
-#define RSCAN0TMDF125L RSCAN0.TMDF125.UINT16[L]
-#define RSCAN0TMDF125LL RSCAN0.TMDF125.UINT8[LL]
-#define RSCAN0TMDF125LH RSCAN0.TMDF125.UINT8[LH]
-#define RSCAN0TMDF125H RSCAN0.TMDF125.UINT16[H]
-#define RSCAN0TMDF125HL RSCAN0.TMDF125.UINT8[HL]
-#define RSCAN0TMDF125HH RSCAN0.TMDF125.UINT8[HH]
-#define RSCAN0TMID26 RSCAN0.TMID26.UINT32
-#define RSCAN0TMID26L RSCAN0.TMID26.UINT16[L]
-#define RSCAN0TMID26LL RSCAN0.TMID26.UINT8[LL]
-#define RSCAN0TMID26LH RSCAN0.TMID26.UINT8[LH]
-#define RSCAN0TMID26H RSCAN0.TMID26.UINT16[H]
-#define RSCAN0TMID26HL RSCAN0.TMID26.UINT8[HL]
-#define RSCAN0TMID26HH RSCAN0.TMID26.UINT8[HH]
-#define RSCAN0TMPTR26 RSCAN0.TMPTR26.UINT32
-#define RSCAN0TMPTR26L RSCAN0.TMPTR26.UINT16[L]
-#define RSCAN0TMPTR26LL RSCAN0.TMPTR26.UINT8[LL]
-#define RSCAN0TMPTR26LH RSCAN0.TMPTR26.UINT8[LH]
-#define RSCAN0TMPTR26H RSCAN0.TMPTR26.UINT16[H]
-#define RSCAN0TMPTR26HL RSCAN0.TMPTR26.UINT8[HL]
-#define RSCAN0TMPTR26HH RSCAN0.TMPTR26.UINT8[HH]
-#define RSCAN0TMDF026 RSCAN0.TMDF026.UINT32
-#define RSCAN0TMDF026L RSCAN0.TMDF026.UINT16[L]
-#define RSCAN0TMDF026LL RSCAN0.TMDF026.UINT8[LL]
-#define RSCAN0TMDF026LH RSCAN0.TMDF026.UINT8[LH]
-#define RSCAN0TMDF026H RSCAN0.TMDF026.UINT16[H]
-#define RSCAN0TMDF026HL RSCAN0.TMDF026.UINT8[HL]
-#define RSCAN0TMDF026HH RSCAN0.TMDF026.UINT8[HH]
-#define RSCAN0TMDF126 RSCAN0.TMDF126.UINT32
-#define RSCAN0TMDF126L RSCAN0.TMDF126.UINT16[L]
-#define RSCAN0TMDF126LL RSCAN0.TMDF126.UINT8[LL]
-#define RSCAN0TMDF126LH RSCAN0.TMDF126.UINT8[LH]
-#define RSCAN0TMDF126H RSCAN0.TMDF126.UINT16[H]
-#define RSCAN0TMDF126HL RSCAN0.TMDF126.UINT8[HL]
-#define RSCAN0TMDF126HH RSCAN0.TMDF126.UINT8[HH]
-#define RSCAN0TMID27 RSCAN0.TMID27.UINT32
-#define RSCAN0TMID27L RSCAN0.TMID27.UINT16[L]
-#define RSCAN0TMID27LL RSCAN0.TMID27.UINT8[LL]
-#define RSCAN0TMID27LH RSCAN0.TMID27.UINT8[LH]
-#define RSCAN0TMID27H RSCAN0.TMID27.UINT16[H]
-#define RSCAN0TMID27HL RSCAN0.TMID27.UINT8[HL]
-#define RSCAN0TMID27HH RSCAN0.TMID27.UINT8[HH]
-#define RSCAN0TMPTR27 RSCAN0.TMPTR27.UINT32
-#define RSCAN0TMPTR27L RSCAN0.TMPTR27.UINT16[L]
-#define RSCAN0TMPTR27LL RSCAN0.TMPTR27.UINT8[LL]
-#define RSCAN0TMPTR27LH RSCAN0.TMPTR27.UINT8[LH]
-#define RSCAN0TMPTR27H RSCAN0.TMPTR27.UINT16[H]
-#define RSCAN0TMPTR27HL RSCAN0.TMPTR27.UINT8[HL]
-#define RSCAN0TMPTR27HH RSCAN0.TMPTR27.UINT8[HH]
-#define RSCAN0TMDF027 RSCAN0.TMDF027.UINT32
-#define RSCAN0TMDF027L RSCAN0.TMDF027.UINT16[L]
-#define RSCAN0TMDF027LL RSCAN0.TMDF027.UINT8[LL]
-#define RSCAN0TMDF027LH RSCAN0.TMDF027.UINT8[LH]
-#define RSCAN0TMDF027H RSCAN0.TMDF027.UINT16[H]
-#define RSCAN0TMDF027HL RSCAN0.TMDF027.UINT8[HL]
-#define RSCAN0TMDF027HH RSCAN0.TMDF027.UINT8[HH]
-#define RSCAN0TMDF127 RSCAN0.TMDF127.UINT32
-#define RSCAN0TMDF127L RSCAN0.TMDF127.UINT16[L]
-#define RSCAN0TMDF127LL RSCAN0.TMDF127.UINT8[LL]
-#define RSCAN0TMDF127LH RSCAN0.TMDF127.UINT8[LH]
-#define RSCAN0TMDF127H RSCAN0.TMDF127.UINT16[H]
-#define RSCAN0TMDF127HL RSCAN0.TMDF127.UINT8[HL]
-#define RSCAN0TMDF127HH RSCAN0.TMDF127.UINT8[HH]
-#define RSCAN0TMID28 RSCAN0.TMID28.UINT32
-#define RSCAN0TMID28L RSCAN0.TMID28.UINT16[L]
-#define RSCAN0TMID28LL RSCAN0.TMID28.UINT8[LL]
-#define RSCAN0TMID28LH RSCAN0.TMID28.UINT8[LH]
-#define RSCAN0TMID28H RSCAN0.TMID28.UINT16[H]
-#define RSCAN0TMID28HL RSCAN0.TMID28.UINT8[HL]
-#define RSCAN0TMID28HH RSCAN0.TMID28.UINT8[HH]
-#define RSCAN0TMPTR28 RSCAN0.TMPTR28.UINT32
-#define RSCAN0TMPTR28L RSCAN0.TMPTR28.UINT16[L]
-#define RSCAN0TMPTR28LL RSCAN0.TMPTR28.UINT8[LL]
-#define RSCAN0TMPTR28LH RSCAN0.TMPTR28.UINT8[LH]
-#define RSCAN0TMPTR28H RSCAN0.TMPTR28.UINT16[H]
-#define RSCAN0TMPTR28HL RSCAN0.TMPTR28.UINT8[HL]
-#define RSCAN0TMPTR28HH RSCAN0.TMPTR28.UINT8[HH]
-#define RSCAN0TMDF028 RSCAN0.TMDF028.UINT32
-#define RSCAN0TMDF028L RSCAN0.TMDF028.UINT16[L]
-#define RSCAN0TMDF028LL RSCAN0.TMDF028.UINT8[LL]
-#define RSCAN0TMDF028LH RSCAN0.TMDF028.UINT8[LH]
-#define RSCAN0TMDF028H RSCAN0.TMDF028.UINT16[H]
-#define RSCAN0TMDF028HL RSCAN0.TMDF028.UINT8[HL]
-#define RSCAN0TMDF028HH RSCAN0.TMDF028.UINT8[HH]
-#define RSCAN0TMDF128 RSCAN0.TMDF128.UINT32
-#define RSCAN0TMDF128L RSCAN0.TMDF128.UINT16[L]
-#define RSCAN0TMDF128LL RSCAN0.TMDF128.UINT8[LL]
-#define RSCAN0TMDF128LH RSCAN0.TMDF128.UINT8[LH]
-#define RSCAN0TMDF128H RSCAN0.TMDF128.UINT16[H]
-#define RSCAN0TMDF128HL RSCAN0.TMDF128.UINT8[HL]
-#define RSCAN0TMDF128HH RSCAN0.TMDF128.UINT8[HH]
-#define RSCAN0TMID29 RSCAN0.TMID29.UINT32
-#define RSCAN0TMID29L RSCAN0.TMID29.UINT16[L]
-#define RSCAN0TMID29LL RSCAN0.TMID29.UINT8[LL]
-#define RSCAN0TMID29LH RSCAN0.TMID29.UINT8[LH]
-#define RSCAN0TMID29H RSCAN0.TMID29.UINT16[H]
-#define RSCAN0TMID29HL RSCAN0.TMID29.UINT8[HL]
-#define RSCAN0TMID29HH RSCAN0.TMID29.UINT8[HH]
-#define RSCAN0TMPTR29 RSCAN0.TMPTR29.UINT32
-#define RSCAN0TMPTR29L RSCAN0.TMPTR29.UINT16[L]
-#define RSCAN0TMPTR29LL RSCAN0.TMPTR29.UINT8[LL]
-#define RSCAN0TMPTR29LH RSCAN0.TMPTR29.UINT8[LH]
-#define RSCAN0TMPTR29H RSCAN0.TMPTR29.UINT16[H]
-#define RSCAN0TMPTR29HL RSCAN0.TMPTR29.UINT8[HL]
-#define RSCAN0TMPTR29HH RSCAN0.TMPTR29.UINT8[HH]
-#define RSCAN0TMDF029 RSCAN0.TMDF029.UINT32
-#define RSCAN0TMDF029L RSCAN0.TMDF029.UINT16[L]
-#define RSCAN0TMDF029LL RSCAN0.TMDF029.UINT8[LL]
-#define RSCAN0TMDF029LH RSCAN0.TMDF029.UINT8[LH]
-#define RSCAN0TMDF029H RSCAN0.TMDF029.UINT16[H]
-#define RSCAN0TMDF029HL RSCAN0.TMDF029.UINT8[HL]
-#define RSCAN0TMDF029HH RSCAN0.TMDF029.UINT8[HH]
-#define RSCAN0TMDF129 RSCAN0.TMDF129.UINT32
-#define RSCAN0TMDF129L RSCAN0.TMDF129.UINT16[L]
-#define RSCAN0TMDF129LL RSCAN0.TMDF129.UINT8[LL]
-#define RSCAN0TMDF129LH RSCAN0.TMDF129.UINT8[LH]
-#define RSCAN0TMDF129H RSCAN0.TMDF129.UINT16[H]
-#define RSCAN0TMDF129HL RSCAN0.TMDF129.UINT8[HL]
-#define RSCAN0TMDF129HH RSCAN0.TMDF129.UINT8[HH]
-#define RSCAN0TMID30 RSCAN0.TMID30.UINT32
-#define RSCAN0TMID30L RSCAN0.TMID30.UINT16[L]
-#define RSCAN0TMID30LL RSCAN0.TMID30.UINT8[LL]
-#define RSCAN0TMID30LH RSCAN0.TMID30.UINT8[LH]
-#define RSCAN0TMID30H RSCAN0.TMID30.UINT16[H]
-#define RSCAN0TMID30HL RSCAN0.TMID30.UINT8[HL]
-#define RSCAN0TMID30HH RSCAN0.TMID30.UINT8[HH]
-#define RSCAN0TMPTR30 RSCAN0.TMPTR30.UINT32
-#define RSCAN0TMPTR30L RSCAN0.TMPTR30.UINT16[L]
-#define RSCAN0TMPTR30LL RSCAN0.TMPTR30.UINT8[LL]
-#define RSCAN0TMPTR30LH RSCAN0.TMPTR30.UINT8[LH]
-#define RSCAN0TMPTR30H RSCAN0.TMPTR30.UINT16[H]
-#define RSCAN0TMPTR30HL RSCAN0.TMPTR30.UINT8[HL]
-#define RSCAN0TMPTR30HH RSCAN0.TMPTR30.UINT8[HH]
-#define RSCAN0TMDF030 RSCAN0.TMDF030.UINT32
-#define RSCAN0TMDF030L RSCAN0.TMDF030.UINT16[L]
-#define RSCAN0TMDF030LL RSCAN0.TMDF030.UINT8[LL]
-#define RSCAN0TMDF030LH RSCAN0.TMDF030.UINT8[LH]
-#define RSCAN0TMDF030H RSCAN0.TMDF030.UINT16[H]
-#define RSCAN0TMDF030HL RSCAN0.TMDF030.UINT8[HL]
-#define RSCAN0TMDF030HH RSCAN0.TMDF030.UINT8[HH]
-#define RSCAN0TMDF130 RSCAN0.TMDF130.UINT32
-#define RSCAN0TMDF130L RSCAN0.TMDF130.UINT16[L]
-#define RSCAN0TMDF130LL RSCAN0.TMDF130.UINT8[LL]
-#define RSCAN0TMDF130LH RSCAN0.TMDF130.UINT8[LH]
-#define RSCAN0TMDF130H RSCAN0.TMDF130.UINT16[H]
-#define RSCAN0TMDF130HL RSCAN0.TMDF130.UINT8[HL]
-#define RSCAN0TMDF130HH RSCAN0.TMDF130.UINT8[HH]
-#define RSCAN0TMID31 RSCAN0.TMID31.UINT32
-#define RSCAN0TMID31L RSCAN0.TMID31.UINT16[L]
-#define RSCAN0TMID31LL RSCAN0.TMID31.UINT8[LL]
-#define RSCAN0TMID31LH RSCAN0.TMID31.UINT8[LH]
-#define RSCAN0TMID31H RSCAN0.TMID31.UINT16[H]
-#define RSCAN0TMID31HL RSCAN0.TMID31.UINT8[HL]
-#define RSCAN0TMID31HH RSCAN0.TMID31.UINT8[HH]
-#define RSCAN0TMPTR31 RSCAN0.TMPTR31.UINT32
-#define RSCAN0TMPTR31L RSCAN0.TMPTR31.UINT16[L]
-#define RSCAN0TMPTR31LL RSCAN0.TMPTR31.UINT8[LL]
-#define RSCAN0TMPTR31LH RSCAN0.TMPTR31.UINT8[LH]
-#define RSCAN0TMPTR31H RSCAN0.TMPTR31.UINT16[H]
-#define RSCAN0TMPTR31HL RSCAN0.TMPTR31.UINT8[HL]
-#define RSCAN0TMPTR31HH RSCAN0.TMPTR31.UINT8[HH]
-#define RSCAN0TMDF031 RSCAN0.TMDF031.UINT32
-#define RSCAN0TMDF031L RSCAN0.TMDF031.UINT16[L]
-#define RSCAN0TMDF031LL RSCAN0.TMDF031.UINT8[LL]
-#define RSCAN0TMDF031LH RSCAN0.TMDF031.UINT8[LH]
-#define RSCAN0TMDF031H RSCAN0.TMDF031.UINT16[H]
-#define RSCAN0TMDF031HL RSCAN0.TMDF031.UINT8[HL]
-#define RSCAN0TMDF031HH RSCAN0.TMDF031.UINT8[HH]
-#define RSCAN0TMDF131 RSCAN0.TMDF131.UINT32
-#define RSCAN0TMDF131L RSCAN0.TMDF131.UINT16[L]
-#define RSCAN0TMDF131LL RSCAN0.TMDF131.UINT8[LL]
-#define RSCAN0TMDF131LH RSCAN0.TMDF131.UINT8[LH]
-#define RSCAN0TMDF131H RSCAN0.TMDF131.UINT16[H]
-#define RSCAN0TMDF131HL RSCAN0.TMDF131.UINT8[HL]
-#define RSCAN0TMDF131HH RSCAN0.TMDF131.UINT8[HH]
-#define RSCAN0TMID32 RSCAN0.TMID32.UINT32
-#define RSCAN0TMID32L RSCAN0.TMID32.UINT16[L]
-#define RSCAN0TMID32LL RSCAN0.TMID32.UINT8[LL]
-#define RSCAN0TMID32LH RSCAN0.TMID32.UINT8[LH]
-#define RSCAN0TMID32H RSCAN0.TMID32.UINT16[H]
-#define RSCAN0TMID32HL RSCAN0.TMID32.UINT8[HL]
-#define RSCAN0TMID32HH RSCAN0.TMID32.UINT8[HH]
-#define RSCAN0TMPTR32 RSCAN0.TMPTR32.UINT32
-#define RSCAN0TMPTR32L RSCAN0.TMPTR32.UINT16[L]
-#define RSCAN0TMPTR32LL RSCAN0.TMPTR32.UINT8[LL]
-#define RSCAN0TMPTR32LH RSCAN0.TMPTR32.UINT8[LH]
-#define RSCAN0TMPTR32H RSCAN0.TMPTR32.UINT16[H]
-#define RSCAN0TMPTR32HL RSCAN0.TMPTR32.UINT8[HL]
-#define RSCAN0TMPTR32HH RSCAN0.TMPTR32.UINT8[HH]
-#define RSCAN0TMDF032 RSCAN0.TMDF032.UINT32
-#define RSCAN0TMDF032L RSCAN0.TMDF032.UINT16[L]
-#define RSCAN0TMDF032LL RSCAN0.TMDF032.UINT8[LL]
-#define RSCAN0TMDF032LH RSCAN0.TMDF032.UINT8[LH]
-#define RSCAN0TMDF032H RSCAN0.TMDF032.UINT16[H]
-#define RSCAN0TMDF032HL RSCAN0.TMDF032.UINT8[HL]
-#define RSCAN0TMDF032HH RSCAN0.TMDF032.UINT8[HH]
-#define RSCAN0TMDF132 RSCAN0.TMDF132.UINT32
-#define RSCAN0TMDF132L RSCAN0.TMDF132.UINT16[L]
-#define RSCAN0TMDF132LL RSCAN0.TMDF132.UINT8[LL]
-#define RSCAN0TMDF132LH RSCAN0.TMDF132.UINT8[LH]
-#define RSCAN0TMDF132H RSCAN0.TMDF132.UINT16[H]
-#define RSCAN0TMDF132HL RSCAN0.TMDF132.UINT8[HL]
-#define RSCAN0TMDF132HH RSCAN0.TMDF132.UINT8[HH]
-#define RSCAN0TMID33 RSCAN0.TMID33.UINT32
-#define RSCAN0TMID33L RSCAN0.TMID33.UINT16[L]
-#define RSCAN0TMID33LL RSCAN0.TMID33.UINT8[LL]
-#define RSCAN0TMID33LH RSCAN0.TMID33.UINT8[LH]
-#define RSCAN0TMID33H RSCAN0.TMID33.UINT16[H]
-#define RSCAN0TMID33HL RSCAN0.TMID33.UINT8[HL]
-#define RSCAN0TMID33HH RSCAN0.TMID33.UINT8[HH]
-#define RSCAN0TMPTR33 RSCAN0.TMPTR33.UINT32
-#define RSCAN0TMPTR33L RSCAN0.TMPTR33.UINT16[L]
-#define RSCAN0TMPTR33LL RSCAN0.TMPTR33.UINT8[LL]
-#define RSCAN0TMPTR33LH RSCAN0.TMPTR33.UINT8[LH]
-#define RSCAN0TMPTR33H RSCAN0.TMPTR33.UINT16[H]
-#define RSCAN0TMPTR33HL RSCAN0.TMPTR33.UINT8[HL]
-#define RSCAN0TMPTR33HH RSCAN0.TMPTR33.UINT8[HH]
-#define RSCAN0TMDF033 RSCAN0.TMDF033.UINT32
-#define RSCAN0TMDF033L RSCAN0.TMDF033.UINT16[L]
-#define RSCAN0TMDF033LL RSCAN0.TMDF033.UINT8[LL]
-#define RSCAN0TMDF033LH RSCAN0.TMDF033.UINT8[LH]
-#define RSCAN0TMDF033H RSCAN0.TMDF033.UINT16[H]
-#define RSCAN0TMDF033HL RSCAN0.TMDF033.UINT8[HL]
-#define RSCAN0TMDF033HH RSCAN0.TMDF033.UINT8[HH]
-#define RSCAN0TMDF133 RSCAN0.TMDF133.UINT32
-#define RSCAN0TMDF133L RSCAN0.TMDF133.UINT16[L]
-#define RSCAN0TMDF133LL RSCAN0.TMDF133.UINT8[LL]
-#define RSCAN0TMDF133LH RSCAN0.TMDF133.UINT8[LH]
-#define RSCAN0TMDF133H RSCAN0.TMDF133.UINT16[H]
-#define RSCAN0TMDF133HL RSCAN0.TMDF133.UINT8[HL]
-#define RSCAN0TMDF133HH RSCAN0.TMDF133.UINT8[HH]
-#define RSCAN0TMID34 RSCAN0.TMID34.UINT32
-#define RSCAN0TMID34L RSCAN0.TMID34.UINT16[L]
-#define RSCAN0TMID34LL RSCAN0.TMID34.UINT8[LL]
-#define RSCAN0TMID34LH RSCAN0.TMID34.UINT8[LH]
-#define RSCAN0TMID34H RSCAN0.TMID34.UINT16[H]
-#define RSCAN0TMID34HL RSCAN0.TMID34.UINT8[HL]
-#define RSCAN0TMID34HH RSCAN0.TMID34.UINT8[HH]
-#define RSCAN0TMPTR34 RSCAN0.TMPTR34.UINT32
-#define RSCAN0TMPTR34L RSCAN0.TMPTR34.UINT16[L]
-#define RSCAN0TMPTR34LL RSCAN0.TMPTR34.UINT8[LL]
-#define RSCAN0TMPTR34LH RSCAN0.TMPTR34.UINT8[LH]
-#define RSCAN0TMPTR34H RSCAN0.TMPTR34.UINT16[H]
-#define RSCAN0TMPTR34HL RSCAN0.TMPTR34.UINT8[HL]
-#define RSCAN0TMPTR34HH RSCAN0.TMPTR34.UINT8[HH]
-#define RSCAN0TMDF034 RSCAN0.TMDF034.UINT32
-#define RSCAN0TMDF034L RSCAN0.TMDF034.UINT16[L]
-#define RSCAN0TMDF034LL RSCAN0.TMDF034.UINT8[LL]
-#define RSCAN0TMDF034LH RSCAN0.TMDF034.UINT8[LH]
-#define RSCAN0TMDF034H RSCAN0.TMDF034.UINT16[H]
-#define RSCAN0TMDF034HL RSCAN0.TMDF034.UINT8[HL]
-#define RSCAN0TMDF034HH RSCAN0.TMDF034.UINT8[HH]
-#define RSCAN0TMDF134 RSCAN0.TMDF134.UINT32
-#define RSCAN0TMDF134L RSCAN0.TMDF134.UINT16[L]
-#define RSCAN0TMDF134LL RSCAN0.TMDF134.UINT8[LL]
-#define RSCAN0TMDF134LH RSCAN0.TMDF134.UINT8[LH]
-#define RSCAN0TMDF134H RSCAN0.TMDF134.UINT16[H]
-#define RSCAN0TMDF134HL RSCAN0.TMDF134.UINT8[HL]
-#define RSCAN0TMDF134HH RSCAN0.TMDF134.UINT8[HH]
-#define RSCAN0TMID35 RSCAN0.TMID35.UINT32
-#define RSCAN0TMID35L RSCAN0.TMID35.UINT16[L]
-#define RSCAN0TMID35LL RSCAN0.TMID35.UINT8[LL]
-#define RSCAN0TMID35LH RSCAN0.TMID35.UINT8[LH]
-#define RSCAN0TMID35H RSCAN0.TMID35.UINT16[H]
-#define RSCAN0TMID35HL RSCAN0.TMID35.UINT8[HL]
-#define RSCAN0TMID35HH RSCAN0.TMID35.UINT8[HH]
-#define RSCAN0TMPTR35 RSCAN0.TMPTR35.UINT32
-#define RSCAN0TMPTR35L RSCAN0.TMPTR35.UINT16[L]
-#define RSCAN0TMPTR35LL RSCAN0.TMPTR35.UINT8[LL]
-#define RSCAN0TMPTR35LH RSCAN0.TMPTR35.UINT8[LH]
-#define RSCAN0TMPTR35H RSCAN0.TMPTR35.UINT16[H]
-#define RSCAN0TMPTR35HL RSCAN0.TMPTR35.UINT8[HL]
-#define RSCAN0TMPTR35HH RSCAN0.TMPTR35.UINT8[HH]
-#define RSCAN0TMDF035 RSCAN0.TMDF035.UINT32
-#define RSCAN0TMDF035L RSCAN0.TMDF035.UINT16[L]
-#define RSCAN0TMDF035LL RSCAN0.TMDF035.UINT8[LL]
-#define RSCAN0TMDF035LH RSCAN0.TMDF035.UINT8[LH]
-#define RSCAN0TMDF035H RSCAN0.TMDF035.UINT16[H]
-#define RSCAN0TMDF035HL RSCAN0.TMDF035.UINT8[HL]
-#define RSCAN0TMDF035HH RSCAN0.TMDF035.UINT8[HH]
-#define RSCAN0TMDF135 RSCAN0.TMDF135.UINT32
-#define RSCAN0TMDF135L RSCAN0.TMDF135.UINT16[L]
-#define RSCAN0TMDF135LL RSCAN0.TMDF135.UINT8[LL]
-#define RSCAN0TMDF135LH RSCAN0.TMDF135.UINT8[LH]
-#define RSCAN0TMDF135H RSCAN0.TMDF135.UINT16[H]
-#define RSCAN0TMDF135HL RSCAN0.TMDF135.UINT8[HL]
-#define RSCAN0TMDF135HH RSCAN0.TMDF135.UINT8[HH]
-#define RSCAN0TMID36 RSCAN0.TMID36.UINT32
-#define RSCAN0TMID36L RSCAN0.TMID36.UINT16[L]
-#define RSCAN0TMID36LL RSCAN0.TMID36.UINT8[LL]
-#define RSCAN0TMID36LH RSCAN0.TMID36.UINT8[LH]
-#define RSCAN0TMID36H RSCAN0.TMID36.UINT16[H]
-#define RSCAN0TMID36HL RSCAN0.TMID36.UINT8[HL]
-#define RSCAN0TMID36HH RSCAN0.TMID36.UINT8[HH]
-#define RSCAN0TMPTR36 RSCAN0.TMPTR36.UINT32
-#define RSCAN0TMPTR36L RSCAN0.TMPTR36.UINT16[L]
-#define RSCAN0TMPTR36LL RSCAN0.TMPTR36.UINT8[LL]
-#define RSCAN0TMPTR36LH RSCAN0.TMPTR36.UINT8[LH]
-#define RSCAN0TMPTR36H RSCAN0.TMPTR36.UINT16[H]
-#define RSCAN0TMPTR36HL RSCAN0.TMPTR36.UINT8[HL]
-#define RSCAN0TMPTR36HH RSCAN0.TMPTR36.UINT8[HH]
-#define RSCAN0TMDF036 RSCAN0.TMDF036.UINT32
-#define RSCAN0TMDF036L RSCAN0.TMDF036.UINT16[L]
-#define RSCAN0TMDF036LL RSCAN0.TMDF036.UINT8[LL]
-#define RSCAN0TMDF036LH RSCAN0.TMDF036.UINT8[LH]
-#define RSCAN0TMDF036H RSCAN0.TMDF036.UINT16[H]
-#define RSCAN0TMDF036HL RSCAN0.TMDF036.UINT8[HL]
-#define RSCAN0TMDF036HH RSCAN0.TMDF036.UINT8[HH]
-#define RSCAN0TMDF136 RSCAN0.TMDF136.UINT32
-#define RSCAN0TMDF136L RSCAN0.TMDF136.UINT16[L]
-#define RSCAN0TMDF136LL RSCAN0.TMDF136.UINT8[LL]
-#define RSCAN0TMDF136LH RSCAN0.TMDF136.UINT8[LH]
-#define RSCAN0TMDF136H RSCAN0.TMDF136.UINT16[H]
-#define RSCAN0TMDF136HL RSCAN0.TMDF136.UINT8[HL]
-#define RSCAN0TMDF136HH RSCAN0.TMDF136.UINT8[HH]
-#define RSCAN0TMID37 RSCAN0.TMID37.UINT32
-#define RSCAN0TMID37L RSCAN0.TMID37.UINT16[L]
-#define RSCAN0TMID37LL RSCAN0.TMID37.UINT8[LL]
-#define RSCAN0TMID37LH RSCAN0.TMID37.UINT8[LH]
-#define RSCAN0TMID37H RSCAN0.TMID37.UINT16[H]
-#define RSCAN0TMID37HL RSCAN0.TMID37.UINT8[HL]
-#define RSCAN0TMID37HH RSCAN0.TMID37.UINT8[HH]
-#define RSCAN0TMPTR37 RSCAN0.TMPTR37.UINT32
-#define RSCAN0TMPTR37L RSCAN0.TMPTR37.UINT16[L]
-#define RSCAN0TMPTR37LL RSCAN0.TMPTR37.UINT8[LL]
-#define RSCAN0TMPTR37LH RSCAN0.TMPTR37.UINT8[LH]
-#define RSCAN0TMPTR37H RSCAN0.TMPTR37.UINT16[H]
-#define RSCAN0TMPTR37HL RSCAN0.TMPTR37.UINT8[HL]
-#define RSCAN0TMPTR37HH RSCAN0.TMPTR37.UINT8[HH]
-#define RSCAN0TMDF037 RSCAN0.TMDF037.UINT32
-#define RSCAN0TMDF037L RSCAN0.TMDF037.UINT16[L]
-#define RSCAN0TMDF037LL RSCAN0.TMDF037.UINT8[LL]
-#define RSCAN0TMDF037LH RSCAN0.TMDF037.UINT8[LH]
-#define RSCAN0TMDF037H RSCAN0.TMDF037.UINT16[H]
-#define RSCAN0TMDF037HL RSCAN0.TMDF037.UINT8[HL]
-#define RSCAN0TMDF037HH RSCAN0.TMDF037.UINT8[HH]
-#define RSCAN0TMDF137 RSCAN0.TMDF137.UINT32
-#define RSCAN0TMDF137L RSCAN0.TMDF137.UINT16[L]
-#define RSCAN0TMDF137LL RSCAN0.TMDF137.UINT8[LL]
-#define RSCAN0TMDF137LH RSCAN0.TMDF137.UINT8[LH]
-#define RSCAN0TMDF137H RSCAN0.TMDF137.UINT16[H]
-#define RSCAN0TMDF137HL RSCAN0.TMDF137.UINT8[HL]
-#define RSCAN0TMDF137HH RSCAN0.TMDF137.UINT8[HH]
-#define RSCAN0TMID38 RSCAN0.TMID38.UINT32
-#define RSCAN0TMID38L RSCAN0.TMID38.UINT16[L]
-#define RSCAN0TMID38LL RSCAN0.TMID38.UINT8[LL]
-#define RSCAN0TMID38LH RSCAN0.TMID38.UINT8[LH]
-#define RSCAN0TMID38H RSCAN0.TMID38.UINT16[H]
-#define RSCAN0TMID38HL RSCAN0.TMID38.UINT8[HL]
-#define RSCAN0TMID38HH RSCAN0.TMID38.UINT8[HH]
-#define RSCAN0TMPTR38 RSCAN0.TMPTR38.UINT32
-#define RSCAN0TMPTR38L RSCAN0.TMPTR38.UINT16[L]
-#define RSCAN0TMPTR38LL RSCAN0.TMPTR38.UINT8[LL]
-#define RSCAN0TMPTR38LH RSCAN0.TMPTR38.UINT8[LH]
-#define RSCAN0TMPTR38H RSCAN0.TMPTR38.UINT16[H]
-#define RSCAN0TMPTR38HL RSCAN0.TMPTR38.UINT8[HL]
-#define RSCAN0TMPTR38HH RSCAN0.TMPTR38.UINT8[HH]
-#define RSCAN0TMDF038 RSCAN0.TMDF038.UINT32
-#define RSCAN0TMDF038L RSCAN0.TMDF038.UINT16[L]
-#define RSCAN0TMDF038LL RSCAN0.TMDF038.UINT8[LL]
-#define RSCAN0TMDF038LH RSCAN0.TMDF038.UINT8[LH]
-#define RSCAN0TMDF038H RSCAN0.TMDF038.UINT16[H]
-#define RSCAN0TMDF038HL RSCAN0.TMDF038.UINT8[HL]
-#define RSCAN0TMDF038HH RSCAN0.TMDF038.UINT8[HH]
-#define RSCAN0TMDF138 RSCAN0.TMDF138.UINT32
-#define RSCAN0TMDF138L RSCAN0.TMDF138.UINT16[L]
-#define RSCAN0TMDF138LL RSCAN0.TMDF138.UINT8[LL]
-#define RSCAN0TMDF138LH RSCAN0.TMDF138.UINT8[LH]
-#define RSCAN0TMDF138H RSCAN0.TMDF138.UINT16[H]
-#define RSCAN0TMDF138HL RSCAN0.TMDF138.UINT8[HL]
-#define RSCAN0TMDF138HH RSCAN0.TMDF138.UINT8[HH]
-#define RSCAN0TMID39 RSCAN0.TMID39.UINT32
-#define RSCAN0TMID39L RSCAN0.TMID39.UINT16[L]
-#define RSCAN0TMID39LL RSCAN0.TMID39.UINT8[LL]
-#define RSCAN0TMID39LH RSCAN0.TMID39.UINT8[LH]
-#define RSCAN0TMID39H RSCAN0.TMID39.UINT16[H]
-#define RSCAN0TMID39HL RSCAN0.TMID39.UINT8[HL]
-#define RSCAN0TMID39HH RSCAN0.TMID39.UINT8[HH]
-#define RSCAN0TMPTR39 RSCAN0.TMPTR39.UINT32
-#define RSCAN0TMPTR39L RSCAN0.TMPTR39.UINT16[L]
-#define RSCAN0TMPTR39LL RSCAN0.TMPTR39.UINT8[LL]
-#define RSCAN0TMPTR39LH RSCAN0.TMPTR39.UINT8[LH]
-#define RSCAN0TMPTR39H RSCAN0.TMPTR39.UINT16[H]
-#define RSCAN0TMPTR39HL RSCAN0.TMPTR39.UINT8[HL]
-#define RSCAN0TMPTR39HH RSCAN0.TMPTR39.UINT8[HH]
-#define RSCAN0TMDF039 RSCAN0.TMDF039.UINT32
-#define RSCAN0TMDF039L RSCAN0.TMDF039.UINT16[L]
-#define RSCAN0TMDF039LL RSCAN0.TMDF039.UINT8[LL]
-#define RSCAN0TMDF039LH RSCAN0.TMDF039.UINT8[LH]
-#define RSCAN0TMDF039H RSCAN0.TMDF039.UINT16[H]
-#define RSCAN0TMDF039HL RSCAN0.TMDF039.UINT8[HL]
-#define RSCAN0TMDF039HH RSCAN0.TMDF039.UINT8[HH]
-#define RSCAN0TMDF139 RSCAN0.TMDF139.UINT32
-#define RSCAN0TMDF139L RSCAN0.TMDF139.UINT16[L]
-#define RSCAN0TMDF139LL RSCAN0.TMDF139.UINT8[LL]
-#define RSCAN0TMDF139LH RSCAN0.TMDF139.UINT8[LH]
-#define RSCAN0TMDF139H RSCAN0.TMDF139.UINT16[H]
-#define RSCAN0TMDF139HL RSCAN0.TMDF139.UINT8[HL]
-#define RSCAN0TMDF139HH RSCAN0.TMDF139.UINT8[HH]
-#define RSCAN0TMID40 RSCAN0.TMID40.UINT32
-#define RSCAN0TMID40L RSCAN0.TMID40.UINT16[L]
-#define RSCAN0TMID40LL RSCAN0.TMID40.UINT8[LL]
-#define RSCAN0TMID40LH RSCAN0.TMID40.UINT8[LH]
-#define RSCAN0TMID40H RSCAN0.TMID40.UINT16[H]
-#define RSCAN0TMID40HL RSCAN0.TMID40.UINT8[HL]
-#define RSCAN0TMID40HH RSCAN0.TMID40.UINT8[HH]
-#define RSCAN0TMPTR40 RSCAN0.TMPTR40.UINT32
-#define RSCAN0TMPTR40L RSCAN0.TMPTR40.UINT16[L]
-#define RSCAN0TMPTR40LL RSCAN0.TMPTR40.UINT8[LL]
-#define RSCAN0TMPTR40LH RSCAN0.TMPTR40.UINT8[LH]
-#define RSCAN0TMPTR40H RSCAN0.TMPTR40.UINT16[H]
-#define RSCAN0TMPTR40HL RSCAN0.TMPTR40.UINT8[HL]
-#define RSCAN0TMPTR40HH RSCAN0.TMPTR40.UINT8[HH]
-#define RSCAN0TMDF040 RSCAN0.TMDF040.UINT32
-#define RSCAN0TMDF040L RSCAN0.TMDF040.UINT16[L]
-#define RSCAN0TMDF040LL RSCAN0.TMDF040.UINT8[LL]
-#define RSCAN0TMDF040LH RSCAN0.TMDF040.UINT8[LH]
-#define RSCAN0TMDF040H RSCAN0.TMDF040.UINT16[H]
-#define RSCAN0TMDF040HL RSCAN0.TMDF040.UINT8[HL]
-#define RSCAN0TMDF040HH RSCAN0.TMDF040.UINT8[HH]
-#define RSCAN0TMDF140 RSCAN0.TMDF140.UINT32
-#define RSCAN0TMDF140L RSCAN0.TMDF140.UINT16[L]
-#define RSCAN0TMDF140LL RSCAN0.TMDF140.UINT8[LL]
-#define RSCAN0TMDF140LH RSCAN0.TMDF140.UINT8[LH]
-#define RSCAN0TMDF140H RSCAN0.TMDF140.UINT16[H]
-#define RSCAN0TMDF140HL RSCAN0.TMDF140.UINT8[HL]
-#define RSCAN0TMDF140HH RSCAN0.TMDF140.UINT8[HH]
-#define RSCAN0TMID41 RSCAN0.TMID41.UINT32
-#define RSCAN0TMID41L RSCAN0.TMID41.UINT16[L]
-#define RSCAN0TMID41LL RSCAN0.TMID41.UINT8[LL]
-#define RSCAN0TMID41LH RSCAN0.TMID41.UINT8[LH]
-#define RSCAN0TMID41H RSCAN0.TMID41.UINT16[H]
-#define RSCAN0TMID41HL RSCAN0.TMID41.UINT8[HL]
-#define RSCAN0TMID41HH RSCAN0.TMID41.UINT8[HH]
-#define RSCAN0TMPTR41 RSCAN0.TMPTR41.UINT32
-#define RSCAN0TMPTR41L RSCAN0.TMPTR41.UINT16[L]
-#define RSCAN0TMPTR41LL RSCAN0.TMPTR41.UINT8[LL]
-#define RSCAN0TMPTR41LH RSCAN0.TMPTR41.UINT8[LH]
-#define RSCAN0TMPTR41H RSCAN0.TMPTR41.UINT16[H]
-#define RSCAN0TMPTR41HL RSCAN0.TMPTR41.UINT8[HL]
-#define RSCAN0TMPTR41HH RSCAN0.TMPTR41.UINT8[HH]
-#define RSCAN0TMDF041 RSCAN0.TMDF041.UINT32
-#define RSCAN0TMDF041L RSCAN0.TMDF041.UINT16[L]
-#define RSCAN0TMDF041LL RSCAN0.TMDF041.UINT8[LL]
-#define RSCAN0TMDF041LH RSCAN0.TMDF041.UINT8[LH]
-#define RSCAN0TMDF041H RSCAN0.TMDF041.UINT16[H]
-#define RSCAN0TMDF041HL RSCAN0.TMDF041.UINT8[HL]
-#define RSCAN0TMDF041HH RSCAN0.TMDF041.UINT8[HH]
-#define RSCAN0TMDF141 RSCAN0.TMDF141.UINT32
-#define RSCAN0TMDF141L RSCAN0.TMDF141.UINT16[L]
-#define RSCAN0TMDF141LL RSCAN0.TMDF141.UINT8[LL]
-#define RSCAN0TMDF141LH RSCAN0.TMDF141.UINT8[LH]
-#define RSCAN0TMDF141H RSCAN0.TMDF141.UINT16[H]
-#define RSCAN0TMDF141HL RSCAN0.TMDF141.UINT8[HL]
-#define RSCAN0TMDF141HH RSCAN0.TMDF141.UINT8[HH]
-#define RSCAN0TMID42 RSCAN0.TMID42.UINT32
-#define RSCAN0TMID42L RSCAN0.TMID42.UINT16[L]
-#define RSCAN0TMID42LL RSCAN0.TMID42.UINT8[LL]
-#define RSCAN0TMID42LH RSCAN0.TMID42.UINT8[LH]
-#define RSCAN0TMID42H RSCAN0.TMID42.UINT16[H]
-#define RSCAN0TMID42HL RSCAN0.TMID42.UINT8[HL]
-#define RSCAN0TMID42HH RSCAN0.TMID42.UINT8[HH]
-#define RSCAN0TMPTR42 RSCAN0.TMPTR42.UINT32
-#define RSCAN0TMPTR42L RSCAN0.TMPTR42.UINT16[L]
-#define RSCAN0TMPTR42LL RSCAN0.TMPTR42.UINT8[LL]
-#define RSCAN0TMPTR42LH RSCAN0.TMPTR42.UINT8[LH]
-#define RSCAN0TMPTR42H RSCAN0.TMPTR42.UINT16[H]
-#define RSCAN0TMPTR42HL RSCAN0.TMPTR42.UINT8[HL]
-#define RSCAN0TMPTR42HH RSCAN0.TMPTR42.UINT8[HH]
-#define RSCAN0TMDF042 RSCAN0.TMDF042.UINT32
-#define RSCAN0TMDF042L RSCAN0.TMDF042.UINT16[L]
-#define RSCAN0TMDF042LL RSCAN0.TMDF042.UINT8[LL]
-#define RSCAN0TMDF042LH RSCAN0.TMDF042.UINT8[LH]
-#define RSCAN0TMDF042H RSCAN0.TMDF042.UINT16[H]
-#define RSCAN0TMDF042HL RSCAN0.TMDF042.UINT8[HL]
-#define RSCAN0TMDF042HH RSCAN0.TMDF042.UINT8[HH]
-#define RSCAN0TMDF142 RSCAN0.TMDF142.UINT32
-#define RSCAN0TMDF142L RSCAN0.TMDF142.UINT16[L]
-#define RSCAN0TMDF142LL RSCAN0.TMDF142.UINT8[LL]
-#define RSCAN0TMDF142LH RSCAN0.TMDF142.UINT8[LH]
-#define RSCAN0TMDF142H RSCAN0.TMDF142.UINT16[H]
-#define RSCAN0TMDF142HL RSCAN0.TMDF142.UINT8[HL]
-#define RSCAN0TMDF142HH RSCAN0.TMDF142.UINT8[HH]
-#define RSCAN0TMID43 RSCAN0.TMID43.UINT32
-#define RSCAN0TMID43L RSCAN0.TMID43.UINT16[L]
-#define RSCAN0TMID43LL RSCAN0.TMID43.UINT8[LL]
-#define RSCAN0TMID43LH RSCAN0.TMID43.UINT8[LH]
-#define RSCAN0TMID43H RSCAN0.TMID43.UINT16[H]
-#define RSCAN0TMID43HL RSCAN0.TMID43.UINT8[HL]
-#define RSCAN0TMID43HH RSCAN0.TMID43.UINT8[HH]
-#define RSCAN0TMPTR43 RSCAN0.TMPTR43.UINT32
-#define RSCAN0TMPTR43L RSCAN0.TMPTR43.UINT16[L]
-#define RSCAN0TMPTR43LL RSCAN0.TMPTR43.UINT8[LL]
-#define RSCAN0TMPTR43LH RSCAN0.TMPTR43.UINT8[LH]
-#define RSCAN0TMPTR43H RSCAN0.TMPTR43.UINT16[H]
-#define RSCAN0TMPTR43HL RSCAN0.TMPTR43.UINT8[HL]
-#define RSCAN0TMPTR43HH RSCAN0.TMPTR43.UINT8[HH]
-#define RSCAN0TMDF043 RSCAN0.TMDF043.UINT32
-#define RSCAN0TMDF043L RSCAN0.TMDF043.UINT16[L]
-#define RSCAN0TMDF043LL RSCAN0.TMDF043.UINT8[LL]
-#define RSCAN0TMDF043LH RSCAN0.TMDF043.UINT8[LH]
-#define RSCAN0TMDF043H RSCAN0.TMDF043.UINT16[H]
-#define RSCAN0TMDF043HL RSCAN0.TMDF043.UINT8[HL]
-#define RSCAN0TMDF043HH RSCAN0.TMDF043.UINT8[HH]
-#define RSCAN0TMDF143 RSCAN0.TMDF143.UINT32
-#define RSCAN0TMDF143L RSCAN0.TMDF143.UINT16[L]
-#define RSCAN0TMDF143LL RSCAN0.TMDF143.UINT8[LL]
-#define RSCAN0TMDF143LH RSCAN0.TMDF143.UINT8[LH]
-#define RSCAN0TMDF143H RSCAN0.TMDF143.UINT16[H]
-#define RSCAN0TMDF143HL RSCAN0.TMDF143.UINT8[HL]
-#define RSCAN0TMDF143HH RSCAN0.TMDF143.UINT8[HH]
-#define RSCAN0TMID44 RSCAN0.TMID44.UINT32
-#define RSCAN0TMID44L RSCAN0.TMID44.UINT16[L]
-#define RSCAN0TMID44LL RSCAN0.TMID44.UINT8[LL]
-#define RSCAN0TMID44LH RSCAN0.TMID44.UINT8[LH]
-#define RSCAN0TMID44H RSCAN0.TMID44.UINT16[H]
-#define RSCAN0TMID44HL RSCAN0.TMID44.UINT8[HL]
-#define RSCAN0TMID44HH RSCAN0.TMID44.UINT8[HH]
-#define RSCAN0TMPTR44 RSCAN0.TMPTR44.UINT32
-#define RSCAN0TMPTR44L RSCAN0.TMPTR44.UINT16[L]
-#define RSCAN0TMPTR44LL RSCAN0.TMPTR44.UINT8[LL]
-#define RSCAN0TMPTR44LH RSCAN0.TMPTR44.UINT8[LH]
-#define RSCAN0TMPTR44H RSCAN0.TMPTR44.UINT16[H]
-#define RSCAN0TMPTR44HL RSCAN0.TMPTR44.UINT8[HL]
-#define RSCAN0TMPTR44HH RSCAN0.TMPTR44.UINT8[HH]
-#define RSCAN0TMDF044 RSCAN0.TMDF044.UINT32
-#define RSCAN0TMDF044L RSCAN0.TMDF044.UINT16[L]
-#define RSCAN0TMDF044LL RSCAN0.TMDF044.UINT8[LL]
-#define RSCAN0TMDF044LH RSCAN0.TMDF044.UINT8[LH]
-#define RSCAN0TMDF044H RSCAN0.TMDF044.UINT16[H]
-#define RSCAN0TMDF044HL RSCAN0.TMDF044.UINT8[HL]
-#define RSCAN0TMDF044HH RSCAN0.TMDF044.UINT8[HH]
-#define RSCAN0TMDF144 RSCAN0.TMDF144.UINT32
-#define RSCAN0TMDF144L RSCAN0.TMDF144.UINT16[L]
-#define RSCAN0TMDF144LL RSCAN0.TMDF144.UINT8[LL]
-#define RSCAN0TMDF144LH RSCAN0.TMDF144.UINT8[LH]
-#define RSCAN0TMDF144H RSCAN0.TMDF144.UINT16[H]
-#define RSCAN0TMDF144HL RSCAN0.TMDF144.UINT8[HL]
-#define RSCAN0TMDF144HH RSCAN0.TMDF144.UINT8[HH]
-#define RSCAN0TMID45 RSCAN0.TMID45.UINT32
-#define RSCAN0TMID45L RSCAN0.TMID45.UINT16[L]
-#define RSCAN0TMID45LL RSCAN0.TMID45.UINT8[LL]
-#define RSCAN0TMID45LH RSCAN0.TMID45.UINT8[LH]
-#define RSCAN0TMID45H RSCAN0.TMID45.UINT16[H]
-#define RSCAN0TMID45HL RSCAN0.TMID45.UINT8[HL]
-#define RSCAN0TMID45HH RSCAN0.TMID45.UINT8[HH]
-#define RSCAN0TMPTR45 RSCAN0.TMPTR45.UINT32
-#define RSCAN0TMPTR45L RSCAN0.TMPTR45.UINT16[L]
-#define RSCAN0TMPTR45LL RSCAN0.TMPTR45.UINT8[LL]
-#define RSCAN0TMPTR45LH RSCAN0.TMPTR45.UINT8[LH]
-#define RSCAN0TMPTR45H RSCAN0.TMPTR45.UINT16[H]
-#define RSCAN0TMPTR45HL RSCAN0.TMPTR45.UINT8[HL]
-#define RSCAN0TMPTR45HH RSCAN0.TMPTR45.UINT8[HH]
-#define RSCAN0TMDF045 RSCAN0.TMDF045.UINT32
-#define RSCAN0TMDF045L RSCAN0.TMDF045.UINT16[L]
-#define RSCAN0TMDF045LL RSCAN0.TMDF045.UINT8[LL]
-#define RSCAN0TMDF045LH RSCAN0.TMDF045.UINT8[LH]
-#define RSCAN0TMDF045H RSCAN0.TMDF045.UINT16[H]
-#define RSCAN0TMDF045HL RSCAN0.TMDF045.UINT8[HL]
-#define RSCAN0TMDF045HH RSCAN0.TMDF045.UINT8[HH]
-#define RSCAN0TMDF145 RSCAN0.TMDF145.UINT32
-#define RSCAN0TMDF145L RSCAN0.TMDF145.UINT16[L]
-#define RSCAN0TMDF145LL RSCAN0.TMDF145.UINT8[LL]
-#define RSCAN0TMDF145LH RSCAN0.TMDF145.UINT8[LH]
-#define RSCAN0TMDF145H RSCAN0.TMDF145.UINT16[H]
-#define RSCAN0TMDF145HL RSCAN0.TMDF145.UINT8[HL]
-#define RSCAN0TMDF145HH RSCAN0.TMDF145.UINT8[HH]
-#define RSCAN0TMID46 RSCAN0.TMID46.UINT32
-#define RSCAN0TMID46L RSCAN0.TMID46.UINT16[L]
-#define RSCAN0TMID46LL RSCAN0.TMID46.UINT8[LL]
-#define RSCAN0TMID46LH RSCAN0.TMID46.UINT8[LH]
-#define RSCAN0TMID46H RSCAN0.TMID46.UINT16[H]
-#define RSCAN0TMID46HL RSCAN0.TMID46.UINT8[HL]
-#define RSCAN0TMID46HH RSCAN0.TMID46.UINT8[HH]
-#define RSCAN0TMPTR46 RSCAN0.TMPTR46.UINT32
-#define RSCAN0TMPTR46L RSCAN0.TMPTR46.UINT16[L]
-#define RSCAN0TMPTR46LL RSCAN0.TMPTR46.UINT8[LL]
-#define RSCAN0TMPTR46LH RSCAN0.TMPTR46.UINT8[LH]
-#define RSCAN0TMPTR46H RSCAN0.TMPTR46.UINT16[H]
-#define RSCAN0TMPTR46HL RSCAN0.TMPTR46.UINT8[HL]
-#define RSCAN0TMPTR46HH RSCAN0.TMPTR46.UINT8[HH]
-#define RSCAN0TMDF046 RSCAN0.TMDF046.UINT32
-#define RSCAN0TMDF046L RSCAN0.TMDF046.UINT16[L]
-#define RSCAN0TMDF046LL RSCAN0.TMDF046.UINT8[LL]
-#define RSCAN0TMDF046LH RSCAN0.TMDF046.UINT8[LH]
-#define RSCAN0TMDF046H RSCAN0.TMDF046.UINT16[H]
-#define RSCAN0TMDF046HL RSCAN0.TMDF046.UINT8[HL]
-#define RSCAN0TMDF046HH RSCAN0.TMDF046.UINT8[HH]
-#define RSCAN0TMDF146 RSCAN0.TMDF146.UINT32
-#define RSCAN0TMDF146L RSCAN0.TMDF146.UINT16[L]
-#define RSCAN0TMDF146LL RSCAN0.TMDF146.UINT8[LL]
-#define RSCAN0TMDF146LH RSCAN0.TMDF146.UINT8[LH]
-#define RSCAN0TMDF146H RSCAN0.TMDF146.UINT16[H]
-#define RSCAN0TMDF146HL RSCAN0.TMDF146.UINT8[HL]
-#define RSCAN0TMDF146HH RSCAN0.TMDF146.UINT8[HH]
-#define RSCAN0TMID47 RSCAN0.TMID47.UINT32
-#define RSCAN0TMID47L RSCAN0.TMID47.UINT16[L]
-#define RSCAN0TMID47LL RSCAN0.TMID47.UINT8[LL]
-#define RSCAN0TMID47LH RSCAN0.TMID47.UINT8[LH]
-#define RSCAN0TMID47H RSCAN0.TMID47.UINT16[H]
-#define RSCAN0TMID47HL RSCAN0.TMID47.UINT8[HL]
-#define RSCAN0TMID47HH RSCAN0.TMID47.UINT8[HH]
-#define RSCAN0TMPTR47 RSCAN0.TMPTR47.UINT32
-#define RSCAN0TMPTR47L RSCAN0.TMPTR47.UINT16[L]
-#define RSCAN0TMPTR47LL RSCAN0.TMPTR47.UINT8[LL]
-#define RSCAN0TMPTR47LH RSCAN0.TMPTR47.UINT8[LH]
-#define RSCAN0TMPTR47H RSCAN0.TMPTR47.UINT16[H]
-#define RSCAN0TMPTR47HL RSCAN0.TMPTR47.UINT8[HL]
-#define RSCAN0TMPTR47HH RSCAN0.TMPTR47.UINT8[HH]
-#define RSCAN0TMDF047 RSCAN0.TMDF047.UINT32
-#define RSCAN0TMDF047L RSCAN0.TMDF047.UINT16[L]
-#define RSCAN0TMDF047LL RSCAN0.TMDF047.UINT8[LL]
-#define RSCAN0TMDF047LH RSCAN0.TMDF047.UINT8[LH]
-#define RSCAN0TMDF047H RSCAN0.TMDF047.UINT16[H]
-#define RSCAN0TMDF047HL RSCAN0.TMDF047.UINT8[HL]
-#define RSCAN0TMDF047HH RSCAN0.TMDF047.UINT8[HH]
-#define RSCAN0TMDF147 RSCAN0.TMDF147.UINT32
-#define RSCAN0TMDF147L RSCAN0.TMDF147.UINT16[L]
-#define RSCAN0TMDF147LL RSCAN0.TMDF147.UINT8[LL]
-#define RSCAN0TMDF147LH RSCAN0.TMDF147.UINT8[LH]
-#define RSCAN0TMDF147H RSCAN0.TMDF147.UINT16[H]
-#define RSCAN0TMDF147HL RSCAN0.TMDF147.UINT8[HL]
-#define RSCAN0TMDF147HH RSCAN0.TMDF147.UINT8[HH]
-#define RSCAN0TMID48 RSCAN0.TMID48.UINT32
-#define RSCAN0TMID48L RSCAN0.TMID48.UINT16[L]
-#define RSCAN0TMID48LL RSCAN0.TMID48.UINT8[LL]
-#define RSCAN0TMID48LH RSCAN0.TMID48.UINT8[LH]
-#define RSCAN0TMID48H RSCAN0.TMID48.UINT16[H]
-#define RSCAN0TMID48HL RSCAN0.TMID48.UINT8[HL]
-#define RSCAN0TMID48HH RSCAN0.TMID48.UINT8[HH]
-#define RSCAN0TMPTR48 RSCAN0.TMPTR48.UINT32
-#define RSCAN0TMPTR48L RSCAN0.TMPTR48.UINT16[L]
-#define RSCAN0TMPTR48LL RSCAN0.TMPTR48.UINT8[LL]
-#define RSCAN0TMPTR48LH RSCAN0.TMPTR48.UINT8[LH]
-#define RSCAN0TMPTR48H RSCAN0.TMPTR48.UINT16[H]
-#define RSCAN0TMPTR48HL RSCAN0.TMPTR48.UINT8[HL]
-#define RSCAN0TMPTR48HH RSCAN0.TMPTR48.UINT8[HH]
-#define RSCAN0TMDF048 RSCAN0.TMDF048.UINT32
-#define RSCAN0TMDF048L RSCAN0.TMDF048.UINT16[L]
-#define RSCAN0TMDF048LL RSCAN0.TMDF048.UINT8[LL]
-#define RSCAN0TMDF048LH RSCAN0.TMDF048.UINT8[LH]
-#define RSCAN0TMDF048H RSCAN0.TMDF048.UINT16[H]
-#define RSCAN0TMDF048HL RSCAN0.TMDF048.UINT8[HL]
-#define RSCAN0TMDF048HH RSCAN0.TMDF048.UINT8[HH]
-#define RSCAN0TMDF148 RSCAN0.TMDF148.UINT32
-#define RSCAN0TMDF148L RSCAN0.TMDF148.UINT16[L]
-#define RSCAN0TMDF148LL RSCAN0.TMDF148.UINT8[LL]
-#define RSCAN0TMDF148LH RSCAN0.TMDF148.UINT8[LH]
-#define RSCAN0TMDF148H RSCAN0.TMDF148.UINT16[H]
-#define RSCAN0TMDF148HL RSCAN0.TMDF148.UINT8[HL]
-#define RSCAN0TMDF148HH RSCAN0.TMDF148.UINT8[HH]
-#define RSCAN0TMID49 RSCAN0.TMID49.UINT32
-#define RSCAN0TMID49L RSCAN0.TMID49.UINT16[L]
-#define RSCAN0TMID49LL RSCAN0.TMID49.UINT8[LL]
-#define RSCAN0TMID49LH RSCAN0.TMID49.UINT8[LH]
-#define RSCAN0TMID49H RSCAN0.TMID49.UINT16[H]
-#define RSCAN0TMID49HL RSCAN0.TMID49.UINT8[HL]
-#define RSCAN0TMID49HH RSCAN0.TMID49.UINT8[HH]
-#define RSCAN0TMPTR49 RSCAN0.TMPTR49.UINT32
-#define RSCAN0TMPTR49L RSCAN0.TMPTR49.UINT16[L]
-#define RSCAN0TMPTR49LL RSCAN0.TMPTR49.UINT8[LL]
-#define RSCAN0TMPTR49LH RSCAN0.TMPTR49.UINT8[LH]
-#define RSCAN0TMPTR49H RSCAN0.TMPTR49.UINT16[H]
-#define RSCAN0TMPTR49HL RSCAN0.TMPTR49.UINT8[HL]
-#define RSCAN0TMPTR49HH RSCAN0.TMPTR49.UINT8[HH]
-#define RSCAN0TMDF049 RSCAN0.TMDF049.UINT32
-#define RSCAN0TMDF049L RSCAN0.TMDF049.UINT16[L]
-#define RSCAN0TMDF049LL RSCAN0.TMDF049.UINT8[LL]
-#define RSCAN0TMDF049LH RSCAN0.TMDF049.UINT8[LH]
-#define RSCAN0TMDF049H RSCAN0.TMDF049.UINT16[H]
-#define RSCAN0TMDF049HL RSCAN0.TMDF049.UINT8[HL]
-#define RSCAN0TMDF049HH RSCAN0.TMDF049.UINT8[HH]
-#define RSCAN0TMDF149 RSCAN0.TMDF149.UINT32
-#define RSCAN0TMDF149L RSCAN0.TMDF149.UINT16[L]
-#define RSCAN0TMDF149LL RSCAN0.TMDF149.UINT8[LL]
-#define RSCAN0TMDF149LH RSCAN0.TMDF149.UINT8[LH]
-#define RSCAN0TMDF149H RSCAN0.TMDF149.UINT16[H]
-#define RSCAN0TMDF149HL RSCAN0.TMDF149.UINT8[HL]
-#define RSCAN0TMDF149HH RSCAN0.TMDF149.UINT8[HH]
-#define RSCAN0TMID50 RSCAN0.TMID50.UINT32
-#define RSCAN0TMID50L RSCAN0.TMID50.UINT16[L]
-#define RSCAN0TMID50LL RSCAN0.TMID50.UINT8[LL]
-#define RSCAN0TMID50LH RSCAN0.TMID50.UINT8[LH]
-#define RSCAN0TMID50H RSCAN0.TMID50.UINT16[H]
-#define RSCAN0TMID50HL RSCAN0.TMID50.UINT8[HL]
-#define RSCAN0TMID50HH RSCAN0.TMID50.UINT8[HH]
-#define RSCAN0TMPTR50 RSCAN0.TMPTR50.UINT32
-#define RSCAN0TMPTR50L RSCAN0.TMPTR50.UINT16[L]
-#define RSCAN0TMPTR50LL RSCAN0.TMPTR50.UINT8[LL]
-#define RSCAN0TMPTR50LH RSCAN0.TMPTR50.UINT8[LH]
-#define RSCAN0TMPTR50H RSCAN0.TMPTR50.UINT16[H]
-#define RSCAN0TMPTR50HL RSCAN0.TMPTR50.UINT8[HL]
-#define RSCAN0TMPTR50HH RSCAN0.TMPTR50.UINT8[HH]
-#define RSCAN0TMDF050 RSCAN0.TMDF050.UINT32
-#define RSCAN0TMDF050L RSCAN0.TMDF050.UINT16[L]
-#define RSCAN0TMDF050LL RSCAN0.TMDF050.UINT8[LL]
-#define RSCAN0TMDF050LH RSCAN0.TMDF050.UINT8[LH]
-#define RSCAN0TMDF050H RSCAN0.TMDF050.UINT16[H]
-#define RSCAN0TMDF050HL RSCAN0.TMDF050.UINT8[HL]
-#define RSCAN0TMDF050HH RSCAN0.TMDF050.UINT8[HH]
-#define RSCAN0TMDF150 RSCAN0.TMDF150.UINT32
-#define RSCAN0TMDF150L RSCAN0.TMDF150.UINT16[L]
-#define RSCAN0TMDF150LL RSCAN0.TMDF150.UINT8[LL]
-#define RSCAN0TMDF150LH RSCAN0.TMDF150.UINT8[LH]
-#define RSCAN0TMDF150H RSCAN0.TMDF150.UINT16[H]
-#define RSCAN0TMDF150HL RSCAN0.TMDF150.UINT8[HL]
-#define RSCAN0TMDF150HH RSCAN0.TMDF150.UINT8[HH]
-#define RSCAN0TMID51 RSCAN0.TMID51.UINT32
-#define RSCAN0TMID51L RSCAN0.TMID51.UINT16[L]
-#define RSCAN0TMID51LL RSCAN0.TMID51.UINT8[LL]
-#define RSCAN0TMID51LH RSCAN0.TMID51.UINT8[LH]
-#define RSCAN0TMID51H RSCAN0.TMID51.UINT16[H]
-#define RSCAN0TMID51HL RSCAN0.TMID51.UINT8[HL]
-#define RSCAN0TMID51HH RSCAN0.TMID51.UINT8[HH]
-#define RSCAN0TMPTR51 RSCAN0.TMPTR51.UINT32
-#define RSCAN0TMPTR51L RSCAN0.TMPTR51.UINT16[L]
-#define RSCAN0TMPTR51LL RSCAN0.TMPTR51.UINT8[LL]
-#define RSCAN0TMPTR51LH RSCAN0.TMPTR51.UINT8[LH]
-#define RSCAN0TMPTR51H RSCAN0.TMPTR51.UINT16[H]
-#define RSCAN0TMPTR51HL RSCAN0.TMPTR51.UINT8[HL]
-#define RSCAN0TMPTR51HH RSCAN0.TMPTR51.UINT8[HH]
-#define RSCAN0TMDF051 RSCAN0.TMDF051.UINT32
-#define RSCAN0TMDF051L RSCAN0.TMDF051.UINT16[L]
-#define RSCAN0TMDF051LL RSCAN0.TMDF051.UINT8[LL]
-#define RSCAN0TMDF051LH RSCAN0.TMDF051.UINT8[LH]
-#define RSCAN0TMDF051H RSCAN0.TMDF051.UINT16[H]
-#define RSCAN0TMDF051HL RSCAN0.TMDF051.UINT8[HL]
-#define RSCAN0TMDF051HH RSCAN0.TMDF051.UINT8[HH]
-#define RSCAN0TMDF151 RSCAN0.TMDF151.UINT32
-#define RSCAN0TMDF151L RSCAN0.TMDF151.UINT16[L]
-#define RSCAN0TMDF151LL RSCAN0.TMDF151.UINT8[LL]
-#define RSCAN0TMDF151LH RSCAN0.TMDF151.UINT8[LH]
-#define RSCAN0TMDF151H RSCAN0.TMDF151.UINT16[H]
-#define RSCAN0TMDF151HL RSCAN0.TMDF151.UINT8[HL]
-#define RSCAN0TMDF151HH RSCAN0.TMDF151.UINT8[HH]
-#define RSCAN0TMID52 RSCAN0.TMID52.UINT32
-#define RSCAN0TMID52L RSCAN0.TMID52.UINT16[L]
-#define RSCAN0TMID52LL RSCAN0.TMID52.UINT8[LL]
-#define RSCAN0TMID52LH RSCAN0.TMID52.UINT8[LH]
-#define RSCAN0TMID52H RSCAN0.TMID52.UINT16[H]
-#define RSCAN0TMID52HL RSCAN0.TMID52.UINT8[HL]
-#define RSCAN0TMID52HH RSCAN0.TMID52.UINT8[HH]
-#define RSCAN0TMPTR52 RSCAN0.TMPTR52.UINT32
-#define RSCAN0TMPTR52L RSCAN0.TMPTR52.UINT16[L]
-#define RSCAN0TMPTR52LL RSCAN0.TMPTR52.UINT8[LL]
-#define RSCAN0TMPTR52LH RSCAN0.TMPTR52.UINT8[LH]
-#define RSCAN0TMPTR52H RSCAN0.TMPTR52.UINT16[H]
-#define RSCAN0TMPTR52HL RSCAN0.TMPTR52.UINT8[HL]
-#define RSCAN0TMPTR52HH RSCAN0.TMPTR52.UINT8[HH]
-#define RSCAN0TMDF052 RSCAN0.TMDF052.UINT32
-#define RSCAN0TMDF052L RSCAN0.TMDF052.UINT16[L]
-#define RSCAN0TMDF052LL RSCAN0.TMDF052.UINT8[LL]
-#define RSCAN0TMDF052LH RSCAN0.TMDF052.UINT8[LH]
-#define RSCAN0TMDF052H RSCAN0.TMDF052.UINT16[H]
-#define RSCAN0TMDF052HL RSCAN0.TMDF052.UINT8[HL]
-#define RSCAN0TMDF052HH RSCAN0.TMDF052.UINT8[HH]
-#define RSCAN0TMDF152 RSCAN0.TMDF152.UINT32
-#define RSCAN0TMDF152L RSCAN0.TMDF152.UINT16[L]
-#define RSCAN0TMDF152LL RSCAN0.TMDF152.UINT8[LL]
-#define RSCAN0TMDF152LH RSCAN0.TMDF152.UINT8[LH]
-#define RSCAN0TMDF152H RSCAN0.TMDF152.UINT16[H]
-#define RSCAN0TMDF152HL RSCAN0.TMDF152.UINT8[HL]
-#define RSCAN0TMDF152HH RSCAN0.TMDF152.UINT8[HH]
-#define RSCAN0TMID53 RSCAN0.TMID53.UINT32
-#define RSCAN0TMID53L RSCAN0.TMID53.UINT16[L]
-#define RSCAN0TMID53LL RSCAN0.TMID53.UINT8[LL]
-#define RSCAN0TMID53LH RSCAN0.TMID53.UINT8[LH]
-#define RSCAN0TMID53H RSCAN0.TMID53.UINT16[H]
-#define RSCAN0TMID53HL RSCAN0.TMID53.UINT8[HL]
-#define RSCAN0TMID53HH RSCAN0.TMID53.UINT8[HH]
-#define RSCAN0TMPTR53 RSCAN0.TMPTR53.UINT32
-#define RSCAN0TMPTR53L RSCAN0.TMPTR53.UINT16[L]
-#define RSCAN0TMPTR53LL RSCAN0.TMPTR53.UINT8[LL]
-#define RSCAN0TMPTR53LH RSCAN0.TMPTR53.UINT8[LH]
-#define RSCAN0TMPTR53H RSCAN0.TMPTR53.UINT16[H]
-#define RSCAN0TMPTR53HL RSCAN0.TMPTR53.UINT8[HL]
-#define RSCAN0TMPTR53HH RSCAN0.TMPTR53.UINT8[HH]
-#define RSCAN0TMDF053 RSCAN0.TMDF053.UINT32
-#define RSCAN0TMDF053L RSCAN0.TMDF053.UINT16[L]
-#define RSCAN0TMDF053LL RSCAN0.TMDF053.UINT8[LL]
-#define RSCAN0TMDF053LH RSCAN0.TMDF053.UINT8[LH]
-#define RSCAN0TMDF053H RSCAN0.TMDF053.UINT16[H]
-#define RSCAN0TMDF053HL RSCAN0.TMDF053.UINT8[HL]
-#define RSCAN0TMDF053HH RSCAN0.TMDF053.UINT8[HH]
-#define RSCAN0TMDF153 RSCAN0.TMDF153.UINT32
-#define RSCAN0TMDF153L RSCAN0.TMDF153.UINT16[L]
-#define RSCAN0TMDF153LL RSCAN0.TMDF153.UINT8[LL]
-#define RSCAN0TMDF153LH RSCAN0.TMDF153.UINT8[LH]
-#define RSCAN0TMDF153H RSCAN0.TMDF153.UINT16[H]
-#define RSCAN0TMDF153HL RSCAN0.TMDF153.UINT8[HL]
-#define RSCAN0TMDF153HH RSCAN0.TMDF153.UINT8[HH]
-#define RSCAN0TMID54 RSCAN0.TMID54.UINT32
-#define RSCAN0TMID54L RSCAN0.TMID54.UINT16[L]
-#define RSCAN0TMID54LL RSCAN0.TMID54.UINT8[LL]
-#define RSCAN0TMID54LH RSCAN0.TMID54.UINT8[LH]
-#define RSCAN0TMID54H RSCAN0.TMID54.UINT16[H]
-#define RSCAN0TMID54HL RSCAN0.TMID54.UINT8[HL]
-#define RSCAN0TMID54HH RSCAN0.TMID54.UINT8[HH]
-#define RSCAN0TMPTR54 RSCAN0.TMPTR54.UINT32
-#define RSCAN0TMPTR54L RSCAN0.TMPTR54.UINT16[L]
-#define RSCAN0TMPTR54LL RSCAN0.TMPTR54.UINT8[LL]
-#define RSCAN0TMPTR54LH RSCAN0.TMPTR54.UINT8[LH]
-#define RSCAN0TMPTR54H RSCAN0.TMPTR54.UINT16[H]
-#define RSCAN0TMPTR54HL RSCAN0.TMPTR54.UINT8[HL]
-#define RSCAN0TMPTR54HH RSCAN0.TMPTR54.UINT8[HH]
-#define RSCAN0TMDF054 RSCAN0.TMDF054.UINT32
-#define RSCAN0TMDF054L RSCAN0.TMDF054.UINT16[L]
-#define RSCAN0TMDF054LL RSCAN0.TMDF054.UINT8[LL]
-#define RSCAN0TMDF054LH RSCAN0.TMDF054.UINT8[LH]
-#define RSCAN0TMDF054H RSCAN0.TMDF054.UINT16[H]
-#define RSCAN0TMDF054HL RSCAN0.TMDF054.UINT8[HL]
-#define RSCAN0TMDF054HH RSCAN0.TMDF054.UINT8[HH]
-#define RSCAN0TMDF154 RSCAN0.TMDF154.UINT32
-#define RSCAN0TMDF154L RSCAN0.TMDF154.UINT16[L]
-#define RSCAN0TMDF154LL RSCAN0.TMDF154.UINT8[LL]
-#define RSCAN0TMDF154LH RSCAN0.TMDF154.UINT8[LH]
-#define RSCAN0TMDF154H RSCAN0.TMDF154.UINT16[H]
-#define RSCAN0TMDF154HL RSCAN0.TMDF154.UINT8[HL]
-#define RSCAN0TMDF154HH RSCAN0.TMDF154.UINT8[HH]
-#define RSCAN0TMID55 RSCAN0.TMID55.UINT32
-#define RSCAN0TMID55L RSCAN0.TMID55.UINT16[L]
-#define RSCAN0TMID55LL RSCAN0.TMID55.UINT8[LL]
-#define RSCAN0TMID55LH RSCAN0.TMID55.UINT8[LH]
-#define RSCAN0TMID55H RSCAN0.TMID55.UINT16[H]
-#define RSCAN0TMID55HL RSCAN0.TMID55.UINT8[HL]
-#define RSCAN0TMID55HH RSCAN0.TMID55.UINT8[HH]
-#define RSCAN0TMPTR55 RSCAN0.TMPTR55.UINT32
-#define RSCAN0TMPTR55L RSCAN0.TMPTR55.UINT16[L]
-#define RSCAN0TMPTR55LL RSCAN0.TMPTR55.UINT8[LL]
-#define RSCAN0TMPTR55LH RSCAN0.TMPTR55.UINT8[LH]
-#define RSCAN0TMPTR55H RSCAN0.TMPTR55.UINT16[H]
-#define RSCAN0TMPTR55HL RSCAN0.TMPTR55.UINT8[HL]
-#define RSCAN0TMPTR55HH RSCAN0.TMPTR55.UINT8[HH]
-#define RSCAN0TMDF055 RSCAN0.TMDF055.UINT32
-#define RSCAN0TMDF055L RSCAN0.TMDF055.UINT16[L]
-#define RSCAN0TMDF055LL RSCAN0.TMDF055.UINT8[LL]
-#define RSCAN0TMDF055LH RSCAN0.TMDF055.UINT8[LH]
-#define RSCAN0TMDF055H RSCAN0.TMDF055.UINT16[H]
-#define RSCAN0TMDF055HL RSCAN0.TMDF055.UINT8[HL]
-#define RSCAN0TMDF055HH RSCAN0.TMDF055.UINT8[HH]
-#define RSCAN0TMDF155 RSCAN0.TMDF155.UINT32
-#define RSCAN0TMDF155L RSCAN0.TMDF155.UINT16[L]
-#define RSCAN0TMDF155LL RSCAN0.TMDF155.UINT8[LL]
-#define RSCAN0TMDF155LH RSCAN0.TMDF155.UINT8[LH]
-#define RSCAN0TMDF155H RSCAN0.TMDF155.UINT16[H]
-#define RSCAN0TMDF155HL RSCAN0.TMDF155.UINT8[HL]
-#define RSCAN0TMDF155HH RSCAN0.TMDF155.UINT8[HH]
-#define RSCAN0TMID56 RSCAN0.TMID56.UINT32
-#define RSCAN0TMID56L RSCAN0.TMID56.UINT16[L]
-#define RSCAN0TMID56LL RSCAN0.TMID56.UINT8[LL]
-#define RSCAN0TMID56LH RSCAN0.TMID56.UINT8[LH]
-#define RSCAN0TMID56H RSCAN0.TMID56.UINT16[H]
-#define RSCAN0TMID56HL RSCAN0.TMID56.UINT8[HL]
-#define RSCAN0TMID56HH RSCAN0.TMID56.UINT8[HH]
-#define RSCAN0TMPTR56 RSCAN0.TMPTR56.UINT32
-#define RSCAN0TMPTR56L RSCAN0.TMPTR56.UINT16[L]
-#define RSCAN0TMPTR56LL RSCAN0.TMPTR56.UINT8[LL]
-#define RSCAN0TMPTR56LH RSCAN0.TMPTR56.UINT8[LH]
-#define RSCAN0TMPTR56H RSCAN0.TMPTR56.UINT16[H]
-#define RSCAN0TMPTR56HL RSCAN0.TMPTR56.UINT8[HL]
-#define RSCAN0TMPTR56HH RSCAN0.TMPTR56.UINT8[HH]
-#define RSCAN0TMDF056 RSCAN0.TMDF056.UINT32
-#define RSCAN0TMDF056L RSCAN0.TMDF056.UINT16[L]
-#define RSCAN0TMDF056LL RSCAN0.TMDF056.UINT8[LL]
-#define RSCAN0TMDF056LH RSCAN0.TMDF056.UINT8[LH]
-#define RSCAN0TMDF056H RSCAN0.TMDF056.UINT16[H]
-#define RSCAN0TMDF056HL RSCAN0.TMDF056.UINT8[HL]
-#define RSCAN0TMDF056HH RSCAN0.TMDF056.UINT8[HH]
-#define RSCAN0TMDF156 RSCAN0.TMDF156.UINT32
-#define RSCAN0TMDF156L RSCAN0.TMDF156.UINT16[L]
-#define RSCAN0TMDF156LL RSCAN0.TMDF156.UINT8[LL]
-#define RSCAN0TMDF156LH RSCAN0.TMDF156.UINT8[LH]
-#define RSCAN0TMDF156H RSCAN0.TMDF156.UINT16[H]
-#define RSCAN0TMDF156HL RSCAN0.TMDF156.UINT8[HL]
-#define RSCAN0TMDF156HH RSCAN0.TMDF156.UINT8[HH]
-#define RSCAN0TMID57 RSCAN0.TMID57.UINT32
-#define RSCAN0TMID57L RSCAN0.TMID57.UINT16[L]
-#define RSCAN0TMID57LL RSCAN0.TMID57.UINT8[LL]
-#define RSCAN0TMID57LH RSCAN0.TMID57.UINT8[LH]
-#define RSCAN0TMID57H RSCAN0.TMID57.UINT16[H]
-#define RSCAN0TMID57HL RSCAN0.TMID57.UINT8[HL]
-#define RSCAN0TMID57HH RSCAN0.TMID57.UINT8[HH]
-#define RSCAN0TMPTR57 RSCAN0.TMPTR57.UINT32
-#define RSCAN0TMPTR57L RSCAN0.TMPTR57.UINT16[L]
-#define RSCAN0TMPTR57LL RSCAN0.TMPTR57.UINT8[LL]
-#define RSCAN0TMPTR57LH RSCAN0.TMPTR57.UINT8[LH]
-#define RSCAN0TMPTR57H RSCAN0.TMPTR57.UINT16[H]
-#define RSCAN0TMPTR57HL RSCAN0.TMPTR57.UINT8[HL]
-#define RSCAN0TMPTR57HH RSCAN0.TMPTR57.UINT8[HH]
-#define RSCAN0TMDF057 RSCAN0.TMDF057.UINT32
-#define RSCAN0TMDF057L RSCAN0.TMDF057.UINT16[L]
-#define RSCAN0TMDF057LL RSCAN0.TMDF057.UINT8[LL]
-#define RSCAN0TMDF057LH RSCAN0.TMDF057.UINT8[LH]
-#define RSCAN0TMDF057H RSCAN0.TMDF057.UINT16[H]
-#define RSCAN0TMDF057HL RSCAN0.TMDF057.UINT8[HL]
-#define RSCAN0TMDF057HH RSCAN0.TMDF057.UINT8[HH]
-#define RSCAN0TMDF157 RSCAN0.TMDF157.UINT32
-#define RSCAN0TMDF157L RSCAN0.TMDF157.UINT16[L]
-#define RSCAN0TMDF157LL RSCAN0.TMDF157.UINT8[LL]
-#define RSCAN0TMDF157LH RSCAN0.TMDF157.UINT8[LH]
-#define RSCAN0TMDF157H RSCAN0.TMDF157.UINT16[H]
-#define RSCAN0TMDF157HL RSCAN0.TMDF157.UINT8[HL]
-#define RSCAN0TMDF157HH RSCAN0.TMDF157.UINT8[HH]
-#define RSCAN0TMID58 RSCAN0.TMID58.UINT32
-#define RSCAN0TMID58L RSCAN0.TMID58.UINT16[L]
-#define RSCAN0TMID58LL RSCAN0.TMID58.UINT8[LL]
-#define RSCAN0TMID58LH RSCAN0.TMID58.UINT8[LH]
-#define RSCAN0TMID58H RSCAN0.TMID58.UINT16[H]
-#define RSCAN0TMID58HL RSCAN0.TMID58.UINT8[HL]
-#define RSCAN0TMID58HH RSCAN0.TMID58.UINT8[HH]
-#define RSCAN0TMPTR58 RSCAN0.TMPTR58.UINT32
-#define RSCAN0TMPTR58L RSCAN0.TMPTR58.UINT16[L]
-#define RSCAN0TMPTR58LL RSCAN0.TMPTR58.UINT8[LL]
-#define RSCAN0TMPTR58LH RSCAN0.TMPTR58.UINT8[LH]
-#define RSCAN0TMPTR58H RSCAN0.TMPTR58.UINT16[H]
-#define RSCAN0TMPTR58HL RSCAN0.TMPTR58.UINT8[HL]
-#define RSCAN0TMPTR58HH RSCAN0.TMPTR58.UINT8[HH]
-#define RSCAN0TMDF058 RSCAN0.TMDF058.UINT32
-#define RSCAN0TMDF058L RSCAN0.TMDF058.UINT16[L]
-#define RSCAN0TMDF058LL RSCAN0.TMDF058.UINT8[LL]
-#define RSCAN0TMDF058LH RSCAN0.TMDF058.UINT8[LH]
-#define RSCAN0TMDF058H RSCAN0.TMDF058.UINT16[H]
-#define RSCAN0TMDF058HL RSCAN0.TMDF058.UINT8[HL]
-#define RSCAN0TMDF058HH RSCAN0.TMDF058.UINT8[HH]
-#define RSCAN0TMDF158 RSCAN0.TMDF158.UINT32
-#define RSCAN0TMDF158L RSCAN0.TMDF158.UINT16[L]
-#define RSCAN0TMDF158LL RSCAN0.TMDF158.UINT8[LL]
-#define RSCAN0TMDF158LH RSCAN0.TMDF158.UINT8[LH]
-#define RSCAN0TMDF158H RSCAN0.TMDF158.UINT16[H]
-#define RSCAN0TMDF158HL RSCAN0.TMDF158.UINT8[HL]
-#define RSCAN0TMDF158HH RSCAN0.TMDF158.UINT8[HH]
-#define RSCAN0TMID59 RSCAN0.TMID59.UINT32
-#define RSCAN0TMID59L RSCAN0.TMID59.UINT16[L]
-#define RSCAN0TMID59LL RSCAN0.TMID59.UINT8[LL]
-#define RSCAN0TMID59LH RSCAN0.TMID59.UINT8[LH]
-#define RSCAN0TMID59H RSCAN0.TMID59.UINT16[H]
-#define RSCAN0TMID59HL RSCAN0.TMID59.UINT8[HL]
-#define RSCAN0TMID59HH RSCAN0.TMID59.UINT8[HH]
-#define RSCAN0TMPTR59 RSCAN0.TMPTR59.UINT32
-#define RSCAN0TMPTR59L RSCAN0.TMPTR59.UINT16[L]
-#define RSCAN0TMPTR59LL RSCAN0.TMPTR59.UINT8[LL]
-#define RSCAN0TMPTR59LH RSCAN0.TMPTR59.UINT8[LH]
-#define RSCAN0TMPTR59H RSCAN0.TMPTR59.UINT16[H]
-#define RSCAN0TMPTR59HL RSCAN0.TMPTR59.UINT8[HL]
-#define RSCAN0TMPTR59HH RSCAN0.TMPTR59.UINT8[HH]
-#define RSCAN0TMDF059 RSCAN0.TMDF059.UINT32
-#define RSCAN0TMDF059L RSCAN0.TMDF059.UINT16[L]
-#define RSCAN0TMDF059LL RSCAN0.TMDF059.UINT8[LL]
-#define RSCAN0TMDF059LH RSCAN0.TMDF059.UINT8[LH]
-#define RSCAN0TMDF059H RSCAN0.TMDF059.UINT16[H]
-#define RSCAN0TMDF059HL RSCAN0.TMDF059.UINT8[HL]
-#define RSCAN0TMDF059HH RSCAN0.TMDF059.UINT8[HH]
-#define RSCAN0TMDF159 RSCAN0.TMDF159.UINT32
-#define RSCAN0TMDF159L RSCAN0.TMDF159.UINT16[L]
-#define RSCAN0TMDF159LL RSCAN0.TMDF159.UINT8[LL]
-#define RSCAN0TMDF159LH RSCAN0.TMDF159.UINT8[LH]
-#define RSCAN0TMDF159H RSCAN0.TMDF159.UINT16[H]
-#define RSCAN0TMDF159HL RSCAN0.TMDF159.UINT8[HL]
-#define RSCAN0TMDF159HH RSCAN0.TMDF159.UINT8[HH]
-#define RSCAN0TMID60 RSCAN0.TMID60.UINT32
-#define RSCAN0TMID60L RSCAN0.TMID60.UINT16[L]
-#define RSCAN0TMID60LL RSCAN0.TMID60.UINT8[LL]
-#define RSCAN0TMID60LH RSCAN0.TMID60.UINT8[LH]
-#define RSCAN0TMID60H RSCAN0.TMID60.UINT16[H]
-#define RSCAN0TMID60HL RSCAN0.TMID60.UINT8[HL]
-#define RSCAN0TMID60HH RSCAN0.TMID60.UINT8[HH]
-#define RSCAN0TMPTR60 RSCAN0.TMPTR60.UINT32
-#define RSCAN0TMPTR60L RSCAN0.TMPTR60.UINT16[L]
-#define RSCAN0TMPTR60LL RSCAN0.TMPTR60.UINT8[LL]
-#define RSCAN0TMPTR60LH RSCAN0.TMPTR60.UINT8[LH]
-#define RSCAN0TMPTR60H RSCAN0.TMPTR60.UINT16[H]
-#define RSCAN0TMPTR60HL RSCAN0.TMPTR60.UINT8[HL]
-#define RSCAN0TMPTR60HH RSCAN0.TMPTR60.UINT8[HH]
-#define RSCAN0TMDF060 RSCAN0.TMDF060.UINT32
-#define RSCAN0TMDF060L RSCAN0.TMDF060.UINT16[L]
-#define RSCAN0TMDF060LL RSCAN0.TMDF060.UINT8[LL]
-#define RSCAN0TMDF060LH RSCAN0.TMDF060.UINT8[LH]
-#define RSCAN0TMDF060H RSCAN0.TMDF060.UINT16[H]
-#define RSCAN0TMDF060HL RSCAN0.TMDF060.UINT8[HL]
-#define RSCAN0TMDF060HH RSCAN0.TMDF060.UINT8[HH]
-#define RSCAN0TMDF160 RSCAN0.TMDF160.UINT32
-#define RSCAN0TMDF160L RSCAN0.TMDF160.UINT16[L]
-#define RSCAN0TMDF160LL RSCAN0.TMDF160.UINT8[LL]
-#define RSCAN0TMDF160LH RSCAN0.TMDF160.UINT8[LH]
-#define RSCAN0TMDF160H RSCAN0.TMDF160.UINT16[H]
-#define RSCAN0TMDF160HL RSCAN0.TMDF160.UINT8[HL]
-#define RSCAN0TMDF160HH RSCAN0.TMDF160.UINT8[HH]
-#define RSCAN0TMID61 RSCAN0.TMID61.UINT32
-#define RSCAN0TMID61L RSCAN0.TMID61.UINT16[L]
-#define RSCAN0TMID61LL RSCAN0.TMID61.UINT8[LL]
-#define RSCAN0TMID61LH RSCAN0.TMID61.UINT8[LH]
-#define RSCAN0TMID61H RSCAN0.TMID61.UINT16[H]
-#define RSCAN0TMID61HL RSCAN0.TMID61.UINT8[HL]
-#define RSCAN0TMID61HH RSCAN0.TMID61.UINT8[HH]
-#define RSCAN0TMPTR61 RSCAN0.TMPTR61.UINT32
-#define RSCAN0TMPTR61L RSCAN0.TMPTR61.UINT16[L]
-#define RSCAN0TMPTR61LL RSCAN0.TMPTR61.UINT8[LL]
-#define RSCAN0TMPTR61LH RSCAN0.TMPTR61.UINT8[LH]
-#define RSCAN0TMPTR61H RSCAN0.TMPTR61.UINT16[H]
-#define RSCAN0TMPTR61HL RSCAN0.TMPTR61.UINT8[HL]
-#define RSCAN0TMPTR61HH RSCAN0.TMPTR61.UINT8[HH]
-#define RSCAN0TMDF061 RSCAN0.TMDF061.UINT32
-#define RSCAN0TMDF061L RSCAN0.TMDF061.UINT16[L]
-#define RSCAN0TMDF061LL RSCAN0.TMDF061.UINT8[LL]
-#define RSCAN0TMDF061LH RSCAN0.TMDF061.UINT8[LH]
-#define RSCAN0TMDF061H RSCAN0.TMDF061.UINT16[H]
-#define RSCAN0TMDF061HL RSCAN0.TMDF061.UINT8[HL]
-#define RSCAN0TMDF061HH RSCAN0.TMDF061.UINT8[HH]
-#define RSCAN0TMDF161 RSCAN0.TMDF161.UINT32
-#define RSCAN0TMDF161L RSCAN0.TMDF161.UINT16[L]
-#define RSCAN0TMDF161LL RSCAN0.TMDF161.UINT8[LL]
-#define RSCAN0TMDF161LH RSCAN0.TMDF161.UINT8[LH]
-#define RSCAN0TMDF161H RSCAN0.TMDF161.UINT16[H]
-#define RSCAN0TMDF161HL RSCAN0.TMDF161.UINT8[HL]
-#define RSCAN0TMDF161HH RSCAN0.TMDF161.UINT8[HH]
-#define RSCAN0TMID62 RSCAN0.TMID62.UINT32
-#define RSCAN0TMID62L RSCAN0.TMID62.UINT16[L]
-#define RSCAN0TMID62LL RSCAN0.TMID62.UINT8[LL]
-#define RSCAN0TMID62LH RSCAN0.TMID62.UINT8[LH]
-#define RSCAN0TMID62H RSCAN0.TMID62.UINT16[H]
-#define RSCAN0TMID62HL RSCAN0.TMID62.UINT8[HL]
-#define RSCAN0TMID62HH RSCAN0.TMID62.UINT8[HH]
-#define RSCAN0TMPTR62 RSCAN0.TMPTR62.UINT32
-#define RSCAN0TMPTR62L RSCAN0.TMPTR62.UINT16[L]
-#define RSCAN0TMPTR62LL RSCAN0.TMPTR62.UINT8[LL]
-#define RSCAN0TMPTR62LH RSCAN0.TMPTR62.UINT8[LH]
-#define RSCAN0TMPTR62H RSCAN0.TMPTR62.UINT16[H]
-#define RSCAN0TMPTR62HL RSCAN0.TMPTR62.UINT8[HL]
-#define RSCAN0TMPTR62HH RSCAN0.TMPTR62.UINT8[HH]
-#define RSCAN0TMDF062 RSCAN0.TMDF062.UINT32
-#define RSCAN0TMDF062L RSCAN0.TMDF062.UINT16[L]
-#define RSCAN0TMDF062LL RSCAN0.TMDF062.UINT8[LL]
-#define RSCAN0TMDF062LH RSCAN0.TMDF062.UINT8[LH]
-#define RSCAN0TMDF062H RSCAN0.TMDF062.UINT16[H]
-#define RSCAN0TMDF062HL RSCAN0.TMDF062.UINT8[HL]
-#define RSCAN0TMDF062HH RSCAN0.TMDF062.UINT8[HH]
-#define RSCAN0TMDF162 RSCAN0.TMDF162.UINT32
-#define RSCAN0TMDF162L RSCAN0.TMDF162.UINT16[L]
-#define RSCAN0TMDF162LL RSCAN0.TMDF162.UINT8[LL]
-#define RSCAN0TMDF162LH RSCAN0.TMDF162.UINT8[LH]
-#define RSCAN0TMDF162H RSCAN0.TMDF162.UINT16[H]
-#define RSCAN0TMDF162HL RSCAN0.TMDF162.UINT8[HL]
-#define RSCAN0TMDF162HH RSCAN0.TMDF162.UINT8[HH]
-#define RSCAN0TMID63 RSCAN0.TMID63.UINT32
-#define RSCAN0TMID63L RSCAN0.TMID63.UINT16[L]
-#define RSCAN0TMID63LL RSCAN0.TMID63.UINT8[LL]
-#define RSCAN0TMID63LH RSCAN0.TMID63.UINT8[LH]
-#define RSCAN0TMID63H RSCAN0.TMID63.UINT16[H]
-#define RSCAN0TMID63HL RSCAN0.TMID63.UINT8[HL]
-#define RSCAN0TMID63HH RSCAN0.TMID63.UINT8[HH]
-#define RSCAN0TMPTR63 RSCAN0.TMPTR63.UINT32
-#define RSCAN0TMPTR63L RSCAN0.TMPTR63.UINT16[L]
-#define RSCAN0TMPTR63LL RSCAN0.TMPTR63.UINT8[LL]
-#define RSCAN0TMPTR63LH RSCAN0.TMPTR63.UINT8[LH]
-#define RSCAN0TMPTR63H RSCAN0.TMPTR63.UINT16[H]
-#define RSCAN0TMPTR63HL RSCAN0.TMPTR63.UINT8[HL]
-#define RSCAN0TMPTR63HH RSCAN0.TMPTR63.UINT8[HH]
-#define RSCAN0TMDF063 RSCAN0.TMDF063.UINT32
-#define RSCAN0TMDF063L RSCAN0.TMDF063.UINT16[L]
-#define RSCAN0TMDF063LL RSCAN0.TMDF063.UINT8[LL]
-#define RSCAN0TMDF063LH RSCAN0.TMDF063.UINT8[LH]
-#define RSCAN0TMDF063H RSCAN0.TMDF063.UINT16[H]
-#define RSCAN0TMDF063HL RSCAN0.TMDF063.UINT8[HL]
-#define RSCAN0TMDF063HH RSCAN0.TMDF063.UINT8[HH]
-#define RSCAN0TMDF163 RSCAN0.TMDF163.UINT32
-#define RSCAN0TMDF163L RSCAN0.TMDF163.UINT16[L]
-#define RSCAN0TMDF163LL RSCAN0.TMDF163.UINT8[LL]
-#define RSCAN0TMDF163LH RSCAN0.TMDF163.UINT8[LH]
-#define RSCAN0TMDF163H RSCAN0.TMDF163.UINT16[H]
-#define RSCAN0TMDF163HL RSCAN0.TMDF163.UINT8[HL]
-#define RSCAN0TMDF163HH RSCAN0.TMDF163.UINT8[HH]
-#define RSCAN0TMID64 RSCAN0.TMID64.UINT32
-#define RSCAN0TMID64L RSCAN0.TMID64.UINT16[L]
-#define RSCAN0TMID64LL RSCAN0.TMID64.UINT8[LL]
-#define RSCAN0TMID64LH RSCAN0.TMID64.UINT8[LH]
-#define RSCAN0TMID64H RSCAN0.TMID64.UINT16[H]
-#define RSCAN0TMID64HL RSCAN0.TMID64.UINT8[HL]
-#define RSCAN0TMID64HH RSCAN0.TMID64.UINT8[HH]
-#define RSCAN0TMPTR64 RSCAN0.TMPTR64.UINT32
-#define RSCAN0TMPTR64L RSCAN0.TMPTR64.UINT16[L]
-#define RSCAN0TMPTR64LL RSCAN0.TMPTR64.UINT8[LL]
-#define RSCAN0TMPTR64LH RSCAN0.TMPTR64.UINT8[LH]
-#define RSCAN0TMPTR64H RSCAN0.TMPTR64.UINT16[H]
-#define RSCAN0TMPTR64HL RSCAN0.TMPTR64.UINT8[HL]
-#define RSCAN0TMPTR64HH RSCAN0.TMPTR64.UINT8[HH]
-#define RSCAN0TMDF064 RSCAN0.TMDF064.UINT32
-#define RSCAN0TMDF064L RSCAN0.TMDF064.UINT16[L]
-#define RSCAN0TMDF064LL RSCAN0.TMDF064.UINT8[LL]
-#define RSCAN0TMDF064LH RSCAN0.TMDF064.UINT8[LH]
-#define RSCAN0TMDF064H RSCAN0.TMDF064.UINT16[H]
-#define RSCAN0TMDF064HL RSCAN0.TMDF064.UINT8[HL]
-#define RSCAN0TMDF064HH RSCAN0.TMDF064.UINT8[HH]
-#define RSCAN0TMDF164 RSCAN0.TMDF164.UINT32
-#define RSCAN0TMDF164L RSCAN0.TMDF164.UINT16[L]
-#define RSCAN0TMDF164LL RSCAN0.TMDF164.UINT8[LL]
-#define RSCAN0TMDF164LH RSCAN0.TMDF164.UINT8[LH]
-#define RSCAN0TMDF164H RSCAN0.TMDF164.UINT16[H]
-#define RSCAN0TMDF164HL RSCAN0.TMDF164.UINT8[HL]
-#define RSCAN0TMDF164HH RSCAN0.TMDF164.UINT8[HH]
-#define RSCAN0TMID65 RSCAN0.TMID65.UINT32
-#define RSCAN0TMID65L RSCAN0.TMID65.UINT16[L]
-#define RSCAN0TMID65LL RSCAN0.TMID65.UINT8[LL]
-#define RSCAN0TMID65LH RSCAN0.TMID65.UINT8[LH]
-#define RSCAN0TMID65H RSCAN0.TMID65.UINT16[H]
-#define RSCAN0TMID65HL RSCAN0.TMID65.UINT8[HL]
-#define RSCAN0TMID65HH RSCAN0.TMID65.UINT8[HH]
-#define RSCAN0TMPTR65 RSCAN0.TMPTR65.UINT32
-#define RSCAN0TMPTR65L RSCAN0.TMPTR65.UINT16[L]
-#define RSCAN0TMPTR65LL RSCAN0.TMPTR65.UINT8[LL]
-#define RSCAN0TMPTR65LH RSCAN0.TMPTR65.UINT8[LH]
-#define RSCAN0TMPTR65H RSCAN0.TMPTR65.UINT16[H]
-#define RSCAN0TMPTR65HL RSCAN0.TMPTR65.UINT8[HL]
-#define RSCAN0TMPTR65HH RSCAN0.TMPTR65.UINT8[HH]
-#define RSCAN0TMDF065 RSCAN0.TMDF065.UINT32
-#define RSCAN0TMDF065L RSCAN0.TMDF065.UINT16[L]
-#define RSCAN0TMDF065LL RSCAN0.TMDF065.UINT8[LL]
-#define RSCAN0TMDF065LH RSCAN0.TMDF065.UINT8[LH]
-#define RSCAN0TMDF065H RSCAN0.TMDF065.UINT16[H]
-#define RSCAN0TMDF065HL RSCAN0.TMDF065.UINT8[HL]
-#define RSCAN0TMDF065HH RSCAN0.TMDF065.UINT8[HH]
-#define RSCAN0TMDF165 RSCAN0.TMDF165.UINT32
-#define RSCAN0TMDF165L RSCAN0.TMDF165.UINT16[L]
-#define RSCAN0TMDF165LL RSCAN0.TMDF165.UINT8[LL]
-#define RSCAN0TMDF165LH RSCAN0.TMDF165.UINT8[LH]
-#define RSCAN0TMDF165H RSCAN0.TMDF165.UINT16[H]
-#define RSCAN0TMDF165HL RSCAN0.TMDF165.UINT8[HL]
-#define RSCAN0TMDF165HH RSCAN0.TMDF165.UINT8[HH]
-#define RSCAN0TMID66 RSCAN0.TMID66.UINT32
-#define RSCAN0TMID66L RSCAN0.TMID66.UINT16[L]
-#define RSCAN0TMID66LL RSCAN0.TMID66.UINT8[LL]
-#define RSCAN0TMID66LH RSCAN0.TMID66.UINT8[LH]
-#define RSCAN0TMID66H RSCAN0.TMID66.UINT16[H]
-#define RSCAN0TMID66HL RSCAN0.TMID66.UINT8[HL]
-#define RSCAN0TMID66HH RSCAN0.TMID66.UINT8[HH]
-#define RSCAN0TMPTR66 RSCAN0.TMPTR66.UINT32
-#define RSCAN0TMPTR66L RSCAN0.TMPTR66.UINT16[L]
-#define RSCAN0TMPTR66LL RSCAN0.TMPTR66.UINT8[LL]
-#define RSCAN0TMPTR66LH RSCAN0.TMPTR66.UINT8[LH]
-#define RSCAN0TMPTR66H RSCAN0.TMPTR66.UINT16[H]
-#define RSCAN0TMPTR66HL RSCAN0.TMPTR66.UINT8[HL]
-#define RSCAN0TMPTR66HH RSCAN0.TMPTR66.UINT8[HH]
-#define RSCAN0TMDF066 RSCAN0.TMDF066.UINT32
-#define RSCAN0TMDF066L RSCAN0.TMDF066.UINT16[L]
-#define RSCAN0TMDF066LL RSCAN0.TMDF066.UINT8[LL]
-#define RSCAN0TMDF066LH RSCAN0.TMDF066.UINT8[LH]
-#define RSCAN0TMDF066H RSCAN0.TMDF066.UINT16[H]
-#define RSCAN0TMDF066HL RSCAN0.TMDF066.UINT8[HL]
-#define RSCAN0TMDF066HH RSCAN0.TMDF066.UINT8[HH]
-#define RSCAN0TMDF166 RSCAN0.TMDF166.UINT32
-#define RSCAN0TMDF166L RSCAN0.TMDF166.UINT16[L]
-#define RSCAN0TMDF166LL RSCAN0.TMDF166.UINT8[LL]
-#define RSCAN0TMDF166LH RSCAN0.TMDF166.UINT8[LH]
-#define RSCAN0TMDF166H RSCAN0.TMDF166.UINT16[H]
-#define RSCAN0TMDF166HL RSCAN0.TMDF166.UINT8[HL]
-#define RSCAN0TMDF166HH RSCAN0.TMDF166.UINT8[HH]
-#define RSCAN0TMID67 RSCAN0.TMID67.UINT32
-#define RSCAN0TMID67L RSCAN0.TMID67.UINT16[L]
-#define RSCAN0TMID67LL RSCAN0.TMID67.UINT8[LL]
-#define RSCAN0TMID67LH RSCAN0.TMID67.UINT8[LH]
-#define RSCAN0TMID67H RSCAN0.TMID67.UINT16[H]
-#define RSCAN0TMID67HL RSCAN0.TMID67.UINT8[HL]
-#define RSCAN0TMID67HH RSCAN0.TMID67.UINT8[HH]
-#define RSCAN0TMPTR67 RSCAN0.TMPTR67.UINT32
-#define RSCAN0TMPTR67L RSCAN0.TMPTR67.UINT16[L]
-#define RSCAN0TMPTR67LL RSCAN0.TMPTR67.UINT8[LL]
-#define RSCAN0TMPTR67LH RSCAN0.TMPTR67.UINT8[LH]
-#define RSCAN0TMPTR67H RSCAN0.TMPTR67.UINT16[H]
-#define RSCAN0TMPTR67HL RSCAN0.TMPTR67.UINT8[HL]
-#define RSCAN0TMPTR67HH RSCAN0.TMPTR67.UINT8[HH]
-#define RSCAN0TMDF067 RSCAN0.TMDF067.UINT32
-#define RSCAN0TMDF067L RSCAN0.TMDF067.UINT16[L]
-#define RSCAN0TMDF067LL RSCAN0.TMDF067.UINT8[LL]
-#define RSCAN0TMDF067LH RSCAN0.TMDF067.UINT8[LH]
-#define RSCAN0TMDF067H RSCAN0.TMDF067.UINT16[H]
-#define RSCAN0TMDF067HL RSCAN0.TMDF067.UINT8[HL]
-#define RSCAN0TMDF067HH RSCAN0.TMDF067.UINT8[HH]
-#define RSCAN0TMDF167 RSCAN0.TMDF167.UINT32
-#define RSCAN0TMDF167L RSCAN0.TMDF167.UINT16[L]
-#define RSCAN0TMDF167LL RSCAN0.TMDF167.UINT8[LL]
-#define RSCAN0TMDF167LH RSCAN0.TMDF167.UINT8[LH]
-#define RSCAN0TMDF167H RSCAN0.TMDF167.UINT16[H]
-#define RSCAN0TMDF167HL RSCAN0.TMDF167.UINT8[HL]
-#define RSCAN0TMDF167HH RSCAN0.TMDF167.UINT8[HH]
-#define RSCAN0TMID68 RSCAN0.TMID68.UINT32
-#define RSCAN0TMID68L RSCAN0.TMID68.UINT16[L]
-#define RSCAN0TMID68LL RSCAN0.TMID68.UINT8[LL]
-#define RSCAN0TMID68LH RSCAN0.TMID68.UINT8[LH]
-#define RSCAN0TMID68H RSCAN0.TMID68.UINT16[H]
-#define RSCAN0TMID68HL RSCAN0.TMID68.UINT8[HL]
-#define RSCAN0TMID68HH RSCAN0.TMID68.UINT8[HH]
-#define RSCAN0TMPTR68 RSCAN0.TMPTR68.UINT32
-#define RSCAN0TMPTR68L RSCAN0.TMPTR68.UINT16[L]
-#define RSCAN0TMPTR68LL RSCAN0.TMPTR68.UINT8[LL]
-#define RSCAN0TMPTR68LH RSCAN0.TMPTR68.UINT8[LH]
-#define RSCAN0TMPTR68H RSCAN0.TMPTR68.UINT16[H]
-#define RSCAN0TMPTR68HL RSCAN0.TMPTR68.UINT8[HL]
-#define RSCAN0TMPTR68HH RSCAN0.TMPTR68.UINT8[HH]
-#define RSCAN0TMDF068 RSCAN0.TMDF068.UINT32
-#define RSCAN0TMDF068L RSCAN0.TMDF068.UINT16[L]
-#define RSCAN0TMDF068LL RSCAN0.TMDF068.UINT8[LL]
-#define RSCAN0TMDF068LH RSCAN0.TMDF068.UINT8[LH]
-#define RSCAN0TMDF068H RSCAN0.TMDF068.UINT16[H]
-#define RSCAN0TMDF068HL RSCAN0.TMDF068.UINT8[HL]
-#define RSCAN0TMDF068HH RSCAN0.TMDF068.UINT8[HH]
-#define RSCAN0TMDF168 RSCAN0.TMDF168.UINT32
-#define RSCAN0TMDF168L RSCAN0.TMDF168.UINT16[L]
-#define RSCAN0TMDF168LL RSCAN0.TMDF168.UINT8[LL]
-#define RSCAN0TMDF168LH RSCAN0.TMDF168.UINT8[LH]
-#define RSCAN0TMDF168H RSCAN0.TMDF168.UINT16[H]
-#define RSCAN0TMDF168HL RSCAN0.TMDF168.UINT8[HL]
-#define RSCAN0TMDF168HH RSCAN0.TMDF168.UINT8[HH]
-#define RSCAN0TMID69 RSCAN0.TMID69.UINT32
-#define RSCAN0TMID69L RSCAN0.TMID69.UINT16[L]
-#define RSCAN0TMID69LL RSCAN0.TMID69.UINT8[LL]
-#define RSCAN0TMID69LH RSCAN0.TMID69.UINT8[LH]
-#define RSCAN0TMID69H RSCAN0.TMID69.UINT16[H]
-#define RSCAN0TMID69HL RSCAN0.TMID69.UINT8[HL]
-#define RSCAN0TMID69HH RSCAN0.TMID69.UINT8[HH]
-#define RSCAN0TMPTR69 RSCAN0.TMPTR69.UINT32
-#define RSCAN0TMPTR69L RSCAN0.TMPTR69.UINT16[L]
-#define RSCAN0TMPTR69LL RSCAN0.TMPTR69.UINT8[LL]
-#define RSCAN0TMPTR69LH RSCAN0.TMPTR69.UINT8[LH]
-#define RSCAN0TMPTR69H RSCAN0.TMPTR69.UINT16[H]
-#define RSCAN0TMPTR69HL RSCAN0.TMPTR69.UINT8[HL]
-#define RSCAN0TMPTR69HH RSCAN0.TMPTR69.UINT8[HH]
-#define RSCAN0TMDF069 RSCAN0.TMDF069.UINT32
-#define RSCAN0TMDF069L RSCAN0.TMDF069.UINT16[L]
-#define RSCAN0TMDF069LL RSCAN0.TMDF069.UINT8[LL]
-#define RSCAN0TMDF069LH RSCAN0.TMDF069.UINT8[LH]
-#define RSCAN0TMDF069H RSCAN0.TMDF069.UINT16[H]
-#define RSCAN0TMDF069HL RSCAN0.TMDF069.UINT8[HL]
-#define RSCAN0TMDF069HH RSCAN0.TMDF069.UINT8[HH]
-#define RSCAN0TMDF169 RSCAN0.TMDF169.UINT32
-#define RSCAN0TMDF169L RSCAN0.TMDF169.UINT16[L]
-#define RSCAN0TMDF169LL RSCAN0.TMDF169.UINT8[LL]
-#define RSCAN0TMDF169LH RSCAN0.TMDF169.UINT8[LH]
-#define RSCAN0TMDF169H RSCAN0.TMDF169.UINT16[H]
-#define RSCAN0TMDF169HL RSCAN0.TMDF169.UINT8[HL]
-#define RSCAN0TMDF169HH RSCAN0.TMDF169.UINT8[HH]
-#define RSCAN0TMID70 RSCAN0.TMID70.UINT32
-#define RSCAN0TMID70L RSCAN0.TMID70.UINT16[L]
-#define RSCAN0TMID70LL RSCAN0.TMID70.UINT8[LL]
-#define RSCAN0TMID70LH RSCAN0.TMID70.UINT8[LH]
-#define RSCAN0TMID70H RSCAN0.TMID70.UINT16[H]
-#define RSCAN0TMID70HL RSCAN0.TMID70.UINT8[HL]
-#define RSCAN0TMID70HH RSCAN0.TMID70.UINT8[HH]
-#define RSCAN0TMPTR70 RSCAN0.TMPTR70.UINT32
-#define RSCAN0TMPTR70L RSCAN0.TMPTR70.UINT16[L]
-#define RSCAN0TMPTR70LL RSCAN0.TMPTR70.UINT8[LL]
-#define RSCAN0TMPTR70LH RSCAN0.TMPTR70.UINT8[LH]
-#define RSCAN0TMPTR70H RSCAN0.TMPTR70.UINT16[H]
-#define RSCAN0TMPTR70HL RSCAN0.TMPTR70.UINT8[HL]
-#define RSCAN0TMPTR70HH RSCAN0.TMPTR70.UINT8[HH]
-#define RSCAN0TMDF070 RSCAN0.TMDF070.UINT32
-#define RSCAN0TMDF070L RSCAN0.TMDF070.UINT16[L]
-#define RSCAN0TMDF070LL RSCAN0.TMDF070.UINT8[LL]
-#define RSCAN0TMDF070LH RSCAN0.TMDF070.UINT8[LH]
-#define RSCAN0TMDF070H RSCAN0.TMDF070.UINT16[H]
-#define RSCAN0TMDF070HL RSCAN0.TMDF070.UINT8[HL]
-#define RSCAN0TMDF070HH RSCAN0.TMDF070.UINT8[HH]
-#define RSCAN0TMDF170 RSCAN0.TMDF170.UINT32
-#define RSCAN0TMDF170L RSCAN0.TMDF170.UINT16[L]
-#define RSCAN0TMDF170LL RSCAN0.TMDF170.UINT8[LL]
-#define RSCAN0TMDF170LH RSCAN0.TMDF170.UINT8[LH]
-#define RSCAN0TMDF170H RSCAN0.TMDF170.UINT16[H]
-#define RSCAN0TMDF170HL RSCAN0.TMDF170.UINT8[HL]
-#define RSCAN0TMDF170HH RSCAN0.TMDF170.UINT8[HH]
-#define RSCAN0TMID71 RSCAN0.TMID71.UINT32
-#define RSCAN0TMID71L RSCAN0.TMID71.UINT16[L]
-#define RSCAN0TMID71LL RSCAN0.TMID71.UINT8[LL]
-#define RSCAN0TMID71LH RSCAN0.TMID71.UINT8[LH]
-#define RSCAN0TMID71H RSCAN0.TMID71.UINT16[H]
-#define RSCAN0TMID71HL RSCAN0.TMID71.UINT8[HL]
-#define RSCAN0TMID71HH RSCAN0.TMID71.UINT8[HH]
-#define RSCAN0TMPTR71 RSCAN0.TMPTR71.UINT32
-#define RSCAN0TMPTR71L RSCAN0.TMPTR71.UINT16[L]
-#define RSCAN0TMPTR71LL RSCAN0.TMPTR71.UINT8[LL]
-#define RSCAN0TMPTR71LH RSCAN0.TMPTR71.UINT8[LH]
-#define RSCAN0TMPTR71H RSCAN0.TMPTR71.UINT16[H]
-#define RSCAN0TMPTR71HL RSCAN0.TMPTR71.UINT8[HL]
-#define RSCAN0TMPTR71HH RSCAN0.TMPTR71.UINT8[HH]
-#define RSCAN0TMDF071 RSCAN0.TMDF071.UINT32
-#define RSCAN0TMDF071L RSCAN0.TMDF071.UINT16[L]
-#define RSCAN0TMDF071LL RSCAN0.TMDF071.UINT8[LL]
-#define RSCAN0TMDF071LH RSCAN0.TMDF071.UINT8[LH]
-#define RSCAN0TMDF071H RSCAN0.TMDF071.UINT16[H]
-#define RSCAN0TMDF071HL RSCAN0.TMDF071.UINT8[HL]
-#define RSCAN0TMDF071HH RSCAN0.TMDF071.UINT8[HH]
-#define RSCAN0TMDF171 RSCAN0.TMDF171.UINT32
-#define RSCAN0TMDF171L RSCAN0.TMDF171.UINT16[L]
-#define RSCAN0TMDF171LL RSCAN0.TMDF171.UINT8[LL]
-#define RSCAN0TMDF171LH RSCAN0.TMDF171.UINT8[LH]
-#define RSCAN0TMDF171H RSCAN0.TMDF171.UINT16[H]
-#define RSCAN0TMDF171HL RSCAN0.TMDF171.UINT8[HL]
-#define RSCAN0TMDF171HH RSCAN0.TMDF171.UINT8[HH]
-#define RSCAN0TMID72 RSCAN0.TMID72.UINT32
-#define RSCAN0TMID72L RSCAN0.TMID72.UINT16[L]
-#define RSCAN0TMID72LL RSCAN0.TMID72.UINT8[LL]
-#define RSCAN0TMID72LH RSCAN0.TMID72.UINT8[LH]
-#define RSCAN0TMID72H RSCAN0.TMID72.UINT16[H]
-#define RSCAN0TMID72HL RSCAN0.TMID72.UINT8[HL]
-#define RSCAN0TMID72HH RSCAN0.TMID72.UINT8[HH]
-#define RSCAN0TMPTR72 RSCAN0.TMPTR72.UINT32
-#define RSCAN0TMPTR72L RSCAN0.TMPTR72.UINT16[L]
-#define RSCAN0TMPTR72LL RSCAN0.TMPTR72.UINT8[LL]
-#define RSCAN0TMPTR72LH RSCAN0.TMPTR72.UINT8[LH]
-#define RSCAN0TMPTR72H RSCAN0.TMPTR72.UINT16[H]
-#define RSCAN0TMPTR72HL RSCAN0.TMPTR72.UINT8[HL]
-#define RSCAN0TMPTR72HH RSCAN0.TMPTR72.UINT8[HH]
-#define RSCAN0TMDF072 RSCAN0.TMDF072.UINT32
-#define RSCAN0TMDF072L RSCAN0.TMDF072.UINT16[L]
-#define RSCAN0TMDF072LL RSCAN0.TMDF072.UINT8[LL]
-#define RSCAN0TMDF072LH RSCAN0.TMDF072.UINT8[LH]
-#define RSCAN0TMDF072H RSCAN0.TMDF072.UINT16[H]
-#define RSCAN0TMDF072HL RSCAN0.TMDF072.UINT8[HL]
-#define RSCAN0TMDF072HH RSCAN0.TMDF072.UINT8[HH]
-#define RSCAN0TMDF172 RSCAN0.TMDF172.UINT32
-#define RSCAN0TMDF172L RSCAN0.TMDF172.UINT16[L]
-#define RSCAN0TMDF172LL RSCAN0.TMDF172.UINT8[LL]
-#define RSCAN0TMDF172LH RSCAN0.TMDF172.UINT8[LH]
-#define RSCAN0TMDF172H RSCAN0.TMDF172.UINT16[H]
-#define RSCAN0TMDF172HL RSCAN0.TMDF172.UINT8[HL]
-#define RSCAN0TMDF172HH RSCAN0.TMDF172.UINT8[HH]
-#define RSCAN0TMID73 RSCAN0.TMID73.UINT32
-#define RSCAN0TMID73L RSCAN0.TMID73.UINT16[L]
-#define RSCAN0TMID73LL RSCAN0.TMID73.UINT8[LL]
-#define RSCAN0TMID73LH RSCAN0.TMID73.UINT8[LH]
-#define RSCAN0TMID73H RSCAN0.TMID73.UINT16[H]
-#define RSCAN0TMID73HL RSCAN0.TMID73.UINT8[HL]
-#define RSCAN0TMID73HH RSCAN0.TMID73.UINT8[HH]
-#define RSCAN0TMPTR73 RSCAN0.TMPTR73.UINT32
-#define RSCAN0TMPTR73L RSCAN0.TMPTR73.UINT16[L]
-#define RSCAN0TMPTR73LL RSCAN0.TMPTR73.UINT8[LL]
-#define RSCAN0TMPTR73LH RSCAN0.TMPTR73.UINT8[LH]
-#define RSCAN0TMPTR73H RSCAN0.TMPTR73.UINT16[H]
-#define RSCAN0TMPTR73HL RSCAN0.TMPTR73.UINT8[HL]
-#define RSCAN0TMPTR73HH RSCAN0.TMPTR73.UINT8[HH]
-#define RSCAN0TMDF073 RSCAN0.TMDF073.UINT32
-#define RSCAN0TMDF073L RSCAN0.TMDF073.UINT16[L]
-#define RSCAN0TMDF073LL RSCAN0.TMDF073.UINT8[LL]
-#define RSCAN0TMDF073LH RSCAN0.TMDF073.UINT8[LH]
-#define RSCAN0TMDF073H RSCAN0.TMDF073.UINT16[H]
-#define RSCAN0TMDF073HL RSCAN0.TMDF073.UINT8[HL]
-#define RSCAN0TMDF073HH RSCAN0.TMDF073.UINT8[HH]
-#define RSCAN0TMDF173 RSCAN0.TMDF173.UINT32
-#define RSCAN0TMDF173L RSCAN0.TMDF173.UINT16[L]
-#define RSCAN0TMDF173LL RSCAN0.TMDF173.UINT8[LL]
-#define RSCAN0TMDF173LH RSCAN0.TMDF173.UINT8[LH]
-#define RSCAN0TMDF173H RSCAN0.TMDF173.UINT16[H]
-#define RSCAN0TMDF173HL RSCAN0.TMDF173.UINT8[HL]
-#define RSCAN0TMDF173HH RSCAN0.TMDF173.UINT8[HH]
-#define RSCAN0TMID74 RSCAN0.TMID74.UINT32
-#define RSCAN0TMID74L RSCAN0.TMID74.UINT16[L]
-#define RSCAN0TMID74LL RSCAN0.TMID74.UINT8[LL]
-#define RSCAN0TMID74LH RSCAN0.TMID74.UINT8[LH]
-#define RSCAN0TMID74H RSCAN0.TMID74.UINT16[H]
-#define RSCAN0TMID74HL RSCAN0.TMID74.UINT8[HL]
-#define RSCAN0TMID74HH RSCAN0.TMID74.UINT8[HH]
-#define RSCAN0TMPTR74 RSCAN0.TMPTR74.UINT32
-#define RSCAN0TMPTR74L RSCAN0.TMPTR74.UINT16[L]
-#define RSCAN0TMPTR74LL RSCAN0.TMPTR74.UINT8[LL]
-#define RSCAN0TMPTR74LH RSCAN0.TMPTR74.UINT8[LH]
-#define RSCAN0TMPTR74H RSCAN0.TMPTR74.UINT16[H]
-#define RSCAN0TMPTR74HL RSCAN0.TMPTR74.UINT8[HL]
-#define RSCAN0TMPTR74HH RSCAN0.TMPTR74.UINT8[HH]
-#define RSCAN0TMDF074 RSCAN0.TMDF074.UINT32
-#define RSCAN0TMDF074L RSCAN0.TMDF074.UINT16[L]
-#define RSCAN0TMDF074LL RSCAN0.TMDF074.UINT8[LL]
-#define RSCAN0TMDF074LH RSCAN0.TMDF074.UINT8[LH]
-#define RSCAN0TMDF074H RSCAN0.TMDF074.UINT16[H]
-#define RSCAN0TMDF074HL RSCAN0.TMDF074.UINT8[HL]
-#define RSCAN0TMDF074HH RSCAN0.TMDF074.UINT8[HH]
-#define RSCAN0TMDF174 RSCAN0.TMDF174.UINT32
-#define RSCAN0TMDF174L RSCAN0.TMDF174.UINT16[L]
-#define RSCAN0TMDF174LL RSCAN0.TMDF174.UINT8[LL]
-#define RSCAN0TMDF174LH RSCAN0.TMDF174.UINT8[LH]
-#define RSCAN0TMDF174H RSCAN0.TMDF174.UINT16[H]
-#define RSCAN0TMDF174HL RSCAN0.TMDF174.UINT8[HL]
-#define RSCAN0TMDF174HH RSCAN0.TMDF174.UINT8[HH]
-#define RSCAN0TMID75 RSCAN0.TMID75.UINT32
-#define RSCAN0TMID75L RSCAN0.TMID75.UINT16[L]
-#define RSCAN0TMID75LL RSCAN0.TMID75.UINT8[LL]
-#define RSCAN0TMID75LH RSCAN0.TMID75.UINT8[LH]
-#define RSCAN0TMID75H RSCAN0.TMID75.UINT16[H]
-#define RSCAN0TMID75HL RSCAN0.TMID75.UINT8[HL]
-#define RSCAN0TMID75HH RSCAN0.TMID75.UINT8[HH]
-#define RSCAN0TMPTR75 RSCAN0.TMPTR75.UINT32
-#define RSCAN0TMPTR75L RSCAN0.TMPTR75.UINT16[L]
-#define RSCAN0TMPTR75LL RSCAN0.TMPTR75.UINT8[LL]
-#define RSCAN0TMPTR75LH RSCAN0.TMPTR75.UINT8[LH]
-#define RSCAN0TMPTR75H RSCAN0.TMPTR75.UINT16[H]
-#define RSCAN0TMPTR75HL RSCAN0.TMPTR75.UINT8[HL]
-#define RSCAN0TMPTR75HH RSCAN0.TMPTR75.UINT8[HH]
-#define RSCAN0TMDF075 RSCAN0.TMDF075.UINT32
-#define RSCAN0TMDF075L RSCAN0.TMDF075.UINT16[L]
-#define RSCAN0TMDF075LL RSCAN0.TMDF075.UINT8[LL]
-#define RSCAN0TMDF075LH RSCAN0.TMDF075.UINT8[LH]
-#define RSCAN0TMDF075H RSCAN0.TMDF075.UINT16[H]
-#define RSCAN0TMDF075HL RSCAN0.TMDF075.UINT8[HL]
-#define RSCAN0TMDF075HH RSCAN0.TMDF075.UINT8[HH]
-#define RSCAN0TMDF175 RSCAN0.TMDF175.UINT32
-#define RSCAN0TMDF175L RSCAN0.TMDF175.UINT16[L]
-#define RSCAN0TMDF175LL RSCAN0.TMDF175.UINT8[LL]
-#define RSCAN0TMDF175LH RSCAN0.TMDF175.UINT8[LH]
-#define RSCAN0TMDF175H RSCAN0.TMDF175.UINT16[H]
-#define RSCAN0TMDF175HL RSCAN0.TMDF175.UINT8[HL]
-#define RSCAN0TMDF175HH RSCAN0.TMDF175.UINT8[HH]
-#define RSCAN0TMID76 RSCAN0.TMID76.UINT32
-#define RSCAN0TMID76L RSCAN0.TMID76.UINT16[L]
-#define RSCAN0TMID76LL RSCAN0.TMID76.UINT8[LL]
-#define RSCAN0TMID76LH RSCAN0.TMID76.UINT8[LH]
-#define RSCAN0TMID76H RSCAN0.TMID76.UINT16[H]
-#define RSCAN0TMID76HL RSCAN0.TMID76.UINT8[HL]
-#define RSCAN0TMID76HH RSCAN0.TMID76.UINT8[HH]
-#define RSCAN0TMPTR76 RSCAN0.TMPTR76.UINT32
-#define RSCAN0TMPTR76L RSCAN0.TMPTR76.UINT16[L]
-#define RSCAN0TMPTR76LL RSCAN0.TMPTR76.UINT8[LL]
-#define RSCAN0TMPTR76LH RSCAN0.TMPTR76.UINT8[LH]
-#define RSCAN0TMPTR76H RSCAN0.TMPTR76.UINT16[H]
-#define RSCAN0TMPTR76HL RSCAN0.TMPTR76.UINT8[HL]
-#define RSCAN0TMPTR76HH RSCAN0.TMPTR76.UINT8[HH]
-#define RSCAN0TMDF076 RSCAN0.TMDF076.UINT32
-#define RSCAN0TMDF076L RSCAN0.TMDF076.UINT16[L]
-#define RSCAN0TMDF076LL RSCAN0.TMDF076.UINT8[LL]
-#define RSCAN0TMDF076LH RSCAN0.TMDF076.UINT8[LH]
-#define RSCAN0TMDF076H RSCAN0.TMDF076.UINT16[H]
-#define RSCAN0TMDF076HL RSCAN0.TMDF076.UINT8[HL]
-#define RSCAN0TMDF076HH RSCAN0.TMDF076.UINT8[HH]
-#define RSCAN0TMDF176 RSCAN0.TMDF176.UINT32
-#define RSCAN0TMDF176L RSCAN0.TMDF176.UINT16[L]
-#define RSCAN0TMDF176LL RSCAN0.TMDF176.UINT8[LL]
-#define RSCAN0TMDF176LH RSCAN0.TMDF176.UINT8[LH]
-#define RSCAN0TMDF176H RSCAN0.TMDF176.UINT16[H]
-#define RSCAN0TMDF176HL RSCAN0.TMDF176.UINT8[HL]
-#define RSCAN0TMDF176HH RSCAN0.TMDF176.UINT8[HH]
-#define RSCAN0TMID77 RSCAN0.TMID77.UINT32
-#define RSCAN0TMID77L RSCAN0.TMID77.UINT16[L]
-#define RSCAN0TMID77LL RSCAN0.TMID77.UINT8[LL]
-#define RSCAN0TMID77LH RSCAN0.TMID77.UINT8[LH]
-#define RSCAN0TMID77H RSCAN0.TMID77.UINT16[H]
-#define RSCAN0TMID77HL RSCAN0.TMID77.UINT8[HL]
-#define RSCAN0TMID77HH RSCAN0.TMID77.UINT8[HH]
-#define RSCAN0TMPTR77 RSCAN0.TMPTR77.UINT32
-#define RSCAN0TMPTR77L RSCAN0.TMPTR77.UINT16[L]
-#define RSCAN0TMPTR77LL RSCAN0.TMPTR77.UINT8[LL]
-#define RSCAN0TMPTR77LH RSCAN0.TMPTR77.UINT8[LH]
-#define RSCAN0TMPTR77H RSCAN0.TMPTR77.UINT16[H]
-#define RSCAN0TMPTR77HL RSCAN0.TMPTR77.UINT8[HL]
-#define RSCAN0TMPTR77HH RSCAN0.TMPTR77.UINT8[HH]
-#define RSCAN0TMDF077 RSCAN0.TMDF077.UINT32
-#define RSCAN0TMDF077L RSCAN0.TMDF077.UINT16[L]
-#define RSCAN0TMDF077LL RSCAN0.TMDF077.UINT8[LL]
-#define RSCAN0TMDF077LH RSCAN0.TMDF077.UINT8[LH]
-#define RSCAN0TMDF077H RSCAN0.TMDF077.UINT16[H]
-#define RSCAN0TMDF077HL RSCAN0.TMDF077.UINT8[HL]
-#define RSCAN0TMDF077HH RSCAN0.TMDF077.UINT8[HH]
-#define RSCAN0TMDF177 RSCAN0.TMDF177.UINT32
-#define RSCAN0TMDF177L RSCAN0.TMDF177.UINT16[L]
-#define RSCAN0TMDF177LL RSCAN0.TMDF177.UINT8[LL]
-#define RSCAN0TMDF177LH RSCAN0.TMDF177.UINT8[LH]
-#define RSCAN0TMDF177H RSCAN0.TMDF177.UINT16[H]
-#define RSCAN0TMDF177HL RSCAN0.TMDF177.UINT8[HL]
-#define RSCAN0TMDF177HH RSCAN0.TMDF177.UINT8[HH]
-#define RSCAN0TMID78 RSCAN0.TMID78.UINT32
-#define RSCAN0TMID78L RSCAN0.TMID78.UINT16[L]
-#define RSCAN0TMID78LL RSCAN0.TMID78.UINT8[LL]
-#define RSCAN0TMID78LH RSCAN0.TMID78.UINT8[LH]
-#define RSCAN0TMID78H RSCAN0.TMID78.UINT16[H]
-#define RSCAN0TMID78HL RSCAN0.TMID78.UINT8[HL]
-#define RSCAN0TMID78HH RSCAN0.TMID78.UINT8[HH]
-#define RSCAN0TMPTR78 RSCAN0.TMPTR78.UINT32
-#define RSCAN0TMPTR78L RSCAN0.TMPTR78.UINT16[L]
-#define RSCAN0TMPTR78LL RSCAN0.TMPTR78.UINT8[LL]
-#define RSCAN0TMPTR78LH RSCAN0.TMPTR78.UINT8[LH]
-#define RSCAN0TMPTR78H RSCAN0.TMPTR78.UINT16[H]
-#define RSCAN0TMPTR78HL RSCAN0.TMPTR78.UINT8[HL]
-#define RSCAN0TMPTR78HH RSCAN0.TMPTR78.UINT8[HH]
-#define RSCAN0TMDF078 RSCAN0.TMDF078.UINT32
-#define RSCAN0TMDF078L RSCAN0.TMDF078.UINT16[L]
-#define RSCAN0TMDF078LL RSCAN0.TMDF078.UINT8[LL]
-#define RSCAN0TMDF078LH RSCAN0.TMDF078.UINT8[LH]
-#define RSCAN0TMDF078H RSCAN0.TMDF078.UINT16[H]
-#define RSCAN0TMDF078HL RSCAN0.TMDF078.UINT8[HL]
-#define RSCAN0TMDF078HH RSCAN0.TMDF078.UINT8[HH]
-#define RSCAN0TMDF178 RSCAN0.TMDF178.UINT32
-#define RSCAN0TMDF178L RSCAN0.TMDF178.UINT16[L]
-#define RSCAN0TMDF178LL RSCAN0.TMDF178.UINT8[LL]
-#define RSCAN0TMDF178LH RSCAN0.TMDF178.UINT8[LH]
-#define RSCAN0TMDF178H RSCAN0.TMDF178.UINT16[H]
-#define RSCAN0TMDF178HL RSCAN0.TMDF178.UINT8[HL]
-#define RSCAN0TMDF178HH RSCAN0.TMDF178.UINT8[HH]
-#define RSCAN0TMID79 RSCAN0.TMID79.UINT32
-#define RSCAN0TMID79L RSCAN0.TMID79.UINT16[L]
-#define RSCAN0TMID79LL RSCAN0.TMID79.UINT8[LL]
-#define RSCAN0TMID79LH RSCAN0.TMID79.UINT8[LH]
-#define RSCAN0TMID79H RSCAN0.TMID79.UINT16[H]
-#define RSCAN0TMID79HL RSCAN0.TMID79.UINT8[HL]
-#define RSCAN0TMID79HH RSCAN0.TMID79.UINT8[HH]
-#define RSCAN0TMPTR79 RSCAN0.TMPTR79.UINT32
-#define RSCAN0TMPTR79L RSCAN0.TMPTR79.UINT16[L]
-#define RSCAN0TMPTR79LL RSCAN0.TMPTR79.UINT8[LL]
-#define RSCAN0TMPTR79LH RSCAN0.TMPTR79.UINT8[LH]
-#define RSCAN0TMPTR79H RSCAN0.TMPTR79.UINT16[H]
-#define RSCAN0TMPTR79HL RSCAN0.TMPTR79.UINT8[HL]
-#define RSCAN0TMPTR79HH RSCAN0.TMPTR79.UINT8[HH]
-#define RSCAN0TMDF079 RSCAN0.TMDF079.UINT32
-#define RSCAN0TMDF079L RSCAN0.TMDF079.UINT16[L]
-#define RSCAN0TMDF079LL RSCAN0.TMDF079.UINT8[LL]
-#define RSCAN0TMDF079LH RSCAN0.TMDF079.UINT8[LH]
-#define RSCAN0TMDF079H RSCAN0.TMDF079.UINT16[H]
-#define RSCAN0TMDF079HL RSCAN0.TMDF079.UINT8[HL]
-#define RSCAN0TMDF079HH RSCAN0.TMDF079.UINT8[HH]
-#define RSCAN0TMDF179 RSCAN0.TMDF179.UINT32
-#define RSCAN0TMDF179L RSCAN0.TMDF179.UINT16[L]
-#define RSCAN0TMDF179LL RSCAN0.TMDF179.UINT8[LL]
-#define RSCAN0TMDF179LH RSCAN0.TMDF179.UINT8[LH]
-#define RSCAN0TMDF179H RSCAN0.TMDF179.UINT16[H]
-#define RSCAN0TMDF179HL RSCAN0.TMDF179.UINT8[HL]
-#define RSCAN0TMDF179HH RSCAN0.TMDF179.UINT8[HH]
-#define RSCAN0THLACC0 RSCAN0.THLACC0.UINT32
-#define RSCAN0THLACC0L RSCAN0.THLACC0.UINT16[L]
-#define RSCAN0THLACC0LL RSCAN0.THLACC0.UINT8[LL]
-#define RSCAN0THLACC0LH RSCAN0.THLACC0.UINT8[LH]
-#define RSCAN0THLACC0H RSCAN0.THLACC0.UINT16[H]
-#define RSCAN0THLACC0HL RSCAN0.THLACC0.UINT8[HL]
-#define RSCAN0THLACC0HH RSCAN0.THLACC0.UINT8[HH]
-#define RSCAN0THLACC1 RSCAN0.THLACC1.UINT32
-#define RSCAN0THLACC1L RSCAN0.THLACC1.UINT16[L]
-#define RSCAN0THLACC1LL RSCAN0.THLACC1.UINT8[LL]
-#define RSCAN0THLACC1LH RSCAN0.THLACC1.UINT8[LH]
-#define RSCAN0THLACC1H RSCAN0.THLACC1.UINT16[H]
-#define RSCAN0THLACC1HL RSCAN0.THLACC1.UINT8[HL]
-#define RSCAN0THLACC1HH RSCAN0.THLACC1.UINT8[HH]
-#define RSCAN0THLACC2 RSCAN0.THLACC2.UINT32
-#define RSCAN0THLACC2L RSCAN0.THLACC2.UINT16[L]
-#define RSCAN0THLACC2LL RSCAN0.THLACC2.UINT8[LL]
-#define RSCAN0THLACC2LH RSCAN0.THLACC2.UINT8[LH]
-#define RSCAN0THLACC2H RSCAN0.THLACC2.UINT16[H]
-#define RSCAN0THLACC2HL RSCAN0.THLACC2.UINT8[HL]
-#define RSCAN0THLACC2HH RSCAN0.THLACC2.UINT8[HH]
-#define RSCAN0THLACC3 RSCAN0.THLACC3.UINT32
-#define RSCAN0THLACC3L RSCAN0.THLACC3.UINT16[L]
-#define RSCAN0THLACC3LL RSCAN0.THLACC3.UINT8[LL]
-#define RSCAN0THLACC3LH RSCAN0.THLACC3.UINT8[LH]
-#define RSCAN0THLACC3H RSCAN0.THLACC3.UINT16[H]
-#define RSCAN0THLACC3HL RSCAN0.THLACC3.UINT8[HL]
-#define RSCAN0THLACC3HH RSCAN0.THLACC3.UINT8[HH]
-#define RSCAN0THLACC4 RSCAN0.THLACC4.UINT32
-#define RSCAN0THLACC4L RSCAN0.THLACC4.UINT16[L]
-#define RSCAN0THLACC4LL RSCAN0.THLACC4.UINT8[LL]
-#define RSCAN0THLACC4LH RSCAN0.THLACC4.UINT8[LH]
-#define RSCAN0THLACC4H RSCAN0.THLACC4.UINT16[H]
-#define RSCAN0THLACC4HL RSCAN0.THLACC4.UINT8[HL]
-#define RSCAN0THLACC4HH RSCAN0.THLACC4.UINT8[HH]
+/* End of channel array defines of RSCAN0 */
+
+
+#define RSCAN0C0CFG (RSCAN0.C0CFG.UINT32)
+#define RSCAN0C0CFGL (RSCAN0.C0CFG.UINT16[R_IO_L])
+#define RSCAN0C0CFGLL (RSCAN0.C0CFG.UINT8[R_IO_LL])
+#define RSCAN0C0CFGLH (RSCAN0.C0CFG.UINT8[R_IO_LH])
+#define RSCAN0C0CFGH (RSCAN0.C0CFG.UINT16[R_IO_H])
+#define RSCAN0C0CFGHL (RSCAN0.C0CFG.UINT8[R_IO_HL])
+#define RSCAN0C0CFGHH (RSCAN0.C0CFG.UINT8[R_IO_HH])
+#define RSCAN0C0CTR (RSCAN0.C0CTR.UINT32)
+#define RSCAN0C0CTRL (RSCAN0.C0CTR.UINT16[R_IO_L])
+#define RSCAN0C0CTRLL (RSCAN0.C0CTR.UINT8[R_IO_LL])
+#define RSCAN0C0CTRLH (RSCAN0.C0CTR.UINT8[R_IO_LH])
+#define RSCAN0C0CTRH (RSCAN0.C0CTR.UINT16[R_IO_H])
+#define RSCAN0C0CTRHL (RSCAN0.C0CTR.UINT8[R_IO_HL])
+#define RSCAN0C0CTRHH (RSCAN0.C0CTR.UINT8[R_IO_HH])
+#define RSCAN0C0STS (RSCAN0.C0STS.UINT32)
+#define RSCAN0C0STSL (RSCAN0.C0STS.UINT16[R_IO_L])
+#define RSCAN0C0STSLL (RSCAN0.C0STS.UINT8[R_IO_LL])
+#define RSCAN0C0STSLH (RSCAN0.C0STS.UINT8[R_IO_LH])
+#define RSCAN0C0STSH (RSCAN0.C0STS.UINT16[R_IO_H])
+#define RSCAN0C0STSHL (RSCAN0.C0STS.UINT8[R_IO_HL])
+#define RSCAN0C0STSHH (RSCAN0.C0STS.UINT8[R_IO_HH])
+#define RSCAN0C0ERFL (RSCAN0.C0ERFL.UINT32)
+#define RSCAN0C0ERFLL (RSCAN0.C0ERFL.UINT16[R_IO_L])
+#define RSCAN0C0ERFLLL (RSCAN0.C0ERFL.UINT8[R_IO_LL])
+#define RSCAN0C0ERFLLH (RSCAN0.C0ERFL.UINT8[R_IO_LH])
+#define RSCAN0C0ERFLH (RSCAN0.C0ERFL.UINT16[R_IO_H])
+#define RSCAN0C0ERFLHL (RSCAN0.C0ERFL.UINT8[R_IO_HL])
+#define RSCAN0C0ERFLHH (RSCAN0.C0ERFL.UINT8[R_IO_HH])
+#define RSCAN0C1CFG (RSCAN0.C1CFG.UINT32)
+#define RSCAN0C1CFGL (RSCAN0.C1CFG.UINT16[R_IO_L])
+#define RSCAN0C1CFGLL (RSCAN0.C1CFG.UINT8[R_IO_LL])
+#define RSCAN0C1CFGLH (RSCAN0.C1CFG.UINT8[R_IO_LH])
+#define RSCAN0C1CFGH (RSCAN0.C1CFG.UINT16[R_IO_H])
+#define RSCAN0C1CFGHL (RSCAN0.C1CFG.UINT8[R_IO_HL])
+#define RSCAN0C1CFGHH (RSCAN0.C1CFG.UINT8[R_IO_HH])
+#define RSCAN0C1CTR (RSCAN0.C1CTR.UINT32)
+#define RSCAN0C1CTRL (RSCAN0.C1CTR.UINT16[R_IO_L])
+#define RSCAN0C1CTRLL (RSCAN0.C1CTR.UINT8[R_IO_LL])
+#define RSCAN0C1CTRLH (RSCAN0.C1CTR.UINT8[R_IO_LH])
+#define RSCAN0C1CTRH (RSCAN0.C1CTR.UINT16[R_IO_H])
+#define RSCAN0C1CTRHL (RSCAN0.C1CTR.UINT8[R_IO_HL])
+#define RSCAN0C1CTRHH (RSCAN0.C1CTR.UINT8[R_IO_HH])
+#define RSCAN0C1STS (RSCAN0.C1STS.UINT32)
+#define RSCAN0C1STSL (RSCAN0.C1STS.UINT16[R_IO_L])
+#define RSCAN0C1STSLL (RSCAN0.C1STS.UINT8[R_IO_LL])
+#define RSCAN0C1STSLH (RSCAN0.C1STS.UINT8[R_IO_LH])
+#define RSCAN0C1STSH (RSCAN0.C1STS.UINT16[R_IO_H])
+#define RSCAN0C1STSHL (RSCAN0.C1STS.UINT8[R_IO_HL])
+#define RSCAN0C1STSHH (RSCAN0.C1STS.UINT8[R_IO_HH])
+#define RSCAN0C1ERFL (RSCAN0.C1ERFL.UINT32)
+#define RSCAN0C1ERFLL (RSCAN0.C1ERFL.UINT16[R_IO_L])
+#define RSCAN0C1ERFLLL (RSCAN0.C1ERFL.UINT8[R_IO_LL])
+#define RSCAN0C1ERFLLH (RSCAN0.C1ERFL.UINT8[R_IO_LH])
+#define RSCAN0C1ERFLH (RSCAN0.C1ERFL.UINT16[R_IO_H])
+#define RSCAN0C1ERFLHL (RSCAN0.C1ERFL.UINT8[R_IO_HL])
+#define RSCAN0C1ERFLHH (RSCAN0.C1ERFL.UINT8[R_IO_HH])
+#define RSCAN0C2CFG (RSCAN0.C2CFG.UINT32)
+#define RSCAN0C2CFGL (RSCAN0.C2CFG.UINT16[R_IO_L])
+#define RSCAN0C2CFGLL (RSCAN0.C2CFG.UINT8[R_IO_LL])
+#define RSCAN0C2CFGLH (RSCAN0.C2CFG.UINT8[R_IO_LH])
+#define RSCAN0C2CFGH (RSCAN0.C2CFG.UINT16[R_IO_H])
+#define RSCAN0C2CFGHL (RSCAN0.C2CFG.UINT8[R_IO_HL])
+#define RSCAN0C2CFGHH (RSCAN0.C2CFG.UINT8[R_IO_HH])
+#define RSCAN0C2CTR (RSCAN0.C2CTR.UINT32)
+#define RSCAN0C2CTRL (RSCAN0.C2CTR.UINT16[R_IO_L])
+#define RSCAN0C2CTRLL (RSCAN0.C2CTR.UINT8[R_IO_LL])
+#define RSCAN0C2CTRLH (RSCAN0.C2CTR.UINT8[R_IO_LH])
+#define RSCAN0C2CTRH (RSCAN0.C2CTR.UINT16[R_IO_H])
+#define RSCAN0C2CTRHL (RSCAN0.C2CTR.UINT8[R_IO_HL])
+#define RSCAN0C2CTRHH (RSCAN0.C2CTR.UINT8[R_IO_HH])
+#define RSCAN0C2STS (RSCAN0.C2STS.UINT32)
+#define RSCAN0C2STSL (RSCAN0.C2STS.UINT16[R_IO_L])
+#define RSCAN0C2STSLL (RSCAN0.C2STS.UINT8[R_IO_LL])
+#define RSCAN0C2STSLH (RSCAN0.C2STS.UINT8[R_IO_LH])
+#define RSCAN0C2STSH (RSCAN0.C2STS.UINT16[R_IO_H])
+#define RSCAN0C2STSHL (RSCAN0.C2STS.UINT8[R_IO_HL])
+#define RSCAN0C2STSHH (RSCAN0.C2STS.UINT8[R_IO_HH])
+#define RSCAN0C2ERFL (RSCAN0.C2ERFL.UINT32)
+#define RSCAN0C2ERFLL (RSCAN0.C2ERFL.UINT16[R_IO_L])
+#define RSCAN0C2ERFLLL (RSCAN0.C2ERFL.UINT8[R_IO_LL])
+#define RSCAN0C2ERFLLH (RSCAN0.C2ERFL.UINT8[R_IO_LH])
+#define RSCAN0C2ERFLH (RSCAN0.C2ERFL.UINT16[R_IO_H])
+#define RSCAN0C2ERFLHL (RSCAN0.C2ERFL.UINT8[R_IO_HL])
+#define RSCAN0C2ERFLHH (RSCAN0.C2ERFL.UINT8[R_IO_HH])
+#define RSCAN0C3CFG (RSCAN0.C3CFG.UINT32)
+#define RSCAN0C3CFGL (RSCAN0.C3CFG.UINT16[R_IO_L])
+#define RSCAN0C3CFGLL (RSCAN0.C3CFG.UINT8[R_IO_LL])
+#define RSCAN0C3CFGLH (RSCAN0.C3CFG.UINT8[R_IO_LH])
+#define RSCAN0C3CFGH (RSCAN0.C3CFG.UINT16[R_IO_H])
+#define RSCAN0C3CFGHL (RSCAN0.C3CFG.UINT8[R_IO_HL])
+#define RSCAN0C3CFGHH (RSCAN0.C3CFG.UINT8[R_IO_HH])
+#define RSCAN0C3CTR (RSCAN0.C3CTR.UINT32)
+#define RSCAN0C3CTRL (RSCAN0.C3CTR.UINT16[R_IO_L])
+#define RSCAN0C3CTRLL (RSCAN0.C3CTR.UINT8[R_IO_LL])
+#define RSCAN0C3CTRLH (RSCAN0.C3CTR.UINT8[R_IO_LH])
+#define RSCAN0C3CTRH (RSCAN0.C3CTR.UINT16[R_IO_H])
+#define RSCAN0C3CTRHL (RSCAN0.C3CTR.UINT8[R_IO_HL])
+#define RSCAN0C3CTRHH (RSCAN0.C3CTR.UINT8[R_IO_HH])
+#define RSCAN0C3STS (RSCAN0.C3STS.UINT32)
+#define RSCAN0C3STSL (RSCAN0.C3STS.UINT16[R_IO_L])
+#define RSCAN0C3STSLL (RSCAN0.C3STS.UINT8[R_IO_LL])
+#define RSCAN0C3STSLH (RSCAN0.C3STS.UINT8[R_IO_LH])
+#define RSCAN0C3STSH (RSCAN0.C3STS.UINT16[R_IO_H])
+#define RSCAN0C3STSHL (RSCAN0.C3STS.UINT8[R_IO_HL])
+#define RSCAN0C3STSHH (RSCAN0.C3STS.UINT8[R_IO_HH])
+#define RSCAN0C3ERFL (RSCAN0.C3ERFL.UINT32)
+#define RSCAN0C3ERFLL (RSCAN0.C3ERFL.UINT16[R_IO_L])
+#define RSCAN0C3ERFLLL (RSCAN0.C3ERFL.UINT8[R_IO_LL])
+#define RSCAN0C3ERFLLH (RSCAN0.C3ERFL.UINT8[R_IO_LH])
+#define RSCAN0C3ERFLH (RSCAN0.C3ERFL.UINT16[R_IO_H])
+#define RSCAN0C3ERFLHL (RSCAN0.C3ERFL.UINT8[R_IO_HL])
+#define RSCAN0C3ERFLHH (RSCAN0.C3ERFL.UINT8[R_IO_HH])
+#define RSCAN0C4CFG (RSCAN0.C4CFG.UINT32)
+#define RSCAN0C4CFGL (RSCAN0.C4CFG.UINT16[R_IO_L])
+#define RSCAN0C4CFGLL (RSCAN0.C4CFG.UINT8[R_IO_LL])
+#define RSCAN0C4CFGLH (RSCAN0.C4CFG.UINT8[R_IO_LH])
+#define RSCAN0C4CFGH (RSCAN0.C4CFG.UINT16[R_IO_H])
+#define RSCAN0C4CFGHL (RSCAN0.C4CFG.UINT8[R_IO_HL])
+#define RSCAN0C4CFGHH (RSCAN0.C4CFG.UINT8[R_IO_HH])
+#define RSCAN0C4CTR (RSCAN0.C4CTR.UINT32)
+#define RSCAN0C4CTRL (RSCAN0.C4CTR.UINT16[R_IO_L])
+#define RSCAN0C4CTRLL (RSCAN0.C4CTR.UINT8[R_IO_LL])
+#define RSCAN0C4CTRLH (RSCAN0.C4CTR.UINT8[R_IO_LH])
+#define RSCAN0C4CTRH (RSCAN0.C4CTR.UINT16[R_IO_H])
+#define RSCAN0C4CTRHL (RSCAN0.C4CTR.UINT8[R_IO_HL])
+#define RSCAN0C4CTRHH (RSCAN0.C4CTR.UINT8[R_IO_HH])
+#define RSCAN0C4STS (RSCAN0.C4STS.UINT32)
+#define RSCAN0C4STSL (RSCAN0.C4STS.UINT16[R_IO_L])
+#define RSCAN0C4STSLL (RSCAN0.C4STS.UINT8[R_IO_LL])
+#define RSCAN0C4STSLH (RSCAN0.C4STS.UINT8[R_IO_LH])
+#define RSCAN0C4STSH (RSCAN0.C4STS.UINT16[R_IO_H])
+#define RSCAN0C4STSHL (RSCAN0.C4STS.UINT8[R_IO_HL])
+#define RSCAN0C4STSHH (RSCAN0.C4STS.UINT8[R_IO_HH])
+#define RSCAN0C4ERFL (RSCAN0.C4ERFL.UINT32)
+#define RSCAN0C4ERFLL (RSCAN0.C4ERFL.UINT16[R_IO_L])
+#define RSCAN0C4ERFLLL (RSCAN0.C4ERFL.UINT8[R_IO_LL])
+#define RSCAN0C4ERFLLH (RSCAN0.C4ERFL.UINT8[R_IO_LH])
+#define RSCAN0C4ERFLH (RSCAN0.C4ERFL.UINT16[R_IO_H])
+#define RSCAN0C4ERFLHL (RSCAN0.C4ERFL.UINT8[R_IO_HL])
+#define RSCAN0C4ERFLHH (RSCAN0.C4ERFL.UINT8[R_IO_HH])
+#define RSCAN0GCFG (RSCAN0.GCFG.UINT32)
+#define RSCAN0GCFGL (RSCAN0.GCFG.UINT16[R_IO_L])
+#define RSCAN0GCFGLL (RSCAN0.GCFG.UINT8[R_IO_LL])
+#define RSCAN0GCFGLH (RSCAN0.GCFG.UINT8[R_IO_LH])
+#define RSCAN0GCFGH (RSCAN0.GCFG.UINT16[R_IO_H])
+#define RSCAN0GCFGHL (RSCAN0.GCFG.UINT8[R_IO_HL])
+#define RSCAN0GCFGHH (RSCAN0.GCFG.UINT8[R_IO_HH])
+#define RSCAN0GCTR (RSCAN0.GCTR.UINT32)
+#define RSCAN0GCTRL (RSCAN0.GCTR.UINT16[R_IO_L])
+#define RSCAN0GCTRLL (RSCAN0.GCTR.UINT8[R_IO_LL])
+#define RSCAN0GCTRLH (RSCAN0.GCTR.UINT8[R_IO_LH])
+#define RSCAN0GCTRH (RSCAN0.GCTR.UINT16[R_IO_H])
+#define RSCAN0GCTRHL (RSCAN0.GCTR.UINT8[R_IO_HL])
+#define RSCAN0GCTRHH (RSCAN0.GCTR.UINT8[R_IO_HH])
+#define RSCAN0GSTS (RSCAN0.GSTS.UINT32)
+#define RSCAN0GSTSL (RSCAN0.GSTS.UINT16[R_IO_L])
+#define RSCAN0GSTSLL (RSCAN0.GSTS.UINT8[R_IO_LL])
+#define RSCAN0GSTSLH (RSCAN0.GSTS.UINT8[R_IO_LH])
+#define RSCAN0GSTSH (RSCAN0.GSTS.UINT16[R_IO_H])
+#define RSCAN0GSTSHL (RSCAN0.GSTS.UINT8[R_IO_HL])
+#define RSCAN0GSTSHH (RSCAN0.GSTS.UINT8[R_IO_HH])
+#define RSCAN0GERFL (RSCAN0.GERFL.UINT32)
+#define RSCAN0GERFLL (RSCAN0.GERFL.UINT16[R_IO_L])
+#define RSCAN0GERFLLL (RSCAN0.GERFL.UINT8[R_IO_LL])
+#define RSCAN0GERFLLH (RSCAN0.GERFL.UINT8[R_IO_LH])
+#define RSCAN0GERFLH (RSCAN0.GERFL.UINT16[R_IO_H])
+#define RSCAN0GERFLHL (RSCAN0.GERFL.UINT8[R_IO_HL])
+#define RSCAN0GERFLHH (RSCAN0.GERFL.UINT8[R_IO_HH])
+#define RSCAN0GTSC (RSCAN0.GTSC.UINT32)
+#define RSCAN0GTSCL (RSCAN0.GTSC.UINT16[R_IO_L])
+#define RSCAN0GTSCH (RSCAN0.GTSC.UINT16[R_IO_H])
+#define RSCAN0GAFLECTR (RSCAN0.GAFLECTR.UINT32)
+#define RSCAN0GAFLECTRL (RSCAN0.GAFLECTR.UINT16[R_IO_L])
+#define RSCAN0GAFLECTRLL (RSCAN0.GAFLECTR.UINT8[R_IO_LL])
+#define RSCAN0GAFLECTRLH (RSCAN0.GAFLECTR.UINT8[R_IO_LH])
+#define RSCAN0GAFLECTRH (RSCAN0.GAFLECTR.UINT16[R_IO_H])
+#define RSCAN0GAFLECTRHL (RSCAN0.GAFLECTR.UINT8[R_IO_HL])
+#define RSCAN0GAFLECTRHH (RSCAN0.GAFLECTR.UINT8[R_IO_HH])
+#define RSCAN0GAFLCFG0 (RSCAN0.GAFLCFG0.UINT32)
+#define RSCAN0GAFLCFG0L (RSCAN0.GAFLCFG0.UINT16[R_IO_L])
+#define RSCAN0GAFLCFG0LL (RSCAN0.GAFLCFG0.UINT8[R_IO_LL])
+#define RSCAN0GAFLCFG0LH (RSCAN0.GAFLCFG0.UINT8[R_IO_LH])
+#define RSCAN0GAFLCFG0H (RSCAN0.GAFLCFG0.UINT16[R_IO_H])
+#define RSCAN0GAFLCFG0HL (RSCAN0.GAFLCFG0.UINT8[R_IO_HL])
+#define RSCAN0GAFLCFG0HH (RSCAN0.GAFLCFG0.UINT8[R_IO_HH])
+#define RSCAN0GAFLCFG1 (RSCAN0.GAFLCFG1.UINT32)
+#define RSCAN0GAFLCFG1L (RSCAN0.GAFLCFG1.UINT16[R_IO_L])
+#define RSCAN0GAFLCFG1LL (RSCAN0.GAFLCFG1.UINT8[R_IO_LL])
+#define RSCAN0GAFLCFG1LH (RSCAN0.GAFLCFG1.UINT8[R_IO_LH])
+#define RSCAN0GAFLCFG1H (RSCAN0.GAFLCFG1.UINT16[R_IO_H])
+#define RSCAN0GAFLCFG1HL (RSCAN0.GAFLCFG1.UINT8[R_IO_HL])
+#define RSCAN0GAFLCFG1HH (RSCAN0.GAFLCFG1.UINT8[R_IO_HH])
+#define RSCAN0RMNB (RSCAN0.RMNB.UINT32)
+#define RSCAN0RMNBL (RSCAN0.RMNB.UINT16[R_IO_L])
+#define RSCAN0RMNBLL (RSCAN0.RMNB.UINT8[R_IO_LL])
+#define RSCAN0RMNBLH (RSCAN0.RMNB.UINT8[R_IO_LH])
+#define RSCAN0RMNBH (RSCAN0.RMNB.UINT16[R_IO_H])
+#define RSCAN0RMNBHL (RSCAN0.RMNB.UINT8[R_IO_HL])
+#define RSCAN0RMNBHH (RSCAN0.RMNB.UINT8[R_IO_HH])
+#define RSCAN0RMND0 (RSCAN0.RMND0.UINT32)
+#define RSCAN0RMND0L (RSCAN0.RMND0.UINT16[R_IO_L])
+#define RSCAN0RMND0LL (RSCAN0.RMND0.UINT8[R_IO_LL])
+#define RSCAN0RMND0LH (RSCAN0.RMND0.UINT8[R_IO_LH])
+#define RSCAN0RMND0H (RSCAN0.RMND0.UINT16[R_IO_H])
+#define RSCAN0RMND0HL (RSCAN0.RMND0.UINT8[R_IO_HL])
+#define RSCAN0RMND0HH (RSCAN0.RMND0.UINT8[R_IO_HH])
+#define RSCAN0RMND1 (RSCAN0.RMND1.UINT32)
+#define RSCAN0RMND1L (RSCAN0.RMND1.UINT16[R_IO_L])
+#define RSCAN0RMND1LL (RSCAN0.RMND1.UINT8[R_IO_LL])
+#define RSCAN0RMND1LH (RSCAN0.RMND1.UINT8[R_IO_LH])
+#define RSCAN0RMND1H (RSCAN0.RMND1.UINT16[R_IO_H])
+#define RSCAN0RMND1HL (RSCAN0.RMND1.UINT8[R_IO_HL])
+#define RSCAN0RMND1HH (RSCAN0.RMND1.UINT8[R_IO_HH])
+#define RSCAN0RMND2 (RSCAN0.RMND2.UINT32)
+#define RSCAN0RMND2L (RSCAN0.RMND2.UINT16[R_IO_L])
+#define RSCAN0RMND2LL (RSCAN0.RMND2.UINT8[R_IO_LL])
+#define RSCAN0RMND2LH (RSCAN0.RMND2.UINT8[R_IO_LH])
+#define RSCAN0RMND2H (RSCAN0.RMND2.UINT16[R_IO_H])
+#define RSCAN0RMND2HL (RSCAN0.RMND2.UINT8[R_IO_HL])
+#define RSCAN0RMND2HH (RSCAN0.RMND2.UINT8[R_IO_HH])
+#define RSCAN0RFCC0 (RSCAN0.RFCC0.UINT32)
+#define RSCAN0RFCC0L (RSCAN0.RFCC0.UINT16[R_IO_L])
+#define RSCAN0RFCC0LL (RSCAN0.RFCC0.UINT8[R_IO_LL])
+#define RSCAN0RFCC0LH (RSCAN0.RFCC0.UINT8[R_IO_LH])
+#define RSCAN0RFCC0H (RSCAN0.RFCC0.UINT16[R_IO_H])
+#define RSCAN0RFCC0HL (RSCAN0.RFCC0.UINT8[R_IO_HL])
+#define RSCAN0RFCC0HH (RSCAN0.RFCC0.UINT8[R_IO_HH])
+#define RSCAN0RFCC1 (RSCAN0.RFCC1.UINT32)
+#define RSCAN0RFCC1L (RSCAN0.RFCC1.UINT16[R_IO_L])
+#define RSCAN0RFCC1LL (RSCAN0.RFCC1.UINT8[R_IO_LL])
+#define RSCAN0RFCC1LH (RSCAN0.RFCC1.UINT8[R_IO_LH])
+#define RSCAN0RFCC1H (RSCAN0.RFCC1.UINT16[R_IO_H])
+#define RSCAN0RFCC1HL (RSCAN0.RFCC1.UINT8[R_IO_HL])
+#define RSCAN0RFCC1HH (RSCAN0.RFCC1.UINT8[R_IO_HH])
+#define RSCAN0RFCC2 (RSCAN0.RFCC2.UINT32)
+#define RSCAN0RFCC2L (RSCAN0.RFCC2.UINT16[R_IO_L])
+#define RSCAN0RFCC2LL (RSCAN0.RFCC2.UINT8[R_IO_LL])
+#define RSCAN0RFCC2LH (RSCAN0.RFCC2.UINT8[R_IO_LH])
+#define RSCAN0RFCC2H (RSCAN0.RFCC2.UINT16[R_IO_H])
+#define RSCAN0RFCC2HL (RSCAN0.RFCC2.UINT8[R_IO_HL])
+#define RSCAN0RFCC2HH (RSCAN0.RFCC2.UINT8[R_IO_HH])
+#define RSCAN0RFCC3 (RSCAN0.RFCC3.UINT32)
+#define RSCAN0RFCC3L (RSCAN0.RFCC3.UINT16[R_IO_L])
+#define RSCAN0RFCC3LL (RSCAN0.RFCC3.UINT8[R_IO_LL])
+#define RSCAN0RFCC3LH (RSCAN0.RFCC3.UINT8[R_IO_LH])
+#define RSCAN0RFCC3H (RSCAN0.RFCC3.UINT16[R_IO_H])
+#define RSCAN0RFCC3HL (RSCAN0.RFCC3.UINT8[R_IO_HL])
+#define RSCAN0RFCC3HH (RSCAN0.RFCC3.UINT8[R_IO_HH])
+#define RSCAN0RFCC4 (RSCAN0.RFCC4.UINT32)
+#define RSCAN0RFCC4L (RSCAN0.RFCC4.UINT16[R_IO_L])
+#define RSCAN0RFCC4LL (RSCAN0.RFCC4.UINT8[R_IO_LL])
+#define RSCAN0RFCC4LH (RSCAN0.RFCC4.UINT8[R_IO_LH])
+#define RSCAN0RFCC4H (RSCAN0.RFCC4.UINT16[R_IO_H])
+#define RSCAN0RFCC4HL (RSCAN0.RFCC4.UINT8[R_IO_HL])
+#define RSCAN0RFCC4HH (RSCAN0.RFCC4.UINT8[R_IO_HH])
+#define RSCAN0RFCC5 (RSCAN0.RFCC5.UINT32)
+#define RSCAN0RFCC5L (RSCAN0.RFCC5.UINT16[R_IO_L])
+#define RSCAN0RFCC5LL (RSCAN0.RFCC5.UINT8[R_IO_LL])
+#define RSCAN0RFCC5LH (RSCAN0.RFCC5.UINT8[R_IO_LH])
+#define RSCAN0RFCC5H (RSCAN0.RFCC5.UINT16[R_IO_H])
+#define RSCAN0RFCC5HL (RSCAN0.RFCC5.UINT8[R_IO_HL])
+#define RSCAN0RFCC5HH (RSCAN0.RFCC5.UINT8[R_IO_HH])
+#define RSCAN0RFCC6 (RSCAN0.RFCC6.UINT32)
+#define RSCAN0RFCC6L (RSCAN0.RFCC6.UINT16[R_IO_L])
+#define RSCAN0RFCC6LL (RSCAN0.RFCC6.UINT8[R_IO_LL])
+#define RSCAN0RFCC6LH (RSCAN0.RFCC6.UINT8[R_IO_LH])
+#define RSCAN0RFCC6H (RSCAN0.RFCC6.UINT16[R_IO_H])
+#define RSCAN0RFCC6HL (RSCAN0.RFCC6.UINT8[R_IO_HL])
+#define RSCAN0RFCC6HH (RSCAN0.RFCC6.UINT8[R_IO_HH])
+#define RSCAN0RFCC7 (RSCAN0.RFCC7.UINT32)
+#define RSCAN0RFCC7L (RSCAN0.RFCC7.UINT16[R_IO_L])
+#define RSCAN0RFCC7LL (RSCAN0.RFCC7.UINT8[R_IO_LL])
+#define RSCAN0RFCC7LH (RSCAN0.RFCC7.UINT8[R_IO_LH])
+#define RSCAN0RFCC7H (RSCAN0.RFCC7.UINT16[R_IO_H])
+#define RSCAN0RFCC7HL (RSCAN0.RFCC7.UINT8[R_IO_HL])
+#define RSCAN0RFCC7HH (RSCAN0.RFCC7.UINT8[R_IO_HH])
+#define RSCAN0RFSTS0 (RSCAN0.RFSTS0.UINT32)
+#define RSCAN0RFSTS0L (RSCAN0.RFSTS0.UINT16[R_IO_L])
+#define RSCAN0RFSTS0LL (RSCAN0.RFSTS0.UINT8[R_IO_LL])
+#define RSCAN0RFSTS0LH (RSCAN0.RFSTS0.UINT8[R_IO_LH])
+#define RSCAN0RFSTS0H (RSCAN0.RFSTS0.UINT16[R_IO_H])
+#define RSCAN0RFSTS0HL (RSCAN0.RFSTS0.UINT8[R_IO_HL])
+#define RSCAN0RFSTS0HH (RSCAN0.RFSTS0.UINT8[R_IO_HH])
+#define RSCAN0RFSTS1 (RSCAN0.RFSTS1.UINT32)
+#define RSCAN0RFSTS1L (RSCAN0.RFSTS1.UINT16[R_IO_L])
+#define RSCAN0RFSTS1LL (RSCAN0.RFSTS1.UINT8[R_IO_LL])
+#define RSCAN0RFSTS1LH (RSCAN0.RFSTS1.UINT8[R_IO_LH])
+#define RSCAN0RFSTS1H (RSCAN0.RFSTS1.UINT16[R_IO_H])
+#define RSCAN0RFSTS1HL (RSCAN0.RFSTS1.UINT8[R_IO_HL])
+#define RSCAN0RFSTS1HH (RSCAN0.RFSTS1.UINT8[R_IO_HH])
+#define RSCAN0RFSTS2 (RSCAN0.RFSTS2.UINT32)
+#define RSCAN0RFSTS2L (RSCAN0.RFSTS2.UINT16[R_IO_L])
+#define RSCAN0RFSTS2LL (RSCAN0.RFSTS2.UINT8[R_IO_LL])
+#define RSCAN0RFSTS2LH (RSCAN0.RFSTS2.UINT8[R_IO_LH])
+#define RSCAN0RFSTS2H (RSCAN0.RFSTS2.UINT16[R_IO_H])
+#define RSCAN0RFSTS2HL (RSCAN0.RFSTS2.UINT8[R_IO_HL])
+#define RSCAN0RFSTS2HH (RSCAN0.RFSTS2.UINT8[R_IO_HH])
+#define RSCAN0RFSTS3 (RSCAN0.RFSTS3.UINT32)
+#define RSCAN0RFSTS3L (RSCAN0.RFSTS3.UINT16[R_IO_L])
+#define RSCAN0RFSTS3LL (RSCAN0.RFSTS3.UINT8[R_IO_LL])
+#define RSCAN0RFSTS3LH (RSCAN0.RFSTS3.UINT8[R_IO_LH])
+#define RSCAN0RFSTS3H (RSCAN0.RFSTS3.UINT16[R_IO_H])
+#define RSCAN0RFSTS3HL (RSCAN0.RFSTS3.UINT8[R_IO_HL])
+#define RSCAN0RFSTS3HH (RSCAN0.RFSTS3.UINT8[R_IO_HH])
+#define RSCAN0RFSTS4 (RSCAN0.RFSTS4.UINT32)
+#define RSCAN0RFSTS4L (RSCAN0.RFSTS4.UINT16[R_IO_L])
+#define RSCAN0RFSTS4LL (RSCAN0.RFSTS4.UINT8[R_IO_LL])
+#define RSCAN0RFSTS4LH (RSCAN0.RFSTS4.UINT8[R_IO_LH])
+#define RSCAN0RFSTS4H (RSCAN0.RFSTS4.UINT16[R_IO_H])
+#define RSCAN0RFSTS4HL (RSCAN0.RFSTS4.UINT8[R_IO_HL])
+#define RSCAN0RFSTS4HH (RSCAN0.RFSTS4.UINT8[R_IO_HH])
+#define RSCAN0RFSTS5 (RSCAN0.RFSTS5.UINT32)
+#define RSCAN0RFSTS5L (RSCAN0.RFSTS5.UINT16[R_IO_L])
+#define RSCAN0RFSTS5LL (RSCAN0.RFSTS5.UINT8[R_IO_LL])
+#define RSCAN0RFSTS5LH (RSCAN0.RFSTS5.UINT8[R_IO_LH])
+#define RSCAN0RFSTS5H (RSCAN0.RFSTS5.UINT16[R_IO_H])
+#define RSCAN0RFSTS5HL (RSCAN0.RFSTS5.UINT8[R_IO_HL])
+#define RSCAN0RFSTS5HH (RSCAN0.RFSTS5.UINT8[R_IO_HH])
+#define RSCAN0RFSTS6 (RSCAN0.RFSTS6.UINT32)
+#define RSCAN0RFSTS6L (RSCAN0.RFSTS6.UINT16[R_IO_L])
+#define RSCAN0RFSTS6LL (RSCAN0.RFSTS6.UINT8[R_IO_LL])
+#define RSCAN0RFSTS6LH (RSCAN0.RFSTS6.UINT8[R_IO_LH])
+#define RSCAN0RFSTS6H (RSCAN0.RFSTS6.UINT16[R_IO_H])
+#define RSCAN0RFSTS6HL (RSCAN0.RFSTS6.UINT8[R_IO_HL])
+#define RSCAN0RFSTS6HH (RSCAN0.RFSTS6.UINT8[R_IO_HH])
+#define RSCAN0RFSTS7 (RSCAN0.RFSTS7.UINT32)
+#define RSCAN0RFSTS7L (RSCAN0.RFSTS7.UINT16[R_IO_L])
+#define RSCAN0RFSTS7LL (RSCAN0.RFSTS7.UINT8[R_IO_LL])
+#define RSCAN0RFSTS7LH (RSCAN0.RFSTS7.UINT8[R_IO_LH])
+#define RSCAN0RFSTS7H (RSCAN0.RFSTS7.UINT16[R_IO_H])
+#define RSCAN0RFSTS7HL (RSCAN0.RFSTS7.UINT8[R_IO_HL])
+#define RSCAN0RFSTS7HH (RSCAN0.RFSTS7.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR0 (RSCAN0.RFPCTR0.UINT32)
+#define RSCAN0RFPCTR0L (RSCAN0.RFPCTR0.UINT16[R_IO_L])
+#define RSCAN0RFPCTR0LL (RSCAN0.RFPCTR0.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR0LH (RSCAN0.RFPCTR0.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR0H (RSCAN0.RFPCTR0.UINT16[R_IO_H])
+#define RSCAN0RFPCTR0HL (RSCAN0.RFPCTR0.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR0HH (RSCAN0.RFPCTR0.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR1 (RSCAN0.RFPCTR1.UINT32)
+#define RSCAN0RFPCTR1L (RSCAN0.RFPCTR1.UINT16[R_IO_L])
+#define RSCAN0RFPCTR1LL (RSCAN0.RFPCTR1.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR1LH (RSCAN0.RFPCTR1.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR1H (RSCAN0.RFPCTR1.UINT16[R_IO_H])
+#define RSCAN0RFPCTR1HL (RSCAN0.RFPCTR1.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR1HH (RSCAN0.RFPCTR1.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR2 (RSCAN0.RFPCTR2.UINT32)
+#define RSCAN0RFPCTR2L (RSCAN0.RFPCTR2.UINT16[R_IO_L])
+#define RSCAN0RFPCTR2LL (RSCAN0.RFPCTR2.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR2LH (RSCAN0.RFPCTR2.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR2H (RSCAN0.RFPCTR2.UINT16[R_IO_H])
+#define RSCAN0RFPCTR2HL (RSCAN0.RFPCTR2.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR2HH (RSCAN0.RFPCTR2.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR3 (RSCAN0.RFPCTR3.UINT32)
+#define RSCAN0RFPCTR3L (RSCAN0.RFPCTR3.UINT16[R_IO_L])
+#define RSCAN0RFPCTR3LL (RSCAN0.RFPCTR3.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR3LH (RSCAN0.RFPCTR3.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR3H (RSCAN0.RFPCTR3.UINT16[R_IO_H])
+#define RSCAN0RFPCTR3HL (RSCAN0.RFPCTR3.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR3HH (RSCAN0.RFPCTR3.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR4 (RSCAN0.RFPCTR4.UINT32)
+#define RSCAN0RFPCTR4L (RSCAN0.RFPCTR4.UINT16[R_IO_L])
+#define RSCAN0RFPCTR4LL (RSCAN0.RFPCTR4.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR4LH (RSCAN0.RFPCTR4.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR4H (RSCAN0.RFPCTR4.UINT16[R_IO_H])
+#define RSCAN0RFPCTR4HL (RSCAN0.RFPCTR4.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR4HH (RSCAN0.RFPCTR4.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR5 (RSCAN0.RFPCTR5.UINT32)
+#define RSCAN0RFPCTR5L (RSCAN0.RFPCTR5.UINT16[R_IO_L])
+#define RSCAN0RFPCTR5LL (RSCAN0.RFPCTR5.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR5LH (RSCAN0.RFPCTR5.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR5H (RSCAN0.RFPCTR5.UINT16[R_IO_H])
+#define RSCAN0RFPCTR5HL (RSCAN0.RFPCTR5.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR5HH (RSCAN0.RFPCTR5.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR6 (RSCAN0.RFPCTR6.UINT32)
+#define RSCAN0RFPCTR6L (RSCAN0.RFPCTR6.UINT16[R_IO_L])
+#define RSCAN0RFPCTR6LL (RSCAN0.RFPCTR6.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR6LH (RSCAN0.RFPCTR6.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR6H (RSCAN0.RFPCTR6.UINT16[R_IO_H])
+#define RSCAN0RFPCTR6HL (RSCAN0.RFPCTR6.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR6HH (RSCAN0.RFPCTR6.UINT8[R_IO_HH])
+#define RSCAN0RFPCTR7 (RSCAN0.RFPCTR7.UINT32)
+#define RSCAN0RFPCTR7L (RSCAN0.RFPCTR7.UINT16[R_IO_L])
+#define RSCAN0RFPCTR7LL (RSCAN0.RFPCTR7.UINT8[R_IO_LL])
+#define RSCAN0RFPCTR7LH (RSCAN0.RFPCTR7.UINT8[R_IO_LH])
+#define RSCAN0RFPCTR7H (RSCAN0.RFPCTR7.UINT16[R_IO_H])
+#define RSCAN0RFPCTR7HL (RSCAN0.RFPCTR7.UINT8[R_IO_HL])
+#define RSCAN0RFPCTR7HH (RSCAN0.RFPCTR7.UINT8[R_IO_HH])
+#define RSCAN0CFCC0 (RSCAN0.CFCC0.UINT32)
+#define RSCAN0CFCC0L (RSCAN0.CFCC0.UINT16[R_IO_L])
+#define RSCAN0CFCC0LL (RSCAN0.CFCC0.UINT8[R_IO_LL])
+#define RSCAN0CFCC0LH (RSCAN0.CFCC0.UINT8[R_IO_LH])
+#define RSCAN0CFCC0H (RSCAN0.CFCC0.UINT16[R_IO_H])
+#define RSCAN0CFCC0HL (RSCAN0.CFCC0.UINT8[R_IO_HL])
+#define RSCAN0CFCC0HH (RSCAN0.CFCC0.UINT8[R_IO_HH])
+#define RSCAN0CFCC1 (RSCAN0.CFCC1.UINT32)
+#define RSCAN0CFCC1L (RSCAN0.CFCC1.UINT16[R_IO_L])
+#define RSCAN0CFCC1LL (RSCAN0.CFCC1.UINT8[R_IO_LL])
+#define RSCAN0CFCC1LH (RSCAN0.CFCC1.UINT8[R_IO_LH])
+#define RSCAN0CFCC1H (RSCAN0.CFCC1.UINT16[R_IO_H])
+#define RSCAN0CFCC1HL (RSCAN0.CFCC1.UINT8[R_IO_HL])
+#define RSCAN0CFCC1HH (RSCAN0.CFCC1.UINT8[R_IO_HH])
+#define RSCAN0CFCC2 (RSCAN0.CFCC2.UINT32)
+#define RSCAN0CFCC2L (RSCAN0.CFCC2.UINT16[R_IO_L])
+#define RSCAN0CFCC2LL (RSCAN0.CFCC2.UINT8[R_IO_LL])
+#define RSCAN0CFCC2LH (RSCAN0.CFCC2.UINT8[R_IO_LH])
+#define RSCAN0CFCC2H (RSCAN0.CFCC2.UINT16[R_IO_H])
+#define RSCAN0CFCC2HL (RSCAN0.CFCC2.UINT8[R_IO_HL])
+#define RSCAN0CFCC2HH (RSCAN0.CFCC2.UINT8[R_IO_HH])
+#define RSCAN0CFCC3 (RSCAN0.CFCC3.UINT32)
+#define RSCAN0CFCC3L (RSCAN0.CFCC3.UINT16[R_IO_L])
+#define RSCAN0CFCC3LL (RSCAN0.CFCC3.UINT8[R_IO_LL])
+#define RSCAN0CFCC3LH (RSCAN0.CFCC3.UINT8[R_IO_LH])
+#define RSCAN0CFCC3H (RSCAN0.CFCC3.UINT16[R_IO_H])
+#define RSCAN0CFCC3HL (RSCAN0.CFCC3.UINT8[R_IO_HL])
+#define RSCAN0CFCC3HH (RSCAN0.CFCC3.UINT8[R_IO_HH])
+#define RSCAN0CFCC4 (RSCAN0.CFCC4.UINT32)
+#define RSCAN0CFCC4L (RSCAN0.CFCC4.UINT16[R_IO_L])
+#define RSCAN0CFCC4LL (RSCAN0.CFCC4.UINT8[R_IO_LL])
+#define RSCAN0CFCC4LH (RSCAN0.CFCC4.UINT8[R_IO_LH])
+#define RSCAN0CFCC4H (RSCAN0.CFCC4.UINT16[R_IO_H])
+#define RSCAN0CFCC4HL (RSCAN0.CFCC4.UINT8[R_IO_HL])
+#define RSCAN0CFCC4HH (RSCAN0.CFCC4.UINT8[R_IO_HH])
+#define RSCAN0CFCC5 (RSCAN0.CFCC5.UINT32)
+#define RSCAN0CFCC5L (RSCAN0.CFCC5.UINT16[R_IO_L])
+#define RSCAN0CFCC5LL (RSCAN0.CFCC5.UINT8[R_IO_LL])
+#define RSCAN0CFCC5LH (RSCAN0.CFCC5.UINT8[R_IO_LH])
+#define RSCAN0CFCC5H (RSCAN0.CFCC5.UINT16[R_IO_H])
+#define RSCAN0CFCC5HL (RSCAN0.CFCC5.UINT8[R_IO_HL])
+#define RSCAN0CFCC5HH (RSCAN0.CFCC5.UINT8[R_IO_HH])
+#define RSCAN0CFCC6 (RSCAN0.CFCC6.UINT32)
+#define RSCAN0CFCC6L (RSCAN0.CFCC6.UINT16[R_IO_L])
+#define RSCAN0CFCC6LL (RSCAN0.CFCC6.UINT8[R_IO_LL])
+#define RSCAN0CFCC6LH (RSCAN0.CFCC6.UINT8[R_IO_LH])
+#define RSCAN0CFCC6H (RSCAN0.CFCC6.UINT16[R_IO_H])
+#define RSCAN0CFCC6HL (RSCAN0.CFCC6.UINT8[R_IO_HL])
+#define RSCAN0CFCC6HH (RSCAN0.CFCC6.UINT8[R_IO_HH])
+#define RSCAN0CFCC7 (RSCAN0.CFCC7.UINT32)
+#define RSCAN0CFCC7L (RSCAN0.CFCC7.UINT16[R_IO_L])
+#define RSCAN0CFCC7LL (RSCAN0.CFCC7.UINT8[R_IO_LL])
+#define RSCAN0CFCC7LH (RSCAN0.CFCC7.UINT8[R_IO_LH])
+#define RSCAN0CFCC7H (RSCAN0.CFCC7.UINT16[R_IO_H])
+#define RSCAN0CFCC7HL (RSCAN0.CFCC7.UINT8[R_IO_HL])
+#define RSCAN0CFCC7HH (RSCAN0.CFCC7.UINT8[R_IO_HH])
+#define RSCAN0CFCC8 (RSCAN0.CFCC8.UINT32)
+#define RSCAN0CFCC8L (RSCAN0.CFCC8.UINT16[R_IO_L])
+#define RSCAN0CFCC8LL (RSCAN0.CFCC8.UINT8[R_IO_LL])
+#define RSCAN0CFCC8LH (RSCAN0.CFCC8.UINT8[R_IO_LH])
+#define RSCAN0CFCC8H (RSCAN0.CFCC8.UINT16[R_IO_H])
+#define RSCAN0CFCC8HL (RSCAN0.CFCC8.UINT8[R_IO_HL])
+#define RSCAN0CFCC8HH (RSCAN0.CFCC8.UINT8[R_IO_HH])
+#define RSCAN0CFCC9 (RSCAN0.CFCC9.UINT32)
+#define RSCAN0CFCC9L (RSCAN0.CFCC9.UINT16[R_IO_L])
+#define RSCAN0CFCC9LL (RSCAN0.CFCC9.UINT8[R_IO_LL])
+#define RSCAN0CFCC9LH (RSCAN0.CFCC9.UINT8[R_IO_LH])
+#define RSCAN0CFCC9H (RSCAN0.CFCC9.UINT16[R_IO_H])
+#define RSCAN0CFCC9HL (RSCAN0.CFCC9.UINT8[R_IO_HL])
+#define RSCAN0CFCC9HH (RSCAN0.CFCC9.UINT8[R_IO_HH])
+#define RSCAN0CFCC10 (RSCAN0.CFCC10.UINT32)
+#define RSCAN0CFCC10L (RSCAN0.CFCC10.UINT16[R_IO_L])
+#define RSCAN0CFCC10LL (RSCAN0.CFCC10.UINT8[R_IO_LL])
+#define RSCAN0CFCC10LH (RSCAN0.CFCC10.UINT8[R_IO_LH])
+#define RSCAN0CFCC10H (RSCAN0.CFCC10.UINT16[R_IO_H])
+#define RSCAN0CFCC10HL (RSCAN0.CFCC10.UINT8[R_IO_HL])
+#define RSCAN0CFCC10HH (RSCAN0.CFCC10.UINT8[R_IO_HH])
+#define RSCAN0CFCC11 (RSCAN0.CFCC11.UINT32)
+#define RSCAN0CFCC11L (RSCAN0.CFCC11.UINT16[R_IO_L])
+#define RSCAN0CFCC11LL (RSCAN0.CFCC11.UINT8[R_IO_LL])
+#define RSCAN0CFCC11LH (RSCAN0.CFCC11.UINT8[R_IO_LH])
+#define RSCAN0CFCC11H (RSCAN0.CFCC11.UINT16[R_IO_H])
+#define RSCAN0CFCC11HL (RSCAN0.CFCC11.UINT8[R_IO_HL])
+#define RSCAN0CFCC11HH (RSCAN0.CFCC11.UINT8[R_IO_HH])
+#define RSCAN0CFCC12 (RSCAN0.CFCC12.UINT32)
+#define RSCAN0CFCC12L (RSCAN0.CFCC12.UINT16[R_IO_L])
+#define RSCAN0CFCC12LL (RSCAN0.CFCC12.UINT8[R_IO_LL])
+#define RSCAN0CFCC12LH (RSCAN0.CFCC12.UINT8[R_IO_LH])
+#define RSCAN0CFCC12H (RSCAN0.CFCC12.UINT16[R_IO_H])
+#define RSCAN0CFCC12HL (RSCAN0.CFCC12.UINT8[R_IO_HL])
+#define RSCAN0CFCC12HH (RSCAN0.CFCC12.UINT8[R_IO_HH])
+#define RSCAN0CFCC13 (RSCAN0.CFCC13.UINT32)
+#define RSCAN0CFCC13L (RSCAN0.CFCC13.UINT16[R_IO_L])
+#define RSCAN0CFCC13LL (RSCAN0.CFCC13.UINT8[R_IO_LL])
+#define RSCAN0CFCC13LH (RSCAN0.CFCC13.UINT8[R_IO_LH])
+#define RSCAN0CFCC13H (RSCAN0.CFCC13.UINT16[R_IO_H])
+#define RSCAN0CFCC13HL (RSCAN0.CFCC13.UINT8[R_IO_HL])
+#define RSCAN0CFCC13HH (RSCAN0.CFCC13.UINT8[R_IO_HH])
+#define RSCAN0CFCC14 (RSCAN0.CFCC14.UINT32)
+#define RSCAN0CFCC14L (RSCAN0.CFCC14.UINT16[R_IO_L])
+#define RSCAN0CFCC14LL (RSCAN0.CFCC14.UINT8[R_IO_LL])
+#define RSCAN0CFCC14LH (RSCAN0.CFCC14.UINT8[R_IO_LH])
+#define RSCAN0CFCC14H (RSCAN0.CFCC14.UINT16[R_IO_H])
+#define RSCAN0CFCC14HL (RSCAN0.CFCC14.UINT8[R_IO_HL])
+#define RSCAN0CFCC14HH (RSCAN0.CFCC14.UINT8[R_IO_HH])
+#define RSCAN0CFSTS0 (RSCAN0.CFSTS0.UINT32)
+#define RSCAN0CFSTS0L (RSCAN0.CFSTS0.UINT16[R_IO_L])
+#define RSCAN0CFSTS0LL (RSCAN0.CFSTS0.UINT8[R_IO_LL])
+#define RSCAN0CFSTS0LH (RSCAN0.CFSTS0.UINT8[R_IO_LH])
+#define RSCAN0CFSTS0H (RSCAN0.CFSTS0.UINT16[R_IO_H])
+#define RSCAN0CFSTS0HL (RSCAN0.CFSTS0.UINT8[R_IO_HL])
+#define RSCAN0CFSTS0HH (RSCAN0.CFSTS0.UINT8[R_IO_HH])
+#define RSCAN0CFSTS1 (RSCAN0.CFSTS1.UINT32)
+#define RSCAN0CFSTS1L (RSCAN0.CFSTS1.UINT16[R_IO_L])
+#define RSCAN0CFSTS1LL (RSCAN0.CFSTS1.UINT8[R_IO_LL])
+#define RSCAN0CFSTS1LH (RSCAN0.CFSTS1.UINT8[R_IO_LH])
+#define RSCAN0CFSTS1H (RSCAN0.CFSTS1.UINT16[R_IO_H])
+#define RSCAN0CFSTS1HL (RSCAN0.CFSTS1.UINT8[R_IO_HL])
+#define RSCAN0CFSTS1HH (RSCAN0.CFSTS1.UINT8[R_IO_HH])
+#define RSCAN0CFSTS2 (RSCAN0.CFSTS2.UINT32)
+#define RSCAN0CFSTS2L (RSCAN0.CFSTS2.UINT16[R_IO_L])
+#define RSCAN0CFSTS2LL (RSCAN0.CFSTS2.UINT8[R_IO_LL])
+#define RSCAN0CFSTS2LH (RSCAN0.CFSTS2.UINT8[R_IO_LH])
+#define RSCAN0CFSTS2H (RSCAN0.CFSTS2.UINT16[R_IO_H])
+#define RSCAN0CFSTS2HL (RSCAN0.CFSTS2.UINT8[R_IO_HL])
+#define RSCAN0CFSTS2HH (RSCAN0.CFSTS2.UINT8[R_IO_HH])
+#define RSCAN0CFSTS3 (RSCAN0.CFSTS3.UINT32)
+#define RSCAN0CFSTS3L (RSCAN0.CFSTS3.UINT16[R_IO_L])
+#define RSCAN0CFSTS3LL (RSCAN0.CFSTS3.UINT8[R_IO_LL])
+#define RSCAN0CFSTS3LH (RSCAN0.CFSTS3.UINT8[R_IO_LH])
+#define RSCAN0CFSTS3H (RSCAN0.CFSTS3.UINT16[R_IO_H])
+#define RSCAN0CFSTS3HL (RSCAN0.CFSTS3.UINT8[R_IO_HL])
+#define RSCAN0CFSTS3HH (RSCAN0.CFSTS3.UINT8[R_IO_HH])
+#define RSCAN0CFSTS4 (RSCAN0.CFSTS4.UINT32)
+#define RSCAN0CFSTS4L (RSCAN0.CFSTS4.UINT16[R_IO_L])
+#define RSCAN0CFSTS4LL (RSCAN0.CFSTS4.UINT8[R_IO_LL])
+#define RSCAN0CFSTS4LH (RSCAN0.CFSTS4.UINT8[R_IO_LH])
+#define RSCAN0CFSTS4H (RSCAN0.CFSTS4.UINT16[R_IO_H])
+#define RSCAN0CFSTS4HL (RSCAN0.CFSTS4.UINT8[R_IO_HL])
+#define RSCAN0CFSTS4HH (RSCAN0.CFSTS4.UINT8[R_IO_HH])
+#define RSCAN0CFSTS5 (RSCAN0.CFSTS5.UINT32)
+#define RSCAN0CFSTS5L (RSCAN0.CFSTS5.UINT16[R_IO_L])
+#define RSCAN0CFSTS5LL (RSCAN0.CFSTS5.UINT8[R_IO_LL])
+#define RSCAN0CFSTS5LH (RSCAN0.CFSTS5.UINT8[R_IO_LH])
+#define RSCAN0CFSTS5H (RSCAN0.CFSTS5.UINT16[R_IO_H])
+#define RSCAN0CFSTS5HL (RSCAN0.CFSTS5.UINT8[R_IO_HL])
+#define RSCAN0CFSTS5HH (RSCAN0.CFSTS5.UINT8[R_IO_HH])
+#define RSCAN0CFSTS6 (RSCAN0.CFSTS6.UINT32)
+#define RSCAN0CFSTS6L (RSCAN0.CFSTS6.UINT16[R_IO_L])
+#define RSCAN0CFSTS6LL (RSCAN0.CFSTS6.UINT8[R_IO_LL])
+#define RSCAN0CFSTS6LH (RSCAN0.CFSTS6.UINT8[R_IO_LH])
+#define RSCAN0CFSTS6H (RSCAN0.CFSTS6.UINT16[R_IO_H])
+#define RSCAN0CFSTS6HL (RSCAN0.CFSTS6.UINT8[R_IO_HL])
+#define RSCAN0CFSTS6HH (RSCAN0.CFSTS6.UINT8[R_IO_HH])
+#define RSCAN0CFSTS7 (RSCAN0.CFSTS7.UINT32)
+#define RSCAN0CFSTS7L (RSCAN0.CFSTS7.UINT16[R_IO_L])
+#define RSCAN0CFSTS7LL (RSCAN0.CFSTS7.UINT8[R_IO_LL])
+#define RSCAN0CFSTS7LH (RSCAN0.CFSTS7.UINT8[R_IO_LH])
+#define RSCAN0CFSTS7H (RSCAN0.CFSTS7.UINT16[R_IO_H])
+#define RSCAN0CFSTS7HL (RSCAN0.CFSTS7.UINT8[R_IO_HL])
+#define RSCAN0CFSTS7HH (RSCAN0.CFSTS7.UINT8[R_IO_HH])
+#define RSCAN0CFSTS8 (RSCAN0.CFSTS8.UINT32)
+#define RSCAN0CFSTS8L (RSCAN0.CFSTS8.UINT16[R_IO_L])
+#define RSCAN0CFSTS8LL (RSCAN0.CFSTS8.UINT8[R_IO_LL])
+#define RSCAN0CFSTS8LH (RSCAN0.CFSTS8.UINT8[R_IO_LH])
+#define RSCAN0CFSTS8H (RSCAN0.CFSTS8.UINT16[R_IO_H])
+#define RSCAN0CFSTS8HL (RSCAN0.CFSTS8.UINT8[R_IO_HL])
+#define RSCAN0CFSTS8HH (RSCAN0.CFSTS8.UINT8[R_IO_HH])
+#define RSCAN0CFSTS9 (RSCAN0.CFSTS9.UINT32)
+#define RSCAN0CFSTS9L (RSCAN0.CFSTS9.UINT16[R_IO_L])
+#define RSCAN0CFSTS9LL (RSCAN0.CFSTS9.UINT8[R_IO_LL])
+#define RSCAN0CFSTS9LH (RSCAN0.CFSTS9.UINT8[R_IO_LH])
+#define RSCAN0CFSTS9H (RSCAN0.CFSTS9.UINT16[R_IO_H])
+#define RSCAN0CFSTS9HL (RSCAN0.CFSTS9.UINT8[R_IO_HL])
+#define RSCAN0CFSTS9HH (RSCAN0.CFSTS9.UINT8[R_IO_HH])
+#define RSCAN0CFSTS10 (RSCAN0.CFSTS10.UINT32)
+#define RSCAN0CFSTS10L (RSCAN0.CFSTS10.UINT16[R_IO_L])
+#define RSCAN0CFSTS10LL (RSCAN0.CFSTS10.UINT8[R_IO_LL])
+#define RSCAN0CFSTS10LH (RSCAN0.CFSTS10.UINT8[R_IO_LH])
+#define RSCAN0CFSTS10H (RSCAN0.CFSTS10.UINT16[R_IO_H])
+#define RSCAN0CFSTS10HL (RSCAN0.CFSTS10.UINT8[R_IO_HL])
+#define RSCAN0CFSTS10HH (RSCAN0.CFSTS10.UINT8[R_IO_HH])
+#define RSCAN0CFSTS11 (RSCAN0.CFSTS11.UINT32)
+#define RSCAN0CFSTS11L (RSCAN0.CFSTS11.UINT16[R_IO_L])
+#define RSCAN0CFSTS11LL (RSCAN0.CFSTS11.UINT8[R_IO_LL])
+#define RSCAN0CFSTS11LH (RSCAN0.CFSTS11.UINT8[R_IO_LH])
+#define RSCAN0CFSTS11H (RSCAN0.CFSTS11.UINT16[R_IO_H])
+#define RSCAN0CFSTS11HL (RSCAN0.CFSTS11.UINT8[R_IO_HL])
+#define RSCAN0CFSTS11HH (RSCAN0.CFSTS11.UINT8[R_IO_HH])
+#define RSCAN0CFSTS12 (RSCAN0.CFSTS12.UINT32)
+#define RSCAN0CFSTS12L (RSCAN0.CFSTS12.UINT16[R_IO_L])
+#define RSCAN0CFSTS12LL (RSCAN0.CFSTS12.UINT8[R_IO_LL])
+#define RSCAN0CFSTS12LH (RSCAN0.CFSTS12.UINT8[R_IO_LH])
+#define RSCAN0CFSTS12H (RSCAN0.CFSTS12.UINT16[R_IO_H])
+#define RSCAN0CFSTS12HL (RSCAN0.CFSTS12.UINT8[R_IO_HL])
+#define RSCAN0CFSTS12HH (RSCAN0.CFSTS12.UINT8[R_IO_HH])
+#define RSCAN0CFSTS13 (RSCAN0.CFSTS13.UINT32)
+#define RSCAN0CFSTS13L (RSCAN0.CFSTS13.UINT16[R_IO_L])
+#define RSCAN0CFSTS13LL (RSCAN0.CFSTS13.UINT8[R_IO_LL])
+#define RSCAN0CFSTS13LH (RSCAN0.CFSTS13.UINT8[R_IO_LH])
+#define RSCAN0CFSTS13H (RSCAN0.CFSTS13.UINT16[R_IO_H])
+#define RSCAN0CFSTS13HL (RSCAN0.CFSTS13.UINT8[R_IO_HL])
+#define RSCAN0CFSTS13HH (RSCAN0.CFSTS13.UINT8[R_IO_HH])
+#define RSCAN0CFSTS14 (RSCAN0.CFSTS14.UINT32)
+#define RSCAN0CFSTS14L (RSCAN0.CFSTS14.UINT16[R_IO_L])
+#define RSCAN0CFSTS14LL (RSCAN0.CFSTS14.UINT8[R_IO_LL])
+#define RSCAN0CFSTS14LH (RSCAN0.CFSTS14.UINT8[R_IO_LH])
+#define RSCAN0CFSTS14H (RSCAN0.CFSTS14.UINT16[R_IO_H])
+#define RSCAN0CFSTS14HL (RSCAN0.CFSTS14.UINT8[R_IO_HL])
+#define RSCAN0CFSTS14HH (RSCAN0.CFSTS14.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR0 (RSCAN0.CFPCTR0.UINT32)
+#define RSCAN0CFPCTR0L (RSCAN0.CFPCTR0.UINT16[R_IO_L])
+#define RSCAN0CFPCTR0LL (RSCAN0.CFPCTR0.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR0LH (RSCAN0.CFPCTR0.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR0H (RSCAN0.CFPCTR0.UINT16[R_IO_H])
+#define RSCAN0CFPCTR0HL (RSCAN0.CFPCTR0.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR0HH (RSCAN0.CFPCTR0.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR1 (RSCAN0.CFPCTR1.UINT32)
+#define RSCAN0CFPCTR1L (RSCAN0.CFPCTR1.UINT16[R_IO_L])
+#define RSCAN0CFPCTR1LL (RSCAN0.CFPCTR1.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR1LH (RSCAN0.CFPCTR1.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR1H (RSCAN0.CFPCTR1.UINT16[R_IO_H])
+#define RSCAN0CFPCTR1HL (RSCAN0.CFPCTR1.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR1HH (RSCAN0.CFPCTR1.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR2 (RSCAN0.CFPCTR2.UINT32)
+#define RSCAN0CFPCTR2L (RSCAN0.CFPCTR2.UINT16[R_IO_L])
+#define RSCAN0CFPCTR2LL (RSCAN0.CFPCTR2.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR2LH (RSCAN0.CFPCTR2.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR2H (RSCAN0.CFPCTR2.UINT16[R_IO_H])
+#define RSCAN0CFPCTR2HL (RSCAN0.CFPCTR2.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR2HH (RSCAN0.CFPCTR2.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR3 (RSCAN0.CFPCTR3.UINT32)
+#define RSCAN0CFPCTR3L (RSCAN0.CFPCTR3.UINT16[R_IO_L])
+#define RSCAN0CFPCTR3LL (RSCAN0.CFPCTR3.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR3LH (RSCAN0.CFPCTR3.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR3H (RSCAN0.CFPCTR3.UINT16[R_IO_H])
+#define RSCAN0CFPCTR3HL (RSCAN0.CFPCTR3.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR3HH (RSCAN0.CFPCTR3.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR4 (RSCAN0.CFPCTR4.UINT32)
+#define RSCAN0CFPCTR4L (RSCAN0.CFPCTR4.UINT16[R_IO_L])
+#define RSCAN0CFPCTR4LL (RSCAN0.CFPCTR4.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR4LH (RSCAN0.CFPCTR4.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR4H (RSCAN0.CFPCTR4.UINT16[R_IO_H])
+#define RSCAN0CFPCTR4HL (RSCAN0.CFPCTR4.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR4HH (RSCAN0.CFPCTR4.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR5 (RSCAN0.CFPCTR5.UINT32)
+#define RSCAN0CFPCTR5L (RSCAN0.CFPCTR5.UINT16[R_IO_L])
+#define RSCAN0CFPCTR5LL (RSCAN0.CFPCTR5.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR5LH (RSCAN0.CFPCTR5.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR5H (RSCAN0.CFPCTR5.UINT16[R_IO_H])
+#define RSCAN0CFPCTR5HL (RSCAN0.CFPCTR5.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR5HH (RSCAN0.CFPCTR5.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR6 (RSCAN0.CFPCTR6.UINT32)
+#define RSCAN0CFPCTR6L (RSCAN0.CFPCTR6.UINT16[R_IO_L])
+#define RSCAN0CFPCTR6LL (RSCAN0.CFPCTR6.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR6LH (RSCAN0.CFPCTR6.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR6H (RSCAN0.CFPCTR6.UINT16[R_IO_H])
+#define RSCAN0CFPCTR6HL (RSCAN0.CFPCTR6.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR6HH (RSCAN0.CFPCTR6.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR7 (RSCAN0.CFPCTR7.UINT32)
+#define RSCAN0CFPCTR7L (RSCAN0.CFPCTR7.UINT16[R_IO_L])
+#define RSCAN0CFPCTR7LL (RSCAN0.CFPCTR7.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR7LH (RSCAN0.CFPCTR7.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR7H (RSCAN0.CFPCTR7.UINT16[R_IO_H])
+#define RSCAN0CFPCTR7HL (RSCAN0.CFPCTR7.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR7HH (RSCAN0.CFPCTR7.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR8 (RSCAN0.CFPCTR8.UINT32)
+#define RSCAN0CFPCTR8L (RSCAN0.CFPCTR8.UINT16[R_IO_L])
+#define RSCAN0CFPCTR8LL (RSCAN0.CFPCTR8.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR8LH (RSCAN0.CFPCTR8.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR8H (RSCAN0.CFPCTR8.UINT16[R_IO_H])
+#define RSCAN0CFPCTR8HL (RSCAN0.CFPCTR8.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR8HH (RSCAN0.CFPCTR8.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR9 (RSCAN0.CFPCTR9.UINT32)
+#define RSCAN0CFPCTR9L (RSCAN0.CFPCTR9.UINT16[R_IO_L])
+#define RSCAN0CFPCTR9LL (RSCAN0.CFPCTR9.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR9LH (RSCAN0.CFPCTR9.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR9H (RSCAN0.CFPCTR9.UINT16[R_IO_H])
+#define RSCAN0CFPCTR9HL (RSCAN0.CFPCTR9.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR9HH (RSCAN0.CFPCTR9.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR10 (RSCAN0.CFPCTR10.UINT32)
+#define RSCAN0CFPCTR10L (RSCAN0.CFPCTR10.UINT16[R_IO_L])
+#define RSCAN0CFPCTR10LL (RSCAN0.CFPCTR10.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR10LH (RSCAN0.CFPCTR10.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR10H (RSCAN0.CFPCTR10.UINT16[R_IO_H])
+#define RSCAN0CFPCTR10HL (RSCAN0.CFPCTR10.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR10HH (RSCAN0.CFPCTR10.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR11 (RSCAN0.CFPCTR11.UINT32)
+#define RSCAN0CFPCTR11L (RSCAN0.CFPCTR11.UINT16[R_IO_L])
+#define RSCAN0CFPCTR11LL (RSCAN0.CFPCTR11.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR11LH (RSCAN0.CFPCTR11.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR11H (RSCAN0.CFPCTR11.UINT16[R_IO_H])
+#define RSCAN0CFPCTR11HL (RSCAN0.CFPCTR11.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR11HH (RSCAN0.CFPCTR11.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR12 (RSCAN0.CFPCTR12.UINT32)
+#define RSCAN0CFPCTR12L (RSCAN0.CFPCTR12.UINT16[R_IO_L])
+#define RSCAN0CFPCTR12LL (RSCAN0.CFPCTR12.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR12LH (RSCAN0.CFPCTR12.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR12H (RSCAN0.CFPCTR12.UINT16[R_IO_H])
+#define RSCAN0CFPCTR12HL (RSCAN0.CFPCTR12.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR12HH (RSCAN0.CFPCTR12.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR13 (RSCAN0.CFPCTR13.UINT32)
+#define RSCAN0CFPCTR13L (RSCAN0.CFPCTR13.UINT16[R_IO_L])
+#define RSCAN0CFPCTR13LL (RSCAN0.CFPCTR13.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR13LH (RSCAN0.CFPCTR13.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR13H (RSCAN0.CFPCTR13.UINT16[R_IO_H])
+#define RSCAN0CFPCTR13HL (RSCAN0.CFPCTR13.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR13HH (RSCAN0.CFPCTR13.UINT8[R_IO_HH])
+#define RSCAN0CFPCTR14 (RSCAN0.CFPCTR14.UINT32)
+#define RSCAN0CFPCTR14L (RSCAN0.CFPCTR14.UINT16[R_IO_L])
+#define RSCAN0CFPCTR14LL (RSCAN0.CFPCTR14.UINT8[R_IO_LL])
+#define RSCAN0CFPCTR14LH (RSCAN0.CFPCTR14.UINT8[R_IO_LH])
+#define RSCAN0CFPCTR14H (RSCAN0.CFPCTR14.UINT16[R_IO_H])
+#define RSCAN0CFPCTR14HL (RSCAN0.CFPCTR14.UINT8[R_IO_HL])
+#define RSCAN0CFPCTR14HH (RSCAN0.CFPCTR14.UINT8[R_IO_HH])
+#define RSCAN0FESTS (RSCAN0.FESTS.UINT32)
+#define RSCAN0FESTSL (RSCAN0.FESTS.UINT16[R_IO_L])
+#define RSCAN0FESTSLL (RSCAN0.FESTS.UINT8[R_IO_LL])
+#define RSCAN0FESTSLH (RSCAN0.FESTS.UINT8[R_IO_LH])
+#define RSCAN0FESTSH (RSCAN0.FESTS.UINT16[R_IO_H])
+#define RSCAN0FESTSHL (RSCAN0.FESTS.UINT8[R_IO_HL])
+#define RSCAN0FESTSHH (RSCAN0.FESTS.UINT8[R_IO_HH])
+#define RSCAN0FFSTS (RSCAN0.FFSTS.UINT32)
+#define RSCAN0FFSTSL (RSCAN0.FFSTS.UINT16[R_IO_L])
+#define RSCAN0FFSTSLL (RSCAN0.FFSTS.UINT8[R_IO_LL])
+#define RSCAN0FFSTSLH (RSCAN0.FFSTS.UINT8[R_IO_LH])
+#define RSCAN0FFSTSH (RSCAN0.FFSTS.UINT16[R_IO_H])
+#define RSCAN0FFSTSHL (RSCAN0.FFSTS.UINT8[R_IO_HL])
+#define RSCAN0FFSTSHH (RSCAN0.FFSTS.UINT8[R_IO_HH])
+#define RSCAN0FMSTS (RSCAN0.FMSTS.UINT32)
+#define RSCAN0FMSTSL (RSCAN0.FMSTS.UINT16[R_IO_L])
+#define RSCAN0FMSTSLL (RSCAN0.FMSTS.UINT8[R_IO_LL])
+#define RSCAN0FMSTSLH (RSCAN0.FMSTS.UINT8[R_IO_LH])
+#define RSCAN0FMSTSH (RSCAN0.FMSTS.UINT16[R_IO_H])
+#define RSCAN0FMSTSHL (RSCAN0.FMSTS.UINT8[R_IO_HL])
+#define RSCAN0FMSTSHH (RSCAN0.FMSTS.UINT8[R_IO_HH])
+#define RSCAN0RFISTS (RSCAN0.RFISTS.UINT32)
+#define RSCAN0RFISTSL (RSCAN0.RFISTS.UINT16[R_IO_L])
+#define RSCAN0RFISTSLL (RSCAN0.RFISTS.UINT8[R_IO_LL])
+#define RSCAN0RFISTSLH (RSCAN0.RFISTS.UINT8[R_IO_LH])
+#define RSCAN0RFISTSH (RSCAN0.RFISTS.UINT16[R_IO_H])
+#define RSCAN0RFISTSHL (RSCAN0.RFISTS.UINT8[R_IO_HL])
+#define RSCAN0RFISTSHH (RSCAN0.RFISTS.UINT8[R_IO_HH])
+#define RSCAN0CFRISTS (RSCAN0.CFRISTS.UINT32)
+#define RSCAN0CFRISTSL (RSCAN0.CFRISTS.UINT16[R_IO_L])
+#define RSCAN0CFRISTSLL (RSCAN0.CFRISTS.UINT8[R_IO_LL])
+#define RSCAN0CFRISTSLH (RSCAN0.CFRISTS.UINT8[R_IO_LH])
+#define RSCAN0CFRISTSH (RSCAN0.CFRISTS.UINT16[R_IO_H])
+#define RSCAN0CFRISTSHL (RSCAN0.CFRISTS.UINT8[R_IO_HL])
+#define RSCAN0CFRISTSHH (RSCAN0.CFRISTS.UINT8[R_IO_HH])
+#define RSCAN0CFTISTS (RSCAN0.CFTISTS.UINT32)
+#define RSCAN0CFTISTSL (RSCAN0.CFTISTS.UINT16[R_IO_L])
+#define RSCAN0CFTISTSLL (RSCAN0.CFTISTS.UINT8[R_IO_LL])
+#define RSCAN0CFTISTSLH (RSCAN0.CFTISTS.UINT8[R_IO_LH])
+#define RSCAN0CFTISTSH (RSCAN0.CFTISTS.UINT16[R_IO_H])
+#define RSCAN0CFTISTSHL (RSCAN0.CFTISTS.UINT8[R_IO_HL])
+#define RSCAN0CFTISTSHH (RSCAN0.CFTISTS.UINT8[R_IO_HH])
+#define RSCAN0TMC0 (RSCAN0.TMC0)
+#define RSCAN0TMC1 (RSCAN0.TMC1)
+#define RSCAN0TMC2 (RSCAN0.TMC2)
+#define RSCAN0TMC3 (RSCAN0.TMC3)
+#define RSCAN0TMC4 (RSCAN0.TMC4)
+#define RSCAN0TMC5 (RSCAN0.TMC5)
+#define RSCAN0TMC6 (RSCAN0.TMC6)
+#define RSCAN0TMC7 (RSCAN0.TMC7)
+#define RSCAN0TMC8 (RSCAN0.TMC8)
+#define RSCAN0TMC9 (RSCAN0.TMC9)
+#define RSCAN0TMC10 (RSCAN0.TMC10)
+#define RSCAN0TMC11 (RSCAN0.TMC11)
+#define RSCAN0TMC12 (RSCAN0.TMC12)
+#define RSCAN0TMC13 (RSCAN0.TMC13)
+#define RSCAN0TMC14 (RSCAN0.TMC14)
+#define RSCAN0TMC15 (RSCAN0.TMC15)
+#define RSCAN0TMC16 (RSCAN0.TMC16)
+#define RSCAN0TMC17 (RSCAN0.TMC17)
+#define RSCAN0TMC18 (RSCAN0.TMC18)
+#define RSCAN0TMC19 (RSCAN0.TMC19)
+#define RSCAN0TMC20 (RSCAN0.TMC20)
+#define RSCAN0TMC21 (RSCAN0.TMC21)
+#define RSCAN0TMC22 (RSCAN0.TMC22)
+#define RSCAN0TMC23 (RSCAN0.TMC23)
+#define RSCAN0TMC24 (RSCAN0.TMC24)
+#define RSCAN0TMC25 (RSCAN0.TMC25)
+#define RSCAN0TMC26 (RSCAN0.TMC26)
+#define RSCAN0TMC27 (RSCAN0.TMC27)
+#define RSCAN0TMC28 (RSCAN0.TMC28)
+#define RSCAN0TMC29 (RSCAN0.TMC29)
+#define RSCAN0TMC30 (RSCAN0.TMC30)
+#define RSCAN0TMC31 (RSCAN0.TMC31)
+#define RSCAN0TMC32 (RSCAN0.TMC32)
+#define RSCAN0TMC33 (RSCAN0.TMC33)
+#define RSCAN0TMC34 (RSCAN0.TMC34)
+#define RSCAN0TMC35 (RSCAN0.TMC35)
+#define RSCAN0TMC36 (RSCAN0.TMC36)
+#define RSCAN0TMC37 (RSCAN0.TMC37)
+#define RSCAN0TMC38 (RSCAN0.TMC38)
+#define RSCAN0TMC39 (RSCAN0.TMC39)
+#define RSCAN0TMC40 (RSCAN0.TMC40)
+#define RSCAN0TMC41 (RSCAN0.TMC41)
+#define RSCAN0TMC42 (RSCAN0.TMC42)
+#define RSCAN0TMC43 (RSCAN0.TMC43)
+#define RSCAN0TMC44 (RSCAN0.TMC44)
+#define RSCAN0TMC45 (RSCAN0.TMC45)
+#define RSCAN0TMC46 (RSCAN0.TMC46)
+#define RSCAN0TMC47 (RSCAN0.TMC47)
+#define RSCAN0TMC48 (RSCAN0.TMC48)
+#define RSCAN0TMC49 (RSCAN0.TMC49)
+#define RSCAN0TMC50 (RSCAN0.TMC50)
+#define RSCAN0TMC51 (RSCAN0.TMC51)
+#define RSCAN0TMC52 (RSCAN0.TMC52)
+#define RSCAN0TMC53 (RSCAN0.TMC53)
+#define RSCAN0TMC54 (RSCAN0.TMC54)
+#define RSCAN0TMC55 (RSCAN0.TMC55)
+#define RSCAN0TMC56 (RSCAN0.TMC56)
+#define RSCAN0TMC57 (RSCAN0.TMC57)
+#define RSCAN0TMC58 (RSCAN0.TMC58)
+#define RSCAN0TMC59 (RSCAN0.TMC59)
+#define RSCAN0TMC60 (RSCAN0.TMC60)
+#define RSCAN0TMC61 (RSCAN0.TMC61)
+#define RSCAN0TMC62 (RSCAN0.TMC62)
+#define RSCAN0TMC63 (RSCAN0.TMC63)
+#define RSCAN0TMC64 (RSCAN0.TMC64)
+#define RSCAN0TMC65 (RSCAN0.TMC65)
+#define RSCAN0TMC66 (RSCAN0.TMC66)
+#define RSCAN0TMC67 (RSCAN0.TMC67)
+#define RSCAN0TMC68 (RSCAN0.TMC68)
+#define RSCAN0TMC69 (RSCAN0.TMC69)
+#define RSCAN0TMC70 (RSCAN0.TMC70)
+#define RSCAN0TMC71 (RSCAN0.TMC71)
+#define RSCAN0TMC72 (RSCAN0.TMC72)
+#define RSCAN0TMC73 (RSCAN0.TMC73)
+#define RSCAN0TMC74 (RSCAN0.TMC74)
+#define RSCAN0TMC75 (RSCAN0.TMC75)
+#define RSCAN0TMC76 (RSCAN0.TMC76)
+#define RSCAN0TMC77 (RSCAN0.TMC77)
+#define RSCAN0TMC78 (RSCAN0.TMC78)
+#define RSCAN0TMC79 (RSCAN0.TMC79)
+#define RSCAN0TMSTS0 (RSCAN0.TMSTS0)
+#define RSCAN0TMSTS1 (RSCAN0.TMSTS1)
+#define RSCAN0TMSTS2 (RSCAN0.TMSTS2)
+#define RSCAN0TMSTS3 (RSCAN0.TMSTS3)
+#define RSCAN0TMSTS4 (RSCAN0.TMSTS4)
+#define RSCAN0TMSTS5 (RSCAN0.TMSTS5)
+#define RSCAN0TMSTS6 (RSCAN0.TMSTS6)
+#define RSCAN0TMSTS7 (RSCAN0.TMSTS7)
+#define RSCAN0TMSTS8 (RSCAN0.TMSTS8)
+#define RSCAN0TMSTS9 (RSCAN0.TMSTS9)
+#define RSCAN0TMSTS10 (RSCAN0.TMSTS10)
+#define RSCAN0TMSTS11 (RSCAN0.TMSTS11)
+#define RSCAN0TMSTS12 (RSCAN0.TMSTS12)
+#define RSCAN0TMSTS13 (RSCAN0.TMSTS13)
+#define RSCAN0TMSTS14 (RSCAN0.TMSTS14)
+#define RSCAN0TMSTS15 (RSCAN0.TMSTS15)
+#define RSCAN0TMSTS16 (RSCAN0.TMSTS16)
+#define RSCAN0TMSTS17 (RSCAN0.TMSTS17)
+#define RSCAN0TMSTS18 (RSCAN0.TMSTS18)
+#define RSCAN0TMSTS19 (RSCAN0.TMSTS19)
+#define RSCAN0TMSTS20 (RSCAN0.TMSTS20)
+#define RSCAN0TMSTS21 (RSCAN0.TMSTS21)
+#define RSCAN0TMSTS22 (RSCAN0.TMSTS22)
+#define RSCAN0TMSTS23 (RSCAN0.TMSTS23)
+#define RSCAN0TMSTS24 (RSCAN0.TMSTS24)
+#define RSCAN0TMSTS25 (RSCAN0.TMSTS25)
+#define RSCAN0TMSTS26 (RSCAN0.TMSTS26)
+#define RSCAN0TMSTS27 (RSCAN0.TMSTS27)
+#define RSCAN0TMSTS28 (RSCAN0.TMSTS28)
+#define RSCAN0TMSTS29 (RSCAN0.TMSTS29)
+#define RSCAN0TMSTS30 (RSCAN0.TMSTS30)
+#define RSCAN0TMSTS31 (RSCAN0.TMSTS31)
+#define RSCAN0TMSTS32 (RSCAN0.TMSTS32)
+#define RSCAN0TMSTS33 (RSCAN0.TMSTS33)
+#define RSCAN0TMSTS34 (RSCAN0.TMSTS34)
+#define RSCAN0TMSTS35 (RSCAN0.TMSTS35)
+#define RSCAN0TMSTS36 (RSCAN0.TMSTS36)
+#define RSCAN0TMSTS37 (RSCAN0.TMSTS37)
+#define RSCAN0TMSTS38 (RSCAN0.TMSTS38)
+#define RSCAN0TMSTS39 (RSCAN0.TMSTS39)
+#define RSCAN0TMSTS40 (RSCAN0.TMSTS40)
+#define RSCAN0TMSTS41 (RSCAN0.TMSTS41)
+#define RSCAN0TMSTS42 (RSCAN0.TMSTS42)
+#define RSCAN0TMSTS43 (RSCAN0.TMSTS43)
+#define RSCAN0TMSTS44 (RSCAN0.TMSTS44)
+#define RSCAN0TMSTS45 (RSCAN0.TMSTS45)
+#define RSCAN0TMSTS46 (RSCAN0.TMSTS46)
+#define RSCAN0TMSTS47 (RSCAN0.TMSTS47)
+#define RSCAN0TMSTS48 (RSCAN0.TMSTS48)
+#define RSCAN0TMSTS49 (RSCAN0.TMSTS49)
+#define RSCAN0TMSTS50 (RSCAN0.TMSTS50)
+#define RSCAN0TMSTS51 (RSCAN0.TMSTS51)
+#define RSCAN0TMSTS52 (RSCAN0.TMSTS52)
+#define RSCAN0TMSTS53 (RSCAN0.TMSTS53)
+#define RSCAN0TMSTS54 (RSCAN0.TMSTS54)
+#define RSCAN0TMSTS55 (RSCAN0.TMSTS55)
+#define RSCAN0TMSTS56 (RSCAN0.TMSTS56)
+#define RSCAN0TMSTS57 (RSCAN0.TMSTS57)
+#define RSCAN0TMSTS58 (RSCAN0.TMSTS58)
+#define RSCAN0TMSTS59 (RSCAN0.TMSTS59)
+#define RSCAN0TMSTS60 (RSCAN0.TMSTS60)
+#define RSCAN0TMSTS61 (RSCAN0.TMSTS61)
+#define RSCAN0TMSTS62 (RSCAN0.TMSTS62)
+#define RSCAN0TMSTS63 (RSCAN0.TMSTS63)
+#define RSCAN0TMSTS64 (RSCAN0.TMSTS64)
+#define RSCAN0TMSTS65 (RSCAN0.TMSTS65)
+#define RSCAN0TMSTS66 (RSCAN0.TMSTS66)
+#define RSCAN0TMSTS67 (RSCAN0.TMSTS67)
+#define RSCAN0TMSTS68 (RSCAN0.TMSTS68)
+#define RSCAN0TMSTS69 (RSCAN0.TMSTS69)
+#define RSCAN0TMSTS70 (RSCAN0.TMSTS70)
+#define RSCAN0TMSTS71 (RSCAN0.TMSTS71)
+#define RSCAN0TMSTS72 (RSCAN0.TMSTS72)
+#define RSCAN0TMSTS73 (RSCAN0.TMSTS73)
+#define RSCAN0TMSTS74 (RSCAN0.TMSTS74)
+#define RSCAN0TMSTS75 (RSCAN0.TMSTS75)
+#define RSCAN0TMSTS76 (RSCAN0.TMSTS76)
+#define RSCAN0TMSTS77 (RSCAN0.TMSTS77)
+#define RSCAN0TMSTS78 (RSCAN0.TMSTS78)
+#define RSCAN0TMSTS79 (RSCAN0.TMSTS79)
+#define RSCAN0TMTRSTS0 (RSCAN0.TMTRSTS0.UINT32)
+#define RSCAN0TMTRSTS0L (RSCAN0.TMTRSTS0.UINT16[R_IO_L])
+#define RSCAN0TMTRSTS0LL (RSCAN0.TMTRSTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTRSTS0LH (RSCAN0.TMTRSTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTRSTS0H (RSCAN0.TMTRSTS0.UINT16[R_IO_H])
+#define RSCAN0TMTRSTS0HL (RSCAN0.TMTRSTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTRSTS0HH (RSCAN0.TMTRSTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTRSTS1 (RSCAN0.TMTRSTS1.UINT32)
+#define RSCAN0TMTRSTS1L (RSCAN0.TMTRSTS1.UINT16[R_IO_L])
+#define RSCAN0TMTRSTS1LL (RSCAN0.TMTRSTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTRSTS1LH (RSCAN0.TMTRSTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTRSTS1H (RSCAN0.TMTRSTS1.UINT16[R_IO_H])
+#define RSCAN0TMTRSTS1HL (RSCAN0.TMTRSTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTRSTS1HH (RSCAN0.TMTRSTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTRSTS2 (RSCAN0.TMTRSTS2.UINT32)
+#define RSCAN0TMTRSTS2L (RSCAN0.TMTRSTS2.UINT16[R_IO_L])
+#define RSCAN0TMTRSTS2LL (RSCAN0.TMTRSTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTRSTS2LH (RSCAN0.TMTRSTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTRSTS2H (RSCAN0.TMTRSTS2.UINT16[R_IO_H])
+#define RSCAN0TMTRSTS2HL (RSCAN0.TMTRSTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTRSTS2HH (RSCAN0.TMTRSTS2.UINT8[R_IO_HH])
+#define RSCAN0TMTARSTS0 (RSCAN0.TMTARSTS0.UINT32)
+#define RSCAN0TMTARSTS0L (RSCAN0.TMTARSTS0.UINT16[R_IO_L])
+#define RSCAN0TMTARSTS0LL (RSCAN0.TMTARSTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTARSTS0LH (RSCAN0.TMTARSTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTARSTS0H (RSCAN0.TMTARSTS0.UINT16[R_IO_H])
+#define RSCAN0TMTARSTS0HL (RSCAN0.TMTARSTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTARSTS0HH (RSCAN0.TMTARSTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTARSTS1 (RSCAN0.TMTARSTS1.UINT32)
+#define RSCAN0TMTARSTS1L (RSCAN0.TMTARSTS1.UINT16[R_IO_L])
+#define RSCAN0TMTARSTS1LL (RSCAN0.TMTARSTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTARSTS1LH (RSCAN0.TMTARSTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTARSTS1H (RSCAN0.TMTARSTS1.UINT16[R_IO_H])
+#define RSCAN0TMTARSTS1HL (RSCAN0.TMTARSTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTARSTS1HH (RSCAN0.TMTARSTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTARSTS2 (RSCAN0.TMTARSTS2.UINT32)
+#define RSCAN0TMTARSTS2L (RSCAN0.TMTARSTS2.UINT16[R_IO_L])
+#define RSCAN0TMTARSTS2LL (RSCAN0.TMTARSTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTARSTS2LH (RSCAN0.TMTARSTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTARSTS2H (RSCAN0.TMTARSTS2.UINT16[R_IO_H])
+#define RSCAN0TMTARSTS2HL (RSCAN0.TMTARSTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTARSTS2HH (RSCAN0.TMTARSTS2.UINT8[R_IO_HH])
+#define RSCAN0TMTCSTS0 (RSCAN0.TMTCSTS0.UINT32)
+#define RSCAN0TMTCSTS0L (RSCAN0.TMTCSTS0.UINT16[R_IO_L])
+#define RSCAN0TMTCSTS0LL (RSCAN0.TMTCSTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTCSTS0LH (RSCAN0.TMTCSTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTCSTS0H (RSCAN0.TMTCSTS0.UINT16[R_IO_H])
+#define RSCAN0TMTCSTS0HL (RSCAN0.TMTCSTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTCSTS0HH (RSCAN0.TMTCSTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTCSTS1 (RSCAN0.TMTCSTS1.UINT32)
+#define RSCAN0TMTCSTS1L (RSCAN0.TMTCSTS1.UINT16[R_IO_L])
+#define RSCAN0TMTCSTS1LL (RSCAN0.TMTCSTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTCSTS1LH (RSCAN0.TMTCSTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTCSTS1H (RSCAN0.TMTCSTS1.UINT16[R_IO_H])
+#define RSCAN0TMTCSTS1HL (RSCAN0.TMTCSTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTCSTS1HH (RSCAN0.TMTCSTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTCSTS2 (RSCAN0.TMTCSTS2.UINT32)
+#define RSCAN0TMTCSTS2L (RSCAN0.TMTCSTS2.UINT16[R_IO_L])
+#define RSCAN0TMTCSTS2LL (RSCAN0.TMTCSTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTCSTS2LH (RSCAN0.TMTCSTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTCSTS2H (RSCAN0.TMTCSTS2.UINT16[R_IO_H])
+#define RSCAN0TMTCSTS2HL (RSCAN0.TMTCSTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTCSTS2HH (RSCAN0.TMTCSTS2.UINT8[R_IO_HH])
+#define RSCAN0TMTASTS0 (RSCAN0.TMTASTS0.UINT32)
+#define RSCAN0TMTASTS0L (RSCAN0.TMTASTS0.UINT16[R_IO_L])
+#define RSCAN0TMTASTS0LL (RSCAN0.TMTASTS0.UINT8[R_IO_LL])
+#define RSCAN0TMTASTS0LH (RSCAN0.TMTASTS0.UINT8[R_IO_LH])
+#define RSCAN0TMTASTS0H (RSCAN0.TMTASTS0.UINT16[R_IO_H])
+#define RSCAN0TMTASTS0HL (RSCAN0.TMTASTS0.UINT8[R_IO_HL])
+#define RSCAN0TMTASTS0HH (RSCAN0.TMTASTS0.UINT8[R_IO_HH])
+#define RSCAN0TMTASTS1 (RSCAN0.TMTASTS1.UINT32)
+#define RSCAN0TMTASTS1L (RSCAN0.TMTASTS1.UINT16[R_IO_L])
+#define RSCAN0TMTASTS1LL (RSCAN0.TMTASTS1.UINT8[R_IO_LL])
+#define RSCAN0TMTASTS1LH (RSCAN0.TMTASTS1.UINT8[R_IO_LH])
+#define RSCAN0TMTASTS1H (RSCAN0.TMTASTS1.UINT16[R_IO_H])
+#define RSCAN0TMTASTS1HL (RSCAN0.TMTASTS1.UINT8[R_IO_HL])
+#define RSCAN0TMTASTS1HH (RSCAN0.TMTASTS1.UINT8[R_IO_HH])
+#define RSCAN0TMTASTS2 (RSCAN0.TMTASTS2.UINT32)
+#define RSCAN0TMTASTS2L (RSCAN0.TMTASTS2.UINT16[R_IO_L])
+#define RSCAN0TMTASTS2LL (RSCAN0.TMTASTS2.UINT8[R_IO_LL])
+#define RSCAN0TMTASTS2LH (RSCAN0.TMTASTS2.UINT8[R_IO_LH])
+#define RSCAN0TMTASTS2H (RSCAN0.TMTASTS2.UINT16[R_IO_H])
+#define RSCAN0TMTASTS2HL (RSCAN0.TMTASTS2.UINT8[R_IO_HL])
+#define RSCAN0TMTASTS2HH (RSCAN0.TMTASTS2.UINT8[R_IO_HH])
+#define RSCAN0TMIEC0 (RSCAN0.TMIEC0.UINT32)
+#define RSCAN0TMIEC0L (RSCAN0.TMIEC0.UINT16[R_IO_L])
+#define RSCAN0TMIEC0LL (RSCAN0.TMIEC0.UINT8[R_IO_LL])
+#define RSCAN0TMIEC0LH (RSCAN0.TMIEC0.UINT8[R_IO_LH])
+#define RSCAN0TMIEC0H (RSCAN0.TMIEC0.UINT16[R_IO_H])
+#define RSCAN0TMIEC0HL (RSCAN0.TMIEC0.UINT8[R_IO_HL])
+#define RSCAN0TMIEC0HH (RSCAN0.TMIEC0.UINT8[R_IO_HH])
+#define RSCAN0TMIEC1 (RSCAN0.TMIEC1.UINT32)
+#define RSCAN0TMIEC1L (RSCAN0.TMIEC1.UINT16[R_IO_L])
+#define RSCAN0TMIEC1LL (RSCAN0.TMIEC1.UINT8[R_IO_LL])
+#define RSCAN0TMIEC1LH (RSCAN0.TMIEC1.UINT8[R_IO_LH])
+#define RSCAN0TMIEC1H (RSCAN0.TMIEC1.UINT16[R_IO_H])
+#define RSCAN0TMIEC1HL (RSCAN0.TMIEC1.UINT8[R_IO_HL])
+#define RSCAN0TMIEC1HH (RSCAN0.TMIEC1.UINT8[R_IO_HH])
+#define RSCAN0TMIEC2 (RSCAN0.TMIEC2.UINT32)
+#define RSCAN0TMIEC2L (RSCAN0.TMIEC2.UINT16[R_IO_L])
+#define RSCAN0TMIEC2LL (RSCAN0.TMIEC2.UINT8[R_IO_LL])
+#define RSCAN0TMIEC2LH (RSCAN0.TMIEC2.UINT8[R_IO_LH])
+#define RSCAN0TMIEC2H (RSCAN0.TMIEC2.UINT16[R_IO_H])
+#define RSCAN0TMIEC2HL (RSCAN0.TMIEC2.UINT8[R_IO_HL])
+#define RSCAN0TMIEC2HH (RSCAN0.TMIEC2.UINT8[R_IO_HH])
+#define RSCAN0TXQCC0 (RSCAN0.TXQCC0.UINT32)
+#define RSCAN0TXQCC0L (RSCAN0.TXQCC0.UINT16[R_IO_L])
+#define RSCAN0TXQCC0LL (RSCAN0.TXQCC0.UINT8[R_IO_LL])
+#define RSCAN0TXQCC0LH (RSCAN0.TXQCC0.UINT8[R_IO_LH])
+#define RSCAN0TXQCC0H (RSCAN0.TXQCC0.UINT16[R_IO_H])
+#define RSCAN0TXQCC0HL (RSCAN0.TXQCC0.UINT8[R_IO_HL])
+#define RSCAN0TXQCC0HH (RSCAN0.TXQCC0.UINT8[R_IO_HH])
+#define RSCAN0TXQCC1 (RSCAN0.TXQCC1.UINT32)
+#define RSCAN0TXQCC1L (RSCAN0.TXQCC1.UINT16[R_IO_L])
+#define RSCAN0TXQCC1LL (RSCAN0.TXQCC1.UINT8[R_IO_LL])
+#define RSCAN0TXQCC1LH (RSCAN0.TXQCC1.UINT8[R_IO_LH])
+#define RSCAN0TXQCC1H (RSCAN0.TXQCC1.UINT16[R_IO_H])
+#define RSCAN0TXQCC1HL (RSCAN0.TXQCC1.UINT8[R_IO_HL])
+#define RSCAN0TXQCC1HH (RSCAN0.TXQCC1.UINT8[R_IO_HH])
+#define RSCAN0TXQCC2 (RSCAN0.TXQCC2.UINT32)
+#define RSCAN0TXQCC2L (RSCAN0.TXQCC2.UINT16[R_IO_L])
+#define RSCAN0TXQCC2LL (RSCAN0.TXQCC2.UINT8[R_IO_LL])
+#define RSCAN0TXQCC2LH (RSCAN0.TXQCC2.UINT8[R_IO_LH])
+#define RSCAN0TXQCC2H (RSCAN0.TXQCC2.UINT16[R_IO_H])
+#define RSCAN0TXQCC2HL (RSCAN0.TXQCC2.UINT8[R_IO_HL])
+#define RSCAN0TXQCC2HH (RSCAN0.TXQCC2.UINT8[R_IO_HH])
+#define RSCAN0TXQCC3 (RSCAN0.TXQCC3.UINT32)
+#define RSCAN0TXQCC3L (RSCAN0.TXQCC3.UINT16[R_IO_L])
+#define RSCAN0TXQCC3LL (RSCAN0.TXQCC3.UINT8[R_IO_LL])
+#define RSCAN0TXQCC3LH (RSCAN0.TXQCC3.UINT8[R_IO_LH])
+#define RSCAN0TXQCC3H (RSCAN0.TXQCC3.UINT16[R_IO_H])
+#define RSCAN0TXQCC3HL (RSCAN0.TXQCC3.UINT8[R_IO_HL])
+#define RSCAN0TXQCC3HH (RSCAN0.TXQCC3.UINT8[R_IO_HH])
+#define RSCAN0TXQCC4 (RSCAN0.TXQCC4.UINT32)
+#define RSCAN0TXQCC4L (RSCAN0.TXQCC4.UINT16[R_IO_L])
+#define RSCAN0TXQCC4LL (RSCAN0.TXQCC4.UINT8[R_IO_LL])
+#define RSCAN0TXQCC4LH (RSCAN0.TXQCC4.UINT8[R_IO_LH])
+#define RSCAN0TXQCC4H (RSCAN0.TXQCC4.UINT16[R_IO_H])
+#define RSCAN0TXQCC4HL (RSCAN0.TXQCC4.UINT8[R_IO_HL])
+#define RSCAN0TXQCC4HH (RSCAN0.TXQCC4.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS0 (RSCAN0.TXQSTS0.UINT32)
+#define RSCAN0TXQSTS0L (RSCAN0.TXQSTS0.UINT16[R_IO_L])
+#define RSCAN0TXQSTS0LL (RSCAN0.TXQSTS0.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS0LH (RSCAN0.TXQSTS0.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS0H (RSCAN0.TXQSTS0.UINT16[R_IO_H])
+#define RSCAN0TXQSTS0HL (RSCAN0.TXQSTS0.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS0HH (RSCAN0.TXQSTS0.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS1 (RSCAN0.TXQSTS1.UINT32)
+#define RSCAN0TXQSTS1L (RSCAN0.TXQSTS1.UINT16[R_IO_L])
+#define RSCAN0TXQSTS1LL (RSCAN0.TXQSTS1.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS1LH (RSCAN0.TXQSTS1.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS1H (RSCAN0.TXQSTS1.UINT16[R_IO_H])
+#define RSCAN0TXQSTS1HL (RSCAN0.TXQSTS1.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS1HH (RSCAN0.TXQSTS1.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS2 (RSCAN0.TXQSTS2.UINT32)
+#define RSCAN0TXQSTS2L (RSCAN0.TXQSTS2.UINT16[R_IO_L])
+#define RSCAN0TXQSTS2LL (RSCAN0.TXQSTS2.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS2LH (RSCAN0.TXQSTS2.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS2H (RSCAN0.TXQSTS2.UINT16[R_IO_H])
+#define RSCAN0TXQSTS2HL (RSCAN0.TXQSTS2.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS2HH (RSCAN0.TXQSTS2.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS3 (RSCAN0.TXQSTS3.UINT32)
+#define RSCAN0TXQSTS3L (RSCAN0.TXQSTS3.UINT16[R_IO_L])
+#define RSCAN0TXQSTS3LL (RSCAN0.TXQSTS3.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS3LH (RSCAN0.TXQSTS3.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS3H (RSCAN0.TXQSTS3.UINT16[R_IO_H])
+#define RSCAN0TXQSTS3HL (RSCAN0.TXQSTS3.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS3HH (RSCAN0.TXQSTS3.UINT8[R_IO_HH])
+#define RSCAN0TXQSTS4 (RSCAN0.TXQSTS4.UINT32)
+#define RSCAN0TXQSTS4L (RSCAN0.TXQSTS4.UINT16[R_IO_L])
+#define RSCAN0TXQSTS4LL (RSCAN0.TXQSTS4.UINT8[R_IO_LL])
+#define RSCAN0TXQSTS4LH (RSCAN0.TXQSTS4.UINT8[R_IO_LH])
+#define RSCAN0TXQSTS4H (RSCAN0.TXQSTS4.UINT16[R_IO_H])
+#define RSCAN0TXQSTS4HL (RSCAN0.TXQSTS4.UINT8[R_IO_HL])
+#define RSCAN0TXQSTS4HH (RSCAN0.TXQSTS4.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR0 (RSCAN0.TXQPCTR0.UINT32)
+#define RSCAN0TXQPCTR0L (RSCAN0.TXQPCTR0.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR0LL (RSCAN0.TXQPCTR0.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR0LH (RSCAN0.TXQPCTR0.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR0H (RSCAN0.TXQPCTR0.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR0HL (RSCAN0.TXQPCTR0.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR0HH (RSCAN0.TXQPCTR0.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR1 (RSCAN0.TXQPCTR1.UINT32)
+#define RSCAN0TXQPCTR1L (RSCAN0.TXQPCTR1.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR1LL (RSCAN0.TXQPCTR1.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR1LH (RSCAN0.TXQPCTR1.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR1H (RSCAN0.TXQPCTR1.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR1HL (RSCAN0.TXQPCTR1.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR1HH (RSCAN0.TXQPCTR1.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR2 (RSCAN0.TXQPCTR2.UINT32)
+#define RSCAN0TXQPCTR2L (RSCAN0.TXQPCTR2.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR2LL (RSCAN0.TXQPCTR2.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR2LH (RSCAN0.TXQPCTR2.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR2H (RSCAN0.TXQPCTR2.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR2HL (RSCAN0.TXQPCTR2.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR2HH (RSCAN0.TXQPCTR2.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR3 (RSCAN0.TXQPCTR3.UINT32)
+#define RSCAN0TXQPCTR3L (RSCAN0.TXQPCTR3.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR3LL (RSCAN0.TXQPCTR3.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR3LH (RSCAN0.TXQPCTR3.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR3H (RSCAN0.TXQPCTR3.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR3HL (RSCAN0.TXQPCTR3.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR3HH (RSCAN0.TXQPCTR3.UINT8[R_IO_HH])
+#define RSCAN0TXQPCTR4 (RSCAN0.TXQPCTR4.UINT32)
+#define RSCAN0TXQPCTR4L (RSCAN0.TXQPCTR4.UINT16[R_IO_L])
+#define RSCAN0TXQPCTR4LL (RSCAN0.TXQPCTR4.UINT8[R_IO_LL])
+#define RSCAN0TXQPCTR4LH (RSCAN0.TXQPCTR4.UINT8[R_IO_LH])
+#define RSCAN0TXQPCTR4H (RSCAN0.TXQPCTR4.UINT16[R_IO_H])
+#define RSCAN0TXQPCTR4HL (RSCAN0.TXQPCTR4.UINT8[R_IO_HL])
+#define RSCAN0TXQPCTR4HH (RSCAN0.TXQPCTR4.UINT8[R_IO_HH])
+#define RSCAN0THLCC0 (RSCAN0.THLCC0.UINT32)
+#define RSCAN0THLCC0L (RSCAN0.THLCC0.UINT16[R_IO_L])
+#define RSCAN0THLCC0LL (RSCAN0.THLCC0.UINT8[R_IO_LL])
+#define RSCAN0THLCC0LH (RSCAN0.THLCC0.UINT8[R_IO_LH])
+#define RSCAN0THLCC0H (RSCAN0.THLCC0.UINT16[R_IO_H])
+#define RSCAN0THLCC0HL (RSCAN0.THLCC0.UINT8[R_IO_HL])
+#define RSCAN0THLCC0HH (RSCAN0.THLCC0.UINT8[R_IO_HH])
+#define RSCAN0THLCC1 (RSCAN0.THLCC1.UINT32)
+#define RSCAN0THLCC1L (RSCAN0.THLCC1.UINT16[R_IO_L])
+#define RSCAN0THLCC1LL (RSCAN0.THLCC1.UINT8[R_IO_LL])
+#define RSCAN0THLCC1LH (RSCAN0.THLCC1.UINT8[R_IO_LH])
+#define RSCAN0THLCC1H (RSCAN0.THLCC1.UINT16[R_IO_H])
+#define RSCAN0THLCC1HL (RSCAN0.THLCC1.UINT8[R_IO_HL])
+#define RSCAN0THLCC1HH (RSCAN0.THLCC1.UINT8[R_IO_HH])
+#define RSCAN0THLCC2 (RSCAN0.THLCC2.UINT32)
+#define RSCAN0THLCC2L (RSCAN0.THLCC2.UINT16[R_IO_L])
+#define RSCAN0THLCC2LL (RSCAN0.THLCC2.UINT8[R_IO_LL])
+#define RSCAN0THLCC2LH (RSCAN0.THLCC2.UINT8[R_IO_LH])
+#define RSCAN0THLCC2H (RSCAN0.THLCC2.UINT16[R_IO_H])
+#define RSCAN0THLCC2HL (RSCAN0.THLCC2.UINT8[R_IO_HL])
+#define RSCAN0THLCC2HH (RSCAN0.THLCC2.UINT8[R_IO_HH])
+#define RSCAN0THLCC3 (RSCAN0.THLCC3.UINT32)
+#define RSCAN0THLCC3L (RSCAN0.THLCC3.UINT16[R_IO_L])
+#define RSCAN0THLCC3LL (RSCAN0.THLCC3.UINT8[R_IO_LL])
+#define RSCAN0THLCC3LH (RSCAN0.THLCC3.UINT8[R_IO_LH])
+#define RSCAN0THLCC3H (RSCAN0.THLCC3.UINT16[R_IO_H])
+#define RSCAN0THLCC3HL (RSCAN0.THLCC3.UINT8[R_IO_HL])
+#define RSCAN0THLCC3HH (RSCAN0.THLCC3.UINT8[R_IO_HH])
+#define RSCAN0THLCC4 (RSCAN0.THLCC4.UINT32)
+#define RSCAN0THLCC4L (RSCAN0.THLCC4.UINT16[R_IO_L])
+#define RSCAN0THLCC4LL (RSCAN0.THLCC4.UINT8[R_IO_LL])
+#define RSCAN0THLCC4LH (RSCAN0.THLCC4.UINT8[R_IO_LH])
+#define RSCAN0THLCC4H (RSCAN0.THLCC4.UINT16[R_IO_H])
+#define RSCAN0THLCC4HL (RSCAN0.THLCC4.UINT8[R_IO_HL])
+#define RSCAN0THLCC4HH (RSCAN0.THLCC4.UINT8[R_IO_HH])
+#define RSCAN0THLSTS0 (RSCAN0.THLSTS0.UINT32)
+#define RSCAN0THLSTS0L (RSCAN0.THLSTS0.UINT16[R_IO_L])
+#define RSCAN0THLSTS0LL (RSCAN0.THLSTS0.UINT8[R_IO_LL])
+#define RSCAN0THLSTS0LH (RSCAN0.THLSTS0.UINT8[R_IO_LH])
+#define RSCAN0THLSTS0H (RSCAN0.THLSTS0.UINT16[R_IO_H])
+#define RSCAN0THLSTS0HL (RSCAN0.THLSTS0.UINT8[R_IO_HL])
+#define RSCAN0THLSTS0HH (RSCAN0.THLSTS0.UINT8[R_IO_HH])
+#define RSCAN0THLSTS1 (RSCAN0.THLSTS1.UINT32)
+#define RSCAN0THLSTS1L (RSCAN0.THLSTS1.UINT16[R_IO_L])
+#define RSCAN0THLSTS1LL (RSCAN0.THLSTS1.UINT8[R_IO_LL])
+#define RSCAN0THLSTS1LH (RSCAN0.THLSTS1.UINT8[R_IO_LH])
+#define RSCAN0THLSTS1H (RSCAN0.THLSTS1.UINT16[R_IO_H])
+#define RSCAN0THLSTS1HL (RSCAN0.THLSTS1.UINT8[R_IO_HL])
+#define RSCAN0THLSTS1HH (RSCAN0.THLSTS1.UINT8[R_IO_HH])
+#define RSCAN0THLSTS2 (RSCAN0.THLSTS2.UINT32)
+#define RSCAN0THLSTS2L (RSCAN0.THLSTS2.UINT16[R_IO_L])
+#define RSCAN0THLSTS2LL (RSCAN0.THLSTS2.UINT8[R_IO_LL])
+#define RSCAN0THLSTS2LH (RSCAN0.THLSTS2.UINT8[R_IO_LH])
+#define RSCAN0THLSTS2H (RSCAN0.THLSTS2.UINT16[R_IO_H])
+#define RSCAN0THLSTS2HL (RSCAN0.THLSTS2.UINT8[R_IO_HL])
+#define RSCAN0THLSTS2HH (RSCAN0.THLSTS2.UINT8[R_IO_HH])
+#define RSCAN0THLSTS3 (RSCAN0.THLSTS3.UINT32)
+#define RSCAN0THLSTS3L (RSCAN0.THLSTS3.UINT16[R_IO_L])
+#define RSCAN0THLSTS3LL (RSCAN0.THLSTS3.UINT8[R_IO_LL])
+#define RSCAN0THLSTS3LH (RSCAN0.THLSTS3.UINT8[R_IO_LH])
+#define RSCAN0THLSTS3H (RSCAN0.THLSTS3.UINT16[R_IO_H])
+#define RSCAN0THLSTS3HL (RSCAN0.THLSTS3.UINT8[R_IO_HL])
+#define RSCAN0THLSTS3HH (RSCAN0.THLSTS3.UINT8[R_IO_HH])
+#define RSCAN0THLSTS4 (RSCAN0.THLSTS4.UINT32)
+#define RSCAN0THLSTS4L (RSCAN0.THLSTS4.UINT16[R_IO_L])
+#define RSCAN0THLSTS4LL (RSCAN0.THLSTS4.UINT8[R_IO_LL])
+#define RSCAN0THLSTS4LH (RSCAN0.THLSTS4.UINT8[R_IO_LH])
+#define RSCAN0THLSTS4H (RSCAN0.THLSTS4.UINT16[R_IO_H])
+#define RSCAN0THLSTS4HL (RSCAN0.THLSTS4.UINT8[R_IO_HL])
+#define RSCAN0THLSTS4HH (RSCAN0.THLSTS4.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR0 (RSCAN0.THLPCTR0.UINT32)
+#define RSCAN0THLPCTR0L (RSCAN0.THLPCTR0.UINT16[R_IO_L])
+#define RSCAN0THLPCTR0LL (RSCAN0.THLPCTR0.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR0LH (RSCAN0.THLPCTR0.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR0H (RSCAN0.THLPCTR0.UINT16[R_IO_H])
+#define RSCAN0THLPCTR0HL (RSCAN0.THLPCTR0.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR0HH (RSCAN0.THLPCTR0.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR1 (RSCAN0.THLPCTR1.UINT32)
+#define RSCAN0THLPCTR1L (RSCAN0.THLPCTR1.UINT16[R_IO_L])
+#define RSCAN0THLPCTR1LL (RSCAN0.THLPCTR1.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR1LH (RSCAN0.THLPCTR1.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR1H (RSCAN0.THLPCTR1.UINT16[R_IO_H])
+#define RSCAN0THLPCTR1HL (RSCAN0.THLPCTR1.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR1HH (RSCAN0.THLPCTR1.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR2 (RSCAN0.THLPCTR2.UINT32)
+#define RSCAN0THLPCTR2L (RSCAN0.THLPCTR2.UINT16[R_IO_L])
+#define RSCAN0THLPCTR2LL (RSCAN0.THLPCTR2.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR2LH (RSCAN0.THLPCTR2.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR2H (RSCAN0.THLPCTR2.UINT16[R_IO_H])
+#define RSCAN0THLPCTR2HL (RSCAN0.THLPCTR2.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR2HH (RSCAN0.THLPCTR2.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR3 (RSCAN0.THLPCTR3.UINT32)
+#define RSCAN0THLPCTR3L (RSCAN0.THLPCTR3.UINT16[R_IO_L])
+#define RSCAN0THLPCTR3LL (RSCAN0.THLPCTR3.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR3LH (RSCAN0.THLPCTR3.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR3H (RSCAN0.THLPCTR3.UINT16[R_IO_H])
+#define RSCAN0THLPCTR3HL (RSCAN0.THLPCTR3.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR3HH (RSCAN0.THLPCTR3.UINT8[R_IO_HH])
+#define RSCAN0THLPCTR4 (RSCAN0.THLPCTR4.UINT32)
+#define RSCAN0THLPCTR4L (RSCAN0.THLPCTR4.UINT16[R_IO_L])
+#define RSCAN0THLPCTR4LL (RSCAN0.THLPCTR4.UINT8[R_IO_LL])
+#define RSCAN0THLPCTR4LH (RSCAN0.THLPCTR4.UINT8[R_IO_LH])
+#define RSCAN0THLPCTR4H (RSCAN0.THLPCTR4.UINT16[R_IO_H])
+#define RSCAN0THLPCTR4HL (RSCAN0.THLPCTR4.UINT8[R_IO_HL])
+#define RSCAN0THLPCTR4HH (RSCAN0.THLPCTR4.UINT8[R_IO_HH])
+#define RSCAN0GTINTSTS0 (RSCAN0.GTINTSTS0.UINT32)
+#define RSCAN0GTINTSTS0L (RSCAN0.GTINTSTS0.UINT16[R_IO_L])
+#define RSCAN0GTINTSTS0LL (RSCAN0.GTINTSTS0.UINT8[R_IO_LL])
+#define RSCAN0GTINTSTS0LH (RSCAN0.GTINTSTS0.UINT8[R_IO_LH])
+#define RSCAN0GTINTSTS0H (RSCAN0.GTINTSTS0.UINT16[R_IO_H])
+#define RSCAN0GTINTSTS0HL (RSCAN0.GTINTSTS0.UINT8[R_IO_HL])
+#define RSCAN0GTINTSTS0HH (RSCAN0.GTINTSTS0.UINT8[R_IO_HH])
+#define RSCAN0GTINTSTS1 (RSCAN0.GTINTSTS1.UINT32)
+#define RSCAN0GTINTSTS1L (RSCAN0.GTINTSTS1.UINT16[R_IO_L])
+#define RSCAN0GTINTSTS1LL (RSCAN0.GTINTSTS1.UINT8[R_IO_LL])
+#define RSCAN0GTINTSTS1LH (RSCAN0.GTINTSTS1.UINT8[R_IO_LH])
+#define RSCAN0GTINTSTS1H (RSCAN0.GTINTSTS1.UINT16[R_IO_H])
+#define RSCAN0GTINTSTS1HL (RSCAN0.GTINTSTS1.UINT8[R_IO_HL])
+#define RSCAN0GTINTSTS1HH (RSCAN0.GTINTSTS1.UINT8[R_IO_HH])
+#define RSCAN0GTSTCFG (RSCAN0.GTSTCFG.UINT32)
+#define RSCAN0GTSTCFGL (RSCAN0.GTSTCFG.UINT16[R_IO_L])
+#define RSCAN0GTSTCFGLL (RSCAN0.GTSTCFG.UINT8[R_IO_LL])
+#define RSCAN0GTSTCFGLH (RSCAN0.GTSTCFG.UINT8[R_IO_LH])
+#define RSCAN0GTSTCFGH (RSCAN0.GTSTCFG.UINT16[R_IO_H])
+#define RSCAN0GTSTCFGHL (RSCAN0.GTSTCFG.UINT8[R_IO_HL])
+#define RSCAN0GTSTCFGHH (RSCAN0.GTSTCFG.UINT8[R_IO_HH])
+#define RSCAN0GTSTCTR (RSCAN0.GTSTCTR.UINT32)
+#define RSCAN0GTSTCTRL (RSCAN0.GTSTCTR.UINT16[R_IO_L])
+#define RSCAN0GTSTCTRLL (RSCAN0.GTSTCTR.UINT8[R_IO_LL])
+#define RSCAN0GTSTCTRLH (RSCAN0.GTSTCTR.UINT8[R_IO_LH])
+#define RSCAN0GTSTCTRH (RSCAN0.GTSTCTR.UINT16[R_IO_H])
+#define RSCAN0GTSTCTRHL (RSCAN0.GTSTCTR.UINT8[R_IO_HL])
+#define RSCAN0GTSTCTRHH (RSCAN0.GTSTCTR.UINT8[R_IO_HH])
+#define RSCAN0GLOCKK (RSCAN0.GLOCKK.UINT32)
+#define RSCAN0GLOCKKL (RSCAN0.GLOCKK.UINT16[R_IO_L])
+#define RSCAN0GLOCKKH (RSCAN0.GLOCKK.UINT16[R_IO_H])
+#define RSCAN0GAFLID0 (RSCAN0.GAFLID0.UINT32)
+#define RSCAN0GAFLID0L (RSCAN0.GAFLID0.UINT16[R_IO_L])
+#define RSCAN0GAFLID0LL (RSCAN0.GAFLID0.UINT8[R_IO_LL])
+#define RSCAN0GAFLID0LH (RSCAN0.GAFLID0.UINT8[R_IO_LH])
+#define RSCAN0GAFLID0H (RSCAN0.GAFLID0.UINT16[R_IO_H])
+#define RSCAN0GAFLID0HL (RSCAN0.GAFLID0.UINT8[R_IO_HL])
+#define RSCAN0GAFLID0HH (RSCAN0.GAFLID0.UINT8[R_IO_HH])
+#define RSCAN0GAFLM0 (RSCAN0.GAFLM0.UINT32)
+#define RSCAN0GAFLM0L (RSCAN0.GAFLM0.UINT16[R_IO_L])
+#define RSCAN0GAFLM0LL (RSCAN0.GAFLM0.UINT8[R_IO_LL])
+#define RSCAN0GAFLM0LH (RSCAN0.GAFLM0.UINT8[R_IO_LH])
+#define RSCAN0GAFLM0H (RSCAN0.GAFLM0.UINT16[R_IO_H])
+#define RSCAN0GAFLM0HL (RSCAN0.GAFLM0.UINT8[R_IO_HL])
+#define RSCAN0GAFLM0HH (RSCAN0.GAFLM0.UINT8[R_IO_HH])
+#define RSCAN0GAFLP00 (RSCAN0.GAFLP00.UINT32)
+#define RSCAN0GAFLP00L (RSCAN0.GAFLP00.UINT16[R_IO_L])
+#define RSCAN0GAFLP00LL (RSCAN0.GAFLP00.UINT8[R_IO_LL])
+#define RSCAN0GAFLP00LH (RSCAN0.GAFLP00.UINT8[R_IO_LH])
+#define RSCAN0GAFLP00H (RSCAN0.GAFLP00.UINT16[R_IO_H])
+#define RSCAN0GAFLP00HL (RSCAN0.GAFLP00.UINT8[R_IO_HL])
+#define RSCAN0GAFLP00HH (RSCAN0.GAFLP00.UINT8[R_IO_HH])
+#define RSCAN0GAFLP10 (RSCAN0.GAFLP10.UINT32)
+#define RSCAN0GAFLP10L (RSCAN0.GAFLP10.UINT16[R_IO_L])
+#define RSCAN0GAFLP10LL (RSCAN0.GAFLP10.UINT8[R_IO_LL])
+#define RSCAN0GAFLP10LH (RSCAN0.GAFLP10.UINT8[R_IO_LH])
+#define RSCAN0GAFLP10H (RSCAN0.GAFLP10.UINT16[R_IO_H])
+#define RSCAN0GAFLP10HL (RSCAN0.GAFLP10.UINT8[R_IO_HL])
+#define RSCAN0GAFLP10HH (RSCAN0.GAFLP10.UINT8[R_IO_HH])
+#define RSCAN0GAFLID1 (RSCAN0.GAFLID1.UINT32)
+#define RSCAN0GAFLID1L (RSCAN0.GAFLID1.UINT16[R_IO_L])
+#define RSCAN0GAFLID1LL (RSCAN0.GAFLID1.UINT8[R_IO_LL])
+#define RSCAN0GAFLID1LH (RSCAN0.GAFLID1.UINT8[R_IO_LH])
+#define RSCAN0GAFLID1H (RSCAN0.GAFLID1.UINT16[R_IO_H])
+#define RSCAN0GAFLID1HL (RSCAN0.GAFLID1.UINT8[R_IO_HL])
+#define RSCAN0GAFLID1HH (RSCAN0.GAFLID1.UINT8[R_IO_HH])
+#define RSCAN0GAFLM1 (RSCAN0.GAFLM1.UINT32)
+#define RSCAN0GAFLM1L (RSCAN0.GAFLM1.UINT16[R_IO_L])
+#define RSCAN0GAFLM1LL (RSCAN0.GAFLM1.UINT8[R_IO_LL])
+#define RSCAN0GAFLM1LH (RSCAN0.GAFLM1.UINT8[R_IO_LH])
+#define RSCAN0GAFLM1H (RSCAN0.GAFLM1.UINT16[R_IO_H])
+#define RSCAN0GAFLM1HL (RSCAN0.GAFLM1.UINT8[R_IO_HL])
+#define RSCAN0GAFLM1HH (RSCAN0.GAFLM1.UINT8[R_IO_HH])
+#define RSCAN0GAFLP01 (RSCAN0.GAFLP01.UINT32)
+#define RSCAN0GAFLP01L (RSCAN0.GAFLP01.UINT16[R_IO_L])
+#define RSCAN0GAFLP01LL (RSCAN0.GAFLP01.UINT8[R_IO_LL])
+#define RSCAN0GAFLP01LH (RSCAN0.GAFLP01.UINT8[R_IO_LH])
+#define RSCAN0GAFLP01H (RSCAN0.GAFLP01.UINT16[R_IO_H])
+#define RSCAN0GAFLP01HL (RSCAN0.GAFLP01.UINT8[R_IO_HL])
+#define RSCAN0GAFLP01HH (RSCAN0.GAFLP01.UINT8[R_IO_HH])
+#define RSCAN0GAFLP11 (RSCAN0.GAFLP11.UINT32)
+#define RSCAN0GAFLP11L (RSCAN0.GAFLP11.UINT16[R_IO_L])
+#define RSCAN0GAFLP11LL (RSCAN0.GAFLP11.UINT8[R_IO_LL])
+#define RSCAN0GAFLP11LH (RSCAN0.GAFLP11.UINT8[R_IO_LH])
+#define RSCAN0GAFLP11H (RSCAN0.GAFLP11.UINT16[R_IO_H])
+#define RSCAN0GAFLP11HL (RSCAN0.GAFLP11.UINT8[R_IO_HL])
+#define RSCAN0GAFLP11HH (RSCAN0.GAFLP11.UINT8[R_IO_HH])
+#define RSCAN0GAFLID2 (RSCAN0.GAFLID2.UINT32)
+#define RSCAN0GAFLID2L (RSCAN0.GAFLID2.UINT16[R_IO_L])
+#define RSCAN0GAFLID2LL (RSCAN0.GAFLID2.UINT8[R_IO_LL])
+#define RSCAN0GAFLID2LH (RSCAN0.GAFLID2.UINT8[R_IO_LH])
+#define RSCAN0GAFLID2H (RSCAN0.GAFLID2.UINT16[R_IO_H])
+#define RSCAN0GAFLID2HL (RSCAN0.GAFLID2.UINT8[R_IO_HL])
+#define RSCAN0GAFLID2HH (RSCAN0.GAFLID2.UINT8[R_IO_HH])
+#define RSCAN0GAFLM2 (RSCAN0.GAFLM2.UINT32)
+#define RSCAN0GAFLM2L (RSCAN0.GAFLM2.UINT16[R_IO_L])
+#define RSCAN0GAFLM2LL (RSCAN0.GAFLM2.UINT8[R_IO_LL])
+#define RSCAN0GAFLM2LH (RSCAN0.GAFLM2.UINT8[R_IO_LH])
+#define RSCAN0GAFLM2H (RSCAN0.GAFLM2.UINT16[R_IO_H])
+#define RSCAN0GAFLM2HL (RSCAN0.GAFLM2.UINT8[R_IO_HL])
+#define RSCAN0GAFLM2HH (RSCAN0.GAFLM2.UINT8[R_IO_HH])
+#define RSCAN0GAFLP02 (RSCAN0.GAFLP02.UINT32)
+#define RSCAN0GAFLP02L (RSCAN0.GAFLP02.UINT16[R_IO_L])
+#define RSCAN0GAFLP02LL (RSCAN0.GAFLP02.UINT8[R_IO_LL])
+#define RSCAN0GAFLP02LH (RSCAN0.GAFLP02.UINT8[R_IO_LH])
+#define RSCAN0GAFLP02H (RSCAN0.GAFLP02.UINT16[R_IO_H])
+#define RSCAN0GAFLP02HL (RSCAN0.GAFLP02.UINT8[R_IO_HL])
+#define RSCAN0GAFLP02HH (RSCAN0.GAFLP02.UINT8[R_IO_HH])
+#define RSCAN0GAFLP12 (RSCAN0.GAFLP12.UINT32)
+#define RSCAN0GAFLP12L (RSCAN0.GAFLP12.UINT16[R_IO_L])
+#define RSCAN0GAFLP12LL (RSCAN0.GAFLP12.UINT8[R_IO_LL])
+#define RSCAN0GAFLP12LH (RSCAN0.GAFLP12.UINT8[R_IO_LH])
+#define RSCAN0GAFLP12H (RSCAN0.GAFLP12.UINT16[R_IO_H])
+#define RSCAN0GAFLP12HL (RSCAN0.GAFLP12.UINT8[R_IO_HL])
+#define RSCAN0GAFLP12HH (RSCAN0.GAFLP12.UINT8[R_IO_HH])
+#define RSCAN0GAFLID3 (RSCAN0.GAFLID3.UINT32)
+#define RSCAN0GAFLID3L (RSCAN0.GAFLID3.UINT16[R_IO_L])
+#define RSCAN0GAFLID3LL (RSCAN0.GAFLID3.UINT8[R_IO_LL])
+#define RSCAN0GAFLID3LH (RSCAN0.GAFLID3.UINT8[R_IO_LH])
+#define RSCAN0GAFLID3H (RSCAN0.GAFLID3.UINT16[R_IO_H])
+#define RSCAN0GAFLID3HL (RSCAN0.GAFLID3.UINT8[R_IO_HL])
+#define RSCAN0GAFLID3HH (RSCAN0.GAFLID3.UINT8[R_IO_HH])
+#define RSCAN0GAFLM3 (RSCAN0.GAFLM3.UINT32)
+#define RSCAN0GAFLM3L (RSCAN0.GAFLM3.UINT16[R_IO_L])
+#define RSCAN0GAFLM3LL (RSCAN0.GAFLM3.UINT8[R_IO_LL])
+#define RSCAN0GAFLM3LH (RSCAN0.GAFLM3.UINT8[R_IO_LH])
+#define RSCAN0GAFLM3H (RSCAN0.GAFLM3.UINT16[R_IO_H])
+#define RSCAN0GAFLM3HL (RSCAN0.GAFLM3.UINT8[R_IO_HL])
+#define RSCAN0GAFLM3HH (RSCAN0.GAFLM3.UINT8[R_IO_HH])
+#define RSCAN0GAFLP03 (RSCAN0.GAFLP03.UINT32)
+#define RSCAN0GAFLP03L (RSCAN0.GAFLP03.UINT16[R_IO_L])
+#define RSCAN0GAFLP03LL (RSCAN0.GAFLP03.UINT8[R_IO_LL])
+#define RSCAN0GAFLP03LH (RSCAN0.GAFLP03.UINT8[R_IO_LH])
+#define RSCAN0GAFLP03H (RSCAN0.GAFLP03.UINT16[R_IO_H])
+#define RSCAN0GAFLP03HL (RSCAN0.GAFLP03.UINT8[R_IO_HL])
+#define RSCAN0GAFLP03HH (RSCAN0.GAFLP03.UINT8[R_IO_HH])
+#define RSCAN0GAFLP13 (RSCAN0.GAFLP13.UINT32)
+#define RSCAN0GAFLP13L (RSCAN0.GAFLP13.UINT16[R_IO_L])
+#define RSCAN0GAFLP13LL (RSCAN0.GAFLP13.UINT8[R_IO_LL])
+#define RSCAN0GAFLP13LH (RSCAN0.GAFLP13.UINT8[R_IO_LH])
+#define RSCAN0GAFLP13H (RSCAN0.GAFLP13.UINT16[R_IO_H])
+#define RSCAN0GAFLP13HL (RSCAN0.GAFLP13.UINT8[R_IO_HL])
+#define RSCAN0GAFLP13HH (RSCAN0.GAFLP13.UINT8[R_IO_HH])
+#define RSCAN0GAFLID4 (RSCAN0.GAFLID4.UINT32)
+#define RSCAN0GAFLID4L (RSCAN0.GAFLID4.UINT16[R_IO_L])
+#define RSCAN0GAFLID4LL (RSCAN0.GAFLID4.UINT8[R_IO_LL])
+#define RSCAN0GAFLID4LH (RSCAN0.GAFLID4.UINT8[R_IO_LH])
+#define RSCAN0GAFLID4H (RSCAN0.GAFLID4.UINT16[R_IO_H])
+#define RSCAN0GAFLID4HL (RSCAN0.GAFLID4.UINT8[R_IO_HL])
+#define RSCAN0GAFLID4HH (RSCAN0.GAFLID4.UINT8[R_IO_HH])
+#define RSCAN0GAFLM4 (RSCAN0.GAFLM4.UINT32)
+#define RSCAN0GAFLM4L (RSCAN0.GAFLM4.UINT16[R_IO_L])
+#define RSCAN0GAFLM4LL (RSCAN0.GAFLM4.UINT8[R_IO_LL])
+#define RSCAN0GAFLM4LH (RSCAN0.GAFLM4.UINT8[R_IO_LH])
+#define RSCAN0GAFLM4H (RSCAN0.GAFLM4.UINT16[R_IO_H])
+#define RSCAN0GAFLM4HL (RSCAN0.GAFLM4.UINT8[R_IO_HL])
+#define RSCAN0GAFLM4HH (RSCAN0.GAFLM4.UINT8[R_IO_HH])
+#define RSCAN0GAFLP04 (RSCAN0.GAFLP04.UINT32)
+#define RSCAN0GAFLP04L (RSCAN0.GAFLP04.UINT16[R_IO_L])
+#define RSCAN0GAFLP04LL (RSCAN0.GAFLP04.UINT8[R_IO_LL])
+#define RSCAN0GAFLP04LH (RSCAN0.GAFLP04.UINT8[R_IO_LH])
+#define RSCAN0GAFLP04H (RSCAN0.GAFLP04.UINT16[R_IO_H])
+#define RSCAN0GAFLP04HL (RSCAN0.GAFLP04.UINT8[R_IO_HL])
+#define RSCAN0GAFLP04HH (RSCAN0.GAFLP04.UINT8[R_IO_HH])
+#define RSCAN0GAFLP14 (RSCAN0.GAFLP14.UINT32)
+#define RSCAN0GAFLP14L (RSCAN0.GAFLP14.UINT16[R_IO_L])
+#define RSCAN0GAFLP14LL (RSCAN0.GAFLP14.UINT8[R_IO_LL])
+#define RSCAN0GAFLP14LH (RSCAN0.GAFLP14.UINT8[R_IO_LH])
+#define RSCAN0GAFLP14H (RSCAN0.GAFLP14.UINT16[R_IO_H])
+#define RSCAN0GAFLP14HL (RSCAN0.GAFLP14.UINT8[R_IO_HL])
+#define RSCAN0GAFLP14HH (RSCAN0.GAFLP14.UINT8[R_IO_HH])
+#define RSCAN0GAFLID5 (RSCAN0.GAFLID5.UINT32)
+#define RSCAN0GAFLID5L (RSCAN0.GAFLID5.UINT16[R_IO_L])
+#define RSCAN0GAFLID5LL (RSCAN0.GAFLID5.UINT8[R_IO_LL])
+#define RSCAN0GAFLID5LH (RSCAN0.GAFLID5.UINT8[R_IO_LH])
+#define RSCAN0GAFLID5H (RSCAN0.GAFLID5.UINT16[R_IO_H])
+#define RSCAN0GAFLID5HL (RSCAN0.GAFLID5.UINT8[R_IO_HL])
+#define RSCAN0GAFLID5HH (RSCAN0.GAFLID5.UINT8[R_IO_HH])
+#define RSCAN0GAFLM5 (RSCAN0.GAFLM5.UINT32)
+#define RSCAN0GAFLM5L (RSCAN0.GAFLM5.UINT16[R_IO_L])
+#define RSCAN0GAFLM5LL (RSCAN0.GAFLM5.UINT8[R_IO_LL])
+#define RSCAN0GAFLM5LH (RSCAN0.GAFLM5.UINT8[R_IO_LH])
+#define RSCAN0GAFLM5H (RSCAN0.GAFLM5.UINT16[R_IO_H])
+#define RSCAN0GAFLM5HL (RSCAN0.GAFLM5.UINT8[R_IO_HL])
+#define RSCAN0GAFLM5HH (RSCAN0.GAFLM5.UINT8[R_IO_HH])
+#define RSCAN0GAFLP05 (RSCAN0.GAFLP05.UINT32)
+#define RSCAN0GAFLP05L (RSCAN0.GAFLP05.UINT16[R_IO_L])
+#define RSCAN0GAFLP05LL (RSCAN0.GAFLP05.UINT8[R_IO_LL])
+#define RSCAN0GAFLP05LH (RSCAN0.GAFLP05.UINT8[R_IO_LH])
+#define RSCAN0GAFLP05H (RSCAN0.GAFLP05.UINT16[R_IO_H])
+#define RSCAN0GAFLP05HL (RSCAN0.GAFLP05.UINT8[R_IO_HL])
+#define RSCAN0GAFLP05HH (RSCAN0.GAFLP05.UINT8[R_IO_HH])
+#define RSCAN0GAFLP15 (RSCAN0.GAFLP15.UINT32)
+#define RSCAN0GAFLP15L (RSCAN0.GAFLP15.UINT16[R_IO_L])
+#define RSCAN0GAFLP15LL (RSCAN0.GAFLP15.UINT8[R_IO_LL])
+#define RSCAN0GAFLP15LH (RSCAN0.GAFLP15.UINT8[R_IO_LH])
+#define RSCAN0GAFLP15H (RSCAN0.GAFLP15.UINT16[R_IO_H])
+#define RSCAN0GAFLP15HL (RSCAN0.GAFLP15.UINT8[R_IO_HL])
+#define RSCAN0GAFLP15HH (RSCAN0.GAFLP15.UINT8[R_IO_HH])
+#define RSCAN0GAFLID6 (RSCAN0.GAFLID6.UINT32)
+#define RSCAN0GAFLID6L (RSCAN0.GAFLID6.UINT16[R_IO_L])
+#define RSCAN0GAFLID6LL (RSCAN0.GAFLID6.UINT8[R_IO_LL])
+#define RSCAN0GAFLID6LH (RSCAN0.GAFLID6.UINT8[R_IO_LH])
+#define RSCAN0GAFLID6H (RSCAN0.GAFLID6.UINT16[R_IO_H])
+#define RSCAN0GAFLID6HL (RSCAN0.GAFLID6.UINT8[R_IO_HL])
+#define RSCAN0GAFLID6HH (RSCAN0.GAFLID6.UINT8[R_IO_HH])
+#define RSCAN0GAFLM6 (RSCAN0.GAFLM6.UINT32)
+#define RSCAN0GAFLM6L (RSCAN0.GAFLM6.UINT16[R_IO_L])
+#define RSCAN0GAFLM6LL (RSCAN0.GAFLM6.UINT8[R_IO_LL])
+#define RSCAN0GAFLM6LH (RSCAN0.GAFLM6.UINT8[R_IO_LH])
+#define RSCAN0GAFLM6H (RSCAN0.GAFLM6.UINT16[R_IO_H])
+#define RSCAN0GAFLM6HL (RSCAN0.GAFLM6.UINT8[R_IO_HL])
+#define RSCAN0GAFLM6HH (RSCAN0.GAFLM6.UINT8[R_IO_HH])
+#define RSCAN0GAFLP06 (RSCAN0.GAFLP06.UINT32)
+#define RSCAN0GAFLP06L (RSCAN0.GAFLP06.UINT16[R_IO_L])
+#define RSCAN0GAFLP06LL (RSCAN0.GAFLP06.UINT8[R_IO_LL])
+#define RSCAN0GAFLP06LH (RSCAN0.GAFLP06.UINT8[R_IO_LH])
+#define RSCAN0GAFLP06H (RSCAN0.GAFLP06.UINT16[R_IO_H])
+#define RSCAN0GAFLP06HL (RSCAN0.GAFLP06.UINT8[R_IO_HL])
+#define RSCAN0GAFLP06HH (RSCAN0.GAFLP06.UINT8[R_IO_HH])
+#define RSCAN0GAFLP16 (RSCAN0.GAFLP16.UINT32)
+#define RSCAN0GAFLP16L (RSCAN0.GAFLP16.UINT16[R_IO_L])
+#define RSCAN0GAFLP16LL (RSCAN0.GAFLP16.UINT8[R_IO_LL])
+#define RSCAN0GAFLP16LH (RSCAN0.GAFLP16.UINT8[R_IO_LH])
+#define RSCAN0GAFLP16H (RSCAN0.GAFLP16.UINT16[R_IO_H])
+#define RSCAN0GAFLP16HL (RSCAN0.GAFLP16.UINT8[R_IO_HL])
+#define RSCAN0GAFLP16HH (RSCAN0.GAFLP16.UINT8[R_IO_HH])
+#define RSCAN0GAFLID7 (RSCAN0.GAFLID7.UINT32)
+#define RSCAN0GAFLID7L (RSCAN0.GAFLID7.UINT16[R_IO_L])
+#define RSCAN0GAFLID7LL (RSCAN0.GAFLID7.UINT8[R_IO_LL])
+#define RSCAN0GAFLID7LH (RSCAN0.GAFLID7.UINT8[R_IO_LH])
+#define RSCAN0GAFLID7H (RSCAN0.GAFLID7.UINT16[R_IO_H])
+#define RSCAN0GAFLID7HL (RSCAN0.GAFLID7.UINT8[R_IO_HL])
+#define RSCAN0GAFLID7HH (RSCAN0.GAFLID7.UINT8[R_IO_HH])
+#define RSCAN0GAFLM7 (RSCAN0.GAFLM7.UINT32)
+#define RSCAN0GAFLM7L (RSCAN0.GAFLM7.UINT16[R_IO_L])
+#define RSCAN0GAFLM7LL (RSCAN0.GAFLM7.UINT8[R_IO_LL])
+#define RSCAN0GAFLM7LH (RSCAN0.GAFLM7.UINT8[R_IO_LH])
+#define RSCAN0GAFLM7H (RSCAN0.GAFLM7.UINT16[R_IO_H])
+#define RSCAN0GAFLM7HL (RSCAN0.GAFLM7.UINT8[R_IO_HL])
+#define RSCAN0GAFLM7HH (RSCAN0.GAFLM7.UINT8[R_IO_HH])
+#define RSCAN0GAFLP07 (RSCAN0.GAFLP07.UINT32)
+#define RSCAN0GAFLP07L (RSCAN0.GAFLP07.UINT16[R_IO_L])
+#define RSCAN0GAFLP07LL (RSCAN0.GAFLP07.UINT8[R_IO_LL])
+#define RSCAN0GAFLP07LH (RSCAN0.GAFLP07.UINT8[R_IO_LH])
+#define RSCAN0GAFLP07H (RSCAN0.GAFLP07.UINT16[R_IO_H])
+#define RSCAN0GAFLP07HL (RSCAN0.GAFLP07.UINT8[R_IO_HL])
+#define RSCAN0GAFLP07HH (RSCAN0.GAFLP07.UINT8[R_IO_HH])
+#define RSCAN0GAFLP17 (RSCAN0.GAFLP17.UINT32)
+#define RSCAN0GAFLP17L (RSCAN0.GAFLP17.UINT16[R_IO_L])
+#define RSCAN0GAFLP17LL (RSCAN0.GAFLP17.UINT8[R_IO_LL])
+#define RSCAN0GAFLP17LH (RSCAN0.GAFLP17.UINT8[R_IO_LH])
+#define RSCAN0GAFLP17H (RSCAN0.GAFLP17.UINT16[R_IO_H])
+#define RSCAN0GAFLP17HL (RSCAN0.GAFLP17.UINT8[R_IO_HL])
+#define RSCAN0GAFLP17HH (RSCAN0.GAFLP17.UINT8[R_IO_HH])
+#define RSCAN0GAFLID8 (RSCAN0.GAFLID8.UINT32)
+#define RSCAN0GAFLID8L (RSCAN0.GAFLID8.UINT16[R_IO_L])
+#define RSCAN0GAFLID8LL (RSCAN0.GAFLID8.UINT8[R_IO_LL])
+#define RSCAN0GAFLID8LH (RSCAN0.GAFLID8.UINT8[R_IO_LH])
+#define RSCAN0GAFLID8H (RSCAN0.GAFLID8.UINT16[R_IO_H])
+#define RSCAN0GAFLID8HL (RSCAN0.GAFLID8.UINT8[R_IO_HL])
+#define RSCAN0GAFLID8HH (RSCAN0.GAFLID8.UINT8[R_IO_HH])
+#define RSCAN0GAFLM8 (RSCAN0.GAFLM8.UINT32)
+#define RSCAN0GAFLM8L (RSCAN0.GAFLM8.UINT16[R_IO_L])
+#define RSCAN0GAFLM8LL (RSCAN0.GAFLM8.UINT8[R_IO_LL])
+#define RSCAN0GAFLM8LH (RSCAN0.GAFLM8.UINT8[R_IO_LH])
+#define RSCAN0GAFLM8H (RSCAN0.GAFLM8.UINT16[R_IO_H])
+#define RSCAN0GAFLM8HL (RSCAN0.GAFLM8.UINT8[R_IO_HL])
+#define RSCAN0GAFLM8HH (RSCAN0.GAFLM8.UINT8[R_IO_HH])
+#define RSCAN0GAFLP08 (RSCAN0.GAFLP08.UINT32)
+#define RSCAN0GAFLP08L (RSCAN0.GAFLP08.UINT16[R_IO_L])
+#define RSCAN0GAFLP08LL (RSCAN0.GAFLP08.UINT8[R_IO_LL])
+#define RSCAN0GAFLP08LH (RSCAN0.GAFLP08.UINT8[R_IO_LH])
+#define RSCAN0GAFLP08H (RSCAN0.GAFLP08.UINT16[R_IO_H])
+#define RSCAN0GAFLP08HL (RSCAN0.GAFLP08.UINT8[R_IO_HL])
+#define RSCAN0GAFLP08HH (RSCAN0.GAFLP08.UINT8[R_IO_HH])
+#define RSCAN0GAFLP18 (RSCAN0.GAFLP18.UINT32)
+#define RSCAN0GAFLP18L (RSCAN0.GAFLP18.UINT16[R_IO_L])
+#define RSCAN0GAFLP18LL (RSCAN0.GAFLP18.UINT8[R_IO_LL])
+#define RSCAN0GAFLP18LH (RSCAN0.GAFLP18.UINT8[R_IO_LH])
+#define RSCAN0GAFLP18H (RSCAN0.GAFLP18.UINT16[R_IO_H])
+#define RSCAN0GAFLP18HL (RSCAN0.GAFLP18.UINT8[R_IO_HL])
+#define RSCAN0GAFLP18HH (RSCAN0.GAFLP18.UINT8[R_IO_HH])
+#define RSCAN0GAFLID9 (RSCAN0.GAFLID9.UINT32)
+#define RSCAN0GAFLID9L (RSCAN0.GAFLID9.UINT16[R_IO_L])
+#define RSCAN0GAFLID9LL (RSCAN0.GAFLID9.UINT8[R_IO_LL])
+#define RSCAN0GAFLID9LH (RSCAN0.GAFLID9.UINT8[R_IO_LH])
+#define RSCAN0GAFLID9H (RSCAN0.GAFLID9.UINT16[R_IO_H])
+#define RSCAN0GAFLID9HL (RSCAN0.GAFLID9.UINT8[R_IO_HL])
+#define RSCAN0GAFLID9HH (RSCAN0.GAFLID9.UINT8[R_IO_HH])
+#define RSCAN0GAFLM9 (RSCAN0.GAFLM9.UINT32)
+#define RSCAN0GAFLM9L (RSCAN0.GAFLM9.UINT16[R_IO_L])
+#define RSCAN0GAFLM9LL (RSCAN0.GAFLM9.UINT8[R_IO_LL])
+#define RSCAN0GAFLM9LH (RSCAN0.GAFLM9.UINT8[R_IO_LH])
+#define RSCAN0GAFLM9H (RSCAN0.GAFLM9.UINT16[R_IO_H])
+#define RSCAN0GAFLM9HL (RSCAN0.GAFLM9.UINT8[R_IO_HL])
+#define RSCAN0GAFLM9HH (RSCAN0.GAFLM9.UINT8[R_IO_HH])
+#define RSCAN0GAFLP09 (RSCAN0.GAFLP09.UINT32)
+#define RSCAN0GAFLP09L (RSCAN0.GAFLP09.UINT16[R_IO_L])
+#define RSCAN0GAFLP09LL (RSCAN0.GAFLP09.UINT8[R_IO_LL])
+#define RSCAN0GAFLP09LH (RSCAN0.GAFLP09.UINT8[R_IO_LH])
+#define RSCAN0GAFLP09H (RSCAN0.GAFLP09.UINT16[R_IO_H])
+#define RSCAN0GAFLP09HL (RSCAN0.GAFLP09.UINT8[R_IO_HL])
+#define RSCAN0GAFLP09HH (RSCAN0.GAFLP09.UINT8[R_IO_HH])
+#define RSCAN0GAFLP19 (RSCAN0.GAFLP19.UINT32)
+#define RSCAN0GAFLP19L (RSCAN0.GAFLP19.UINT16[R_IO_L])
+#define RSCAN0GAFLP19LL (RSCAN0.GAFLP19.UINT8[R_IO_LL])
+#define RSCAN0GAFLP19LH (RSCAN0.GAFLP19.UINT8[R_IO_LH])
+#define RSCAN0GAFLP19H (RSCAN0.GAFLP19.UINT16[R_IO_H])
+#define RSCAN0GAFLP19HL (RSCAN0.GAFLP19.UINT8[R_IO_HL])
+#define RSCAN0GAFLP19HH (RSCAN0.GAFLP19.UINT8[R_IO_HH])
+#define RSCAN0GAFLID10 (RSCAN0.GAFLID10.UINT32)
+#define RSCAN0GAFLID10L (RSCAN0.GAFLID10.UINT16[R_IO_L])
+#define RSCAN0GAFLID10LL (RSCAN0.GAFLID10.UINT8[R_IO_LL])
+#define RSCAN0GAFLID10LH (RSCAN0.GAFLID10.UINT8[R_IO_LH])
+#define RSCAN0GAFLID10H (RSCAN0.GAFLID10.UINT16[R_IO_H])
+#define RSCAN0GAFLID10HL (RSCAN0.GAFLID10.UINT8[R_IO_HL])
+#define RSCAN0GAFLID10HH (RSCAN0.GAFLID10.UINT8[R_IO_HH])
+#define RSCAN0GAFLM10 (RSCAN0.GAFLM10.UINT32)
+#define RSCAN0GAFLM10L (RSCAN0.GAFLM10.UINT16[R_IO_L])
+#define RSCAN0GAFLM10LL (RSCAN0.GAFLM10.UINT8[R_IO_LL])
+#define RSCAN0GAFLM10LH (RSCAN0.GAFLM10.UINT8[R_IO_LH])
+#define RSCAN0GAFLM10H (RSCAN0.GAFLM10.UINT16[R_IO_H])
+#define RSCAN0GAFLM10HL (RSCAN0.GAFLM10.UINT8[R_IO_HL])
+#define RSCAN0GAFLM10HH (RSCAN0.GAFLM10.UINT8[R_IO_HH])
+#define RSCAN0GAFLP010 (RSCAN0.GAFLP010.UINT32)
+#define RSCAN0GAFLP010L (RSCAN0.GAFLP010.UINT16[R_IO_L])
+#define RSCAN0GAFLP010LL (RSCAN0.GAFLP010.UINT8[R_IO_LL])
+#define RSCAN0GAFLP010LH (RSCAN0.GAFLP010.UINT8[R_IO_LH])
+#define RSCAN0GAFLP010H (RSCAN0.GAFLP010.UINT16[R_IO_H])
+#define RSCAN0GAFLP010HL (RSCAN0.GAFLP010.UINT8[R_IO_HL])
+#define RSCAN0GAFLP010HH (RSCAN0.GAFLP010.UINT8[R_IO_HH])
+#define RSCAN0GAFLP110 (RSCAN0.GAFLP110.UINT32)
+#define RSCAN0GAFLP110L (RSCAN0.GAFLP110.UINT16[R_IO_L])
+#define RSCAN0GAFLP110LL (RSCAN0.GAFLP110.UINT8[R_IO_LL])
+#define RSCAN0GAFLP110LH (RSCAN0.GAFLP110.UINT8[R_IO_LH])
+#define RSCAN0GAFLP110H (RSCAN0.GAFLP110.UINT16[R_IO_H])
+#define RSCAN0GAFLP110HL (RSCAN0.GAFLP110.UINT8[R_IO_HL])
+#define RSCAN0GAFLP110HH (RSCAN0.GAFLP110.UINT8[R_IO_HH])
+#define RSCAN0GAFLID11 (RSCAN0.GAFLID11.UINT32)
+#define RSCAN0GAFLID11L (RSCAN0.GAFLID11.UINT16[R_IO_L])
+#define RSCAN0GAFLID11LL (RSCAN0.GAFLID11.UINT8[R_IO_LL])
+#define RSCAN0GAFLID11LH (RSCAN0.GAFLID11.UINT8[R_IO_LH])
+#define RSCAN0GAFLID11H (RSCAN0.GAFLID11.UINT16[R_IO_H])
+#define RSCAN0GAFLID11HL (RSCAN0.GAFLID11.UINT8[R_IO_HL])
+#define RSCAN0GAFLID11HH (RSCAN0.GAFLID11.UINT8[R_IO_HH])
+#define RSCAN0GAFLM11 (RSCAN0.GAFLM11.UINT32)
+#define RSCAN0GAFLM11L (RSCAN0.GAFLM11.UINT16[R_IO_L])
+#define RSCAN0GAFLM11LL (RSCAN0.GAFLM11.UINT8[R_IO_LL])
+#define RSCAN0GAFLM11LH (RSCAN0.GAFLM11.UINT8[R_IO_LH])
+#define RSCAN0GAFLM11H (RSCAN0.GAFLM11.UINT16[R_IO_H])
+#define RSCAN0GAFLM11HL (RSCAN0.GAFLM11.UINT8[R_IO_HL])
+#define RSCAN0GAFLM11HH (RSCAN0.GAFLM11.UINT8[R_IO_HH])
+#define RSCAN0GAFLP011 (RSCAN0.GAFLP011.UINT32)
+#define RSCAN0GAFLP011L (RSCAN0.GAFLP011.UINT16[R_IO_L])
+#define RSCAN0GAFLP011LL (RSCAN0.GAFLP011.UINT8[R_IO_LL])
+#define RSCAN0GAFLP011LH (RSCAN0.GAFLP011.UINT8[R_IO_LH])
+#define RSCAN0GAFLP011H (RSCAN0.GAFLP011.UINT16[R_IO_H])
+#define RSCAN0GAFLP011HL (RSCAN0.GAFLP011.UINT8[R_IO_HL])
+#define RSCAN0GAFLP011HH (RSCAN0.GAFLP011.UINT8[R_IO_HH])
+#define RSCAN0GAFLP111 (RSCAN0.GAFLP111.UINT32)
+#define RSCAN0GAFLP111L (RSCAN0.GAFLP111.UINT16[R_IO_L])
+#define RSCAN0GAFLP111LL (RSCAN0.GAFLP111.UINT8[R_IO_LL])
+#define RSCAN0GAFLP111LH (RSCAN0.GAFLP111.UINT8[R_IO_LH])
+#define RSCAN0GAFLP111H (RSCAN0.GAFLP111.UINT16[R_IO_H])
+#define RSCAN0GAFLP111HL (RSCAN0.GAFLP111.UINT8[R_IO_HL])
+#define RSCAN0GAFLP111HH (RSCAN0.GAFLP111.UINT8[R_IO_HH])
+#define RSCAN0GAFLID12 (RSCAN0.GAFLID12.UINT32)
+#define RSCAN0GAFLID12L (RSCAN0.GAFLID12.UINT16[R_IO_L])
+#define RSCAN0GAFLID12LL (RSCAN0.GAFLID12.UINT8[R_IO_LL])
+#define RSCAN0GAFLID12LH (RSCAN0.GAFLID12.UINT8[R_IO_LH])
+#define RSCAN0GAFLID12H (RSCAN0.GAFLID12.UINT16[R_IO_H])
+#define RSCAN0GAFLID12HL (RSCAN0.GAFLID12.UINT8[R_IO_HL])
+#define RSCAN0GAFLID12HH (RSCAN0.GAFLID12.UINT8[R_IO_HH])
+#define RSCAN0GAFLM12 (RSCAN0.GAFLM12.UINT32)
+#define RSCAN0GAFLM12L (RSCAN0.GAFLM12.UINT16[R_IO_L])
+#define RSCAN0GAFLM12LL (RSCAN0.GAFLM12.UINT8[R_IO_LL])
+#define RSCAN0GAFLM12LH (RSCAN0.GAFLM12.UINT8[R_IO_LH])
+#define RSCAN0GAFLM12H (RSCAN0.GAFLM12.UINT16[R_IO_H])
+#define RSCAN0GAFLM12HL (RSCAN0.GAFLM12.UINT8[R_IO_HL])
+#define RSCAN0GAFLM12HH (RSCAN0.GAFLM12.UINT8[R_IO_HH])
+#define RSCAN0GAFLP012 (RSCAN0.GAFLP012.UINT32)
+#define RSCAN0GAFLP012L (RSCAN0.GAFLP012.UINT16[R_IO_L])
+#define RSCAN0GAFLP012LL (RSCAN0.GAFLP012.UINT8[R_IO_LL])
+#define RSCAN0GAFLP012LH (RSCAN0.GAFLP012.UINT8[R_IO_LH])
+#define RSCAN0GAFLP012H (RSCAN0.GAFLP012.UINT16[R_IO_H])
+#define RSCAN0GAFLP012HL (RSCAN0.GAFLP012.UINT8[R_IO_HL])
+#define RSCAN0GAFLP012HH (RSCAN0.GAFLP012.UINT8[R_IO_HH])
+#define RSCAN0GAFLP112 (RSCAN0.GAFLP112.UINT32)
+#define RSCAN0GAFLP112L (RSCAN0.GAFLP112.UINT16[R_IO_L])
+#define RSCAN0GAFLP112LL (RSCAN0.GAFLP112.UINT8[R_IO_LL])
+#define RSCAN0GAFLP112LH (RSCAN0.GAFLP112.UINT8[R_IO_LH])
+#define RSCAN0GAFLP112H (RSCAN0.GAFLP112.UINT16[R_IO_H])
+#define RSCAN0GAFLP112HL (RSCAN0.GAFLP112.UINT8[R_IO_HL])
+#define RSCAN0GAFLP112HH (RSCAN0.GAFLP112.UINT8[R_IO_HH])
+#define RSCAN0GAFLID13 (RSCAN0.GAFLID13.UINT32)
+#define RSCAN0GAFLID13L (RSCAN0.GAFLID13.UINT16[R_IO_L])
+#define RSCAN0GAFLID13LL (RSCAN0.GAFLID13.UINT8[R_IO_LL])
+#define RSCAN0GAFLID13LH (RSCAN0.GAFLID13.UINT8[R_IO_LH])
+#define RSCAN0GAFLID13H (RSCAN0.GAFLID13.UINT16[R_IO_H])
+#define RSCAN0GAFLID13HL (RSCAN0.GAFLID13.UINT8[R_IO_HL])
+#define RSCAN0GAFLID13HH (RSCAN0.GAFLID13.UINT8[R_IO_HH])
+#define RSCAN0GAFLM13 (RSCAN0.GAFLM13.UINT32)
+#define RSCAN0GAFLM13L (RSCAN0.GAFLM13.UINT16[R_IO_L])
+#define RSCAN0GAFLM13LL (RSCAN0.GAFLM13.UINT8[R_IO_LL])
+#define RSCAN0GAFLM13LH (RSCAN0.GAFLM13.UINT8[R_IO_LH])
+#define RSCAN0GAFLM13H (RSCAN0.GAFLM13.UINT16[R_IO_H])
+#define RSCAN0GAFLM13HL (RSCAN0.GAFLM13.UINT8[R_IO_HL])
+#define RSCAN0GAFLM13HH (RSCAN0.GAFLM13.UINT8[R_IO_HH])
+#define RSCAN0GAFLP013 (RSCAN0.GAFLP013.UINT32)
+#define RSCAN0GAFLP013L (RSCAN0.GAFLP013.UINT16[R_IO_L])
+#define RSCAN0GAFLP013LL (RSCAN0.GAFLP013.UINT8[R_IO_LL])
+#define RSCAN0GAFLP013LH (RSCAN0.GAFLP013.UINT8[R_IO_LH])
+#define RSCAN0GAFLP013H (RSCAN0.GAFLP013.UINT16[R_IO_H])
+#define RSCAN0GAFLP013HL (RSCAN0.GAFLP013.UINT8[R_IO_HL])
+#define RSCAN0GAFLP013HH (RSCAN0.GAFLP013.UINT8[R_IO_HH])
+#define RSCAN0GAFLP113 (RSCAN0.GAFLP113.UINT32)
+#define RSCAN0GAFLP113L (RSCAN0.GAFLP113.UINT16[R_IO_L])
+#define RSCAN0GAFLP113LL (RSCAN0.GAFLP113.UINT8[R_IO_LL])
+#define RSCAN0GAFLP113LH (RSCAN0.GAFLP113.UINT8[R_IO_LH])
+#define RSCAN0GAFLP113H (RSCAN0.GAFLP113.UINT16[R_IO_H])
+#define RSCAN0GAFLP113HL (RSCAN0.GAFLP113.UINT8[R_IO_HL])
+#define RSCAN0GAFLP113HH (RSCAN0.GAFLP113.UINT8[R_IO_HH])
+#define RSCAN0GAFLID14 (RSCAN0.GAFLID14.UINT32)
+#define RSCAN0GAFLID14L (RSCAN0.GAFLID14.UINT16[R_IO_L])
+#define RSCAN0GAFLID14LL (RSCAN0.GAFLID14.UINT8[R_IO_LL])
+#define RSCAN0GAFLID14LH (RSCAN0.GAFLID14.UINT8[R_IO_LH])
+#define RSCAN0GAFLID14H (RSCAN0.GAFLID14.UINT16[R_IO_H])
+#define RSCAN0GAFLID14HL (RSCAN0.GAFLID14.UINT8[R_IO_HL])
+#define RSCAN0GAFLID14HH (RSCAN0.GAFLID14.UINT8[R_IO_HH])
+#define RSCAN0GAFLM14 (RSCAN0.GAFLM14.UINT32)
+#define RSCAN0GAFLM14L (RSCAN0.GAFLM14.UINT16[R_IO_L])
+#define RSCAN0GAFLM14LL (RSCAN0.GAFLM14.UINT8[R_IO_LL])
+#define RSCAN0GAFLM14LH (RSCAN0.GAFLM14.UINT8[R_IO_LH])
+#define RSCAN0GAFLM14H (RSCAN0.GAFLM14.UINT16[R_IO_H])
+#define RSCAN0GAFLM14HL (RSCAN0.GAFLM14.UINT8[R_IO_HL])
+#define RSCAN0GAFLM14HH (RSCAN0.GAFLM14.UINT8[R_IO_HH])
+#define RSCAN0GAFLP014 (RSCAN0.GAFLP014.UINT32)
+#define RSCAN0GAFLP014L (RSCAN0.GAFLP014.UINT16[R_IO_L])
+#define RSCAN0GAFLP014LL (RSCAN0.GAFLP014.UINT8[R_IO_LL])
+#define RSCAN0GAFLP014LH (RSCAN0.GAFLP014.UINT8[R_IO_LH])
+#define RSCAN0GAFLP014H (RSCAN0.GAFLP014.UINT16[R_IO_H])
+#define RSCAN0GAFLP014HL (RSCAN0.GAFLP014.UINT8[R_IO_HL])
+#define RSCAN0GAFLP014HH (RSCAN0.GAFLP014.UINT8[R_IO_HH])
+#define RSCAN0GAFLP114 (RSCAN0.GAFLP114.UINT32)
+#define RSCAN0GAFLP114L (RSCAN0.GAFLP114.UINT16[R_IO_L])
+#define RSCAN0GAFLP114LL (RSCAN0.GAFLP114.UINT8[R_IO_LL])
+#define RSCAN0GAFLP114LH (RSCAN0.GAFLP114.UINT8[R_IO_LH])
+#define RSCAN0GAFLP114H (RSCAN0.GAFLP114.UINT16[R_IO_H])
+#define RSCAN0GAFLP114HL (RSCAN0.GAFLP114.UINT8[R_IO_HL])
+#define RSCAN0GAFLP114HH (RSCAN0.GAFLP114.UINT8[R_IO_HH])
+#define RSCAN0GAFLID15 (RSCAN0.GAFLID15.UINT32)
+#define RSCAN0GAFLID15L (RSCAN0.GAFLID15.UINT16[R_IO_L])
+#define RSCAN0GAFLID15LL (RSCAN0.GAFLID15.UINT8[R_IO_LL])
+#define RSCAN0GAFLID15LH (RSCAN0.GAFLID15.UINT8[R_IO_LH])
+#define RSCAN0GAFLID15H (RSCAN0.GAFLID15.UINT16[R_IO_H])
+#define RSCAN0GAFLID15HL (RSCAN0.GAFLID15.UINT8[R_IO_HL])
+#define RSCAN0GAFLID15HH (RSCAN0.GAFLID15.UINT8[R_IO_HH])
+#define RSCAN0GAFLM15 (RSCAN0.GAFLM15.UINT32)
+#define RSCAN0GAFLM15L (RSCAN0.GAFLM15.UINT16[R_IO_L])
+#define RSCAN0GAFLM15LL (RSCAN0.GAFLM15.UINT8[R_IO_LL])
+#define RSCAN0GAFLM15LH (RSCAN0.GAFLM15.UINT8[R_IO_LH])
+#define RSCAN0GAFLM15H (RSCAN0.GAFLM15.UINT16[R_IO_H])
+#define RSCAN0GAFLM15HL (RSCAN0.GAFLM15.UINT8[R_IO_HL])
+#define RSCAN0GAFLM15HH (RSCAN0.GAFLM15.UINT8[R_IO_HH])
+#define RSCAN0GAFLP015 (RSCAN0.GAFLP015.UINT32)
+#define RSCAN0GAFLP015L (RSCAN0.GAFLP015.UINT16[R_IO_L])
+#define RSCAN0GAFLP015LL (RSCAN0.GAFLP015.UINT8[R_IO_LL])
+#define RSCAN0GAFLP015LH (RSCAN0.GAFLP015.UINT8[R_IO_LH])
+#define RSCAN0GAFLP015H (RSCAN0.GAFLP015.UINT16[R_IO_H])
+#define RSCAN0GAFLP015HL (RSCAN0.GAFLP015.UINT8[R_IO_HL])
+#define RSCAN0GAFLP015HH (RSCAN0.GAFLP015.UINT8[R_IO_HH])
+#define RSCAN0GAFLP115 (RSCAN0.GAFLP115.UINT32)
+#define RSCAN0GAFLP115L (RSCAN0.GAFLP115.UINT16[R_IO_L])
+#define RSCAN0GAFLP115LL (RSCAN0.GAFLP115.UINT8[R_IO_LL])
+#define RSCAN0GAFLP115LH (RSCAN0.GAFLP115.UINT8[R_IO_LH])
+#define RSCAN0GAFLP115H (RSCAN0.GAFLP115.UINT16[R_IO_H])
+#define RSCAN0GAFLP115HL (RSCAN0.GAFLP115.UINT8[R_IO_HL])
+#define RSCAN0GAFLP115HH (RSCAN0.GAFLP115.UINT8[R_IO_HH])
+#define RSCAN0RMID0 (RSCAN0.RMID0.UINT32)
+#define RSCAN0RMID0L (RSCAN0.RMID0.UINT16[R_IO_L])
+#define RSCAN0RMID0LL (RSCAN0.RMID0.UINT8[R_IO_LL])
+#define RSCAN0RMID0LH (RSCAN0.RMID0.UINT8[R_IO_LH])
+#define RSCAN0RMID0H (RSCAN0.RMID0.UINT16[R_IO_H])
+#define RSCAN0RMID0HL (RSCAN0.RMID0.UINT8[R_IO_HL])
+#define RSCAN0RMID0HH (RSCAN0.RMID0.UINT8[R_IO_HH])
+#define RSCAN0RMPTR0 (RSCAN0.RMPTR0.UINT32)
+#define RSCAN0RMPTR0L (RSCAN0.RMPTR0.UINT16[R_IO_L])
+#define RSCAN0RMPTR0LL (RSCAN0.RMPTR0.UINT8[R_IO_LL])
+#define RSCAN0RMPTR0LH (RSCAN0.RMPTR0.UINT8[R_IO_LH])
+#define RSCAN0RMPTR0H (RSCAN0.RMPTR0.UINT16[R_IO_H])
+#define RSCAN0RMPTR0HL (RSCAN0.RMPTR0.UINT8[R_IO_HL])
+#define RSCAN0RMPTR0HH (RSCAN0.RMPTR0.UINT8[R_IO_HH])
+#define RSCAN0RMDF00 (RSCAN0.RMDF00.UINT32)
+#define RSCAN0RMDF00L (RSCAN0.RMDF00.UINT16[R_IO_L])
+#define RSCAN0RMDF00LL (RSCAN0.RMDF00.UINT8[R_IO_LL])
+#define RSCAN0RMDF00LH (RSCAN0.RMDF00.UINT8[R_IO_LH])
+#define RSCAN0RMDF00H (RSCAN0.RMDF00.UINT16[R_IO_H])
+#define RSCAN0RMDF00HL (RSCAN0.RMDF00.UINT8[R_IO_HL])
+#define RSCAN0RMDF00HH (RSCAN0.RMDF00.UINT8[R_IO_HH])
+#define RSCAN0RMDF10 (RSCAN0.RMDF10.UINT32)
+#define RSCAN0RMDF10L (RSCAN0.RMDF10.UINT16[R_IO_L])
+#define RSCAN0RMDF10LL (RSCAN0.RMDF10.UINT8[R_IO_LL])
+#define RSCAN0RMDF10LH (RSCAN0.RMDF10.UINT8[R_IO_LH])
+#define RSCAN0RMDF10H (RSCAN0.RMDF10.UINT16[R_IO_H])
+#define RSCAN0RMDF10HL (RSCAN0.RMDF10.UINT8[R_IO_HL])
+#define RSCAN0RMDF10HH (RSCAN0.RMDF10.UINT8[R_IO_HH])
+#define RSCAN0RMID1 (RSCAN0.RMID1.UINT32)
+#define RSCAN0RMID1L (RSCAN0.RMID1.UINT16[R_IO_L])
+#define RSCAN0RMID1LL (RSCAN0.RMID1.UINT8[R_IO_LL])
+#define RSCAN0RMID1LH (RSCAN0.RMID1.UINT8[R_IO_LH])
+#define RSCAN0RMID1H (RSCAN0.RMID1.UINT16[R_IO_H])
+#define RSCAN0RMID1HL (RSCAN0.RMID1.UINT8[R_IO_HL])
+#define RSCAN0RMID1HH (RSCAN0.RMID1.UINT8[R_IO_HH])
+#define RSCAN0RMPTR1 (RSCAN0.RMPTR1.UINT32)
+#define RSCAN0RMPTR1L (RSCAN0.RMPTR1.UINT16[R_IO_L])
+#define RSCAN0RMPTR1LL (RSCAN0.RMPTR1.UINT8[R_IO_LL])
+#define RSCAN0RMPTR1LH (RSCAN0.RMPTR1.UINT8[R_IO_LH])
+#define RSCAN0RMPTR1H (RSCAN0.RMPTR1.UINT16[R_IO_H])
+#define RSCAN0RMPTR1HL (RSCAN0.RMPTR1.UINT8[R_IO_HL])
+#define RSCAN0RMPTR1HH (RSCAN0.RMPTR1.UINT8[R_IO_HH])
+#define RSCAN0RMDF01 (RSCAN0.RMDF01.UINT32)
+#define RSCAN0RMDF01L (RSCAN0.RMDF01.UINT16[R_IO_L])
+#define RSCAN0RMDF01LL (RSCAN0.RMDF01.UINT8[R_IO_LL])
+#define RSCAN0RMDF01LH (RSCAN0.RMDF01.UINT8[R_IO_LH])
+#define RSCAN0RMDF01H (RSCAN0.RMDF01.UINT16[R_IO_H])
+#define RSCAN0RMDF01HL (RSCAN0.RMDF01.UINT8[R_IO_HL])
+#define RSCAN0RMDF01HH (RSCAN0.RMDF01.UINT8[R_IO_HH])
+#define RSCAN0RMDF11 (RSCAN0.RMDF11.UINT32)
+#define RSCAN0RMDF11L (RSCAN0.RMDF11.UINT16[R_IO_L])
+#define RSCAN0RMDF11LL (RSCAN0.RMDF11.UINT8[R_IO_LL])
+#define RSCAN0RMDF11LH (RSCAN0.RMDF11.UINT8[R_IO_LH])
+#define RSCAN0RMDF11H (RSCAN0.RMDF11.UINT16[R_IO_H])
+#define RSCAN0RMDF11HL (RSCAN0.RMDF11.UINT8[R_IO_HL])
+#define RSCAN0RMDF11HH (RSCAN0.RMDF11.UINT8[R_IO_HH])
+#define RSCAN0RMID2 (RSCAN0.RMID2.UINT32)
+#define RSCAN0RMID2L (RSCAN0.RMID2.UINT16[R_IO_L])
+#define RSCAN0RMID2LL (RSCAN0.RMID2.UINT8[R_IO_LL])
+#define RSCAN0RMID2LH (RSCAN0.RMID2.UINT8[R_IO_LH])
+#define RSCAN0RMID2H (RSCAN0.RMID2.UINT16[R_IO_H])
+#define RSCAN0RMID2HL (RSCAN0.RMID2.UINT8[R_IO_HL])
+#define RSCAN0RMID2HH (RSCAN0.RMID2.UINT8[R_IO_HH])
+#define RSCAN0RMPTR2 (RSCAN0.RMPTR2.UINT32)
+#define RSCAN0RMPTR2L (RSCAN0.RMPTR2.UINT16[R_IO_L])
+#define RSCAN0RMPTR2LL (RSCAN0.RMPTR2.UINT8[R_IO_LL])
+#define RSCAN0RMPTR2LH (RSCAN0.RMPTR2.UINT8[R_IO_LH])
+#define RSCAN0RMPTR2H (RSCAN0.RMPTR2.UINT16[R_IO_H])
+#define RSCAN0RMPTR2HL (RSCAN0.RMPTR2.UINT8[R_IO_HL])
+#define RSCAN0RMPTR2HH (RSCAN0.RMPTR2.UINT8[R_IO_HH])
+#define RSCAN0RMDF02 (RSCAN0.RMDF02.UINT32)
+#define RSCAN0RMDF02L (RSCAN0.RMDF02.UINT16[R_IO_L])
+#define RSCAN0RMDF02LL (RSCAN0.RMDF02.UINT8[R_IO_LL])
+#define RSCAN0RMDF02LH (RSCAN0.RMDF02.UINT8[R_IO_LH])
+#define RSCAN0RMDF02H (RSCAN0.RMDF02.UINT16[R_IO_H])
+#define RSCAN0RMDF02HL (RSCAN0.RMDF02.UINT8[R_IO_HL])
+#define RSCAN0RMDF02HH (RSCAN0.RMDF02.UINT8[R_IO_HH])
+#define RSCAN0RMDF12 (RSCAN0.RMDF12.UINT32)
+#define RSCAN0RMDF12L (RSCAN0.RMDF12.UINT16[R_IO_L])
+#define RSCAN0RMDF12LL (RSCAN0.RMDF12.UINT8[R_IO_LL])
+#define RSCAN0RMDF12LH (RSCAN0.RMDF12.UINT8[R_IO_LH])
+#define RSCAN0RMDF12H (RSCAN0.RMDF12.UINT16[R_IO_H])
+#define RSCAN0RMDF12HL (RSCAN0.RMDF12.UINT8[R_IO_HL])
+#define RSCAN0RMDF12HH (RSCAN0.RMDF12.UINT8[R_IO_HH])
+#define RSCAN0RMID3 (RSCAN0.RMID3.UINT32)
+#define RSCAN0RMID3L (RSCAN0.RMID3.UINT16[R_IO_L])
+#define RSCAN0RMID3LL (RSCAN0.RMID3.UINT8[R_IO_LL])
+#define RSCAN0RMID3LH (RSCAN0.RMID3.UINT8[R_IO_LH])
+#define RSCAN0RMID3H (RSCAN0.RMID3.UINT16[R_IO_H])
+#define RSCAN0RMID3HL (RSCAN0.RMID3.UINT8[R_IO_HL])
+#define RSCAN0RMID3HH (RSCAN0.RMID3.UINT8[R_IO_HH])
+#define RSCAN0RMPTR3 (RSCAN0.RMPTR3.UINT32)
+#define RSCAN0RMPTR3L (RSCAN0.RMPTR3.UINT16[R_IO_L])
+#define RSCAN0RMPTR3LL (RSCAN0.RMPTR3.UINT8[R_IO_LL])
+#define RSCAN0RMPTR3LH (RSCAN0.RMPTR3.UINT8[R_IO_LH])
+#define RSCAN0RMPTR3H (RSCAN0.RMPTR3.UINT16[R_IO_H])
+#define RSCAN0RMPTR3HL (RSCAN0.RMPTR3.UINT8[R_IO_HL])
+#define RSCAN0RMPTR3HH (RSCAN0.RMPTR3.UINT8[R_IO_HH])
+#define RSCAN0RMDF03 (RSCAN0.RMDF03.UINT32)
+#define RSCAN0RMDF03L (RSCAN0.RMDF03.UINT16[R_IO_L])
+#define RSCAN0RMDF03LL (RSCAN0.RMDF03.UINT8[R_IO_LL])
+#define RSCAN0RMDF03LH (RSCAN0.RMDF03.UINT8[R_IO_LH])
+#define RSCAN0RMDF03H (RSCAN0.RMDF03.UINT16[R_IO_H])
+#define RSCAN0RMDF03HL (RSCAN0.RMDF03.UINT8[R_IO_HL])
+#define RSCAN0RMDF03HH (RSCAN0.RMDF03.UINT8[R_IO_HH])
+#define RSCAN0RMDF13 (RSCAN0.RMDF13.UINT32)
+#define RSCAN0RMDF13L (RSCAN0.RMDF13.UINT16[R_IO_L])
+#define RSCAN0RMDF13LL (RSCAN0.RMDF13.UINT8[R_IO_LL])
+#define RSCAN0RMDF13LH (RSCAN0.RMDF13.UINT8[R_IO_LH])
+#define RSCAN0RMDF13H (RSCAN0.RMDF13.UINT16[R_IO_H])
+#define RSCAN0RMDF13HL (RSCAN0.RMDF13.UINT8[R_IO_HL])
+#define RSCAN0RMDF13HH (RSCAN0.RMDF13.UINT8[R_IO_HH])
+#define RSCAN0RMID4 (RSCAN0.RMID4.UINT32)
+#define RSCAN0RMID4L (RSCAN0.RMID4.UINT16[R_IO_L])
+#define RSCAN0RMID4LL (RSCAN0.RMID4.UINT8[R_IO_LL])
+#define RSCAN0RMID4LH (RSCAN0.RMID4.UINT8[R_IO_LH])
+#define RSCAN0RMID4H (RSCAN0.RMID4.UINT16[R_IO_H])
+#define RSCAN0RMID4HL (RSCAN0.RMID4.UINT8[R_IO_HL])
+#define RSCAN0RMID4HH (RSCAN0.RMID4.UINT8[R_IO_HH])
+#define RSCAN0RMPTR4 (RSCAN0.RMPTR4.UINT32)
+#define RSCAN0RMPTR4L (RSCAN0.RMPTR4.UINT16[R_IO_L])
+#define RSCAN0RMPTR4LL (RSCAN0.RMPTR4.UINT8[R_IO_LL])
+#define RSCAN0RMPTR4LH (RSCAN0.RMPTR4.UINT8[R_IO_LH])
+#define RSCAN0RMPTR4H (RSCAN0.RMPTR4.UINT16[R_IO_H])
+#define RSCAN0RMPTR4HL (RSCAN0.RMPTR4.UINT8[R_IO_HL])
+#define RSCAN0RMPTR4HH (RSCAN0.RMPTR4.UINT8[R_IO_HH])
+#define RSCAN0RMDF04 (RSCAN0.RMDF04.UINT32)
+#define RSCAN0RMDF04L (RSCAN0.RMDF04.UINT16[R_IO_L])
+#define RSCAN0RMDF04LL (RSCAN0.RMDF04.UINT8[R_IO_LL])
+#define RSCAN0RMDF04LH (RSCAN0.RMDF04.UINT8[R_IO_LH])
+#define RSCAN0RMDF04H (RSCAN0.RMDF04.UINT16[R_IO_H])
+#define RSCAN0RMDF04HL (RSCAN0.RMDF04.UINT8[R_IO_HL])
+#define RSCAN0RMDF04HH (RSCAN0.RMDF04.UINT8[R_IO_HH])
+#define RSCAN0RMDF14 (RSCAN0.RMDF14.UINT32)
+#define RSCAN0RMDF14L (RSCAN0.RMDF14.UINT16[R_IO_L])
+#define RSCAN0RMDF14LL (RSCAN0.RMDF14.UINT8[R_IO_LL])
+#define RSCAN0RMDF14LH (RSCAN0.RMDF14.UINT8[R_IO_LH])
+#define RSCAN0RMDF14H (RSCAN0.RMDF14.UINT16[R_IO_H])
+#define RSCAN0RMDF14HL (RSCAN0.RMDF14.UINT8[R_IO_HL])
+#define RSCAN0RMDF14HH (RSCAN0.RMDF14.UINT8[R_IO_HH])
+#define RSCAN0RMID5 (RSCAN0.RMID5.UINT32)
+#define RSCAN0RMID5L (RSCAN0.RMID5.UINT16[R_IO_L])
+#define RSCAN0RMID5LL (RSCAN0.RMID5.UINT8[R_IO_LL])
+#define RSCAN0RMID5LH (RSCAN0.RMID5.UINT8[R_IO_LH])
+#define RSCAN0RMID5H (RSCAN0.RMID5.UINT16[R_IO_H])
+#define RSCAN0RMID5HL (RSCAN0.RMID5.UINT8[R_IO_HL])
+#define RSCAN0RMID5HH (RSCAN0.RMID5.UINT8[R_IO_HH])
+#define RSCAN0RMPTR5 (RSCAN0.RMPTR5.UINT32)
+#define RSCAN0RMPTR5L (RSCAN0.RMPTR5.UINT16[R_IO_L])
+#define RSCAN0RMPTR5LL (RSCAN0.RMPTR5.UINT8[R_IO_LL])
+#define RSCAN0RMPTR5LH (RSCAN0.RMPTR5.UINT8[R_IO_LH])
+#define RSCAN0RMPTR5H (RSCAN0.RMPTR5.UINT16[R_IO_H])
+#define RSCAN0RMPTR5HL (RSCAN0.RMPTR5.UINT8[R_IO_HL])
+#define RSCAN0RMPTR5HH (RSCAN0.RMPTR5.UINT8[R_IO_HH])
+#define RSCAN0RMDF05 (RSCAN0.RMDF05.UINT32)
+#define RSCAN0RMDF05L (RSCAN0.RMDF05.UINT16[R_IO_L])
+#define RSCAN0RMDF05LL (RSCAN0.RMDF05.UINT8[R_IO_LL])
+#define RSCAN0RMDF05LH (RSCAN0.RMDF05.UINT8[R_IO_LH])
+#define RSCAN0RMDF05H (RSCAN0.RMDF05.UINT16[R_IO_H])
+#define RSCAN0RMDF05HL (RSCAN0.RMDF05.UINT8[R_IO_HL])
+#define RSCAN0RMDF05HH (RSCAN0.RMDF05.UINT8[R_IO_HH])
+#define RSCAN0RMDF15 (RSCAN0.RMDF15.UINT32)
+#define RSCAN0RMDF15L (RSCAN0.RMDF15.UINT16[R_IO_L])
+#define RSCAN0RMDF15LL (RSCAN0.RMDF15.UINT8[R_IO_LL])
+#define RSCAN0RMDF15LH (RSCAN0.RMDF15.UINT8[R_IO_LH])
+#define RSCAN0RMDF15H (RSCAN0.RMDF15.UINT16[R_IO_H])
+#define RSCAN0RMDF15HL (RSCAN0.RMDF15.UINT8[R_IO_HL])
+#define RSCAN0RMDF15HH (RSCAN0.RMDF15.UINT8[R_IO_HH])
+#define RSCAN0RMID6 (RSCAN0.RMID6.UINT32)
+#define RSCAN0RMID6L (RSCAN0.RMID6.UINT16[R_IO_L])
+#define RSCAN0RMID6LL (RSCAN0.RMID6.UINT8[R_IO_LL])
+#define RSCAN0RMID6LH (RSCAN0.RMID6.UINT8[R_IO_LH])
+#define RSCAN0RMID6H (RSCAN0.RMID6.UINT16[R_IO_H])
+#define RSCAN0RMID6HL (RSCAN0.RMID6.UINT8[R_IO_HL])
+#define RSCAN0RMID6HH (RSCAN0.RMID6.UINT8[R_IO_HH])
+#define RSCAN0RMPTR6 (RSCAN0.RMPTR6.UINT32)
+#define RSCAN0RMPTR6L (RSCAN0.RMPTR6.UINT16[R_IO_L])
+#define RSCAN0RMPTR6LL (RSCAN0.RMPTR6.UINT8[R_IO_LL])
+#define RSCAN0RMPTR6LH (RSCAN0.RMPTR6.UINT8[R_IO_LH])
+#define RSCAN0RMPTR6H (RSCAN0.RMPTR6.UINT16[R_IO_H])
+#define RSCAN0RMPTR6HL (RSCAN0.RMPTR6.UINT8[R_IO_HL])
+#define RSCAN0RMPTR6HH (RSCAN0.RMPTR6.UINT8[R_IO_HH])
+#define RSCAN0RMDF06 (RSCAN0.RMDF06.UINT32)
+#define RSCAN0RMDF06L (RSCAN0.RMDF06.UINT16[R_IO_L])
+#define RSCAN0RMDF06LL (RSCAN0.RMDF06.UINT8[R_IO_LL])
+#define RSCAN0RMDF06LH (RSCAN0.RMDF06.UINT8[R_IO_LH])
+#define RSCAN0RMDF06H (RSCAN0.RMDF06.UINT16[R_IO_H])
+#define RSCAN0RMDF06HL (RSCAN0.RMDF06.UINT8[R_IO_HL])
+#define RSCAN0RMDF06HH (RSCAN0.RMDF06.UINT8[R_IO_HH])
+#define RSCAN0RMDF16 (RSCAN0.RMDF16.UINT32)
+#define RSCAN0RMDF16L (RSCAN0.RMDF16.UINT16[R_IO_L])
+#define RSCAN0RMDF16LL (RSCAN0.RMDF16.UINT8[R_IO_LL])
+#define RSCAN0RMDF16LH (RSCAN0.RMDF16.UINT8[R_IO_LH])
+#define RSCAN0RMDF16H (RSCAN0.RMDF16.UINT16[R_IO_H])
+#define RSCAN0RMDF16HL (RSCAN0.RMDF16.UINT8[R_IO_HL])
+#define RSCAN0RMDF16HH (RSCAN0.RMDF16.UINT8[R_IO_HH])
+#define RSCAN0RMID7 (RSCAN0.RMID7.UINT32)
+#define RSCAN0RMID7L (RSCAN0.RMID7.UINT16[R_IO_L])
+#define RSCAN0RMID7LL (RSCAN0.RMID7.UINT8[R_IO_LL])
+#define RSCAN0RMID7LH (RSCAN0.RMID7.UINT8[R_IO_LH])
+#define RSCAN0RMID7H (RSCAN0.RMID7.UINT16[R_IO_H])
+#define RSCAN0RMID7HL (RSCAN0.RMID7.UINT8[R_IO_HL])
+#define RSCAN0RMID7HH (RSCAN0.RMID7.UINT8[R_IO_HH])
+#define RSCAN0RMPTR7 (RSCAN0.RMPTR7.UINT32)
+#define RSCAN0RMPTR7L (RSCAN0.RMPTR7.UINT16[R_IO_L])
+#define RSCAN0RMPTR7LL (RSCAN0.RMPTR7.UINT8[R_IO_LL])
+#define RSCAN0RMPTR7LH (RSCAN0.RMPTR7.UINT8[R_IO_LH])
+#define RSCAN0RMPTR7H (RSCAN0.RMPTR7.UINT16[R_IO_H])
+#define RSCAN0RMPTR7HL (RSCAN0.RMPTR7.UINT8[R_IO_HL])
+#define RSCAN0RMPTR7HH (RSCAN0.RMPTR7.UINT8[R_IO_HH])
+#define RSCAN0RMDF07 (RSCAN0.RMDF07.UINT32)
+#define RSCAN0RMDF07L (RSCAN0.RMDF07.UINT16[R_IO_L])
+#define RSCAN0RMDF07LL (RSCAN0.RMDF07.UINT8[R_IO_LL])
+#define RSCAN0RMDF07LH (RSCAN0.RMDF07.UINT8[R_IO_LH])
+#define RSCAN0RMDF07H (RSCAN0.RMDF07.UINT16[R_IO_H])
+#define RSCAN0RMDF07HL (RSCAN0.RMDF07.UINT8[R_IO_HL])
+#define RSCAN0RMDF07HH (RSCAN0.RMDF07.UINT8[R_IO_HH])
+#define RSCAN0RMDF17 (RSCAN0.RMDF17.UINT32)
+#define RSCAN0RMDF17L (RSCAN0.RMDF17.UINT16[R_IO_L])
+#define RSCAN0RMDF17LL (RSCAN0.RMDF17.UINT8[R_IO_LL])
+#define RSCAN0RMDF17LH (RSCAN0.RMDF17.UINT8[R_IO_LH])
+#define RSCAN0RMDF17H (RSCAN0.RMDF17.UINT16[R_IO_H])
+#define RSCAN0RMDF17HL (RSCAN0.RMDF17.UINT8[R_IO_HL])
+#define RSCAN0RMDF17HH (RSCAN0.RMDF17.UINT8[R_IO_HH])
+#define RSCAN0RMID8 (RSCAN0.RMID8.UINT32)
+#define RSCAN0RMID8L (RSCAN0.RMID8.UINT16[R_IO_L])
+#define RSCAN0RMID8LL (RSCAN0.RMID8.UINT8[R_IO_LL])
+#define RSCAN0RMID8LH (RSCAN0.RMID8.UINT8[R_IO_LH])
+#define RSCAN0RMID8H (RSCAN0.RMID8.UINT16[R_IO_H])
+#define RSCAN0RMID8HL (RSCAN0.RMID8.UINT8[R_IO_HL])
+#define RSCAN0RMID8HH (RSCAN0.RMID8.UINT8[R_IO_HH])
+#define RSCAN0RMPTR8 (RSCAN0.RMPTR8.UINT32)
+#define RSCAN0RMPTR8L (RSCAN0.RMPTR8.UINT16[R_IO_L])
+#define RSCAN0RMPTR8LL (RSCAN0.RMPTR8.UINT8[R_IO_LL])
+#define RSCAN0RMPTR8LH (RSCAN0.RMPTR8.UINT8[R_IO_LH])
+#define RSCAN0RMPTR8H (RSCAN0.RMPTR8.UINT16[R_IO_H])
+#define RSCAN0RMPTR8HL (RSCAN0.RMPTR8.UINT8[R_IO_HL])
+#define RSCAN0RMPTR8HH (RSCAN0.RMPTR8.UINT8[R_IO_HH])
+#define RSCAN0RMDF08 (RSCAN0.RMDF08.UINT32)
+#define RSCAN0RMDF08L (RSCAN0.RMDF08.UINT16[R_IO_L])
+#define RSCAN0RMDF08LL (RSCAN0.RMDF08.UINT8[R_IO_LL])
+#define RSCAN0RMDF08LH (RSCAN0.RMDF08.UINT8[R_IO_LH])
+#define RSCAN0RMDF08H (RSCAN0.RMDF08.UINT16[R_IO_H])
+#define RSCAN0RMDF08HL (RSCAN0.RMDF08.UINT8[R_IO_HL])
+#define RSCAN0RMDF08HH (RSCAN0.RMDF08.UINT8[R_IO_HH])
+#define RSCAN0RMDF18 (RSCAN0.RMDF18.UINT32)
+#define RSCAN0RMDF18L (RSCAN0.RMDF18.UINT16[R_IO_L])
+#define RSCAN0RMDF18LL (RSCAN0.RMDF18.UINT8[R_IO_LL])
+#define RSCAN0RMDF18LH (RSCAN0.RMDF18.UINT8[R_IO_LH])
+#define RSCAN0RMDF18H (RSCAN0.RMDF18.UINT16[R_IO_H])
+#define RSCAN0RMDF18HL (RSCAN0.RMDF18.UINT8[R_IO_HL])
+#define RSCAN0RMDF18HH (RSCAN0.RMDF18.UINT8[R_IO_HH])
+#define RSCAN0RMID9 (RSCAN0.RMID9.UINT32)
+#define RSCAN0RMID9L (RSCAN0.RMID9.UINT16[R_IO_L])
+#define RSCAN0RMID9LL (RSCAN0.RMID9.UINT8[R_IO_LL])
+#define RSCAN0RMID9LH (RSCAN0.RMID9.UINT8[R_IO_LH])
+#define RSCAN0RMID9H (RSCAN0.RMID9.UINT16[R_IO_H])
+#define RSCAN0RMID9HL (RSCAN0.RMID9.UINT8[R_IO_HL])
+#define RSCAN0RMID9HH (RSCAN0.RMID9.UINT8[R_IO_HH])
+#define RSCAN0RMPTR9 (RSCAN0.RMPTR9.UINT32)
+#define RSCAN0RMPTR9L (RSCAN0.RMPTR9.UINT16[R_IO_L])
+#define RSCAN0RMPTR9LL (RSCAN0.RMPTR9.UINT8[R_IO_LL])
+#define RSCAN0RMPTR9LH (RSCAN0.RMPTR9.UINT8[R_IO_LH])
+#define RSCAN0RMPTR9H (RSCAN0.RMPTR9.UINT16[R_IO_H])
+#define RSCAN0RMPTR9HL (RSCAN0.RMPTR9.UINT8[R_IO_HL])
+#define RSCAN0RMPTR9HH (RSCAN0.RMPTR9.UINT8[R_IO_HH])
+#define RSCAN0RMDF09 (RSCAN0.RMDF09.UINT32)
+#define RSCAN0RMDF09L (RSCAN0.RMDF09.UINT16[R_IO_L])
+#define RSCAN0RMDF09LL (RSCAN0.RMDF09.UINT8[R_IO_LL])
+#define RSCAN0RMDF09LH (RSCAN0.RMDF09.UINT8[R_IO_LH])
+#define RSCAN0RMDF09H (RSCAN0.RMDF09.UINT16[R_IO_H])
+#define RSCAN0RMDF09HL (RSCAN0.RMDF09.UINT8[R_IO_HL])
+#define RSCAN0RMDF09HH (RSCAN0.RMDF09.UINT8[R_IO_HH])
+#define RSCAN0RMDF19 (RSCAN0.RMDF19.UINT32)
+#define RSCAN0RMDF19L (RSCAN0.RMDF19.UINT16[R_IO_L])
+#define RSCAN0RMDF19LL (RSCAN0.RMDF19.UINT8[R_IO_LL])
+#define RSCAN0RMDF19LH (RSCAN0.RMDF19.UINT8[R_IO_LH])
+#define RSCAN0RMDF19H (RSCAN0.RMDF19.UINT16[R_IO_H])
+#define RSCAN0RMDF19HL (RSCAN0.RMDF19.UINT8[R_IO_HL])
+#define RSCAN0RMDF19HH (RSCAN0.RMDF19.UINT8[R_IO_HH])
+#define RSCAN0RMID10 (RSCAN0.RMID10.UINT32)
+#define RSCAN0RMID10L (RSCAN0.RMID10.UINT16[R_IO_L])
+#define RSCAN0RMID10LL (RSCAN0.RMID10.UINT8[R_IO_LL])
+#define RSCAN0RMID10LH (RSCAN0.RMID10.UINT8[R_IO_LH])
+#define RSCAN0RMID10H (RSCAN0.RMID10.UINT16[R_IO_H])
+#define RSCAN0RMID10HL (RSCAN0.RMID10.UINT8[R_IO_HL])
+#define RSCAN0RMID10HH (RSCAN0.RMID10.UINT8[R_IO_HH])
+#define RSCAN0RMPTR10 (RSCAN0.RMPTR10.UINT32)
+#define RSCAN0RMPTR10L (RSCAN0.RMPTR10.UINT16[R_IO_L])
+#define RSCAN0RMPTR10LL (RSCAN0.RMPTR10.UINT8[R_IO_LL])
+#define RSCAN0RMPTR10LH (RSCAN0.RMPTR10.UINT8[R_IO_LH])
+#define RSCAN0RMPTR10H (RSCAN0.RMPTR10.UINT16[R_IO_H])
+#define RSCAN0RMPTR10HL (RSCAN0.RMPTR10.UINT8[R_IO_HL])
+#define RSCAN0RMPTR10HH (RSCAN0.RMPTR10.UINT8[R_IO_HH])
+#define RSCAN0RMDF010 (RSCAN0.RMDF010.UINT32)
+#define RSCAN0RMDF010L (RSCAN0.RMDF010.UINT16[R_IO_L])
+#define RSCAN0RMDF010LL (RSCAN0.RMDF010.UINT8[R_IO_LL])
+#define RSCAN0RMDF010LH (RSCAN0.RMDF010.UINT8[R_IO_LH])
+#define RSCAN0RMDF010H (RSCAN0.RMDF010.UINT16[R_IO_H])
+#define RSCAN0RMDF010HL (RSCAN0.RMDF010.UINT8[R_IO_HL])
+#define RSCAN0RMDF010HH (RSCAN0.RMDF010.UINT8[R_IO_HH])
+#define RSCAN0RMDF110 (RSCAN0.RMDF110.UINT32)
+#define RSCAN0RMDF110L (RSCAN0.RMDF110.UINT16[R_IO_L])
+#define RSCAN0RMDF110LL (RSCAN0.RMDF110.UINT8[R_IO_LL])
+#define RSCAN0RMDF110LH (RSCAN0.RMDF110.UINT8[R_IO_LH])
+#define RSCAN0RMDF110H (RSCAN0.RMDF110.UINT16[R_IO_H])
+#define RSCAN0RMDF110HL (RSCAN0.RMDF110.UINT8[R_IO_HL])
+#define RSCAN0RMDF110HH (RSCAN0.RMDF110.UINT8[R_IO_HH])
+#define RSCAN0RMID11 (RSCAN0.RMID11.UINT32)
+#define RSCAN0RMID11L (RSCAN0.RMID11.UINT16[R_IO_L])
+#define RSCAN0RMID11LL (RSCAN0.RMID11.UINT8[R_IO_LL])
+#define RSCAN0RMID11LH (RSCAN0.RMID11.UINT8[R_IO_LH])
+#define RSCAN0RMID11H (RSCAN0.RMID11.UINT16[R_IO_H])
+#define RSCAN0RMID11HL (RSCAN0.RMID11.UINT8[R_IO_HL])
+#define RSCAN0RMID11HH (RSCAN0.RMID11.UINT8[R_IO_HH])
+#define RSCAN0RMPTR11 (RSCAN0.RMPTR11.UINT32)
+#define RSCAN0RMPTR11L (RSCAN0.RMPTR11.UINT16[R_IO_L])
+#define RSCAN0RMPTR11LL (RSCAN0.RMPTR11.UINT8[R_IO_LL])
+#define RSCAN0RMPTR11LH (RSCAN0.RMPTR11.UINT8[R_IO_LH])
+#define RSCAN0RMPTR11H (RSCAN0.RMPTR11.UINT16[R_IO_H])
+#define RSCAN0RMPTR11HL (RSCAN0.RMPTR11.UINT8[R_IO_HL])
+#define RSCAN0RMPTR11HH (RSCAN0.RMPTR11.UINT8[R_IO_HH])
+#define RSCAN0RMDF011 (RSCAN0.RMDF011.UINT32)
+#define RSCAN0RMDF011L (RSCAN0.RMDF011.UINT16[R_IO_L])
+#define RSCAN0RMDF011LL (RSCAN0.RMDF011.UINT8[R_IO_LL])
+#define RSCAN0RMDF011LH (RSCAN0.RMDF011.UINT8[R_IO_LH])
+#define RSCAN0RMDF011H (RSCAN0.RMDF011.UINT16[R_IO_H])
+#define RSCAN0RMDF011HL (RSCAN0.RMDF011.UINT8[R_IO_HL])
+#define RSCAN0RMDF011HH (RSCAN0.RMDF011.UINT8[R_IO_HH])
+#define RSCAN0RMDF111 (RSCAN0.RMDF111.UINT32)
+#define RSCAN0RMDF111L (RSCAN0.RMDF111.UINT16[R_IO_L])
+#define RSCAN0RMDF111LL (RSCAN0.RMDF111.UINT8[R_IO_LL])
+#define RSCAN0RMDF111LH (RSCAN0.RMDF111.UINT8[R_IO_LH])
+#define RSCAN0RMDF111H (RSCAN0.RMDF111.UINT16[R_IO_H])
+#define RSCAN0RMDF111HL (RSCAN0.RMDF111.UINT8[R_IO_HL])
+#define RSCAN0RMDF111HH (RSCAN0.RMDF111.UINT8[R_IO_HH])
+#define RSCAN0RMID12 (RSCAN0.RMID12.UINT32)
+#define RSCAN0RMID12L (RSCAN0.RMID12.UINT16[R_IO_L])
+#define RSCAN0RMID12LL (RSCAN0.RMID12.UINT8[R_IO_LL])
+#define RSCAN0RMID12LH (RSCAN0.RMID12.UINT8[R_IO_LH])
+#define RSCAN0RMID12H (RSCAN0.RMID12.UINT16[R_IO_H])
+#define RSCAN0RMID12HL (RSCAN0.RMID12.UINT8[R_IO_HL])
+#define RSCAN0RMID12HH (RSCAN0.RMID12.UINT8[R_IO_HH])
+#define RSCAN0RMPTR12 (RSCAN0.RMPTR12.UINT32)
+#define RSCAN0RMPTR12L (RSCAN0.RMPTR12.UINT16[R_IO_L])
+#define RSCAN0RMPTR12LL (RSCAN0.RMPTR12.UINT8[R_IO_LL])
+#define RSCAN0RMPTR12LH (RSCAN0.RMPTR12.UINT8[R_IO_LH])
+#define RSCAN0RMPTR12H (RSCAN0.RMPTR12.UINT16[R_IO_H])
+#define RSCAN0RMPTR12HL (RSCAN0.RMPTR12.UINT8[R_IO_HL])
+#define RSCAN0RMPTR12HH (RSCAN0.RMPTR12.UINT8[R_IO_HH])
+#define RSCAN0RMDF012 (RSCAN0.RMDF012.UINT32)
+#define RSCAN0RMDF012L (RSCAN0.RMDF012.UINT16[R_IO_L])
+#define RSCAN0RMDF012LL (RSCAN0.RMDF012.UINT8[R_IO_LL])
+#define RSCAN0RMDF012LH (RSCAN0.RMDF012.UINT8[R_IO_LH])
+#define RSCAN0RMDF012H (RSCAN0.RMDF012.UINT16[R_IO_H])
+#define RSCAN0RMDF012HL (RSCAN0.RMDF012.UINT8[R_IO_HL])
+#define RSCAN0RMDF012HH (RSCAN0.RMDF012.UINT8[R_IO_HH])
+#define RSCAN0RMDF112 (RSCAN0.RMDF112.UINT32)
+#define RSCAN0RMDF112L (RSCAN0.RMDF112.UINT16[R_IO_L])
+#define RSCAN0RMDF112LL (RSCAN0.RMDF112.UINT8[R_IO_LL])
+#define RSCAN0RMDF112LH (RSCAN0.RMDF112.UINT8[R_IO_LH])
+#define RSCAN0RMDF112H (RSCAN0.RMDF112.UINT16[R_IO_H])
+#define RSCAN0RMDF112HL (RSCAN0.RMDF112.UINT8[R_IO_HL])
+#define RSCAN0RMDF112HH (RSCAN0.RMDF112.UINT8[R_IO_HH])
+#define RSCAN0RMID13 (RSCAN0.RMID13.UINT32)
+#define RSCAN0RMID13L (RSCAN0.RMID13.UINT16[R_IO_L])
+#define RSCAN0RMID13LL (RSCAN0.RMID13.UINT8[R_IO_LL])
+#define RSCAN0RMID13LH (RSCAN0.RMID13.UINT8[R_IO_LH])
+#define RSCAN0RMID13H (RSCAN0.RMID13.UINT16[R_IO_H])
+#define RSCAN0RMID13HL (RSCAN0.RMID13.UINT8[R_IO_HL])
+#define RSCAN0RMID13HH (RSCAN0.RMID13.UINT8[R_IO_HH])
+#define RSCAN0RMPTR13 (RSCAN0.RMPTR13.UINT32)
+#define RSCAN0RMPTR13L (RSCAN0.RMPTR13.UINT16[R_IO_L])
+#define RSCAN0RMPTR13LL (RSCAN0.RMPTR13.UINT8[R_IO_LL])
+#define RSCAN0RMPTR13LH (RSCAN0.RMPTR13.UINT8[R_IO_LH])
+#define RSCAN0RMPTR13H (RSCAN0.RMPTR13.UINT16[R_IO_H])
+#define RSCAN0RMPTR13HL (RSCAN0.RMPTR13.UINT8[R_IO_HL])
+#define RSCAN0RMPTR13HH (RSCAN0.RMPTR13.UINT8[R_IO_HH])
+#define RSCAN0RMDF013 (RSCAN0.RMDF013.UINT32)
+#define RSCAN0RMDF013L (RSCAN0.RMDF013.UINT16[R_IO_L])
+#define RSCAN0RMDF013LL (RSCAN0.RMDF013.UINT8[R_IO_LL])
+#define RSCAN0RMDF013LH (RSCAN0.RMDF013.UINT8[R_IO_LH])
+#define RSCAN0RMDF013H (RSCAN0.RMDF013.UINT16[R_IO_H])
+#define RSCAN0RMDF013HL (RSCAN0.RMDF013.UINT8[R_IO_HL])
+#define RSCAN0RMDF013HH (RSCAN0.RMDF013.UINT8[R_IO_HH])
+#define RSCAN0RMDF113 (RSCAN0.RMDF113.UINT32)
+#define RSCAN0RMDF113L (RSCAN0.RMDF113.UINT16[R_IO_L])
+#define RSCAN0RMDF113LL (RSCAN0.RMDF113.UINT8[R_IO_LL])
+#define RSCAN0RMDF113LH (RSCAN0.RMDF113.UINT8[R_IO_LH])
+#define RSCAN0RMDF113H (RSCAN0.RMDF113.UINT16[R_IO_H])
+#define RSCAN0RMDF113HL (RSCAN0.RMDF113.UINT8[R_IO_HL])
+#define RSCAN0RMDF113HH (RSCAN0.RMDF113.UINT8[R_IO_HH])
+#define RSCAN0RMID14 (RSCAN0.RMID14.UINT32)
+#define RSCAN0RMID14L (RSCAN0.RMID14.UINT16[R_IO_L])
+#define RSCAN0RMID14LL (RSCAN0.RMID14.UINT8[R_IO_LL])
+#define RSCAN0RMID14LH (RSCAN0.RMID14.UINT8[R_IO_LH])
+#define RSCAN0RMID14H (RSCAN0.RMID14.UINT16[R_IO_H])
+#define RSCAN0RMID14HL (RSCAN0.RMID14.UINT8[R_IO_HL])
+#define RSCAN0RMID14HH (RSCAN0.RMID14.UINT8[R_IO_HH])
+#define RSCAN0RMPTR14 (RSCAN0.RMPTR14.UINT32)
+#define RSCAN0RMPTR14L (RSCAN0.RMPTR14.UINT16[R_IO_L])
+#define RSCAN0RMPTR14LL (RSCAN0.RMPTR14.UINT8[R_IO_LL])
+#define RSCAN0RMPTR14LH (RSCAN0.RMPTR14.UINT8[R_IO_LH])
+#define RSCAN0RMPTR14H (RSCAN0.RMPTR14.UINT16[R_IO_H])
+#define RSCAN0RMPTR14HL (RSCAN0.RMPTR14.UINT8[R_IO_HL])
+#define RSCAN0RMPTR14HH (RSCAN0.RMPTR14.UINT8[R_IO_HH])
+#define RSCAN0RMDF014 (RSCAN0.RMDF014.UINT32)
+#define RSCAN0RMDF014L (RSCAN0.RMDF014.UINT16[R_IO_L])
+#define RSCAN0RMDF014LL (RSCAN0.RMDF014.UINT8[R_IO_LL])
+#define RSCAN0RMDF014LH (RSCAN0.RMDF014.UINT8[R_IO_LH])
+#define RSCAN0RMDF014H (RSCAN0.RMDF014.UINT16[R_IO_H])
+#define RSCAN0RMDF014HL (RSCAN0.RMDF014.UINT8[R_IO_HL])
+#define RSCAN0RMDF014HH (RSCAN0.RMDF014.UINT8[R_IO_HH])
+#define RSCAN0RMDF114 (RSCAN0.RMDF114.UINT32)
+#define RSCAN0RMDF114L (RSCAN0.RMDF114.UINT16[R_IO_L])
+#define RSCAN0RMDF114LL (RSCAN0.RMDF114.UINT8[R_IO_LL])
+#define RSCAN0RMDF114LH (RSCAN0.RMDF114.UINT8[R_IO_LH])
+#define RSCAN0RMDF114H (RSCAN0.RMDF114.UINT16[R_IO_H])
+#define RSCAN0RMDF114HL (RSCAN0.RMDF114.UINT8[R_IO_HL])
+#define RSCAN0RMDF114HH (RSCAN0.RMDF114.UINT8[R_IO_HH])
+#define RSCAN0RMID15 (RSCAN0.RMID15.UINT32)
+#define RSCAN0RMID15L (RSCAN0.RMID15.UINT16[R_IO_L])
+#define RSCAN0RMID15LL (RSCAN0.RMID15.UINT8[R_IO_LL])
+#define RSCAN0RMID15LH (RSCAN0.RMID15.UINT8[R_IO_LH])
+#define RSCAN0RMID15H (RSCAN0.RMID15.UINT16[R_IO_H])
+#define RSCAN0RMID15HL (RSCAN0.RMID15.UINT8[R_IO_HL])
+#define RSCAN0RMID15HH (RSCAN0.RMID15.UINT8[R_IO_HH])
+#define RSCAN0RMPTR15 (RSCAN0.RMPTR15.UINT32)
+#define RSCAN0RMPTR15L (RSCAN0.RMPTR15.UINT16[R_IO_L])
+#define RSCAN0RMPTR15LL (RSCAN0.RMPTR15.UINT8[R_IO_LL])
+#define RSCAN0RMPTR15LH (RSCAN0.RMPTR15.UINT8[R_IO_LH])
+#define RSCAN0RMPTR15H (RSCAN0.RMPTR15.UINT16[R_IO_H])
+#define RSCAN0RMPTR15HL (RSCAN0.RMPTR15.UINT8[R_IO_HL])
+#define RSCAN0RMPTR15HH (RSCAN0.RMPTR15.UINT8[R_IO_HH])
+#define RSCAN0RMDF015 (RSCAN0.RMDF015.UINT32)
+#define RSCAN0RMDF015L (RSCAN0.RMDF015.UINT16[R_IO_L])
+#define RSCAN0RMDF015LL (RSCAN0.RMDF015.UINT8[R_IO_LL])
+#define RSCAN0RMDF015LH (RSCAN0.RMDF015.UINT8[R_IO_LH])
+#define RSCAN0RMDF015H (RSCAN0.RMDF015.UINT16[R_IO_H])
+#define RSCAN0RMDF015HL (RSCAN0.RMDF015.UINT8[R_IO_HL])
+#define RSCAN0RMDF015HH (RSCAN0.RMDF015.UINT8[R_IO_HH])
+#define RSCAN0RMDF115 (RSCAN0.RMDF115.UINT32)
+#define RSCAN0RMDF115L (RSCAN0.RMDF115.UINT16[R_IO_L])
+#define RSCAN0RMDF115LL (RSCAN0.RMDF115.UINT8[R_IO_LL])
+#define RSCAN0RMDF115LH (RSCAN0.RMDF115.UINT8[R_IO_LH])
+#define RSCAN0RMDF115H (RSCAN0.RMDF115.UINT16[R_IO_H])
+#define RSCAN0RMDF115HL (RSCAN0.RMDF115.UINT8[R_IO_HL])
+#define RSCAN0RMDF115HH (RSCAN0.RMDF115.UINT8[R_IO_HH])
+#define RSCAN0RMID16 (RSCAN0.RMID16.UINT32)
+#define RSCAN0RMID16L (RSCAN0.RMID16.UINT16[R_IO_L])
+#define RSCAN0RMID16LL (RSCAN0.RMID16.UINT8[R_IO_LL])
+#define RSCAN0RMID16LH (RSCAN0.RMID16.UINT8[R_IO_LH])
+#define RSCAN0RMID16H (RSCAN0.RMID16.UINT16[R_IO_H])
+#define RSCAN0RMID16HL (RSCAN0.RMID16.UINT8[R_IO_HL])
+#define RSCAN0RMID16HH (RSCAN0.RMID16.UINT8[R_IO_HH])
+#define RSCAN0RMPTR16 (RSCAN0.RMPTR16.UINT32)
+#define RSCAN0RMPTR16L (RSCAN0.RMPTR16.UINT16[R_IO_L])
+#define RSCAN0RMPTR16LL (RSCAN0.RMPTR16.UINT8[R_IO_LL])
+#define RSCAN0RMPTR16LH (RSCAN0.RMPTR16.UINT8[R_IO_LH])
+#define RSCAN0RMPTR16H (RSCAN0.RMPTR16.UINT16[R_IO_H])
+#define RSCAN0RMPTR16HL (RSCAN0.RMPTR16.UINT8[R_IO_HL])
+#define RSCAN0RMPTR16HH (RSCAN0.RMPTR16.UINT8[R_IO_HH])
+#define RSCAN0RMDF016 (RSCAN0.RMDF016.UINT32)
+#define RSCAN0RMDF016L (RSCAN0.RMDF016.UINT16[R_IO_L])
+#define RSCAN0RMDF016LL (RSCAN0.RMDF016.UINT8[R_IO_LL])
+#define RSCAN0RMDF016LH (RSCAN0.RMDF016.UINT8[R_IO_LH])
+#define RSCAN0RMDF016H (RSCAN0.RMDF016.UINT16[R_IO_H])
+#define RSCAN0RMDF016HL (RSCAN0.RMDF016.UINT8[R_IO_HL])
+#define RSCAN0RMDF016HH (RSCAN0.RMDF016.UINT8[R_IO_HH])
+#define RSCAN0RMDF116 (RSCAN0.RMDF116.UINT32)
+#define RSCAN0RMDF116L (RSCAN0.RMDF116.UINT16[R_IO_L])
+#define RSCAN0RMDF116LL (RSCAN0.RMDF116.UINT8[R_IO_LL])
+#define RSCAN0RMDF116LH (RSCAN0.RMDF116.UINT8[R_IO_LH])
+#define RSCAN0RMDF116H (RSCAN0.RMDF116.UINT16[R_IO_H])
+#define RSCAN0RMDF116HL (RSCAN0.RMDF116.UINT8[R_IO_HL])
+#define RSCAN0RMDF116HH (RSCAN0.RMDF116.UINT8[R_IO_HH])
+#define RSCAN0RMID17 (RSCAN0.RMID17.UINT32)
+#define RSCAN0RMID17L (RSCAN0.RMID17.UINT16[R_IO_L])
+#define RSCAN0RMID17LL (RSCAN0.RMID17.UINT8[R_IO_LL])
+#define RSCAN0RMID17LH (RSCAN0.RMID17.UINT8[R_IO_LH])
+#define RSCAN0RMID17H (RSCAN0.RMID17.UINT16[R_IO_H])
+#define RSCAN0RMID17HL (RSCAN0.RMID17.UINT8[R_IO_HL])
+#define RSCAN0RMID17HH (RSCAN0.RMID17.UINT8[R_IO_HH])
+#define RSCAN0RMPTR17 (RSCAN0.RMPTR17.UINT32)
+#define RSCAN0RMPTR17L (RSCAN0.RMPTR17.UINT16[R_IO_L])
+#define RSCAN0RMPTR17LL (RSCAN0.RMPTR17.UINT8[R_IO_LL])
+#define RSCAN0RMPTR17LH (RSCAN0.RMPTR17.UINT8[R_IO_LH])
+#define RSCAN0RMPTR17H (RSCAN0.RMPTR17.UINT16[R_IO_H])
+#define RSCAN0RMPTR17HL (RSCAN0.RMPTR17.UINT8[R_IO_HL])
+#define RSCAN0RMPTR17HH (RSCAN0.RMPTR17.UINT8[R_IO_HH])
+#define RSCAN0RMDF017 (RSCAN0.RMDF017.UINT32)
+#define RSCAN0RMDF017L (RSCAN0.RMDF017.UINT16[R_IO_L])
+#define RSCAN0RMDF017LL (RSCAN0.RMDF017.UINT8[R_IO_LL])
+#define RSCAN0RMDF017LH (RSCAN0.RMDF017.UINT8[R_IO_LH])
+#define RSCAN0RMDF017H (RSCAN0.RMDF017.UINT16[R_IO_H])
+#define RSCAN0RMDF017HL (RSCAN0.RMDF017.UINT8[R_IO_HL])
+#define RSCAN0RMDF017HH (RSCAN0.RMDF017.UINT8[R_IO_HH])
+#define RSCAN0RMDF117 (RSCAN0.RMDF117.UINT32)
+#define RSCAN0RMDF117L (RSCAN0.RMDF117.UINT16[R_IO_L])
+#define RSCAN0RMDF117LL (RSCAN0.RMDF117.UINT8[R_IO_LL])
+#define RSCAN0RMDF117LH (RSCAN0.RMDF117.UINT8[R_IO_LH])
+#define RSCAN0RMDF117H (RSCAN0.RMDF117.UINT16[R_IO_H])
+#define RSCAN0RMDF117HL (RSCAN0.RMDF117.UINT8[R_IO_HL])
+#define RSCAN0RMDF117HH (RSCAN0.RMDF117.UINT8[R_IO_HH])
+#define RSCAN0RMID18 (RSCAN0.RMID18.UINT32)
+#define RSCAN0RMID18L (RSCAN0.RMID18.UINT16[R_IO_L])
+#define RSCAN0RMID18LL (RSCAN0.RMID18.UINT8[R_IO_LL])
+#define RSCAN0RMID18LH (RSCAN0.RMID18.UINT8[R_IO_LH])
+#define RSCAN0RMID18H (RSCAN0.RMID18.UINT16[R_IO_H])
+#define RSCAN0RMID18HL (RSCAN0.RMID18.UINT8[R_IO_HL])
+#define RSCAN0RMID18HH (RSCAN0.RMID18.UINT8[R_IO_HH])
+#define RSCAN0RMPTR18 (RSCAN0.RMPTR18.UINT32)
+#define RSCAN0RMPTR18L (RSCAN0.RMPTR18.UINT16[R_IO_L])
+#define RSCAN0RMPTR18LL (RSCAN0.RMPTR18.UINT8[R_IO_LL])
+#define RSCAN0RMPTR18LH (RSCAN0.RMPTR18.UINT8[R_IO_LH])
+#define RSCAN0RMPTR18H (RSCAN0.RMPTR18.UINT16[R_IO_H])
+#define RSCAN0RMPTR18HL (RSCAN0.RMPTR18.UINT8[R_IO_HL])
+#define RSCAN0RMPTR18HH (RSCAN0.RMPTR18.UINT8[R_IO_HH])
+#define RSCAN0RMDF018 (RSCAN0.RMDF018.UINT32)
+#define RSCAN0RMDF018L (RSCAN0.RMDF018.UINT16[R_IO_L])
+#define RSCAN0RMDF018LL (RSCAN0.RMDF018.UINT8[R_IO_LL])
+#define RSCAN0RMDF018LH (RSCAN0.RMDF018.UINT8[R_IO_LH])
+#define RSCAN0RMDF018H (RSCAN0.RMDF018.UINT16[R_IO_H])
+#define RSCAN0RMDF018HL (RSCAN0.RMDF018.UINT8[R_IO_HL])
+#define RSCAN0RMDF018HH (RSCAN0.RMDF018.UINT8[R_IO_HH])
+#define RSCAN0RMDF118 (RSCAN0.RMDF118.UINT32)
+#define RSCAN0RMDF118L (RSCAN0.RMDF118.UINT16[R_IO_L])
+#define RSCAN0RMDF118LL (RSCAN0.RMDF118.UINT8[R_IO_LL])
+#define RSCAN0RMDF118LH (RSCAN0.RMDF118.UINT8[R_IO_LH])
+#define RSCAN0RMDF118H (RSCAN0.RMDF118.UINT16[R_IO_H])
+#define RSCAN0RMDF118HL (RSCAN0.RMDF118.UINT8[R_IO_HL])
+#define RSCAN0RMDF118HH (RSCAN0.RMDF118.UINT8[R_IO_HH])
+#define RSCAN0RMID19 (RSCAN0.RMID19.UINT32)
+#define RSCAN0RMID19L (RSCAN0.RMID19.UINT16[R_IO_L])
+#define RSCAN0RMID19LL (RSCAN0.RMID19.UINT8[R_IO_LL])
+#define RSCAN0RMID19LH (RSCAN0.RMID19.UINT8[R_IO_LH])
+#define RSCAN0RMID19H (RSCAN0.RMID19.UINT16[R_IO_H])
+#define RSCAN0RMID19HL (RSCAN0.RMID19.UINT8[R_IO_HL])
+#define RSCAN0RMID19HH (RSCAN0.RMID19.UINT8[R_IO_HH])
+#define RSCAN0RMPTR19 (RSCAN0.RMPTR19.UINT32)
+#define RSCAN0RMPTR19L (RSCAN0.RMPTR19.UINT16[R_IO_L])
+#define RSCAN0RMPTR19LL (RSCAN0.RMPTR19.UINT8[R_IO_LL])
+#define RSCAN0RMPTR19LH (RSCAN0.RMPTR19.UINT8[R_IO_LH])
+#define RSCAN0RMPTR19H (RSCAN0.RMPTR19.UINT16[R_IO_H])
+#define RSCAN0RMPTR19HL (RSCAN0.RMPTR19.UINT8[R_IO_HL])
+#define RSCAN0RMPTR19HH (RSCAN0.RMPTR19.UINT8[R_IO_HH])
+#define RSCAN0RMDF019 (RSCAN0.RMDF019.UINT32)
+#define RSCAN0RMDF019L (RSCAN0.RMDF019.UINT16[R_IO_L])
+#define RSCAN0RMDF019LL (RSCAN0.RMDF019.UINT8[R_IO_LL])
+#define RSCAN0RMDF019LH (RSCAN0.RMDF019.UINT8[R_IO_LH])
+#define RSCAN0RMDF019H (RSCAN0.RMDF019.UINT16[R_IO_H])
+#define RSCAN0RMDF019HL (RSCAN0.RMDF019.UINT8[R_IO_HL])
+#define RSCAN0RMDF019HH (RSCAN0.RMDF019.UINT8[R_IO_HH])
+#define RSCAN0RMDF119 (RSCAN0.RMDF119.UINT32)
+#define RSCAN0RMDF119L (RSCAN0.RMDF119.UINT16[R_IO_L])
+#define RSCAN0RMDF119LL (RSCAN0.RMDF119.UINT8[R_IO_LL])
+#define RSCAN0RMDF119LH (RSCAN0.RMDF119.UINT8[R_IO_LH])
+#define RSCAN0RMDF119H (RSCAN0.RMDF119.UINT16[R_IO_H])
+#define RSCAN0RMDF119HL (RSCAN0.RMDF119.UINT8[R_IO_HL])
+#define RSCAN0RMDF119HH (RSCAN0.RMDF119.UINT8[R_IO_HH])
+#define RSCAN0RMID20 (RSCAN0.RMID20.UINT32)
+#define RSCAN0RMID20L (RSCAN0.RMID20.UINT16[R_IO_L])
+#define RSCAN0RMID20LL (RSCAN0.RMID20.UINT8[R_IO_LL])
+#define RSCAN0RMID20LH (RSCAN0.RMID20.UINT8[R_IO_LH])
+#define RSCAN0RMID20H (RSCAN0.RMID20.UINT16[R_IO_H])
+#define RSCAN0RMID20HL (RSCAN0.RMID20.UINT8[R_IO_HL])
+#define RSCAN0RMID20HH (RSCAN0.RMID20.UINT8[R_IO_HH])
+#define RSCAN0RMPTR20 (RSCAN0.RMPTR20.UINT32)
+#define RSCAN0RMPTR20L (RSCAN0.RMPTR20.UINT16[R_IO_L])
+#define RSCAN0RMPTR20LL (RSCAN0.RMPTR20.UINT8[R_IO_LL])
+#define RSCAN0RMPTR20LH (RSCAN0.RMPTR20.UINT8[R_IO_LH])
+#define RSCAN0RMPTR20H (RSCAN0.RMPTR20.UINT16[R_IO_H])
+#define RSCAN0RMPTR20HL (RSCAN0.RMPTR20.UINT8[R_IO_HL])
+#define RSCAN0RMPTR20HH (RSCAN0.RMPTR20.UINT8[R_IO_HH])
+#define RSCAN0RMDF020 (RSCAN0.RMDF020.UINT32)
+#define RSCAN0RMDF020L (RSCAN0.RMDF020.UINT16[R_IO_L])
+#define RSCAN0RMDF020LL (RSCAN0.RMDF020.UINT8[R_IO_LL])
+#define RSCAN0RMDF020LH (RSCAN0.RMDF020.UINT8[R_IO_LH])
+#define RSCAN0RMDF020H (RSCAN0.RMDF020.UINT16[R_IO_H])
+#define RSCAN0RMDF020HL (RSCAN0.RMDF020.UINT8[R_IO_HL])
+#define RSCAN0RMDF020HH (RSCAN0.RMDF020.UINT8[R_IO_HH])
+#define RSCAN0RMDF120 (RSCAN0.RMDF120.UINT32)
+#define RSCAN0RMDF120L (RSCAN0.RMDF120.UINT16[R_IO_L])
+#define RSCAN0RMDF120LL (RSCAN0.RMDF120.UINT8[R_IO_LL])
+#define RSCAN0RMDF120LH (RSCAN0.RMDF120.UINT8[R_IO_LH])
+#define RSCAN0RMDF120H (RSCAN0.RMDF120.UINT16[R_IO_H])
+#define RSCAN0RMDF120HL (RSCAN0.RMDF120.UINT8[R_IO_HL])
+#define RSCAN0RMDF120HH (RSCAN0.RMDF120.UINT8[R_IO_HH])
+#define RSCAN0RMID21 (RSCAN0.RMID21.UINT32)
+#define RSCAN0RMID21L (RSCAN0.RMID21.UINT16[R_IO_L])
+#define RSCAN0RMID21LL (RSCAN0.RMID21.UINT8[R_IO_LL])
+#define RSCAN0RMID21LH (RSCAN0.RMID21.UINT8[R_IO_LH])
+#define RSCAN0RMID21H (RSCAN0.RMID21.UINT16[R_IO_H])
+#define RSCAN0RMID21HL (RSCAN0.RMID21.UINT8[R_IO_HL])
+#define RSCAN0RMID21HH (RSCAN0.RMID21.UINT8[R_IO_HH])
+#define RSCAN0RMPTR21 (RSCAN0.RMPTR21.UINT32)
+#define RSCAN0RMPTR21L (RSCAN0.RMPTR21.UINT16[R_IO_L])
+#define RSCAN0RMPTR21LL (RSCAN0.RMPTR21.UINT8[R_IO_LL])
+#define RSCAN0RMPTR21LH (RSCAN0.RMPTR21.UINT8[R_IO_LH])
+#define RSCAN0RMPTR21H (RSCAN0.RMPTR21.UINT16[R_IO_H])
+#define RSCAN0RMPTR21HL (RSCAN0.RMPTR21.UINT8[R_IO_HL])
+#define RSCAN0RMPTR21HH (RSCAN0.RMPTR21.UINT8[R_IO_HH])
+#define RSCAN0RMDF021 (RSCAN0.RMDF021.UINT32)
+#define RSCAN0RMDF021L (RSCAN0.RMDF021.UINT16[R_IO_L])
+#define RSCAN0RMDF021LL (RSCAN0.RMDF021.UINT8[R_IO_LL])
+#define RSCAN0RMDF021LH (RSCAN0.RMDF021.UINT8[R_IO_LH])
+#define RSCAN0RMDF021H (RSCAN0.RMDF021.UINT16[R_IO_H])
+#define RSCAN0RMDF021HL (RSCAN0.RMDF021.UINT8[R_IO_HL])
+#define RSCAN0RMDF021HH (RSCAN0.RMDF021.UINT8[R_IO_HH])
+#define RSCAN0RMDF121 (RSCAN0.RMDF121.UINT32)
+#define RSCAN0RMDF121L (RSCAN0.RMDF121.UINT16[R_IO_L])
+#define RSCAN0RMDF121LL (RSCAN0.RMDF121.UINT8[R_IO_LL])
+#define RSCAN0RMDF121LH (RSCAN0.RMDF121.UINT8[R_IO_LH])
+#define RSCAN0RMDF121H (RSCAN0.RMDF121.UINT16[R_IO_H])
+#define RSCAN0RMDF121HL (RSCAN0.RMDF121.UINT8[R_IO_HL])
+#define RSCAN0RMDF121HH (RSCAN0.RMDF121.UINT8[R_IO_HH])
+#define RSCAN0RMID22 (RSCAN0.RMID22.UINT32)
+#define RSCAN0RMID22L (RSCAN0.RMID22.UINT16[R_IO_L])
+#define RSCAN0RMID22LL (RSCAN0.RMID22.UINT8[R_IO_LL])
+#define RSCAN0RMID22LH (RSCAN0.RMID22.UINT8[R_IO_LH])
+#define RSCAN0RMID22H (RSCAN0.RMID22.UINT16[R_IO_H])
+#define RSCAN0RMID22HL (RSCAN0.RMID22.UINT8[R_IO_HL])
+#define RSCAN0RMID22HH (RSCAN0.RMID22.UINT8[R_IO_HH])
+#define RSCAN0RMPTR22 (RSCAN0.RMPTR22.UINT32)
+#define RSCAN0RMPTR22L (RSCAN0.RMPTR22.UINT16[R_IO_L])
+#define RSCAN0RMPTR22LL (RSCAN0.RMPTR22.UINT8[R_IO_LL])
+#define RSCAN0RMPTR22LH (RSCAN0.RMPTR22.UINT8[R_IO_LH])
+#define RSCAN0RMPTR22H (RSCAN0.RMPTR22.UINT16[R_IO_H])
+#define RSCAN0RMPTR22HL (RSCAN0.RMPTR22.UINT8[R_IO_HL])
+#define RSCAN0RMPTR22HH (RSCAN0.RMPTR22.UINT8[R_IO_HH])
+#define RSCAN0RMDF022 (RSCAN0.RMDF022.UINT32)
+#define RSCAN0RMDF022L (RSCAN0.RMDF022.UINT16[R_IO_L])
+#define RSCAN0RMDF022LL (RSCAN0.RMDF022.UINT8[R_IO_LL])
+#define RSCAN0RMDF022LH (RSCAN0.RMDF022.UINT8[R_IO_LH])
+#define RSCAN0RMDF022H (RSCAN0.RMDF022.UINT16[R_IO_H])
+#define RSCAN0RMDF022HL (RSCAN0.RMDF022.UINT8[R_IO_HL])
+#define RSCAN0RMDF022HH (RSCAN0.RMDF022.UINT8[R_IO_HH])
+#define RSCAN0RMDF122 (RSCAN0.RMDF122.UINT32)
+#define RSCAN0RMDF122L (RSCAN0.RMDF122.UINT16[R_IO_L])
+#define RSCAN0RMDF122LL (RSCAN0.RMDF122.UINT8[R_IO_LL])
+#define RSCAN0RMDF122LH (RSCAN0.RMDF122.UINT8[R_IO_LH])
+#define RSCAN0RMDF122H (RSCAN0.RMDF122.UINT16[R_IO_H])
+#define RSCAN0RMDF122HL (RSCAN0.RMDF122.UINT8[R_IO_HL])
+#define RSCAN0RMDF122HH (RSCAN0.RMDF122.UINT8[R_IO_HH])
+#define RSCAN0RMID23 (RSCAN0.RMID23.UINT32)
+#define RSCAN0RMID23L (RSCAN0.RMID23.UINT16[R_IO_L])
+#define RSCAN0RMID23LL (RSCAN0.RMID23.UINT8[R_IO_LL])
+#define RSCAN0RMID23LH (RSCAN0.RMID23.UINT8[R_IO_LH])
+#define RSCAN0RMID23H (RSCAN0.RMID23.UINT16[R_IO_H])
+#define RSCAN0RMID23HL (RSCAN0.RMID23.UINT8[R_IO_HL])
+#define RSCAN0RMID23HH (RSCAN0.RMID23.UINT8[R_IO_HH])
+#define RSCAN0RMPTR23 (RSCAN0.RMPTR23.UINT32)
+#define RSCAN0RMPTR23L (RSCAN0.RMPTR23.UINT16[R_IO_L])
+#define RSCAN0RMPTR23LL (RSCAN0.RMPTR23.UINT8[R_IO_LL])
+#define RSCAN0RMPTR23LH (RSCAN0.RMPTR23.UINT8[R_IO_LH])
+#define RSCAN0RMPTR23H (RSCAN0.RMPTR23.UINT16[R_IO_H])
+#define RSCAN0RMPTR23HL (RSCAN0.RMPTR23.UINT8[R_IO_HL])
+#define RSCAN0RMPTR23HH (RSCAN0.RMPTR23.UINT8[R_IO_HH])
+#define RSCAN0RMDF023 (RSCAN0.RMDF023.UINT32)
+#define RSCAN0RMDF023L (RSCAN0.RMDF023.UINT16[R_IO_L])
+#define RSCAN0RMDF023LL (RSCAN0.RMDF023.UINT8[R_IO_LL])
+#define RSCAN0RMDF023LH (RSCAN0.RMDF023.UINT8[R_IO_LH])
+#define RSCAN0RMDF023H (RSCAN0.RMDF023.UINT16[R_IO_H])
+#define RSCAN0RMDF023HL (RSCAN0.RMDF023.UINT8[R_IO_HL])
+#define RSCAN0RMDF023HH (RSCAN0.RMDF023.UINT8[R_IO_HH])
+#define RSCAN0RMDF123 (RSCAN0.RMDF123.UINT32)
+#define RSCAN0RMDF123L (RSCAN0.RMDF123.UINT16[R_IO_L])
+#define RSCAN0RMDF123LL (RSCAN0.RMDF123.UINT8[R_IO_LL])
+#define RSCAN0RMDF123LH (RSCAN0.RMDF123.UINT8[R_IO_LH])
+#define RSCAN0RMDF123H (RSCAN0.RMDF123.UINT16[R_IO_H])
+#define RSCAN0RMDF123HL (RSCAN0.RMDF123.UINT8[R_IO_HL])
+#define RSCAN0RMDF123HH (RSCAN0.RMDF123.UINT8[R_IO_HH])
+#define RSCAN0RMID24 (RSCAN0.RMID24.UINT32)
+#define RSCAN0RMID24L (RSCAN0.RMID24.UINT16[R_IO_L])
+#define RSCAN0RMID24LL (RSCAN0.RMID24.UINT8[R_IO_LL])
+#define RSCAN0RMID24LH (RSCAN0.RMID24.UINT8[R_IO_LH])
+#define RSCAN0RMID24H (RSCAN0.RMID24.UINT16[R_IO_H])
+#define RSCAN0RMID24HL (RSCAN0.RMID24.UINT8[R_IO_HL])
+#define RSCAN0RMID24HH (RSCAN0.RMID24.UINT8[R_IO_HH])
+#define RSCAN0RMPTR24 (RSCAN0.RMPTR24.UINT32)
+#define RSCAN0RMPTR24L (RSCAN0.RMPTR24.UINT16[R_IO_L])
+#define RSCAN0RMPTR24LL (RSCAN0.RMPTR24.UINT8[R_IO_LL])
+#define RSCAN0RMPTR24LH (RSCAN0.RMPTR24.UINT8[R_IO_LH])
+#define RSCAN0RMPTR24H (RSCAN0.RMPTR24.UINT16[R_IO_H])
+#define RSCAN0RMPTR24HL (RSCAN0.RMPTR24.UINT8[R_IO_HL])
+#define RSCAN0RMPTR24HH (RSCAN0.RMPTR24.UINT8[R_IO_HH])
+#define RSCAN0RMDF024 (RSCAN0.RMDF024.UINT32)
+#define RSCAN0RMDF024L (RSCAN0.RMDF024.UINT16[R_IO_L])
+#define RSCAN0RMDF024LL (RSCAN0.RMDF024.UINT8[R_IO_LL])
+#define RSCAN0RMDF024LH (RSCAN0.RMDF024.UINT8[R_IO_LH])
+#define RSCAN0RMDF024H (RSCAN0.RMDF024.UINT16[R_IO_H])
+#define RSCAN0RMDF024HL (RSCAN0.RMDF024.UINT8[R_IO_HL])
+#define RSCAN0RMDF024HH (RSCAN0.RMDF024.UINT8[R_IO_HH])
+#define RSCAN0RMDF124 (RSCAN0.RMDF124.UINT32)
+#define RSCAN0RMDF124L (RSCAN0.RMDF124.UINT16[R_IO_L])
+#define RSCAN0RMDF124LL (RSCAN0.RMDF124.UINT8[R_IO_LL])
+#define RSCAN0RMDF124LH (RSCAN0.RMDF124.UINT8[R_IO_LH])
+#define RSCAN0RMDF124H (RSCAN0.RMDF124.UINT16[R_IO_H])
+#define RSCAN0RMDF124HL (RSCAN0.RMDF124.UINT8[R_IO_HL])
+#define RSCAN0RMDF124HH (RSCAN0.RMDF124.UINT8[R_IO_HH])
+#define RSCAN0RMID25 (RSCAN0.RMID25.UINT32)
+#define RSCAN0RMID25L (RSCAN0.RMID25.UINT16[R_IO_L])
+#define RSCAN0RMID25LL (RSCAN0.RMID25.UINT8[R_IO_LL])
+#define RSCAN0RMID25LH (RSCAN0.RMID25.UINT8[R_IO_LH])
+#define RSCAN0RMID25H (RSCAN0.RMID25.UINT16[R_IO_H])
+#define RSCAN0RMID25HL (RSCAN0.RMID25.UINT8[R_IO_HL])
+#define RSCAN0RMID25HH (RSCAN0.RMID25.UINT8[R_IO_HH])
+#define RSCAN0RMPTR25 (RSCAN0.RMPTR25.UINT32)
+#define RSCAN0RMPTR25L (RSCAN0.RMPTR25.UINT16[R_IO_L])
+#define RSCAN0RMPTR25LL (RSCAN0.RMPTR25.UINT8[R_IO_LL])
+#define RSCAN0RMPTR25LH (RSCAN0.RMPTR25.UINT8[R_IO_LH])
+#define RSCAN0RMPTR25H (RSCAN0.RMPTR25.UINT16[R_IO_H])
+#define RSCAN0RMPTR25HL (RSCAN0.RMPTR25.UINT8[R_IO_HL])
+#define RSCAN0RMPTR25HH (RSCAN0.RMPTR25.UINT8[R_IO_HH])
+#define RSCAN0RMDF025 (RSCAN0.RMDF025.UINT32)
+#define RSCAN0RMDF025L (RSCAN0.RMDF025.UINT16[R_IO_L])
+#define RSCAN0RMDF025LL (RSCAN0.RMDF025.UINT8[R_IO_LL])
+#define RSCAN0RMDF025LH (RSCAN0.RMDF025.UINT8[R_IO_LH])
+#define RSCAN0RMDF025H (RSCAN0.RMDF025.UINT16[R_IO_H])
+#define RSCAN0RMDF025HL (RSCAN0.RMDF025.UINT8[R_IO_HL])
+#define RSCAN0RMDF025HH (RSCAN0.RMDF025.UINT8[R_IO_HH])
+#define RSCAN0RMDF125 (RSCAN0.RMDF125.UINT32)
+#define RSCAN0RMDF125L (RSCAN0.RMDF125.UINT16[R_IO_L])
+#define RSCAN0RMDF125LL (RSCAN0.RMDF125.UINT8[R_IO_LL])
+#define RSCAN0RMDF125LH (RSCAN0.RMDF125.UINT8[R_IO_LH])
+#define RSCAN0RMDF125H (RSCAN0.RMDF125.UINT16[R_IO_H])
+#define RSCAN0RMDF125HL (RSCAN0.RMDF125.UINT8[R_IO_HL])
+#define RSCAN0RMDF125HH (RSCAN0.RMDF125.UINT8[R_IO_HH])
+#define RSCAN0RMID26 (RSCAN0.RMID26.UINT32)
+#define RSCAN0RMID26L (RSCAN0.RMID26.UINT16[R_IO_L])
+#define RSCAN0RMID26LL (RSCAN0.RMID26.UINT8[R_IO_LL])
+#define RSCAN0RMID26LH (RSCAN0.RMID26.UINT8[R_IO_LH])
+#define RSCAN0RMID26H (RSCAN0.RMID26.UINT16[R_IO_H])
+#define RSCAN0RMID26HL (RSCAN0.RMID26.UINT8[R_IO_HL])
+#define RSCAN0RMID26HH (RSCAN0.RMID26.UINT8[R_IO_HH])
+#define RSCAN0RMPTR26 (RSCAN0.RMPTR26.UINT32)
+#define RSCAN0RMPTR26L (RSCAN0.RMPTR26.UINT16[R_IO_L])
+#define RSCAN0RMPTR26LL (RSCAN0.RMPTR26.UINT8[R_IO_LL])
+#define RSCAN0RMPTR26LH (RSCAN0.RMPTR26.UINT8[R_IO_LH])
+#define RSCAN0RMPTR26H (RSCAN0.RMPTR26.UINT16[R_IO_H])
+#define RSCAN0RMPTR26HL (RSCAN0.RMPTR26.UINT8[R_IO_HL])
+#define RSCAN0RMPTR26HH (RSCAN0.RMPTR26.UINT8[R_IO_HH])
+#define RSCAN0RMDF026 (RSCAN0.RMDF026.UINT32)
+#define RSCAN0RMDF026L (RSCAN0.RMDF026.UINT16[R_IO_L])
+#define RSCAN0RMDF026LL (RSCAN0.RMDF026.UINT8[R_IO_LL])
+#define RSCAN0RMDF026LH (RSCAN0.RMDF026.UINT8[R_IO_LH])
+#define RSCAN0RMDF026H (RSCAN0.RMDF026.UINT16[R_IO_H])
+#define RSCAN0RMDF026HL (RSCAN0.RMDF026.UINT8[R_IO_HL])
+#define RSCAN0RMDF026HH (RSCAN0.RMDF026.UINT8[R_IO_HH])
+#define RSCAN0RMDF126 (RSCAN0.RMDF126.UINT32)
+#define RSCAN0RMDF126L (RSCAN0.RMDF126.UINT16[R_IO_L])
+#define RSCAN0RMDF126LL (RSCAN0.RMDF126.UINT8[R_IO_LL])
+#define RSCAN0RMDF126LH (RSCAN0.RMDF126.UINT8[R_IO_LH])
+#define RSCAN0RMDF126H (RSCAN0.RMDF126.UINT16[R_IO_H])
+#define RSCAN0RMDF126HL (RSCAN0.RMDF126.UINT8[R_IO_HL])
+#define RSCAN0RMDF126HH (RSCAN0.RMDF126.UINT8[R_IO_HH])
+#define RSCAN0RMID27 (RSCAN0.RMID27.UINT32)
+#define RSCAN0RMID27L (RSCAN0.RMID27.UINT16[R_IO_L])
+#define RSCAN0RMID27LL (RSCAN0.RMID27.UINT8[R_IO_LL])
+#define RSCAN0RMID27LH (RSCAN0.RMID27.UINT8[R_IO_LH])
+#define RSCAN0RMID27H (RSCAN0.RMID27.UINT16[R_IO_H])
+#define RSCAN0RMID27HL (RSCAN0.RMID27.UINT8[R_IO_HL])
+#define RSCAN0RMID27HH (RSCAN0.RMID27.UINT8[R_IO_HH])
+#define RSCAN0RMPTR27 (RSCAN0.RMPTR27.UINT32)
+#define RSCAN0RMPTR27L (RSCAN0.RMPTR27.UINT16[R_IO_L])
+#define RSCAN0RMPTR27LL (RSCAN0.RMPTR27.UINT8[R_IO_LL])
+#define RSCAN0RMPTR27LH (RSCAN0.RMPTR27.UINT8[R_IO_LH])
+#define RSCAN0RMPTR27H (RSCAN0.RMPTR27.UINT16[R_IO_H])
+#define RSCAN0RMPTR27HL (RSCAN0.RMPTR27.UINT8[R_IO_HL])
+#define RSCAN0RMPTR27HH (RSCAN0.RMPTR27.UINT8[R_IO_HH])
+#define RSCAN0RMDF027 (RSCAN0.RMDF027.UINT32)
+#define RSCAN0RMDF027L (RSCAN0.RMDF027.UINT16[R_IO_L])
+#define RSCAN0RMDF027LL (RSCAN0.RMDF027.UINT8[R_IO_LL])
+#define RSCAN0RMDF027LH (RSCAN0.RMDF027.UINT8[R_IO_LH])
+#define RSCAN0RMDF027H (RSCAN0.RMDF027.UINT16[R_IO_H])
+#define RSCAN0RMDF027HL (RSCAN0.RMDF027.UINT8[R_IO_HL])
+#define RSCAN0RMDF027HH (RSCAN0.RMDF027.UINT8[R_IO_HH])
+#define RSCAN0RMDF127 (RSCAN0.RMDF127.UINT32)
+#define RSCAN0RMDF127L (RSCAN0.RMDF127.UINT16[R_IO_L])
+#define RSCAN0RMDF127LL (RSCAN0.RMDF127.UINT8[R_IO_LL])
+#define RSCAN0RMDF127LH (RSCAN0.RMDF127.UINT8[R_IO_LH])
+#define RSCAN0RMDF127H (RSCAN0.RMDF127.UINT16[R_IO_H])
+#define RSCAN0RMDF127HL (RSCAN0.RMDF127.UINT8[R_IO_HL])
+#define RSCAN0RMDF127HH (RSCAN0.RMDF127.UINT8[R_IO_HH])
+#define RSCAN0RMID28 (RSCAN0.RMID28.UINT32)
+#define RSCAN0RMID28L (RSCAN0.RMID28.UINT16[R_IO_L])
+#define RSCAN0RMID28LL (RSCAN0.RMID28.UINT8[R_IO_LL])
+#define RSCAN0RMID28LH (RSCAN0.RMID28.UINT8[R_IO_LH])
+#define RSCAN0RMID28H (RSCAN0.RMID28.UINT16[R_IO_H])
+#define RSCAN0RMID28HL (RSCAN0.RMID28.UINT8[R_IO_HL])
+#define RSCAN0RMID28HH (RSCAN0.RMID28.UINT8[R_IO_HH])
+#define RSCAN0RMPTR28 (RSCAN0.RMPTR28.UINT32)
+#define RSCAN0RMPTR28L (RSCAN0.RMPTR28.UINT16[R_IO_L])
+#define RSCAN0RMPTR28LL (RSCAN0.RMPTR28.UINT8[R_IO_LL])
+#define RSCAN0RMPTR28LH (RSCAN0.RMPTR28.UINT8[R_IO_LH])
+#define RSCAN0RMPTR28H (RSCAN0.RMPTR28.UINT16[R_IO_H])
+#define RSCAN0RMPTR28HL (RSCAN0.RMPTR28.UINT8[R_IO_HL])
+#define RSCAN0RMPTR28HH (RSCAN0.RMPTR28.UINT8[R_IO_HH])
+#define RSCAN0RMDF028 (RSCAN0.RMDF028.UINT32)
+#define RSCAN0RMDF028L (RSCAN0.RMDF028.UINT16[R_IO_L])
+#define RSCAN0RMDF028LL (RSCAN0.RMDF028.UINT8[R_IO_LL])
+#define RSCAN0RMDF028LH (RSCAN0.RMDF028.UINT8[R_IO_LH])
+#define RSCAN0RMDF028H (RSCAN0.RMDF028.UINT16[R_IO_H])
+#define RSCAN0RMDF028HL (RSCAN0.RMDF028.UINT8[R_IO_HL])
+#define RSCAN0RMDF028HH (RSCAN0.RMDF028.UINT8[R_IO_HH])
+#define RSCAN0RMDF128 (RSCAN0.RMDF128.UINT32)
+#define RSCAN0RMDF128L (RSCAN0.RMDF128.UINT16[R_IO_L])
+#define RSCAN0RMDF128LL (RSCAN0.RMDF128.UINT8[R_IO_LL])
+#define RSCAN0RMDF128LH (RSCAN0.RMDF128.UINT8[R_IO_LH])
+#define RSCAN0RMDF128H (RSCAN0.RMDF128.UINT16[R_IO_H])
+#define RSCAN0RMDF128HL (RSCAN0.RMDF128.UINT8[R_IO_HL])
+#define RSCAN0RMDF128HH (RSCAN0.RMDF128.UINT8[R_IO_HH])
+#define RSCAN0RMID29 (RSCAN0.RMID29.UINT32)
+#define RSCAN0RMID29L (RSCAN0.RMID29.UINT16[R_IO_L])
+#define RSCAN0RMID29LL (RSCAN0.RMID29.UINT8[R_IO_LL])
+#define RSCAN0RMID29LH (RSCAN0.RMID29.UINT8[R_IO_LH])
+#define RSCAN0RMID29H (RSCAN0.RMID29.UINT16[R_IO_H])
+#define RSCAN0RMID29HL (RSCAN0.RMID29.UINT8[R_IO_HL])
+#define RSCAN0RMID29HH (RSCAN0.RMID29.UINT8[R_IO_HH])
+#define RSCAN0RMPTR29 (RSCAN0.RMPTR29.UINT32)
+#define RSCAN0RMPTR29L (RSCAN0.RMPTR29.UINT16[R_IO_L])
+#define RSCAN0RMPTR29LL (RSCAN0.RMPTR29.UINT8[R_IO_LL])
+#define RSCAN0RMPTR29LH (RSCAN0.RMPTR29.UINT8[R_IO_LH])
+#define RSCAN0RMPTR29H (RSCAN0.RMPTR29.UINT16[R_IO_H])
+#define RSCAN0RMPTR29HL (RSCAN0.RMPTR29.UINT8[R_IO_HL])
+#define RSCAN0RMPTR29HH (RSCAN0.RMPTR29.UINT8[R_IO_HH])
+#define RSCAN0RMDF029 (RSCAN0.RMDF029.UINT32)
+#define RSCAN0RMDF029L (RSCAN0.RMDF029.UINT16[R_IO_L])
+#define RSCAN0RMDF029LL (RSCAN0.RMDF029.UINT8[R_IO_LL])
+#define RSCAN0RMDF029LH (RSCAN0.RMDF029.UINT8[R_IO_LH])
+#define RSCAN0RMDF029H (RSCAN0.RMDF029.UINT16[R_IO_H])
+#define RSCAN0RMDF029HL (RSCAN0.RMDF029.UINT8[R_IO_HL])
+#define RSCAN0RMDF029HH (RSCAN0.RMDF029.UINT8[R_IO_HH])
+#define RSCAN0RMDF129 (RSCAN0.RMDF129.UINT32)
+#define RSCAN0RMDF129L (RSCAN0.RMDF129.UINT16[R_IO_L])
+#define RSCAN0RMDF129LL (RSCAN0.RMDF129.UINT8[R_IO_LL])
+#define RSCAN0RMDF129LH (RSCAN0.RMDF129.UINT8[R_IO_LH])
+#define RSCAN0RMDF129H (RSCAN0.RMDF129.UINT16[R_IO_H])
+#define RSCAN0RMDF129HL (RSCAN0.RMDF129.UINT8[R_IO_HL])
+#define RSCAN0RMDF129HH (RSCAN0.RMDF129.UINT8[R_IO_HH])
+#define RSCAN0RMID30 (RSCAN0.RMID30.UINT32)
+#define RSCAN0RMID30L (RSCAN0.RMID30.UINT16[R_IO_L])
+#define RSCAN0RMID30LL (RSCAN0.RMID30.UINT8[R_IO_LL])
+#define RSCAN0RMID30LH (RSCAN0.RMID30.UINT8[R_IO_LH])
+#define RSCAN0RMID30H (RSCAN0.RMID30.UINT16[R_IO_H])
+#define RSCAN0RMID30HL (RSCAN0.RMID30.UINT8[R_IO_HL])
+#define RSCAN0RMID30HH (RSCAN0.RMID30.UINT8[R_IO_HH])
+#define RSCAN0RMPTR30 (RSCAN0.RMPTR30.UINT32)
+#define RSCAN0RMPTR30L (RSCAN0.RMPTR30.UINT16[R_IO_L])
+#define RSCAN0RMPTR30LL (RSCAN0.RMPTR30.UINT8[R_IO_LL])
+#define RSCAN0RMPTR30LH (RSCAN0.RMPTR30.UINT8[R_IO_LH])
+#define RSCAN0RMPTR30H (RSCAN0.RMPTR30.UINT16[R_IO_H])
+#define RSCAN0RMPTR30HL (RSCAN0.RMPTR30.UINT8[R_IO_HL])
+#define RSCAN0RMPTR30HH (RSCAN0.RMPTR30.UINT8[R_IO_HH])
+#define RSCAN0RMDF030 (RSCAN0.RMDF030.UINT32)
+#define RSCAN0RMDF030L (RSCAN0.RMDF030.UINT16[R_IO_L])
+#define RSCAN0RMDF030LL (RSCAN0.RMDF030.UINT8[R_IO_LL])
+#define RSCAN0RMDF030LH (RSCAN0.RMDF030.UINT8[R_IO_LH])
+#define RSCAN0RMDF030H (RSCAN0.RMDF030.UINT16[R_IO_H])
+#define RSCAN0RMDF030HL (RSCAN0.RMDF030.UINT8[R_IO_HL])
+#define RSCAN0RMDF030HH (RSCAN0.RMDF030.UINT8[R_IO_HH])
+#define RSCAN0RMDF130 (RSCAN0.RMDF130.UINT32)
+#define RSCAN0RMDF130L (RSCAN0.RMDF130.UINT16[R_IO_L])
+#define RSCAN0RMDF130LL (RSCAN0.RMDF130.UINT8[R_IO_LL])
+#define RSCAN0RMDF130LH (RSCAN0.RMDF130.UINT8[R_IO_LH])
+#define RSCAN0RMDF130H (RSCAN0.RMDF130.UINT16[R_IO_H])
+#define RSCAN0RMDF130HL (RSCAN0.RMDF130.UINT8[R_IO_HL])
+#define RSCAN0RMDF130HH (RSCAN0.RMDF130.UINT8[R_IO_HH])
+#define RSCAN0RMID31 (RSCAN0.RMID31.UINT32)
+#define RSCAN0RMID31L (RSCAN0.RMID31.UINT16[R_IO_L])
+#define RSCAN0RMID31LL (RSCAN0.RMID31.UINT8[R_IO_LL])
+#define RSCAN0RMID31LH (RSCAN0.RMID31.UINT8[R_IO_LH])
+#define RSCAN0RMID31H (RSCAN0.RMID31.UINT16[R_IO_H])
+#define RSCAN0RMID31HL (RSCAN0.RMID31.UINT8[R_IO_HL])
+#define RSCAN0RMID31HH (RSCAN0.RMID31.UINT8[R_IO_HH])
+#define RSCAN0RMPTR31 (RSCAN0.RMPTR31.UINT32)
+#define RSCAN0RMPTR31L (RSCAN0.RMPTR31.UINT16[R_IO_L])
+#define RSCAN0RMPTR31LL (RSCAN0.RMPTR31.UINT8[R_IO_LL])
+#define RSCAN0RMPTR31LH (RSCAN0.RMPTR31.UINT8[R_IO_LH])
+#define RSCAN0RMPTR31H (RSCAN0.RMPTR31.UINT16[R_IO_H])
+#define RSCAN0RMPTR31HL (RSCAN0.RMPTR31.UINT8[R_IO_HL])
+#define RSCAN0RMPTR31HH (RSCAN0.RMPTR31.UINT8[R_IO_HH])
+#define RSCAN0RMDF031 (RSCAN0.RMDF031.UINT32)
+#define RSCAN0RMDF031L (RSCAN0.RMDF031.UINT16[R_IO_L])
+#define RSCAN0RMDF031LL (RSCAN0.RMDF031.UINT8[R_IO_LL])
+#define RSCAN0RMDF031LH (RSCAN0.RMDF031.UINT8[R_IO_LH])
+#define RSCAN0RMDF031H (RSCAN0.RMDF031.UINT16[R_IO_H])
+#define RSCAN0RMDF031HL (RSCAN0.RMDF031.UINT8[R_IO_HL])
+#define RSCAN0RMDF031HH (RSCAN0.RMDF031.UINT8[R_IO_HH])
+#define RSCAN0RMDF131 (RSCAN0.RMDF131.UINT32)
+#define RSCAN0RMDF131L (RSCAN0.RMDF131.UINT16[R_IO_L])
+#define RSCAN0RMDF131LL (RSCAN0.RMDF131.UINT8[R_IO_LL])
+#define RSCAN0RMDF131LH (RSCAN0.RMDF131.UINT8[R_IO_LH])
+#define RSCAN0RMDF131H (RSCAN0.RMDF131.UINT16[R_IO_H])
+#define RSCAN0RMDF131HL (RSCAN0.RMDF131.UINT8[R_IO_HL])
+#define RSCAN0RMDF131HH (RSCAN0.RMDF131.UINT8[R_IO_HH])
+#define RSCAN0RMID32 (RSCAN0.RMID32.UINT32)
+#define RSCAN0RMID32L (RSCAN0.RMID32.UINT16[R_IO_L])
+#define RSCAN0RMID32LL (RSCAN0.RMID32.UINT8[R_IO_LL])
+#define RSCAN0RMID32LH (RSCAN0.RMID32.UINT8[R_IO_LH])
+#define RSCAN0RMID32H (RSCAN0.RMID32.UINT16[R_IO_H])
+#define RSCAN0RMID32HL (RSCAN0.RMID32.UINT8[R_IO_HL])
+#define RSCAN0RMID32HH (RSCAN0.RMID32.UINT8[R_IO_HH])
+#define RSCAN0RMPTR32 (RSCAN0.RMPTR32.UINT32)
+#define RSCAN0RMPTR32L (RSCAN0.RMPTR32.UINT16[R_IO_L])
+#define RSCAN0RMPTR32LL (RSCAN0.RMPTR32.UINT8[R_IO_LL])
+#define RSCAN0RMPTR32LH (RSCAN0.RMPTR32.UINT8[R_IO_LH])
+#define RSCAN0RMPTR32H (RSCAN0.RMPTR32.UINT16[R_IO_H])
+#define RSCAN0RMPTR32HL (RSCAN0.RMPTR32.UINT8[R_IO_HL])
+#define RSCAN0RMPTR32HH (RSCAN0.RMPTR32.UINT8[R_IO_HH])
+#define RSCAN0RMDF032 (RSCAN0.RMDF032.UINT32)
+#define RSCAN0RMDF032L (RSCAN0.RMDF032.UINT16[R_IO_L])
+#define RSCAN0RMDF032LL (RSCAN0.RMDF032.UINT8[R_IO_LL])
+#define RSCAN0RMDF032LH (RSCAN0.RMDF032.UINT8[R_IO_LH])
+#define RSCAN0RMDF032H (RSCAN0.RMDF032.UINT16[R_IO_H])
+#define RSCAN0RMDF032HL (RSCAN0.RMDF032.UINT8[R_IO_HL])
+#define RSCAN0RMDF032HH (RSCAN0.RMDF032.UINT8[R_IO_HH])
+#define RSCAN0RMDF132 (RSCAN0.RMDF132.UINT32)
+#define RSCAN0RMDF132L (RSCAN0.RMDF132.UINT16[R_IO_L])
+#define RSCAN0RMDF132LL (RSCAN0.RMDF132.UINT8[R_IO_LL])
+#define RSCAN0RMDF132LH (RSCAN0.RMDF132.UINT8[R_IO_LH])
+#define RSCAN0RMDF132H (RSCAN0.RMDF132.UINT16[R_IO_H])
+#define RSCAN0RMDF132HL (RSCAN0.RMDF132.UINT8[R_IO_HL])
+#define RSCAN0RMDF132HH (RSCAN0.RMDF132.UINT8[R_IO_HH])
+#define RSCAN0RMID33 (RSCAN0.RMID33.UINT32)
+#define RSCAN0RMID33L (RSCAN0.RMID33.UINT16[R_IO_L])
+#define RSCAN0RMID33LL (RSCAN0.RMID33.UINT8[R_IO_LL])
+#define RSCAN0RMID33LH (RSCAN0.RMID33.UINT8[R_IO_LH])
+#define RSCAN0RMID33H (RSCAN0.RMID33.UINT16[R_IO_H])
+#define RSCAN0RMID33HL (RSCAN0.RMID33.UINT8[R_IO_HL])
+#define RSCAN0RMID33HH (RSCAN0.RMID33.UINT8[R_IO_HH])
+#define RSCAN0RMPTR33 (RSCAN0.RMPTR33.UINT32)
+#define RSCAN0RMPTR33L (RSCAN0.RMPTR33.UINT16[R_IO_L])
+#define RSCAN0RMPTR33LL (RSCAN0.RMPTR33.UINT8[R_IO_LL])
+#define RSCAN0RMPTR33LH (RSCAN0.RMPTR33.UINT8[R_IO_LH])
+#define RSCAN0RMPTR33H (RSCAN0.RMPTR33.UINT16[R_IO_H])
+#define RSCAN0RMPTR33HL (RSCAN0.RMPTR33.UINT8[R_IO_HL])
+#define RSCAN0RMPTR33HH (RSCAN0.RMPTR33.UINT8[R_IO_HH])
+#define RSCAN0RMDF033 (RSCAN0.RMDF033.UINT32)
+#define RSCAN0RMDF033L (RSCAN0.RMDF033.UINT16[R_IO_L])
+#define RSCAN0RMDF033LL (RSCAN0.RMDF033.UINT8[R_IO_LL])
+#define RSCAN0RMDF033LH (RSCAN0.RMDF033.UINT8[R_IO_LH])
+#define RSCAN0RMDF033H (RSCAN0.RMDF033.UINT16[R_IO_H])
+#define RSCAN0RMDF033HL (RSCAN0.RMDF033.UINT8[R_IO_HL])
+#define RSCAN0RMDF033HH (RSCAN0.RMDF033.UINT8[R_IO_HH])
+#define RSCAN0RMDF133 (RSCAN0.RMDF133.UINT32)
+#define RSCAN0RMDF133L (RSCAN0.RMDF133.UINT16[R_IO_L])
+#define RSCAN0RMDF133LL (RSCAN0.RMDF133.UINT8[R_IO_LL])
+#define RSCAN0RMDF133LH (RSCAN0.RMDF133.UINT8[R_IO_LH])
+#define RSCAN0RMDF133H (RSCAN0.RMDF133.UINT16[R_IO_H])
+#define RSCAN0RMDF133HL (RSCAN0.RMDF133.UINT8[R_IO_HL])
+#define RSCAN0RMDF133HH (RSCAN0.RMDF133.UINT8[R_IO_HH])
+#define RSCAN0RMID34 (RSCAN0.RMID34.UINT32)
+#define RSCAN0RMID34L (RSCAN0.RMID34.UINT16[R_IO_L])
+#define RSCAN0RMID34LL (RSCAN0.RMID34.UINT8[R_IO_LL])
+#define RSCAN0RMID34LH (RSCAN0.RMID34.UINT8[R_IO_LH])
+#define RSCAN0RMID34H (RSCAN0.RMID34.UINT16[R_IO_H])
+#define RSCAN0RMID34HL (RSCAN0.RMID34.UINT8[R_IO_HL])
+#define RSCAN0RMID34HH (RSCAN0.RMID34.UINT8[R_IO_HH])
+#define RSCAN0RMPTR34 (RSCAN0.RMPTR34.UINT32)
+#define RSCAN0RMPTR34L (RSCAN0.RMPTR34.UINT16[R_IO_L])
+#define RSCAN0RMPTR34LL (RSCAN0.RMPTR34.UINT8[R_IO_LL])
+#define RSCAN0RMPTR34LH (RSCAN0.RMPTR34.UINT8[R_IO_LH])
+#define RSCAN0RMPTR34H (RSCAN0.RMPTR34.UINT16[R_IO_H])
+#define RSCAN0RMPTR34HL (RSCAN0.RMPTR34.UINT8[R_IO_HL])
+#define RSCAN0RMPTR34HH (RSCAN0.RMPTR34.UINT8[R_IO_HH])
+#define RSCAN0RMDF034 (RSCAN0.RMDF034.UINT32)
+#define RSCAN0RMDF034L (RSCAN0.RMDF034.UINT16[R_IO_L])
+#define RSCAN0RMDF034LL (RSCAN0.RMDF034.UINT8[R_IO_LL])
+#define RSCAN0RMDF034LH (RSCAN0.RMDF034.UINT8[R_IO_LH])
+#define RSCAN0RMDF034H (RSCAN0.RMDF034.UINT16[R_IO_H])
+#define RSCAN0RMDF034HL (RSCAN0.RMDF034.UINT8[R_IO_HL])
+#define RSCAN0RMDF034HH (RSCAN0.RMDF034.UINT8[R_IO_HH])
+#define RSCAN0RMDF134 (RSCAN0.RMDF134.UINT32)
+#define RSCAN0RMDF134L (RSCAN0.RMDF134.UINT16[R_IO_L])
+#define RSCAN0RMDF134LL (RSCAN0.RMDF134.UINT8[R_IO_LL])
+#define RSCAN0RMDF134LH (RSCAN0.RMDF134.UINT8[R_IO_LH])
+#define RSCAN0RMDF134H (RSCAN0.RMDF134.UINT16[R_IO_H])
+#define RSCAN0RMDF134HL (RSCAN0.RMDF134.UINT8[R_IO_HL])
+#define RSCAN0RMDF134HH (RSCAN0.RMDF134.UINT8[R_IO_HH])
+#define RSCAN0RMID35 (RSCAN0.RMID35.UINT32)
+#define RSCAN0RMID35L (RSCAN0.RMID35.UINT16[R_IO_L])
+#define RSCAN0RMID35LL (RSCAN0.RMID35.UINT8[R_IO_LL])
+#define RSCAN0RMID35LH (RSCAN0.RMID35.UINT8[R_IO_LH])
+#define RSCAN0RMID35H (RSCAN0.RMID35.UINT16[R_IO_H])
+#define RSCAN0RMID35HL (RSCAN0.RMID35.UINT8[R_IO_HL])
+#define RSCAN0RMID35HH (RSCAN0.RMID35.UINT8[R_IO_HH])
+#define RSCAN0RMPTR35 (RSCAN0.RMPTR35.UINT32)
+#define RSCAN0RMPTR35L (RSCAN0.RMPTR35.UINT16[R_IO_L])
+#define RSCAN0RMPTR35LL (RSCAN0.RMPTR35.UINT8[R_IO_LL])
+#define RSCAN0RMPTR35LH (RSCAN0.RMPTR35.UINT8[R_IO_LH])
+#define RSCAN0RMPTR35H (RSCAN0.RMPTR35.UINT16[R_IO_H])
+#define RSCAN0RMPTR35HL (RSCAN0.RMPTR35.UINT8[R_IO_HL])
+#define RSCAN0RMPTR35HH (RSCAN0.RMPTR35.UINT8[R_IO_HH])
+#define RSCAN0RMDF035 (RSCAN0.RMDF035.UINT32)
+#define RSCAN0RMDF035L (RSCAN0.RMDF035.UINT16[R_IO_L])
+#define RSCAN0RMDF035LL (RSCAN0.RMDF035.UINT8[R_IO_LL])
+#define RSCAN0RMDF035LH (RSCAN0.RMDF035.UINT8[R_IO_LH])
+#define RSCAN0RMDF035H (RSCAN0.RMDF035.UINT16[R_IO_H])
+#define RSCAN0RMDF035HL (RSCAN0.RMDF035.UINT8[R_IO_HL])
+#define RSCAN0RMDF035HH (RSCAN0.RMDF035.UINT8[R_IO_HH])
+#define RSCAN0RMDF135 (RSCAN0.RMDF135.UINT32)
+#define RSCAN0RMDF135L (RSCAN0.RMDF135.UINT16[R_IO_L])
+#define RSCAN0RMDF135LL (RSCAN0.RMDF135.UINT8[R_IO_LL])
+#define RSCAN0RMDF135LH (RSCAN0.RMDF135.UINT8[R_IO_LH])
+#define RSCAN0RMDF135H (RSCAN0.RMDF135.UINT16[R_IO_H])
+#define RSCAN0RMDF135HL (RSCAN0.RMDF135.UINT8[R_IO_HL])
+#define RSCAN0RMDF135HH (RSCAN0.RMDF135.UINT8[R_IO_HH])
+#define RSCAN0RMID36 (RSCAN0.RMID36.UINT32)
+#define RSCAN0RMID36L (RSCAN0.RMID36.UINT16[R_IO_L])
+#define RSCAN0RMID36LL (RSCAN0.RMID36.UINT8[R_IO_LL])
+#define RSCAN0RMID36LH (RSCAN0.RMID36.UINT8[R_IO_LH])
+#define RSCAN0RMID36H (RSCAN0.RMID36.UINT16[R_IO_H])
+#define RSCAN0RMID36HL (RSCAN0.RMID36.UINT8[R_IO_HL])
+#define RSCAN0RMID36HH (RSCAN0.RMID36.UINT8[R_IO_HH])
+#define RSCAN0RMPTR36 (RSCAN0.RMPTR36.UINT32)
+#define RSCAN0RMPTR36L (RSCAN0.RMPTR36.UINT16[R_IO_L])
+#define RSCAN0RMPTR36LL (RSCAN0.RMPTR36.UINT8[R_IO_LL])
+#define RSCAN0RMPTR36LH (RSCAN0.RMPTR36.UINT8[R_IO_LH])
+#define RSCAN0RMPTR36H (RSCAN0.RMPTR36.UINT16[R_IO_H])
+#define RSCAN0RMPTR36HL (RSCAN0.RMPTR36.UINT8[R_IO_HL])
+#define RSCAN0RMPTR36HH (RSCAN0.RMPTR36.UINT8[R_IO_HH])
+#define RSCAN0RMDF036 (RSCAN0.RMDF036.UINT32)
+#define RSCAN0RMDF036L (RSCAN0.RMDF036.UINT16[R_IO_L])
+#define RSCAN0RMDF036LL (RSCAN0.RMDF036.UINT8[R_IO_LL])
+#define RSCAN0RMDF036LH (RSCAN0.RMDF036.UINT8[R_IO_LH])
+#define RSCAN0RMDF036H (RSCAN0.RMDF036.UINT16[R_IO_H])
+#define RSCAN0RMDF036HL (RSCAN0.RMDF036.UINT8[R_IO_HL])
+#define RSCAN0RMDF036HH (RSCAN0.RMDF036.UINT8[R_IO_HH])
+#define RSCAN0RMDF136 (RSCAN0.RMDF136.UINT32)
+#define RSCAN0RMDF136L (RSCAN0.RMDF136.UINT16[R_IO_L])
+#define RSCAN0RMDF136LL (RSCAN0.RMDF136.UINT8[R_IO_LL])
+#define RSCAN0RMDF136LH (RSCAN0.RMDF136.UINT8[R_IO_LH])
+#define RSCAN0RMDF136H (RSCAN0.RMDF136.UINT16[R_IO_H])
+#define RSCAN0RMDF136HL (RSCAN0.RMDF136.UINT8[R_IO_HL])
+#define RSCAN0RMDF136HH (RSCAN0.RMDF136.UINT8[R_IO_HH])
+#define RSCAN0RMID37 (RSCAN0.RMID37.UINT32)
+#define RSCAN0RMID37L (RSCAN0.RMID37.UINT16[R_IO_L])
+#define RSCAN0RMID37LL (RSCAN0.RMID37.UINT8[R_IO_LL])
+#define RSCAN0RMID37LH (RSCAN0.RMID37.UINT8[R_IO_LH])
+#define RSCAN0RMID37H (RSCAN0.RMID37.UINT16[R_IO_H])
+#define RSCAN0RMID37HL (RSCAN0.RMID37.UINT8[R_IO_HL])
+#define RSCAN0RMID37HH (RSCAN0.RMID37.UINT8[R_IO_HH])
+#define RSCAN0RMPTR37 (RSCAN0.RMPTR37.UINT32)
+#define RSCAN0RMPTR37L (RSCAN0.RMPTR37.UINT16[R_IO_L])
+#define RSCAN0RMPTR37LL (RSCAN0.RMPTR37.UINT8[R_IO_LL])
+#define RSCAN0RMPTR37LH (RSCAN0.RMPTR37.UINT8[R_IO_LH])
+#define RSCAN0RMPTR37H (RSCAN0.RMPTR37.UINT16[R_IO_H])
+#define RSCAN0RMPTR37HL (RSCAN0.RMPTR37.UINT8[R_IO_HL])
+#define RSCAN0RMPTR37HH (RSCAN0.RMPTR37.UINT8[R_IO_HH])
+#define RSCAN0RMDF037 (RSCAN0.RMDF037.UINT32)
+#define RSCAN0RMDF037L (RSCAN0.RMDF037.UINT16[R_IO_L])
+#define RSCAN0RMDF037LL (RSCAN0.RMDF037.UINT8[R_IO_LL])
+#define RSCAN0RMDF037LH (RSCAN0.RMDF037.UINT8[R_IO_LH])
+#define RSCAN0RMDF037H (RSCAN0.RMDF037.UINT16[R_IO_H])
+#define RSCAN0RMDF037HL (RSCAN0.RMDF037.UINT8[R_IO_HL])
+#define RSCAN0RMDF037HH (RSCAN0.RMDF037.UINT8[R_IO_HH])
+#define RSCAN0RMDF137 (RSCAN0.RMDF137.UINT32)
+#define RSCAN0RMDF137L (RSCAN0.RMDF137.UINT16[R_IO_L])
+#define RSCAN0RMDF137LL (RSCAN0.RMDF137.UINT8[R_IO_LL])
+#define RSCAN0RMDF137LH (RSCAN0.RMDF137.UINT8[R_IO_LH])
+#define RSCAN0RMDF137H (RSCAN0.RMDF137.UINT16[R_IO_H])
+#define RSCAN0RMDF137HL (RSCAN0.RMDF137.UINT8[R_IO_HL])
+#define RSCAN0RMDF137HH (RSCAN0.RMDF137.UINT8[R_IO_HH])
+#define RSCAN0RMID38 (RSCAN0.RMID38.UINT32)
+#define RSCAN0RMID38L (RSCAN0.RMID38.UINT16[R_IO_L])
+#define RSCAN0RMID38LL (RSCAN0.RMID38.UINT8[R_IO_LL])
+#define RSCAN0RMID38LH (RSCAN0.RMID38.UINT8[R_IO_LH])
+#define RSCAN0RMID38H (RSCAN0.RMID38.UINT16[R_IO_H])
+#define RSCAN0RMID38HL (RSCAN0.RMID38.UINT8[R_IO_HL])
+#define RSCAN0RMID38HH (RSCAN0.RMID38.UINT8[R_IO_HH])
+#define RSCAN0RMPTR38 (RSCAN0.RMPTR38.UINT32)
+#define RSCAN0RMPTR38L (RSCAN0.RMPTR38.UINT16[R_IO_L])
+#define RSCAN0RMPTR38LL (RSCAN0.RMPTR38.UINT8[R_IO_LL])
+#define RSCAN0RMPTR38LH (RSCAN0.RMPTR38.UINT8[R_IO_LH])
+#define RSCAN0RMPTR38H (RSCAN0.RMPTR38.UINT16[R_IO_H])
+#define RSCAN0RMPTR38HL (RSCAN0.RMPTR38.UINT8[R_IO_HL])
+#define RSCAN0RMPTR38HH (RSCAN0.RMPTR38.UINT8[R_IO_HH])
+#define RSCAN0RMDF038 (RSCAN0.RMDF038.UINT32)
+#define RSCAN0RMDF038L (RSCAN0.RMDF038.UINT16[R_IO_L])
+#define RSCAN0RMDF038LL (RSCAN0.RMDF038.UINT8[R_IO_LL])
+#define RSCAN0RMDF038LH (RSCAN0.RMDF038.UINT8[R_IO_LH])
+#define RSCAN0RMDF038H (RSCAN0.RMDF038.UINT16[R_IO_H])
+#define RSCAN0RMDF038HL (RSCAN0.RMDF038.UINT8[R_IO_HL])
+#define RSCAN0RMDF038HH (RSCAN0.RMDF038.UINT8[R_IO_HH])
+#define RSCAN0RMDF138 (RSCAN0.RMDF138.UINT32)
+#define RSCAN0RMDF138L (RSCAN0.RMDF138.UINT16[R_IO_L])
+#define RSCAN0RMDF138LL (RSCAN0.RMDF138.UINT8[R_IO_LL])
+#define RSCAN0RMDF138LH (RSCAN0.RMDF138.UINT8[R_IO_LH])
+#define RSCAN0RMDF138H (RSCAN0.RMDF138.UINT16[R_IO_H])
+#define RSCAN0RMDF138HL (RSCAN0.RMDF138.UINT8[R_IO_HL])
+#define RSCAN0RMDF138HH (RSCAN0.RMDF138.UINT8[R_IO_HH])
+#define RSCAN0RMID39 (RSCAN0.RMID39.UINT32)
+#define RSCAN0RMID39L (RSCAN0.RMID39.UINT16[R_IO_L])
+#define RSCAN0RMID39LL (RSCAN0.RMID39.UINT8[R_IO_LL])
+#define RSCAN0RMID39LH (RSCAN0.RMID39.UINT8[R_IO_LH])
+#define RSCAN0RMID39H (RSCAN0.RMID39.UINT16[R_IO_H])
+#define RSCAN0RMID39HL (RSCAN0.RMID39.UINT8[R_IO_HL])
+#define RSCAN0RMID39HH (RSCAN0.RMID39.UINT8[R_IO_HH])
+#define RSCAN0RMPTR39 (RSCAN0.RMPTR39.UINT32)
+#define RSCAN0RMPTR39L (RSCAN0.RMPTR39.UINT16[R_IO_L])
+#define RSCAN0RMPTR39LL (RSCAN0.RMPTR39.UINT8[R_IO_LL])
+#define RSCAN0RMPTR39LH (RSCAN0.RMPTR39.UINT8[R_IO_LH])
+#define RSCAN0RMPTR39H (RSCAN0.RMPTR39.UINT16[R_IO_H])
+#define RSCAN0RMPTR39HL (RSCAN0.RMPTR39.UINT8[R_IO_HL])
+#define RSCAN0RMPTR39HH (RSCAN0.RMPTR39.UINT8[R_IO_HH])
+#define RSCAN0RMDF039 (RSCAN0.RMDF039.UINT32)
+#define RSCAN0RMDF039L (RSCAN0.RMDF039.UINT16[R_IO_L])
+#define RSCAN0RMDF039LL (RSCAN0.RMDF039.UINT8[R_IO_LL])
+#define RSCAN0RMDF039LH (RSCAN0.RMDF039.UINT8[R_IO_LH])
+#define RSCAN0RMDF039H (RSCAN0.RMDF039.UINT16[R_IO_H])
+#define RSCAN0RMDF039HL (RSCAN0.RMDF039.UINT8[R_IO_HL])
+#define RSCAN0RMDF039HH (RSCAN0.RMDF039.UINT8[R_IO_HH])
+#define RSCAN0RMDF139 (RSCAN0.RMDF139.UINT32)
+#define RSCAN0RMDF139L (RSCAN0.RMDF139.UINT16[R_IO_L])
+#define RSCAN0RMDF139LL (RSCAN0.RMDF139.UINT8[R_IO_LL])
+#define RSCAN0RMDF139LH (RSCAN0.RMDF139.UINT8[R_IO_LH])
+#define RSCAN0RMDF139H (RSCAN0.RMDF139.UINT16[R_IO_H])
+#define RSCAN0RMDF139HL (RSCAN0.RMDF139.UINT8[R_IO_HL])
+#define RSCAN0RMDF139HH (RSCAN0.RMDF139.UINT8[R_IO_HH])
+#define RSCAN0RMID40 (RSCAN0.RMID40.UINT32)
+#define RSCAN0RMID40L (RSCAN0.RMID40.UINT16[R_IO_L])
+#define RSCAN0RMID40LL (RSCAN0.RMID40.UINT8[R_IO_LL])
+#define RSCAN0RMID40LH (RSCAN0.RMID40.UINT8[R_IO_LH])
+#define RSCAN0RMID40H (RSCAN0.RMID40.UINT16[R_IO_H])
+#define RSCAN0RMID40HL (RSCAN0.RMID40.UINT8[R_IO_HL])
+#define RSCAN0RMID40HH (RSCAN0.RMID40.UINT8[R_IO_HH])
+#define RSCAN0RMPTR40 (RSCAN0.RMPTR40.UINT32)
+#define RSCAN0RMPTR40L (RSCAN0.RMPTR40.UINT16[R_IO_L])
+#define RSCAN0RMPTR40LL (RSCAN0.RMPTR40.UINT8[R_IO_LL])
+#define RSCAN0RMPTR40LH (RSCAN0.RMPTR40.UINT8[R_IO_LH])
+#define RSCAN0RMPTR40H (RSCAN0.RMPTR40.UINT16[R_IO_H])
+#define RSCAN0RMPTR40HL (RSCAN0.RMPTR40.UINT8[R_IO_HL])
+#define RSCAN0RMPTR40HH (RSCAN0.RMPTR40.UINT8[R_IO_HH])
+#define RSCAN0RMDF040 (RSCAN0.RMDF040.UINT32)
+#define RSCAN0RMDF040L (RSCAN0.RMDF040.UINT16[R_IO_L])
+#define RSCAN0RMDF040LL (RSCAN0.RMDF040.UINT8[R_IO_LL])
+#define RSCAN0RMDF040LH (RSCAN0.RMDF040.UINT8[R_IO_LH])
+#define RSCAN0RMDF040H (RSCAN0.RMDF040.UINT16[R_IO_H])
+#define RSCAN0RMDF040HL (RSCAN0.RMDF040.UINT8[R_IO_HL])
+#define RSCAN0RMDF040HH (RSCAN0.RMDF040.UINT8[R_IO_HH])
+#define RSCAN0RMDF140 (RSCAN0.RMDF140.UINT32)
+#define RSCAN0RMDF140L (RSCAN0.RMDF140.UINT16[R_IO_L])
+#define RSCAN0RMDF140LL (RSCAN0.RMDF140.UINT8[R_IO_LL])
+#define RSCAN0RMDF140LH (RSCAN0.RMDF140.UINT8[R_IO_LH])
+#define RSCAN0RMDF140H (RSCAN0.RMDF140.UINT16[R_IO_H])
+#define RSCAN0RMDF140HL (RSCAN0.RMDF140.UINT8[R_IO_HL])
+#define RSCAN0RMDF140HH (RSCAN0.RMDF140.UINT8[R_IO_HH])
+#define RSCAN0RMID41 (RSCAN0.RMID41.UINT32)
+#define RSCAN0RMID41L (RSCAN0.RMID41.UINT16[R_IO_L])
+#define RSCAN0RMID41LL (RSCAN0.RMID41.UINT8[R_IO_LL])
+#define RSCAN0RMID41LH (RSCAN0.RMID41.UINT8[R_IO_LH])
+#define RSCAN0RMID41H (RSCAN0.RMID41.UINT16[R_IO_H])
+#define RSCAN0RMID41HL (RSCAN0.RMID41.UINT8[R_IO_HL])
+#define RSCAN0RMID41HH (RSCAN0.RMID41.UINT8[R_IO_HH])
+#define RSCAN0RMPTR41 (RSCAN0.RMPTR41.UINT32)
+#define RSCAN0RMPTR41L (RSCAN0.RMPTR41.UINT16[R_IO_L])
+#define RSCAN0RMPTR41LL (RSCAN0.RMPTR41.UINT8[R_IO_LL])
+#define RSCAN0RMPTR41LH (RSCAN0.RMPTR41.UINT8[R_IO_LH])
+#define RSCAN0RMPTR41H (RSCAN0.RMPTR41.UINT16[R_IO_H])
+#define RSCAN0RMPTR41HL (RSCAN0.RMPTR41.UINT8[R_IO_HL])
+#define RSCAN0RMPTR41HH (RSCAN0.RMPTR41.UINT8[R_IO_HH])
+#define RSCAN0RMDF041 (RSCAN0.RMDF041.UINT32)
+#define RSCAN0RMDF041L (RSCAN0.RMDF041.UINT16[R_IO_L])
+#define RSCAN0RMDF041LL (RSCAN0.RMDF041.UINT8[R_IO_LL])
+#define RSCAN0RMDF041LH (RSCAN0.RMDF041.UINT8[R_IO_LH])
+#define RSCAN0RMDF041H (RSCAN0.RMDF041.UINT16[R_IO_H])
+#define RSCAN0RMDF041HL (RSCAN0.RMDF041.UINT8[R_IO_HL])
+#define RSCAN0RMDF041HH (RSCAN0.RMDF041.UINT8[R_IO_HH])
+#define RSCAN0RMDF141 (RSCAN0.RMDF141.UINT32)
+#define RSCAN0RMDF141L (RSCAN0.RMDF141.UINT16[R_IO_L])
+#define RSCAN0RMDF141LL (RSCAN0.RMDF141.UINT8[R_IO_LL])
+#define RSCAN0RMDF141LH (RSCAN0.RMDF141.UINT8[R_IO_LH])
+#define RSCAN0RMDF141H (RSCAN0.RMDF141.UINT16[R_IO_H])
+#define RSCAN0RMDF141HL (RSCAN0.RMDF141.UINT8[R_IO_HL])
+#define RSCAN0RMDF141HH (RSCAN0.RMDF141.UINT8[R_IO_HH])
+#define RSCAN0RMID42 (RSCAN0.RMID42.UINT32)
+#define RSCAN0RMID42L (RSCAN0.RMID42.UINT16[R_IO_L])
+#define RSCAN0RMID42LL (RSCAN0.RMID42.UINT8[R_IO_LL])
+#define RSCAN0RMID42LH (RSCAN0.RMID42.UINT8[R_IO_LH])
+#define RSCAN0RMID42H (RSCAN0.RMID42.UINT16[R_IO_H])
+#define RSCAN0RMID42HL (RSCAN0.RMID42.UINT8[R_IO_HL])
+#define RSCAN0RMID42HH (RSCAN0.RMID42.UINT8[R_IO_HH])
+#define RSCAN0RMPTR42 (RSCAN0.RMPTR42.UINT32)
+#define RSCAN0RMPTR42L (RSCAN0.RMPTR42.UINT16[R_IO_L])
+#define RSCAN0RMPTR42LL (RSCAN0.RMPTR42.UINT8[R_IO_LL])
+#define RSCAN0RMPTR42LH (RSCAN0.RMPTR42.UINT8[R_IO_LH])
+#define RSCAN0RMPTR42H (RSCAN0.RMPTR42.UINT16[R_IO_H])
+#define RSCAN0RMPTR42HL (RSCAN0.RMPTR42.UINT8[R_IO_HL])
+#define RSCAN0RMPTR42HH (RSCAN0.RMPTR42.UINT8[R_IO_HH])
+#define RSCAN0RMDF042 (RSCAN0.RMDF042.UINT32)
+#define RSCAN0RMDF042L (RSCAN0.RMDF042.UINT16[R_IO_L])
+#define RSCAN0RMDF042LL (RSCAN0.RMDF042.UINT8[R_IO_LL])
+#define RSCAN0RMDF042LH (RSCAN0.RMDF042.UINT8[R_IO_LH])
+#define RSCAN0RMDF042H (RSCAN0.RMDF042.UINT16[R_IO_H])
+#define RSCAN0RMDF042HL (RSCAN0.RMDF042.UINT8[R_IO_HL])
+#define RSCAN0RMDF042HH (RSCAN0.RMDF042.UINT8[R_IO_HH])
+#define RSCAN0RMDF142 (RSCAN0.RMDF142.UINT32)
+#define RSCAN0RMDF142L (RSCAN0.RMDF142.UINT16[R_IO_L])
+#define RSCAN0RMDF142LL (RSCAN0.RMDF142.UINT8[R_IO_LL])
+#define RSCAN0RMDF142LH (RSCAN0.RMDF142.UINT8[R_IO_LH])
+#define RSCAN0RMDF142H (RSCAN0.RMDF142.UINT16[R_IO_H])
+#define RSCAN0RMDF142HL (RSCAN0.RMDF142.UINT8[R_IO_HL])
+#define RSCAN0RMDF142HH (RSCAN0.RMDF142.UINT8[R_IO_HH])
+#define RSCAN0RMID43 (RSCAN0.RMID43.UINT32)
+#define RSCAN0RMID43L (RSCAN0.RMID43.UINT16[R_IO_L])
+#define RSCAN0RMID43LL (RSCAN0.RMID43.UINT8[R_IO_LL])
+#define RSCAN0RMID43LH (RSCAN0.RMID43.UINT8[R_IO_LH])
+#define RSCAN0RMID43H (RSCAN0.RMID43.UINT16[R_IO_H])
+#define RSCAN0RMID43HL (RSCAN0.RMID43.UINT8[R_IO_HL])
+#define RSCAN0RMID43HH (RSCAN0.RMID43.UINT8[R_IO_HH])
+#define RSCAN0RMPTR43 (RSCAN0.RMPTR43.UINT32)
+#define RSCAN0RMPTR43L (RSCAN0.RMPTR43.UINT16[R_IO_L])
+#define RSCAN0RMPTR43LL (RSCAN0.RMPTR43.UINT8[R_IO_LL])
+#define RSCAN0RMPTR43LH (RSCAN0.RMPTR43.UINT8[R_IO_LH])
+#define RSCAN0RMPTR43H (RSCAN0.RMPTR43.UINT16[R_IO_H])
+#define RSCAN0RMPTR43HL (RSCAN0.RMPTR43.UINT8[R_IO_HL])
+#define RSCAN0RMPTR43HH (RSCAN0.RMPTR43.UINT8[R_IO_HH])
+#define RSCAN0RMDF043 (RSCAN0.RMDF043.UINT32)
+#define RSCAN0RMDF043L (RSCAN0.RMDF043.UINT16[R_IO_L])
+#define RSCAN0RMDF043LL (RSCAN0.RMDF043.UINT8[R_IO_LL])
+#define RSCAN0RMDF043LH (RSCAN0.RMDF043.UINT8[R_IO_LH])
+#define RSCAN0RMDF043H (RSCAN0.RMDF043.UINT16[R_IO_H])
+#define RSCAN0RMDF043HL (RSCAN0.RMDF043.UINT8[R_IO_HL])
+#define RSCAN0RMDF043HH (RSCAN0.RMDF043.UINT8[R_IO_HH])
+#define RSCAN0RMDF143 (RSCAN0.RMDF143.UINT32)
+#define RSCAN0RMDF143L (RSCAN0.RMDF143.UINT16[R_IO_L])
+#define RSCAN0RMDF143LL (RSCAN0.RMDF143.UINT8[R_IO_LL])
+#define RSCAN0RMDF143LH (RSCAN0.RMDF143.UINT8[R_IO_LH])
+#define RSCAN0RMDF143H (RSCAN0.RMDF143.UINT16[R_IO_H])
+#define RSCAN0RMDF143HL (RSCAN0.RMDF143.UINT8[R_IO_HL])
+#define RSCAN0RMDF143HH (RSCAN0.RMDF143.UINT8[R_IO_HH])
+#define RSCAN0RMID44 (RSCAN0.RMID44.UINT32)
+#define RSCAN0RMID44L (RSCAN0.RMID44.UINT16[R_IO_L])
+#define RSCAN0RMID44LL (RSCAN0.RMID44.UINT8[R_IO_LL])
+#define RSCAN0RMID44LH (RSCAN0.RMID44.UINT8[R_IO_LH])
+#define RSCAN0RMID44H (RSCAN0.RMID44.UINT16[R_IO_H])
+#define RSCAN0RMID44HL (RSCAN0.RMID44.UINT8[R_IO_HL])
+#define RSCAN0RMID44HH (RSCAN0.RMID44.UINT8[R_IO_HH])
+#define RSCAN0RMPTR44 (RSCAN0.RMPTR44.UINT32)
+#define RSCAN0RMPTR44L (RSCAN0.RMPTR44.UINT16[R_IO_L])
+#define RSCAN0RMPTR44LL (RSCAN0.RMPTR44.UINT8[R_IO_LL])
+#define RSCAN0RMPTR44LH (RSCAN0.RMPTR44.UINT8[R_IO_LH])
+#define RSCAN0RMPTR44H (RSCAN0.RMPTR44.UINT16[R_IO_H])
+#define RSCAN0RMPTR44HL (RSCAN0.RMPTR44.UINT8[R_IO_HL])
+#define RSCAN0RMPTR44HH (RSCAN0.RMPTR44.UINT8[R_IO_HH])
+#define RSCAN0RMDF044 (RSCAN0.RMDF044.UINT32)
+#define RSCAN0RMDF044L (RSCAN0.RMDF044.UINT16[R_IO_L])
+#define RSCAN0RMDF044LL (RSCAN0.RMDF044.UINT8[R_IO_LL])
+#define RSCAN0RMDF044LH (RSCAN0.RMDF044.UINT8[R_IO_LH])
+#define RSCAN0RMDF044H (RSCAN0.RMDF044.UINT16[R_IO_H])
+#define RSCAN0RMDF044HL (RSCAN0.RMDF044.UINT8[R_IO_HL])
+#define RSCAN0RMDF044HH (RSCAN0.RMDF044.UINT8[R_IO_HH])
+#define RSCAN0RMDF144 (RSCAN0.RMDF144.UINT32)
+#define RSCAN0RMDF144L (RSCAN0.RMDF144.UINT16[R_IO_L])
+#define RSCAN0RMDF144LL (RSCAN0.RMDF144.UINT8[R_IO_LL])
+#define RSCAN0RMDF144LH (RSCAN0.RMDF144.UINT8[R_IO_LH])
+#define RSCAN0RMDF144H (RSCAN0.RMDF144.UINT16[R_IO_H])
+#define RSCAN0RMDF144HL (RSCAN0.RMDF144.UINT8[R_IO_HL])
+#define RSCAN0RMDF144HH (RSCAN0.RMDF144.UINT8[R_IO_HH])
+#define RSCAN0RMID45 (RSCAN0.RMID45.UINT32)
+#define RSCAN0RMID45L (RSCAN0.RMID45.UINT16[R_IO_L])
+#define RSCAN0RMID45LL (RSCAN0.RMID45.UINT8[R_IO_LL])
+#define RSCAN0RMID45LH (RSCAN0.RMID45.UINT8[R_IO_LH])
+#define RSCAN0RMID45H (RSCAN0.RMID45.UINT16[R_IO_H])
+#define RSCAN0RMID45HL (RSCAN0.RMID45.UINT8[R_IO_HL])
+#define RSCAN0RMID45HH (RSCAN0.RMID45.UINT8[R_IO_HH])
+#define RSCAN0RMPTR45 (RSCAN0.RMPTR45.UINT32)
+#define RSCAN0RMPTR45L (RSCAN0.RMPTR45.UINT16[R_IO_L])
+#define RSCAN0RMPTR45LL (RSCAN0.RMPTR45.UINT8[R_IO_LL])
+#define RSCAN0RMPTR45LH (RSCAN0.RMPTR45.UINT8[R_IO_LH])
+#define RSCAN0RMPTR45H (RSCAN0.RMPTR45.UINT16[R_IO_H])
+#define RSCAN0RMPTR45HL (RSCAN0.RMPTR45.UINT8[R_IO_HL])
+#define RSCAN0RMPTR45HH (RSCAN0.RMPTR45.UINT8[R_IO_HH])
+#define RSCAN0RMDF045 (RSCAN0.RMDF045.UINT32)
+#define RSCAN0RMDF045L (RSCAN0.RMDF045.UINT16[R_IO_L])
+#define RSCAN0RMDF045LL (RSCAN0.RMDF045.UINT8[R_IO_LL])
+#define RSCAN0RMDF045LH (RSCAN0.RMDF045.UINT8[R_IO_LH])
+#define RSCAN0RMDF045H (RSCAN0.RMDF045.UINT16[R_IO_H])
+#define RSCAN0RMDF045HL (RSCAN0.RMDF045.UINT8[R_IO_HL])
+#define RSCAN0RMDF045HH (RSCAN0.RMDF045.UINT8[R_IO_HH])
+#define RSCAN0RMDF145 (RSCAN0.RMDF145.UINT32)
+#define RSCAN0RMDF145L (RSCAN0.RMDF145.UINT16[R_IO_L])
+#define RSCAN0RMDF145LL (RSCAN0.RMDF145.UINT8[R_IO_LL])
+#define RSCAN0RMDF145LH (RSCAN0.RMDF145.UINT8[R_IO_LH])
+#define RSCAN0RMDF145H (RSCAN0.RMDF145.UINT16[R_IO_H])
+#define RSCAN0RMDF145HL (RSCAN0.RMDF145.UINT8[R_IO_HL])
+#define RSCAN0RMDF145HH (RSCAN0.RMDF145.UINT8[R_IO_HH])
+#define RSCAN0RMID46 (RSCAN0.RMID46.UINT32)
+#define RSCAN0RMID46L (RSCAN0.RMID46.UINT16[R_IO_L])
+#define RSCAN0RMID46LL (RSCAN0.RMID46.UINT8[R_IO_LL])
+#define RSCAN0RMID46LH (RSCAN0.RMID46.UINT8[R_IO_LH])
+#define RSCAN0RMID46H (RSCAN0.RMID46.UINT16[R_IO_H])
+#define RSCAN0RMID46HL (RSCAN0.RMID46.UINT8[R_IO_HL])
+#define RSCAN0RMID46HH (RSCAN0.RMID46.UINT8[R_IO_HH])
+#define RSCAN0RMPTR46 (RSCAN0.RMPTR46.UINT32)
+#define RSCAN0RMPTR46L (RSCAN0.RMPTR46.UINT16[R_IO_L])
+#define RSCAN0RMPTR46LL (RSCAN0.RMPTR46.UINT8[R_IO_LL])
+#define RSCAN0RMPTR46LH (RSCAN0.RMPTR46.UINT8[R_IO_LH])
+#define RSCAN0RMPTR46H (RSCAN0.RMPTR46.UINT16[R_IO_H])
+#define RSCAN0RMPTR46HL (RSCAN0.RMPTR46.UINT8[R_IO_HL])
+#define RSCAN0RMPTR46HH (RSCAN0.RMPTR46.UINT8[R_IO_HH])
+#define RSCAN0RMDF046 (RSCAN0.RMDF046.UINT32)
+#define RSCAN0RMDF046L (RSCAN0.RMDF046.UINT16[R_IO_L])
+#define RSCAN0RMDF046LL (RSCAN0.RMDF046.UINT8[R_IO_LL])
+#define RSCAN0RMDF046LH (RSCAN0.RMDF046.UINT8[R_IO_LH])
+#define RSCAN0RMDF046H (RSCAN0.RMDF046.UINT16[R_IO_H])
+#define RSCAN0RMDF046HL (RSCAN0.RMDF046.UINT8[R_IO_HL])
+#define RSCAN0RMDF046HH (RSCAN0.RMDF046.UINT8[R_IO_HH])
+#define RSCAN0RMDF146 (RSCAN0.RMDF146.UINT32)
+#define RSCAN0RMDF146L (RSCAN0.RMDF146.UINT16[R_IO_L])
+#define RSCAN0RMDF146LL (RSCAN0.RMDF146.UINT8[R_IO_LL])
+#define RSCAN0RMDF146LH (RSCAN0.RMDF146.UINT8[R_IO_LH])
+#define RSCAN0RMDF146H (RSCAN0.RMDF146.UINT16[R_IO_H])
+#define RSCAN0RMDF146HL (RSCAN0.RMDF146.UINT8[R_IO_HL])
+#define RSCAN0RMDF146HH (RSCAN0.RMDF146.UINT8[R_IO_HH])
+#define RSCAN0RMID47 (RSCAN0.RMID47.UINT32)
+#define RSCAN0RMID47L (RSCAN0.RMID47.UINT16[R_IO_L])
+#define RSCAN0RMID47LL (RSCAN0.RMID47.UINT8[R_IO_LL])
+#define RSCAN0RMID47LH (RSCAN0.RMID47.UINT8[R_IO_LH])
+#define RSCAN0RMID47H (RSCAN0.RMID47.UINT16[R_IO_H])
+#define RSCAN0RMID47HL (RSCAN0.RMID47.UINT8[R_IO_HL])
+#define RSCAN0RMID47HH (RSCAN0.RMID47.UINT8[R_IO_HH])
+#define RSCAN0RMPTR47 (RSCAN0.RMPTR47.UINT32)
+#define RSCAN0RMPTR47L (RSCAN0.RMPTR47.UINT16[R_IO_L])
+#define RSCAN0RMPTR47LL (RSCAN0.RMPTR47.UINT8[R_IO_LL])
+#define RSCAN0RMPTR47LH (RSCAN0.RMPTR47.UINT8[R_IO_LH])
+#define RSCAN0RMPTR47H (RSCAN0.RMPTR47.UINT16[R_IO_H])
+#define RSCAN0RMPTR47HL (RSCAN0.RMPTR47.UINT8[R_IO_HL])
+#define RSCAN0RMPTR47HH (RSCAN0.RMPTR47.UINT8[R_IO_HH])
+#define RSCAN0RMDF047 (RSCAN0.RMDF047.UINT32)
+#define RSCAN0RMDF047L (RSCAN0.RMDF047.UINT16[R_IO_L])
+#define RSCAN0RMDF047LL (RSCAN0.RMDF047.UINT8[R_IO_LL])
+#define RSCAN0RMDF047LH (RSCAN0.RMDF047.UINT8[R_IO_LH])
+#define RSCAN0RMDF047H (RSCAN0.RMDF047.UINT16[R_IO_H])
+#define RSCAN0RMDF047HL (RSCAN0.RMDF047.UINT8[R_IO_HL])
+#define RSCAN0RMDF047HH (RSCAN0.RMDF047.UINT8[R_IO_HH])
+#define RSCAN0RMDF147 (RSCAN0.RMDF147.UINT32)
+#define RSCAN0RMDF147L (RSCAN0.RMDF147.UINT16[R_IO_L])
+#define RSCAN0RMDF147LL (RSCAN0.RMDF147.UINT8[R_IO_LL])
+#define RSCAN0RMDF147LH (RSCAN0.RMDF147.UINT8[R_IO_LH])
+#define RSCAN0RMDF147H (RSCAN0.RMDF147.UINT16[R_IO_H])
+#define RSCAN0RMDF147HL (RSCAN0.RMDF147.UINT8[R_IO_HL])
+#define RSCAN0RMDF147HH (RSCAN0.RMDF147.UINT8[R_IO_HH])
+#define RSCAN0RMID48 (RSCAN0.RMID48.UINT32)
+#define RSCAN0RMID48L (RSCAN0.RMID48.UINT16[R_IO_L])
+#define RSCAN0RMID48LL (RSCAN0.RMID48.UINT8[R_IO_LL])
+#define RSCAN0RMID48LH (RSCAN0.RMID48.UINT8[R_IO_LH])
+#define RSCAN0RMID48H (RSCAN0.RMID48.UINT16[R_IO_H])
+#define RSCAN0RMID48HL (RSCAN0.RMID48.UINT8[R_IO_HL])
+#define RSCAN0RMID48HH (RSCAN0.RMID48.UINT8[R_IO_HH])
+#define RSCAN0RMPTR48 (RSCAN0.RMPTR48.UINT32)
+#define RSCAN0RMPTR48L (RSCAN0.RMPTR48.UINT16[R_IO_L])
+#define RSCAN0RMPTR48LL (RSCAN0.RMPTR48.UINT8[R_IO_LL])
+#define RSCAN0RMPTR48LH (RSCAN0.RMPTR48.UINT8[R_IO_LH])
+#define RSCAN0RMPTR48H (RSCAN0.RMPTR48.UINT16[R_IO_H])
+#define RSCAN0RMPTR48HL (RSCAN0.RMPTR48.UINT8[R_IO_HL])
+#define RSCAN0RMPTR48HH (RSCAN0.RMPTR48.UINT8[R_IO_HH])
+#define RSCAN0RMDF048 (RSCAN0.RMDF048.UINT32)
+#define RSCAN0RMDF048L (RSCAN0.RMDF048.UINT16[R_IO_L])
+#define RSCAN0RMDF048LL (RSCAN0.RMDF048.UINT8[R_IO_LL])
+#define RSCAN0RMDF048LH (RSCAN0.RMDF048.UINT8[R_IO_LH])
+#define RSCAN0RMDF048H (RSCAN0.RMDF048.UINT16[R_IO_H])
+#define RSCAN0RMDF048HL (RSCAN0.RMDF048.UINT8[R_IO_HL])
+#define RSCAN0RMDF048HH (RSCAN0.RMDF048.UINT8[R_IO_HH])
+#define RSCAN0RMDF148 (RSCAN0.RMDF148.UINT32)
+#define RSCAN0RMDF148L (RSCAN0.RMDF148.UINT16[R_IO_L])
+#define RSCAN0RMDF148LL (RSCAN0.RMDF148.UINT8[R_IO_LL])
+#define RSCAN0RMDF148LH (RSCAN0.RMDF148.UINT8[R_IO_LH])
+#define RSCAN0RMDF148H (RSCAN0.RMDF148.UINT16[R_IO_H])
+#define RSCAN0RMDF148HL (RSCAN0.RMDF148.UINT8[R_IO_HL])
+#define RSCAN0RMDF148HH (RSCAN0.RMDF148.UINT8[R_IO_HH])
+#define RSCAN0RMID49 (RSCAN0.RMID49.UINT32)
+#define RSCAN0RMID49L (RSCAN0.RMID49.UINT16[R_IO_L])
+#define RSCAN0RMID49LL (RSCAN0.RMID49.UINT8[R_IO_LL])
+#define RSCAN0RMID49LH (RSCAN0.RMID49.UINT8[R_IO_LH])
+#define RSCAN0RMID49H (RSCAN0.RMID49.UINT16[R_IO_H])
+#define RSCAN0RMID49HL (RSCAN0.RMID49.UINT8[R_IO_HL])
+#define RSCAN0RMID49HH (RSCAN0.RMID49.UINT8[R_IO_HH])
+#define RSCAN0RMPTR49 (RSCAN0.RMPTR49.UINT32)
+#define RSCAN0RMPTR49L (RSCAN0.RMPTR49.UINT16[R_IO_L])
+#define RSCAN0RMPTR49LL (RSCAN0.RMPTR49.UINT8[R_IO_LL])
+#define RSCAN0RMPTR49LH (RSCAN0.RMPTR49.UINT8[R_IO_LH])
+#define RSCAN0RMPTR49H (RSCAN0.RMPTR49.UINT16[R_IO_H])
+#define RSCAN0RMPTR49HL (RSCAN0.RMPTR49.UINT8[R_IO_HL])
+#define RSCAN0RMPTR49HH (RSCAN0.RMPTR49.UINT8[R_IO_HH])
+#define RSCAN0RMDF049 (RSCAN0.RMDF049.UINT32)
+#define RSCAN0RMDF049L (RSCAN0.RMDF049.UINT16[R_IO_L])
+#define RSCAN0RMDF049LL (RSCAN0.RMDF049.UINT8[R_IO_LL])
+#define RSCAN0RMDF049LH (RSCAN0.RMDF049.UINT8[R_IO_LH])
+#define RSCAN0RMDF049H (RSCAN0.RMDF049.UINT16[R_IO_H])
+#define RSCAN0RMDF049HL (RSCAN0.RMDF049.UINT8[R_IO_HL])
+#define RSCAN0RMDF049HH (RSCAN0.RMDF049.UINT8[R_IO_HH])
+#define RSCAN0RMDF149 (RSCAN0.RMDF149.UINT32)
+#define RSCAN0RMDF149L (RSCAN0.RMDF149.UINT16[R_IO_L])
+#define RSCAN0RMDF149LL (RSCAN0.RMDF149.UINT8[R_IO_LL])
+#define RSCAN0RMDF149LH (RSCAN0.RMDF149.UINT8[R_IO_LH])
+#define RSCAN0RMDF149H (RSCAN0.RMDF149.UINT16[R_IO_H])
+#define RSCAN0RMDF149HL (RSCAN0.RMDF149.UINT8[R_IO_HL])
+#define RSCAN0RMDF149HH (RSCAN0.RMDF149.UINT8[R_IO_HH])
+#define RSCAN0RMID50 (RSCAN0.RMID50.UINT32)
+#define RSCAN0RMID50L (RSCAN0.RMID50.UINT16[R_IO_L])
+#define RSCAN0RMID50LL (RSCAN0.RMID50.UINT8[R_IO_LL])
+#define RSCAN0RMID50LH (RSCAN0.RMID50.UINT8[R_IO_LH])
+#define RSCAN0RMID50H (RSCAN0.RMID50.UINT16[R_IO_H])
+#define RSCAN0RMID50HL (RSCAN0.RMID50.UINT8[R_IO_HL])
+#define RSCAN0RMID50HH (RSCAN0.RMID50.UINT8[R_IO_HH])
+#define RSCAN0RMPTR50 (RSCAN0.RMPTR50.UINT32)
+#define RSCAN0RMPTR50L (RSCAN0.RMPTR50.UINT16[R_IO_L])
+#define RSCAN0RMPTR50LL (RSCAN0.RMPTR50.UINT8[R_IO_LL])
+#define RSCAN0RMPTR50LH (RSCAN0.RMPTR50.UINT8[R_IO_LH])
+#define RSCAN0RMPTR50H (RSCAN0.RMPTR50.UINT16[R_IO_H])
+#define RSCAN0RMPTR50HL (RSCAN0.RMPTR50.UINT8[R_IO_HL])
+#define RSCAN0RMPTR50HH (RSCAN0.RMPTR50.UINT8[R_IO_HH])
+#define RSCAN0RMDF050 (RSCAN0.RMDF050.UINT32)
+#define RSCAN0RMDF050L (RSCAN0.RMDF050.UINT16[R_IO_L])
+#define RSCAN0RMDF050LL (RSCAN0.RMDF050.UINT8[R_IO_LL])
+#define RSCAN0RMDF050LH (RSCAN0.RMDF050.UINT8[R_IO_LH])
+#define RSCAN0RMDF050H (RSCAN0.RMDF050.UINT16[R_IO_H])
+#define RSCAN0RMDF050HL (RSCAN0.RMDF050.UINT8[R_IO_HL])
+#define RSCAN0RMDF050HH (RSCAN0.RMDF050.UINT8[R_IO_HH])
+#define RSCAN0RMDF150 (RSCAN0.RMDF150.UINT32)
+#define RSCAN0RMDF150L (RSCAN0.RMDF150.UINT16[R_IO_L])
+#define RSCAN0RMDF150LL (RSCAN0.RMDF150.UINT8[R_IO_LL])
+#define RSCAN0RMDF150LH (RSCAN0.RMDF150.UINT8[R_IO_LH])
+#define RSCAN0RMDF150H (RSCAN0.RMDF150.UINT16[R_IO_H])
+#define RSCAN0RMDF150HL (RSCAN0.RMDF150.UINT8[R_IO_HL])
+#define RSCAN0RMDF150HH (RSCAN0.RMDF150.UINT8[R_IO_HH])
+#define RSCAN0RMID51 (RSCAN0.RMID51.UINT32)
+#define RSCAN0RMID51L (RSCAN0.RMID51.UINT16[R_IO_L])
+#define RSCAN0RMID51LL (RSCAN0.RMID51.UINT8[R_IO_LL])
+#define RSCAN0RMID51LH (RSCAN0.RMID51.UINT8[R_IO_LH])
+#define RSCAN0RMID51H (RSCAN0.RMID51.UINT16[R_IO_H])
+#define RSCAN0RMID51HL (RSCAN0.RMID51.UINT8[R_IO_HL])
+#define RSCAN0RMID51HH (RSCAN0.RMID51.UINT8[R_IO_HH])
+#define RSCAN0RMPTR51 (RSCAN0.RMPTR51.UINT32)
+#define RSCAN0RMPTR51L (RSCAN0.RMPTR51.UINT16[R_IO_L])
+#define RSCAN0RMPTR51LL (RSCAN0.RMPTR51.UINT8[R_IO_LL])
+#define RSCAN0RMPTR51LH (RSCAN0.RMPTR51.UINT8[R_IO_LH])
+#define RSCAN0RMPTR51H (RSCAN0.RMPTR51.UINT16[R_IO_H])
+#define RSCAN0RMPTR51HL (RSCAN0.RMPTR51.UINT8[R_IO_HL])
+#define RSCAN0RMPTR51HH (RSCAN0.RMPTR51.UINT8[R_IO_HH])
+#define RSCAN0RMDF051 (RSCAN0.RMDF051.UINT32)
+#define RSCAN0RMDF051L (RSCAN0.RMDF051.UINT16[R_IO_L])
+#define RSCAN0RMDF051LL (RSCAN0.RMDF051.UINT8[R_IO_LL])
+#define RSCAN0RMDF051LH (RSCAN0.RMDF051.UINT8[R_IO_LH])
+#define RSCAN0RMDF051H (RSCAN0.RMDF051.UINT16[R_IO_H])
+#define RSCAN0RMDF051HL (RSCAN0.RMDF051.UINT8[R_IO_HL])
+#define RSCAN0RMDF051HH (RSCAN0.RMDF051.UINT8[R_IO_HH])
+#define RSCAN0RMDF151 (RSCAN0.RMDF151.UINT32)
+#define RSCAN0RMDF151L (RSCAN0.RMDF151.UINT16[R_IO_L])
+#define RSCAN0RMDF151LL (RSCAN0.RMDF151.UINT8[R_IO_LL])
+#define RSCAN0RMDF151LH (RSCAN0.RMDF151.UINT8[R_IO_LH])
+#define RSCAN0RMDF151H (RSCAN0.RMDF151.UINT16[R_IO_H])
+#define RSCAN0RMDF151HL (RSCAN0.RMDF151.UINT8[R_IO_HL])
+#define RSCAN0RMDF151HH (RSCAN0.RMDF151.UINT8[R_IO_HH])
+#define RSCAN0RMID52 (RSCAN0.RMID52.UINT32)
+#define RSCAN0RMID52L (RSCAN0.RMID52.UINT16[R_IO_L])
+#define RSCAN0RMID52LL (RSCAN0.RMID52.UINT8[R_IO_LL])
+#define RSCAN0RMID52LH (RSCAN0.RMID52.UINT8[R_IO_LH])
+#define RSCAN0RMID52H (RSCAN0.RMID52.UINT16[R_IO_H])
+#define RSCAN0RMID52HL (RSCAN0.RMID52.UINT8[R_IO_HL])
+#define RSCAN0RMID52HH (RSCAN0.RMID52.UINT8[R_IO_HH])
+#define RSCAN0RMPTR52 (RSCAN0.RMPTR52.UINT32)
+#define RSCAN0RMPTR52L (RSCAN0.RMPTR52.UINT16[R_IO_L])
+#define RSCAN0RMPTR52LL (RSCAN0.RMPTR52.UINT8[R_IO_LL])
+#define RSCAN0RMPTR52LH (RSCAN0.RMPTR52.UINT8[R_IO_LH])
+#define RSCAN0RMPTR52H (RSCAN0.RMPTR52.UINT16[R_IO_H])
+#define RSCAN0RMPTR52HL (RSCAN0.RMPTR52.UINT8[R_IO_HL])
+#define RSCAN0RMPTR52HH (RSCAN0.RMPTR52.UINT8[R_IO_HH])
+#define RSCAN0RMDF052 (RSCAN0.RMDF052.UINT32)
+#define RSCAN0RMDF052L (RSCAN0.RMDF052.UINT16[R_IO_L])
+#define RSCAN0RMDF052LL (RSCAN0.RMDF052.UINT8[R_IO_LL])
+#define RSCAN0RMDF052LH (RSCAN0.RMDF052.UINT8[R_IO_LH])
+#define RSCAN0RMDF052H (RSCAN0.RMDF052.UINT16[R_IO_H])
+#define RSCAN0RMDF052HL (RSCAN0.RMDF052.UINT8[R_IO_HL])
+#define RSCAN0RMDF052HH (RSCAN0.RMDF052.UINT8[R_IO_HH])
+#define RSCAN0RMDF152 (RSCAN0.RMDF152.UINT32)
+#define RSCAN0RMDF152L (RSCAN0.RMDF152.UINT16[R_IO_L])
+#define RSCAN0RMDF152LL (RSCAN0.RMDF152.UINT8[R_IO_LL])
+#define RSCAN0RMDF152LH (RSCAN0.RMDF152.UINT8[R_IO_LH])
+#define RSCAN0RMDF152H (RSCAN0.RMDF152.UINT16[R_IO_H])
+#define RSCAN0RMDF152HL (RSCAN0.RMDF152.UINT8[R_IO_HL])
+#define RSCAN0RMDF152HH (RSCAN0.RMDF152.UINT8[R_IO_HH])
+#define RSCAN0RMID53 (RSCAN0.RMID53.UINT32)
+#define RSCAN0RMID53L (RSCAN0.RMID53.UINT16[R_IO_L])
+#define RSCAN0RMID53LL (RSCAN0.RMID53.UINT8[R_IO_LL])
+#define RSCAN0RMID53LH (RSCAN0.RMID53.UINT8[R_IO_LH])
+#define RSCAN0RMID53H (RSCAN0.RMID53.UINT16[R_IO_H])
+#define RSCAN0RMID53HL (RSCAN0.RMID53.UINT8[R_IO_HL])
+#define RSCAN0RMID53HH (RSCAN0.RMID53.UINT8[R_IO_HH])
+#define RSCAN0RMPTR53 (RSCAN0.RMPTR53.UINT32)
+#define RSCAN0RMPTR53L (RSCAN0.RMPTR53.UINT16[R_IO_L])
+#define RSCAN0RMPTR53LL (RSCAN0.RMPTR53.UINT8[R_IO_LL])
+#define RSCAN0RMPTR53LH (RSCAN0.RMPTR53.UINT8[R_IO_LH])
+#define RSCAN0RMPTR53H (RSCAN0.RMPTR53.UINT16[R_IO_H])
+#define RSCAN0RMPTR53HL (RSCAN0.RMPTR53.UINT8[R_IO_HL])
+#define RSCAN0RMPTR53HH (RSCAN0.RMPTR53.UINT8[R_IO_HH])
+#define RSCAN0RMDF053 (RSCAN0.RMDF053.UINT32)
+#define RSCAN0RMDF053L (RSCAN0.RMDF053.UINT16[R_IO_L])
+#define RSCAN0RMDF053LL (RSCAN0.RMDF053.UINT8[R_IO_LL])
+#define RSCAN0RMDF053LH (RSCAN0.RMDF053.UINT8[R_IO_LH])
+#define RSCAN0RMDF053H (RSCAN0.RMDF053.UINT16[R_IO_H])
+#define RSCAN0RMDF053HL (RSCAN0.RMDF053.UINT8[R_IO_HL])
+#define RSCAN0RMDF053HH (RSCAN0.RMDF053.UINT8[R_IO_HH])
+#define RSCAN0RMDF153 (RSCAN0.RMDF153.UINT32)
+#define RSCAN0RMDF153L (RSCAN0.RMDF153.UINT16[R_IO_L])
+#define RSCAN0RMDF153LL (RSCAN0.RMDF153.UINT8[R_IO_LL])
+#define RSCAN0RMDF153LH (RSCAN0.RMDF153.UINT8[R_IO_LH])
+#define RSCAN0RMDF153H (RSCAN0.RMDF153.UINT16[R_IO_H])
+#define RSCAN0RMDF153HL (RSCAN0.RMDF153.UINT8[R_IO_HL])
+#define RSCAN0RMDF153HH (RSCAN0.RMDF153.UINT8[R_IO_HH])
+#define RSCAN0RMID54 (RSCAN0.RMID54.UINT32)
+#define RSCAN0RMID54L (RSCAN0.RMID54.UINT16[R_IO_L])
+#define RSCAN0RMID54LL (RSCAN0.RMID54.UINT8[R_IO_LL])
+#define RSCAN0RMID54LH (RSCAN0.RMID54.UINT8[R_IO_LH])
+#define RSCAN0RMID54H (RSCAN0.RMID54.UINT16[R_IO_H])
+#define RSCAN0RMID54HL (RSCAN0.RMID54.UINT8[R_IO_HL])
+#define RSCAN0RMID54HH (RSCAN0.RMID54.UINT8[R_IO_HH])
+#define RSCAN0RMPTR54 (RSCAN0.RMPTR54.UINT32)
+#define RSCAN0RMPTR54L (RSCAN0.RMPTR54.UINT16[R_IO_L])
+#define RSCAN0RMPTR54LL (RSCAN0.RMPTR54.UINT8[R_IO_LL])
+#define RSCAN0RMPTR54LH (RSCAN0.RMPTR54.UINT8[R_IO_LH])
+#define RSCAN0RMPTR54H (RSCAN0.RMPTR54.UINT16[R_IO_H])
+#define RSCAN0RMPTR54HL (RSCAN0.RMPTR54.UINT8[R_IO_HL])
+#define RSCAN0RMPTR54HH (RSCAN0.RMPTR54.UINT8[R_IO_HH])
+#define RSCAN0RMDF054 (RSCAN0.RMDF054.UINT32)
+#define RSCAN0RMDF054L (RSCAN0.RMDF054.UINT16[R_IO_L])
+#define RSCAN0RMDF054LL (RSCAN0.RMDF054.UINT8[R_IO_LL])
+#define RSCAN0RMDF054LH (RSCAN0.RMDF054.UINT8[R_IO_LH])
+#define RSCAN0RMDF054H (RSCAN0.RMDF054.UINT16[R_IO_H])
+#define RSCAN0RMDF054HL (RSCAN0.RMDF054.UINT8[R_IO_HL])
+#define RSCAN0RMDF054HH (RSCAN0.RMDF054.UINT8[R_IO_HH])
+#define RSCAN0RMDF154 (RSCAN0.RMDF154.UINT32)
+#define RSCAN0RMDF154L (RSCAN0.RMDF154.UINT16[R_IO_L])
+#define RSCAN0RMDF154LL (RSCAN0.RMDF154.UINT8[R_IO_LL])
+#define RSCAN0RMDF154LH (RSCAN0.RMDF154.UINT8[R_IO_LH])
+#define RSCAN0RMDF154H (RSCAN0.RMDF154.UINT16[R_IO_H])
+#define RSCAN0RMDF154HL (RSCAN0.RMDF154.UINT8[R_IO_HL])
+#define RSCAN0RMDF154HH (RSCAN0.RMDF154.UINT8[R_IO_HH])
+#define RSCAN0RMID55 (RSCAN0.RMID55.UINT32)
+#define RSCAN0RMID55L (RSCAN0.RMID55.UINT16[R_IO_L])
+#define RSCAN0RMID55LL (RSCAN0.RMID55.UINT8[R_IO_LL])
+#define RSCAN0RMID55LH (RSCAN0.RMID55.UINT8[R_IO_LH])
+#define RSCAN0RMID55H (RSCAN0.RMID55.UINT16[R_IO_H])
+#define RSCAN0RMID55HL (RSCAN0.RMID55.UINT8[R_IO_HL])
+#define RSCAN0RMID55HH (RSCAN0.RMID55.UINT8[R_IO_HH])
+#define RSCAN0RMPTR55 (RSCAN0.RMPTR55.UINT32)
+#define RSCAN0RMPTR55L (RSCAN0.RMPTR55.UINT16[R_IO_L])
+#define RSCAN0RMPTR55LL (RSCAN0.RMPTR55.UINT8[R_IO_LL])
+#define RSCAN0RMPTR55LH (RSCAN0.RMPTR55.UINT8[R_IO_LH])
+#define RSCAN0RMPTR55H (RSCAN0.RMPTR55.UINT16[R_IO_H])
+#define RSCAN0RMPTR55HL (RSCAN0.RMPTR55.UINT8[R_IO_HL])
+#define RSCAN0RMPTR55HH (RSCAN0.RMPTR55.UINT8[R_IO_HH])
+#define RSCAN0RMDF055 (RSCAN0.RMDF055.UINT32)
+#define RSCAN0RMDF055L (RSCAN0.RMDF055.UINT16[R_IO_L])
+#define RSCAN0RMDF055LL (RSCAN0.RMDF055.UINT8[R_IO_LL])
+#define RSCAN0RMDF055LH (RSCAN0.RMDF055.UINT8[R_IO_LH])
+#define RSCAN0RMDF055H (RSCAN0.RMDF055.UINT16[R_IO_H])
+#define RSCAN0RMDF055HL (RSCAN0.RMDF055.UINT8[R_IO_HL])
+#define RSCAN0RMDF055HH (RSCAN0.RMDF055.UINT8[R_IO_HH])
+#define RSCAN0RMDF155 (RSCAN0.RMDF155.UINT32)
+#define RSCAN0RMDF155L (RSCAN0.RMDF155.UINT16[R_IO_L])
+#define RSCAN0RMDF155LL (RSCAN0.RMDF155.UINT8[R_IO_LL])
+#define RSCAN0RMDF155LH (RSCAN0.RMDF155.UINT8[R_IO_LH])
+#define RSCAN0RMDF155H (RSCAN0.RMDF155.UINT16[R_IO_H])
+#define RSCAN0RMDF155HL (RSCAN0.RMDF155.UINT8[R_IO_HL])
+#define RSCAN0RMDF155HH (RSCAN0.RMDF155.UINT8[R_IO_HH])
+#define RSCAN0RMID56 (RSCAN0.RMID56.UINT32)
+#define RSCAN0RMID56L (RSCAN0.RMID56.UINT16[R_IO_L])
+#define RSCAN0RMID56LL (RSCAN0.RMID56.UINT8[R_IO_LL])
+#define RSCAN0RMID56LH (RSCAN0.RMID56.UINT8[R_IO_LH])
+#define RSCAN0RMID56H (RSCAN0.RMID56.UINT16[R_IO_H])
+#define RSCAN0RMID56HL (RSCAN0.RMID56.UINT8[R_IO_HL])
+#define RSCAN0RMID56HH (RSCAN0.RMID56.UINT8[R_IO_HH])
+#define RSCAN0RMPTR56 (RSCAN0.RMPTR56.UINT32)
+#define RSCAN0RMPTR56L (RSCAN0.RMPTR56.UINT16[R_IO_L])
+#define RSCAN0RMPTR56LL (RSCAN0.RMPTR56.UINT8[R_IO_LL])
+#define RSCAN0RMPTR56LH (RSCAN0.RMPTR56.UINT8[R_IO_LH])
+#define RSCAN0RMPTR56H (RSCAN0.RMPTR56.UINT16[R_IO_H])
+#define RSCAN0RMPTR56HL (RSCAN0.RMPTR56.UINT8[R_IO_HL])
+#define RSCAN0RMPTR56HH (RSCAN0.RMPTR56.UINT8[R_IO_HH])
+#define RSCAN0RMDF056 (RSCAN0.RMDF056.UINT32)
+#define RSCAN0RMDF056L (RSCAN0.RMDF056.UINT16[R_IO_L])
+#define RSCAN0RMDF056LL (RSCAN0.RMDF056.UINT8[R_IO_LL])
+#define RSCAN0RMDF056LH (RSCAN0.RMDF056.UINT8[R_IO_LH])
+#define RSCAN0RMDF056H (RSCAN0.RMDF056.UINT16[R_IO_H])
+#define RSCAN0RMDF056HL (RSCAN0.RMDF056.UINT8[R_IO_HL])
+#define RSCAN0RMDF056HH (RSCAN0.RMDF056.UINT8[R_IO_HH])
+#define RSCAN0RMDF156 (RSCAN0.RMDF156.UINT32)
+#define RSCAN0RMDF156L (RSCAN0.RMDF156.UINT16[R_IO_L])
+#define RSCAN0RMDF156LL (RSCAN0.RMDF156.UINT8[R_IO_LL])
+#define RSCAN0RMDF156LH (RSCAN0.RMDF156.UINT8[R_IO_LH])
+#define RSCAN0RMDF156H (RSCAN0.RMDF156.UINT16[R_IO_H])
+#define RSCAN0RMDF156HL (RSCAN0.RMDF156.UINT8[R_IO_HL])
+#define RSCAN0RMDF156HH (RSCAN0.RMDF156.UINT8[R_IO_HH])
+#define RSCAN0RMID57 (RSCAN0.RMID57.UINT32)
+#define RSCAN0RMID57L (RSCAN0.RMID57.UINT16[R_IO_L])
+#define RSCAN0RMID57LL (RSCAN0.RMID57.UINT8[R_IO_LL])
+#define RSCAN0RMID57LH (RSCAN0.RMID57.UINT8[R_IO_LH])
+#define RSCAN0RMID57H (RSCAN0.RMID57.UINT16[R_IO_H])
+#define RSCAN0RMID57HL (RSCAN0.RMID57.UINT8[R_IO_HL])
+#define RSCAN0RMID57HH (RSCAN0.RMID57.UINT8[R_IO_HH])
+#define RSCAN0RMPTR57 (RSCAN0.RMPTR57.UINT32)
+#define RSCAN0RMPTR57L (RSCAN0.RMPTR57.UINT16[R_IO_L])
+#define RSCAN0RMPTR57LL (RSCAN0.RMPTR57.UINT8[R_IO_LL])
+#define RSCAN0RMPTR57LH (RSCAN0.RMPTR57.UINT8[R_IO_LH])
+#define RSCAN0RMPTR57H (RSCAN0.RMPTR57.UINT16[R_IO_H])
+#define RSCAN0RMPTR57HL (RSCAN0.RMPTR57.UINT8[R_IO_HL])
+#define RSCAN0RMPTR57HH (RSCAN0.RMPTR57.UINT8[R_IO_HH])
+#define RSCAN0RMDF057 (RSCAN0.RMDF057.UINT32)
+#define RSCAN0RMDF057L (RSCAN0.RMDF057.UINT16[R_IO_L])
+#define RSCAN0RMDF057LL (RSCAN0.RMDF057.UINT8[R_IO_LL])
+#define RSCAN0RMDF057LH (RSCAN0.RMDF057.UINT8[R_IO_LH])
+#define RSCAN0RMDF057H (RSCAN0.RMDF057.UINT16[R_IO_H])
+#define RSCAN0RMDF057HL (RSCAN0.RMDF057.UINT8[R_IO_HL])
+#define RSCAN0RMDF057HH (RSCAN0.RMDF057.UINT8[R_IO_HH])
+#define RSCAN0RMDF157 (RSCAN0.RMDF157.UINT32)
+#define RSCAN0RMDF157L (RSCAN0.RMDF157.UINT16[R_IO_L])
+#define RSCAN0RMDF157LL (RSCAN0.RMDF157.UINT8[R_IO_LL])
+#define RSCAN0RMDF157LH (RSCAN0.RMDF157.UINT8[R_IO_LH])
+#define RSCAN0RMDF157H (RSCAN0.RMDF157.UINT16[R_IO_H])
+#define RSCAN0RMDF157HL (RSCAN0.RMDF157.UINT8[R_IO_HL])
+#define RSCAN0RMDF157HH (RSCAN0.RMDF157.UINT8[R_IO_HH])
+#define RSCAN0RMID58 (RSCAN0.RMID58.UINT32)
+#define RSCAN0RMID58L (RSCAN0.RMID58.UINT16[R_IO_L])
+#define RSCAN0RMID58LL (RSCAN0.RMID58.UINT8[R_IO_LL])
+#define RSCAN0RMID58LH (RSCAN0.RMID58.UINT8[R_IO_LH])
+#define RSCAN0RMID58H (RSCAN0.RMID58.UINT16[R_IO_H])
+#define RSCAN0RMID58HL (RSCAN0.RMID58.UINT8[R_IO_HL])
+#define RSCAN0RMID58HH (RSCAN0.RMID58.UINT8[R_IO_HH])
+#define RSCAN0RMPTR58 (RSCAN0.RMPTR58.UINT32)
+#define RSCAN0RMPTR58L (RSCAN0.RMPTR58.UINT16[R_IO_L])
+#define RSCAN0RMPTR58LL (RSCAN0.RMPTR58.UINT8[R_IO_LL])
+#define RSCAN0RMPTR58LH (RSCAN0.RMPTR58.UINT8[R_IO_LH])
+#define RSCAN0RMPTR58H (RSCAN0.RMPTR58.UINT16[R_IO_H])
+#define RSCAN0RMPTR58HL (RSCAN0.RMPTR58.UINT8[R_IO_HL])
+#define RSCAN0RMPTR58HH (RSCAN0.RMPTR58.UINT8[R_IO_HH])
+#define RSCAN0RMDF058 (RSCAN0.RMDF058.UINT32)
+#define RSCAN0RMDF058L (RSCAN0.RMDF058.UINT16[R_IO_L])
+#define RSCAN0RMDF058LL (RSCAN0.RMDF058.UINT8[R_IO_LL])
+#define RSCAN0RMDF058LH (RSCAN0.RMDF058.UINT8[R_IO_LH])
+#define RSCAN0RMDF058H (RSCAN0.RMDF058.UINT16[R_IO_H])
+#define RSCAN0RMDF058HL (RSCAN0.RMDF058.UINT8[R_IO_HL])
+#define RSCAN0RMDF058HH (RSCAN0.RMDF058.UINT8[R_IO_HH])
+#define RSCAN0RMDF158 (RSCAN0.RMDF158.UINT32)
+#define RSCAN0RMDF158L (RSCAN0.RMDF158.UINT16[R_IO_L])
+#define RSCAN0RMDF158LL (RSCAN0.RMDF158.UINT8[R_IO_LL])
+#define RSCAN0RMDF158LH (RSCAN0.RMDF158.UINT8[R_IO_LH])
+#define RSCAN0RMDF158H (RSCAN0.RMDF158.UINT16[R_IO_H])
+#define RSCAN0RMDF158HL (RSCAN0.RMDF158.UINT8[R_IO_HL])
+#define RSCAN0RMDF158HH (RSCAN0.RMDF158.UINT8[R_IO_HH])
+#define RSCAN0RMID59 (RSCAN0.RMID59.UINT32)
+#define RSCAN0RMID59L (RSCAN0.RMID59.UINT16[R_IO_L])
+#define RSCAN0RMID59LL (RSCAN0.RMID59.UINT8[R_IO_LL])
+#define RSCAN0RMID59LH (RSCAN0.RMID59.UINT8[R_IO_LH])
+#define RSCAN0RMID59H (RSCAN0.RMID59.UINT16[R_IO_H])
+#define RSCAN0RMID59HL (RSCAN0.RMID59.UINT8[R_IO_HL])
+#define RSCAN0RMID59HH (RSCAN0.RMID59.UINT8[R_IO_HH])
+#define RSCAN0RMPTR59 (RSCAN0.RMPTR59.UINT32)
+#define RSCAN0RMPTR59L (RSCAN0.RMPTR59.UINT16[R_IO_L])
+#define RSCAN0RMPTR59LL (RSCAN0.RMPTR59.UINT8[R_IO_LL])
+#define RSCAN0RMPTR59LH (RSCAN0.RMPTR59.UINT8[R_IO_LH])
+#define RSCAN0RMPTR59H (RSCAN0.RMPTR59.UINT16[R_IO_H])
+#define RSCAN0RMPTR59HL (RSCAN0.RMPTR59.UINT8[R_IO_HL])
+#define RSCAN0RMPTR59HH (RSCAN0.RMPTR59.UINT8[R_IO_HH])
+#define RSCAN0RMDF059 (RSCAN0.RMDF059.UINT32)
+#define RSCAN0RMDF059L (RSCAN0.RMDF059.UINT16[R_IO_L])
+#define RSCAN0RMDF059LL (RSCAN0.RMDF059.UINT8[R_IO_LL])
+#define RSCAN0RMDF059LH (RSCAN0.RMDF059.UINT8[R_IO_LH])
+#define RSCAN0RMDF059H (RSCAN0.RMDF059.UINT16[R_IO_H])
+#define RSCAN0RMDF059HL (RSCAN0.RMDF059.UINT8[R_IO_HL])
+#define RSCAN0RMDF059HH (RSCAN0.RMDF059.UINT8[R_IO_HH])
+#define RSCAN0RMDF159 (RSCAN0.RMDF159.UINT32)
+#define RSCAN0RMDF159L (RSCAN0.RMDF159.UINT16[R_IO_L])
+#define RSCAN0RMDF159LL (RSCAN0.RMDF159.UINT8[R_IO_LL])
+#define RSCAN0RMDF159LH (RSCAN0.RMDF159.UINT8[R_IO_LH])
+#define RSCAN0RMDF159H (RSCAN0.RMDF159.UINT16[R_IO_H])
+#define RSCAN0RMDF159HL (RSCAN0.RMDF159.UINT8[R_IO_HL])
+#define RSCAN0RMDF159HH (RSCAN0.RMDF159.UINT8[R_IO_HH])
+#define RSCAN0RMID60 (RSCAN0.RMID60.UINT32)
+#define RSCAN0RMID60L (RSCAN0.RMID60.UINT16[R_IO_L])
+#define RSCAN0RMID60LL (RSCAN0.RMID60.UINT8[R_IO_LL])
+#define RSCAN0RMID60LH (RSCAN0.RMID60.UINT8[R_IO_LH])
+#define RSCAN0RMID60H (RSCAN0.RMID60.UINT16[R_IO_H])
+#define RSCAN0RMID60HL (RSCAN0.RMID60.UINT8[R_IO_HL])
+#define RSCAN0RMID60HH (RSCAN0.RMID60.UINT8[R_IO_HH])
+#define RSCAN0RMPTR60 (RSCAN0.RMPTR60.UINT32)
+#define RSCAN0RMPTR60L (RSCAN0.RMPTR60.UINT16[R_IO_L])
+#define RSCAN0RMPTR60LL (RSCAN0.RMPTR60.UINT8[R_IO_LL])
+#define RSCAN0RMPTR60LH (RSCAN0.RMPTR60.UINT8[R_IO_LH])
+#define RSCAN0RMPTR60H (RSCAN0.RMPTR60.UINT16[R_IO_H])
+#define RSCAN0RMPTR60HL (RSCAN0.RMPTR60.UINT8[R_IO_HL])
+#define RSCAN0RMPTR60HH (RSCAN0.RMPTR60.UINT8[R_IO_HH])
+#define RSCAN0RMDF060 (RSCAN0.RMDF060.UINT32)
+#define RSCAN0RMDF060L (RSCAN0.RMDF060.UINT16[R_IO_L])
+#define RSCAN0RMDF060LL (RSCAN0.RMDF060.UINT8[R_IO_LL])
+#define RSCAN0RMDF060LH (RSCAN0.RMDF060.UINT8[R_IO_LH])
+#define RSCAN0RMDF060H (RSCAN0.RMDF060.UINT16[R_IO_H])
+#define RSCAN0RMDF060HL (RSCAN0.RMDF060.UINT8[R_IO_HL])
+#define RSCAN0RMDF060HH (RSCAN0.RMDF060.UINT8[R_IO_HH])
+#define RSCAN0RMDF160 (RSCAN0.RMDF160.UINT32)
+#define RSCAN0RMDF160L (RSCAN0.RMDF160.UINT16[R_IO_L])
+#define RSCAN0RMDF160LL (RSCAN0.RMDF160.UINT8[R_IO_LL])
+#define RSCAN0RMDF160LH (RSCAN0.RMDF160.UINT8[R_IO_LH])
+#define RSCAN0RMDF160H (RSCAN0.RMDF160.UINT16[R_IO_H])
+#define RSCAN0RMDF160HL (RSCAN0.RMDF160.UINT8[R_IO_HL])
+#define RSCAN0RMDF160HH (RSCAN0.RMDF160.UINT8[R_IO_HH])
+#define RSCAN0RMID61 (RSCAN0.RMID61.UINT32)
+#define RSCAN0RMID61L (RSCAN0.RMID61.UINT16[R_IO_L])
+#define RSCAN0RMID61LL (RSCAN0.RMID61.UINT8[R_IO_LL])
+#define RSCAN0RMID61LH (RSCAN0.RMID61.UINT8[R_IO_LH])
+#define RSCAN0RMID61H (RSCAN0.RMID61.UINT16[R_IO_H])
+#define RSCAN0RMID61HL (RSCAN0.RMID61.UINT8[R_IO_HL])
+#define RSCAN0RMID61HH (RSCAN0.RMID61.UINT8[R_IO_HH])
+#define RSCAN0RMPTR61 (RSCAN0.RMPTR61.UINT32)
+#define RSCAN0RMPTR61L (RSCAN0.RMPTR61.UINT16[R_IO_L])
+#define RSCAN0RMPTR61LL (RSCAN0.RMPTR61.UINT8[R_IO_LL])
+#define RSCAN0RMPTR61LH (RSCAN0.RMPTR61.UINT8[R_IO_LH])
+#define RSCAN0RMPTR61H (RSCAN0.RMPTR61.UINT16[R_IO_H])
+#define RSCAN0RMPTR61HL (RSCAN0.RMPTR61.UINT8[R_IO_HL])
+#define RSCAN0RMPTR61HH (RSCAN0.RMPTR61.UINT8[R_IO_HH])
+#define RSCAN0RMDF061 (RSCAN0.RMDF061.UINT32)
+#define RSCAN0RMDF061L (RSCAN0.RMDF061.UINT16[R_IO_L])
+#define RSCAN0RMDF061LL (RSCAN0.RMDF061.UINT8[R_IO_LL])
+#define RSCAN0RMDF061LH (RSCAN0.RMDF061.UINT8[R_IO_LH])
+#define RSCAN0RMDF061H (RSCAN0.RMDF061.UINT16[R_IO_H])
+#define RSCAN0RMDF061HL (RSCAN0.RMDF061.UINT8[R_IO_HL])
+#define RSCAN0RMDF061HH (RSCAN0.RMDF061.UINT8[R_IO_HH])
+#define RSCAN0RMDF161 (RSCAN0.RMDF161.UINT32)
+#define RSCAN0RMDF161L (RSCAN0.RMDF161.UINT16[R_IO_L])
+#define RSCAN0RMDF161LL (RSCAN0.RMDF161.UINT8[R_IO_LL])
+#define RSCAN0RMDF161LH (RSCAN0.RMDF161.UINT8[R_IO_LH])
+#define RSCAN0RMDF161H (RSCAN0.RMDF161.UINT16[R_IO_H])
+#define RSCAN0RMDF161HL (RSCAN0.RMDF161.UINT8[R_IO_HL])
+#define RSCAN0RMDF161HH (RSCAN0.RMDF161.UINT8[R_IO_HH])
+#define RSCAN0RMID62 (RSCAN0.RMID62.UINT32)
+#define RSCAN0RMID62L (RSCAN0.RMID62.UINT16[R_IO_L])
+#define RSCAN0RMID62LL (RSCAN0.RMID62.UINT8[R_IO_LL])
+#define RSCAN0RMID62LH (RSCAN0.RMID62.UINT8[R_IO_LH])
+#define RSCAN0RMID62H (RSCAN0.RMID62.UINT16[R_IO_H])
+#define RSCAN0RMID62HL (RSCAN0.RMID62.UINT8[R_IO_HL])
+#define RSCAN0RMID62HH (RSCAN0.RMID62.UINT8[R_IO_HH])
+#define RSCAN0RMPTR62 (RSCAN0.RMPTR62.UINT32)
+#define RSCAN0RMPTR62L (RSCAN0.RMPTR62.UINT16[R_IO_L])
+#define RSCAN0RMPTR62LL (RSCAN0.RMPTR62.UINT8[R_IO_LL])
+#define RSCAN0RMPTR62LH (RSCAN0.RMPTR62.UINT8[R_IO_LH])
+#define RSCAN0RMPTR62H (RSCAN0.RMPTR62.UINT16[R_IO_H])
+#define RSCAN0RMPTR62HL (RSCAN0.RMPTR62.UINT8[R_IO_HL])
+#define RSCAN0RMPTR62HH (RSCAN0.RMPTR62.UINT8[R_IO_HH])
+#define RSCAN0RMDF062 (RSCAN0.RMDF062.UINT32)
+#define RSCAN0RMDF062L (RSCAN0.RMDF062.UINT16[R_IO_L])
+#define RSCAN0RMDF062LL (RSCAN0.RMDF062.UINT8[R_IO_LL])
+#define RSCAN0RMDF062LH (RSCAN0.RMDF062.UINT8[R_IO_LH])
+#define RSCAN0RMDF062H (RSCAN0.RMDF062.UINT16[R_IO_H])
+#define RSCAN0RMDF062HL (RSCAN0.RMDF062.UINT8[R_IO_HL])
+#define RSCAN0RMDF062HH (RSCAN0.RMDF062.UINT8[R_IO_HH])
+#define RSCAN0RMDF162 (RSCAN0.RMDF162.UINT32)
+#define RSCAN0RMDF162L (RSCAN0.RMDF162.UINT16[R_IO_L])
+#define RSCAN0RMDF162LL (RSCAN0.RMDF162.UINT8[R_IO_LL])
+#define RSCAN0RMDF162LH (RSCAN0.RMDF162.UINT8[R_IO_LH])
+#define RSCAN0RMDF162H (RSCAN0.RMDF162.UINT16[R_IO_H])
+#define RSCAN0RMDF162HL (RSCAN0.RMDF162.UINT8[R_IO_HL])
+#define RSCAN0RMDF162HH (RSCAN0.RMDF162.UINT8[R_IO_HH])
+#define RSCAN0RMID63 (RSCAN0.RMID63.UINT32)
+#define RSCAN0RMID63L (RSCAN0.RMID63.UINT16[R_IO_L])
+#define RSCAN0RMID63LL (RSCAN0.RMID63.UINT8[R_IO_LL])
+#define RSCAN0RMID63LH (RSCAN0.RMID63.UINT8[R_IO_LH])
+#define RSCAN0RMID63H (RSCAN0.RMID63.UINT16[R_IO_H])
+#define RSCAN0RMID63HL (RSCAN0.RMID63.UINT8[R_IO_HL])
+#define RSCAN0RMID63HH (RSCAN0.RMID63.UINT8[R_IO_HH])
+#define RSCAN0RMPTR63 (RSCAN0.RMPTR63.UINT32)
+#define RSCAN0RMPTR63L (RSCAN0.RMPTR63.UINT16[R_IO_L])
+#define RSCAN0RMPTR63LL (RSCAN0.RMPTR63.UINT8[R_IO_LL])
+#define RSCAN0RMPTR63LH (RSCAN0.RMPTR63.UINT8[R_IO_LH])
+#define RSCAN0RMPTR63H (RSCAN0.RMPTR63.UINT16[R_IO_H])
+#define RSCAN0RMPTR63HL (RSCAN0.RMPTR63.UINT8[R_IO_HL])
+#define RSCAN0RMPTR63HH (RSCAN0.RMPTR63.UINT8[R_IO_HH])
+#define RSCAN0RMDF063 (RSCAN0.RMDF063.UINT32)
+#define RSCAN0RMDF063L (RSCAN0.RMDF063.UINT16[R_IO_L])
+#define RSCAN0RMDF063LL (RSCAN0.RMDF063.UINT8[R_IO_LL])
+#define RSCAN0RMDF063LH (RSCAN0.RMDF063.UINT8[R_IO_LH])
+#define RSCAN0RMDF063H (RSCAN0.RMDF063.UINT16[R_IO_H])
+#define RSCAN0RMDF063HL (RSCAN0.RMDF063.UINT8[R_IO_HL])
+#define RSCAN0RMDF063HH (RSCAN0.RMDF063.UINT8[R_IO_HH])
+#define RSCAN0RMDF163 (RSCAN0.RMDF163.UINT32)
+#define RSCAN0RMDF163L (RSCAN0.RMDF163.UINT16[R_IO_L])
+#define RSCAN0RMDF163LL (RSCAN0.RMDF163.UINT8[R_IO_LL])
+#define RSCAN0RMDF163LH (RSCAN0.RMDF163.UINT8[R_IO_LH])
+#define RSCAN0RMDF163H (RSCAN0.RMDF163.UINT16[R_IO_H])
+#define RSCAN0RMDF163HL (RSCAN0.RMDF163.UINT8[R_IO_HL])
+#define RSCAN0RMDF163HH (RSCAN0.RMDF163.UINT8[R_IO_HH])
+#define RSCAN0RMID64 (RSCAN0.RMID64.UINT32)
+#define RSCAN0RMID64L (RSCAN0.RMID64.UINT16[R_IO_L])
+#define RSCAN0RMID64LL (RSCAN0.RMID64.UINT8[R_IO_LL])
+#define RSCAN0RMID64LH (RSCAN0.RMID64.UINT8[R_IO_LH])
+#define RSCAN0RMID64H (RSCAN0.RMID64.UINT16[R_IO_H])
+#define RSCAN0RMID64HL (RSCAN0.RMID64.UINT8[R_IO_HL])
+#define RSCAN0RMID64HH (RSCAN0.RMID64.UINT8[R_IO_HH])
+#define RSCAN0RMPTR64 (RSCAN0.RMPTR64.UINT32)
+#define RSCAN0RMPTR64L (RSCAN0.RMPTR64.UINT16[R_IO_L])
+#define RSCAN0RMPTR64LL (RSCAN0.RMPTR64.UINT8[R_IO_LL])
+#define RSCAN0RMPTR64LH (RSCAN0.RMPTR64.UINT8[R_IO_LH])
+#define RSCAN0RMPTR64H (RSCAN0.RMPTR64.UINT16[R_IO_H])
+#define RSCAN0RMPTR64HL (RSCAN0.RMPTR64.UINT8[R_IO_HL])
+#define RSCAN0RMPTR64HH (RSCAN0.RMPTR64.UINT8[R_IO_HH])
+#define RSCAN0RMDF064 (RSCAN0.RMDF064.UINT32)
+#define RSCAN0RMDF064L (RSCAN0.RMDF064.UINT16[R_IO_L])
+#define RSCAN0RMDF064LL (RSCAN0.RMDF064.UINT8[R_IO_LL])
+#define RSCAN0RMDF064LH (RSCAN0.RMDF064.UINT8[R_IO_LH])
+#define RSCAN0RMDF064H (RSCAN0.RMDF064.UINT16[R_IO_H])
+#define RSCAN0RMDF064HL (RSCAN0.RMDF064.UINT8[R_IO_HL])
+#define RSCAN0RMDF064HH (RSCAN0.RMDF064.UINT8[R_IO_HH])
+#define RSCAN0RMDF164 (RSCAN0.RMDF164.UINT32)
+#define RSCAN0RMDF164L (RSCAN0.RMDF164.UINT16[R_IO_L])
+#define RSCAN0RMDF164LL (RSCAN0.RMDF164.UINT8[R_IO_LL])
+#define RSCAN0RMDF164LH (RSCAN0.RMDF164.UINT8[R_IO_LH])
+#define RSCAN0RMDF164H (RSCAN0.RMDF164.UINT16[R_IO_H])
+#define RSCAN0RMDF164HL (RSCAN0.RMDF164.UINT8[R_IO_HL])
+#define RSCAN0RMDF164HH (RSCAN0.RMDF164.UINT8[R_IO_HH])
+#define RSCAN0RMID65 (RSCAN0.RMID65.UINT32)
+#define RSCAN0RMID65L (RSCAN0.RMID65.UINT16[R_IO_L])
+#define RSCAN0RMID65LL (RSCAN0.RMID65.UINT8[R_IO_LL])
+#define RSCAN0RMID65LH (RSCAN0.RMID65.UINT8[R_IO_LH])
+#define RSCAN0RMID65H (RSCAN0.RMID65.UINT16[R_IO_H])
+#define RSCAN0RMID65HL (RSCAN0.RMID65.UINT8[R_IO_HL])
+#define RSCAN0RMID65HH (RSCAN0.RMID65.UINT8[R_IO_HH])
+#define RSCAN0RMPTR65 (RSCAN0.RMPTR65.UINT32)
+#define RSCAN0RMPTR65L (RSCAN0.RMPTR65.UINT16[R_IO_L])
+#define RSCAN0RMPTR65LL (RSCAN0.RMPTR65.UINT8[R_IO_LL])
+#define RSCAN0RMPTR65LH (RSCAN0.RMPTR65.UINT8[R_IO_LH])
+#define RSCAN0RMPTR65H (RSCAN0.RMPTR65.UINT16[R_IO_H])
+#define RSCAN0RMPTR65HL (RSCAN0.RMPTR65.UINT8[R_IO_HL])
+#define RSCAN0RMPTR65HH (RSCAN0.RMPTR65.UINT8[R_IO_HH])
+#define RSCAN0RMDF065 (RSCAN0.RMDF065.UINT32)
+#define RSCAN0RMDF065L (RSCAN0.RMDF065.UINT16[R_IO_L])
+#define RSCAN0RMDF065LL (RSCAN0.RMDF065.UINT8[R_IO_LL])
+#define RSCAN0RMDF065LH (RSCAN0.RMDF065.UINT8[R_IO_LH])
+#define RSCAN0RMDF065H (RSCAN0.RMDF065.UINT16[R_IO_H])
+#define RSCAN0RMDF065HL (RSCAN0.RMDF065.UINT8[R_IO_HL])
+#define RSCAN0RMDF065HH (RSCAN0.RMDF065.UINT8[R_IO_HH])
+#define RSCAN0RMDF165 (RSCAN0.RMDF165.UINT32)
+#define RSCAN0RMDF165L (RSCAN0.RMDF165.UINT16[R_IO_L])
+#define RSCAN0RMDF165LL (RSCAN0.RMDF165.UINT8[R_IO_LL])
+#define RSCAN0RMDF165LH (RSCAN0.RMDF165.UINT8[R_IO_LH])
+#define RSCAN0RMDF165H (RSCAN0.RMDF165.UINT16[R_IO_H])
+#define RSCAN0RMDF165HL (RSCAN0.RMDF165.UINT8[R_IO_HL])
+#define RSCAN0RMDF165HH (RSCAN0.RMDF165.UINT8[R_IO_HH])
+#define RSCAN0RMID66 (RSCAN0.RMID66.UINT32)
+#define RSCAN0RMID66L (RSCAN0.RMID66.UINT16[R_IO_L])
+#define RSCAN0RMID66LL (RSCAN0.RMID66.UINT8[R_IO_LL])
+#define RSCAN0RMID66LH (RSCAN0.RMID66.UINT8[R_IO_LH])
+#define RSCAN0RMID66H (RSCAN0.RMID66.UINT16[R_IO_H])
+#define RSCAN0RMID66HL (RSCAN0.RMID66.UINT8[R_IO_HL])
+#define RSCAN0RMID66HH (RSCAN0.RMID66.UINT8[R_IO_HH])
+#define RSCAN0RMPTR66 (RSCAN0.RMPTR66.UINT32)
+#define RSCAN0RMPTR66L (RSCAN0.RMPTR66.UINT16[R_IO_L])
+#define RSCAN0RMPTR66LL (RSCAN0.RMPTR66.UINT8[R_IO_LL])
+#define RSCAN0RMPTR66LH (RSCAN0.RMPTR66.UINT8[R_IO_LH])
+#define RSCAN0RMPTR66H (RSCAN0.RMPTR66.UINT16[R_IO_H])
+#define RSCAN0RMPTR66HL (RSCAN0.RMPTR66.UINT8[R_IO_HL])
+#define RSCAN0RMPTR66HH (RSCAN0.RMPTR66.UINT8[R_IO_HH])
+#define RSCAN0RMDF066 (RSCAN0.RMDF066.UINT32)
+#define RSCAN0RMDF066L (RSCAN0.RMDF066.UINT16[R_IO_L])
+#define RSCAN0RMDF066LL (RSCAN0.RMDF066.UINT8[R_IO_LL])
+#define RSCAN0RMDF066LH (RSCAN0.RMDF066.UINT8[R_IO_LH])
+#define RSCAN0RMDF066H (RSCAN0.RMDF066.UINT16[R_IO_H])
+#define RSCAN0RMDF066HL (RSCAN0.RMDF066.UINT8[R_IO_HL])
+#define RSCAN0RMDF066HH (RSCAN0.RMDF066.UINT8[R_IO_HH])
+#define RSCAN0RMDF166 (RSCAN0.RMDF166.UINT32)
+#define RSCAN0RMDF166L (RSCAN0.RMDF166.UINT16[R_IO_L])
+#define RSCAN0RMDF166LL (RSCAN0.RMDF166.UINT8[R_IO_LL])
+#define RSCAN0RMDF166LH (RSCAN0.RMDF166.UINT8[R_IO_LH])
+#define RSCAN0RMDF166H (RSCAN0.RMDF166.UINT16[R_IO_H])
+#define RSCAN0RMDF166HL (RSCAN0.RMDF166.UINT8[R_IO_HL])
+#define RSCAN0RMDF166HH (RSCAN0.RMDF166.UINT8[R_IO_HH])
+#define RSCAN0RMID67 (RSCAN0.RMID67.UINT32)
+#define RSCAN0RMID67L (RSCAN0.RMID67.UINT16[R_IO_L])
+#define RSCAN0RMID67LL (RSCAN0.RMID67.UINT8[R_IO_LL])
+#define RSCAN0RMID67LH (RSCAN0.RMID67.UINT8[R_IO_LH])
+#define RSCAN0RMID67H (RSCAN0.RMID67.UINT16[R_IO_H])
+#define RSCAN0RMID67HL (RSCAN0.RMID67.UINT8[R_IO_HL])
+#define RSCAN0RMID67HH (RSCAN0.RMID67.UINT8[R_IO_HH])
+#define RSCAN0RMPTR67 (RSCAN0.RMPTR67.UINT32)
+#define RSCAN0RMPTR67L (RSCAN0.RMPTR67.UINT16[R_IO_L])
+#define RSCAN0RMPTR67LL (RSCAN0.RMPTR67.UINT8[R_IO_LL])
+#define RSCAN0RMPTR67LH (RSCAN0.RMPTR67.UINT8[R_IO_LH])
+#define RSCAN0RMPTR67H (RSCAN0.RMPTR67.UINT16[R_IO_H])
+#define RSCAN0RMPTR67HL (RSCAN0.RMPTR67.UINT8[R_IO_HL])
+#define RSCAN0RMPTR67HH (RSCAN0.RMPTR67.UINT8[R_IO_HH])
+#define RSCAN0RMDF067 (RSCAN0.RMDF067.UINT32)
+#define RSCAN0RMDF067L (RSCAN0.RMDF067.UINT16[R_IO_L])
+#define RSCAN0RMDF067LL (RSCAN0.RMDF067.UINT8[R_IO_LL])
+#define RSCAN0RMDF067LH (RSCAN0.RMDF067.UINT8[R_IO_LH])
+#define RSCAN0RMDF067H (RSCAN0.RMDF067.UINT16[R_IO_H])
+#define RSCAN0RMDF067HL (RSCAN0.RMDF067.UINT8[R_IO_HL])
+#define RSCAN0RMDF067HH (RSCAN0.RMDF067.UINT8[R_IO_HH])
+#define RSCAN0RMDF167 (RSCAN0.RMDF167.UINT32)
+#define RSCAN0RMDF167L (RSCAN0.RMDF167.UINT16[R_IO_L])
+#define RSCAN0RMDF167LL (RSCAN0.RMDF167.UINT8[R_IO_LL])
+#define RSCAN0RMDF167LH (RSCAN0.RMDF167.UINT8[R_IO_LH])
+#define RSCAN0RMDF167H (RSCAN0.RMDF167.UINT16[R_IO_H])
+#define RSCAN0RMDF167HL (RSCAN0.RMDF167.UINT8[R_IO_HL])
+#define RSCAN0RMDF167HH (RSCAN0.RMDF167.UINT8[R_IO_HH])
+#define RSCAN0RMID68 (RSCAN0.RMID68.UINT32)
+#define RSCAN0RMID68L (RSCAN0.RMID68.UINT16[R_IO_L])
+#define RSCAN0RMID68LL (RSCAN0.RMID68.UINT8[R_IO_LL])
+#define RSCAN0RMID68LH (RSCAN0.RMID68.UINT8[R_IO_LH])
+#define RSCAN0RMID68H (RSCAN0.RMID68.UINT16[R_IO_H])
+#define RSCAN0RMID68HL (RSCAN0.RMID68.UINT8[R_IO_HL])
+#define RSCAN0RMID68HH (RSCAN0.RMID68.UINT8[R_IO_HH])
+#define RSCAN0RMPTR68 (RSCAN0.RMPTR68.UINT32)
+#define RSCAN0RMPTR68L (RSCAN0.RMPTR68.UINT16[R_IO_L])
+#define RSCAN0RMPTR68LL (RSCAN0.RMPTR68.UINT8[R_IO_LL])
+#define RSCAN0RMPTR68LH (RSCAN0.RMPTR68.UINT8[R_IO_LH])
+#define RSCAN0RMPTR68H (RSCAN0.RMPTR68.UINT16[R_IO_H])
+#define RSCAN0RMPTR68HL (RSCAN0.RMPTR68.UINT8[R_IO_HL])
+#define RSCAN0RMPTR68HH (RSCAN0.RMPTR68.UINT8[R_IO_HH])
+#define RSCAN0RMDF068 (RSCAN0.RMDF068.UINT32)
+#define RSCAN0RMDF068L (RSCAN0.RMDF068.UINT16[R_IO_L])
+#define RSCAN0RMDF068LL (RSCAN0.RMDF068.UINT8[R_IO_LL])
+#define RSCAN0RMDF068LH (RSCAN0.RMDF068.UINT8[R_IO_LH])
+#define RSCAN0RMDF068H (RSCAN0.RMDF068.UINT16[R_IO_H])
+#define RSCAN0RMDF068HL (RSCAN0.RMDF068.UINT8[R_IO_HL])
+#define RSCAN0RMDF068HH (RSCAN0.RMDF068.UINT8[R_IO_HH])
+#define RSCAN0RMDF168 (RSCAN0.RMDF168.UINT32)
+#define RSCAN0RMDF168L (RSCAN0.RMDF168.UINT16[R_IO_L])
+#define RSCAN0RMDF168LL (RSCAN0.RMDF168.UINT8[R_IO_LL])
+#define RSCAN0RMDF168LH (RSCAN0.RMDF168.UINT8[R_IO_LH])
+#define RSCAN0RMDF168H (RSCAN0.RMDF168.UINT16[R_IO_H])
+#define RSCAN0RMDF168HL (RSCAN0.RMDF168.UINT8[R_IO_HL])
+#define RSCAN0RMDF168HH (RSCAN0.RMDF168.UINT8[R_IO_HH])
+#define RSCAN0RMID69 (RSCAN0.RMID69.UINT32)
+#define RSCAN0RMID69L (RSCAN0.RMID69.UINT16[R_IO_L])
+#define RSCAN0RMID69LL (RSCAN0.RMID69.UINT8[R_IO_LL])
+#define RSCAN0RMID69LH (RSCAN0.RMID69.UINT8[R_IO_LH])
+#define RSCAN0RMID69H (RSCAN0.RMID69.UINT16[R_IO_H])
+#define RSCAN0RMID69HL (RSCAN0.RMID69.UINT8[R_IO_HL])
+#define RSCAN0RMID69HH (RSCAN0.RMID69.UINT8[R_IO_HH])
+#define RSCAN0RMPTR69 (RSCAN0.RMPTR69.UINT32)
+#define RSCAN0RMPTR69L (RSCAN0.RMPTR69.UINT16[R_IO_L])
+#define RSCAN0RMPTR69LL (RSCAN0.RMPTR69.UINT8[R_IO_LL])
+#define RSCAN0RMPTR69LH (RSCAN0.RMPTR69.UINT8[R_IO_LH])
+#define RSCAN0RMPTR69H (RSCAN0.RMPTR69.UINT16[R_IO_H])
+#define RSCAN0RMPTR69HL (RSCAN0.RMPTR69.UINT8[R_IO_HL])
+#define RSCAN0RMPTR69HH (RSCAN0.RMPTR69.UINT8[R_IO_HH])
+#define RSCAN0RMDF069 (RSCAN0.RMDF069.UINT32)
+#define RSCAN0RMDF069L (RSCAN0.RMDF069.UINT16[R_IO_L])
+#define RSCAN0RMDF069LL (RSCAN0.RMDF069.UINT8[R_IO_LL])
+#define RSCAN0RMDF069LH (RSCAN0.RMDF069.UINT8[R_IO_LH])
+#define RSCAN0RMDF069H (RSCAN0.RMDF069.UINT16[R_IO_H])
+#define RSCAN0RMDF069HL (RSCAN0.RMDF069.UINT8[R_IO_HL])
+#define RSCAN0RMDF069HH (RSCAN0.RMDF069.UINT8[R_IO_HH])
+#define RSCAN0RMDF169 (RSCAN0.RMDF169.UINT32)
+#define RSCAN0RMDF169L (RSCAN0.RMDF169.UINT16[R_IO_L])
+#define RSCAN0RMDF169LL (RSCAN0.RMDF169.UINT8[R_IO_LL])
+#define RSCAN0RMDF169LH (RSCAN0.RMDF169.UINT8[R_IO_LH])
+#define RSCAN0RMDF169H (RSCAN0.RMDF169.UINT16[R_IO_H])
+#define RSCAN0RMDF169HL (RSCAN0.RMDF169.UINT8[R_IO_HL])
+#define RSCAN0RMDF169HH (RSCAN0.RMDF169.UINT8[R_IO_HH])
+#define RSCAN0RMID70 (RSCAN0.RMID70.UINT32)
+#define RSCAN0RMID70L (RSCAN0.RMID70.UINT16[R_IO_L])
+#define RSCAN0RMID70LL (RSCAN0.RMID70.UINT8[R_IO_LL])
+#define RSCAN0RMID70LH (RSCAN0.RMID70.UINT8[R_IO_LH])
+#define RSCAN0RMID70H (RSCAN0.RMID70.UINT16[R_IO_H])
+#define RSCAN0RMID70HL (RSCAN0.RMID70.UINT8[R_IO_HL])
+#define RSCAN0RMID70HH (RSCAN0.RMID70.UINT8[R_IO_HH])
+#define RSCAN0RMPTR70 (RSCAN0.RMPTR70.UINT32)
+#define RSCAN0RMPTR70L (RSCAN0.RMPTR70.UINT16[R_IO_L])
+#define RSCAN0RMPTR70LL (RSCAN0.RMPTR70.UINT8[R_IO_LL])
+#define RSCAN0RMPTR70LH (RSCAN0.RMPTR70.UINT8[R_IO_LH])
+#define RSCAN0RMPTR70H (RSCAN0.RMPTR70.UINT16[R_IO_H])
+#define RSCAN0RMPTR70HL (RSCAN0.RMPTR70.UINT8[R_IO_HL])
+#define RSCAN0RMPTR70HH (RSCAN0.RMPTR70.UINT8[R_IO_HH])
+#define RSCAN0RMDF070 (RSCAN0.RMDF070.UINT32)
+#define RSCAN0RMDF070L (RSCAN0.RMDF070.UINT16[R_IO_L])
+#define RSCAN0RMDF070LL (RSCAN0.RMDF070.UINT8[R_IO_LL])
+#define RSCAN0RMDF070LH (RSCAN0.RMDF070.UINT8[R_IO_LH])
+#define RSCAN0RMDF070H (RSCAN0.RMDF070.UINT16[R_IO_H])
+#define RSCAN0RMDF070HL (RSCAN0.RMDF070.UINT8[R_IO_HL])
+#define RSCAN0RMDF070HH (RSCAN0.RMDF070.UINT8[R_IO_HH])
+#define RSCAN0RMDF170 (RSCAN0.RMDF170.UINT32)
+#define RSCAN0RMDF170L (RSCAN0.RMDF170.UINT16[R_IO_L])
+#define RSCAN0RMDF170LL (RSCAN0.RMDF170.UINT8[R_IO_LL])
+#define RSCAN0RMDF170LH (RSCAN0.RMDF170.UINT8[R_IO_LH])
+#define RSCAN0RMDF170H (RSCAN0.RMDF170.UINT16[R_IO_H])
+#define RSCAN0RMDF170HL (RSCAN0.RMDF170.UINT8[R_IO_HL])
+#define RSCAN0RMDF170HH (RSCAN0.RMDF170.UINT8[R_IO_HH])
+#define RSCAN0RMID71 (RSCAN0.RMID71.UINT32)
+#define RSCAN0RMID71L (RSCAN0.RMID71.UINT16[R_IO_L])
+#define RSCAN0RMID71LL (RSCAN0.RMID71.UINT8[R_IO_LL])
+#define RSCAN0RMID71LH (RSCAN0.RMID71.UINT8[R_IO_LH])
+#define RSCAN0RMID71H (RSCAN0.RMID71.UINT16[R_IO_H])
+#define RSCAN0RMID71HL (RSCAN0.RMID71.UINT8[R_IO_HL])
+#define RSCAN0RMID71HH (RSCAN0.RMID71.UINT8[R_IO_HH])
+#define RSCAN0RMPTR71 (RSCAN0.RMPTR71.UINT32)
+#define RSCAN0RMPTR71L (RSCAN0.RMPTR71.UINT16[R_IO_L])
+#define RSCAN0RMPTR71LL (RSCAN0.RMPTR71.UINT8[R_IO_LL])
+#define RSCAN0RMPTR71LH (RSCAN0.RMPTR71.UINT8[R_IO_LH])
+#define RSCAN0RMPTR71H (RSCAN0.RMPTR71.UINT16[R_IO_H])
+#define RSCAN0RMPTR71HL (RSCAN0.RMPTR71.UINT8[R_IO_HL])
+#define RSCAN0RMPTR71HH (RSCAN0.RMPTR71.UINT8[R_IO_HH])
+#define RSCAN0RMDF071 (RSCAN0.RMDF071.UINT32)
+#define RSCAN0RMDF071L (RSCAN0.RMDF071.UINT16[R_IO_L])
+#define RSCAN0RMDF071LL (RSCAN0.RMDF071.UINT8[R_IO_LL])
+#define RSCAN0RMDF071LH (RSCAN0.RMDF071.UINT8[R_IO_LH])
+#define RSCAN0RMDF071H (RSCAN0.RMDF071.UINT16[R_IO_H])
+#define RSCAN0RMDF071HL (RSCAN0.RMDF071.UINT8[R_IO_HL])
+#define RSCAN0RMDF071HH (RSCAN0.RMDF071.UINT8[R_IO_HH])
+#define RSCAN0RMDF171 (RSCAN0.RMDF171.UINT32)
+#define RSCAN0RMDF171L (RSCAN0.RMDF171.UINT16[R_IO_L])
+#define RSCAN0RMDF171LL (RSCAN0.RMDF171.UINT8[R_IO_LL])
+#define RSCAN0RMDF171LH (RSCAN0.RMDF171.UINT8[R_IO_LH])
+#define RSCAN0RMDF171H (RSCAN0.RMDF171.UINT16[R_IO_H])
+#define RSCAN0RMDF171HL (RSCAN0.RMDF171.UINT8[R_IO_HL])
+#define RSCAN0RMDF171HH (RSCAN0.RMDF171.UINT8[R_IO_HH])
+#define RSCAN0RMID72 (RSCAN0.RMID72.UINT32)
+#define RSCAN0RMID72L (RSCAN0.RMID72.UINT16[R_IO_L])
+#define RSCAN0RMID72LL (RSCAN0.RMID72.UINT8[R_IO_LL])
+#define RSCAN0RMID72LH (RSCAN0.RMID72.UINT8[R_IO_LH])
+#define RSCAN0RMID72H (RSCAN0.RMID72.UINT16[R_IO_H])
+#define RSCAN0RMID72HL (RSCAN0.RMID72.UINT8[R_IO_HL])
+#define RSCAN0RMID72HH (RSCAN0.RMID72.UINT8[R_IO_HH])
+#define RSCAN0RMPTR72 (RSCAN0.RMPTR72.UINT32)
+#define RSCAN0RMPTR72L (RSCAN0.RMPTR72.UINT16[R_IO_L])
+#define RSCAN0RMPTR72LL (RSCAN0.RMPTR72.UINT8[R_IO_LL])
+#define RSCAN0RMPTR72LH (RSCAN0.RMPTR72.UINT8[R_IO_LH])
+#define RSCAN0RMPTR72H (RSCAN0.RMPTR72.UINT16[R_IO_H])
+#define RSCAN0RMPTR72HL (RSCAN0.RMPTR72.UINT8[R_IO_HL])
+#define RSCAN0RMPTR72HH (RSCAN0.RMPTR72.UINT8[R_IO_HH])
+#define RSCAN0RMDF072 (RSCAN0.RMDF072.UINT32)
+#define RSCAN0RMDF072L (RSCAN0.RMDF072.UINT16[R_IO_L])
+#define RSCAN0RMDF072LL (RSCAN0.RMDF072.UINT8[R_IO_LL])
+#define RSCAN0RMDF072LH (RSCAN0.RMDF072.UINT8[R_IO_LH])
+#define RSCAN0RMDF072H (RSCAN0.RMDF072.UINT16[R_IO_H])
+#define RSCAN0RMDF072HL (RSCAN0.RMDF072.UINT8[R_IO_HL])
+#define RSCAN0RMDF072HH (RSCAN0.RMDF072.UINT8[R_IO_HH])
+#define RSCAN0RMDF172 (RSCAN0.RMDF172.UINT32)
+#define RSCAN0RMDF172L (RSCAN0.RMDF172.UINT16[R_IO_L])
+#define RSCAN0RMDF172LL (RSCAN0.RMDF172.UINT8[R_IO_LL])
+#define RSCAN0RMDF172LH (RSCAN0.RMDF172.UINT8[R_IO_LH])
+#define RSCAN0RMDF172H (RSCAN0.RMDF172.UINT16[R_IO_H])
+#define RSCAN0RMDF172HL (RSCAN0.RMDF172.UINT8[R_IO_HL])
+#define RSCAN0RMDF172HH (RSCAN0.RMDF172.UINT8[R_IO_HH])
+#define RSCAN0RMID73 (RSCAN0.RMID73.UINT32)
+#define RSCAN0RMID73L (RSCAN0.RMID73.UINT16[R_IO_L])
+#define RSCAN0RMID73LL (RSCAN0.RMID73.UINT8[R_IO_LL])
+#define RSCAN0RMID73LH (RSCAN0.RMID73.UINT8[R_IO_LH])
+#define RSCAN0RMID73H (RSCAN0.RMID73.UINT16[R_IO_H])
+#define RSCAN0RMID73HL (RSCAN0.RMID73.UINT8[R_IO_HL])
+#define RSCAN0RMID73HH (RSCAN0.RMID73.UINT8[R_IO_HH])
+#define RSCAN0RMPTR73 (RSCAN0.RMPTR73.UINT32)
+#define RSCAN0RMPTR73L (RSCAN0.RMPTR73.UINT16[R_IO_L])
+#define RSCAN0RMPTR73LL (RSCAN0.RMPTR73.UINT8[R_IO_LL])
+#define RSCAN0RMPTR73LH (RSCAN0.RMPTR73.UINT8[R_IO_LH])
+#define RSCAN0RMPTR73H (RSCAN0.RMPTR73.UINT16[R_IO_H])
+#define RSCAN0RMPTR73HL (RSCAN0.RMPTR73.UINT8[R_IO_HL])
+#define RSCAN0RMPTR73HH (RSCAN0.RMPTR73.UINT8[R_IO_HH])
+#define RSCAN0RMDF073 (RSCAN0.RMDF073.UINT32)
+#define RSCAN0RMDF073L (RSCAN0.RMDF073.UINT16[R_IO_L])
+#define RSCAN0RMDF073LL (RSCAN0.RMDF073.UINT8[R_IO_LL])
+#define RSCAN0RMDF073LH (RSCAN0.RMDF073.UINT8[R_IO_LH])
+#define RSCAN0RMDF073H (RSCAN0.RMDF073.UINT16[R_IO_H])
+#define RSCAN0RMDF073HL (RSCAN0.RMDF073.UINT8[R_IO_HL])
+#define RSCAN0RMDF073HH (RSCAN0.RMDF073.UINT8[R_IO_HH])
+#define RSCAN0RMDF173 (RSCAN0.RMDF173.UINT32)
+#define RSCAN0RMDF173L (RSCAN0.RMDF173.UINT16[R_IO_L])
+#define RSCAN0RMDF173LL (RSCAN0.RMDF173.UINT8[R_IO_LL])
+#define RSCAN0RMDF173LH (RSCAN0.RMDF173.UINT8[R_IO_LH])
+#define RSCAN0RMDF173H (RSCAN0.RMDF173.UINT16[R_IO_H])
+#define RSCAN0RMDF173HL (RSCAN0.RMDF173.UINT8[R_IO_HL])
+#define RSCAN0RMDF173HH (RSCAN0.RMDF173.UINT8[R_IO_HH])
+#define RSCAN0RMID74 (RSCAN0.RMID74.UINT32)
+#define RSCAN0RMID74L (RSCAN0.RMID74.UINT16[R_IO_L])
+#define RSCAN0RMID74LL (RSCAN0.RMID74.UINT8[R_IO_LL])
+#define RSCAN0RMID74LH (RSCAN0.RMID74.UINT8[R_IO_LH])
+#define RSCAN0RMID74H (RSCAN0.RMID74.UINT16[R_IO_H])
+#define RSCAN0RMID74HL (RSCAN0.RMID74.UINT8[R_IO_HL])
+#define RSCAN0RMID74HH (RSCAN0.RMID74.UINT8[R_IO_HH])
+#define RSCAN0RMPTR74 (RSCAN0.RMPTR74.UINT32)
+#define RSCAN0RMPTR74L (RSCAN0.RMPTR74.UINT16[R_IO_L])
+#define RSCAN0RMPTR74LL (RSCAN0.RMPTR74.UINT8[R_IO_LL])
+#define RSCAN0RMPTR74LH (RSCAN0.RMPTR74.UINT8[R_IO_LH])
+#define RSCAN0RMPTR74H (RSCAN0.RMPTR74.UINT16[R_IO_H])
+#define RSCAN0RMPTR74HL (RSCAN0.RMPTR74.UINT8[R_IO_HL])
+#define RSCAN0RMPTR74HH (RSCAN0.RMPTR74.UINT8[R_IO_HH])
+#define RSCAN0RMDF074 (RSCAN0.RMDF074.UINT32)
+#define RSCAN0RMDF074L (RSCAN0.RMDF074.UINT16[R_IO_L])
+#define RSCAN0RMDF074LL (RSCAN0.RMDF074.UINT8[R_IO_LL])
+#define RSCAN0RMDF074LH (RSCAN0.RMDF074.UINT8[R_IO_LH])
+#define RSCAN0RMDF074H (RSCAN0.RMDF074.UINT16[R_IO_H])
+#define RSCAN0RMDF074HL (RSCAN0.RMDF074.UINT8[R_IO_HL])
+#define RSCAN0RMDF074HH (RSCAN0.RMDF074.UINT8[R_IO_HH])
+#define RSCAN0RMDF174 (RSCAN0.RMDF174.UINT32)
+#define RSCAN0RMDF174L (RSCAN0.RMDF174.UINT16[R_IO_L])
+#define RSCAN0RMDF174LL (RSCAN0.RMDF174.UINT8[R_IO_LL])
+#define RSCAN0RMDF174LH (RSCAN0.RMDF174.UINT8[R_IO_LH])
+#define RSCAN0RMDF174H (RSCAN0.RMDF174.UINT16[R_IO_H])
+#define RSCAN0RMDF174HL (RSCAN0.RMDF174.UINT8[R_IO_HL])
+#define RSCAN0RMDF174HH (RSCAN0.RMDF174.UINT8[R_IO_HH])
+#define RSCAN0RMID75 (RSCAN0.RMID75.UINT32)
+#define RSCAN0RMID75L (RSCAN0.RMID75.UINT16[R_IO_L])
+#define RSCAN0RMID75LL (RSCAN0.RMID75.UINT8[R_IO_LL])
+#define RSCAN0RMID75LH (RSCAN0.RMID75.UINT8[R_IO_LH])
+#define RSCAN0RMID75H (RSCAN0.RMID75.UINT16[R_IO_H])
+#define RSCAN0RMID75HL (RSCAN0.RMID75.UINT8[R_IO_HL])
+#define RSCAN0RMID75HH (RSCAN0.RMID75.UINT8[R_IO_HH])
+#define RSCAN0RMPTR75 (RSCAN0.RMPTR75.UINT32)
+#define RSCAN0RMPTR75L (RSCAN0.RMPTR75.UINT16[R_IO_L])
+#define RSCAN0RMPTR75LL (RSCAN0.RMPTR75.UINT8[R_IO_LL])
+#define RSCAN0RMPTR75LH (RSCAN0.RMPTR75.UINT8[R_IO_LH])
+#define RSCAN0RMPTR75H (RSCAN0.RMPTR75.UINT16[R_IO_H])
+#define RSCAN0RMPTR75HL (RSCAN0.RMPTR75.UINT8[R_IO_HL])
+#define RSCAN0RMPTR75HH (RSCAN0.RMPTR75.UINT8[R_IO_HH])
+#define RSCAN0RMDF075 (RSCAN0.RMDF075.UINT32)
+#define RSCAN0RMDF075L (RSCAN0.RMDF075.UINT16[R_IO_L])
+#define RSCAN0RMDF075LL (RSCAN0.RMDF075.UINT8[R_IO_LL])
+#define RSCAN0RMDF075LH (RSCAN0.RMDF075.UINT8[R_IO_LH])
+#define RSCAN0RMDF075H (RSCAN0.RMDF075.UINT16[R_IO_H])
+#define RSCAN0RMDF075HL (RSCAN0.RMDF075.UINT8[R_IO_HL])
+#define RSCAN0RMDF075HH (RSCAN0.RMDF075.UINT8[R_IO_HH])
+#define RSCAN0RMDF175 (RSCAN0.RMDF175.UINT32)
+#define RSCAN0RMDF175L (RSCAN0.RMDF175.UINT16[R_IO_L])
+#define RSCAN0RMDF175LL (RSCAN0.RMDF175.UINT8[R_IO_LL])
+#define RSCAN0RMDF175LH (RSCAN0.RMDF175.UINT8[R_IO_LH])
+#define RSCAN0RMDF175H (RSCAN0.RMDF175.UINT16[R_IO_H])
+#define RSCAN0RMDF175HL (RSCAN0.RMDF175.UINT8[R_IO_HL])
+#define RSCAN0RMDF175HH (RSCAN0.RMDF175.UINT8[R_IO_HH])
+#define RSCAN0RMID76 (RSCAN0.RMID76.UINT32)
+#define RSCAN0RMID76L (RSCAN0.RMID76.UINT16[R_IO_L])
+#define RSCAN0RMID76LL (RSCAN0.RMID76.UINT8[R_IO_LL])
+#define RSCAN0RMID76LH (RSCAN0.RMID76.UINT8[R_IO_LH])
+#define RSCAN0RMID76H (RSCAN0.RMID76.UINT16[R_IO_H])
+#define RSCAN0RMID76HL (RSCAN0.RMID76.UINT8[R_IO_HL])
+#define RSCAN0RMID76HH (RSCAN0.RMID76.UINT8[R_IO_HH])
+#define RSCAN0RMPTR76 (RSCAN0.RMPTR76.UINT32)
+#define RSCAN0RMPTR76L (RSCAN0.RMPTR76.UINT16[R_IO_L])
+#define RSCAN0RMPTR76LL (RSCAN0.RMPTR76.UINT8[R_IO_LL])
+#define RSCAN0RMPTR76LH (RSCAN0.RMPTR76.UINT8[R_IO_LH])
+#define RSCAN0RMPTR76H (RSCAN0.RMPTR76.UINT16[R_IO_H])
+#define RSCAN0RMPTR76HL (RSCAN0.RMPTR76.UINT8[R_IO_HL])
+#define RSCAN0RMPTR76HH (RSCAN0.RMPTR76.UINT8[R_IO_HH])
+#define RSCAN0RMDF076 (RSCAN0.RMDF076.UINT32)
+#define RSCAN0RMDF076L (RSCAN0.RMDF076.UINT16[R_IO_L])
+#define RSCAN0RMDF076LL (RSCAN0.RMDF076.UINT8[R_IO_LL])
+#define RSCAN0RMDF076LH (RSCAN0.RMDF076.UINT8[R_IO_LH])
+#define RSCAN0RMDF076H (RSCAN0.RMDF076.UINT16[R_IO_H])
+#define RSCAN0RMDF076HL (RSCAN0.RMDF076.UINT8[R_IO_HL])
+#define RSCAN0RMDF076HH (RSCAN0.RMDF076.UINT8[R_IO_HH])
+#define RSCAN0RMDF176 (RSCAN0.RMDF176.UINT32)
+#define RSCAN0RMDF176L (RSCAN0.RMDF176.UINT16[R_IO_L])
+#define RSCAN0RMDF176LL (RSCAN0.RMDF176.UINT8[R_IO_LL])
+#define RSCAN0RMDF176LH (RSCAN0.RMDF176.UINT8[R_IO_LH])
+#define RSCAN0RMDF176H (RSCAN0.RMDF176.UINT16[R_IO_H])
+#define RSCAN0RMDF176HL (RSCAN0.RMDF176.UINT8[R_IO_HL])
+#define RSCAN0RMDF176HH (RSCAN0.RMDF176.UINT8[R_IO_HH])
+#define RSCAN0RMID77 (RSCAN0.RMID77.UINT32)
+#define RSCAN0RMID77L (RSCAN0.RMID77.UINT16[R_IO_L])
+#define RSCAN0RMID77LL (RSCAN0.RMID77.UINT8[R_IO_LL])
+#define RSCAN0RMID77LH (RSCAN0.RMID77.UINT8[R_IO_LH])
+#define RSCAN0RMID77H (RSCAN0.RMID77.UINT16[R_IO_H])
+#define RSCAN0RMID77HL (RSCAN0.RMID77.UINT8[R_IO_HL])
+#define RSCAN0RMID77HH (RSCAN0.RMID77.UINT8[R_IO_HH])
+#define RSCAN0RMPTR77 (RSCAN0.RMPTR77.UINT32)
+#define RSCAN0RMPTR77L (RSCAN0.RMPTR77.UINT16[R_IO_L])
+#define RSCAN0RMPTR77LL (RSCAN0.RMPTR77.UINT8[R_IO_LL])
+#define RSCAN0RMPTR77LH (RSCAN0.RMPTR77.UINT8[R_IO_LH])
+#define RSCAN0RMPTR77H (RSCAN0.RMPTR77.UINT16[R_IO_H])
+#define RSCAN0RMPTR77HL (RSCAN0.RMPTR77.UINT8[R_IO_HL])
+#define RSCAN0RMPTR77HH (RSCAN0.RMPTR77.UINT8[R_IO_HH])
+#define RSCAN0RMDF077 (RSCAN0.RMDF077.UINT32)
+#define RSCAN0RMDF077L (RSCAN0.RMDF077.UINT16[R_IO_L])
+#define RSCAN0RMDF077LL (RSCAN0.RMDF077.UINT8[R_IO_LL])
+#define RSCAN0RMDF077LH (RSCAN0.RMDF077.UINT8[R_IO_LH])
+#define RSCAN0RMDF077H (RSCAN0.RMDF077.UINT16[R_IO_H])
+#define RSCAN0RMDF077HL (RSCAN0.RMDF077.UINT8[R_IO_HL])
+#define RSCAN0RMDF077HH (RSCAN0.RMDF077.UINT8[R_IO_HH])
+#define RSCAN0RMDF177 (RSCAN0.RMDF177.UINT32)
+#define RSCAN0RMDF177L (RSCAN0.RMDF177.UINT16[R_IO_L])
+#define RSCAN0RMDF177LL (RSCAN0.RMDF177.UINT8[R_IO_LL])
+#define RSCAN0RMDF177LH (RSCAN0.RMDF177.UINT8[R_IO_LH])
+#define RSCAN0RMDF177H (RSCAN0.RMDF177.UINT16[R_IO_H])
+#define RSCAN0RMDF177HL (RSCAN0.RMDF177.UINT8[R_IO_HL])
+#define RSCAN0RMDF177HH (RSCAN0.RMDF177.UINT8[R_IO_HH])
+#define RSCAN0RMID78 (RSCAN0.RMID78.UINT32)
+#define RSCAN0RMID78L (RSCAN0.RMID78.UINT16[R_IO_L])
+#define RSCAN0RMID78LL (RSCAN0.RMID78.UINT8[R_IO_LL])
+#define RSCAN0RMID78LH (RSCAN0.RMID78.UINT8[R_IO_LH])
+#define RSCAN0RMID78H (RSCAN0.RMID78.UINT16[R_IO_H])
+#define RSCAN0RMID78HL (RSCAN0.RMID78.UINT8[R_IO_HL])
+#define RSCAN0RMID78HH (RSCAN0.RMID78.UINT8[R_IO_HH])
+#define RSCAN0RMPTR78 (RSCAN0.RMPTR78.UINT32)
+#define RSCAN0RMPTR78L (RSCAN0.RMPTR78.UINT16[R_IO_L])
+#define RSCAN0RMPTR78LL (RSCAN0.RMPTR78.UINT8[R_IO_LL])
+#define RSCAN0RMPTR78LH (RSCAN0.RMPTR78.UINT8[R_IO_LH])
+#define RSCAN0RMPTR78H (RSCAN0.RMPTR78.UINT16[R_IO_H])
+#define RSCAN0RMPTR78HL (RSCAN0.RMPTR78.UINT8[R_IO_HL])
+#define RSCAN0RMPTR78HH (RSCAN0.RMPTR78.UINT8[R_IO_HH])
+#define RSCAN0RMDF078 (RSCAN0.RMDF078.UINT32)
+#define RSCAN0RMDF078L (RSCAN0.RMDF078.UINT16[R_IO_L])
+#define RSCAN0RMDF078LL (RSCAN0.RMDF078.UINT8[R_IO_LL])
+#define RSCAN0RMDF078LH (RSCAN0.RMDF078.UINT8[R_IO_LH])
+#define RSCAN0RMDF078H (RSCAN0.RMDF078.UINT16[R_IO_H])
+#define RSCAN0RMDF078HL (RSCAN0.RMDF078.UINT8[R_IO_HL])
+#define RSCAN0RMDF078HH (RSCAN0.RMDF078.UINT8[R_IO_HH])
+#define RSCAN0RMDF178 (RSCAN0.RMDF178.UINT32)
+#define RSCAN0RMDF178L (RSCAN0.RMDF178.UINT16[R_IO_L])
+#define RSCAN0RMDF178LL (RSCAN0.RMDF178.UINT8[R_IO_LL])
+#define RSCAN0RMDF178LH (RSCAN0.RMDF178.UINT8[R_IO_LH])
+#define RSCAN0RMDF178H (RSCAN0.RMDF178.UINT16[R_IO_H])
+#define RSCAN0RMDF178HL (RSCAN0.RMDF178.UINT8[R_IO_HL])
+#define RSCAN0RMDF178HH (RSCAN0.RMDF178.UINT8[R_IO_HH])
+#define RSCAN0RMID79 (RSCAN0.RMID79.UINT32)
+#define RSCAN0RMID79L (RSCAN0.RMID79.UINT16[R_IO_L])
+#define RSCAN0RMID79LL (RSCAN0.RMID79.UINT8[R_IO_LL])
+#define RSCAN0RMID79LH (RSCAN0.RMID79.UINT8[R_IO_LH])
+#define RSCAN0RMID79H (RSCAN0.RMID79.UINT16[R_IO_H])
+#define RSCAN0RMID79HL (RSCAN0.RMID79.UINT8[R_IO_HL])
+#define RSCAN0RMID79HH (RSCAN0.RMID79.UINT8[R_IO_HH])
+#define RSCAN0RMPTR79 (RSCAN0.RMPTR79.UINT32)
+#define RSCAN0RMPTR79L (RSCAN0.RMPTR79.UINT16[R_IO_L])
+#define RSCAN0RMPTR79LL (RSCAN0.RMPTR79.UINT8[R_IO_LL])
+#define RSCAN0RMPTR79LH (RSCAN0.RMPTR79.UINT8[R_IO_LH])
+#define RSCAN0RMPTR79H (RSCAN0.RMPTR79.UINT16[R_IO_H])
+#define RSCAN0RMPTR79HL (RSCAN0.RMPTR79.UINT8[R_IO_HL])
+#define RSCAN0RMPTR79HH (RSCAN0.RMPTR79.UINT8[R_IO_HH])
+#define RSCAN0RMDF079 (RSCAN0.RMDF079.UINT32)
+#define RSCAN0RMDF079L (RSCAN0.RMDF079.UINT16[R_IO_L])
+#define RSCAN0RMDF079LL (RSCAN0.RMDF079.UINT8[R_IO_LL])
+#define RSCAN0RMDF079LH (RSCAN0.RMDF079.UINT8[R_IO_LH])
+#define RSCAN0RMDF079H (RSCAN0.RMDF079.UINT16[R_IO_H])
+#define RSCAN0RMDF079HL (RSCAN0.RMDF079.UINT8[R_IO_HL])
+#define RSCAN0RMDF079HH (RSCAN0.RMDF079.UINT8[R_IO_HH])
+#define RSCAN0RMDF179 (RSCAN0.RMDF179.UINT32)
+#define RSCAN0RMDF179L (RSCAN0.RMDF179.UINT16[R_IO_L])
+#define RSCAN0RMDF179LL (RSCAN0.RMDF179.UINT8[R_IO_LL])
+#define RSCAN0RMDF179LH (RSCAN0.RMDF179.UINT8[R_IO_LH])
+#define RSCAN0RMDF179H (RSCAN0.RMDF179.UINT16[R_IO_H])
+#define RSCAN0RMDF179HL (RSCAN0.RMDF179.UINT8[R_IO_HL])
+#define RSCAN0RMDF179HH (RSCAN0.RMDF179.UINT8[R_IO_HH])
+#define RSCAN0RFID0 (RSCAN0.RFID0.UINT32)
+#define RSCAN0RFID0L (RSCAN0.RFID0.UINT16[R_IO_L])
+#define RSCAN0RFID0LL (RSCAN0.RFID0.UINT8[R_IO_LL])
+#define RSCAN0RFID0LH (RSCAN0.RFID0.UINT8[R_IO_LH])
+#define RSCAN0RFID0H (RSCAN0.RFID0.UINT16[R_IO_H])
+#define RSCAN0RFID0HL (RSCAN0.RFID0.UINT8[R_IO_HL])
+#define RSCAN0RFID0HH (RSCAN0.RFID0.UINT8[R_IO_HH])
+#define RSCAN0RFPTR0 (RSCAN0.RFPTR0.UINT32)
+#define RSCAN0RFPTR0L (RSCAN0.RFPTR0.UINT16[R_IO_L])
+#define RSCAN0RFPTR0LL (RSCAN0.RFPTR0.UINT8[R_IO_LL])
+#define RSCAN0RFPTR0LH (RSCAN0.RFPTR0.UINT8[R_IO_LH])
+#define RSCAN0RFPTR0H (RSCAN0.RFPTR0.UINT16[R_IO_H])
+#define RSCAN0RFPTR0HL (RSCAN0.RFPTR0.UINT8[R_IO_HL])
+#define RSCAN0RFPTR0HH (RSCAN0.RFPTR0.UINT8[R_IO_HH])
+#define RSCAN0RFDF00 (RSCAN0.RFDF00.UINT32)
+#define RSCAN0RFDF00L (RSCAN0.RFDF00.UINT16[R_IO_L])
+#define RSCAN0RFDF00LL (RSCAN0.RFDF00.UINT8[R_IO_LL])
+#define RSCAN0RFDF00LH (RSCAN0.RFDF00.UINT8[R_IO_LH])
+#define RSCAN0RFDF00H (RSCAN0.RFDF00.UINT16[R_IO_H])
+#define RSCAN0RFDF00HL (RSCAN0.RFDF00.UINT8[R_IO_HL])
+#define RSCAN0RFDF00HH (RSCAN0.RFDF00.UINT8[R_IO_HH])
+#define RSCAN0RFDF10 (RSCAN0.RFDF10.UINT32)
+#define RSCAN0RFDF10L (RSCAN0.RFDF10.UINT16[R_IO_L])
+#define RSCAN0RFDF10LL (RSCAN0.RFDF10.UINT8[R_IO_LL])
+#define RSCAN0RFDF10LH (RSCAN0.RFDF10.UINT8[R_IO_LH])
+#define RSCAN0RFDF10H (RSCAN0.RFDF10.UINT16[R_IO_H])
+#define RSCAN0RFDF10HL (RSCAN0.RFDF10.UINT8[R_IO_HL])
+#define RSCAN0RFDF10HH (RSCAN0.RFDF10.UINT8[R_IO_HH])
+#define RSCAN0RFID1 (RSCAN0.RFID1.UINT32)
+#define RSCAN0RFID1L (RSCAN0.RFID1.UINT16[R_IO_L])
+#define RSCAN0RFID1LL (RSCAN0.RFID1.UINT8[R_IO_LL])
+#define RSCAN0RFID1LH (RSCAN0.RFID1.UINT8[R_IO_LH])
+#define RSCAN0RFID1H (RSCAN0.RFID1.UINT16[R_IO_H])
+#define RSCAN0RFID1HL (RSCAN0.RFID1.UINT8[R_IO_HL])
+#define RSCAN0RFID1HH (RSCAN0.RFID1.UINT8[R_IO_HH])
+#define RSCAN0RFPTR1 (RSCAN0.RFPTR1.UINT32)
+#define RSCAN0RFPTR1L (RSCAN0.RFPTR1.UINT16[R_IO_L])
+#define RSCAN0RFPTR1LL (RSCAN0.RFPTR1.UINT8[R_IO_LL])
+#define RSCAN0RFPTR1LH (RSCAN0.RFPTR1.UINT8[R_IO_LH])
+#define RSCAN0RFPTR1H (RSCAN0.RFPTR1.UINT16[R_IO_H])
+#define RSCAN0RFPTR1HL (RSCAN0.RFPTR1.UINT8[R_IO_HL])
+#define RSCAN0RFPTR1HH (RSCAN0.RFPTR1.UINT8[R_IO_HH])
+#define RSCAN0RFDF01 (RSCAN0.RFDF01.UINT32)
+#define RSCAN0RFDF01L (RSCAN0.RFDF01.UINT16[R_IO_L])
+#define RSCAN0RFDF01LL (RSCAN0.RFDF01.UINT8[R_IO_LL])
+#define RSCAN0RFDF01LH (RSCAN0.RFDF01.UINT8[R_IO_LH])
+#define RSCAN0RFDF01H (RSCAN0.RFDF01.UINT16[R_IO_H])
+#define RSCAN0RFDF01HL (RSCAN0.RFDF01.UINT8[R_IO_HL])
+#define RSCAN0RFDF01HH (RSCAN0.RFDF01.UINT8[R_IO_HH])
+#define RSCAN0RFDF11 (RSCAN0.RFDF11.UINT32)
+#define RSCAN0RFDF11L (RSCAN0.RFDF11.UINT16[R_IO_L])
+#define RSCAN0RFDF11LL (RSCAN0.RFDF11.UINT8[R_IO_LL])
+#define RSCAN0RFDF11LH (RSCAN0.RFDF11.UINT8[R_IO_LH])
+#define RSCAN0RFDF11H (RSCAN0.RFDF11.UINT16[R_IO_H])
+#define RSCAN0RFDF11HL (RSCAN0.RFDF11.UINT8[R_IO_HL])
+#define RSCAN0RFDF11HH (RSCAN0.RFDF11.UINT8[R_IO_HH])
+#define RSCAN0RFID2 (RSCAN0.RFID2.UINT32)
+#define RSCAN0RFID2L (RSCAN0.RFID2.UINT16[R_IO_L])
+#define RSCAN0RFID2LL (RSCAN0.RFID2.UINT8[R_IO_LL])
+#define RSCAN0RFID2LH (RSCAN0.RFID2.UINT8[R_IO_LH])
+#define RSCAN0RFID2H (RSCAN0.RFID2.UINT16[R_IO_H])
+#define RSCAN0RFID2HL (RSCAN0.RFID2.UINT8[R_IO_HL])
+#define RSCAN0RFID2HH (RSCAN0.RFID2.UINT8[R_IO_HH])
+#define RSCAN0RFPTR2 (RSCAN0.RFPTR2.UINT32)
+#define RSCAN0RFPTR2L (RSCAN0.RFPTR2.UINT16[R_IO_L])
+#define RSCAN0RFPTR2LL (RSCAN0.RFPTR2.UINT8[R_IO_LL])
+#define RSCAN0RFPTR2LH (RSCAN0.RFPTR2.UINT8[R_IO_LH])
+#define RSCAN0RFPTR2H (RSCAN0.RFPTR2.UINT16[R_IO_H])
+#define RSCAN0RFPTR2HL (RSCAN0.RFPTR2.UINT8[R_IO_HL])
+#define RSCAN0RFPTR2HH (RSCAN0.RFPTR2.UINT8[R_IO_HH])
+#define RSCAN0RFDF02 (RSCAN0.RFDF02.UINT32)
+#define RSCAN0RFDF02L (RSCAN0.RFDF02.UINT16[R_IO_L])
+#define RSCAN0RFDF02LL (RSCAN0.RFDF02.UINT8[R_IO_LL])
+#define RSCAN0RFDF02LH (RSCAN0.RFDF02.UINT8[R_IO_LH])
+#define RSCAN0RFDF02H (RSCAN0.RFDF02.UINT16[R_IO_H])
+#define RSCAN0RFDF02HL (RSCAN0.RFDF02.UINT8[R_IO_HL])
+#define RSCAN0RFDF02HH (RSCAN0.RFDF02.UINT8[R_IO_HH])
+#define RSCAN0RFDF12 (RSCAN0.RFDF12.UINT32)
+#define RSCAN0RFDF12L (RSCAN0.RFDF12.UINT16[R_IO_L])
+#define RSCAN0RFDF12LL (RSCAN0.RFDF12.UINT8[R_IO_LL])
+#define RSCAN0RFDF12LH (RSCAN0.RFDF12.UINT8[R_IO_LH])
+#define RSCAN0RFDF12H (RSCAN0.RFDF12.UINT16[R_IO_H])
+#define RSCAN0RFDF12HL (RSCAN0.RFDF12.UINT8[R_IO_HL])
+#define RSCAN0RFDF12HH (RSCAN0.RFDF12.UINT8[R_IO_HH])
+#define RSCAN0RFID3 (RSCAN0.RFID3.UINT32)
+#define RSCAN0RFID3L (RSCAN0.RFID3.UINT16[R_IO_L])
+#define RSCAN0RFID3LL (RSCAN0.RFID3.UINT8[R_IO_LL])
+#define RSCAN0RFID3LH (RSCAN0.RFID3.UINT8[R_IO_LH])
+#define RSCAN0RFID3H (RSCAN0.RFID3.UINT16[R_IO_H])
+#define RSCAN0RFID3HL (RSCAN0.RFID3.UINT8[R_IO_HL])
+#define RSCAN0RFID3HH (RSCAN0.RFID3.UINT8[R_IO_HH])
+#define RSCAN0RFPTR3 (RSCAN0.RFPTR3.UINT32)
+#define RSCAN0RFPTR3L (RSCAN0.RFPTR3.UINT16[R_IO_L])
+#define RSCAN0RFPTR3LL (RSCAN0.RFPTR3.UINT8[R_IO_LL])
+#define RSCAN0RFPTR3LH (RSCAN0.RFPTR3.UINT8[R_IO_LH])
+#define RSCAN0RFPTR3H (RSCAN0.RFPTR3.UINT16[R_IO_H])
+#define RSCAN0RFPTR3HL (RSCAN0.RFPTR3.UINT8[R_IO_HL])
+#define RSCAN0RFPTR3HH (RSCAN0.RFPTR3.UINT8[R_IO_HH])
+#define RSCAN0RFDF03 (RSCAN0.RFDF03.UINT32)
+#define RSCAN0RFDF03L (RSCAN0.RFDF03.UINT16[R_IO_L])
+#define RSCAN0RFDF03LL (RSCAN0.RFDF03.UINT8[R_IO_LL])
+#define RSCAN0RFDF03LH (RSCAN0.RFDF03.UINT8[R_IO_LH])
+#define RSCAN0RFDF03H (RSCAN0.RFDF03.UINT16[R_IO_H])
+#define RSCAN0RFDF03HL (RSCAN0.RFDF03.UINT8[R_IO_HL])
+#define RSCAN0RFDF03HH (RSCAN0.RFDF03.UINT8[R_IO_HH])
+#define RSCAN0RFDF13 (RSCAN0.RFDF13.UINT32)
+#define RSCAN0RFDF13L (RSCAN0.RFDF13.UINT16[R_IO_L])
+#define RSCAN0RFDF13LL (RSCAN0.RFDF13.UINT8[R_IO_LL])
+#define RSCAN0RFDF13LH (RSCAN0.RFDF13.UINT8[R_IO_LH])
+#define RSCAN0RFDF13H (RSCAN0.RFDF13.UINT16[R_IO_H])
+#define RSCAN0RFDF13HL (RSCAN0.RFDF13.UINT8[R_IO_HL])
+#define RSCAN0RFDF13HH (RSCAN0.RFDF13.UINT8[R_IO_HH])
+#define RSCAN0RFID4 (RSCAN0.RFID4.UINT32)
+#define RSCAN0RFID4L (RSCAN0.RFID4.UINT16[R_IO_L])
+#define RSCAN0RFID4LL (RSCAN0.RFID4.UINT8[R_IO_LL])
+#define RSCAN0RFID4LH (RSCAN0.RFID4.UINT8[R_IO_LH])
+#define RSCAN0RFID4H (RSCAN0.RFID4.UINT16[R_IO_H])
+#define RSCAN0RFID4HL (RSCAN0.RFID4.UINT8[R_IO_HL])
+#define RSCAN0RFID4HH (RSCAN0.RFID4.UINT8[R_IO_HH])
+#define RSCAN0RFPTR4 (RSCAN0.RFPTR4.UINT32)
+#define RSCAN0RFPTR4L (RSCAN0.RFPTR4.UINT16[R_IO_L])
+#define RSCAN0RFPTR4LL (RSCAN0.RFPTR4.UINT8[R_IO_LL])
+#define RSCAN0RFPTR4LH (RSCAN0.RFPTR4.UINT8[R_IO_LH])
+#define RSCAN0RFPTR4H (RSCAN0.RFPTR4.UINT16[R_IO_H])
+#define RSCAN0RFPTR4HL (RSCAN0.RFPTR4.UINT8[R_IO_HL])
+#define RSCAN0RFPTR4HH (RSCAN0.RFPTR4.UINT8[R_IO_HH])
+#define RSCAN0RFDF04 (RSCAN0.RFDF04.UINT32)
+#define RSCAN0RFDF04L (RSCAN0.RFDF04.UINT16[R_IO_L])
+#define RSCAN0RFDF04LL (RSCAN0.RFDF04.UINT8[R_IO_LL])
+#define RSCAN0RFDF04LH (RSCAN0.RFDF04.UINT8[R_IO_LH])
+#define RSCAN0RFDF04H (RSCAN0.RFDF04.UINT16[R_IO_H])
+#define RSCAN0RFDF04HL (RSCAN0.RFDF04.UINT8[R_IO_HL])
+#define RSCAN0RFDF04HH (RSCAN0.RFDF04.UINT8[R_IO_HH])
+#define RSCAN0RFDF14 (RSCAN0.RFDF14.UINT32)
+#define RSCAN0RFDF14L (RSCAN0.RFDF14.UINT16[R_IO_L])
+#define RSCAN0RFDF14LL (RSCAN0.RFDF14.UINT8[R_IO_LL])
+#define RSCAN0RFDF14LH (RSCAN0.RFDF14.UINT8[R_IO_LH])
+#define RSCAN0RFDF14H (RSCAN0.RFDF14.UINT16[R_IO_H])
+#define RSCAN0RFDF14HL (RSCAN0.RFDF14.UINT8[R_IO_HL])
+#define RSCAN0RFDF14HH (RSCAN0.RFDF14.UINT8[R_IO_HH])
+#define RSCAN0RFID5 (RSCAN0.RFID5.UINT32)
+#define RSCAN0RFID5L (RSCAN0.RFID5.UINT16[R_IO_L])
+#define RSCAN0RFID5LL (RSCAN0.RFID5.UINT8[R_IO_LL])
+#define RSCAN0RFID5LH (RSCAN0.RFID5.UINT8[R_IO_LH])
+#define RSCAN0RFID5H (RSCAN0.RFID5.UINT16[R_IO_H])
+#define RSCAN0RFID5HL (RSCAN0.RFID5.UINT8[R_IO_HL])
+#define RSCAN0RFID5HH (RSCAN0.RFID5.UINT8[R_IO_HH])
+#define RSCAN0RFPTR5 (RSCAN0.RFPTR5.UINT32)
+#define RSCAN0RFPTR5L (RSCAN0.RFPTR5.UINT16[R_IO_L])
+#define RSCAN0RFPTR5LL (RSCAN0.RFPTR5.UINT8[R_IO_LL])
+#define RSCAN0RFPTR5LH (RSCAN0.RFPTR5.UINT8[R_IO_LH])
+#define RSCAN0RFPTR5H (RSCAN0.RFPTR5.UINT16[R_IO_H])
+#define RSCAN0RFPTR5HL (RSCAN0.RFPTR5.UINT8[R_IO_HL])
+#define RSCAN0RFPTR5HH (RSCAN0.RFPTR5.UINT8[R_IO_HH])
+#define RSCAN0RFDF05 (RSCAN0.RFDF05.UINT32)
+#define RSCAN0RFDF05L (RSCAN0.RFDF05.UINT16[R_IO_L])
+#define RSCAN0RFDF05LL (RSCAN0.RFDF05.UINT8[R_IO_LL])
+#define RSCAN0RFDF05LH (RSCAN0.RFDF05.UINT8[R_IO_LH])
+#define RSCAN0RFDF05H (RSCAN0.RFDF05.UINT16[R_IO_H])
+#define RSCAN0RFDF05HL (RSCAN0.RFDF05.UINT8[R_IO_HL])
+#define RSCAN0RFDF05HH (RSCAN0.RFDF05.UINT8[R_IO_HH])
+#define RSCAN0RFDF15 (RSCAN0.RFDF15.UINT32)
+#define RSCAN0RFDF15L (RSCAN0.RFDF15.UINT16[R_IO_L])
+#define RSCAN0RFDF15LL (RSCAN0.RFDF15.UINT8[R_IO_LL])
+#define RSCAN0RFDF15LH (RSCAN0.RFDF15.UINT8[R_IO_LH])
+#define RSCAN0RFDF15H (RSCAN0.RFDF15.UINT16[R_IO_H])
+#define RSCAN0RFDF15HL (RSCAN0.RFDF15.UINT8[R_IO_HL])
+#define RSCAN0RFDF15HH (RSCAN0.RFDF15.UINT8[R_IO_HH])
+#define RSCAN0RFID6 (RSCAN0.RFID6.UINT32)
+#define RSCAN0RFID6L (RSCAN0.RFID6.UINT16[R_IO_L])
+#define RSCAN0RFID6LL (RSCAN0.RFID6.UINT8[R_IO_LL])
+#define RSCAN0RFID6LH (RSCAN0.RFID6.UINT8[R_IO_LH])
+#define RSCAN0RFID6H (RSCAN0.RFID6.UINT16[R_IO_H])
+#define RSCAN0RFID6HL (RSCAN0.RFID6.UINT8[R_IO_HL])
+#define RSCAN0RFID6HH (RSCAN0.RFID6.UINT8[R_IO_HH])
+#define RSCAN0RFPTR6 (RSCAN0.RFPTR6.UINT32)
+#define RSCAN0RFPTR6L (RSCAN0.RFPTR6.UINT16[R_IO_L])
+#define RSCAN0RFPTR6LL (RSCAN0.RFPTR6.UINT8[R_IO_LL])
+#define RSCAN0RFPTR6LH (RSCAN0.RFPTR6.UINT8[R_IO_LH])
+#define RSCAN0RFPTR6H (RSCAN0.RFPTR6.UINT16[R_IO_H])
+#define RSCAN0RFPTR6HL (RSCAN0.RFPTR6.UINT8[R_IO_HL])
+#define RSCAN0RFPTR6HH (RSCAN0.RFPTR6.UINT8[R_IO_HH])
+#define RSCAN0RFDF06 (RSCAN0.RFDF06.UINT32)
+#define RSCAN0RFDF06L (RSCAN0.RFDF06.UINT16[R_IO_L])
+#define RSCAN0RFDF06LL (RSCAN0.RFDF06.UINT8[R_IO_LL])
+#define RSCAN0RFDF06LH (RSCAN0.RFDF06.UINT8[R_IO_LH])
+#define RSCAN0RFDF06H (RSCAN0.RFDF06.UINT16[R_IO_H])
+#define RSCAN0RFDF06HL (RSCAN0.RFDF06.UINT8[R_IO_HL])
+#define RSCAN0RFDF06HH (RSCAN0.RFDF06.UINT8[R_IO_HH])
+#define RSCAN0RFDF16 (RSCAN0.RFDF16.UINT32)
+#define RSCAN0RFDF16L (RSCAN0.RFDF16.UINT16[R_IO_L])
+#define RSCAN0RFDF16LL (RSCAN0.RFDF16.UINT8[R_IO_LL])
+#define RSCAN0RFDF16LH (RSCAN0.RFDF16.UINT8[R_IO_LH])
+#define RSCAN0RFDF16H (RSCAN0.RFDF16.UINT16[R_IO_H])
+#define RSCAN0RFDF16HL (RSCAN0.RFDF16.UINT8[R_IO_HL])
+#define RSCAN0RFDF16HH (RSCAN0.RFDF16.UINT8[R_IO_HH])
+#define RSCAN0RFID7 (RSCAN0.RFID7.UINT32)
+#define RSCAN0RFID7L (RSCAN0.RFID7.UINT16[R_IO_L])
+#define RSCAN0RFID7LL (RSCAN0.RFID7.UINT8[R_IO_LL])
+#define RSCAN0RFID7LH (RSCAN0.RFID7.UINT8[R_IO_LH])
+#define RSCAN0RFID7H (RSCAN0.RFID7.UINT16[R_IO_H])
+#define RSCAN0RFID7HL (RSCAN0.RFID7.UINT8[R_IO_HL])
+#define RSCAN0RFID7HH (RSCAN0.RFID7.UINT8[R_IO_HH])
+#define RSCAN0RFPTR7 (RSCAN0.RFPTR7.UINT32)
+#define RSCAN0RFPTR7L (RSCAN0.RFPTR7.UINT16[R_IO_L])
+#define RSCAN0RFPTR7LL (RSCAN0.RFPTR7.UINT8[R_IO_LL])
+#define RSCAN0RFPTR7LH (RSCAN0.RFPTR7.UINT8[R_IO_LH])
+#define RSCAN0RFPTR7H (RSCAN0.RFPTR7.UINT16[R_IO_H])
+#define RSCAN0RFPTR7HL (RSCAN0.RFPTR7.UINT8[R_IO_HL])
+#define RSCAN0RFPTR7HH (RSCAN0.RFPTR7.UINT8[R_IO_HH])
+#define RSCAN0RFDF07 (RSCAN0.RFDF07.UINT32)
+#define RSCAN0RFDF07L (RSCAN0.RFDF07.UINT16[R_IO_L])
+#define RSCAN0RFDF07LL (RSCAN0.RFDF07.UINT8[R_IO_LL])
+#define RSCAN0RFDF07LH (RSCAN0.RFDF07.UINT8[R_IO_LH])
+#define RSCAN0RFDF07H (RSCAN0.RFDF07.UINT16[R_IO_H])
+#define RSCAN0RFDF07HL (RSCAN0.RFDF07.UINT8[R_IO_HL])
+#define RSCAN0RFDF07HH (RSCAN0.RFDF07.UINT8[R_IO_HH])
+#define RSCAN0RFDF17 (RSCAN0.RFDF17.UINT32)
+#define RSCAN0RFDF17L (RSCAN0.RFDF17.UINT16[R_IO_L])
+#define RSCAN0RFDF17LL (RSCAN0.RFDF17.UINT8[R_IO_LL])
+#define RSCAN0RFDF17LH (RSCAN0.RFDF17.UINT8[R_IO_LH])
+#define RSCAN0RFDF17H (RSCAN0.RFDF17.UINT16[R_IO_H])
+#define RSCAN0RFDF17HL (RSCAN0.RFDF17.UINT8[R_IO_HL])
+#define RSCAN0RFDF17HH (RSCAN0.RFDF17.UINT8[R_IO_HH])
+#define RSCAN0CFID0 (RSCAN0.CFID0.UINT32)
+#define RSCAN0CFID0L (RSCAN0.CFID0.UINT16[R_IO_L])
+#define RSCAN0CFID0LL (RSCAN0.CFID0.UINT8[R_IO_LL])
+#define RSCAN0CFID0LH (RSCAN0.CFID0.UINT8[R_IO_LH])
+#define RSCAN0CFID0H (RSCAN0.CFID0.UINT16[R_IO_H])
+#define RSCAN0CFID0HL (RSCAN0.CFID0.UINT8[R_IO_HL])
+#define RSCAN0CFID0HH (RSCAN0.CFID0.UINT8[R_IO_HH])
+#define RSCAN0CFPTR0 (RSCAN0.CFPTR0.UINT32)
+#define RSCAN0CFPTR0L (RSCAN0.CFPTR0.UINT16[R_IO_L])
+#define RSCAN0CFPTR0LL (RSCAN0.CFPTR0.UINT8[R_IO_LL])
+#define RSCAN0CFPTR0LH (RSCAN0.CFPTR0.UINT8[R_IO_LH])
+#define RSCAN0CFPTR0H (RSCAN0.CFPTR0.UINT16[R_IO_H])
+#define RSCAN0CFPTR0HL (RSCAN0.CFPTR0.UINT8[R_IO_HL])
+#define RSCAN0CFPTR0HH (RSCAN0.CFPTR0.UINT8[R_IO_HH])
+#define RSCAN0CFDF00 (RSCAN0.CFDF00.UINT32)
+#define RSCAN0CFDF00L (RSCAN0.CFDF00.UINT16[R_IO_L])
+#define RSCAN0CFDF00LL (RSCAN0.CFDF00.UINT8[R_IO_LL])
+#define RSCAN0CFDF00LH (RSCAN0.CFDF00.UINT8[R_IO_LH])
+#define RSCAN0CFDF00H (RSCAN0.CFDF00.UINT16[R_IO_H])
+#define RSCAN0CFDF00HL (RSCAN0.CFDF00.UINT8[R_IO_HL])
+#define RSCAN0CFDF00HH (RSCAN0.CFDF00.UINT8[R_IO_HH])
+#define RSCAN0CFDF10 (RSCAN0.CFDF10.UINT32)
+#define RSCAN0CFDF10L (RSCAN0.CFDF10.UINT16[R_IO_L])
+#define RSCAN0CFDF10LL (RSCAN0.CFDF10.UINT8[R_IO_LL])
+#define RSCAN0CFDF10LH (RSCAN0.CFDF10.UINT8[R_IO_LH])
+#define RSCAN0CFDF10H (RSCAN0.CFDF10.UINT16[R_IO_H])
+#define RSCAN0CFDF10HL (RSCAN0.CFDF10.UINT8[R_IO_HL])
+#define RSCAN0CFDF10HH (RSCAN0.CFDF10.UINT8[R_IO_HH])
+#define RSCAN0CFID1 (RSCAN0.CFID1.UINT32)
+#define RSCAN0CFID1L (RSCAN0.CFID1.UINT16[R_IO_L])
+#define RSCAN0CFID1LL (RSCAN0.CFID1.UINT8[R_IO_LL])
+#define RSCAN0CFID1LH (RSCAN0.CFID1.UINT8[R_IO_LH])
+#define RSCAN0CFID1H (RSCAN0.CFID1.UINT16[R_IO_H])
+#define RSCAN0CFID1HL (RSCAN0.CFID1.UINT8[R_IO_HL])
+#define RSCAN0CFID1HH (RSCAN0.CFID1.UINT8[R_IO_HH])
+#define RSCAN0CFPTR1 (RSCAN0.CFPTR1.UINT32)
+#define RSCAN0CFPTR1L (RSCAN0.CFPTR1.UINT16[R_IO_L])
+#define RSCAN0CFPTR1LL (RSCAN0.CFPTR1.UINT8[R_IO_LL])
+#define RSCAN0CFPTR1LH (RSCAN0.CFPTR1.UINT8[R_IO_LH])
+#define RSCAN0CFPTR1H (RSCAN0.CFPTR1.UINT16[R_IO_H])
+#define RSCAN0CFPTR1HL (RSCAN0.CFPTR1.UINT8[R_IO_HL])
+#define RSCAN0CFPTR1HH (RSCAN0.CFPTR1.UINT8[R_IO_HH])
+#define RSCAN0CFDF01 (RSCAN0.CFDF01.UINT32)
+#define RSCAN0CFDF01L (RSCAN0.CFDF01.UINT16[R_IO_L])
+#define RSCAN0CFDF01LL (RSCAN0.CFDF01.UINT8[R_IO_LL])
+#define RSCAN0CFDF01LH (RSCAN0.CFDF01.UINT8[R_IO_LH])
+#define RSCAN0CFDF01H (RSCAN0.CFDF01.UINT16[R_IO_H])
+#define RSCAN0CFDF01HL (RSCAN0.CFDF01.UINT8[R_IO_HL])
+#define RSCAN0CFDF01HH (RSCAN0.CFDF01.UINT8[R_IO_HH])
+#define RSCAN0CFDF11 (RSCAN0.CFDF11.UINT32)
+#define RSCAN0CFDF11L (RSCAN0.CFDF11.UINT16[R_IO_L])
+#define RSCAN0CFDF11LL (RSCAN0.CFDF11.UINT8[R_IO_LL])
+#define RSCAN0CFDF11LH (RSCAN0.CFDF11.UINT8[R_IO_LH])
+#define RSCAN0CFDF11H (RSCAN0.CFDF11.UINT16[R_IO_H])
+#define RSCAN0CFDF11HL (RSCAN0.CFDF11.UINT8[R_IO_HL])
+#define RSCAN0CFDF11HH (RSCAN0.CFDF11.UINT8[R_IO_HH])
+#define RSCAN0CFID2 (RSCAN0.CFID2.UINT32)
+#define RSCAN0CFID2L (RSCAN0.CFID2.UINT16[R_IO_L])
+#define RSCAN0CFID2LL (RSCAN0.CFID2.UINT8[R_IO_LL])
+#define RSCAN0CFID2LH (RSCAN0.CFID2.UINT8[R_IO_LH])
+#define RSCAN0CFID2H (RSCAN0.CFID2.UINT16[R_IO_H])
+#define RSCAN0CFID2HL (RSCAN0.CFID2.UINT8[R_IO_HL])
+#define RSCAN0CFID2HH (RSCAN0.CFID2.UINT8[R_IO_HH])
+#define RSCAN0CFPTR2 (RSCAN0.CFPTR2.UINT32)
+#define RSCAN0CFPTR2L (RSCAN0.CFPTR2.UINT16[R_IO_L])
+#define RSCAN0CFPTR2LL (RSCAN0.CFPTR2.UINT8[R_IO_LL])
+#define RSCAN0CFPTR2LH (RSCAN0.CFPTR2.UINT8[R_IO_LH])
+#define RSCAN0CFPTR2H (RSCAN0.CFPTR2.UINT16[R_IO_H])
+#define RSCAN0CFPTR2HL (RSCAN0.CFPTR2.UINT8[R_IO_HL])
+#define RSCAN0CFPTR2HH (RSCAN0.CFPTR2.UINT8[R_IO_HH])
+#define RSCAN0CFDF02 (RSCAN0.CFDF02.UINT32)
+#define RSCAN0CFDF02L (RSCAN0.CFDF02.UINT16[R_IO_L])
+#define RSCAN0CFDF02LL (RSCAN0.CFDF02.UINT8[R_IO_LL])
+#define RSCAN0CFDF02LH (RSCAN0.CFDF02.UINT8[R_IO_LH])
+#define RSCAN0CFDF02H (RSCAN0.CFDF02.UINT16[R_IO_H])
+#define RSCAN0CFDF02HL (RSCAN0.CFDF02.UINT8[R_IO_HL])
+#define RSCAN0CFDF02HH (RSCAN0.CFDF02.UINT8[R_IO_HH])
+#define RSCAN0CFDF12 (RSCAN0.CFDF12.UINT32)
+#define RSCAN0CFDF12L (RSCAN0.CFDF12.UINT16[R_IO_L])
+#define RSCAN0CFDF12LL (RSCAN0.CFDF12.UINT8[R_IO_LL])
+#define RSCAN0CFDF12LH (RSCAN0.CFDF12.UINT8[R_IO_LH])
+#define RSCAN0CFDF12H (RSCAN0.CFDF12.UINT16[R_IO_H])
+#define RSCAN0CFDF12HL (RSCAN0.CFDF12.UINT8[R_IO_HL])
+#define RSCAN0CFDF12HH (RSCAN0.CFDF12.UINT8[R_IO_HH])
+#define RSCAN0CFID3 (RSCAN0.CFID3.UINT32)
+#define RSCAN0CFID3L (RSCAN0.CFID3.UINT16[R_IO_L])
+#define RSCAN0CFID3LL (RSCAN0.CFID3.UINT8[R_IO_LL])
+#define RSCAN0CFID3LH (RSCAN0.CFID3.UINT8[R_IO_LH])
+#define RSCAN0CFID3H (RSCAN0.CFID3.UINT16[R_IO_H])
+#define RSCAN0CFID3HL (RSCAN0.CFID3.UINT8[R_IO_HL])
+#define RSCAN0CFID3HH (RSCAN0.CFID3.UINT8[R_IO_HH])
+#define RSCAN0CFPTR3 (RSCAN0.CFPTR3.UINT32)
+#define RSCAN0CFPTR3L (RSCAN0.CFPTR3.UINT16[R_IO_L])
+#define RSCAN0CFPTR3LL (RSCAN0.CFPTR3.UINT8[R_IO_LL])
+#define RSCAN0CFPTR3LH (RSCAN0.CFPTR3.UINT8[R_IO_LH])
+#define RSCAN0CFPTR3H (RSCAN0.CFPTR3.UINT16[R_IO_H])
+#define RSCAN0CFPTR3HL (RSCAN0.CFPTR3.UINT8[R_IO_HL])
+#define RSCAN0CFPTR3HH (RSCAN0.CFPTR3.UINT8[R_IO_HH])
+#define RSCAN0CFDF03 (RSCAN0.CFDF03.UINT32)
+#define RSCAN0CFDF03L (RSCAN0.CFDF03.UINT16[R_IO_L])
+#define RSCAN0CFDF03LL (RSCAN0.CFDF03.UINT8[R_IO_LL])
+#define RSCAN0CFDF03LH (RSCAN0.CFDF03.UINT8[R_IO_LH])
+#define RSCAN0CFDF03H (RSCAN0.CFDF03.UINT16[R_IO_H])
+#define RSCAN0CFDF03HL (RSCAN0.CFDF03.UINT8[R_IO_HL])
+#define RSCAN0CFDF03HH (RSCAN0.CFDF03.UINT8[R_IO_HH])
+#define RSCAN0CFDF13 (RSCAN0.CFDF13.UINT32)
+#define RSCAN0CFDF13L (RSCAN0.CFDF13.UINT16[R_IO_L])
+#define RSCAN0CFDF13LL (RSCAN0.CFDF13.UINT8[R_IO_LL])
+#define RSCAN0CFDF13LH (RSCAN0.CFDF13.UINT8[R_IO_LH])
+#define RSCAN0CFDF13H (RSCAN0.CFDF13.UINT16[R_IO_H])
+#define RSCAN0CFDF13HL (RSCAN0.CFDF13.UINT8[R_IO_HL])
+#define RSCAN0CFDF13HH (RSCAN0.CFDF13.UINT8[R_IO_HH])
+#define RSCAN0CFID4 (RSCAN0.CFID4.UINT32)
+#define RSCAN0CFID4L (RSCAN0.CFID4.UINT16[R_IO_L])
+#define RSCAN0CFID4LL (RSCAN0.CFID4.UINT8[R_IO_LL])
+#define RSCAN0CFID4LH (RSCAN0.CFID4.UINT8[R_IO_LH])
+#define RSCAN0CFID4H (RSCAN0.CFID4.UINT16[R_IO_H])
+#define RSCAN0CFID4HL (RSCAN0.CFID4.UINT8[R_IO_HL])
+#define RSCAN0CFID4HH (RSCAN0.CFID4.UINT8[R_IO_HH])
+#define RSCAN0CFPTR4 (RSCAN0.CFPTR4.UINT32)
+#define RSCAN0CFPTR4L (RSCAN0.CFPTR4.UINT16[R_IO_L])
+#define RSCAN0CFPTR4LL (RSCAN0.CFPTR4.UINT8[R_IO_LL])
+#define RSCAN0CFPTR4LH (RSCAN0.CFPTR4.UINT8[R_IO_LH])
+#define RSCAN0CFPTR4H (RSCAN0.CFPTR4.UINT16[R_IO_H])
+#define RSCAN0CFPTR4HL (RSCAN0.CFPTR4.UINT8[R_IO_HL])
+#define RSCAN0CFPTR4HH (RSCAN0.CFPTR4.UINT8[R_IO_HH])
+#define RSCAN0CFDF04 (RSCAN0.CFDF04.UINT32)
+#define RSCAN0CFDF04L (RSCAN0.CFDF04.UINT16[R_IO_L])
+#define RSCAN0CFDF04LL (RSCAN0.CFDF04.UINT8[R_IO_LL])
+#define RSCAN0CFDF04LH (RSCAN0.CFDF04.UINT8[R_IO_LH])
+#define RSCAN0CFDF04H (RSCAN0.CFDF04.UINT16[R_IO_H])
+#define RSCAN0CFDF04HL (RSCAN0.CFDF04.UINT8[R_IO_HL])
+#define RSCAN0CFDF04HH (RSCAN0.CFDF04.UINT8[R_IO_HH])
+#define RSCAN0CFDF14 (RSCAN0.CFDF14.UINT32)
+#define RSCAN0CFDF14L (RSCAN0.CFDF14.UINT16[R_IO_L])
+#define RSCAN0CFDF14LL (RSCAN0.CFDF14.UINT8[R_IO_LL])
+#define RSCAN0CFDF14LH (RSCAN0.CFDF14.UINT8[R_IO_LH])
+#define RSCAN0CFDF14H (RSCAN0.CFDF14.UINT16[R_IO_H])
+#define RSCAN0CFDF14HL (RSCAN0.CFDF14.UINT8[R_IO_HL])
+#define RSCAN0CFDF14HH (RSCAN0.CFDF14.UINT8[R_IO_HH])
+#define RSCAN0CFID5 (RSCAN0.CFID5.UINT32)
+#define RSCAN0CFID5L (RSCAN0.CFID5.UINT16[R_IO_L])
+#define RSCAN0CFID5LL (RSCAN0.CFID5.UINT8[R_IO_LL])
+#define RSCAN0CFID5LH (RSCAN0.CFID5.UINT8[R_IO_LH])
+#define RSCAN0CFID5H (RSCAN0.CFID5.UINT16[R_IO_H])
+#define RSCAN0CFID5HL (RSCAN0.CFID5.UINT8[R_IO_HL])
+#define RSCAN0CFID5HH (RSCAN0.CFID5.UINT8[R_IO_HH])
+#define RSCAN0CFPTR5 (RSCAN0.CFPTR5.UINT32)
+#define RSCAN0CFPTR5L (RSCAN0.CFPTR5.UINT16[R_IO_L])
+#define RSCAN0CFPTR5LL (RSCAN0.CFPTR5.UINT8[R_IO_LL])
+#define RSCAN0CFPTR5LH (RSCAN0.CFPTR5.UINT8[R_IO_LH])
+#define RSCAN0CFPTR5H (RSCAN0.CFPTR5.UINT16[R_IO_H])
+#define RSCAN0CFPTR5HL (RSCAN0.CFPTR5.UINT8[R_IO_HL])
+#define RSCAN0CFPTR5HH (RSCAN0.CFPTR5.UINT8[R_IO_HH])
+#define RSCAN0CFDF05 (RSCAN0.CFDF05.UINT32)
+#define RSCAN0CFDF05L (RSCAN0.CFDF05.UINT16[R_IO_L])
+#define RSCAN0CFDF05LL (RSCAN0.CFDF05.UINT8[R_IO_LL])
+#define RSCAN0CFDF05LH (RSCAN0.CFDF05.UINT8[R_IO_LH])
+#define RSCAN0CFDF05H (RSCAN0.CFDF05.UINT16[R_IO_H])
+#define RSCAN0CFDF05HL (RSCAN0.CFDF05.UINT8[R_IO_HL])
+#define RSCAN0CFDF05HH (RSCAN0.CFDF05.UINT8[R_IO_HH])
+#define RSCAN0CFDF15 (RSCAN0.CFDF15.UINT32)
+#define RSCAN0CFDF15L (RSCAN0.CFDF15.UINT16[R_IO_L])
+#define RSCAN0CFDF15LL (RSCAN0.CFDF15.UINT8[R_IO_LL])
+#define RSCAN0CFDF15LH (RSCAN0.CFDF15.UINT8[R_IO_LH])
+#define RSCAN0CFDF15H (RSCAN0.CFDF15.UINT16[R_IO_H])
+#define RSCAN0CFDF15HL (RSCAN0.CFDF15.UINT8[R_IO_HL])
+#define RSCAN0CFDF15HH (RSCAN0.CFDF15.UINT8[R_IO_HH])
+#define RSCAN0CFID6 (RSCAN0.CFID6.UINT32)
+#define RSCAN0CFID6L (RSCAN0.CFID6.UINT16[R_IO_L])
+#define RSCAN0CFID6LL (RSCAN0.CFID6.UINT8[R_IO_LL])
+#define RSCAN0CFID6LH (RSCAN0.CFID6.UINT8[R_IO_LH])
+#define RSCAN0CFID6H (RSCAN0.CFID6.UINT16[R_IO_H])
+#define RSCAN0CFID6HL (RSCAN0.CFID6.UINT8[R_IO_HL])
+#define RSCAN0CFID6HH (RSCAN0.CFID6.UINT8[R_IO_HH])
+#define RSCAN0CFPTR6 (RSCAN0.CFPTR6.UINT32)
+#define RSCAN0CFPTR6L (RSCAN0.CFPTR6.UINT16[R_IO_L])
+#define RSCAN0CFPTR6LL (RSCAN0.CFPTR6.UINT8[R_IO_LL])
+#define RSCAN0CFPTR6LH (RSCAN0.CFPTR6.UINT8[R_IO_LH])
+#define RSCAN0CFPTR6H (RSCAN0.CFPTR6.UINT16[R_IO_H])
+#define RSCAN0CFPTR6HL (RSCAN0.CFPTR6.UINT8[R_IO_HL])
+#define RSCAN0CFPTR6HH (RSCAN0.CFPTR6.UINT8[R_IO_HH])
+#define RSCAN0CFDF06 (RSCAN0.CFDF06.UINT32)
+#define RSCAN0CFDF06L (RSCAN0.CFDF06.UINT16[R_IO_L])
+#define RSCAN0CFDF06LL (RSCAN0.CFDF06.UINT8[R_IO_LL])
+#define RSCAN0CFDF06LH (RSCAN0.CFDF06.UINT8[R_IO_LH])
+#define RSCAN0CFDF06H (RSCAN0.CFDF06.UINT16[R_IO_H])
+#define RSCAN0CFDF06HL (RSCAN0.CFDF06.UINT8[R_IO_HL])
+#define RSCAN0CFDF06HH (RSCAN0.CFDF06.UINT8[R_IO_HH])
+#define RSCAN0CFDF16 (RSCAN0.CFDF16.UINT32)
+#define RSCAN0CFDF16L (RSCAN0.CFDF16.UINT16[R_IO_L])
+#define RSCAN0CFDF16LL (RSCAN0.CFDF16.UINT8[R_IO_LL])
+#define RSCAN0CFDF16LH (RSCAN0.CFDF16.UINT8[R_IO_LH])
+#define RSCAN0CFDF16H (RSCAN0.CFDF16.UINT16[R_IO_H])
+#define RSCAN0CFDF16HL (RSCAN0.CFDF16.UINT8[R_IO_HL])
+#define RSCAN0CFDF16HH (RSCAN0.CFDF16.UINT8[R_IO_HH])
+#define RSCAN0CFID7 (RSCAN0.CFID7.UINT32)
+#define RSCAN0CFID7L (RSCAN0.CFID7.UINT16[R_IO_L])
+#define RSCAN0CFID7LL (RSCAN0.CFID7.UINT8[R_IO_LL])
+#define RSCAN0CFID7LH (RSCAN0.CFID7.UINT8[R_IO_LH])
+#define RSCAN0CFID7H (RSCAN0.CFID7.UINT16[R_IO_H])
+#define RSCAN0CFID7HL (RSCAN0.CFID7.UINT8[R_IO_HL])
+#define RSCAN0CFID7HH (RSCAN0.CFID7.UINT8[R_IO_HH])
+#define RSCAN0CFPTR7 (RSCAN0.CFPTR7.UINT32)
+#define RSCAN0CFPTR7L (RSCAN0.CFPTR7.UINT16[R_IO_L])
+#define RSCAN0CFPTR7LL (RSCAN0.CFPTR7.UINT8[R_IO_LL])
+#define RSCAN0CFPTR7LH (RSCAN0.CFPTR7.UINT8[R_IO_LH])
+#define RSCAN0CFPTR7H (RSCAN0.CFPTR7.UINT16[R_IO_H])
+#define RSCAN0CFPTR7HL (RSCAN0.CFPTR7.UINT8[R_IO_HL])
+#define RSCAN0CFPTR7HH (RSCAN0.CFPTR7.UINT8[R_IO_HH])
+#define RSCAN0CFDF07 (RSCAN0.CFDF07.UINT32)
+#define RSCAN0CFDF07L (RSCAN0.CFDF07.UINT16[R_IO_L])
+#define RSCAN0CFDF07LL (RSCAN0.CFDF07.UINT8[R_IO_LL])
+#define RSCAN0CFDF07LH (RSCAN0.CFDF07.UINT8[R_IO_LH])
+#define RSCAN0CFDF07H (RSCAN0.CFDF07.UINT16[R_IO_H])
+#define RSCAN0CFDF07HL (RSCAN0.CFDF07.UINT8[R_IO_HL])
+#define RSCAN0CFDF07HH (RSCAN0.CFDF07.UINT8[R_IO_HH])
+#define RSCAN0CFDF17 (RSCAN0.CFDF17.UINT32)
+#define RSCAN0CFDF17L (RSCAN0.CFDF17.UINT16[R_IO_L])
+#define RSCAN0CFDF17LL (RSCAN0.CFDF17.UINT8[R_IO_LL])
+#define RSCAN0CFDF17LH (RSCAN0.CFDF17.UINT8[R_IO_LH])
+#define RSCAN0CFDF17H (RSCAN0.CFDF17.UINT16[R_IO_H])
+#define RSCAN0CFDF17HL (RSCAN0.CFDF17.UINT8[R_IO_HL])
+#define RSCAN0CFDF17HH (RSCAN0.CFDF17.UINT8[R_IO_HH])
+#define RSCAN0CFID8 (RSCAN0.CFID8.UINT32)
+#define RSCAN0CFID8L (RSCAN0.CFID8.UINT16[R_IO_L])
+#define RSCAN0CFID8LL (RSCAN0.CFID8.UINT8[R_IO_LL])
+#define RSCAN0CFID8LH (RSCAN0.CFID8.UINT8[R_IO_LH])
+#define RSCAN0CFID8H (RSCAN0.CFID8.UINT16[R_IO_H])
+#define RSCAN0CFID8HL (RSCAN0.CFID8.UINT8[R_IO_HL])
+#define RSCAN0CFID8HH (RSCAN0.CFID8.UINT8[R_IO_HH])
+#define RSCAN0CFPTR8 (RSCAN0.CFPTR8.UINT32)
+#define RSCAN0CFPTR8L (RSCAN0.CFPTR8.UINT16[R_IO_L])
+#define RSCAN0CFPTR8LL (RSCAN0.CFPTR8.UINT8[R_IO_LL])
+#define RSCAN0CFPTR8LH (RSCAN0.CFPTR8.UINT8[R_IO_LH])
+#define RSCAN0CFPTR8H (RSCAN0.CFPTR8.UINT16[R_IO_H])
+#define RSCAN0CFPTR8HL (RSCAN0.CFPTR8.UINT8[R_IO_HL])
+#define RSCAN0CFPTR8HH (RSCAN0.CFPTR8.UINT8[R_IO_HH])
+#define RSCAN0CFDF08 (RSCAN0.CFDF08.UINT32)
+#define RSCAN0CFDF08L (RSCAN0.CFDF08.UINT16[R_IO_L])
+#define RSCAN0CFDF08LL (RSCAN0.CFDF08.UINT8[R_IO_LL])
+#define RSCAN0CFDF08LH (RSCAN0.CFDF08.UINT8[R_IO_LH])
+#define RSCAN0CFDF08H (RSCAN0.CFDF08.UINT16[R_IO_H])
+#define RSCAN0CFDF08HL (RSCAN0.CFDF08.UINT8[R_IO_HL])
+#define RSCAN0CFDF08HH (RSCAN0.CFDF08.UINT8[R_IO_HH])
+#define RSCAN0CFDF18 (RSCAN0.CFDF18.UINT32)
+#define RSCAN0CFDF18L (RSCAN0.CFDF18.UINT16[R_IO_L])
+#define RSCAN0CFDF18LL (RSCAN0.CFDF18.UINT8[R_IO_LL])
+#define RSCAN0CFDF18LH (RSCAN0.CFDF18.UINT8[R_IO_LH])
+#define RSCAN0CFDF18H (RSCAN0.CFDF18.UINT16[R_IO_H])
+#define RSCAN0CFDF18HL (RSCAN0.CFDF18.UINT8[R_IO_HL])
+#define RSCAN0CFDF18HH (RSCAN0.CFDF18.UINT8[R_IO_HH])
+#define RSCAN0CFID9 (RSCAN0.CFID9.UINT32)
+#define RSCAN0CFID9L (RSCAN0.CFID9.UINT16[R_IO_L])
+#define RSCAN0CFID9LL (RSCAN0.CFID9.UINT8[R_IO_LL])
+#define RSCAN0CFID9LH (RSCAN0.CFID9.UINT8[R_IO_LH])
+#define RSCAN0CFID9H (RSCAN0.CFID9.UINT16[R_IO_H])
+#define RSCAN0CFID9HL (RSCAN0.CFID9.UINT8[R_IO_HL])
+#define RSCAN0CFID9HH (RSCAN0.CFID9.UINT8[R_IO_HH])
+#define RSCAN0CFPTR9 (RSCAN0.CFPTR9.UINT32)
+#define RSCAN0CFPTR9L (RSCAN0.CFPTR9.UINT16[R_IO_L])
+#define RSCAN0CFPTR9LL (RSCAN0.CFPTR9.UINT8[R_IO_LL])
+#define RSCAN0CFPTR9LH (RSCAN0.CFPTR9.UINT8[R_IO_LH])
+#define RSCAN0CFPTR9H (RSCAN0.CFPTR9.UINT16[R_IO_H])
+#define RSCAN0CFPTR9HL (RSCAN0.CFPTR9.UINT8[R_IO_HL])
+#define RSCAN0CFPTR9HH (RSCAN0.CFPTR9.UINT8[R_IO_HH])
+#define RSCAN0CFDF09 (RSCAN0.CFDF09.UINT32)
+#define RSCAN0CFDF09L (RSCAN0.CFDF09.UINT16[R_IO_L])
+#define RSCAN0CFDF09LL (RSCAN0.CFDF09.UINT8[R_IO_LL])
+#define RSCAN0CFDF09LH (RSCAN0.CFDF09.UINT8[R_IO_LH])
+#define RSCAN0CFDF09H (RSCAN0.CFDF09.UINT16[R_IO_H])
+#define RSCAN0CFDF09HL (RSCAN0.CFDF09.UINT8[R_IO_HL])
+#define RSCAN0CFDF09HH (RSCAN0.CFDF09.UINT8[R_IO_HH])
+#define RSCAN0CFDF19 (RSCAN0.CFDF19.UINT32)
+#define RSCAN0CFDF19L (RSCAN0.CFDF19.UINT16[R_IO_L])
+#define RSCAN0CFDF19LL (RSCAN0.CFDF19.UINT8[R_IO_LL])
+#define RSCAN0CFDF19LH (RSCAN0.CFDF19.UINT8[R_IO_LH])
+#define RSCAN0CFDF19H (RSCAN0.CFDF19.UINT16[R_IO_H])
+#define RSCAN0CFDF19HL (RSCAN0.CFDF19.UINT8[R_IO_HL])
+#define RSCAN0CFDF19HH (RSCAN0.CFDF19.UINT8[R_IO_HH])
+#define RSCAN0CFID10 (RSCAN0.CFID10.UINT32)
+#define RSCAN0CFID10L (RSCAN0.CFID10.UINT16[R_IO_L])
+#define RSCAN0CFID10LL (RSCAN0.CFID10.UINT8[R_IO_LL])
+#define RSCAN0CFID10LH (RSCAN0.CFID10.UINT8[R_IO_LH])
+#define RSCAN0CFID10H (RSCAN0.CFID10.UINT16[R_IO_H])
+#define RSCAN0CFID10HL (RSCAN0.CFID10.UINT8[R_IO_HL])
+#define RSCAN0CFID10HH (RSCAN0.CFID10.UINT8[R_IO_HH])
+#define RSCAN0CFPTR10 (RSCAN0.CFPTR10.UINT32)
+#define RSCAN0CFPTR10L (RSCAN0.CFPTR10.UINT16[R_IO_L])
+#define RSCAN0CFPTR10LL (RSCAN0.CFPTR10.UINT8[R_IO_LL])
+#define RSCAN0CFPTR10LH (RSCAN0.CFPTR10.UINT8[R_IO_LH])
+#define RSCAN0CFPTR10H (RSCAN0.CFPTR10.UINT16[R_IO_H])
+#define RSCAN0CFPTR10HL (RSCAN0.CFPTR10.UINT8[R_IO_HL])
+#define RSCAN0CFPTR10HH (RSCAN0.CFPTR10.UINT8[R_IO_HH])
+#define RSCAN0CFDF010 (RSCAN0.CFDF010.UINT32)
+#define RSCAN0CFDF010L (RSCAN0.CFDF010.UINT16[R_IO_L])
+#define RSCAN0CFDF010LL (RSCAN0.CFDF010.UINT8[R_IO_LL])
+#define RSCAN0CFDF010LH (RSCAN0.CFDF010.UINT8[R_IO_LH])
+#define RSCAN0CFDF010H (RSCAN0.CFDF010.UINT16[R_IO_H])
+#define RSCAN0CFDF010HL (RSCAN0.CFDF010.UINT8[R_IO_HL])
+#define RSCAN0CFDF010HH (RSCAN0.CFDF010.UINT8[R_IO_HH])
+#define RSCAN0CFDF110 (RSCAN0.CFDF110.UINT32)
+#define RSCAN0CFDF110L (RSCAN0.CFDF110.UINT16[R_IO_L])
+#define RSCAN0CFDF110LL (RSCAN0.CFDF110.UINT8[R_IO_LL])
+#define RSCAN0CFDF110LH (RSCAN0.CFDF110.UINT8[R_IO_LH])
+#define RSCAN0CFDF110H (RSCAN0.CFDF110.UINT16[R_IO_H])
+#define RSCAN0CFDF110HL (RSCAN0.CFDF110.UINT8[R_IO_HL])
+#define RSCAN0CFDF110HH (RSCAN0.CFDF110.UINT8[R_IO_HH])
+#define RSCAN0CFID11 (RSCAN0.CFID11.UINT32)
+#define RSCAN0CFID11L (RSCAN0.CFID11.UINT16[R_IO_L])
+#define RSCAN0CFID11LL (RSCAN0.CFID11.UINT8[R_IO_LL])
+#define RSCAN0CFID11LH (RSCAN0.CFID11.UINT8[R_IO_LH])
+#define RSCAN0CFID11H (RSCAN0.CFID11.UINT16[R_IO_H])
+#define RSCAN0CFID11HL (RSCAN0.CFID11.UINT8[R_IO_HL])
+#define RSCAN0CFID11HH (RSCAN0.CFID11.UINT8[R_IO_HH])
+#define RSCAN0CFPTR11 (RSCAN0.CFPTR11.UINT32)
+#define RSCAN0CFPTR11L (RSCAN0.CFPTR11.UINT16[R_IO_L])
+#define RSCAN0CFPTR11LL (RSCAN0.CFPTR11.UINT8[R_IO_LL])
+#define RSCAN0CFPTR11LH (RSCAN0.CFPTR11.UINT8[R_IO_LH])
+#define RSCAN0CFPTR11H (RSCAN0.CFPTR11.UINT16[R_IO_H])
+#define RSCAN0CFPTR11HL (RSCAN0.CFPTR11.UINT8[R_IO_HL])
+#define RSCAN0CFPTR11HH (RSCAN0.CFPTR11.UINT8[R_IO_HH])
+#define RSCAN0CFDF011 (RSCAN0.CFDF011.UINT32)
+#define RSCAN0CFDF011L (RSCAN0.CFDF011.UINT16[R_IO_L])
+#define RSCAN0CFDF011LL (RSCAN0.CFDF011.UINT8[R_IO_LL])
+#define RSCAN0CFDF011LH (RSCAN0.CFDF011.UINT8[R_IO_LH])
+#define RSCAN0CFDF011H (RSCAN0.CFDF011.UINT16[R_IO_H])
+#define RSCAN0CFDF011HL (RSCAN0.CFDF011.UINT8[R_IO_HL])
+#define RSCAN0CFDF011HH (RSCAN0.CFDF011.UINT8[R_IO_HH])
+#define RSCAN0CFDF111 (RSCAN0.CFDF111.UINT32)
+#define RSCAN0CFDF111L (RSCAN0.CFDF111.UINT16[R_IO_L])
+#define RSCAN0CFDF111LL (RSCAN0.CFDF111.UINT8[R_IO_LL])
+#define RSCAN0CFDF111LH (RSCAN0.CFDF111.UINT8[R_IO_LH])
+#define RSCAN0CFDF111H (RSCAN0.CFDF111.UINT16[R_IO_H])
+#define RSCAN0CFDF111HL (RSCAN0.CFDF111.UINT8[R_IO_HL])
+#define RSCAN0CFDF111HH (RSCAN0.CFDF111.UINT8[R_IO_HH])
+#define RSCAN0CFID12 (RSCAN0.CFID12.UINT32)
+#define RSCAN0CFID12L (RSCAN0.CFID12.UINT16[R_IO_L])
+#define RSCAN0CFID12LL (RSCAN0.CFID12.UINT8[R_IO_LL])
+#define RSCAN0CFID12LH (RSCAN0.CFID12.UINT8[R_IO_LH])
+#define RSCAN0CFID12H (RSCAN0.CFID12.UINT16[R_IO_H])
+#define RSCAN0CFID12HL (RSCAN0.CFID12.UINT8[R_IO_HL])
+#define RSCAN0CFID12HH (RSCAN0.CFID12.UINT8[R_IO_HH])
+#define RSCAN0CFPTR12 (RSCAN0.CFPTR12.UINT32)
+#define RSCAN0CFPTR12L (RSCAN0.CFPTR12.UINT16[R_IO_L])
+#define RSCAN0CFPTR12LL (RSCAN0.CFPTR12.UINT8[R_IO_LL])
+#define RSCAN0CFPTR12LH (RSCAN0.CFPTR12.UINT8[R_IO_LH])
+#define RSCAN0CFPTR12H (RSCAN0.CFPTR12.UINT16[R_IO_H])
+#define RSCAN0CFPTR12HL (RSCAN0.CFPTR12.UINT8[R_IO_HL])
+#define RSCAN0CFPTR12HH (RSCAN0.CFPTR12.UINT8[R_IO_HH])
+#define RSCAN0CFDF012 (RSCAN0.CFDF012.UINT32)
+#define RSCAN0CFDF012L (RSCAN0.CFDF012.UINT16[R_IO_L])
+#define RSCAN0CFDF012LL (RSCAN0.CFDF012.UINT8[R_IO_LL])
+#define RSCAN0CFDF012LH (RSCAN0.CFDF012.UINT8[R_IO_LH])
+#define RSCAN0CFDF012H (RSCAN0.CFDF012.UINT16[R_IO_H])
+#define RSCAN0CFDF012HL (RSCAN0.CFDF012.UINT8[R_IO_HL])
+#define RSCAN0CFDF012HH (RSCAN0.CFDF012.UINT8[R_IO_HH])
+#define RSCAN0CFDF112 (RSCAN0.CFDF112.UINT32)
+#define RSCAN0CFDF112L (RSCAN0.CFDF112.UINT16[R_IO_L])
+#define RSCAN0CFDF112LL (RSCAN0.CFDF112.UINT8[R_IO_LL])
+#define RSCAN0CFDF112LH (RSCAN0.CFDF112.UINT8[R_IO_LH])
+#define RSCAN0CFDF112H (RSCAN0.CFDF112.UINT16[R_IO_H])
+#define RSCAN0CFDF112HL (RSCAN0.CFDF112.UINT8[R_IO_HL])
+#define RSCAN0CFDF112HH (RSCAN0.CFDF112.UINT8[R_IO_HH])
+#define RSCAN0CFID13 (RSCAN0.CFID13.UINT32)
+#define RSCAN0CFID13L (RSCAN0.CFID13.UINT16[R_IO_L])
+#define RSCAN0CFID13LL (RSCAN0.CFID13.UINT8[R_IO_LL])
+#define RSCAN0CFID13LH (RSCAN0.CFID13.UINT8[R_IO_LH])
+#define RSCAN0CFID13H (RSCAN0.CFID13.UINT16[R_IO_H])
+#define RSCAN0CFID13HL (RSCAN0.CFID13.UINT8[R_IO_HL])
+#define RSCAN0CFID13HH (RSCAN0.CFID13.UINT8[R_IO_HH])
+#define RSCAN0CFPTR13 (RSCAN0.CFPTR13.UINT32)
+#define RSCAN0CFPTR13L (RSCAN0.CFPTR13.UINT16[R_IO_L])
+#define RSCAN0CFPTR13LL (RSCAN0.CFPTR13.UINT8[R_IO_LL])
+#define RSCAN0CFPTR13LH (RSCAN0.CFPTR13.UINT8[R_IO_LH])
+#define RSCAN0CFPTR13H (RSCAN0.CFPTR13.UINT16[R_IO_H])
+#define RSCAN0CFPTR13HL (RSCAN0.CFPTR13.UINT8[R_IO_HL])
+#define RSCAN0CFPTR13HH (RSCAN0.CFPTR13.UINT8[R_IO_HH])
+#define RSCAN0CFDF013 (RSCAN0.CFDF013.UINT32)
+#define RSCAN0CFDF013L (RSCAN0.CFDF013.UINT16[R_IO_L])
+#define RSCAN0CFDF013LL (RSCAN0.CFDF013.UINT8[R_IO_LL])
+#define RSCAN0CFDF013LH (RSCAN0.CFDF013.UINT8[R_IO_LH])
+#define RSCAN0CFDF013H (RSCAN0.CFDF013.UINT16[R_IO_H])
+#define RSCAN0CFDF013HL (RSCAN0.CFDF013.UINT8[R_IO_HL])
+#define RSCAN0CFDF013HH (RSCAN0.CFDF013.UINT8[R_IO_HH])
+#define RSCAN0CFDF113 (RSCAN0.CFDF113.UINT32)
+#define RSCAN0CFDF113L (RSCAN0.CFDF113.UINT16[R_IO_L])
+#define RSCAN0CFDF113LL (RSCAN0.CFDF113.UINT8[R_IO_LL])
+#define RSCAN0CFDF113LH (RSCAN0.CFDF113.UINT8[R_IO_LH])
+#define RSCAN0CFDF113H (RSCAN0.CFDF113.UINT16[R_IO_H])
+#define RSCAN0CFDF113HL (RSCAN0.CFDF113.UINT8[R_IO_HL])
+#define RSCAN0CFDF113HH (RSCAN0.CFDF113.UINT8[R_IO_HH])
+#define RSCAN0CFID14 (RSCAN0.CFID14.UINT32)
+#define RSCAN0CFID14L (RSCAN0.CFID14.UINT16[R_IO_L])
+#define RSCAN0CFID14LL (RSCAN0.CFID14.UINT8[R_IO_LL])
+#define RSCAN0CFID14LH (RSCAN0.CFID14.UINT8[R_IO_LH])
+#define RSCAN0CFID14H (RSCAN0.CFID14.UINT16[R_IO_H])
+#define RSCAN0CFID14HL (RSCAN0.CFID14.UINT8[R_IO_HL])
+#define RSCAN0CFID14HH (RSCAN0.CFID14.UINT8[R_IO_HH])
+#define RSCAN0CFPTR14 (RSCAN0.CFPTR14.UINT32)
+#define RSCAN0CFPTR14L (RSCAN0.CFPTR14.UINT16[R_IO_L])
+#define RSCAN0CFPTR14LL (RSCAN0.CFPTR14.UINT8[R_IO_LL])
+#define RSCAN0CFPTR14LH (RSCAN0.CFPTR14.UINT8[R_IO_LH])
+#define RSCAN0CFPTR14H (RSCAN0.CFPTR14.UINT16[R_IO_H])
+#define RSCAN0CFPTR14HL (RSCAN0.CFPTR14.UINT8[R_IO_HL])
+#define RSCAN0CFPTR14HH (RSCAN0.CFPTR14.UINT8[R_IO_HH])
+#define RSCAN0CFDF014 (RSCAN0.CFDF014.UINT32)
+#define RSCAN0CFDF014L (RSCAN0.CFDF014.UINT16[R_IO_L])
+#define RSCAN0CFDF014LL (RSCAN0.CFDF014.UINT8[R_IO_LL])
+#define RSCAN0CFDF014LH (RSCAN0.CFDF014.UINT8[R_IO_LH])
+#define RSCAN0CFDF014H (RSCAN0.CFDF014.UINT16[R_IO_H])
+#define RSCAN0CFDF014HL (RSCAN0.CFDF014.UINT8[R_IO_HL])
+#define RSCAN0CFDF014HH (RSCAN0.CFDF014.UINT8[R_IO_HH])
+#define RSCAN0CFDF114 (RSCAN0.CFDF114.UINT32)
+#define RSCAN0CFDF114L (RSCAN0.CFDF114.UINT16[R_IO_L])
+#define RSCAN0CFDF114LL (RSCAN0.CFDF114.UINT8[R_IO_LL])
+#define RSCAN0CFDF114LH (RSCAN0.CFDF114.UINT8[R_IO_LH])
+#define RSCAN0CFDF114H (RSCAN0.CFDF114.UINT16[R_IO_H])
+#define RSCAN0CFDF114HL (RSCAN0.CFDF114.UINT8[R_IO_HL])
+#define RSCAN0CFDF114HH (RSCAN0.CFDF114.UINT8[R_IO_HH])
+#define RSCAN0TMID0 (RSCAN0.TMID0.UINT32)
+#define RSCAN0TMID0L (RSCAN0.TMID0.UINT16[R_IO_L])
+#define RSCAN0TMID0LL (RSCAN0.TMID0.UINT8[R_IO_LL])
+#define RSCAN0TMID0LH (RSCAN0.TMID0.UINT8[R_IO_LH])
+#define RSCAN0TMID0H (RSCAN0.TMID0.UINT16[R_IO_H])
+#define RSCAN0TMID0HL (RSCAN0.TMID0.UINT8[R_IO_HL])
+#define RSCAN0TMID0HH (RSCAN0.TMID0.UINT8[R_IO_HH])
+#define RSCAN0TMPTR0 (RSCAN0.TMPTR0.UINT32)
+#define RSCAN0TMPTR0L (RSCAN0.TMPTR0.UINT16[R_IO_L])
+#define RSCAN0TMPTR0LL (RSCAN0.TMPTR0.UINT8[R_IO_LL])
+#define RSCAN0TMPTR0LH (RSCAN0.TMPTR0.UINT8[R_IO_LH])
+#define RSCAN0TMPTR0H (RSCAN0.TMPTR0.UINT16[R_IO_H])
+#define RSCAN0TMPTR0HL (RSCAN0.TMPTR0.UINT8[R_IO_HL])
+#define RSCAN0TMPTR0HH (RSCAN0.TMPTR0.UINT8[R_IO_HH])
+#define RSCAN0TMDF00 (RSCAN0.TMDF00.UINT32)
+#define RSCAN0TMDF00L (RSCAN0.TMDF00.UINT16[R_IO_L])
+#define RSCAN0TMDF00LL (RSCAN0.TMDF00.UINT8[R_IO_LL])
+#define RSCAN0TMDF00LH (RSCAN0.TMDF00.UINT8[R_IO_LH])
+#define RSCAN0TMDF00H (RSCAN0.TMDF00.UINT16[R_IO_H])
+#define RSCAN0TMDF00HL (RSCAN0.TMDF00.UINT8[R_IO_HL])
+#define RSCAN0TMDF00HH (RSCAN0.TMDF00.UINT8[R_IO_HH])
+#define RSCAN0TMDF10 (RSCAN0.TMDF10.UINT32)
+#define RSCAN0TMDF10L (RSCAN0.TMDF10.UINT16[R_IO_L])
+#define RSCAN0TMDF10LL (RSCAN0.TMDF10.UINT8[R_IO_LL])
+#define RSCAN0TMDF10LH (RSCAN0.TMDF10.UINT8[R_IO_LH])
+#define RSCAN0TMDF10H (RSCAN0.TMDF10.UINT16[R_IO_H])
+#define RSCAN0TMDF10HL (RSCAN0.TMDF10.UINT8[R_IO_HL])
+#define RSCAN0TMDF10HH (RSCAN0.TMDF10.UINT8[R_IO_HH])
+#define RSCAN0TMID1 (RSCAN0.TMID1.UINT32)
+#define RSCAN0TMID1L (RSCAN0.TMID1.UINT16[R_IO_L])
+#define RSCAN0TMID1LL (RSCAN0.TMID1.UINT8[R_IO_LL])
+#define RSCAN0TMID1LH (RSCAN0.TMID1.UINT8[R_IO_LH])
+#define RSCAN0TMID1H (RSCAN0.TMID1.UINT16[R_IO_H])
+#define RSCAN0TMID1HL (RSCAN0.TMID1.UINT8[R_IO_HL])
+#define RSCAN0TMID1HH (RSCAN0.TMID1.UINT8[R_IO_HH])
+#define RSCAN0TMPTR1 (RSCAN0.TMPTR1.UINT32)
+#define RSCAN0TMPTR1L (RSCAN0.TMPTR1.UINT16[R_IO_L])
+#define RSCAN0TMPTR1LL (RSCAN0.TMPTR1.UINT8[R_IO_LL])
+#define RSCAN0TMPTR1LH (RSCAN0.TMPTR1.UINT8[R_IO_LH])
+#define RSCAN0TMPTR1H (RSCAN0.TMPTR1.UINT16[R_IO_H])
+#define RSCAN0TMPTR1HL (RSCAN0.TMPTR1.UINT8[R_IO_HL])
+#define RSCAN0TMPTR1HH (RSCAN0.TMPTR1.UINT8[R_IO_HH])
+#define RSCAN0TMDF01 (RSCAN0.TMDF01.UINT32)
+#define RSCAN0TMDF01L (RSCAN0.TMDF01.UINT16[R_IO_L])
+#define RSCAN0TMDF01LL (RSCAN0.TMDF01.UINT8[R_IO_LL])
+#define RSCAN0TMDF01LH (RSCAN0.TMDF01.UINT8[R_IO_LH])
+#define RSCAN0TMDF01H (RSCAN0.TMDF01.UINT16[R_IO_H])
+#define RSCAN0TMDF01HL (RSCAN0.TMDF01.UINT8[R_IO_HL])
+#define RSCAN0TMDF01HH (RSCAN0.TMDF01.UINT8[R_IO_HH])
+#define RSCAN0TMDF11 (RSCAN0.TMDF11.UINT32)
+#define RSCAN0TMDF11L (RSCAN0.TMDF11.UINT16[R_IO_L])
+#define RSCAN0TMDF11LL (RSCAN0.TMDF11.UINT8[R_IO_LL])
+#define RSCAN0TMDF11LH (RSCAN0.TMDF11.UINT8[R_IO_LH])
+#define RSCAN0TMDF11H (RSCAN0.TMDF11.UINT16[R_IO_H])
+#define RSCAN0TMDF11HL (RSCAN0.TMDF11.UINT8[R_IO_HL])
+#define RSCAN0TMDF11HH (RSCAN0.TMDF11.UINT8[R_IO_HH])
+#define RSCAN0TMID2 (RSCAN0.TMID2.UINT32)
+#define RSCAN0TMID2L (RSCAN0.TMID2.UINT16[R_IO_L])
+#define RSCAN0TMID2LL (RSCAN0.TMID2.UINT8[R_IO_LL])
+#define RSCAN0TMID2LH (RSCAN0.TMID2.UINT8[R_IO_LH])
+#define RSCAN0TMID2H (RSCAN0.TMID2.UINT16[R_IO_H])
+#define RSCAN0TMID2HL (RSCAN0.TMID2.UINT8[R_IO_HL])
+#define RSCAN0TMID2HH (RSCAN0.TMID2.UINT8[R_IO_HH])
+#define RSCAN0TMPTR2 (RSCAN0.TMPTR2.UINT32)
+#define RSCAN0TMPTR2L (RSCAN0.TMPTR2.UINT16[R_IO_L])
+#define RSCAN0TMPTR2LL (RSCAN0.TMPTR2.UINT8[R_IO_LL])
+#define RSCAN0TMPTR2LH (RSCAN0.TMPTR2.UINT8[R_IO_LH])
+#define RSCAN0TMPTR2H (RSCAN0.TMPTR2.UINT16[R_IO_H])
+#define RSCAN0TMPTR2HL (RSCAN0.TMPTR2.UINT8[R_IO_HL])
+#define RSCAN0TMPTR2HH (RSCAN0.TMPTR2.UINT8[R_IO_HH])
+#define RSCAN0TMDF02 (RSCAN0.TMDF02.UINT32)
+#define RSCAN0TMDF02L (RSCAN0.TMDF02.UINT16[R_IO_L])
+#define RSCAN0TMDF02LL (RSCAN0.TMDF02.UINT8[R_IO_LL])
+#define RSCAN0TMDF02LH (RSCAN0.TMDF02.UINT8[R_IO_LH])
+#define RSCAN0TMDF02H (RSCAN0.TMDF02.UINT16[R_IO_H])
+#define RSCAN0TMDF02HL (RSCAN0.TMDF02.UINT8[R_IO_HL])
+#define RSCAN0TMDF02HH (RSCAN0.TMDF02.UINT8[R_IO_HH])
+#define RSCAN0TMDF12 (RSCAN0.TMDF12.UINT32)
+#define RSCAN0TMDF12L (RSCAN0.TMDF12.UINT16[R_IO_L])
+#define RSCAN0TMDF12LL (RSCAN0.TMDF12.UINT8[R_IO_LL])
+#define RSCAN0TMDF12LH (RSCAN0.TMDF12.UINT8[R_IO_LH])
+#define RSCAN0TMDF12H (RSCAN0.TMDF12.UINT16[R_IO_H])
+#define RSCAN0TMDF12HL (RSCAN0.TMDF12.UINT8[R_IO_HL])
+#define RSCAN0TMDF12HH (RSCAN0.TMDF12.UINT8[R_IO_HH])
+#define RSCAN0TMID3 (RSCAN0.TMID3.UINT32)
+#define RSCAN0TMID3L (RSCAN0.TMID3.UINT16[R_IO_L])
+#define RSCAN0TMID3LL (RSCAN0.TMID3.UINT8[R_IO_LL])
+#define RSCAN0TMID3LH (RSCAN0.TMID3.UINT8[R_IO_LH])
+#define RSCAN0TMID3H (RSCAN0.TMID3.UINT16[R_IO_H])
+#define RSCAN0TMID3HL (RSCAN0.TMID3.UINT8[R_IO_HL])
+#define RSCAN0TMID3HH (RSCAN0.TMID3.UINT8[R_IO_HH])
+#define RSCAN0TMPTR3 (RSCAN0.TMPTR3.UINT32)
+#define RSCAN0TMPTR3L (RSCAN0.TMPTR3.UINT16[R_IO_L])
+#define RSCAN0TMPTR3LL (RSCAN0.TMPTR3.UINT8[R_IO_LL])
+#define RSCAN0TMPTR3LH (RSCAN0.TMPTR3.UINT8[R_IO_LH])
+#define RSCAN0TMPTR3H (RSCAN0.TMPTR3.UINT16[R_IO_H])
+#define RSCAN0TMPTR3HL (RSCAN0.TMPTR3.UINT8[R_IO_HL])
+#define RSCAN0TMPTR3HH (RSCAN0.TMPTR3.UINT8[R_IO_HH])
+#define RSCAN0TMDF03 (RSCAN0.TMDF03.UINT32)
+#define RSCAN0TMDF03L (RSCAN0.TMDF03.UINT16[R_IO_L])
+#define RSCAN0TMDF03LL (RSCAN0.TMDF03.UINT8[R_IO_LL])
+#define RSCAN0TMDF03LH (RSCAN0.TMDF03.UINT8[R_IO_LH])
+#define RSCAN0TMDF03H (RSCAN0.TMDF03.UINT16[R_IO_H])
+#define RSCAN0TMDF03HL (RSCAN0.TMDF03.UINT8[R_IO_HL])
+#define RSCAN0TMDF03HH (RSCAN0.TMDF03.UINT8[R_IO_HH])
+#define RSCAN0TMDF13 (RSCAN0.TMDF13.UINT32)
+#define RSCAN0TMDF13L (RSCAN0.TMDF13.UINT16[R_IO_L])
+#define RSCAN0TMDF13LL (RSCAN0.TMDF13.UINT8[R_IO_LL])
+#define RSCAN0TMDF13LH (RSCAN0.TMDF13.UINT8[R_IO_LH])
+#define RSCAN0TMDF13H (RSCAN0.TMDF13.UINT16[R_IO_H])
+#define RSCAN0TMDF13HL (RSCAN0.TMDF13.UINT8[R_IO_HL])
+#define RSCAN0TMDF13HH (RSCAN0.TMDF13.UINT8[R_IO_HH])
+#define RSCAN0TMID4 (RSCAN0.TMID4.UINT32)
+#define RSCAN0TMID4L (RSCAN0.TMID4.UINT16[R_IO_L])
+#define RSCAN0TMID4LL (RSCAN0.TMID4.UINT8[R_IO_LL])
+#define RSCAN0TMID4LH (RSCAN0.TMID4.UINT8[R_IO_LH])
+#define RSCAN0TMID4H (RSCAN0.TMID4.UINT16[R_IO_H])
+#define RSCAN0TMID4HL (RSCAN0.TMID4.UINT8[R_IO_HL])
+#define RSCAN0TMID4HH (RSCAN0.TMID4.UINT8[R_IO_HH])
+#define RSCAN0TMPTR4 (RSCAN0.TMPTR4.UINT32)
+#define RSCAN0TMPTR4L (RSCAN0.TMPTR4.UINT16[R_IO_L])
+#define RSCAN0TMPTR4LL (RSCAN0.TMPTR4.UINT8[R_IO_LL])
+#define RSCAN0TMPTR4LH (RSCAN0.TMPTR4.UINT8[R_IO_LH])
+#define RSCAN0TMPTR4H (RSCAN0.TMPTR4.UINT16[R_IO_H])
+#define RSCAN0TMPTR4HL (RSCAN0.TMPTR4.UINT8[R_IO_HL])
+#define RSCAN0TMPTR4HH (RSCAN0.TMPTR4.UINT8[R_IO_HH])
+#define RSCAN0TMDF04 (RSCAN0.TMDF04.UINT32)
+#define RSCAN0TMDF04L (RSCAN0.TMDF04.UINT16[R_IO_L])
+#define RSCAN0TMDF04LL (RSCAN0.TMDF04.UINT8[R_IO_LL])
+#define RSCAN0TMDF04LH (RSCAN0.TMDF04.UINT8[R_IO_LH])
+#define RSCAN0TMDF04H (RSCAN0.TMDF04.UINT16[R_IO_H])
+#define RSCAN0TMDF04HL (RSCAN0.TMDF04.UINT8[R_IO_HL])
+#define RSCAN0TMDF04HH (RSCAN0.TMDF04.UINT8[R_IO_HH])
+#define RSCAN0TMDF14 (RSCAN0.TMDF14.UINT32)
+#define RSCAN0TMDF14L (RSCAN0.TMDF14.UINT16[R_IO_L])
+#define RSCAN0TMDF14LL (RSCAN0.TMDF14.UINT8[R_IO_LL])
+#define RSCAN0TMDF14LH (RSCAN0.TMDF14.UINT8[R_IO_LH])
+#define RSCAN0TMDF14H (RSCAN0.TMDF14.UINT16[R_IO_H])
+#define RSCAN0TMDF14HL (RSCAN0.TMDF14.UINT8[R_IO_HL])
+#define RSCAN0TMDF14HH (RSCAN0.TMDF14.UINT8[R_IO_HH])
+#define RSCAN0TMID5 (RSCAN0.TMID5.UINT32)
+#define RSCAN0TMID5L (RSCAN0.TMID5.UINT16[R_IO_L])
+#define RSCAN0TMID5LL (RSCAN0.TMID5.UINT8[R_IO_LL])
+#define RSCAN0TMID5LH (RSCAN0.TMID5.UINT8[R_IO_LH])
+#define RSCAN0TMID5H (RSCAN0.TMID5.UINT16[R_IO_H])
+#define RSCAN0TMID5HL (RSCAN0.TMID5.UINT8[R_IO_HL])
+#define RSCAN0TMID5HH (RSCAN0.TMID5.UINT8[R_IO_HH])
+#define RSCAN0TMPTR5 (RSCAN0.TMPTR5.UINT32)
+#define RSCAN0TMPTR5L (RSCAN0.TMPTR5.UINT16[R_IO_L])
+#define RSCAN0TMPTR5LL (RSCAN0.TMPTR5.UINT8[R_IO_LL])
+#define RSCAN0TMPTR5LH (RSCAN0.TMPTR5.UINT8[R_IO_LH])
+#define RSCAN0TMPTR5H (RSCAN0.TMPTR5.UINT16[R_IO_H])
+#define RSCAN0TMPTR5HL (RSCAN0.TMPTR5.UINT8[R_IO_HL])
+#define RSCAN0TMPTR5HH (RSCAN0.TMPTR5.UINT8[R_IO_HH])
+#define RSCAN0TMDF05 (RSCAN0.TMDF05.UINT32)
+#define RSCAN0TMDF05L (RSCAN0.TMDF05.UINT16[R_IO_L])
+#define RSCAN0TMDF05LL (RSCAN0.TMDF05.UINT8[R_IO_LL])
+#define RSCAN0TMDF05LH (RSCAN0.TMDF05.UINT8[R_IO_LH])
+#define RSCAN0TMDF05H (RSCAN0.TMDF05.UINT16[R_IO_H])
+#define RSCAN0TMDF05HL (RSCAN0.TMDF05.UINT8[R_IO_HL])
+#define RSCAN0TMDF05HH (RSCAN0.TMDF05.UINT8[R_IO_HH])
+#define RSCAN0TMDF15 (RSCAN0.TMDF15.UINT32)
+#define RSCAN0TMDF15L (RSCAN0.TMDF15.UINT16[R_IO_L])
+#define RSCAN0TMDF15LL (RSCAN0.TMDF15.UINT8[R_IO_LL])
+#define RSCAN0TMDF15LH (RSCAN0.TMDF15.UINT8[R_IO_LH])
+#define RSCAN0TMDF15H (RSCAN0.TMDF15.UINT16[R_IO_H])
+#define RSCAN0TMDF15HL (RSCAN0.TMDF15.UINT8[R_IO_HL])
+#define RSCAN0TMDF15HH (RSCAN0.TMDF15.UINT8[R_IO_HH])
+#define RSCAN0TMID6 (RSCAN0.TMID6.UINT32)
+#define RSCAN0TMID6L (RSCAN0.TMID6.UINT16[R_IO_L])
+#define RSCAN0TMID6LL (RSCAN0.TMID6.UINT8[R_IO_LL])
+#define RSCAN0TMID6LH (RSCAN0.TMID6.UINT8[R_IO_LH])
+#define RSCAN0TMID6H (RSCAN0.TMID6.UINT16[R_IO_H])
+#define RSCAN0TMID6HL (RSCAN0.TMID6.UINT8[R_IO_HL])
+#define RSCAN0TMID6HH (RSCAN0.TMID6.UINT8[R_IO_HH])
+#define RSCAN0TMPTR6 (RSCAN0.TMPTR6.UINT32)
+#define RSCAN0TMPTR6L (RSCAN0.TMPTR6.UINT16[R_IO_L])
+#define RSCAN0TMPTR6LL (RSCAN0.TMPTR6.UINT8[R_IO_LL])
+#define RSCAN0TMPTR6LH (RSCAN0.TMPTR6.UINT8[R_IO_LH])
+#define RSCAN0TMPTR6H (RSCAN0.TMPTR6.UINT16[R_IO_H])
+#define RSCAN0TMPTR6HL (RSCAN0.TMPTR6.UINT8[R_IO_HL])
+#define RSCAN0TMPTR6HH (RSCAN0.TMPTR6.UINT8[R_IO_HH])
+#define RSCAN0TMDF06 (RSCAN0.TMDF06.UINT32)
+#define RSCAN0TMDF06L (RSCAN0.TMDF06.UINT16[R_IO_L])
+#define RSCAN0TMDF06LL (RSCAN0.TMDF06.UINT8[R_IO_LL])
+#define RSCAN0TMDF06LH (RSCAN0.TMDF06.UINT8[R_IO_LH])
+#define RSCAN0TMDF06H (RSCAN0.TMDF06.UINT16[R_IO_H])
+#define RSCAN0TMDF06HL (RSCAN0.TMDF06.UINT8[R_IO_HL])
+#define RSCAN0TMDF06HH (RSCAN0.TMDF06.UINT8[R_IO_HH])
+#define RSCAN0TMDF16 (RSCAN0.TMDF16.UINT32)
+#define RSCAN0TMDF16L (RSCAN0.TMDF16.UINT16[R_IO_L])
+#define RSCAN0TMDF16LL (RSCAN0.TMDF16.UINT8[R_IO_LL])
+#define RSCAN0TMDF16LH (RSCAN0.TMDF16.UINT8[R_IO_LH])
+#define RSCAN0TMDF16H (RSCAN0.TMDF16.UINT16[R_IO_H])
+#define RSCAN0TMDF16HL (RSCAN0.TMDF16.UINT8[R_IO_HL])
+#define RSCAN0TMDF16HH (RSCAN0.TMDF16.UINT8[R_IO_HH])
+#define RSCAN0TMID7 (RSCAN0.TMID7.UINT32)
+#define RSCAN0TMID7L (RSCAN0.TMID7.UINT16[R_IO_L])
+#define RSCAN0TMID7LL (RSCAN0.TMID7.UINT8[R_IO_LL])
+#define RSCAN0TMID7LH (RSCAN0.TMID7.UINT8[R_IO_LH])
+#define RSCAN0TMID7H (RSCAN0.TMID7.UINT16[R_IO_H])
+#define RSCAN0TMID7HL (RSCAN0.TMID7.UINT8[R_IO_HL])
+#define RSCAN0TMID7HH (RSCAN0.TMID7.UINT8[R_IO_HH])
+#define RSCAN0TMPTR7 (RSCAN0.TMPTR7.UINT32)
+#define RSCAN0TMPTR7L (RSCAN0.TMPTR7.UINT16[R_IO_L])
+#define RSCAN0TMPTR7LL (RSCAN0.TMPTR7.UINT8[R_IO_LL])
+#define RSCAN0TMPTR7LH (RSCAN0.TMPTR7.UINT8[R_IO_LH])
+#define RSCAN0TMPTR7H (RSCAN0.TMPTR7.UINT16[R_IO_H])
+#define RSCAN0TMPTR7HL (RSCAN0.TMPTR7.UINT8[R_IO_HL])
+#define RSCAN0TMPTR7HH (RSCAN0.TMPTR7.UINT8[R_IO_HH])
+#define RSCAN0TMDF07 (RSCAN0.TMDF07.UINT32)
+#define RSCAN0TMDF07L (RSCAN0.TMDF07.UINT16[R_IO_L])
+#define RSCAN0TMDF07LL (RSCAN0.TMDF07.UINT8[R_IO_LL])
+#define RSCAN0TMDF07LH (RSCAN0.TMDF07.UINT8[R_IO_LH])
+#define RSCAN0TMDF07H (RSCAN0.TMDF07.UINT16[R_IO_H])
+#define RSCAN0TMDF07HL (RSCAN0.TMDF07.UINT8[R_IO_HL])
+#define RSCAN0TMDF07HH (RSCAN0.TMDF07.UINT8[R_IO_HH])
+#define RSCAN0TMDF17 (RSCAN0.TMDF17.UINT32)
+#define RSCAN0TMDF17L (RSCAN0.TMDF17.UINT16[R_IO_L])
+#define RSCAN0TMDF17LL (RSCAN0.TMDF17.UINT8[R_IO_LL])
+#define RSCAN0TMDF17LH (RSCAN0.TMDF17.UINT8[R_IO_LH])
+#define RSCAN0TMDF17H (RSCAN0.TMDF17.UINT16[R_IO_H])
+#define RSCAN0TMDF17HL (RSCAN0.TMDF17.UINT8[R_IO_HL])
+#define RSCAN0TMDF17HH (RSCAN0.TMDF17.UINT8[R_IO_HH])
+#define RSCAN0TMID8 (RSCAN0.TMID8.UINT32)
+#define RSCAN0TMID8L (RSCAN0.TMID8.UINT16[R_IO_L])
+#define RSCAN0TMID8LL (RSCAN0.TMID8.UINT8[R_IO_LL])
+#define RSCAN0TMID8LH (RSCAN0.TMID8.UINT8[R_IO_LH])
+#define RSCAN0TMID8H (RSCAN0.TMID8.UINT16[R_IO_H])
+#define RSCAN0TMID8HL (RSCAN0.TMID8.UINT8[R_IO_HL])
+#define RSCAN0TMID8HH (RSCAN0.TMID8.UINT8[R_IO_HH])
+#define RSCAN0TMPTR8 (RSCAN0.TMPTR8.UINT32)
+#define RSCAN0TMPTR8L (RSCAN0.TMPTR8.UINT16[R_IO_L])
+#define RSCAN0TMPTR8LL (RSCAN0.TMPTR8.UINT8[R_IO_LL])
+#define RSCAN0TMPTR8LH (RSCAN0.TMPTR8.UINT8[R_IO_LH])
+#define RSCAN0TMPTR8H (RSCAN0.TMPTR8.UINT16[R_IO_H])
+#define RSCAN0TMPTR8HL (RSCAN0.TMPTR8.UINT8[R_IO_HL])
+#define RSCAN0TMPTR8HH (RSCAN0.TMPTR8.UINT8[R_IO_HH])
+#define RSCAN0TMDF08 (RSCAN0.TMDF08.UINT32)
+#define RSCAN0TMDF08L (RSCAN0.TMDF08.UINT16[R_IO_L])
+#define RSCAN0TMDF08LL (RSCAN0.TMDF08.UINT8[R_IO_LL])
+#define RSCAN0TMDF08LH (RSCAN0.TMDF08.UINT8[R_IO_LH])
+#define RSCAN0TMDF08H (RSCAN0.TMDF08.UINT16[R_IO_H])
+#define RSCAN0TMDF08HL (RSCAN0.TMDF08.UINT8[R_IO_HL])
+#define RSCAN0TMDF08HH (RSCAN0.TMDF08.UINT8[R_IO_HH])
+#define RSCAN0TMDF18 (RSCAN0.TMDF18.UINT32)
+#define RSCAN0TMDF18L (RSCAN0.TMDF18.UINT16[R_IO_L])
+#define RSCAN0TMDF18LL (RSCAN0.TMDF18.UINT8[R_IO_LL])
+#define RSCAN0TMDF18LH (RSCAN0.TMDF18.UINT8[R_IO_LH])
+#define RSCAN0TMDF18H (RSCAN0.TMDF18.UINT16[R_IO_H])
+#define RSCAN0TMDF18HL (RSCAN0.TMDF18.UINT8[R_IO_HL])
+#define RSCAN0TMDF18HH (RSCAN0.TMDF18.UINT8[R_IO_HH])
+#define RSCAN0TMID9 (RSCAN0.TMID9.UINT32)
+#define RSCAN0TMID9L (RSCAN0.TMID9.UINT16[R_IO_L])
+#define RSCAN0TMID9LL (RSCAN0.TMID9.UINT8[R_IO_LL])
+#define RSCAN0TMID9LH (RSCAN0.TMID9.UINT8[R_IO_LH])
+#define RSCAN0TMID9H (RSCAN0.TMID9.UINT16[R_IO_H])
+#define RSCAN0TMID9HL (RSCAN0.TMID9.UINT8[R_IO_HL])
+#define RSCAN0TMID9HH (RSCAN0.TMID9.UINT8[R_IO_HH])
+#define RSCAN0TMPTR9 (RSCAN0.TMPTR9.UINT32)
+#define RSCAN0TMPTR9L (RSCAN0.TMPTR9.UINT16[R_IO_L])
+#define RSCAN0TMPTR9LL (RSCAN0.TMPTR9.UINT8[R_IO_LL])
+#define RSCAN0TMPTR9LH (RSCAN0.TMPTR9.UINT8[R_IO_LH])
+#define RSCAN0TMPTR9H (RSCAN0.TMPTR9.UINT16[R_IO_H])
+#define RSCAN0TMPTR9HL (RSCAN0.TMPTR9.UINT8[R_IO_HL])
+#define RSCAN0TMPTR9HH (RSCAN0.TMPTR9.UINT8[R_IO_HH])
+#define RSCAN0TMDF09 (RSCAN0.TMDF09.UINT32)
+#define RSCAN0TMDF09L (RSCAN0.TMDF09.UINT16[R_IO_L])
+#define RSCAN0TMDF09LL (RSCAN0.TMDF09.UINT8[R_IO_LL])
+#define RSCAN0TMDF09LH (RSCAN0.TMDF09.UINT8[R_IO_LH])
+#define RSCAN0TMDF09H (RSCAN0.TMDF09.UINT16[R_IO_H])
+#define RSCAN0TMDF09HL (RSCAN0.TMDF09.UINT8[R_IO_HL])
+#define RSCAN0TMDF09HH (RSCAN0.TMDF09.UINT8[R_IO_HH])
+#define RSCAN0TMDF19 (RSCAN0.TMDF19.UINT32)
+#define RSCAN0TMDF19L (RSCAN0.TMDF19.UINT16[R_IO_L])
+#define RSCAN0TMDF19LL (RSCAN0.TMDF19.UINT8[R_IO_LL])
+#define RSCAN0TMDF19LH (RSCAN0.TMDF19.UINT8[R_IO_LH])
+#define RSCAN0TMDF19H (RSCAN0.TMDF19.UINT16[R_IO_H])
+#define RSCAN0TMDF19HL (RSCAN0.TMDF19.UINT8[R_IO_HL])
+#define RSCAN0TMDF19HH (RSCAN0.TMDF19.UINT8[R_IO_HH])
+#define RSCAN0TMID10 (RSCAN0.TMID10.UINT32)
+#define RSCAN0TMID10L (RSCAN0.TMID10.UINT16[R_IO_L])
+#define RSCAN0TMID10LL (RSCAN0.TMID10.UINT8[R_IO_LL])
+#define RSCAN0TMID10LH (RSCAN0.TMID10.UINT8[R_IO_LH])
+#define RSCAN0TMID10H (RSCAN0.TMID10.UINT16[R_IO_H])
+#define RSCAN0TMID10HL (RSCAN0.TMID10.UINT8[R_IO_HL])
+#define RSCAN0TMID10HH (RSCAN0.TMID10.UINT8[R_IO_HH])
+#define RSCAN0TMPTR10 (RSCAN0.TMPTR10.UINT32)
+#define RSCAN0TMPTR10L (RSCAN0.TMPTR10.UINT16[R_IO_L])
+#define RSCAN0TMPTR10LL (RSCAN0.TMPTR10.UINT8[R_IO_LL])
+#define RSCAN0TMPTR10LH (RSCAN0.TMPTR10.UINT8[R_IO_LH])
+#define RSCAN0TMPTR10H (RSCAN0.TMPTR10.UINT16[R_IO_H])
+#define RSCAN0TMPTR10HL (RSCAN0.TMPTR10.UINT8[R_IO_HL])
+#define RSCAN0TMPTR10HH (RSCAN0.TMPTR10.UINT8[R_IO_HH])
+#define RSCAN0TMDF010 (RSCAN0.TMDF010.UINT32)
+#define RSCAN0TMDF010L (RSCAN0.TMDF010.UINT16[R_IO_L])
+#define RSCAN0TMDF010LL (RSCAN0.TMDF010.UINT8[R_IO_LL])
+#define RSCAN0TMDF010LH (RSCAN0.TMDF010.UINT8[R_IO_LH])
+#define RSCAN0TMDF010H (RSCAN0.TMDF010.UINT16[R_IO_H])
+#define RSCAN0TMDF010HL (RSCAN0.TMDF010.UINT8[R_IO_HL])
+#define RSCAN0TMDF010HH (RSCAN0.TMDF010.UINT8[R_IO_HH])
+#define RSCAN0TMDF110 (RSCAN0.TMDF110.UINT32)
+#define RSCAN0TMDF110L (RSCAN0.TMDF110.UINT16[R_IO_L])
+#define RSCAN0TMDF110LL (RSCAN0.TMDF110.UINT8[R_IO_LL])
+#define RSCAN0TMDF110LH (RSCAN0.TMDF110.UINT8[R_IO_LH])
+#define RSCAN0TMDF110H (RSCAN0.TMDF110.UINT16[R_IO_H])
+#define RSCAN0TMDF110HL (RSCAN0.TMDF110.UINT8[R_IO_HL])
+#define RSCAN0TMDF110HH (RSCAN0.TMDF110.UINT8[R_IO_HH])
+#define RSCAN0TMID11 (RSCAN0.TMID11.UINT32)
+#define RSCAN0TMID11L (RSCAN0.TMID11.UINT16[R_IO_L])
+#define RSCAN0TMID11LL (RSCAN0.TMID11.UINT8[R_IO_LL])
+#define RSCAN0TMID11LH (RSCAN0.TMID11.UINT8[R_IO_LH])
+#define RSCAN0TMID11H (RSCAN0.TMID11.UINT16[R_IO_H])
+#define RSCAN0TMID11HL (RSCAN0.TMID11.UINT8[R_IO_HL])
+#define RSCAN0TMID11HH (RSCAN0.TMID11.UINT8[R_IO_HH])
+#define RSCAN0TMPTR11 (RSCAN0.TMPTR11.UINT32)
+#define RSCAN0TMPTR11L (RSCAN0.TMPTR11.UINT16[R_IO_L])
+#define RSCAN0TMPTR11LL (RSCAN0.TMPTR11.UINT8[R_IO_LL])
+#define RSCAN0TMPTR11LH (RSCAN0.TMPTR11.UINT8[R_IO_LH])
+#define RSCAN0TMPTR11H (RSCAN0.TMPTR11.UINT16[R_IO_H])
+#define RSCAN0TMPTR11HL (RSCAN0.TMPTR11.UINT8[R_IO_HL])
+#define RSCAN0TMPTR11HH (RSCAN0.TMPTR11.UINT8[R_IO_HH])
+#define RSCAN0TMDF011 (RSCAN0.TMDF011.UINT32)
+#define RSCAN0TMDF011L (RSCAN0.TMDF011.UINT16[R_IO_L])
+#define RSCAN0TMDF011LL (RSCAN0.TMDF011.UINT8[R_IO_LL])
+#define RSCAN0TMDF011LH (RSCAN0.TMDF011.UINT8[R_IO_LH])
+#define RSCAN0TMDF011H (RSCAN0.TMDF011.UINT16[R_IO_H])
+#define RSCAN0TMDF011HL (RSCAN0.TMDF011.UINT8[R_IO_HL])
+#define RSCAN0TMDF011HH (RSCAN0.TMDF011.UINT8[R_IO_HH])
+#define RSCAN0TMDF111 (RSCAN0.TMDF111.UINT32)
+#define RSCAN0TMDF111L (RSCAN0.TMDF111.UINT16[R_IO_L])
+#define RSCAN0TMDF111LL (RSCAN0.TMDF111.UINT8[R_IO_LL])
+#define RSCAN0TMDF111LH (RSCAN0.TMDF111.UINT8[R_IO_LH])
+#define RSCAN0TMDF111H (RSCAN0.TMDF111.UINT16[R_IO_H])
+#define RSCAN0TMDF111HL (RSCAN0.TMDF111.UINT8[R_IO_HL])
+#define RSCAN0TMDF111HH (RSCAN0.TMDF111.UINT8[R_IO_HH])
+#define RSCAN0TMID12 (RSCAN0.TMID12.UINT32)
+#define RSCAN0TMID12L (RSCAN0.TMID12.UINT16[R_IO_L])
+#define RSCAN0TMID12LL (RSCAN0.TMID12.UINT8[R_IO_LL])
+#define RSCAN0TMID12LH (RSCAN0.TMID12.UINT8[R_IO_LH])
+#define RSCAN0TMID12H (RSCAN0.TMID12.UINT16[R_IO_H])
+#define RSCAN0TMID12HL (RSCAN0.TMID12.UINT8[R_IO_HL])
+#define RSCAN0TMID12HH (RSCAN0.TMID12.UINT8[R_IO_HH])
+#define RSCAN0TMPTR12 (RSCAN0.TMPTR12.UINT32)
+#define RSCAN0TMPTR12L (RSCAN0.TMPTR12.UINT16[R_IO_L])
+#define RSCAN0TMPTR12LL (RSCAN0.TMPTR12.UINT8[R_IO_LL])
+#define RSCAN0TMPTR12LH (RSCAN0.TMPTR12.UINT8[R_IO_LH])
+#define RSCAN0TMPTR12H (RSCAN0.TMPTR12.UINT16[R_IO_H])
+#define RSCAN0TMPTR12HL (RSCAN0.TMPTR12.UINT8[R_IO_HL])
+#define RSCAN0TMPTR12HH (RSCAN0.TMPTR12.UINT8[R_IO_HH])
+#define RSCAN0TMDF012 (RSCAN0.TMDF012.UINT32)
+#define RSCAN0TMDF012L (RSCAN0.TMDF012.UINT16[R_IO_L])
+#define RSCAN0TMDF012LL (RSCAN0.TMDF012.UINT8[R_IO_LL])
+#define RSCAN0TMDF012LH (RSCAN0.TMDF012.UINT8[R_IO_LH])
+#define RSCAN0TMDF012H (RSCAN0.TMDF012.UINT16[R_IO_H])
+#define RSCAN0TMDF012HL (RSCAN0.TMDF012.UINT8[R_IO_HL])
+#define RSCAN0TMDF012HH (RSCAN0.TMDF012.UINT8[R_IO_HH])
+#define RSCAN0TMDF112 (RSCAN0.TMDF112.UINT32)
+#define RSCAN0TMDF112L (RSCAN0.TMDF112.UINT16[R_IO_L])
+#define RSCAN0TMDF112LL (RSCAN0.TMDF112.UINT8[R_IO_LL])
+#define RSCAN0TMDF112LH (RSCAN0.TMDF112.UINT8[R_IO_LH])
+#define RSCAN0TMDF112H (RSCAN0.TMDF112.UINT16[R_IO_H])
+#define RSCAN0TMDF112HL (RSCAN0.TMDF112.UINT8[R_IO_HL])
+#define RSCAN0TMDF112HH (RSCAN0.TMDF112.UINT8[R_IO_HH])
+#define RSCAN0TMID13 (RSCAN0.TMID13.UINT32)
+#define RSCAN0TMID13L (RSCAN0.TMID13.UINT16[R_IO_L])
+#define RSCAN0TMID13LL (RSCAN0.TMID13.UINT8[R_IO_LL])
+#define RSCAN0TMID13LH (RSCAN0.TMID13.UINT8[R_IO_LH])
+#define RSCAN0TMID13H (RSCAN0.TMID13.UINT16[R_IO_H])
+#define RSCAN0TMID13HL (RSCAN0.TMID13.UINT8[R_IO_HL])
+#define RSCAN0TMID13HH (RSCAN0.TMID13.UINT8[R_IO_HH])
+#define RSCAN0TMPTR13 (RSCAN0.TMPTR13.UINT32)
+#define RSCAN0TMPTR13L (RSCAN0.TMPTR13.UINT16[R_IO_L])
+#define RSCAN0TMPTR13LL (RSCAN0.TMPTR13.UINT8[R_IO_LL])
+#define RSCAN0TMPTR13LH (RSCAN0.TMPTR13.UINT8[R_IO_LH])
+#define RSCAN0TMPTR13H (RSCAN0.TMPTR13.UINT16[R_IO_H])
+#define RSCAN0TMPTR13HL (RSCAN0.TMPTR13.UINT8[R_IO_HL])
+#define RSCAN0TMPTR13HH (RSCAN0.TMPTR13.UINT8[R_IO_HH])
+#define RSCAN0TMDF013 (RSCAN0.TMDF013.UINT32)
+#define RSCAN0TMDF013L (RSCAN0.TMDF013.UINT16[R_IO_L])
+#define RSCAN0TMDF013LL (RSCAN0.TMDF013.UINT8[R_IO_LL])
+#define RSCAN0TMDF013LH (RSCAN0.TMDF013.UINT8[R_IO_LH])
+#define RSCAN0TMDF013H (RSCAN0.TMDF013.UINT16[R_IO_H])
+#define RSCAN0TMDF013HL (RSCAN0.TMDF013.UINT8[R_IO_HL])
+#define RSCAN0TMDF013HH (RSCAN0.TMDF013.UINT8[R_IO_HH])
+#define RSCAN0TMDF113 (RSCAN0.TMDF113.UINT32)
+#define RSCAN0TMDF113L (RSCAN0.TMDF113.UINT16[R_IO_L])
+#define RSCAN0TMDF113LL (RSCAN0.TMDF113.UINT8[R_IO_LL])
+#define RSCAN0TMDF113LH (RSCAN0.TMDF113.UINT8[R_IO_LH])
+#define RSCAN0TMDF113H (RSCAN0.TMDF113.UINT16[R_IO_H])
+#define RSCAN0TMDF113HL (RSCAN0.TMDF113.UINT8[R_IO_HL])
+#define RSCAN0TMDF113HH (RSCAN0.TMDF113.UINT8[R_IO_HH])
+#define RSCAN0TMID14 (RSCAN0.TMID14.UINT32)
+#define RSCAN0TMID14L (RSCAN0.TMID14.UINT16[R_IO_L])
+#define RSCAN0TMID14LL (RSCAN0.TMID14.UINT8[R_IO_LL])
+#define RSCAN0TMID14LH (RSCAN0.TMID14.UINT8[R_IO_LH])
+#define RSCAN0TMID14H (RSCAN0.TMID14.UINT16[R_IO_H])
+#define RSCAN0TMID14HL (RSCAN0.TMID14.UINT8[R_IO_HL])
+#define RSCAN0TMID14HH (RSCAN0.TMID14.UINT8[R_IO_HH])
+#define RSCAN0TMPTR14 (RSCAN0.TMPTR14.UINT32)
+#define RSCAN0TMPTR14L (RSCAN0.TMPTR14.UINT16[R_IO_L])
+#define RSCAN0TMPTR14LL (RSCAN0.TMPTR14.UINT8[R_IO_LL])
+#define RSCAN0TMPTR14LH (RSCAN0.TMPTR14.UINT8[R_IO_LH])
+#define RSCAN0TMPTR14H (RSCAN0.TMPTR14.UINT16[R_IO_H])
+#define RSCAN0TMPTR14HL (RSCAN0.TMPTR14.UINT8[R_IO_HL])
+#define RSCAN0TMPTR14HH (RSCAN0.TMPTR14.UINT8[R_IO_HH])
+#define RSCAN0TMDF014 (RSCAN0.TMDF014.UINT32)
+#define RSCAN0TMDF014L (RSCAN0.TMDF014.UINT16[R_IO_L])
+#define RSCAN0TMDF014LL (RSCAN0.TMDF014.UINT8[R_IO_LL])
+#define RSCAN0TMDF014LH (RSCAN0.TMDF014.UINT8[R_IO_LH])
+#define RSCAN0TMDF014H (RSCAN0.TMDF014.UINT16[R_IO_H])
+#define RSCAN0TMDF014HL (RSCAN0.TMDF014.UINT8[R_IO_HL])
+#define RSCAN0TMDF014HH (RSCAN0.TMDF014.UINT8[R_IO_HH])
+#define RSCAN0TMDF114 (RSCAN0.TMDF114.UINT32)
+#define RSCAN0TMDF114L (RSCAN0.TMDF114.UINT16[R_IO_L])
+#define RSCAN0TMDF114LL (RSCAN0.TMDF114.UINT8[R_IO_LL])
+#define RSCAN0TMDF114LH (RSCAN0.TMDF114.UINT8[R_IO_LH])
+#define RSCAN0TMDF114H (RSCAN0.TMDF114.UINT16[R_IO_H])
+#define RSCAN0TMDF114HL (RSCAN0.TMDF114.UINT8[R_IO_HL])
+#define RSCAN0TMDF114HH (RSCAN0.TMDF114.UINT8[R_IO_HH])
+#define RSCAN0TMID15 (RSCAN0.TMID15.UINT32)
+#define RSCAN0TMID15L (RSCAN0.TMID15.UINT16[R_IO_L])
+#define RSCAN0TMID15LL (RSCAN0.TMID15.UINT8[R_IO_LL])
+#define RSCAN0TMID15LH (RSCAN0.TMID15.UINT8[R_IO_LH])
+#define RSCAN0TMID15H (RSCAN0.TMID15.UINT16[R_IO_H])
+#define RSCAN0TMID15HL (RSCAN0.TMID15.UINT8[R_IO_HL])
+#define RSCAN0TMID15HH (RSCAN0.TMID15.UINT8[R_IO_HH])
+#define RSCAN0TMPTR15 (RSCAN0.TMPTR15.UINT32)
+#define RSCAN0TMPTR15L (RSCAN0.TMPTR15.UINT16[R_IO_L])
+#define RSCAN0TMPTR15LL (RSCAN0.TMPTR15.UINT8[R_IO_LL])
+#define RSCAN0TMPTR15LH (RSCAN0.TMPTR15.UINT8[R_IO_LH])
+#define RSCAN0TMPTR15H (RSCAN0.TMPTR15.UINT16[R_IO_H])
+#define RSCAN0TMPTR15HL (RSCAN0.TMPTR15.UINT8[R_IO_HL])
+#define RSCAN0TMPTR15HH (RSCAN0.TMPTR15.UINT8[R_IO_HH])
+#define RSCAN0TMDF015 (RSCAN0.TMDF015.UINT32)
+#define RSCAN0TMDF015L (RSCAN0.TMDF015.UINT16[R_IO_L])
+#define RSCAN0TMDF015LL (RSCAN0.TMDF015.UINT8[R_IO_LL])
+#define RSCAN0TMDF015LH (RSCAN0.TMDF015.UINT8[R_IO_LH])
+#define RSCAN0TMDF015H (RSCAN0.TMDF015.UINT16[R_IO_H])
+#define RSCAN0TMDF015HL (RSCAN0.TMDF015.UINT8[R_IO_HL])
+#define RSCAN0TMDF015HH (RSCAN0.TMDF015.UINT8[R_IO_HH])
+#define RSCAN0TMDF115 (RSCAN0.TMDF115.UINT32)
+#define RSCAN0TMDF115L (RSCAN0.TMDF115.UINT16[R_IO_L])
+#define RSCAN0TMDF115LL (RSCAN0.TMDF115.UINT8[R_IO_LL])
+#define RSCAN0TMDF115LH (RSCAN0.TMDF115.UINT8[R_IO_LH])
+#define RSCAN0TMDF115H (RSCAN0.TMDF115.UINT16[R_IO_H])
+#define RSCAN0TMDF115HL (RSCAN0.TMDF115.UINT8[R_IO_HL])
+#define RSCAN0TMDF115HH (RSCAN0.TMDF115.UINT8[R_IO_HH])
+#define RSCAN0TMID16 (RSCAN0.TMID16.UINT32)
+#define RSCAN0TMID16L (RSCAN0.TMID16.UINT16[R_IO_L])
+#define RSCAN0TMID16LL (RSCAN0.TMID16.UINT8[R_IO_LL])
+#define RSCAN0TMID16LH (RSCAN0.TMID16.UINT8[R_IO_LH])
+#define RSCAN0TMID16H (RSCAN0.TMID16.UINT16[R_IO_H])
+#define RSCAN0TMID16HL (RSCAN0.TMID16.UINT8[R_IO_HL])
+#define RSCAN0TMID16HH (RSCAN0.TMID16.UINT8[R_IO_HH])
+#define RSCAN0TMPTR16 (RSCAN0.TMPTR16.UINT32)
+#define RSCAN0TMPTR16L (RSCAN0.TMPTR16.UINT16[R_IO_L])
+#define RSCAN0TMPTR16LL (RSCAN0.TMPTR16.UINT8[R_IO_LL])
+#define RSCAN0TMPTR16LH (RSCAN0.TMPTR16.UINT8[R_IO_LH])
+#define RSCAN0TMPTR16H (RSCAN0.TMPTR16.UINT16[R_IO_H])
+#define RSCAN0TMPTR16HL (RSCAN0.TMPTR16.UINT8[R_IO_HL])
+#define RSCAN0TMPTR16HH (RSCAN0.TMPTR16.UINT8[R_IO_HH])
+#define RSCAN0TMDF016 (RSCAN0.TMDF016.UINT32)
+#define RSCAN0TMDF016L (RSCAN0.TMDF016.UINT16[R_IO_L])
+#define RSCAN0TMDF016LL (RSCAN0.TMDF016.UINT8[R_IO_LL])
+#define RSCAN0TMDF016LH (RSCAN0.TMDF016.UINT8[R_IO_LH])
+#define RSCAN0TMDF016H (RSCAN0.TMDF016.UINT16[R_IO_H])
+#define RSCAN0TMDF016HL (RSCAN0.TMDF016.UINT8[R_IO_HL])
+#define RSCAN0TMDF016HH (RSCAN0.TMDF016.UINT8[R_IO_HH])
+#define RSCAN0TMDF116 (RSCAN0.TMDF116.UINT32)
+#define RSCAN0TMDF116L (RSCAN0.TMDF116.UINT16[R_IO_L])
+#define RSCAN0TMDF116LL (RSCAN0.TMDF116.UINT8[R_IO_LL])
+#define RSCAN0TMDF116LH (RSCAN0.TMDF116.UINT8[R_IO_LH])
+#define RSCAN0TMDF116H (RSCAN0.TMDF116.UINT16[R_IO_H])
+#define RSCAN0TMDF116HL (RSCAN0.TMDF116.UINT8[R_IO_HL])
+#define RSCAN0TMDF116HH (RSCAN0.TMDF116.UINT8[R_IO_HH])
+#define RSCAN0TMID17 (RSCAN0.TMID17.UINT32)
+#define RSCAN0TMID17L (RSCAN0.TMID17.UINT16[R_IO_L])
+#define RSCAN0TMID17LL (RSCAN0.TMID17.UINT8[R_IO_LL])
+#define RSCAN0TMID17LH (RSCAN0.TMID17.UINT8[R_IO_LH])
+#define RSCAN0TMID17H (RSCAN0.TMID17.UINT16[R_IO_H])
+#define RSCAN0TMID17HL (RSCAN0.TMID17.UINT8[R_IO_HL])
+#define RSCAN0TMID17HH (RSCAN0.TMID17.UINT8[R_IO_HH])
+#define RSCAN0TMPTR17 (RSCAN0.TMPTR17.UINT32)
+#define RSCAN0TMPTR17L (RSCAN0.TMPTR17.UINT16[R_IO_L])
+#define RSCAN0TMPTR17LL (RSCAN0.TMPTR17.UINT8[R_IO_LL])
+#define RSCAN0TMPTR17LH (RSCAN0.TMPTR17.UINT8[R_IO_LH])
+#define RSCAN0TMPTR17H (RSCAN0.TMPTR17.UINT16[R_IO_H])
+#define RSCAN0TMPTR17HL (RSCAN0.TMPTR17.UINT8[R_IO_HL])
+#define RSCAN0TMPTR17HH (RSCAN0.TMPTR17.UINT8[R_IO_HH])
+#define RSCAN0TMDF017 (RSCAN0.TMDF017.UINT32)
+#define RSCAN0TMDF017L (RSCAN0.TMDF017.UINT16[R_IO_L])
+#define RSCAN0TMDF017LL (RSCAN0.TMDF017.UINT8[R_IO_LL])
+#define RSCAN0TMDF017LH (RSCAN0.TMDF017.UINT8[R_IO_LH])
+#define RSCAN0TMDF017H (RSCAN0.TMDF017.UINT16[R_IO_H])
+#define RSCAN0TMDF017HL (RSCAN0.TMDF017.UINT8[R_IO_HL])
+#define RSCAN0TMDF017HH (RSCAN0.TMDF017.UINT8[R_IO_HH])
+#define RSCAN0TMDF117 (RSCAN0.TMDF117.UINT32)
+#define RSCAN0TMDF117L (RSCAN0.TMDF117.UINT16[R_IO_L])
+#define RSCAN0TMDF117LL (RSCAN0.TMDF117.UINT8[R_IO_LL])
+#define RSCAN0TMDF117LH (RSCAN0.TMDF117.UINT8[R_IO_LH])
+#define RSCAN0TMDF117H (RSCAN0.TMDF117.UINT16[R_IO_H])
+#define RSCAN0TMDF117HL (RSCAN0.TMDF117.UINT8[R_IO_HL])
+#define RSCAN0TMDF117HH (RSCAN0.TMDF117.UINT8[R_IO_HH])
+#define RSCAN0TMID18 (RSCAN0.TMID18.UINT32)
+#define RSCAN0TMID18L (RSCAN0.TMID18.UINT16[R_IO_L])
+#define RSCAN0TMID18LL (RSCAN0.TMID18.UINT8[R_IO_LL])
+#define RSCAN0TMID18LH (RSCAN0.TMID18.UINT8[R_IO_LH])
+#define RSCAN0TMID18H (RSCAN0.TMID18.UINT16[R_IO_H])
+#define RSCAN0TMID18HL (RSCAN0.TMID18.UINT8[R_IO_HL])
+#define RSCAN0TMID18HH (RSCAN0.TMID18.UINT8[R_IO_HH])
+#define RSCAN0TMPTR18 (RSCAN0.TMPTR18.UINT32)
+#define RSCAN0TMPTR18L (RSCAN0.TMPTR18.UINT16[R_IO_L])
+#define RSCAN0TMPTR18LL (RSCAN0.TMPTR18.UINT8[R_IO_LL])
+#define RSCAN0TMPTR18LH (RSCAN0.TMPTR18.UINT8[R_IO_LH])
+#define RSCAN0TMPTR18H (RSCAN0.TMPTR18.UINT16[R_IO_H])
+#define RSCAN0TMPTR18HL (RSCAN0.TMPTR18.UINT8[R_IO_HL])
+#define RSCAN0TMPTR18HH (RSCAN0.TMPTR18.UINT8[R_IO_HH])
+#define RSCAN0TMDF018 (RSCAN0.TMDF018.UINT32)
+#define RSCAN0TMDF018L (RSCAN0.TMDF018.UINT16[R_IO_L])
+#define RSCAN0TMDF018LL (RSCAN0.TMDF018.UINT8[R_IO_LL])
+#define RSCAN0TMDF018LH (RSCAN0.TMDF018.UINT8[R_IO_LH])
+#define RSCAN0TMDF018H (RSCAN0.TMDF018.UINT16[R_IO_H])
+#define RSCAN0TMDF018HL (RSCAN0.TMDF018.UINT8[R_IO_HL])
+#define RSCAN0TMDF018HH (RSCAN0.TMDF018.UINT8[R_IO_HH])
+#define RSCAN0TMDF118 (RSCAN0.TMDF118.UINT32)
+#define RSCAN0TMDF118L (RSCAN0.TMDF118.UINT16[R_IO_L])
+#define RSCAN0TMDF118LL (RSCAN0.TMDF118.UINT8[R_IO_LL])
+#define RSCAN0TMDF118LH (RSCAN0.TMDF118.UINT8[R_IO_LH])
+#define RSCAN0TMDF118H (RSCAN0.TMDF118.UINT16[R_IO_H])
+#define RSCAN0TMDF118HL (RSCAN0.TMDF118.UINT8[R_IO_HL])
+#define RSCAN0TMDF118HH (RSCAN0.TMDF118.UINT8[R_IO_HH])
+#define RSCAN0TMID19 (RSCAN0.TMID19.UINT32)
+#define RSCAN0TMID19L (RSCAN0.TMID19.UINT16[R_IO_L])
+#define RSCAN0TMID19LL (RSCAN0.TMID19.UINT8[R_IO_LL])
+#define RSCAN0TMID19LH (RSCAN0.TMID19.UINT8[R_IO_LH])
+#define RSCAN0TMID19H (RSCAN0.TMID19.UINT16[R_IO_H])
+#define RSCAN0TMID19HL (RSCAN0.TMID19.UINT8[R_IO_HL])
+#define RSCAN0TMID19HH (RSCAN0.TMID19.UINT8[R_IO_HH])
+#define RSCAN0TMPTR19 (RSCAN0.TMPTR19.UINT32)
+#define RSCAN0TMPTR19L (RSCAN0.TMPTR19.UINT16[R_IO_L])
+#define RSCAN0TMPTR19LL (RSCAN0.TMPTR19.UINT8[R_IO_LL])
+#define RSCAN0TMPTR19LH (RSCAN0.TMPTR19.UINT8[R_IO_LH])
+#define RSCAN0TMPTR19H (RSCAN0.TMPTR19.UINT16[R_IO_H])
+#define RSCAN0TMPTR19HL (RSCAN0.TMPTR19.UINT8[R_IO_HL])
+#define RSCAN0TMPTR19HH (RSCAN0.TMPTR19.UINT8[R_IO_HH])
+#define RSCAN0TMDF019 (RSCAN0.TMDF019.UINT32)
+#define RSCAN0TMDF019L (RSCAN0.TMDF019.UINT16[R_IO_L])
+#define RSCAN0TMDF019LL (RSCAN0.TMDF019.UINT8[R_IO_LL])
+#define RSCAN0TMDF019LH (RSCAN0.TMDF019.UINT8[R_IO_LH])
+#define RSCAN0TMDF019H (RSCAN0.TMDF019.UINT16[R_IO_H])
+#define RSCAN0TMDF019HL (RSCAN0.TMDF019.UINT8[R_IO_HL])
+#define RSCAN0TMDF019HH (RSCAN0.TMDF019.UINT8[R_IO_HH])
+#define RSCAN0TMDF119 (RSCAN0.TMDF119.UINT32)
+#define RSCAN0TMDF119L (RSCAN0.TMDF119.UINT16[R_IO_L])
+#define RSCAN0TMDF119LL (RSCAN0.TMDF119.UINT8[R_IO_LL])
+#define RSCAN0TMDF119LH (RSCAN0.TMDF119.UINT8[R_IO_LH])
+#define RSCAN0TMDF119H (RSCAN0.TMDF119.UINT16[R_IO_H])
+#define RSCAN0TMDF119HL (RSCAN0.TMDF119.UINT8[R_IO_HL])
+#define RSCAN0TMDF119HH (RSCAN0.TMDF119.UINT8[R_IO_HH])
+#define RSCAN0TMID20 (RSCAN0.TMID20.UINT32)
+#define RSCAN0TMID20L (RSCAN0.TMID20.UINT16[R_IO_L])
+#define RSCAN0TMID20LL (RSCAN0.TMID20.UINT8[R_IO_LL])
+#define RSCAN0TMID20LH (RSCAN0.TMID20.UINT8[R_IO_LH])
+#define RSCAN0TMID20H (RSCAN0.TMID20.UINT16[R_IO_H])
+#define RSCAN0TMID20HL (RSCAN0.TMID20.UINT8[R_IO_HL])
+#define RSCAN0TMID20HH (RSCAN0.TMID20.UINT8[R_IO_HH])
+#define RSCAN0TMPTR20 (RSCAN0.TMPTR20.UINT32)
+#define RSCAN0TMPTR20L (RSCAN0.TMPTR20.UINT16[R_IO_L])
+#define RSCAN0TMPTR20LL (RSCAN0.TMPTR20.UINT8[R_IO_LL])
+#define RSCAN0TMPTR20LH (RSCAN0.TMPTR20.UINT8[R_IO_LH])
+#define RSCAN0TMPTR20H (RSCAN0.TMPTR20.UINT16[R_IO_H])
+#define RSCAN0TMPTR20HL (RSCAN0.TMPTR20.UINT8[R_IO_HL])
+#define RSCAN0TMPTR20HH (RSCAN0.TMPTR20.UINT8[R_IO_HH])
+#define RSCAN0TMDF020 (RSCAN0.TMDF020.UINT32)
+#define RSCAN0TMDF020L (RSCAN0.TMDF020.UINT16[R_IO_L])
+#define RSCAN0TMDF020LL (RSCAN0.TMDF020.UINT8[R_IO_LL])
+#define RSCAN0TMDF020LH (RSCAN0.TMDF020.UINT8[R_IO_LH])
+#define RSCAN0TMDF020H (RSCAN0.TMDF020.UINT16[R_IO_H])
+#define RSCAN0TMDF020HL (RSCAN0.TMDF020.UINT8[R_IO_HL])
+#define RSCAN0TMDF020HH (RSCAN0.TMDF020.UINT8[R_IO_HH])
+#define RSCAN0TMDF120 (RSCAN0.TMDF120.UINT32)
+#define RSCAN0TMDF120L (RSCAN0.TMDF120.UINT16[R_IO_L])
+#define RSCAN0TMDF120LL (RSCAN0.TMDF120.UINT8[R_IO_LL])
+#define RSCAN0TMDF120LH (RSCAN0.TMDF120.UINT8[R_IO_LH])
+#define RSCAN0TMDF120H (RSCAN0.TMDF120.UINT16[R_IO_H])
+#define RSCAN0TMDF120HL (RSCAN0.TMDF120.UINT8[R_IO_HL])
+#define RSCAN0TMDF120HH (RSCAN0.TMDF120.UINT8[R_IO_HH])
+#define RSCAN0TMID21 (RSCAN0.TMID21.UINT32)
+#define RSCAN0TMID21L (RSCAN0.TMID21.UINT16[R_IO_L])
+#define RSCAN0TMID21LL (RSCAN0.TMID21.UINT8[R_IO_LL])
+#define RSCAN0TMID21LH (RSCAN0.TMID21.UINT8[R_IO_LH])
+#define RSCAN0TMID21H (RSCAN0.TMID21.UINT16[R_IO_H])
+#define RSCAN0TMID21HL (RSCAN0.TMID21.UINT8[R_IO_HL])
+#define RSCAN0TMID21HH (RSCAN0.TMID21.UINT8[R_IO_HH])
+#define RSCAN0TMPTR21 (RSCAN0.TMPTR21.UINT32)
+#define RSCAN0TMPTR21L (RSCAN0.TMPTR21.UINT16[R_IO_L])
+#define RSCAN0TMPTR21LL (RSCAN0.TMPTR21.UINT8[R_IO_LL])
+#define RSCAN0TMPTR21LH (RSCAN0.TMPTR21.UINT8[R_IO_LH])
+#define RSCAN0TMPTR21H (RSCAN0.TMPTR21.UINT16[R_IO_H])
+#define RSCAN0TMPTR21HL (RSCAN0.TMPTR21.UINT8[R_IO_HL])
+#define RSCAN0TMPTR21HH (RSCAN0.TMPTR21.UINT8[R_IO_HH])
+#define RSCAN0TMDF021 (RSCAN0.TMDF021.UINT32)
+#define RSCAN0TMDF021L (RSCAN0.TMDF021.UINT16[R_IO_L])
+#define RSCAN0TMDF021LL (RSCAN0.TMDF021.UINT8[R_IO_LL])
+#define RSCAN0TMDF021LH (RSCAN0.TMDF021.UINT8[R_IO_LH])
+#define RSCAN0TMDF021H (RSCAN0.TMDF021.UINT16[R_IO_H])
+#define RSCAN0TMDF021HL (RSCAN0.TMDF021.UINT8[R_IO_HL])
+#define RSCAN0TMDF021HH (RSCAN0.TMDF021.UINT8[R_IO_HH])
+#define RSCAN0TMDF121 (RSCAN0.TMDF121.UINT32)
+#define RSCAN0TMDF121L (RSCAN0.TMDF121.UINT16[R_IO_L])
+#define RSCAN0TMDF121LL (RSCAN0.TMDF121.UINT8[R_IO_LL])
+#define RSCAN0TMDF121LH (RSCAN0.TMDF121.UINT8[R_IO_LH])
+#define RSCAN0TMDF121H (RSCAN0.TMDF121.UINT16[R_IO_H])
+#define RSCAN0TMDF121HL (RSCAN0.TMDF121.UINT8[R_IO_HL])
+#define RSCAN0TMDF121HH (RSCAN0.TMDF121.UINT8[R_IO_HH])
+#define RSCAN0TMID22 (RSCAN0.TMID22.UINT32)
+#define RSCAN0TMID22L (RSCAN0.TMID22.UINT16[R_IO_L])
+#define RSCAN0TMID22LL (RSCAN0.TMID22.UINT8[R_IO_LL])
+#define RSCAN0TMID22LH (RSCAN0.TMID22.UINT8[R_IO_LH])
+#define RSCAN0TMID22H (RSCAN0.TMID22.UINT16[R_IO_H])
+#define RSCAN0TMID22HL (RSCAN0.TMID22.UINT8[R_IO_HL])
+#define RSCAN0TMID22HH (RSCAN0.TMID22.UINT8[R_IO_HH])
+#define RSCAN0TMPTR22 (RSCAN0.TMPTR22.UINT32)
+#define RSCAN0TMPTR22L (RSCAN0.TMPTR22.UINT16[R_IO_L])
+#define RSCAN0TMPTR22LL (RSCAN0.TMPTR22.UINT8[R_IO_LL])
+#define RSCAN0TMPTR22LH (RSCAN0.TMPTR22.UINT8[R_IO_LH])
+#define RSCAN0TMPTR22H (RSCAN0.TMPTR22.UINT16[R_IO_H])
+#define RSCAN0TMPTR22HL (RSCAN0.TMPTR22.UINT8[R_IO_HL])
+#define RSCAN0TMPTR22HH (RSCAN0.TMPTR22.UINT8[R_IO_HH])
+#define RSCAN0TMDF022 (RSCAN0.TMDF022.UINT32)
+#define RSCAN0TMDF022L (RSCAN0.TMDF022.UINT16[R_IO_L])
+#define RSCAN0TMDF022LL (RSCAN0.TMDF022.UINT8[R_IO_LL])
+#define RSCAN0TMDF022LH (RSCAN0.TMDF022.UINT8[R_IO_LH])
+#define RSCAN0TMDF022H (RSCAN0.TMDF022.UINT16[R_IO_H])
+#define RSCAN0TMDF022HL (RSCAN0.TMDF022.UINT8[R_IO_HL])
+#define RSCAN0TMDF022HH (RSCAN0.TMDF022.UINT8[R_IO_HH])
+#define RSCAN0TMDF122 (RSCAN0.TMDF122.UINT32)
+#define RSCAN0TMDF122L (RSCAN0.TMDF122.UINT16[R_IO_L])
+#define RSCAN0TMDF122LL (RSCAN0.TMDF122.UINT8[R_IO_LL])
+#define RSCAN0TMDF122LH (RSCAN0.TMDF122.UINT8[R_IO_LH])
+#define RSCAN0TMDF122H (RSCAN0.TMDF122.UINT16[R_IO_H])
+#define RSCAN0TMDF122HL (RSCAN0.TMDF122.UINT8[R_IO_HL])
+#define RSCAN0TMDF122HH (RSCAN0.TMDF122.UINT8[R_IO_HH])
+#define RSCAN0TMID23 (RSCAN0.TMID23.UINT32)
+#define RSCAN0TMID23L (RSCAN0.TMID23.UINT16[R_IO_L])
+#define RSCAN0TMID23LL (RSCAN0.TMID23.UINT8[R_IO_LL])
+#define RSCAN0TMID23LH (RSCAN0.TMID23.UINT8[R_IO_LH])
+#define RSCAN0TMID23H (RSCAN0.TMID23.UINT16[R_IO_H])
+#define RSCAN0TMID23HL (RSCAN0.TMID23.UINT8[R_IO_HL])
+#define RSCAN0TMID23HH (RSCAN0.TMID23.UINT8[R_IO_HH])
+#define RSCAN0TMPTR23 (RSCAN0.TMPTR23.UINT32)
+#define RSCAN0TMPTR23L (RSCAN0.TMPTR23.UINT16[R_IO_L])
+#define RSCAN0TMPTR23LL (RSCAN0.TMPTR23.UINT8[R_IO_LL])
+#define RSCAN0TMPTR23LH (RSCAN0.TMPTR23.UINT8[R_IO_LH])
+#define RSCAN0TMPTR23H (RSCAN0.TMPTR23.UINT16[R_IO_H])
+#define RSCAN0TMPTR23HL (RSCAN0.TMPTR23.UINT8[R_IO_HL])
+#define RSCAN0TMPTR23HH (RSCAN0.TMPTR23.UINT8[R_IO_HH])
+#define RSCAN0TMDF023 (RSCAN0.TMDF023.UINT32)
+#define RSCAN0TMDF023L (RSCAN0.TMDF023.UINT16[R_IO_L])
+#define RSCAN0TMDF023LL (RSCAN0.TMDF023.UINT8[R_IO_LL])
+#define RSCAN0TMDF023LH (RSCAN0.TMDF023.UINT8[R_IO_LH])
+#define RSCAN0TMDF023H (RSCAN0.TMDF023.UINT16[R_IO_H])
+#define RSCAN0TMDF023HL (RSCAN0.TMDF023.UINT8[R_IO_HL])
+#define RSCAN0TMDF023HH (RSCAN0.TMDF023.UINT8[R_IO_HH])
+#define RSCAN0TMDF123 (RSCAN0.TMDF123.UINT32)
+#define RSCAN0TMDF123L (RSCAN0.TMDF123.UINT16[R_IO_L])
+#define RSCAN0TMDF123LL (RSCAN0.TMDF123.UINT8[R_IO_LL])
+#define RSCAN0TMDF123LH (RSCAN0.TMDF123.UINT8[R_IO_LH])
+#define RSCAN0TMDF123H (RSCAN0.TMDF123.UINT16[R_IO_H])
+#define RSCAN0TMDF123HL (RSCAN0.TMDF123.UINT8[R_IO_HL])
+#define RSCAN0TMDF123HH (RSCAN0.TMDF123.UINT8[R_IO_HH])
+#define RSCAN0TMID24 (RSCAN0.TMID24.UINT32)
+#define RSCAN0TMID24L (RSCAN0.TMID24.UINT16[R_IO_L])
+#define RSCAN0TMID24LL (RSCAN0.TMID24.UINT8[R_IO_LL])
+#define RSCAN0TMID24LH (RSCAN0.TMID24.UINT8[R_IO_LH])
+#define RSCAN0TMID24H (RSCAN0.TMID24.UINT16[R_IO_H])
+#define RSCAN0TMID24HL (RSCAN0.TMID24.UINT8[R_IO_HL])
+#define RSCAN0TMID24HH (RSCAN0.TMID24.UINT8[R_IO_HH])
+#define RSCAN0TMPTR24 (RSCAN0.TMPTR24.UINT32)
+#define RSCAN0TMPTR24L (RSCAN0.TMPTR24.UINT16[R_IO_L])
+#define RSCAN0TMPTR24LL (RSCAN0.TMPTR24.UINT8[R_IO_LL])
+#define RSCAN0TMPTR24LH (RSCAN0.TMPTR24.UINT8[R_IO_LH])
+#define RSCAN0TMPTR24H (RSCAN0.TMPTR24.UINT16[R_IO_H])
+#define RSCAN0TMPTR24HL (RSCAN0.TMPTR24.UINT8[R_IO_HL])
+#define RSCAN0TMPTR24HH (RSCAN0.TMPTR24.UINT8[R_IO_HH])
+#define RSCAN0TMDF024 (RSCAN0.TMDF024.UINT32)
+#define RSCAN0TMDF024L (RSCAN0.TMDF024.UINT16[R_IO_L])
+#define RSCAN0TMDF024LL (RSCAN0.TMDF024.UINT8[R_IO_LL])
+#define RSCAN0TMDF024LH (RSCAN0.TMDF024.UINT8[R_IO_LH])
+#define RSCAN0TMDF024H (RSCAN0.TMDF024.UINT16[R_IO_H])
+#define RSCAN0TMDF024HL (RSCAN0.TMDF024.UINT8[R_IO_HL])
+#define RSCAN0TMDF024HH (RSCAN0.TMDF024.UINT8[R_IO_HH])
+#define RSCAN0TMDF124 (RSCAN0.TMDF124.UINT32)
+#define RSCAN0TMDF124L (RSCAN0.TMDF124.UINT16[R_IO_L])
+#define RSCAN0TMDF124LL (RSCAN0.TMDF124.UINT8[R_IO_LL])
+#define RSCAN0TMDF124LH (RSCAN0.TMDF124.UINT8[R_IO_LH])
+#define RSCAN0TMDF124H (RSCAN0.TMDF124.UINT16[R_IO_H])
+#define RSCAN0TMDF124HL (RSCAN0.TMDF124.UINT8[R_IO_HL])
+#define RSCAN0TMDF124HH (RSCAN0.TMDF124.UINT8[R_IO_HH])
+#define RSCAN0TMID25 (RSCAN0.TMID25.UINT32)
+#define RSCAN0TMID25L (RSCAN0.TMID25.UINT16[R_IO_L])
+#define RSCAN0TMID25LL (RSCAN0.TMID25.UINT8[R_IO_LL])
+#define RSCAN0TMID25LH (RSCAN0.TMID25.UINT8[R_IO_LH])
+#define RSCAN0TMID25H (RSCAN0.TMID25.UINT16[R_IO_H])
+#define RSCAN0TMID25HL (RSCAN0.TMID25.UINT8[R_IO_HL])
+#define RSCAN0TMID25HH (RSCAN0.TMID25.UINT8[R_IO_HH])
+#define RSCAN0TMPTR25 (RSCAN0.TMPTR25.UINT32)
+#define RSCAN0TMPTR25L (RSCAN0.TMPTR25.UINT16[R_IO_L])
+#define RSCAN0TMPTR25LL (RSCAN0.TMPTR25.UINT8[R_IO_LL])
+#define RSCAN0TMPTR25LH (RSCAN0.TMPTR25.UINT8[R_IO_LH])
+#define RSCAN0TMPTR25H (RSCAN0.TMPTR25.UINT16[R_IO_H])
+#define RSCAN0TMPTR25HL (RSCAN0.TMPTR25.UINT8[R_IO_HL])
+#define RSCAN0TMPTR25HH (RSCAN0.TMPTR25.UINT8[R_IO_HH])
+#define RSCAN0TMDF025 (RSCAN0.TMDF025.UINT32)
+#define RSCAN0TMDF025L (RSCAN0.TMDF025.UINT16[R_IO_L])
+#define RSCAN0TMDF025LL (RSCAN0.TMDF025.UINT8[R_IO_LL])
+#define RSCAN0TMDF025LH (RSCAN0.TMDF025.UINT8[R_IO_LH])
+#define RSCAN0TMDF025H (RSCAN0.TMDF025.UINT16[R_IO_H])
+#define RSCAN0TMDF025HL (RSCAN0.TMDF025.UINT8[R_IO_HL])
+#define RSCAN0TMDF025HH (RSCAN0.TMDF025.UINT8[R_IO_HH])
+#define RSCAN0TMDF125 (RSCAN0.TMDF125.UINT32)
+#define RSCAN0TMDF125L (RSCAN0.TMDF125.UINT16[R_IO_L])
+#define RSCAN0TMDF125LL (RSCAN0.TMDF125.UINT8[R_IO_LL])
+#define RSCAN0TMDF125LH (RSCAN0.TMDF125.UINT8[R_IO_LH])
+#define RSCAN0TMDF125H (RSCAN0.TMDF125.UINT16[R_IO_H])
+#define RSCAN0TMDF125HL (RSCAN0.TMDF125.UINT8[R_IO_HL])
+#define RSCAN0TMDF125HH (RSCAN0.TMDF125.UINT8[R_IO_HH])
+#define RSCAN0TMID26 (RSCAN0.TMID26.UINT32)
+#define RSCAN0TMID26L (RSCAN0.TMID26.UINT16[R_IO_L])
+#define RSCAN0TMID26LL (RSCAN0.TMID26.UINT8[R_IO_LL])
+#define RSCAN0TMID26LH (RSCAN0.TMID26.UINT8[R_IO_LH])
+#define RSCAN0TMID26H (RSCAN0.TMID26.UINT16[R_IO_H])
+#define RSCAN0TMID26HL (RSCAN0.TMID26.UINT8[R_IO_HL])
+#define RSCAN0TMID26HH (RSCAN0.TMID26.UINT8[R_IO_HH])
+#define RSCAN0TMPTR26 (RSCAN0.TMPTR26.UINT32)
+#define RSCAN0TMPTR26L (RSCAN0.TMPTR26.UINT16[R_IO_L])
+#define RSCAN0TMPTR26LL (RSCAN0.TMPTR26.UINT8[R_IO_LL])
+#define RSCAN0TMPTR26LH (RSCAN0.TMPTR26.UINT8[R_IO_LH])
+#define RSCAN0TMPTR26H (RSCAN0.TMPTR26.UINT16[R_IO_H])
+#define RSCAN0TMPTR26HL (RSCAN0.TMPTR26.UINT8[R_IO_HL])
+#define RSCAN0TMPTR26HH (RSCAN0.TMPTR26.UINT8[R_IO_HH])
+#define RSCAN0TMDF026 (RSCAN0.TMDF026.UINT32)
+#define RSCAN0TMDF026L (RSCAN0.TMDF026.UINT16[R_IO_L])
+#define RSCAN0TMDF026LL (RSCAN0.TMDF026.UINT8[R_IO_LL])
+#define RSCAN0TMDF026LH (RSCAN0.TMDF026.UINT8[R_IO_LH])
+#define RSCAN0TMDF026H (RSCAN0.TMDF026.UINT16[R_IO_H])
+#define RSCAN0TMDF026HL (RSCAN0.TMDF026.UINT8[R_IO_HL])
+#define RSCAN0TMDF026HH (RSCAN0.TMDF026.UINT8[R_IO_HH])
+#define RSCAN0TMDF126 (RSCAN0.TMDF126.UINT32)
+#define RSCAN0TMDF126L (RSCAN0.TMDF126.UINT16[R_IO_L])
+#define RSCAN0TMDF126LL (RSCAN0.TMDF126.UINT8[R_IO_LL])
+#define RSCAN0TMDF126LH (RSCAN0.TMDF126.UINT8[R_IO_LH])
+#define RSCAN0TMDF126H (RSCAN0.TMDF126.UINT16[R_IO_H])
+#define RSCAN0TMDF126HL (RSCAN0.TMDF126.UINT8[R_IO_HL])
+#define RSCAN0TMDF126HH (RSCAN0.TMDF126.UINT8[R_IO_HH])
+#define RSCAN0TMID27 (RSCAN0.TMID27.UINT32)
+#define RSCAN0TMID27L (RSCAN0.TMID27.UINT16[R_IO_L])
+#define RSCAN0TMID27LL (RSCAN0.TMID27.UINT8[R_IO_LL])
+#define RSCAN0TMID27LH (RSCAN0.TMID27.UINT8[R_IO_LH])
+#define RSCAN0TMID27H (RSCAN0.TMID27.UINT16[R_IO_H])
+#define RSCAN0TMID27HL (RSCAN0.TMID27.UINT8[R_IO_HL])
+#define RSCAN0TMID27HH (RSCAN0.TMID27.UINT8[R_IO_HH])
+#define RSCAN0TMPTR27 (RSCAN0.TMPTR27.UINT32)
+#define RSCAN0TMPTR27L (RSCAN0.TMPTR27.UINT16[R_IO_L])
+#define RSCAN0TMPTR27LL (RSCAN0.TMPTR27.UINT8[R_IO_LL])
+#define RSCAN0TMPTR27LH (RSCAN0.TMPTR27.UINT8[R_IO_LH])
+#define RSCAN0TMPTR27H (RSCAN0.TMPTR27.UINT16[R_IO_H])
+#define RSCAN0TMPTR27HL (RSCAN0.TMPTR27.UINT8[R_IO_HL])
+#define RSCAN0TMPTR27HH (RSCAN0.TMPTR27.UINT8[R_IO_HH])
+#define RSCAN0TMDF027 (RSCAN0.TMDF027.UINT32)
+#define RSCAN0TMDF027L (RSCAN0.TMDF027.UINT16[R_IO_L])
+#define RSCAN0TMDF027LL (RSCAN0.TMDF027.UINT8[R_IO_LL])
+#define RSCAN0TMDF027LH (RSCAN0.TMDF027.UINT8[R_IO_LH])
+#define RSCAN0TMDF027H (RSCAN0.TMDF027.UINT16[R_IO_H])
+#define RSCAN0TMDF027HL (RSCAN0.TMDF027.UINT8[R_IO_HL])
+#define RSCAN0TMDF027HH (RSCAN0.TMDF027.UINT8[R_IO_HH])
+#define RSCAN0TMDF127 (RSCAN0.TMDF127.UINT32)
+#define RSCAN0TMDF127L (RSCAN0.TMDF127.UINT16[R_IO_L])
+#define RSCAN0TMDF127LL (RSCAN0.TMDF127.UINT8[R_IO_LL])
+#define RSCAN0TMDF127LH (RSCAN0.TMDF127.UINT8[R_IO_LH])
+#define RSCAN0TMDF127H (RSCAN0.TMDF127.UINT16[R_IO_H])
+#define RSCAN0TMDF127HL (RSCAN0.TMDF127.UINT8[R_IO_HL])
+#define RSCAN0TMDF127HH (RSCAN0.TMDF127.UINT8[R_IO_HH])
+#define RSCAN0TMID28 (RSCAN0.TMID28.UINT32)
+#define RSCAN0TMID28L (RSCAN0.TMID28.UINT16[R_IO_L])
+#define RSCAN0TMID28LL (RSCAN0.TMID28.UINT8[R_IO_LL])
+#define RSCAN0TMID28LH (RSCAN0.TMID28.UINT8[R_IO_LH])
+#define RSCAN0TMID28H (RSCAN0.TMID28.UINT16[R_IO_H])
+#define RSCAN0TMID28HL (RSCAN0.TMID28.UINT8[R_IO_HL])
+#define RSCAN0TMID28HH (RSCAN0.TMID28.UINT8[R_IO_HH])
+#define RSCAN0TMPTR28 (RSCAN0.TMPTR28.UINT32)
+#define RSCAN0TMPTR28L (RSCAN0.TMPTR28.UINT16[R_IO_L])
+#define RSCAN0TMPTR28LL (RSCAN0.TMPTR28.UINT8[R_IO_LL])
+#define RSCAN0TMPTR28LH (RSCAN0.TMPTR28.UINT8[R_IO_LH])
+#define RSCAN0TMPTR28H (RSCAN0.TMPTR28.UINT16[R_IO_H])
+#define RSCAN0TMPTR28HL (RSCAN0.TMPTR28.UINT8[R_IO_HL])
+#define RSCAN0TMPTR28HH (RSCAN0.TMPTR28.UINT8[R_IO_HH])
+#define RSCAN0TMDF028 (RSCAN0.TMDF028.UINT32)
+#define RSCAN0TMDF028L (RSCAN0.TMDF028.UINT16[R_IO_L])
+#define RSCAN0TMDF028LL (RSCAN0.TMDF028.UINT8[R_IO_LL])
+#define RSCAN0TMDF028LH (RSCAN0.TMDF028.UINT8[R_IO_LH])
+#define RSCAN0TMDF028H (RSCAN0.TMDF028.UINT16[R_IO_H])
+#define RSCAN0TMDF028HL (RSCAN0.TMDF028.UINT8[R_IO_HL])
+#define RSCAN0TMDF028HH (RSCAN0.TMDF028.UINT8[R_IO_HH])
+#define RSCAN0TMDF128 (RSCAN0.TMDF128.UINT32)
+#define RSCAN0TMDF128L (RSCAN0.TMDF128.UINT16[R_IO_L])
+#define RSCAN0TMDF128LL (RSCAN0.TMDF128.UINT8[R_IO_LL])
+#define RSCAN0TMDF128LH (RSCAN0.TMDF128.UINT8[R_IO_LH])
+#define RSCAN0TMDF128H (RSCAN0.TMDF128.UINT16[R_IO_H])
+#define RSCAN0TMDF128HL (RSCAN0.TMDF128.UINT8[R_IO_HL])
+#define RSCAN0TMDF128HH (RSCAN0.TMDF128.UINT8[R_IO_HH])
+#define RSCAN0TMID29 (RSCAN0.TMID29.UINT32)
+#define RSCAN0TMID29L (RSCAN0.TMID29.UINT16[R_IO_L])
+#define RSCAN0TMID29LL (RSCAN0.TMID29.UINT8[R_IO_LL])
+#define RSCAN0TMID29LH (RSCAN0.TMID29.UINT8[R_IO_LH])
+#define RSCAN0TMID29H (RSCAN0.TMID29.UINT16[R_IO_H])
+#define RSCAN0TMID29HL (RSCAN0.TMID29.UINT8[R_IO_HL])
+#define RSCAN0TMID29HH (RSCAN0.TMID29.UINT8[R_IO_HH])
+#define RSCAN0TMPTR29 (RSCAN0.TMPTR29.UINT32)
+#define RSCAN0TMPTR29L (RSCAN0.TMPTR29.UINT16[R_IO_L])
+#define RSCAN0TMPTR29LL (RSCAN0.TMPTR29.UINT8[R_IO_LL])
+#define RSCAN0TMPTR29LH (RSCAN0.TMPTR29.UINT8[R_IO_LH])
+#define RSCAN0TMPTR29H (RSCAN0.TMPTR29.UINT16[R_IO_H])
+#define RSCAN0TMPTR29HL (RSCAN0.TMPTR29.UINT8[R_IO_HL])
+#define RSCAN0TMPTR29HH (RSCAN0.TMPTR29.UINT8[R_IO_HH])
+#define RSCAN0TMDF029 (RSCAN0.TMDF029.UINT32)
+#define RSCAN0TMDF029L (RSCAN0.TMDF029.UINT16[R_IO_L])
+#define RSCAN0TMDF029LL (RSCAN0.TMDF029.UINT8[R_IO_LL])
+#define RSCAN0TMDF029LH (RSCAN0.TMDF029.UINT8[R_IO_LH])
+#define RSCAN0TMDF029H (RSCAN0.TMDF029.UINT16[R_IO_H])
+#define RSCAN0TMDF029HL (RSCAN0.TMDF029.UINT8[R_IO_HL])
+#define RSCAN0TMDF029HH (RSCAN0.TMDF029.UINT8[R_IO_HH])
+#define RSCAN0TMDF129 (RSCAN0.TMDF129.UINT32)
+#define RSCAN0TMDF129L (RSCAN0.TMDF129.UINT16[R_IO_L])
+#define RSCAN0TMDF129LL (RSCAN0.TMDF129.UINT8[R_IO_LL])
+#define RSCAN0TMDF129LH (RSCAN0.TMDF129.UINT8[R_IO_LH])
+#define RSCAN0TMDF129H (RSCAN0.TMDF129.UINT16[R_IO_H])
+#define RSCAN0TMDF129HL (RSCAN0.TMDF129.UINT8[R_IO_HL])
+#define RSCAN0TMDF129HH (RSCAN0.TMDF129.UINT8[R_IO_HH])
+#define RSCAN0TMID30 (RSCAN0.TMID30.UINT32)
+#define RSCAN0TMID30L (RSCAN0.TMID30.UINT16[R_IO_L])
+#define RSCAN0TMID30LL (RSCAN0.TMID30.UINT8[R_IO_LL])
+#define RSCAN0TMID30LH (RSCAN0.TMID30.UINT8[R_IO_LH])
+#define RSCAN0TMID30H (RSCAN0.TMID30.UINT16[R_IO_H])
+#define RSCAN0TMID30HL (RSCAN0.TMID30.UINT8[R_IO_HL])
+#define RSCAN0TMID30HH (RSCAN0.TMID30.UINT8[R_IO_HH])
+#define RSCAN0TMPTR30 (RSCAN0.TMPTR30.UINT32)
+#define RSCAN0TMPTR30L (RSCAN0.TMPTR30.UINT16[R_IO_L])
+#define RSCAN0TMPTR30LL (RSCAN0.TMPTR30.UINT8[R_IO_LL])
+#define RSCAN0TMPTR30LH (RSCAN0.TMPTR30.UINT8[R_IO_LH])
+#define RSCAN0TMPTR30H (RSCAN0.TMPTR30.UINT16[R_IO_H])
+#define RSCAN0TMPTR30HL (RSCAN0.TMPTR30.UINT8[R_IO_HL])
+#define RSCAN0TMPTR30HH (RSCAN0.TMPTR30.UINT8[R_IO_HH])
+#define RSCAN0TMDF030 (RSCAN0.TMDF030.UINT32)
+#define RSCAN0TMDF030L (RSCAN0.TMDF030.UINT16[R_IO_L])
+#define RSCAN0TMDF030LL (RSCAN0.TMDF030.UINT8[R_IO_LL])
+#define RSCAN0TMDF030LH (RSCAN0.TMDF030.UINT8[R_IO_LH])
+#define RSCAN0TMDF030H (RSCAN0.TMDF030.UINT16[R_IO_H])
+#define RSCAN0TMDF030HL (RSCAN0.TMDF030.UINT8[R_IO_HL])
+#define RSCAN0TMDF030HH (RSCAN0.TMDF030.UINT8[R_IO_HH])
+#define RSCAN0TMDF130 (RSCAN0.TMDF130.UINT32)
+#define RSCAN0TMDF130L (RSCAN0.TMDF130.UINT16[R_IO_L])
+#define RSCAN0TMDF130LL (RSCAN0.TMDF130.UINT8[R_IO_LL])
+#define RSCAN0TMDF130LH (RSCAN0.TMDF130.UINT8[R_IO_LH])
+#define RSCAN0TMDF130H (RSCAN0.TMDF130.UINT16[R_IO_H])
+#define RSCAN0TMDF130HL (RSCAN0.TMDF130.UINT8[R_IO_HL])
+#define RSCAN0TMDF130HH (RSCAN0.TMDF130.UINT8[R_IO_HH])
+#define RSCAN0TMID31 (RSCAN0.TMID31.UINT32)
+#define RSCAN0TMID31L (RSCAN0.TMID31.UINT16[R_IO_L])
+#define RSCAN0TMID31LL (RSCAN0.TMID31.UINT8[R_IO_LL])
+#define RSCAN0TMID31LH (RSCAN0.TMID31.UINT8[R_IO_LH])
+#define RSCAN0TMID31H (RSCAN0.TMID31.UINT16[R_IO_H])
+#define RSCAN0TMID31HL (RSCAN0.TMID31.UINT8[R_IO_HL])
+#define RSCAN0TMID31HH (RSCAN0.TMID31.UINT8[R_IO_HH])
+#define RSCAN0TMPTR31 (RSCAN0.TMPTR31.UINT32)
+#define RSCAN0TMPTR31L (RSCAN0.TMPTR31.UINT16[R_IO_L])
+#define RSCAN0TMPTR31LL (RSCAN0.TMPTR31.UINT8[R_IO_LL])
+#define RSCAN0TMPTR31LH (RSCAN0.TMPTR31.UINT8[R_IO_LH])
+#define RSCAN0TMPTR31H (RSCAN0.TMPTR31.UINT16[R_IO_H])
+#define RSCAN0TMPTR31HL (RSCAN0.TMPTR31.UINT8[R_IO_HL])
+#define RSCAN0TMPTR31HH (RSCAN0.TMPTR31.UINT8[R_IO_HH])
+#define RSCAN0TMDF031 (RSCAN0.TMDF031.UINT32)
+#define RSCAN0TMDF031L (RSCAN0.TMDF031.UINT16[R_IO_L])
+#define RSCAN0TMDF031LL (RSCAN0.TMDF031.UINT8[R_IO_LL])
+#define RSCAN0TMDF031LH (RSCAN0.TMDF031.UINT8[R_IO_LH])
+#define RSCAN0TMDF031H (RSCAN0.TMDF031.UINT16[R_IO_H])
+#define RSCAN0TMDF031HL (RSCAN0.TMDF031.UINT8[R_IO_HL])
+#define RSCAN0TMDF031HH (RSCAN0.TMDF031.UINT8[R_IO_HH])
+#define RSCAN0TMDF131 (RSCAN0.TMDF131.UINT32)
+#define RSCAN0TMDF131L (RSCAN0.TMDF131.UINT16[R_IO_L])
+#define RSCAN0TMDF131LL (RSCAN0.TMDF131.UINT8[R_IO_LL])
+#define RSCAN0TMDF131LH (RSCAN0.TMDF131.UINT8[R_IO_LH])
+#define RSCAN0TMDF131H (RSCAN0.TMDF131.UINT16[R_IO_H])
+#define RSCAN0TMDF131HL (RSCAN0.TMDF131.UINT8[R_IO_HL])
+#define RSCAN0TMDF131HH (RSCAN0.TMDF131.UINT8[R_IO_HH])
+#define RSCAN0TMID32 (RSCAN0.TMID32.UINT32)
+#define RSCAN0TMID32L (RSCAN0.TMID32.UINT16[R_IO_L])
+#define RSCAN0TMID32LL (RSCAN0.TMID32.UINT8[R_IO_LL])
+#define RSCAN0TMID32LH (RSCAN0.TMID32.UINT8[R_IO_LH])
+#define RSCAN0TMID32H (RSCAN0.TMID32.UINT16[R_IO_H])
+#define RSCAN0TMID32HL (RSCAN0.TMID32.UINT8[R_IO_HL])
+#define RSCAN0TMID32HH (RSCAN0.TMID32.UINT8[R_IO_HH])
+#define RSCAN0TMPTR32 (RSCAN0.TMPTR32.UINT32)
+#define RSCAN0TMPTR32L (RSCAN0.TMPTR32.UINT16[R_IO_L])
+#define RSCAN0TMPTR32LL (RSCAN0.TMPTR32.UINT8[R_IO_LL])
+#define RSCAN0TMPTR32LH (RSCAN0.TMPTR32.UINT8[R_IO_LH])
+#define RSCAN0TMPTR32H (RSCAN0.TMPTR32.UINT16[R_IO_H])
+#define RSCAN0TMPTR32HL (RSCAN0.TMPTR32.UINT8[R_IO_HL])
+#define RSCAN0TMPTR32HH (RSCAN0.TMPTR32.UINT8[R_IO_HH])
+#define RSCAN0TMDF032 (RSCAN0.TMDF032.UINT32)
+#define RSCAN0TMDF032L (RSCAN0.TMDF032.UINT16[R_IO_L])
+#define RSCAN0TMDF032LL (RSCAN0.TMDF032.UINT8[R_IO_LL])
+#define RSCAN0TMDF032LH (RSCAN0.TMDF032.UINT8[R_IO_LH])
+#define RSCAN0TMDF032H (RSCAN0.TMDF032.UINT16[R_IO_H])
+#define RSCAN0TMDF032HL (RSCAN0.TMDF032.UINT8[R_IO_HL])
+#define RSCAN0TMDF032HH (RSCAN0.TMDF032.UINT8[R_IO_HH])
+#define RSCAN0TMDF132 (RSCAN0.TMDF132.UINT32)
+#define RSCAN0TMDF132L (RSCAN0.TMDF132.UINT16[R_IO_L])
+#define RSCAN0TMDF132LL (RSCAN0.TMDF132.UINT8[R_IO_LL])
+#define RSCAN0TMDF132LH (RSCAN0.TMDF132.UINT8[R_IO_LH])
+#define RSCAN0TMDF132H (RSCAN0.TMDF132.UINT16[R_IO_H])
+#define RSCAN0TMDF132HL (RSCAN0.TMDF132.UINT8[R_IO_HL])
+#define RSCAN0TMDF132HH (RSCAN0.TMDF132.UINT8[R_IO_HH])
+#define RSCAN0TMID33 (RSCAN0.TMID33.UINT32)
+#define RSCAN0TMID33L (RSCAN0.TMID33.UINT16[R_IO_L])
+#define RSCAN0TMID33LL (RSCAN0.TMID33.UINT8[R_IO_LL])
+#define RSCAN0TMID33LH (RSCAN0.TMID33.UINT8[R_IO_LH])
+#define RSCAN0TMID33H (RSCAN0.TMID33.UINT16[R_IO_H])
+#define RSCAN0TMID33HL (RSCAN0.TMID33.UINT8[R_IO_HL])
+#define RSCAN0TMID33HH (RSCAN0.TMID33.UINT8[R_IO_HH])
+#define RSCAN0TMPTR33 (RSCAN0.TMPTR33.UINT32)
+#define RSCAN0TMPTR33L (RSCAN0.TMPTR33.UINT16[R_IO_L])
+#define RSCAN0TMPTR33LL (RSCAN0.TMPTR33.UINT8[R_IO_LL])
+#define RSCAN0TMPTR33LH (RSCAN0.TMPTR33.UINT8[R_IO_LH])
+#define RSCAN0TMPTR33H (RSCAN0.TMPTR33.UINT16[R_IO_H])
+#define RSCAN0TMPTR33HL (RSCAN0.TMPTR33.UINT8[R_IO_HL])
+#define RSCAN0TMPTR33HH (RSCAN0.TMPTR33.UINT8[R_IO_HH])
+#define RSCAN0TMDF033 (RSCAN0.TMDF033.UINT32)
+#define RSCAN0TMDF033L (RSCAN0.TMDF033.UINT16[R_IO_L])
+#define RSCAN0TMDF033LL (RSCAN0.TMDF033.UINT8[R_IO_LL])
+#define RSCAN0TMDF033LH (RSCAN0.TMDF033.UINT8[R_IO_LH])
+#define RSCAN0TMDF033H (RSCAN0.TMDF033.UINT16[R_IO_H])
+#define RSCAN0TMDF033HL (RSCAN0.TMDF033.UINT8[R_IO_HL])
+#define RSCAN0TMDF033HH (RSCAN0.TMDF033.UINT8[R_IO_HH])
+#define RSCAN0TMDF133 (RSCAN0.TMDF133.UINT32)
+#define RSCAN0TMDF133L (RSCAN0.TMDF133.UINT16[R_IO_L])
+#define RSCAN0TMDF133LL (RSCAN0.TMDF133.UINT8[R_IO_LL])
+#define RSCAN0TMDF133LH (RSCAN0.TMDF133.UINT8[R_IO_LH])
+#define RSCAN0TMDF133H (RSCAN0.TMDF133.UINT16[R_IO_H])
+#define RSCAN0TMDF133HL (RSCAN0.TMDF133.UINT8[R_IO_HL])
+#define RSCAN0TMDF133HH (RSCAN0.TMDF133.UINT8[R_IO_HH])
+#define RSCAN0TMID34 (RSCAN0.TMID34.UINT32)
+#define RSCAN0TMID34L (RSCAN0.TMID34.UINT16[R_IO_L])
+#define RSCAN0TMID34LL (RSCAN0.TMID34.UINT8[R_IO_LL])
+#define RSCAN0TMID34LH (RSCAN0.TMID34.UINT8[R_IO_LH])
+#define RSCAN0TMID34H (RSCAN0.TMID34.UINT16[R_IO_H])
+#define RSCAN0TMID34HL (RSCAN0.TMID34.UINT8[R_IO_HL])
+#define RSCAN0TMID34HH (RSCAN0.TMID34.UINT8[R_IO_HH])
+#define RSCAN0TMPTR34 (RSCAN0.TMPTR34.UINT32)
+#define RSCAN0TMPTR34L (RSCAN0.TMPTR34.UINT16[R_IO_L])
+#define RSCAN0TMPTR34LL (RSCAN0.TMPTR34.UINT8[R_IO_LL])
+#define RSCAN0TMPTR34LH (RSCAN0.TMPTR34.UINT8[R_IO_LH])
+#define RSCAN0TMPTR34H (RSCAN0.TMPTR34.UINT16[R_IO_H])
+#define RSCAN0TMPTR34HL (RSCAN0.TMPTR34.UINT8[R_IO_HL])
+#define RSCAN0TMPTR34HH (RSCAN0.TMPTR34.UINT8[R_IO_HH])
+#define RSCAN0TMDF034 (RSCAN0.TMDF034.UINT32)
+#define RSCAN0TMDF034L (RSCAN0.TMDF034.UINT16[R_IO_L])
+#define RSCAN0TMDF034LL (RSCAN0.TMDF034.UINT8[R_IO_LL])
+#define RSCAN0TMDF034LH (RSCAN0.TMDF034.UINT8[R_IO_LH])
+#define RSCAN0TMDF034H (RSCAN0.TMDF034.UINT16[R_IO_H])
+#define RSCAN0TMDF034HL (RSCAN0.TMDF034.UINT8[R_IO_HL])
+#define RSCAN0TMDF034HH (RSCAN0.TMDF034.UINT8[R_IO_HH])
+#define RSCAN0TMDF134 (RSCAN0.TMDF134.UINT32)
+#define RSCAN0TMDF134L (RSCAN0.TMDF134.UINT16[R_IO_L])
+#define RSCAN0TMDF134LL (RSCAN0.TMDF134.UINT8[R_IO_LL])
+#define RSCAN0TMDF134LH (RSCAN0.TMDF134.UINT8[R_IO_LH])
+#define RSCAN0TMDF134H (RSCAN0.TMDF134.UINT16[R_IO_H])
+#define RSCAN0TMDF134HL (RSCAN0.TMDF134.UINT8[R_IO_HL])
+#define RSCAN0TMDF134HH (RSCAN0.TMDF134.UINT8[R_IO_HH])
+#define RSCAN0TMID35 (RSCAN0.TMID35.UINT32)
+#define RSCAN0TMID35L (RSCAN0.TMID35.UINT16[R_IO_L])
+#define RSCAN0TMID35LL (RSCAN0.TMID35.UINT8[R_IO_LL])
+#define RSCAN0TMID35LH (RSCAN0.TMID35.UINT8[R_IO_LH])
+#define RSCAN0TMID35H (RSCAN0.TMID35.UINT16[R_IO_H])
+#define RSCAN0TMID35HL (RSCAN0.TMID35.UINT8[R_IO_HL])
+#define RSCAN0TMID35HH (RSCAN0.TMID35.UINT8[R_IO_HH])
+#define RSCAN0TMPTR35 (RSCAN0.TMPTR35.UINT32)
+#define RSCAN0TMPTR35L (RSCAN0.TMPTR35.UINT16[R_IO_L])
+#define RSCAN0TMPTR35LL (RSCAN0.TMPTR35.UINT8[R_IO_LL])
+#define RSCAN0TMPTR35LH (RSCAN0.TMPTR35.UINT8[R_IO_LH])
+#define RSCAN0TMPTR35H (RSCAN0.TMPTR35.UINT16[R_IO_H])
+#define RSCAN0TMPTR35HL (RSCAN0.TMPTR35.UINT8[R_IO_HL])
+#define RSCAN0TMPTR35HH (RSCAN0.TMPTR35.UINT8[R_IO_HH])
+#define RSCAN0TMDF035 (RSCAN0.TMDF035.UINT32)
+#define RSCAN0TMDF035L (RSCAN0.TMDF035.UINT16[R_IO_L])
+#define RSCAN0TMDF035LL (RSCAN0.TMDF035.UINT8[R_IO_LL])
+#define RSCAN0TMDF035LH (RSCAN0.TMDF035.UINT8[R_IO_LH])
+#define RSCAN0TMDF035H (RSCAN0.TMDF035.UINT16[R_IO_H])
+#define RSCAN0TMDF035HL (RSCAN0.TMDF035.UINT8[R_IO_HL])
+#define RSCAN0TMDF035HH (RSCAN0.TMDF035.UINT8[R_IO_HH])
+#define RSCAN0TMDF135 (RSCAN0.TMDF135.UINT32)
+#define RSCAN0TMDF135L (RSCAN0.TMDF135.UINT16[R_IO_L])
+#define RSCAN0TMDF135LL (RSCAN0.TMDF135.UINT8[R_IO_LL])
+#define RSCAN0TMDF135LH (RSCAN0.TMDF135.UINT8[R_IO_LH])
+#define RSCAN0TMDF135H (RSCAN0.TMDF135.UINT16[R_IO_H])
+#define RSCAN0TMDF135HL (RSCAN0.TMDF135.UINT8[R_IO_HL])
+#define RSCAN0TMDF135HH (RSCAN0.TMDF135.UINT8[R_IO_HH])
+#define RSCAN0TMID36 (RSCAN0.TMID36.UINT32)
+#define RSCAN0TMID36L (RSCAN0.TMID36.UINT16[R_IO_L])
+#define RSCAN0TMID36LL (RSCAN0.TMID36.UINT8[R_IO_LL])
+#define RSCAN0TMID36LH (RSCAN0.TMID36.UINT8[R_IO_LH])
+#define RSCAN0TMID36H (RSCAN0.TMID36.UINT16[R_IO_H])
+#define RSCAN0TMID36HL (RSCAN0.TMID36.UINT8[R_IO_HL])
+#define RSCAN0TMID36HH (RSCAN0.TMID36.UINT8[R_IO_HH])
+#define RSCAN0TMPTR36 (RSCAN0.TMPTR36.UINT32)
+#define RSCAN0TMPTR36L (RSCAN0.TMPTR36.UINT16[R_IO_L])
+#define RSCAN0TMPTR36LL (RSCAN0.TMPTR36.UINT8[R_IO_LL])
+#define RSCAN0TMPTR36LH (RSCAN0.TMPTR36.UINT8[R_IO_LH])
+#define RSCAN0TMPTR36H (RSCAN0.TMPTR36.UINT16[R_IO_H])
+#define RSCAN0TMPTR36HL (RSCAN0.TMPTR36.UINT8[R_IO_HL])
+#define RSCAN0TMPTR36HH (RSCAN0.TMPTR36.UINT8[R_IO_HH])
+#define RSCAN0TMDF036 (RSCAN0.TMDF036.UINT32)
+#define RSCAN0TMDF036L (RSCAN0.TMDF036.UINT16[R_IO_L])
+#define RSCAN0TMDF036LL (RSCAN0.TMDF036.UINT8[R_IO_LL])
+#define RSCAN0TMDF036LH (RSCAN0.TMDF036.UINT8[R_IO_LH])
+#define RSCAN0TMDF036H (RSCAN0.TMDF036.UINT16[R_IO_H])
+#define RSCAN0TMDF036HL (RSCAN0.TMDF036.UINT8[R_IO_HL])
+#define RSCAN0TMDF036HH (RSCAN0.TMDF036.UINT8[R_IO_HH])
+#define RSCAN0TMDF136 (RSCAN0.TMDF136.UINT32)
+#define RSCAN0TMDF136L (RSCAN0.TMDF136.UINT16[R_IO_L])
+#define RSCAN0TMDF136LL (RSCAN0.TMDF136.UINT8[R_IO_LL])
+#define RSCAN0TMDF136LH (RSCAN0.TMDF136.UINT8[R_IO_LH])
+#define RSCAN0TMDF136H (RSCAN0.TMDF136.UINT16[R_IO_H])
+#define RSCAN0TMDF136HL (RSCAN0.TMDF136.UINT8[R_IO_HL])
+#define RSCAN0TMDF136HH (RSCAN0.TMDF136.UINT8[R_IO_HH])
+#define RSCAN0TMID37 (RSCAN0.TMID37.UINT32)
+#define RSCAN0TMID37L (RSCAN0.TMID37.UINT16[R_IO_L])
+#define RSCAN0TMID37LL (RSCAN0.TMID37.UINT8[R_IO_LL])
+#define RSCAN0TMID37LH (RSCAN0.TMID37.UINT8[R_IO_LH])
+#define RSCAN0TMID37H (RSCAN0.TMID37.UINT16[R_IO_H])
+#define RSCAN0TMID37HL (RSCAN0.TMID37.UINT8[R_IO_HL])
+#define RSCAN0TMID37HH (RSCAN0.TMID37.UINT8[R_IO_HH])
+#define RSCAN0TMPTR37 (RSCAN0.TMPTR37.UINT32)
+#define RSCAN0TMPTR37L (RSCAN0.TMPTR37.UINT16[R_IO_L])
+#define RSCAN0TMPTR37LL (RSCAN0.TMPTR37.UINT8[R_IO_LL])
+#define RSCAN0TMPTR37LH (RSCAN0.TMPTR37.UINT8[R_IO_LH])
+#define RSCAN0TMPTR37H (RSCAN0.TMPTR37.UINT16[R_IO_H])
+#define RSCAN0TMPTR37HL (RSCAN0.TMPTR37.UINT8[R_IO_HL])
+#define RSCAN0TMPTR37HH (RSCAN0.TMPTR37.UINT8[R_IO_HH])
+#define RSCAN0TMDF037 (RSCAN0.TMDF037.UINT32)
+#define RSCAN0TMDF037L (RSCAN0.TMDF037.UINT16[R_IO_L])
+#define RSCAN0TMDF037LL (RSCAN0.TMDF037.UINT8[R_IO_LL])
+#define RSCAN0TMDF037LH (RSCAN0.TMDF037.UINT8[R_IO_LH])
+#define RSCAN0TMDF037H (RSCAN0.TMDF037.UINT16[R_IO_H])
+#define RSCAN0TMDF037HL (RSCAN0.TMDF037.UINT8[R_IO_HL])
+#define RSCAN0TMDF037HH (RSCAN0.TMDF037.UINT8[R_IO_HH])
+#define RSCAN0TMDF137 (RSCAN0.TMDF137.UINT32)
+#define RSCAN0TMDF137L (RSCAN0.TMDF137.UINT16[R_IO_L])
+#define RSCAN0TMDF137LL (RSCAN0.TMDF137.UINT8[R_IO_LL])
+#define RSCAN0TMDF137LH (RSCAN0.TMDF137.UINT8[R_IO_LH])
+#define RSCAN0TMDF137H (RSCAN0.TMDF137.UINT16[R_IO_H])
+#define RSCAN0TMDF137HL (RSCAN0.TMDF137.UINT8[R_IO_HL])
+#define RSCAN0TMDF137HH (RSCAN0.TMDF137.UINT8[R_IO_HH])
+#define RSCAN0TMID38 (RSCAN0.TMID38.UINT32)
+#define RSCAN0TMID38L (RSCAN0.TMID38.UINT16[R_IO_L])
+#define RSCAN0TMID38LL (RSCAN0.TMID38.UINT8[R_IO_LL])
+#define RSCAN0TMID38LH (RSCAN0.TMID38.UINT8[R_IO_LH])
+#define RSCAN0TMID38H (RSCAN0.TMID38.UINT16[R_IO_H])
+#define RSCAN0TMID38HL (RSCAN0.TMID38.UINT8[R_IO_HL])
+#define RSCAN0TMID38HH (RSCAN0.TMID38.UINT8[R_IO_HH])
+#define RSCAN0TMPTR38 (RSCAN0.TMPTR38.UINT32)
+#define RSCAN0TMPTR38L (RSCAN0.TMPTR38.UINT16[R_IO_L])
+#define RSCAN0TMPTR38LL (RSCAN0.TMPTR38.UINT8[R_IO_LL])
+#define RSCAN0TMPTR38LH (RSCAN0.TMPTR38.UINT8[R_IO_LH])
+#define RSCAN0TMPTR38H (RSCAN0.TMPTR38.UINT16[R_IO_H])
+#define RSCAN0TMPTR38HL (RSCAN0.TMPTR38.UINT8[R_IO_HL])
+#define RSCAN0TMPTR38HH (RSCAN0.TMPTR38.UINT8[R_IO_HH])
+#define RSCAN0TMDF038 (RSCAN0.TMDF038.UINT32)
+#define RSCAN0TMDF038L (RSCAN0.TMDF038.UINT16[R_IO_L])
+#define RSCAN0TMDF038LL (RSCAN0.TMDF038.UINT8[R_IO_LL])
+#define RSCAN0TMDF038LH (RSCAN0.TMDF038.UINT8[R_IO_LH])
+#define RSCAN0TMDF038H (RSCAN0.TMDF038.UINT16[R_IO_H])
+#define RSCAN0TMDF038HL (RSCAN0.TMDF038.UINT8[R_IO_HL])
+#define RSCAN0TMDF038HH (RSCAN0.TMDF038.UINT8[R_IO_HH])
+#define RSCAN0TMDF138 (RSCAN0.TMDF138.UINT32)
+#define RSCAN0TMDF138L (RSCAN0.TMDF138.UINT16[R_IO_L])
+#define RSCAN0TMDF138LL (RSCAN0.TMDF138.UINT8[R_IO_LL])
+#define RSCAN0TMDF138LH (RSCAN0.TMDF138.UINT8[R_IO_LH])
+#define RSCAN0TMDF138H (RSCAN0.TMDF138.UINT16[R_IO_H])
+#define RSCAN0TMDF138HL (RSCAN0.TMDF138.UINT8[R_IO_HL])
+#define RSCAN0TMDF138HH (RSCAN0.TMDF138.UINT8[R_IO_HH])
+#define RSCAN0TMID39 (RSCAN0.TMID39.UINT32)
+#define RSCAN0TMID39L (RSCAN0.TMID39.UINT16[R_IO_L])
+#define RSCAN0TMID39LL (RSCAN0.TMID39.UINT8[R_IO_LL])
+#define RSCAN0TMID39LH (RSCAN0.TMID39.UINT8[R_IO_LH])
+#define RSCAN0TMID39H (RSCAN0.TMID39.UINT16[R_IO_H])
+#define RSCAN0TMID39HL (RSCAN0.TMID39.UINT8[R_IO_HL])
+#define RSCAN0TMID39HH (RSCAN0.TMID39.UINT8[R_IO_HH])
+#define RSCAN0TMPTR39 (RSCAN0.TMPTR39.UINT32)
+#define RSCAN0TMPTR39L (RSCAN0.TMPTR39.UINT16[R_IO_L])
+#define RSCAN0TMPTR39LL (RSCAN0.TMPTR39.UINT8[R_IO_LL])
+#define RSCAN0TMPTR39LH (RSCAN0.TMPTR39.UINT8[R_IO_LH])
+#define RSCAN0TMPTR39H (RSCAN0.TMPTR39.UINT16[R_IO_H])
+#define RSCAN0TMPTR39HL (RSCAN0.TMPTR39.UINT8[R_IO_HL])
+#define RSCAN0TMPTR39HH (RSCAN0.TMPTR39.UINT8[R_IO_HH])
+#define RSCAN0TMDF039 (RSCAN0.TMDF039.UINT32)
+#define RSCAN0TMDF039L (RSCAN0.TMDF039.UINT16[R_IO_L])
+#define RSCAN0TMDF039LL (RSCAN0.TMDF039.UINT8[R_IO_LL])
+#define RSCAN0TMDF039LH (RSCAN0.TMDF039.UINT8[R_IO_LH])
+#define RSCAN0TMDF039H (RSCAN0.TMDF039.UINT16[R_IO_H])
+#define RSCAN0TMDF039HL (RSCAN0.TMDF039.UINT8[R_IO_HL])
+#define RSCAN0TMDF039HH (RSCAN0.TMDF039.UINT8[R_IO_HH])
+#define RSCAN0TMDF139 (RSCAN0.TMDF139.UINT32)
+#define RSCAN0TMDF139L (RSCAN0.TMDF139.UINT16[R_IO_L])
+#define RSCAN0TMDF139LL (RSCAN0.TMDF139.UINT8[R_IO_LL])
+#define RSCAN0TMDF139LH (RSCAN0.TMDF139.UINT8[R_IO_LH])
+#define RSCAN0TMDF139H (RSCAN0.TMDF139.UINT16[R_IO_H])
+#define RSCAN0TMDF139HL (RSCAN0.TMDF139.UINT8[R_IO_HL])
+#define RSCAN0TMDF139HH (RSCAN0.TMDF139.UINT8[R_IO_HH])
+#define RSCAN0TMID40 (RSCAN0.TMID40.UINT32)
+#define RSCAN0TMID40L (RSCAN0.TMID40.UINT16[R_IO_L])
+#define RSCAN0TMID40LL (RSCAN0.TMID40.UINT8[R_IO_LL])
+#define RSCAN0TMID40LH (RSCAN0.TMID40.UINT8[R_IO_LH])
+#define RSCAN0TMID40H (RSCAN0.TMID40.UINT16[R_IO_H])
+#define RSCAN0TMID40HL (RSCAN0.TMID40.UINT8[R_IO_HL])
+#define RSCAN0TMID40HH (RSCAN0.TMID40.UINT8[R_IO_HH])
+#define RSCAN0TMPTR40 (RSCAN0.TMPTR40.UINT32)
+#define RSCAN0TMPTR40L (RSCAN0.TMPTR40.UINT16[R_IO_L])
+#define RSCAN0TMPTR40LL (RSCAN0.TMPTR40.UINT8[R_IO_LL])
+#define RSCAN0TMPTR40LH (RSCAN0.TMPTR40.UINT8[R_IO_LH])
+#define RSCAN0TMPTR40H (RSCAN0.TMPTR40.UINT16[R_IO_H])
+#define RSCAN0TMPTR40HL (RSCAN0.TMPTR40.UINT8[R_IO_HL])
+#define RSCAN0TMPTR40HH (RSCAN0.TMPTR40.UINT8[R_IO_HH])
+#define RSCAN0TMDF040 (RSCAN0.TMDF040.UINT32)
+#define RSCAN0TMDF040L (RSCAN0.TMDF040.UINT16[R_IO_L])
+#define RSCAN0TMDF040LL (RSCAN0.TMDF040.UINT8[R_IO_LL])
+#define RSCAN0TMDF040LH (RSCAN0.TMDF040.UINT8[R_IO_LH])
+#define RSCAN0TMDF040H (RSCAN0.TMDF040.UINT16[R_IO_H])
+#define RSCAN0TMDF040HL (RSCAN0.TMDF040.UINT8[R_IO_HL])
+#define RSCAN0TMDF040HH (RSCAN0.TMDF040.UINT8[R_IO_HH])
+#define RSCAN0TMDF140 (RSCAN0.TMDF140.UINT32)
+#define RSCAN0TMDF140L (RSCAN0.TMDF140.UINT16[R_IO_L])
+#define RSCAN0TMDF140LL (RSCAN0.TMDF140.UINT8[R_IO_LL])
+#define RSCAN0TMDF140LH (RSCAN0.TMDF140.UINT8[R_IO_LH])
+#define RSCAN0TMDF140H (RSCAN0.TMDF140.UINT16[R_IO_H])
+#define RSCAN0TMDF140HL (RSCAN0.TMDF140.UINT8[R_IO_HL])
+#define RSCAN0TMDF140HH (RSCAN0.TMDF140.UINT8[R_IO_HH])
+#define RSCAN0TMID41 (RSCAN0.TMID41.UINT32)
+#define RSCAN0TMID41L (RSCAN0.TMID41.UINT16[R_IO_L])
+#define RSCAN0TMID41LL (RSCAN0.TMID41.UINT8[R_IO_LL])
+#define RSCAN0TMID41LH (RSCAN0.TMID41.UINT8[R_IO_LH])
+#define RSCAN0TMID41H (RSCAN0.TMID41.UINT16[R_IO_H])
+#define RSCAN0TMID41HL (RSCAN0.TMID41.UINT8[R_IO_HL])
+#define RSCAN0TMID41HH (RSCAN0.TMID41.UINT8[R_IO_HH])
+#define RSCAN0TMPTR41 (RSCAN0.TMPTR41.UINT32)
+#define RSCAN0TMPTR41L (RSCAN0.TMPTR41.UINT16[R_IO_L])
+#define RSCAN0TMPTR41LL (RSCAN0.TMPTR41.UINT8[R_IO_LL])
+#define RSCAN0TMPTR41LH (RSCAN0.TMPTR41.UINT8[R_IO_LH])
+#define RSCAN0TMPTR41H (RSCAN0.TMPTR41.UINT16[R_IO_H])
+#define RSCAN0TMPTR41HL (RSCAN0.TMPTR41.UINT8[R_IO_HL])
+#define RSCAN0TMPTR41HH (RSCAN0.TMPTR41.UINT8[R_IO_HH])
+#define RSCAN0TMDF041 (RSCAN0.TMDF041.UINT32)
+#define RSCAN0TMDF041L (RSCAN0.TMDF041.UINT16[R_IO_L])
+#define RSCAN0TMDF041LL (RSCAN0.TMDF041.UINT8[R_IO_LL])
+#define RSCAN0TMDF041LH (RSCAN0.TMDF041.UINT8[R_IO_LH])
+#define RSCAN0TMDF041H (RSCAN0.TMDF041.UINT16[R_IO_H])
+#define RSCAN0TMDF041HL (RSCAN0.TMDF041.UINT8[R_IO_HL])
+#define RSCAN0TMDF041HH (RSCAN0.TMDF041.UINT8[R_IO_HH])
+#define RSCAN0TMDF141 (RSCAN0.TMDF141.UINT32)
+#define RSCAN0TMDF141L (RSCAN0.TMDF141.UINT16[R_IO_L])
+#define RSCAN0TMDF141LL (RSCAN0.TMDF141.UINT8[R_IO_LL])
+#define RSCAN0TMDF141LH (RSCAN0.TMDF141.UINT8[R_IO_LH])
+#define RSCAN0TMDF141H (RSCAN0.TMDF141.UINT16[R_IO_H])
+#define RSCAN0TMDF141HL (RSCAN0.TMDF141.UINT8[R_IO_HL])
+#define RSCAN0TMDF141HH (RSCAN0.TMDF141.UINT8[R_IO_HH])
+#define RSCAN0TMID42 (RSCAN0.TMID42.UINT32)
+#define RSCAN0TMID42L (RSCAN0.TMID42.UINT16[R_IO_L])
+#define RSCAN0TMID42LL (RSCAN0.TMID42.UINT8[R_IO_LL])
+#define RSCAN0TMID42LH (RSCAN0.TMID42.UINT8[R_IO_LH])
+#define RSCAN0TMID42H (RSCAN0.TMID42.UINT16[R_IO_H])
+#define RSCAN0TMID42HL (RSCAN0.TMID42.UINT8[R_IO_HL])
+#define RSCAN0TMID42HH (RSCAN0.TMID42.UINT8[R_IO_HH])
+#define RSCAN0TMPTR42 (RSCAN0.TMPTR42.UINT32)
+#define RSCAN0TMPTR42L (RSCAN0.TMPTR42.UINT16[R_IO_L])
+#define RSCAN0TMPTR42LL (RSCAN0.TMPTR42.UINT8[R_IO_LL])
+#define RSCAN0TMPTR42LH (RSCAN0.TMPTR42.UINT8[R_IO_LH])
+#define RSCAN0TMPTR42H (RSCAN0.TMPTR42.UINT16[R_IO_H])
+#define RSCAN0TMPTR42HL (RSCAN0.TMPTR42.UINT8[R_IO_HL])
+#define RSCAN0TMPTR42HH (RSCAN0.TMPTR42.UINT8[R_IO_HH])
+#define RSCAN0TMDF042 (RSCAN0.TMDF042.UINT32)
+#define RSCAN0TMDF042L (RSCAN0.TMDF042.UINT16[R_IO_L])
+#define RSCAN0TMDF042LL (RSCAN0.TMDF042.UINT8[R_IO_LL])
+#define RSCAN0TMDF042LH (RSCAN0.TMDF042.UINT8[R_IO_LH])
+#define RSCAN0TMDF042H (RSCAN0.TMDF042.UINT16[R_IO_H])
+#define RSCAN0TMDF042HL (RSCAN0.TMDF042.UINT8[R_IO_HL])
+#define RSCAN0TMDF042HH (RSCAN0.TMDF042.UINT8[R_IO_HH])
+#define RSCAN0TMDF142 (RSCAN0.TMDF142.UINT32)
+#define RSCAN0TMDF142L (RSCAN0.TMDF142.UINT16[R_IO_L])
+#define RSCAN0TMDF142LL (RSCAN0.TMDF142.UINT8[R_IO_LL])
+#define RSCAN0TMDF142LH (RSCAN0.TMDF142.UINT8[R_IO_LH])
+#define RSCAN0TMDF142H (RSCAN0.TMDF142.UINT16[R_IO_H])
+#define RSCAN0TMDF142HL (RSCAN0.TMDF142.UINT8[R_IO_HL])
+#define RSCAN0TMDF142HH (RSCAN0.TMDF142.UINT8[R_IO_HH])
+#define RSCAN0TMID43 (RSCAN0.TMID43.UINT32)
+#define RSCAN0TMID43L (RSCAN0.TMID43.UINT16[R_IO_L])
+#define RSCAN0TMID43LL (RSCAN0.TMID43.UINT8[R_IO_LL])
+#define RSCAN0TMID43LH (RSCAN0.TMID43.UINT8[R_IO_LH])
+#define RSCAN0TMID43H (RSCAN0.TMID43.UINT16[R_IO_H])
+#define RSCAN0TMID43HL (RSCAN0.TMID43.UINT8[R_IO_HL])
+#define RSCAN0TMID43HH (RSCAN0.TMID43.UINT8[R_IO_HH])
+#define RSCAN0TMPTR43 (RSCAN0.TMPTR43.UINT32)
+#define RSCAN0TMPTR43L (RSCAN0.TMPTR43.UINT16[R_IO_L])
+#define RSCAN0TMPTR43LL (RSCAN0.TMPTR43.UINT8[R_IO_LL])
+#define RSCAN0TMPTR43LH (RSCAN0.TMPTR43.UINT8[R_IO_LH])
+#define RSCAN0TMPTR43H (RSCAN0.TMPTR43.UINT16[R_IO_H])
+#define RSCAN0TMPTR43HL (RSCAN0.TMPTR43.UINT8[R_IO_HL])
+#define RSCAN0TMPTR43HH (RSCAN0.TMPTR43.UINT8[R_IO_HH])
+#define RSCAN0TMDF043 (RSCAN0.TMDF043.UINT32)
+#define RSCAN0TMDF043L (RSCAN0.TMDF043.UINT16[R_IO_L])
+#define RSCAN0TMDF043LL (RSCAN0.TMDF043.UINT8[R_IO_LL])
+#define RSCAN0TMDF043LH (RSCAN0.TMDF043.UINT8[R_IO_LH])
+#define RSCAN0TMDF043H (RSCAN0.TMDF043.UINT16[R_IO_H])
+#define RSCAN0TMDF043HL (RSCAN0.TMDF043.UINT8[R_IO_HL])
+#define RSCAN0TMDF043HH (RSCAN0.TMDF043.UINT8[R_IO_HH])
+#define RSCAN0TMDF143 (RSCAN0.TMDF143.UINT32)
+#define RSCAN0TMDF143L (RSCAN0.TMDF143.UINT16[R_IO_L])
+#define RSCAN0TMDF143LL (RSCAN0.TMDF143.UINT8[R_IO_LL])
+#define RSCAN0TMDF143LH (RSCAN0.TMDF143.UINT8[R_IO_LH])
+#define RSCAN0TMDF143H (RSCAN0.TMDF143.UINT16[R_IO_H])
+#define RSCAN0TMDF143HL (RSCAN0.TMDF143.UINT8[R_IO_HL])
+#define RSCAN0TMDF143HH (RSCAN0.TMDF143.UINT8[R_IO_HH])
+#define RSCAN0TMID44 (RSCAN0.TMID44.UINT32)
+#define RSCAN0TMID44L (RSCAN0.TMID44.UINT16[R_IO_L])
+#define RSCAN0TMID44LL (RSCAN0.TMID44.UINT8[R_IO_LL])
+#define RSCAN0TMID44LH (RSCAN0.TMID44.UINT8[R_IO_LH])
+#define RSCAN0TMID44H (RSCAN0.TMID44.UINT16[R_IO_H])
+#define RSCAN0TMID44HL (RSCAN0.TMID44.UINT8[R_IO_HL])
+#define RSCAN0TMID44HH (RSCAN0.TMID44.UINT8[R_IO_HH])
+#define RSCAN0TMPTR44 (RSCAN0.TMPTR44.UINT32)
+#define RSCAN0TMPTR44L (RSCAN0.TMPTR44.UINT16[R_IO_L])
+#define RSCAN0TMPTR44LL (RSCAN0.TMPTR44.UINT8[R_IO_LL])
+#define RSCAN0TMPTR44LH (RSCAN0.TMPTR44.UINT8[R_IO_LH])
+#define RSCAN0TMPTR44H (RSCAN0.TMPTR44.UINT16[R_IO_H])
+#define RSCAN0TMPTR44HL (RSCAN0.TMPTR44.UINT8[R_IO_HL])
+#define RSCAN0TMPTR44HH (RSCAN0.TMPTR44.UINT8[R_IO_HH])
+#define RSCAN0TMDF044 (RSCAN0.TMDF044.UINT32)
+#define RSCAN0TMDF044L (RSCAN0.TMDF044.UINT16[R_IO_L])
+#define RSCAN0TMDF044LL (RSCAN0.TMDF044.UINT8[R_IO_LL])
+#define RSCAN0TMDF044LH (RSCAN0.TMDF044.UINT8[R_IO_LH])
+#define RSCAN0TMDF044H (RSCAN0.TMDF044.UINT16[R_IO_H])
+#define RSCAN0TMDF044HL (RSCAN0.TMDF044.UINT8[R_IO_HL])
+#define RSCAN0TMDF044HH (RSCAN0.TMDF044.UINT8[R_IO_HH])
+#define RSCAN0TMDF144 (RSCAN0.TMDF144.UINT32)
+#define RSCAN0TMDF144L (RSCAN0.TMDF144.UINT16[R_IO_L])
+#define RSCAN0TMDF144LL (RSCAN0.TMDF144.UINT8[R_IO_LL])
+#define RSCAN0TMDF144LH (RSCAN0.TMDF144.UINT8[R_IO_LH])
+#define RSCAN0TMDF144H (RSCAN0.TMDF144.UINT16[R_IO_H])
+#define RSCAN0TMDF144HL (RSCAN0.TMDF144.UINT8[R_IO_HL])
+#define RSCAN0TMDF144HH (RSCAN0.TMDF144.UINT8[R_IO_HH])
+#define RSCAN0TMID45 (RSCAN0.TMID45.UINT32)
+#define RSCAN0TMID45L (RSCAN0.TMID45.UINT16[R_IO_L])
+#define RSCAN0TMID45LL (RSCAN0.TMID45.UINT8[R_IO_LL])
+#define RSCAN0TMID45LH (RSCAN0.TMID45.UINT8[R_IO_LH])
+#define RSCAN0TMID45H (RSCAN0.TMID45.UINT16[R_IO_H])
+#define RSCAN0TMID45HL (RSCAN0.TMID45.UINT8[R_IO_HL])
+#define RSCAN0TMID45HH (RSCAN0.TMID45.UINT8[R_IO_HH])
+#define RSCAN0TMPTR45 (RSCAN0.TMPTR45.UINT32)
+#define RSCAN0TMPTR45L (RSCAN0.TMPTR45.UINT16[R_IO_L])
+#define RSCAN0TMPTR45LL (RSCAN0.TMPTR45.UINT8[R_IO_LL])
+#define RSCAN0TMPTR45LH (RSCAN0.TMPTR45.UINT8[R_IO_LH])
+#define RSCAN0TMPTR45H (RSCAN0.TMPTR45.UINT16[R_IO_H])
+#define RSCAN0TMPTR45HL (RSCAN0.TMPTR45.UINT8[R_IO_HL])
+#define RSCAN0TMPTR45HH (RSCAN0.TMPTR45.UINT8[R_IO_HH])
+#define RSCAN0TMDF045 (RSCAN0.TMDF045.UINT32)
+#define RSCAN0TMDF045L (RSCAN0.TMDF045.UINT16[R_IO_L])
+#define RSCAN0TMDF045LL (RSCAN0.TMDF045.UINT8[R_IO_LL])
+#define RSCAN0TMDF045LH (RSCAN0.TMDF045.UINT8[R_IO_LH])
+#define RSCAN0TMDF045H (RSCAN0.TMDF045.UINT16[R_IO_H])
+#define RSCAN0TMDF045HL (RSCAN0.TMDF045.UINT8[R_IO_HL])
+#define RSCAN0TMDF045HH (RSCAN0.TMDF045.UINT8[R_IO_HH])
+#define RSCAN0TMDF145 (RSCAN0.TMDF145.UINT32)
+#define RSCAN0TMDF145L (RSCAN0.TMDF145.UINT16[R_IO_L])
+#define RSCAN0TMDF145LL (RSCAN0.TMDF145.UINT8[R_IO_LL])
+#define RSCAN0TMDF145LH (RSCAN0.TMDF145.UINT8[R_IO_LH])
+#define RSCAN0TMDF145H (RSCAN0.TMDF145.UINT16[R_IO_H])
+#define RSCAN0TMDF145HL (RSCAN0.TMDF145.UINT8[R_IO_HL])
+#define RSCAN0TMDF145HH (RSCAN0.TMDF145.UINT8[R_IO_HH])
+#define RSCAN0TMID46 (RSCAN0.TMID46.UINT32)
+#define RSCAN0TMID46L (RSCAN0.TMID46.UINT16[R_IO_L])
+#define RSCAN0TMID46LL (RSCAN0.TMID46.UINT8[R_IO_LL])
+#define RSCAN0TMID46LH (RSCAN0.TMID46.UINT8[R_IO_LH])
+#define RSCAN0TMID46H (RSCAN0.TMID46.UINT16[R_IO_H])
+#define RSCAN0TMID46HL (RSCAN0.TMID46.UINT8[R_IO_HL])
+#define RSCAN0TMID46HH (RSCAN0.TMID46.UINT8[R_IO_HH])
+#define RSCAN0TMPTR46 (RSCAN0.TMPTR46.UINT32)
+#define RSCAN0TMPTR46L (RSCAN0.TMPTR46.UINT16[R_IO_L])
+#define RSCAN0TMPTR46LL (RSCAN0.TMPTR46.UINT8[R_IO_LL])
+#define RSCAN0TMPTR46LH (RSCAN0.TMPTR46.UINT8[R_IO_LH])
+#define RSCAN0TMPTR46H (RSCAN0.TMPTR46.UINT16[R_IO_H])
+#define RSCAN0TMPTR46HL (RSCAN0.TMPTR46.UINT8[R_IO_HL])
+#define RSCAN0TMPTR46HH (RSCAN0.TMPTR46.UINT8[R_IO_HH])
+#define RSCAN0TMDF046 (RSCAN0.TMDF046.UINT32)
+#define RSCAN0TMDF046L (RSCAN0.TMDF046.UINT16[R_IO_L])
+#define RSCAN0TMDF046LL (RSCAN0.TMDF046.UINT8[R_IO_LL])
+#define RSCAN0TMDF046LH (RSCAN0.TMDF046.UINT8[R_IO_LH])
+#define RSCAN0TMDF046H (RSCAN0.TMDF046.UINT16[R_IO_H])
+#define RSCAN0TMDF046HL (RSCAN0.TMDF046.UINT8[R_IO_HL])
+#define RSCAN0TMDF046HH (RSCAN0.TMDF046.UINT8[R_IO_HH])
+#define RSCAN0TMDF146 (RSCAN0.TMDF146.UINT32)
+#define RSCAN0TMDF146L (RSCAN0.TMDF146.UINT16[R_IO_L])
+#define RSCAN0TMDF146LL (RSCAN0.TMDF146.UINT8[R_IO_LL])
+#define RSCAN0TMDF146LH (RSCAN0.TMDF146.UINT8[R_IO_LH])
+#define RSCAN0TMDF146H (RSCAN0.TMDF146.UINT16[R_IO_H])
+#define RSCAN0TMDF146HL (RSCAN0.TMDF146.UINT8[R_IO_HL])
+#define RSCAN0TMDF146HH (RSCAN0.TMDF146.UINT8[R_IO_HH])
+#define RSCAN0TMID47 (RSCAN0.TMID47.UINT32)
+#define RSCAN0TMID47L (RSCAN0.TMID47.UINT16[R_IO_L])
+#define RSCAN0TMID47LL (RSCAN0.TMID47.UINT8[R_IO_LL])
+#define RSCAN0TMID47LH (RSCAN0.TMID47.UINT8[R_IO_LH])
+#define RSCAN0TMID47H (RSCAN0.TMID47.UINT16[R_IO_H])
+#define RSCAN0TMID47HL (RSCAN0.TMID47.UINT8[R_IO_HL])
+#define RSCAN0TMID47HH (RSCAN0.TMID47.UINT8[R_IO_HH])
+#define RSCAN0TMPTR47 (RSCAN0.TMPTR47.UINT32)
+#define RSCAN0TMPTR47L (RSCAN0.TMPTR47.UINT16[R_IO_L])
+#define RSCAN0TMPTR47LL (RSCAN0.TMPTR47.UINT8[R_IO_LL])
+#define RSCAN0TMPTR47LH (RSCAN0.TMPTR47.UINT8[R_IO_LH])
+#define RSCAN0TMPTR47H (RSCAN0.TMPTR47.UINT16[R_IO_H])
+#define RSCAN0TMPTR47HL (RSCAN0.TMPTR47.UINT8[R_IO_HL])
+#define RSCAN0TMPTR47HH (RSCAN0.TMPTR47.UINT8[R_IO_HH])
+#define RSCAN0TMDF047 (RSCAN0.TMDF047.UINT32)
+#define RSCAN0TMDF047L (RSCAN0.TMDF047.UINT16[R_IO_L])
+#define RSCAN0TMDF047LL (RSCAN0.TMDF047.UINT8[R_IO_LL])
+#define RSCAN0TMDF047LH (RSCAN0.TMDF047.UINT8[R_IO_LH])
+#define RSCAN0TMDF047H (RSCAN0.TMDF047.UINT16[R_IO_H])
+#define RSCAN0TMDF047HL (RSCAN0.TMDF047.UINT8[R_IO_HL])
+#define RSCAN0TMDF047HH (RSCAN0.TMDF047.UINT8[R_IO_HH])
+#define RSCAN0TMDF147 (RSCAN0.TMDF147.UINT32)
+#define RSCAN0TMDF147L (RSCAN0.TMDF147.UINT16[R_IO_L])
+#define RSCAN0TMDF147LL (RSCAN0.TMDF147.UINT8[R_IO_LL])
+#define RSCAN0TMDF147LH (RSCAN0.TMDF147.UINT8[R_IO_LH])
+#define RSCAN0TMDF147H (RSCAN0.TMDF147.UINT16[R_IO_H])
+#define RSCAN0TMDF147HL (RSCAN0.TMDF147.UINT8[R_IO_HL])
+#define RSCAN0TMDF147HH (RSCAN0.TMDF147.UINT8[R_IO_HH])
+#define RSCAN0TMID48 (RSCAN0.TMID48.UINT32)
+#define RSCAN0TMID48L (RSCAN0.TMID48.UINT16[R_IO_L])
+#define RSCAN0TMID48LL (RSCAN0.TMID48.UINT8[R_IO_LL])
+#define RSCAN0TMID48LH (RSCAN0.TMID48.UINT8[R_IO_LH])
+#define RSCAN0TMID48H (RSCAN0.TMID48.UINT16[R_IO_H])
+#define RSCAN0TMID48HL (RSCAN0.TMID48.UINT8[R_IO_HL])
+#define RSCAN0TMID48HH (RSCAN0.TMID48.UINT8[R_IO_HH])
+#define RSCAN0TMPTR48 (RSCAN0.TMPTR48.UINT32)
+#define RSCAN0TMPTR48L (RSCAN0.TMPTR48.UINT16[R_IO_L])
+#define RSCAN0TMPTR48LL (RSCAN0.TMPTR48.UINT8[R_IO_LL])
+#define RSCAN0TMPTR48LH (RSCAN0.TMPTR48.UINT8[R_IO_LH])
+#define RSCAN0TMPTR48H (RSCAN0.TMPTR48.UINT16[R_IO_H])
+#define RSCAN0TMPTR48HL (RSCAN0.TMPTR48.UINT8[R_IO_HL])
+#define RSCAN0TMPTR48HH (RSCAN0.TMPTR48.UINT8[R_IO_HH])
+#define RSCAN0TMDF048 (RSCAN0.TMDF048.UINT32)
+#define RSCAN0TMDF048L (RSCAN0.TMDF048.UINT16[R_IO_L])
+#define RSCAN0TMDF048LL (RSCAN0.TMDF048.UINT8[R_IO_LL])
+#define RSCAN0TMDF048LH (RSCAN0.TMDF048.UINT8[R_IO_LH])
+#define RSCAN0TMDF048H (RSCAN0.TMDF048.UINT16[R_IO_H])
+#define RSCAN0TMDF048HL (RSCAN0.TMDF048.UINT8[R_IO_HL])
+#define RSCAN0TMDF048HH (RSCAN0.TMDF048.UINT8[R_IO_HH])
+#define RSCAN0TMDF148 (RSCAN0.TMDF148.UINT32)
+#define RSCAN0TMDF148L (RSCAN0.TMDF148.UINT16[R_IO_L])
+#define RSCAN0TMDF148LL (RSCAN0.TMDF148.UINT8[R_IO_LL])
+#define RSCAN0TMDF148LH (RSCAN0.TMDF148.UINT8[R_IO_LH])
+#define RSCAN0TMDF148H (RSCAN0.TMDF148.UINT16[R_IO_H])
+#define RSCAN0TMDF148HL (RSCAN0.TMDF148.UINT8[R_IO_HL])
+#define RSCAN0TMDF148HH (RSCAN0.TMDF148.UINT8[R_IO_HH])
+#define RSCAN0TMID49 (RSCAN0.TMID49.UINT32)
+#define RSCAN0TMID49L (RSCAN0.TMID49.UINT16[R_IO_L])
+#define RSCAN0TMID49LL (RSCAN0.TMID49.UINT8[R_IO_LL])
+#define RSCAN0TMID49LH (RSCAN0.TMID49.UINT8[R_IO_LH])
+#define RSCAN0TMID49H (RSCAN0.TMID49.UINT16[R_IO_H])
+#define RSCAN0TMID49HL (RSCAN0.TMID49.UINT8[R_IO_HL])
+#define RSCAN0TMID49HH (RSCAN0.TMID49.UINT8[R_IO_HH])
+#define RSCAN0TMPTR49 (RSCAN0.TMPTR49.UINT32)
+#define RSCAN0TMPTR49L (RSCAN0.TMPTR49.UINT16[R_IO_L])
+#define RSCAN0TMPTR49LL (RSCAN0.TMPTR49.UINT8[R_IO_LL])
+#define RSCAN0TMPTR49LH (RSCAN0.TMPTR49.UINT8[R_IO_LH])
+#define RSCAN0TMPTR49H (RSCAN0.TMPTR49.UINT16[R_IO_H])
+#define RSCAN0TMPTR49HL (RSCAN0.TMPTR49.UINT8[R_IO_HL])
+#define RSCAN0TMPTR49HH (RSCAN0.TMPTR49.UINT8[R_IO_HH])
+#define RSCAN0TMDF049 (RSCAN0.TMDF049.UINT32)
+#define RSCAN0TMDF049L (RSCAN0.TMDF049.UINT16[R_IO_L])
+#define RSCAN0TMDF049LL (RSCAN0.TMDF049.UINT8[R_IO_LL])
+#define RSCAN0TMDF049LH (RSCAN0.TMDF049.UINT8[R_IO_LH])
+#define RSCAN0TMDF049H (RSCAN0.TMDF049.UINT16[R_IO_H])
+#define RSCAN0TMDF049HL (RSCAN0.TMDF049.UINT8[R_IO_HL])
+#define RSCAN0TMDF049HH (RSCAN0.TMDF049.UINT8[R_IO_HH])
+#define RSCAN0TMDF149 (RSCAN0.TMDF149.UINT32)
+#define RSCAN0TMDF149L (RSCAN0.TMDF149.UINT16[R_IO_L])
+#define RSCAN0TMDF149LL (RSCAN0.TMDF149.UINT8[R_IO_LL])
+#define RSCAN0TMDF149LH (RSCAN0.TMDF149.UINT8[R_IO_LH])
+#define RSCAN0TMDF149H (RSCAN0.TMDF149.UINT16[R_IO_H])
+#define RSCAN0TMDF149HL (RSCAN0.TMDF149.UINT8[R_IO_HL])
+#define RSCAN0TMDF149HH (RSCAN0.TMDF149.UINT8[R_IO_HH])
+#define RSCAN0TMID50 (RSCAN0.TMID50.UINT32)
+#define RSCAN0TMID50L (RSCAN0.TMID50.UINT16[R_IO_L])
+#define RSCAN0TMID50LL (RSCAN0.TMID50.UINT8[R_IO_LL])
+#define RSCAN0TMID50LH (RSCAN0.TMID50.UINT8[R_IO_LH])
+#define RSCAN0TMID50H (RSCAN0.TMID50.UINT16[R_IO_H])
+#define RSCAN0TMID50HL (RSCAN0.TMID50.UINT8[R_IO_HL])
+#define RSCAN0TMID50HH (RSCAN0.TMID50.UINT8[R_IO_HH])
+#define RSCAN0TMPTR50 (RSCAN0.TMPTR50.UINT32)
+#define RSCAN0TMPTR50L (RSCAN0.TMPTR50.UINT16[R_IO_L])
+#define RSCAN0TMPTR50LL (RSCAN0.TMPTR50.UINT8[R_IO_LL])
+#define RSCAN0TMPTR50LH (RSCAN0.TMPTR50.UINT8[R_IO_LH])
+#define RSCAN0TMPTR50H (RSCAN0.TMPTR50.UINT16[R_IO_H])
+#define RSCAN0TMPTR50HL (RSCAN0.TMPTR50.UINT8[R_IO_HL])
+#define RSCAN0TMPTR50HH (RSCAN0.TMPTR50.UINT8[R_IO_HH])
+#define RSCAN0TMDF050 (RSCAN0.TMDF050.UINT32)
+#define RSCAN0TMDF050L (RSCAN0.TMDF050.UINT16[R_IO_L])
+#define RSCAN0TMDF050LL (RSCAN0.TMDF050.UINT8[R_IO_LL])
+#define RSCAN0TMDF050LH (RSCAN0.TMDF050.UINT8[R_IO_LH])
+#define RSCAN0TMDF050H (RSCAN0.TMDF050.UINT16[R_IO_H])
+#define RSCAN0TMDF050HL (RSCAN0.TMDF050.UINT8[R_IO_HL])
+#define RSCAN0TMDF050HH (RSCAN0.TMDF050.UINT8[R_IO_HH])
+#define RSCAN0TMDF150 (RSCAN0.TMDF150.UINT32)
+#define RSCAN0TMDF150L (RSCAN0.TMDF150.UINT16[R_IO_L])
+#define RSCAN0TMDF150LL (RSCAN0.TMDF150.UINT8[R_IO_LL])
+#define RSCAN0TMDF150LH (RSCAN0.TMDF150.UINT8[R_IO_LH])
+#define RSCAN0TMDF150H (RSCAN0.TMDF150.UINT16[R_IO_H])
+#define RSCAN0TMDF150HL (RSCAN0.TMDF150.UINT8[R_IO_HL])
+#define RSCAN0TMDF150HH (RSCAN0.TMDF150.UINT8[R_IO_HH])
+#define RSCAN0TMID51 (RSCAN0.TMID51.UINT32)
+#define RSCAN0TMID51L (RSCAN0.TMID51.UINT16[R_IO_L])
+#define RSCAN0TMID51LL (RSCAN0.TMID51.UINT8[R_IO_LL])
+#define RSCAN0TMID51LH (RSCAN0.TMID51.UINT8[R_IO_LH])
+#define RSCAN0TMID51H (RSCAN0.TMID51.UINT16[R_IO_H])
+#define RSCAN0TMID51HL (RSCAN0.TMID51.UINT8[R_IO_HL])
+#define RSCAN0TMID51HH (RSCAN0.TMID51.UINT8[R_IO_HH])
+#define RSCAN0TMPTR51 (RSCAN0.TMPTR51.UINT32)
+#define RSCAN0TMPTR51L (RSCAN0.TMPTR51.UINT16[R_IO_L])
+#define RSCAN0TMPTR51LL (RSCAN0.TMPTR51.UINT8[R_IO_LL])
+#define RSCAN0TMPTR51LH (RSCAN0.TMPTR51.UINT8[R_IO_LH])
+#define RSCAN0TMPTR51H (RSCAN0.TMPTR51.UINT16[R_IO_H])
+#define RSCAN0TMPTR51HL (RSCAN0.TMPTR51.UINT8[R_IO_HL])
+#define RSCAN0TMPTR51HH (RSCAN0.TMPTR51.UINT8[R_IO_HH])
+#define RSCAN0TMDF051 (RSCAN0.TMDF051.UINT32)
+#define RSCAN0TMDF051L (RSCAN0.TMDF051.UINT16[R_IO_L])
+#define RSCAN0TMDF051LL (RSCAN0.TMDF051.UINT8[R_IO_LL])
+#define RSCAN0TMDF051LH (RSCAN0.TMDF051.UINT8[R_IO_LH])
+#define RSCAN0TMDF051H (RSCAN0.TMDF051.UINT16[R_IO_H])
+#define RSCAN0TMDF051HL (RSCAN0.TMDF051.UINT8[R_IO_HL])
+#define RSCAN0TMDF051HH (RSCAN0.TMDF051.UINT8[R_IO_HH])
+#define RSCAN0TMDF151 (RSCAN0.TMDF151.UINT32)
+#define RSCAN0TMDF151L (RSCAN0.TMDF151.UINT16[R_IO_L])
+#define RSCAN0TMDF151LL (RSCAN0.TMDF151.UINT8[R_IO_LL])
+#define RSCAN0TMDF151LH (RSCAN0.TMDF151.UINT8[R_IO_LH])
+#define RSCAN0TMDF151H (RSCAN0.TMDF151.UINT16[R_IO_H])
+#define RSCAN0TMDF151HL (RSCAN0.TMDF151.UINT8[R_IO_HL])
+#define RSCAN0TMDF151HH (RSCAN0.TMDF151.UINT8[R_IO_HH])
+#define RSCAN0TMID52 (RSCAN0.TMID52.UINT32)
+#define RSCAN0TMID52L (RSCAN0.TMID52.UINT16[R_IO_L])
+#define RSCAN0TMID52LL (RSCAN0.TMID52.UINT8[R_IO_LL])
+#define RSCAN0TMID52LH (RSCAN0.TMID52.UINT8[R_IO_LH])
+#define RSCAN0TMID52H (RSCAN0.TMID52.UINT16[R_IO_H])
+#define RSCAN0TMID52HL (RSCAN0.TMID52.UINT8[R_IO_HL])
+#define RSCAN0TMID52HH (RSCAN0.TMID52.UINT8[R_IO_HH])
+#define RSCAN0TMPTR52 (RSCAN0.TMPTR52.UINT32)
+#define RSCAN0TMPTR52L (RSCAN0.TMPTR52.UINT16[R_IO_L])
+#define RSCAN0TMPTR52LL (RSCAN0.TMPTR52.UINT8[R_IO_LL])
+#define RSCAN0TMPTR52LH (RSCAN0.TMPTR52.UINT8[R_IO_LH])
+#define RSCAN0TMPTR52H (RSCAN0.TMPTR52.UINT16[R_IO_H])
+#define RSCAN0TMPTR52HL (RSCAN0.TMPTR52.UINT8[R_IO_HL])
+#define RSCAN0TMPTR52HH (RSCAN0.TMPTR52.UINT8[R_IO_HH])
+#define RSCAN0TMDF052 (RSCAN0.TMDF052.UINT32)
+#define RSCAN0TMDF052L (RSCAN0.TMDF052.UINT16[R_IO_L])
+#define RSCAN0TMDF052LL (RSCAN0.TMDF052.UINT8[R_IO_LL])
+#define RSCAN0TMDF052LH (RSCAN0.TMDF052.UINT8[R_IO_LH])
+#define RSCAN0TMDF052H (RSCAN0.TMDF052.UINT16[R_IO_H])
+#define RSCAN0TMDF052HL (RSCAN0.TMDF052.UINT8[R_IO_HL])
+#define RSCAN0TMDF052HH (RSCAN0.TMDF052.UINT8[R_IO_HH])
+#define RSCAN0TMDF152 (RSCAN0.TMDF152.UINT32)
+#define RSCAN0TMDF152L (RSCAN0.TMDF152.UINT16[R_IO_L])
+#define RSCAN0TMDF152LL (RSCAN0.TMDF152.UINT8[R_IO_LL])
+#define RSCAN0TMDF152LH (RSCAN0.TMDF152.UINT8[R_IO_LH])
+#define RSCAN0TMDF152H (RSCAN0.TMDF152.UINT16[R_IO_H])
+#define RSCAN0TMDF152HL (RSCAN0.TMDF152.UINT8[R_IO_HL])
+#define RSCAN0TMDF152HH (RSCAN0.TMDF152.UINT8[R_IO_HH])
+#define RSCAN0TMID53 (RSCAN0.TMID53.UINT32)
+#define RSCAN0TMID53L (RSCAN0.TMID53.UINT16[R_IO_L])
+#define RSCAN0TMID53LL (RSCAN0.TMID53.UINT8[R_IO_LL])
+#define RSCAN0TMID53LH (RSCAN0.TMID53.UINT8[R_IO_LH])
+#define RSCAN0TMID53H (RSCAN0.TMID53.UINT16[R_IO_H])
+#define RSCAN0TMID53HL (RSCAN0.TMID53.UINT8[R_IO_HL])
+#define RSCAN0TMID53HH (RSCAN0.TMID53.UINT8[R_IO_HH])
+#define RSCAN0TMPTR53 (RSCAN0.TMPTR53.UINT32)
+#define RSCAN0TMPTR53L (RSCAN0.TMPTR53.UINT16[R_IO_L])
+#define RSCAN0TMPTR53LL (RSCAN0.TMPTR53.UINT8[R_IO_LL])
+#define RSCAN0TMPTR53LH (RSCAN0.TMPTR53.UINT8[R_IO_LH])
+#define RSCAN0TMPTR53H (RSCAN0.TMPTR53.UINT16[R_IO_H])
+#define RSCAN0TMPTR53HL (RSCAN0.TMPTR53.UINT8[R_IO_HL])
+#define RSCAN0TMPTR53HH (RSCAN0.TMPTR53.UINT8[R_IO_HH])
+#define RSCAN0TMDF053 (RSCAN0.TMDF053.UINT32)
+#define RSCAN0TMDF053L (RSCAN0.TMDF053.UINT16[R_IO_L])
+#define RSCAN0TMDF053LL (RSCAN0.TMDF053.UINT8[R_IO_LL])
+#define RSCAN0TMDF053LH (RSCAN0.TMDF053.UINT8[R_IO_LH])
+#define RSCAN0TMDF053H (RSCAN0.TMDF053.UINT16[R_IO_H])
+#define RSCAN0TMDF053HL (RSCAN0.TMDF053.UINT8[R_IO_HL])
+#define RSCAN0TMDF053HH (RSCAN0.TMDF053.UINT8[R_IO_HH])
+#define RSCAN0TMDF153 (RSCAN0.TMDF153.UINT32)
+#define RSCAN0TMDF153L (RSCAN0.TMDF153.UINT16[R_IO_L])
+#define RSCAN0TMDF153LL (RSCAN0.TMDF153.UINT8[R_IO_LL])
+#define RSCAN0TMDF153LH (RSCAN0.TMDF153.UINT8[R_IO_LH])
+#define RSCAN0TMDF153H (RSCAN0.TMDF153.UINT16[R_IO_H])
+#define RSCAN0TMDF153HL (RSCAN0.TMDF153.UINT8[R_IO_HL])
+#define RSCAN0TMDF153HH (RSCAN0.TMDF153.UINT8[R_IO_HH])
+#define RSCAN0TMID54 (RSCAN0.TMID54.UINT32)
+#define RSCAN0TMID54L (RSCAN0.TMID54.UINT16[R_IO_L])
+#define RSCAN0TMID54LL (RSCAN0.TMID54.UINT8[R_IO_LL])
+#define RSCAN0TMID54LH (RSCAN0.TMID54.UINT8[R_IO_LH])
+#define RSCAN0TMID54H (RSCAN0.TMID54.UINT16[R_IO_H])
+#define RSCAN0TMID54HL (RSCAN0.TMID54.UINT8[R_IO_HL])
+#define RSCAN0TMID54HH (RSCAN0.TMID54.UINT8[R_IO_HH])
+#define RSCAN0TMPTR54 (RSCAN0.TMPTR54.UINT32)
+#define RSCAN0TMPTR54L (RSCAN0.TMPTR54.UINT16[R_IO_L])
+#define RSCAN0TMPTR54LL (RSCAN0.TMPTR54.UINT8[R_IO_LL])
+#define RSCAN0TMPTR54LH (RSCAN0.TMPTR54.UINT8[R_IO_LH])
+#define RSCAN0TMPTR54H (RSCAN0.TMPTR54.UINT16[R_IO_H])
+#define RSCAN0TMPTR54HL (RSCAN0.TMPTR54.UINT8[R_IO_HL])
+#define RSCAN0TMPTR54HH (RSCAN0.TMPTR54.UINT8[R_IO_HH])
+#define RSCAN0TMDF054 (RSCAN0.TMDF054.UINT32)
+#define RSCAN0TMDF054L (RSCAN0.TMDF054.UINT16[R_IO_L])
+#define RSCAN0TMDF054LL (RSCAN0.TMDF054.UINT8[R_IO_LL])
+#define RSCAN0TMDF054LH (RSCAN0.TMDF054.UINT8[R_IO_LH])
+#define RSCAN0TMDF054H (RSCAN0.TMDF054.UINT16[R_IO_H])
+#define RSCAN0TMDF054HL (RSCAN0.TMDF054.UINT8[R_IO_HL])
+#define RSCAN0TMDF054HH (RSCAN0.TMDF054.UINT8[R_IO_HH])
+#define RSCAN0TMDF154 (RSCAN0.TMDF154.UINT32)
+#define RSCAN0TMDF154L (RSCAN0.TMDF154.UINT16[R_IO_L])
+#define RSCAN0TMDF154LL (RSCAN0.TMDF154.UINT8[R_IO_LL])
+#define RSCAN0TMDF154LH (RSCAN0.TMDF154.UINT8[R_IO_LH])
+#define RSCAN0TMDF154H (RSCAN0.TMDF154.UINT16[R_IO_H])
+#define RSCAN0TMDF154HL (RSCAN0.TMDF154.UINT8[R_IO_HL])
+#define RSCAN0TMDF154HH (RSCAN0.TMDF154.UINT8[R_IO_HH])
+#define RSCAN0TMID55 (RSCAN0.TMID55.UINT32)
+#define RSCAN0TMID55L (RSCAN0.TMID55.UINT16[R_IO_L])
+#define RSCAN0TMID55LL (RSCAN0.TMID55.UINT8[R_IO_LL])
+#define RSCAN0TMID55LH (RSCAN0.TMID55.UINT8[R_IO_LH])
+#define RSCAN0TMID55H (RSCAN0.TMID55.UINT16[R_IO_H])
+#define RSCAN0TMID55HL (RSCAN0.TMID55.UINT8[R_IO_HL])
+#define RSCAN0TMID55HH (RSCAN0.TMID55.UINT8[R_IO_HH])
+#define RSCAN0TMPTR55 (RSCAN0.TMPTR55.UINT32)
+#define RSCAN0TMPTR55L (RSCAN0.TMPTR55.UINT16[R_IO_L])
+#define RSCAN0TMPTR55LL (RSCAN0.TMPTR55.UINT8[R_IO_LL])
+#define RSCAN0TMPTR55LH (RSCAN0.TMPTR55.UINT8[R_IO_LH])
+#define RSCAN0TMPTR55H (RSCAN0.TMPTR55.UINT16[R_IO_H])
+#define RSCAN0TMPTR55HL (RSCAN0.TMPTR55.UINT8[R_IO_HL])
+#define RSCAN0TMPTR55HH (RSCAN0.TMPTR55.UINT8[R_IO_HH])
+#define RSCAN0TMDF055 (RSCAN0.TMDF055.UINT32)
+#define RSCAN0TMDF055L (RSCAN0.TMDF055.UINT16[R_IO_L])
+#define RSCAN0TMDF055LL (RSCAN0.TMDF055.UINT8[R_IO_LL])
+#define RSCAN0TMDF055LH (RSCAN0.TMDF055.UINT8[R_IO_LH])
+#define RSCAN0TMDF055H (RSCAN0.TMDF055.UINT16[R_IO_H])
+#define RSCAN0TMDF055HL (RSCAN0.TMDF055.UINT8[R_IO_HL])
+#define RSCAN0TMDF055HH (RSCAN0.TMDF055.UINT8[R_IO_HH])
+#define RSCAN0TMDF155 (RSCAN0.TMDF155.UINT32)
+#define RSCAN0TMDF155L (RSCAN0.TMDF155.UINT16[R_IO_L])
+#define RSCAN0TMDF155LL (RSCAN0.TMDF155.UINT8[R_IO_LL])
+#define RSCAN0TMDF155LH (RSCAN0.TMDF155.UINT8[R_IO_LH])
+#define RSCAN0TMDF155H (RSCAN0.TMDF155.UINT16[R_IO_H])
+#define RSCAN0TMDF155HL (RSCAN0.TMDF155.UINT8[R_IO_HL])
+#define RSCAN0TMDF155HH (RSCAN0.TMDF155.UINT8[R_IO_HH])
+#define RSCAN0TMID56 (RSCAN0.TMID56.UINT32)
+#define RSCAN0TMID56L (RSCAN0.TMID56.UINT16[R_IO_L])
+#define RSCAN0TMID56LL (RSCAN0.TMID56.UINT8[R_IO_LL])
+#define RSCAN0TMID56LH (RSCAN0.TMID56.UINT8[R_IO_LH])
+#define RSCAN0TMID56H (RSCAN0.TMID56.UINT16[R_IO_H])
+#define RSCAN0TMID56HL (RSCAN0.TMID56.UINT8[R_IO_HL])
+#define RSCAN0TMID56HH (RSCAN0.TMID56.UINT8[R_IO_HH])
+#define RSCAN0TMPTR56 (RSCAN0.TMPTR56.UINT32)
+#define RSCAN0TMPTR56L (RSCAN0.TMPTR56.UINT16[R_IO_L])
+#define RSCAN0TMPTR56LL (RSCAN0.TMPTR56.UINT8[R_IO_LL])
+#define RSCAN0TMPTR56LH (RSCAN0.TMPTR56.UINT8[R_IO_LH])
+#define RSCAN0TMPTR56H (RSCAN0.TMPTR56.UINT16[R_IO_H])
+#define RSCAN0TMPTR56HL (RSCAN0.TMPTR56.UINT8[R_IO_HL])
+#define RSCAN0TMPTR56HH (RSCAN0.TMPTR56.UINT8[R_IO_HH])
+#define RSCAN0TMDF056 (RSCAN0.TMDF056.UINT32)
+#define RSCAN0TMDF056L (RSCAN0.TMDF056.UINT16[R_IO_L])
+#define RSCAN0TMDF056LL (RSCAN0.TMDF056.UINT8[R_IO_LL])
+#define RSCAN0TMDF056LH (RSCAN0.TMDF056.UINT8[R_IO_LH])
+#define RSCAN0TMDF056H (RSCAN0.TMDF056.UINT16[R_IO_H])
+#define RSCAN0TMDF056HL (RSCAN0.TMDF056.UINT8[R_IO_HL])
+#define RSCAN0TMDF056HH (RSCAN0.TMDF056.UINT8[R_IO_HH])
+#define RSCAN0TMDF156 (RSCAN0.TMDF156.UINT32)
+#define RSCAN0TMDF156L (RSCAN0.TMDF156.UINT16[R_IO_L])
+#define RSCAN0TMDF156LL (RSCAN0.TMDF156.UINT8[R_IO_LL])
+#define RSCAN0TMDF156LH (RSCAN0.TMDF156.UINT8[R_IO_LH])
+#define RSCAN0TMDF156H (RSCAN0.TMDF156.UINT16[R_IO_H])
+#define RSCAN0TMDF156HL (RSCAN0.TMDF156.UINT8[R_IO_HL])
+#define RSCAN0TMDF156HH (RSCAN0.TMDF156.UINT8[R_IO_HH])
+#define RSCAN0TMID57 (RSCAN0.TMID57.UINT32)
+#define RSCAN0TMID57L (RSCAN0.TMID57.UINT16[R_IO_L])
+#define RSCAN0TMID57LL (RSCAN0.TMID57.UINT8[R_IO_LL])
+#define RSCAN0TMID57LH (RSCAN0.TMID57.UINT8[R_IO_LH])
+#define RSCAN0TMID57H (RSCAN0.TMID57.UINT16[R_IO_H])
+#define RSCAN0TMID57HL (RSCAN0.TMID57.UINT8[R_IO_HL])
+#define RSCAN0TMID57HH (RSCAN0.TMID57.UINT8[R_IO_HH])
+#define RSCAN0TMPTR57 (RSCAN0.TMPTR57.UINT32)
+#define RSCAN0TMPTR57L (RSCAN0.TMPTR57.UINT16[R_IO_L])
+#define RSCAN0TMPTR57LL (RSCAN0.TMPTR57.UINT8[R_IO_LL])
+#define RSCAN0TMPTR57LH (RSCAN0.TMPTR57.UINT8[R_IO_LH])
+#define RSCAN0TMPTR57H (RSCAN0.TMPTR57.UINT16[R_IO_H])
+#define RSCAN0TMPTR57HL (RSCAN0.TMPTR57.UINT8[R_IO_HL])
+#define RSCAN0TMPTR57HH (RSCAN0.TMPTR57.UINT8[R_IO_HH])
+#define RSCAN0TMDF057 (RSCAN0.TMDF057.UINT32)
+#define RSCAN0TMDF057L (RSCAN0.TMDF057.UINT16[R_IO_L])
+#define RSCAN0TMDF057LL (RSCAN0.TMDF057.UINT8[R_IO_LL])
+#define RSCAN0TMDF057LH (RSCAN0.TMDF057.UINT8[R_IO_LH])
+#define RSCAN0TMDF057H (RSCAN0.TMDF057.UINT16[R_IO_H])
+#define RSCAN0TMDF057HL (RSCAN0.TMDF057.UINT8[R_IO_HL])
+#define RSCAN0TMDF057HH (RSCAN0.TMDF057.UINT8[R_IO_HH])
+#define RSCAN0TMDF157 (RSCAN0.TMDF157.UINT32)
+#define RSCAN0TMDF157L (RSCAN0.TMDF157.UINT16[R_IO_L])
+#define RSCAN0TMDF157LL (RSCAN0.TMDF157.UINT8[R_IO_LL])
+#define RSCAN0TMDF157LH (RSCAN0.TMDF157.UINT8[R_IO_LH])
+#define RSCAN0TMDF157H (RSCAN0.TMDF157.UINT16[R_IO_H])
+#define RSCAN0TMDF157HL (RSCAN0.TMDF157.UINT8[R_IO_HL])
+#define RSCAN0TMDF157HH (RSCAN0.TMDF157.UINT8[R_IO_HH])
+#define RSCAN0TMID58 (RSCAN0.TMID58.UINT32)
+#define RSCAN0TMID58L (RSCAN0.TMID58.UINT16[R_IO_L])
+#define RSCAN0TMID58LL (RSCAN0.TMID58.UINT8[R_IO_LL])
+#define RSCAN0TMID58LH (RSCAN0.TMID58.UINT8[R_IO_LH])
+#define RSCAN0TMID58H (RSCAN0.TMID58.UINT16[R_IO_H])
+#define RSCAN0TMID58HL (RSCAN0.TMID58.UINT8[R_IO_HL])
+#define RSCAN0TMID58HH (RSCAN0.TMID58.UINT8[R_IO_HH])
+#define RSCAN0TMPTR58 (RSCAN0.TMPTR58.UINT32)
+#define RSCAN0TMPTR58L (RSCAN0.TMPTR58.UINT16[R_IO_L])
+#define RSCAN0TMPTR58LL (RSCAN0.TMPTR58.UINT8[R_IO_LL])
+#define RSCAN0TMPTR58LH (RSCAN0.TMPTR58.UINT8[R_IO_LH])
+#define RSCAN0TMPTR58H (RSCAN0.TMPTR58.UINT16[R_IO_H])
+#define RSCAN0TMPTR58HL (RSCAN0.TMPTR58.UINT8[R_IO_HL])
+#define RSCAN0TMPTR58HH (RSCAN0.TMPTR58.UINT8[R_IO_HH])
+#define RSCAN0TMDF058 (RSCAN0.TMDF058.UINT32)
+#define RSCAN0TMDF058L (RSCAN0.TMDF058.UINT16[R_IO_L])
+#define RSCAN0TMDF058LL (RSCAN0.TMDF058.UINT8[R_IO_LL])
+#define RSCAN0TMDF058LH (RSCAN0.TMDF058.UINT8[R_IO_LH])
+#define RSCAN0TMDF058H (RSCAN0.TMDF058.UINT16[R_IO_H])
+#define RSCAN0TMDF058HL (RSCAN0.TMDF058.UINT8[R_IO_HL])
+#define RSCAN0TMDF058HH (RSCAN0.TMDF058.UINT8[R_IO_HH])
+#define RSCAN0TMDF158 (RSCAN0.TMDF158.UINT32)
+#define RSCAN0TMDF158L (RSCAN0.TMDF158.UINT16[R_IO_L])
+#define RSCAN0TMDF158LL (RSCAN0.TMDF158.UINT8[R_IO_LL])
+#define RSCAN0TMDF158LH (RSCAN0.TMDF158.UINT8[R_IO_LH])
+#define RSCAN0TMDF158H (RSCAN0.TMDF158.UINT16[R_IO_H])
+#define RSCAN0TMDF158HL (RSCAN0.TMDF158.UINT8[R_IO_HL])
+#define RSCAN0TMDF158HH (RSCAN0.TMDF158.UINT8[R_IO_HH])
+#define RSCAN0TMID59 (RSCAN0.TMID59.UINT32)
+#define RSCAN0TMID59L (RSCAN0.TMID59.UINT16[R_IO_L])
+#define RSCAN0TMID59LL (RSCAN0.TMID59.UINT8[R_IO_LL])
+#define RSCAN0TMID59LH (RSCAN0.TMID59.UINT8[R_IO_LH])
+#define RSCAN0TMID59H (RSCAN0.TMID59.UINT16[R_IO_H])
+#define RSCAN0TMID59HL (RSCAN0.TMID59.UINT8[R_IO_HL])
+#define RSCAN0TMID59HH (RSCAN0.TMID59.UINT8[R_IO_HH])
+#define RSCAN0TMPTR59 (RSCAN0.TMPTR59.UINT32)
+#define RSCAN0TMPTR59L (RSCAN0.TMPTR59.UINT16[R_IO_L])
+#define RSCAN0TMPTR59LL (RSCAN0.TMPTR59.UINT8[R_IO_LL])
+#define RSCAN0TMPTR59LH (RSCAN0.TMPTR59.UINT8[R_IO_LH])
+#define RSCAN0TMPTR59H (RSCAN0.TMPTR59.UINT16[R_IO_H])
+#define RSCAN0TMPTR59HL (RSCAN0.TMPTR59.UINT8[R_IO_HL])
+#define RSCAN0TMPTR59HH (RSCAN0.TMPTR59.UINT8[R_IO_HH])
+#define RSCAN0TMDF059 (RSCAN0.TMDF059.UINT32)
+#define RSCAN0TMDF059L (RSCAN0.TMDF059.UINT16[R_IO_L])
+#define RSCAN0TMDF059LL (RSCAN0.TMDF059.UINT8[R_IO_LL])
+#define RSCAN0TMDF059LH (RSCAN0.TMDF059.UINT8[R_IO_LH])
+#define RSCAN0TMDF059H (RSCAN0.TMDF059.UINT16[R_IO_H])
+#define RSCAN0TMDF059HL (RSCAN0.TMDF059.UINT8[R_IO_HL])
+#define RSCAN0TMDF059HH (RSCAN0.TMDF059.UINT8[R_IO_HH])
+#define RSCAN0TMDF159 (RSCAN0.TMDF159.UINT32)
+#define RSCAN0TMDF159L (RSCAN0.TMDF159.UINT16[R_IO_L])
+#define RSCAN0TMDF159LL (RSCAN0.TMDF159.UINT8[R_IO_LL])
+#define RSCAN0TMDF159LH (RSCAN0.TMDF159.UINT8[R_IO_LH])
+#define RSCAN0TMDF159H (RSCAN0.TMDF159.UINT16[R_IO_H])
+#define RSCAN0TMDF159HL (RSCAN0.TMDF159.UINT8[R_IO_HL])
+#define RSCAN0TMDF159HH (RSCAN0.TMDF159.UINT8[R_IO_HH])
+#define RSCAN0TMID60 (RSCAN0.TMID60.UINT32)
+#define RSCAN0TMID60L (RSCAN0.TMID60.UINT16[R_IO_L])
+#define RSCAN0TMID60LL (RSCAN0.TMID60.UINT8[R_IO_LL])
+#define RSCAN0TMID60LH (RSCAN0.TMID60.UINT8[R_IO_LH])
+#define RSCAN0TMID60H (RSCAN0.TMID60.UINT16[R_IO_H])
+#define RSCAN0TMID60HL (RSCAN0.TMID60.UINT8[R_IO_HL])
+#define RSCAN0TMID60HH (RSCAN0.TMID60.UINT8[R_IO_HH])
+#define RSCAN0TMPTR60 (RSCAN0.TMPTR60.UINT32)
+#define RSCAN0TMPTR60L (RSCAN0.TMPTR60.UINT16[R_IO_L])
+#define RSCAN0TMPTR60LL (RSCAN0.TMPTR60.UINT8[R_IO_LL])
+#define RSCAN0TMPTR60LH (RSCAN0.TMPTR60.UINT8[R_IO_LH])
+#define RSCAN0TMPTR60H (RSCAN0.TMPTR60.UINT16[R_IO_H])
+#define RSCAN0TMPTR60HL (RSCAN0.TMPTR60.UINT8[R_IO_HL])
+#define RSCAN0TMPTR60HH (RSCAN0.TMPTR60.UINT8[R_IO_HH])
+#define RSCAN0TMDF060 (RSCAN0.TMDF060.UINT32)
+#define RSCAN0TMDF060L (RSCAN0.TMDF060.UINT16[R_IO_L])
+#define RSCAN0TMDF060LL (RSCAN0.TMDF060.UINT8[R_IO_LL])
+#define RSCAN0TMDF060LH (RSCAN0.TMDF060.UINT8[R_IO_LH])
+#define RSCAN0TMDF060H (RSCAN0.TMDF060.UINT16[R_IO_H])
+#define RSCAN0TMDF060HL (RSCAN0.TMDF060.UINT8[R_IO_HL])
+#define RSCAN0TMDF060HH (RSCAN0.TMDF060.UINT8[R_IO_HH])
+#define RSCAN0TMDF160 (RSCAN0.TMDF160.UINT32)
+#define RSCAN0TMDF160L (RSCAN0.TMDF160.UINT16[R_IO_L])
+#define RSCAN0TMDF160LL (RSCAN0.TMDF160.UINT8[R_IO_LL])
+#define RSCAN0TMDF160LH (RSCAN0.TMDF160.UINT8[R_IO_LH])
+#define RSCAN0TMDF160H (RSCAN0.TMDF160.UINT16[R_IO_H])
+#define RSCAN0TMDF160HL (RSCAN0.TMDF160.UINT8[R_IO_HL])
+#define RSCAN0TMDF160HH (RSCAN0.TMDF160.UINT8[R_IO_HH])
+#define RSCAN0TMID61 (RSCAN0.TMID61.UINT32)
+#define RSCAN0TMID61L (RSCAN0.TMID61.UINT16[R_IO_L])
+#define RSCAN0TMID61LL (RSCAN0.TMID61.UINT8[R_IO_LL])
+#define RSCAN0TMID61LH (RSCAN0.TMID61.UINT8[R_IO_LH])
+#define RSCAN0TMID61H (RSCAN0.TMID61.UINT16[R_IO_H])
+#define RSCAN0TMID61HL (RSCAN0.TMID61.UINT8[R_IO_HL])
+#define RSCAN0TMID61HH (RSCAN0.TMID61.UINT8[R_IO_HH])
+#define RSCAN0TMPTR61 (RSCAN0.TMPTR61.UINT32)
+#define RSCAN0TMPTR61L (RSCAN0.TMPTR61.UINT16[R_IO_L])
+#define RSCAN0TMPTR61LL (RSCAN0.TMPTR61.UINT8[R_IO_LL])
+#define RSCAN0TMPTR61LH (RSCAN0.TMPTR61.UINT8[R_IO_LH])
+#define RSCAN0TMPTR61H (RSCAN0.TMPTR61.UINT16[R_IO_H])
+#define RSCAN0TMPTR61HL (RSCAN0.TMPTR61.UINT8[R_IO_HL])
+#define RSCAN0TMPTR61HH (RSCAN0.TMPTR61.UINT8[R_IO_HH])
+#define RSCAN0TMDF061 (RSCAN0.TMDF061.UINT32)
+#define RSCAN0TMDF061L (RSCAN0.TMDF061.UINT16[R_IO_L])
+#define RSCAN0TMDF061LL (RSCAN0.TMDF061.UINT8[R_IO_LL])
+#define RSCAN0TMDF061LH (RSCAN0.TMDF061.UINT8[R_IO_LH])
+#define RSCAN0TMDF061H (RSCAN0.TMDF061.UINT16[R_IO_H])
+#define RSCAN0TMDF061HL (RSCAN0.TMDF061.UINT8[R_IO_HL])
+#define RSCAN0TMDF061HH (RSCAN0.TMDF061.UINT8[R_IO_HH])
+#define RSCAN0TMDF161 (RSCAN0.TMDF161.UINT32)
+#define RSCAN0TMDF161L (RSCAN0.TMDF161.UINT16[R_IO_L])
+#define RSCAN0TMDF161LL (RSCAN0.TMDF161.UINT8[R_IO_LL])
+#define RSCAN0TMDF161LH (RSCAN0.TMDF161.UINT8[R_IO_LH])
+#define RSCAN0TMDF161H (RSCAN0.TMDF161.UINT16[R_IO_H])
+#define RSCAN0TMDF161HL (RSCAN0.TMDF161.UINT8[R_IO_HL])
+#define RSCAN0TMDF161HH (RSCAN0.TMDF161.UINT8[R_IO_HH])
+#define RSCAN0TMID62 (RSCAN0.TMID62.UINT32)
+#define RSCAN0TMID62L (RSCAN0.TMID62.UINT16[R_IO_L])
+#define RSCAN0TMID62LL (RSCAN0.TMID62.UINT8[R_IO_LL])
+#define RSCAN0TMID62LH (RSCAN0.TMID62.UINT8[R_IO_LH])
+#define RSCAN0TMID62H (RSCAN0.TMID62.UINT16[R_IO_H])
+#define RSCAN0TMID62HL (RSCAN0.TMID62.UINT8[R_IO_HL])
+#define RSCAN0TMID62HH (RSCAN0.TMID62.UINT8[R_IO_HH])
+#define RSCAN0TMPTR62 (RSCAN0.TMPTR62.UINT32)
+#define RSCAN0TMPTR62L (RSCAN0.TMPTR62.UINT16[R_IO_L])
+#define RSCAN0TMPTR62LL (RSCAN0.TMPTR62.UINT8[R_IO_LL])
+#define RSCAN0TMPTR62LH (RSCAN0.TMPTR62.UINT8[R_IO_LH])
+#define RSCAN0TMPTR62H (RSCAN0.TMPTR62.UINT16[R_IO_H])
+#define RSCAN0TMPTR62HL (RSCAN0.TMPTR62.UINT8[R_IO_HL])
+#define RSCAN0TMPTR62HH (RSCAN0.TMPTR62.UINT8[R_IO_HH])
+#define RSCAN0TMDF062 (RSCAN0.TMDF062.UINT32)
+#define RSCAN0TMDF062L (RSCAN0.TMDF062.UINT16[R_IO_L])
+#define RSCAN0TMDF062LL (RSCAN0.TMDF062.UINT8[R_IO_LL])
+#define RSCAN0TMDF062LH (RSCAN0.TMDF062.UINT8[R_IO_LH])
+#define RSCAN0TMDF062H (RSCAN0.TMDF062.UINT16[R_IO_H])
+#define RSCAN0TMDF062HL (RSCAN0.TMDF062.UINT8[R_IO_HL])
+#define RSCAN0TMDF062HH (RSCAN0.TMDF062.UINT8[R_IO_HH])
+#define RSCAN0TMDF162 (RSCAN0.TMDF162.UINT32)
+#define RSCAN0TMDF162L (RSCAN0.TMDF162.UINT16[R_IO_L])
+#define RSCAN0TMDF162LL (RSCAN0.TMDF162.UINT8[R_IO_LL])
+#define RSCAN0TMDF162LH (RSCAN0.TMDF162.UINT8[R_IO_LH])
+#define RSCAN0TMDF162H (RSCAN0.TMDF162.UINT16[R_IO_H])
+#define RSCAN0TMDF162HL (RSCAN0.TMDF162.UINT8[R_IO_HL])
+#define RSCAN0TMDF162HH (RSCAN0.TMDF162.UINT8[R_IO_HH])
+#define RSCAN0TMID63 (RSCAN0.TMID63.UINT32)
+#define RSCAN0TMID63L (RSCAN0.TMID63.UINT16[R_IO_L])
+#define RSCAN0TMID63LL (RSCAN0.TMID63.UINT8[R_IO_LL])
+#define RSCAN0TMID63LH (RSCAN0.TMID63.UINT8[R_IO_LH])
+#define RSCAN0TMID63H (RSCAN0.TMID63.UINT16[R_IO_H])
+#define RSCAN0TMID63HL (RSCAN0.TMID63.UINT8[R_IO_HL])
+#define RSCAN0TMID63HH (RSCAN0.TMID63.UINT8[R_IO_HH])
+#define RSCAN0TMPTR63 (RSCAN0.TMPTR63.UINT32)
+#define RSCAN0TMPTR63L (RSCAN0.TMPTR63.UINT16[R_IO_L])
+#define RSCAN0TMPTR63LL (RSCAN0.TMPTR63.UINT8[R_IO_LL])
+#define RSCAN0TMPTR63LH (RSCAN0.TMPTR63.UINT8[R_IO_LH])
+#define RSCAN0TMPTR63H (RSCAN0.TMPTR63.UINT16[R_IO_H])
+#define RSCAN0TMPTR63HL (RSCAN0.TMPTR63.UINT8[R_IO_HL])
+#define RSCAN0TMPTR63HH (RSCAN0.TMPTR63.UINT8[R_IO_HH])
+#define RSCAN0TMDF063 (RSCAN0.TMDF063.UINT32)
+#define RSCAN0TMDF063L (RSCAN0.TMDF063.UINT16[R_IO_L])
+#define RSCAN0TMDF063LL (RSCAN0.TMDF063.UINT8[R_IO_LL])
+#define RSCAN0TMDF063LH (RSCAN0.TMDF063.UINT8[R_IO_LH])
+#define RSCAN0TMDF063H (RSCAN0.TMDF063.UINT16[R_IO_H])
+#define RSCAN0TMDF063HL (RSCAN0.TMDF063.UINT8[R_IO_HL])
+#define RSCAN0TMDF063HH (RSCAN0.TMDF063.UINT8[R_IO_HH])
+#define RSCAN0TMDF163 (RSCAN0.TMDF163.UINT32)
+#define RSCAN0TMDF163L (RSCAN0.TMDF163.UINT16[R_IO_L])
+#define RSCAN0TMDF163LL (RSCAN0.TMDF163.UINT8[R_IO_LL])
+#define RSCAN0TMDF163LH (RSCAN0.TMDF163.UINT8[R_IO_LH])
+#define RSCAN0TMDF163H (RSCAN0.TMDF163.UINT16[R_IO_H])
+#define RSCAN0TMDF163HL (RSCAN0.TMDF163.UINT8[R_IO_HL])
+#define RSCAN0TMDF163HH (RSCAN0.TMDF163.UINT8[R_IO_HH])
+#define RSCAN0TMID64 (RSCAN0.TMID64.UINT32)
+#define RSCAN0TMID64L (RSCAN0.TMID64.UINT16[R_IO_L])
+#define RSCAN0TMID64LL (RSCAN0.TMID64.UINT8[R_IO_LL])
+#define RSCAN0TMID64LH (RSCAN0.TMID64.UINT8[R_IO_LH])
+#define RSCAN0TMID64H (RSCAN0.TMID64.UINT16[R_IO_H])
+#define RSCAN0TMID64HL (RSCAN0.TMID64.UINT8[R_IO_HL])
+#define RSCAN0TMID64HH (RSCAN0.TMID64.UINT8[R_IO_HH])
+#define RSCAN0TMPTR64 (RSCAN0.TMPTR64.UINT32)
+#define RSCAN0TMPTR64L (RSCAN0.TMPTR64.UINT16[R_IO_L])
+#define RSCAN0TMPTR64LL (RSCAN0.TMPTR64.UINT8[R_IO_LL])
+#define RSCAN0TMPTR64LH (RSCAN0.TMPTR64.UINT8[R_IO_LH])
+#define RSCAN0TMPTR64H (RSCAN0.TMPTR64.UINT16[R_IO_H])
+#define RSCAN0TMPTR64HL (RSCAN0.TMPTR64.UINT8[R_IO_HL])
+#define RSCAN0TMPTR64HH (RSCAN0.TMPTR64.UINT8[R_IO_HH])
+#define RSCAN0TMDF064 (RSCAN0.TMDF064.UINT32)
+#define RSCAN0TMDF064L (RSCAN0.TMDF064.UINT16[R_IO_L])
+#define RSCAN0TMDF064LL (RSCAN0.TMDF064.UINT8[R_IO_LL])
+#define RSCAN0TMDF064LH (RSCAN0.TMDF064.UINT8[R_IO_LH])
+#define RSCAN0TMDF064H (RSCAN0.TMDF064.UINT16[R_IO_H])
+#define RSCAN0TMDF064HL (RSCAN0.TMDF064.UINT8[R_IO_HL])
+#define RSCAN0TMDF064HH (RSCAN0.TMDF064.UINT8[R_IO_HH])
+#define RSCAN0TMDF164 (RSCAN0.TMDF164.UINT32)
+#define RSCAN0TMDF164L (RSCAN0.TMDF164.UINT16[R_IO_L])
+#define RSCAN0TMDF164LL (RSCAN0.TMDF164.UINT8[R_IO_LL])
+#define RSCAN0TMDF164LH (RSCAN0.TMDF164.UINT8[R_IO_LH])
+#define RSCAN0TMDF164H (RSCAN0.TMDF164.UINT16[R_IO_H])
+#define RSCAN0TMDF164HL (RSCAN0.TMDF164.UINT8[R_IO_HL])
+#define RSCAN0TMDF164HH (RSCAN0.TMDF164.UINT8[R_IO_HH])
+#define RSCAN0TMID65 (RSCAN0.TMID65.UINT32)
+#define RSCAN0TMID65L (RSCAN0.TMID65.UINT16[R_IO_L])
+#define RSCAN0TMID65LL (RSCAN0.TMID65.UINT8[R_IO_LL])
+#define RSCAN0TMID65LH (RSCAN0.TMID65.UINT8[R_IO_LH])
+#define RSCAN0TMID65H (RSCAN0.TMID65.UINT16[R_IO_H])
+#define RSCAN0TMID65HL (RSCAN0.TMID65.UINT8[R_IO_HL])
+#define RSCAN0TMID65HH (RSCAN0.TMID65.UINT8[R_IO_HH])
+#define RSCAN0TMPTR65 (RSCAN0.TMPTR65.UINT32)
+#define RSCAN0TMPTR65L (RSCAN0.TMPTR65.UINT16[R_IO_L])
+#define RSCAN0TMPTR65LL (RSCAN0.TMPTR65.UINT8[R_IO_LL])
+#define RSCAN0TMPTR65LH (RSCAN0.TMPTR65.UINT8[R_IO_LH])
+#define RSCAN0TMPTR65H (RSCAN0.TMPTR65.UINT16[R_IO_H])
+#define RSCAN0TMPTR65HL (RSCAN0.TMPTR65.UINT8[R_IO_HL])
+#define RSCAN0TMPTR65HH (RSCAN0.TMPTR65.UINT8[R_IO_HH])
+#define RSCAN0TMDF065 (RSCAN0.TMDF065.UINT32)
+#define RSCAN0TMDF065L (RSCAN0.TMDF065.UINT16[R_IO_L])
+#define RSCAN0TMDF065LL (RSCAN0.TMDF065.UINT8[R_IO_LL])
+#define RSCAN0TMDF065LH (RSCAN0.TMDF065.UINT8[R_IO_LH])
+#define RSCAN0TMDF065H (RSCAN0.TMDF065.UINT16[R_IO_H])
+#define RSCAN0TMDF065HL (RSCAN0.TMDF065.UINT8[R_IO_HL])
+#define RSCAN0TMDF065HH (RSCAN0.TMDF065.UINT8[R_IO_HH])
+#define RSCAN0TMDF165 (RSCAN0.TMDF165.UINT32)
+#define RSCAN0TMDF165L (RSCAN0.TMDF165.UINT16[R_IO_L])
+#define RSCAN0TMDF165LL (RSCAN0.TMDF165.UINT8[R_IO_LL])
+#define RSCAN0TMDF165LH (RSCAN0.TMDF165.UINT8[R_IO_LH])
+#define RSCAN0TMDF165H (RSCAN0.TMDF165.UINT16[R_IO_H])
+#define RSCAN0TMDF165HL (RSCAN0.TMDF165.UINT8[R_IO_HL])
+#define RSCAN0TMDF165HH (RSCAN0.TMDF165.UINT8[R_IO_HH])
+#define RSCAN0TMID66 (RSCAN0.TMID66.UINT32)
+#define RSCAN0TMID66L (RSCAN0.TMID66.UINT16[R_IO_L])
+#define RSCAN0TMID66LL (RSCAN0.TMID66.UINT8[R_IO_LL])
+#define RSCAN0TMID66LH (RSCAN0.TMID66.UINT8[R_IO_LH])
+#define RSCAN0TMID66H (RSCAN0.TMID66.UINT16[R_IO_H])
+#define RSCAN0TMID66HL (RSCAN0.TMID66.UINT8[R_IO_HL])
+#define RSCAN0TMID66HH (RSCAN0.TMID66.UINT8[R_IO_HH])
+#define RSCAN0TMPTR66 (RSCAN0.TMPTR66.UINT32)
+#define RSCAN0TMPTR66L (RSCAN0.TMPTR66.UINT16[R_IO_L])
+#define RSCAN0TMPTR66LL (RSCAN0.TMPTR66.UINT8[R_IO_LL])
+#define RSCAN0TMPTR66LH (RSCAN0.TMPTR66.UINT8[R_IO_LH])
+#define RSCAN0TMPTR66H (RSCAN0.TMPTR66.UINT16[R_IO_H])
+#define RSCAN0TMPTR66HL (RSCAN0.TMPTR66.UINT8[R_IO_HL])
+#define RSCAN0TMPTR66HH (RSCAN0.TMPTR66.UINT8[R_IO_HH])
+#define RSCAN0TMDF066 (RSCAN0.TMDF066.UINT32)
+#define RSCAN0TMDF066L (RSCAN0.TMDF066.UINT16[R_IO_L])
+#define RSCAN0TMDF066LL (RSCAN0.TMDF066.UINT8[R_IO_LL])
+#define RSCAN0TMDF066LH (RSCAN0.TMDF066.UINT8[R_IO_LH])
+#define RSCAN0TMDF066H (RSCAN0.TMDF066.UINT16[R_IO_H])
+#define RSCAN0TMDF066HL (RSCAN0.TMDF066.UINT8[R_IO_HL])
+#define RSCAN0TMDF066HH (RSCAN0.TMDF066.UINT8[R_IO_HH])
+#define RSCAN0TMDF166 (RSCAN0.TMDF166.UINT32)
+#define RSCAN0TMDF166L (RSCAN0.TMDF166.UINT16[R_IO_L])
+#define RSCAN0TMDF166LL (RSCAN0.TMDF166.UINT8[R_IO_LL])
+#define RSCAN0TMDF166LH (RSCAN0.TMDF166.UINT8[R_IO_LH])
+#define RSCAN0TMDF166H (RSCAN0.TMDF166.UINT16[R_IO_H])
+#define RSCAN0TMDF166HL (RSCAN0.TMDF166.UINT8[R_IO_HL])
+#define RSCAN0TMDF166HH (RSCAN0.TMDF166.UINT8[R_IO_HH])
+#define RSCAN0TMID67 (RSCAN0.TMID67.UINT32)
+#define RSCAN0TMID67L (RSCAN0.TMID67.UINT16[R_IO_L])
+#define RSCAN0TMID67LL (RSCAN0.TMID67.UINT8[R_IO_LL])
+#define RSCAN0TMID67LH (RSCAN0.TMID67.UINT8[R_IO_LH])
+#define RSCAN0TMID67H (RSCAN0.TMID67.UINT16[R_IO_H])
+#define RSCAN0TMID67HL (RSCAN0.TMID67.UINT8[R_IO_HL])
+#define RSCAN0TMID67HH (RSCAN0.TMID67.UINT8[R_IO_HH])
+#define RSCAN0TMPTR67 (RSCAN0.TMPTR67.UINT32)
+#define RSCAN0TMPTR67L (RSCAN0.TMPTR67.UINT16[R_IO_L])
+#define RSCAN0TMPTR67LL (RSCAN0.TMPTR67.UINT8[R_IO_LL])
+#define RSCAN0TMPTR67LH (RSCAN0.TMPTR67.UINT8[R_IO_LH])
+#define RSCAN0TMPTR67H (RSCAN0.TMPTR67.UINT16[R_IO_H])
+#define RSCAN0TMPTR67HL (RSCAN0.TMPTR67.UINT8[R_IO_HL])
+#define RSCAN0TMPTR67HH (RSCAN0.TMPTR67.UINT8[R_IO_HH])
+#define RSCAN0TMDF067 (RSCAN0.TMDF067.UINT32)
+#define RSCAN0TMDF067L (RSCAN0.TMDF067.UINT16[R_IO_L])
+#define RSCAN0TMDF067LL (RSCAN0.TMDF067.UINT8[R_IO_LL])
+#define RSCAN0TMDF067LH (RSCAN0.TMDF067.UINT8[R_IO_LH])
+#define RSCAN0TMDF067H (RSCAN0.TMDF067.UINT16[R_IO_H])
+#define RSCAN0TMDF067HL (RSCAN0.TMDF067.UINT8[R_IO_HL])
+#define RSCAN0TMDF067HH (RSCAN0.TMDF067.UINT8[R_IO_HH])
+#define RSCAN0TMDF167 (RSCAN0.TMDF167.UINT32)
+#define RSCAN0TMDF167L (RSCAN0.TMDF167.UINT16[R_IO_L])
+#define RSCAN0TMDF167LL (RSCAN0.TMDF167.UINT8[R_IO_LL])
+#define RSCAN0TMDF167LH (RSCAN0.TMDF167.UINT8[R_IO_LH])
+#define RSCAN0TMDF167H (RSCAN0.TMDF167.UINT16[R_IO_H])
+#define RSCAN0TMDF167HL (RSCAN0.TMDF167.UINT8[R_IO_HL])
+#define RSCAN0TMDF167HH (RSCAN0.TMDF167.UINT8[R_IO_HH])
+#define RSCAN0TMID68 (RSCAN0.TMID68.UINT32)
+#define RSCAN0TMID68L (RSCAN0.TMID68.UINT16[R_IO_L])
+#define RSCAN0TMID68LL (RSCAN0.TMID68.UINT8[R_IO_LL])
+#define RSCAN0TMID68LH (RSCAN0.TMID68.UINT8[R_IO_LH])
+#define RSCAN0TMID68H (RSCAN0.TMID68.UINT16[R_IO_H])
+#define RSCAN0TMID68HL (RSCAN0.TMID68.UINT8[R_IO_HL])
+#define RSCAN0TMID68HH (RSCAN0.TMID68.UINT8[R_IO_HH])
+#define RSCAN0TMPTR68 (RSCAN0.TMPTR68.UINT32)
+#define RSCAN0TMPTR68L (RSCAN0.TMPTR68.UINT16[R_IO_L])
+#define RSCAN0TMPTR68LL (RSCAN0.TMPTR68.UINT8[R_IO_LL])
+#define RSCAN0TMPTR68LH (RSCAN0.TMPTR68.UINT8[R_IO_LH])
+#define RSCAN0TMPTR68H (RSCAN0.TMPTR68.UINT16[R_IO_H])
+#define RSCAN0TMPTR68HL (RSCAN0.TMPTR68.UINT8[R_IO_HL])
+#define RSCAN0TMPTR68HH (RSCAN0.TMPTR68.UINT8[R_IO_HH])
+#define RSCAN0TMDF068 (RSCAN0.TMDF068.UINT32)
+#define RSCAN0TMDF068L (RSCAN0.TMDF068.UINT16[R_IO_L])
+#define RSCAN0TMDF068LL (RSCAN0.TMDF068.UINT8[R_IO_LL])
+#define RSCAN0TMDF068LH (RSCAN0.TMDF068.UINT8[R_IO_LH])
+#define RSCAN0TMDF068H (RSCAN0.TMDF068.UINT16[R_IO_H])
+#define RSCAN0TMDF068HL (RSCAN0.TMDF068.UINT8[R_IO_HL])
+#define RSCAN0TMDF068HH (RSCAN0.TMDF068.UINT8[R_IO_HH])
+#define RSCAN0TMDF168 (RSCAN0.TMDF168.UINT32)
+#define RSCAN0TMDF168L (RSCAN0.TMDF168.UINT16[R_IO_L])
+#define RSCAN0TMDF168LL (RSCAN0.TMDF168.UINT8[R_IO_LL])
+#define RSCAN0TMDF168LH (RSCAN0.TMDF168.UINT8[R_IO_LH])
+#define RSCAN0TMDF168H (RSCAN0.TMDF168.UINT16[R_IO_H])
+#define RSCAN0TMDF168HL (RSCAN0.TMDF168.UINT8[R_IO_HL])
+#define RSCAN0TMDF168HH (RSCAN0.TMDF168.UINT8[R_IO_HH])
+#define RSCAN0TMID69 (RSCAN0.TMID69.UINT32)
+#define RSCAN0TMID69L (RSCAN0.TMID69.UINT16[R_IO_L])
+#define RSCAN0TMID69LL (RSCAN0.TMID69.UINT8[R_IO_LL])
+#define RSCAN0TMID69LH (RSCAN0.TMID69.UINT8[R_IO_LH])
+#define RSCAN0TMID69H (RSCAN0.TMID69.UINT16[R_IO_H])
+#define RSCAN0TMID69HL (RSCAN0.TMID69.UINT8[R_IO_HL])
+#define RSCAN0TMID69HH (RSCAN0.TMID69.UINT8[R_IO_HH])
+#define RSCAN0TMPTR69 (RSCAN0.TMPTR69.UINT32)
+#define RSCAN0TMPTR69L (RSCAN0.TMPTR69.UINT16[R_IO_L])
+#define RSCAN0TMPTR69LL (RSCAN0.TMPTR69.UINT8[R_IO_LL])
+#define RSCAN0TMPTR69LH (RSCAN0.TMPTR69.UINT8[R_IO_LH])
+#define RSCAN0TMPTR69H (RSCAN0.TMPTR69.UINT16[R_IO_H])
+#define RSCAN0TMPTR69HL (RSCAN0.TMPTR69.UINT8[R_IO_HL])
+#define RSCAN0TMPTR69HH (RSCAN0.TMPTR69.UINT8[R_IO_HH])
+#define RSCAN0TMDF069 (RSCAN0.TMDF069.UINT32)
+#define RSCAN0TMDF069L (RSCAN0.TMDF069.UINT16[R_IO_L])
+#define RSCAN0TMDF069LL (RSCAN0.TMDF069.UINT8[R_IO_LL])
+#define RSCAN0TMDF069LH (RSCAN0.TMDF069.UINT8[R_IO_LH])
+#define RSCAN0TMDF069H (RSCAN0.TMDF069.UINT16[R_IO_H])
+#define RSCAN0TMDF069HL (RSCAN0.TMDF069.UINT8[R_IO_HL])
+#define RSCAN0TMDF069HH (RSCAN0.TMDF069.UINT8[R_IO_HH])
+#define RSCAN0TMDF169 (RSCAN0.TMDF169.UINT32)
+#define RSCAN0TMDF169L (RSCAN0.TMDF169.UINT16[R_IO_L])
+#define RSCAN0TMDF169LL (RSCAN0.TMDF169.UINT8[R_IO_LL])
+#define RSCAN0TMDF169LH (RSCAN0.TMDF169.UINT8[R_IO_LH])
+#define RSCAN0TMDF169H (RSCAN0.TMDF169.UINT16[R_IO_H])
+#define RSCAN0TMDF169HL (RSCAN0.TMDF169.UINT8[R_IO_HL])
+#define RSCAN0TMDF169HH (RSCAN0.TMDF169.UINT8[R_IO_HH])
+#define RSCAN0TMID70 (RSCAN0.TMID70.UINT32)
+#define RSCAN0TMID70L (RSCAN0.TMID70.UINT16[R_IO_L])
+#define RSCAN0TMID70LL (RSCAN0.TMID70.UINT8[R_IO_LL])
+#define RSCAN0TMID70LH (RSCAN0.TMID70.UINT8[R_IO_LH])
+#define RSCAN0TMID70H (RSCAN0.TMID70.UINT16[R_IO_H])
+#define RSCAN0TMID70HL (RSCAN0.TMID70.UINT8[R_IO_HL])
+#define RSCAN0TMID70HH (RSCAN0.TMID70.UINT8[R_IO_HH])
+#define RSCAN0TMPTR70 (RSCAN0.TMPTR70.UINT32)
+#define RSCAN0TMPTR70L (RSCAN0.TMPTR70.UINT16[R_IO_L])
+#define RSCAN0TMPTR70LL (RSCAN0.TMPTR70.UINT8[R_IO_LL])
+#define RSCAN0TMPTR70LH (RSCAN0.TMPTR70.UINT8[R_IO_LH])
+#define RSCAN0TMPTR70H (RSCAN0.TMPTR70.UINT16[R_IO_H])
+#define RSCAN0TMPTR70HL (RSCAN0.TMPTR70.UINT8[R_IO_HL])
+#define RSCAN0TMPTR70HH (RSCAN0.TMPTR70.UINT8[R_IO_HH])
+#define RSCAN0TMDF070 (RSCAN0.TMDF070.UINT32)
+#define RSCAN0TMDF070L (RSCAN0.TMDF070.UINT16[R_IO_L])
+#define RSCAN0TMDF070LL (RSCAN0.TMDF070.UINT8[R_IO_LL])
+#define RSCAN0TMDF070LH (RSCAN0.TMDF070.UINT8[R_IO_LH])
+#define RSCAN0TMDF070H (RSCAN0.TMDF070.UINT16[R_IO_H])
+#define RSCAN0TMDF070HL (RSCAN0.TMDF070.UINT8[R_IO_HL])
+#define RSCAN0TMDF070HH (RSCAN0.TMDF070.UINT8[R_IO_HH])
+#define RSCAN0TMDF170 (RSCAN0.TMDF170.UINT32)
+#define RSCAN0TMDF170L (RSCAN0.TMDF170.UINT16[R_IO_L])
+#define RSCAN0TMDF170LL (RSCAN0.TMDF170.UINT8[R_IO_LL])
+#define RSCAN0TMDF170LH (RSCAN0.TMDF170.UINT8[R_IO_LH])
+#define RSCAN0TMDF170H (RSCAN0.TMDF170.UINT16[R_IO_H])
+#define RSCAN0TMDF170HL (RSCAN0.TMDF170.UINT8[R_IO_HL])
+#define RSCAN0TMDF170HH (RSCAN0.TMDF170.UINT8[R_IO_HH])
+#define RSCAN0TMID71 (RSCAN0.TMID71.UINT32)
+#define RSCAN0TMID71L (RSCAN0.TMID71.UINT16[R_IO_L])
+#define RSCAN0TMID71LL (RSCAN0.TMID71.UINT8[R_IO_LL])
+#define RSCAN0TMID71LH (RSCAN0.TMID71.UINT8[R_IO_LH])
+#define RSCAN0TMID71H (RSCAN0.TMID71.UINT16[R_IO_H])
+#define RSCAN0TMID71HL (RSCAN0.TMID71.UINT8[R_IO_HL])
+#define RSCAN0TMID71HH (RSCAN0.TMID71.UINT8[R_IO_HH])
+#define RSCAN0TMPTR71 (RSCAN0.TMPTR71.UINT32)
+#define RSCAN0TMPTR71L (RSCAN0.TMPTR71.UINT16[R_IO_L])
+#define RSCAN0TMPTR71LL (RSCAN0.TMPTR71.UINT8[R_IO_LL])
+#define RSCAN0TMPTR71LH (RSCAN0.TMPTR71.UINT8[R_IO_LH])
+#define RSCAN0TMPTR71H (RSCAN0.TMPTR71.UINT16[R_IO_H])
+#define RSCAN0TMPTR71HL (RSCAN0.TMPTR71.UINT8[R_IO_HL])
+#define RSCAN0TMPTR71HH (RSCAN0.TMPTR71.UINT8[R_IO_HH])
+#define RSCAN0TMDF071 (RSCAN0.TMDF071.UINT32)
+#define RSCAN0TMDF071L (RSCAN0.TMDF071.UINT16[R_IO_L])
+#define RSCAN0TMDF071LL (RSCAN0.TMDF071.UINT8[R_IO_LL])
+#define RSCAN0TMDF071LH (RSCAN0.TMDF071.UINT8[R_IO_LH])
+#define RSCAN0TMDF071H (RSCAN0.TMDF071.UINT16[R_IO_H])
+#define RSCAN0TMDF071HL (RSCAN0.TMDF071.UINT8[R_IO_HL])
+#define RSCAN0TMDF071HH (RSCAN0.TMDF071.UINT8[R_IO_HH])
+#define RSCAN0TMDF171 (RSCAN0.TMDF171.UINT32)
+#define RSCAN0TMDF171L (RSCAN0.TMDF171.UINT16[R_IO_L])
+#define RSCAN0TMDF171LL (RSCAN0.TMDF171.UINT8[R_IO_LL])
+#define RSCAN0TMDF171LH (RSCAN0.TMDF171.UINT8[R_IO_LH])
+#define RSCAN0TMDF171H (RSCAN0.TMDF171.UINT16[R_IO_H])
+#define RSCAN0TMDF171HL (RSCAN0.TMDF171.UINT8[R_IO_HL])
+#define RSCAN0TMDF171HH (RSCAN0.TMDF171.UINT8[R_IO_HH])
+#define RSCAN0TMID72 (RSCAN0.TMID72.UINT32)
+#define RSCAN0TMID72L (RSCAN0.TMID72.UINT16[R_IO_L])
+#define RSCAN0TMID72LL (RSCAN0.TMID72.UINT8[R_IO_LL])
+#define RSCAN0TMID72LH (RSCAN0.TMID72.UINT8[R_IO_LH])
+#define RSCAN0TMID72H (RSCAN0.TMID72.UINT16[R_IO_H])
+#define RSCAN0TMID72HL (RSCAN0.TMID72.UINT8[R_IO_HL])
+#define RSCAN0TMID72HH (RSCAN0.TMID72.UINT8[R_IO_HH])
+#define RSCAN0TMPTR72 (RSCAN0.TMPTR72.UINT32)
+#define RSCAN0TMPTR72L (RSCAN0.TMPTR72.UINT16[R_IO_L])
+#define RSCAN0TMPTR72LL (RSCAN0.TMPTR72.UINT8[R_IO_LL])
+#define RSCAN0TMPTR72LH (RSCAN0.TMPTR72.UINT8[R_IO_LH])
+#define RSCAN0TMPTR72H (RSCAN0.TMPTR72.UINT16[R_IO_H])
+#define RSCAN0TMPTR72HL (RSCAN0.TMPTR72.UINT8[R_IO_HL])
+#define RSCAN0TMPTR72HH (RSCAN0.TMPTR72.UINT8[R_IO_HH])
+#define RSCAN0TMDF072 (RSCAN0.TMDF072.UINT32)
+#define RSCAN0TMDF072L (RSCAN0.TMDF072.UINT16[R_IO_L])
+#define RSCAN0TMDF072LL (RSCAN0.TMDF072.UINT8[R_IO_LL])
+#define RSCAN0TMDF072LH (RSCAN0.TMDF072.UINT8[R_IO_LH])
+#define RSCAN0TMDF072H (RSCAN0.TMDF072.UINT16[R_IO_H])
+#define RSCAN0TMDF072HL (RSCAN0.TMDF072.UINT8[R_IO_HL])
+#define RSCAN0TMDF072HH (RSCAN0.TMDF072.UINT8[R_IO_HH])
+#define RSCAN0TMDF172 (RSCAN0.TMDF172.UINT32)
+#define RSCAN0TMDF172L (RSCAN0.TMDF172.UINT16[R_IO_L])
+#define RSCAN0TMDF172LL (RSCAN0.TMDF172.UINT8[R_IO_LL])
+#define RSCAN0TMDF172LH (RSCAN0.TMDF172.UINT8[R_IO_LH])
+#define RSCAN0TMDF172H (RSCAN0.TMDF172.UINT16[R_IO_H])
+#define RSCAN0TMDF172HL (RSCAN0.TMDF172.UINT8[R_IO_HL])
+#define RSCAN0TMDF172HH (RSCAN0.TMDF172.UINT8[R_IO_HH])
+#define RSCAN0TMID73 (RSCAN0.TMID73.UINT32)
+#define RSCAN0TMID73L (RSCAN0.TMID73.UINT16[R_IO_L])
+#define RSCAN0TMID73LL (RSCAN0.TMID73.UINT8[R_IO_LL])
+#define RSCAN0TMID73LH (RSCAN0.TMID73.UINT8[R_IO_LH])
+#define RSCAN0TMID73H (RSCAN0.TMID73.UINT16[R_IO_H])
+#define RSCAN0TMID73HL (RSCAN0.TMID73.UINT8[R_IO_HL])
+#define RSCAN0TMID73HH (RSCAN0.TMID73.UINT8[R_IO_HH])
+#define RSCAN0TMPTR73 (RSCAN0.TMPTR73.UINT32)
+#define RSCAN0TMPTR73L (RSCAN0.TMPTR73.UINT16[R_IO_L])
+#define RSCAN0TMPTR73LL (RSCAN0.TMPTR73.UINT8[R_IO_LL])
+#define RSCAN0TMPTR73LH (RSCAN0.TMPTR73.UINT8[R_IO_LH])
+#define RSCAN0TMPTR73H (RSCAN0.TMPTR73.UINT16[R_IO_H])
+#define RSCAN0TMPTR73HL (RSCAN0.TMPTR73.UINT8[R_IO_HL])
+#define RSCAN0TMPTR73HH (RSCAN0.TMPTR73.UINT8[R_IO_HH])
+#define RSCAN0TMDF073 (RSCAN0.TMDF073.UINT32)
+#define RSCAN0TMDF073L (RSCAN0.TMDF073.UINT16[R_IO_L])
+#define RSCAN0TMDF073LL (RSCAN0.TMDF073.UINT8[R_IO_LL])
+#define RSCAN0TMDF073LH (RSCAN0.TMDF073.UINT8[R_IO_LH])
+#define RSCAN0TMDF073H (RSCAN0.TMDF073.UINT16[R_IO_H])
+#define RSCAN0TMDF073HL (RSCAN0.TMDF073.UINT8[R_IO_HL])
+#define RSCAN0TMDF073HH (RSCAN0.TMDF073.UINT8[R_IO_HH])
+#define RSCAN0TMDF173 (RSCAN0.TMDF173.UINT32)
+#define RSCAN0TMDF173L (RSCAN0.TMDF173.UINT16[R_IO_L])
+#define RSCAN0TMDF173LL (RSCAN0.TMDF173.UINT8[R_IO_LL])
+#define RSCAN0TMDF173LH (RSCAN0.TMDF173.UINT8[R_IO_LH])
+#define RSCAN0TMDF173H (RSCAN0.TMDF173.UINT16[R_IO_H])
+#define RSCAN0TMDF173HL (RSCAN0.TMDF173.UINT8[R_IO_HL])
+#define RSCAN0TMDF173HH (RSCAN0.TMDF173.UINT8[R_IO_HH])
+#define RSCAN0TMID74 (RSCAN0.TMID74.UINT32)
+#define RSCAN0TMID74L (RSCAN0.TMID74.UINT16[R_IO_L])
+#define RSCAN0TMID74LL (RSCAN0.TMID74.UINT8[R_IO_LL])
+#define RSCAN0TMID74LH (RSCAN0.TMID74.UINT8[R_IO_LH])
+#define RSCAN0TMID74H (RSCAN0.TMID74.UINT16[R_IO_H])
+#define RSCAN0TMID74HL (RSCAN0.TMID74.UINT8[R_IO_HL])
+#define RSCAN0TMID74HH (RSCAN0.TMID74.UINT8[R_IO_HH])
+#define RSCAN0TMPTR74 (RSCAN0.TMPTR74.UINT32)
+#define RSCAN0TMPTR74L (RSCAN0.TMPTR74.UINT16[R_IO_L])
+#define RSCAN0TMPTR74LL (RSCAN0.TMPTR74.UINT8[R_IO_LL])
+#define RSCAN0TMPTR74LH (RSCAN0.TMPTR74.UINT8[R_IO_LH])
+#define RSCAN0TMPTR74H (RSCAN0.TMPTR74.UINT16[R_IO_H])
+#define RSCAN0TMPTR74HL (RSCAN0.TMPTR74.UINT8[R_IO_HL])
+#define RSCAN0TMPTR74HH (RSCAN0.TMPTR74.UINT8[R_IO_HH])
+#define RSCAN0TMDF074 (RSCAN0.TMDF074.UINT32)
+#define RSCAN0TMDF074L (RSCAN0.TMDF074.UINT16[R_IO_L])
+#define RSCAN0TMDF074LL (RSCAN0.TMDF074.UINT8[R_IO_LL])
+#define RSCAN0TMDF074LH (RSCAN0.TMDF074.UINT8[R_IO_LH])
+#define RSCAN0TMDF074H (RSCAN0.TMDF074.UINT16[R_IO_H])
+#define RSCAN0TMDF074HL (RSCAN0.TMDF074.UINT8[R_IO_HL])
+#define RSCAN0TMDF074HH (RSCAN0.TMDF074.UINT8[R_IO_HH])
+#define RSCAN0TMDF174 (RSCAN0.TMDF174.UINT32)
+#define RSCAN0TMDF174L (RSCAN0.TMDF174.UINT16[R_IO_L])
+#define RSCAN0TMDF174LL (RSCAN0.TMDF174.UINT8[R_IO_LL])
+#define RSCAN0TMDF174LH (RSCAN0.TMDF174.UINT8[R_IO_LH])
+#define RSCAN0TMDF174H (RSCAN0.TMDF174.UINT16[R_IO_H])
+#define RSCAN0TMDF174HL (RSCAN0.TMDF174.UINT8[R_IO_HL])
+#define RSCAN0TMDF174HH (RSCAN0.TMDF174.UINT8[R_IO_HH])
+#define RSCAN0TMID75 (RSCAN0.TMID75.UINT32)
+#define RSCAN0TMID75L (RSCAN0.TMID75.UINT16[R_IO_L])
+#define RSCAN0TMID75LL (RSCAN0.TMID75.UINT8[R_IO_LL])
+#define RSCAN0TMID75LH (RSCAN0.TMID75.UINT8[R_IO_LH])
+#define RSCAN0TMID75H (RSCAN0.TMID75.UINT16[R_IO_H])
+#define RSCAN0TMID75HL (RSCAN0.TMID75.UINT8[R_IO_HL])
+#define RSCAN0TMID75HH (RSCAN0.TMID75.UINT8[R_IO_HH])
+#define RSCAN0TMPTR75 (RSCAN0.TMPTR75.UINT32)
+#define RSCAN0TMPTR75L (RSCAN0.TMPTR75.UINT16[R_IO_L])
+#define RSCAN0TMPTR75LL (RSCAN0.TMPTR75.UINT8[R_IO_LL])
+#define RSCAN0TMPTR75LH (RSCAN0.TMPTR75.UINT8[R_IO_LH])
+#define RSCAN0TMPTR75H (RSCAN0.TMPTR75.UINT16[R_IO_H])
+#define RSCAN0TMPTR75HL (RSCAN0.TMPTR75.UINT8[R_IO_HL])
+#define RSCAN0TMPTR75HH (RSCAN0.TMPTR75.UINT8[R_IO_HH])
+#define RSCAN0TMDF075 (RSCAN0.TMDF075.UINT32)
+#define RSCAN0TMDF075L (RSCAN0.TMDF075.UINT16[R_IO_L])
+#define RSCAN0TMDF075LL (RSCAN0.TMDF075.UINT8[R_IO_LL])
+#define RSCAN0TMDF075LH (RSCAN0.TMDF075.UINT8[R_IO_LH])
+#define RSCAN0TMDF075H (RSCAN0.TMDF075.UINT16[R_IO_H])
+#define RSCAN0TMDF075HL (RSCAN0.TMDF075.UINT8[R_IO_HL])
+#define RSCAN0TMDF075HH (RSCAN0.TMDF075.UINT8[R_IO_HH])
+#define RSCAN0TMDF175 (RSCAN0.TMDF175.UINT32)
+#define RSCAN0TMDF175L (RSCAN0.TMDF175.UINT16[R_IO_L])
+#define RSCAN0TMDF175LL (RSCAN0.TMDF175.UINT8[R_IO_LL])
+#define RSCAN0TMDF175LH (RSCAN0.TMDF175.UINT8[R_IO_LH])
+#define RSCAN0TMDF175H (RSCAN0.TMDF175.UINT16[R_IO_H])
+#define RSCAN0TMDF175HL (RSCAN0.TMDF175.UINT8[R_IO_HL])
+#define RSCAN0TMDF175HH (RSCAN0.TMDF175.UINT8[R_IO_HH])
+#define RSCAN0TMID76 (RSCAN0.TMID76.UINT32)
+#define RSCAN0TMID76L (RSCAN0.TMID76.UINT16[R_IO_L])
+#define RSCAN0TMID76LL (RSCAN0.TMID76.UINT8[R_IO_LL])
+#define RSCAN0TMID76LH (RSCAN0.TMID76.UINT8[R_IO_LH])
+#define RSCAN0TMID76H (RSCAN0.TMID76.UINT16[R_IO_H])
+#define RSCAN0TMID76HL (RSCAN0.TMID76.UINT8[R_IO_HL])
+#define RSCAN0TMID76HH (RSCAN0.TMID76.UINT8[R_IO_HH])
+#define RSCAN0TMPTR76 (RSCAN0.TMPTR76.UINT32)
+#define RSCAN0TMPTR76L (RSCAN0.TMPTR76.UINT16[R_IO_L])
+#define RSCAN0TMPTR76LL (RSCAN0.TMPTR76.UINT8[R_IO_LL])
+#define RSCAN0TMPTR76LH (RSCAN0.TMPTR76.UINT8[R_IO_LH])
+#define RSCAN0TMPTR76H (RSCAN0.TMPTR76.UINT16[R_IO_H])
+#define RSCAN0TMPTR76HL (RSCAN0.TMPTR76.UINT8[R_IO_HL])
+#define RSCAN0TMPTR76HH (RSCAN0.TMPTR76.UINT8[R_IO_HH])
+#define RSCAN0TMDF076 (RSCAN0.TMDF076.UINT32)
+#define RSCAN0TMDF076L (RSCAN0.TMDF076.UINT16[R_IO_L])
+#define RSCAN0TMDF076LL (RSCAN0.TMDF076.UINT8[R_IO_LL])
+#define RSCAN0TMDF076LH (RSCAN0.TMDF076.UINT8[R_IO_LH])
+#define RSCAN0TMDF076H (RSCAN0.TMDF076.UINT16[R_IO_H])
+#define RSCAN0TMDF076HL (RSCAN0.TMDF076.UINT8[R_IO_HL])
+#define RSCAN0TMDF076HH (RSCAN0.TMDF076.UINT8[R_IO_HH])
+#define RSCAN0TMDF176 (RSCAN0.TMDF176.UINT32)
+#define RSCAN0TMDF176L (RSCAN0.TMDF176.UINT16[R_IO_L])
+#define RSCAN0TMDF176LL (RSCAN0.TMDF176.UINT8[R_IO_LL])
+#define RSCAN0TMDF176LH (RSCAN0.TMDF176.UINT8[R_IO_LH])
+#define RSCAN0TMDF176H (RSCAN0.TMDF176.UINT16[R_IO_H])
+#define RSCAN0TMDF176HL (RSCAN0.TMDF176.UINT8[R_IO_HL])
+#define RSCAN0TMDF176HH (RSCAN0.TMDF176.UINT8[R_IO_HH])
+#define RSCAN0TMID77 (RSCAN0.TMID77.UINT32)
+#define RSCAN0TMID77L (RSCAN0.TMID77.UINT16[R_IO_L])
+#define RSCAN0TMID77LL (RSCAN0.TMID77.UINT8[R_IO_LL])
+#define RSCAN0TMID77LH (RSCAN0.TMID77.UINT8[R_IO_LH])
+#define RSCAN0TMID77H (RSCAN0.TMID77.UINT16[R_IO_H])
+#define RSCAN0TMID77HL (RSCAN0.TMID77.UINT8[R_IO_HL])
+#define RSCAN0TMID77HH (RSCAN0.TMID77.UINT8[R_IO_HH])
+#define RSCAN0TMPTR77 (RSCAN0.TMPTR77.UINT32)
+#define RSCAN0TMPTR77L (RSCAN0.TMPTR77.UINT16[R_IO_L])
+#define RSCAN0TMPTR77LL (RSCAN0.TMPTR77.UINT8[R_IO_LL])
+#define RSCAN0TMPTR77LH (RSCAN0.TMPTR77.UINT8[R_IO_LH])
+#define RSCAN0TMPTR77H (RSCAN0.TMPTR77.UINT16[R_IO_H])
+#define RSCAN0TMPTR77HL (RSCAN0.TMPTR77.UINT8[R_IO_HL])
+#define RSCAN0TMPTR77HH (RSCAN0.TMPTR77.UINT8[R_IO_HH])
+#define RSCAN0TMDF077 (RSCAN0.TMDF077.UINT32)
+#define RSCAN0TMDF077L (RSCAN0.TMDF077.UINT16[R_IO_L])
+#define RSCAN0TMDF077LL (RSCAN0.TMDF077.UINT8[R_IO_LL])
+#define RSCAN0TMDF077LH (RSCAN0.TMDF077.UINT8[R_IO_LH])
+#define RSCAN0TMDF077H (RSCAN0.TMDF077.UINT16[R_IO_H])
+#define RSCAN0TMDF077HL (RSCAN0.TMDF077.UINT8[R_IO_HL])
+#define RSCAN0TMDF077HH (RSCAN0.TMDF077.UINT8[R_IO_HH])
+#define RSCAN0TMDF177 (RSCAN0.TMDF177.UINT32)
+#define RSCAN0TMDF177L (RSCAN0.TMDF177.UINT16[R_IO_L])
+#define RSCAN0TMDF177LL (RSCAN0.TMDF177.UINT8[R_IO_LL])
+#define RSCAN0TMDF177LH (RSCAN0.TMDF177.UINT8[R_IO_LH])
+#define RSCAN0TMDF177H (RSCAN0.TMDF177.UINT16[R_IO_H])
+#define RSCAN0TMDF177HL (RSCAN0.TMDF177.UINT8[R_IO_HL])
+#define RSCAN0TMDF177HH (RSCAN0.TMDF177.UINT8[R_IO_HH])
+#define RSCAN0TMID78 (RSCAN0.TMID78.UINT32)
+#define RSCAN0TMID78L (RSCAN0.TMID78.UINT16[R_IO_L])
+#define RSCAN0TMID78LL (RSCAN0.TMID78.UINT8[R_IO_LL])
+#define RSCAN0TMID78LH (RSCAN0.TMID78.UINT8[R_IO_LH])
+#define RSCAN0TMID78H (RSCAN0.TMID78.UINT16[R_IO_H])
+#define RSCAN0TMID78HL (RSCAN0.TMID78.UINT8[R_IO_HL])
+#define RSCAN0TMID78HH (RSCAN0.TMID78.UINT8[R_IO_HH])
+#define RSCAN0TMPTR78 (RSCAN0.TMPTR78.UINT32)
+#define RSCAN0TMPTR78L (RSCAN0.TMPTR78.UINT16[R_IO_L])
+#define RSCAN0TMPTR78LL (RSCAN0.TMPTR78.UINT8[R_IO_LL])
+#define RSCAN0TMPTR78LH (RSCAN0.TMPTR78.UINT8[R_IO_LH])
+#define RSCAN0TMPTR78H (RSCAN0.TMPTR78.UINT16[R_IO_H])
+#define RSCAN0TMPTR78HL (RSCAN0.TMPTR78.UINT8[R_IO_HL])
+#define RSCAN0TMPTR78HH (RSCAN0.TMPTR78.UINT8[R_IO_HH])
+#define RSCAN0TMDF078 (RSCAN0.TMDF078.UINT32)
+#define RSCAN0TMDF078L (RSCAN0.TMDF078.UINT16[R_IO_L])
+#define RSCAN0TMDF078LL (RSCAN0.TMDF078.UINT8[R_IO_LL])
+#define RSCAN0TMDF078LH (RSCAN0.TMDF078.UINT8[R_IO_LH])
+#define RSCAN0TMDF078H (RSCAN0.TMDF078.UINT16[R_IO_H])
+#define RSCAN0TMDF078HL (RSCAN0.TMDF078.UINT8[R_IO_HL])
+#define RSCAN0TMDF078HH (RSCAN0.TMDF078.UINT8[R_IO_HH])
+#define RSCAN0TMDF178 (RSCAN0.TMDF178.UINT32)
+#define RSCAN0TMDF178L (RSCAN0.TMDF178.UINT16[R_IO_L])
+#define RSCAN0TMDF178LL (RSCAN0.TMDF178.UINT8[R_IO_LL])
+#define RSCAN0TMDF178LH (RSCAN0.TMDF178.UINT8[R_IO_LH])
+#define RSCAN0TMDF178H (RSCAN0.TMDF178.UINT16[R_IO_H])
+#define RSCAN0TMDF178HL (RSCAN0.TMDF178.UINT8[R_IO_HL])
+#define RSCAN0TMDF178HH (RSCAN0.TMDF178.UINT8[R_IO_HH])
+#define RSCAN0TMID79 (RSCAN0.TMID79.UINT32)
+#define RSCAN0TMID79L (RSCAN0.TMID79.UINT16[R_IO_L])
+#define RSCAN0TMID79LL (RSCAN0.TMID79.UINT8[R_IO_LL])
+#define RSCAN0TMID79LH (RSCAN0.TMID79.UINT8[R_IO_LH])
+#define RSCAN0TMID79H (RSCAN0.TMID79.UINT16[R_IO_H])
+#define RSCAN0TMID79HL (RSCAN0.TMID79.UINT8[R_IO_HL])
+#define RSCAN0TMID79HH (RSCAN0.TMID79.UINT8[R_IO_HH])
+#define RSCAN0TMPTR79 (RSCAN0.TMPTR79.UINT32)
+#define RSCAN0TMPTR79L (RSCAN0.TMPTR79.UINT16[R_IO_L])
+#define RSCAN0TMPTR79LL (RSCAN0.TMPTR79.UINT8[R_IO_LL])
+#define RSCAN0TMPTR79LH (RSCAN0.TMPTR79.UINT8[R_IO_LH])
+#define RSCAN0TMPTR79H (RSCAN0.TMPTR79.UINT16[R_IO_H])
+#define RSCAN0TMPTR79HL (RSCAN0.TMPTR79.UINT8[R_IO_HL])
+#define RSCAN0TMPTR79HH (RSCAN0.TMPTR79.UINT8[R_IO_HH])
+#define RSCAN0TMDF079 (RSCAN0.TMDF079.UINT32)
+#define RSCAN0TMDF079L (RSCAN0.TMDF079.UINT16[R_IO_L])
+#define RSCAN0TMDF079LL (RSCAN0.TMDF079.UINT8[R_IO_LL])
+#define RSCAN0TMDF079LH (RSCAN0.TMDF079.UINT8[R_IO_LH])
+#define RSCAN0TMDF079H (RSCAN0.TMDF079.UINT16[R_IO_H])
+#define RSCAN0TMDF079HL (RSCAN0.TMDF079.UINT8[R_IO_HL])
+#define RSCAN0TMDF079HH (RSCAN0.TMDF079.UINT8[R_IO_HH])
+#define RSCAN0TMDF179 (RSCAN0.TMDF179.UINT32)
+#define RSCAN0TMDF179L (RSCAN0.TMDF179.UINT16[R_IO_L])
+#define RSCAN0TMDF179LL (RSCAN0.TMDF179.UINT8[R_IO_LL])
+#define RSCAN0TMDF179LH (RSCAN0.TMDF179.UINT8[R_IO_LH])
+#define RSCAN0TMDF179H (RSCAN0.TMDF179.UINT16[R_IO_H])
+#define RSCAN0TMDF179HL (RSCAN0.TMDF179.UINT8[R_IO_HL])
+#define RSCAN0TMDF179HH (RSCAN0.TMDF179.UINT8[R_IO_HH])
+#define RSCAN0THLACC0 (RSCAN0.THLACC0.UINT32)
+#define RSCAN0THLACC0L (RSCAN0.THLACC0.UINT16[R_IO_L])
+#define RSCAN0THLACC0LL (RSCAN0.THLACC0.UINT8[R_IO_LL])
+#define RSCAN0THLACC0LH (RSCAN0.THLACC0.UINT8[R_IO_LH])
+#define RSCAN0THLACC0H (RSCAN0.THLACC0.UINT16[R_IO_H])
+#define RSCAN0THLACC0HL (RSCAN0.THLACC0.UINT8[R_IO_HL])
+#define RSCAN0THLACC0HH (RSCAN0.THLACC0.UINT8[R_IO_HH])
+#define RSCAN0THLACC1 (RSCAN0.THLACC1.UINT32)
+#define RSCAN0THLACC1L (RSCAN0.THLACC1.UINT16[R_IO_L])
+#define RSCAN0THLACC1LL (RSCAN0.THLACC1.UINT8[R_IO_LL])
+#define RSCAN0THLACC1LH (RSCAN0.THLACC1.UINT8[R_IO_LH])
+#define RSCAN0THLACC1H (RSCAN0.THLACC1.UINT16[R_IO_H])
+#define RSCAN0THLACC1HL (RSCAN0.THLACC1.UINT8[R_IO_HL])
+#define RSCAN0THLACC1HH (RSCAN0.THLACC1.UINT8[R_IO_HH])
+#define RSCAN0THLACC2 (RSCAN0.THLACC2.UINT32)
+#define RSCAN0THLACC2L (RSCAN0.THLACC2.UINT16[R_IO_L])
+#define RSCAN0THLACC2LL (RSCAN0.THLACC2.UINT8[R_IO_LL])
+#define RSCAN0THLACC2LH (RSCAN0.THLACC2.UINT8[R_IO_LH])
+#define RSCAN0THLACC2H (RSCAN0.THLACC2.UINT16[R_IO_H])
+#define RSCAN0THLACC2HL (RSCAN0.THLACC2.UINT8[R_IO_HL])
+#define RSCAN0THLACC2HH (RSCAN0.THLACC2.UINT8[R_IO_HH])
+#define RSCAN0THLACC3 (RSCAN0.THLACC3.UINT32)
+#define RSCAN0THLACC3L (RSCAN0.THLACC3.UINT16[R_IO_L])
+#define RSCAN0THLACC3LL (RSCAN0.THLACC3.UINT8[R_IO_LL])
+#define RSCAN0THLACC3LH (RSCAN0.THLACC3.UINT8[R_IO_LH])
+#define RSCAN0THLACC3H (RSCAN0.THLACC3.UINT16[R_IO_H])
+#define RSCAN0THLACC3HL (RSCAN0.THLACC3.UINT8[R_IO_HL])
+#define RSCAN0THLACC3HH (RSCAN0.THLACC3.UINT8[R_IO_HH])
+#define RSCAN0THLACC4 (RSCAN0.THLACC4.UINT32)
+#define RSCAN0THLACC4L (RSCAN0.THLACC4.UINT16[R_IO_L])
+#define RSCAN0THLACC4LL (RSCAN0.THLACC4.UINT8[R_IO_LL])
+#define RSCAN0THLACC4LH (RSCAN0.THLACC4.UINT8[R_IO_LH])
+#define RSCAN0THLACC4H (RSCAN0.THLACC4.UINT16[R_IO_H])
+#define RSCAN0THLACC4HL (RSCAN0.THLACC4.UINT8[R_IO_HL])
+#define RSCAN0THLACC4HH (RSCAN0.THLACC4.UINT8[R_IO_HH])
+
+#define RSCAN0_GAFLCFG0_COUNT (2)
+#define RSCAN0_RMND0_COUNT (3)
+#define RSCAN0_RFCC0_COUNT (8)
+#define RSCAN0_RFSTS0_COUNT (8)
+#define RSCAN0_RFPCTR0_COUNT (8)
+#define RSCAN0_CFCC0_COUNT (15)
+#define RSCAN0_CFSTS0_COUNT (15)
+#define RSCAN0_CFPCTR0_COUNT (15)
+#define RSCAN0_TMC0_COUNT (80)
+#define RSCAN0_TMSTS0_COUNT (80)
+#define RSCAN0_TMTRSTS0_COUNT (3)
+#define RSCAN0_TMTARSTS0_COUNT (3)
+#define RSCAN0_TMTCSTS0_COUNT (3)
+#define RSCAN0_TMTASTS0_COUNT (3)
+#define RSCAN0_TMIEC0_COUNT (3)
+#define RSCAN0_TXQCC0_COUNT (5)
+#define RSCAN0_TXQSTS0_COUNT (5)
+#define RSCAN0_TXQPCTR0_COUNT (5)
+#define RSCAN0_THLCC0_COUNT (5)
+#define RSCAN0_THLSTS0_COUNT (5)
+#define RSCAN0_THLPCTR0_COUNT (5)
+#define RSCAN0_GTINTSTS0_COUNT (2)
+#define RSCAN0_THLACC0_COUNT (5)
+
+
+typedef struct st_rscan0
+{
+                                                           /* RSCAN0           */
+
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C0CFG;                         /*  C0CFG           */
+    union iodefine_reg32_t  C0CTR;                         /*  C0CTR           */
+    union iodefine_reg32_t  C0STS;                         /*  C0STS           */
+    union iodefine_reg32_t  C0ERFL;                        /*  C0ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C1CFG;                         /*  C1CFG           */
+    union iodefine_reg32_t  C1CTR;                         /*  C1CTR           */
+    union iodefine_reg32_t  C1STS;                         /*  C1STS           */
+    union iodefine_reg32_t  C1ERFL;                        /*  C1ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C2CFG;                         /*  C2CFG           */
+    union iodefine_reg32_t  C2CTR;                         /*  C2CTR           */
+    union iodefine_reg32_t  C2STS;                         /*  C2STS           */
+    union iodefine_reg32_t  C2ERFL;                        /*  C2ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C3CFG;                         /*  C3CFG           */
+    union iodefine_reg32_t  C3CTR;                         /*  C3CTR           */
+    union iodefine_reg32_t  C3STS;                         /*  C3STS           */
+    union iodefine_reg32_t  C3ERFL;                        /*  C3ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+/* start of struct st_rscan_from_rscan0cncfg */
+    union iodefine_reg32_t  C4CFG;                         /*  C4CFG           */
+    union iodefine_reg32_t  C4CTR;                         /*  C4CTR           */
+    union iodefine_reg32_t  C4STS;                         /*  C4STS           */
+    union iodefine_reg32_t  C4ERFL;                        /*  C4ERFL          */
+
+/* end of struct st_rscan_from_rscan0cncfg */
+    
+    volatile uint8_t   dummy159[52];                           /*                  */
+    union iodefine_reg32_t  GCFG;                          /*  GCFG            */
+    union iodefine_reg32_t  GCTR;                          /*  GCTR            */
+    union iodefine_reg32_t  GSTS;                          /*  GSTS            */
+    union iodefine_reg32_t  GERFL;                         /*  GERFL           */
+    union iodefine_reg32_16_t  GTSC;                       /*  GTSC            */
+    union iodefine_reg32_t  GAFLECTR;                      /*  GAFLECTR        */
+
+/* #define RSCAN0_GAFLCFG0_COUNT (2) */
+    union iodefine_reg32_t  GAFLCFG0;                      /*  GAFLCFG0        */
+    union iodefine_reg32_t  GAFLCFG1;                      /*  GAFLCFG1        */
+    union iodefine_reg32_t  RMNB;                          /*  RMNB            */
+
+/* #define RSCAN0_RMND0_COUNT (3) */
+    union iodefine_reg32_t  RMND0;                         /*  RMND0           */
+    union iodefine_reg32_t  RMND1;                         /*  RMND1           */
+    union iodefine_reg32_t  RMND2;                         /*  RMND2           */
+    
+    volatile uint8_t   dummy160[4];                            /*                  */
+
+/* #define RSCAN0_RFCC0_COUNT (8) */
+    union iodefine_reg32_t  RFCC0;                         /*  RFCC0           */
+    union iodefine_reg32_t  RFCC1;                         /*  RFCC1           */
+    union iodefine_reg32_t  RFCC2;                         /*  RFCC2           */
+    union iodefine_reg32_t  RFCC3;                         /*  RFCC3           */
+    union iodefine_reg32_t  RFCC4;                         /*  RFCC4           */
+    union iodefine_reg32_t  RFCC5;                         /*  RFCC5           */
+    union iodefine_reg32_t  RFCC6;                         /*  RFCC6           */
+    union iodefine_reg32_t  RFCC7;                         /*  RFCC7           */
+
+/* #define RSCAN0_RFSTS0_COUNT (8) */
+    union iodefine_reg32_t  RFSTS0;                        /*  RFSTS0          */
+    union iodefine_reg32_t  RFSTS1;                        /*  RFSTS1          */
+    union iodefine_reg32_t  RFSTS2;                        /*  RFSTS2          */
+    union iodefine_reg32_t  RFSTS3;                        /*  RFSTS3          */
+    union iodefine_reg32_t  RFSTS4;                        /*  RFSTS4          */
+    union iodefine_reg32_t  RFSTS5;                        /*  RFSTS5          */
+    union iodefine_reg32_t  RFSTS6;                        /*  RFSTS6          */
+    union iodefine_reg32_t  RFSTS7;                        /*  RFSTS7          */
+
+/* #define RSCAN0_RFPCTR0_COUNT (8) */
+    union iodefine_reg32_t  RFPCTR0;                       /*  RFPCTR0         */
+    union iodefine_reg32_t  RFPCTR1;                       /*  RFPCTR1         */
+    union iodefine_reg32_t  RFPCTR2;                       /*  RFPCTR2         */
+    union iodefine_reg32_t  RFPCTR3;                       /*  RFPCTR3         */
+    union iodefine_reg32_t  RFPCTR4;                       /*  RFPCTR4         */
+    union iodefine_reg32_t  RFPCTR5;                       /*  RFPCTR5         */
+    union iodefine_reg32_t  RFPCTR6;                       /*  RFPCTR6         */
+    union iodefine_reg32_t  RFPCTR7;                       /*  RFPCTR7         */
+
+/* #define RSCAN0_CFCC0_COUNT (15) */
+    union iodefine_reg32_t  CFCC0;                         /*  CFCC0           */
+    union iodefine_reg32_t  CFCC1;                         /*  CFCC1           */
+    union iodefine_reg32_t  CFCC2;                         /*  CFCC2           */
+    union iodefine_reg32_t  CFCC3;                         /*  CFCC3           */
+    union iodefine_reg32_t  CFCC4;                         /*  CFCC4           */
+    union iodefine_reg32_t  CFCC5;                         /*  CFCC5           */
+    union iodefine_reg32_t  CFCC6;                         /*  CFCC6           */
+    union iodefine_reg32_t  CFCC7;                         /*  CFCC7           */
+    union iodefine_reg32_t  CFCC8;                         /*  CFCC8           */
+    union iodefine_reg32_t  CFCC9;                         /*  CFCC9           */
+    union iodefine_reg32_t  CFCC10;                        /*  CFCC10          */
+    union iodefine_reg32_t  CFCC11;                        /*  CFCC11          */
+    union iodefine_reg32_t  CFCC12;                        /*  CFCC12          */
+    union iodefine_reg32_t  CFCC13;                        /*  CFCC13          */
+    union iodefine_reg32_t  CFCC14;                        /*  CFCC14          */
+    
+    volatile uint8_t   dummy161[36];                           /*                  */
+
+/* #define RSCAN0_CFSTS0_COUNT (15) */
+    union iodefine_reg32_t  CFSTS0;                        /*  CFSTS0          */
+    union iodefine_reg32_t  CFSTS1;                        /*  CFSTS1          */
+    union iodefine_reg32_t  CFSTS2;                        /*  CFSTS2          */
+    union iodefine_reg32_t  CFSTS3;                        /*  CFSTS3          */
+    union iodefine_reg32_t  CFSTS4;                        /*  CFSTS4          */
+    union iodefine_reg32_t  CFSTS5;                        /*  CFSTS5          */
+    union iodefine_reg32_t  CFSTS6;                        /*  CFSTS6          */
+    union iodefine_reg32_t  CFSTS7;                        /*  CFSTS7          */
+    union iodefine_reg32_t  CFSTS8;                        /*  CFSTS8          */
+    union iodefine_reg32_t  CFSTS9;                        /*  CFSTS9          */
+    union iodefine_reg32_t  CFSTS10;                       /*  CFSTS10         */
+    union iodefine_reg32_t  CFSTS11;                       /*  CFSTS11         */
+    union iodefine_reg32_t  CFSTS12;                       /*  CFSTS12         */
+    union iodefine_reg32_t  CFSTS13;                       /*  CFSTS13         */
+    union iodefine_reg32_t  CFSTS14;                       /*  CFSTS14         */
+    
+    volatile uint8_t   dummy162[36];                           /*                  */
+
+/* #define RSCAN0_CFPCTR0_COUNT (15) */
+    union iodefine_reg32_t  CFPCTR0;                       /*  CFPCTR0         */
+    union iodefine_reg32_t  CFPCTR1;                       /*  CFPCTR1         */
+    union iodefine_reg32_t  CFPCTR2;                       /*  CFPCTR2         */
+    union iodefine_reg32_t  CFPCTR3;                       /*  CFPCTR3         */
+    union iodefine_reg32_t  CFPCTR4;                       /*  CFPCTR4         */
+    union iodefine_reg32_t  CFPCTR5;                       /*  CFPCTR5         */
+    union iodefine_reg32_t  CFPCTR6;                       /*  CFPCTR6         */
+    union iodefine_reg32_t  CFPCTR7;                       /*  CFPCTR7         */
+    union iodefine_reg32_t  CFPCTR8;                       /*  CFPCTR8         */
+    union iodefine_reg32_t  CFPCTR9;                       /*  CFPCTR9         */
+    union iodefine_reg32_t  CFPCTR10;                      /*  CFPCTR10        */
+    union iodefine_reg32_t  CFPCTR11;                      /*  CFPCTR11        */
+    union iodefine_reg32_t  CFPCTR12;                      /*  CFPCTR12        */
+    union iodefine_reg32_t  CFPCTR13;                      /*  CFPCTR13        */
+    union iodefine_reg32_t  CFPCTR14;                      /*  CFPCTR14        */
+    
+    volatile uint8_t   dummy163[36];                           /*                  */
+    union iodefine_reg32_t  FESTS;                         /*  FESTS           */
+    union iodefine_reg32_t  FFSTS;                         /*  FFSTS           */
+    union iodefine_reg32_t  FMSTS;                         /*  FMSTS           */
+    union iodefine_reg32_t  RFISTS;                        /*  RFISTS          */
+    union iodefine_reg32_t  CFRISTS;                       /*  CFRISTS         */
+    union iodefine_reg32_t  CFTISTS;                       /*  CFTISTS         */
+    
+
+/* #define RSCAN0_TMC0_COUNT (80) */
+    volatile uint8_t   TMC0;                                   /*  TMC0            */
+    volatile uint8_t   TMC1;                                   /*  TMC1            */
+    volatile uint8_t   TMC2;                                   /*  TMC2            */
+    volatile uint8_t   TMC3;                                   /*  TMC3            */
+    volatile uint8_t   TMC4;                                   /*  TMC4            */
+    volatile uint8_t   TMC5;                                   /*  TMC5            */
+    volatile uint8_t   TMC6;                                   /*  TMC6            */
+    volatile uint8_t   TMC7;                                   /*  TMC7            */
+    volatile uint8_t   TMC8;                                   /*  TMC8            */
+    volatile uint8_t   TMC9;                                   /*  TMC9            */
+    volatile uint8_t   TMC10;                                  /*  TMC10           */
+    volatile uint8_t   TMC11;                                  /*  TMC11           */
+    volatile uint8_t   TMC12;                                  /*  TMC12           */
+    volatile uint8_t   TMC13;                                  /*  TMC13           */
+    volatile uint8_t   TMC14;                                  /*  TMC14           */
+    volatile uint8_t   TMC15;                                  /*  TMC15           */
+    volatile uint8_t   TMC16;                                  /*  TMC16           */
+    volatile uint8_t   TMC17;                                  /*  TMC17           */
+    volatile uint8_t   TMC18;                                  /*  TMC18           */
+    volatile uint8_t   TMC19;                                  /*  TMC19           */
+    volatile uint8_t   TMC20;                                  /*  TMC20           */
+    volatile uint8_t   TMC21;                                  /*  TMC21           */
+    volatile uint8_t   TMC22;                                  /*  TMC22           */
+    volatile uint8_t   TMC23;                                  /*  TMC23           */
+    volatile uint8_t   TMC24;                                  /*  TMC24           */
+    volatile uint8_t   TMC25;                                  /*  TMC25           */
+    volatile uint8_t   TMC26;                                  /*  TMC26           */
+    volatile uint8_t   TMC27;                                  /*  TMC27           */
+    volatile uint8_t   TMC28;                                  /*  TMC28           */
+    volatile uint8_t   TMC29;                                  /*  TMC29           */
+    volatile uint8_t   TMC30;                                  /*  TMC30           */
+    volatile uint8_t   TMC31;                                  /*  TMC31           */
+    volatile uint8_t   TMC32;                                  /*  TMC32           */
+    volatile uint8_t   TMC33;                                  /*  TMC33           */
+    volatile uint8_t   TMC34;                                  /*  TMC34           */
+    volatile uint8_t   TMC35;                                  /*  TMC35           */
+    volatile uint8_t   TMC36;                                  /*  TMC36           */
+    volatile uint8_t   TMC37;                                  /*  TMC37           */
+    volatile uint8_t   TMC38;                                  /*  TMC38           */
+    volatile uint8_t   TMC39;                                  /*  TMC39           */
+    volatile uint8_t   TMC40;                                  /*  TMC40           */
+    volatile uint8_t   TMC41;                                  /*  TMC41           */
+    volatile uint8_t   TMC42;                                  /*  TMC42           */
+    volatile uint8_t   TMC43;                                  /*  TMC43           */
+    volatile uint8_t   TMC44;                                  /*  TMC44           */
+    volatile uint8_t   TMC45;                                  /*  TMC45           */
+    volatile uint8_t   TMC46;                                  /*  TMC46           */
+    volatile uint8_t   TMC47;                                  /*  TMC47           */
+    volatile uint8_t   TMC48;                                  /*  TMC48           */
+    volatile uint8_t   TMC49;                                  /*  TMC49           */
+    volatile uint8_t   TMC50;                                  /*  TMC50           */
+    volatile uint8_t   TMC51;                                  /*  TMC51           */
+    volatile uint8_t   TMC52;                                  /*  TMC52           */
+    volatile uint8_t   TMC53;                                  /*  TMC53           */
+    volatile uint8_t   TMC54;                                  /*  TMC54           */
+    volatile uint8_t   TMC55;                                  /*  TMC55           */
+    volatile uint8_t   TMC56;                                  /*  TMC56           */
+    volatile uint8_t   TMC57;                                  /*  TMC57           */
+    volatile uint8_t   TMC58;                                  /*  TMC58           */
+    volatile uint8_t   TMC59;                                  /*  TMC59           */
+    volatile uint8_t   TMC60;                                  /*  TMC60           */
+    volatile uint8_t   TMC61;                                  /*  TMC61           */
+    volatile uint8_t   TMC62;                                  /*  TMC62           */
+    volatile uint8_t   TMC63;                                  /*  TMC63           */
+    volatile uint8_t   TMC64;                                  /*  TMC64           */
+    volatile uint8_t   TMC65;                                  /*  TMC65           */
+    volatile uint8_t   TMC66;                                  /*  TMC66           */
+    volatile uint8_t   TMC67;                                  /*  TMC67           */
+    volatile uint8_t   TMC68;                                  /*  TMC68           */
+    volatile uint8_t   TMC69;                                  /*  TMC69           */
+    volatile uint8_t   TMC70;                                  /*  TMC70           */
+    volatile uint8_t   TMC71;                                  /*  TMC71           */
+    volatile uint8_t   TMC72;                                  /*  TMC72           */
+    volatile uint8_t   TMC73;                                  /*  TMC73           */
+    volatile uint8_t   TMC74;                                  /*  TMC74           */
+    volatile uint8_t   TMC75;                                  /*  TMC75           */
+    volatile uint8_t   TMC76;                                  /*  TMC76           */
+    volatile uint8_t   TMC77;                                  /*  TMC77           */
+    volatile uint8_t   TMC78;                                  /*  TMC78           */
+    volatile uint8_t   TMC79;                                  /*  TMC79           */
+    volatile uint8_t   dummy164[48];                           /*                  */
+
+/* #define RSCAN0_TMSTS0_COUNT (80) */
+    volatile uint8_t   TMSTS0;                                 /*  TMSTS0          */
+    volatile uint8_t   TMSTS1;                                 /*  TMSTS1          */
+    volatile uint8_t   TMSTS2;                                 /*  TMSTS2          */
+    volatile uint8_t   TMSTS3;                                 /*  TMSTS3          */
+    volatile uint8_t   TMSTS4;                                 /*  TMSTS4          */
+    volatile uint8_t   TMSTS5;                                 /*  TMSTS5          */
+    volatile uint8_t   TMSTS6;                                 /*  TMSTS6          */
+    volatile uint8_t   TMSTS7;                                 /*  TMSTS7          */
+    volatile uint8_t   TMSTS8;                                 /*  TMSTS8          */
+    volatile uint8_t   TMSTS9;                                 /*  TMSTS9          */
+    volatile uint8_t   TMSTS10;                                /*  TMSTS10         */
+    volatile uint8_t   TMSTS11;                                /*  TMSTS11         */
+    volatile uint8_t   TMSTS12;                                /*  TMSTS12         */
+    volatile uint8_t   TMSTS13;                                /*  TMSTS13         */
+    volatile uint8_t   TMSTS14;                                /*  TMSTS14         */
+    volatile uint8_t   TMSTS15;                                /*  TMSTS15         */
+    volatile uint8_t   TMSTS16;                                /*  TMSTS16         */
+    volatile uint8_t   TMSTS17;                                /*  TMSTS17         */
+    volatile uint8_t   TMSTS18;                                /*  TMSTS18         */
+    volatile uint8_t   TMSTS19;                                /*  TMSTS19         */
+    volatile uint8_t   TMSTS20;                                /*  TMSTS20         */
+    volatile uint8_t   TMSTS21;                                /*  TMSTS21         */
+    volatile uint8_t   TMSTS22;                                /*  TMSTS22         */
+    volatile uint8_t   TMSTS23;                                /*  TMSTS23         */
+    volatile uint8_t   TMSTS24;                                /*  TMSTS24         */
+    volatile uint8_t   TMSTS25;                                /*  TMSTS25         */
+    volatile uint8_t   TMSTS26;                                /*  TMSTS26         */
+    volatile uint8_t   TMSTS27;                                /*  TMSTS27         */
+    volatile uint8_t   TMSTS28;                                /*  TMSTS28         */
+    volatile uint8_t   TMSTS29;                                /*  TMSTS29         */
+    volatile uint8_t   TMSTS30;                                /*  TMSTS30         */
+    volatile uint8_t   TMSTS31;                                /*  TMSTS31         */
+    volatile uint8_t   TMSTS32;                                /*  TMSTS32         */
+    volatile uint8_t   TMSTS33;                                /*  TMSTS33         */
+    volatile uint8_t   TMSTS34;                                /*  TMSTS34         */
+    volatile uint8_t   TMSTS35;                                /*  TMSTS35         */
+    volatile uint8_t   TMSTS36;                                /*  TMSTS36         */
+    volatile uint8_t   TMSTS37;                                /*  TMSTS37         */
+    volatile uint8_t   TMSTS38;                                /*  TMSTS38         */
+    volatile uint8_t   TMSTS39;                                /*  TMSTS39         */
+    volatile uint8_t   TMSTS40;                                /*  TMSTS40         */
+    volatile uint8_t   TMSTS41;                                /*  TMSTS41         */
+    volatile uint8_t   TMSTS42;                                /*  TMSTS42         */
+    volatile uint8_t   TMSTS43;                                /*  TMSTS43         */
+    volatile uint8_t   TMSTS44;                                /*  TMSTS44         */
+    volatile uint8_t   TMSTS45;                                /*  TMSTS45         */
+    volatile uint8_t   TMSTS46;                                /*  TMSTS46         */
+    volatile uint8_t   TMSTS47;                                /*  TMSTS47         */
+    volatile uint8_t   TMSTS48;                                /*  TMSTS48         */
+    volatile uint8_t   TMSTS49;                                /*  TMSTS49         */
+    volatile uint8_t   TMSTS50;                                /*  TMSTS50         */
+    volatile uint8_t   TMSTS51;                                /*  TMSTS51         */
+    volatile uint8_t   TMSTS52;                                /*  TMSTS52         */
+    volatile uint8_t   TMSTS53;                                /*  TMSTS53         */
+    volatile uint8_t   TMSTS54;                                /*  TMSTS54         */
+    volatile uint8_t   TMSTS55;                                /*  TMSTS55         */
+    volatile uint8_t   TMSTS56;                                /*  TMSTS56         */
+    volatile uint8_t   TMSTS57;                                /*  TMSTS57         */
+    volatile uint8_t   TMSTS58;                                /*  TMSTS58         */
+    volatile uint8_t   TMSTS59;                                /*  TMSTS59         */
+    volatile uint8_t   TMSTS60;                                /*  TMSTS60         */
+    volatile uint8_t   TMSTS61;                                /*  TMSTS61         */
+    volatile uint8_t   TMSTS62;                                /*  TMSTS62         */
+    volatile uint8_t   TMSTS63;                                /*  TMSTS63         */
+    volatile uint8_t   TMSTS64;                                /*  TMSTS64         */
+    volatile uint8_t   TMSTS65;                                /*  TMSTS65         */
+    volatile uint8_t   TMSTS66;                                /*  TMSTS66         */
+    volatile uint8_t   TMSTS67;                                /*  TMSTS67         */
+    volatile uint8_t   TMSTS68;                                /*  TMSTS68         */
+    volatile uint8_t   TMSTS69;                                /*  TMSTS69         */
+    volatile uint8_t   TMSTS70;                                /*  TMSTS70         */
+    volatile uint8_t   TMSTS71;                                /*  TMSTS71         */
+    volatile uint8_t   TMSTS72;                                /*  TMSTS72         */
+    volatile uint8_t   TMSTS73;                                /*  TMSTS73         */
+    volatile uint8_t   TMSTS74;                                /*  TMSTS74         */
+    volatile uint8_t   TMSTS75;                                /*  TMSTS75         */
+    volatile uint8_t   TMSTS76;                                /*  TMSTS76         */
+    volatile uint8_t   TMSTS77;                                /*  TMSTS77         */
+    volatile uint8_t   TMSTS78;                                /*  TMSTS78         */
+    volatile uint8_t   TMSTS79;                                /*  TMSTS79         */
+    volatile uint8_t   dummy165[48];                           /*                  */
+
+/* #define RSCAN0_TMTRSTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTRSTS0;                      /*  TMTRSTS0        */
+    union iodefine_reg32_t  TMTRSTS1;                      /*  TMTRSTS1        */
+    union iodefine_reg32_t  TMTRSTS2;                      /*  TMTRSTS2        */
+    
+    volatile uint8_t   dummy166[4];                            /*                  */
+
+/* #define RSCAN0_TMTARSTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTARSTS0;                     /*  TMTARSTS0       */
+    union iodefine_reg32_t  TMTARSTS1;                     /*  TMTARSTS1       */
+    union iodefine_reg32_t  TMTARSTS2;                     /*  TMTARSTS2       */
+    
+    volatile uint8_t   dummy167[4];                            /*                  */
+
+/* #define RSCAN0_TMTCSTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTCSTS0;                      /*  TMTCSTS0        */
+    union iodefine_reg32_t  TMTCSTS1;                      /*  TMTCSTS1        */
+    union iodefine_reg32_t  TMTCSTS2;                      /*  TMTCSTS2        */
+    
+    volatile uint8_t   dummy168[4];                            /*                  */
+
+/* #define RSCAN0_TMTASTS0_COUNT (3) */
+    union iodefine_reg32_t  TMTASTS0;                      /*  TMTASTS0        */
+    union iodefine_reg32_t  TMTASTS1;                      /*  TMTASTS1        */
+    union iodefine_reg32_t  TMTASTS2;                      /*  TMTASTS2        */
+    
+    volatile uint8_t   dummy169[4];                            /*                  */
+
+/* #define RSCAN0_TMIEC0_COUNT (3) */
+    union iodefine_reg32_t  TMIEC0;                        /*  TMIEC0          */
+    union iodefine_reg32_t  TMIEC1;                        /*  TMIEC1          */
+    union iodefine_reg32_t  TMIEC2;                        /*  TMIEC2          */
+    
+    volatile uint8_t   dummy170[4];                            /*                  */
+
+/* #define RSCAN0_TXQCC0_COUNT (5) */
+    union iodefine_reg32_t  TXQCC0;                        /*  TXQCC0          */
+    union iodefine_reg32_t  TXQCC1;                        /*  TXQCC1          */
+    union iodefine_reg32_t  TXQCC2;                        /*  TXQCC2          */
+    union iodefine_reg32_t  TXQCC3;                        /*  TXQCC3          */
+    union iodefine_reg32_t  TXQCC4;                        /*  TXQCC4          */
+    
+    volatile uint8_t   dummy171[12];                           /*                  */
+
+/* #define RSCAN0_TXQSTS0_COUNT (5) */
+    union iodefine_reg32_t  TXQSTS0;                       /*  TXQSTS0         */
+    union iodefine_reg32_t  TXQSTS1;                       /*  TXQSTS1         */
+    union iodefine_reg32_t  TXQSTS2;                       /*  TXQSTS2         */
+    union iodefine_reg32_t  TXQSTS3;                       /*  TXQSTS3         */
+    union iodefine_reg32_t  TXQSTS4;                       /*  TXQSTS4         */
+    
+    volatile uint8_t   dummy172[12];                           /*                  */
+
+/* #define RSCAN0_TXQPCTR0_COUNT (5) */
+    union iodefine_reg32_t  TXQPCTR0;                      /*  TXQPCTR0        */
+    union iodefine_reg32_t  TXQPCTR1;                      /*  TXQPCTR1        */
+    union iodefine_reg32_t  TXQPCTR2;                      /*  TXQPCTR2        */
+    union iodefine_reg32_t  TXQPCTR3;                      /*  TXQPCTR3        */
+    union iodefine_reg32_t  TXQPCTR4;                      /*  TXQPCTR4        */
+    
+    volatile uint8_t   dummy173[12];                           /*                  */
+
+/* #define RSCAN0_THLCC0_COUNT (5) */
+    union iodefine_reg32_t  THLCC0;                        /*  THLCC0          */
+    union iodefine_reg32_t  THLCC1;                        /*  THLCC1          */
+    union iodefine_reg32_t  THLCC2;                        /*  THLCC2          */
+    union iodefine_reg32_t  THLCC3;                        /*  THLCC3          */
+    union iodefine_reg32_t  THLCC4;                        /*  THLCC4          */
+    
+    volatile uint8_t   dummy174[12];                           /*                  */
+
+/* #define RSCAN0_THLSTS0_COUNT (5) */
+    union iodefine_reg32_t  THLSTS0;                       /*  THLSTS0         */
+    union iodefine_reg32_t  THLSTS1;                       /*  THLSTS1         */
+    union iodefine_reg32_t  THLSTS2;                       /*  THLSTS2         */
+    union iodefine_reg32_t  THLSTS3;                       /*  THLSTS3         */
+    union iodefine_reg32_t  THLSTS4;                       /*  THLSTS4         */
+    
+    volatile uint8_t   dummy175[12];                           /*                  */
+
+/* #define RSCAN0_THLPCTR0_COUNT (5) */
+    union iodefine_reg32_t  THLPCTR0;                      /*  THLPCTR0        */
+    union iodefine_reg32_t  THLPCTR1;                      /*  THLPCTR1        */
+    union iodefine_reg32_t  THLPCTR2;                      /*  THLPCTR2        */
+    union iodefine_reg32_t  THLPCTR3;                      /*  THLPCTR3        */
+    union iodefine_reg32_t  THLPCTR4;                      /*  THLPCTR4        */
+    
+    volatile uint8_t   dummy176[12];                           /*                  */
+
+/* #define RSCAN0_GTINTSTS0_COUNT (2) */
+    union iodefine_reg32_t  GTINTSTS0;                     /*  GTINTSTS0       */
+    union iodefine_reg32_t  GTINTSTS1;                     /*  GTINTSTS1       */
+    union iodefine_reg32_t  GTSTCFG;                       /*  GTSTCFG         */
+    union iodefine_reg32_t  GTSTCTR;                       /*  GTSTCTR         */
+    
+    volatile uint8_t   dummy177[12];                           /*                  */
+    union iodefine_reg32_16_t  GLOCKK;                     /*  GLOCKK          */
+    
+    volatile uint8_t   dummy178[128];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID0;                       /*  GAFLID0         */
+    union iodefine_reg32_t  GAFLM0;                        /*  GAFLM0          */
+    union iodefine_reg32_t  GAFLP00;                       /*  GAFLP00         */
+    union iodefine_reg32_t  GAFLP10;                       /*  GAFLP10         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID1;                       /*  GAFLID1         */
+    union iodefine_reg32_t  GAFLM1;                        /*  GAFLM1          */
+    union iodefine_reg32_t  GAFLP01;                       /*  GAFLP01         */
+    union iodefine_reg32_t  GAFLP11;                       /*  GAFLP11         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID2;                       /*  GAFLID2         */
+    union iodefine_reg32_t  GAFLM2;                        /*  GAFLM2          */
+    union iodefine_reg32_t  GAFLP02;                       /*  GAFLP02         */
+    union iodefine_reg32_t  GAFLP12;                       /*  GAFLP12         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID3;                       /*  GAFLID3         */
+    union iodefine_reg32_t  GAFLM3;                        /*  GAFLM3          */
+    union iodefine_reg32_t  GAFLP03;                       /*  GAFLP03         */
+    union iodefine_reg32_t  GAFLP13;                       /*  GAFLP13         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID4;                       /*  GAFLID4         */
+    union iodefine_reg32_t  GAFLM4;                        /*  GAFLM4          */
+    union iodefine_reg32_t  GAFLP04;                       /*  GAFLP04         */
+    union iodefine_reg32_t  GAFLP14;                       /*  GAFLP14         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID5;                       /*  GAFLID5         */
+    union iodefine_reg32_t  GAFLM5;                        /*  GAFLM5          */
+    union iodefine_reg32_t  GAFLP05;                       /*  GAFLP05         */
+    union iodefine_reg32_t  GAFLP15;                       /*  GAFLP15         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID6;                       /*  GAFLID6         */
+    union iodefine_reg32_t  GAFLM6;                        /*  GAFLM6          */
+    union iodefine_reg32_t  GAFLP06;                       /*  GAFLP06         */
+    union iodefine_reg32_t  GAFLP16;                       /*  GAFLP16         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID7;                       /*  GAFLID7         */
+    union iodefine_reg32_t  GAFLM7;                        /*  GAFLM7          */
+    union iodefine_reg32_t  GAFLP07;                       /*  GAFLP07         */
+    union iodefine_reg32_t  GAFLP17;                       /*  GAFLP17         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID8;                       /*  GAFLID8         */
+    union iodefine_reg32_t  GAFLM8;                        /*  GAFLM8          */
+    union iodefine_reg32_t  GAFLP08;                       /*  GAFLP08         */
+    union iodefine_reg32_t  GAFLP18;                       /*  GAFLP18         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID9;                       /*  GAFLID9         */
+    union iodefine_reg32_t  GAFLM9;                        /*  GAFLM9          */
+    union iodefine_reg32_t  GAFLP09;                       /*  GAFLP09         */
+    union iodefine_reg32_t  GAFLP19;                       /*  GAFLP19         */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID10;                      /*  GAFLID10        */
+    union iodefine_reg32_t  GAFLM10;                       /*  GAFLM10         */
+    union iodefine_reg32_t  GAFLP010;                      /*  GAFLP010        */
+    union iodefine_reg32_t  GAFLP110;                      /*  GAFLP110        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID11;                      /*  GAFLID11        */
+    union iodefine_reg32_t  GAFLM11;                       /*  GAFLM11         */
+    union iodefine_reg32_t  GAFLP011;                      /*  GAFLP011        */
+    union iodefine_reg32_t  GAFLP111;                      /*  GAFLP111        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID12;                      /*  GAFLID12        */
+    union iodefine_reg32_t  GAFLM12;                       /*  GAFLM12         */
+    union iodefine_reg32_t  GAFLP012;                      /*  GAFLP012        */
+    union iodefine_reg32_t  GAFLP112;                      /*  GAFLP112        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID13;                      /*  GAFLID13        */
+    union iodefine_reg32_t  GAFLM13;                       /*  GAFLM13         */
+    union iodefine_reg32_t  GAFLP013;                      /*  GAFLP013        */
+    union iodefine_reg32_t  GAFLP113;                      /*  GAFLP113        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID14;                      /*  GAFLID14        */
+    union iodefine_reg32_t  GAFLM14;                       /*  GAFLM14         */
+    union iodefine_reg32_t  GAFLP014;                      /*  GAFLP014        */
+    union iodefine_reg32_t  GAFLP114;                      /*  GAFLP114        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0gaflidj */
+    union iodefine_reg32_t  GAFLID15;                      /*  GAFLID15        */
+    union iodefine_reg32_t  GAFLM15;                       /*  GAFLM15         */
+    union iodefine_reg32_t  GAFLP015;                      /*  GAFLP015        */
+    union iodefine_reg32_t  GAFLP115;                      /*  GAFLP115        */
+
+/* end of struct st_rscan_from_rscan0gaflidj */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID0;                         /*  RMID0           */
+    union iodefine_reg32_t  RMPTR0;                        /*  RMPTR0          */
+    union iodefine_reg32_t  RMDF00;                        /*  RMDF00          */
+    union iodefine_reg32_t  RMDF10;                        /*  RMDF10          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID1;                         /*  RMID1           */
+    union iodefine_reg32_t  RMPTR1;                        /*  RMPTR1          */
+    union iodefine_reg32_t  RMDF01;                        /*  RMDF01          */
+    union iodefine_reg32_t  RMDF11;                        /*  RMDF11          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID2;                         /*  RMID2           */
+    union iodefine_reg32_t  RMPTR2;                        /*  RMPTR2          */
+    union iodefine_reg32_t  RMDF02;                        /*  RMDF02          */
+    union iodefine_reg32_t  RMDF12;                        /*  RMDF12          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID3;                         /*  RMID3           */
+    union iodefine_reg32_t  RMPTR3;                        /*  RMPTR3          */
+    union iodefine_reg32_t  RMDF03;                        /*  RMDF03          */
+    union iodefine_reg32_t  RMDF13;                        /*  RMDF13          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID4;                         /*  RMID4           */
+    union iodefine_reg32_t  RMPTR4;                        /*  RMPTR4          */
+    union iodefine_reg32_t  RMDF04;                        /*  RMDF04          */
+    union iodefine_reg32_t  RMDF14;                        /*  RMDF14          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID5;                         /*  RMID5           */
+    union iodefine_reg32_t  RMPTR5;                        /*  RMPTR5          */
+    union iodefine_reg32_t  RMDF05;                        /*  RMDF05          */
+    union iodefine_reg32_t  RMDF15;                        /*  RMDF15          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID6;                         /*  RMID6           */
+    union iodefine_reg32_t  RMPTR6;                        /*  RMPTR6          */
+    union iodefine_reg32_t  RMDF06;                        /*  RMDF06          */
+    union iodefine_reg32_t  RMDF16;                        /*  RMDF16          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID7;                         /*  RMID7           */
+    union iodefine_reg32_t  RMPTR7;                        /*  RMPTR7          */
+    union iodefine_reg32_t  RMDF07;                        /*  RMDF07          */
+    union iodefine_reg32_t  RMDF17;                        /*  RMDF17          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID8;                         /*  RMID8           */
+    union iodefine_reg32_t  RMPTR8;                        /*  RMPTR8          */
+    union iodefine_reg32_t  RMDF08;                        /*  RMDF08          */
+    union iodefine_reg32_t  RMDF18;                        /*  RMDF18          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID9;                         /*  RMID9           */
+    union iodefine_reg32_t  RMPTR9;                        /*  RMPTR9          */
+    union iodefine_reg32_t  RMDF09;                        /*  RMDF09          */
+    union iodefine_reg32_t  RMDF19;                        /*  RMDF19          */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID10;                        /*  RMID10          */
+    union iodefine_reg32_t  RMPTR10;                       /*  RMPTR10         */
+    union iodefine_reg32_t  RMDF010;                       /*  RMDF010         */
+    union iodefine_reg32_t  RMDF110;                       /*  RMDF110         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID11;                        /*  RMID11          */
+    union iodefine_reg32_t  RMPTR11;                       /*  RMPTR11         */
+    union iodefine_reg32_t  RMDF011;                       /*  RMDF011         */
+    union iodefine_reg32_t  RMDF111;                       /*  RMDF111         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID12;                        /*  RMID12          */
+    union iodefine_reg32_t  RMPTR12;                       /*  RMPTR12         */
+    union iodefine_reg32_t  RMDF012;                       /*  RMDF012         */
+    union iodefine_reg32_t  RMDF112;                       /*  RMDF112         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID13;                        /*  RMID13          */
+    union iodefine_reg32_t  RMPTR13;                       /*  RMPTR13         */
+    union iodefine_reg32_t  RMDF013;                       /*  RMDF013         */
+    union iodefine_reg32_t  RMDF113;                       /*  RMDF113         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID14;                        /*  RMID14          */
+    union iodefine_reg32_t  RMPTR14;                       /*  RMPTR14         */
+    union iodefine_reg32_t  RMDF014;                       /*  RMDF014         */
+    union iodefine_reg32_t  RMDF114;                       /*  RMDF114         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID15;                        /*  RMID15          */
+    union iodefine_reg32_t  RMPTR15;                       /*  RMPTR15         */
+    union iodefine_reg32_t  RMDF015;                       /*  RMDF015         */
+    union iodefine_reg32_t  RMDF115;                       /*  RMDF115         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID16;                        /*  RMID16          */
+    union iodefine_reg32_t  RMPTR16;                       /*  RMPTR16         */
+    union iodefine_reg32_t  RMDF016;                       /*  RMDF016         */
+    union iodefine_reg32_t  RMDF116;                       /*  RMDF116         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID17;                        /*  RMID17          */
+    union iodefine_reg32_t  RMPTR17;                       /*  RMPTR17         */
+    union iodefine_reg32_t  RMDF017;                       /*  RMDF017         */
+    union iodefine_reg32_t  RMDF117;                       /*  RMDF117         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID18;                        /*  RMID18          */
+    union iodefine_reg32_t  RMPTR18;                       /*  RMPTR18         */
+    union iodefine_reg32_t  RMDF018;                       /*  RMDF018         */
+    union iodefine_reg32_t  RMDF118;                       /*  RMDF118         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID19;                        /*  RMID19          */
+    union iodefine_reg32_t  RMPTR19;                       /*  RMPTR19         */
+    union iodefine_reg32_t  RMDF019;                       /*  RMDF019         */
+    union iodefine_reg32_t  RMDF119;                       /*  RMDF119         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID20;                        /*  RMID20          */
+    union iodefine_reg32_t  RMPTR20;                       /*  RMPTR20         */
+    union iodefine_reg32_t  RMDF020;                       /*  RMDF020         */
+    union iodefine_reg32_t  RMDF120;                       /*  RMDF120         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID21;                        /*  RMID21          */
+    union iodefine_reg32_t  RMPTR21;                       /*  RMPTR21         */
+    union iodefine_reg32_t  RMDF021;                       /*  RMDF021         */
+    union iodefine_reg32_t  RMDF121;                       /*  RMDF121         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID22;                        /*  RMID22          */
+    union iodefine_reg32_t  RMPTR22;                       /*  RMPTR22         */
+    union iodefine_reg32_t  RMDF022;                       /*  RMDF022         */
+    union iodefine_reg32_t  RMDF122;                       /*  RMDF122         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID23;                        /*  RMID23          */
+    union iodefine_reg32_t  RMPTR23;                       /*  RMPTR23         */
+    union iodefine_reg32_t  RMDF023;                       /*  RMDF023         */
+    union iodefine_reg32_t  RMDF123;                       /*  RMDF123         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID24;                        /*  RMID24          */
+    union iodefine_reg32_t  RMPTR24;                       /*  RMPTR24         */
+    union iodefine_reg32_t  RMDF024;                       /*  RMDF024         */
+    union iodefine_reg32_t  RMDF124;                       /*  RMDF124         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID25;                        /*  RMID25          */
+    union iodefine_reg32_t  RMPTR25;                       /*  RMPTR25         */
+    union iodefine_reg32_t  RMDF025;                       /*  RMDF025         */
+    union iodefine_reg32_t  RMDF125;                       /*  RMDF125         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID26;                        /*  RMID26          */
+    union iodefine_reg32_t  RMPTR26;                       /*  RMPTR26         */
+    union iodefine_reg32_t  RMDF026;                       /*  RMDF026         */
+    union iodefine_reg32_t  RMDF126;                       /*  RMDF126         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID27;                        /*  RMID27          */
+    union iodefine_reg32_t  RMPTR27;                       /*  RMPTR27         */
+    union iodefine_reg32_t  RMDF027;                       /*  RMDF027         */
+    union iodefine_reg32_t  RMDF127;                       /*  RMDF127         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID28;                        /*  RMID28          */
+    union iodefine_reg32_t  RMPTR28;                       /*  RMPTR28         */
+    union iodefine_reg32_t  RMDF028;                       /*  RMDF028         */
+    union iodefine_reg32_t  RMDF128;                       /*  RMDF128         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID29;                        /*  RMID29          */
+    union iodefine_reg32_t  RMPTR29;                       /*  RMPTR29         */
+    union iodefine_reg32_t  RMDF029;                       /*  RMDF029         */
+    union iodefine_reg32_t  RMDF129;                       /*  RMDF129         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID30;                        /*  RMID30          */
+    union iodefine_reg32_t  RMPTR30;                       /*  RMPTR30         */
+    union iodefine_reg32_t  RMDF030;                       /*  RMDF030         */
+    union iodefine_reg32_t  RMDF130;                       /*  RMDF130         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID31;                        /*  RMID31          */
+    union iodefine_reg32_t  RMPTR31;                       /*  RMPTR31         */
+    union iodefine_reg32_t  RMDF031;                       /*  RMDF031         */
+    union iodefine_reg32_t  RMDF131;                       /*  RMDF131         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID32;                        /*  RMID32          */
+    union iodefine_reg32_t  RMPTR32;                       /*  RMPTR32         */
+    union iodefine_reg32_t  RMDF032;                       /*  RMDF032         */
+    union iodefine_reg32_t  RMDF132;                       /*  RMDF132         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID33;                        /*  RMID33          */
+    union iodefine_reg32_t  RMPTR33;                       /*  RMPTR33         */
+    union iodefine_reg32_t  RMDF033;                       /*  RMDF033         */
+    union iodefine_reg32_t  RMDF133;                       /*  RMDF133         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID34;                        /*  RMID34          */
+    union iodefine_reg32_t  RMPTR34;                       /*  RMPTR34         */
+    union iodefine_reg32_t  RMDF034;                       /*  RMDF034         */
+    union iodefine_reg32_t  RMDF134;                       /*  RMDF134         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID35;                        /*  RMID35          */
+    union iodefine_reg32_t  RMPTR35;                       /*  RMPTR35         */
+    union iodefine_reg32_t  RMDF035;                       /*  RMDF035         */
+    union iodefine_reg32_t  RMDF135;                       /*  RMDF135         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID36;                        /*  RMID36          */
+    union iodefine_reg32_t  RMPTR36;                       /*  RMPTR36         */
+    union iodefine_reg32_t  RMDF036;                       /*  RMDF036         */
+    union iodefine_reg32_t  RMDF136;                       /*  RMDF136         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID37;                        /*  RMID37          */
+    union iodefine_reg32_t  RMPTR37;                       /*  RMPTR37         */
+    union iodefine_reg32_t  RMDF037;                       /*  RMDF037         */
+    union iodefine_reg32_t  RMDF137;                       /*  RMDF137         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID38;                        /*  RMID38          */
+    union iodefine_reg32_t  RMPTR38;                       /*  RMPTR38         */
+    union iodefine_reg32_t  RMDF038;                       /*  RMDF038         */
+    union iodefine_reg32_t  RMDF138;                       /*  RMDF138         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID39;                        /*  RMID39          */
+    union iodefine_reg32_t  RMPTR39;                       /*  RMPTR39         */
+    union iodefine_reg32_t  RMDF039;                       /*  RMDF039         */
+    union iodefine_reg32_t  RMDF139;                       /*  RMDF139         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID40;                        /*  RMID40          */
+    union iodefine_reg32_t  RMPTR40;                       /*  RMPTR40         */
+    union iodefine_reg32_t  RMDF040;                       /*  RMDF040         */
+    union iodefine_reg32_t  RMDF140;                       /*  RMDF140         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID41;                        /*  RMID41          */
+    union iodefine_reg32_t  RMPTR41;                       /*  RMPTR41         */
+    union iodefine_reg32_t  RMDF041;                       /*  RMDF041         */
+    union iodefine_reg32_t  RMDF141;                       /*  RMDF141         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID42;                        /*  RMID42          */
+    union iodefine_reg32_t  RMPTR42;                       /*  RMPTR42         */
+    union iodefine_reg32_t  RMDF042;                       /*  RMDF042         */
+    union iodefine_reg32_t  RMDF142;                       /*  RMDF142         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID43;                        /*  RMID43          */
+    union iodefine_reg32_t  RMPTR43;                       /*  RMPTR43         */
+    union iodefine_reg32_t  RMDF043;                       /*  RMDF043         */
+    union iodefine_reg32_t  RMDF143;                       /*  RMDF143         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID44;                        /*  RMID44          */
+    union iodefine_reg32_t  RMPTR44;                       /*  RMPTR44         */
+    union iodefine_reg32_t  RMDF044;                       /*  RMDF044         */
+    union iodefine_reg32_t  RMDF144;                       /*  RMDF144         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID45;                        /*  RMID45          */
+    union iodefine_reg32_t  RMPTR45;                       /*  RMPTR45         */
+    union iodefine_reg32_t  RMDF045;                       /*  RMDF045         */
+    union iodefine_reg32_t  RMDF145;                       /*  RMDF145         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID46;                        /*  RMID46          */
+    union iodefine_reg32_t  RMPTR46;                       /*  RMPTR46         */
+    union iodefine_reg32_t  RMDF046;                       /*  RMDF046         */
+    union iodefine_reg32_t  RMDF146;                       /*  RMDF146         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID47;                        /*  RMID47          */
+    union iodefine_reg32_t  RMPTR47;                       /*  RMPTR47         */
+    union iodefine_reg32_t  RMDF047;                       /*  RMDF047         */
+    union iodefine_reg32_t  RMDF147;                       /*  RMDF147         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID48;                        /*  RMID48          */
+    union iodefine_reg32_t  RMPTR48;                       /*  RMPTR48         */
+    union iodefine_reg32_t  RMDF048;                       /*  RMDF048         */
+    union iodefine_reg32_t  RMDF148;                       /*  RMDF148         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID49;                        /*  RMID49          */
+    union iodefine_reg32_t  RMPTR49;                       /*  RMPTR49         */
+    union iodefine_reg32_t  RMDF049;                       /*  RMDF049         */
+    union iodefine_reg32_t  RMDF149;                       /*  RMDF149         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID50;                        /*  RMID50          */
+    union iodefine_reg32_t  RMPTR50;                       /*  RMPTR50         */
+    union iodefine_reg32_t  RMDF050;                       /*  RMDF050         */
+    union iodefine_reg32_t  RMDF150;                       /*  RMDF150         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID51;                        /*  RMID51          */
+    union iodefine_reg32_t  RMPTR51;                       /*  RMPTR51         */
+    union iodefine_reg32_t  RMDF051;                       /*  RMDF051         */
+    union iodefine_reg32_t  RMDF151;                       /*  RMDF151         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID52;                        /*  RMID52          */
+    union iodefine_reg32_t  RMPTR52;                       /*  RMPTR52         */
+    union iodefine_reg32_t  RMDF052;                       /*  RMDF052         */
+    union iodefine_reg32_t  RMDF152;                       /*  RMDF152         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID53;                        /*  RMID53          */
+    union iodefine_reg32_t  RMPTR53;                       /*  RMPTR53         */
+    union iodefine_reg32_t  RMDF053;                       /*  RMDF053         */
+    union iodefine_reg32_t  RMDF153;                       /*  RMDF153         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID54;                        /*  RMID54          */
+    union iodefine_reg32_t  RMPTR54;                       /*  RMPTR54         */
+    union iodefine_reg32_t  RMDF054;                       /*  RMDF054         */
+    union iodefine_reg32_t  RMDF154;                       /*  RMDF154         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID55;                        /*  RMID55          */
+    union iodefine_reg32_t  RMPTR55;                       /*  RMPTR55         */
+    union iodefine_reg32_t  RMDF055;                       /*  RMDF055         */
+    union iodefine_reg32_t  RMDF155;                       /*  RMDF155         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID56;                        /*  RMID56          */
+    union iodefine_reg32_t  RMPTR56;                       /*  RMPTR56         */
+    union iodefine_reg32_t  RMDF056;                       /*  RMDF056         */
+    union iodefine_reg32_t  RMDF156;                       /*  RMDF156         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID57;                        /*  RMID57          */
+    union iodefine_reg32_t  RMPTR57;                       /*  RMPTR57         */
+    union iodefine_reg32_t  RMDF057;                       /*  RMDF057         */
+    union iodefine_reg32_t  RMDF157;                       /*  RMDF157         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID58;                        /*  RMID58          */
+    union iodefine_reg32_t  RMPTR58;                       /*  RMPTR58         */
+    union iodefine_reg32_t  RMDF058;                       /*  RMDF058         */
+    union iodefine_reg32_t  RMDF158;                       /*  RMDF158         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID59;                        /*  RMID59          */
+    union iodefine_reg32_t  RMPTR59;                       /*  RMPTR59         */
+    union iodefine_reg32_t  RMDF059;                       /*  RMDF059         */
+    union iodefine_reg32_t  RMDF159;                       /*  RMDF159         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID60;                        /*  RMID60          */
+    union iodefine_reg32_t  RMPTR60;                       /*  RMPTR60         */
+    union iodefine_reg32_t  RMDF060;                       /*  RMDF060         */
+    union iodefine_reg32_t  RMDF160;                       /*  RMDF160         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID61;                        /*  RMID61          */
+    union iodefine_reg32_t  RMPTR61;                       /*  RMPTR61         */
+    union iodefine_reg32_t  RMDF061;                       /*  RMDF061         */
+    union iodefine_reg32_t  RMDF161;                       /*  RMDF161         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID62;                        /*  RMID62          */
+    union iodefine_reg32_t  RMPTR62;                       /*  RMPTR62         */
+    union iodefine_reg32_t  RMDF062;                       /*  RMDF062         */
+    union iodefine_reg32_t  RMDF162;                       /*  RMDF162         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID63;                        /*  RMID63          */
+    union iodefine_reg32_t  RMPTR63;                       /*  RMPTR63         */
+    union iodefine_reg32_t  RMDF063;                       /*  RMDF063         */
+    union iodefine_reg32_t  RMDF163;                       /*  RMDF163         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID64;                        /*  RMID64          */
+    union iodefine_reg32_t  RMPTR64;                       /*  RMPTR64         */
+    union iodefine_reg32_t  RMDF064;                       /*  RMDF064         */
+    union iodefine_reg32_t  RMDF164;                       /*  RMDF164         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID65;                        /*  RMID65          */
+    union iodefine_reg32_t  RMPTR65;                       /*  RMPTR65         */
+    union iodefine_reg32_t  RMDF065;                       /*  RMDF065         */
+    union iodefine_reg32_t  RMDF165;                       /*  RMDF165         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID66;                        /*  RMID66          */
+    union iodefine_reg32_t  RMPTR66;                       /*  RMPTR66         */
+    union iodefine_reg32_t  RMDF066;                       /*  RMDF066         */
+    union iodefine_reg32_t  RMDF166;                       /*  RMDF166         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID67;                        /*  RMID67          */
+    union iodefine_reg32_t  RMPTR67;                       /*  RMPTR67         */
+    union iodefine_reg32_t  RMDF067;                       /*  RMDF067         */
+    union iodefine_reg32_t  RMDF167;                       /*  RMDF167         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID68;                        /*  RMID68          */
+    union iodefine_reg32_t  RMPTR68;                       /*  RMPTR68         */
+    union iodefine_reg32_t  RMDF068;                       /*  RMDF068         */
+    union iodefine_reg32_t  RMDF168;                       /*  RMDF168         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID69;                        /*  RMID69          */
+    union iodefine_reg32_t  RMPTR69;                       /*  RMPTR69         */
+    union iodefine_reg32_t  RMDF069;                       /*  RMDF069         */
+    union iodefine_reg32_t  RMDF169;                       /*  RMDF169         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID70;                        /*  RMID70          */
+    union iodefine_reg32_t  RMPTR70;                       /*  RMPTR70         */
+    union iodefine_reg32_t  RMDF070;                       /*  RMDF070         */
+    union iodefine_reg32_t  RMDF170;                       /*  RMDF170         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID71;                        /*  RMID71          */
+    union iodefine_reg32_t  RMPTR71;                       /*  RMPTR71         */
+    union iodefine_reg32_t  RMDF071;                       /*  RMDF071         */
+    union iodefine_reg32_t  RMDF171;                       /*  RMDF171         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID72;                        /*  RMID72          */
+    union iodefine_reg32_t  RMPTR72;                       /*  RMPTR72         */
+    union iodefine_reg32_t  RMDF072;                       /*  RMDF072         */
+    union iodefine_reg32_t  RMDF172;                       /*  RMDF172         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID73;                        /*  RMID73          */
+    union iodefine_reg32_t  RMPTR73;                       /*  RMPTR73         */
+    union iodefine_reg32_t  RMDF073;                       /*  RMDF073         */
+    union iodefine_reg32_t  RMDF173;                       /*  RMDF173         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID74;                        /*  RMID74          */
+    union iodefine_reg32_t  RMPTR74;                       /*  RMPTR74         */
+    union iodefine_reg32_t  RMDF074;                       /*  RMDF074         */
+    union iodefine_reg32_t  RMDF174;                       /*  RMDF174         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID75;                        /*  RMID75          */
+    union iodefine_reg32_t  RMPTR75;                       /*  RMPTR75         */
+    union iodefine_reg32_t  RMDF075;                       /*  RMDF075         */
+    union iodefine_reg32_t  RMDF175;                       /*  RMDF175         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID76;                        /*  RMID76          */
+    union iodefine_reg32_t  RMPTR76;                       /*  RMPTR76         */
+    union iodefine_reg32_t  RMDF076;                       /*  RMDF076         */
+    union iodefine_reg32_t  RMDF176;                       /*  RMDF176         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID77;                        /*  RMID77          */
+    union iodefine_reg32_t  RMPTR77;                       /*  RMPTR77         */
+    union iodefine_reg32_t  RMDF077;                       /*  RMDF077         */
+    union iodefine_reg32_t  RMDF177;                       /*  RMDF177         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID78;                        /*  RMID78          */
+    union iodefine_reg32_t  RMPTR78;                       /*  RMPTR78         */
+    union iodefine_reg32_t  RMDF078;                       /*  RMDF078         */
+    union iodefine_reg32_t  RMDF178;                       /*  RMDF178         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+/* start of struct st_rscan_from_rscan0rmidp */
+    union iodefine_reg32_t  RMID79;                        /*  RMID79          */
+    union iodefine_reg32_t  RMPTR79;                       /*  RMPTR79         */
+    union iodefine_reg32_t  RMDF079;                       /*  RMDF079         */
+    union iodefine_reg32_t  RMDF179;                       /*  RMDF179         */
+
+/* end of struct st_rscan_from_rscan0rmidp */
+    
+    volatile uint8_t   dummy179[768];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID0;                         /*  RFID0           */
+    union iodefine_reg32_t  RFPTR0;                        /*  RFPTR0          */
+    union iodefine_reg32_t  RFDF00;                        /*  RFDF00          */
+    union iodefine_reg32_t  RFDF10;                        /*  RFDF10          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID1;                         /*  RFID1           */
+    union iodefine_reg32_t  RFPTR1;                        /*  RFPTR1          */
+    union iodefine_reg32_t  RFDF01;                        /*  RFDF01          */
+    union iodefine_reg32_t  RFDF11;                        /*  RFDF11          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID2;                         /*  RFID2           */
+    union iodefine_reg32_t  RFPTR2;                        /*  RFPTR2          */
+    union iodefine_reg32_t  RFDF02;                        /*  RFDF02          */
+    union iodefine_reg32_t  RFDF12;                        /*  RFDF12          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID3;                         /*  RFID3           */
+    union iodefine_reg32_t  RFPTR3;                        /*  RFPTR3          */
+    union iodefine_reg32_t  RFDF03;                        /*  RFDF03          */
+    union iodefine_reg32_t  RFDF13;                        /*  RFDF13          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID4;                         /*  RFID4           */
+    union iodefine_reg32_t  RFPTR4;                        /*  RFPTR4          */
+    union iodefine_reg32_t  RFDF04;                        /*  RFDF04          */
+    union iodefine_reg32_t  RFDF14;                        /*  RFDF14          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID5;                         /*  RFID5           */
+    union iodefine_reg32_t  RFPTR5;                        /*  RFPTR5          */
+    union iodefine_reg32_t  RFDF05;                        /*  RFDF05          */
+    union iodefine_reg32_t  RFDF15;                        /*  RFDF15          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID6;                         /*  RFID6           */
+    union iodefine_reg32_t  RFPTR6;                        /*  RFPTR6          */
+    union iodefine_reg32_t  RFDF06;                        /*  RFDF06          */
+    union iodefine_reg32_t  RFDF16;                        /*  RFDF16          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0rfidm */
+    union iodefine_reg32_t  RFID7;                         /*  RFID7           */
+    union iodefine_reg32_t  RFPTR7;                        /*  RFPTR7          */
+    union iodefine_reg32_t  RFDF07;                        /*  RFDF07          */
+    union iodefine_reg32_t  RFDF17;                        /*  RFDF17          */
+
+/* end of struct st_rscan_from_rscan0rfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID0;                         /*  CFID0           */
+    union iodefine_reg32_t  CFPTR0;                        /*  CFPTR0          */
+    union iodefine_reg32_t  CFDF00;                        /*  CFDF00          */
+    union iodefine_reg32_t  CFDF10;                        /*  CFDF10          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID1;                         /*  CFID1           */
+    union iodefine_reg32_t  CFPTR1;                        /*  CFPTR1          */
+    union iodefine_reg32_t  CFDF01;                        /*  CFDF01          */
+    union iodefine_reg32_t  CFDF11;                        /*  CFDF11          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID2;                         /*  CFID2           */
+    union iodefine_reg32_t  CFPTR2;                        /*  CFPTR2          */
+    union iodefine_reg32_t  CFDF02;                        /*  CFDF02          */
+    union iodefine_reg32_t  CFDF12;                        /*  CFDF12          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID3;                         /*  CFID3           */
+    union iodefine_reg32_t  CFPTR3;                        /*  CFPTR3          */
+    union iodefine_reg32_t  CFDF03;                        /*  CFDF03          */
+    union iodefine_reg32_t  CFDF13;                        /*  CFDF13          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID4;                         /*  CFID4           */
+    union iodefine_reg32_t  CFPTR4;                        /*  CFPTR4          */
+    union iodefine_reg32_t  CFDF04;                        /*  CFDF04          */
+    union iodefine_reg32_t  CFDF14;                        /*  CFDF14          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID5;                         /*  CFID5           */
+    union iodefine_reg32_t  CFPTR5;                        /*  CFPTR5          */
+    union iodefine_reg32_t  CFDF05;                        /*  CFDF05          */
+    union iodefine_reg32_t  CFDF15;                        /*  CFDF15          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID6;                         /*  CFID6           */
+    union iodefine_reg32_t  CFPTR6;                        /*  CFPTR6          */
+    union iodefine_reg32_t  CFDF06;                        /*  CFDF06          */
+    union iodefine_reg32_t  CFDF16;                        /*  CFDF16          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID7;                         /*  CFID7           */
+    union iodefine_reg32_t  CFPTR7;                        /*  CFPTR7          */
+    union iodefine_reg32_t  CFDF07;                        /*  CFDF07          */
+    union iodefine_reg32_t  CFDF17;                        /*  CFDF17          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID8;                         /*  CFID8           */
+    union iodefine_reg32_t  CFPTR8;                        /*  CFPTR8          */
+    union iodefine_reg32_t  CFDF08;                        /*  CFDF08          */
+    union iodefine_reg32_t  CFDF18;                        /*  CFDF18          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID9;                         /*  CFID9           */
+    union iodefine_reg32_t  CFPTR9;                        /*  CFPTR9          */
+    union iodefine_reg32_t  CFDF09;                        /*  CFDF09          */
+    union iodefine_reg32_t  CFDF19;                        /*  CFDF19          */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID10;                        /*  CFID10          */
+    union iodefine_reg32_t  CFPTR10;                       /*  CFPTR10         */
+    union iodefine_reg32_t  CFDF010;                       /*  CFDF010         */
+    union iodefine_reg32_t  CFDF110;                       /*  CFDF110         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID11;                        /*  CFID11          */
+    union iodefine_reg32_t  CFPTR11;                       /*  CFPTR11         */
+    union iodefine_reg32_t  CFDF011;                       /*  CFDF011         */
+    union iodefine_reg32_t  CFDF111;                       /*  CFDF111         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID12;                        /*  CFID12          */
+    union iodefine_reg32_t  CFPTR12;                       /*  CFPTR12         */
+    union iodefine_reg32_t  CFDF012;                       /*  CFDF012         */
+    union iodefine_reg32_t  CFDF112;                       /*  CFDF112         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID13;                        /*  CFID13          */
+    union iodefine_reg32_t  CFPTR13;                       /*  CFPTR13         */
+    union iodefine_reg32_t  CFDF013;                       /*  CFDF013         */
+    union iodefine_reg32_t  CFDF113;                       /*  CFDF113         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+/* start of struct st_rscan_from_rscan0cfidm */
+    union iodefine_reg32_t  CFID14;                        /*  CFID14          */
+    union iodefine_reg32_t  CFPTR14;                       /*  CFPTR14         */
+    union iodefine_reg32_t  CFDF014;                       /*  CFDF014         */
+    union iodefine_reg32_t  CFDF114;                       /*  CFDF114         */
+
+/* end of struct st_rscan_from_rscan0cfidm */
+    
+    volatile uint8_t   dummy180[144];                          /*                  */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID0;                         /*  TMID0           */
+    union iodefine_reg32_t  TMPTR0;                        /*  TMPTR0          */
+    union iodefine_reg32_t  TMDF00;                        /*  TMDF00          */
+    union iodefine_reg32_t  TMDF10;                        /*  TMDF10          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID1;                         /*  TMID1           */
+    union iodefine_reg32_t  TMPTR1;                        /*  TMPTR1          */
+    union iodefine_reg32_t  TMDF01;                        /*  TMDF01          */
+    union iodefine_reg32_t  TMDF11;                        /*  TMDF11          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID2;                         /*  TMID2           */
+    union iodefine_reg32_t  TMPTR2;                        /*  TMPTR2          */
+    union iodefine_reg32_t  TMDF02;                        /*  TMDF02          */
+    union iodefine_reg32_t  TMDF12;                        /*  TMDF12          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID3;                         /*  TMID3           */
+    union iodefine_reg32_t  TMPTR3;                        /*  TMPTR3          */
+    union iodefine_reg32_t  TMDF03;                        /*  TMDF03          */
+    union iodefine_reg32_t  TMDF13;                        /*  TMDF13          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID4;                         /*  TMID4           */
+    union iodefine_reg32_t  TMPTR4;                        /*  TMPTR4          */
+    union iodefine_reg32_t  TMDF04;                        /*  TMDF04          */
+    union iodefine_reg32_t  TMDF14;                        /*  TMDF14          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID5;                         /*  TMID5           */
+    union iodefine_reg32_t  TMPTR5;                        /*  TMPTR5          */
+    union iodefine_reg32_t  TMDF05;                        /*  TMDF05          */
+    union iodefine_reg32_t  TMDF15;                        /*  TMDF15          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID6;                         /*  TMID6           */
+    union iodefine_reg32_t  TMPTR6;                        /*  TMPTR6          */
+    union iodefine_reg32_t  TMDF06;                        /*  TMDF06          */
+    union iodefine_reg32_t  TMDF16;                        /*  TMDF16          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID7;                         /*  TMID7           */
+    union iodefine_reg32_t  TMPTR7;                        /*  TMPTR7          */
+    union iodefine_reg32_t  TMDF07;                        /*  TMDF07          */
+    union iodefine_reg32_t  TMDF17;                        /*  TMDF17          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID8;                         /*  TMID8           */
+    union iodefine_reg32_t  TMPTR8;                        /*  TMPTR8          */
+    union iodefine_reg32_t  TMDF08;                        /*  TMDF08          */
+    union iodefine_reg32_t  TMDF18;                        /*  TMDF18          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID9;                         /*  TMID9           */
+    union iodefine_reg32_t  TMPTR9;                        /*  TMPTR9          */
+    union iodefine_reg32_t  TMDF09;                        /*  TMDF09          */
+    union iodefine_reg32_t  TMDF19;                        /*  TMDF19          */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID10;                        /*  TMID10          */
+    union iodefine_reg32_t  TMPTR10;                       /*  TMPTR10         */
+    union iodefine_reg32_t  TMDF010;                       /*  TMDF010         */
+    union iodefine_reg32_t  TMDF110;                       /*  TMDF110         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID11;                        /*  TMID11          */
+    union iodefine_reg32_t  TMPTR11;                       /*  TMPTR11         */
+    union iodefine_reg32_t  TMDF011;                       /*  TMDF011         */
+    union iodefine_reg32_t  TMDF111;                       /*  TMDF111         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID12;                        /*  TMID12          */
+    union iodefine_reg32_t  TMPTR12;                       /*  TMPTR12         */
+    union iodefine_reg32_t  TMDF012;                       /*  TMDF012         */
+    union iodefine_reg32_t  TMDF112;                       /*  TMDF112         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID13;                        /*  TMID13          */
+    union iodefine_reg32_t  TMPTR13;                       /*  TMPTR13         */
+    union iodefine_reg32_t  TMDF013;                       /*  TMDF013         */
+    union iodefine_reg32_t  TMDF113;                       /*  TMDF113         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID14;                        /*  TMID14          */
+    union iodefine_reg32_t  TMPTR14;                       /*  TMPTR14         */
+    union iodefine_reg32_t  TMDF014;                       /*  TMDF014         */
+    union iodefine_reg32_t  TMDF114;                       /*  TMDF114         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID15;                        /*  TMID15          */
+    union iodefine_reg32_t  TMPTR15;                       /*  TMPTR15         */
+    union iodefine_reg32_t  TMDF015;                       /*  TMDF015         */
+    union iodefine_reg32_t  TMDF115;                       /*  TMDF115         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID16;                        /*  TMID16          */
+    union iodefine_reg32_t  TMPTR16;                       /*  TMPTR16         */
+    union iodefine_reg32_t  TMDF016;                       /*  TMDF016         */
+    union iodefine_reg32_t  TMDF116;                       /*  TMDF116         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID17;                        /*  TMID17          */
+    union iodefine_reg32_t  TMPTR17;                       /*  TMPTR17         */
+    union iodefine_reg32_t  TMDF017;                       /*  TMDF017         */
+    union iodefine_reg32_t  TMDF117;                       /*  TMDF117         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID18;                        /*  TMID18          */
+    union iodefine_reg32_t  TMPTR18;                       /*  TMPTR18         */
+    union iodefine_reg32_t  TMDF018;                       /*  TMDF018         */
+    union iodefine_reg32_t  TMDF118;                       /*  TMDF118         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID19;                        /*  TMID19          */
+    union iodefine_reg32_t  TMPTR19;                       /*  TMPTR19         */
+    union iodefine_reg32_t  TMDF019;                       /*  TMDF019         */
+    union iodefine_reg32_t  TMDF119;                       /*  TMDF119         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID20;                        /*  TMID20          */
+    union iodefine_reg32_t  TMPTR20;                       /*  TMPTR20         */
+    union iodefine_reg32_t  TMDF020;                       /*  TMDF020         */
+    union iodefine_reg32_t  TMDF120;                       /*  TMDF120         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID21;                        /*  TMID21          */
+    union iodefine_reg32_t  TMPTR21;                       /*  TMPTR21         */
+    union iodefine_reg32_t  TMDF021;                       /*  TMDF021         */
+    union iodefine_reg32_t  TMDF121;                       /*  TMDF121         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID22;                        /*  TMID22          */
+    union iodefine_reg32_t  TMPTR22;                       /*  TMPTR22         */
+    union iodefine_reg32_t  TMDF022;                       /*  TMDF022         */
+    union iodefine_reg32_t  TMDF122;                       /*  TMDF122         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID23;                        /*  TMID23          */
+    union iodefine_reg32_t  TMPTR23;                       /*  TMPTR23         */
+    union iodefine_reg32_t  TMDF023;                       /*  TMDF023         */
+    union iodefine_reg32_t  TMDF123;                       /*  TMDF123         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID24;                        /*  TMID24          */
+    union iodefine_reg32_t  TMPTR24;                       /*  TMPTR24         */
+    union iodefine_reg32_t  TMDF024;                       /*  TMDF024         */
+    union iodefine_reg32_t  TMDF124;                       /*  TMDF124         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID25;                        /*  TMID25          */
+    union iodefine_reg32_t  TMPTR25;                       /*  TMPTR25         */
+    union iodefine_reg32_t  TMDF025;                       /*  TMDF025         */
+    union iodefine_reg32_t  TMDF125;                       /*  TMDF125         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID26;                        /*  TMID26          */
+    union iodefine_reg32_t  TMPTR26;                       /*  TMPTR26         */
+    union iodefine_reg32_t  TMDF026;                       /*  TMDF026         */
+    union iodefine_reg32_t  TMDF126;                       /*  TMDF126         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID27;                        /*  TMID27          */
+    union iodefine_reg32_t  TMPTR27;                       /*  TMPTR27         */
+    union iodefine_reg32_t  TMDF027;                       /*  TMDF027         */
+    union iodefine_reg32_t  TMDF127;                       /*  TMDF127         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID28;                        /*  TMID28          */
+    union iodefine_reg32_t  TMPTR28;                       /*  TMPTR28         */
+    union iodefine_reg32_t  TMDF028;                       /*  TMDF028         */
+    union iodefine_reg32_t  TMDF128;                       /*  TMDF128         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID29;                        /*  TMID29          */
+    union iodefine_reg32_t  TMPTR29;                       /*  TMPTR29         */
+    union iodefine_reg32_t  TMDF029;                       /*  TMDF029         */
+    union iodefine_reg32_t  TMDF129;                       /*  TMDF129         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID30;                        /*  TMID30          */
+    union iodefine_reg32_t  TMPTR30;                       /*  TMPTR30         */
+    union iodefine_reg32_t  TMDF030;                       /*  TMDF030         */
+    union iodefine_reg32_t  TMDF130;                       /*  TMDF130         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID31;                        /*  TMID31          */
+    union iodefine_reg32_t  TMPTR31;                       /*  TMPTR31         */
+    union iodefine_reg32_t  TMDF031;                       /*  TMDF031         */
+    union iodefine_reg32_t  TMDF131;                       /*  TMDF131         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID32;                        /*  TMID32          */
+    union iodefine_reg32_t  TMPTR32;                       /*  TMPTR32         */
+    union iodefine_reg32_t  TMDF032;                       /*  TMDF032         */
+    union iodefine_reg32_t  TMDF132;                       /*  TMDF132         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID33;                        /*  TMID33          */
+    union iodefine_reg32_t  TMPTR33;                       /*  TMPTR33         */
+    union iodefine_reg32_t  TMDF033;                       /*  TMDF033         */
+    union iodefine_reg32_t  TMDF133;                       /*  TMDF133         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID34;                        /*  TMID34          */
+    union iodefine_reg32_t  TMPTR34;                       /*  TMPTR34         */
+    union iodefine_reg32_t  TMDF034;                       /*  TMDF034         */
+    union iodefine_reg32_t  TMDF134;                       /*  TMDF134         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID35;                        /*  TMID35          */
+    union iodefine_reg32_t  TMPTR35;                       /*  TMPTR35         */
+    union iodefine_reg32_t  TMDF035;                       /*  TMDF035         */
+    union iodefine_reg32_t  TMDF135;                       /*  TMDF135         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID36;                        /*  TMID36          */
+    union iodefine_reg32_t  TMPTR36;                       /*  TMPTR36         */
+    union iodefine_reg32_t  TMDF036;                       /*  TMDF036         */
+    union iodefine_reg32_t  TMDF136;                       /*  TMDF136         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID37;                        /*  TMID37          */
+    union iodefine_reg32_t  TMPTR37;                       /*  TMPTR37         */
+    union iodefine_reg32_t  TMDF037;                       /*  TMDF037         */
+    union iodefine_reg32_t  TMDF137;                       /*  TMDF137         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID38;                        /*  TMID38          */
+    union iodefine_reg32_t  TMPTR38;                       /*  TMPTR38         */
+    union iodefine_reg32_t  TMDF038;                       /*  TMDF038         */
+    union iodefine_reg32_t  TMDF138;                       /*  TMDF138         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID39;                        /*  TMID39          */
+    union iodefine_reg32_t  TMPTR39;                       /*  TMPTR39         */
+    union iodefine_reg32_t  TMDF039;                       /*  TMDF039         */
+    union iodefine_reg32_t  TMDF139;                       /*  TMDF139         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID40;                        /*  TMID40          */
+    union iodefine_reg32_t  TMPTR40;                       /*  TMPTR40         */
+    union iodefine_reg32_t  TMDF040;                       /*  TMDF040         */
+    union iodefine_reg32_t  TMDF140;                       /*  TMDF140         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID41;                        /*  TMID41          */
+    union iodefine_reg32_t  TMPTR41;                       /*  TMPTR41         */
+    union iodefine_reg32_t  TMDF041;                       /*  TMDF041         */
+    union iodefine_reg32_t  TMDF141;                       /*  TMDF141         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID42;                        /*  TMID42          */
+    union iodefine_reg32_t  TMPTR42;                       /*  TMPTR42         */
+    union iodefine_reg32_t  TMDF042;                       /*  TMDF042         */
+    union iodefine_reg32_t  TMDF142;                       /*  TMDF142         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID43;                        /*  TMID43          */
+    union iodefine_reg32_t  TMPTR43;                       /*  TMPTR43         */
+    union iodefine_reg32_t  TMDF043;                       /*  TMDF043         */
+    union iodefine_reg32_t  TMDF143;                       /*  TMDF143         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID44;                        /*  TMID44          */
+    union iodefine_reg32_t  TMPTR44;                       /*  TMPTR44         */
+    union iodefine_reg32_t  TMDF044;                       /*  TMDF044         */
+    union iodefine_reg32_t  TMDF144;                       /*  TMDF144         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID45;                        /*  TMID45          */
+    union iodefine_reg32_t  TMPTR45;                       /*  TMPTR45         */
+    union iodefine_reg32_t  TMDF045;                       /*  TMDF045         */
+    union iodefine_reg32_t  TMDF145;                       /*  TMDF145         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID46;                        /*  TMID46          */
+    union iodefine_reg32_t  TMPTR46;                       /*  TMPTR46         */
+    union iodefine_reg32_t  TMDF046;                       /*  TMDF046         */
+    union iodefine_reg32_t  TMDF146;                       /*  TMDF146         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID47;                        /*  TMID47          */
+    union iodefine_reg32_t  TMPTR47;                       /*  TMPTR47         */
+    union iodefine_reg32_t  TMDF047;                       /*  TMDF047         */
+    union iodefine_reg32_t  TMDF147;                       /*  TMDF147         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID48;                        /*  TMID48          */
+    union iodefine_reg32_t  TMPTR48;                       /*  TMPTR48         */
+    union iodefine_reg32_t  TMDF048;                       /*  TMDF048         */
+    union iodefine_reg32_t  TMDF148;                       /*  TMDF148         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID49;                        /*  TMID49          */
+    union iodefine_reg32_t  TMPTR49;                       /*  TMPTR49         */
+    union iodefine_reg32_t  TMDF049;                       /*  TMDF049         */
+    union iodefine_reg32_t  TMDF149;                       /*  TMDF149         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID50;                        /*  TMID50          */
+    union iodefine_reg32_t  TMPTR50;                       /*  TMPTR50         */
+    union iodefine_reg32_t  TMDF050;                       /*  TMDF050         */
+    union iodefine_reg32_t  TMDF150;                       /*  TMDF150         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID51;                        /*  TMID51          */
+    union iodefine_reg32_t  TMPTR51;                       /*  TMPTR51         */
+    union iodefine_reg32_t  TMDF051;                       /*  TMDF051         */
+    union iodefine_reg32_t  TMDF151;                       /*  TMDF151         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID52;                        /*  TMID52          */
+    union iodefine_reg32_t  TMPTR52;                       /*  TMPTR52         */
+    union iodefine_reg32_t  TMDF052;                       /*  TMDF052         */
+    union iodefine_reg32_t  TMDF152;                       /*  TMDF152         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID53;                        /*  TMID53          */
+    union iodefine_reg32_t  TMPTR53;                       /*  TMPTR53         */
+    union iodefine_reg32_t  TMDF053;                       /*  TMDF053         */
+    union iodefine_reg32_t  TMDF153;                       /*  TMDF153         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID54;                        /*  TMID54          */
+    union iodefine_reg32_t  TMPTR54;                       /*  TMPTR54         */
+    union iodefine_reg32_t  TMDF054;                       /*  TMDF054         */
+    union iodefine_reg32_t  TMDF154;                       /*  TMDF154         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID55;                        /*  TMID55          */
+    union iodefine_reg32_t  TMPTR55;                       /*  TMPTR55         */
+    union iodefine_reg32_t  TMDF055;                       /*  TMDF055         */
+    union iodefine_reg32_t  TMDF155;                       /*  TMDF155         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID56;                        /*  TMID56          */
+    union iodefine_reg32_t  TMPTR56;                       /*  TMPTR56         */
+    union iodefine_reg32_t  TMDF056;                       /*  TMDF056         */
+    union iodefine_reg32_t  TMDF156;                       /*  TMDF156         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID57;                        /*  TMID57          */
+    union iodefine_reg32_t  TMPTR57;                       /*  TMPTR57         */
+    union iodefine_reg32_t  TMDF057;                       /*  TMDF057         */
+    union iodefine_reg32_t  TMDF157;                       /*  TMDF157         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID58;                        /*  TMID58          */
+    union iodefine_reg32_t  TMPTR58;                       /*  TMPTR58         */
+    union iodefine_reg32_t  TMDF058;                       /*  TMDF058         */
+    union iodefine_reg32_t  TMDF158;                       /*  TMDF158         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID59;                        /*  TMID59          */
+    union iodefine_reg32_t  TMPTR59;                       /*  TMPTR59         */
+    union iodefine_reg32_t  TMDF059;                       /*  TMDF059         */
+    union iodefine_reg32_t  TMDF159;                       /*  TMDF159         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID60;                        /*  TMID60          */
+    union iodefine_reg32_t  TMPTR60;                       /*  TMPTR60         */
+    union iodefine_reg32_t  TMDF060;                       /*  TMDF060         */
+    union iodefine_reg32_t  TMDF160;                       /*  TMDF160         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID61;                        /*  TMID61          */
+    union iodefine_reg32_t  TMPTR61;                       /*  TMPTR61         */
+    union iodefine_reg32_t  TMDF061;                       /*  TMDF061         */
+    union iodefine_reg32_t  TMDF161;                       /*  TMDF161         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID62;                        /*  TMID62          */
+    union iodefine_reg32_t  TMPTR62;                       /*  TMPTR62         */
+    union iodefine_reg32_t  TMDF062;                       /*  TMDF062         */
+    union iodefine_reg32_t  TMDF162;                       /*  TMDF162         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID63;                        /*  TMID63          */
+    union iodefine_reg32_t  TMPTR63;                       /*  TMPTR63         */
+    union iodefine_reg32_t  TMDF063;                       /*  TMDF063         */
+    union iodefine_reg32_t  TMDF163;                       /*  TMDF163         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID64;                        /*  TMID64          */
+    union iodefine_reg32_t  TMPTR64;                       /*  TMPTR64         */
+    union iodefine_reg32_t  TMDF064;                       /*  TMDF064         */
+    union iodefine_reg32_t  TMDF164;                       /*  TMDF164         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID65;                        /*  TMID65          */
+    union iodefine_reg32_t  TMPTR65;                       /*  TMPTR65         */
+    union iodefine_reg32_t  TMDF065;                       /*  TMDF065         */
+    union iodefine_reg32_t  TMDF165;                       /*  TMDF165         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID66;                        /*  TMID66          */
+    union iodefine_reg32_t  TMPTR66;                       /*  TMPTR66         */
+    union iodefine_reg32_t  TMDF066;                       /*  TMDF066         */
+    union iodefine_reg32_t  TMDF166;                       /*  TMDF166         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID67;                        /*  TMID67          */
+    union iodefine_reg32_t  TMPTR67;                       /*  TMPTR67         */
+    union iodefine_reg32_t  TMDF067;                       /*  TMDF067         */
+    union iodefine_reg32_t  TMDF167;                       /*  TMDF167         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID68;                        /*  TMID68          */
+    union iodefine_reg32_t  TMPTR68;                       /*  TMPTR68         */
+    union iodefine_reg32_t  TMDF068;                       /*  TMDF068         */
+    union iodefine_reg32_t  TMDF168;                       /*  TMDF168         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID69;                        /*  TMID69          */
+    union iodefine_reg32_t  TMPTR69;                       /*  TMPTR69         */
+    union iodefine_reg32_t  TMDF069;                       /*  TMDF069         */
+    union iodefine_reg32_t  TMDF169;                       /*  TMDF169         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID70;                        /*  TMID70          */
+    union iodefine_reg32_t  TMPTR70;                       /*  TMPTR70         */
+    union iodefine_reg32_t  TMDF070;                       /*  TMDF070         */
+    union iodefine_reg32_t  TMDF170;                       /*  TMDF170         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID71;                        /*  TMID71          */
+    union iodefine_reg32_t  TMPTR71;                       /*  TMPTR71         */
+    union iodefine_reg32_t  TMDF071;                       /*  TMDF071         */
+    union iodefine_reg32_t  TMDF171;                       /*  TMDF171         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID72;                        /*  TMID72          */
+    union iodefine_reg32_t  TMPTR72;                       /*  TMPTR72         */
+    union iodefine_reg32_t  TMDF072;                       /*  TMDF072         */
+    union iodefine_reg32_t  TMDF172;                       /*  TMDF172         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID73;                        /*  TMID73          */
+    union iodefine_reg32_t  TMPTR73;                       /*  TMPTR73         */
+    union iodefine_reg32_t  TMDF073;                       /*  TMDF073         */
+    union iodefine_reg32_t  TMDF173;                       /*  TMDF173         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID74;                        /*  TMID74          */
+    union iodefine_reg32_t  TMPTR74;                       /*  TMPTR74         */
+    union iodefine_reg32_t  TMDF074;                       /*  TMDF074         */
+    union iodefine_reg32_t  TMDF174;                       /*  TMDF174         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID75;                        /*  TMID75          */
+    union iodefine_reg32_t  TMPTR75;                       /*  TMPTR75         */
+    union iodefine_reg32_t  TMDF075;                       /*  TMDF075         */
+    union iodefine_reg32_t  TMDF175;                       /*  TMDF175         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID76;                        /*  TMID76          */
+    union iodefine_reg32_t  TMPTR76;                       /*  TMPTR76         */
+    union iodefine_reg32_t  TMDF076;                       /*  TMDF076         */
+    union iodefine_reg32_t  TMDF176;                       /*  TMDF176         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID77;                        /*  TMID77          */
+    union iodefine_reg32_t  TMPTR77;                       /*  TMPTR77         */
+    union iodefine_reg32_t  TMDF077;                       /*  TMDF077         */
+    union iodefine_reg32_t  TMDF177;                       /*  TMDF177         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID78;                        /*  TMID78          */
+    union iodefine_reg32_t  TMPTR78;                       /*  TMPTR78         */
+    union iodefine_reg32_t  TMDF078;                       /*  TMDF078         */
+    union iodefine_reg32_t  TMDF178;                       /*  TMDF178         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+/* start of struct st_rscan_from_rscan0tmidp */
+    union iodefine_reg32_t  TMID79;                        /*  TMID79          */
+    union iodefine_reg32_t  TMPTR79;                       /*  TMPTR79         */
+    union iodefine_reg32_t  TMDF079;                       /*  TMDF079         */
+    union iodefine_reg32_t  TMDF179;                       /*  TMDF179         */
+
+/* end of struct st_rscan_from_rscan0tmidp */
+    
+    volatile uint8_t   dummy181[768];                          /*                  */
+
+/* #define RSCAN0_THLACC0_COUNT (5) */
+    union iodefine_reg32_t  THLACC0;                       /*  THLACC0         */
+    union iodefine_reg32_t  THLACC1;                       /*  THLACC1         */
+    union iodefine_reg32_t  THLACC2;                       /*  THLACC2         */
+    union iodefine_reg32_t  THLACC3;                       /*  THLACC3         */
+    union iodefine_reg32_t  THLACC4;                       /*  THLACC4         */
+    
+} r_io_rscan0_t;
+
+
+typedef struct st_rscan_from_rscan0cncfg
+{
+ 
+    union iodefine_reg32_t  CnCFG;                         /*  CnCFG           */
+    union iodefine_reg32_t  CnCTR;                         /*  CnCTR           */
+    union iodefine_reg32_t  CnSTS;                         /*  CnSTS           */
+    union iodefine_reg32_t  CnERFL;                        /*  CnERFL          */
+} r_io_rscan_from_rscan0cncfg_t;
+
+
+typedef struct st_rscan_from_rscan0gaflidj
+{
+ 
+    union iodefine_reg32_t  GAFLIDj;                       /*  GAFLIDj         */
+    union iodefine_reg32_t  GAFLMj;                        /*  GAFLMj          */
+    union iodefine_reg32_t  GAFLP0j;                       /*  GAFLP0j         */
+    union iodefine_reg32_t  GAFLP1j;                       /*  GAFLP1j         */
+} r_io_rscan_from_rscan0gaflidj_t;
+
+
+typedef struct st_rscan_from_rscan0rmidp
+{
+ 
+    union iodefine_reg32_t  RMIDp;                         /*  RMIDp           */
+    union iodefine_reg32_t  RMPTRp;                        /*  RMPTRp          */
+    union iodefine_reg32_t  RMDF0p;                        /*  RMDF0p          */
+    union iodefine_reg32_t  RMDF1p;                        /*  RMDF1p          */
+} r_io_rscan_from_rscan0rmidp_t;
+
+
+typedef struct st_rscan_from_rscan0rfidm
+{
+ 
+    union iodefine_reg32_t  RFIDm;                         /*  RFIDm           */
+    union iodefine_reg32_t  RFPTRm;                        /*  RFPTRm          */
+    union iodefine_reg32_t  RFDF0m;                        /*  RFDF0m          */
+    union iodefine_reg32_t  RFDF1m;                        /*  RFDF1m          */
+} r_io_rscan_from_rscan0rfidm_t;
+
+
+typedef struct st_rscan_from_rscan0tmidp
+{
+ 
+    union iodefine_reg32_t  TMIDp;                         /*  TMIDp           */
+    union iodefine_reg32_t  TMPTRp;                        /*  TMPTRp          */
+    union iodefine_reg32_t  TMDF0p;                        /*  TMDF0p          */
+    union iodefine_reg32_t  TMDF1p;                        /*  TMDF1p          */
+} r_io_rscan_from_rscan0tmidp_t;
+
+
+typedef struct st_rscan_from_rscan0cfidm
+{
+ 
+    union iodefine_reg32_t  CFIDm;                         /*  CFIDm           */
+    union iodefine_reg32_t  CFPTRm;                        /*  CFPTRm          */
+    union iodefine_reg32_t  CFDF0m;                        /*  CFDF0m          */
+    union iodefine_reg32_t  CFDF1m;                        /*  CFDF1m          */
+} r_io_rscan_from_rscan0cfidm_t;
+
+
+/* Channel array defines of RSCAN0 (2)*/
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS
+volatile struct st_rscan_from_rscan0cfidm*  RSCAN_FROM_RSCAN0_CFIDm[ RSCAN_FROM_RSCAN0_CFIDm_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_CFIDm_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_CFIDm_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS
+volatile struct st_rscan_from_rscan0tmidp*  RSCAN_FROM_RSCAN0_TMIDp[ RSCAN_FROM_RSCAN0_TMIDp_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_TMIDp_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_TMIDp_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS
+volatile struct st_rscan_from_rscan0rfidm*  RSCAN_FROM_RSCAN0_RFIDm[ RSCAN_FROM_RSCAN0_RFIDm_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_RFIDm_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_RFIDm_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS
+volatile struct st_rscan_from_rscan0rmidp*  RSCAN_FROM_RSCAN0_RMIDp[ RSCAN_FROM_RSCAN0_RMIDp_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_RMIDp_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_RMIDp_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS
+volatile struct st_rscan_from_rscan0gaflidj*  RSCAN_FROM_RSCAN0_GAFLIDj[ RSCAN_FROM_RSCAN0_GAFLIDj_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_GAFLIDj_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_GAFLIDj_CHANNELS */
+
+#ifdef  DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS
+volatile struct st_rscan_from_rscan0cncfg*  RSCAN_FROM_RSCAN0_CnCFG[ RSCAN_FROM_RSCAN0_CnCFG_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSCAN_FROM_RSCAN0_CnCFG_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSCAN_FROM_RSCAN0_CnCFG_CHANNELS */
+/* End of channel array defines of RSCAN0 (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
 /* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rspi_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,27 +18,173 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : rspi_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef RSPI_IODEFINE_H
 #define RSPI_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-#include "reg32_t.h"
+#define RSPI0   (*(struct st_rspi    *)0xE800C800uL) /* RSPI0 */
+#define RSPI1   (*(struct st_rspi    *)0xE800D000uL) /* RSPI1 */
+#define RSPI2   (*(struct st_rspi    *)0xE800D800uL) /* RSPI2 */
+#define RSPI3   (*(struct st_rspi    *)0xE800E000uL) /* RSPI3 */
+#define RSPI4   (*(struct st_rspi    *)0xE800E800uL) /* RSPI4 */
+
+
+/* Start of channel array defines of RSPI */
+
+/* Channel array defines of RSPI */
+/*(Sample) value = RSPI[ channel ]->SPCR; */
+#define RSPI_COUNT  (5)
+#define RSPI_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of RSPI */
+
 
-struct st_rspi
-{                                                          /* RSPI             */
+#define SPCR_0 (RSPI0.SPCR)
+#define SSLP_0 (RSPI0.SSLP)
+#define SPPCR_0 (RSPI0.SPPCR)
+#define SPSR_0 (RSPI0.SPSR)
+#define SPDR_0   (RSPI0.SPDR.UINT32)
+#define SPDR_0L  (RSPI0.SPDR.UINT16[R_IO_L])
+#define SPDR_0H  (RSPI0.SPDR.UINT16[R_IO_H])
+#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL])
+#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH])
+#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL])
+#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH])
+#define SPSCR_0 (RSPI0.SPSCR)
+#define SPSSR_0 (RSPI0.SPSSR)
+#define SPBR_0 (RSPI0.SPBR)
+#define SPDCR_0 (RSPI0.SPDCR)
+#define SPCKD_0 (RSPI0.SPCKD)
+#define SSLND_0 (RSPI0.SSLND)
+#define SPND_0 (RSPI0.SPND)
+#define SPCMD0_0 (RSPI0.SPCMD0)
+#define SPCMD1_0 (RSPI0.SPCMD1)
+#define SPCMD2_0 (RSPI0.SPCMD2)
+#define SPCMD3_0 (RSPI0.SPCMD3)
+#define SPBFCR_0 (RSPI0.SPBFCR)
+#define SPBFDR_0 (RSPI0.SPBFDR)
+#define SPCR_1 (RSPI1.SPCR)
+#define SSLP_1 (RSPI1.SSLP)
+#define SPPCR_1 (RSPI1.SPPCR)
+#define SPSR_1 (RSPI1.SPSR)
+#define SPDR_1   (RSPI1.SPDR.UINT32)
+#define SPDR_1L  (RSPI1.SPDR.UINT16[R_IO_L])
+#define SPDR_1H  (RSPI1.SPDR.UINT16[R_IO_H])
+#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL])
+#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH])
+#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL])
+#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH])
+#define SPSCR_1 (RSPI1.SPSCR)
+#define SPSSR_1 (RSPI1.SPSSR)
+#define SPBR_1 (RSPI1.SPBR)
+#define SPDCR_1 (RSPI1.SPDCR)
+#define SPCKD_1 (RSPI1.SPCKD)
+#define SSLND_1 (RSPI1.SSLND)
+#define SPND_1 (RSPI1.SPND)
+#define SPCMD0_1 (RSPI1.SPCMD0)
+#define SPCMD1_1 (RSPI1.SPCMD1)
+#define SPCMD2_1 (RSPI1.SPCMD2)
+#define SPCMD3_1 (RSPI1.SPCMD3)
+#define SPBFCR_1 (RSPI1.SPBFCR)
+#define SPBFDR_1 (RSPI1.SPBFDR)
+#define SPCR_2 (RSPI2.SPCR)
+#define SSLP_2 (RSPI2.SSLP)
+#define SPPCR_2 (RSPI2.SPPCR)
+#define SPSR_2 (RSPI2.SPSR)
+#define SPDR_2   (RSPI2.SPDR.UINT32)
+#define SPDR_2L  (RSPI2.SPDR.UINT16[R_IO_L])
+#define SPDR_2H  (RSPI2.SPDR.UINT16[R_IO_H])
+#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL])
+#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH])
+#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL])
+#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH])
+#define SPSCR_2 (RSPI2.SPSCR)
+#define SPSSR_2 (RSPI2.SPSSR)
+#define SPBR_2 (RSPI2.SPBR)
+#define SPDCR_2 (RSPI2.SPDCR)
+#define SPCKD_2 (RSPI2.SPCKD)
+#define SSLND_2 (RSPI2.SSLND)
+#define SPND_2 (RSPI2.SPND)
+#define SPCMD0_2 (RSPI2.SPCMD0)
+#define SPCMD1_2 (RSPI2.SPCMD1)
+#define SPCMD2_2 (RSPI2.SPCMD2)
+#define SPCMD3_2 (RSPI2.SPCMD3)
+#define SPBFCR_2 (RSPI2.SPBFCR)
+#define SPBFDR_2 (RSPI2.SPBFDR)
+#define SPCR_3 (RSPI3.SPCR)
+#define SSLP_3 (RSPI3.SSLP)
+#define SPPCR_3 (RSPI3.SPPCR)
+#define SPSR_3 (RSPI3.SPSR)
+#define SPDR_3   (RSPI3.SPDR.UINT32)
+#define SPDR_3L  (RSPI3.SPDR.UINT16[R_IO_L])
+#define SPDR_3H  (RSPI3.SPDR.UINT16[R_IO_H])
+#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL])
+#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH])
+#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL])
+#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH])
+#define SPSCR_3 (RSPI3.SPSCR)
+#define SPSSR_3 (RSPI3.SPSSR)
+#define SPBR_3 (RSPI3.SPBR)
+#define SPDCR_3 (RSPI3.SPDCR)
+#define SPCKD_3 (RSPI3.SPCKD)
+#define SSLND_3 (RSPI3.SSLND)
+#define SPND_3 (RSPI3.SPND)
+#define SPCMD0_3 (RSPI3.SPCMD0)
+#define SPCMD1_3 (RSPI3.SPCMD1)
+#define SPCMD2_3 (RSPI3.SPCMD2)
+#define SPCMD3_3 (RSPI3.SPCMD3)
+#define SPBFCR_3 (RSPI3.SPBFCR)
+#define SPBFDR_3 (RSPI3.SPBFDR)
+#define SPCR_4 (RSPI4.SPCR)
+#define SSLP_4 (RSPI4.SSLP)
+#define SPPCR_4 (RSPI4.SPPCR)
+#define SPSR_4 (RSPI4.SPSR)
+#define SPDR_4   (RSPI4.SPDR.UINT32)
+#define SPDR_4L  (RSPI4.SPDR.UINT16[R_IO_L])
+#define SPDR_4H  (RSPI4.SPDR.UINT16[R_IO_H])
+#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL])
+#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH])
+#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL])
+#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH])
+#define SPSCR_4 (RSPI4.SPSCR)
+#define SPSSR_4 (RSPI4.SPSSR)
+#define SPBR_4 (RSPI4.SPBR)
+#define SPDCR_4 (RSPI4.SPDCR)
+#define SPCKD_4 (RSPI4.SPCKD)
+#define SSLND_4 (RSPI4.SSLND)
+#define SPND_4 (RSPI4.SPND)
+#define SPCMD0_4 (RSPI4.SPCMD0)
+#define SPCMD1_4 (RSPI4.SPCMD1)
+#define SPCMD2_4 (RSPI4.SPCMD2)
+#define SPCMD3_4 (RSPI4.SPCMD3)
+#define SPBFCR_4 (RSPI4.SPBFCR)
+#define SPBFDR_4 (RSPI4.SPBFDR)
+
+#define SPCMD_COUNT (4)
+
+
+typedef struct st_rspi
+{
+                                                           /* RSPI             */
     volatile uint8_t   SPCR;                                   /*  SPCR            */
     volatile uint8_t   SSLP;                                   /*  SSLP            */
     volatile uint8_t   SPPCR;                                  /*  SPPCR           */
     volatile uint8_t   SPSR;                                   /*  SPSR            */
-    union reg32_t  SPDR;                          /*  SPDR            */
+    union iodefine_reg32_t  SPDR;                          /*  SPDR            */
     
     volatile uint8_t   SPSCR;                                  /*  SPSCR           */
     volatile uint8_t   SPSSR;                                  /*  SPSSR           */
@@ -48,7 +194,8 @@
     volatile uint8_t   SSLND;                                  /*  SSLND           */
     volatile uint8_t   SPND;                                   /*  SPND            */
     volatile uint8_t   dummy1[1];                              /*                  */
-#define SPCMD_COUNT 4
+
+/* #define SPCMD_COUNT (4) */
     volatile uint16_t SPCMD0;                                 /*  SPCMD0          */
     volatile uint16_t SPCMD1;                                 /*  SPCMD1          */
     volatile uint16_t SPCMD2;                                 /*  SPCMD2          */
@@ -57,148 +204,21 @@
     volatile uint8_t   SPBFCR;                                 /*  SPBFCR          */
     volatile uint8_t   dummy3[1];                              /*                  */
     volatile uint16_t SPBFDR;                                 /*  SPBFDR          */
-};
-
-
-#define RSPI0   (*(struct st_rspi    *)0xE800C800uL) /* RSPI0 */
-#define RSPI1   (*(struct st_rspi    *)0xE800D000uL) /* RSPI1 */
-#define RSPI2   (*(struct st_rspi    *)0xE800D800uL) /* RSPI2 */
-#define RSPI3   (*(struct st_rspi    *)0xE800E000uL) /* RSPI3 */
-#define RSPI4   (*(struct st_rspi    *)0xE800E800uL) /* RSPI4 */
-
-
-/* Start of channnel array defines of RSPI */
-
-/* Channnel array defines of RSPI */
-/*(Sample) value = RSPI[ channel ]->SPCR; */
-#define RSPI_COUNT  5
-#define RSPI_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of RSPI */
+} r_io_rspi_t;
 
 
-#define SPCR_0 RSPI0.SPCR
-#define SSLP_0 RSPI0.SSLP
-#define SPPCR_0 RSPI0.SPPCR
-#define SPSR_0 RSPI0.SPSR
-#define SPDR_0   RSPI0.SPDR.UINT32
-#define SPDR_0L  RSPI0.SPDR.UINT16[L]
-#define SPDR_0H  RSPI0.SPDR.UINT16[H]
-#define SPDR_0LL RSPI0.SPDR.UINT8[LL]
-#define SPDR_0LH RSPI0.SPDR.UINT8[LH]
-#define SPDR_0HL RSPI0.SPDR.UINT8[HL]
-#define SPDR_0HH RSPI0.SPDR.UINT8[HH]
-#define SPSCR_0 RSPI0.SPSCR
-#define SPSSR_0 RSPI0.SPSSR
-#define SPBR_0 RSPI0.SPBR
-#define SPDCR_0 RSPI0.SPDCR
-#define SPCKD_0 RSPI0.SPCKD
-#define SSLND_0 RSPI0.SSLND
-#define SPND_0 RSPI0.SPND
-#define SPCMD0_0 RSPI0.SPCMD0
-#define SPCMD1_0 RSPI0.SPCMD1
-#define SPCMD2_0 RSPI0.SPCMD2
-#define SPCMD3_0 RSPI0.SPCMD3
-#define SPBFCR_0 RSPI0.SPBFCR
-#define SPBFDR_0 RSPI0.SPBFDR
-#define SPCR_1 RSPI1.SPCR
-#define SSLP_1 RSPI1.SSLP
-#define SPPCR_1 RSPI1.SPPCR
-#define SPSR_1 RSPI1.SPSR
-#define SPDR_1   RSPI1.SPDR.UINT32
-#define SPDR_1L  RSPI1.SPDR.UINT16[L]
-#define SPDR_1H  RSPI1.SPDR.UINT16[H]
-#define SPDR_1LL RSPI1.SPDR.UINT8[LL]
-#define SPDR_1LH RSPI1.SPDR.UINT8[LH]
-#define SPDR_1HL RSPI1.SPDR.UINT8[HL]
-#define SPDR_1HH RSPI1.SPDR.UINT8[HH]
-#define SPSCR_1 RSPI1.SPSCR
-#define SPSSR_1 RSPI1.SPSSR
-#define SPBR_1 RSPI1.SPBR
-#define SPDCR_1 RSPI1.SPDCR
-#define SPCKD_1 RSPI1.SPCKD
-#define SSLND_1 RSPI1.SSLND
-#define SPND_1 RSPI1.SPND
-#define SPCMD0_1 RSPI1.SPCMD0
-#define SPCMD1_1 RSPI1.SPCMD1
-#define SPCMD2_1 RSPI1.SPCMD2
-#define SPCMD3_1 RSPI1.SPCMD3
-#define SPBFCR_1 RSPI1.SPBFCR
-#define SPBFDR_1 RSPI1.SPBFDR
-#define SPCR_2 RSPI2.SPCR
-#define SSLP_2 RSPI2.SSLP
-#define SPPCR_2 RSPI2.SPPCR
-#define SPSR_2 RSPI2.SPSR
-#define SPDR_2   RSPI2.SPDR.UINT32
-#define SPDR_2L  RSPI2.SPDR.UINT16[L]
-#define SPDR_2H  RSPI2.SPDR.UINT16[H]
-#define SPDR_2LL RSPI2.SPDR.UINT8[LL]
-#define SPDR_2LH RSPI2.SPDR.UINT8[LH]
-#define SPDR_2HL RSPI2.SPDR.UINT8[HL]
-#define SPDR_2HH RSPI2.SPDR.UINT8[HH]
-#define SPSCR_2 RSPI2.SPSCR
-#define SPSSR_2 RSPI2.SPSSR
-#define SPBR_2 RSPI2.SPBR
-#define SPDCR_2 RSPI2.SPDCR
-#define SPCKD_2 RSPI2.SPCKD
-#define SSLND_2 RSPI2.SSLND
-#define SPND_2 RSPI2.SPND
-#define SPCMD0_2 RSPI2.SPCMD0
-#define SPCMD1_2 RSPI2.SPCMD1
-#define SPCMD2_2 RSPI2.SPCMD2
-#define SPCMD3_2 RSPI2.SPCMD3
-#define SPBFCR_2 RSPI2.SPBFCR
-#define SPBFDR_2 RSPI2.SPBFDR
-#define SPCR_3 RSPI3.SPCR
-#define SSLP_3 RSPI3.SSLP
-#define SPPCR_3 RSPI3.SPPCR
-#define SPSR_3 RSPI3.SPSR
-#define SPDR_3   RSPI3.SPDR.UINT32
-#define SPDR_3L  RSPI3.SPDR.UINT16[L]
-#define SPDR_3H  RSPI3.SPDR.UINT16[H]
-#define SPDR_3LL RSPI3.SPDR.UINT8[LL]
-#define SPDR_3LH RSPI3.SPDR.UINT8[LH]
-#define SPDR_3HL RSPI3.SPDR.UINT8[HL]
-#define SPDR_3HH RSPI3.SPDR.UINT8[HH]
-#define SPSCR_3 RSPI3.SPSCR
-#define SPSSR_3 RSPI3.SPSSR
-#define SPBR_3 RSPI3.SPBR
-#define SPDCR_3 RSPI3.SPDCR
-#define SPCKD_3 RSPI3.SPCKD
-#define SSLND_3 RSPI3.SSLND
-#define SPND_3 RSPI3.SPND
-#define SPCMD0_3 RSPI3.SPCMD0
-#define SPCMD1_3 RSPI3.SPCMD1
-#define SPCMD2_3 RSPI3.SPCMD2
-#define SPCMD3_3 RSPI3.SPCMD3
-#define SPBFCR_3 RSPI3.SPBFCR
-#define SPBFDR_3 RSPI3.SPBFDR
-#define SPCR_4 RSPI4.SPCR
-#define SSLP_4 RSPI4.SSLP
-#define SPPCR_4 RSPI4.SPPCR
-#define SPSR_4 RSPI4.SPSR
-#define SPDR_4   RSPI4.SPDR.UINT32
-#define SPDR_4L  RSPI4.SPDR.UINT16[L]
-#define SPDR_4H  RSPI4.SPDR.UINT16[H]
-#define SPDR_4LL RSPI4.SPDR.UINT8[LL]
-#define SPDR_4LH RSPI4.SPDR.UINT8[LH]
-#define SPDR_4HL RSPI4.SPDR.UINT8[HL]
-#define SPDR_4HH RSPI4.SPDR.UINT8[HH]
-#define SPSCR_4 RSPI4.SPSCR
-#define SPSSR_4 RSPI4.SPSSR
-#define SPBR_4 RSPI4.SPBR
-#define SPDCR_4 RSPI4.SPDCR
-#define SPCKD_4 RSPI4.SPCKD
-#define SSLND_4 RSPI4.SSLND
-#define SPND_4 RSPI4.SPND
-#define SPCMD0_4 RSPI4.SPCMD0
-#define SPCMD1_4 RSPI4.SPCMD1
-#define SPCMD2_4 RSPI4.SPCMD2
-#define SPCMD3_4 RSPI4.SPCMD3
-#define SPBFCR_4 RSPI4.SPBFCR
-#define SPBFDR_4 RSPI4.SPBFDR
+/* Channel array defines of RSPI (2)*/
+#ifdef  DECLARE_RSPI_CHANNELS
+volatile struct st_rspi*  RSPI[ RSPI_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    RSPI_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_RSPI_CHANNELS */
+/* End of channel array defines of RSPI (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/rtc_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,50 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : rtc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef RTC_IODEFINE_H
 #define RTC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_rtc
-{                                                          /* RTC              */
+#define RTC     (*(struct st_rtc     *)0xFCFF1000uL) /* RTC */
+
+
+#define RTCR64CNT (RTC.R64CNT)
+#define RTCRSECCNT (RTC.RSECCNT)
+#define RTCRMINCNT (RTC.RMINCNT)
+#define RTCRHRCNT (RTC.RHRCNT)
+#define RTCRWKCNT (RTC.RWKCNT)
+#define RTCRDAYCNT (RTC.RDAYCNT)
+#define RTCRMONCNT (RTC.RMONCNT)
+#define RTCRYRCNT (RTC.RYRCNT)
+#define RTCRSECAR (RTC.RSECAR)
+#define RTCRMINAR (RTC.RMINAR)
+#define RTCRHRAR (RTC.RHRAR)
+#define RTCRWKAR (RTC.RWKAR)
+#define RTCRDAYAR (RTC.RDAYAR)
+#define RTCRMONAR (RTC.RMONAR)
+#define RTCRCR1 (RTC.RCR1)
+#define RTCRCR2 (RTC.RCR2)
+#define RTCRYRAR (RTC.RYRAR)
+#define RTCRCR3 (RTC.RCR3)
+#define RTCRCR5 (RTC.RCR5)
+#define RTCRFRH (RTC.RFRH)
+#define RTCRFRL (RTC.RFRL)
+
+
+typedef struct st_rtc
+{
+                                                           /* RTC              */
     volatile uint8_t   R64CNT;                                 /*  R64CNT          */
     volatile uint8_t   dummy537[1];                            /*                  */
     volatile uint8_t   RSECCNT;                                /*  RSECCNT         */
@@ -71,32 +101,11 @@
     volatile uint8_t   dummy554[3];                            /*                  */
     volatile uint16_t RFRH;                                   /*  RFRH            */
     volatile uint16_t RFRL;                                   /*  RFRL            */
-};
-
-
-#define RTC     (*(struct st_rtc     *)0xFCFF1000uL) /* RTC */
+} r_io_rtc_t;
 
 
-#define RTCR64CNT RTC.R64CNT
-#define RTCRSECCNT RTC.RSECCNT
-#define RTCRMINCNT RTC.RMINCNT
-#define RTCRHRCNT RTC.RHRCNT
-#define RTCRWKCNT RTC.RWKCNT
-#define RTCRDAYCNT RTC.RDAYCNT
-#define RTCRMONCNT RTC.RMONCNT
-#define RTCRYRCNT RTC.RYRCNT
-#define RTCRSECAR RTC.RSECAR
-#define RTCRMINAR RTC.RMINAR
-#define RTCRHRAR RTC.RHRAR
-#define RTCRWKAR RTC.RWKAR
-#define RTCRDAYAR RTC.RDAYAR
-#define RTCRMONAR RTC.RMONAR
-#define RTCRCR1 RTC.RCR1
-#define RTCRCR2 RTC.RCR2
-#define RTCRYRAR RTC.RYRAR
-#define RTCRCR3 RTC.RCR3
-#define RTCRCR5 RTC.RCR5
-#define RTCRFRH RTC.RFRH
-#define RTCRFRL RTC.RFRL
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scif_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,21 +18,137 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : scif_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SCIF_IODEFINE_H
 #define SCIF_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
 /* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_scif
-{                                                          /* SCIF             */
+#define SCIF0   (*(struct st_scif    *)0xE8007000uL) /* SCIF0 */
+#define SCIF1   (*(struct st_scif    *)0xE8007800uL) /* SCIF1 */
+#define SCIF2   (*(struct st_scif    *)0xE8008000uL) /* SCIF2 */
+#define SCIF3   (*(struct st_scif    *)0xE8008800uL) /* SCIF3 */
+#define SCIF4   (*(struct st_scif    *)0xE8009000uL) /* SCIF4 */
+#define SCIF5   (*(struct st_scif    *)0xE8009800uL) /* SCIF5 */
+#define SCIF6   (*(struct st_scif    *)0xE800A000uL) /* SCIF6 */
+#define SCIF7   (*(struct st_scif    *)0xE800A800uL) /* SCIF7 */
+
+
+/* Start of channel array defines of SCIF */
+
+/* Channel array defines of SCIF */
+/*(Sample) value = SCIF[ channel ]->SCSMR; */
+#define SCIF_COUNT  (8)
+#define SCIF_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SCIF */
+
+
+#define SCSMR_0 (SCIF0.SCSMR)
+#define SCBRR_0 (SCIF0.SCBRR)
+#define SCSCR_0 (SCIF0.SCSCR)
+#define SCFTDR_0 (SCIF0.SCFTDR)
+#define SCFSR_0 (SCIF0.SCFSR)
+#define SCFRDR_0 (SCIF0.SCFRDR)
+#define SCFCR_0 (SCIF0.SCFCR)
+#define SCFDR_0 (SCIF0.SCFDR)
+#define SCSPTR_0 (SCIF0.SCSPTR)
+#define SCLSR_0 (SCIF0.SCLSR)
+#define SCEMR_0 (SCIF0.SCEMR)
+#define SCSMR_1 (SCIF1.SCSMR)
+#define SCBRR_1 (SCIF1.SCBRR)
+#define SCSCR_1 (SCIF1.SCSCR)
+#define SCFTDR_1 (SCIF1.SCFTDR)
+#define SCFSR_1 (SCIF1.SCFSR)
+#define SCFRDR_1 (SCIF1.SCFRDR)
+#define SCFCR_1 (SCIF1.SCFCR)
+#define SCFDR_1 (SCIF1.SCFDR)
+#define SCSPTR_1 (SCIF1.SCSPTR)
+#define SCLSR_1 (SCIF1.SCLSR)
+#define SCEMR_1 (SCIF1.SCEMR)
+#define SCSMR_2 (SCIF2.SCSMR)
+#define SCBRR_2 (SCIF2.SCBRR)
+#define SCSCR_2 (SCIF2.SCSCR)
+#define SCFTDR_2 (SCIF2.SCFTDR)
+#define SCFSR_2 (SCIF2.SCFSR)
+#define SCFRDR_2 (SCIF2.SCFRDR)
+#define SCFCR_2 (SCIF2.SCFCR)
+#define SCFDR_2 (SCIF2.SCFDR)
+#define SCSPTR_2 (SCIF2.SCSPTR)
+#define SCLSR_2 (SCIF2.SCLSR)
+#define SCEMR_2 (SCIF2.SCEMR)
+#define SCSMR_3 (SCIF3.SCSMR)
+#define SCBRR_3 (SCIF3.SCBRR)
+#define SCSCR_3 (SCIF3.SCSCR)
+#define SCFTDR_3 (SCIF3.SCFTDR)
+#define SCFSR_3 (SCIF3.SCFSR)
+#define SCFRDR_3 (SCIF3.SCFRDR)
+#define SCFCR_3 (SCIF3.SCFCR)
+#define SCFDR_3 (SCIF3.SCFDR)
+#define SCSPTR_3 (SCIF3.SCSPTR)
+#define SCLSR_3 (SCIF3.SCLSR)
+#define SCEMR_3 (SCIF3.SCEMR)
+#define SCSMR_4 (SCIF4.SCSMR)
+#define SCBRR_4 (SCIF4.SCBRR)
+#define SCSCR_4 (SCIF4.SCSCR)
+#define SCFTDR_4 (SCIF4.SCFTDR)
+#define SCFSR_4 (SCIF4.SCFSR)
+#define SCFRDR_4 (SCIF4.SCFRDR)
+#define SCFCR_4 (SCIF4.SCFCR)
+#define SCFDR_4 (SCIF4.SCFDR)
+#define SCSPTR_4 (SCIF4.SCSPTR)
+#define SCLSR_4 (SCIF4.SCLSR)
+#define SCEMR_4 (SCIF4.SCEMR)
+#define SCSMR_5 (SCIF5.SCSMR)
+#define SCBRR_5 (SCIF5.SCBRR)
+#define SCSCR_5 (SCIF5.SCSCR)
+#define SCFTDR_5 (SCIF5.SCFTDR)
+#define SCFSR_5 (SCIF5.SCFSR)
+#define SCFRDR_5 (SCIF5.SCFRDR)
+#define SCFCR_5 (SCIF5.SCFCR)
+#define SCFDR_5 (SCIF5.SCFDR)
+#define SCSPTR_5 (SCIF5.SCSPTR)
+#define SCLSR_5 (SCIF5.SCLSR)
+#define SCEMR_5 (SCIF5.SCEMR)
+#define SCSMR_6 (SCIF6.SCSMR)
+#define SCBRR_6 (SCIF6.SCBRR)
+#define SCSCR_6 (SCIF6.SCSCR)
+#define SCFTDR_6 (SCIF6.SCFTDR)
+#define SCFSR_6 (SCIF6.SCFSR)
+#define SCFRDR_6 (SCIF6.SCFRDR)
+#define SCFCR_6 (SCIF6.SCFCR)
+#define SCFDR_6 (SCIF6.SCFDR)
+#define SCSPTR_6 (SCIF6.SCSPTR)
+#define SCLSR_6 (SCIF6.SCLSR)
+#define SCEMR_6 (SCIF6.SCEMR)
+#define SCSMR_7 (SCIF7.SCSMR)
+#define SCBRR_7 (SCIF7.SCBRR)
+#define SCSCR_7 (SCIF7.SCSCR)
+#define SCFTDR_7 (SCIF7.SCFTDR)
+#define SCFSR_7 (SCIF7.SCFSR)
+#define SCFRDR_7 (SCIF7.SCFRDR)
+#define SCFCR_7 (SCIF7.SCFCR)
+#define SCFDR_7 (SCIF7.SCFDR)
+#define SCSPTR_7 (SCIF7.SCSPTR)
+#define SCLSR_7 (SCIF7.SCLSR)
+#define SCEMR_7 (SCIF7.SCEMR)
+
+
+typedef struct st_scif
+{
+                                                           /* SCIF             */
     volatile uint16_t SCSMR;                                  /*  SCSMR           */
     volatile uint8_t   dummy1[2];                              /*                  */
     volatile uint8_t   SCBRR;                                  /*  SCBRR           */
@@ -54,129 +170,21 @@
     volatile uint16_t SCLSR;                                  /*  SCLSR           */
     volatile uint8_t   dummy10[2];                             /*                  */
     volatile uint16_t SCEMR;                                  /*  SCEMR           */
-};
-
-
-#define SCIF0   (*(struct st_scif    *)0xE8007000uL) /* SCIF0 */
-#define SCIF1   (*(struct st_scif    *)0xE8007800uL) /* SCIF1 */
-#define SCIF2   (*(struct st_scif    *)0xE8008000uL) /* SCIF2 */
-#define SCIF3   (*(struct st_scif    *)0xE8008800uL) /* SCIF3 */
-#define SCIF4   (*(struct st_scif    *)0xE8009000uL) /* SCIF4 */
-#define SCIF5   (*(struct st_scif    *)0xE8009800uL) /* SCIF5 */
-#define SCIF6   (*(struct st_scif    *)0xE800A000uL) /* SCIF6 */
-#define SCIF7   (*(struct st_scif    *)0xE800A800uL) /* SCIF7 */
-
-#define P_SCIF0   (0xE8007000uL) /* SCIF0 */
-#define P_SCIF1   (0xE8007800uL) /* SCIF1 */
-#define P_SCIF2   (0xE8008000uL) /* SCIF2 */
-#define P_SCIF3   (0xE8008800uL) /* SCIF3 */
-#define P_SCIF4   (0xE8009000uL) /* SCIF4 */
-#define P_SCIF5   (0xE8009800uL) /* SCIF5 */
-#define P_SCIF6   (0xE800A000uL) /* SCIF6 */
-#define P_SCIF7   (0xE800A800uL) /* SCIF7 */
-
-
-/* Start of channnel array defines of SCIF */
-
-/* Channnel array defines of SCIF */
-/*(Sample) value = SCIF[ channel ]->SCSMR; */
-#define SCIF_COUNT  8
-#define SCIF_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of SCIF */
+} r_io_scif_t;
 
 
-#define SCSMR_0 SCIF0.SCSMR
-#define SCBRR_0 SCIF0.SCBRR
-#define SCSCR_0 SCIF0.SCSCR
-#define SCFTDR_0 SCIF0.SCFTDR
-#define SCFSR_0 SCIF0.SCFSR
-#define SCFRDR_0 SCIF0.SCFRDR
-#define SCFCR_0 SCIF0.SCFCR
-#define SCFDR_0 SCIF0.SCFDR
-#define SCSPTR_0 SCIF0.SCSPTR
-#define SCLSR_0 SCIF0.SCLSR
-#define SCEMR_0 SCIF0.SCEMR
-#define SCSMR_1 SCIF1.SCSMR
-#define SCBRR_1 SCIF1.SCBRR
-#define SCSCR_1 SCIF1.SCSCR
-#define SCFTDR_1 SCIF1.SCFTDR
-#define SCFSR_1 SCIF1.SCFSR
-#define SCFRDR_1 SCIF1.SCFRDR
-#define SCFCR_1 SCIF1.SCFCR
-#define SCFDR_1 SCIF1.SCFDR
-#define SCSPTR_1 SCIF1.SCSPTR
-#define SCLSR_1 SCIF1.SCLSR
-#define SCEMR_1 SCIF1.SCEMR
-#define SCSMR_2 SCIF2.SCSMR
-#define SCBRR_2 SCIF2.SCBRR
-#define SCSCR_2 SCIF2.SCSCR
-#define SCFTDR_2 SCIF2.SCFTDR
-#define SCFSR_2 SCIF2.SCFSR
-#define SCFRDR_2 SCIF2.SCFRDR
-#define SCFCR_2 SCIF2.SCFCR
-#define SCFDR_2 SCIF2.SCFDR
-#define SCSPTR_2 SCIF2.SCSPTR
-#define SCLSR_2 SCIF2.SCLSR
-#define SCEMR_2 SCIF2.SCEMR
-#define SCSMR_3 SCIF3.SCSMR
-#define SCBRR_3 SCIF3.SCBRR
-#define SCSCR_3 SCIF3.SCSCR
-#define SCFTDR_3 SCIF3.SCFTDR
-#define SCFSR_3 SCIF3.SCFSR
-#define SCFRDR_3 SCIF3.SCFRDR
-#define SCFCR_3 SCIF3.SCFCR
-#define SCFDR_3 SCIF3.SCFDR
-#define SCSPTR_3 SCIF3.SCSPTR
-#define SCLSR_3 SCIF3.SCLSR
-#define SCEMR_3 SCIF3.SCEMR
-#define SCSMR_4 SCIF4.SCSMR
-#define SCBRR_4 SCIF4.SCBRR
-#define SCSCR_4 SCIF4.SCSCR
-#define SCFTDR_4 SCIF4.SCFTDR
-#define SCFSR_4 SCIF4.SCFSR
-#define SCFRDR_4 SCIF4.SCFRDR
-#define SCFCR_4 SCIF4.SCFCR
-#define SCFDR_4 SCIF4.SCFDR
-#define SCSPTR_4 SCIF4.SCSPTR
-#define SCLSR_4 SCIF4.SCLSR
-#define SCEMR_4 SCIF4.SCEMR
-#define SCSMR_5 SCIF5.SCSMR
-#define SCBRR_5 SCIF5.SCBRR
-#define SCSCR_5 SCIF5.SCSCR
-#define SCFTDR_5 SCIF5.SCFTDR
-#define SCFSR_5 SCIF5.SCFSR
-#define SCFRDR_5 SCIF5.SCFRDR
-#define SCFCR_5 SCIF5.SCFCR
-#define SCFDR_5 SCIF5.SCFDR
-#define SCSPTR_5 SCIF5.SCSPTR
-#define SCLSR_5 SCIF5.SCLSR
-#define SCEMR_5 SCIF5.SCEMR
-#define SCSMR_6 SCIF6.SCSMR
-#define SCBRR_6 SCIF6.SCBRR
-#define SCSCR_6 SCIF6.SCSCR
-#define SCFTDR_6 SCIF6.SCFTDR
-#define SCFSR_6 SCIF6.SCFSR
-#define SCFRDR_6 SCIF6.SCFRDR
-#define SCFCR_6 SCIF6.SCFCR
-#define SCFDR_6 SCIF6.SCFDR
-#define SCSPTR_6 SCIF6.SCSPTR
-#define SCLSR_6 SCIF6.SCLSR
-#define SCEMR_6 SCIF6.SCEMR
-#define SCSMR_7 SCIF7.SCSMR
-#define SCBRR_7 SCIF7.SCBRR
-#define SCSCR_7 SCIF7.SCSCR
-#define SCFTDR_7 SCIF7.SCFTDR
-#define SCFSR_7 SCIF7.SCFSR
-#define SCFRDR_7 SCIF7.SCFRDR
-#define SCFCR_7 SCIF7.SCFCR
-#define SCFDR_7 SCIF7.SCFDR
-#define SCSPTR_7 SCIF7.SCSPTR
-#define SCLSR_7 SCIF7.SCLSR
-#define SCEMR_7 SCIF7.SCEMR
+/* Channel array defines of SCIF (2)*/
+#ifdef  DECLARE_SCIF_CHANNELS
+volatile struct st_scif*  SCIF[ SCIF_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCIF_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCIF_CHANNELS */
+/* End of channel array defines of SCIF (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
 /* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scim_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,63 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : scim_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SCIM_IODEFINE_H
 #define SCIM_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_scim
-{                                                          /* SCIM             */
+#define SCIM0   (*(struct st_scim    *)0xE800B000uL) /* SCIM0 */
+#define SCIM1   (*(struct st_scim    *)0xE800B800uL) /* SCIM1 */
+
+
+/* Start of channel array defines of SCIM */
+
+/* Channel array defines of SCIM */
+/*(Sample) value = SCIM[ channel ]->SMR; */
+#define SCIM_COUNT  (2)
+#define SCIM_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCIM0, &SCIM1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SCIM */
+
+
+#define SMR0 (SCIM0.SMR)
+#define BRR0 (SCIM0.BRR)
+#define SCR0 (SCIM0.SCR)
+#define TDR0 (SCIM0.TDR)
+#define SSR0 (SCIM0.SSR)
+#define RDR0 (SCIM0.RDR)
+#define SCMR0 (SCIM0.SCMR)
+#define SEMR0 (SCIM0.SEMR)
+#define SNFR0 (SCIM0.SNFR)
+#define SECR0 (SCIM0.SECR)
+#define SMR1 (SCIM1.SMR)
+#define BRR1 (SCIM1.BRR)
+#define SCR1 (SCIM1.SCR)
+#define TDR1 (SCIM1.TDR)
+#define SSR1 (SCIM1.SSR)
+#define RDR1 (SCIM1.RDR)
+#define SCMR1 (SCIM1.SCMR)
+#define SEMR1 (SCIM1.SEMR)
+#define SNFR1 (SCIM1.SNFR)
+#define SECR1 (SCIM1.SECR)
+
+
+typedef struct st_scim
+{
+                                                           /* SCIM             */
     volatile uint8_t   SMR;                                    /*  SMR             */
     volatile uint8_t   BRR;                                    /*  BRR             */
     volatile uint8_t   SCR;                                    /*  SCR             */
@@ -43,45 +86,21 @@
     volatile uint8_t   SNFR;                                   /*  SNFR            */
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint8_t   SECR;                                   /*  SECR            */
-};
-
-
-#define SCIM0   (*(struct st_scim    *)0xE800B000uL) /* SCIM0 */
-#define SCIM1   (*(struct st_scim    *)0xE800B800uL) /* SCIM1 */
-
-
-/* Start of channnel array defines of SCIM */
-
-/* Channnel array defines of SCIM */
-/*(Sample) value = SCIM[ channel ]->SMR; */
-#define SCIM_COUNT  2
-#define SCIM_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCIM0, &SCIM1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of SCIM */
+} r_io_scim_t;
 
 
-#define SMR0 SCIM0.SMR
-#define BRR0 SCIM0.BRR
-#define SCR0 SCIM0.SCR
-#define TDR0 SCIM0.TDR
-#define SSR0 SCIM0.SSR
-#define RDR0 SCIM0.RDR
-#define SCMR0 SCIM0.SCMR
-#define SEMR0 SCIM0.SEMR
-#define SNFR0 SCIM0.SNFR
-#define SECR0 SCIM0.SECR
-#define SMR1 SCIM1.SMR
-#define BRR1 SCIM1.BRR
-#define SCR1 SCIM1.SCR
-#define TDR1 SCIM1.TDR
-#define SSR1 SCIM1.SSR
-#define RDR1 SCIM1.RDR
-#define SCMR1 SCIM1.SCMR
-#define SEMR1 SCIM1.SEMR
-#define SNFR1 SCIM1.SNFR
-#define SECR1 SCIM1.SECR
+/* Channel array defines of SCIM (2)*/
+#ifdef  DECLARE_SCIM_CHANNELS
+volatile struct st_scim*  SCIM[ SCIM_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCIM_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCIM_CHANNELS */
+/* End of channel array defines of SCIM (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/scux_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,61 +18,427 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : scux_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SCUX_IODEFINE_H
 #define SCUX_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_scux
-{                                                          /* SCUX             */
+#define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
+
+
+/* Start of channel array defines of SCUX */
+
+/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
+#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
+#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
+#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
+
+
+/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  (2)
+#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
+#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
+
+
+/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
+#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
+#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
+#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
+
+
+/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
+#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
+#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
+#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
+
+
+/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
+#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
+#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
+#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
+
+
+/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
+/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  (4)
+#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
+#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
+#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
+#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
+
+/* End of channel array defines of SCUX */
+
+
+#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0)
+#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0)
+#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1)
+#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1)
+#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2)
+#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2)
+#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3)
+#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3)
+#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0)
+#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0)
+#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1)
+#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1)
+#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2)
+#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2)
+#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3)
+#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3)
+#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0)
+#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0)
+#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0)
+#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0)
+#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0)
+#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0)
+#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0)
+#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1)
+#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1)
+#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1)
+#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1)
+#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1)
+#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1)
+#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1)
+#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2)
+#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2)
+#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2)
+#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2)
+#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2)
+#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2)
+#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2)
+#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3)
+#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3)
+#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3)
+#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3)
+#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3)
+#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3)
+#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3)
+#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0)
+#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0)
+#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0)
+#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0)
+#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0)
+#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0)
+#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1)
+#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1)
+#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1)
+#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1)
+#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1)
+#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1)
+#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2)
+#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2)
+#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2)
+#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2)
+#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2)
+#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2)
+#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3)
+#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3)
+#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3)
+#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3)
+#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3)
+#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3)
+#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0)
+#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0)
+#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0)
+#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0)
+#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0)
+#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0)
+#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0)
+#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0)
+#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0)
+#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0)
+#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0)
+#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0)
+#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0)
+#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0)
+#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0)
+#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0)
+#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0)
+#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0)
+#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0)
+#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0)
+#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0)
+#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0)
+#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0)
+#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0)
+#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0)
+#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1)
+#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1)
+#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1)
+#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1)
+#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1)
+#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1)
+#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1)
+#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1)
+#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1)
+#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1)
+#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1)
+#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1)
+#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1)
+#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1)
+#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1)
+#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1)
+#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1)
+#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1)
+#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1)
+#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1)
+#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1)
+#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1)
+#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1)
+#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1)
+#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1)
+#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0)
+#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0)
+#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0)
+#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0)
+#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0)
+#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0)
+#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0)
+#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0)
+#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0)
+#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0)
+#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0)
+#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0)
+#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0)
+#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0)
+#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0)
+#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0)
+#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0)
+#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0)
+#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0)
+#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0)
+#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0)
+#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1)
+#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1)
+#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1)
+#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1)
+#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1)
+#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1)
+#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1)
+#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1)
+#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1)
+#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1)
+#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1)
+#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1)
+#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1)
+#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1)
+#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1)
+#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1)
+#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1)
+#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1)
+#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1)
+#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1)
+#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1)
+#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2)
+#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2)
+#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2)
+#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2)
+#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2)
+#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2)
+#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2)
+#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2)
+#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2)
+#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2)
+#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2)
+#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2)
+#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2)
+#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2)
+#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2)
+#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2)
+#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2)
+#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2)
+#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2)
+#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2)
+#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2)
+#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3)
+#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3)
+#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3)
+#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3)
+#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3)
+#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3)
+#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3)
+#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3)
+#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3)
+#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3)
+#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3)
+#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3)
+#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3)
+#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3)
+#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3)
+#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3)
+#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3)
+#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3)
+#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3)
+#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3)
+#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3)
+#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0)
+#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0)
+#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0)
+#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0)
+#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0)
+#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0)
+#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0)
+#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0)
+#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0)
+#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0)
+#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0)
+#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM)
+#define SCUXDMACR_CIM (SCUX.DMACR_CIM)
+#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32)
+#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L])
+#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H])
+#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32)
+#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L])
+#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H])
+#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32)
+#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L])
+#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H])
+#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32)
+#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L])
+#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H])
+#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32)
+#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L])
+#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H])
+#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32)
+#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L])
+#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H])
+#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32)
+#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L])
+#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H])
+#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32)
+#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L])
+#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H])
+#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM)
+#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM)
+#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM)
+#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM)
+#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM)
+#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM)
+#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM)
+#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM)
+#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM)
+#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM)
+#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM)
+#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM)
+#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM)
+#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM)
+#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM)
+#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM)
+
+#define SCUX_DMATDnCIM_COUNT (4)
+#define SCUX_DMATUnCIM_COUNT (4)
+#define SCUX_FDTSELnCIM_COUNT (4)
+#define SCUX_FUTSELnCIM_COUNT (4)
+#define SCUX_SRCRSELnCIM_COUNT (4)
+
+
+typedef struct st_scux
+{
+                                                           /* SCUX             */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
     volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
     volatile uint8_t   dummy259[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_1;                           /*  IPCIR_IPC0_1    */
     volatile uint32_t  IPSLR_IPC0_1;                           /*  IPSLR_IPC0_1    */
     volatile uint8_t   dummy260[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_2;                           /*  IPCIR_IPC0_2    */
     volatile uint32_t  IPSLR_IPC0_2;                           /*  IPSLR_IPC0_2    */
     volatile uint8_t   dummy261[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_ipcir_ipc0_n */
     volatile uint32_t  IPCIR_IPC0_3;                           /*  IPCIR_IPC0_3    */
     volatile uint32_t  IPSLR_IPC0_3;                           /*  IPSLR_IPC0_3    */
     volatile uint8_t   dummy262[248];                          /*                  */
+
 /* end of struct st_scux_from_ipcir_ipc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
     volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
     volatile uint8_t   dummy263[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_1;                           /*  OPCIR_OPC0_1    */
     volatile uint32_t  OPSLR_OPC0_1;                           /*  OPSLR_OPC0_1    */
     volatile uint8_t   dummy264[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_2;                           /*  OPCIR_OPC0_2    */
     volatile uint32_t  OPSLR_OPC0_2;                           /*  OPSLR_OPC0_2    */
     volatile uint8_t   dummy265[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_opcir_opc0_n */
     volatile uint32_t  OPCIR_OPC0_3;                           /*  OPCIR_OPC0_3    */
     volatile uint32_t  OPSLR_OPC0_3;                           /*  OPSLR_OPC0_3    */
     volatile uint8_t   dummy266[248];                          /*                  */
+
 /* end of struct st_scux_from_opcir_opc0_n */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
     volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
@@ -82,8 +448,10 @@
     volatile uint32_t  DEVMR_FFD0_0;                           /*  DEVMR_FFD0_0    */
     volatile uint8_t   dummy267[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy268[224];                          /*                  */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_1;                           /*  FFDIR_FFD0_1    */
     volatile uint32_t  FDAIR_FFD0_1;                           /*  FDAIR_FFD0_1    */
@@ -93,8 +461,10 @@
     volatile uint32_t  DEVMR_FFD0_1;                           /*  DEVMR_FFD0_1    */
     volatile uint8_t   dummy269[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_1;                           /*  DEVCR_FFD0_1    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy270[224];                          /*                  */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_2;                           /*  FFDIR_FFD0_2    */
     volatile uint32_t  FDAIR_FFD0_2;                           /*  FDAIR_FFD0_2    */
@@ -104,8 +474,10 @@
     volatile uint32_t  DEVMR_FFD0_2;                           /*  DEVMR_FFD0_2    */
     volatile uint8_t   dummy271[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_2;                           /*  DEVCR_FFD0_2    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy272[224];                          /*                  */
+
 /* start of struct st_scux_from_ffdir_ffd0_n */
     volatile uint32_t  FFDIR_FFD0_3;                           /*  FFDIR_FFD0_3    */
     volatile uint32_t  FDAIR_FFD0_3;                           /*  FDAIR_FFD0_3    */
@@ -115,8 +487,10 @@
     volatile uint32_t  DEVMR_FFD0_3;                           /*  DEVMR_FFD0_3    */
     volatile uint8_t   dummy273[4];                            /*                  */
     volatile uint32_t  DEVCR_FFD0_3;                           /*  DEVCR_FFD0_3    */
+
 /* end of struct st_scux_from_ffdir_ffd0_n */
     volatile uint8_t   dummy274[224];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
     volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
@@ -125,8 +499,10 @@
     volatile uint32_t  UEVMR_FFU0_0;                           /*  UEVMR_FFU0_0    */
     volatile uint8_t   dummy275[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy276[228];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_1;                           /*  FFUIR_FFU0_1    */
     volatile uint32_t  FUAIR_FFU0_1;                           /*  FUAIR_FFU0_1    */
@@ -135,8 +511,10 @@
     volatile uint32_t  UEVMR_FFU0_1;                           /*  UEVMR_FFU0_1    */
     volatile uint8_t   dummy277[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_1;                           /*  UEVCR_FFU0_1    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy278[228];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_2;                           /*  FFUIR_FFU0_2    */
     volatile uint32_t  FUAIR_FFU0_2;                           /*  FUAIR_FFU0_2    */
@@ -145,8 +523,10 @@
     volatile uint32_t  UEVMR_FFU0_2;                           /*  UEVMR_FFU0_2    */
     volatile uint8_t   dummy279[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_2;                           /*  UEVCR_FFU0_2    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy280[228];                          /*                  */
+
 /* start of struct st_scux_from_ffuir_ffu0_n */
     volatile uint32_t  FFUIR_FFU0_3;                           /*  FFUIR_FFU0_3    */
     volatile uint32_t  FUAIR_FFU0_3;                           /*  FUAIR_FFU0_3    */
@@ -155,8 +535,10 @@
     volatile uint32_t  UEVMR_FFU0_3;                           /*  UEVMR_FFU0_3    */
     volatile uint8_t   dummy281[4];                            /*                  */
     volatile uint32_t  UEVCR_FFU0_3;                           /*  UEVCR_FFU0_3    */
+
 /* end of struct st_scux_from_ffuir_ffu0_n */
     volatile uint8_t   dummy282[228];                          /*                  */
+
 /* start of struct st_scux_from_srcir0_2src0_n */
     volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
     volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
@@ -185,8 +567,10 @@
     volatile uint8_t   dummy284[4];                            /*                  */
     volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
     volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
+
 /* end of struct st_scux_from_srcir0_2src0_n */
     volatile uint8_t   dummy285[148];                          /*                  */
+
 /* start of struct st_scux_from_srcir0_2src0_n */
     volatile uint32_t  SRCIR0_2SRC0_1;                         /*  SRCIR0_2SRC0_1  */
     volatile uint32_t  SADIR0_2SRC0_1;                         /*  SADIR0_2SRC0_1  */
@@ -215,8 +599,10 @@
     volatile uint8_t   dummy287[4];                            /*                  */
     volatile uint32_t  SEVCR1_2SRC0_1;                         /*  SEVCR1_2SRC0_1  */
     volatile uint32_t  SRCIRR_2SRC0_1;                         /*  SRCIRR_2SRC0_1  */
+
 /* end of struct st_scux_from_srcir0_2src0_n */
     volatile uint8_t   dummy288[148];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
     volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
@@ -240,8 +626,10 @@
     volatile uint32_t  VEVMR_DVU0_0;                           /*  VEVMR_DVU0_0    */
     volatile uint8_t   dummy289[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy290[168];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_1;                           /*  DVUIR_DVU0_1    */
     volatile uint32_t  VADIR_DVU0_1;                           /*  VADIR_DVU0_1    */
@@ -265,8 +653,10 @@
     volatile uint32_t  VEVMR_DVU0_1;                           /*  VEVMR_DVU0_1    */
     volatile uint8_t   dummy291[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_1;                           /*  VEVCR_DVU0_1    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy292[168];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_2;                           /*  DVUIR_DVU0_2    */
     volatile uint32_t  VADIR_DVU0_2;                           /*  VADIR_DVU0_2    */
@@ -290,8 +680,10 @@
     volatile uint32_t  VEVMR_DVU0_2;                           /*  VEVMR_DVU0_2    */
     volatile uint8_t   dummy293[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_2;                           /*  VEVCR_DVU0_2    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy294[168];                          /*                  */
+
 /* start of struct st_scux_from_dvuir_dvu0_n */
     volatile uint32_t  DVUIR_DVU0_3;                           /*  DVUIR_DVU0_3    */
     volatile uint32_t  VADIR_DVU0_3;                           /*  VADIR_DVU0_3    */
@@ -315,6 +707,7 @@
     volatile uint32_t  VEVMR_DVU0_3;                           /*  VEVMR_DVU0_3    */
     volatile uint8_t   dummy295[4];                            /*                  */
     volatile uint32_t  VEVCR_DVU0_3;                           /*  VEVCR_DVU0_3    */
+
 /* end of struct st_scux_from_dvuir_dvu0_n */
     volatile uint8_t   dummy296[168];                          /*                  */
     volatile uint32_t  MIXIR_MIX0_0;                           /*  MIXIR_MIX0_0    */
@@ -331,12 +724,14 @@
     volatile uint8_t   dummy297[212];                          /*                  */
     volatile uint32_t  SWRSR_CIM;                              /*  SWRSR_CIM       */
     volatile uint32_t  DMACR_CIM;                              /*  DMACR_CIM       */
-#define SCUX_DMATDn_CIM_COUNT 4
+
+/* #define SCUX_DMATDnCIM_COUNT (4) */
     union iodefine_reg32_16_t  DMATD0_CIM;                 /*  DMATD0_CIM      */
     union iodefine_reg32_16_t  DMATD1_CIM;                 /*  DMATD1_CIM      */
     union iodefine_reg32_16_t  DMATD2_CIM;                 /*  DMATD2_CIM      */
     union iodefine_reg32_16_t  DMATD3_CIM;                 /*  DMATD3_CIM      */
-#define SCUX_DMATUn_CIM_COUNT 4
+
+/* #define SCUX_DMATUnCIM_COUNT (4) */
     union iodefine_reg32_16_t  DMATU0_CIM;                 /*  DMATU0_CIM      */
     union iodefine_reg32_16_t  DMATU1_CIM;                 /*  DMATU1_CIM      */
     union iodefine_reg32_16_t  DMATU2_CIM;                 /*  DMATU2_CIM      */
@@ -344,45 +739,51 @@
     
     volatile uint8_t   dummy298[16];                           /*                  */
     volatile uint32_t  SSIRSEL_CIM;                            /*  SSIRSEL_CIM     */
-#define SCUX_FDTSELn_CIM_COUNT 4
+
+/* #define SCUX_FDTSELnCIM_COUNT (4) */
     volatile uint32_t  FDTSEL0_CIM;                            /*  FDTSEL0_CIM     */
     volatile uint32_t  FDTSEL1_CIM;                            /*  FDTSEL1_CIM     */
     volatile uint32_t  FDTSEL2_CIM;                            /*  FDTSEL2_CIM     */
     volatile uint32_t  FDTSEL3_CIM;                            /*  FDTSEL3_CIM     */
-#define SCUX_FUTSELn_CIM_COUNT 4
+
+/* #define SCUX_FUTSELnCIM_COUNT (4) */
     volatile uint32_t  FUTSEL0_CIM;                            /*  FUTSEL0_CIM     */
     volatile uint32_t  FUTSEL1_CIM;                            /*  FUTSEL1_CIM     */
     volatile uint32_t  FUTSEL2_CIM;                            /*  FUTSEL2_CIM     */
     volatile uint32_t  FUTSEL3_CIM;                            /*  FUTSEL3_CIM     */
     volatile uint32_t  SSIPMD_CIM;                             /*  SSIPMD_CIM      */
     volatile uint32_t  SSICTRL_CIM;                            /*  SSICTRL_CIM     */
-#define SCUX_SRCRSELn_CIM_COUNT 4
+
+/* #define SCUX_SRCRSELnCIM_COUNT (4) */
     volatile uint32_t  SRCRSEL0_CIM;                           /*  SRCRSEL0_CIM    */
     volatile uint32_t  SRCRSEL1_CIM;                           /*  SRCRSEL1_CIM    */
     volatile uint32_t  SRCRSEL2_CIM;                           /*  SRCRSEL2_CIM    */
     volatile uint32_t  SRCRSEL3_CIM;                           /*  SRCRSEL3_CIM    */
     volatile uint32_t  MIXRSEL_CIM;                            /*  MIXRSEL_CIM     */
-};
+} r_io_scux_t;
 
 
-struct st_scux_from_ipcir_ipc0_n
+typedef struct st_scux_from_ipcir_ipc0_n
 {
+ 
     volatile uint32_t  IPCIR_IPC0_0;                           /*  IPCIR_IPC0_0    */
     volatile uint32_t  IPSLR_IPC0_0;                           /*  IPSLR_IPC0_0    */
     volatile uint8_t   dummy1[248];                            /*                  */
-};
+} r_io_scux_from_ipcir_ipc0_n_t;
 
 
-struct st_scux_from_opcir_opc0_n
+typedef struct st_scux_from_opcir_opc0_n
 {
+ 
     volatile uint32_t  OPCIR_OPC0_0;                           /*  OPCIR_OPC0_0    */
     volatile uint32_t  OPSLR_OPC0_0;                           /*  OPSLR_OPC0_0    */
     volatile uint8_t   dummy1[248];                            /*                  */
-};
+} r_io_scux_from_opcir_opc0_n_t;
 
 
-struct st_scux_from_ffdir_ffd0_n
+typedef struct st_scux_from_ffdir_ffd0_n
 {
+ 
     volatile uint32_t  FFDIR_FFD0_0;                           /*  FFDIR_FFD0_0    */
     volatile uint32_t  FDAIR_FFD0_0;                           /*  FDAIR_FFD0_0    */
     volatile uint32_t  DRQSR_FFD0_0;                           /*  DRQSR_FFD0_0    */
@@ -391,11 +792,12 @@
     volatile uint32_t  DEVMR_FFD0_0;                           /*  DEVMR_FFD0_0    */
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint32_t  DEVCR_FFD0_0;                           /*  DEVCR_FFD0_0    */
-};
+} r_io_scux_from_ffdir_ffd0_n_t;
 
 
-struct st_scux_from_ffuir_ffu0_n
+typedef struct st_scux_from_ffuir_ffu0_n
 {
+ 
     volatile uint32_t  FFUIR_FFU0_0;                           /*  FFUIR_FFU0_0    */
     volatile uint32_t  FUAIR_FFU0_0;                           /*  FUAIR_FFU0_0    */
     volatile uint32_t  URQSR_FFU0_0;                           /*  URQSR_FFU0_0    */
@@ -403,11 +805,12 @@
     volatile uint32_t  UEVMR_FFU0_0;                           /*  UEVMR_FFU0_0    */
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint32_t  UEVCR_FFU0_0;                           /*  UEVCR_FFU0_0    */
-};
+} r_io_scux_from_ffuir_ffu0_n_t;
 
 
-struct st_scux_from_srcir0_2src0_n
+typedef struct st_scux_from_srcir0_2src0_n
 {
+ 
     volatile uint32_t  SRCIR0_2SRC0_0;                         /*  SRCIR0_2SRC0_0  */
     volatile uint32_t  SADIR0_2SRC0_0;                         /*  SADIR0_2SRC0_0  */
     volatile uint32_t  SRCBR0_2SRC0_0;                         /*  SRCBR0_2SRC0_0  */
@@ -435,11 +838,12 @@
     volatile uint8_t   dummy2[4];                              /*                  */
     volatile uint32_t  SEVCR1_2SRC0_0;                         /*  SEVCR1_2SRC0_0  */
     volatile uint32_t  SRCIRR_2SRC0_0;                         /*  SRCIRR_2SRC0_0  */
-};
+} r_io_scux_from_srcir0_2src0_n_t;
 
 
-struct st_scux_from_dvuir_dvu0_n
+typedef struct st_scux_from_dvuir_dvu0_n
 {
+ 
     volatile uint32_t  DVUIR_DVU0_0;                           /*  DVUIR_DVU0_0    */
     volatile uint32_t  VADIR_DVU0_0;                           /*  VADIR_DVU0_0    */
     volatile uint32_t  DVUBR_DVU0_0;                           /*  DVUBR_DVU0_0    */
@@ -462,347 +866,56 @@
     volatile uint32_t  VEVMR_DVU0_0;                           /*  VEVMR_DVU0_0    */
     volatile uint8_t   dummy1[4];                              /*                  */
     volatile uint32_t  VEVCR_DVU0_0;                           /*  VEVCR_DVU0_0    */
-};
-
-
-#define SCUX    (*(struct st_scux    *)0xE8208000uL) /* SCUX */
-
-
-/* Start of channnel array defines of SCUX */
-
-/* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
-#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT  4
-#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
-#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
-#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
-#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
-#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT  2
-#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
-#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
-
-
-/* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
-#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT  4
-#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
-#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
-#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
-#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
-#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT  4
-#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
-#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
-#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
-#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
-#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT  4
-#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
-#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
-#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
-#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
-
-
-/* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
-/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
-#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT  4
-#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
-#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
-#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
-#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
-
-/* End of channnel array defines of SCUX */
+} r_io_scux_from_dvuir_dvu0_n_t;
 
 
-#define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
-#define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
-#define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
-#define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
-#define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
-#define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
-#define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
-#define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
-#define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
-#define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
-#define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
-#define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
-#define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
-#define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
-#define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
-#define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
-#define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
-#define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
-#define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
-#define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
-#define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
-#define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
-#define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
-#define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
-#define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
-#define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
-#define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
-#define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
-#define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
-#define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
-#define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
-#define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
-#define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
-#define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
-#define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
-#define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
-#define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
-#define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
-#define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
-#define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
-#define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
-#define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
-#define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
-#define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
-#define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
-#define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
-#define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
-#define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
-#define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
-#define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
-#define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
-#define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
-#define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
-#define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
-#define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
-#define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
-#define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
-#define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
-#define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
-#define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
-#define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
-#define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
-#define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
-#define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
-#define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
-#define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
-#define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
-#define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
-#define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
-#define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
-#define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
-#define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
-#define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
-#define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
-#define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
-#define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
-#define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
-#define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
-#define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
-#define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
-#define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
-#define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
-#define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
-#define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
-#define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
-#define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
-#define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
-#define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
-#define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
-#define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
-#define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
-#define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
-#define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
-#define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
-#define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
-#define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
-#define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
-#define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
-#define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
-#define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
-#define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
-#define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
-#define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
-#define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
-#define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
-#define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
-#define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
-#define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
-#define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
-#define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
-#define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
-#define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
-#define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
-#define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
-#define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
-#define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
-#define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
-#define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
-#define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
-#define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
-#define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
-#define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
-#define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
-#define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
-#define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
-#define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
-#define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
-#define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
-#define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
-#define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
-#define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
-#define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
-#define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
-#define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
-#define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
-#define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
-#define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
-#define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
-#define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
-#define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
-#define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
-#define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
-#define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
-#define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
-#define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
-#define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
-#define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
-#define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
-#define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
-#define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
-#define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
-#define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
-#define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
-#define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
-#define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
-#define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
-#define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
-#define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
-#define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
-#define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
-#define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
-#define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
-#define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
-#define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
-#define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
-#define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
-#define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
-#define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
-#define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
-#define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
-#define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
-#define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
-#define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
-#define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
-#define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
-#define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
-#define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
-#define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
-#define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
-#define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
-#define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
-#define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
-#define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
-#define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
-#define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
-#define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
-#define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
-#define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
-#define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
-#define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
-#define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
-#define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
-#define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
-#define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
-#define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
-#define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
-#define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
-#define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
-#define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
-#define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
-#define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
-#define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
-#define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
-#define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
-#define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
-#define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
-#define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
-#define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
-#define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
-#define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
-#define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
-#define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
-#define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
-#define SCUXSWRSR_CIM SCUX.SWRSR_CIM
-#define SCUXDMACR_CIM SCUX.DMACR_CIM
-#define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
-#define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
-#define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
-#define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
-#define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
-#define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
-#define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
-#define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
-#define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
-#define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
-#define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
-#define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
-#define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
-#define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
-#define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
-#define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
-#define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
-#define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
-#define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
-#define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
-#define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
-#define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
-#define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
-#define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
-#define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
-#define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
-#define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
-#define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
-#define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
-#define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
-#define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
-#define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
-#define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
-#define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
-#define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
-#define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
-#define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
-#define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
-#define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
-#define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
+/* Channel array defines of SCUX (2)*/
+#ifdef  DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_dvuir_dvu0_n*  SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_srcir0_2src0_n*  SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ffuir_ffu0_n*  SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ffdir_ffd0_n*  SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_opcir_opc0_n*  SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS
+volatile struct st_scux_from_ipcir_ipc0_n*  SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */
+/* End of channel array defines of SCUX (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/sdg_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,27 +18,20 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : sdg_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SDG_IODEFINE_H
 #define SDG_IODEFINE_H
-
-struct st_sdg
-{                                                          /* SDG              */
-    volatile uint8_t   SGCR1;                                  /*  SGCR1           */
-    volatile uint8_t   SGCSR;                                  /*  SGCSR           */
-    volatile uint8_t   SGCR2;                                  /*  SGCR2           */
-    volatile uint8_t   SGLR;                                   /*  SGLR            */
-    volatile uint8_t   SGTFR;                                  /*  SGTFR           */
-    volatile uint8_t   SGSFR;                                  /*  SGSFR           */
-};
-
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
 #define SDG0    (*(struct st_sdg     *)0xFCFF4800uL) /* SDG0 */
 #define SDG1    (*(struct st_sdg     *)0xFCFF4A00uL) /* SDG1 */
@@ -46,41 +39,69 @@
 #define SDG3    (*(struct st_sdg     *)0xFCFF4E00uL) /* SDG3 */
 
 
-/* Start of channnel array defines of SDG */
+/* Start of channel array defines of SDG */
 
-/* Channnel array defines of SDG */
+/* Channel array defines of SDG */
 /*(Sample) value = SDG[ channel ]->SGCR1; */
-#define SDG_COUNT  4
+#define SDG_COUNT  (4)
 #define SDG_ADDRESS_LIST \
 {   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
     &SDG0, &SDG1, &SDG2, &SDG3 \
 }   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
 
-/* End of channnel array defines of SDG */
+/* End of channel array defines of SDG */
 
 
-#define SGCR1_0 SDG0.SGCR1
-#define SGCSR_0 SDG0.SGCSR
-#define SGCR2_0 SDG0.SGCR2
-#define SGLR_0 SDG0.SGLR
-#define SGTFR_0 SDG0.SGTFR
-#define SGSFR_0 SDG0.SGSFR
-#define SGCR1_1 SDG1.SGCR1
-#define SGCSR_1 SDG1.SGCSR
-#define SGCR2_1 SDG1.SGCR2
-#define SGLR_1 SDG1.SGLR
-#define SGTFR_1 SDG1.SGTFR
-#define SGSFR_1 SDG1.SGSFR
-#define SGCR1_2 SDG2.SGCR1
-#define SGCSR_2 SDG2.SGCSR
-#define SGCR2_2 SDG2.SGCR2
-#define SGLR_2 SDG2.SGLR
-#define SGTFR_2 SDG2.SGTFR
-#define SGSFR_2 SDG2.SGSFR
-#define SGCR1_3 SDG3.SGCR1
-#define SGCSR_3 SDG3.SGCSR
-#define SGCR2_3 SDG3.SGCR2
-#define SGLR_3 SDG3.SGLR
-#define SGTFR_3 SDG3.SGTFR
-#define SGSFR_3 SDG3.SGSFR
+#define SGCR1_0 (SDG0.SGCR1)
+#define SGCSR_0 (SDG0.SGCSR)
+#define SGCR2_0 (SDG0.SGCR2)
+#define SGLR_0 (SDG0.SGLR)
+#define SGTFR_0 (SDG0.SGTFR)
+#define SGSFR_0 (SDG0.SGSFR)
+#define SGCR1_1 (SDG1.SGCR1)
+#define SGCSR_1 (SDG1.SGCSR)
+#define SGCR2_1 (SDG1.SGCR2)
+#define SGLR_1 (SDG1.SGLR)
+#define SGTFR_1 (SDG1.SGTFR)
+#define SGSFR_1 (SDG1.SGSFR)
+#define SGCR1_2 (SDG2.SGCR1)
+#define SGCSR_2 (SDG2.SGCSR)
+#define SGCR2_2 (SDG2.SGCR2)
+#define SGLR_2 (SDG2.SGLR)
+#define SGTFR_2 (SDG2.SGTFR)
+#define SGSFR_2 (SDG2.SGSFR)
+#define SGCR1_3 (SDG3.SGCR1)
+#define SGCSR_3 (SDG3.SGCSR)
+#define SGCR2_3 (SDG3.SGCR2)
+#define SGLR_3 (SDG3.SGLR)
+#define SGTFR_3 (SDG3.SGTFR)
+#define SGSFR_3 (SDG3.SGSFR)
+
+
+typedef struct st_sdg
+{
+                                                           /* SDG              */
+    volatile uint8_t   SGCR1;                                  /*  SGCR1           */
+    volatile uint8_t   SGCSR;                                  /*  SGCSR           */
+    volatile uint8_t   SGCR2;                                  /*  SGCR2           */
+    volatile uint8_t   SGLR;                                   /*  SGLR            */
+    volatile uint8_t   SGTFR;                                  /*  SGTFR           */
+    volatile uint8_t   SGSFR;                                  /*  SGSFR           */
+} r_io_sdg_t;
+
+
+/* Channel array defines of SDG (2)*/
+#ifdef  DECLARE_SDG_CHANNELS
+volatile struct st_sdg*  SDG[ SDG_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SDG_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SDG_CHANNELS */
+/* End of channel array defines of SDG (2)*/
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spdif_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,19 +18,43 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : spdif_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SPDIF_IODEFINE_H
 #define SPDIF_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
-struct st_spdif
-{                                                          /* SPDIF            */
+#define SPDIF   (*(struct st_spdif   *)0xE8012000uL) /* SPDIF */
+
+
+#define SPDIFTLCA (SPDIF.TLCA)
+#define SPDIFTRCA (SPDIF.TRCA)
+#define SPDIFTLCS (SPDIF.TLCS)
+#define SPDIFTRCS (SPDIF.TRCS)
+#define SPDIFTUI (SPDIF.TUI)
+#define SPDIFRLCA (SPDIF.RLCA)
+#define SPDIFRRCA (SPDIF.RRCA)
+#define SPDIFRLCS (SPDIF.RLCS)
+#define SPDIFRRCS (SPDIF.RRCS)
+#define SPDIFRUI (SPDIF.RUI)
+#define SPDIFCTRL (SPDIF.CTRL)
+#define SPDIFSTAT (SPDIF.STAT)
+#define SPDIFTDAD (SPDIF.TDAD)
+#define SPDIFRDAD (SPDIF.RDAD)
+
+
+typedef struct st_spdif
+{
+                                                           /* SPDIF            */
     volatile uint32_t  TLCA;                                   /*  TLCA            */
     volatile uint32_t  TRCA;                                   /*  TRCA            */
     volatile uint32_t  TLCS;                                   /*  TLCS            */
@@ -45,24 +69,11 @@
     volatile uint32_t  STAT;                                   /*  STAT            */
     volatile uint32_t  TDAD;                                   /*  TDAD            */
     volatile uint32_t  RDAD;                                   /*  RDAD            */
-};
-
-
-#define SPDIF   (*(struct st_spdif   *)0xE8012000uL) /* SPDIF */
+} r_io_spdif_t;
 
 
-#define SPDIFTLCA SPDIF.TLCA
-#define SPDIFTRCA SPDIF.TRCA
-#define SPDIFTLCS SPDIF.TLCS
-#define SPDIFTRCS SPDIF.TRCS
-#define SPDIFTUI SPDIF.TUI
-#define SPDIFRLCA SPDIF.RLCA
-#define SPDIFRRCA SPDIF.RRCA
-#define SPDIFRLCS SPDIF.RLCS
-#define SPDIFRRCS SPDIF.RRCS
-#define SPDIFRUI SPDIF.RUI
-#define SPDIFCTRL SPDIF.CTRL
-#define SPDIFSTAT SPDIF.STAT
-#define SPDIFTDAD SPDIF.TDAD
-#define SPDIFRDAD SPDIF.RDAD
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/spibsc_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,139 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : spibsc_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SPIBSC_IODEFINE_H
 #define SPIBSC_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_spibsc
-{                                                          /* SPIBSC           */
+#define SPIBSC0 (*(struct st_spibsc  *)0x3FEFA000uL) /* SPIBSC0 */
+#define SPIBSC1 (*(struct st_spibsc  *)0x3FEFB000uL) /* SPIBSC1 */
+
+
+/* Start of channel array defines of SPIBSC */
+
+/* Channel array defines of SPIBSC */
+/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
+#define SPIBSC_COUNT  (2)
+#define SPIBSC_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SPIBSC0, &SPIBSC1 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SPIBSC */
+
+
+#define CMNCR_0 (SPIBSC0.CMNCR)
+#define SSLDR_0 (SPIBSC0.SSLDR)
+#define SPBCR_0 (SPIBSC0.SPBCR)
+#define DRCR_0 (SPIBSC0.DRCR)
+#define DRCMR_0 (SPIBSC0.DRCMR)
+#define DREAR_0 (SPIBSC0.DREAR)
+#define DROPR_0 (SPIBSC0.DROPR)
+#define DRENR_0 (SPIBSC0.DRENR)
+#define SMCR_0 (SPIBSC0.SMCR)
+#define SMCMR_0 (SPIBSC0.SMCMR)
+#define SMADR_0 (SPIBSC0.SMADR)
+#define SMOPR_0 (SPIBSC0.SMOPR)
+#define SMENR_0 (SPIBSC0.SMENR)
+#define SMRDR0_0   (SPIBSC0.SMRDR0.UINT32)
+#define SMRDR0_0L  (SPIBSC0.SMRDR0.UINT16[R_IO_L])
+#define SMRDR0_0H  (SPIBSC0.SMRDR0.UINT16[R_IO_H])
+#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL])
+#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH])
+#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL])
+#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH])
+#define SMRDR1_0   (SPIBSC0.SMRDR1.UINT32)
+#define SMRDR1_0L  (SPIBSC0.SMRDR1.UINT16[R_IO_L])
+#define SMRDR1_0H  (SPIBSC0.SMRDR1.UINT16[R_IO_H])
+#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL])
+#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH])
+#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL])
+#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH])
+#define SMWDR0_0   (SPIBSC0.SMWDR0.UINT32)
+#define SMWDR0_0L  (SPIBSC0.SMWDR0.UINT16[R_IO_L])
+#define SMWDR0_0H  (SPIBSC0.SMWDR0.UINT16[R_IO_H])
+#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL])
+#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH])
+#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL])
+#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH])
+#define SMWDR1_0   (SPIBSC0.SMWDR1.UINT32)
+#define SMWDR1_0L  (SPIBSC0.SMWDR1.UINT16[R_IO_L])
+#define SMWDR1_0H  (SPIBSC0.SMWDR1.UINT16[R_IO_H])
+#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL])
+#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH])
+#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL])
+#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH])
+#define CMNSR_0 (SPIBSC0.CMNSR)
+#define CKDLY_0 (SPIBSC0.CKDLY)
+#define DRDMCR_0 (SPIBSC0.DRDMCR)
+#define DRDRENR_0 (SPIBSC0.DRDRENR)
+#define SMDMCR_0 (SPIBSC0.SMDMCR)
+#define SMDRENR_0 (SPIBSC0.SMDRENR)
+#define SPODLY_0 (SPIBSC0.SPODLY)
+#define CMNCR_1 (SPIBSC1.CMNCR)
+#define SSLDR_1 (SPIBSC1.SSLDR)
+#define SPBCR_1 (SPIBSC1.SPBCR)
+#define DRCR_1 (SPIBSC1.DRCR)
+#define DRCMR_1 (SPIBSC1.DRCMR)
+#define DREAR_1 (SPIBSC1.DREAR)
+#define DROPR_1 (SPIBSC1.DROPR)
+#define DRENR_1 (SPIBSC1.DRENR)
+#define SMCR_1 (SPIBSC1.SMCR)
+#define SMCMR_1 (SPIBSC1.SMCMR)
+#define SMADR_1 (SPIBSC1.SMADR)
+#define SMOPR_1 (SPIBSC1.SMOPR)
+#define SMENR_1 (SPIBSC1.SMENR)
+#define SMRDR0_1   (SPIBSC1.SMRDR0.UINT32)
+#define SMRDR0_1L  (SPIBSC1.SMRDR0.UINT16[R_IO_L])
+#define SMRDR0_1H  (SPIBSC1.SMRDR0.UINT16[R_IO_H])
+#define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL])
+#define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH])
+#define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL])
+#define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH])
+#define SMRDR1_1   (SPIBSC1.SMRDR1.UINT32)
+#define SMRDR1_1L  (SPIBSC1.SMRDR1.UINT16[R_IO_L])
+#define SMRDR1_1H  (SPIBSC1.SMRDR1.UINT16[R_IO_H])
+#define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL])
+#define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH])
+#define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL])
+#define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH])
+#define SMWDR0_1   (SPIBSC1.SMWDR0.UINT32)
+#define SMWDR0_1L  (SPIBSC1.SMWDR0.UINT16[R_IO_L])
+#define SMWDR0_1H  (SPIBSC1.SMWDR0.UINT16[R_IO_H])
+#define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL])
+#define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH])
+#define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL])
+#define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH])
+#define SMWDR1_1   (SPIBSC1.SMWDR1.UINT32)
+#define SMWDR1_1L  (SPIBSC1.SMWDR1.UINT16[R_IO_L])
+#define SMWDR1_1H  (SPIBSC1.SMWDR1.UINT16[R_IO_H])
+#define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL])
+#define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH])
+#define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL])
+#define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH])
+#define CMNSR_1 (SPIBSC1.CMNSR)
+#define CKDLY_1 (SPIBSC1.CKDLY)
+#define DRDMCR_1 (SPIBSC1.DRDMCR)
+#define DRDRENR_1 (SPIBSC1.DRDRENR)
+#define SMDMCR_1 (SPIBSC1.SMDMCR)
+#define SMDRENR_1 (SPIBSC1.SMDRENR)
+#define SPODLY_1 (SPIBSC1.SPODLY)
+
+
+typedef struct st_spibsc
+{
+                                                           /* SPIBSC           */
     volatile uint32_t  CMNCR;                                  /*  CMNCR           */
     volatile uint32_t  SSLDR;                                  /*  SSLDR           */
     volatile uint32_t  SPBCR;                                  /*  SPBCR           */
@@ -52,122 +171,29 @@
     union iodefine_reg32_t  SMWDR1;                        /*  SMWDR1          */
     
     volatile uint32_t  CMNSR;                                  /*  CMNSR           */
-    volatile uint8_t   dummy2[12];                             /*                  */
+    volatile uint8_t   dummy2[4];                              /*                  */
+    volatile uint32_t  CKDLY;                                  /*  CKDLY           */
+    volatile uint8_t   dummy3[4];                              /*                  */
     volatile uint32_t  DRDMCR;                                 /*  DRDMCR          */
     volatile uint32_t  DRDRENR;                                /*  DRDRENR         */
     volatile uint32_t  SMDMCR;                                 /*  SMDMCR          */
     volatile uint32_t  SMDRENR;                                /*  SMDRENR         */
-};
-
-
-#define SPIBSC0 (*(struct st_spibsc  *)0x3FEFA000uL) /* SPIBSC0 */
-#define SPIBSC1 (*(struct st_spibsc  *)0x3FEFB000uL) /* SPIBSC1 */
-
-
-/* Start of channnel array defines of SPIBSC */
-
-/* Channnel array defines of SPIBSC */
-/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
-#define SPIBSC_COUNT  2
-#define SPIBSC_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SPIBSC0, &SPIBSC1 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of SPIBSC */
+    volatile uint32_t  SPODLY;                                 /*  SPODLY          */
+} r_io_spibsc_t;
 
 
-#define CMNCR_0 SPIBSC0.CMNCR
-#define SSLDR_0 SPIBSC0.SSLDR
-#define SPBCR_0 SPIBSC0.SPBCR
-#define DRCR_0 SPIBSC0.DRCR
-#define DRCMR_0 SPIBSC0.DRCMR
-#define DREAR_0 SPIBSC0.DREAR
-#define DROPR_0 SPIBSC0.DROPR
-#define DRENR_0 SPIBSC0.DRENR
-#define SMCR_0 SPIBSC0.SMCR
-#define SMCMR_0 SPIBSC0.SMCMR
-#define SMADR_0 SPIBSC0.SMADR
-#define SMOPR_0 SPIBSC0.SMOPR
-#define SMENR_0 SPIBSC0.SMENR
-#define SMRDR0_0   SPIBSC0.SMRDR0.UINT32
-#define SMRDR0_0L  SPIBSC0.SMRDR0.UINT16[L]
-#define SMRDR0_0H  SPIBSC0.SMRDR0.UINT16[H]
-#define SMRDR0_0LL SPIBSC0.SMRDR0.UINT8[LL]
-#define SMRDR0_0LH SPIBSC0.SMRDR0.UINT8[LH]
-#define SMRDR0_0HL SPIBSC0.SMRDR0.UINT8[HL]
-#define SMRDR0_0HH SPIBSC0.SMRDR0.UINT8[HH]
-#define SMRDR1_0   SPIBSC0.SMRDR1.UINT32
-#define SMRDR1_0L  SPIBSC0.SMRDR1.UINT16[L]
-#define SMRDR1_0H  SPIBSC0.SMRDR1.UINT16[H]
-#define SMRDR1_0LL SPIBSC0.SMRDR1.UINT8[LL]
-#define SMRDR1_0LH SPIBSC0.SMRDR1.UINT8[LH]
-#define SMRDR1_0HL SPIBSC0.SMRDR1.UINT8[HL]
-#define SMRDR1_0HH SPIBSC0.SMRDR1.UINT8[HH]
-#define SMWDR0_0   SPIBSC0.SMWDR0.UINT32
-#define SMWDR0_0L  SPIBSC0.SMWDR0.UINT16[L]
-#define SMWDR0_0H  SPIBSC0.SMWDR0.UINT16[H]
-#define SMWDR0_0LL SPIBSC0.SMWDR0.UINT8[LL]
-#define SMWDR0_0LH SPIBSC0.SMWDR0.UINT8[LH]
-#define SMWDR0_0HL SPIBSC0.SMWDR0.UINT8[HL]
-#define SMWDR0_0HH SPIBSC0.SMWDR0.UINT8[HH]
-#define SMWDR1_0   SPIBSC0.SMWDR1.UINT32
-#define SMWDR1_0L  SPIBSC0.SMWDR1.UINT16[L]
-#define SMWDR1_0H  SPIBSC0.SMWDR1.UINT16[H]
-#define SMWDR1_0LL SPIBSC0.SMWDR1.UINT8[LL]
-#define SMWDR1_0LH SPIBSC0.SMWDR1.UINT8[LH]
-#define SMWDR1_0HL SPIBSC0.SMWDR1.UINT8[HL]
-#define SMWDR1_0HH SPIBSC0.SMWDR1.UINT8[HH]
-#define CMNSR_0 SPIBSC0.CMNSR
-#define DRDMCR_0 SPIBSC0.DRDMCR
-#define DRDRENR_0 SPIBSC0.DRDRENR
-#define SMDMCR_0 SPIBSC0.SMDMCR
-#define SMDRENR_0 SPIBSC0.SMDRENR
-#define CMNCR_1 SPIBSC1.CMNCR
-#define SSLDR_1 SPIBSC1.SSLDR
-#define SPBCR_1 SPIBSC1.SPBCR
-#define DRCR_1 SPIBSC1.DRCR
-#define DRCMR_1 SPIBSC1.DRCMR
-#define DREAR_1 SPIBSC1.DREAR
-#define DROPR_1 SPIBSC1.DROPR
-#define DRENR_1 SPIBSC1.DRENR
-#define SMCR_1 SPIBSC1.SMCR
-#define SMCMR_1 SPIBSC1.SMCMR
-#define SMADR_1 SPIBSC1.SMADR
-#define SMOPR_1 SPIBSC1.SMOPR
-#define SMENR_1 SPIBSC1.SMENR
-#define SMRDR0_1   SPIBSC1.SMRDR0.UINT32
-#define SMRDR0_1L  SPIBSC1.SMRDR0.UINT16[L]
-#define SMRDR0_1H  SPIBSC1.SMRDR0.UINT16[H]
-#define SMRDR0_1LL SPIBSC1.SMRDR0.UINT8[LL]
-#define SMRDR0_1LH SPIBSC1.SMRDR0.UINT8[LH]
-#define SMRDR0_1HL SPIBSC1.SMRDR0.UINT8[HL]
-#define SMRDR0_1HH SPIBSC1.SMRDR0.UINT8[HH]
-#define SMRDR1_1   SPIBSC1.SMRDR1.UINT32
-#define SMRDR1_1L  SPIBSC1.SMRDR1.UINT16[L]
-#define SMRDR1_1H  SPIBSC1.SMRDR1.UINT16[H]
-#define SMRDR1_1LL SPIBSC1.SMRDR1.UINT8[LL]
-#define SMRDR1_1LH SPIBSC1.SMRDR1.UINT8[LH]
-#define SMRDR1_1HL SPIBSC1.SMRDR1.UINT8[HL]
-#define SMRDR1_1HH SPIBSC1.SMRDR1.UINT8[HH]
-#define SMWDR0_1   SPIBSC1.SMWDR0.UINT32
-#define SMWDR0_1L  SPIBSC1.SMWDR0.UINT16[L]
-#define SMWDR0_1H  SPIBSC1.SMWDR0.UINT16[H]
-#define SMWDR0_1LL SPIBSC1.SMWDR0.UINT8[LL]
-#define SMWDR0_1LH SPIBSC1.SMWDR0.UINT8[LH]
-#define SMWDR0_1HL SPIBSC1.SMWDR0.UINT8[HL]
-#define SMWDR0_1HH SPIBSC1.SMWDR0.UINT8[HH]
-#define SMWDR1_1   SPIBSC1.SMWDR1.UINT32
-#define SMWDR1_1L  SPIBSC1.SMWDR1.UINT16[L]
-#define SMWDR1_1H  SPIBSC1.SMWDR1.UINT16[H]
-#define SMWDR1_1LL SPIBSC1.SMWDR1.UINT8[LL]
-#define SMWDR1_1LH SPIBSC1.SMWDR1.UINT8[LH]
-#define SMWDR1_1HL SPIBSC1.SMWDR1.UINT8[HL]
-#define SMWDR1_1HH SPIBSC1.SMWDR1.UINT8[HH]
-#define CMNSR_1 SPIBSC1.CMNSR
-#define DRDMCR_1 SPIBSC1.DRDMCR
-#define DRDRENR_1 SPIBSC1.DRDRENR
-#define SMDMCR_1 SPIBSC1.SMDMCR
-#define SMDRENR_1 SPIBSC1.SMDRENR
+/* Channel array defines of SPIBSC (2)*/
+#ifdef  DECLARE_SPIBSC_CHANNELS
+volatile struct st_spibsc*  SPIBSC[ SPIBSC_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SPIBSC_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SPIBSC_CHANNELS */
+/* End of channel array defines of SPIBSC (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ssif_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,107 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : ssif_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef SSIF_IODEFINE_H
 #define SSIF_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_ssif
-{                                                          /* SSIF             */
+#define SSIF0   (*(struct st_ssif    *)0xE820B000uL) /* SSIF0 */
+#define SSIF1   (*(struct st_ssif    *)0xE820B800uL) /* SSIF1 */
+#define SSIF2   (*(struct st_ssif    *)0xE820C000uL) /* SSIF2 */
+#define SSIF3   (*(struct st_ssif    *)0xE820C800uL) /* SSIF3 */
+#define SSIF4   (*(struct st_ssif    *)0xE820D000uL) /* SSIF4 */
+#define SSIF5   (*(struct st_ssif    *)0xE820D800uL) /* SSIF5 */
+
+
+/* Start of channel array defines of SSIF */
+
+/* Channel array defines of SSIF */
+/*(Sample) value = SSIF[ channel ]->SSICR; */
+#define SSIF_COUNT  (6)
+#define SSIF_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+/* End of channel array defines of SSIF */
+
+
+#define SSICR_0 (SSIF0.SSICR)
+#define SSISR_0 (SSIF0.SSISR)
+#define SSIFCR_0 (SSIF0.SSIFCR)
+#define SSIFSR_0 (SSIF0.SSIFSR)
+#define SSIFTDR_0 (SSIF0.SSIFTDR)
+#define SSIFRDR_0 (SSIF0.SSIFRDR)
+#define SSITDMR_0 (SSIF0.SSITDMR)
+#define SSIFCCR_0 (SSIF0.SSIFCCR)
+#define SSIFCMR_0 (SSIF0.SSIFCMR)
+#define SSIFCSR_0 (SSIF0.SSIFCSR)
+#define SSICR_1 (SSIF1.SSICR)
+#define SSISR_1 (SSIF1.SSISR)
+#define SSIFCR_1 (SSIF1.SSIFCR)
+#define SSIFSR_1 (SSIF1.SSIFSR)
+#define SSIFTDR_1 (SSIF1.SSIFTDR)
+#define SSIFRDR_1 (SSIF1.SSIFRDR)
+#define SSITDMR_1 (SSIF1.SSITDMR)
+#define SSIFCCR_1 (SSIF1.SSIFCCR)
+#define SSIFCMR_1 (SSIF1.SSIFCMR)
+#define SSIFCSR_1 (SSIF1.SSIFCSR)
+#define SSICR_2 (SSIF2.SSICR)
+#define SSISR_2 (SSIF2.SSISR)
+#define SSIFCR_2 (SSIF2.SSIFCR)
+#define SSIFSR_2 (SSIF2.SSIFSR)
+#define SSIFTDR_2 (SSIF2.SSIFTDR)
+#define SSIFRDR_2 (SSIF2.SSIFRDR)
+#define SSITDMR_2 (SSIF2.SSITDMR)
+#define SSIFCCR_2 (SSIF2.SSIFCCR)
+#define SSIFCMR_2 (SSIF2.SSIFCMR)
+#define SSIFCSR_2 (SSIF2.SSIFCSR)
+#define SSICR_3 (SSIF3.SSICR)
+#define SSISR_3 (SSIF3.SSISR)
+#define SSIFCR_3 (SSIF3.SSIFCR)
+#define SSIFSR_3 (SSIF3.SSIFSR)
+#define SSIFTDR_3 (SSIF3.SSIFTDR)
+#define SSIFRDR_3 (SSIF3.SSIFRDR)
+#define SSITDMR_3 (SSIF3.SSITDMR)
+#define SSIFCCR_3 (SSIF3.SSIFCCR)
+#define SSIFCMR_3 (SSIF3.SSIFCMR)
+#define SSIFCSR_3 (SSIF3.SSIFCSR)
+#define SSICR_4 (SSIF4.SSICR)
+#define SSISR_4 (SSIF4.SSISR)
+#define SSIFCR_4 (SSIF4.SSIFCR)
+#define SSIFSR_4 (SSIF4.SSIFSR)
+#define SSIFTDR_4 (SSIF4.SSIFTDR)
+#define SSIFRDR_4 (SSIF4.SSIFRDR)
+#define SSITDMR_4 (SSIF4.SSITDMR)
+#define SSIFCCR_4 (SSIF4.SSIFCCR)
+#define SSIFCMR_4 (SSIF4.SSIFCMR)
+#define SSIFCSR_4 (SSIF4.SSIFCSR)
+#define SSICR_5 (SSIF5.SSICR)
+#define SSISR_5 (SSIF5.SSISR)
+#define SSIFCR_5 (SSIF5.SSIFCR)
+#define SSIFSR_5 (SSIF5.SSIFSR)
+#define SSIFTDR_5 (SSIF5.SSIFTDR)
+#define SSIFRDR_5 (SSIF5.SSIFRDR)
+#define SSITDMR_5 (SSIF5.SSITDMR)
+#define SSIFCCR_5 (SSIF5.SSIFCCR)
+#define SSIFCMR_5 (SSIF5.SSIFCMR)
+#define SSIFCSR_5 (SSIF5.SSIFCSR)
+
+
+typedef struct st_ssif
+{
+                                                           /* SSIF             */
     volatile uint32_t  SSICR;                                  /*  SSICR           */
     volatile uint32_t  SSISR;                                  /*  SSISR           */
     volatile uint8_t   dummy1[8];                              /*                  */
@@ -43,89 +130,21 @@
     volatile uint32_t  SSIFCCR;                                /*  SSIFCCR         */
     volatile uint32_t  SSIFCMR;                                /*  SSIFCMR         */
     volatile uint32_t  SSIFCSR;                                /*  SSIFCSR         */
-};
-
-
-#define SSIF0   (*(struct st_ssif    *)0xE820B000uL) /* SSIF0 */
-#define SSIF1   (*(struct st_ssif    *)0xE820B800uL) /* SSIF1 */
-#define SSIF2   (*(struct st_ssif    *)0xE820C000uL) /* SSIF2 */
-#define SSIF3   (*(struct st_ssif    *)0xE820C800uL) /* SSIF3 */
-#define SSIF4   (*(struct st_ssif    *)0xE820D000uL) /* SSIF4 */
-#define SSIF5   (*(struct st_ssif    *)0xE820D800uL) /* SSIF5 */
-
-
-/* Start of channnel array defines of SSIF */
-
-/* Channnel array defines of SSIF */
-/*(Sample) value = SSIF[ channel ]->SSICR; */
-#define SSIF_COUNT  6
-#define SSIF_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-/* End of channnel array defines of SSIF */
+} r_io_ssif_t;
 
 
-#define SSICR_0 SSIF0.SSICR
-#define SSISR_0 SSIF0.SSISR
-#define SSIFCR_0 SSIF0.SSIFCR
-#define SSIFSR_0 SSIF0.SSIFSR
-#define SSIFTDR_0 SSIF0.SSIFTDR
-#define SSIFRDR_0 SSIF0.SSIFRDR
-#define SSITDMR_0 SSIF0.SSITDMR
-#define SSIFCCR_0 SSIF0.SSIFCCR
-#define SSIFCMR_0 SSIF0.SSIFCMR
-#define SSIFCSR_0 SSIF0.SSIFCSR
-#define SSICR_1 SSIF1.SSICR
-#define SSISR_1 SSIF1.SSISR
-#define SSIFCR_1 SSIF1.SSIFCR
-#define SSIFSR_1 SSIF1.SSIFSR
-#define SSIFTDR_1 SSIF1.SSIFTDR
-#define SSIFRDR_1 SSIF1.SSIFRDR
-#define SSITDMR_1 SSIF1.SSITDMR
-#define SSIFCCR_1 SSIF1.SSIFCCR
-#define SSIFCMR_1 SSIF1.SSIFCMR
-#define SSIFCSR_1 SSIF1.SSIFCSR
-#define SSICR_2 SSIF2.SSICR
-#define SSISR_2 SSIF2.SSISR
-#define SSIFCR_2 SSIF2.SSIFCR
-#define SSIFSR_2 SSIF2.SSIFSR
-#define SSIFTDR_2 SSIF2.SSIFTDR
-#define SSIFRDR_2 SSIF2.SSIFRDR
-#define SSITDMR_2 SSIF2.SSITDMR
-#define SSIFCCR_2 SSIF2.SSIFCCR
-#define SSIFCMR_2 SSIF2.SSIFCMR
-#define SSIFCSR_2 SSIF2.SSIFCSR
-#define SSICR_3 SSIF3.SSICR
-#define SSISR_3 SSIF3.SSISR
-#define SSIFCR_3 SSIF3.SSIFCR
-#define SSIFSR_3 SSIF3.SSIFSR
-#define SSIFTDR_3 SSIF3.SSIFTDR
-#define SSIFRDR_3 SSIF3.SSIFRDR
-#define SSITDMR_3 SSIF3.SSITDMR
-#define SSIFCCR_3 SSIF3.SSIFCCR
-#define SSIFCMR_3 SSIF3.SSIFCMR
-#define SSIFCSR_3 SSIF3.SSIFCSR
-#define SSICR_4 SSIF4.SSICR
-#define SSISR_4 SSIF4.SSISR
-#define SSIFCR_4 SSIF4.SSIFCR
-#define SSIFSR_4 SSIF4.SSIFSR
-#define SSIFTDR_4 SSIF4.SSIFTDR
-#define SSIFRDR_4 SSIF4.SSIFRDR
-#define SSITDMR_4 SSIF4.SSITDMR
-#define SSIFCCR_4 SSIF4.SSIFCCR
-#define SSIFCMR_4 SSIF4.SSIFCMR
-#define SSIFCSR_4 SSIF4.SSIFCSR
-#define SSICR_5 SSIF5.SSICR
-#define SSISR_5 SSIF5.SSISR
-#define SSIFCR_5 SSIF5.SSIFCR
-#define SSIFSR_5 SSIF5.SSIFSR
-#define SSIFTDR_5 SSIF5.SSIFTDR
-#define SSIFRDR_5 SSIF5.SSIFRDR
-#define SSITDMR_5 SSIF5.SSITDMR
-#define SSIFCCR_5 SSIF5.SSIFCCR
-#define SSIFCMR_5 SSIF5.SSIFCMR
-#define SSIFCSR_5 SSIF5.SSIFCSR
+/* Channel array defines of SSIF (2)*/
+#ifdef  DECLARE_SSIF_CHANNELS
+volatile struct st_ssif*  SSIF[ SSIF_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    SSIF_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_SSIF_CHANNELS */
+/* End of channel array defines of SSIF (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/usb20_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,20 +18,365 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : usb20_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef USB20_IODEFINE_H
 #define USB20_IODEFINE_H
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_usb20
-{                                                          /* USB20            */
+#define USB200  (*(struct st_usb20   *)0xE8010000uL) /* USB200 */
+#define USB201  (*(struct st_usb20   *)0xE8207000uL) /* USB201 */
+
+
+/* Start of channel array defines of USB20 */
+
+/* Channel array defines of USB20 */
+/*(Sample) value = USB20[ channel ]->SYSCFG0; */
+#define USB20_COUNT  (2)
+#define USB20_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &USB200, &USB201 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channel array defines of USB20_FROM_D0FIFOB0 */
+/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
+#define USB20_FROM_D0FIFOB0_COUNT  (2)
+#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
+    &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
+#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
+#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
+#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
+
+
+
+
+/* Channel array defines of USB20_FROM_PIPE1ATRE */
+/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
+#define USB20_FROM_PIPE1ATRE_COUNT  (5)
+#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
+    &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
+#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
+#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
+#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
+#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
+#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
+#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
+#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
+#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
+#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
+
+
+
+
+/* Channel array defines of USB20_FROM_D0FIFOSEL */
+/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
+#define USB20_FROM_D0FIFOSEL_COUNT  (2)
+#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
+    &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
+#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
+#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
+#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
+
+
+/* End of channel array defines of USB20 */
+
+
+#define SYSCFG0_0 (USB200.SYSCFG0)
+#define BUSWAIT_0 (USB200.BUSWAIT)
+#define SYSSTS0_0 (USB200.SYSSTS0)
+#define DVSTCTR0_0 (USB200.DVSTCTR0)
+#define TESTMODE_0 (USB200.TESTMODE)
+#define D0FBCFG_0 (USB200.D0FBCFG)
+#define D1FBCFG_0 (USB200.D1FBCFG)
+#define CFIFO_0   (USB200.CFIFO.UINT32)
+#define CFIFO_0L  (USB200.CFIFO.UINT16[R_IO_L])
+#define CFIFO_0H  (USB200.CFIFO.UINT16[R_IO_H])
+#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL])
+#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH])
+#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL])
+#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH])
+#define D0FIFO_0   (USB200.D0FIFO.UINT32)
+#define D0FIFO_0L  (USB200.D0FIFO.UINT16[R_IO_L])
+#define D0FIFO_0H  (USB200.D0FIFO.UINT16[R_IO_H])
+#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL])
+#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH])
+#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL])
+#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH])
+#define D1FIFO_0   (USB200.D1FIFO.UINT32)
+#define D1FIFO_0L  (USB200.D1FIFO.UINT16[R_IO_L])
+#define D1FIFO_0H  (USB200.D1FIFO.UINT16[R_IO_H])
+#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL])
+#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH])
+#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL])
+#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH])
+#define CFIFOSEL_0 (USB200.CFIFOSEL)
+#define CFIFOCTR_0 (USB200.CFIFOCTR)
+#define D0FIFOSEL_0 (USB200.D0FIFOSEL)
+#define D0FIFOCTR_0 (USB200.D0FIFOCTR)
+#define D1FIFOSEL_0 (USB200.D1FIFOSEL)
+#define D1FIFOCTR_0 (USB200.D1FIFOCTR)
+#define INTENB0_0 (USB200.INTENB0)
+#define INTENB1_0 (USB200.INTENB1)
+#define BRDYENB_0 (USB200.BRDYENB)
+#define NRDYENB_0 (USB200.NRDYENB)
+#define BEMPENB_0 (USB200.BEMPENB)
+#define SOFCFG_0 (USB200.SOFCFG)
+#define INTSTS0_0 (USB200.INTSTS0)
+#define INTSTS1_0 (USB200.INTSTS1)
+#define BRDYSTS_0 (USB200.BRDYSTS)
+#define NRDYSTS_0 (USB200.NRDYSTS)
+#define BEMPSTS_0 (USB200.BEMPSTS)
+#define FRMNUM_0 (USB200.FRMNUM)
+#define UFRMNUM_0 (USB200.UFRMNUM)
+#define USBADDR_0 (USB200.USBADDR)
+#define USBREQ_0 (USB200.USBREQ)
+#define USBVAL_0 (USB200.USBVAL)
+#define USBINDX_0 (USB200.USBINDX)
+#define USBLENG_0 (USB200.USBLENG)
+#define DCPCFG_0 (USB200.DCPCFG)
+#define DCPMAXP_0 (USB200.DCPMAXP)
+#define DCPCTR_0 (USB200.DCPCTR)
+#define PIPESEL_0 (USB200.PIPESEL)
+#define PIPECFG_0 (USB200.PIPECFG)
+#define PIPEBUF_0 (USB200.PIPEBUF)
+#define PIPEMAXP_0 (USB200.PIPEMAXP)
+#define PIPEPERI_0 (USB200.PIPEPERI)
+#define PIPE1CTR_0 (USB200.PIPE1CTR)
+#define PIPE2CTR_0 (USB200.PIPE2CTR)
+#define PIPE3CTR_0 (USB200.PIPE3CTR)
+#define PIPE4CTR_0 (USB200.PIPE4CTR)
+#define PIPE5CTR_0 (USB200.PIPE5CTR)
+#define PIPE6CTR_0 (USB200.PIPE6CTR)
+#define PIPE7CTR_0 (USB200.PIPE7CTR)
+#define PIPE8CTR_0 (USB200.PIPE8CTR)
+#define PIPE9CTR_0 (USB200.PIPE9CTR)
+#define PIPEACTR_0 (USB200.PIPEACTR)
+#define PIPEBCTR_0 (USB200.PIPEBCTR)
+#define PIPECCTR_0 (USB200.PIPECCTR)
+#define PIPEDCTR_0 (USB200.PIPEDCTR)
+#define PIPEECTR_0 (USB200.PIPEECTR)
+#define PIPEFCTR_0 (USB200.PIPEFCTR)
+#define PIPE1TRE_0 (USB200.PIPE1TRE)
+#define PIPE1TRN_0 (USB200.PIPE1TRN)
+#define PIPE2TRE_0 (USB200.PIPE2TRE)
+#define PIPE2TRN_0 (USB200.PIPE2TRN)
+#define PIPE3TRE_0 (USB200.PIPE3TRE)
+#define PIPE3TRN_0 (USB200.PIPE3TRN)
+#define PIPE4TRE_0 (USB200.PIPE4TRE)
+#define PIPE4TRN_0 (USB200.PIPE4TRN)
+#define PIPE5TRE_0 (USB200.PIPE5TRE)
+#define PIPE5TRN_0 (USB200.PIPE5TRN)
+#define PIPEBTRE_0 (USB200.PIPEBTRE)
+#define PIPEBTRN_0 (USB200.PIPEBTRN)
+#define PIPECTRE_0 (USB200.PIPECTRE)
+#define PIPECTRN_0 (USB200.PIPECTRN)
+#define PIPEDTRE_0 (USB200.PIPEDTRE)
+#define PIPEDTRN_0 (USB200.PIPEDTRN)
+#define PIPEETRE_0 (USB200.PIPEETRE)
+#define PIPEETRN_0 (USB200.PIPEETRN)
+#define PIPEFTRE_0 (USB200.PIPEFTRE)
+#define PIPEFTRN_0 (USB200.PIPEFTRN)
+#define PIPE9TRE_0 (USB200.PIPE9TRE)
+#define PIPE9TRN_0 (USB200.PIPE9TRN)
+#define PIPEATRE_0 (USB200.PIPEATRE)
+#define PIPEATRN_0 (USB200.PIPEATRN)
+#define DEVADD0_0 (USB200.DEVADD0)
+#define DEVADD1_0 (USB200.DEVADD1)
+#define DEVADD2_0 (USB200.DEVADD2)
+#define DEVADD3_0 (USB200.DEVADD3)
+#define DEVADD4_0 (USB200.DEVADD4)
+#define DEVADD5_0 (USB200.DEVADD5)
+#define DEVADD6_0 (USB200.DEVADD6)
+#define DEVADD7_0 (USB200.DEVADD7)
+#define DEVADD8_0 (USB200.DEVADD8)
+#define DEVADD9_0 (USB200.DEVADD9)
+#define DEVADDA_0 (USB200.DEVADDA)
+#define SUSPMODE_0 (USB200.SUSPMODE)
+#define D0FIFOB0_0 (USB200.D0FIFOB0)
+#define D0FIFOB1_0 (USB200.D0FIFOB1)
+#define D0FIFOB2_0 (USB200.D0FIFOB2)
+#define D0FIFOB3_0 (USB200.D0FIFOB3)
+#define D0FIFOB4_0 (USB200.D0FIFOB4)
+#define D0FIFOB5_0 (USB200.D0FIFOB5)
+#define D0FIFOB6_0 (USB200.D0FIFOB6)
+#define D0FIFOB7_0 (USB200.D0FIFOB7)
+#define D1FIFOB0_0 (USB200.D1FIFOB0)
+#define D1FIFOB1_0 (USB200.D1FIFOB1)
+#define D1FIFOB2_0 (USB200.D1FIFOB2)
+#define D1FIFOB3_0 (USB200.D1FIFOB3)
+#define D1FIFOB4_0 (USB200.D1FIFOB4)
+#define D1FIFOB5_0 (USB200.D1FIFOB5)
+#define D1FIFOB6_0 (USB200.D1FIFOB6)
+#define D1FIFOB7_0 (USB200.D1FIFOB7)
+#define SYSCFG0_1 (USB201.SYSCFG0)
+#define BUSWAIT_1 (USB201.BUSWAIT)
+#define SYSSTS0_1 (USB201.SYSSTS0)
+#define DVSTCTR0_1 (USB201.DVSTCTR0)
+#define TESTMODE_1 (USB201.TESTMODE)
+#define D0FBCFG_1 (USB201.D0FBCFG)
+#define D1FBCFG_1 (USB201.D1FBCFG)
+#define CFIFO_1   (USB201.CFIFO.UINT32)
+#define CFIFO_1L  (USB201.CFIFO.UINT16[R_IO_L])
+#define CFIFO_1H  (USB201.CFIFO.UINT16[R_IO_H])
+#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL])
+#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH])
+#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL])
+#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH])
+#define D0FIFO_1   (USB201.D0FIFO.UINT32)
+#define D0FIFO_1L  (USB201.D0FIFO.UINT16[R_IO_L])
+#define D0FIFO_1H  (USB201.D0FIFO.UINT16[R_IO_H])
+#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL])
+#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH])
+#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL])
+#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH])
+#define D1FIFO_1   (USB201.D1FIFO.UINT32)
+#define D1FIFO_1L  (USB201.D1FIFO.UINT16[R_IO_L])
+#define D1FIFO_1H  (USB201.D1FIFO.UINT16[R_IO_H])
+#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL])
+#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH])
+#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL])
+#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH])
+#define CFIFOSEL_1 (USB201.CFIFOSEL)
+#define CFIFOCTR_1 (USB201.CFIFOCTR)
+#define D0FIFOSEL_1 (USB201.D0FIFOSEL)
+#define D0FIFOCTR_1 (USB201.D0FIFOCTR)
+#define D1FIFOSEL_1 (USB201.D1FIFOSEL)
+#define D1FIFOCTR_1 (USB201.D1FIFOCTR)
+#define INTENB0_1 (USB201.INTENB0)
+#define INTENB1_1 (USB201.INTENB1)
+#define BRDYENB_1 (USB201.BRDYENB)
+#define NRDYENB_1 (USB201.NRDYENB)
+#define BEMPENB_1 (USB201.BEMPENB)
+#define SOFCFG_1 (USB201.SOFCFG)
+#define INTSTS0_1 (USB201.INTSTS0)
+#define INTSTS1_1 (USB201.INTSTS1)
+#define BRDYSTS_1 (USB201.BRDYSTS)
+#define NRDYSTS_1 (USB201.NRDYSTS)
+#define BEMPSTS_1 (USB201.BEMPSTS)
+#define FRMNUM_1 (USB201.FRMNUM)
+#define UFRMNUM_1 (USB201.UFRMNUM)
+#define USBADDR_1 (USB201.USBADDR)
+#define USBREQ_1 (USB201.USBREQ)
+#define USBVAL_1 (USB201.USBVAL)
+#define USBINDX_1 (USB201.USBINDX)
+#define USBLENG_1 (USB201.USBLENG)
+#define DCPCFG_1 (USB201.DCPCFG)
+#define DCPMAXP_1 (USB201.DCPMAXP)
+#define DCPCTR_1 (USB201.DCPCTR)
+#define PIPESEL_1 (USB201.PIPESEL)
+#define PIPECFG_1 (USB201.PIPECFG)
+#define PIPEBUF_1 (USB201.PIPEBUF)
+#define PIPEMAXP_1 (USB201.PIPEMAXP)
+#define PIPEPERI_1 (USB201.PIPEPERI)
+#define PIPE1CTR_1 (USB201.PIPE1CTR)
+#define PIPE2CTR_1 (USB201.PIPE2CTR)
+#define PIPE3CTR_1 (USB201.PIPE3CTR)
+#define PIPE4CTR_1 (USB201.PIPE4CTR)
+#define PIPE5CTR_1 (USB201.PIPE5CTR)
+#define PIPE6CTR_1 (USB201.PIPE6CTR)
+#define PIPE7CTR_1 (USB201.PIPE7CTR)
+#define PIPE8CTR_1 (USB201.PIPE8CTR)
+#define PIPE9CTR_1 (USB201.PIPE9CTR)
+#define PIPEACTR_1 (USB201.PIPEACTR)
+#define PIPEBCTR_1 (USB201.PIPEBCTR)
+#define PIPECCTR_1 (USB201.PIPECCTR)
+#define PIPEDCTR_1 (USB201.PIPEDCTR)
+#define PIPEECTR_1 (USB201.PIPEECTR)
+#define PIPEFCTR_1 (USB201.PIPEFCTR)
+#define PIPE1TRE_1 (USB201.PIPE1TRE)
+#define PIPE1TRN_1 (USB201.PIPE1TRN)
+#define PIPE2TRE_1 (USB201.PIPE2TRE)
+#define PIPE2TRN_1 (USB201.PIPE2TRN)
+#define PIPE3TRE_1 (USB201.PIPE3TRE)
+#define PIPE3TRN_1 (USB201.PIPE3TRN)
+#define PIPE4TRE_1 (USB201.PIPE4TRE)
+#define PIPE4TRN_1 (USB201.PIPE4TRN)
+#define PIPE5TRE_1 (USB201.PIPE5TRE)
+#define PIPE5TRN_1 (USB201.PIPE5TRN)
+#define PIPEBTRE_1 (USB201.PIPEBTRE)
+#define PIPEBTRN_1 (USB201.PIPEBTRN)
+#define PIPECTRE_1 (USB201.PIPECTRE)
+#define PIPECTRN_1 (USB201.PIPECTRN)
+#define PIPEDTRE_1 (USB201.PIPEDTRE)
+#define PIPEDTRN_1 (USB201.PIPEDTRN)
+#define PIPEETRE_1 (USB201.PIPEETRE)
+#define PIPEETRN_1 (USB201.PIPEETRN)
+#define PIPEFTRE_1 (USB201.PIPEFTRE)
+#define PIPEFTRN_1 (USB201.PIPEFTRN)
+#define PIPE9TRE_1 (USB201.PIPE9TRE)
+#define PIPE9TRN_1 (USB201.PIPE9TRN)
+#define PIPEATRE_1 (USB201.PIPEATRE)
+#define PIPEATRN_1 (USB201.PIPEATRN)
+#define DEVADD0_1 (USB201.DEVADD0)
+#define DEVADD1_1 (USB201.DEVADD1)
+#define DEVADD2_1 (USB201.DEVADD2)
+#define DEVADD3_1 (USB201.DEVADD3)
+#define DEVADD4_1 (USB201.DEVADD4)
+#define DEVADD5_1 (USB201.DEVADD5)
+#define DEVADD6_1 (USB201.DEVADD6)
+#define DEVADD7_1 (USB201.DEVADD7)
+#define DEVADD8_1 (USB201.DEVADD8)
+#define DEVADD9_1 (USB201.DEVADD9)
+#define DEVADDA_1 (USB201.DEVADDA)
+#define SUSPMODE_1 (USB201.SUSPMODE)
+#define D0FIFOB0_1 (USB201.D0FIFOB0)
+#define D0FIFOB1_1 (USB201.D0FIFOB1)
+#define D0FIFOB2_1 (USB201.D0FIFOB2)
+#define D0FIFOB3_1 (USB201.D0FIFOB3)
+#define D0FIFOB4_1 (USB201.D0FIFOB4)
+#define D0FIFOB5_1 (USB201.D0FIFOB5)
+#define D0FIFOB6_1 (USB201.D0FIFOB6)
+#define D0FIFOB7_1 (USB201.D0FIFOB7)
+#define D1FIFOB0_1 (USB201.D1FIFOB0)
+#define D1FIFOB1_1 (USB201.D1FIFOB1)
+#define D1FIFOB2_1 (USB201.D1FIFOB2)
+#define D1FIFOB3_1 (USB201.D1FIFOB3)
+#define D1FIFOB4_1 (USB201.D1FIFOB4)
+#define D1FIFOB5_1 (USB201.D1FIFOB5)
+#define D1FIFOB6_1 (USB201.D1FIFOB6)
+#define D1FIFOB7_1 (USB201.D1FIFOB7)
+
+#define USB20_D0FBCFG_COUNT (2)
+#define USB20_D0FIFO_COUNT (2)
+#define USB20_INTENB0_COUNT (2)
+#define USB20_INTSTS0_COUNT (2)
+#define USB20_PIPE1CTR_COUNT (0xF)
+#define USB20_DEVADD0_COUNT (0xB)
+#define USB20_D0FIFOB0_COUNT (0x8)
+
+
+typedef struct st_usb20
+{
+                                                           /* USB20            */
     volatile uint16_t SYSCFG0;                                /*  SYSCFG0         */
     volatile uint16_t BUSWAIT;                                /*  BUSWAIT         */
     volatile uint16_t SYSSTS0;                                /*  SYSSTS0         */
@@ -40,26 +385,33 @@
     volatile uint8_t   dummy2[2];                              /*                  */
     volatile uint16_t TESTMODE;                               /*  TESTMODE        */
     volatile uint8_t   dummy3[2];                              /*                  */
-#define USB20_D0FBCFG_COUNT 2
+
+/* #define USB20_D0FBCFG_COUNT (2) */
     volatile uint16_t D0FBCFG;                                /*  D0FBCFG         */
     volatile uint16_t D1FBCFG;                                /*  D1FBCFG         */
     union iodefine_reg32_t  CFIFO;                         /*  CFIFO           */
-#define USB20_D0FIFO_COUNT 2
+
+/* #define USB20_D0FIFO_COUNT (2) */
     union iodefine_reg32_t  D0FIFO;                        /*  D0FIFO          */
     union iodefine_reg32_t  D1FIFO;                        /*  D1FIFO          */
     
     volatile uint16_t CFIFOSEL;                               /*  CFIFOSEL        */
     volatile uint16_t CFIFOCTR;                               /*  CFIFOCTR        */
     volatile uint8_t   dummy4[4];                              /*                  */
+
 /* start of struct st_usb20_from_d0fifosel */
     volatile uint16_t D0FIFOSEL;                              /*  D0FIFOSEL       */
     volatile uint16_t D0FIFOCTR;                              /*  D0FIFOCTR       */
+
 /* end of struct st_usb20_from_d0fifosel */
+
 /* start of struct st_usb20_from_d0fifosel */
     volatile uint16_t D1FIFOSEL;                              /*  D1FIFOSEL       */
     volatile uint16_t D1FIFOCTR;                              /*  D1FIFOCTR       */
+
 /* end of struct st_usb20_from_d0fifosel */
-#define USB20_INTENB0_COUNT 2
+
+/* #define USB20_INTENB0_COUNT (2) */
     volatile uint16_t INTENB0;                                /*  INTENB0         */
     volatile uint16_t INTENB1;                                /*  INTENB1         */
     volatile uint8_t   dummy5[2];                              /*                  */
@@ -68,7 +420,8 @@
     volatile uint16_t BEMPENB;                                /*  BEMPENB         */
     volatile uint16_t SOFCFG;                                 /*  SOFCFG          */
     volatile uint8_t   dummy6[2];                              /*                  */
-#define USB20_INTSTS0_COUNT 2
+
+/* #define USB20_INTSTS0_COUNT (2) */
     volatile uint16_t INTSTS0;                                /*  INTSTS0         */
     volatile uint16_t INTSTS1;                                /*  INTSTS1         */
     volatile uint8_t   dummy7[2];                              /*                  */
@@ -93,7 +446,8 @@
     volatile uint16_t PIPEBUF;                                /*  PIPEBUF         */
     volatile uint16_t PIPEMAXP;                               /*  PIPEMAXP        */
     volatile uint16_t PIPEPERI;                               /*  PIPEPERI        */
-#define USB20_PIPE1CTR_COUNT 0xF
+
+/* #define USB20_PIPE1CTR_COUNT (0xF) */
     volatile uint16_t PIPE1CTR;                               /*  PIPE1CTR        */
     volatile uint16_t PIPE2CTR;                               /*  PIPE2CTR        */
     volatile uint16_t PIPE3CTR;                               /*  PIPE3CTR        */
@@ -110,25 +464,35 @@
     volatile uint16_t PIPEECTR;                               /*  PIPEECTR        */
     volatile uint16_t PIPEFCTR;                               /*  PIPEFCTR        */
     volatile uint8_t   dummy11[2];                             /*                  */
+
 /* start of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPE1TRE;                               /*  PIPE1TRE        */
     volatile uint16_t PIPE1TRN;                               /*  PIPE1TRN        */
+
 /* end of struct st_usb20_from_pipe1tre */
+
 /* start of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPE2TRE;                               /*  PIPE2TRE        */
     volatile uint16_t PIPE2TRN;                               /*  PIPE2TRN        */
+
 /* end of struct st_usb20_from_pipe1tre */
+
 /* start of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPE3TRE;                               /*  PIPE3TRE        */
     volatile uint16_t PIPE3TRN;                               /*  PIPE3TRN        */
+
 /* end of struct st_usb20_from_pipe1tre */
+
 /* start of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPE4TRE;                               /*  PIPE4TRE        */
     volatile uint16_t PIPE4TRN;                               /*  PIPE4TRN        */
+
 /* end of struct st_usb20_from_pipe1tre */
+
 /* start of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPE5TRE;                               /*  PIPE5TRE        */
     volatile uint16_t PIPE5TRN;                               /*  PIPE5TRN        */
+
 /* end of struct st_usb20_from_pipe1tre */
     volatile uint16_t PIPEBTRE;                               /*  PIPEBTRE        */
     volatile uint16_t PIPEBTRN;                               /*  PIPEBTRN        */
@@ -145,7 +509,8 @@
     volatile uint16_t PIPEATRE;                               /*  PIPEATRE        */
     volatile uint16_t PIPEATRN;                               /*  PIPEATRN        */
     volatile uint8_t   dummy12[16];                            /*                  */
-#define USB20_DEVADD0_COUNT 0xB
+
+/* #define USB20_DEVADD0_COUNT (0xB) */
     volatile uint16_t DEVADD0;                                /*  DEVADD0         */
     volatile uint16_t DEVADD1;                                /*  DEVADD1         */
     volatile uint16_t DEVADD2;                                /*  DEVADD2         */
@@ -160,6 +525,7 @@
     volatile uint8_t   dummy13[28];                            /*                  */
     volatile uint16_t SUSPMODE;                               /*  SUSPMODE        */
     volatile uint8_t   dummy14[92];                            /*                  */
+
 /* start of struct st_usb20_from_dmfifob0 */
     volatile uint32_t  D0FIFOB0;                               /*  D0FIFOB0        */
     volatile uint32_t  D0FIFOB1;                               /*  D0FIFOB1        */
@@ -169,7 +535,9 @@
     volatile uint32_t  D0FIFOB5;                               /*  D0FIFOB5        */
     volatile uint32_t  D0FIFOB6;                               /*  D0FIFOB6        */
     volatile uint32_t  D0FIFOB7;                               /*  D0FIFOB7        */
+
 /* end of struct st_usb20_from_dmfifob0 */
+
 /* start of struct st_usb20_from_dmfifob0 */
     volatile uint32_t  D1FIFOB0;                               /*  D1FIFOB0        */
     volatile uint32_t  D1FIFOB1;                               /*  D1FIFOB1        */
@@ -179,27 +547,32 @@
     volatile uint32_t  D1FIFOB5;                               /*  D1FIFOB5        */
     volatile uint32_t  D1FIFOB6;                               /*  D1FIFOB6        */
     volatile uint32_t  D1FIFOB7;                               /*  D1FIFOB7        */
+
 /* end of struct st_usb20_from_dmfifob0 */
-};
+} r_io_usb20_t;
 
 
-struct st_usb20_from_d0fifosel
+typedef struct st_usb20_from_d0fifosel
 {
+ 
     volatile uint16_t D0FIFOSEL;                              /*  D0FIFOSEL       */
     volatile uint16_t D0FIFOCTR;                              /*  D0FIFOCTR       */
-};
+} r_io_usb20_from_d0fifosel_t;
 
 
-struct st_usb20_from_pipe1tre
+typedef struct st_usb20_from_pipe1tre
 {
+ 
     volatile uint16_t PIPE1TRE;                               /*  PIPE1TRE        */
     volatile uint16_t PIPE1TRN;                               /*  PIPE1TRN        */
-};
+} r_io_usb20_from_pipe1tre_t;
 
 
-struct st_usb20_from_dmfifob0
+typedef struct st_usb20_from_dmfifob0
 {
-#define USB20_D0FIFOB0_COUNT 0x8
+ 
+
+/* #define USB20_D0FIFOB0_COUNT (0x8) */
     volatile uint32_t  D0FIFOB0;                               /*  D0FIFOB0        */
     volatile uint32_t  D0FIFOB1;                               /*  D0FIFOB1        */
     volatile uint32_t  D0FIFOB2;                               /*  D0FIFOB2        */
@@ -208,339 +581,42 @@
     volatile uint32_t  D0FIFOB5;                               /*  D0FIFOB5        */
     volatile uint32_t  D0FIFOB6;                               /*  D0FIFOB6        */
     volatile uint32_t  D0FIFOB7;                               /*  D0FIFOB7        */
-};
-
-
-#define USB200  (*(struct st_usb20   *)0xE8010000uL) /* USB200 */
-#define USB201  (*(struct st_usb20   *)0xE8207000uL) /* USB201 */
-
-
-/* Start of channnel array defines of USB20 */
-
-/* Channnel array defines of USB20 */
-/*(Sample) value = USB20[ channel ]->SYSCFG0; */
-#define USB20_COUNT  2
-#define USB20_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &USB200, &USB201 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-
-
-/* Channnel array defines of USB20_FROM_D0FIFOB0 */
-/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
-#define USB20_FROM_D0FIFOB0_COUNT  2
-#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
-    &USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
-#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
-#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
-#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
-
-
-
-
-/* Channnel array defines of USB20_FROM_PIPE1ATRE */
-/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
-#define USB20_FROM_PIPE1ATRE_COUNT  5
-#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
-    &USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
-#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
-#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
-#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
-#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
-#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
-#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
-#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
-#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
-#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
-
-
-
-
-/* Channnel array defines of USB20_FROM_D0FIFOSEL */
-/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
-#define USB20_FROM_D0FIFOSEL_COUNT  2
-#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
-    &USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
-#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
-#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
-#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
-
-
-/* End of channnel array defines of USB20 */
+} r_io_usb20_from_dmfifob0_t;
 
 
-#define SYSCFG0_0 USB200.SYSCFG0
-#define BUSWAIT_0 USB200.BUSWAIT
-#define SYSSTS0_0 USB200.SYSSTS0
-#define DVSTCTR0_0 USB200.DVSTCTR0
-#define TESTMODE_0 USB200.TESTMODE
-#define D0FBCFG_0 USB200.D0FBCFG
-#define D1FBCFG_0 USB200.D1FBCFG
-#define CFIFO_0   USB200.CFIFO.UINT32
-#define CFIFO_0L  USB200.CFIFO.UINT16[L]
-#define CFIFO_0H  USB200.CFIFO.UINT16[H]
-#define CFIFO_0LL USB200.CFIFO.UINT8[LL]
-#define CFIFO_0LH USB200.CFIFO.UINT8[LH]
-#define CFIFO_0HL USB200.CFIFO.UINT8[HL]
-#define CFIFO_0HH USB200.CFIFO.UINT8[HH]
-#define D0FIFO_0   USB200.D0FIFO.UINT32
-#define D0FIFO_0L  USB200.D0FIFO.UINT16[L]
-#define D0FIFO_0H  USB200.D0FIFO.UINT16[H]
-#define D0FIFO_0LL USB200.D0FIFO.UINT8[LL]
-#define D0FIFO_0LH USB200.D0FIFO.UINT8[LH]
-#define D0FIFO_0HL USB200.D0FIFO.UINT8[HL]
-#define D0FIFO_0HH USB200.D0FIFO.UINT8[HH]
-#define D1FIFO_0   USB200.D1FIFO.UINT32
-#define D1FIFO_0L  USB200.D1FIFO.UINT16[L]
-#define D1FIFO_0H  USB200.D1FIFO.UINT16[H]
-#define D1FIFO_0LL USB200.D1FIFO.UINT8[LL]
-#define D1FIFO_0LH USB200.D1FIFO.UINT8[LH]
-#define D1FIFO_0HL USB200.D1FIFO.UINT8[HL]
-#define D1FIFO_0HH USB200.D1FIFO.UINT8[HH]
-#define CFIFOSEL_0 USB200.CFIFOSEL
-#define CFIFOCTR_0 USB200.CFIFOCTR
-#define D0FIFOSEL_0 USB200.D0FIFOSEL
-#define D0FIFOCTR_0 USB200.D0FIFOCTR
-#define D1FIFOSEL_0 USB200.D1FIFOSEL
-#define D1FIFOCTR_0 USB200.D1FIFOCTR
-#define INTENB0_0 USB200.INTENB0
-#define INTENB1_0 USB200.INTENB1
-#define BRDYENB_0 USB200.BRDYENB
-#define NRDYENB_0 USB200.NRDYENB
-#define BEMPENB_0 USB200.BEMPENB
-#define SOFCFG_0 USB200.SOFCFG
-#define INTSTS0_0 USB200.INTSTS0
-#define INTSTS1_0 USB200.INTSTS1
-#define BRDYSTS_0 USB200.BRDYSTS
-#define NRDYSTS_0 USB200.NRDYSTS
-#define BEMPSTS_0 USB200.BEMPSTS
-#define FRMNUM_0 USB200.FRMNUM
-#define UFRMNUM_0 USB200.UFRMNUM
-#define USBADDR_0 USB200.USBADDR
-#define USBREQ_0 USB200.USBREQ
-#define USBVAL_0 USB200.USBVAL
-#define USBINDX_0 USB200.USBINDX
-#define USBLENG_0 USB200.USBLENG
-#define DCPCFG_0 USB200.DCPCFG
-#define DCPMAXP_0 USB200.DCPMAXP
-#define DCPCTR_0 USB200.DCPCTR
-#define PIPESEL_0 USB200.PIPESEL
-#define PIPECFG_0 USB200.PIPECFG
-#define PIPEBUF_0 USB200.PIPEBUF
-#define PIPEMAXP_0 USB200.PIPEMAXP
-#define PIPEPERI_0 USB200.PIPEPERI
-#define PIPE1CTR_0 USB200.PIPE1CTR
-#define PIPE2CTR_0 USB200.PIPE2CTR
-#define PIPE3CTR_0 USB200.PIPE3CTR
-#define PIPE4CTR_0 USB200.PIPE4CTR
-#define PIPE5CTR_0 USB200.PIPE5CTR
-#define PIPE6CTR_0 USB200.PIPE6CTR
-#define PIPE7CTR_0 USB200.PIPE7CTR
-#define PIPE8CTR_0 USB200.PIPE8CTR
-#define PIPE9CTR_0 USB200.PIPE9CTR
-#define PIPEACTR_0 USB200.PIPEACTR
-#define PIPEBCTR_0 USB200.PIPEBCTR
-#define PIPECCTR_0 USB200.PIPECCTR
-#define PIPEDCTR_0 USB200.PIPEDCTR
-#define PIPEECTR_0 USB200.PIPEECTR
-#define PIPEFCTR_0 USB200.PIPEFCTR
-#define PIPE1TRE_0 USB200.PIPE1TRE
-#define PIPE1TRN_0 USB200.PIPE1TRN
-#define PIPE2TRE_0 USB200.PIPE2TRE
-#define PIPE2TRN_0 USB200.PIPE2TRN
-#define PIPE3TRE_0 USB200.PIPE3TRE
-#define PIPE3TRN_0 USB200.PIPE3TRN
-#define PIPE4TRE_0 USB200.PIPE4TRE
-#define PIPE4TRN_0 USB200.PIPE4TRN
-#define PIPE5TRE_0 USB200.PIPE5TRE
-#define PIPE5TRN_0 USB200.PIPE5TRN
-#define PIPEBTRE_0 USB200.PIPEBTRE
-#define PIPEBTRN_0 USB200.PIPEBTRN
-#define PIPECTRE_0 USB200.PIPECTRE
-#define PIPECTRN_0 USB200.PIPECTRN
-#define PIPEDTRE_0 USB200.PIPEDTRE
-#define PIPEDTRN_0 USB200.PIPEDTRN
-#define PIPEETRE_0 USB200.PIPEETRE
-#define PIPEETRN_0 USB200.PIPEETRN
-#define PIPEFTRE_0 USB200.PIPEFTRE
-#define PIPEFTRN_0 USB200.PIPEFTRN
-#define PIPE9TRE_0 USB200.PIPE9TRE
-#define PIPE9TRN_0 USB200.PIPE9TRN
-#define PIPEATRE_0 USB200.PIPEATRE
-#define PIPEATRN_0 USB200.PIPEATRN
-#define DEVADD0_0 USB200.DEVADD0
-#define DEVADD1_0 USB200.DEVADD1
-#define DEVADD2_0 USB200.DEVADD2
-#define DEVADD3_0 USB200.DEVADD3
-#define DEVADD4_0 USB200.DEVADD4
-#define DEVADD5_0 USB200.DEVADD5
-#define DEVADD6_0 USB200.DEVADD6
-#define DEVADD7_0 USB200.DEVADD7
-#define DEVADD8_0 USB200.DEVADD8
-#define DEVADD9_0 USB200.DEVADD9
-#define DEVADDA_0 USB200.DEVADDA
-#define SUSPMODE_0 USB200.SUSPMODE
-#define D0FIFOB0_0 USB200.D0FIFOB0
-#define D0FIFOB1_0 USB200.D0FIFOB1
-#define D0FIFOB2_0 USB200.D0FIFOB2
-#define D0FIFOB3_0 USB200.D0FIFOB3
-#define D0FIFOB4_0 USB200.D0FIFOB4
-#define D0FIFOB5_0 USB200.D0FIFOB5
-#define D0FIFOB6_0 USB200.D0FIFOB6
-#define D0FIFOB7_0 USB200.D0FIFOB7
-#define D1FIFOB0_0 USB200.D1FIFOB0
-#define D1FIFOB1_0 USB200.D1FIFOB1
-#define D1FIFOB2_0 USB200.D1FIFOB2
-#define D1FIFOB3_0 USB200.D1FIFOB3
-#define D1FIFOB4_0 USB200.D1FIFOB4
-#define D1FIFOB5_0 USB200.D1FIFOB5
-#define D1FIFOB6_0 USB200.D1FIFOB6
-#define D1FIFOB7_0 USB200.D1FIFOB7
-#define SYSCFG0_1 USB201.SYSCFG0
-#define BUSWAIT_1 USB201.BUSWAIT
-#define SYSSTS0_1 USB201.SYSSTS0
-#define DVSTCTR0_1 USB201.DVSTCTR0
-#define TESTMODE_1 USB201.TESTMODE
-#define D0FBCFG_1 USB201.D0FBCFG
-#define D1FBCFG_1 USB201.D1FBCFG
-#define CFIFO_1   USB201.CFIFO.UINT32
-#define CFIFO_1L  USB201.CFIFO.UINT16[L]
-#define CFIFO_1H  USB201.CFIFO.UINT16[H]
-#define CFIFO_1LL USB201.CFIFO.UINT8[LL]
-#define CFIFO_1LH USB201.CFIFO.UINT8[LH]
-#define CFIFO_1HL USB201.CFIFO.UINT8[HL]
-#define CFIFO_1HH USB201.CFIFO.UINT8[HH]
-#define D0FIFO_1   USB201.D0FIFO.UINT32
-#define D0FIFO_1L  USB201.D0FIFO.UINT16[L]
-#define D0FIFO_1H  USB201.D0FIFO.UINT16[H]
-#define D0FIFO_1LL USB201.D0FIFO.UINT8[LL]
-#define D0FIFO_1LH USB201.D0FIFO.UINT8[LH]
-#define D0FIFO_1HL USB201.D0FIFO.UINT8[HL]
-#define D0FIFO_1HH USB201.D0FIFO.UINT8[HH]
-#define D1FIFO_1   USB201.D1FIFO.UINT32
-#define D1FIFO_1L  USB201.D1FIFO.UINT16[L]
-#define D1FIFO_1H  USB201.D1FIFO.UINT16[H]
-#define D1FIFO_1LL USB201.D1FIFO.UINT8[LL]
-#define D1FIFO_1LH USB201.D1FIFO.UINT8[LH]
-#define D1FIFO_1HL USB201.D1FIFO.UINT8[HL]
-#define D1FIFO_1HH USB201.D1FIFO.UINT8[HH]
-#define CFIFOSEL_1 USB201.CFIFOSEL
-#define CFIFOCTR_1 USB201.CFIFOCTR
-#define D0FIFOSEL_1 USB201.D0FIFOSEL
-#define D0FIFOCTR_1 USB201.D0FIFOCTR
-#define D1FIFOSEL_1 USB201.D1FIFOSEL
-#define D1FIFOCTR_1 USB201.D1FIFOCTR
-#define INTENB0_1 USB201.INTENB0
-#define INTENB1_1 USB201.INTENB1
-#define BRDYENB_1 USB201.BRDYENB
-#define NRDYENB_1 USB201.NRDYENB
-#define BEMPENB_1 USB201.BEMPENB
-#define SOFCFG_1 USB201.SOFCFG
-#define INTSTS0_1 USB201.INTSTS0
-#define INTSTS1_1 USB201.INTSTS1
-#define BRDYSTS_1 USB201.BRDYSTS
-#define NRDYSTS_1 USB201.NRDYSTS
-#define BEMPSTS_1 USB201.BEMPSTS
-#define FRMNUM_1 USB201.FRMNUM
-#define UFRMNUM_1 USB201.UFRMNUM
-#define USBADDR_1 USB201.USBADDR
-#define USBREQ_1 USB201.USBREQ
-#define USBVAL_1 USB201.USBVAL
-#define USBINDX_1 USB201.USBINDX
-#define USBLENG_1 USB201.USBLENG
-#define DCPCFG_1 USB201.DCPCFG
-#define DCPMAXP_1 USB201.DCPMAXP
-#define DCPCTR_1 USB201.DCPCTR
-#define PIPESEL_1 USB201.PIPESEL
-#define PIPECFG_1 USB201.PIPECFG
-#define PIPEBUF_1 USB201.PIPEBUF
-#define PIPEMAXP_1 USB201.PIPEMAXP
-#define PIPEPERI_1 USB201.PIPEPERI
-#define PIPE1CTR_1 USB201.PIPE1CTR
-#define PIPE2CTR_1 USB201.PIPE2CTR
-#define PIPE3CTR_1 USB201.PIPE3CTR
-#define PIPE4CTR_1 USB201.PIPE4CTR
-#define PIPE5CTR_1 USB201.PIPE5CTR
-#define PIPE6CTR_1 USB201.PIPE6CTR
-#define PIPE7CTR_1 USB201.PIPE7CTR
-#define PIPE8CTR_1 USB201.PIPE8CTR
-#define PIPE9CTR_1 USB201.PIPE9CTR
-#define PIPEACTR_1 USB201.PIPEACTR
-#define PIPEBCTR_1 USB201.PIPEBCTR
-#define PIPECCTR_1 USB201.PIPECCTR
-#define PIPEDCTR_1 USB201.PIPEDCTR
-#define PIPEECTR_1 USB201.PIPEECTR
-#define PIPEFCTR_1 USB201.PIPEFCTR
-#define PIPE1TRE_1 USB201.PIPE1TRE
-#define PIPE1TRN_1 USB201.PIPE1TRN
-#define PIPE2TRE_1 USB201.PIPE2TRE
-#define PIPE2TRN_1 USB201.PIPE2TRN
-#define PIPE3TRE_1 USB201.PIPE3TRE
-#define PIPE3TRN_1 USB201.PIPE3TRN
-#define PIPE4TRE_1 USB201.PIPE4TRE
-#define PIPE4TRN_1 USB201.PIPE4TRN
-#define PIPE5TRE_1 USB201.PIPE5TRE
-#define PIPE5TRN_1 USB201.PIPE5TRN
-#define PIPEBTRE_1 USB201.PIPEBTRE
-#define PIPEBTRN_1 USB201.PIPEBTRN
-#define PIPECTRE_1 USB201.PIPECTRE
-#define PIPECTRN_1 USB201.PIPECTRN
-#define PIPEDTRE_1 USB201.PIPEDTRE
-#define PIPEDTRN_1 USB201.PIPEDTRN
-#define PIPEETRE_1 USB201.PIPEETRE
-#define PIPEETRN_1 USB201.PIPEETRN
-#define PIPEFTRE_1 USB201.PIPEFTRE
-#define PIPEFTRN_1 USB201.PIPEFTRN
-#define PIPE9TRE_1 USB201.PIPE9TRE
-#define PIPE9TRN_1 USB201.PIPE9TRN
-#define PIPEATRE_1 USB201.PIPEATRE
-#define PIPEATRN_1 USB201.PIPEATRN
-#define DEVADD0_1 USB201.DEVADD0
-#define DEVADD1_1 USB201.DEVADD1
-#define DEVADD2_1 USB201.DEVADD2
-#define DEVADD3_1 USB201.DEVADD3
-#define DEVADD4_1 USB201.DEVADD4
-#define DEVADD5_1 USB201.DEVADD5
-#define DEVADD6_1 USB201.DEVADD6
-#define DEVADD7_1 USB201.DEVADD7
-#define DEVADD8_1 USB201.DEVADD8
-#define DEVADD9_1 USB201.DEVADD9
-#define DEVADDA_1 USB201.DEVADDA
-#define SUSPMODE_1 USB201.SUSPMODE
-#define D0FIFOB0_1 USB201.D0FIFOB0
-#define D0FIFOB1_1 USB201.D0FIFOB1
-#define D0FIFOB2_1 USB201.D0FIFOB2
-#define D0FIFOB3_1 USB201.D0FIFOB3
-#define D0FIFOB4_1 USB201.D0FIFOB4
-#define D0FIFOB5_1 USB201.D0FIFOB5
-#define D0FIFOB6_1 USB201.D0FIFOB6
-#define D0FIFOB7_1 USB201.D0FIFOB7
-#define D1FIFOB0_1 USB201.D1FIFOB0
-#define D1FIFOB1_1 USB201.D1FIFOB1
-#define D1FIFOB2_1 USB201.D1FIFOB2
-#define D1FIFOB3_1 USB201.D1FIFOB3
-#define D1FIFOB4_1 USB201.D1FIFOB4
-#define D1FIFOB5_1 USB201.D1FIFOB5
-#define D1FIFOB6_1 USB201.D1FIFOB6
-#define D1FIFOB7_1 USB201.D1FIFOB7
+/* Channel array defines of USB20 (2)*/
+#ifdef  DECLARE_USB20_CHANNELS
+volatile struct st_usb20*  USB20[ USB20_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_CHANNELS */
+
+#ifdef  DECLARE_USB20_FROM_D0FIFOB0_CHANNELS
+volatile struct st_usb20_from_dmfifob0*  USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_FROM_D0FIFOB0_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */
+
+#ifdef  DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS
+volatile struct st_usb20_from_pipe1tre*  USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_FROM_PIPE1ATRE_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */
+
+#ifdef  DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS
+volatile struct st_usb20_from_d0fifosel*  USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    USB20_FROM_D0FIFOSEL_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */
+/* End of channel array defines of USB20 (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,21 +18,1004 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : vdc5_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef VDC5_IODEFINE_H
 #define VDC5_IODEFINE_H
 /* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
 /* ->SEC M1.10.1 : Not magic number */
 
-struct st_vdc5
-{                                                          /* VDC5             */
+#define VDC50   (*(struct st_vdc5    *)0xFCFF7400uL) /* VDC50 */
+#define VDC51   (*(struct st_vdc5    *)0xFCFF9400uL) /* VDC51 */
+
+
+/* Start of channel array defines of VDC5 */
+
+/* Channel array defines of VDC5 */
+/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
+#define VDC5_COUNT  (2)
+#define VDC5_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+    &VDC50, &VDC51 \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+
+
+
+/* Channel array defines of VDC50_FROM_GR2_AB7_ARRAY */
+/*(Sample) value = VDC50_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC50_FROM_GR2_AB7_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
+    &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
+#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
+#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
+#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
+
+
+
+
+/* Channel array defines of VDC50_FROM_GR2_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC50_FROM_GR2_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
+    &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
+#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
+#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
+#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
+
+
+
+
+/* Channel array defines of VDC50_FROM_SC0_SCL1_PBUF0_ARRAY */
+/*(Sample) value = VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
+#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT  (2)
+#define VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
+    &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
+#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
+#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
+#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
+
+
+
+
+/* Channel array defines of VDC50_FROM_SC0_SCL0_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
+#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
+    &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
+#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
+#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
+#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
+
+
+
+
+/* Channel array defines of VDC50_FROM_ADJ0_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
+#define VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
+    &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
+#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
+#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
+#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
+
+
+
+
+/* Channel array defines of VDC50_FROM_GR0_AB7_ARRAY */
+/*(Sample) value = VDC50_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
+#define VDC50_FROM_GR0_AB7_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
+    &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
+#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
+#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
+#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
+
+
+
+
+/* Channel array defines of VDC50_FROM_GR0_UPDATE_ARRAY */
+/*(Sample) value = VDC50_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
+#define VDC50_FROM_GR0_UPDATE_ARRAY_COUNT  (2)
+#define VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
+{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
+{ \
+    &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
+    &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
+} \
+}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
+#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
+#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
+#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
+#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
+
+
+/* End of channel array defines of VDC5 */
+
+
+#define VDC50INP_UPDATE (VDC50.INP_UPDATE)
+#define VDC50INP_SEL_CNT (VDC50.INP_SEL_CNT)
+#define VDC50INP_EXT_SYNC_CNT (VDC50.INP_EXT_SYNC_CNT)
+#define VDC50INP_VSYNC_PH_ADJ (VDC50.INP_VSYNC_PH_ADJ)
+#define VDC50INP_DLY_ADJ (VDC50.INP_DLY_ADJ)
+#define VDC50IMGCNT_UPDATE (VDC50.IMGCNT_UPDATE)
+#define VDC50IMGCNT_NR_CNT0 (VDC50.IMGCNT_NR_CNT0)
+#define VDC50IMGCNT_NR_CNT1 (VDC50.IMGCNT_NR_CNT1)
+#define VDC50IMGCNT_MTX_MODE (VDC50.IMGCNT_MTX_MODE)
+#define VDC50IMGCNT_MTX_YG_ADJ0 (VDC50.IMGCNT_MTX_YG_ADJ0)
+#define VDC50IMGCNT_MTX_YG_ADJ1 (VDC50.IMGCNT_MTX_YG_ADJ1)
+#define VDC50IMGCNT_MTX_CBB_ADJ0 (VDC50.IMGCNT_MTX_CBB_ADJ0)
+#define VDC50IMGCNT_MTX_CBB_ADJ1 (VDC50.IMGCNT_MTX_CBB_ADJ1)
+#define VDC50IMGCNT_MTX_CRR_ADJ0 (VDC50.IMGCNT_MTX_CRR_ADJ0)
+#define VDC50IMGCNT_MTX_CRR_ADJ1 (VDC50.IMGCNT_MTX_CRR_ADJ1)
+#define VDC50IMGCNT_DRC_REG (VDC50.IMGCNT_DRC_REG)
+#define VDC50SC0_SCL0_UPDATE (VDC50.SC0_SCL0_UPDATE)
+#define VDC50SC0_SCL0_FRC1 (VDC50.SC0_SCL0_FRC1)
+#define VDC50SC0_SCL0_FRC2 (VDC50.SC0_SCL0_FRC2)
+#define VDC50SC0_SCL0_FRC3 (VDC50.SC0_SCL0_FRC3)
+#define VDC50SC0_SCL0_FRC4 (VDC50.SC0_SCL0_FRC4)
+#define VDC50SC0_SCL0_FRC5 (VDC50.SC0_SCL0_FRC5)
+#define VDC50SC0_SCL0_FRC6 (VDC50.SC0_SCL0_FRC6)
+#define VDC50SC0_SCL0_FRC7 (VDC50.SC0_SCL0_FRC7)
+#define VDC50SC0_SCL0_FRC9 (VDC50.SC0_SCL0_FRC9)
+#define VDC50SC0_SCL0_MON0 (VDC50.SC0_SCL0_MON0)
+#define VDC50SC0_SCL0_INT (VDC50.SC0_SCL0_INT)
+#define VDC50SC0_SCL0_DS1 (VDC50.SC0_SCL0_DS1)
+#define VDC50SC0_SCL0_DS2 (VDC50.SC0_SCL0_DS2)
+#define VDC50SC0_SCL0_DS3 (VDC50.SC0_SCL0_DS3)
+#define VDC50SC0_SCL0_DS4 (VDC50.SC0_SCL0_DS4)
+#define VDC50SC0_SCL0_DS5 (VDC50.SC0_SCL0_DS5)
+#define VDC50SC0_SCL0_DS6 (VDC50.SC0_SCL0_DS6)
+#define VDC50SC0_SCL0_DS7 (VDC50.SC0_SCL0_DS7)
+#define VDC50SC0_SCL0_US1 (VDC50.SC0_SCL0_US1)
+#define VDC50SC0_SCL0_US2 (VDC50.SC0_SCL0_US2)
+#define VDC50SC0_SCL0_US3 (VDC50.SC0_SCL0_US3)
+#define VDC50SC0_SCL0_US4 (VDC50.SC0_SCL0_US4)
+#define VDC50SC0_SCL0_US5 (VDC50.SC0_SCL0_US5)
+#define VDC50SC0_SCL0_US6 (VDC50.SC0_SCL0_US6)
+#define VDC50SC0_SCL0_US7 (VDC50.SC0_SCL0_US7)
+#define VDC50SC0_SCL0_US8 (VDC50.SC0_SCL0_US8)
+#define VDC50SC0_SCL0_OVR1 (VDC50.SC0_SCL0_OVR1)
+#define VDC50SC0_SCL1_UPDATE (VDC50.SC0_SCL1_UPDATE)
+#define VDC50SC0_SCL1_WR1 (VDC50.SC0_SCL1_WR1)
+#define VDC50SC0_SCL1_WR2 (VDC50.SC0_SCL1_WR2)
+#define VDC50SC0_SCL1_WR3 (VDC50.SC0_SCL1_WR3)
+#define VDC50SC0_SCL1_WR4 (VDC50.SC0_SCL1_WR4)
+#define VDC50SC0_SCL1_WR5 (VDC50.SC0_SCL1_WR5)
+#define VDC50SC0_SCL1_WR6 (VDC50.SC0_SCL1_WR6)
+#define VDC50SC0_SCL1_WR7 (VDC50.SC0_SCL1_WR7)
+#define VDC50SC0_SCL1_WR8 (VDC50.SC0_SCL1_WR8)
+#define VDC50SC0_SCL1_WR9 (VDC50.SC0_SCL1_WR9)
+#define VDC50SC0_SCL1_WR10 (VDC50.SC0_SCL1_WR10)
+#define VDC50SC0_SCL1_WR11 (VDC50.SC0_SCL1_WR11)
+#define VDC50SC0_SCL1_MON1 (VDC50.SC0_SCL1_MON1)
+#define VDC50SC0_SCL1_PBUF0 (VDC50.SC0_SCL1_PBUF0)
+#define VDC50SC0_SCL1_PBUF1 (VDC50.SC0_SCL1_PBUF1)
+#define VDC50SC0_SCL1_PBUF2 (VDC50.SC0_SCL1_PBUF2)
+#define VDC50SC0_SCL1_PBUF3 (VDC50.SC0_SCL1_PBUF3)
+#define VDC50SC0_SCL1_PBUF_FLD (VDC50.SC0_SCL1_PBUF_FLD)
+#define VDC50SC0_SCL1_PBUF_CNT (VDC50.SC0_SCL1_PBUF_CNT)
+#define VDC50GR0_UPDATE (VDC50.GR0_UPDATE)
+#define VDC50GR0_FLM_RD (VDC50.GR0_FLM_RD)
+#define VDC50GR0_FLM1 (VDC50.GR0_FLM1)
+#define VDC50GR0_FLM2 (VDC50.GR0_FLM2)
+#define VDC50GR0_FLM3 (VDC50.GR0_FLM3)
+#define VDC50GR0_FLM4 (VDC50.GR0_FLM4)
+#define VDC50GR0_FLM5 (VDC50.GR0_FLM5)
+#define VDC50GR0_FLM6 (VDC50.GR0_FLM6)
+#define VDC50GR0_AB1 (VDC50.GR0_AB1)
+#define VDC50GR0_AB2 (VDC50.GR0_AB2)
+#define VDC50GR0_AB3 (VDC50.GR0_AB3)
+#define VDC50GR0_AB7 (VDC50.GR0_AB7)
+#define VDC50GR0_AB8 (VDC50.GR0_AB8)
+#define VDC50GR0_AB9 (VDC50.GR0_AB9)
+#define VDC50GR0_AB10 (VDC50.GR0_AB10)
+#define VDC50GR0_AB11 (VDC50.GR0_AB11)
+#define VDC50GR0_BASE (VDC50.GR0_BASE)
+#define VDC50GR0_CLUT (VDC50.GR0_CLUT)
+#define VDC50ADJ0_UPDATE (VDC50.ADJ0_UPDATE)
+#define VDC50ADJ0_BKSTR_SET (VDC50.ADJ0_BKSTR_SET)
+#define VDC50ADJ0_ENH_TIM1 (VDC50.ADJ0_ENH_TIM1)
+#define VDC50ADJ0_ENH_TIM2 (VDC50.ADJ0_ENH_TIM2)
+#define VDC50ADJ0_ENH_TIM3 (VDC50.ADJ0_ENH_TIM3)
+#define VDC50ADJ0_ENH_SHP1 (VDC50.ADJ0_ENH_SHP1)
+#define VDC50ADJ0_ENH_SHP2 (VDC50.ADJ0_ENH_SHP2)
+#define VDC50ADJ0_ENH_SHP3 (VDC50.ADJ0_ENH_SHP3)
+#define VDC50ADJ0_ENH_SHP4 (VDC50.ADJ0_ENH_SHP4)
+#define VDC50ADJ0_ENH_SHP5 (VDC50.ADJ0_ENH_SHP5)
+#define VDC50ADJ0_ENH_SHP6 (VDC50.ADJ0_ENH_SHP6)
+#define VDC50ADJ0_ENH_LTI1 (VDC50.ADJ0_ENH_LTI1)
+#define VDC50ADJ0_ENH_LTI2 (VDC50.ADJ0_ENH_LTI2)
+#define VDC50ADJ0_MTX_MODE (VDC50.ADJ0_MTX_MODE)
+#define VDC50ADJ0_MTX_YG_ADJ0 (VDC50.ADJ0_MTX_YG_ADJ0)
+#define VDC50ADJ0_MTX_YG_ADJ1 (VDC50.ADJ0_MTX_YG_ADJ1)
+#define VDC50ADJ0_MTX_CBB_ADJ0 (VDC50.ADJ0_MTX_CBB_ADJ0)
+#define VDC50ADJ0_MTX_CBB_ADJ1 (VDC50.ADJ0_MTX_CBB_ADJ1)
+#define VDC50ADJ0_MTX_CRR_ADJ0 (VDC50.ADJ0_MTX_CRR_ADJ0)
+#define VDC50ADJ0_MTX_CRR_ADJ1 (VDC50.ADJ0_MTX_CRR_ADJ1)
+#define VDC50GR2_UPDATE (VDC50.GR2_UPDATE)
+#define VDC50GR2_FLM_RD (VDC50.GR2_FLM_RD)
+#define VDC50GR2_FLM1 (VDC50.GR2_FLM1)
+#define VDC50GR2_FLM2 (VDC50.GR2_FLM2)
+#define VDC50GR2_FLM3 (VDC50.GR2_FLM3)
+#define VDC50GR2_FLM4 (VDC50.GR2_FLM4)
+#define VDC50GR2_FLM5 (VDC50.GR2_FLM5)
+#define VDC50GR2_FLM6 (VDC50.GR2_FLM6)
+#define VDC50GR2_AB1 (VDC50.GR2_AB1)
+#define VDC50GR2_AB2 (VDC50.GR2_AB2)
+#define VDC50GR2_AB3 (VDC50.GR2_AB3)
+#define VDC50GR2_AB4 (VDC50.GR2_AB4)
+#define VDC50GR2_AB5 (VDC50.GR2_AB5)
+#define VDC50GR2_AB6 (VDC50.GR2_AB6)
+#define VDC50GR2_AB7 (VDC50.GR2_AB7)
+#define VDC50GR2_AB8 (VDC50.GR2_AB8)
+#define VDC50GR2_AB9 (VDC50.GR2_AB9)
+#define VDC50GR2_AB10 (VDC50.GR2_AB10)
+#define VDC50GR2_AB11 (VDC50.GR2_AB11)
+#define VDC50GR2_BASE (VDC50.GR2_BASE)
+#define VDC50GR2_CLUT (VDC50.GR2_CLUT)
+#define VDC50GR2_MON (VDC50.GR2_MON)
+#define VDC50GR3_UPDATE (VDC50.GR3_UPDATE)
+#define VDC50GR3_FLM_RD (VDC50.GR3_FLM_RD)
+#define VDC50GR3_FLM1 (VDC50.GR3_FLM1)
+#define VDC50GR3_FLM2 (VDC50.GR3_FLM2)
+#define VDC50GR3_FLM3 (VDC50.GR3_FLM3)
+#define VDC50GR3_FLM4 (VDC50.GR3_FLM4)
+#define VDC50GR3_FLM5 (VDC50.GR3_FLM5)
+#define VDC50GR3_FLM6 (VDC50.GR3_FLM6)
+#define VDC50GR3_AB1 (VDC50.GR3_AB1)
+#define VDC50GR3_AB2 (VDC50.GR3_AB2)
+#define VDC50GR3_AB3 (VDC50.GR3_AB3)
+#define VDC50GR3_AB4 (VDC50.GR3_AB4)
+#define VDC50GR3_AB5 (VDC50.GR3_AB5)
+#define VDC50GR3_AB6 (VDC50.GR3_AB6)
+#define VDC50GR3_AB7 (VDC50.GR3_AB7)
+#define VDC50GR3_AB8 (VDC50.GR3_AB8)
+#define VDC50GR3_AB9 (VDC50.GR3_AB9)
+#define VDC50GR3_AB10 (VDC50.GR3_AB10)
+#define VDC50GR3_AB11 (VDC50.GR3_AB11)
+#define VDC50GR3_BASE (VDC50.GR3_BASE)
+#define VDC50GR3_CLUT_INT (VDC50.GR3_CLUT_INT)
+#define VDC50GR3_MON (VDC50.GR3_MON)
+#define VDC50GAM_G_UPDATE (VDC50.GAM_G_UPDATE)
+#define VDC50GAM_SW (VDC50.GAM_SW)
+#define VDC50GAM_G_LUT1 (VDC50.GAM_G_LUT1)
+#define VDC50GAM_G_LUT2 (VDC50.GAM_G_LUT2)
+#define VDC50GAM_G_LUT3 (VDC50.GAM_G_LUT3)
+#define VDC50GAM_G_LUT4 (VDC50.GAM_G_LUT4)
+#define VDC50GAM_G_LUT5 (VDC50.GAM_G_LUT5)
+#define VDC50GAM_G_LUT6 (VDC50.GAM_G_LUT6)
+#define VDC50GAM_G_LUT7 (VDC50.GAM_G_LUT7)
+#define VDC50GAM_G_LUT8 (VDC50.GAM_G_LUT8)
+#define VDC50GAM_G_LUT9 (VDC50.GAM_G_LUT9)
+#define VDC50GAM_G_LUT10 (VDC50.GAM_G_LUT10)
+#define VDC50GAM_G_LUT11 (VDC50.GAM_G_LUT11)
+#define VDC50GAM_G_LUT12 (VDC50.GAM_G_LUT12)
+#define VDC50GAM_G_LUT13 (VDC50.GAM_G_LUT13)
+#define VDC50GAM_G_LUT14 (VDC50.GAM_G_LUT14)
+#define VDC50GAM_G_LUT15 (VDC50.GAM_G_LUT15)
+#define VDC50GAM_G_LUT16 (VDC50.GAM_G_LUT16)
+#define VDC50GAM_G_AREA1 (VDC50.GAM_G_AREA1)
+#define VDC50GAM_G_AREA2 (VDC50.GAM_G_AREA2)
+#define VDC50GAM_G_AREA3 (VDC50.GAM_G_AREA3)
+#define VDC50GAM_G_AREA4 (VDC50.GAM_G_AREA4)
+#define VDC50GAM_G_AREA5 (VDC50.GAM_G_AREA5)
+#define VDC50GAM_G_AREA6 (VDC50.GAM_G_AREA6)
+#define VDC50GAM_G_AREA7 (VDC50.GAM_G_AREA7)
+#define VDC50GAM_G_AREA8 (VDC50.GAM_G_AREA8)
+#define VDC50GAM_B_UPDATE (VDC50.GAM_B_UPDATE)
+#define VDC50GAM_B_LUT1 (VDC50.GAM_B_LUT1)
+#define VDC50GAM_B_LUT2 (VDC50.GAM_B_LUT2)
+#define VDC50GAM_B_LUT3 (VDC50.GAM_B_LUT3)
+#define VDC50GAM_B_LUT4 (VDC50.GAM_B_LUT4)
+#define VDC50GAM_B_LUT5 (VDC50.GAM_B_LUT5)
+#define VDC50GAM_B_LUT6 (VDC50.GAM_B_LUT6)
+#define VDC50GAM_B_LUT7 (VDC50.GAM_B_LUT7)
+#define VDC50GAM_B_LUT8 (VDC50.GAM_B_LUT8)
+#define VDC50GAM_B_LUT9 (VDC50.GAM_B_LUT9)
+#define VDC50GAM_B_LUT10 (VDC50.GAM_B_LUT10)
+#define VDC50GAM_B_LUT11 (VDC50.GAM_B_LUT11)
+#define VDC50GAM_B_LUT12 (VDC50.GAM_B_LUT12)
+#define VDC50GAM_B_LUT13 (VDC50.GAM_B_LUT13)
+#define VDC50GAM_B_LUT14 (VDC50.GAM_B_LUT14)
+#define VDC50GAM_B_LUT15 (VDC50.GAM_B_LUT15)
+#define VDC50GAM_B_LUT16 (VDC50.GAM_B_LUT16)
+#define VDC50GAM_B_AREA1 (VDC50.GAM_B_AREA1)
+#define VDC50GAM_B_AREA2 (VDC50.GAM_B_AREA2)
+#define VDC50GAM_B_AREA3 (VDC50.GAM_B_AREA3)
+#define VDC50GAM_B_AREA4 (VDC50.GAM_B_AREA4)
+#define VDC50GAM_B_AREA5 (VDC50.GAM_B_AREA5)
+#define VDC50GAM_B_AREA6 (VDC50.GAM_B_AREA6)
+#define VDC50GAM_B_AREA7 (VDC50.GAM_B_AREA7)
+#define VDC50GAM_B_AREA8 (VDC50.GAM_B_AREA8)
+#define VDC50GAM_R_UPDATE (VDC50.GAM_R_UPDATE)
+#define VDC50GAM_R_LUT1 (VDC50.GAM_R_LUT1)
+#define VDC50GAM_R_LUT2 (VDC50.GAM_R_LUT2)
+#define VDC50GAM_R_LUT3 (VDC50.GAM_R_LUT3)
+#define VDC50GAM_R_LUT4 (VDC50.GAM_R_LUT4)
+#define VDC50GAM_R_LUT5 (VDC50.GAM_R_LUT5)
+#define VDC50GAM_R_LUT6 (VDC50.GAM_R_LUT6)
+#define VDC50GAM_R_LUT7 (VDC50.GAM_R_LUT7)
+#define VDC50GAM_R_LUT8 (VDC50.GAM_R_LUT8)
+#define VDC50GAM_R_LUT9 (VDC50.GAM_R_LUT9)
+#define VDC50GAM_R_LUT10 (VDC50.GAM_R_LUT10)
+#define VDC50GAM_R_LUT11 (VDC50.GAM_R_LUT11)
+#define VDC50GAM_R_LUT12 (VDC50.GAM_R_LUT12)
+#define VDC50GAM_R_LUT13 (VDC50.GAM_R_LUT13)
+#define VDC50GAM_R_LUT14 (VDC50.GAM_R_LUT14)
+#define VDC50GAM_R_LUT15 (VDC50.GAM_R_LUT15)
+#define VDC50GAM_R_LUT16 (VDC50.GAM_R_LUT16)
+#define VDC50GAM_R_AREA1 (VDC50.GAM_R_AREA1)
+#define VDC50GAM_R_AREA2 (VDC50.GAM_R_AREA2)
+#define VDC50GAM_R_AREA3 (VDC50.GAM_R_AREA3)
+#define VDC50GAM_R_AREA4 (VDC50.GAM_R_AREA4)
+#define VDC50GAM_R_AREA5 (VDC50.GAM_R_AREA5)
+#define VDC50GAM_R_AREA6 (VDC50.GAM_R_AREA6)
+#define VDC50GAM_R_AREA7 (VDC50.GAM_R_AREA7)
+#define VDC50GAM_R_AREA8 (VDC50.GAM_R_AREA8)
+#define VDC50TCON_UPDATE (VDC50.TCON_UPDATE)
+#define VDC50TCON_TIM (VDC50.TCON_TIM)
+#define VDC50TCON_TIM_STVA1 (VDC50.TCON_TIM_STVA1)
+#define VDC50TCON_TIM_STVA2 (VDC50.TCON_TIM_STVA2)
+#define VDC50TCON_TIM_STVB1 (VDC50.TCON_TIM_STVB1)
+#define VDC50TCON_TIM_STVB2 (VDC50.TCON_TIM_STVB2)
+#define VDC50TCON_TIM_STH1 (VDC50.TCON_TIM_STH1)
+#define VDC50TCON_TIM_STH2 (VDC50.TCON_TIM_STH2)
+#define VDC50TCON_TIM_STB1 (VDC50.TCON_TIM_STB1)
+#define VDC50TCON_TIM_STB2 (VDC50.TCON_TIM_STB2)
+#define VDC50TCON_TIM_CPV1 (VDC50.TCON_TIM_CPV1)
+#define VDC50TCON_TIM_CPV2 (VDC50.TCON_TIM_CPV2)
+#define VDC50TCON_TIM_POLA1 (VDC50.TCON_TIM_POLA1)
+#define VDC50TCON_TIM_POLA2 (VDC50.TCON_TIM_POLA2)
+#define VDC50TCON_TIM_POLB1 (VDC50.TCON_TIM_POLB1)
+#define VDC50TCON_TIM_POLB2 (VDC50.TCON_TIM_POLB2)
+#define VDC50TCON_TIM_DE (VDC50.TCON_TIM_DE)
+#define VDC50OUT_UPDATE (VDC50.OUT_UPDATE)
+#define VDC50OUT_SET (VDC50.OUT_SET)
+#define VDC50OUT_BRIGHT1 (VDC50.OUT_BRIGHT1)
+#define VDC50OUT_BRIGHT2 (VDC50.OUT_BRIGHT2)
+#define VDC50OUT_CONTRAST (VDC50.OUT_CONTRAST)
+#define VDC50OUT_PDTHA (VDC50.OUT_PDTHA)
+#define VDC50OUT_CLK_PHASE (VDC50.OUT_CLK_PHASE)
+#define VDC50SYSCNT_INT1 (VDC50.SYSCNT_INT1)
+#define VDC50SYSCNT_INT2 (VDC50.SYSCNT_INT2)
+#define VDC50SYSCNT_INT3 (VDC50.SYSCNT_INT3)
+#define VDC50SYSCNT_INT4 (VDC50.SYSCNT_INT4)
+#define VDC50SYSCNT_INT5 (VDC50.SYSCNT_INT5)
+#define VDC50SYSCNT_INT6 (VDC50.SYSCNT_INT6)
+#define VDC50SYSCNT_PANEL_CLK (VDC50.SYSCNT_PANEL_CLK)
+#define VDC50SYSCNT_CLUT (VDC50.SYSCNT_CLUT)
+#define VDC50SC1_SCL0_UPDATE (VDC50.SC1_SCL0_UPDATE)
+#define VDC50SC1_SCL0_FRC1 (VDC50.SC1_SCL0_FRC1)
+#define VDC50SC1_SCL0_FRC2 (VDC50.SC1_SCL0_FRC2)
+#define VDC50SC1_SCL0_FRC3 (VDC50.SC1_SCL0_FRC3)
+#define VDC50SC1_SCL0_FRC4 (VDC50.SC1_SCL0_FRC4)
+#define VDC50SC1_SCL0_FRC5 (VDC50.SC1_SCL0_FRC5)
+#define VDC50SC1_SCL0_FRC6 (VDC50.SC1_SCL0_FRC6)
+#define VDC50SC1_SCL0_FRC7 (VDC50.SC1_SCL0_FRC7)
+#define VDC50SC1_SCL0_FRC9 (VDC50.SC1_SCL0_FRC9)
+#define VDC50SC1_SCL0_MON0 (VDC50.SC1_SCL0_MON0)
+#define VDC50SC1_SCL0_INT (VDC50.SC1_SCL0_INT)
+#define VDC50SC1_SCL0_DS1 (VDC50.SC1_SCL0_DS1)
+#define VDC50SC1_SCL0_DS2 (VDC50.SC1_SCL0_DS2)
+#define VDC50SC1_SCL0_DS3 (VDC50.SC1_SCL0_DS3)
+#define VDC50SC1_SCL0_DS4 (VDC50.SC1_SCL0_DS4)
+#define VDC50SC1_SCL0_DS5 (VDC50.SC1_SCL0_DS5)
+#define VDC50SC1_SCL0_DS6 (VDC50.SC1_SCL0_DS6)
+#define VDC50SC1_SCL0_DS7 (VDC50.SC1_SCL0_DS7)
+#define VDC50SC1_SCL0_US1 (VDC50.SC1_SCL0_US1)
+#define VDC50SC1_SCL0_US2 (VDC50.SC1_SCL0_US2)
+#define VDC50SC1_SCL0_US3 (VDC50.SC1_SCL0_US3)
+#define VDC50SC1_SCL0_US4 (VDC50.SC1_SCL0_US4)
+#define VDC50SC1_SCL0_US5 (VDC50.SC1_SCL0_US5)
+#define VDC50SC1_SCL0_US6 (VDC50.SC1_SCL0_US6)
+#define VDC50SC1_SCL0_US7 (VDC50.SC1_SCL0_US7)
+#define VDC50SC1_SCL0_US8 (VDC50.SC1_SCL0_US8)
+#define VDC50SC1_SCL0_OVR1 (VDC50.SC1_SCL0_OVR1)
+#define VDC50SC1_SCL1_UPDATE (VDC50.SC1_SCL1_UPDATE)
+#define VDC50SC1_SCL1_WR1 (VDC50.SC1_SCL1_WR1)
+#define VDC50SC1_SCL1_WR2 (VDC50.SC1_SCL1_WR2)
+#define VDC50SC1_SCL1_WR3 (VDC50.SC1_SCL1_WR3)
+#define VDC50SC1_SCL1_WR4 (VDC50.SC1_SCL1_WR4)
+#define VDC50SC1_SCL1_WR5 (VDC50.SC1_SCL1_WR5)
+#define VDC50SC1_SCL1_WR6 (VDC50.SC1_SCL1_WR6)
+#define VDC50SC1_SCL1_WR7 (VDC50.SC1_SCL1_WR7)
+#define VDC50SC1_SCL1_WR8 (VDC50.SC1_SCL1_WR8)
+#define VDC50SC1_SCL1_WR9 (VDC50.SC1_SCL1_WR9)
+#define VDC50SC1_SCL1_WR10 (VDC50.SC1_SCL1_WR10)
+#define VDC50SC1_SCL1_WR11 (VDC50.SC1_SCL1_WR11)
+#define VDC50SC1_SCL1_MON1 (VDC50.SC1_SCL1_MON1)
+#define VDC50SC1_SCL1_PBUF0 (VDC50.SC1_SCL1_PBUF0)
+#define VDC50SC1_SCL1_PBUF1 (VDC50.SC1_SCL1_PBUF1)
+#define VDC50SC1_SCL1_PBUF2 (VDC50.SC1_SCL1_PBUF2)
+#define VDC50SC1_SCL1_PBUF3 (VDC50.SC1_SCL1_PBUF3)
+#define VDC50SC1_SCL1_PBUF_FLD (VDC50.SC1_SCL1_PBUF_FLD)
+#define VDC50SC1_SCL1_PBUF_CNT (VDC50.SC1_SCL1_PBUF_CNT)
+#define VDC50GR1_UPDATE (VDC50.GR1_UPDATE)
+#define VDC50GR1_FLM_RD (VDC50.GR1_FLM_RD)
+#define VDC50GR1_FLM1 (VDC50.GR1_FLM1)
+#define VDC50GR1_FLM2 (VDC50.GR1_FLM2)
+#define VDC50GR1_FLM3 (VDC50.GR1_FLM3)
+#define VDC50GR1_FLM4 (VDC50.GR1_FLM4)
+#define VDC50GR1_FLM5 (VDC50.GR1_FLM5)
+#define VDC50GR1_FLM6 (VDC50.GR1_FLM6)
+#define VDC50GR1_AB1 (VDC50.GR1_AB1)
+#define VDC50GR1_AB2 (VDC50.GR1_AB2)
+#define VDC50GR1_AB3 (VDC50.GR1_AB3)
+#define VDC50GR1_AB4 (VDC50.GR1_AB4)
+#define VDC50GR1_AB5 (VDC50.GR1_AB5)
+#define VDC50GR1_AB6 (VDC50.GR1_AB6)
+#define VDC50GR1_AB7 (VDC50.GR1_AB7)
+#define VDC50GR1_AB8 (VDC50.GR1_AB8)
+#define VDC50GR1_AB9 (VDC50.GR1_AB9)
+#define VDC50GR1_AB10 (VDC50.GR1_AB10)
+#define VDC50GR1_AB11 (VDC50.GR1_AB11)
+#define VDC50GR1_BASE (VDC50.GR1_BASE)
+#define VDC50GR1_CLUT (VDC50.GR1_CLUT)
+#define VDC50GR1_MON (VDC50.GR1_MON)
+#define VDC50ADJ1_UPDATE (VDC50.ADJ1_UPDATE)
+#define VDC50ADJ1_BKSTR_SET (VDC50.ADJ1_BKSTR_SET)
+#define VDC50ADJ1_ENH_TIM1 (VDC50.ADJ1_ENH_TIM1)
+#define VDC50ADJ1_ENH_TIM2 (VDC50.ADJ1_ENH_TIM2)
+#define VDC50ADJ1_ENH_TIM3 (VDC50.ADJ1_ENH_TIM3)
+#define VDC50ADJ1_ENH_SHP1 (VDC50.ADJ1_ENH_SHP1)
+#define VDC50ADJ1_ENH_SHP2 (VDC50.ADJ1_ENH_SHP2)
+#define VDC50ADJ1_ENH_SHP3 (VDC50.ADJ1_ENH_SHP3)
+#define VDC50ADJ1_ENH_SHP4 (VDC50.ADJ1_ENH_SHP4)
+#define VDC50ADJ1_ENH_SHP5 (VDC50.ADJ1_ENH_SHP5)
+#define VDC50ADJ1_ENH_SHP6 (VDC50.ADJ1_ENH_SHP6)
+#define VDC50ADJ1_ENH_LTI1 (VDC50.ADJ1_ENH_LTI1)
+#define VDC50ADJ1_ENH_LTI2 (VDC50.ADJ1_ENH_LTI2)
+#define VDC50ADJ1_MTX_MODE (VDC50.ADJ1_MTX_MODE)
+#define VDC50ADJ1_MTX_YG_ADJ0 (VDC50.ADJ1_MTX_YG_ADJ0)
+#define VDC50ADJ1_MTX_YG_ADJ1 (VDC50.ADJ1_MTX_YG_ADJ1)
+#define VDC50ADJ1_MTX_CBB_ADJ0 (VDC50.ADJ1_MTX_CBB_ADJ0)
+#define VDC50ADJ1_MTX_CBB_ADJ1 (VDC50.ADJ1_MTX_CBB_ADJ1)
+#define VDC50ADJ1_MTX_CRR_ADJ0 (VDC50.ADJ1_MTX_CRR_ADJ0)
+#define VDC50ADJ1_MTX_CRR_ADJ1 (VDC50.ADJ1_MTX_CRR_ADJ1)
+#define VDC50GR_VIN_UPDATE (VDC50.GR_VIN_UPDATE)
+#define VDC50GR_VIN_AB1 (VDC50.GR_VIN_AB1)
+#define VDC50GR_VIN_AB2 (VDC50.GR_VIN_AB2)
+#define VDC50GR_VIN_AB3 (VDC50.GR_VIN_AB3)
+#define VDC50GR_VIN_AB4 (VDC50.GR_VIN_AB4)
+#define VDC50GR_VIN_AB5 (VDC50.GR_VIN_AB5)
+#define VDC50GR_VIN_AB6 (VDC50.GR_VIN_AB6)
+#define VDC50GR_VIN_AB7 (VDC50.GR_VIN_AB7)
+#define VDC50GR_VIN_BASE (VDC50.GR_VIN_BASE)
+#define VDC50GR_VIN_MON (VDC50.GR_VIN_MON)
+#define VDC50OIR_SCL0_UPDATE (VDC50.OIR_SCL0_UPDATE)
+#define VDC50OIR_SCL0_FRC1 (VDC50.OIR_SCL0_FRC1)
+#define VDC50OIR_SCL0_FRC2 (VDC50.OIR_SCL0_FRC2)
+#define VDC50OIR_SCL0_FRC3 (VDC50.OIR_SCL0_FRC3)
+#define VDC50OIR_SCL0_FRC4 (VDC50.OIR_SCL0_FRC4)
+#define VDC50OIR_SCL0_FRC5 (VDC50.OIR_SCL0_FRC5)
+#define VDC50OIR_SCL0_FRC6 (VDC50.OIR_SCL0_FRC6)
+#define VDC50OIR_SCL0_FRC7 (VDC50.OIR_SCL0_FRC7)
+#define VDC50OIR_SCL0_DS1 (VDC50.OIR_SCL0_DS1)
+#define VDC50OIR_SCL0_DS2 (VDC50.OIR_SCL0_DS2)
+#define VDC50OIR_SCL0_DS3 (VDC50.OIR_SCL0_DS3)
+#define VDC50OIR_SCL0_DS7 (VDC50.OIR_SCL0_DS7)
+#define VDC50OIR_SCL0_US1 (VDC50.OIR_SCL0_US1)
+#define VDC50OIR_SCL0_US2 (VDC50.OIR_SCL0_US2)
+#define VDC50OIR_SCL0_US3 (VDC50.OIR_SCL0_US3)
+#define VDC50OIR_SCL0_US8 (VDC50.OIR_SCL0_US8)
+#define VDC50OIR_SCL0_OVR1 (VDC50.OIR_SCL0_OVR1)
+#define VDC50OIR_SCL1_UPDATE (VDC50.OIR_SCL1_UPDATE)
+#define VDC50OIR_SCL1_WR1 (VDC50.OIR_SCL1_WR1)
+#define VDC50OIR_SCL1_WR2 (VDC50.OIR_SCL1_WR2)
+#define VDC50OIR_SCL1_WR3 (VDC50.OIR_SCL1_WR3)
+#define VDC50OIR_SCL1_WR4 (VDC50.OIR_SCL1_WR4)
+#define VDC50OIR_SCL1_WR5 (VDC50.OIR_SCL1_WR5)
+#define VDC50OIR_SCL1_WR6 (VDC50.OIR_SCL1_WR6)
+#define VDC50OIR_SCL1_WR7 (VDC50.OIR_SCL1_WR7)
+#define VDC50GR_OIR_UPDATE (VDC50.GR_OIR_UPDATE)
+#define VDC50GR_OIR_FLM_RD (VDC50.GR_OIR_FLM_RD)
+#define VDC50GR_OIR_FLM1 (VDC50.GR_OIR_FLM1)
+#define VDC50GR_OIR_FLM2 (VDC50.GR_OIR_FLM2)
+#define VDC50GR_OIR_FLM3 (VDC50.GR_OIR_FLM3)
+#define VDC50GR_OIR_FLM4 (VDC50.GR_OIR_FLM4)
+#define VDC50GR_OIR_FLM5 (VDC50.GR_OIR_FLM5)
+#define VDC50GR_OIR_FLM6 (VDC50.GR_OIR_FLM6)
+#define VDC50GR_OIR_AB1 (VDC50.GR_OIR_AB1)
+#define VDC50GR_OIR_AB2 (VDC50.GR_OIR_AB2)
+#define VDC50GR_OIR_AB3 (VDC50.GR_OIR_AB3)
+#define VDC50GR_OIR_AB7 (VDC50.GR_OIR_AB7)
+#define VDC50GR_OIR_AB8 (VDC50.GR_OIR_AB8)
+#define VDC50GR_OIR_AB9 (VDC50.GR_OIR_AB9)
+#define VDC50GR_OIR_AB10 (VDC50.GR_OIR_AB10)
+#define VDC50GR_OIR_AB11 (VDC50.GR_OIR_AB11)
+#define VDC50GR_OIR_BASE (VDC50.GR_OIR_BASE)
+#define VDC50GR_OIR_CLUT (VDC50.GR_OIR_CLUT)
+#define VDC50GR_OIR_MON (VDC50.GR_OIR_MON)
+#define VDC51INP_UPDATE (VDC51.INP_UPDATE)
+#define VDC51INP_SEL_CNT (VDC51.INP_SEL_CNT)
+#define VDC51INP_EXT_SYNC_CNT (VDC51.INP_EXT_SYNC_CNT)
+#define VDC51INP_VSYNC_PH_ADJ (VDC51.INP_VSYNC_PH_ADJ)
+#define VDC51INP_DLY_ADJ (VDC51.INP_DLY_ADJ)
+#define VDC51IMGCNT_UPDATE (VDC51.IMGCNT_UPDATE)
+#define VDC51IMGCNT_NR_CNT0 (VDC51.IMGCNT_NR_CNT0)
+#define VDC51IMGCNT_NR_CNT1 (VDC51.IMGCNT_NR_CNT1)
+#define VDC51IMGCNT_MTX_MODE (VDC51.IMGCNT_MTX_MODE)
+#define VDC51IMGCNT_MTX_YG_ADJ0 (VDC51.IMGCNT_MTX_YG_ADJ0)
+#define VDC51IMGCNT_MTX_YG_ADJ1 (VDC51.IMGCNT_MTX_YG_ADJ1)
+#define VDC51IMGCNT_MTX_CBB_ADJ0 (VDC51.IMGCNT_MTX_CBB_ADJ0)
+#define VDC51IMGCNT_MTX_CBB_ADJ1 (VDC51.IMGCNT_MTX_CBB_ADJ1)
+#define VDC51IMGCNT_MTX_CRR_ADJ0 (VDC51.IMGCNT_MTX_CRR_ADJ0)
+#define VDC51IMGCNT_MTX_CRR_ADJ1 (VDC51.IMGCNT_MTX_CRR_ADJ1)
+#define VDC51IMGCNT_DRC_REG (VDC51.IMGCNT_DRC_REG)
+#define VDC51SC0_SCL0_UPDATE (VDC51.SC0_SCL0_UPDATE)
+#define VDC51SC0_SCL0_FRC1 (VDC51.SC0_SCL0_FRC1)
+#define VDC51SC0_SCL0_FRC2 (VDC51.SC0_SCL0_FRC2)
+#define VDC51SC0_SCL0_FRC3 (VDC51.SC0_SCL0_FRC3)
+#define VDC51SC0_SCL0_FRC4 (VDC51.SC0_SCL0_FRC4)
+#define VDC51SC0_SCL0_FRC5 (VDC51.SC0_SCL0_FRC5)
+#define VDC51SC0_SCL0_FRC6 (VDC51.SC0_SCL0_FRC6)
+#define VDC51SC0_SCL0_FRC7 (VDC51.SC0_SCL0_FRC7)
+#define VDC51SC0_SCL0_FRC9 (VDC51.SC0_SCL0_FRC9)
+#define VDC51SC0_SCL0_MON0 (VDC51.SC0_SCL0_MON0)
+#define VDC51SC0_SCL0_INT (VDC51.SC0_SCL0_INT)
+#define VDC51SC0_SCL0_DS1 (VDC51.SC0_SCL0_DS1)
+#define VDC51SC0_SCL0_DS2 (VDC51.SC0_SCL0_DS2)
+#define VDC51SC0_SCL0_DS3 (VDC51.SC0_SCL0_DS3)
+#define VDC51SC0_SCL0_DS4 (VDC51.SC0_SCL0_DS4)
+#define VDC51SC0_SCL0_DS5 (VDC51.SC0_SCL0_DS5)
+#define VDC51SC0_SCL0_DS6 (VDC51.SC0_SCL0_DS6)
+#define VDC51SC0_SCL0_DS7 (VDC51.SC0_SCL0_DS7)
+#define VDC51SC0_SCL0_US1 (VDC51.SC0_SCL0_US1)
+#define VDC51SC0_SCL0_US2 (VDC51.SC0_SCL0_US2)
+#define VDC51SC0_SCL0_US3 (VDC51.SC0_SCL0_US3)
+#define VDC51SC0_SCL0_US4 (VDC51.SC0_SCL0_US4)
+#define VDC51SC0_SCL0_US5 (VDC51.SC0_SCL0_US5)
+#define VDC51SC0_SCL0_US6 (VDC51.SC0_SCL0_US6)
+#define VDC51SC0_SCL0_US7 (VDC51.SC0_SCL0_US7)
+#define VDC51SC0_SCL0_US8 (VDC51.SC0_SCL0_US8)
+#define VDC51SC0_SCL0_OVR1 (VDC51.SC0_SCL0_OVR1)
+#define VDC51SC0_SCL1_UPDATE (VDC51.SC0_SCL1_UPDATE)
+#define VDC51SC0_SCL1_WR1 (VDC51.SC0_SCL1_WR1)
+#define VDC51SC0_SCL1_WR2 (VDC51.SC0_SCL1_WR2)
+#define VDC51SC0_SCL1_WR3 (VDC51.SC0_SCL1_WR3)
+#define VDC51SC0_SCL1_WR4 (VDC51.SC0_SCL1_WR4)
+#define VDC51SC0_SCL1_WR5 (VDC51.SC0_SCL1_WR5)
+#define VDC51SC0_SCL1_WR6 (VDC51.SC0_SCL1_WR6)
+#define VDC51SC0_SCL1_WR7 (VDC51.SC0_SCL1_WR7)
+#define VDC51SC0_SCL1_WR8 (VDC51.SC0_SCL1_WR8)
+#define VDC51SC0_SCL1_WR9 (VDC51.SC0_SCL1_WR9)
+#define VDC51SC0_SCL1_WR10 (VDC51.SC0_SCL1_WR10)
+#define VDC51SC0_SCL1_WR11 (VDC51.SC0_SCL1_WR11)
+#define VDC51SC0_SCL1_MON1 (VDC51.SC0_SCL1_MON1)
+#define VDC51SC0_SCL1_PBUF0 (VDC51.SC0_SCL1_PBUF0)
+#define VDC51SC0_SCL1_PBUF1 (VDC51.SC0_SCL1_PBUF1)
+#define VDC51SC0_SCL1_PBUF2 (VDC51.SC0_SCL1_PBUF2)
+#define VDC51SC0_SCL1_PBUF3 (VDC51.SC0_SCL1_PBUF3)
+#define VDC51SC0_SCL1_PBUF_FLD (VDC51.SC0_SCL1_PBUF_FLD)
+#define VDC51SC0_SCL1_PBUF_CNT (VDC51.SC0_SCL1_PBUF_CNT)
+#define VDC51GR0_UPDATE (VDC51.GR0_UPDATE)
+#define VDC51GR0_FLM_RD (VDC51.GR0_FLM_RD)
+#define VDC51GR0_FLM1 (VDC51.GR0_FLM1)
+#define VDC51GR0_FLM2 (VDC51.GR0_FLM2)
+#define VDC51GR0_FLM3 (VDC51.GR0_FLM3)
+#define VDC51GR0_FLM4 (VDC51.GR0_FLM4)
+#define VDC51GR0_FLM5 (VDC51.GR0_FLM5)
+#define VDC51GR0_FLM6 (VDC51.GR0_FLM6)
+#define VDC51GR0_AB1 (VDC51.GR0_AB1)
+#define VDC51GR0_AB2 (VDC51.GR0_AB2)
+#define VDC51GR0_AB3 (VDC51.GR0_AB3)
+#define VDC51GR0_AB7 (VDC51.GR0_AB7)
+#define VDC51GR0_AB8 (VDC51.GR0_AB8)
+#define VDC51GR0_AB9 (VDC51.GR0_AB9)
+#define VDC51GR0_AB10 (VDC51.GR0_AB10)
+#define VDC51GR0_AB11 (VDC51.GR0_AB11)
+#define VDC51GR0_BASE (VDC51.GR0_BASE)
+#define VDC51GR0_CLUT (VDC51.GR0_CLUT)
+#define VDC51ADJ0_UPDATE (VDC51.ADJ0_UPDATE)
+#define VDC51ADJ0_BKSTR_SET (VDC51.ADJ0_BKSTR_SET)
+#define VDC51ADJ0_ENH_TIM1 (VDC51.ADJ0_ENH_TIM1)
+#define VDC51ADJ0_ENH_TIM2 (VDC51.ADJ0_ENH_TIM2)
+#define VDC51ADJ0_ENH_TIM3 (VDC51.ADJ0_ENH_TIM3)
+#define VDC51ADJ0_ENH_SHP1 (VDC51.ADJ0_ENH_SHP1)
+#define VDC51ADJ0_ENH_SHP2 (VDC51.ADJ0_ENH_SHP2)
+#define VDC51ADJ0_ENH_SHP3 (VDC51.ADJ0_ENH_SHP3)
+#define VDC51ADJ0_ENH_SHP4 (VDC51.ADJ0_ENH_SHP4)
+#define VDC51ADJ0_ENH_SHP5 (VDC51.ADJ0_ENH_SHP5)
+#define VDC51ADJ0_ENH_SHP6 (VDC51.ADJ0_ENH_SHP6)
+#define VDC51ADJ0_ENH_LTI1 (VDC51.ADJ0_ENH_LTI1)
+#define VDC51ADJ0_ENH_LTI2 (VDC51.ADJ0_ENH_LTI2)
+#define VDC51ADJ0_MTX_MODE (VDC51.ADJ0_MTX_MODE)
+#define VDC51ADJ0_MTX_YG_ADJ0 (VDC51.ADJ0_MTX_YG_ADJ0)
+#define VDC51ADJ0_MTX_YG_ADJ1 (VDC51.ADJ0_MTX_YG_ADJ1)
+#define VDC51ADJ0_MTX_CBB_ADJ0 (VDC51.ADJ0_MTX_CBB_ADJ0)
+#define VDC51ADJ0_MTX_CBB_ADJ1 (VDC51.ADJ0_MTX_CBB_ADJ1)
+#define VDC51ADJ0_MTX_CRR_ADJ0 (VDC51.ADJ0_MTX_CRR_ADJ0)
+#define VDC51ADJ0_MTX_CRR_ADJ1 (VDC51.ADJ0_MTX_CRR_ADJ1)
+#define VDC51GR2_UPDATE (VDC51.GR2_UPDATE)
+#define VDC51GR2_FLM_RD (VDC51.GR2_FLM_RD)
+#define VDC51GR2_FLM1 (VDC51.GR2_FLM1)
+#define VDC51GR2_FLM2 (VDC51.GR2_FLM2)
+#define VDC51GR2_FLM3 (VDC51.GR2_FLM3)
+#define VDC51GR2_FLM4 (VDC51.GR2_FLM4)
+#define VDC51GR2_FLM5 (VDC51.GR2_FLM5)
+#define VDC51GR2_FLM6 (VDC51.GR2_FLM6)
+#define VDC51GR2_AB1 (VDC51.GR2_AB1)
+#define VDC51GR2_AB2 (VDC51.GR2_AB2)
+#define VDC51GR2_AB3 (VDC51.GR2_AB3)
+#define VDC51GR2_AB4 (VDC51.GR2_AB4)
+#define VDC51GR2_AB5 (VDC51.GR2_AB5)
+#define VDC51GR2_AB6 (VDC51.GR2_AB6)
+#define VDC51GR2_AB7 (VDC51.GR2_AB7)
+#define VDC51GR2_AB8 (VDC51.GR2_AB8)
+#define VDC51GR2_AB9 (VDC51.GR2_AB9)
+#define VDC51GR2_AB10 (VDC51.GR2_AB10)
+#define VDC51GR2_AB11 (VDC51.GR2_AB11)
+#define VDC51GR2_BASE (VDC51.GR2_BASE)
+#define VDC51GR2_CLUT (VDC51.GR2_CLUT)
+#define VDC51GR2_MON (VDC51.GR2_MON)
+#define VDC51GR3_UPDATE (VDC51.GR3_UPDATE)
+#define VDC51GR3_FLM_RD (VDC51.GR3_FLM_RD)
+#define VDC51GR3_FLM1 (VDC51.GR3_FLM1)
+#define VDC51GR3_FLM2 (VDC51.GR3_FLM2)
+#define VDC51GR3_FLM3 (VDC51.GR3_FLM3)
+#define VDC51GR3_FLM4 (VDC51.GR3_FLM4)
+#define VDC51GR3_FLM5 (VDC51.GR3_FLM5)
+#define VDC51GR3_FLM6 (VDC51.GR3_FLM6)
+#define VDC51GR3_AB1 (VDC51.GR3_AB1)
+#define VDC51GR3_AB2 (VDC51.GR3_AB2)
+#define VDC51GR3_AB3 (VDC51.GR3_AB3)
+#define VDC51GR3_AB4 (VDC51.GR3_AB4)
+#define VDC51GR3_AB5 (VDC51.GR3_AB5)
+#define VDC51GR3_AB6 (VDC51.GR3_AB6)
+#define VDC51GR3_AB7 (VDC51.GR3_AB7)
+#define VDC51GR3_AB8 (VDC51.GR3_AB8)
+#define VDC51GR3_AB9 (VDC51.GR3_AB9)
+#define VDC51GR3_AB10 (VDC51.GR3_AB10)
+#define VDC51GR3_AB11 (VDC51.GR3_AB11)
+#define VDC51GR3_BASE (VDC51.GR3_BASE)
+#define VDC51GR3_CLUT_INT (VDC51.GR3_CLUT_INT)
+#define VDC51GR3_MON (VDC51.GR3_MON)
+#define VDC51GAM_G_UPDATE (VDC51.GAM_G_UPDATE)
+#define VDC51GAM_SW (VDC51.GAM_SW)
+#define VDC51GAM_G_LUT1 (VDC51.GAM_G_LUT1)
+#define VDC51GAM_G_LUT2 (VDC51.GAM_G_LUT2)
+#define VDC51GAM_G_LUT3 (VDC51.GAM_G_LUT3)
+#define VDC51GAM_G_LUT4 (VDC51.GAM_G_LUT4)
+#define VDC51GAM_G_LUT5 (VDC51.GAM_G_LUT5)
+#define VDC51GAM_G_LUT6 (VDC51.GAM_G_LUT6)
+#define VDC51GAM_G_LUT7 (VDC51.GAM_G_LUT7)
+#define VDC51GAM_G_LUT8 (VDC51.GAM_G_LUT8)
+#define VDC51GAM_G_LUT9 (VDC51.GAM_G_LUT9)
+#define VDC51GAM_G_LUT10 (VDC51.GAM_G_LUT10)
+#define VDC51GAM_G_LUT11 (VDC51.GAM_G_LUT11)
+#define VDC51GAM_G_LUT12 (VDC51.GAM_G_LUT12)
+#define VDC51GAM_G_LUT13 (VDC51.GAM_G_LUT13)
+#define VDC51GAM_G_LUT14 (VDC51.GAM_G_LUT14)
+#define VDC51GAM_G_LUT15 (VDC51.GAM_G_LUT15)
+#define VDC51GAM_G_LUT16 (VDC51.GAM_G_LUT16)
+#define VDC51GAM_G_AREA1 (VDC51.GAM_G_AREA1)
+#define VDC51GAM_G_AREA2 (VDC51.GAM_G_AREA2)
+#define VDC51GAM_G_AREA3 (VDC51.GAM_G_AREA3)
+#define VDC51GAM_G_AREA4 (VDC51.GAM_G_AREA4)
+#define VDC51GAM_G_AREA5 (VDC51.GAM_G_AREA5)
+#define VDC51GAM_G_AREA6 (VDC51.GAM_G_AREA6)
+#define VDC51GAM_G_AREA7 (VDC51.GAM_G_AREA7)
+#define VDC51GAM_G_AREA8 (VDC51.GAM_G_AREA8)
+#define VDC51GAM_B_UPDATE (VDC51.GAM_B_UPDATE)
+#define VDC51GAM_B_LUT1 (VDC51.GAM_B_LUT1)
+#define VDC51GAM_B_LUT2 (VDC51.GAM_B_LUT2)
+#define VDC51GAM_B_LUT3 (VDC51.GAM_B_LUT3)
+#define VDC51GAM_B_LUT4 (VDC51.GAM_B_LUT4)
+#define VDC51GAM_B_LUT5 (VDC51.GAM_B_LUT5)
+#define VDC51GAM_B_LUT6 (VDC51.GAM_B_LUT6)
+#define VDC51GAM_B_LUT7 (VDC51.GAM_B_LUT7)
+#define VDC51GAM_B_LUT8 (VDC51.GAM_B_LUT8)
+#define VDC51GAM_B_LUT9 (VDC51.GAM_B_LUT9)
+#define VDC51GAM_B_LUT10 (VDC51.GAM_B_LUT10)
+#define VDC51GAM_B_LUT11 (VDC51.GAM_B_LUT11)
+#define VDC51GAM_B_LUT12 (VDC51.GAM_B_LUT12)
+#define VDC51GAM_B_LUT13 (VDC51.GAM_B_LUT13)
+#define VDC51GAM_B_LUT14 (VDC51.GAM_B_LUT14)
+#define VDC51GAM_B_LUT15 (VDC51.GAM_B_LUT15)
+#define VDC51GAM_B_LUT16 (VDC51.GAM_B_LUT16)
+#define VDC51GAM_B_AREA1 (VDC51.GAM_B_AREA1)
+#define VDC51GAM_B_AREA2 (VDC51.GAM_B_AREA2)
+#define VDC51GAM_B_AREA3 (VDC51.GAM_B_AREA3)
+#define VDC51GAM_B_AREA4 (VDC51.GAM_B_AREA4)
+#define VDC51GAM_B_AREA5 (VDC51.GAM_B_AREA5)
+#define VDC51GAM_B_AREA6 (VDC51.GAM_B_AREA6)
+#define VDC51GAM_B_AREA7 (VDC51.GAM_B_AREA7)
+#define VDC51GAM_B_AREA8 (VDC51.GAM_B_AREA8)
+#define VDC51GAM_R_UPDATE (VDC51.GAM_R_UPDATE)
+#define VDC51GAM_R_LUT1 (VDC51.GAM_R_LUT1)
+#define VDC51GAM_R_LUT2 (VDC51.GAM_R_LUT2)
+#define VDC51GAM_R_LUT3 (VDC51.GAM_R_LUT3)
+#define VDC51GAM_R_LUT4 (VDC51.GAM_R_LUT4)
+#define VDC51GAM_R_LUT5 (VDC51.GAM_R_LUT5)
+#define VDC51GAM_R_LUT6 (VDC51.GAM_R_LUT6)
+#define VDC51GAM_R_LUT7 (VDC51.GAM_R_LUT7)
+#define VDC51GAM_R_LUT8 (VDC51.GAM_R_LUT8)
+#define VDC51GAM_R_LUT9 (VDC51.GAM_R_LUT9)
+#define VDC51GAM_R_LUT10 (VDC51.GAM_R_LUT10)
+#define VDC51GAM_R_LUT11 (VDC51.GAM_R_LUT11)
+#define VDC51GAM_R_LUT12 (VDC51.GAM_R_LUT12)
+#define VDC51GAM_R_LUT13 (VDC51.GAM_R_LUT13)
+#define VDC51GAM_R_LUT14 (VDC51.GAM_R_LUT14)
+#define VDC51GAM_R_LUT15 (VDC51.GAM_R_LUT15)
+#define VDC51GAM_R_LUT16 (VDC51.GAM_R_LUT16)
+#define VDC51GAM_R_AREA1 (VDC51.GAM_R_AREA1)
+#define VDC51GAM_R_AREA2 (VDC51.GAM_R_AREA2)
+#define VDC51GAM_R_AREA3 (VDC51.GAM_R_AREA3)
+#define VDC51GAM_R_AREA4 (VDC51.GAM_R_AREA4)
+#define VDC51GAM_R_AREA5 (VDC51.GAM_R_AREA5)
+#define VDC51GAM_R_AREA6 (VDC51.GAM_R_AREA6)
+#define VDC51GAM_R_AREA7 (VDC51.GAM_R_AREA7)
+#define VDC51GAM_R_AREA8 (VDC51.GAM_R_AREA8)
+#define VDC51TCON_UPDATE (VDC51.TCON_UPDATE)
+#define VDC51TCON_TIM (VDC51.TCON_TIM)
+#define VDC51TCON_TIM_STVA1 (VDC51.TCON_TIM_STVA1)
+#define VDC51TCON_TIM_STVA2 (VDC51.TCON_TIM_STVA2)
+#define VDC51TCON_TIM_STVB1 (VDC51.TCON_TIM_STVB1)
+#define VDC51TCON_TIM_STVB2 (VDC51.TCON_TIM_STVB2)
+#define VDC51TCON_TIM_STH1 (VDC51.TCON_TIM_STH1)
+#define VDC51TCON_TIM_STH2 (VDC51.TCON_TIM_STH2)
+#define VDC51TCON_TIM_STB1 (VDC51.TCON_TIM_STB1)
+#define VDC51TCON_TIM_STB2 (VDC51.TCON_TIM_STB2)
+#define VDC51TCON_TIM_CPV1 (VDC51.TCON_TIM_CPV1)
+#define VDC51TCON_TIM_CPV2 (VDC51.TCON_TIM_CPV2)
+#define VDC51TCON_TIM_POLA1 (VDC51.TCON_TIM_POLA1)
+#define VDC51TCON_TIM_POLA2 (VDC51.TCON_TIM_POLA2)
+#define VDC51TCON_TIM_POLB1 (VDC51.TCON_TIM_POLB1)
+#define VDC51TCON_TIM_POLB2 (VDC51.TCON_TIM_POLB2)
+#define VDC51TCON_TIM_DE (VDC51.TCON_TIM_DE)
+#define VDC51OUT_UPDATE (VDC51.OUT_UPDATE)
+#define VDC51OUT_SET (VDC51.OUT_SET)
+#define VDC51OUT_BRIGHT1 (VDC51.OUT_BRIGHT1)
+#define VDC51OUT_BRIGHT2 (VDC51.OUT_BRIGHT2)
+#define VDC51OUT_CONTRAST (VDC51.OUT_CONTRAST)
+#define VDC51OUT_PDTHA (VDC51.OUT_PDTHA)
+#define VDC51OUT_CLK_PHASE (VDC51.OUT_CLK_PHASE)
+#define VDC51SYSCNT_INT1 (VDC51.SYSCNT_INT1)
+#define VDC51SYSCNT_INT2 (VDC51.SYSCNT_INT2)
+#define VDC51SYSCNT_INT3 (VDC51.SYSCNT_INT3)
+#define VDC51SYSCNT_INT4 (VDC51.SYSCNT_INT4)
+#define VDC51SYSCNT_INT5 (VDC51.SYSCNT_INT5)
+#define VDC51SYSCNT_INT6 (VDC51.SYSCNT_INT6)
+#define VDC51SYSCNT_PANEL_CLK (VDC51.SYSCNT_PANEL_CLK)
+#define VDC51SYSCNT_CLUT (VDC51.SYSCNT_CLUT)
+#define VDC51SC1_SCL0_UPDATE (VDC51.SC1_SCL0_UPDATE)
+#define VDC51SC1_SCL0_FRC1 (VDC51.SC1_SCL0_FRC1)
+#define VDC51SC1_SCL0_FRC2 (VDC51.SC1_SCL0_FRC2)
+#define VDC51SC1_SCL0_FRC3 (VDC51.SC1_SCL0_FRC3)
+#define VDC51SC1_SCL0_FRC4 (VDC51.SC1_SCL0_FRC4)
+#define VDC51SC1_SCL0_FRC5 (VDC51.SC1_SCL0_FRC5)
+#define VDC51SC1_SCL0_FRC6 (VDC51.SC1_SCL0_FRC6)
+#define VDC51SC1_SCL0_FRC7 (VDC51.SC1_SCL0_FRC7)
+#define VDC51SC1_SCL0_FRC9 (VDC51.SC1_SCL0_FRC9)
+#define VDC51SC1_SCL0_MON0 (VDC51.SC1_SCL0_MON0)
+#define VDC51SC1_SCL0_INT (VDC51.SC1_SCL0_INT)
+#define VDC51SC1_SCL0_DS1 (VDC51.SC1_SCL0_DS1)
+#define VDC51SC1_SCL0_DS2 (VDC51.SC1_SCL0_DS2)
+#define VDC51SC1_SCL0_DS3 (VDC51.SC1_SCL0_DS3)
+#define VDC51SC1_SCL0_DS4 (VDC51.SC1_SCL0_DS4)
+#define VDC51SC1_SCL0_DS5 (VDC51.SC1_SCL0_DS5)
+#define VDC51SC1_SCL0_DS6 (VDC51.SC1_SCL0_DS6)
+#define VDC51SC1_SCL0_DS7 (VDC51.SC1_SCL0_DS7)
+#define VDC51SC1_SCL0_US1 (VDC51.SC1_SCL0_US1)
+#define VDC51SC1_SCL0_US2 (VDC51.SC1_SCL0_US2)
+#define VDC51SC1_SCL0_US3 (VDC51.SC1_SCL0_US3)
+#define VDC51SC1_SCL0_US4 (VDC51.SC1_SCL0_US4)
+#define VDC51SC1_SCL0_US5 (VDC51.SC1_SCL0_US5)
+#define VDC51SC1_SCL0_US6 (VDC51.SC1_SCL0_US6)
+#define VDC51SC1_SCL0_US7 (VDC51.SC1_SCL0_US7)
+#define VDC51SC1_SCL0_US8 (VDC51.SC1_SCL0_US8)
+#define VDC51SC1_SCL0_OVR1 (VDC51.SC1_SCL0_OVR1)
+#define VDC51SC1_SCL1_UPDATE (VDC51.SC1_SCL1_UPDATE)
+#define VDC51SC1_SCL1_WR1 (VDC51.SC1_SCL1_WR1)
+#define VDC51SC1_SCL1_WR2 (VDC51.SC1_SCL1_WR2)
+#define VDC51SC1_SCL1_WR3 (VDC51.SC1_SCL1_WR3)
+#define VDC51SC1_SCL1_WR4 (VDC51.SC1_SCL1_WR4)
+#define VDC51SC1_SCL1_WR5 (VDC51.SC1_SCL1_WR5)
+#define VDC51SC1_SCL1_WR6 (VDC51.SC1_SCL1_WR6)
+#define VDC51SC1_SCL1_WR7 (VDC51.SC1_SCL1_WR7)
+#define VDC51SC1_SCL1_WR8 (VDC51.SC1_SCL1_WR8)
+#define VDC51SC1_SCL1_WR9 (VDC51.SC1_SCL1_WR9)
+#define VDC51SC1_SCL1_WR10 (VDC51.SC1_SCL1_WR10)
+#define VDC51SC1_SCL1_WR11 (VDC51.SC1_SCL1_WR11)
+#define VDC51SC1_SCL1_MON1 (VDC51.SC1_SCL1_MON1)
+#define VDC51SC1_SCL1_PBUF0 (VDC51.SC1_SCL1_PBUF0)
+#define VDC51SC1_SCL1_PBUF1 (VDC51.SC1_SCL1_PBUF1)
+#define VDC51SC1_SCL1_PBUF2 (VDC51.SC1_SCL1_PBUF2)
+#define VDC51SC1_SCL1_PBUF3 (VDC51.SC1_SCL1_PBUF3)
+#define VDC51SC1_SCL1_PBUF_FLD (VDC51.SC1_SCL1_PBUF_FLD)
+#define VDC51SC1_SCL1_PBUF_CNT (VDC51.SC1_SCL1_PBUF_CNT)
+#define VDC51GR1_UPDATE (VDC51.GR1_UPDATE)
+#define VDC51GR1_FLM_RD (VDC51.GR1_FLM_RD)
+#define VDC51GR1_FLM1 (VDC51.GR1_FLM1)
+#define VDC51GR1_FLM2 (VDC51.GR1_FLM2)
+#define VDC51GR1_FLM3 (VDC51.GR1_FLM3)
+#define VDC51GR1_FLM4 (VDC51.GR1_FLM4)
+#define VDC51GR1_FLM5 (VDC51.GR1_FLM5)
+#define VDC51GR1_FLM6 (VDC51.GR1_FLM6)
+#define VDC51GR1_AB1 (VDC51.GR1_AB1)
+#define VDC51GR1_AB2 (VDC51.GR1_AB2)
+#define VDC51GR1_AB3 (VDC51.GR1_AB3)
+#define VDC51GR1_AB4 (VDC51.GR1_AB4)
+#define VDC51GR1_AB5 (VDC51.GR1_AB5)
+#define VDC51GR1_AB6 (VDC51.GR1_AB6)
+#define VDC51GR1_AB7 (VDC51.GR1_AB7)
+#define VDC51GR1_AB8 (VDC51.GR1_AB8)
+#define VDC51GR1_AB9 (VDC51.GR1_AB9)
+#define VDC51GR1_AB10 (VDC51.GR1_AB10)
+#define VDC51GR1_AB11 (VDC51.GR1_AB11)
+#define VDC51GR1_BASE (VDC51.GR1_BASE)
+#define VDC51GR1_CLUT (VDC51.GR1_CLUT)
+#define VDC51GR1_MON (VDC51.GR1_MON)
+#define VDC51ADJ1_UPDATE (VDC51.ADJ1_UPDATE)
+#define VDC51ADJ1_BKSTR_SET (VDC51.ADJ1_BKSTR_SET)
+#define VDC51ADJ1_ENH_TIM1 (VDC51.ADJ1_ENH_TIM1)
+#define VDC51ADJ1_ENH_TIM2 (VDC51.ADJ1_ENH_TIM2)
+#define VDC51ADJ1_ENH_TIM3 (VDC51.ADJ1_ENH_TIM3)
+#define VDC51ADJ1_ENH_SHP1 (VDC51.ADJ1_ENH_SHP1)
+#define VDC51ADJ1_ENH_SHP2 (VDC51.ADJ1_ENH_SHP2)
+#define VDC51ADJ1_ENH_SHP3 (VDC51.ADJ1_ENH_SHP3)
+#define VDC51ADJ1_ENH_SHP4 (VDC51.ADJ1_ENH_SHP4)
+#define VDC51ADJ1_ENH_SHP5 (VDC51.ADJ1_ENH_SHP5)
+#define VDC51ADJ1_ENH_SHP6 (VDC51.ADJ1_ENH_SHP6)
+#define VDC51ADJ1_ENH_LTI1 (VDC51.ADJ1_ENH_LTI1)
+#define VDC51ADJ1_ENH_LTI2 (VDC51.ADJ1_ENH_LTI2)
+#define VDC51ADJ1_MTX_MODE (VDC51.ADJ1_MTX_MODE)
+#define VDC51ADJ1_MTX_YG_ADJ0 (VDC51.ADJ1_MTX_YG_ADJ0)
+#define VDC51ADJ1_MTX_YG_ADJ1 (VDC51.ADJ1_MTX_YG_ADJ1)
+#define VDC51ADJ1_MTX_CBB_ADJ0 (VDC51.ADJ1_MTX_CBB_ADJ0)
+#define VDC51ADJ1_MTX_CBB_ADJ1 (VDC51.ADJ1_MTX_CBB_ADJ1)
+#define VDC51ADJ1_MTX_CRR_ADJ0 (VDC51.ADJ1_MTX_CRR_ADJ0)
+#define VDC51ADJ1_MTX_CRR_ADJ1 (VDC51.ADJ1_MTX_CRR_ADJ1)
+#define VDC51GR_VIN_UPDATE (VDC51.GR_VIN_UPDATE)
+#define VDC51GR_VIN_AB1 (VDC51.GR_VIN_AB1)
+#define VDC51GR_VIN_AB2 (VDC51.GR_VIN_AB2)
+#define VDC51GR_VIN_AB3 (VDC51.GR_VIN_AB3)
+#define VDC51GR_VIN_AB4 (VDC51.GR_VIN_AB4)
+#define VDC51GR_VIN_AB5 (VDC51.GR_VIN_AB5)
+#define VDC51GR_VIN_AB6 (VDC51.GR_VIN_AB6)
+#define VDC51GR_VIN_AB7 (VDC51.GR_VIN_AB7)
+#define VDC51GR_VIN_BASE (VDC51.GR_VIN_BASE)
+#define VDC51GR_VIN_MON (VDC51.GR_VIN_MON)
+#define VDC51OIR_SCL0_UPDATE (VDC51.OIR_SCL0_UPDATE)
+#define VDC51OIR_SCL0_FRC1 (VDC51.OIR_SCL0_FRC1)
+#define VDC51OIR_SCL0_FRC2 (VDC51.OIR_SCL0_FRC2)
+#define VDC51OIR_SCL0_FRC3 (VDC51.OIR_SCL0_FRC3)
+#define VDC51OIR_SCL0_FRC4 (VDC51.OIR_SCL0_FRC4)
+#define VDC51OIR_SCL0_FRC5 (VDC51.OIR_SCL0_FRC5)
+#define VDC51OIR_SCL0_FRC6 (VDC51.OIR_SCL0_FRC6)
+#define VDC51OIR_SCL0_FRC7 (VDC51.OIR_SCL0_FRC7)
+#define VDC51OIR_SCL0_DS1 (VDC51.OIR_SCL0_DS1)
+#define VDC51OIR_SCL0_DS2 (VDC51.OIR_SCL0_DS2)
+#define VDC51OIR_SCL0_DS3 (VDC51.OIR_SCL0_DS3)
+#define VDC51OIR_SCL0_DS7 (VDC51.OIR_SCL0_DS7)
+#define VDC51OIR_SCL0_US1 (VDC51.OIR_SCL0_US1)
+#define VDC51OIR_SCL0_US2 (VDC51.OIR_SCL0_US2)
+#define VDC51OIR_SCL0_US3 (VDC51.OIR_SCL0_US3)
+#define VDC51OIR_SCL0_US8 (VDC51.OIR_SCL0_US8)
+#define VDC51OIR_SCL0_OVR1 (VDC51.OIR_SCL0_OVR1)
+#define VDC51OIR_SCL1_UPDATE (VDC51.OIR_SCL1_UPDATE)
+#define VDC51OIR_SCL1_WR1 (VDC51.OIR_SCL1_WR1)
+#define VDC51OIR_SCL1_WR2 (VDC51.OIR_SCL1_WR2)
+#define VDC51OIR_SCL1_WR3 (VDC51.OIR_SCL1_WR3)
+#define VDC51OIR_SCL1_WR4 (VDC51.OIR_SCL1_WR4)
+#define VDC51OIR_SCL1_WR5 (VDC51.OIR_SCL1_WR5)
+#define VDC51OIR_SCL1_WR6 (VDC51.OIR_SCL1_WR6)
+#define VDC51OIR_SCL1_WR7 (VDC51.OIR_SCL1_WR7)
+#define VDC51GR_OIR_UPDATE (VDC51.GR_OIR_UPDATE)
+#define VDC51GR_OIR_FLM_RD (VDC51.GR_OIR_FLM_RD)
+#define VDC51GR_OIR_FLM1 (VDC51.GR_OIR_FLM1)
+#define VDC51GR_OIR_FLM2 (VDC51.GR_OIR_FLM2)
+#define VDC51GR_OIR_FLM3 (VDC51.GR_OIR_FLM3)
+#define VDC51GR_OIR_FLM4 (VDC51.GR_OIR_FLM4)
+#define VDC51GR_OIR_FLM5 (VDC51.GR_OIR_FLM5)
+#define VDC51GR_OIR_FLM6 (VDC51.GR_OIR_FLM6)
+#define VDC51GR_OIR_AB1 (VDC51.GR_OIR_AB1)
+#define VDC51GR_OIR_AB2 (VDC51.GR_OIR_AB2)
+#define VDC51GR_OIR_AB3 (VDC51.GR_OIR_AB3)
+#define VDC51GR_OIR_AB7 (VDC51.GR_OIR_AB7)
+#define VDC51GR_OIR_AB8 (VDC51.GR_OIR_AB8)
+#define VDC51GR_OIR_AB9 (VDC51.GR_OIR_AB9)
+#define VDC51GR_OIR_AB10 (VDC51.GR_OIR_AB10)
+#define VDC51GR_OIR_AB11 (VDC51.GR_OIR_AB11)
+#define VDC51GR_OIR_BASE (VDC51.GR_OIR_BASE)
+#define VDC51GR_OIR_CLUT (VDC51.GR_OIR_CLUT)
+#define VDC51GR_OIR_MON (VDC51.GR_OIR_MON)
+
+#define VDC5_IMGCNT_NR_CNT0_COUNT (2)
+#define VDC5_SC0_SCL0_FRC1_COUNT (7)
+#define VDC5_SC0_SCL0_DS1_COUNT (7)
+#define VDC5_SC0_SCL0_US1_COUNT (8)
+#define VDC5_SC0_SCL1_WR1_COUNT (4)
+#define VDC5_SC0_SCL1_PBUF0_COUNT (4)
+#define VDC5_GR0_FLM1_COUNT (6)
+#define VDC5_GR0_AB1_COUNT (3)
+#define VDC5_ADJ0_ENH_TIM1_COUNT (3)
+#define VDC5_ADJ0_ENH_SHP1_COUNT (6)
+#define VDC5_ADJ0_ENH_LTI1_COUNT (2)
+#define VDC5_GR2_FLM1_COUNT (6)
+#define VDC5_GR2_AB1_COUNT (3)
+#define VDC5_GR3_FLM1_COUNT (6)
+#define VDC5_GR3_AB1_COUNT (3)
+#define VDC5_GAM_G_LUT1_COUNT (16)
+#define VDC5_GAM_G_AREA1_COUNT (8)
+#define VDC5_GAM_B_LUT1_COUNT (16)
+#define VDC5_GAM_B_AREA1_COUNT (8)
+#define VDC5_GAM_R_LUT1_COUNT (16)
+#define VDC5_GAM_R_AREA1_COUNT (8)
+#define VDC5_TCON_TIM_STVA1_COUNT (2)
+#define VDC5_TCON_TIM_STVB1_COUNT (2)
+#define VDC5_TCON_TIM_STH1_COUNT (2)
+#define VDC5_TCON_TIM_STB1_COUNT (2)
+#define VDC5_TCON_TIM_CPV1_COUNT (2)
+#define VDC5_TCON_TIM_POLA1_COUNT (2)
+#define VDC5_TCON_TIM_POLB1_COUNT (2)
+#define VDC5_OUT_BRIGHT1_COUNT (2)
+#define VDC5_SYSCNT_INT1_COUNT (6)
+#define VDC5_SC1_SCL0_FRC1_COUNT (7)
+#define VDC5_SC1_SC1_SCL0_DS1_COUNT (7)
+#define VDC5_SC1_SC1_SCL0_US1_COUNT (8)
+#define VDC5_SC1_SCL1_WR1_COUNT (4)
+#define VDC5_SC1_SCL1_PBUF0_COUNT (4)
+#define VDC5_GR1_FLM1_COUNT (6)
+#define VDC5_GR1_AB1_COUNT (3)
+#define VDC5_ADJ1_ENH_TIM1_COUNT (3)
+#define VDC5_ADJ1_ENH_SHP1_COUNT (6)
+#define VDC5_ADJ1_ENH_LTI1_COUNT (2)
+#define VDC5_GR_VIN_AB1_COUNT (7)
+#define VDC5_OIR_SCL0_FRC1_COUNT (7)
+#define VDC5_OIR_SCL0_DS1_COUNT (3)
+#define VDC5_OIR_SCL1_WR1_COUNT (4)
+#define VDC5_GR_OIR_FLM1_COUNT (6)
+#define VDC5_GR_OIR_AB1_COUNT (3)
+
+
+typedef struct st_vdc5
+{
+                                                           /* VDC5             */
     volatile uint32_t  INP_UPDATE;                             /*  INP_UPDATE      */
     volatile uint32_t  INP_SEL_CNT;                            /*  INP_SEL_CNT     */
     volatile uint32_t  INP_EXT_SYNC_CNT;                       /*  INP_EXT_SYNC_CNT */
@@ -40,7 +1023,8 @@
     volatile uint32_t  INP_DLY_ADJ;                            /*  INP_DLY_ADJ     */
     volatile uint8_t   dummy1[108];                            /*                  */
     volatile uint32_t  IMGCNT_UPDATE;                          /*  IMGCNT_UPDATE   */
-#define VDC5_IMGCNT_NR_CNT0_COUNT 2
+
+/* #define VDC5_IMGCNT_NR_CNT0_COUNT (2) */
     volatile uint32_t  IMGCNT_NR_CNT0;                         /*  IMGCNT_NR_CNT0  */
     volatile uint32_t  IMGCNT_NR_CNT1;                         /*  IMGCNT_NR_CNT1  */
     volatile uint8_t   dummy2[20];                             /*                  */
@@ -54,9 +1038,11 @@
     volatile uint8_t   dummy3[4];                              /*                  */
     volatile uint32_t  IMGCNT_DRC_REG;                         /*  IMGCNT_DRC_REG  */
     volatile uint8_t   dummy4[60];                             /*                  */
+
 /* start of struct st_vdc5_from_sc0_scl0_update */
     volatile uint32_t  SC0_SCL0_UPDATE;                        /*  SC0_SCL0_UPDATE */
-#define VDC5_SC0_SCL0_FRC1_COUNT 7
+
+/* #define VDC5_SC0_SCL0_FRC1_COUNT (7) */
     volatile uint32_t  SC0_SCL0_FRC1;                          /*  SC0_SCL0_FRC1   */
     volatile uint32_t  SC0_SCL0_FRC2;                          /*  SC0_SCL0_FRC2   */
     volatile uint32_t  SC0_SCL0_FRC3;                          /*  SC0_SCL0_FRC3   */
@@ -68,7 +1054,8 @@
     volatile uint32_t  SC0_SCL0_FRC9;                          /*  SC0_SCL0_FRC9   */
     volatile uint16_t SC0_SCL0_MON0;                          /*  SC0_SCL0_MON0   */
     volatile uint16_t SC0_SCL0_INT;                           /*  SC0_SCL0_INT    */
-#define VDC5_SC0_SCL0_DS1_COUNT 7
+
+/* #define VDC5_SC0_SCL0_DS1_COUNT (7) */
     volatile uint32_t  SC0_SCL0_DS1;                           /*  SC0_SCL0_DS1    */
     volatile uint32_t  SC0_SCL0_DS2;                           /*  SC0_SCL0_DS2    */
     volatile uint32_t  SC0_SCL0_DS3;                           /*  SC0_SCL0_DS3    */
@@ -76,7 +1063,8 @@
     volatile uint32_t  SC0_SCL0_DS5;                           /*  SC0_SCL0_DS5    */
     volatile uint32_t  SC0_SCL0_DS6;                           /*  SC0_SCL0_DS6    */
     volatile uint32_t  SC0_SCL0_DS7;                           /*  SC0_SCL0_DS7    */
-#define VDC5_SC0_SCL0_US1_COUNT 8
+
+/* #define VDC5_SC0_SCL0_US1_COUNT (8) */
     volatile uint32_t  SC0_SCL0_US1;                           /*  SC0_SCL0_US1    */
     volatile uint32_t  SC0_SCL0_US2;                           /*  SC0_SCL0_US2    */
     volatile uint32_t  SC0_SCL0_US3;                           /*  SC0_SCL0_US3    */
@@ -90,7 +1078,8 @@
     volatile uint8_t   dummy7[16];                             /*                  */
     volatile uint32_t  SC0_SCL1_UPDATE;                        /*  SC0_SCL1_UPDATE */
     volatile uint8_t   dummy8[4];                              /*                  */
-#define VDC5_SC0_SCL1_WR1_COUNT 4
+
+/* #define VDC5_SC0_SCL1_WR1_COUNT (4) */
     volatile uint32_t  SC0_SCL1_WR1;                           /*  SC0_SCL1_WR1    */
     volatile uint32_t  SC0_SCL1_WR2;                           /*  SC0_SCL1_WR2    */
     volatile uint32_t  SC0_SCL1_WR3;                           /*  SC0_SCL1_WR3    */
@@ -102,35 +1091,44 @@
     volatile uint32_t  SC0_SCL1_WR8;                           /*  SC0_SCL1_WR8    */
     volatile uint32_t  SC0_SCL1_WR9;                           /*  SC0_SCL1_WR9    */
     volatile uint32_t  SC0_SCL1_WR10;                          /*  SC0_SCL1_WR10   */
+
 /* end of struct st_vdc5_from_sc0_scl0_update */
     volatile uint32_t  SC0_SCL1_WR11;                          /*  SC0_SCL1_WR11   */
     volatile uint32_t  SC0_SCL1_MON1;                          /*  SC0_SCL1_MON1   */
+
 /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
-#define VDC5_SC0_SCL1_PBUF0_COUNT 4
+
+/* #define VDC5_SC0_SCL1_PBUF0_COUNT (4) */
     volatile uint32_t  SC0_SCL1_PBUF0;                         /*  SC0_SCL1_PBUF0  */
     volatile uint32_t  SC0_SCL1_PBUF1;                         /*  SC0_SCL1_PBUF1  */
     volatile uint32_t  SC0_SCL1_PBUF2;                         /*  SC0_SCL1_PBUF2  */
     volatile uint32_t  SC0_SCL1_PBUF3;                         /*  SC0_SCL1_PBUF3  */
     volatile uint32_t  SC0_SCL1_PBUF_FLD;                      /*  SC0_SCL1_PBUF_FLD */
     volatile uint32_t  SC0_SCL1_PBUF_CNT;                      /*  SC0_SCL1_PBUF_CNT */
+
 /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
     volatile uint8_t   dummy10[44];                            /*                  */
+
 /* start of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR0_UPDATE;                             /*  GR0_UPDATE      */
     volatile uint32_t  GR0_FLM_RD;                             /*  GR0_FLM_RD      */
-#define VDC5_GR0_FLM1_COUNT 6
+
+/* #define VDC5_GR0_FLM1_COUNT (6) */
     volatile uint32_t  GR0_FLM1;                               /*  GR0_FLM1        */
     volatile uint32_t  GR0_FLM2;                               /*  GR0_FLM2        */
     volatile uint32_t  GR0_FLM3;                               /*  GR0_FLM3        */
     volatile uint32_t  GR0_FLM4;                               /*  GR0_FLM4        */
     volatile uint32_t  GR0_FLM5;                               /*  GR0_FLM5        */
     volatile uint32_t  GR0_FLM6;                               /*  GR0_FLM6        */
-#define VDC5_GR0_AB1_COUNT 3
+
+/* #define VDC5_GR0_AB1_COUNT (3) */
     volatile uint32_t  GR0_AB1;                                /*  GR0_AB1         */
     volatile uint32_t  GR0_AB2;                                /*  GR0_AB2         */
     volatile uint32_t  GR0_AB3;                                /*  GR0_AB3         */
+
 /* end of struct st_vdc5_from_gr0_update */
     volatile uint8_t   dummy11[12];                            /*                  */
+
 /* start of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR0_AB7;                                /*  GR0_AB7         */
     volatile uint32_t  GR0_AB8;                                /*  GR0_AB8         */
@@ -138,24 +1136,29 @@
     volatile uint32_t  GR0_AB10;                               /*  GR0_AB10        */
     volatile uint32_t  GR0_AB11;                               /*  GR0_AB11        */
     volatile uint32_t  GR0_BASE;                               /*  GR0_BASE        */
+
 /* end of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR0_CLUT;                               /*  GR0_CLUT        */
     volatile uint8_t   dummy12[44];                            /*                  */
+
 /* start of struct st_vdc5_from_adj0_update */
     volatile uint32_t  ADJ0_UPDATE;                            /*  ADJ0_UPDATE     */
     volatile uint32_t  ADJ0_BKSTR_SET;                         /*  ADJ0_BKSTR_SET  */
-#define VDC5_ADJ0_ENH_TIM1_COUNT 3
+
+/* #define VDC5_ADJ0_ENH_TIM1_COUNT (3) */
     volatile uint32_t  ADJ0_ENH_TIM1;                          /*  ADJ0_ENH_TIM1   */
     volatile uint32_t  ADJ0_ENH_TIM2;                          /*  ADJ0_ENH_TIM2   */
     volatile uint32_t  ADJ0_ENH_TIM3;                          /*  ADJ0_ENH_TIM3   */
-#define VDC5_ADJ0_ENH_SHP1_COUNT 6
+
+/* #define VDC5_ADJ0_ENH_SHP1_COUNT (6) */
     volatile uint32_t  ADJ0_ENH_SHP1;                          /*  ADJ0_ENH_SHP1   */
     volatile uint32_t  ADJ0_ENH_SHP2;                          /*  ADJ0_ENH_SHP2   */
     volatile uint32_t  ADJ0_ENH_SHP3;                          /*  ADJ0_ENH_SHP3   */
     volatile uint32_t  ADJ0_ENH_SHP4;                          /*  ADJ0_ENH_SHP4   */
     volatile uint32_t  ADJ0_ENH_SHP5;                          /*  ADJ0_ENH_SHP5   */
     volatile uint32_t  ADJ0_ENH_SHP6;                          /*  ADJ0_ENH_SHP6   */
-#define VDC5_ADJ0_ENH_LTI1_COUNT 2
+
+/* #define VDC5_ADJ0_ENH_LTI1_COUNT (2) */
     volatile uint32_t  ADJ0_ENH_LTI1;                          /*  ADJ0_ENH_LTI1   */
     volatile uint32_t  ADJ0_ENH_LTI2;                          /*  ADJ0_ENH_LTI2   */
     volatile uint32_t  ADJ0_MTX_MODE;                          /*  ADJ0_MTX_MODE   */
@@ -165,26 +1168,32 @@
     volatile uint32_t  ADJ0_MTX_CBB_ADJ1;                      /*  ADJ0_MTX_CBB_ADJ1 */
     volatile uint32_t  ADJ0_MTX_CRR_ADJ0;                      /*  ADJ0_MTX_CRR_ADJ0 */
     volatile uint32_t  ADJ0_MTX_CRR_ADJ1;                      /*  ADJ0_MTX_CRR_ADJ1 */
+
 /* end of struct st_vdc5_from_adj0_update */
     volatile uint8_t   dummy13[48];                            /*                  */
+
 /* start of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR2_UPDATE;                             /*  GR2_UPDATE      */
     volatile uint32_t  GR2_FLM_RD;                             /*  GR2_FLM_RD      */
-#define VDC5_GR2_FLM1_COUNT 6
+
+/* #define VDC5_GR2_FLM1_COUNT (6) */
     volatile uint32_t  GR2_FLM1;                               /*  GR2_FLM1        */
     volatile uint32_t  GR2_FLM2;                               /*  GR2_FLM2        */
     volatile uint32_t  GR2_FLM3;                               /*  GR2_FLM3        */
     volatile uint32_t  GR2_FLM4;                               /*  GR2_FLM4        */
     volatile uint32_t  GR2_FLM5;                               /*  GR2_FLM5        */
     volatile uint32_t  GR2_FLM6;                               /*  GR2_FLM6        */
-#define VDC5_GR2_AB1_COUNT 3
+
+/* #define VDC5_GR2_AB1_COUNT (3) */
     volatile uint32_t  GR2_AB1;                                /*  GR2_AB1         */
     volatile uint32_t  GR2_AB2;                                /*  GR2_AB2         */
     volatile uint32_t  GR2_AB3;                                /*  GR2_AB3         */
+
 /* end of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR2_AB4;                                /*  GR2_AB4         */
     volatile uint32_t  GR2_AB5;                                /*  GR2_AB5         */
     volatile uint32_t  GR2_AB6;                                /*  GR2_AB6         */
+
 /* start of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR2_AB7;                                /*  GR2_AB7         */
     volatile uint32_t  GR2_AB8;                                /*  GR2_AB8         */
@@ -192,28 +1201,34 @@
     volatile uint32_t  GR2_AB10;                               /*  GR2_AB10        */
     volatile uint32_t  GR2_AB11;                               /*  GR2_AB11        */
     volatile uint32_t  GR2_BASE;                               /*  GR2_BASE        */
+
 /* end of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR2_CLUT;                               /*  GR2_CLUT        */
     volatile uint32_t  GR2_MON;                                /*  GR2_MON         */
     volatile uint8_t   dummy14[40];                            /*                  */
+
 /* start of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR3_UPDATE;                             /*  GR3_UPDATE      */
     volatile uint32_t  GR3_FLM_RD;                             /*  GR3_FLM_RD      */
-#define VDC5_GR3_FLM1_COUNT 6
+
+/* #define VDC5_GR3_FLM1_COUNT (6) */
     volatile uint32_t  GR3_FLM1;                               /*  GR3_FLM1        */
     volatile uint32_t  GR3_FLM2;                               /*  GR3_FLM2        */
     volatile uint32_t  GR3_FLM3;                               /*  GR3_FLM3        */
     volatile uint32_t  GR3_FLM4;                               /*  GR3_FLM4        */
     volatile uint32_t  GR3_FLM5;                               /*  GR3_FLM5        */
     volatile uint32_t  GR3_FLM6;                               /*  GR3_FLM6        */
-#define VDC5_GR3_AB1_COUNT 3
+
+/* #define VDC5_GR3_AB1_COUNT (3) */
     volatile uint32_t  GR3_AB1;                                /*  GR3_AB1         */
     volatile uint32_t  GR3_AB2;                                /*  GR3_AB2         */
     volatile uint32_t  GR3_AB3;                                /*  GR3_AB3         */
+
 /* end of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR3_AB4;                                /*  GR3_AB4         */
     volatile uint32_t  GR3_AB5;                                /*  GR3_AB5         */
     volatile uint32_t  GR3_AB6;                                /*  GR3_AB6         */
+
 /* start of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR3_AB7;                                /*  GR3_AB7         */
     volatile uint32_t  GR3_AB8;                                /*  GR3_AB8         */
@@ -221,13 +1236,15 @@
     volatile uint32_t  GR3_AB10;                               /*  GR3_AB10        */
     volatile uint32_t  GR3_AB11;                               /*  GR3_AB11        */
     volatile uint32_t  GR3_BASE;                               /*  GR3_BASE        */
+
 /* end of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR3_CLUT_INT;                           /*  GR3_CLUT_INT    */
     volatile uint32_t  GR3_MON;                                /*  GR3_MON         */
     volatile uint8_t   dummy15[40];                            /*                  */
     volatile uint32_t  GAM_G_UPDATE;                           /*  GAM_G_UPDATE    */
     volatile uint32_t  GAM_SW;                                 /*  GAM_SW          */
-#define VDC5_GAM_G_LUT1_COUNT 16
+
+/* #define VDC5_GAM_G_LUT1_COUNT (16) */
     volatile uint32_t  GAM_G_LUT1;                             /*  GAM_G_LUT1      */
     volatile uint32_t  GAM_G_LUT2;                             /*  GAM_G_LUT2      */
     volatile uint32_t  GAM_G_LUT3;                             /*  GAM_G_LUT3      */
@@ -244,7 +1261,8 @@
     volatile uint32_t  GAM_G_LUT14;                            /*  GAM_G_LUT14     */
     volatile uint32_t  GAM_G_LUT15;                            /*  GAM_G_LUT15     */
     volatile uint32_t  GAM_G_LUT16;                            /*  GAM_G_LUT16     */
-#define VDC5_GAM_G_AREA1_COUNT 8
+
+/* #define VDC5_GAM_G_AREA1_COUNT (8) */
     volatile uint32_t  GAM_G_AREA1;                            /*  GAM_G_AREA1     */
     volatile uint32_t  GAM_G_AREA2;                            /*  GAM_G_AREA2     */
     volatile uint32_t  GAM_G_AREA3;                            /*  GAM_G_AREA3     */
@@ -256,7 +1274,8 @@
     volatile uint8_t   dummy16[24];                            /*                  */
     volatile uint32_t  GAM_B_UPDATE;                           /*  GAM_B_UPDATE    */
     volatile uint8_t   dummy17[4];                             /*                  */
-#define VDC5_GAM_B_LUT1_COUNT 16
+
+/* #define VDC5_GAM_B_LUT1_COUNT (16) */
     volatile uint32_t  GAM_B_LUT1;                             /*  GAM_B_LUT1      */
     volatile uint32_t  GAM_B_LUT2;                             /*  GAM_B_LUT2      */
     volatile uint32_t  GAM_B_LUT3;                             /*  GAM_B_LUT3      */
@@ -273,7 +1292,8 @@
     volatile uint32_t  GAM_B_LUT14;                            /*  GAM_B_LUT14     */
     volatile uint32_t  GAM_B_LUT15;                            /*  GAM_B_LUT15     */
     volatile uint32_t  GAM_B_LUT16;                            /*  GAM_B_LUT16     */
-#define VDC5_GAM_B_AREA1_COUNT 8
+
+/* #define VDC5_GAM_B_AREA1_COUNT (8) */
     volatile uint32_t  GAM_B_AREA1;                            /*  GAM_B_AREA1     */
     volatile uint32_t  GAM_B_AREA2;                            /*  GAM_B_AREA2     */
     volatile uint32_t  GAM_B_AREA3;                            /*  GAM_B_AREA3     */
@@ -285,7 +1305,8 @@
     volatile uint8_t   dummy18[24];                            /*                  */
     volatile uint32_t  GAM_R_UPDATE;                           /*  GAM_R_UPDATE    */
     volatile uint8_t   dummy19[4];                             /*                  */
-#define VDC5_GAM_R_LUT1_COUNT 16
+
+/* #define VDC5_GAM_R_LUT1_COUNT (16) */
     volatile uint32_t  GAM_R_LUT1;                             /*  GAM_R_LUT1      */
     volatile uint32_t  GAM_R_LUT2;                             /*  GAM_R_LUT2      */
     volatile uint32_t  GAM_R_LUT3;                             /*  GAM_R_LUT3      */
@@ -302,7 +1323,8 @@
     volatile uint32_t  GAM_R_LUT14;                            /*  GAM_R_LUT14     */
     volatile uint32_t  GAM_R_LUT15;                            /*  GAM_R_LUT15     */
     volatile uint32_t  GAM_R_LUT16;                            /*  GAM_R_LUT16     */
-#define VDC5_GAM_R_AREA1_COUNT 8
+
+/* #define VDC5_GAM_R_AREA1_COUNT (8) */
     volatile uint32_t  GAM_R_AREA1;                            /*  GAM_R_AREA1     */
     volatile uint32_t  GAM_R_AREA2;                            /*  GAM_R_AREA2     */
     volatile uint32_t  GAM_R_AREA3;                            /*  GAM_R_AREA3     */
@@ -314,32 +1336,40 @@
     volatile uint8_t   dummy20[24];                            /*                  */
     volatile uint32_t  TCON_UPDATE;                            /*  TCON_UPDATE     */
     volatile uint32_t  TCON_TIM;                               /*  TCON_TIM        */
-#define VDC5_TCON_TIM_STVA1_COUNT 2
+
+/* #define VDC5_TCON_TIM_STVA1_COUNT (2) */
     volatile uint32_t  TCON_TIM_STVA1;                         /*  TCON_TIM_STVA1  */
     volatile uint32_t  TCON_TIM_STVA2;                         /*  TCON_TIM_STVA2  */
-#define VDC5_TCON_TIM_STVB1_COUNT 2
+
+/* #define VDC5_TCON_TIM_STVB1_COUNT (2) */
     volatile uint32_t  TCON_TIM_STVB1;                         /*  TCON_TIM_STVB1  */
     volatile uint32_t  TCON_TIM_STVB2;                         /*  TCON_TIM_STVB2  */
-#define VDC5_TCON_TIM_STH1_COUNT 2
+
+/* #define VDC5_TCON_TIM_STH1_COUNT (2) */
     volatile uint32_t  TCON_TIM_STH1;                          /*  TCON_TIM_STH1   */
     volatile uint32_t  TCON_TIM_STH2;                          /*  TCON_TIM_STH2   */
-#define VDC5_TCON_TIM_STB1_COUNT 2
+
+/* #define VDC5_TCON_TIM_STB1_COUNT (2) */
     volatile uint32_t  TCON_TIM_STB1;                          /*  TCON_TIM_STB1   */
     volatile uint32_t  TCON_TIM_STB2;                          /*  TCON_TIM_STB2   */
-#define VDC5_TCON_TIM_CPV1_COUNT 2
+
+/* #define VDC5_TCON_TIM_CPV1_COUNT (2) */
     volatile uint32_t  TCON_TIM_CPV1;                          /*  TCON_TIM_CPV1   */
     volatile uint32_t  TCON_TIM_CPV2;                          /*  TCON_TIM_CPV2   */
-#define VDC5_TCON_TIM_POLA1_COUNT 2
+
+/* #define VDC5_TCON_TIM_POLA1_COUNT (2) */
     volatile uint32_t  TCON_TIM_POLA1;                         /*  TCON_TIM_POLA1  */
     volatile uint32_t  TCON_TIM_POLA2;                         /*  TCON_TIM_POLA2  */
-#define VDC5_TCON_TIM_POLB1_COUNT 2
+
+/* #define VDC5_TCON_TIM_POLB1_COUNT (2) */
     volatile uint32_t  TCON_TIM_POLB1;                         /*  TCON_TIM_POLB1  */
     volatile uint32_t  TCON_TIM_POLB2;                         /*  TCON_TIM_POLB2  */
     volatile uint32_t  TCON_TIM_DE;                            /*  TCON_TIM_DE     */
     volatile uint8_t   dummy21[60];                            /*                  */
     volatile uint32_t  OUT_UPDATE;                             /*  OUT_UPDATE      */
     volatile uint32_t  OUT_SET;                                /*  OUT_SET         */
-#define VDC5_OUT_BRIGHT1_COUNT 2
+
+/* #define VDC5_OUT_BRIGHT1_COUNT (2) */
     volatile uint32_t  OUT_BRIGHT1;                            /*  OUT_BRIGHT1     */
     volatile uint32_t  OUT_BRIGHT2;                            /*  OUT_BRIGHT2     */
     volatile uint32_t  OUT_CONTRAST;                           /*  OUT_CONTRAST    */
@@ -347,7 +1377,8 @@
     volatile uint8_t   dummy22[12];                            /*                  */
     volatile uint32_t  OUT_CLK_PHASE;                          /*  OUT_CLK_PHASE   */
     volatile uint8_t   dummy23[88];                            /*                  */
-#define VDC5_SYSCNT_INT1_COUNT 6
+
+/* #define VDC5_SYSCNT_INT1_COUNT (6) */
     volatile uint32_t  SYSCNT_INT1;                            /*  SYSCNT_INT1     */
     volatile uint32_t  SYSCNT_INT2;                            /*  SYSCNT_INT2     */
     volatile uint32_t  SYSCNT_INT3;                            /*  SYSCNT_INT3     */
@@ -357,9 +1388,11 @@
     volatile uint16_t SYSCNT_PANEL_CLK;                       /*  SYSCNT_PANEL_CLK */
     volatile uint16_t SYSCNT_CLUT;                            /*  SYSCNT_CLUT     */
     volatile uint8_t   dummy24[356];                           /*                  */
+
 /* start of struct st_vdc5_from_sc0_scl0_update */
     volatile uint32_t  SC1_SCL0_UPDATE;                        /*  SC1_SCL0_UPDATE */
-#define VDC5_SC1_SCL0_FRC1_COUNT 7
+
+/* #define VDC5_SC1_SCL0_FRC1_COUNT (7) */
     volatile uint32_t  SC1_SCL0_FRC1;                          /*  SC1_SCL0_FRC1   */
     volatile uint32_t  SC1_SCL0_FRC2;                          /*  SC1_SCL0_FRC2   */
     volatile uint32_t  SC1_SCL0_FRC3;                          /*  SC1_SCL0_FRC3   */
@@ -371,7 +1404,8 @@
     volatile uint32_t  SC1_SCL0_FRC9;                          /*  SC1_SCL0_FRC9   */
     volatile uint16_t SC1_SCL0_MON0;                          /*  SC1_SCL0_MON0   */
     volatile uint16_t SC1_SCL0_INT;                           /*  SC1_SCL0_INT    */
-#define VDC5_SC1_SC1_SCL0_DS1_COUNT 7
+
+/* #define VDC5_SC1_SC1_SCL0_DS1_COUNT (7) */
     volatile uint32_t  SC1_SCL0_DS1;                           /*  SC1_SCL0_DS1    */
     volatile uint32_t  SC1_SCL0_DS2;                           /*  SC1_SCL0_DS2    */
     volatile uint32_t  SC1_SCL0_DS3;                           /*  SC1_SCL0_DS3    */
@@ -379,7 +1413,8 @@
     volatile uint32_t  SC1_SCL0_DS5;                           /*  SC1_SCL0_DS5    */
     volatile uint32_t  SC1_SCL0_DS6;                           /*  SC1_SCL0_DS6    */
     volatile uint32_t  SC1_SCL0_DS7;                           /*  SC1_SCL0_DS7    */
-#define VDC5_SC1_SC1_SCL0_US1_COUNT 8
+
+/* #define VDC5_SC1_SC1_SCL0_US1_COUNT (8) */
     volatile uint32_t  SC1_SCL0_US1;                           /*  SC1_SCL0_US1    */
     volatile uint32_t  SC1_SCL0_US2;                           /*  SC1_SCL0_US2    */
     volatile uint32_t  SC1_SCL0_US3;                           /*  SC1_SCL0_US3    */
@@ -393,7 +1428,8 @@
     volatile uint8_t   dummy27[16];                            /*                  */
     volatile uint32_t  SC1_SCL1_UPDATE;                        /*  SC1_SCL1_UPDATE */
     volatile uint8_t   dummy28[4];                             /*                  */
-#define VDC5_SC1_SCL1_WR1_COUNT 4
+
+/* #define VDC5_SC1_SCL1_WR1_COUNT (4) */
     volatile uint32_t  SC1_SCL1_WR1;                           /*  SC1_SCL1_WR1    */
     volatile uint32_t  SC1_SCL1_WR2;                           /*  SC1_SCL1_WR2    */
     volatile uint32_t  SC1_SCL1_WR3;                           /*  SC1_SCL1_WR3    */
@@ -405,37 +1441,46 @@
     volatile uint32_t  SC1_SCL1_WR8;                           /*  SC1_SCL1_WR8    */
     volatile uint32_t  SC1_SCL1_WR9;                           /*  SC1_SCL1_WR9    */
     volatile uint32_t  SC1_SCL1_WR10;                          /*  SC1_SCL1_WR10   */
+
 /* end of struct st_vdc5_from_sc0_scl0_update */
     volatile uint32_t  SC1_SCL1_WR11;                          /*  SC1_SCL1_WR11   */
     volatile uint32_t  SC1_SCL1_MON1;                          /*  SC1_SCL1_MON1   */
+
 /* start of struct st_vdc5_from_sc0_scl1_pbuf0 */
-#define VDC5_SC1_SCL1_PBUF0_COUNT 4
+
+/* #define VDC5_SC1_SCL1_PBUF0_COUNT (4) */
     volatile uint32_t  SC1_SCL1_PBUF0;                         /*  SC1_SCL1_PBUF0  */
     volatile uint32_t  SC1_SCL1_PBUF1;                         /*  SC1_SCL1_PBUF1  */
     volatile uint32_t  SC1_SCL1_PBUF2;                         /*  SC1_SCL1_PBUF2  */
     volatile uint32_t  SC1_SCL1_PBUF3;                         /*  SC1_SCL1_PBUF3  */
     volatile uint32_t  SC1_SCL1_PBUF_FLD;                      /*  SC1_SCL1_PBUF_FLD */
     volatile uint32_t  SC1_SCL1_PBUF_CNT;                      /*  SC1_SCL1_PBUF_CNT */
+
 /* end of struct st_vdc5_from_sc0_scl1_pbuf0 */
     volatile uint8_t   dummy30[44];                            /*                  */
+
 /* start of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR1_UPDATE;                             /*  GR1_UPDATE      */
     volatile uint32_t  GR1_FLM_RD;                             /*  GR1_FLM_RD      */
-#define VDC5_GR1_FLM1_COUNT 6
+
+/* #define VDC5_GR1_FLM1_COUNT (6) */
     volatile uint32_t  GR1_FLM1;                               /*  GR1_FLM1        */
     volatile uint32_t  GR1_FLM2;                               /*  GR1_FLM2        */
     volatile uint32_t  GR1_FLM3;                               /*  GR1_FLM3        */
     volatile uint32_t  GR1_FLM4;                               /*  GR1_FLM4        */
     volatile uint32_t  GR1_FLM5;                               /*  GR1_FLM5        */
     volatile uint32_t  GR1_FLM6;                               /*  GR1_FLM6        */
-#define VDC5_GR1_AB1_COUNT 3
+
+/* #define VDC5_GR1_AB1_COUNT (3) */
     volatile uint32_t  GR1_AB1;                                /*  GR1_AB1         */
     volatile uint32_t  GR1_AB2;                                /*  GR1_AB2         */
     volatile uint32_t  GR1_AB3;                                /*  GR1_AB3         */
+
 /* end of struct st_vdc5_from_gr0_update */
     volatile uint32_t  GR1_AB4;                                /*  GR1_AB4         */
     volatile uint32_t  GR1_AB5;                                /*  GR1_AB5         */
     volatile uint32_t  GR1_AB6;                                /*  GR1_AB6         */
+
 /* start of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR1_AB7;                                /*  GR1_AB7         */
     volatile uint32_t  GR1_AB8;                                /*  GR1_AB8         */
@@ -443,25 +1488,30 @@
     volatile uint32_t  GR1_AB10;                               /*  GR1_AB10        */
     volatile uint32_t  GR1_AB11;                               /*  GR1_AB11        */
     volatile uint32_t  GR1_BASE;                               /*  GR1_BASE        */
+
 /* end of struct st_vdc5_from_gr0_ab7 */
     volatile uint32_t  GR1_CLUT;                               /*  GR1_CLUT        */
     volatile uint32_t  GR1_MON;                                /*  GR1_MON         */
     volatile uint8_t   dummy31[40];                            /*                  */
+
 /* start of struct st_vdc5_from_adj0_update */
     volatile uint32_t  ADJ1_UPDATE;                            /*  ADJ1_UPDATE     */
     volatile uint32_t  ADJ1_BKSTR_SET;                         /*  ADJ1_BKSTR_SET  */
-#define VDC5_ADJ1_ENH_TIM1_COUNT 3
+
+/* #define VDC5_ADJ1_ENH_TIM1_COUNT (3) */
     volatile uint32_t  ADJ1_ENH_TIM1;                          /*  ADJ1_ENH_TIM1   */
     volatile uint32_t  ADJ1_ENH_TIM2;                          /*  ADJ1_ENH_TIM2   */
     volatile uint32_t  ADJ1_ENH_TIM3;                          /*  ADJ1_ENH_TIM3   */
-#define VDC5_ADJ1_ENH_SHP1_COUNT 6
+
+/* #define VDC5_ADJ1_ENH_SHP1_COUNT (6) */
     volatile uint32_t  ADJ1_ENH_SHP1;                          /*  ADJ1_ENH_SHP1   */
     volatile uint32_t  ADJ1_ENH_SHP2;                          /*  ADJ1_ENH_SHP2   */
     volatile uint32_t  ADJ1_ENH_SHP3;                          /*  ADJ1_ENH_SHP3   */
     volatile uint32_t  ADJ1_ENH_SHP4;                          /*  ADJ1_ENH_SHP4   */
     volatile uint32_t  ADJ1_ENH_SHP5;                          /*  ADJ1_ENH_SHP5   */
     volatile uint32_t  ADJ1_ENH_SHP6;                          /*  ADJ1_ENH_SHP6   */
-#define VDC5_ADJ1_ENH_LTI1_COUNT 2
+
+/* #define VDC5_ADJ1_ENH_LTI1_COUNT (2) */
     volatile uint32_t  ADJ1_ENH_LTI1;                          /*  ADJ1_ENH_LTI1   */
     volatile uint32_t  ADJ1_ENH_LTI2;                          /*  ADJ1_ENH_LTI2   */
     volatile uint32_t  ADJ1_MTX_MODE;                          /*  ADJ1_MTX_MODE   */
@@ -471,11 +1521,13 @@
     volatile uint32_t  ADJ1_MTX_CBB_ADJ1;                      /*  ADJ1_MTX_CBB_ADJ1 */
     volatile uint32_t  ADJ1_MTX_CRR_ADJ0;                      /*  ADJ1_MTX_CRR_ADJ0 */
     volatile uint32_t  ADJ1_MTX_CRR_ADJ1;                      /*  ADJ1_MTX_CRR_ADJ1 */
+
 /* end of struct st_vdc5_from_adj0_update */
     volatile uint8_t   dummy32[48];                            /*                  */
     volatile uint32_t  GR_VIN_UPDATE;                          /*  GR_VIN_UPDATE   */
     volatile uint8_t   dummy33[28];                            /*                  */
-#define VDC5_GR_VIN_AB1_COUNT 7
+
+/* #define VDC5_GR_VIN_AB1_COUNT (7) */
     volatile uint32_t  GR_VIN_AB1;                             /*  GR_VIN_AB1      */
     volatile uint32_t  GR_VIN_AB2;                             /*  GR_VIN_AB2      */
     volatile uint32_t  GR_VIN_AB3;                             /*  GR_VIN_AB3      */
@@ -489,7 +1541,8 @@
     volatile uint32_t  GR_VIN_MON;                             /*  GR_VIN_MON      */
     volatile uint8_t   dummy36[40];                            /*                  */
     volatile uint32_t  OIR_SCL0_UPDATE;                        /*  OIR_SCL0_UPDATE */
-#define VDC5_OIR_SCL0_FRC1_COUNT 7
+
+/* #define VDC5_OIR_SCL0_FRC1_COUNT (7) */
     volatile uint32_t  OIR_SCL0_FRC1;                          /*  OIR_SCL0_FRC1   */
     volatile uint32_t  OIR_SCL0_FRC2;                          /*  OIR_SCL0_FRC2   */
     volatile uint32_t  OIR_SCL0_FRC3;                          /*  OIR_SCL0_FRC3   */
@@ -498,7 +1551,8 @@
     volatile uint32_t  OIR_SCL0_FRC6;                          /*  OIR_SCL0_FRC6   */
     volatile uint32_t  OIR_SCL0_FRC7;                          /*  OIR_SCL0_FRC7   */
     volatile uint8_t   dummy37[12];                            /*                  */
-#define VDC5_OIR_SCL0_DS1_COUNT 3
+
+/* #define VDC5_OIR_SCL0_DS1_COUNT (3) */
     volatile uint32_t  OIR_SCL0_DS1;                           /*  OIR_SCL0_DS1    */
     volatile uint32_t  OIR_SCL0_DS2;                           /*  OIR_SCL0_DS2    */
     volatile uint32_t  OIR_SCL0_DS3;                           /*  OIR_SCL0_DS3    */
@@ -514,7 +1568,8 @@
     volatile uint8_t   dummy41[16];                            /*                  */
     volatile uint32_t  OIR_SCL1_UPDATE;                        /*  OIR_SCL1_UPDATE */
     volatile uint8_t   dummy42[4];                             /*                  */
-#define VDC5_OIR_SCL1_WR1_COUNT 4
+
+/* #define VDC5_OIR_SCL1_WR1_COUNT (4) */
     volatile uint32_t  OIR_SCL1_WR1;                           /*  OIR_SCL1_WR1    */
     volatile uint32_t  OIR_SCL1_WR2;                           /*  OIR_SCL1_WR2    */
     volatile uint32_t  OIR_SCL1_WR3;                           /*  OIR_SCL1_WR3    */
@@ -526,14 +1581,16 @@
     volatile uint8_t   dummy44[88];                            /*                  */
     volatile uint32_t  GR_OIR_UPDATE;                          /*  GR_OIR_UPDATE   */
     volatile uint32_t  GR_OIR_FLM_RD;                          /*  GR_OIR_FLM_RD   */
-#define VDC5_GR_OIR_FLM1_COUNT 6
+
+/* #define VDC5_GR_OIR_FLM1_COUNT (6) */
     volatile uint32_t  GR_OIR_FLM1;                            /*  GR_OIR_FLM1     */
     volatile uint32_t  GR_OIR_FLM2;                            /*  GR_OIR_FLM2     */
     volatile uint32_t  GR_OIR_FLM3;                            /*  GR_OIR_FLM3     */
     volatile uint32_t  GR_OIR_FLM4;                            /*  GR_OIR_FLM4     */
     volatile uint32_t  GR_OIR_FLM5;                            /*  GR_OIR_FLM5     */
     volatile uint32_t  GR_OIR_FLM6;                            /*  GR_OIR_FLM6     */
-#define VDC5_GR_OIR_AB1_COUNT 3
+
+/* #define VDC5_GR_OIR_AB1_COUNT (3) */
     volatile uint32_t  GR_OIR_AB1;                             /*  GR_OIR_AB1      */
     volatile uint32_t  GR_OIR_AB2;                             /*  GR_OIR_AB2      */
     volatile uint32_t  GR_OIR_AB3;                             /*  GR_OIR_AB3      */
@@ -546,11 +1603,12 @@
     volatile uint32_t  GR_OIR_BASE;                            /*  GR_OIR_BASE     */
     volatile uint32_t  GR_OIR_CLUT;                            /*  GR_OIR_CLUT     */
     volatile uint32_t  GR_OIR_MON;                             /*  GR_OIR_MON      */
-};
+} r_io_vdc5_t;
 
 
-struct st_vdc5_from_gr0_update
+typedef struct st_vdc5_from_gr0_update
 {
+ 
     volatile uint32_t  GR0_UPDATE;                             /*  GR0_UPDATE      */
     volatile uint32_t  GR0_FLM_RD;                             /*  GR0_FLM_RD      */
     volatile uint32_t  GR0_FLM1;                               /*  GR0_FLM1        */
@@ -562,22 +1620,24 @@
     volatile uint32_t  GR0_AB1;                                /*  GR0_AB1         */
     volatile uint32_t  GR0_AB2;                                /*  GR0_AB2         */
     volatile uint32_t  GR0_AB3;                                /*  GR0_AB3         */
-};
+} r_io_vdc5_from_gr0_update_t;
 
 
-struct st_vdc5_from_gr0_ab7
+typedef struct st_vdc5_from_gr0_ab7
 {
+ 
     volatile uint32_t  GR0_AB7;                                /*  GR0_AB7         */
     volatile uint32_t  GR0_AB8;                                /*  GR0_AB8         */
     volatile uint32_t  GR0_AB9;                                /*  GR0_AB9         */
     volatile uint32_t  GR0_AB10;                               /*  GR0_AB10        */
     volatile uint32_t  GR0_AB11;                               /*  GR0_AB11        */
     volatile uint32_t  GR0_BASE;                               /*  GR0_BASE        */
-};
+} r_io_vdc5_from_gr0_ab7_t;
 
 
-struct st_vdc5_from_adj0_update
+typedef struct st_vdc5_from_adj0_update
 {
+ 
     volatile uint32_t  ADJ0_UPDATE;                            /*  ADJ0_UPDATE     */
     volatile uint32_t  ADJ0_BKSTR_SET;                         /*  ADJ0_BKSTR_SET  */
     volatile uint32_t  ADJ0_ENH_TIM1;                          /*  ADJ0_ENH_TIM1   */
@@ -598,11 +1658,12 @@
     volatile uint32_t  ADJ0_MTX_CBB_ADJ1;                      /*  ADJ0_MTX_CBB_ADJ1 */
     volatile uint32_t  ADJ0_MTX_CRR_ADJ0;                      /*  ADJ0_MTX_CRR_ADJ0 */
     volatile uint32_t  ADJ0_MTX_CRR_ADJ1;                      /*  ADJ0_MTX_CRR_ADJ1 */
-};
+} r_io_vdc5_from_adj0_update_t;
 
 
-struct st_vdc5_from_sc0_scl0_update
+typedef struct st_vdc5_from_sc0_scl0_update
 {
+ 
     volatile uint32_t  SC0_SCL0_UPDATE;                        /*  SC0_SCL0_UPDATE */
     volatile uint32_t  SC0_SCL0_FRC1;                          /*  SC0_SCL0_FRC1   */
     volatile uint32_t  SC0_SCL0_FRC2;                          /*  SC0_SCL0_FRC2   */
@@ -646,951 +1707,82 @@
     volatile uint32_t  SC0_SCL1_WR8;                           /*  SC0_SCL1_WR8    */
     volatile uint32_t  SC0_SCL1_WR9;                           /*  SC0_SCL1_WR9    */
     volatile uint32_t  SC0_SCL1_WR10;                          /*  SC0_SCL1_WR10   */
-};
+} r_io_vdc5_from_sc0_scl0_updat_t /* Short of r_io_vdc5_from_sc0_scl0_update_t */;
 
 
-struct st_vdc5_from_sc0_scl1_pbuf0
+typedef struct st_vdc5_from_sc0_scl1_pbuf0
 {
+ 
     volatile uint32_t  SC0_SCL1_PBUF0;                         /*  SC0_SCL1_PBUF0  */
     volatile uint32_t  SC0_SCL1_PBUF1;                         /*  SC0_SCL1_PBUF1  */
     volatile uint32_t  SC0_SCL1_PBUF2;                         /*  SC0_SCL1_PBUF2  */
     volatile uint32_t  SC0_SCL1_PBUF3;                         /*  SC0_SCL1_PBUF3  */
     volatile uint32_t  SC0_SCL1_PBUF_FLD;                      /*  SC0_SCL1_PBUF_FLD */
     volatile uint32_t  SC0_SCL1_PBUF_CNT;                      /*  SC0_SCL1_PBUF_CNT */
-};
-
-
-#define VDC50   (*(struct st_vdc5    *)0xFCFF7400uL) /* VDC50 */
-#define VDC51   (*(struct st_vdc5    *)0xFCFF9400uL) /* VDC51 */
-
-
-/* Start of channnel array defines of VDC5 */
-
-/* Channnel array defines of VDC5 */
-/*(Sample) value = VDC5[ channel ]->INP_UPDATE; */
-#define VDC5_COUNT  2
-#define VDC5_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-    &VDC50, &VDC51 \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-
-
-
-/* Channnel array defines of VDC5n_FROM_GR2_AB7_ARRAY */
-/*(Sample) value = VDC5n_FROM_GR2_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
-#define VDC5n_FROM_GR2_AB7_ARRAY_COUNT  2
-#define VDC5n_FROM_GR2_AB7_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_GR2_AB7, &VDC50_FROM_GR3_AB7 },{ \
-    &VDC51_FROM_GR2_AB7, &VDC51_FROM_GR3_AB7 \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR2_AB7) /* VDC50_FROM_GR2_AB7 */
-#define VDC50_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR3_AB7) /* VDC50_FROM_GR3_AB7 */
-#define VDC51_FROM_GR2_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR2_AB7) /* VDC51_FROM_GR2_AB7 */
-#define VDC51_FROM_GR3_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR3_AB7) /* VDC51_FROM_GR3_AB7 */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_GR2_UPDATE_ARRAY */
-/*(Sample) value = VDC5n_FROM_GR2_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
-#define VDC5n_FROM_GR2_UPDATE_ARRAY_COUNT  2
-#define VDC5n_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_GR2_UPDATE, &VDC50_FROM_GR3_UPDATE },{ \
-    &VDC51_FROM_GR2_UPDATE, &VDC51_FROM_GR3_UPDATE \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR2_UPDATE) /* VDC50_FROM_GR2_UPDATE */
-#define VDC50_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR3_UPDATE) /* VDC50_FROM_GR3_UPDATE */
-#define VDC51_FROM_GR2_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR2_UPDATE) /* VDC51_FROM_GR2_UPDATE */
-#define VDC51_FROM_GR3_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR3_UPDATE) /* VDC51_FROM_GR3_UPDATE */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY */
-/*(Sample) value = VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY[ channel ][ index ]->SC0_SCL1_PBUF0; */
-#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT  2
-#define VDC5n_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_SC0_SCL1_PBUF0, &VDC50_FROM_SC1_SCL1_PBUF0 },{ \
-    &VDC51_FROM_SC0_SCL1_PBUF0, &VDC51_FROM_SC1_SCL1_PBUF0 \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC0_SCL1_PBUF0) /* VDC50_FROM_SC0_SCL1_PBUF0 */
-#define VDC50_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC50.SC1_SCL1_PBUF0) /* VDC50_FROM_SC1_SCL1_PBUF0 */
-#define VDC51_FROM_SC0_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC0_SCL1_PBUF0) /* VDC51_FROM_SC0_SCL1_PBUF0 */
-#define VDC51_FROM_SC1_SCL1_PBUF0 (*(struct st_vdc5_from_sc0_scl1_pbuf0 *)&VDC51.SC1_SCL1_PBUF0) /* VDC51_FROM_SC1_SCL1_PBUF0 */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY */
-/*(Sample) value = VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY[ channel ][ index ]->SC0_SCL0_UPDATE; */
-#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT  2
-#define VDC5n_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_SC0_SCL0_UPDATE, &VDC50_FROM_SC1_SCL0_UPDATE },{ \
-    &VDC51_FROM_SC0_SCL0_UPDATE, &VDC51_FROM_SC1_SCL0_UPDATE \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC0_SCL0_UPDATE) /* VDC50_FROM_SC0_SCL0_UPDATE */
-#define VDC50_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC50.SC1_SCL0_UPDATE) /* VDC50_FROM_SC1_SCL0_UPDATE */
-#define VDC51_FROM_SC0_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC0_SCL0_UPDATE) /* VDC51_FROM_SC0_SCL0_UPDATE */
-#define VDC51_FROM_SC1_SCL0_UPDATE (*(struct st_vdc5_from_sc0_scl0_update *)&VDC51.SC1_SCL0_UPDATE) /* VDC51_FROM_SC1_SCL0_UPDATE */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_ADJ0_UPDATE_ARRAY */
-/*(Sample) value = VDC5n_FROM_ADJ0_UPDATE_ARRAY[ channel ][ index ]->ADJ0_UPDATE; */
-#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_COUNT  2
-#define VDC5n_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_ADJ0_UPDATE, &VDC50_FROM_ADJ1_UPDATE },{ \
-    &VDC51_FROM_ADJ0_UPDATE, &VDC51_FROM_ADJ1_UPDATE \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ0_UPDATE) /* VDC50_FROM_ADJ0_UPDATE */
-#define VDC50_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC50.ADJ1_UPDATE) /* VDC50_FROM_ADJ1_UPDATE */
-#define VDC51_FROM_ADJ0_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ0_UPDATE) /* VDC51_FROM_ADJ0_UPDATE */
-#define VDC51_FROM_ADJ1_UPDATE (*(struct st_vdc5_from_adj0_update *)&VDC51.ADJ1_UPDATE) /* VDC51_FROM_ADJ1_UPDATE */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_GR0_AB7_ARRAY */
-/*(Sample) value = VDC5n_FROM_GR0_AB7_ARRAY[ channel ][ index ]->GR0_AB7; */
-#define VDC5n_FROM_GR0_AB7_ARRAY_COUNT  2
-#define VDC5n_FROM_GR0_AB7_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_GR0_AB7, &VDC50_FROM_GR1_AB7 },{ \
-    &VDC51_FROM_GR0_AB7, &VDC51_FROM_GR1_AB7 \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR0_AB7) /* VDC50_FROM_GR0_AB7 */
-#define VDC50_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC50.GR1_AB7) /* VDC50_FROM_GR1_AB7 */
-#define VDC51_FROM_GR0_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR0_AB7) /* VDC51_FROM_GR0_AB7 */
-#define VDC51_FROM_GR1_AB7 (*(struct st_vdc5_from_gr0_ab7 *)&VDC51.GR1_AB7) /* VDC51_FROM_GR1_AB7 */
-
-
-
-
-/* Channnel array defines of VDC5n_FROM_GR0_UPDATE_ARRAY */
-/*(Sample) value = VDC5n_FROM_GR0_UPDATE_ARRAY[ channel ][ index ]->GR0_UPDATE; */
-#define VDC5n_FROM_GR0_UPDATE_ARRAY_COUNT  2
-#define VDC5n_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST \
-{   /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
-{ \
-    &VDC50_FROM_GR0_UPDATE, &VDC50_FROM_GR1_UPDATE },{ \
-    &VDC51_FROM_GR0_UPDATE, &VDC51_FROM_GR1_UPDATE \
-} \
-}   /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
-#define VDC50_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR0_UPDATE) /* VDC50_FROM_GR0_UPDATE */
-#define VDC50_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC50.GR1_UPDATE) /* VDC50_FROM_GR1_UPDATE */
-#define VDC51_FROM_GR0_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR0_UPDATE) /* VDC51_FROM_GR0_UPDATE */
-#define VDC51_FROM_GR1_UPDATE (*(struct st_vdc5_from_gr0_update *)&VDC51.GR1_UPDATE) /* VDC51_FROM_GR1_UPDATE */
-
-
-/* End of channnel array defines of VDC5 */
+} r_io_vdc5_from_sc0_scl1_pbuf0_t;
 
 
-#define VDC50INP_UPDATE VDC50.INP_UPDATE
-#define VDC50INP_SEL_CNT VDC50.INP_SEL_CNT
-#define VDC50INP_EXT_SYNC_CNT VDC50.INP_EXT_SYNC_CNT
-#define VDC50INP_VSYNC_PH_ADJ VDC50.INP_VSYNC_PH_ADJ
-#define VDC50INP_DLY_ADJ VDC50.INP_DLY_ADJ
-#define VDC50IMGCNT_UPDATE VDC50.IMGCNT_UPDATE
-#define VDC50IMGCNT_NR_CNT0 VDC50.IMGCNT_NR_CNT0
-#define VDC50IMGCNT_NR_CNT1 VDC50.IMGCNT_NR_CNT1
-#define VDC50IMGCNT_MTX_MODE VDC50.IMGCNT_MTX_MODE
-#define VDC50IMGCNT_MTX_YG_ADJ0 VDC50.IMGCNT_MTX_YG_ADJ0
-#define VDC50IMGCNT_MTX_YG_ADJ1 VDC50.IMGCNT_MTX_YG_ADJ1
-#define VDC50IMGCNT_MTX_CBB_ADJ0 VDC50.IMGCNT_MTX_CBB_ADJ0
-#define VDC50IMGCNT_MTX_CBB_ADJ1 VDC50.IMGCNT_MTX_CBB_ADJ1
-#define VDC50IMGCNT_MTX_CRR_ADJ0 VDC50.IMGCNT_MTX_CRR_ADJ0
-#define VDC50IMGCNT_MTX_CRR_ADJ1 VDC50.IMGCNT_MTX_CRR_ADJ1
-#define VDC50IMGCNT_DRC_REG VDC50.IMGCNT_DRC_REG
-#define VDC50SC0_SCL0_UPDATE VDC50.SC0_SCL0_UPDATE
-#define VDC50SC0_SCL0_FRC1 VDC50.SC0_SCL0_FRC1
-#define VDC50SC0_SCL0_FRC2 VDC50.SC0_SCL0_FRC2
-#define VDC50SC0_SCL0_FRC3 VDC50.SC0_SCL0_FRC3
-#define VDC50SC0_SCL0_FRC4 VDC50.SC0_SCL0_FRC4
-#define VDC50SC0_SCL0_FRC5 VDC50.SC0_SCL0_FRC5
-#define VDC50SC0_SCL0_FRC6 VDC50.SC0_SCL0_FRC6
-#define VDC50SC0_SCL0_FRC7 VDC50.SC0_SCL0_FRC7
-#define VDC50SC0_SCL0_FRC9 VDC50.SC0_SCL0_FRC9
-#define VDC50SC0_SCL0_MON0 VDC50.SC0_SCL0_MON0
-#define VDC50SC0_SCL0_INT VDC50.SC0_SCL0_INT
-#define VDC50SC0_SCL0_DS1 VDC50.SC0_SCL0_DS1
-#define VDC50SC0_SCL0_DS2 VDC50.SC0_SCL0_DS2
-#define VDC50SC0_SCL0_DS3 VDC50.SC0_SCL0_DS3
-#define VDC50SC0_SCL0_DS4 VDC50.SC0_SCL0_DS4
-#define VDC50SC0_SCL0_DS5 VDC50.SC0_SCL0_DS5
-#define VDC50SC0_SCL0_DS6 VDC50.SC0_SCL0_DS6
-#define VDC50SC0_SCL0_DS7 VDC50.SC0_SCL0_DS7
-#define VDC50SC0_SCL0_US1 VDC50.SC0_SCL0_US1
-#define VDC50SC0_SCL0_US2 VDC50.SC0_SCL0_US2
-#define VDC50SC0_SCL0_US3 VDC50.SC0_SCL0_US3
-#define VDC50SC0_SCL0_US4 VDC50.SC0_SCL0_US4
-#define VDC50SC0_SCL0_US5 VDC50.SC0_SCL0_US5
-#define VDC50SC0_SCL0_US6 VDC50.SC0_SCL0_US6
-#define VDC50SC0_SCL0_US7 VDC50.SC0_SCL0_US7
-#define VDC50SC0_SCL0_US8 VDC50.SC0_SCL0_US8
-#define VDC50SC0_SCL0_OVR1 VDC50.SC0_SCL0_OVR1
-#define VDC50SC0_SCL1_UPDATE VDC50.SC0_SCL1_UPDATE
-#define VDC50SC0_SCL1_WR1 VDC50.SC0_SCL1_WR1
-#define VDC50SC0_SCL1_WR2 VDC50.SC0_SCL1_WR2
-#define VDC50SC0_SCL1_WR3 VDC50.SC0_SCL1_WR3
-#define VDC50SC0_SCL1_WR4 VDC50.SC0_SCL1_WR4
-#define VDC50SC0_SCL1_WR5 VDC50.SC0_SCL1_WR5
-#define VDC50SC0_SCL1_WR6 VDC50.SC0_SCL1_WR6
-#define VDC50SC0_SCL1_WR7 VDC50.SC0_SCL1_WR7
-#define VDC50SC0_SCL1_WR8 VDC50.SC0_SCL1_WR8
-#define VDC50SC0_SCL1_WR9 VDC50.SC0_SCL1_WR9
-#define VDC50SC0_SCL1_WR10 VDC50.SC0_SCL1_WR10
-#define VDC50SC0_SCL1_WR11 VDC50.SC0_SCL1_WR11
-#define VDC50SC0_SCL1_MON1 VDC50.SC0_SCL1_MON1
-#define VDC50SC0_SCL1_PBUF0 VDC50.SC0_SCL1_PBUF0
-#define VDC50SC0_SCL1_PBUF1 VDC50.SC0_SCL1_PBUF1
-#define VDC50SC0_SCL1_PBUF2 VDC50.SC0_SCL1_PBUF2
-#define VDC50SC0_SCL1_PBUF3 VDC50.SC0_SCL1_PBUF3
-#define VDC50SC0_SCL1_PBUF_FLD VDC50.SC0_SCL1_PBUF_FLD
-#define VDC50SC0_SCL1_PBUF_CNT VDC50.SC0_SCL1_PBUF_CNT
-#define VDC50GR0_UPDATE VDC50.GR0_UPDATE
-#define VDC50GR0_FLM_RD VDC50.GR0_FLM_RD
-#define VDC50GR0_FLM1 VDC50.GR0_FLM1
-#define VDC50GR0_FLM2 VDC50.GR0_FLM2
-#define VDC50GR0_FLM3 VDC50.GR0_FLM3
-#define VDC50GR0_FLM4 VDC50.GR0_FLM4
-#define VDC50GR0_FLM5 VDC50.GR0_FLM5
-#define VDC50GR0_FLM6 VDC50.GR0_FLM6
-#define VDC50GR0_AB1 VDC50.GR0_AB1
-#define VDC50GR0_AB2 VDC50.GR0_AB2
-#define VDC50GR0_AB3 VDC50.GR0_AB3
-#define VDC50GR0_AB7 VDC50.GR0_AB7
-#define VDC50GR0_AB8 VDC50.GR0_AB8
-#define VDC50GR0_AB9 VDC50.GR0_AB9
-#define VDC50GR0_AB10 VDC50.GR0_AB10
-#define VDC50GR0_AB11 VDC50.GR0_AB11
-#define VDC50GR0_BASE VDC50.GR0_BASE
-#define VDC50GR0_CLUT VDC50.GR0_CLUT
-#define VDC50ADJ0_UPDATE VDC50.ADJ0_UPDATE
-#define VDC50ADJ0_BKSTR_SET VDC50.ADJ0_BKSTR_SET
-#define VDC50ADJ0_ENH_TIM1 VDC50.ADJ0_ENH_TIM1
-#define VDC50ADJ0_ENH_TIM2 VDC50.ADJ0_ENH_TIM2
-#define VDC50ADJ0_ENH_TIM3 VDC50.ADJ0_ENH_TIM3
-#define VDC50ADJ0_ENH_SHP1 VDC50.ADJ0_ENH_SHP1
-#define VDC50ADJ0_ENH_SHP2 VDC50.ADJ0_ENH_SHP2
-#define VDC50ADJ0_ENH_SHP3 VDC50.ADJ0_ENH_SHP3
-#define VDC50ADJ0_ENH_SHP4 VDC50.ADJ0_ENH_SHP4
-#define VDC50ADJ0_ENH_SHP5 VDC50.ADJ0_ENH_SHP5
-#define VDC50ADJ0_ENH_SHP6 VDC50.ADJ0_ENH_SHP6
-#define VDC50ADJ0_ENH_LTI1 VDC50.ADJ0_ENH_LTI1
-#define VDC50ADJ0_ENH_LTI2 VDC50.ADJ0_ENH_LTI2
-#define VDC50ADJ0_MTX_MODE VDC50.ADJ0_MTX_MODE
-#define VDC50ADJ0_MTX_YG_ADJ0 VDC50.ADJ0_MTX_YG_ADJ0
-#define VDC50ADJ0_MTX_YG_ADJ1 VDC50.ADJ0_MTX_YG_ADJ1
-#define VDC50ADJ0_MTX_CBB_ADJ0 VDC50.ADJ0_MTX_CBB_ADJ0
-#define VDC50ADJ0_MTX_CBB_ADJ1 VDC50.ADJ0_MTX_CBB_ADJ1
-#define VDC50ADJ0_MTX_CRR_ADJ0 VDC50.ADJ0_MTX_CRR_ADJ0
-#define VDC50ADJ0_MTX_CRR_ADJ1 VDC50.ADJ0_MTX_CRR_ADJ1
-#define VDC50GR2_UPDATE VDC50.GR2_UPDATE
-#define VDC50GR2_FLM_RD VDC50.GR2_FLM_RD
-#define VDC50GR2_FLM1 VDC50.GR2_FLM1
-#define VDC50GR2_FLM2 VDC50.GR2_FLM2
-#define VDC50GR2_FLM3 VDC50.GR2_FLM3
-#define VDC50GR2_FLM4 VDC50.GR2_FLM4
-#define VDC50GR2_FLM5 VDC50.GR2_FLM5
-#define VDC50GR2_FLM6 VDC50.GR2_FLM6
-#define VDC50GR2_AB1 VDC50.GR2_AB1
-#define VDC50GR2_AB2 VDC50.GR2_AB2
-#define VDC50GR2_AB3 VDC50.GR2_AB3
-#define VDC50GR2_AB4 VDC50.GR2_AB4
-#define VDC50GR2_AB5 VDC50.GR2_AB5
-#define VDC50GR2_AB6 VDC50.GR2_AB6
-#define VDC50GR2_AB7 VDC50.GR2_AB7
-#define VDC50GR2_AB8 VDC50.GR2_AB8
-#define VDC50GR2_AB9 VDC50.GR2_AB9
-#define VDC50GR2_AB10 VDC50.GR2_AB10
-#define VDC50GR2_AB11 VDC50.GR2_AB11
-#define VDC50GR2_BASE VDC50.GR2_BASE
-#define VDC50GR2_CLUT VDC50.GR2_CLUT
-#define VDC50GR2_MON VDC50.GR2_MON
-#define VDC50GR3_UPDATE VDC50.GR3_UPDATE
-#define VDC50GR3_FLM_RD VDC50.GR3_FLM_RD
-#define VDC50GR3_FLM1 VDC50.GR3_FLM1
-#define VDC50GR3_FLM2 VDC50.GR3_FLM2
-#define VDC50GR3_FLM3 VDC50.GR3_FLM3
-#define VDC50GR3_FLM4 VDC50.GR3_FLM4
-#define VDC50GR3_FLM5 VDC50.GR3_FLM5
-#define VDC50GR3_FLM6 VDC50.GR3_FLM6
-#define VDC50GR3_AB1 VDC50.GR3_AB1
-#define VDC50GR3_AB2 VDC50.GR3_AB2
-#define VDC50GR3_AB3 VDC50.GR3_AB3
-#define VDC50GR3_AB4 VDC50.GR3_AB4
-#define VDC50GR3_AB5 VDC50.GR3_AB5
-#define VDC50GR3_AB6 VDC50.GR3_AB6
-#define VDC50GR3_AB7 VDC50.GR3_AB7
-#define VDC50GR3_AB8 VDC50.GR3_AB8
-#define VDC50GR3_AB9 VDC50.GR3_AB9
-#define VDC50GR3_AB10 VDC50.GR3_AB10
-#define VDC50GR3_AB11 VDC50.GR3_AB11
-#define VDC50GR3_BASE VDC50.GR3_BASE
-#define VDC50GR3_CLUT_INT VDC50.GR3_CLUT_INT
-#define VDC50GR3_MON VDC50.GR3_MON
-#define VDC50GAM_G_UPDATE VDC50.GAM_G_UPDATE
-#define VDC50GAM_SW VDC50.GAM_SW
-#define VDC50GAM_G_LUT1 VDC50.GAM_G_LUT1
-#define VDC50GAM_G_LUT2 VDC50.GAM_G_LUT2
-#define VDC50GAM_G_LUT3 VDC50.GAM_G_LUT3
-#define VDC50GAM_G_LUT4 VDC50.GAM_G_LUT4
-#define VDC50GAM_G_LUT5 VDC50.GAM_G_LUT5
-#define VDC50GAM_G_LUT6 VDC50.GAM_G_LUT6
-#define VDC50GAM_G_LUT7 VDC50.GAM_G_LUT7
-#define VDC50GAM_G_LUT8 VDC50.GAM_G_LUT8
-#define VDC50GAM_G_LUT9 VDC50.GAM_G_LUT9
-#define VDC50GAM_G_LUT10 VDC50.GAM_G_LUT10
-#define VDC50GAM_G_LUT11 VDC50.GAM_G_LUT11
-#define VDC50GAM_G_LUT12 VDC50.GAM_G_LUT12
-#define VDC50GAM_G_LUT13 VDC50.GAM_G_LUT13
-#define VDC50GAM_G_LUT14 VDC50.GAM_G_LUT14
-#define VDC50GAM_G_LUT15 VDC50.GAM_G_LUT15
-#define VDC50GAM_G_LUT16 VDC50.GAM_G_LUT16
-#define VDC50GAM_G_AREA1 VDC50.GAM_G_AREA1
-#define VDC50GAM_G_AREA2 VDC50.GAM_G_AREA2
-#define VDC50GAM_G_AREA3 VDC50.GAM_G_AREA3
-#define VDC50GAM_G_AREA4 VDC50.GAM_G_AREA4
-#define VDC50GAM_G_AREA5 VDC50.GAM_G_AREA5
-#define VDC50GAM_G_AREA6 VDC50.GAM_G_AREA6
-#define VDC50GAM_G_AREA7 VDC50.GAM_G_AREA7
-#define VDC50GAM_G_AREA8 VDC50.GAM_G_AREA8
-#define VDC50GAM_B_UPDATE VDC50.GAM_B_UPDATE
-#define VDC50GAM_B_LUT1 VDC50.GAM_B_LUT1
-#define VDC50GAM_B_LUT2 VDC50.GAM_B_LUT2
-#define VDC50GAM_B_LUT3 VDC50.GAM_B_LUT3
-#define VDC50GAM_B_LUT4 VDC50.GAM_B_LUT4
-#define VDC50GAM_B_LUT5 VDC50.GAM_B_LUT5
-#define VDC50GAM_B_LUT6 VDC50.GAM_B_LUT6
-#define VDC50GAM_B_LUT7 VDC50.GAM_B_LUT7
-#define VDC50GAM_B_LUT8 VDC50.GAM_B_LUT8
-#define VDC50GAM_B_LUT9 VDC50.GAM_B_LUT9
-#define VDC50GAM_B_LUT10 VDC50.GAM_B_LUT10
-#define VDC50GAM_B_LUT11 VDC50.GAM_B_LUT11
-#define VDC50GAM_B_LUT12 VDC50.GAM_B_LUT12
-#define VDC50GAM_B_LUT13 VDC50.GAM_B_LUT13
-#define VDC50GAM_B_LUT14 VDC50.GAM_B_LUT14
-#define VDC50GAM_B_LUT15 VDC50.GAM_B_LUT15
-#define VDC50GAM_B_LUT16 VDC50.GAM_B_LUT16
-#define VDC50GAM_B_AREA1 VDC50.GAM_B_AREA1
-#define VDC50GAM_B_AREA2 VDC50.GAM_B_AREA2
-#define VDC50GAM_B_AREA3 VDC50.GAM_B_AREA3
-#define VDC50GAM_B_AREA4 VDC50.GAM_B_AREA4
-#define VDC50GAM_B_AREA5 VDC50.GAM_B_AREA5
-#define VDC50GAM_B_AREA6 VDC50.GAM_B_AREA6
-#define VDC50GAM_B_AREA7 VDC50.GAM_B_AREA7
-#define VDC50GAM_B_AREA8 VDC50.GAM_B_AREA8
-#define VDC50GAM_R_UPDATE VDC50.GAM_R_UPDATE
-#define VDC50GAM_R_LUT1 VDC50.GAM_R_LUT1
-#define VDC50GAM_R_LUT2 VDC50.GAM_R_LUT2
-#define VDC50GAM_R_LUT3 VDC50.GAM_R_LUT3
-#define VDC50GAM_R_LUT4 VDC50.GAM_R_LUT4
-#define VDC50GAM_R_LUT5 VDC50.GAM_R_LUT5
-#define VDC50GAM_R_LUT6 VDC50.GAM_R_LUT6
-#define VDC50GAM_R_LUT7 VDC50.GAM_R_LUT7
-#define VDC50GAM_R_LUT8 VDC50.GAM_R_LUT8
-#define VDC50GAM_R_LUT9 VDC50.GAM_R_LUT9
-#define VDC50GAM_R_LUT10 VDC50.GAM_R_LUT10
-#define VDC50GAM_R_LUT11 VDC50.GAM_R_LUT11
-#define VDC50GAM_R_LUT12 VDC50.GAM_R_LUT12
-#define VDC50GAM_R_LUT13 VDC50.GAM_R_LUT13
-#define VDC50GAM_R_LUT14 VDC50.GAM_R_LUT14
-#define VDC50GAM_R_LUT15 VDC50.GAM_R_LUT15
-#define VDC50GAM_R_LUT16 VDC50.GAM_R_LUT16
-#define VDC50GAM_R_AREA1 VDC50.GAM_R_AREA1
-#define VDC50GAM_R_AREA2 VDC50.GAM_R_AREA2
-#define VDC50GAM_R_AREA3 VDC50.GAM_R_AREA3
-#define VDC50GAM_R_AREA4 VDC50.GAM_R_AREA4
-#define VDC50GAM_R_AREA5 VDC50.GAM_R_AREA5
-#define VDC50GAM_R_AREA6 VDC50.GAM_R_AREA6
-#define VDC50GAM_R_AREA7 VDC50.GAM_R_AREA7
-#define VDC50GAM_R_AREA8 VDC50.GAM_R_AREA8
-#define VDC50TCON_UPDATE VDC50.TCON_UPDATE
-#define VDC50TCON_TIM VDC50.TCON_TIM
-#define VDC50TCON_TIM_STVA1 VDC50.TCON_TIM_STVA1
-#define VDC50TCON_TIM_STVA2 VDC50.TCON_TIM_STVA2
-#define VDC50TCON_TIM_STVB1 VDC50.TCON_TIM_STVB1
-#define VDC50TCON_TIM_STVB2 VDC50.TCON_TIM_STVB2
-#define VDC50TCON_TIM_STH1 VDC50.TCON_TIM_STH1
-#define VDC50TCON_TIM_STH2 VDC50.TCON_TIM_STH2
-#define VDC50TCON_TIM_STB1 VDC50.TCON_TIM_STB1
-#define VDC50TCON_TIM_STB2 VDC50.TCON_TIM_STB2
-#define VDC50TCON_TIM_CPV1 VDC50.TCON_TIM_CPV1
-#define VDC50TCON_TIM_CPV2 VDC50.TCON_TIM_CPV2
-#define VDC50TCON_TIM_POLA1 VDC50.TCON_TIM_POLA1
-#define VDC50TCON_TIM_POLA2 VDC50.TCON_TIM_POLA2
-#define VDC50TCON_TIM_POLB1 VDC50.TCON_TIM_POLB1
-#define VDC50TCON_TIM_POLB2 VDC50.TCON_TIM_POLB2
-#define VDC50TCON_TIM_DE VDC50.TCON_TIM_DE
-#define VDC50OUT_UPDATE VDC50.OUT_UPDATE
-#define VDC50OUT_SET VDC50.OUT_SET
-#define VDC50OUT_BRIGHT1 VDC50.OUT_BRIGHT1
-#define VDC50OUT_BRIGHT2 VDC50.OUT_BRIGHT2
-#define VDC50OUT_CONTRAST VDC50.OUT_CONTRAST
-#define VDC50OUT_PDTHA VDC50.OUT_PDTHA
-#define VDC50OUT_CLK_PHASE VDC50.OUT_CLK_PHASE
-#define VDC50SYSCNT_INT1 VDC50.SYSCNT_INT1
-#define VDC50SYSCNT_INT2 VDC50.SYSCNT_INT2
-#define VDC50SYSCNT_INT3 VDC50.SYSCNT_INT3
-#define VDC50SYSCNT_INT4 VDC50.SYSCNT_INT4
-#define VDC50SYSCNT_INT5 VDC50.SYSCNT_INT5
-#define VDC50SYSCNT_INT6 VDC50.SYSCNT_INT6
-#define VDC50SYSCNT_PANEL_CLK VDC50.SYSCNT_PANEL_CLK
-#define VDC50SYSCNT_CLUT VDC50.SYSCNT_CLUT
-#define VDC50SC1_SCL0_UPDATE VDC50.SC1_SCL0_UPDATE
-#define VDC50SC1_SCL0_FRC1 VDC50.SC1_SCL0_FRC1
-#define VDC50SC1_SCL0_FRC2 VDC50.SC1_SCL0_FRC2
-#define VDC50SC1_SCL0_FRC3 VDC50.SC1_SCL0_FRC3
-#define VDC50SC1_SCL0_FRC4 VDC50.SC1_SCL0_FRC4
-#define VDC50SC1_SCL0_FRC5 VDC50.SC1_SCL0_FRC5
-#define VDC50SC1_SCL0_FRC6 VDC50.SC1_SCL0_FRC6
-#define VDC50SC1_SCL0_FRC7 VDC50.SC1_SCL0_FRC7
-#define VDC50SC1_SCL0_FRC9 VDC50.SC1_SCL0_FRC9
-#define VDC50SC1_SCL0_MON0 VDC50.SC1_SCL0_MON0
-#define VDC50SC1_SCL0_INT VDC50.SC1_SCL0_INT
-#define VDC50SC1_SCL0_DS1 VDC50.SC1_SCL0_DS1
-#define VDC50SC1_SCL0_DS2 VDC50.SC1_SCL0_DS2
-#define VDC50SC1_SCL0_DS3 VDC50.SC1_SCL0_DS3
-#define VDC50SC1_SCL0_DS4 VDC50.SC1_SCL0_DS4
-#define VDC50SC1_SCL0_DS5 VDC50.SC1_SCL0_DS5
-#define VDC50SC1_SCL0_DS6 VDC50.SC1_SCL0_DS6
-#define VDC50SC1_SCL0_DS7 VDC50.SC1_SCL0_DS7
-#define VDC50SC1_SCL0_US1 VDC50.SC1_SCL0_US1
-#define VDC50SC1_SCL0_US2 VDC50.SC1_SCL0_US2
-#define VDC50SC1_SCL0_US3 VDC50.SC1_SCL0_US3
-#define VDC50SC1_SCL0_US4 VDC50.SC1_SCL0_US4
-#define VDC50SC1_SCL0_US5 VDC50.SC1_SCL0_US5
-#define VDC50SC1_SCL0_US6 VDC50.SC1_SCL0_US6
-#define VDC50SC1_SCL0_US7 VDC50.SC1_SCL0_US7
-#define VDC50SC1_SCL0_US8 VDC50.SC1_SCL0_US8
-#define VDC50SC1_SCL0_OVR1 VDC50.SC1_SCL0_OVR1
-#define VDC50SC1_SCL1_UPDATE VDC50.SC1_SCL1_UPDATE
-#define VDC50SC1_SCL1_WR1 VDC50.SC1_SCL1_WR1
-#define VDC50SC1_SCL1_WR2 VDC50.SC1_SCL1_WR2
-#define VDC50SC1_SCL1_WR3 VDC50.SC1_SCL1_WR3
-#define VDC50SC1_SCL1_WR4 VDC50.SC1_SCL1_WR4
-#define VDC50SC1_SCL1_WR5 VDC50.SC1_SCL1_WR5
-#define VDC50SC1_SCL1_WR6 VDC50.SC1_SCL1_WR6
-#define VDC50SC1_SCL1_WR7 VDC50.SC1_SCL1_WR7
-#define VDC50SC1_SCL1_WR8 VDC50.SC1_SCL1_WR8
-#define VDC50SC1_SCL1_WR9 VDC50.SC1_SCL1_WR9
-#define VDC50SC1_SCL1_WR10 VDC50.SC1_SCL1_WR10
-#define VDC50SC1_SCL1_WR11 VDC50.SC1_SCL1_WR11
-#define VDC50SC1_SCL1_MON1 VDC50.SC1_SCL1_MON1
-#define VDC50SC1_SCL1_PBUF0 VDC50.SC1_SCL1_PBUF0
-#define VDC50SC1_SCL1_PBUF1 VDC50.SC1_SCL1_PBUF1
-#define VDC50SC1_SCL1_PBUF2 VDC50.SC1_SCL1_PBUF2
-#define VDC50SC1_SCL1_PBUF3 VDC50.SC1_SCL1_PBUF3
-#define VDC50SC1_SCL1_PBUF_FLD VDC50.SC1_SCL1_PBUF_FLD
-#define VDC50SC1_SCL1_PBUF_CNT VDC50.SC1_SCL1_PBUF_CNT
-#define VDC50GR1_UPDATE VDC50.GR1_UPDATE
-#define VDC50GR1_FLM_RD VDC50.GR1_FLM_RD
-#define VDC50GR1_FLM1 VDC50.GR1_FLM1
-#define VDC50GR1_FLM2 VDC50.GR1_FLM2
-#define VDC50GR1_FLM3 VDC50.GR1_FLM3
-#define VDC50GR1_FLM4 VDC50.GR1_FLM4
-#define VDC50GR1_FLM5 VDC50.GR1_FLM5
-#define VDC50GR1_FLM6 VDC50.GR1_FLM6
-#define VDC50GR1_AB1 VDC50.GR1_AB1
-#define VDC50GR1_AB2 VDC50.GR1_AB2
-#define VDC50GR1_AB3 VDC50.GR1_AB3
-#define VDC50GR1_AB4 VDC50.GR1_AB4
-#define VDC50GR1_AB5 VDC50.GR1_AB5
-#define VDC50GR1_AB6 VDC50.GR1_AB6
-#define VDC50GR1_AB7 VDC50.GR1_AB7
-#define VDC50GR1_AB8 VDC50.GR1_AB8
-#define VDC50GR1_AB9 VDC50.GR1_AB9
-#define VDC50GR1_AB10 VDC50.GR1_AB10
-#define VDC50GR1_AB11 VDC50.GR1_AB11
-#define VDC50GR1_BASE VDC50.GR1_BASE
-#define VDC50GR1_CLUT VDC50.GR1_CLUT
-#define VDC50GR1_MON VDC50.GR1_MON
-#define VDC50ADJ1_UPDATE VDC50.ADJ1_UPDATE
-#define VDC50ADJ1_BKSTR_SET VDC50.ADJ1_BKSTR_SET
-#define VDC50ADJ1_ENH_TIM1 VDC50.ADJ1_ENH_TIM1
-#define VDC50ADJ1_ENH_TIM2 VDC50.ADJ1_ENH_TIM2
-#define VDC50ADJ1_ENH_TIM3 VDC50.ADJ1_ENH_TIM3
-#define VDC50ADJ1_ENH_SHP1 VDC50.ADJ1_ENH_SHP1
-#define VDC50ADJ1_ENH_SHP2 VDC50.ADJ1_ENH_SHP2
-#define VDC50ADJ1_ENH_SHP3 VDC50.ADJ1_ENH_SHP3
-#define VDC50ADJ1_ENH_SHP4 VDC50.ADJ1_ENH_SHP4
-#define VDC50ADJ1_ENH_SHP5 VDC50.ADJ1_ENH_SHP5
-#define VDC50ADJ1_ENH_SHP6 VDC50.ADJ1_ENH_SHP6
-#define VDC50ADJ1_ENH_LTI1 VDC50.ADJ1_ENH_LTI1
-#define VDC50ADJ1_ENH_LTI2 VDC50.ADJ1_ENH_LTI2
-#define VDC50ADJ1_MTX_MODE VDC50.ADJ1_MTX_MODE
-#define VDC50ADJ1_MTX_YG_ADJ0 VDC50.ADJ1_MTX_YG_ADJ0
-#define VDC50ADJ1_MTX_YG_ADJ1 VDC50.ADJ1_MTX_YG_ADJ1
-#define VDC50ADJ1_MTX_CBB_ADJ0 VDC50.ADJ1_MTX_CBB_ADJ0
-#define VDC50ADJ1_MTX_CBB_ADJ1 VDC50.ADJ1_MTX_CBB_ADJ1
-#define VDC50ADJ1_MTX_CRR_ADJ0 VDC50.ADJ1_MTX_CRR_ADJ0
-#define VDC50ADJ1_MTX_CRR_ADJ1 VDC50.ADJ1_MTX_CRR_ADJ1
-#define VDC50GR_VIN_UPDATE VDC50.GR_VIN_UPDATE
-#define VDC50GR_VIN_AB1 VDC50.GR_VIN_AB1
-#define VDC50GR_VIN_AB2 VDC50.GR_VIN_AB2
-#define VDC50GR_VIN_AB3 VDC50.GR_VIN_AB3
-#define VDC50GR_VIN_AB4 VDC50.GR_VIN_AB4
-#define VDC50GR_VIN_AB5 VDC50.GR_VIN_AB5
-#define VDC50GR_VIN_AB6 VDC50.GR_VIN_AB6
-#define VDC50GR_VIN_AB7 VDC50.GR_VIN_AB7
-#define VDC50GR_VIN_BASE VDC50.GR_VIN_BASE
-#define VDC50GR_VIN_MON VDC50.GR_VIN_MON
-#define VDC50OIR_SCL0_UPDATE VDC50.OIR_SCL0_UPDATE
-#define VDC50OIR_SCL0_FRC1 VDC50.OIR_SCL0_FRC1
-#define VDC50OIR_SCL0_FRC2 VDC50.OIR_SCL0_FRC2
-#define VDC50OIR_SCL0_FRC3 VDC50.OIR_SCL0_FRC3
-#define VDC50OIR_SCL0_FRC4 VDC50.OIR_SCL0_FRC4
-#define VDC50OIR_SCL0_FRC5 VDC50.OIR_SCL0_FRC5
-#define VDC50OIR_SCL0_FRC6 VDC50.OIR_SCL0_FRC6
-#define VDC50OIR_SCL0_FRC7 VDC50.OIR_SCL0_FRC7
-#define VDC50OIR_SCL0_DS1 VDC50.OIR_SCL0_DS1
-#define VDC50OIR_SCL0_DS2 VDC50.OIR_SCL0_DS2
-#define VDC50OIR_SCL0_DS3 VDC50.OIR_SCL0_DS3
-#define VDC50OIR_SCL0_DS7 VDC50.OIR_SCL0_DS7
-#define VDC50OIR_SCL0_US1 VDC50.OIR_SCL0_US1
-#define VDC50OIR_SCL0_US2 VDC50.OIR_SCL0_US2
-#define VDC50OIR_SCL0_US3 VDC50.OIR_SCL0_US3
-#define VDC50OIR_SCL0_US8 VDC50.OIR_SCL0_US8
-#define VDC50OIR_SCL0_OVR1 VDC50.OIR_SCL0_OVR1
-#define VDC50OIR_SCL1_UPDATE VDC50.OIR_SCL1_UPDATE
-#define VDC50OIR_SCL1_WR1 VDC50.OIR_SCL1_WR1
-#define VDC50OIR_SCL1_WR2 VDC50.OIR_SCL1_WR2
-#define VDC50OIR_SCL1_WR3 VDC50.OIR_SCL1_WR3
-#define VDC50OIR_SCL1_WR4 VDC50.OIR_SCL1_WR4
-#define VDC50OIR_SCL1_WR5 VDC50.OIR_SCL1_WR5
-#define VDC50OIR_SCL1_WR6 VDC50.OIR_SCL1_WR6
-#define VDC50OIR_SCL1_WR7 VDC50.OIR_SCL1_WR7
-#define VDC50GR_OIR_UPDATE VDC50.GR_OIR_UPDATE
-#define VDC50GR_OIR_FLM_RD VDC50.GR_OIR_FLM_RD
-#define VDC50GR_OIR_FLM1 VDC50.GR_OIR_FLM1
-#define VDC50GR_OIR_FLM2 VDC50.GR_OIR_FLM2
-#define VDC50GR_OIR_FLM3 VDC50.GR_OIR_FLM3
-#define VDC50GR_OIR_FLM4 VDC50.GR_OIR_FLM4
-#define VDC50GR_OIR_FLM5 VDC50.GR_OIR_FLM5
-#define VDC50GR_OIR_FLM6 VDC50.GR_OIR_FLM6
-#define VDC50GR_OIR_AB1 VDC50.GR_OIR_AB1
-#define VDC50GR_OIR_AB2 VDC50.GR_OIR_AB2
-#define VDC50GR_OIR_AB3 VDC50.GR_OIR_AB3
-#define VDC50GR_OIR_AB7 VDC50.GR_OIR_AB7
-#define VDC50GR_OIR_AB8 VDC50.GR_OIR_AB8
-#define VDC50GR_OIR_AB9 VDC50.GR_OIR_AB9
-#define VDC50GR_OIR_AB10 VDC50.GR_OIR_AB10
-#define VDC50GR_OIR_AB11 VDC50.GR_OIR_AB11
-#define VDC50GR_OIR_BASE VDC50.GR_OIR_BASE
-#define VDC50GR_OIR_CLUT VDC50.GR_OIR_CLUT
-#define VDC50GR_OIR_MON VDC50.GR_OIR_MON
-#define VDC51INP_UPDATE VDC51.INP_UPDATE
-#define VDC51INP_SEL_CNT VDC51.INP_SEL_CNT
-#define VDC51INP_EXT_SYNC_CNT VDC51.INP_EXT_SYNC_CNT
-#define VDC51INP_VSYNC_PH_ADJ VDC51.INP_VSYNC_PH_ADJ
-#define VDC51INP_DLY_ADJ VDC51.INP_DLY_ADJ
-#define VDC51IMGCNT_UPDATE VDC51.IMGCNT_UPDATE
-#define VDC51IMGCNT_NR_CNT0 VDC51.IMGCNT_NR_CNT0
-#define VDC51IMGCNT_NR_CNT1 VDC51.IMGCNT_NR_CNT1
-#define VDC51IMGCNT_MTX_MODE VDC51.IMGCNT_MTX_MODE
-#define VDC51IMGCNT_MTX_YG_ADJ0 VDC51.IMGCNT_MTX_YG_ADJ0
-#define VDC51IMGCNT_MTX_YG_ADJ1 VDC51.IMGCNT_MTX_YG_ADJ1
-#define VDC51IMGCNT_MTX_CBB_ADJ0 VDC51.IMGCNT_MTX_CBB_ADJ0
-#define VDC51IMGCNT_MTX_CBB_ADJ1 VDC51.IMGCNT_MTX_CBB_ADJ1
-#define VDC51IMGCNT_MTX_CRR_ADJ0 VDC51.IMGCNT_MTX_CRR_ADJ0
-#define VDC51IMGCNT_MTX_CRR_ADJ1 VDC51.IMGCNT_MTX_CRR_ADJ1
-#define VDC51IMGCNT_DRC_REG VDC51.IMGCNT_DRC_REG
-#define VDC51SC0_SCL0_UPDATE VDC51.SC0_SCL0_UPDATE
-#define VDC51SC0_SCL0_FRC1 VDC51.SC0_SCL0_FRC1
-#define VDC51SC0_SCL0_FRC2 VDC51.SC0_SCL0_FRC2
-#define VDC51SC0_SCL0_FRC3 VDC51.SC0_SCL0_FRC3
-#define VDC51SC0_SCL0_FRC4 VDC51.SC0_SCL0_FRC4
-#define VDC51SC0_SCL0_FRC5 VDC51.SC0_SCL0_FRC5
-#define VDC51SC0_SCL0_FRC6 VDC51.SC0_SCL0_FRC6
-#define VDC51SC0_SCL0_FRC7 VDC51.SC0_SCL0_FRC7
-#define VDC51SC0_SCL0_FRC9 VDC51.SC0_SCL0_FRC9
-#define VDC51SC0_SCL0_MON0 VDC51.SC0_SCL0_MON0
-#define VDC51SC0_SCL0_INT VDC51.SC0_SCL0_INT
-#define VDC51SC0_SCL0_DS1 VDC51.SC0_SCL0_DS1
-#define VDC51SC0_SCL0_DS2 VDC51.SC0_SCL0_DS2
-#define VDC51SC0_SCL0_DS3 VDC51.SC0_SCL0_DS3
-#define VDC51SC0_SCL0_DS4 VDC51.SC0_SCL0_DS4
-#define VDC51SC0_SCL0_DS5 VDC51.SC0_SCL0_DS5
-#define VDC51SC0_SCL0_DS6 VDC51.SC0_SCL0_DS6
-#define VDC51SC0_SCL0_DS7 VDC51.SC0_SCL0_DS7
-#define VDC51SC0_SCL0_US1 VDC51.SC0_SCL0_US1
-#define VDC51SC0_SCL0_US2 VDC51.SC0_SCL0_US2
-#define VDC51SC0_SCL0_US3 VDC51.SC0_SCL0_US3
-#define VDC51SC0_SCL0_US4 VDC51.SC0_SCL0_US4
-#define VDC51SC0_SCL0_US5 VDC51.SC0_SCL0_US5
-#define VDC51SC0_SCL0_US6 VDC51.SC0_SCL0_US6
-#define VDC51SC0_SCL0_US7 VDC51.SC0_SCL0_US7
-#define VDC51SC0_SCL0_US8 VDC51.SC0_SCL0_US8
-#define VDC51SC0_SCL0_OVR1 VDC51.SC0_SCL0_OVR1
-#define VDC51SC0_SCL1_UPDATE VDC51.SC0_SCL1_UPDATE
-#define VDC51SC0_SCL1_WR1 VDC51.SC0_SCL1_WR1
-#define VDC51SC0_SCL1_WR2 VDC51.SC0_SCL1_WR2
-#define VDC51SC0_SCL1_WR3 VDC51.SC0_SCL1_WR3
-#define VDC51SC0_SCL1_WR4 VDC51.SC0_SCL1_WR4
-#define VDC51SC0_SCL1_WR5 VDC51.SC0_SCL1_WR5
-#define VDC51SC0_SCL1_WR6 VDC51.SC0_SCL1_WR6
-#define VDC51SC0_SCL1_WR7 VDC51.SC0_SCL1_WR7
-#define VDC51SC0_SCL1_WR8 VDC51.SC0_SCL1_WR8
-#define VDC51SC0_SCL1_WR9 VDC51.SC0_SCL1_WR9
-#define VDC51SC0_SCL1_WR10 VDC51.SC0_SCL1_WR10
-#define VDC51SC0_SCL1_WR11 VDC51.SC0_SCL1_WR11
-#define VDC51SC0_SCL1_MON1 VDC51.SC0_SCL1_MON1
-#define VDC51SC0_SCL1_PBUF0 VDC51.SC0_SCL1_PBUF0
-#define VDC51SC0_SCL1_PBUF1 VDC51.SC0_SCL1_PBUF1
-#define VDC51SC0_SCL1_PBUF2 VDC51.SC0_SCL1_PBUF2
-#define VDC51SC0_SCL1_PBUF3 VDC51.SC0_SCL1_PBUF3
-#define VDC51SC0_SCL1_PBUF_FLD VDC51.SC0_SCL1_PBUF_FLD
-#define VDC51SC0_SCL1_PBUF_CNT VDC51.SC0_SCL1_PBUF_CNT
-#define VDC51GR0_UPDATE VDC51.GR0_UPDATE
-#define VDC51GR0_FLM_RD VDC51.GR0_FLM_RD
-#define VDC51GR0_FLM1 VDC51.GR0_FLM1
-#define VDC51GR0_FLM2 VDC51.GR0_FLM2
-#define VDC51GR0_FLM3 VDC51.GR0_FLM3
-#define VDC51GR0_FLM4 VDC51.GR0_FLM4
-#define VDC51GR0_FLM5 VDC51.GR0_FLM5
-#define VDC51GR0_FLM6 VDC51.GR0_FLM6
-#define VDC51GR0_AB1 VDC51.GR0_AB1
-#define VDC51GR0_AB2 VDC51.GR0_AB2
-#define VDC51GR0_AB3 VDC51.GR0_AB3
-#define VDC51GR0_AB7 VDC51.GR0_AB7
-#define VDC51GR0_AB8 VDC51.GR0_AB8
-#define VDC51GR0_AB9 VDC51.GR0_AB9
-#define VDC51GR0_AB10 VDC51.GR0_AB10
-#define VDC51GR0_AB11 VDC51.GR0_AB11
-#define VDC51GR0_BASE VDC51.GR0_BASE
-#define VDC51GR0_CLUT VDC51.GR0_CLUT
-#define VDC51ADJ0_UPDATE VDC51.ADJ0_UPDATE
-#define VDC51ADJ0_BKSTR_SET VDC51.ADJ0_BKSTR_SET
-#define VDC51ADJ0_ENH_TIM1 VDC51.ADJ0_ENH_TIM1
-#define VDC51ADJ0_ENH_TIM2 VDC51.ADJ0_ENH_TIM2
-#define VDC51ADJ0_ENH_TIM3 VDC51.ADJ0_ENH_TIM3
-#define VDC51ADJ0_ENH_SHP1 VDC51.ADJ0_ENH_SHP1
-#define VDC51ADJ0_ENH_SHP2 VDC51.ADJ0_ENH_SHP2
-#define VDC51ADJ0_ENH_SHP3 VDC51.ADJ0_ENH_SHP3
-#define VDC51ADJ0_ENH_SHP4 VDC51.ADJ0_ENH_SHP4
-#define VDC51ADJ0_ENH_SHP5 VDC51.ADJ0_ENH_SHP5
-#define VDC51ADJ0_ENH_SHP6 VDC51.ADJ0_ENH_SHP6
-#define VDC51ADJ0_ENH_LTI1 VDC51.ADJ0_ENH_LTI1
-#define VDC51ADJ0_ENH_LTI2 VDC51.ADJ0_ENH_LTI2
-#define VDC51ADJ0_MTX_MODE VDC51.ADJ0_MTX_MODE
-#define VDC51ADJ0_MTX_YG_ADJ0 VDC51.ADJ0_MTX_YG_ADJ0
-#define VDC51ADJ0_MTX_YG_ADJ1 VDC51.ADJ0_MTX_YG_ADJ1
-#define VDC51ADJ0_MTX_CBB_ADJ0 VDC51.ADJ0_MTX_CBB_ADJ0
-#define VDC51ADJ0_MTX_CBB_ADJ1 VDC51.ADJ0_MTX_CBB_ADJ1
-#define VDC51ADJ0_MTX_CRR_ADJ0 VDC51.ADJ0_MTX_CRR_ADJ0
-#define VDC51ADJ0_MTX_CRR_ADJ1 VDC51.ADJ0_MTX_CRR_ADJ1
-#define VDC51GR2_UPDATE VDC51.GR2_UPDATE
-#define VDC51GR2_FLM_RD VDC51.GR2_FLM_RD
-#define VDC51GR2_FLM1 VDC51.GR2_FLM1
-#define VDC51GR2_FLM2 VDC51.GR2_FLM2
-#define VDC51GR2_FLM3 VDC51.GR2_FLM3
-#define VDC51GR2_FLM4 VDC51.GR2_FLM4
-#define VDC51GR2_FLM5 VDC51.GR2_FLM5
-#define VDC51GR2_FLM6 VDC51.GR2_FLM6
-#define VDC51GR2_AB1 VDC51.GR2_AB1
-#define VDC51GR2_AB2 VDC51.GR2_AB2
-#define VDC51GR2_AB3 VDC51.GR2_AB3
-#define VDC51GR2_AB4 VDC51.GR2_AB4
-#define VDC51GR2_AB5 VDC51.GR2_AB5
-#define VDC51GR2_AB6 VDC51.GR2_AB6
-#define VDC51GR2_AB7 VDC51.GR2_AB7
-#define VDC51GR2_AB8 VDC51.GR2_AB8
-#define VDC51GR2_AB9 VDC51.GR2_AB9
-#define VDC51GR2_AB10 VDC51.GR2_AB10
-#define VDC51GR2_AB11 VDC51.GR2_AB11
-#define VDC51GR2_BASE VDC51.GR2_BASE
-#define VDC51GR2_CLUT VDC51.GR2_CLUT
-#define VDC51GR2_MON VDC51.GR2_MON
-#define VDC51GR3_UPDATE VDC51.GR3_UPDATE
-#define VDC51GR3_FLM_RD VDC51.GR3_FLM_RD
-#define VDC51GR3_FLM1 VDC51.GR3_FLM1
-#define VDC51GR3_FLM2 VDC51.GR3_FLM2
-#define VDC51GR3_FLM3 VDC51.GR3_FLM3
-#define VDC51GR3_FLM4 VDC51.GR3_FLM4
-#define VDC51GR3_FLM5 VDC51.GR3_FLM5
-#define VDC51GR3_FLM6 VDC51.GR3_FLM6
-#define VDC51GR3_AB1 VDC51.GR3_AB1
-#define VDC51GR3_AB2 VDC51.GR3_AB2
-#define VDC51GR3_AB3 VDC51.GR3_AB3
-#define VDC51GR3_AB4 VDC51.GR3_AB4
-#define VDC51GR3_AB5 VDC51.GR3_AB5
-#define VDC51GR3_AB6 VDC51.GR3_AB6
-#define VDC51GR3_AB7 VDC51.GR3_AB7
-#define VDC51GR3_AB8 VDC51.GR3_AB8
-#define VDC51GR3_AB9 VDC51.GR3_AB9
-#define VDC51GR3_AB10 VDC51.GR3_AB10
-#define VDC51GR3_AB11 VDC51.GR3_AB11
-#define VDC51GR3_BASE VDC51.GR3_BASE
-#define VDC51GR3_CLUT_INT VDC51.GR3_CLUT_INT
-#define VDC51GR3_MON VDC51.GR3_MON
-#define VDC51GAM_G_UPDATE VDC51.GAM_G_UPDATE
-#define VDC51GAM_SW VDC51.GAM_SW
-#define VDC51GAM_G_LUT1 VDC51.GAM_G_LUT1
-#define VDC51GAM_G_LUT2 VDC51.GAM_G_LUT2
-#define VDC51GAM_G_LUT3 VDC51.GAM_G_LUT3
-#define VDC51GAM_G_LUT4 VDC51.GAM_G_LUT4
-#define VDC51GAM_G_LUT5 VDC51.GAM_G_LUT5
-#define VDC51GAM_G_LUT6 VDC51.GAM_G_LUT6
-#define VDC51GAM_G_LUT7 VDC51.GAM_G_LUT7
-#define VDC51GAM_G_LUT8 VDC51.GAM_G_LUT8
-#define VDC51GAM_G_LUT9 VDC51.GAM_G_LUT9
-#define VDC51GAM_G_LUT10 VDC51.GAM_G_LUT10
-#define VDC51GAM_G_LUT11 VDC51.GAM_G_LUT11
-#define VDC51GAM_G_LUT12 VDC51.GAM_G_LUT12
-#define VDC51GAM_G_LUT13 VDC51.GAM_G_LUT13
-#define VDC51GAM_G_LUT14 VDC51.GAM_G_LUT14
-#define VDC51GAM_G_LUT15 VDC51.GAM_G_LUT15
-#define VDC51GAM_G_LUT16 VDC51.GAM_G_LUT16
-#define VDC51GAM_G_AREA1 VDC51.GAM_G_AREA1
-#define VDC51GAM_G_AREA2 VDC51.GAM_G_AREA2
-#define VDC51GAM_G_AREA3 VDC51.GAM_G_AREA3
-#define VDC51GAM_G_AREA4 VDC51.GAM_G_AREA4
-#define VDC51GAM_G_AREA5 VDC51.GAM_G_AREA5
-#define VDC51GAM_G_AREA6 VDC51.GAM_G_AREA6
-#define VDC51GAM_G_AREA7 VDC51.GAM_G_AREA7
-#define VDC51GAM_G_AREA8 VDC51.GAM_G_AREA8
-#define VDC51GAM_B_UPDATE VDC51.GAM_B_UPDATE
-#define VDC51GAM_B_LUT1 VDC51.GAM_B_LUT1
-#define VDC51GAM_B_LUT2 VDC51.GAM_B_LUT2
-#define VDC51GAM_B_LUT3 VDC51.GAM_B_LUT3
-#define VDC51GAM_B_LUT4 VDC51.GAM_B_LUT4
-#define VDC51GAM_B_LUT5 VDC51.GAM_B_LUT5
-#define VDC51GAM_B_LUT6 VDC51.GAM_B_LUT6
-#define VDC51GAM_B_LUT7 VDC51.GAM_B_LUT7
-#define VDC51GAM_B_LUT8 VDC51.GAM_B_LUT8
-#define VDC51GAM_B_LUT9 VDC51.GAM_B_LUT9
-#define VDC51GAM_B_LUT10 VDC51.GAM_B_LUT10
-#define VDC51GAM_B_LUT11 VDC51.GAM_B_LUT11
-#define VDC51GAM_B_LUT12 VDC51.GAM_B_LUT12
-#define VDC51GAM_B_LUT13 VDC51.GAM_B_LUT13
-#define VDC51GAM_B_LUT14 VDC51.GAM_B_LUT14
-#define VDC51GAM_B_LUT15 VDC51.GAM_B_LUT15
-#define VDC51GAM_B_LUT16 VDC51.GAM_B_LUT16
-#define VDC51GAM_B_AREA1 VDC51.GAM_B_AREA1
-#define VDC51GAM_B_AREA2 VDC51.GAM_B_AREA2
-#define VDC51GAM_B_AREA3 VDC51.GAM_B_AREA3
-#define VDC51GAM_B_AREA4 VDC51.GAM_B_AREA4
-#define VDC51GAM_B_AREA5 VDC51.GAM_B_AREA5
-#define VDC51GAM_B_AREA6 VDC51.GAM_B_AREA6
-#define VDC51GAM_B_AREA7 VDC51.GAM_B_AREA7
-#define VDC51GAM_B_AREA8 VDC51.GAM_B_AREA8
-#define VDC51GAM_R_UPDATE VDC51.GAM_R_UPDATE
-#define VDC51GAM_R_LUT1 VDC51.GAM_R_LUT1
-#define VDC51GAM_R_LUT2 VDC51.GAM_R_LUT2
-#define VDC51GAM_R_LUT3 VDC51.GAM_R_LUT3
-#define VDC51GAM_R_LUT4 VDC51.GAM_R_LUT4
-#define VDC51GAM_R_LUT5 VDC51.GAM_R_LUT5
-#define VDC51GAM_R_LUT6 VDC51.GAM_R_LUT6
-#define VDC51GAM_R_LUT7 VDC51.GAM_R_LUT7
-#define VDC51GAM_R_LUT8 VDC51.GAM_R_LUT8
-#define VDC51GAM_R_LUT9 VDC51.GAM_R_LUT9
-#define VDC51GAM_R_LUT10 VDC51.GAM_R_LUT10
-#define VDC51GAM_R_LUT11 VDC51.GAM_R_LUT11
-#define VDC51GAM_R_LUT12 VDC51.GAM_R_LUT12
-#define VDC51GAM_R_LUT13 VDC51.GAM_R_LUT13
-#define VDC51GAM_R_LUT14 VDC51.GAM_R_LUT14
-#define VDC51GAM_R_LUT15 VDC51.GAM_R_LUT15
-#define VDC51GAM_R_LUT16 VDC51.GAM_R_LUT16
-#define VDC51GAM_R_AREA1 VDC51.GAM_R_AREA1
-#define VDC51GAM_R_AREA2 VDC51.GAM_R_AREA2
-#define VDC51GAM_R_AREA3 VDC51.GAM_R_AREA3
-#define VDC51GAM_R_AREA4 VDC51.GAM_R_AREA4
-#define VDC51GAM_R_AREA5 VDC51.GAM_R_AREA5
-#define VDC51GAM_R_AREA6 VDC51.GAM_R_AREA6
-#define VDC51GAM_R_AREA7 VDC51.GAM_R_AREA7
-#define VDC51GAM_R_AREA8 VDC51.GAM_R_AREA8
-#define VDC51TCON_UPDATE VDC51.TCON_UPDATE
-#define VDC51TCON_TIM VDC51.TCON_TIM
-#define VDC51TCON_TIM_STVA1 VDC51.TCON_TIM_STVA1
-#define VDC51TCON_TIM_STVA2 VDC51.TCON_TIM_STVA2
-#define VDC51TCON_TIM_STVB1 VDC51.TCON_TIM_STVB1
-#define VDC51TCON_TIM_STVB2 VDC51.TCON_TIM_STVB2
-#define VDC51TCON_TIM_STH1 VDC51.TCON_TIM_STH1
-#define VDC51TCON_TIM_STH2 VDC51.TCON_TIM_STH2
-#define VDC51TCON_TIM_STB1 VDC51.TCON_TIM_STB1
-#define VDC51TCON_TIM_STB2 VDC51.TCON_TIM_STB2
-#define VDC51TCON_TIM_CPV1 VDC51.TCON_TIM_CPV1
-#define VDC51TCON_TIM_CPV2 VDC51.TCON_TIM_CPV2
-#define VDC51TCON_TIM_POLA1 VDC51.TCON_TIM_POLA1
-#define VDC51TCON_TIM_POLA2 VDC51.TCON_TIM_POLA2
-#define VDC51TCON_TIM_POLB1 VDC51.TCON_TIM_POLB1
-#define VDC51TCON_TIM_POLB2 VDC51.TCON_TIM_POLB2
-#define VDC51TCON_TIM_DE VDC51.TCON_TIM_DE
-#define VDC51OUT_UPDATE VDC51.OUT_UPDATE
-#define VDC51OUT_SET VDC51.OUT_SET
-#define VDC51OUT_BRIGHT1 VDC51.OUT_BRIGHT1
-#define VDC51OUT_BRIGHT2 VDC51.OUT_BRIGHT2
-#define VDC51OUT_CONTRAST VDC51.OUT_CONTRAST
-#define VDC51OUT_PDTHA VDC51.OUT_PDTHA
-#define VDC51OUT_CLK_PHASE VDC51.OUT_CLK_PHASE
-#define VDC51SYSCNT_INT1 VDC51.SYSCNT_INT1
-#define VDC51SYSCNT_INT2 VDC51.SYSCNT_INT2
-#define VDC51SYSCNT_INT3 VDC51.SYSCNT_INT3
-#define VDC51SYSCNT_INT4 VDC51.SYSCNT_INT4
-#define VDC51SYSCNT_INT5 VDC51.SYSCNT_INT5
-#define VDC51SYSCNT_INT6 VDC51.SYSCNT_INT6
-#define VDC51SYSCNT_PANEL_CLK VDC51.SYSCNT_PANEL_CLK
-#define VDC51SYSCNT_CLUT VDC51.SYSCNT_CLUT
-#define VDC51SC1_SCL0_UPDATE VDC51.SC1_SCL0_UPDATE
-#define VDC51SC1_SCL0_FRC1 VDC51.SC1_SCL0_FRC1
-#define VDC51SC1_SCL0_FRC2 VDC51.SC1_SCL0_FRC2
-#define VDC51SC1_SCL0_FRC3 VDC51.SC1_SCL0_FRC3
-#define VDC51SC1_SCL0_FRC4 VDC51.SC1_SCL0_FRC4
-#define VDC51SC1_SCL0_FRC5 VDC51.SC1_SCL0_FRC5
-#define VDC51SC1_SCL0_FRC6 VDC51.SC1_SCL0_FRC6
-#define VDC51SC1_SCL0_FRC7 VDC51.SC1_SCL0_FRC7
-#define VDC51SC1_SCL0_FRC9 VDC51.SC1_SCL0_FRC9
-#define VDC51SC1_SCL0_MON0 VDC51.SC1_SCL0_MON0
-#define VDC51SC1_SCL0_INT VDC51.SC1_SCL0_INT
-#define VDC51SC1_SCL0_DS1 VDC51.SC1_SCL0_DS1
-#define VDC51SC1_SCL0_DS2 VDC51.SC1_SCL0_DS2
-#define VDC51SC1_SCL0_DS3 VDC51.SC1_SCL0_DS3
-#define VDC51SC1_SCL0_DS4 VDC51.SC1_SCL0_DS4
-#define VDC51SC1_SCL0_DS5 VDC51.SC1_SCL0_DS5
-#define VDC51SC1_SCL0_DS6 VDC51.SC1_SCL0_DS6
-#define VDC51SC1_SCL0_DS7 VDC51.SC1_SCL0_DS7
-#define VDC51SC1_SCL0_US1 VDC51.SC1_SCL0_US1
-#define VDC51SC1_SCL0_US2 VDC51.SC1_SCL0_US2
-#define VDC51SC1_SCL0_US3 VDC51.SC1_SCL0_US3
-#define VDC51SC1_SCL0_US4 VDC51.SC1_SCL0_US4
-#define VDC51SC1_SCL0_US5 VDC51.SC1_SCL0_US5
-#define VDC51SC1_SCL0_US6 VDC51.SC1_SCL0_US6
-#define VDC51SC1_SCL0_US7 VDC51.SC1_SCL0_US7
-#define VDC51SC1_SCL0_US8 VDC51.SC1_SCL0_US8
-#define VDC51SC1_SCL0_OVR1 VDC51.SC1_SCL0_OVR1
-#define VDC51SC1_SCL1_UPDATE VDC51.SC1_SCL1_UPDATE
-#define VDC51SC1_SCL1_WR1 VDC51.SC1_SCL1_WR1
-#define VDC51SC1_SCL1_WR2 VDC51.SC1_SCL1_WR2
-#define VDC51SC1_SCL1_WR3 VDC51.SC1_SCL1_WR3
-#define VDC51SC1_SCL1_WR4 VDC51.SC1_SCL1_WR4
-#define VDC51SC1_SCL1_WR5 VDC51.SC1_SCL1_WR5
-#define VDC51SC1_SCL1_WR6 VDC51.SC1_SCL1_WR6
-#define VDC51SC1_SCL1_WR7 VDC51.SC1_SCL1_WR7
-#define VDC51SC1_SCL1_WR8 VDC51.SC1_SCL1_WR8
-#define VDC51SC1_SCL1_WR9 VDC51.SC1_SCL1_WR9
-#define VDC51SC1_SCL1_WR10 VDC51.SC1_SCL1_WR10
-#define VDC51SC1_SCL1_WR11 VDC51.SC1_SCL1_WR11
-#define VDC51SC1_SCL1_MON1 VDC51.SC1_SCL1_MON1
-#define VDC51SC1_SCL1_PBUF0 VDC51.SC1_SCL1_PBUF0
-#define VDC51SC1_SCL1_PBUF1 VDC51.SC1_SCL1_PBUF1
-#define VDC51SC1_SCL1_PBUF2 VDC51.SC1_SCL1_PBUF2
-#define VDC51SC1_SCL1_PBUF3 VDC51.SC1_SCL1_PBUF3
-#define VDC51SC1_SCL1_PBUF_FLD VDC51.SC1_SCL1_PBUF_FLD
-#define VDC51SC1_SCL1_PBUF_CNT VDC51.SC1_SCL1_PBUF_CNT
-#define VDC51GR1_UPDATE VDC51.GR1_UPDATE
-#define VDC51GR1_FLM_RD VDC51.GR1_FLM_RD
-#define VDC51GR1_FLM1 VDC51.GR1_FLM1
-#define VDC51GR1_FLM2 VDC51.GR1_FLM2
-#define VDC51GR1_FLM3 VDC51.GR1_FLM3
-#define VDC51GR1_FLM4 VDC51.GR1_FLM4
-#define VDC51GR1_FLM5 VDC51.GR1_FLM5
-#define VDC51GR1_FLM6 VDC51.GR1_FLM6
-#define VDC51GR1_AB1 VDC51.GR1_AB1
-#define VDC51GR1_AB2 VDC51.GR1_AB2
-#define VDC51GR1_AB3 VDC51.GR1_AB3
-#define VDC51GR1_AB4 VDC51.GR1_AB4
-#define VDC51GR1_AB5 VDC51.GR1_AB5
-#define VDC51GR1_AB6 VDC51.GR1_AB6
-#define VDC51GR1_AB7 VDC51.GR1_AB7
-#define VDC51GR1_AB8 VDC51.GR1_AB8
-#define VDC51GR1_AB9 VDC51.GR1_AB9
-#define VDC51GR1_AB10 VDC51.GR1_AB10
-#define VDC51GR1_AB11 VDC51.GR1_AB11
-#define VDC51GR1_BASE VDC51.GR1_BASE
-#define VDC51GR1_CLUT VDC51.GR1_CLUT
-#define VDC51GR1_MON VDC51.GR1_MON
-#define VDC51ADJ1_UPDATE VDC51.ADJ1_UPDATE
-#define VDC51ADJ1_BKSTR_SET VDC51.ADJ1_BKSTR_SET
-#define VDC51ADJ1_ENH_TIM1 VDC51.ADJ1_ENH_TIM1
-#define VDC51ADJ1_ENH_TIM2 VDC51.ADJ1_ENH_TIM2
-#define VDC51ADJ1_ENH_TIM3 VDC51.ADJ1_ENH_TIM3
-#define VDC51ADJ1_ENH_SHP1 VDC51.ADJ1_ENH_SHP1
-#define VDC51ADJ1_ENH_SHP2 VDC51.ADJ1_ENH_SHP2
-#define VDC51ADJ1_ENH_SHP3 VDC51.ADJ1_ENH_SHP3
-#define VDC51ADJ1_ENH_SHP4 VDC51.ADJ1_ENH_SHP4
-#define VDC51ADJ1_ENH_SHP5 VDC51.ADJ1_ENH_SHP5
-#define VDC51ADJ1_ENH_SHP6 VDC51.ADJ1_ENH_SHP6
-#define VDC51ADJ1_ENH_LTI1 VDC51.ADJ1_ENH_LTI1
-#define VDC51ADJ1_ENH_LTI2 VDC51.ADJ1_ENH_LTI2
-#define VDC51ADJ1_MTX_MODE VDC51.ADJ1_MTX_MODE
-#define VDC51ADJ1_MTX_YG_ADJ0 VDC51.ADJ1_MTX_YG_ADJ0
-#define VDC51ADJ1_MTX_YG_ADJ1 VDC51.ADJ1_MTX_YG_ADJ1
-#define VDC51ADJ1_MTX_CBB_ADJ0 VDC51.ADJ1_MTX_CBB_ADJ0
-#define VDC51ADJ1_MTX_CBB_ADJ1 VDC51.ADJ1_MTX_CBB_ADJ1
-#define VDC51ADJ1_MTX_CRR_ADJ0 VDC51.ADJ1_MTX_CRR_ADJ0
-#define VDC51ADJ1_MTX_CRR_ADJ1 VDC51.ADJ1_MTX_CRR_ADJ1
-#define VDC51GR_VIN_UPDATE VDC51.GR_VIN_UPDATE
-#define VDC51GR_VIN_AB1 VDC51.GR_VIN_AB1
-#define VDC51GR_VIN_AB2 VDC51.GR_VIN_AB2
-#define VDC51GR_VIN_AB3 VDC51.GR_VIN_AB3
-#define VDC51GR_VIN_AB4 VDC51.GR_VIN_AB4
-#define VDC51GR_VIN_AB5 VDC51.GR_VIN_AB5
-#define VDC51GR_VIN_AB6 VDC51.GR_VIN_AB6
-#define VDC51GR_VIN_AB7 VDC51.GR_VIN_AB7
-#define VDC51GR_VIN_BASE VDC51.GR_VIN_BASE
-#define VDC51GR_VIN_MON VDC51.GR_VIN_MON
-#define VDC51OIR_SCL0_UPDATE VDC51.OIR_SCL0_UPDATE
-#define VDC51OIR_SCL0_FRC1 VDC51.OIR_SCL0_FRC1
-#define VDC51OIR_SCL0_FRC2 VDC51.OIR_SCL0_FRC2
-#define VDC51OIR_SCL0_FRC3 VDC51.OIR_SCL0_FRC3
-#define VDC51OIR_SCL0_FRC4 VDC51.OIR_SCL0_FRC4
-#define VDC51OIR_SCL0_FRC5 VDC51.OIR_SCL0_FRC5
-#define VDC51OIR_SCL0_FRC6 VDC51.OIR_SCL0_FRC6
-#define VDC51OIR_SCL0_FRC7 VDC51.OIR_SCL0_FRC7
-#define VDC51OIR_SCL0_DS1 VDC51.OIR_SCL0_DS1
-#define VDC51OIR_SCL0_DS2 VDC51.OIR_SCL0_DS2
-#define VDC51OIR_SCL0_DS3 VDC51.OIR_SCL0_DS3
-#define VDC51OIR_SCL0_DS7 VDC51.OIR_SCL0_DS7
-#define VDC51OIR_SCL0_US1 VDC51.OIR_SCL0_US1
-#define VDC51OIR_SCL0_US2 VDC51.OIR_SCL0_US2
-#define VDC51OIR_SCL0_US3 VDC51.OIR_SCL0_US3
-#define VDC51OIR_SCL0_US8 VDC51.OIR_SCL0_US8
-#define VDC51OIR_SCL0_OVR1 VDC51.OIR_SCL0_OVR1
-#define VDC51OIR_SCL1_UPDATE VDC51.OIR_SCL1_UPDATE
-#define VDC51OIR_SCL1_WR1 VDC51.OIR_SCL1_WR1
-#define VDC51OIR_SCL1_WR2 VDC51.OIR_SCL1_WR2
-#define VDC51OIR_SCL1_WR3 VDC51.OIR_SCL1_WR3
-#define VDC51OIR_SCL1_WR4 VDC51.OIR_SCL1_WR4
-#define VDC51OIR_SCL1_WR5 VDC51.OIR_SCL1_WR5
-#define VDC51OIR_SCL1_WR6 VDC51.OIR_SCL1_WR6
-#define VDC51OIR_SCL1_WR7 VDC51.OIR_SCL1_WR7
-#define VDC51GR_OIR_UPDATE VDC51.GR_OIR_UPDATE
-#define VDC51GR_OIR_FLM_RD VDC51.GR_OIR_FLM_RD
-#define VDC51GR_OIR_FLM1 VDC51.GR_OIR_FLM1
-#define VDC51GR_OIR_FLM2 VDC51.GR_OIR_FLM2
-#define VDC51GR_OIR_FLM3 VDC51.GR_OIR_FLM3
-#define VDC51GR_OIR_FLM4 VDC51.GR_OIR_FLM4
-#define VDC51GR_OIR_FLM5 VDC51.GR_OIR_FLM5
-#define VDC51GR_OIR_FLM6 VDC51.GR_OIR_FLM6
-#define VDC51GR_OIR_AB1 VDC51.GR_OIR_AB1
-#define VDC51GR_OIR_AB2 VDC51.GR_OIR_AB2
-#define VDC51GR_OIR_AB3 VDC51.GR_OIR_AB3
-#define VDC51GR_OIR_AB7 VDC51.GR_OIR_AB7
-#define VDC51GR_OIR_AB8 VDC51.GR_OIR_AB8
-#define VDC51GR_OIR_AB9 VDC51.GR_OIR_AB9
-#define VDC51GR_OIR_AB10 VDC51.GR_OIR_AB10
-#define VDC51GR_OIR_AB11 VDC51.GR_OIR_AB11
-#define VDC51GR_OIR_BASE VDC51.GR_OIR_BASE
-#define VDC51GR_OIR_CLUT VDC51.GR_OIR_CLUT
-#define VDC51GR_OIR_MON VDC51.GR_OIR_MON
+/* Channel array defines of VDC5 (2)*/
+#ifdef  DECLARE_VDC5_CHANNELS
+volatile struct st_vdc5*  VDC5[ VDC5_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC5_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC5_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_ab7*  VDC50_FROM_GR2_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_AB7_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR2_AB7_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR2_AB7_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_update*  VDC50_FROM_GR2_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR2_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR2_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR2_UPDATE_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS
+volatile struct st_vdc5_from_sc0_scl1_pbuf0*  VDC50_FROM_SC0_SCL1_PBUF0_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_SC0_SCL1_PBUF0_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_sc0_scl0_update*  VDC50_FROM_SC0_SCL0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_SC0_SCL0_UPDATE_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_adj0_update*  VDC50_FROM_ADJ0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_ADJ0_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_ADJ0_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_ADJ0_UPDATE_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_ab7*  VDC50_FROM_GR0_AB7_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_AB7_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR0_AB7_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR0_AB7_ARRAY_CHANNELS */
+
+#ifdef  DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS
+volatile struct st_vdc5_from_gr0_update*  VDC50_FROM_GR0_UPDATE_ARRAY[ VDC5_COUNT ][ VDC50_FROM_GR0_UPDATE_ARRAY_COUNT ] =
+    /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
+    VDC50_FROM_GR0_UPDATE_ARRAY_ADDRESS_LIST;
+    /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
+#endif  /* DECLARE_VDC50_FROM_GR0_UPDATE_ARRAY_CHANNELS */
+/* End of channel array defines of VDC5 (2)*/
+
+
 /* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
 /* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,29 +18,40 @@
 * you agree to the additional terms and conditions found by accessing the
 * following link:
 * http://www.renesas.com/disclaimer*
-* Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
 *******************************************************************************/
 /*******************************************************************************
 * File Name : wdt_iodefine.h
 * $Rev: $
 * $Date::                           $
-* Description : Definition of I/O Register (V1.00a)
+* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
 ******************************************************************************/
 #ifndef WDT_IODEFINE_H
 #define WDT_IODEFINE_H
-
-struct st_wdt
-{                                                          /* WDT              */
-    volatile uint16_t WTCSR;                                  /*  WTCSR           */
-    volatile uint16_t WTCNT;                                  /*  WTCNT           */
-    volatile uint16_t WRCSR;                                  /*  WRCSR           */
-};
-
+/* ->QAC 0639 : Over 127 members (C90) */
+/* ->QAC 0857 : Over 1024 #define (C90) */
+/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
+/* ->SEC M1.10.1 : Not magic number */
 
 #define WDT     (*(struct st_wdt     *)0xFCFE0000uL) /* WDT */
 
 
-#define WDTWTCSR WDT.WTCSR
-#define WDTWTCNT WDT.WTCNT
-#define WDTWRCSR WDT.WRCSR
+#define WDTWTCSR (WDT.WTCSR)
+#define WDTWTCNT (WDT.WTCNT)
+#define WDTWRCSR (WDT.WRCSR)
+
+
+typedef struct st_wdt
+{
+                                                           /* WDT              */
+    volatile uint16_t WTCSR;                                  /*  WTCSR           */
+    volatile uint16_t WTCNT;                                  /*  WTCNT           */
+    volatile uint16_t WRCSR;                                  /*  WRCSR           */
+} r_io_wdt_t;
+
+
+/* <-SEC M1.10.1 */
+/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
+/* <-QAC 0857 */
+/* <-QAC 0639 */
 #endif

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_Renesas_RZ_A1.c	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,243 +0,0 @@
-/**************************************************************************//**
- * @file     mmu_Renesas_RZ_A1.c
- * @brief    MMU Startup File for
- *           mmu_Renesas_RZ_A1 Device Series
- * @version  V1.01
- * @date     2 Aug 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#define Renesas_RZ_A1_SPI_MIO_BASE                 (0x3fe00000UL)                        /*!< (SPI_MIO   ) Base Address */
-#define Renesas_RZ_A1_BSC_BASE                     (0x3ff00000UL)                        /*!< (BSC       ) Base Address */
-#define Renesas_RZ_A1_PERIPH_BASE0                 (0xe8000000UL)                        /*!< (PERIPH0   ) Base Address */
-#define Renesas_RZ_A1_PERIPH_BASE1                 (0xfcf00000UL)                        /*!< (PERIPH1   ) Base Address */
-// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
-// Write-Through support *not* available
-// Write-Back support available.
-// Read allocation support available.
-// Write allocation support available.
-
-//Note: You should use the Shareable attribute carefully.
-//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless the inner cache settings.
-//CA9-RTX uses LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
-//Some A9 implementations does not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
-
-//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
-//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
-//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
-
-
-//Following MMU configuration is expected
-//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
-//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
-//Domain 0 is always the Client domain
-//Descriptors place all memory in domain 0
-//There are no restrictions by privilege level (PL0 can access all memory)
-
-#include <stdint.h>
-#include "VKRZA1H.h"
-
-//Import symbols from linker
-extern uint32_t Image$$VECTORS$$Base;
-extern uint32_t Image$$RO_DATA$$Base;
-extern uint32_t Image$$RW_DATA$$Base;
-extern uint32_t Image$$ZI_DATA$$Base;
-#if !defined ( __ICCARM__ )
-extern uint32_t Image$$TTB$$ZI$$Base;
-#endif 
-
-#if defined( __CC_ARM )
-#elif defined( __ICCARM__ )
-#else
-extern uint32_t Image$$RW_DATA_NC$$Base;
-extern uint32_t Image$$ZI_DATA_NC$$Base;
-#endif
-
-extern uint32_t Image$$VECTORS$$Limit;
-extern uint32_t Image$$RO_DATA$$Limit;
-extern uint32_t Image$$RW_DATA$$Limit;
-extern uint32_t Image$$ZI_DATA$$Limit;
-#if defined( __CC_ARM )
-#else
-extern uint32_t Image$$RW_DATA_NC$$Limit;
-extern uint32_t Image$$ZI_DATA_NC$$Limit;
-#endif
-
-#if defined( __ICCARM__ )
-#define VECTORS_SIZE    (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
-#define RO_DATA_SIZE    (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
-#define RW_DATA_SIZE    (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
-#define ZI_DATA_SIZE    (((uint32_t)Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)Image$$ZI_DATA$$Base >> 20) + 1)
-#else
-#define VECTORS_SIZE    (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
-#define RO_DATA_SIZE    (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
-#define RW_DATA_SIZE    (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
-#define ZI_DATA_SIZE    (((uint32_t)&Image$$ZI_DATA$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA$$Base >> 20) + 1)
-#endif
-
-#if defined( __CC_ARM )
-#else
-#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
-#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
-#endif
-
-static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
-static uint32_t Sect_Normal_NC;  //non-shareable, non-executable, rw, domain 0, base addr 0
-static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
-static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
-static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
-static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
-static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
-
-/* Define global descriptors */
-static uint32_t Page_L1_4k  = 0x0;  //generic
-static uint32_t Page_L1_64k = 0x0;  //generic
-static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
-static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
-
-#if defined ( __ICCARM__ )
-__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
-uint32_t Image$$VECTORS$$Base;
-uint32_t Image$$RO_DATA$$Base;
-uint32_t Image$$RW_DATA$$Base;
-uint32_t Image$$ZI_DATA$$Base;
-
-uint32_t Image$$VECTORS$$Limit;
-uint32_t Image$$RO_DATA$$Limit;
-uint32_t Image$$RW_DATA$$Limit;
-uint32_t Image$$ZI_DATA$$Limit;
-#endif
-
-void create_translation_table(void)
-{
-    mmu_region_attributes_Type region;
-#if defined ( __ICCARM__ )
-#pragma section=".intvec"
-#pragma section=".rodata"
-#pragma section=".rwdata"
-#pragma section=".bss"
-
-    Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
-    Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
-    Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
-    Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
-    Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); 
-    Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
-    Image$$ZI_DATA$$Base = (uint32_t) __section_begin(".bss");  
-    Image$$ZI_DATA$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
-#endif
-    /*
-     * Generate descriptors. Refer to VKRZA1H.h to get information about attributes
-     *
-     */
-    //Create descriptors for Vectors, RO, RW, ZI sections
-    section_normal(Sect_Normal, region);
-    section_normal_cod(Sect_Normal_Cod, region);
-    section_normal_ro(Sect_Normal_RO, region);
-    section_normal_rw(Sect_Normal_RW, region);
-    //Create descriptors for peripherals
-    section_device_ro(Sect_Device_RO, region);
-    section_device_rw(Sect_Device_RW, region);
-    section_normal_nc(Sect_Normal_NC, region);
-    //Create descriptors for 64k pages
-    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
-    //Create descriptors for 4k pages
-    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
-
-    /*
-     *  Define MMU flat-map regions and attributes
-     *
-     */
-
-    //Create 4GB of faulting entries
-    __TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
-
-    // R7S72100 memory map.
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE0    , 64, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_NORFLASH_BASE1    , 64, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE0       , 64, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SDRAM_BASE1       , 64, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA0        , 64, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_USER_AREA1        , 64, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO0           , 64, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_IO1           , 64, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_BASE  , 10, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_SPI_MIO_BASE      ,  1, Sect_Device_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_BSC_BASE          ,  1, Sect_Device_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE0      ,  3, Sect_Device_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_PERIPH_BASE1      , 49, Sect_Device_RW);
-
-#if defined( __ICCARM__ )
-    //Define Image
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
-#else
-    //Define Image
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base, RO_DATA_SIZE, Sect_Normal_RO);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base, VECTORS_SIZE, Sect_Normal_Cod);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base, RW_DATA_SIZE, Sect_Normal_RW);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA$$Base, ZI_DATA_SIZE, Sect_Normal_RW);
-#endif
-
-#if defined( __CC_ARM )
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
-#elif defined ( __ICCARM__ ) 
-    __TTSection (&Image$$TTB$$ZI$$Base, Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE,         10, Sect_Normal_NC);
-
-#else
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
-    __TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
-#endif
-
-    /* Set location of level 1 page table
-    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
-    ; 13:7  - 0x0
-    ; 6     - IRGN[0] 0x0 (Inner WB WA)
-    ; 5     - NOS     0x0 (Non-shared)
-    ; 4:3   - RGN     0x1 (Outer WB WA)
-    ; 2     - IMP     0x0 (Implementation Defined)
-    ; 1     - S       0x0 (Non-shared)
-    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
-    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
-
-    /* Set up domain access control register
-    ; We set domain 0 to Client and all other domains to No Access.
-    ; All translation table entries specify domain 0 */
-    __set_DACR(1);
-}
-
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,281 @@
+/**************************************************************************//**
+ * @file     mmu_VK_RZ_A1H.c
+ * @brief    MMU Configuration for RZ_A1H Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+   *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf
+
+                                                     Memory Type
+0xffffffff |--------------------------|             ------------
+           |        Peripherals       |                Device
+0xfcf00000 |--------------------------|             ------------
+           |        Page Fault        |                Fault
+0xe8300000 |--------------------------|             ------------
+           |        Peripherals       |                Device
+0xe8000000 |--------------------------|             ------------
+           |        Page Fault        |                Fault
+0x60A00000 |--------------------------|             ------------
+           | On Chip RAM (10M) Mirror |                Fault
+0x60000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                Fault
+0x5c000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                Fault
+0x58000000 |--------------------------|             ------------
+           |        CS5 Mirror        |                Fault
+0x54000000 |--------------------------|             ------------
+           |        CS4 Mirror        |                Fault
+0x50000000 |--------------------------|             ------------
+           |        CS3 Mirror        |                Fault
+0x4c000000 |--------------------------|             ------------
+           |        CS2 Mirror        |                Fault
+0x48000000 |--------------------------|             ------------
+           |        CS1 Mirror        |                Fault
+0x44000000 |--------------------------|             ------------
+           |        CS0 Mirror        |                Fault
+0x40000000 |--------------------------|             ------------
+           |          BSC             |                 RW
+0x3ff00000 |--------------------------|             ------------
+           |      SPI_MIO_BASE        |                 RW
+0x3fe00000 |--------------------------|             ------------
+           |        Page Fault        |                Fault
+0x20A00000 |--------------------------|             ------------
+           |    On Chip RAM (10M)     |                 RW
+0x20000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                 RO
+0x1c000000 |--------------------------|             ------------
+           |  SPI multi I/O 64MB      |                 RO
+0x18000000 |--------------------------|             ------------
+           |  CS5 User Area 64MB      |                 RW
+0x14000000 |--------------------------|             ------------
+           |  CS4 User Area 64MB      |                 RW
+0x10000000 |--------------------------|             ------------
+           |      CS3 SDRAM 64MB      |                 RW
+0x0c000000 |--------------------------|             ------------
+           |      CS2 SDRAM 64MB      |                 RW
+0x08000000 |--------------------------|             ------------
+           |  CS1 NOR Flash 64MB      |                 RO
+0x04000000 |--------------------------|             ------------
+           |  CS0 NOR Flash 64MB      |                 RO
+0x00000000 |--------------------------|             ------------
+*/
+
+// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
+// Write-Through support *not* available
+// Write-Back support available.
+// Read allocation support available.
+// Write allocation support available.
+
+//Note: You should use the Shareable attribute carefully.
+//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
+//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
+//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
+
+//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
+//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
+//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
+
+
+//Following MMU configuration is expected
+//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
+//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
+//Domain 0 is always the Client domain
+//Descriptors should place all memory in domain 0
+//There are no restrictions by privilege level (PL0 can access all memory)
+
+
+#include "VK_RZ_A1H.h"
+
+//Import symbols from linker
+extern uint32_t Image$$VECTORS$$Base;
+extern uint32_t Image$$RO_DATA$$Base;
+extern uint32_t Image$$RW_DATA$$Base;
+extern uint32_t Image$$RW_IRAM1$$Base;
+#if !defined ( __ICCARM__ )
+extern uint32_t Image$$TTB$$ZI$$Base;
+#endif 
+
+#if defined( __CC_ARM )
+#elif defined( __ICCARM__ )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Base;
+extern uint32_t Image$$ZI_DATA_NC$$Base;
+#endif
+
+extern uint32_t Image$$VECTORS$$Limit;
+extern uint32_t Image$$RO_DATA$$Limit;
+extern uint32_t Image$$RW_DATA$$Limit;
+extern uint32_t Image$$RW_IRAM1$$Limit;
+#if defined( __CC_ARM )
+#else
+extern uint32_t Image$$RW_DATA_NC$$Limit;
+extern uint32_t Image$$ZI_DATA_NC$$Limit;
+#endif
+
+#if defined( __ICCARM__ )
+#define VECTORS_SIZE    (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE    (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE    (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
+#define RW_IRAM1_SIZE   (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1)
+#else
+#define VECTORS_SIZE    (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
+#define RO_DATA_SIZE    (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
+#define RW_DATA_SIZE    (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
+#define RW_IRAM1_SIZE   (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
+#endif
+
+#if defined( __CC_ARM )
+#else
+#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
+#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
+#endif
+
+static uint32_t Sect_Normal;     //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_NC;  //non-shareable, non-executable, rw, domain 0, base addr 0
+static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
+static uint32_t Sect_Normal_RO;  //as Sect_Normal_Cod, but not executable
+static uint32_t Sect_Normal_RW;  //as Sect_Normal_Cod, but writeable and not executable
+static uint32_t Sect_Device_RO;  //device, non-shareable, non-executable, ro, domain 0, base addr 0
+static uint32_t Sect_Device_RW;  //as Sect_Device_RO, but writeable
+
+/* Define global descriptors */
+static uint32_t Page_L1_4k  = 0x0;  //generic
+static uint32_t Page_L1_64k = 0x0;  //generic
+static uint32_t Page_4k_Device_RW;  //Shared device, not executable, rw, domain 0
+static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
+
+#if defined ( __ICCARM__ )
+__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
+uint32_t Image$$VECTORS$$Base;
+uint32_t Image$$RO_DATA$$Base;
+uint32_t Image$$RW_DATA$$Base;
+uint32_t Image$$RW_IRAM1$$Base;
+
+uint32_t Image$$VECTORS$$Limit;
+uint32_t Image$$RO_DATA$$Limit;
+uint32_t Image$$RW_DATA$$Limit;
+uint32_t Image$$RW_IRAM1$$Limit;
+#endif
+
+void MMU_CreateTranslationTable(void)
+{
+    mmu_region_attributes_Type region;
+#if defined ( __ICCARM__ )
+#pragma section=".intvec"
+#pragma section=".rodata"
+#pragma section=".rwdata"
+#pragma section=".bss"
+
+    Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
+    Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
+    Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
+    Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
+    Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata"); 
+    Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
+    Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss");  
+    Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
+#endif
+    /*
+     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     *
+     */
+    //Create descriptors for Vectors, RO, RW, ZI sections
+    section_normal(Sect_Normal, region);
+    section_normal_cod(Sect_Normal_Cod, region);
+    section_normal_ro(Sect_Normal_RO, region);
+    section_normal_rw(Sect_Normal_RW, region);
+    //Create descriptors for peripherals
+    section_device_ro(Sect_Device_RO, region);
+    section_device_rw(Sect_Device_RW, region);
+    section_normal_nc(Sect_Normal_NC, region);
+    //Create descriptors for 64k pages
+    page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
+    //Create descriptors for 4k pages
+    page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
+
+    /*
+     *  Define MMU flat-map regions and attributes
+     *
+     */
+
+    //Create 4GB of faulting entries
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
+
+    // R7S72100 memory map.
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0    , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1    , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0       , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1       , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0        , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1        , 64, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0           , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1           , 64, Sect_Normal_RO);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE  , 10, Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE      ,  1, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE          ,  1, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0      ,  3, Sect_Device_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1      , 49, Sect_Device_RW);
+
+#if defined( __ICCARM__ )
+    //Define Image
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
+#else
+    //Define Image
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
+#endif
+
+#if defined( __CC_ARM )
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE         ,              10, Sect_Normal_NC);
+#elif defined ( __ICCARM__ ) 
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE         ,              10, Sect_Normal_NC);
+
+#else
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
+    MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
+#endif
+
+    /* Set location of level 1 page table
+    ; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
+    ; 13:7  - 0x0
+    ; 6     - IRGN[0] 0x0 (Inner WB WA)
+    ; 5     - NOS     0x0 (Non-shared)
+    ; 4:3   - RGN     0x1 (Outer WB WA)
+    ; 2     - IMP     0x0 (Implementation Defined)
+    ; 1     - S       0x0 (Non-shared)
+    ; 0     - IRGN[1] 0x1 (Inner WB WA) */
+    __set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
+    __ISB();
+
+    /* Set up domain access control register
+    ; We set domain 0 to Client and all other domains to No Access.
+    ; All translation table entries specify domain 0 */
+    __set_DACR(1);
+    __ISB();
+}

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c	Thu Apr 19 17:12:19 2018 +0100
@@ -33,7 +33,6 @@
 #include "VKRZA1H.h"
 #include "wdt_iodefine.h"
 #include "nvic_wrapper.h"
-#include "gic.h"
 
 /******************************************************************************
 Typedef definitions
@@ -71,7 +70,7 @@
 
 uint32_t NVIC_GetPriorityGrouping(void)
 {
-    return GIC_GetBinaryPoint(0);
+    return GIC_GetBinaryPoint();
 }
 
 
@@ -214,14 +213,16 @@
 }
 
 
-int32_t ITM_ReceiveChar (void) {
+int32_t ITM_ReceiveChar (void)
+{
     /* Not support this function */
     /* Use mbed Serial */
     return (-1);    /* no character available */
 }
 
 
-int32_t ITM_CheckChar (void) {
+int32_t ITM_CheckChar (void)
+{
     /* Not support this function */
     /* Use mbed Serial */
     return (0);                                 /* no character available */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,201 @@
+/**************************************************************************//**
+ * @file     os_tick_ostm.c
+ * @brief    CMSIS OS Tick implementation for OS Timer
+ * @version  V1.0.1
+ * @date     19. September 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifdef MBED_CONF_RTOS_PRESENT
+
+#include "os_tick.h"
+#include "irq_ctrl.h"
+
+#include <VKRZA1H.h>
+
+#include <cmsis.h>
+
+
+// Define OS TImer interrupt priority
+#ifndef OSTM_IRQ_PRIORITY
+#define OSTM_IRQ_PRIORITY           0xFFU
+#endif
+
+// Define OS Timer channel and interrupt number
+#define OSTM                        (OSTM0)
+#define OSTM_IRQn                   ((IRQn_ID_t)OSTMI0TINT_IRQn)
+
+
+static uint32_t OSTM_Clock;         // Timer tick frequency
+static uint8_t  OSTM_PendIRQ;       // Timer interrupt pending flag
+
+
+// Setup OS Tick.
+int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
+{
+  uint32_t clock;
+  uint32_t prio;
+  uint32_t bits;
+
+  if (freq == 0U) {
+    return (-1);
+  }
+  
+  OSTM_PendIRQ = 0U;
+
+  // Get CPG.FRQCR[IFC] bits
+  clock = (CPG.FRQCR >> 8) & 0x03;
+
+  // Determine Divider 2 output clock by using SystemCoreClock
+  if (clock == 0x03U) {
+    clock = (SystemCoreClock * 3U);
+  }
+  else if (clock == 0x01U) {
+    clock = (SystemCoreClock * 3U)/2U;
+  }
+  else {
+    clock = SystemCoreClock;
+  }
+
+  // Determine tick frequency
+  clock = clock / freq;
+
+  // Save frequency for later
+  OSTM_Clock = clock;
+
+  // Enable OSTM clock
+  CPG.STBCR5 &= ~(CPG_STBCR5_BIT_MSTP51);
+
+  // Stop the OSTM counter
+  OSTM.OSTMnTT  = 0x01U;
+
+  // Set interval timer mode and disable interrupts when counting starts
+  OSTM.OSTMnCTL = 0x00U;
+
+  // Set compare value
+  OSTM.OSTMnCMP = clock - 1U;
+
+  // Disable corresponding IRQ
+  IRQ_Disable     (OSTM_IRQn);
+  IRQ_ClearPending(OSTM_IRQn);
+
+  // Determine number of implemented priority bits
+  IRQ_SetPriority (OSTM_IRQn, 0xFFU);
+
+  prio = IRQ_GetPriority (OSTM_IRQn);
+
+  // At least bits [7:4] must be implemented
+  if ((prio & 0xF0U) == 0U) {
+    return (-1);
+  }
+
+  for (bits = 0; bits < 4; bits++) {
+    if ((prio & 0x01) != 0) {
+      break;
+    }
+    prio >>= 1;
+  }
+  
+  // Adjust configured priority to the number of implemented priority bits
+  prio = (OSTM_IRQ_PRIORITY << bits) & 0xFFUL;
+
+  // Set OSTM interrupt priority
+  IRQ_SetPriority(OSTM_IRQn, prio-1U);
+
+  // Set edge-triggered, non-secure, single CPU targeted IRQ
+  IRQ_SetMode (OSTM_IRQn, IRQ_MODE_TRIG_EDGE);
+
+  // Register tick interrupt handler function
+  IRQ_SetHandler(OSTM_IRQn, (IRQHandler_t)handler);
+
+  // Enable corresponding IRQ
+  IRQ_Enable (OSTM_IRQn);
+
+  return (0);
+}
+
+/// Enable OS Tick.
+int32_t  OS_Tick_Enable (void)
+{
+
+  if (OSTM_PendIRQ != 0U) {
+    OSTM_PendIRQ = 0U;
+    IRQ_SetPending (OSTM_IRQn);
+  }
+
+  // Start the OSTM counter
+  OSTM.OSTMnTS = 0x01U;
+
+  return (0);
+}
+
+/// Disable OS Tick.
+int32_t  OS_Tick_Disable (void)
+{
+
+  // Stop the OSTM counter
+  OSTM.OSTMnTT = 0x01U;
+
+  if (IRQ_GetPending(OSTM_IRQn) != 0) {
+    IRQ_ClearPending (OSTM_IRQn);
+    OSTM_PendIRQ = 1U;
+  }
+
+  return (0);
+}
+
+// Acknowledge OS Tick IRQ.
+int32_t OS_Tick_AcknowledgeIRQ (void)
+{
+  return (IRQ_ClearPending (OSTM_IRQn));
+}
+
+// Get OS Tick IRQ number.
+int32_t  OS_Tick_GetIRQn (void)
+{
+  return (OSTM_IRQn);
+}
+
+// Get OS Tick clock.
+uint32_t OS_Tick_GetClock (void)
+{
+  return (OSTM_Clock);
+}
+
+// Get OS Tick interval.
+uint32_t OS_Tick_GetInterval (void)
+{
+  return (OSTM.OSTMnCMP + 1U);
+}
+
+// Get OS Tick count value.
+uint32_t OS_Tick_GetCount (void)
+{
+  uint32_t cmp = OSTM.OSTMnCMP;
+  return  (cmp - OSTM.OSTMnCNT);
+}
+
+// Get OS Tick overflow status.
+uint32_t OS_Tick_GetOverflow (void)
+{
+  return (IRQ_GetPending(OSTM_IRQn));
+}
+
+#endif
+

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.c	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,128 +0,0 @@
-/**************************************************************************//**
- * @file     pl310.c
- * @brief    Implementation of PL310 PrimeCell Level 2 Cache Controller functions
- * @version
- * @date     3 December 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-#include "VKRZA1H.h"
-
-//Cache Sync operation
-void PL310_Sync(void)
-{
-    PL310->CACHE_SYNC = 0x0;
-}
-
-//return Cache controller cache ID
-int PL310_GetID (void)
-{
-    return PL310->CACHE_ID;
-}
-
-//return Cache controller cache Type
-int PL310_GetType (void)
-{
-    return PL310->CACHE_TYPE;
-}
-
-//Invalidate all cache by way
-void PL310_InvAllByWay (void)
-{
-    unsigned int assoc;
-
-    if (PL310->AUX_CNT & (1<<16))
-        assoc = 16;
-    else
-        assoc =  8;
-
-    PL310->INV_WAY = (1 << assoc) - 1;
-    while(PL310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
-
-    PL310_Sync();
-}
-
-//Clean and Invalidate all cache by way
-void PL310_CleanInvAllByWay (void)
-{
-    unsigned int assoc;
-
-    if (PL310->AUX_CNT & (1<<16))
-        assoc = 16;
-    else
-        assoc =  8;
-
-    PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
-    while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
-
-    PL310_Sync();
-}
-
-//Enable Cache
-void PL310_Enable(void)
-{
-    PL310->CONTROL = 0;
-    PL310->INTERRUPT_CLEAR = 0x000001FFuL;
-    PL310->DEBUG_CONTROL = 0;
-    PL310->DATA_LOCK_0_WAY = 0;
-    PL310->CACHE_SYNC = 0;
-
-    PL310->CONTROL = 0x01;
-    PL310_Sync();
-}
-//Disable Cache
-void PL310_Disable(void)
-{
-    PL310->CONTROL = 0x00;
-    PL310_Sync();
-}
-
-//Invalidate cache by physical address
-void PL310_InvPa (void *pa)
-{
-    PL310->INV_LINE_PA = (unsigned int)pa;
-    PL310_Sync();
-}
-
-//Clean cache by physical address
-void PL310_CleanPa (void *pa)
-{
-    PL310->CLEAN_LINE_PA = (unsigned int)pa;
-    PL310_Sync();
-}
-
-//Clean and invalidate cache by physical address
-void PL310_CleanInvPa (void *pa)
-{
-    PL310->CLEAN_INV_LINE_PA = (unsigned int)pa;
-    PL310_Sync();
-}
-
-

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/pl310.h	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,114 +0,0 @@
-/**************************************************************************//**
- * @file     pl310.h
- * @brief    Implementation of pl310 functions
- * @version
- * @date     11 June 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-#ifndef __PL310
-#define __PL310
-
-typedef struct
-{
-  __I  uint32_t CACHE_ID;                   /*!< Offset: 0x0000   Cache ID Register               */
-  __I  uint32_t CACHE_TYPE;                 /*!< Offset: 0x0004   Cache Type Register             */
-       uint32_t RESERVED0[0x3e];
-  __IO uint32_t CONTROL;                    /*!< Offset: 0x0100   Control Register                */
-  __IO uint32_t AUX_CNT;                    /*!< Offset: 0x0104   Auxiliary Control               */
-       uint32_t RESERVED1[0x3e];
-  __IO uint32_t EVENT_CONTROL;              /*!< Offset: 0x0200   Event Counter Control           */
-  __IO uint32_t EVENT_COUNTER1_CONF;        /*!< Offset: 0x0204   Event Counter 1 Configuration   */
-  __IO uint32_t EVENT_COUNTER0_CONF;        /*!< Offset: 0x0208   Event Counter 1 Configuration   */
-       uint32_t RESERVED2[0x2];
-  __IO uint32_t INTERRUPT_MASK;             /*!< Offset: 0x0214   Interrupt Mask                  */
-  __I  uint32_t MASKED_INT_STATUS;          /*!< Offset: 0x0218   Masked Interrupt Status         */
-  __I  uint32_t RAW_INT_STATUS;             /*!< Offset: 0x021c   Raw Interrupt Status            */
-  __O  uint32_t INTERRUPT_CLEAR;            /*!< Offset: 0x0220   Interrupt Clear                 */
-       uint32_t RESERVED3[0x143];
-  __IO uint32_t CACHE_SYNC;                 /*!< Offset: 0x0730   Cache Sync                      */
-       uint32_t RESERVED4[0xf];
-  __IO uint32_t INV_LINE_PA;                /*!< Offset: 0x0770   Invalidate Line By PA           */
-       uint32_t RESERVED6[2];
-  __IO uint32_t INV_WAY;                    /*!< Offset: 0x077c   Invalidate by Way               */
-       uint32_t RESERVED5[0xc];
-  __IO uint32_t CLEAN_LINE_PA;              /*!< Offset: 0x07b0   Clean Line by PA                */
-       uint32_t RESERVED7[1];
-  __IO uint32_t CLEAN_LINE_INDEX_WAY;       /*!< Offset: 0x07b8   Clean Line by Index/Way         */
-  __IO uint32_t CLEAN_WAY;                  /*!< Offset: 0x07bc   Clean by Way                    */
-       uint32_t RESERVED8[0xc];
-  __IO uint32_t CLEAN_INV_LINE_PA;          /*!< Offset: 0x07f0   Clean and Invalidate Line by PA  */
-       uint32_t RESERVED9[1];
-  __IO uint32_t CLEAN_INV_LINE_INDEX_WAY;   /*!< Offset: 0x07f8   Clean and Invalidate Line by Index/Way  */
-  __IO uint32_t CLEAN_INV_WAY;              /*!< Offset: 0x07fc   Clean and Invalidate by Way     */
-       uint32_t RESERVED10[0x40];
-  __IO uint32_t DATA_LOCK_0_WAY;            /*!< Offset: 0x0900   Data Lockdown 0 by Way          */
-  __IO uint32_t INST_LOCK_0_WAY;            /*!< Offset: 0x0904   Instruction Lockdown 0 by Way   */
-  __IO uint32_t DATA_LOCK_1_WAY;            /*!< Offset: 0x0908   Data Lockdown 1 by Way          */
-  __IO uint32_t INST_LOCK_1_WAY;            /*!< Offset: 0x090c   Instruction Lockdown 1 by Way   */
-  __IO uint32_t DATA_LOCK_2_WAY;            /*!< Offset: 0x0910   Data Lockdown 2 by Way          */
-  __IO uint32_t INST_LOCK_2_WAY;            /*!< Offset: 0x0914   Instruction Lockdown 2 by Way   */
-  __IO uint32_t DATA_LOCK_3_WAY;            /*!< Offset: 0x0918   Data Lockdown 3 by Way          */
-  __IO uint32_t INST_LOCK_3_WAY;            /*!< Offset: 0x091c   Instruction Lockdown 3 by Way   */
-  __IO uint32_t DATA_LOCK_4_WAY;            /*!< Offset: 0x0920   Data Lockdown 4 by Way          */
-  __IO uint32_t INST_LOCK_4_WAY;            /*!< Offset: 0x0924   Instruction Lockdown 4 by Way   */
-  __IO uint32_t DATA_LOCK_5_WAY;            /*!< Offset: 0x0928   Data Lockdown 5 by Way          */
-  __IO uint32_t INST_LOCK_5_WAY;            /*!< Offset: 0x092c   Instruction Lockdown 5 by Way   */
-  __IO uint32_t DATA_LOCK_6_WAY;            /*!< Offset: 0x0930   Data Lockdown 5 by Way          */
-  __IO uint32_t INST_LOCK_6_WAY;            /*!< Offset: 0x0934   Instruction Lockdown 5 by Way   */
-  __IO uint32_t DATA_LOCK_7_WAY;            /*!< Offset: 0x0938   Data Lockdown 6 by Way          */
-  __IO uint32_t INST_LOCK_7_WAY;            /*!< Offset: 0x093c   Instruction Lockdown 6 by Way   */
-       uint32_t RESERVED11[0x4];
-  __IO uint32_t LOCK_LINE_EN;               /*!< Offset: 0x0950   Lockdown by Line Enable         */
-  __IO uint32_t UNLOCK_ALL_BY_WAY;          /*!< Offset: 0x0954   Unlock All Lines by Way         */
-       uint32_t RESERVED12[0xaa];
-  __IO uint32_t ADDRESS_FILTER_START;       /*!< Offset: 0x0c00   Address Filtering Start         */
-  __IO uint32_t ADDRESS_FILTER_END;         /*!< Offset: 0x0c04   Address Filtering End           */
-       uint32_t RESERVED13[0xce];
-  __IO uint32_t DEBUG_CONTROL;              /*!< Offset: 0x0f40   Debug Control Register          */
-
-} PL310_TypeDef;
-
-#define PL310           ((PL310_TypeDef *)Renesas_RZ_A1_PL310_BASE) /*!< PL310 Declaration */
-
-extern int PL310_GetID (void);
-extern int PL310_GetType (void);
-extern void PL310_InvAllByWay (void);
-extern void PL310_CleanInvAllByWay(void);
-extern void PL310_Enable(void);
-extern void PL310_Disable(void);
-extern void PL310_InvPa (void *);
-extern void PL310_CleanPa (void *);
-extern void PL310_CleanInvPa (void *);
-
-#endif
-
-

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.c	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,521 +0,0 @@
-/**************************************************************************//**
- * @file     system_VKRZA1H.c
- * @brief    CMSIS Device System Source File for
- *           ARM Cortex-A9 Device Series
- * @version  V1.00
- * @date     09 January 2015
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2015 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#include <stdint.h>
-#include "VKRZA1H.h"
-#include "RZ_A1_Init.h"
-
-
-#if defined(__ARMCC_VERSION)
-extern void $Super$$main(void);
-__asm void FPUEnable(void);
-#else 
-void FPUEnable(void); 
-
-#endif
-
-#define FRQCR_IFC_MSK          (0x0030)
-#define FRQCR_IFC_SHFT         (8)
-#define FRQCR_IFC_1P1          (0) /* x1/1 */
-#define FRQCR_IFC_2P3          (1) /* x2/3 */
-#define FRQCR_IFC_1P3          (3) /* x1/3 */
-
-uint32_t IRQNestLevel;
-unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
-uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;     /*!< System Clock Frequency (Core Clock)  */
-
-
-/**
- * Initialize the cache.
- *
- * @param  none
- * @return none
- *
- * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
- */
-#if defined(__ARMCC_VERSION)
-#pragma push
-#pragma arm
-
-void InitMemorySubsystem(void) {
-
-    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
-     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
-     * You are not required to invalidate the main TLB, even though it is recommended for safety
-     * reasons. This ensures compatibility with future revisions of the processor. */
-
-    unsigned int l2_id;
-
-    /* Invalidate undefined data */
-    __ca9u_inv_tlb_all();
-    __v7_inv_icache_all();
-    __v7_inv_dcache_all();
-    __v7_inv_btac();
-
-    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
-     * invalidate in order to flush the valid data to the next level cache.
-     */
-    __enable_mmu();
-
-    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
-    __enable_caches();
-    __enable_btac();
-
-    /* If present, you may also need to Invalidate and Enable L2 cache here */
-    l2_id = PL310_GetID();
-    if (l2_id)
-    {
-       PL310_InvAllByWay();
-       PL310_Enable();
-    }
-}
-#pragma pop
-
-#elif defined(__GNUC__) 
-
-void InitMemorySubsystem(void) { 
- 
-    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before 
-     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. 
-     * You are not required to invalidate the main TLB, even though it is recommended for safety 
-     * reasons. This ensures compatibility with future revisions of the processor. */ 
- 
-    unsigned int l2_id; 
- 
-    /* Invalidate undefined data */ 
-    __ca9u_inv_tlb_all(); 
-    __v7_inv_icache_all(); 
-    __v7_inv_dcache_all(); 
-    __v7_inv_btac(); 
- 
-    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and 
-     * invalidate in order to flush the valid data to the next level cache. 
-     */ 
-    __enable_mmu(); 
- 
-    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ 
-    __enable_caches(); 
-    __enable_btac(); 
- 
-    /* If present, you may also need to Invalidate and Enable L2 cache here */ 
-    l2_id = PL310_GetID(); 
-    if (l2_id) 
-    { 
-       PL310_InvAllByWay(); 
-       PL310_Enable(); 
-    } 
-} 
-#elif defined ( __ICCARM__ )
-
-void InitMemorySubsystem(void) { 
- 
-    /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before 
-     * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC. 
-     * You are not required to invalidate the main TLB, even though it is recommended for safety 
-     * reasons. This ensures compatibility with future revisions of the processor. */ 
- 
-    unsigned int l2_id; 
- 
-    /* Invalidate undefined data */ 
-    __ca9u_inv_tlb_all(); 
-    __v7_inv_icache_all(); 
-    __v7_inv_dcache_all(); 
-    __v7_inv_btac(); 
- 
-    /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and 
-     * invalidate in order to flush the valid data to the next level cache. 
-     */ 
-    __enable_mmu();
- 
-    /* After MMU is enabled and data has been invalidated, enable caches and BTAC */ 
-    __enable_caches(); 
-    __enable_btac(); 
- 
-    /* If present, you may also need to Invalidate and Enable L2 cache here */ 
-    l2_id = PL310_GetID(); 
-    if (l2_id) 
-    { 
-       PL310_InvAllByWay(); 
-       PL310_Enable(); 
-    } 
-} 
-#else 
-
-#endif 
-
-
-IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
-
-uint32_t IRQCount = sizeof IRQTable / 4;
-
-uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
-{
-    if (irq < IRQCount) {
-        IRQTable[irq] = handler;
-        return 0;
-    }
-    else {
-        return 1;
-    }
-}
-
-uint32_t InterruptHandlerUnregister (IRQn_Type irq)
-{
-    if (irq < IRQCount) {
-        IRQTable[irq] = 0;
-        return 0;
-    }
-    else {
-        return 1;
-    }
-}
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock.
- */
-void SystemCoreClockUpdate (void)
-{
-    uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
-
-    switch (frqcr_ifc) {
-        case FRQCR_IFC_1P1:
-            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
-            break;
-        case FRQCR_IFC_2P3:
-            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
-            break;
-        case FRQCR_IFC_1P3:
-            SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK  / 3;
-            break;
-        default:
-            /* do nothing */
-            break;
-    }
-}
-
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System.
- */
-void SystemInit (void)
-{
-    IRQNestLevel = 0;
-/*       do not use global variables because this function is called before
-         reaching pre-main. RW section maybe overwritten afterwards.          */
-    RZ_A1_InitClock();
-    RZ_A1_InitBus();
-
-	//Configure GIC ICDICFR GIC_SetICDICFR()
-    GIC_Enable();
-    __enable_irq();
-
-}
-
-
-//Fault Status Register (IFSR/DFSR) definitions
-#define FSR_ALIGNMENT_FAULT                  0x01   //DFSR only. Fault on first lookup
-#define FSR_INSTRUCTION_CACHE_MAINTENANCE    0x04   //DFSR only - async/external
-#define FSR_SYNC_EXT_TTB_WALK_FIRST          0x0c   //sync/external
-#define FSR_SYNC_EXT_TTB_WALK_SECOND         0x0e   //sync/external
-#define FSR_SYNC_PARITY_TTB_WALK_FIRST       0x1c   //sync/external
-#define FSR_SYNC_PARITY_TTB_WALK_SECOND      0x1e   //sync/external
-#define FSR_TRANSLATION_FAULT_FIRST          0x05   //MMU Fault - internal
-#define FSR_TRANSLATION_FAULT_SECOND         0x07   //MMU Fault - internal
-#define FSR_ACCESS_FLAG_FAULT_FIRST          0x03   //MMU Fault - internal
-#define FSR_ACCESS_FLAG_FAULT_SECOND         0x06   //MMU Fault - internal
-#define FSR_DOMAIN_FAULT_FIRST               0x09   //MMU Fault - internal
-#define FSR_DOMAIN_FAULT_SECOND              0x0b   //MMU Fault - internal
-#define FSR_PERMISION_FAULT_FIRST            0x0f   //MMU Fault - internal
-#define FSR_PERMISION_FAULT_SECOND           0x0d   //MMU Fault - internal
-#define FSR_DEBUG_EVENT                      0x02   //internal
-#define FSR_SYNC_EXT_ABORT                   0x08   //sync/external
-#define FSR_TLB_CONFLICT_ABORT               0x10   //sync/external
-#define FSR_LOCKDOWN                         0x14   //internal
-#define FSR_COPROCESSOR_ABORT                0x1a   //internal
-#define FSR_SYNC_PARITY_ERROR                0x19   //sync/external
-#define FSR_ASYNC_EXTERNAL_ABORT             0x16   //DFSR only - async/external
-#define FSR_ASYNC_PARITY_ERROR               0x18   //DFSR only - async/external
-
-void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
-    uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
-
-    switch(FS) {
-        //Synchronous parity errors - retry
-        case FSR_SYNC_PARITY_ERROR:
-        case FSR_SYNC_PARITY_TTB_WALK_FIRST:
-        case FSR_SYNC_PARITY_TTB_WALK_SECOND:
-            return;
-
-        //Your code here. Value in DFAR is invalid for some fault statuses.
-        case FSR_ALIGNMENT_FAULT:
-        case FSR_INSTRUCTION_CACHE_MAINTENANCE:
-        case FSR_SYNC_EXT_TTB_WALK_FIRST:
-        case FSR_SYNC_EXT_TTB_WALK_SECOND:
-        case FSR_TRANSLATION_FAULT_FIRST:
-        case FSR_TRANSLATION_FAULT_SECOND:
-        case FSR_ACCESS_FLAG_FAULT_FIRST:
-        case FSR_ACCESS_FLAG_FAULT_SECOND:
-        case FSR_DOMAIN_FAULT_FIRST:
-        case FSR_DOMAIN_FAULT_SECOND:
-        case FSR_PERMISION_FAULT_FIRST:
-        case FSR_PERMISION_FAULT_SECOND:
-        case FSR_DEBUG_EVENT:
-        case FSR_SYNC_EXT_ABORT:
-        case FSR_TLB_CONFLICT_ABORT:
-        case FSR_LOCKDOWN:
-        case FSR_COPROCESSOR_ABORT:
-        case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
-        case FSR_ASYNC_PARITY_ERROR:   //DFAR invalid
-        default:
-            while(1);
-    }
-}
-
-void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
-    uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
-
-    switch(FS) {
-        //Synchronous parity errors - retry
-        case FSR_SYNC_PARITY_ERROR:
-        case FSR_SYNC_PARITY_TTB_WALK_FIRST:
-        case FSR_SYNC_PARITY_TTB_WALK_SECOND:
-            return;
-
-        //Your code here. Value in IFAR is invalid for some fault statuses.
-        case FSR_SYNC_EXT_TTB_WALK_FIRST:
-        case FSR_SYNC_EXT_TTB_WALK_SECOND:
-        case FSR_TRANSLATION_FAULT_FIRST:
-        case FSR_TRANSLATION_FAULT_SECOND:
-        case FSR_ACCESS_FLAG_FAULT_FIRST:
-        case FSR_ACCESS_FLAG_FAULT_SECOND:
-        case FSR_DOMAIN_FAULT_FIRST:
-        case FSR_DOMAIN_FAULT_SECOND:
-        case FSR_PERMISION_FAULT_FIRST:
-        case FSR_PERMISION_FAULT_SECOND:
-        case FSR_DEBUG_EVENT: //IFAR invalid
-        case FSR_SYNC_EXT_ABORT:
-        case FSR_TLB_CONFLICT_ABORT:
-        case FSR_LOCKDOWN:
-        case FSR_COPROCESSOR_ABORT:
-        default:
-            while(1);
-    }
-}
-
-//returns amount to decrement lr by
-//this will be 0 when we have emulated the instruction and want to execute the next instruction
-//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
-//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
-uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
-    const unsigned int THUMB = 2;
-    const unsigned int ARM = 4;
-    //Lazy VFP/NEON initialisation and switching
-
-    // (ARM ARM section A7.5) VFP data processing instruction?
-    // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
-    // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
-    // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
-    if ((state == ARM   && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
-        (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
-        if (((opcode & 0x00000E00) >> 9) == 5) {
-            FPUEnable();
-            return state;
-        }
-    }
-
-    // (ARM ARM section A7.4) NEON data processing instruction?
-    if ((state == ARM   && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
-        (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
-    // (ARM ARM section A7.7) NEON load/store instruction?
-        (state == ARM   && ((opcode >> 24) == 0xF4)) ||
-        (state == THUMB && ((opcode >> 24) == 0xF9))) {
-        FPUEnable();
-        return state;
-    }
-
-    //Add code here for other Undef cases
-    while(1);
-}
-
-#if defined(__ARMCC_VERSION)
-#pragma push
-#pragma arm
-//Critical section, called from undef handler, so systick is disabled
-__asm void FPUEnable(void) {
-        ARM
-
-        //Permit access to VFP/NEON, registers by modifying CPACR
-        MRC     p15,0,R1,c1,c0,2
-        ORR     R1,R1,#0x00F00000
-        MCR     p15,0,R1,c1,c0,2
-
-        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
-        ISB
-
-        //Enable VFP/NEON
-        VMRS    R1,FPEXC
-        ORR     R1,R1,#0x40000000
-        VMSR    FPEXC,R1
-
-        //Initialise VFP/NEON registers to 0
-        MOV     R2,#0
-        //Initialise D16 registers to 0
-        VMOV    D0, R2,R2
-        VMOV    D1, R2,R2
-        VMOV    D2, R2,R2
-        VMOV    D3, R2,R2
-        VMOV    D4, R2,R2
-        VMOV    D5, R2,R2
-        VMOV    D6, R2,R2
-        VMOV    D7, R2,R2
-        VMOV    D8, R2,R2
-        VMOV    D9, R2,R2
-        VMOV    D10,R2,R2
-        VMOV    D11,R2,R2
-        VMOV    D12,R2,R2
-        VMOV    D13,R2,R2
-        VMOV    D14,R2,R2
-        VMOV    D15,R2,R2
-        //Initialise D32 registers to 0
-        VMOV    D16,R2,R2
-        VMOV    D17,R2,R2
-        VMOV    D18,R2,R2
-        VMOV    D19,R2,R2
-        VMOV    D20,R2,R2
-        VMOV    D21,R2,R2
-        VMOV    D22,R2,R2
-        VMOV    D23,R2,R2
-        VMOV    D24,R2,R2
-        VMOV    D25,R2,R2
-        VMOV    D26,R2,R2
-        VMOV    D27,R2,R2
-        VMOV    D28,R2,R2
-        VMOV    D29,R2,R2
-        VMOV    D30,R2,R2
-        VMOV    D31,R2,R2
-        //Initialise FPSCR to a known state
-        VMRS    R2,FPSCR
-        LDR     R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-        AND     R2,R2,R3
-        VMSR    FPSCR,R2
-
-        BX      LR
-}
-#pragma pop
-
-#elif defined(__GNUC__)
-void FPUEnable(void) {
-    __asm__ (
-        ".ARM;"
-
-        //Permit access to VFP/NEON, registers by modifying CPACR
-        "MRC     p15,0,R1,c1,c0,2;"
-        "ORR     R1,R1,#0x00F00000;"
-        "MCR     p15,0,R1,c1,c0,2;"
-
-        //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
-        "ISB;"
-
-        //Enable VFP/NEON
-        "VMRS    R1,FPEXC;"
-        "ORR     R1,R1,#0x40000000;"
-        "VMSR    FPEXC,R1;"
-
-        //Initialise VFP/NEON registers to 0
-        "MOV     R2,#0;"
-        //Initialise D16 registers to 0
-        "VMOV    D0, R2,R2;"
-        "VMOV    D1, R2,R2;"
-        "VMOV    D2, R2,R2;"
-        "VMOV    D3, R2,R2;"
-        "VMOV    D4, R2,R2;"
-        "VMOV    D5, R2,R2;"
-        "VMOV    D6, R2,R2;"
-        "VMOV    D7, R2,R2;"
-        "VMOV    D8, R2,R2;"
-        "VMOV    D9, R2,R2;"
-        "VMOV    D10,R2,R2;"
-        "VMOV    D11,R2,R2;"
-        "VMOV    D12,R2,R2;"
-        "VMOV    D13,R2,R2;"
-        "VMOV    D14,R2,R2;"
-        "VMOV    D15,R2,R2;"
-        //Initialise D32 registers to 0
-        "VMOV    D16,R2,R2;"
-        "VMOV    D17,R2,R2;"
-        "VMOV    D18,R2,R2;"
-        "VMOV    D19,R2,R2;"
-        "VMOV    D20,R2,R2;"
-        "VMOV    D21,R2,R2;"
-        "VMOV    D22,R2,R2;"
-        "VMOV    D23,R2,R2;"
-        "VMOV    D24,R2,R2;"
-        "VMOV    D25,R2,R2;"
-        "VMOV    D26,R2,R2;"
-        "VMOV    D27,R2,R2;"
-        "VMOV    D28,R2,R2;"
-        "VMOV    D29,R2,R2;"
-        "VMOV    D30,R2,R2;"
-        "VMOV    D31,R2,R2;"
-
-        //Initialise FPSCR to a known state
-        "VMRS    R2,FPSCR;"
-        "LDR     R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
-        "AND     R2,R2,R3;"
-        "VMSR    FPSCR,R2;"
-
-        //"BX      LR;"
-             :
-             :
-             :"r1", "r2", "r3");
-    return;
-}
-#else
-#endif
-

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VKRZA1H.h	Tue Mar 20 17:01:51 2018 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,67 +0,0 @@
-/**************************************************************************//**
- * @file     system_VKRZA1H.h
- * @brief    CMSIS Device System Header File for
- *           ARMCA9 Device Series
- * @version  V1.00
- * @date     11 June 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2011 - 2013 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __SYSTEM_VKRZA1H
-#define __SYSTEM_VKRZA1H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
-
-typedef void(*IRQHandler)();
-uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
-uint32_t InterruptHandlerUnregister(IRQn_Type);
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the Systd short        int16_t;emCoreClock variable.
- */
-extern void SystemInit (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_VKRZA1H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,157 @@
+/******************************************************************************
+ * @file     system_VK_RZ_A1H_H.c
+ * @brief    CMSIS Device System Source File for ARM Cortex-A9 Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+   *
+ * SPDX-License-Identifier: Apache-2.0
+   *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <VK_RZ_A1H.h>
+#include "RZ_A1_Init.h"
+#include "irq_ctrl.h"
+
+#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
+#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
+#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
+
+/*
+ Port 0 (P0) MD pin assignment
+ P0_0: MD_BOOT0
+ P0_1: MD_BOOT1
+ P0_2: MD_CLK
+ P0_3: MD_CLKS
+     */
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_P0_CLK;
+
+/*----------------------------------------------------------------------------
+  System Core Clock update function
+ *----------------------------------------------------------------------------*/
+void SystemCoreClockUpdate (void)
+    {
+  uint32_t freq;
+  uint16_t mode;
+  uint16_t ifc;
+
+  mode = (GPIO.PPR0 >> 2U) & 0x01U;
+
+  if (mode == 0) {
+    /* Clock Mode 0 */
+    /* CLKIN is between 10MHz and 13.33MHz */
+    /* Divider 1 uses 1/1 ratio, PLL x30 is ON */
+    freq = CM0_RENESAS_RZ_A1_CLKIN * 30U;
+  } else {
+    /* Clock Mode 1 */
+    /* CLKIN is 48MHz */
+    /* Divider 1 uses 1/4 ratio, PLL x32 is ON */
+    freq = (CM1_RENESAS_RZ_A1_CLKIN * 32U) / 4U;
+} 
+ 
+  /* Get CPG.FRQCR[IFC] bits */
+  ifc = (CPG.FRQCR >> 8U) & 0x03U;
+ 
+  /* Determine Divider 2 output clock */
+  if (ifc == 0x03U) {
+    /* Division ratio is 1/3 */
+    freq = (freq / 3U);
+  }
+  else {
+    if (ifc == 0x01U) {
+      /* Division ratio is 2/3 */
+      freq = (freq * 2U) / 3U;
+    } 
+} 
+
+  SystemCoreClock = freq;
+} 
+
+/*----------------------------------------------------------------------------
+  IRQ Handler Register/Unregister
+ *----------------------------------------------------------------------------*/
+uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
+{
+    return IRQ_SetHandler(irq, handler);
+}
+
+uint32_t InterruptHandlerUnregister (IRQn_Type irq)
+{
+    return IRQ_SetHandler(irq, (IRQHandler_t)NULL);
+}
+
+/*----------------------------------------------------------------------------
+  System Initialization
+ *----------------------------------------------------------------------------*/
+void SystemInit (void)
+{
+/*       do not use global variables because this function is called before
+         reaching pre-main. RW section maybe overwritten afterwards.          */
+
+  // Enable SRAM write access
+  CPG.SYSCR3 = 0x0F;
+
+    RZ_A1_InitClock();
+    RZ_A1_InitBus();
+
+  // Invalidate entire Unified TLB
+  __set_TLBIALL(0);
+
+  // Invalidate entire branch predictor array
+  __set_BPIALL(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate instruction cache and flush branch target cache
+  __set_ICIALLU(0);
+  __DSB();
+  __ISB();
+
+  //  Invalidate data cache
+  L1C_InvalidateDCacheAll();
+
+  // Create Translation Table
+  MMU_CreateTranslationTable();
+
+  // Enable MMU
+  MMU_Enable();
+
+  // Enable Caches
+  L1C_EnableCaches();
+  L1C_EnableBTAC();
+
+#if (__L2C_PRESENT == 1) 
+  L2C_InvAllByWay();
+  // Enable L2C
+  L2C_Enable();
+#endif
+
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  // Enable FPU
+  __FPU_Enable();
+#endif
+
+  // IRQ Initialize
+  IRQ_Initialize();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,81 @@
+/******************************************************************************
+ * @file     system_VK_RZ_A1H.h
+ * @brief    CMSIS Device System Header File for ARM Cortex-A Device Series
+ * @version  V1.00
+ * @date     10 Mar 2017
+ *
+ * @note
+ *
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+   *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+   *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __SYSTEM_VK_RZ_A1H_H
+#define __SYSTEM_VK_RZ_A1H_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+typedef void(*IRQHandler)();         /*!< Type Definition for Interrupt Handlers */
+
+/**
+  \brief Setup the microcontroller system.
+
+   Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+
+/**
+  \brief  Update SystemCoreClock variable.
+
+   Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+/**
+  \brief  Interrupt Handler Register.
+
+   Registers an Interrupt Handler into the IRQ Table.
+ */
+extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
+
+/**
+  \brief  Interrupt Handler Unregister.
+
+   Unregisters an Interrupt Handler from the IRQ Table.
+ */
+extern uint32_t InterruptHandlerUnregister(IRQn_Type);
+
+/**
+  \brief  Create Translation Table.
+
+   Creates Memory Management Unit Translation Table.
+ */
+extern void MMU_CreateTranslationTable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_VK_RZ_A1H_H */

--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/rtc_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -66,7 +66,7 @@
 #define SHIFT_1BYTE      (8u)
 #define SHIFT_2BYTE      (16u)
 
-#define TIME_ERROR_VAL   (0xFFFFFFFFu)
+#define TIME_ERROR_VAL   (0u)
 
 static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val);
 static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val);
@@ -246,7 +246,9 @@
 
     if (err == 0) {
         // Convert to timestamp
-        t = _rtc_mktime(&timeinfo);
+        if (_rtc_maketime(&timeinfo, &t, RTC_FULL_LEAP_YEAR_SUPPORT) == false) {
+            return TIME_ERROR_VAL;
+        }
     } else {
         // Error
         t = TIME_ERROR_VAL;
@@ -337,9 +339,10 @@
 void rtc_write(time_t t) {
 
     struct tm timeinfo;
-    if (_rtc_localtime(t, &timeinfo) == false) {
+    if (_rtc_localtime(t, &timeinfo, RTC_FULL_LEAP_YEAR_SUPPORT) == false) {
         return;
     }
+
     volatile uint16_t dummy_read;
 
     if (rtc_isenabled() != 0) {

--- a/targets/TARGET_RENESAS/mbed_rtx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_RENESAS/mbed_rtx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -18,7 +18,7 @@
 
 #include <stdint.h>
 
-#if defined(TARGET_RZ_A1H) || defined(TARGET_GR_LYCHEE)
+#if defined(TARGET_RZ_A1H) || defined(TARGET_VK_RZ_A1H) || defined(TARGET_GR_LYCHEE)
 #define OS_IDLE_THREAD_STACK_SIZE   512
 
 #if defined(__CC_ARM)

--- a/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/RTWInterface.cpp	Thu Apr 19 17:12:19 2018 +0100
@@ -86,7 +86,7 @@
 }
 
 RTWInterface::RTWInterface(bool debug)
-    : _dhcp(true), _ip_address(), _netmask(), _gateway()
+    : _dhcp(true), _ssid(), _pass(), _ip_address(), _netmask(), _gateway()
 {
     emac_interface_t *emac;
     int ret;
@@ -135,7 +135,7 @@
  */
 nsapi_error_t RTWInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security)
 {
-    if(!ssid) {
+    if(!ssid || (strlen(ssid) == 0)) {
         return NSAPI_ERROR_PARAMETER;
     }
 
@@ -149,6 +149,9 @@
             }
             break;
         case NSAPI_SECURITY_NONE:
+            if(pass && strlen(pass) > 0) {
+                return NSAPI_ERROR_PARAMETER;
+            }
             break;
         default:
             return NSAPI_ERROR_PARAMETER;
@@ -166,7 +169,8 @@
     int ret;
     rtw_security_t sec;
 
-    if (!_ssid || (!_pass && _security != NSAPI_SECURITY_NONE)) {
+    if (!_ssid || (strlen(_ssid) == 0) ||
+       (!_pass && _security != NSAPI_SECURITY_NONE)) {
         printf("Invalid credentials\r\n");
         return NSAPI_ERROR_PARAMETER;
     }
@@ -187,11 +191,6 @@
             return NSAPI_ERROR_PARAMETER;
     }
 
-    if(_channel > 0 && _channel < 14){
-        uint8_t pscan_config = PSCAN_ENABLE;
-        wifi_set_pscan_chan(&_channel, &pscan_config, 1);
-    }
-
     ret = wifi_connect(_ssid, sec, _pass, strlen(_ssid), strlen(_pass), 0, (void *)NULL);
     if (ret != RTW_SUCCESS) {
         printf("failed: %d\r\n", ret);
@@ -229,7 +228,10 @@
 
 nsapi_error_t RTWInterface::set_channel(uint8_t channel)
 {
-    _channel = channel;
+    // Not supported for STA mode wifi driver
+    if (channel != 0)
+        return NSAPI_ERROR_UNSUPPORTED;
+
     return NSAPI_ERROR_OK;
 }
 
@@ -244,8 +246,14 @@
 nsapi_error_t RTWInterface::connect(const char *ssid, const char *pass,
                             nsapi_security_t security, uint8_t channel)
 {
-    set_credentials(ssid, pass, security);
-    set_channel(channel);
+    nsapi_error_t ret;
+
+    ret = set_credentials(ssid, pass, security);
+    if(ret != NSAPI_ERROR_OK) return ret;
+
+    ret = set_channel(channel);
+    if(ret != NSAPI_ERROR_OK) return ret;
+
     return connect();
 }
 

--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct	Thu Apr 19 17:12:19 2018 +0100
@@ -18,21 +18,29 @@
   }
 
   ER_IRAM +0 FIXED {
+    *(.ARM.exidx)
+    *(.init_array)
     *rtl8195a_crypto*.o (+RO)
     *(i.mbedtls*)
     *libc.a (+RO)
     *rtx_*.o (+RO)
+    *main*.o (+RO)
+    *lib_peripheral_mbed_arm.ar (+RO)
+    *_api*.o (+RO)
   }
 
   RW_IRAM1 +0 UNINIT FIXED {
     *rtl8195a_crypto*.o(+RW)
     *libc.a (+RW)
-    *(.sdram.data*)
+    *main*.o (+RW)
     *lib_peripheral_mbed_arm.ar (+RW)
-    *rtl8195a_crypto*.o(+ZI, COMMON)
-    *libc.a (+ZI, COMMON)
-    *(.bss.thread_stack_main)
-    *lib_peripheral_mbed_arm.ar (+ZI, COMMON)
+    *_api*.o (+RW)
+    *rtl8195a_crypto*.o(+ZI)
+    *libc.a (+ZI)
+    *main*.o (+ZI)
+    *lib_peripheral_mbed_arm.ar (+ZI)
+    *_api*.o (+ZI)
+    *mbed_boot*.o (+ZI)
   }
 
   ARM_LIB_STACK (0x10070000 - 0x1000) EMPTY 0x1000 {
@@ -41,8 +49,8 @@
 
 LR_TCM 0x1FFF0000 0x10000 {
     TCM_OVERLAY 0x1FFF0000 0x10000 {
-        *lwip_mem*.o(.bss*)
-        *lwip_memp*.o(.bss*)
+        *lwip_mem*.o(+ZI)
+        *lwip_memp*.o(+ZI)
         *.o(.tcm.heap*)
     }
 }

--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_GCC_ARM/rtl8195a.ld	Thu Apr 19 17:12:19 2018 +0100
@@ -67,18 +67,17 @@
     .text.sram1 :
     {
         . = ALIGN(4);
-        *rtl8195a_crypto.o (.text* .rodata*)
+        *rtl8195a_crypto*.o (.text* .rodata*)
         *mbedtls*.o (.text* .rodata*)
         *libc.a: (.text* .rodata*)
+        *lib_peripheral_mbed_gcc.a: (.text* .rodata*)
+        *_api*.o (.text* .rodata*)
+        *main*.o (.text* .rodata*)
     } > SRAM1
 
     .text.sram2 :
     {
         . = ALIGN(4);
-        *(.mon.ram.text*)
-        *(.hal.flash.text*)
-        *(.hal.sdrc.text*)
-        *(.hal.gpio.text*)
         *(.text*)
 
         KEEP(*(.init))
@@ -165,9 +164,11 @@
     .bss.sram1 (NOLOAD) :
     {
         __bss_sram_start__ = .;
-        *rtl8195a_crypto.o (.bss* COMMON)
+        *rtl8195a_crypto*.o (.bss* COMMON)
         *mbedtls*.o (.bss* COMMON)
         *(.bss.thread_stack_main)
+        *lib_peripheral_mbed_gcc.a: (.bss* COMMON)
+        *mbed_boot*.o (.bss* COMMON)
         __bss_sram_end__ = .;
     } > SRAM1
 
@@ -198,11 +199,11 @@
         __HeapLimit = .;
     } > SRAM1
     
-    .TCM_overlay :
+    .TCM_overlay (NOLOAD):
     {
         __bss_dtcm_start__ = .;
-        *lwip_mem.o (.bss*)
-        *lwip_memp.o (.bss*)
+        *lwip_mem*.o (.bss* COMMON)
+        *lwip_memp*.o (.bss* COMMON)
         *(.tcm.heap*)
         __bss_dtcm_end__ = .;
     } > TCM

--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -210,13 +210,13 @@
 
     pUartAdapter = &(obj->log_hal_uart);
     pUartAdapter->api_irq_handler = handler;
-    pUartAdapter->api_irq_id = id;    
+    pUartAdapter->api_irq_id = id;
 }
 
 void log_uart_irq_set(log_uart_t *obj, LOG_UART_INT_ID irq, uint32_t enable) 
 {
     HAL_LOG_UART_ADAPTER *pUartAdapter;
-    u8 int_en=0;
+    u8 int_en = 0;
 
     pUartAdapter = &(obj->log_hal_uart);
 
@@ -241,7 +241,7 @@
         DBG_UART_WARN("log_uart_irq_set: Unknown Irq Id\n");
         return;
     }
-        
+
     if (enable) {
         pUartAdapter->IntEnReg |= int_en;
     } else {

--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -284,32 +284,29 @@
 #ifdef CONFIG_MBED_ENABLED
 static void serial_loguart_irq_handler(uint32_t id, LOG_UART_INT_ID event)
 {
-    if (event == IIR_RX_RDY || event == IIR_CHAR_TIMEOUT)
-    {
-        if (log_irq_handler) {
+    log_uart_irq_set(&stdio_uart_log, event, 0);
+    if (log_irq_handler) {
+        if (event == IIR_RX_RDY || event == IIR_CHAR_TIMEOUT) {
             log_irq_handler(serial_log_irq_ids, RxIrq);
-            }
-    } else if (event == IIR_THR_EMPTY) {
-        if (log_irq_handler) {
-                log_irq_handler(serial_log_irq_ids, TxIrq);
-            }
+        } else if (event == IIR_THR_EMPTY) {
+            log_irq_handler(serial_log_irq_ids, TxIrq);
+        }
     }
     return;
 }
 #endif
 
 
-
 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) 
 {
 
 #ifdef CONFIG_MBED_ENABLED
-            if (obj->index == UART_3) {
-                log_irq_handler = handler;
-                serial_log_irq_ids = id;
-                log_uart_irq_handler(&stdio_uart_log, serial_loguart_irq_handler, id);
-                return;
-            }             
+    if (obj->index == UART_3) {
+        log_irq_handler = handler;
+        serial_log_irq_ids = id;
+        log_uart_irq_handler(&stdio_uart_log, serial_loguart_irq_handler, id);
+        return;
+    }
 #endif
     PHAL_RUART_ADAPTER pHalRuartAdapter;
     u8 uart_idx;
@@ -326,14 +323,33 @@
 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) 
 {
 #ifdef CONFIG_MBED_ENABLED
-        if (obj->index == UART_3) {
+    if (obj->index == UART_3) {
+        if(enable) {
+            if (irq == RxIrq) {
+                log_uart_irq_set(&stdio_uart_log, IIR_RX_RDY, enable);
+                serial_log_irq_en |= SERIAL_RX_IRQ_EN;
+            } else {
+                log_uart_irq_set(&stdio_uart_log, IIR_THR_EMPTY, enable);
+                serial_log_irq_en |= SERIAL_TX_IRQ_EN;
+            }
+        } else {
             if (irq == RxIrq) {
                 log_uart_irq_set(&stdio_uart_log, IIR_RX_RDY, enable);
+                serial_log_irq_en &= ~SERIAL_RX_IRQ_EN;
             } else {
                 log_uart_irq_set(&stdio_uart_log, IIR_THR_EMPTY, enable);
+                serial_log_irq_en &= ~SERIAL_TX_IRQ_EN;
             }
-            return;
+
+            log_uart_t *log_obj = &stdio_uart_log;
+            HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(log_obj->log_hal_uart);
+            if (pUartAdapter->IntEnReg == 0) {
+                InterruptUnRegister(&pUartAdapter->IrqHandle);
+                InterruptDis(&pUartAdapter->IrqHandle);
+            }
         }
+        return;
+    }
 #endif
     PHAL_RUART_ADAPTER pHalRuartAdapter;
     PHAL_RUART_OP pHalRuartOp;
@@ -352,7 +368,6 @@
         }
          
         pHalRuartOp->HalRuartRegIrq(pHalRuartAdapter);
-        //log_uart
         pHalRuartOp->HalRuartIntEnable(pHalRuartAdapter);
     } else { // disable
         if (irq == RxIrq) {
@@ -394,6 +409,14 @@
 #ifdef CONFIG_MBED_ENABLED
     if (obj->index == UART_3) {
         log_uart_putc(&stdio_uart_log, (char)c);
+
+        // UnMask LOG_UART TX FIFO empty IRQ
+        if (serial_log_irq_en & SERIAL_TX_IRQ_EN) {
+            log_uart_t *log_obj = &stdio_uart_log;
+            HAL_LOG_UART_ADAPTER *pUartAdapter=(PHAL_LOG_UART_ADAPTER)&(log_obj->log_hal_uart);
+            pUartAdapter->IntEnReg |= IER_ETBEI;
+            HalLogUartSetIntEn(pUartAdapter);
+        }
         return;
     }
 #endif

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c	Thu Apr 19 17:12:19 2018 +0100
@@ -236,11 +236,3 @@
     return 1; // OK
 }
 
-/******************************************************************************/
-/*            Hard Fault Handler                                              */
-/******************************************************************************/
-void HardFault_Handler(void)
-{
-    debug("Hard Fault\n");
-    NVIC_SystemReset();
-}

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c	Thu Apr 19 17:12:19 2018 +0100
@@ -236,11 +236,3 @@
     return 1; // OK
 }
 
-/******************************************************************************/
-/*            Hard Fault Handler                                              */
-/******************************************************************************/
-void HardFault_Handler(void)
-{
-    debug("Hard Fault\n");
-    NVIC_SystemReset();
-}

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/stm32f411xe.icf	Thu Apr 19 17:12:19 2018 +0100
@@ -1,5 +1,5 @@
 /* [ROM = 512kb = 0x80000] */
-define symbol __intvec_start__     = 0x08000000;
+define symbol __intvec_start__     = 0x08010000;
 define symbol __region_ROM_start__ = 0x08010000;
 define symbol __region_ROM_end__   = 0x0807FFFF;
 

--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c	Thu Apr 19 17:12:19 2018 +0100
@@ -238,11 +238,3 @@
     return 1; // OK
 }
 
-/******************************************************************************/
-/*            Hard Fault Handler                                              */
-/******************************************************************************/
-void HardFault_Handler(void)
-{
-    debug("Hard Fault\n");
-    NVIC_SystemReset();
-}

Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_ARM/libublox-odin-w2-driver.ar has changed

Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_GCC_ARM/libublox-odin-w2-driver.a has changed

Binary file targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/sdk/TOOLCHAIN_IAR/libublox-odin-w2-driver.a has changed

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l152xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L152XC Devices vector for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* COPYRIGHT(c) 2016 STMicroelectronics
+;* COPYRIGHT(c) 2017 STMicroelectronics
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_ARM_STD/startup_stm32l152xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_ARM_STD/startup_stm32l152xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l152xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L152XC Devices vector for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* COPYRIGHT(c) 2016 STMicroelectronics
+;* COPYRIGHT(c) 2017 STMicroelectronics
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l152xc.s
   * @author    MCD Application Team
-  * @version   V2.2.0
-  * @date      01-July-2016
   * @brief     STM32L152XC Devices vector table for 
   *            Atollic toolchain.
   *            This module performs:
@@ -17,7 +15,7 @@
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_IAR/startup_stm32l152xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/TOOLCHAIN_IAR/startup_stm32l152xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l152xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L152XC Devices vector for EWARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+;* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/stm32l152xc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/stm32l152xc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l152xc.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32L1xx devices.            
@@ -16,7 +14,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -454,21 +452,27 @@
 typedef struct
 {
   __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,       Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,        Address offset: 0x08 */
+  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
+  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
   __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,               Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,               Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved, 0x18                                                                  */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,         Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                   Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,  Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,         Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                   Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,  Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,         Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                   Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,  Address offset: 0x3C */
+  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
+  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
+  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
+  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
+  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
+  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
+  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
+  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
+  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
+  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
+  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
+  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
+  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
+  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
+  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
+  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
+  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
+  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
 } RI_TypeDef;
 
 /** 
@@ -3586,56 +3590,56 @@
 #define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFRL0_Msk                  (0xFU << GPIO_AFRL_AFRL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFRL0_Msk               
-#define GPIO_AFRL_AFRL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFRL1_Msk                  (0xFU << GPIO_AFRL_AFRL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFRL1_Msk               
-#define GPIO_AFRL_AFRL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFRL2_Msk                  (0xFU << GPIO_AFRL_AFRL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFRL2_Msk               
-#define GPIO_AFRL_AFRL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFRL3_Msk                  (0xFU << GPIO_AFRL_AFRL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFRL3_Msk               
-#define GPIO_AFRL_AFRL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFRL4_Msk                  (0xFU << GPIO_AFRL_AFRL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFRL4_Msk               
-#define GPIO_AFRL_AFRL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFRL5_Msk                  (0xFU << GPIO_AFRL_AFRL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFRL5_Msk               
-#define GPIO_AFRL_AFRL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFRL6_Msk                  (0xFU << GPIO_AFRL_AFRL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFRL6_Msk               
-#define GPIO_AFRL_AFRL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFRL7_Msk                  (0xFU << GPIO_AFRL_AFRL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFRL7_Msk               
+#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
+#define GPIO_AFRL_AFSEL0_Msk                  (0xFU << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
+#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
+#define GPIO_AFRL_AFSEL1_Msk                  (0xFU << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
+#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
+#define GPIO_AFRL_AFSEL2_Msk                  (0xFU << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
+#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
+#define GPIO_AFRL_AFSEL3_Msk                  (0xFU << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
+#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
+#define GPIO_AFRL_AFSEL4_Msk                  (0xFU << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
+#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
+#define GPIO_AFRL_AFSEL5_Msk                  (0xFU << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
+#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
+#define GPIO_AFRL_AFSEL6_Msk                  (0xFU << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
+#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
+#define GPIO_AFRL_AFSEL7_Msk                  (0xFU << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos                  (0U)                              
-#define GPIO_AFRH_AFRH0_Msk                  (0xFU << GPIO_AFRH_AFRH0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFRH0_Msk               
-#define GPIO_AFRH_AFRH1_Pos                  (4U)                              
-#define GPIO_AFRH_AFRH1_Msk                  (0xFU << GPIO_AFRH_AFRH1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFRH1_Msk               
-#define GPIO_AFRH_AFRH2_Pos                  (8U)                              
-#define GPIO_AFRH_AFRH2_Msk                  (0xFU << GPIO_AFRH_AFRH2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFRH2_Msk               
-#define GPIO_AFRH_AFRH3_Pos                  (12U)                             
-#define GPIO_AFRH_AFRH3_Msk                  (0xFU << GPIO_AFRH_AFRH3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFRH3_Msk               
-#define GPIO_AFRH_AFRH4_Pos                  (16U)                             
-#define GPIO_AFRH_AFRH4_Msk                  (0xFU << GPIO_AFRH_AFRH4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFRH4_Msk               
-#define GPIO_AFRH_AFRH5_Pos                  (20U)                             
-#define GPIO_AFRH_AFRH5_Msk                  (0xFU << GPIO_AFRH_AFRH5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFRH5_Msk               
-#define GPIO_AFRH_AFRH6_Pos                  (24U)                             
-#define GPIO_AFRH_AFRH6_Msk                  (0xFU << GPIO_AFRH_AFRH6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFRH6_Msk               
-#define GPIO_AFRH_AFRH7_Pos                  (28U)                             
-#define GPIO_AFRH_AFRH7_Msk                  (0xFU << GPIO_AFRH_AFRH7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFRH7_Msk               
+#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
+#define GPIO_AFRH_AFSEL8_Msk                  (0xFU << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
+#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
+#define GPIO_AFRH_AFSEL9_Msk                  (0xFU << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
+#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
+#define GPIO_AFRH_AFSEL10_Msk                  (0xFU << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
+#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
+#define GPIO_AFRH_AFSEL11_Msk                  (0xFU << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
+#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
+#define GPIO_AFRH_AFSEL12_Msk                  (0xFU << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
+#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
+#define GPIO_AFRH_AFSEL13_Msk                  (0xFU << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
+#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
+#define GPIO_AFRH_AFSEL14_Msk                  (0xFU << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
+#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
+#define GPIO_AFRH_AFSEL15_Msk                  (0xFU << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                        (0x00000001U)                     
@@ -4972,9 +4976,9 @@
 #define RTC_CR_COSEL_Pos                     (19U)                             
 #define RTC_CR_COSEL_Msk                     (0x1U << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
 #define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BCK_Pos                       (18U)                             
-#define RTC_CR_BCK_Msk                       (0x1U << RTC_CR_BCK_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BCK                           RTC_CR_BCK_Msk                    
+#define RTC_CR_BKP_Pos                       (18U)                             
+#define RTC_CR_BKP_Msk                       (0x1U << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
+#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
 #define RTC_CR_SUB1H_Pos                     (17U)                             
 #define RTC_CR_SUB1H_Msk                     (0x1U << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
 #define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
@@ -5027,6 +5031,11 @@
 #define RTC_CR_WUCKSEL_1                     (0x2U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2                     (0x4U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
 
+/* Legacy defines */
+#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
+#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
+#define  RTC_CR_BCK     RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF_Pos                  (16U)                             
 #define RTC_ISR_RECALPF_Msk                  (0x1U << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
@@ -6264,6 +6273,45 @@
 #define RI_HYSCR3_PE_13                 (0x2000U << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
 #define RI_HYSCR3_PE_14                 (0x4000U << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
 #define RI_HYSCR3_PE_15                 (0x8000U << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
+#define RI_HYSCR3_PF_Pos                (16U)                                  
+#define RI_HYSCR3_PF_Msk                (0xFFFFU << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
+#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
+#define RI_HYSCR3_PF_0                  (0x0001U << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
+#define RI_HYSCR3_PF_1                  (0x0002U << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
+#define RI_HYSCR3_PF_2                  (0x0004U << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
+#define RI_HYSCR3_PF_3                  (0x0008U << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
+#define RI_HYSCR3_PF_4                  (0x0010U << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
+#define RI_HYSCR3_PF_5                  (0x0020U << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
+#define RI_HYSCR3_PF_6                  (0x0040U << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
+#define RI_HYSCR3_PF_7                  (0x0080U << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
+#define RI_HYSCR3_PF_8                  (0x0100U << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
+#define RI_HYSCR3_PF_9                  (0x0200U << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
+#define RI_HYSCR3_PF_10                 (0x0400U << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
+#define RI_HYSCR3_PF_11                 (0x0800U << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
+#define RI_HYSCR3_PF_12                 (0x1000U << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
+#define RI_HYSCR3_PF_13                 (0x2000U << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
+#define RI_HYSCR3_PF_14                 (0x4000U << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
+#define RI_HYSCR3_PF_15                 (0x8000U << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
+/********************  Bit definition for RI_HYSCR4 register  ********************/
+#define RI_HYSCR4_PG_Pos                (0U)                                   
+#define RI_HYSCR4_PG_Msk                (0xFFFFU << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
+#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
+#define RI_HYSCR4_PG_0                  (0x0001U << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
+#define RI_HYSCR4_PG_1                  (0x0002U << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
+#define RI_HYSCR4_PG_2                  (0x0004U << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
+#define RI_HYSCR4_PG_3                  (0x0008U << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
+#define RI_HYSCR4_PG_4                  (0x0010U << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
+#define RI_HYSCR4_PG_5                  (0x0020U << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
+#define RI_HYSCR4_PG_6                  (0x0040U << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
+#define RI_HYSCR4_PG_7                  (0x0080U << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
+#define RI_HYSCR4_PG_8                  (0x0100U << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
+#define RI_HYSCR4_PG_9                  (0x0200U << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
+#define RI_HYSCR4_PG_10                 (0x0400U << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
+#define RI_HYSCR4_PG_11                 (0x0800U << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
+#define RI_HYSCR4_PG_12                 (0x1000U << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
+#define RI_HYSCR4_PG_13                 (0x2000U << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
+#define RI_HYSCR4_PG_14                 (0x4000U << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
+#define RI_HYSCR4_PG_15                 (0x8000U << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
 
 /********************  Bit definition for RI_ASMR1 register  ********************/
 #define RI_ASMR1_PA_Pos                 (0U)                                   
@@ -6454,6 +6502,132 @@
 #define RI_CICR3_PC_14                  (0x4000U << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
 #define RI_CICR3_PC_15                  (0x8000U << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
 
+/********************  Bit definition for RI_ASMR4 register  ********************/
+#define RI_ASMR4_PF_Pos                 (0U)                                   
+#define RI_ASMR4_PF_Msk                 (0xFFFFU << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
+#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
+#define RI_ASMR4_PF_0                   (0x0001U << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
+#define RI_ASMR4_PF_1                   (0x0002U << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
+#define RI_ASMR4_PF_2                   (0x0004U << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
+#define RI_ASMR4_PF_3                   (0x0008U << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
+#define RI_ASMR4_PF_4                   (0x0010U << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
+#define RI_ASMR4_PF_5                   (0x0020U << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
+#define RI_ASMR4_PF_6                   (0x0040U << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
+#define RI_ASMR4_PF_7                   (0x0080U << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
+#define RI_ASMR4_PF_8                   (0x0100U << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
+#define RI_ASMR4_PF_9                   (0x0200U << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
+#define RI_ASMR4_PF_10                  (0x0400U << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
+#define RI_ASMR4_PF_11                  (0x0800U << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
+#define RI_ASMR4_PF_12                  (0x1000U << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
+#define RI_ASMR4_PF_13                  (0x2000U << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
+#define RI_ASMR4_PF_14                  (0x4000U << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
+#define RI_ASMR4_PF_15                  (0x8000U << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CMR4 register  ********************/
+#define RI_CMR4_PF_Pos                  (0U)                                   
+#define RI_CMR4_PF_Msk                  (0xFFFFU << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
+#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
+#define RI_CMR4_PF_0                    (0x0001U << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
+#define RI_CMR4_PF_1                    (0x0002U << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
+#define RI_CMR4_PF_2                    (0x0004U << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
+#define RI_CMR4_PF_3                    (0x0008U << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
+#define RI_CMR4_PF_4                    (0x0010U << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
+#define RI_CMR4_PF_5                    (0x0020U << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
+#define RI_CMR4_PF_6                    (0x0040U << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
+#define RI_CMR4_PF_7                    (0x0080U << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
+#define RI_CMR4_PF_8                    (0x0100U << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
+#define RI_CMR4_PF_9                    (0x0200U << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
+#define RI_CMR4_PF_10                   (0x0400U << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
+#define RI_CMR4_PF_11                   (0x0800U << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
+#define RI_CMR4_PF_12                   (0x1000U << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
+#define RI_CMR4_PF_13                   (0x2000U << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
+#define RI_CMR4_PF_14                   (0x4000U << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
+#define RI_CMR4_PF_15                   (0x8000U << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CICR4 register  ********************/
+#define RI_CICR4_PF_Pos                 (0U)                                   
+#define RI_CICR4_PF_Msk                 (0xFFFFU << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
+#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
+#define RI_CICR4_PF_0                   (0x0001U << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
+#define RI_CICR4_PF_1                   (0x0002U << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
+#define RI_CICR4_PF_2                   (0x0004U << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
+#define RI_CICR4_PF_3                   (0x0008U << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
+#define RI_CICR4_PF_4                   (0x0010U << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
+#define RI_CICR4_PF_5                   (0x0020U << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
+#define RI_CICR4_PF_6                   (0x0040U << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
+#define RI_CICR4_PF_7                   (0x0080U << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
+#define RI_CICR4_PF_8                   (0x0100U << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
+#define RI_CICR4_PF_9                   (0x0200U << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
+#define RI_CICR4_PF_10                  (0x0400U << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
+#define RI_CICR4_PF_11                  (0x0800U << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
+#define RI_CICR4_PF_12                  (0x1000U << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
+#define RI_CICR4_PF_13                  (0x2000U << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
+#define RI_CICR4_PF_14                  (0x4000U << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
+#define RI_CICR4_PF_15                  (0x8000U << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_ASMR5 register  ********************/
+#define RI_ASMR5_PG_Pos                 (0U)                                   
+#define RI_ASMR5_PG_Msk                 (0xFFFFU << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
+#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
+#define RI_ASMR5_PG_0                   (0x0001U << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
+#define RI_ASMR5_PG_1                   (0x0002U << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
+#define RI_ASMR5_PG_2                   (0x0004U << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
+#define RI_ASMR5_PG_3                   (0x0008U << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
+#define RI_ASMR5_PG_4                   (0x0010U << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
+#define RI_ASMR5_PG_5                   (0x0020U << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
+#define RI_ASMR5_PG_6                   (0x0040U << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
+#define RI_ASMR5_PG_7                   (0x0080U << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
+#define RI_ASMR5_PG_8                   (0x0100U << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
+#define RI_ASMR5_PG_9                   (0x0200U << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
+#define RI_ASMR5_PG_10                  (0x0400U << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
+#define RI_ASMR5_PG_11                  (0x0800U << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
+#define RI_ASMR5_PG_12                  (0x1000U << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
+#define RI_ASMR5_PG_13                  (0x2000U << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
+#define RI_ASMR5_PG_14                  (0x4000U << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
+#define RI_ASMR5_PG_15                  (0x8000U << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CMR5 register  ********************/
+#define RI_CMR5_PG_Pos                  (0U)                                   
+#define RI_CMR5_PG_Msk                  (0xFFFFU << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
+#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
+#define RI_CMR5_PG_0                    (0x0001U << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
+#define RI_CMR5_PG_1                    (0x0002U << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
+#define RI_CMR5_PG_2                    (0x0004U << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
+#define RI_CMR5_PG_3                    (0x0008U << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
+#define RI_CMR5_PG_4                    (0x0010U << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
+#define RI_CMR5_PG_5                    (0x0020U << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
+#define RI_CMR5_PG_6                    (0x0040U << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
+#define RI_CMR5_PG_7                    (0x0080U << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
+#define RI_CMR5_PG_8                    (0x0100U << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
+#define RI_CMR5_PG_9                    (0x0200U << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
+#define RI_CMR5_PG_10                   (0x0400U << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
+#define RI_CMR5_PG_11                   (0x0800U << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
+#define RI_CMR5_PG_12                   (0x1000U << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
+#define RI_CMR5_PG_13                   (0x2000U << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
+#define RI_CMR5_PG_14                   (0x4000U << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
+#define RI_CMR5_PG_15                   (0x8000U << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CICR5 register  ********************/
+#define RI_CICR5_PG_Pos                 (0U)                                   
+#define RI_CICR5_PG_Msk                 (0xFFFFU << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
+#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
+#define RI_CICR5_PG_0                   (0x0001U << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
+#define RI_CICR5_PG_1                   (0x0002U << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
+#define RI_CICR5_PG_2                   (0x0004U << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
+#define RI_CICR5_PG_3                   (0x0008U << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
+#define RI_CICR5_PG_4                   (0x0010U << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
+#define RI_CICR5_PG_5                   (0x0020U << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
+#define RI_CICR5_PG_6                   (0x0040U << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
+#define RI_CICR5_PG_7                   (0x0080U << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
+#define RI_CICR5_PG_8                   (0x0100U << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
+#define RI_CICR5_PG_9                   (0x0200U << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
+#define RI_CICR5_PG_10                  (0x0400U << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
+#define RI_CICR5_PG_11                  (0x0800U << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
+#define RI_CICR5_PG_12                  (0x1000U << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
+#define RI_CICR5_PG_13                  (0x2000U << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
+#define RI_CICR5_PG_14                  (0x4000U << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
+#define RI_CICR5_PG_15                  (0x8000U << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
+
 /******************************************************************************/
 /*                                                                            */
 /*                               Timers (TIM)                                 */
@@ -8631,24 +8805,58 @@
 
 /*******************  Bit definition for SCB_CFSR register  *******************/
 /*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)    /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)  /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
 #define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)    /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)      /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
 #define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)    /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)     /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
 #define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)    /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)       /*!< SCB CFSR (MMFSR): MSTKERR Mask */
 #define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)    /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)     /*!< SCB CFSR (MMFSR): MMARVALID Mask */
 #define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */
 /*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)       /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)        /*!< SCB CFSR (BFSR): IBUSERR Mask */
 #define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)       /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)      /*!< SCB CFSR (BFSR): PRECISERR Mask */
 #define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)       /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)    /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
 #define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)       /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)       /*!< SCB CFSR (BFSR): UNSTKERR Mask */
 #define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)       /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)         /*!< SCB CFSR (BFSR): STKERR Mask */
 #define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)       /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)      /*!< SCB CFSR (BFSR): BFARVALID Mask */
 #define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */
 /*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)       /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)     /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
 #define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)       /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)       /*!< SCB CFSR (UFSR): INVSTATE Mask */
 #define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)       /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)          /*!< SCB CFSR (UFSR): INVPC Mask */
 #define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)       /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)           /*!< SCB CFSR (UFSR): NOCP Mask */
 #define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)       /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)      /*!< SCB CFSR (UFSR): UNALIGNED Mask */
 #define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)       /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)      /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
 #define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
 
 /*******************  Bit definition for SCB_HFSR register  *******************/

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/stm32l1xx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
   *
   *          The file is the unique include file that the application programmer
@@ -18,7 +16,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -122,7 +120,7 @@
   */
 #define __STM32L1xx_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
 #define __STM32L1xx_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32L1xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32L1xx_CMSIS_VERSION        ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_stm32l1xx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/system_stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    system_stm32l1xx.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l151xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L151XC Devices vector for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* COPYRIGHT(c) 2016 STMicroelectronics
+;* COPYRIGHT(c) 2017 STMicroelectronics
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l151xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L151XC Devices vector for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* COPYRIGHT(c) 2016 STMicroelectronics
+;* COPYRIGHT(c) 2017 STMicroelectronics
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l151xc.s
   * @author    MCD Application Team
-  * @version   V2.2.0
-  * @date      01-July-2016
   * @brief     STM32L151XC Devices vector table for 
   *            Atollic toolchain.
   *            This module performs:
@@ -17,7 +15,7 @@
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_IAR/startup_stm32l152xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/TOOLCHAIN_IAR/startup_stm32l152xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l152xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L152XC Devices vector for EWARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+;* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/stm32l151xc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/stm32l151xc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l151xc.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32L1xx devices.            
@@ -16,7 +14,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -439,21 +437,27 @@
 typedef struct
 {
   __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,       Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,        Address offset: 0x08 */
+  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
+  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
   __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,               Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,               Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved, 0x18                                                                  */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,         Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                   Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,  Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,         Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                   Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,  Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,         Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                   Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,  Address offset: 0x3C */
+  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
+  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
+  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
+  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
+  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
+  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
+  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
+  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
+  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
+  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
+  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
+  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
+  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
+  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
+  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
+  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
+  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
+  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
 } RI_TypeDef;
 
 /** 
@@ -3569,56 +3573,56 @@
 #define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFRL0_Msk                  (0xFU << GPIO_AFRL_AFRL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFRL0_Msk               
-#define GPIO_AFRL_AFRL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFRL1_Msk                  (0xFU << GPIO_AFRL_AFRL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFRL1_Msk               
-#define GPIO_AFRL_AFRL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFRL2_Msk                  (0xFU << GPIO_AFRL_AFRL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFRL2_Msk               
-#define GPIO_AFRL_AFRL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFRL3_Msk                  (0xFU << GPIO_AFRL_AFRL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFRL3_Msk               
-#define GPIO_AFRL_AFRL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFRL4_Msk                  (0xFU << GPIO_AFRL_AFRL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFRL4_Msk               
-#define GPIO_AFRL_AFRL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFRL5_Msk                  (0xFU << GPIO_AFRL_AFRL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFRL5_Msk               
-#define GPIO_AFRL_AFRL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFRL6_Msk                  (0xFU << GPIO_AFRL_AFRL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFRL6_Msk               
-#define GPIO_AFRL_AFRL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFRL7_Msk                  (0xFU << GPIO_AFRL_AFRL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFRL7_Msk               
+#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
+#define GPIO_AFRL_AFSEL0_Msk                  (0xFU << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
+#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
+#define GPIO_AFRL_AFSEL1_Msk                  (0xFU << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
+#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
+#define GPIO_AFRL_AFSEL2_Msk                  (0xFU << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
+#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
+#define GPIO_AFRL_AFSEL3_Msk                  (0xFU << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
+#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
+#define GPIO_AFRL_AFSEL4_Msk                  (0xFU << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
+#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
+#define GPIO_AFRL_AFSEL5_Msk                  (0xFU << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
+#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
+#define GPIO_AFRL_AFSEL6_Msk                  (0xFU << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
+#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
+#define GPIO_AFRL_AFSEL7_Msk                  (0xFU << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos                  (0U)                              
-#define GPIO_AFRH_AFRH0_Msk                  (0xFU << GPIO_AFRH_AFRH0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFRH0_Msk               
-#define GPIO_AFRH_AFRH1_Pos                  (4U)                              
-#define GPIO_AFRH_AFRH1_Msk                  (0xFU << GPIO_AFRH_AFRH1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFRH1_Msk               
-#define GPIO_AFRH_AFRH2_Pos                  (8U)                              
-#define GPIO_AFRH_AFRH2_Msk                  (0xFU << GPIO_AFRH_AFRH2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFRH2_Msk               
-#define GPIO_AFRH_AFRH3_Pos                  (12U)                             
-#define GPIO_AFRH_AFRH3_Msk                  (0xFU << GPIO_AFRH_AFRH3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFRH3_Msk               
-#define GPIO_AFRH_AFRH4_Pos                  (16U)                             
-#define GPIO_AFRH_AFRH4_Msk                  (0xFU << GPIO_AFRH_AFRH4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFRH4_Msk               
-#define GPIO_AFRH_AFRH5_Pos                  (20U)                             
-#define GPIO_AFRH_AFRH5_Msk                  (0xFU << GPIO_AFRH_AFRH5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFRH5_Msk               
-#define GPIO_AFRH_AFRH6_Pos                  (24U)                             
-#define GPIO_AFRH_AFRH6_Msk                  (0xFU << GPIO_AFRH_AFRH6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFRH6_Msk               
-#define GPIO_AFRH_AFRH7_Pos                  (28U)                             
-#define GPIO_AFRH_AFRH7_Msk                  (0xFU << GPIO_AFRH_AFRH7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFRH7_Msk               
+#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
+#define GPIO_AFRH_AFSEL8_Msk                  (0xFU << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
+#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
+#define GPIO_AFRH_AFSEL9_Msk                  (0xFU << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
+#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
+#define GPIO_AFRH_AFSEL10_Msk                  (0xFU << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
+#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
+#define GPIO_AFRH_AFSEL11_Msk                  (0xFU << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
+#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
+#define GPIO_AFRH_AFSEL12_Msk                  (0xFU << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
+#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
+#define GPIO_AFRH_AFSEL13_Msk                  (0xFU << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
+#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
+#define GPIO_AFRH_AFSEL14_Msk                  (0xFU << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
+#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
+#define GPIO_AFRH_AFSEL15_Msk                  (0xFU << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                        (0x00000001U)                     
@@ -4830,9 +4834,9 @@
 #define RTC_CR_COSEL_Pos                     (19U)                             
 #define RTC_CR_COSEL_Msk                     (0x1U << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
 #define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BCK_Pos                       (18U)                             
-#define RTC_CR_BCK_Msk                       (0x1U << RTC_CR_BCK_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BCK                           RTC_CR_BCK_Msk                    
+#define RTC_CR_BKP_Pos                       (18U)                             
+#define RTC_CR_BKP_Msk                       (0x1U << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
+#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
 #define RTC_CR_SUB1H_Pos                     (17U)                             
 #define RTC_CR_SUB1H_Msk                     (0x1U << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
 #define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
@@ -4885,6 +4889,11 @@
 #define RTC_CR_WUCKSEL_1                     (0x2U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2                     (0x4U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
 
+/* Legacy defines */
+#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
+#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
+#define  RTC_CR_BCK     RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF_Pos                  (16U)                             
 #define RTC_ISR_RECALPF_Msk                  (0x1U << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
@@ -6114,6 +6123,45 @@
 #define RI_HYSCR3_PE_13                 (0x2000U << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
 #define RI_HYSCR3_PE_14                 (0x4000U << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
 #define RI_HYSCR3_PE_15                 (0x8000U << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
+#define RI_HYSCR3_PF_Pos                (16U)                                  
+#define RI_HYSCR3_PF_Msk                (0xFFFFU << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
+#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
+#define RI_HYSCR3_PF_0                  (0x0001U << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
+#define RI_HYSCR3_PF_1                  (0x0002U << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
+#define RI_HYSCR3_PF_2                  (0x0004U << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
+#define RI_HYSCR3_PF_3                  (0x0008U << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
+#define RI_HYSCR3_PF_4                  (0x0010U << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
+#define RI_HYSCR3_PF_5                  (0x0020U << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
+#define RI_HYSCR3_PF_6                  (0x0040U << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
+#define RI_HYSCR3_PF_7                  (0x0080U << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
+#define RI_HYSCR3_PF_8                  (0x0100U << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
+#define RI_HYSCR3_PF_9                  (0x0200U << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
+#define RI_HYSCR3_PF_10                 (0x0400U << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
+#define RI_HYSCR3_PF_11                 (0x0800U << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
+#define RI_HYSCR3_PF_12                 (0x1000U << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
+#define RI_HYSCR3_PF_13                 (0x2000U << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
+#define RI_HYSCR3_PF_14                 (0x4000U << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
+#define RI_HYSCR3_PF_15                 (0x8000U << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
+/********************  Bit definition for RI_HYSCR4 register  ********************/
+#define RI_HYSCR4_PG_Pos                (0U)                                   
+#define RI_HYSCR4_PG_Msk                (0xFFFFU << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
+#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
+#define RI_HYSCR4_PG_0                  (0x0001U << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
+#define RI_HYSCR4_PG_1                  (0x0002U << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
+#define RI_HYSCR4_PG_2                  (0x0004U << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
+#define RI_HYSCR4_PG_3                  (0x0008U << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
+#define RI_HYSCR4_PG_4                  (0x0010U << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
+#define RI_HYSCR4_PG_5                  (0x0020U << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
+#define RI_HYSCR4_PG_6                  (0x0040U << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
+#define RI_HYSCR4_PG_7                  (0x0080U << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
+#define RI_HYSCR4_PG_8                  (0x0100U << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
+#define RI_HYSCR4_PG_9                  (0x0200U << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
+#define RI_HYSCR4_PG_10                 (0x0400U << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
+#define RI_HYSCR4_PG_11                 (0x0800U << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
+#define RI_HYSCR4_PG_12                 (0x1000U << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
+#define RI_HYSCR4_PG_13                 (0x2000U << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
+#define RI_HYSCR4_PG_14                 (0x4000U << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
+#define RI_HYSCR4_PG_15                 (0x8000U << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
 
 /********************  Bit definition for RI_ASMR1 register  ********************/
 #define RI_ASMR1_PA_Pos                 (0U)                                   
@@ -6304,6 +6352,132 @@
 #define RI_CICR3_PC_14                  (0x4000U << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
 #define RI_CICR3_PC_15                  (0x8000U << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
 
+/********************  Bit definition for RI_ASMR4 register  ********************/
+#define RI_ASMR4_PF_Pos                 (0U)                                   
+#define RI_ASMR4_PF_Msk                 (0xFFFFU << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
+#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
+#define RI_ASMR4_PF_0                   (0x0001U << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
+#define RI_ASMR4_PF_1                   (0x0002U << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
+#define RI_ASMR4_PF_2                   (0x0004U << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
+#define RI_ASMR4_PF_3                   (0x0008U << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
+#define RI_ASMR4_PF_4                   (0x0010U << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
+#define RI_ASMR4_PF_5                   (0x0020U << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
+#define RI_ASMR4_PF_6                   (0x0040U << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
+#define RI_ASMR4_PF_7                   (0x0080U << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
+#define RI_ASMR4_PF_8                   (0x0100U << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
+#define RI_ASMR4_PF_9                   (0x0200U << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
+#define RI_ASMR4_PF_10                  (0x0400U << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
+#define RI_ASMR4_PF_11                  (0x0800U << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
+#define RI_ASMR4_PF_12                  (0x1000U << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
+#define RI_ASMR4_PF_13                  (0x2000U << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
+#define RI_ASMR4_PF_14                  (0x4000U << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
+#define RI_ASMR4_PF_15                  (0x8000U << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CMR4 register  ********************/
+#define RI_CMR4_PF_Pos                  (0U)                                   
+#define RI_CMR4_PF_Msk                  (0xFFFFU << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
+#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
+#define RI_CMR4_PF_0                    (0x0001U << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
+#define RI_CMR4_PF_1                    (0x0002U << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
+#define RI_CMR4_PF_2                    (0x0004U << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
+#define RI_CMR4_PF_3                    (0x0008U << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
+#define RI_CMR4_PF_4                    (0x0010U << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
+#define RI_CMR4_PF_5                    (0x0020U << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
+#define RI_CMR4_PF_6                    (0x0040U << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
+#define RI_CMR4_PF_7                    (0x0080U << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
+#define RI_CMR4_PF_8                    (0x0100U << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
+#define RI_CMR4_PF_9                    (0x0200U << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
+#define RI_CMR4_PF_10                   (0x0400U << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
+#define RI_CMR4_PF_11                   (0x0800U << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
+#define RI_CMR4_PF_12                   (0x1000U << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
+#define RI_CMR4_PF_13                   (0x2000U << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
+#define RI_CMR4_PF_14                   (0x4000U << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
+#define RI_CMR4_PF_15                   (0x8000U << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CICR4 register  ********************/
+#define RI_CICR4_PF_Pos                 (0U)                                   
+#define RI_CICR4_PF_Msk                 (0xFFFFU << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
+#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
+#define RI_CICR4_PF_0                   (0x0001U << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
+#define RI_CICR4_PF_1                   (0x0002U << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
+#define RI_CICR4_PF_2                   (0x0004U << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
+#define RI_CICR4_PF_3                   (0x0008U << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
+#define RI_CICR4_PF_4                   (0x0010U << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
+#define RI_CICR4_PF_5                   (0x0020U << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
+#define RI_CICR4_PF_6                   (0x0040U << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
+#define RI_CICR4_PF_7                   (0x0080U << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
+#define RI_CICR4_PF_8                   (0x0100U << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
+#define RI_CICR4_PF_9                   (0x0200U << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
+#define RI_CICR4_PF_10                  (0x0400U << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
+#define RI_CICR4_PF_11                  (0x0800U << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
+#define RI_CICR4_PF_12                  (0x1000U << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
+#define RI_CICR4_PF_13                  (0x2000U << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
+#define RI_CICR4_PF_14                  (0x4000U << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
+#define RI_CICR4_PF_15                  (0x8000U << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_ASMR5 register  ********************/
+#define RI_ASMR5_PG_Pos                 (0U)                                   
+#define RI_ASMR5_PG_Msk                 (0xFFFFU << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
+#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
+#define RI_ASMR5_PG_0                   (0x0001U << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
+#define RI_ASMR5_PG_1                   (0x0002U << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
+#define RI_ASMR5_PG_2                   (0x0004U << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
+#define RI_ASMR5_PG_3                   (0x0008U << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
+#define RI_ASMR5_PG_4                   (0x0010U << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
+#define RI_ASMR5_PG_5                   (0x0020U << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
+#define RI_ASMR5_PG_6                   (0x0040U << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
+#define RI_ASMR5_PG_7                   (0x0080U << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
+#define RI_ASMR5_PG_8                   (0x0100U << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
+#define RI_ASMR5_PG_9                   (0x0200U << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
+#define RI_ASMR5_PG_10                  (0x0400U << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
+#define RI_ASMR5_PG_11                  (0x0800U << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
+#define RI_ASMR5_PG_12                  (0x1000U << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
+#define RI_ASMR5_PG_13                  (0x2000U << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
+#define RI_ASMR5_PG_14                  (0x4000U << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
+#define RI_ASMR5_PG_15                  (0x8000U << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CMR5 register  ********************/
+#define RI_CMR5_PG_Pos                  (0U)                                   
+#define RI_CMR5_PG_Msk                  (0xFFFFU << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
+#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
+#define RI_CMR5_PG_0                    (0x0001U << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
+#define RI_CMR5_PG_1                    (0x0002U << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
+#define RI_CMR5_PG_2                    (0x0004U << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
+#define RI_CMR5_PG_3                    (0x0008U << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
+#define RI_CMR5_PG_4                    (0x0010U << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
+#define RI_CMR5_PG_5                    (0x0020U << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
+#define RI_CMR5_PG_6                    (0x0040U << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
+#define RI_CMR5_PG_7                    (0x0080U << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
+#define RI_CMR5_PG_8                    (0x0100U << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
+#define RI_CMR5_PG_9                    (0x0200U << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
+#define RI_CMR5_PG_10                   (0x0400U << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
+#define RI_CMR5_PG_11                   (0x0800U << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
+#define RI_CMR5_PG_12                   (0x1000U << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
+#define RI_CMR5_PG_13                   (0x2000U << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
+#define RI_CMR5_PG_14                   (0x4000U << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
+#define RI_CMR5_PG_15                   (0x8000U << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CICR5 register  ********************/
+#define RI_CICR5_PG_Pos                 (0U)                                   
+#define RI_CICR5_PG_Msk                 (0xFFFFU << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
+#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
+#define RI_CICR5_PG_0                   (0x0001U << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
+#define RI_CICR5_PG_1                   (0x0002U << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
+#define RI_CICR5_PG_2                   (0x0004U << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
+#define RI_CICR5_PG_3                   (0x0008U << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
+#define RI_CICR5_PG_4                   (0x0010U << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
+#define RI_CICR5_PG_5                   (0x0020U << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
+#define RI_CICR5_PG_6                   (0x0040U << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
+#define RI_CICR5_PG_7                   (0x0080U << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
+#define RI_CICR5_PG_8                   (0x0100U << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
+#define RI_CICR5_PG_9                   (0x0200U << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
+#define RI_CICR5_PG_10                  (0x0400U << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
+#define RI_CICR5_PG_11                  (0x0800U << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
+#define RI_CICR5_PG_12                  (0x1000U << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
+#define RI_CICR5_PG_13                  (0x2000U << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
+#define RI_CICR5_PG_14                  (0x4000U << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
+#define RI_CICR5_PG_15                  (0x8000U << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
+
 /******************************************************************************/
 /*                                                                            */
 /*                               Timers (TIM)                                 */
@@ -8481,24 +8655,58 @@
 
 /*******************  Bit definition for SCB_CFSR register  *******************/
 /*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)    /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)  /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
 #define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)    /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)      /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
 #define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)    /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)     /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
 #define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)    /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)       /*!< SCB CFSR (MMFSR): MSTKERR Mask */
 #define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)    /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)     /*!< SCB CFSR (MMFSR): MMARVALID Mask */
 #define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */
 /*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)       /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)        /*!< SCB CFSR (BFSR): IBUSERR Mask */
 #define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)       /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)      /*!< SCB CFSR (BFSR): PRECISERR Mask */
 #define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)       /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)    /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
 #define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)       /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)       /*!< SCB CFSR (BFSR): UNSTKERR Mask */
 #define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)       /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)         /*!< SCB CFSR (BFSR): STKERR Mask */
 #define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)       /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)      /*!< SCB CFSR (BFSR): BFARVALID Mask */
 #define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */
 /*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)       /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)     /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
 #define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)       /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)       /*!< SCB CFSR (UFSR): INVSTATE Mask */
 #define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)       /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)          /*!< SCB CFSR (UFSR): INVPC Mask */
 #define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)       /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)           /*!< SCB CFSR (UFSR): NOCP Mask */
 #define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)       /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)      /*!< SCB CFSR (UFSR): UNALIGNED Mask */
 #define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)       /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)      /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
 #define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
 
 /*******************  Bit definition for SCB_HFSR register  *******************/

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/stm32l1xx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
   *
   *          The file is the unique include file that the application programmer
@@ -18,7 +16,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -121,7 +119,7 @@
   */
 #define __STM32L1xx_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
 #define __STM32L1xx_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32L1xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32L1xx_CMSIS_VERSION        ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_clock.c	Thu Apr 19 17:12:19 2018 +0100
@@ -249,12 +249,4 @@
     return 1; // OK
 }
 
-/******************************************************************************/
-/*            Hard Fault Handler                                              */
-/******************************************************************************/
-void HardFault_Handler(void)
-{
-    debug("Hard Fault\n");
-    NVIC_SystemReset();
-}
 

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_stm32l1xx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_MTS_XDOT/device/system_stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    system_stm32l1xx.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PeripheralNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,76 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE
+} UARTName;
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE
+} I2CName;
+
+typedef enum {
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE, // used as us_ticker
+    PWM_9  = (int)TIM9_BASE,
+    PWM_10 = (int)TIM10_BASE,
+    PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PeripheralPins.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,125 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PB_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC_IN18
+    {PB_14, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 20, 0)}, // ADC_IN20
+    {PB_15, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 21, 0)}, // ADC_IN21
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_ADC_Internal[] = {
+    {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)},
+    {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {NC,    NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// TIM5 cannot be used because already used by the us_ticker.
+const PinMap PinMap_PWM[] = {
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)},  // TIM2_CH3
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)},  // TIM2_CH4
+    {NC,    NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC,    NC,     0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {NC,    NC,     0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_12,     SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_15,     SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC,        NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_14,     SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC,        NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3,      SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {NC,        NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_15,     SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_12,     SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC,        NC,    0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/PinNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,148 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12, // not used
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_13 = 0x2D,
+    PC_14 = 0x2E, // not used ?
+    PC_15 = 0x2F, // not used ?
+
+    PH_0  = 0x70,
+    PH_1  = 0x71, // not used ?
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+
+    ADC1_0   = PB_14,
+    ADC1_1   = PB_15,
+    ADC1_2   = PB_12,
+
+    UARTn_RX = PA_10,
+    UARTn_TX = PA_9,
+
+    SPI_RF_MOSI = PA_7,
+    SPI_RF_MISO = PA_6,
+    SPI_RF_SCK  = PA_5,
+    SPI_RF_CS   = PB_0,
+    SPI_RF_RESET= PB_13,
+
+    DIO0        = PA_11,
+    DIO1        = PB_1,
+    DIO2        = PA_3,
+    DIO3        = PH_0,
+    DIO4        = PC_13,
+    //DIO5        = ,
+
+    ANT_CTX_PA  = PA_4,
+    ANT_CRX_RX  = PB_6,
+    ANT_CBT_HF  = PB_7,
+    RF_TCXO_EN  = PH_1,
+
+    SPI_MISO    = PB_4,
+    SPI_MOSI    = PB_5,
+    SPI_SCK     = PB_3,
+    FLASH_CS    = PA_15,
+
+    I2C_SCL     = PB_8,
+    I2C_SDA     = PB_0,
+
+    LCD_A0      = PA_8,
+    LCD_nCS     = PA_1,
+    LCD_nRESET  = PA_2,
+
+    // Generic signals namings
+    LED1        = PA_12, // red
+    LED2        = PB_10, // blue
+    LED3        = PB_11, // green
+    USER_BUTTON = PA_0,
+
+    STDIO_UART_RX = PA_10,
+    STDIO_UART_TX = PA_9,
+
+    // aliases
+    POT         = ADC1_2,
+    BUTTON1     = USER_BUTTON,
+    SERIAL_TX   = STDIO_UART_TX,
+    SERIAL_RX   = STDIO_UART_RX,
+    USBTX       = STDIO_UART_TX,
+    USBRX       = STDIO_UART_RX,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xba.S	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,306 @@
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l151xb.s
+;* Author             : MCD Application Team
+;* Version            : V2.2.0
+;* Date               : 01-July-2016
+;* Description        : STM32L151XB Devices vector for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Configure the system clock
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* COPYRIGHT(c) 2016 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __initial_sp
+
+Stack_Mem       SPACE   Stack_Size
+__initial_sp    EQU     0x20008000 ; Top of RAM (32 KB)
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit    EQU (__initial_sp - Stack_Size)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
+                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
+                DCD     FLASH_IRQHandler          ; FLASH
+                DCD     RCC_IRQHandler            ; RCC
+                DCD     EXTI0_IRQHandler          ; EXTI Line 0
+                DCD     EXTI1_IRQHandler          ; EXTI Line 1
+                DCD     EXTI2_IRQHandler          ; EXTI Line 2
+                DCD     EXTI3_IRQHandler          ; EXTI Line 3
+                DCD     EXTI4_IRQHandler          ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler           ; ADC1
+                DCD     USB_HP_IRQHandler         ; USB High Priority
+                DCD     USB_LP_IRQHandler         ; USB Low  Priority
+                DCD     DAC_IRQHandler            ; DAC
+                DCD     COMP_IRQHandler           ; COMP through EXTI Line
+                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+                DCD     0                         ; Reserved
+                DCD     TIM9_IRQHandler           ; TIM9
+                DCD     TIM10_IRQHandler          ; TIM10
+                DCD     TIM11_IRQHandler          ; TIM11
+                DCD     TIM2_IRQHandler           ; TIM2
+                DCD     TIM3_IRQHandler           ; TIM3
+                DCD     TIM4_IRQHandler           ; TIM4
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+                DCD     SPI1_IRQHandler           ; SPI1
+                DCD     SPI2_IRQHandler           ; SPI2
+                DCD     USART1_IRQHandler         ; USART1
+                DCD     USART2_IRQHandler         ; USART2
+                DCD     USART3_IRQHandler         ; USART3
+                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
+                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
+                DCD     TIM6_IRQHandler           ; TIM6
+                DCD     TIM7_IRQHandler           ; TIM7
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_IRQHandler            [WEAK]
+                EXPORT  USB_HP_IRQHandler          [WEAK]
+                EXPORT  USB_LP_IRQHandler          [WEAK]
+                EXPORT  DAC_IRQHandler             [WEAK]
+                EXPORT  COMP_IRQHandler            [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM9_IRQHandler            [WEAK]
+                EXPORT  TIM10_IRQHandler           [WEAK]
+                EXPORT  TIM11_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
+                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM9_IRQHandler
+TIM10_IRQHandler
+TIM11_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USB_FS_WKUP_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_MICRO/stm32l151cba.sct	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32L151CB: 128KB FLASH + 32KB SRAM
+LR_IROM1 0x08000000 0x20000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x20000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; 61 vectors = 244 bytes (0xF4) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0xF4) (0x8000-0xF4)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_STD/startup_stm32l151xba.S	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,285 @@
+;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l151xb.s
+;* Author             : MCD Application Team
+;* Version            : V2.2.0
+;* Date               : 01-July-2016
+;* Description        : STM32L151XB Devices vector for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Configure the system clock
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* COPYRIGHT(c) 2016 STMicroelectronics
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*******************************************************************************
+;
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+__initial_sp    EQU     0x20008000 ; Top of RAM (32 KB)
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler           ; Window Watchdog
+                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
+                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
+                DCD     FLASH_IRQHandler          ; FLASH
+                DCD     RCC_IRQHandler            ; RCC
+                DCD     EXTI0_IRQHandler          ; EXTI Line 0
+                DCD     EXTI1_IRQHandler          ; EXTI Line 1
+                DCD     EXTI2_IRQHandler          ; EXTI Line 2
+                DCD     EXTI3_IRQHandler          ; EXTI Line 3
+                DCD     EXTI4_IRQHandler          ; EXTI Line 4
+                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+                DCD     ADC1_IRQHandler           ; ADC1
+                DCD     USB_HP_IRQHandler         ; USB High Priority
+                DCD     USB_LP_IRQHandler         ; USB Low  Priority
+                DCD     DAC_IRQHandler            ; DAC
+                DCD     COMP_IRQHandler           ; COMP through EXTI Line
+                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+                DCD     0                         ; Reserved
+                DCD     TIM9_IRQHandler           ; TIM9
+                DCD     TIM10_IRQHandler          ; TIM10
+                DCD     TIM11_IRQHandler          ; TIM11
+                DCD     TIM2_IRQHandler           ; TIM2
+                DCD     TIM3_IRQHandler           ; TIM3
+                DCD     TIM4_IRQHandler           ; TIM4
+                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+                DCD     SPI1_IRQHandler           ; SPI1
+                DCD     SPI2_IRQHandler           ; SPI2
+                DCD     USART1_IRQHandler         ; USART1
+                DCD     USART2_IRQHandler         ; USART2
+                DCD     USART3_IRQHandler         ; USART3
+                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
+                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
+                DCD     TIM6_IRQHandler           ; TIM6
+                DCD     TIM7_IRQHandler           ; TIM7
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler routine
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+     IMPORT  __main
+     IMPORT  SystemInit
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler            [WEAK]
+                EXPORT  PVD_IRQHandler             [WEAK]
+                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
+                EXPORT  FLASH_IRQHandler           [WEAK]
+                EXPORT  RCC_IRQHandler             [WEAK]
+                EXPORT  EXTI0_IRQHandler           [WEAK]
+                EXPORT  EXTI1_IRQHandler           [WEAK]
+                EXPORT  EXTI2_IRQHandler           [WEAK]
+                EXPORT  EXTI3_IRQHandler           [WEAK]
+                EXPORT  EXTI4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
+                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
+                EXPORT  ADC1_IRQHandler            [WEAK]
+                EXPORT  USB_HP_IRQHandler          [WEAK]
+                EXPORT  USB_LP_IRQHandler          [WEAK]
+                EXPORT  DAC_IRQHandler             [WEAK]
+                EXPORT  COMP_IRQHandler            [WEAK]
+                EXPORT  EXTI9_5_IRQHandler         [WEAK]
+                EXPORT  TIM9_IRQHandler            [WEAK]
+                EXPORT  TIM10_IRQHandler           [WEAK]
+                EXPORT  TIM11_IRQHandler           [WEAK]
+                EXPORT  TIM2_IRQHandler            [WEAK]
+                EXPORT  TIM3_IRQHandler            [WEAK]
+                EXPORT  TIM4_IRQHandler            [WEAK]
+                EXPORT  I2C1_EV_IRQHandler         [WEAK]
+                EXPORT  I2C1_ER_IRQHandler         [WEAK]
+                EXPORT  I2C2_EV_IRQHandler         [WEAK]
+                EXPORT  I2C2_ER_IRQHandler         [WEAK]
+                EXPORT  SPI1_IRQHandler            [WEAK]
+                EXPORT  SPI2_IRQHandler            [WEAK]
+                EXPORT  USART1_IRQHandler          [WEAK]
+                EXPORT  USART2_IRQHandler          [WEAK]
+                EXPORT  USART3_IRQHandler          [WEAK]
+                EXPORT  EXTI15_10_IRQHandler       [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
+                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
+                EXPORT  TIM6_IRQHandler            [WEAK]
+                EXPORT  TIM7_IRQHandler            [WEAK]
+
+WWDG_IRQHandler
+PVD_IRQHandler
+TAMPER_STAMP_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Channel1_IRQHandler
+DMA1_Channel2_IRQHandler
+DMA1_Channel3_IRQHandler
+DMA1_Channel4_IRQHandler
+DMA1_Channel5_IRQHandler
+DMA1_Channel6_IRQHandler
+DMA1_Channel7_IRQHandler
+ADC1_IRQHandler
+USB_HP_IRQHandler
+USB_LP_IRQHandler
+DAC_IRQHandler
+COMP_IRQHandler
+EXTI9_5_IRQHandler
+TIM9_IRQHandler
+TIM10_IRQHandler
+TIM11_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+USB_FS_WKUP_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_ARM_STD/stm32l151cba.sct	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,45 @@
+; Scatter-Loading Description File
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Copyright (c) 2015, STMicroelectronics
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+;
+; 1. Redistributions of source code must retain the above copyright notice,
+;     this list of conditions and the following disclaimer.
+; 2. Redistributions in binary form must reproduce the above copyright notice,
+;    this list of conditions and the following disclaimer in the documentation
+;    and/or other materials provided with the distribution.
+; 3. Neither the name of STMicroelectronics nor the names of its contributors
+;    may be used to endorse or promote products derived from this software
+;    without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+; STM32L151CB: 128KB FLASH + 32KB SRAM
+LR_IROM1 0x08000000 0x20000  {    ; load region size_region
+
+  ER_IROM1 0x08000000 0x20000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  ; 61 vectors = 244 bytes (0xF4) to be reserved in RAM
+  RW_IRAM1 (0x20000000+0xF4) (0x8000-0xF4)  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+
+}
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_GCC_ARM/STM32L151XB-A.ld	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,157 @@
+/* Linker script to configure memory regions. */
+
+MEMORY
+{
+  /* 128KB FLASH, 32KB RAM, Reserve up till 0xF4. There are 61 vectors = 244
+   * bytes (0xF4) in RAM.
+   */
+  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128k
+  RAM (rwx) : ORIGIN = 0x200000F4, LENGTH = 0x8000-0xF4
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.isr_vector))
+        *(.text*)
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab : 
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+    _sidata = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        _sdata = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        KEEP(*(.jcr*))
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+        _edata = .;
+
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        _sbss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+        _ebss = .;
+    } > RAM
+
+    .heap (COPY):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*)
+        __HeapLimit = .;
+    } > RAM
+
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (COPY):
+    {
+        *(.stack*)
+    } > RAM
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    _estack = __StackTop;
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+    PROVIDE(__stack = __StackTop);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xba.S	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,363 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32l151xb.s
+  * @author    MCD Application Team
+  * @version   V2.2.0
+  * @date      01-July-2016
+  * @brief     STM32L151XB Devices vector table for 
+  *            Atollic toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M3 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+
+/* Call the clock system intitialization function.*/
+    bl  SystemInit
+
+/**
+ * Calling the crt0 'cold-start' entry point. There __libc_init_array is called
+ * and when existing hardware_init_hook() and software_init_hook() before 
+ * starting main(). software_init_hook() is available and has to be called due 
+ * to initializsation when using rtos.
+*/
+    bl _start
+    bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+  .word WWDG_IRQHandler
+  .word PVD_IRQHandler
+  .word TAMPER_STAMP_IRQHandler
+  .word RTC_WKUP_IRQHandler
+  .word FLASH_IRQHandler
+  .word RCC_IRQHandler
+  .word EXTI0_IRQHandler
+  .word EXTI1_IRQHandler
+  .word EXTI2_IRQHandler
+  .word EXTI3_IRQHandler
+  .word EXTI4_IRQHandler
+  .word DMA1_Channel1_IRQHandler
+  .word DMA1_Channel2_IRQHandler
+  .word DMA1_Channel3_IRQHandler
+  .word DMA1_Channel4_IRQHandler
+  .word DMA1_Channel5_IRQHandler
+  .word DMA1_Channel6_IRQHandler
+  .word DMA1_Channel7_IRQHandler
+  .word ADC1_IRQHandler
+  .word USB_HP_IRQHandler
+  .word USB_LP_IRQHandler
+  .word DAC_IRQHandler
+  .word COMP_IRQHandler
+  .word EXTI9_5_IRQHandler
+  .word 0  
+  .word TIM9_IRQHandler
+  .word TIM10_IRQHandler
+  .word TIM11_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM4_IRQHandler
+  .word I2C1_EV_IRQHandler
+  .word I2C1_ER_IRQHandler
+  .word I2C2_EV_IRQHandler
+  .word I2C2_ER_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word USART1_IRQHandler
+  .word USART2_IRQHandler
+  .word USART3_IRQHandler
+  .word EXTI15_10_IRQHandler
+  .word RTC_Alarm_IRQHandler
+  .word USB_FS_WKUP_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WWDG_IRQHandler
+  .thumb_set WWDG_IRQHandler,Default_Handler
+
+  .weak PVD_IRQHandler
+  .thumb_set PVD_IRQHandler,Default_Handler
+
+  .weak TAMPER_STAMP_IRQHandler
+  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
+
+  .weak RTC_WKUP_IRQHandler
+  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+  .weak FLASH_IRQHandler
+  .thumb_set FLASH_IRQHandler,Default_Handler
+
+  .weak RCC_IRQHandler
+  .thumb_set RCC_IRQHandler,Default_Handler
+
+  .weak EXTI0_IRQHandler
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+
+  .weak EXTI1_IRQHandler
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+
+  .weak EXTI2_IRQHandler
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+
+  .weak EXTI3_IRQHandler
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+
+  .weak EXTI4_IRQHandler
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel1_IRQHandler
+  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel2_IRQHandler
+  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel3_IRQHandler
+  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel4_IRQHandler
+  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel5_IRQHandler
+  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel6_IRQHandler
+  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+  .weak DMA1_Channel7_IRQHandler
+  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+  .weak ADC1_IRQHandler
+  .thumb_set ADC1_IRQHandler,Default_Handler
+
+  .weak USB_HP_IRQHandler
+  .thumb_set USB_HP_IRQHandler,Default_Handler
+
+  .weak USB_LP_IRQHandler
+  .thumb_set USB_LP_IRQHandler,Default_Handler
+
+  .weak DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak COMP_IRQHandler
+  .thumb_set COMP_IRQHandler,Default_Handler
+
+  .weak EXTI9_5_IRQHandler
+  .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+  .weak TIM9_IRQHandler
+  .thumb_set TIM9_IRQHandler,Default_Handler
+
+  .weak TIM10_IRQHandler
+  .thumb_set TIM10_IRQHandler,Default_Handler
+
+  .weak TIM11_IRQHandler
+  .thumb_set TIM11_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak I2C1_EV_IRQHandler
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+  .weak I2C1_ER_IRQHandler
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+  .weak I2C2_EV_IRQHandler
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+  .weak I2C2_ER_IRQHandler
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak USART1_IRQHandler
+  .thumb_set USART1_IRQHandler,Default_Handler
+
+  .weak USART2_IRQHandler
+  .thumb_set USART2_IRQHandler,Default_Handler
+
+  .weak USART3_IRQHandler
+  .thumb_set USART3_IRQHandler,Default_Handler
+
+  .weak EXTI15_10_IRQHandler
+  .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+  .weak RTC_Alarm_IRQHandler
+  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+  .weak USB_FS_WKUP_IRQHandler
+  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
+
+  .weak TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_IAR/startup_stm32l151xba.S	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,471 @@
+;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;* File Name          : startup_stm32l152xc.s
+;* Author             : MCD Application Team
+;* Version            : V2.2.0
+;* Date               : 01-July-2016
+;* Description        : STM32L152XC Devices vector for EWARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == __iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      - Configure the system clock
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+;*
+;* Redistribution and use in source and binary forms, with or without modification,
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit        
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler           ; Window Watchdog
+        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
+        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
+        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
+        DCD     FLASH_IRQHandler          ; FLASH
+        DCD     RCC_IRQHandler            ; RCC
+        DCD     EXTI0_IRQHandler          ; EXTI Line 0
+        DCD     EXTI1_IRQHandler          ; EXTI Line 1
+        DCD     EXTI2_IRQHandler          ; EXTI Line 2
+        DCD     EXTI3_IRQHandler          ; EXTI Line 3
+        DCD     EXTI4_IRQHandler          ; EXTI Line 4
+        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
+        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
+        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
+        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
+        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
+        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
+        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
+        DCD     ADC1_IRQHandler           ; ADC1
+        DCD     USB_HP_IRQHandler         ; USB High Priority
+        DCD     USB_LP_IRQHandler         ; USB Low  Priority
+        DCD     DAC_IRQHandler            ; DAC
+        DCD     COMP_IRQHandler           ; COMP through EXTI Line
+        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
+        DCD     0                         ; Reserved
+        DCD     TIM9_IRQHandler           ; TIM9
+        DCD     TIM10_IRQHandler          ; TIM10
+        DCD     TIM11_IRQHandler          ; TIM11
+        DCD     TIM2_IRQHandler           ; TIM2
+        DCD     TIM3_IRQHandler           ; TIM3
+        DCD     TIM4_IRQHandler           ; TIM4
+        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
+        DCD     SPI1_IRQHandler           ; SPI1
+        DCD     SPI2_IRQHandler           ; SPI2
+        DCD     USART1_IRQHandler         ; USART1
+        DCD     USART2_IRQHandler         ; USART2
+        DCD     USART3_IRQHandler         ; USART3
+        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
+        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
+        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
+        DCD     TIM6_IRQHandler           ; TIM6
+        DCD     TIM7_IRQHandler           ; TIM7
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B NMI_Handler
+        
+        
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B HardFault_Handler
+        
+        
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+        B MemManage_Handler
+        
+                
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+        B BusFault_Handler
+        
+        
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+        B UsageFault_Handler
+        
+        
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B SVC_Handler
+        
+        
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+        B DebugMon_Handler
+        
+        
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B PendSV_Handler
+        
+        
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B SysTick_Handler
+        
+        
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+        
+        
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PVD_IRQHandler
+        B PVD_IRQHandler
+        
+        
+        PUBWEAK TAMPER_STAMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TAMPER_STAMP_IRQHandler
+        B TAMPER_STAMP_IRQHandler
+        
+        
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+        
+        
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+        
+        
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+        
+        
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+        
+        
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+        
+        
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+        
+        
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+        
+        
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel1_IRQHandler
+        B DMA1_Channel1_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel2_IRQHandler
+        B DMA1_Channel2_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel3_IRQHandler
+        B DMA1_Channel3_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel4_IRQHandler
+        B DMA1_Channel4_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel5_IRQHandler
+        B DMA1_Channel5_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel6_IRQHandler
+        B DMA1_Channel6_IRQHandler
+        
+        
+        PUBWEAK DMA1_Channel7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DMA1_Channel7_IRQHandler
+        B DMA1_Channel7_IRQHandler
+        
+        
+        PUBWEAK ADC1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC1_IRQHandler
+        B ADC1_IRQHandler
+        
+        
+        PUBWEAK USB_HP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USB_HP_IRQHandler
+        B USB_HP_IRQHandler
+        
+        
+        PUBWEAK USB_LP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USB_LP_IRQHandler
+        B USB_LP_IRQHandler
+        
+        
+        PUBWEAK DAC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+DAC_IRQHandler
+        B DAC_IRQHandler
+        
+        
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+        
+        
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+        
+        
+        PUBWEAK TIM9_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM9_IRQHandler
+        B TIM9_IRQHandler
+        
+        
+        PUBWEAK TIM10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM10_IRQHandler
+        B TIM10_IRQHandler
+        
+        
+        PUBWEAK TIM11_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM11_IRQHandler
+        B TIM11_IRQHandler
+        
+        
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+        
+        
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+        
+        
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+        
+        
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+        
+        
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+        
+        
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+        
+        
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+        
+        
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+        
+        
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+        
+        
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+        
+        
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+        
+        
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+        
+        
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+        
+        
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+        
+        
+        PUBWEAK USB_FS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+USB_FS_WKUP_IRQHandler
+        B USB_FS_WKUP_IRQHandler
+        
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+        
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/TOOLCHAIN_IAR/stm32l152xba.icf	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,32 @@
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x08000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x20000; }
+/* [ROM = 128kb = 0x20000] */
+define symbol __intvec_start__     = MBED_APP_START;
+define symbol __region_ROM_start__ = MBED_APP_START;
+define symbol __region_ROM_end__   = MBED_APP_START + MBED_APP_SIZE - 1;
+
+/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 61 vectors = 244 bytes (0xF4) to be reserved in RAM */
+define symbol __NVIC_start__          = 0x20000000;
+define symbol __NVIC_end__            = 0x200000F3;
+define symbol __region_RAM_start__    = 0x200000F4;
+define symbol __region_RAM_end__      = 0x20007FFF;
+
+/* Memory regions */
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x800;
+define symbol __size_heap__   = 0x800;
+define block CSTACK    with alignment = 8, size = __size_cstack__   { };
+define block HEAP      with alignment = 8, size = __size_heap__     { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy with packing = zeros { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite, block STACKHEAP };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/cmsis.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,38 @@
+/* mbed Microcontroller Library
+ * A generic CMSIS include header
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "stm32l1xx.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/cmsis_nvic.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+// STM32L151CB
+// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
+// MCU Peripherals: 45 vectors = 180 bytes from 0x40 to 0xF3
+// Total: 61 vectors = 244 bytes (0xF4) to be reserved in RAM
+#define NVIC_NUM_VECTORS        61
+#define NVIC_RAM_VECTOR_ADDRESS 0x20000000    // Vectors positioned at start of RAM
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/hal_tick.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,66 @@
+/**
+  ******************************************************************************
+  * @file    hal_tick.h
+  * @author  MCD Application Team
+  * @brief   Initialization of HAL tick
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HAL_TICK_H
+#define __HAL_TICK_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "stm32l1xx.h"
+#include "stm32l1xx_ll_tim.h"
+#include "cmsis_nvic.h"
+
+#define TIM_MST      TIM4
+#define TIM_MST_IRQ  TIM4_IRQn
+#define TIM_MST_RCC  __TIM4_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
+
+#define TIM_MST_RESET_ON   __TIM4_FORCE_RESET()
+#define TIM_MST_RESET_OFF  __TIM4_RELEASE_RESET()
+
+#define TIM_MST_16BIT  1 // 1=16-bit timer, 0=32-bit timer
+
+#define TIM_MST_PCLK  1 // Select the peripheral clock number (1 or 2)
+
+#define HAL_TICK_DELAY (1000) // 1 ms
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __HAL_TICK_H
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/stm32l151xba.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,8167 @@
+/**
+  ******************************************************************************
+  * @file    stm32l151xba.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+  *          This file contains all the peripheral register's definitions, bits
+  *          definitions and memory mapping for STM32L1xx devices.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l151xba
+  * @{
+  */
+
+#ifndef __STM32L151xBA_H
+#define __STM32L151xBA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+  /** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+/**
+  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
+ */
+#define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
+#define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
+#define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
+#define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+
+ /*!< Interrupt Number Definition */
+typedef enum
+{
+/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
+  HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
+  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
+
+/******  STM32L specific Interrupt Numbers ***********************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
+  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
+  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
+  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
+  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
+  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
+  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
+  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
+  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
+  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
+  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
+  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
+  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
+  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
+  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
+  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
+  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
+  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
+  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
+  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm3.h"
+#include "system_stm32l1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */
+
+/**
+  * @brief Analog to Digital Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
+  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
+  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
+  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
+  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
+  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
+  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
+  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
+  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
+  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
+  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
+  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
+  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
+  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
+  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
+  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
+  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
+  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
+  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
+  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+} ADC_Common_TypeDef;
+
+/**
+  * @brief Comparator
+  */
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+  * @brief CRC calculation unit
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
+  __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
+  uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
+  uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */
+  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
+  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
+  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
+  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
+  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
+  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
+  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
+  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
+  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
+  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
+  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
+  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
+  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
+  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
+  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
+  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
+  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
+  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
+  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
+  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
+  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
+  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+  * @brief FLASH Registers
+  */
+typedef struct
+{
+  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
+  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
+  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
+  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
+  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
+  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
+  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
+  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
+  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
+} FLASH_TypeDef;
+
+/**
+  * @brief Option Bytes Registers
+  */
+typedef struct
+{
+  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
+  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
+  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
+  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
+} OB_TypeDef;
+
+/**
+  * @brief General Purpose IO
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
+  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
+  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
+  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
+  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
+  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
+  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
+  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/**
+  * @brief SysTem Configuration
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+} SYSCFG_TypeDef;
+
+/**
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
+  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
+  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
+  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
+  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
+  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
+  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
+  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
+  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
+} I2C_TypeDef;
+
+/**
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
+  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
+  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
+  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/**
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
+  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
+  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
+  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
+  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
+  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
+} RCC_TypeDef;
+
+/**
+  * @brief Routing Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
+  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
+  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
+  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
+  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
+  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
+  uint32_t RESERVED1;       /*!< Reserved,                                      Address offset: 0x18 */
+} RI_TypeDef;
+
+/**
+  * @brief Real-Time Clock
+  */
+typedef struct
+{
+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
+  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
+  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
+  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
+} RTC_TypeDef;
+
+/**
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< SPI Control register 1                              Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
+  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
+  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register                         Address offset: 0x10 */
+  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register                                 Address offset: 0x14 */
+  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register                                 Address offset: 0x18 */
+} SPI_TypeDef;
+
+/**
+  * @brief TIM
+  */
+typedef struct
+{
+  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
+  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
+  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */
+  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */
+  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
+} TIM_TypeDef;
+/**
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/**
+  * @brief Universal Serial Bus Full Speed Device
+  */
+
+typedef struct
+{
+  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */
+  __IO uint16_t RESERVED0;       /*!< Reserved */
+  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
+  __IO uint16_t RESERVED1;       /*!< Reserved */
+  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
+  __IO uint16_t RESERVED2;       /*!< Reserved */
+  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */
+  __IO uint16_t RESERVED3;       /*!< Reserved */
+  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
+  __IO uint16_t RESERVED4;       /*!< Reserved */
+  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
+  __IO uint16_t RESERVED5;       /*!< Reserved */
+  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
+  __IO uint16_t RESERVED6;       /*!< Reserved */
+  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
+  __IO uint16_t RESERVED7[17];   /*!< Reserved */
+  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
+  __IO uint16_t RESERVED8;       /*!< Reserved */
+  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
+  __IO uint16_t RESERVED9;       /*!< Reserved */
+  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
+  __IO uint16_t RESERVEDA;       /*!< Reserved */
+  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
+  __IO uint16_t RESERVEDB;       /*!< Reserved */
+  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
+  __IO uint16_t RESERVEDC;       /*!< Reserved */
+} USB_TypeDef;
+
+/**
+  * @brief Window WATCHDOG
+  */
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+  * @brief Universal Serial Bus Full Speed Device
+  */
+/**
+  * @}
+  */
+/** @addtogroup FLASH_Page_Size
+  * @{
+  */
+#define FLASH_SIZE                (uint32_t)(*((uint8_t *)FLASHSIZE_BASE) * 1024U)
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000U)              /*!< FLASH base address in the alias region */
+#define FLASH_EEPROM_BASE     ((uint32_t)(FLASH_BASE + 0x80000U))  /*!< FLASH EEPROM base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000U)              /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000U)              /*!< Peripheral base address in the alias region */
+#define SRAM_BB_BASE          ((uint32_t)0x22000000U)              /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000U)              /*!< Peripheral base address in the bit-band region */
+#define FLASH_END             ((uint32_t)0x0801FFFFU)              /*!< Program end FLASH address for Cat1 & Cat2 */
+#define FLASH_EEPROM_END      ((uint32_t)0x08080FFFU)              /*!< FLASH EEPROM end address (4KB) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800U)
+
+/* USB device FS */
+#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
+#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
+
+/* USB device FS SRAM */
+#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400U)
+#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00U)
+#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04U)
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000U)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800U)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00U)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000U)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700U)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)
+
+/*!< AHB peripherals */
+#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000U)
+#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400U)
+#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800U)
+#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00U)
+#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000U)
+#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400U)
+#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800U)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */
+#define OB_BASE               ((uint32_t)0x1FF80000U)        /*!< FLASH Option Bytes base address */
+#define FLASHSIZE_BASE        ((uint32_t)0x1FF8004CU)        /*!< FLASH Size register base address for Cat.1 and Cat.2 devices */
+#define UID_BASE              ((uint32_t)0x1FF80050U)        /*!< Unique device ID register base address for Cat.1 and Cat.2 devices */
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000U)
+#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008U)
+#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CU)
+#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030U)
+#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044U)
+#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058U)
+#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CU)
+#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080U)
+#define DBGMCU_BASE           ((uint32_t)0xE0042000U)     /*!< Debug MCU registers base address */
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */
+
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+/* USB device FS */
+#define USB                   ((USB_TypeDef *) USB_BASE)
+/* USB device FS SRAM */
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+
+#define DAC1                ((DAC_TypeDef *) DAC_BASE)
+/* Legacy define */
+#define DAC                 DAC1
+
+#define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
+#define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
+#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
+
+#define RI                  ((RI_TypeDef *) RI_BASE)
+
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
+/* Legacy defines */
+#define ADC                 ADC1_COMMON
+
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB                  ((OB_TypeDef *) OB_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+ /**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog to Digital Converter (ADC)                     */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_SR register  ********************/
+#define ADC_SR_AWD_Pos                       (0U)
+#define ADC_SR_AWD_Msk                       (0x1U << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
+#define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
+#define ADC_SR_EOCS_Pos                      (1U)
+#define ADC_SR_EOCS_Msk                      (0x1U << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
+#define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
+#define ADC_SR_JEOS_Pos                      (2U)
+#define ADC_SR_JEOS_Msk                      (0x1U << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
+#define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
+#define ADC_SR_JSTRT_Pos                     (3U)
+#define ADC_SR_JSTRT_Msk                     (0x1U << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
+#define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
+#define ADC_SR_STRT_Pos                      (4U)
+#define ADC_SR_STRT_Msk                      (0x1U << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
+#define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
+#define ADC_SR_OVR_Pos                       (5U)
+#define ADC_SR_OVR_Msk                       (0x1U << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
+#define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
+#define ADC_SR_ADONS_Pos                     (6U)
+#define ADC_SR_ADONS_Msk                     (0x1U << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
+#define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
+#define ADC_SR_RCNR_Pos                      (8U)
+#define ADC_SR_RCNR_Msk                      (0x1U << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
+#define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
+#define ADC_SR_JCNR_Pos                      (9U)
+#define ADC_SR_JCNR_Msk                      (0x1U << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
+#define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
+
+/* Legacy defines */
+#define  ADC_SR_EOC                          (ADC_SR_EOCS)
+#define  ADC_SR_JEOC                         (ADC_SR_JEOS)
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define ADC_CR1_AWDCH_Pos                    (0U)
+#define ADC_CR1_AWDCH_Msk                    (0x1FU << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
+#define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CR1_AWDCH_0                      (0x01U << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1                      (0x02U << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2                      (0x04U << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3                      (0x08U << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4                      (0x10U << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
+
+#define ADC_CR1_EOCSIE_Pos                   (5U)
+#define ADC_CR1_EOCSIE_Msk                   (0x1U << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
+#define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
+#define ADC_CR1_AWDIE_Pos                    (6U)
+#define ADC_CR1_AWDIE_Msk                    (0x1U << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
+#define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
+#define ADC_CR1_JEOSIE_Pos                   (7U)
+#define ADC_CR1_JEOSIE_Msk                   (0x1U << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
+#define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_CR1_SCAN_Pos                     (8U)
+#define ADC_CR1_SCAN_Msk                     (0x1U << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
+#define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
+#define ADC_CR1_AWDSGL_Pos                   (9U)
+#define ADC_CR1_AWDSGL_Msk                   (0x1U << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CR1_JAUTO_Pos                    (10U)
+#define ADC_CR1_JAUTO_Msk                    (0x1U << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
+#define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
+#define ADC_CR1_DISCEN_Pos                   (11U)
+#define ADC_CR1_DISCEN_Msk                   (0x1U << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
+#define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
+#define ADC_CR1_JDISCEN_Pos                  (12U)
+#define ADC_CR1_JDISCEN_Msk                  (0x1U << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
+
+#define ADC_CR1_DISCNUM_Pos                  (13U)
+#define ADC_CR1_DISCNUM_Msk                  (0x7U << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CR1_DISCNUM_0                    (0x1U << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1                    (0x2U << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2                    (0x4U << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
+
+#define ADC_CR1_PDD_Pos                      (16U)
+#define ADC_CR1_PDD_Msk                      (0x1U << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
+#define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
+#define ADC_CR1_PDI_Pos                      (17U)
+#define ADC_CR1_PDI_Msk                      (0x1U << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
+#define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
+
+#define ADC_CR1_JAWDEN_Pos                   (22U)
+#define ADC_CR1_JAWDEN_Msk                   (0x1U << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CR1_AWDEN_Pos                    (23U)
+#define ADC_CR1_AWDEN_Msk                    (0x1U << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
+#define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+
+#define ADC_CR1_RES_Pos                      (24U)
+#define ADC_CR1_RES_Msk                      (0x3U << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
+#define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
+#define ADC_CR1_RES_0                        (0x1U << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
+#define ADC_CR1_RES_1                        (0x2U << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
+
+#define ADC_CR1_OVRIE_Pos                    (26U)
+#define ADC_CR1_OVRIE_Msk                    (0x1U << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
+#define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
+
+/* Legacy defines */
+#define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
+#define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
+
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define ADC_CR2_ADON_Pos                     (0U)
+#define ADC_CR2_ADON_Msk                     (0x1U << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
+#define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
+#define ADC_CR2_CONT_Pos                     (1U)
+#define ADC_CR2_CONT_Msk                     (0x1U << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
+#define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
+
+#define ADC_CR2_DELS_Pos                     (4U)
+#define ADC_CR2_DELS_Msk                     (0x7U << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
+#define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
+#define ADC_CR2_DELS_0                       (0x1U << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
+#define ADC_CR2_DELS_1                       (0x2U << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
+#define ADC_CR2_DELS_2                       (0x4U << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
+
+#define ADC_CR2_DMA_Pos                      (8U)
+#define ADC_CR2_DMA_Msk                      (0x1U << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
+#define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
+#define ADC_CR2_DDS_Pos                      (9U)
+#define ADC_CR2_DDS_Msk                      (0x1U << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
+#define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
+#define ADC_CR2_EOCS_Pos                     (10U)
+#define ADC_CR2_EOCS_Msk                     (0x1U << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
+#define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
+#define ADC_CR2_ALIGN_Pos                    (11U)
+#define ADC_CR2_ALIGN_Msk                    (0x1U << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
+#define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
+
+#define ADC_CR2_JEXTSEL_Pos                  (16U)
+#define ADC_CR2_JEXTSEL_Msk                  (0xFU << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
+#define ADC_CR2_JEXTSEL_0                    (0x1U << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1                    (0x2U << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2                    (0x4U << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3                    (0x8U << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
+
+#define ADC_CR2_JEXTEN_Pos                   (20U)
+#define ADC_CR2_JEXTEN_Msk                   (0x3U << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
+#define ADC_CR2_JEXTEN_0                     (0x1U << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1                     (0x2U << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
+
+#define ADC_CR2_JSWSTART_Pos                 (22U)
+#define ADC_CR2_JSWSTART_Msk                 (0x1U << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
+
+#define ADC_CR2_EXTSEL_Pos                   (24U)
+#define ADC_CR2_EXTSEL_Msk                   (0xFU << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
+#define ADC_CR2_EXTSEL_0                     (0x1U << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1                     (0x2U << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2                     (0x4U << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3                     (0x8U << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
+
+#define ADC_CR2_EXTEN_Pos                    (28U)
+#define ADC_CR2_EXTEN_Msk                    (0x3U << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
+#define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
+#define ADC_CR2_EXTEN_0                      (0x1U << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1                      (0x2U << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
+
+#define ADC_CR2_SWSTART_Pos                  (30U)
+#define ADC_CR2_SWSTART_Msk                  (0x1U << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
+#define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define ADC_SMPR1_SMP20_Pos                  (0U)
+#define ADC_SMPR1_SMP20_Msk                  (0x7U << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
+#define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
+#define ADC_SMPR1_SMP20_0                    (0x1U << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
+#define ADC_SMPR1_SMP20_1                    (0x2U << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
+#define ADC_SMPR1_SMP20_2                    (0x4U << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP21_Pos                  (3U)
+#define ADC_SMPR1_SMP21_Msk                  (0x7U << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
+#define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
+#define ADC_SMPR1_SMP21_0                    (0x1U << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
+#define ADC_SMPR1_SMP21_1                    (0x2U << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
+#define ADC_SMPR1_SMP21_2                    (0x4U << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP22_Pos                  (6U)
+#define ADC_SMPR1_SMP22_Msk                  (0x7U << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
+#define ADC_SMPR1_SMP22_0                    (0x1U << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
+#define ADC_SMPR1_SMP22_1                    (0x2U << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
+#define ADC_SMPR1_SMP22_2                    (0x4U << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP23_Pos                  (9U)
+#define ADC_SMPR1_SMP23_Msk                  (0x7U << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
+#define ADC_SMPR1_SMP23_0                    (0x1U << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
+#define ADC_SMPR1_SMP23_1                    (0x2U << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
+#define ADC_SMPR1_SMP23_2                    (0x4U << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP24_Pos                  (12U)
+#define ADC_SMPR1_SMP24_Msk                  (0x7U << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
+#define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
+#define ADC_SMPR1_SMP24_0                    (0x1U << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
+#define ADC_SMPR1_SMP24_1                    (0x2U << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
+#define ADC_SMPR1_SMP24_2                    (0x4U << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP25_Pos                  (15U)
+#define ADC_SMPR1_SMP25_Msk                  (0x7U << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
+#define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
+#define ADC_SMPR1_SMP25_0                    (0x1U << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
+#define ADC_SMPR1_SMP25_1                    (0x2U << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
+#define ADC_SMPR1_SMP25_2                    (0x4U << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP26_Pos                  (18U)
+#define ADC_SMPR1_SMP26_Msk                  (0x7U << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
+#define ADC_SMPR1_SMP26_0                    (0x1U << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
+#define ADC_SMPR1_SMP26_1                    (0x2U << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
+#define ADC_SMPR1_SMP26_2                    (0x4U << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define ADC_SMPR2_SMP10_Pos                  (0U)
+#define ADC_SMPR2_SMP10_Msk                  (0x7U << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR2_SMP10_0                    (0x1U << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1                    (0x2U << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2                    (0x4U << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos                  (3U)
+#define ADC_SMPR2_SMP11_Msk                  (0x7U << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR2_SMP11_0                    (0x1U << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1                    (0x2U << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2                    (0x4U << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos                  (6U)
+#define ADC_SMPR2_SMP12_Msk                  (0x7U << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR2_SMP12_0                    (0x1U << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1                    (0x2U << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2                    (0x4U << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos                  (9U)
+#define ADC_SMPR2_SMP13_Msk                  (0x7U << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR2_SMP13_0                    (0x1U << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1                    (0x2U << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2                    (0x4U << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos                  (12U)
+#define ADC_SMPR2_SMP14_Msk                  (0x7U << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR2_SMP14_0                    (0x1U << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1                    (0x2U << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2                    (0x4U << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos                  (15U)
+#define ADC_SMPR2_SMP15_Msk                  (0x7U << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR2_SMP15_0                    (0x1U << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1                    (0x2U << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2                    (0x4U << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos                  (18U)
+#define ADC_SMPR2_SMP16_Msk                  (0x7U << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR2_SMP16_0                    (0x1U << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1                    (0x2U << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2                    (0x4U << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos                  (21U)
+#define ADC_SMPR2_SMP17_Msk                  (0x7U << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR2_SMP17_0                    (0x1U << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1                    (0x2U << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2                    (0x4U << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos                  (24U)
+#define ADC_SMPR2_SMP18_Msk                  (0x7U << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
+#define ADC_SMPR2_SMP18_0                    (0x1U << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1                    (0x2U << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2                    (0x4U << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
+
+#define ADC_SMPR2_SMP19_Pos                  (27U)
+#define ADC_SMPR2_SMP19_Msk                  (0x7U << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
+#define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
+#define ADC_SMPR2_SMP19_0                    (0x1U << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
+#define ADC_SMPR2_SMP19_1                    (0x2U << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
+#define ADC_SMPR2_SMP19_2                    (0x4U << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
+
+/******************  Bit definition for ADC_SMPR3 register  *******************/
+#define ADC_SMPR3_SMP0_Pos                   (0U)
+#define ADC_SMPR3_SMP0_Msk                   (0x7U << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
+#define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR3_SMP0_0                     (0x1U << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
+#define ADC_SMPR3_SMP0_1                     (0x2U << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
+#define ADC_SMPR3_SMP0_2                     (0x4U << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
+
+#define ADC_SMPR3_SMP1_Pos                   (3U)
+#define ADC_SMPR3_SMP1_Msk                   (0x7U << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
+#define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR3_SMP1_0                     (0x1U << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
+#define ADC_SMPR3_SMP1_1                     (0x2U << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
+#define ADC_SMPR3_SMP1_2                     (0x4U << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
+
+#define ADC_SMPR3_SMP2_Pos                   (6U)
+#define ADC_SMPR3_SMP2_Msk                   (0x7U << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
+#define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR3_SMP2_0                     (0x1U << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
+#define ADC_SMPR3_SMP2_1                     (0x2U << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
+#define ADC_SMPR3_SMP2_2                     (0x4U << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
+
+#define ADC_SMPR3_SMP3_Pos                   (9U)
+#define ADC_SMPR3_SMP3_Msk                   (0x7U << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
+#define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR3_SMP3_0                     (0x1U << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
+#define ADC_SMPR3_SMP3_1                     (0x2U << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
+#define ADC_SMPR3_SMP3_2                     (0x4U << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
+
+#define ADC_SMPR3_SMP4_Pos                   (12U)
+#define ADC_SMPR3_SMP4_Msk                   (0x7U << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
+#define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR3_SMP4_0                     (0x1U << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
+#define ADC_SMPR3_SMP4_1                     (0x2U << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
+#define ADC_SMPR3_SMP4_2                     (0x4U << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
+
+#define ADC_SMPR3_SMP5_Pos                   (15U)
+#define ADC_SMPR3_SMP5_Msk                   (0x7U << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
+#define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR3_SMP5_0                     (0x1U << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
+#define ADC_SMPR3_SMP5_1                     (0x2U << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
+#define ADC_SMPR3_SMP5_2                     (0x4U << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
+
+#define ADC_SMPR3_SMP6_Pos                   (18U)
+#define ADC_SMPR3_SMP6_Msk                   (0x7U << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
+#define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR3_SMP6_0                     (0x1U << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
+#define ADC_SMPR3_SMP6_1                     (0x2U << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
+#define ADC_SMPR3_SMP6_2                     (0x4U << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
+
+#define ADC_SMPR3_SMP7_Pos                   (21U)
+#define ADC_SMPR3_SMP7_Msk                   (0x7U << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
+#define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR3_SMP7_0                     (0x1U << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
+#define ADC_SMPR3_SMP7_1                     (0x2U << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
+#define ADC_SMPR3_SMP7_2                     (0x4U << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
+
+#define ADC_SMPR3_SMP8_Pos                   (24U)
+#define ADC_SMPR3_SMP8_Msk                   (0x7U << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
+#define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR3_SMP8_0                     (0x1U << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
+#define ADC_SMPR3_SMP8_1                     (0x2U << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
+#define ADC_SMPR3_SMP8_2                     (0x4U << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
+
+#define ADC_SMPR3_SMP9_Pos                   (27U)
+#define ADC_SMPR3_SMP9_Msk                   (0x7U << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
+#define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR3_SMP9_0                     (0x1U << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
+#define ADC_SMPR3_SMP9_1                     (0x2U << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
+#define ADC_SMPR3_SMP9_2                     (0x4U << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define ADC_JOFR1_JOFFSET1_Pos               (0U)
+#define ADC_JOFR1_JOFFSET1_Msk               (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define ADC_JOFR2_JOFFSET2_Pos               (0U)
+#define ADC_JOFR2_JOFFSET2_Msk               (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define ADC_JOFR3_JOFFSET3_Pos               (0U)
+#define ADC_JOFR3_JOFFSET3_Msk               (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define ADC_JOFR4_JOFFSET4_Pos               (0U)
+#define ADC_JOFR4_JOFFSET4_Msk               (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define ADC_HTR_HT_Pos                       (0U)
+#define ADC_HTR_HT_Msk                       (0xFFFU << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
+#define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define ADC_LTR_LT_Pos                       (0U)
+#define ADC_LTR_LT_Msk                       (0xFFFU << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
+#define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define ADC_SQR1_L_Pos                       (20U)
+#define ADC_SQR1_L_Msk                       (0x1FU << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
+#define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0                         (0x01U << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
+#define ADC_SQR1_L_1                         (0x02U << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
+#define ADC_SQR1_L_2                         (0x04U << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
+#define ADC_SQR1_L_3                         (0x08U << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
+#define ADC_SQR1_L_4                         (0x10U << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
+
+#define ADC_SQR1_SQ27_Pos                    (10U)
+#define ADC_SQR1_SQ27_Msk                    (0x1FU << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
+#define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
+#define ADC_SQR1_SQ27_0                      (0x01U << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
+#define ADC_SQR1_SQ27_1                      (0x02U << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
+#define ADC_SQR1_SQ27_2                      (0x04U << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
+#define ADC_SQR1_SQ27_3                      (0x08U << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
+#define ADC_SQR1_SQ27_4                      (0x10U << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
+
+#define ADC_SQR1_SQ26_Pos                    (5U)
+#define ADC_SQR1_SQ26_Msk                    (0x1FU << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
+#define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
+#define ADC_SQR1_SQ26_0                      (0x01U << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
+#define ADC_SQR1_SQ26_1                      (0x02U << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
+#define ADC_SQR1_SQ26_2                      (0x04U << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
+#define ADC_SQR1_SQ26_3                      (0x08U << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
+#define ADC_SQR1_SQ26_4                      (0x10U << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
+
+#define ADC_SQR1_SQ25_Pos                    (0U)
+#define ADC_SQR1_SQ25_Msk                    (0x1FU << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
+#define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
+#define ADC_SQR1_SQ25_0                      (0x01U << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
+#define ADC_SQR1_SQ25_1                      (0x02U << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
+#define ADC_SQR1_SQ25_2                      (0x04U << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
+#define ADC_SQR1_SQ25_3                      (0x08U << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
+#define ADC_SQR1_SQ25_4                      (0x10U << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define ADC_SQR2_SQ19_Pos                    (0U)
+#define ADC_SQR2_SQ19_Msk                    (0x1FU << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
+#define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
+#define ADC_SQR2_SQ19_0                      (0x01U << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
+#define ADC_SQR2_SQ19_1                      (0x02U << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
+#define ADC_SQR2_SQ19_2                      (0x04U << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
+#define ADC_SQR2_SQ19_3                      (0x08U << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
+#define ADC_SQR2_SQ19_4                      (0x10U << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ20_Pos                    (5U)
+#define ADC_SQR2_SQ20_Msk                    (0x1FU << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
+#define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
+#define ADC_SQR2_SQ20_0                      (0x01U << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
+#define ADC_SQR2_SQ20_1                      (0x02U << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
+#define ADC_SQR2_SQ20_2                      (0x04U << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
+#define ADC_SQR2_SQ20_3                      (0x08U << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
+#define ADC_SQR2_SQ20_4                      (0x10U << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
+
+#define ADC_SQR2_SQ21_Pos                    (10U)
+#define ADC_SQR2_SQ21_Msk                    (0x1FU << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
+#define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
+#define ADC_SQR2_SQ21_0                      (0x01U << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
+#define ADC_SQR2_SQ21_1                      (0x02U << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
+#define ADC_SQR2_SQ21_2                      (0x04U << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
+#define ADC_SQR2_SQ21_3                      (0x08U << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
+#define ADC_SQR2_SQ21_4                      (0x10U << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
+
+#define ADC_SQR2_SQ22_Pos                    (15U)
+#define ADC_SQR2_SQ22_Msk                    (0x1FU << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
+#define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
+#define ADC_SQR2_SQ22_0                      (0x01U << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
+#define ADC_SQR2_SQ22_1                      (0x02U << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
+#define ADC_SQR2_SQ22_2                      (0x04U << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
+#define ADC_SQR2_SQ22_3                      (0x08U << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
+#define ADC_SQR2_SQ22_4                      (0x10U << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
+
+#define ADC_SQR2_SQ23_Pos                    (20U)
+#define ADC_SQR2_SQ23_Msk                    (0x1FU << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
+#define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
+#define ADC_SQR2_SQ23_0                      (0x01U << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
+#define ADC_SQR2_SQ23_1                      (0x02U << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
+#define ADC_SQR2_SQ23_2                      (0x04U << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
+#define ADC_SQR2_SQ23_3                      (0x08U << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
+#define ADC_SQR2_SQ23_4                      (0x10U << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
+
+#define ADC_SQR2_SQ24_Pos                    (25U)
+#define ADC_SQR2_SQ24_Msk                    (0x1FU << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
+#define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
+#define ADC_SQR2_SQ24_0                      (0x01U << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
+#define ADC_SQR2_SQ24_1                      (0x02U << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
+#define ADC_SQR2_SQ24_2                      (0x04U << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
+#define ADC_SQR2_SQ24_3                      (0x08U << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
+#define ADC_SQR2_SQ24_4                      (0x10U << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define ADC_SQR3_SQ13_Pos                    (0U)
+#define ADC_SQR3_SQ13_Msk                    (0x1FU << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
+#define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0                      (0x01U << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
+#define ADC_SQR3_SQ13_1                      (0x02U << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
+#define ADC_SQR3_SQ13_2                      (0x04U << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
+#define ADC_SQR3_SQ13_3                      (0x08U << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
+#define ADC_SQR3_SQ13_4                      (0x10U << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ14_Pos                    (5U)
+#define ADC_SQR3_SQ14_Msk                    (0x1FU << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
+#define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0                      (0x01U << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
+#define ADC_SQR3_SQ14_1                      (0x02U << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
+#define ADC_SQR3_SQ14_2                      (0x04U << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
+#define ADC_SQR3_SQ14_3                      (0x08U << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
+#define ADC_SQR3_SQ14_4                      (0x10U << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
+
+#define ADC_SQR3_SQ15_Pos                    (10U)
+#define ADC_SQR3_SQ15_Msk                    (0x1FU << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
+#define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR3_SQ15_0                      (0x01U << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
+#define ADC_SQR3_SQ15_1                      (0x02U << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
+#define ADC_SQR3_SQ15_2                      (0x04U << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
+#define ADC_SQR3_SQ15_3                      (0x08U << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
+#define ADC_SQR3_SQ15_4                      (0x10U << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
+
+#define ADC_SQR3_SQ16_Pos                    (15U)
+#define ADC_SQR3_SQ16_Msk                    (0x1FU << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
+#define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR3_SQ16_0                      (0x01U << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
+#define ADC_SQR3_SQ16_1                      (0x02U << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
+#define ADC_SQR3_SQ16_2                      (0x04U << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
+#define ADC_SQR3_SQ16_3                      (0x08U << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
+#define ADC_SQR3_SQ16_4                      (0x10U << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
+
+#define ADC_SQR3_SQ17_Pos                    (20U)
+#define ADC_SQR3_SQ17_Msk                    (0x1FU << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
+#define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
+#define ADC_SQR3_SQ17_0                      (0x01U << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
+#define ADC_SQR3_SQ17_1                      (0x02U << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
+#define ADC_SQR3_SQ17_2                      (0x04U << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
+#define ADC_SQR3_SQ17_3                      (0x08U << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
+#define ADC_SQR3_SQ17_4                      (0x10U << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
+
+#define ADC_SQR3_SQ18_Pos                    (25U)
+#define ADC_SQR3_SQ18_Msk                    (0x1FU << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
+#define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
+#define ADC_SQR3_SQ18_0                      (0x01U << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
+#define ADC_SQR3_SQ18_1                      (0x02U << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
+#define ADC_SQR3_SQ18_2                      (0x04U << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
+#define ADC_SQR3_SQ18_3                      (0x08U << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
+#define ADC_SQR3_SQ18_4                      (0x10U << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
+
+/*******************  Bit definition for ADC_SQR4 register  *******************/
+#define ADC_SQR4_SQ7_Pos                     (0U)
+#define ADC_SQR4_SQ7_Msk                     (0x1FU << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
+#define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR4_SQ7_0                       (0x01U << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
+#define ADC_SQR4_SQ7_1                       (0x02U << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
+#define ADC_SQR4_SQ7_2                       (0x04U << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
+#define ADC_SQR4_SQ7_3                       (0x08U << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
+#define ADC_SQR4_SQ7_4                       (0x10U << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ8_Pos                     (5U)
+#define ADC_SQR4_SQ8_Msk                     (0x1FU << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
+#define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR4_SQ8_0                       (0x01U << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
+#define ADC_SQR4_SQ8_1                       (0x02U << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
+#define ADC_SQR4_SQ8_2                       (0x04U << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
+#define ADC_SQR4_SQ8_3                       (0x08U << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
+#define ADC_SQR4_SQ8_4                       (0x10U << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
+
+#define ADC_SQR4_SQ9_Pos                     (10U)
+#define ADC_SQR4_SQ9_Msk                     (0x1FU << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
+#define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR4_SQ9_0                       (0x01U << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
+#define ADC_SQR4_SQ9_1                       (0x02U << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
+#define ADC_SQR4_SQ9_2                       (0x04U << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
+#define ADC_SQR4_SQ9_3                       (0x08U << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
+#define ADC_SQR4_SQ9_4                       (0x10U << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
+
+#define ADC_SQR4_SQ10_Pos                    (15U)
+#define ADC_SQR4_SQ10_Msk                    (0x1FU << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
+#define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR4_SQ10_0                      (0x01U << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
+#define ADC_SQR4_SQ10_1                      (0x02U << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
+#define ADC_SQR4_SQ10_2                      (0x04U << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
+#define ADC_SQR4_SQ10_3                      (0x08U << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
+#define ADC_SQR4_SQ10_4                      (0x10U << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
+
+#define ADC_SQR4_SQ11_Pos                    (20U)
+#define ADC_SQR4_SQ11_Msk                    (0x1FU << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
+#define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR4_SQ11_0                      (0x01U << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
+#define ADC_SQR4_SQ11_1                      (0x02U << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
+#define ADC_SQR4_SQ11_2                      (0x04U << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
+#define ADC_SQR4_SQ11_3                      (0x08U << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
+#define ADC_SQR4_SQ11_4                      (0x10U << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
+
+#define ADC_SQR4_SQ12_Pos                    (25U)
+#define ADC_SQR4_SQ12_Msk                    (0x1FU << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
+#define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR4_SQ12_0                      (0x01U << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
+#define ADC_SQR4_SQ12_1                      (0x02U << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
+#define ADC_SQR4_SQ12_2                      (0x04U << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
+#define ADC_SQR4_SQ12_3                      (0x08U << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
+#define ADC_SQR4_SQ12_4                      (0x10U << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
+
+/*******************  Bit definition for ADC_SQR5 register  *******************/
+#define ADC_SQR5_SQ1_Pos                     (0U)
+#define ADC_SQR5_SQ1_Msk                     (0x1FU << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
+#define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR5_SQ1_0                       (0x01U << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
+#define ADC_SQR5_SQ1_1                       (0x02U << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
+#define ADC_SQR5_SQ1_2                       (0x04U << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
+#define ADC_SQR5_SQ1_3                       (0x08U << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
+#define ADC_SQR5_SQ1_4                       (0x10U << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
+
+#define ADC_SQR5_SQ2_Pos                     (5U)
+#define ADC_SQR5_SQ2_Msk                     (0x1FU << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
+#define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR5_SQ2_0                       (0x01U << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
+#define ADC_SQR5_SQ2_1                       (0x02U << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
+#define ADC_SQR5_SQ2_2                       (0x04U << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
+#define ADC_SQR5_SQ2_3                       (0x08U << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
+#define ADC_SQR5_SQ2_4                       (0x10U << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
+
+#define ADC_SQR5_SQ3_Pos                     (10U)
+#define ADC_SQR5_SQ3_Msk                     (0x1FU << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
+#define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR5_SQ3_0                       (0x01U << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
+#define ADC_SQR5_SQ3_1                       (0x02U << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
+#define ADC_SQR5_SQ3_2                       (0x04U << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
+#define ADC_SQR5_SQ3_3                       (0x08U << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
+#define ADC_SQR5_SQ3_4                       (0x10U << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
+
+#define ADC_SQR5_SQ4_Pos                     (15U)
+#define ADC_SQR5_SQ4_Msk                     (0x1FU << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
+#define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR5_SQ4_0                       (0x01U << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
+#define ADC_SQR5_SQ4_1                       (0x02U << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
+#define ADC_SQR5_SQ4_2                       (0x04U << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
+#define ADC_SQR5_SQ4_3                       (0x08U << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
+#define ADC_SQR5_SQ4_4                       (0x10U << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
+
+#define ADC_SQR5_SQ5_Pos                     (20U)
+#define ADC_SQR5_SQ5_Msk                     (0x1FU << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
+#define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR5_SQ5_0                       (0x01U << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
+#define ADC_SQR5_SQ5_1                       (0x02U << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
+#define ADC_SQR5_SQ5_2                       (0x04U << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
+#define ADC_SQR5_SQ5_3                       (0x08U << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
+#define ADC_SQR5_SQ5_4                       (0x10U << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
+
+#define ADC_SQR5_SQ6_Pos                     (25U)
+#define ADC_SQR5_SQ6_Msk                     (0x1FU << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
+#define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR5_SQ6_0                       (0x01U << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
+#define ADC_SQR5_SQ6_1                       (0x02U << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
+#define ADC_SQR5_SQ6_2                       (0x04U << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
+#define ADC_SQR5_SQ6_3                       (0x08U << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
+#define ADC_SQR5_SQ6_4                       (0x10U << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
+
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define ADC_JSQR_JSQ1_Pos                    (0U)
+#define ADC_JSQR_JSQ1_Msk                    (0x1FU << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0                      (0x01U << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1                      (0x02U << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2                      (0x04U << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3                      (0x08U << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4                      (0x10U << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
+
+#define ADC_JSQR_JSQ2_Pos                    (5U)
+#define ADC_JSQR_JSQ2_Msk                    (0x1FU << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0                      (0x01U << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1                      (0x02U << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2                      (0x04U << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3                      (0x08U << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4                      (0x10U << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
+
+#define ADC_JSQR_JSQ3_Pos                    (10U)
+#define ADC_JSQR_JSQ3_Msk                    (0x1FU << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0                      (0x01U << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1                      (0x02U << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2                      (0x04U << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3                      (0x08U << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4                      (0x10U << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
+
+#define ADC_JSQR_JSQ4_Pos                    (15U)
+#define ADC_JSQR_JSQ4_Msk                    (0x1FU << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0                      (0x01U << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1                      (0x02U << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2                      (0x04U << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3                      (0x08U << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4                      (0x10U << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
+
+#define ADC_JSQR_JL_Pos                      (20U)
+#define ADC_JSQR_JL_Msk                      (0x3U << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
+#define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0                        (0x1U << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
+#define ADC_JSQR_JL_1                        (0x2U << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define ADC_JDR1_JDATA_Pos                   (0U)
+#define ADC_JDR1_JDATA_Msk                   (0xFFFFU << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define ADC_JDR2_JDATA_Pos                   (0U)
+#define ADC_JDR2_JDATA_Msk                   (0xFFFFU << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define ADC_JDR3_JDATA_Pos                   (0U)
+#define ADC_JDR3_JDATA_Msk                   (0xFFFFU << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define ADC_JDR4_JDATA_Pos                   (0U)
+#define ADC_JDR4_JDATA_Msk                   (0xFFFFU << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_DATA_Pos                      (0U)
+#define ADC_DR_DATA_Msk                      (0xFFFFU << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
+#define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define ADC_CSR_AWD1_Pos                     (0U)
+#define ADC_CSR_AWD1_Msk                     (0x1U << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
+#define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
+#define ADC_CSR_EOCS1_Pos                    (1U)
+#define ADC_CSR_EOCS1_Msk                    (0x1U << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
+#define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
+#define ADC_CSR_JEOS1_Pos                    (2U)
+#define ADC_CSR_JEOS1_Msk                    (0x1U << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
+#define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
+#define ADC_CSR_JSTRT1_Pos                   (3U)
+#define ADC_CSR_JSTRT1_Msk                   (0x1U << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
+#define ADC_CSR_STRT1_Pos                    (4U)
+#define ADC_CSR_STRT1_Msk                    (0x1U << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
+#define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
+#define ADC_CSR_OVR1_Pos                     (5U)
+#define ADC_CSR_OVR1_Msk                     (0x1U << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
+#define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
+#define ADC_CSR_ADONS1_Pos                   (6U)
+#define ADC_CSR_ADONS1_Msk                   (0x1U << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
+#define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
+
+/* Legacy defines */
+#define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
+#define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_ADCPRE_Pos                   (16U)
+#define ADC_CCR_ADCPRE_Msk                   (0x3U << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
+#define ADC_CCR_ADCPRE_0                     (0x1U << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1                     (0x2U << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
+#define ADC_CCR_TSVREFE_Pos                  (23U)
+#define ADC_CCR_TSVREFE_Msk                  (0x1U << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Analog Comparators (COMP)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for COMP_CSR register  ********************/
+#define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
+#define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
+#define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
+#define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
+#define COMP_CSR_CMP1EN_Pos                 (4U)
+#define COMP_CSR_CMP1EN_Msk                 (0x1U << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
+#define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
+#define COMP_CSR_CMP1OUT_Pos                (7U)
+#define COMP_CSR_CMP1OUT_Msk                (0x1U << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
+#define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
+#define COMP_CSR_SPEED_Pos                  (12U)
+#define COMP_CSR_SPEED_Msk                  (0x1U << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
+#define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
+#define COMP_CSR_CMP2OUT_Pos                (13U)
+#define COMP_CSR_CMP2OUT_Msk                (0x1U << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
+#define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
+
+#define COMP_CSR_WNDWE_Pos                  (17U)
+#define COMP_CSR_WNDWE_Msk                  (0x1U << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
+#define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
+
+#define COMP_CSR_INSEL_Pos                  (18U)
+#define COMP_CSR_INSEL_Msk                  (0x7U << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
+#define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
+#define COMP_CSR_INSEL_0                    (0x1U << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
+#define COMP_CSR_INSEL_1                    (0x2U << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
+#define COMP_CSR_INSEL_2                    (0x4U << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
+#define COMP_CSR_OUTSEL_Pos                 (21U)
+#define COMP_CSR_OUTSEL_Msk                 (0x7U << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
+#define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
+#define COMP_CSR_OUTSEL_0                   (0x1U << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
+#define COMP_CSR_OUTSEL_1                   (0x2U << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
+#define COMP_CSR_OUTSEL_2                   (0x4U << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
+
+/* Bits present in COMP register but not related to comparator */
+/* (or partially related to comparator, in addition to other peripherals) */
+#define COMP_CSR_VREFOUTEN_Pos              (16U)
+#define COMP_CSR_VREFOUTEN_Msk              (0x1U << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
+#define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       CRC calculation unit (CRC)                           */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos                       (0U)
+#define CRC_DR_DR_Msk                       (0xFFFFFFFFU << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
+#define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos                     (0U)
+#define CRC_IDR_IDR_Msk                     (0xFFU << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
+#define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos                    (0U)
+#define CRC_CR_RESET_Msk                    (0x1U << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
+#define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                    Digital to Analog Converter (DAC)                       */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos                      (0U)
+#define DAC_CR_EN1_Msk                      (0x1U << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
+#define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos                    (1U)
+#define DAC_CR_BOFF1_Msk                    (0x1U << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
+#define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos                     (2U)
+#define DAC_CR_TEN1_Msk                     (0x1U << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
+#define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos                    (3U)
+#define DAC_CR_TSEL1_Msk                    (0x7U << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
+#define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0                      (0x1U << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1                      (0x2U << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2                      (0x4U << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos                    (6U)
+#define DAC_CR_WAVE1_Msk                    (0x3U << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0                      (0x1U << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1                      (0x2U << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos                    (8U)
+#define DAC_CR_MAMP1_Msk                    (0xFU << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0                      (0x1U << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1                      (0x2U << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2                      (0x4U << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3                      (0x8U << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos                   (12U)
+#define DAC_CR_DMAEN1_Msk                   (0x1U << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
+#define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos                (13U)
+#define DAC_CR_DMAUDRIE1_Msk                (0x1U << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
+#define DAC_CR_EN2_Pos                      (16U)
+#define DAC_CR_EN2_Msk                      (0x1U << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
+#define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos                    (17U)
+#define DAC_CR_BOFF2_Msk                    (0x1U << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
+#define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos                     (18U)
+#define DAC_CR_TEN2_Msk                     (0x1U << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
+#define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos                    (19U)
+#define DAC_CR_TSEL2_Msk                    (0x7U << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
+#define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0                      (0x1U << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1                      (0x2U << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2                      (0x4U << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos                    (22U)
+#define DAC_CR_WAVE2_Msk                    (0x3U << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0                      (0x1U << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1                      (0x2U << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos                    (24U)
+#define DAC_CR_MAMP2_Msk                    (0xFU << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0                      (0x1U << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1                      (0x2U << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2                      (0x4U << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3                      (0x8U << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos                   (28U)
+#define DAC_CR_DMAEN2_Msk                   (0x1U << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
+#define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos                (29U)
+#define DAC_CR_DMAUDRIE2_Msk                (0x1U << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos             (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk             (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos             (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk             (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos            (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos            (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos             (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk             (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos            (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos            (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos             (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk             (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos            (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos            (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos            (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos            (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos             (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk             (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos             (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk             (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos               (0U)
+#define DAC_DOR1_DACC1DOR_Msk               (0xFFFU << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos               (0U)
+#define DAC_DOR2_DACC2DOR_Msk               (0xFFFU << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos                  (13U)
+#define DAC_SR_DMAUDR1_Msk                  (0x1U << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos                  (29U)
+#define DAC_SR_DMAUDR2_Msk                  (0x1U << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Debug MCU (DBGMCU)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/****************  Bit definition for DBGMCU_IDCODE register  *****************/
+#define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)
+#define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID_Pos                 (16U)
+#define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0                   (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
+#define DBGMCU_IDCODE_REV_ID_1                   (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
+#define DBGMCU_IDCODE_REV_ID_2                   (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
+#define DBGMCU_IDCODE_REV_ID_3                   (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
+#define DBGMCU_IDCODE_REV_ID_4                   (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
+#define DBGMCU_IDCODE_REV_ID_5                   (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
+#define DBGMCU_IDCODE_REV_ID_6                   (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
+#define DBGMCU_IDCODE_REV_ID_7                   (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
+#define DBGMCU_IDCODE_REV_ID_8                   (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
+#define DBGMCU_IDCODE_REV_ID_9                   (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
+#define DBGMCU_IDCODE_REV_ID_10                  (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
+#define DBGMCU_IDCODE_REV_ID_11                  (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
+#define DBGMCU_IDCODE_REV_ID_12                  (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
+#define DBGMCU_IDCODE_REV_ID_13                  (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
+#define DBGMCU_IDCODE_REV_ID_14                  (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
+#define DBGMCU_IDCODE_REV_ID_15                  (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
+
+/******************  Bit definition for DBGMCU_CR register  *******************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)
+#define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP_Pos                   (1U)
+#define DBGMCU_CR_DBG_STOP_Msk                   (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY_Pos                (2U)
+#define DBGMCU_CR_DBG_STANDBY_Msk                (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)
+#define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE_Pos                 (6U)
+#define DBGMCU_CR_TRACE_MODE_Msk                 (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0                   (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                   (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
+
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
+
+/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
+
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           DMA Controller (DMA)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_ISR register  ********************/
+#define DMA_ISR_GIF1_Pos                    (0U)
+#define DMA_ISR_GIF1_Msk                    (0x1U << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
+#define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1_Pos                   (1U)
+#define DMA_ISR_TCIF1_Msk                   (0x1U << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
+#define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1_Pos                   (2U)
+#define DMA_ISR_HTIF1_Msk                   (0x1U << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
+#define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1_Pos                   (3U)
+#define DMA_ISR_TEIF1_Msk                   (0x1U << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
+#define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2_Pos                    (4U)
+#define DMA_ISR_GIF2_Msk                    (0x1U << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
+#define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2_Pos                   (5U)
+#define DMA_ISR_TCIF2_Msk                   (0x1U << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
+#define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2_Pos                   (6U)
+#define DMA_ISR_HTIF2_Msk                   (0x1U << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
+#define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2_Pos                   (7U)
+#define DMA_ISR_TEIF2_Msk                   (0x1U << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
+#define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3_Pos                    (8U)
+#define DMA_ISR_GIF3_Msk                    (0x1U << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
+#define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3_Pos                   (9U)
+#define DMA_ISR_TCIF3_Msk                   (0x1U << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
+#define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3_Pos                   (10U)
+#define DMA_ISR_HTIF3_Msk                   (0x1U << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
+#define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3_Pos                   (11U)
+#define DMA_ISR_TEIF3_Msk                   (0x1U << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
+#define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4_Pos                    (12U)
+#define DMA_ISR_GIF4_Msk                    (0x1U << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
+#define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4_Pos                   (13U)
+#define DMA_ISR_TCIF4_Msk                   (0x1U << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
+#define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4_Pos                   (14U)
+#define DMA_ISR_HTIF4_Msk                   (0x1U << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
+#define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4_Pos                   (15U)
+#define DMA_ISR_TEIF4_Msk                   (0x1U << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
+#define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5_Pos                    (16U)
+#define DMA_ISR_GIF5_Msk                    (0x1U << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
+#define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5_Pos                   (17U)
+#define DMA_ISR_TCIF5_Msk                   (0x1U << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
+#define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5_Pos                   (18U)
+#define DMA_ISR_HTIF5_Msk                   (0x1U << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
+#define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5_Pos                   (19U)
+#define DMA_ISR_TEIF5_Msk                   (0x1U << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
+#define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6_Pos                    (20U)
+#define DMA_ISR_GIF6_Msk                    (0x1U << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
+#define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6_Pos                   (21U)
+#define DMA_ISR_TCIF6_Msk                   (0x1U << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
+#define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6_Pos                   (22U)
+#define DMA_ISR_HTIF6_Msk                   (0x1U << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
+#define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6_Pos                   (23U)
+#define DMA_ISR_TEIF6_Msk                   (0x1U << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
+#define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7_Pos                    (24U)
+#define DMA_ISR_GIF7_Msk                    (0x1U << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
+#define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7_Pos                   (25U)
+#define DMA_ISR_TCIF7_Msk                   (0x1U << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
+#define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7_Pos                   (26U)
+#define DMA_ISR_HTIF7_Msk                   (0x1U << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
+#define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7_Pos                   (27U)
+#define DMA_ISR_TEIF7_Msk                   (0x1U << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
+#define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_IFCR register  *******************/
+#define DMA_IFCR_CGIF1_Pos                  (0U)
+#define DMA_IFCR_CGIF1_Msk                  (0x1U << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
+#define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
+#define DMA_IFCR_CTCIF1_Pos                 (1U)
+#define DMA_IFCR_CTCIF1_Msk                 (0x1U << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
+#define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1_Pos                 (2U)
+#define DMA_IFCR_CHTIF1_Msk                 (0x1U << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
+#define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1_Pos                 (3U)
+#define DMA_IFCR_CTEIF1_Msk                 (0x1U << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
+#define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2_Pos                  (4U)
+#define DMA_IFCR_CGIF2_Msk                  (0x1U << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
+#define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2_Pos                 (5U)
+#define DMA_IFCR_CTCIF2_Msk                 (0x1U << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
+#define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2_Pos                 (6U)
+#define DMA_IFCR_CHTIF2_Msk                 (0x1U << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
+#define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2_Pos                 (7U)
+#define DMA_IFCR_CTEIF2_Msk                 (0x1U << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
+#define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3_Pos                  (8U)
+#define DMA_IFCR_CGIF3_Msk                  (0x1U << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
+#define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3_Pos                 (9U)
+#define DMA_IFCR_CTCIF3_Msk                 (0x1U << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
+#define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3_Pos                 (10U)
+#define DMA_IFCR_CHTIF3_Msk                 (0x1U << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
+#define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3_Pos                 (11U)
+#define DMA_IFCR_CTEIF3_Msk                 (0x1U << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
+#define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4_Pos                  (12U)
+#define DMA_IFCR_CGIF4_Msk                  (0x1U << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
+#define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4_Pos                 (13U)
+#define DMA_IFCR_CTCIF4_Msk                 (0x1U << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
+#define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4_Pos                 (14U)
+#define DMA_IFCR_CHTIF4_Msk                 (0x1U << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
+#define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4_Pos                 (15U)
+#define DMA_IFCR_CTEIF4_Msk                 (0x1U << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
+#define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5_Pos                  (16U)
+#define DMA_IFCR_CGIF5_Msk                  (0x1U << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
+#define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5_Pos                 (17U)
+#define DMA_IFCR_CTCIF5_Msk                 (0x1U << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
+#define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5_Pos                 (18U)
+#define DMA_IFCR_CHTIF5_Msk                 (0x1U << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
+#define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5_Pos                 (19U)
+#define DMA_IFCR_CTEIF5_Msk                 (0x1U << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
+#define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6_Pos                  (20U)
+#define DMA_IFCR_CGIF6_Msk                  (0x1U << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
+#define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6_Pos                 (21U)
+#define DMA_IFCR_CTCIF6_Msk                 (0x1U << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
+#define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6_Pos                 (22U)
+#define DMA_IFCR_CHTIF6_Msk                 (0x1U << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
+#define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6_Pos                 (23U)
+#define DMA_IFCR_CTEIF6_Msk                 (0x1U << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
+#define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7_Pos                  (24U)
+#define DMA_IFCR_CGIF7_Msk                  (0x1U << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
+#define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7_Pos                 (25U)
+#define DMA_IFCR_CTCIF7_Msk                 (0x1U << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
+#define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7_Pos                 (26U)
+#define DMA_IFCR_CHTIF7_Msk                 (0x1U << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
+#define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7_Pos                 (27U)
+#define DMA_IFCR_CTEIF7_Msk                 (0x1U << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
+#define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CCR register  *******************/
+#define DMA_CCR_EN_Pos                      (0U)
+#define DMA_CCR_EN_Msk                      (0x1U << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
+#define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
+#define DMA_CCR_TCIE_Pos                    (1U)
+#define DMA_CCR_TCIE_Msk                    (0x1U << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
+#define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
+#define DMA_CCR_HTIE_Pos                    (2U)
+#define DMA_CCR_HTIE_Msk                    (0x1U << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
+#define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
+#define DMA_CCR_TEIE_Pos                    (3U)
+#define DMA_CCR_TEIE_Msk                    (0x1U << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
+#define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
+#define DMA_CCR_DIR_Pos                     (4U)
+#define DMA_CCR_DIR_Msk                     (0x1U << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
+#define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
+#define DMA_CCR_CIRC_Pos                    (5U)
+#define DMA_CCR_CIRC_Msk                    (0x1U << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
+#define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
+#define DMA_CCR_PINC_Pos                    (6U)
+#define DMA_CCR_PINC_Msk                    (0x1U << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
+#define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
+#define DMA_CCR_MINC_Pos                    (7U)
+#define DMA_CCR_MINC_Msk                    (0x1U << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
+#define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
+
+#define DMA_CCR_PSIZE_Pos                   (8U)
+#define DMA_CCR_PSIZE_Msk                   (0x3U << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
+#define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR_PSIZE_0                     (0x1U << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
+#define DMA_CCR_PSIZE_1                     (0x2U << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
+
+#define DMA_CCR_MSIZE_Pos                   (10U)
+#define DMA_CCR_MSIZE_Msk                   (0x3U << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
+#define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR_MSIZE_0                     (0x1U << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
+#define DMA_CCR_MSIZE_1                     (0x2U << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
+
+#define DMA_CCR_PL_Pos                      (12U)
+#define DMA_CCR_PL_Msk                      (0x3U << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
+#define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR_PL_0                        (0x1U << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
+#define DMA_CCR_PL_1                        (0x2U << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
+
+#define DMA_CCR_MEM2MEM_Pos                 (14U)
+#define DMA_CCR_MEM2MEM_Msk                 (0x1U << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
+#define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
+
+/******************  Bit definition generic for DMA_CNDTR register  *******************/
+#define DMA_CNDTR_NDT_Pos                   (0U)
+#define DMA_CNDTR_NDT_Msk                   (0xFFFFU << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
+#define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR1 register  ******************/
+#define DMA_CNDTR1_NDT_Pos                  (0U)
+#define DMA_CNDTR1_NDT_Msk                  (0xFFFFU << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
+#define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR2 register  ******************/
+#define DMA_CNDTR2_NDT_Pos                  (0U)
+#define DMA_CNDTR2_NDT_Msk                  (0xFFFFU << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
+#define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR3 register  ******************/
+#define DMA_CNDTR3_NDT_Pos                  (0U)
+#define DMA_CNDTR3_NDT_Msk                  (0xFFFFU << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
+#define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR4 register  ******************/
+#define DMA_CNDTR4_NDT_Pos                  (0U)
+#define DMA_CNDTR4_NDT_Msk                  (0xFFFFU << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
+#define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR5 register  ******************/
+#define DMA_CNDTR5_NDT_Pos                  (0U)
+#define DMA_CNDTR5_NDT_Msk                  (0xFFFFU << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
+#define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR6 register  ******************/
+#define DMA_CNDTR6_NDT_Pos                  (0U)
+#define DMA_CNDTR6_NDT_Msk                  (0xFFFFU << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
+#define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNDTR7 register  ******************/
+#define DMA_CNDTR7_NDT_Pos                  (0U)
+#define DMA_CNDTR7_NDT_Msk                  (0xFFFFU << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
+#define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
+
+/******************  Bit definition generic for DMA_CPAR register  ********************/
+#define DMA_CPAR_PA_Pos                     (0U)
+#define DMA_CPAR_PA_Msk                     (0xFFFFFFFFU << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
+#define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR1 register  *******************/
+#define DMA_CPAR1_PA_Pos                    (0U)
+#define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR2 register  *******************/
+#define DMA_CPAR2_PA_Pos                    (0U)
+#define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR3 register  *******************/
+#define DMA_CPAR3_PA_Pos                    (0U)
+#define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR4 register  *******************/
+#define DMA_CPAR4_PA_Pos                    (0U)
+#define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR5 register  *******************/
+#define DMA_CPAR5_PA_Pos                    (0U)
+#define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_CPAR6 register  *******************/
+#define DMA_CPAR6_PA_Pos                    (0U)
+#define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
+
+
+/******************  Bit definition for DMA_CPAR7 register  *******************/
+#define DMA_CPAR7_PA_Pos                    (0U)
+#define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
+
+/******************  Bit definition generic for DMA_CMAR register  ********************/
+#define DMA_CMAR_MA_Pos                     (0U)
+#define DMA_CMAR_MA_Msk                     (0xFFFFFFFFU << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
+#define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR1 register  *******************/
+#define DMA_CMAR1_MA_Pos                    (0U)
+#define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR2 register  *******************/
+#define DMA_CMAR2_MA_Pos                    (0U)
+#define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR3 register  *******************/
+#define DMA_CMAR3_MA_Pos                    (0U)
+#define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
+
+
+/******************  Bit definition for DMA_CMAR4 register  *******************/
+#define DMA_CMAR4_MA_Pos                    (0U)
+#define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR5 register  *******************/
+#define DMA_CMAR5_MA_Pos                    (0U)
+#define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR6 register  *******************/
+#define DMA_CMAR6_MA_Pos                    (0U)
+#define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
+
+/******************  Bit definition for DMA_CMAR7 register  *******************/
+#define DMA_CMAR7_MA_Pos                    (0U)
+#define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
+#define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
+
+/******************************************************************************/
+/*                                                                            */
+/*                  External Interrupt/Event Controller (EXTI)                */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define EXTI_IMR_MR0_Pos                    (0U)
+#define EXTI_IMR_MR0_Msk                    (0x1U << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
+#define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos                    (1U)
+#define EXTI_IMR_MR1_Msk                    (0x1U << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
+#define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos                    (2U)
+#define EXTI_IMR_MR2_Msk                    (0x1U << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
+#define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos                    (3U)
+#define EXTI_IMR_MR3_Msk                    (0x1U << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
+#define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos                    (4U)
+#define EXTI_IMR_MR4_Msk                    (0x1U << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
+#define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos                    (5U)
+#define EXTI_IMR_MR5_Msk                    (0x1U << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
+#define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos                    (6U)
+#define EXTI_IMR_MR6_Msk                    (0x1U << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
+#define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos                    (7U)
+#define EXTI_IMR_MR7_Msk                    (0x1U << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
+#define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos                    (8U)
+#define EXTI_IMR_MR8_Msk                    (0x1U << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
+#define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos                    (9U)
+#define EXTI_IMR_MR9_Msk                    (0x1U << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
+#define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos                   (10U)
+#define EXTI_IMR_MR10_Msk                   (0x1U << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
+#define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos                   (11U)
+#define EXTI_IMR_MR11_Msk                   (0x1U << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
+#define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos                   (12U)
+#define EXTI_IMR_MR12_Msk                   (0x1U << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
+#define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos                   (13U)
+#define EXTI_IMR_MR13_Msk                   (0x1U << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
+#define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos                   (14U)
+#define EXTI_IMR_MR14_Msk                   (0x1U << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
+#define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos                   (15U)
+#define EXTI_IMR_MR15_Msk                   (0x1U << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
+#define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos                   (16U)
+#define EXTI_IMR_MR16_Msk                   (0x1U << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
+#define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos                   (17U)
+#define EXTI_IMR_MR17_Msk                   (0x1U << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
+#define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos                   (18U)
+#define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
+#define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos                   (19U)
+#define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
+#define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos                   (20U)
+#define EXTI_IMR_MR20_Msk                   (0x1U << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
+#define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos                   (21U)
+#define EXTI_IMR_MR21_Msk                   (0x1U << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
+#define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos                   (22U)
+#define EXTI_IMR_MR22_Msk                   (0x1U << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
+#define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
+/* Catgeroy 1 & 2 */
+
+/* References Defines */
+#define  EXTI_IMR_IM0 EXTI_IMR_MR0
+#define  EXTI_IMR_IM1 EXTI_IMR_MR1
+#define  EXTI_IMR_IM2 EXTI_IMR_MR2
+#define  EXTI_IMR_IM3 EXTI_IMR_MR3
+#define  EXTI_IMR_IM4 EXTI_IMR_MR4
+#define  EXTI_IMR_IM5 EXTI_IMR_MR5
+#define  EXTI_IMR_IM6 EXTI_IMR_MR6
+#define  EXTI_IMR_IM7 EXTI_IMR_MR7
+#define  EXTI_IMR_IM8 EXTI_IMR_MR8
+#define  EXTI_IMR_IM9 EXTI_IMR_MR9
+#define  EXTI_IMR_IM10 EXTI_IMR_MR10
+#define  EXTI_IMR_IM11 EXTI_IMR_MR11
+#define  EXTI_IMR_IM12 EXTI_IMR_MR12
+#define  EXTI_IMR_IM13 EXTI_IMR_MR13
+#define  EXTI_IMR_IM14 EXTI_IMR_MR14
+#define  EXTI_IMR_IM15 EXTI_IMR_MR15
+#define  EXTI_IMR_IM16 EXTI_IMR_MR16
+#define  EXTI_IMR_IM17 EXTI_IMR_MR17
+#define  EXTI_IMR_IM18 EXTI_IMR_MR18
+#define  EXTI_IMR_IM19 EXTI_IMR_MR19
+#define  EXTI_IMR_IM20 EXTI_IMR_MR20
+#define  EXTI_IMR_IM21 EXTI_IMR_MR21
+#define  EXTI_IMR_IM22 EXTI_IMR_MR22
+/* Catgeroy 1 & 2 */
+#define EXTI_IMR_IM_Pos                     (0U)
+#define EXTI_IMR_IM_Msk                     (0x7FFFFFU << EXTI_IMR_IM_Pos)     /*!< 0x007FFFFF */
+#define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define EXTI_EMR_MR0_Pos                    (0U)
+#define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
+#define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos                    (1U)
+#define EXTI_EMR_MR1_Msk                    (0x1U << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
+#define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos                    (2U)
+#define EXTI_EMR_MR2_Msk                    (0x1U << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
+#define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos                    (3U)
+#define EXTI_EMR_MR3_Msk                    (0x1U << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
+#define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos                    (4U)
+#define EXTI_EMR_MR4_Msk                    (0x1U << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
+#define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos                    (5U)
+#define EXTI_EMR_MR5_Msk                    (0x1U << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
+#define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos                    (6U)
+#define EXTI_EMR_MR6_Msk                    (0x1U << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
+#define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos                    (7U)
+#define EXTI_EMR_MR7_Msk                    (0x1U << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
+#define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos                    (8U)
+#define EXTI_EMR_MR8_Msk                    (0x1U << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
+#define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos                    (9U)
+#define EXTI_EMR_MR9_Msk                    (0x1U << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
+#define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos                   (10U)
+#define EXTI_EMR_MR10_Msk                   (0x1U << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
+#define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos                   (11U)
+#define EXTI_EMR_MR11_Msk                   (0x1U << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
+#define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos                   (12U)
+#define EXTI_EMR_MR12_Msk                   (0x1U << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
+#define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos                   (13U)
+#define EXTI_EMR_MR13_Msk                   (0x1U << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
+#define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos                   (14U)
+#define EXTI_EMR_MR14_Msk                   (0x1U << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
+#define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos                   (15U)
+#define EXTI_EMR_MR15_Msk                   (0x1U << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
+#define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos                   (16U)
+#define EXTI_EMR_MR16_Msk                   (0x1U << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
+#define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos                   (17U)
+#define EXTI_EMR_MR17_Msk                   (0x1U << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
+#define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos                   (18U)
+#define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
+#define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos                   (19U)
+#define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
+#define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos                   (20U)
+#define EXTI_EMR_MR20_Msk                   (0x1U << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
+#define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos                   (21U)
+#define EXTI_EMR_MR21_Msk                   (0x1U << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
+#define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos                   (22U)
+#define EXTI_EMR_MR22_Msk                   (0x1U << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
+#define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
+
+/* References Defines */
+#define  EXTI_EMR_EM0 EXTI_EMR_MR0
+#define  EXTI_EMR_EM1 EXTI_EMR_MR1
+#define  EXTI_EMR_EM2 EXTI_EMR_MR2
+#define  EXTI_EMR_EM3 EXTI_EMR_MR3
+#define  EXTI_EMR_EM4 EXTI_EMR_MR4
+#define  EXTI_EMR_EM5 EXTI_EMR_MR5
+#define  EXTI_EMR_EM6 EXTI_EMR_MR6
+#define  EXTI_EMR_EM7 EXTI_EMR_MR7
+#define  EXTI_EMR_EM8 EXTI_EMR_MR8
+#define  EXTI_EMR_EM9 EXTI_EMR_MR9
+#define  EXTI_EMR_EM10 EXTI_EMR_MR10
+#define  EXTI_EMR_EM11 EXTI_EMR_MR11
+#define  EXTI_EMR_EM12 EXTI_EMR_MR12
+#define  EXTI_EMR_EM13 EXTI_EMR_MR13
+#define  EXTI_EMR_EM14 EXTI_EMR_MR14
+#define  EXTI_EMR_EM15 EXTI_EMR_MR15
+#define  EXTI_EMR_EM16 EXTI_EMR_MR16
+#define  EXTI_EMR_EM17 EXTI_EMR_MR17
+#define  EXTI_EMR_EM18 EXTI_EMR_MR18
+#define  EXTI_EMR_EM19 EXTI_EMR_MR19
+#define  EXTI_EMR_EM20 EXTI_EMR_MR20
+#define  EXTI_EMR_EM21 EXTI_EMR_MR21
+#define  EXTI_EMR_EM22 EXTI_EMR_MR22
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define EXTI_RTSR_TR0_Pos                   (0U)
+#define EXTI_RTSR_TR0_Msk                   (0x1U << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
+#define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos                   (1U)
+#define EXTI_RTSR_TR1_Msk                   (0x1U << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
+#define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos                   (2U)
+#define EXTI_RTSR_TR2_Msk                   (0x1U << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
+#define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos                   (3U)
+#define EXTI_RTSR_TR3_Msk                   (0x1U << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
+#define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos                   (4U)
+#define EXTI_RTSR_TR4_Msk                   (0x1U << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
+#define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos                   (5U)
+#define EXTI_RTSR_TR5_Msk                   (0x1U << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
+#define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos                   (6U)
+#define EXTI_RTSR_TR6_Msk                   (0x1U << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
+#define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos                   (7U)
+#define EXTI_RTSR_TR7_Msk                   (0x1U << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
+#define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos                   (8U)
+#define EXTI_RTSR_TR8_Msk                   (0x1U << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
+#define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos                   (9U)
+#define EXTI_RTSR_TR9_Msk                   (0x1U << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
+#define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos                  (10U)
+#define EXTI_RTSR_TR10_Msk                  (0x1U << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
+#define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos                  (11U)
+#define EXTI_RTSR_TR11_Msk                  (0x1U << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
+#define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos                  (12U)
+#define EXTI_RTSR_TR12_Msk                  (0x1U << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
+#define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos                  (13U)
+#define EXTI_RTSR_TR13_Msk                  (0x1U << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
+#define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos                  (14U)
+#define EXTI_RTSR_TR14_Msk                  (0x1U << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
+#define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos                  (15U)
+#define EXTI_RTSR_TR15_Msk                  (0x1U << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
+#define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos                  (16U)
+#define EXTI_RTSR_TR16_Msk                  (0x1U << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
+#define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos                  (17U)
+#define EXTI_RTSR_TR17_Msk                  (0x1U << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
+#define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos                  (18U)
+#define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
+#define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos                  (19U)
+#define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
+#define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos                  (20U)
+#define EXTI_RTSR_TR20_Msk                  (0x1U << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
+#define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos                  (21U)
+#define EXTI_RTSR_TR21_Msk                  (0x1U << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
+#define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos                  (22U)
+#define EXTI_RTSR_TR22_Msk                  (0x1U << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
+#define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
+
+/* References Defines */
+#define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
+#define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
+#define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
+#define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
+#define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
+#define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
+#define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
+#define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
+#define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
+#define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
+#define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
+#define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
+#define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
+#define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
+#define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
+#define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
+#define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
+#define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
+#define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
+#define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
+#define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
+#define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
+#define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define EXTI_FTSR_TR0_Pos                   (0U)
+#define EXTI_FTSR_TR0_Msk                   (0x1U << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
+#define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos                   (1U)
+#define EXTI_FTSR_TR1_Msk                   (0x1U << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
+#define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos                   (2U)
+#define EXTI_FTSR_TR2_Msk                   (0x1U << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
+#define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos                   (3U)
+#define EXTI_FTSR_TR3_Msk                   (0x1U << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
+#define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos                   (4U)
+#define EXTI_FTSR_TR4_Msk                   (0x1U << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
+#define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos                   (5U)
+#define EXTI_FTSR_TR5_Msk                   (0x1U << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
+#define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos                   (6U)
+#define EXTI_FTSR_TR6_Msk                   (0x1U << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
+#define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos                   (7U)
+#define EXTI_FTSR_TR7_Msk                   (0x1U << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
+#define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos                   (8U)
+#define EXTI_FTSR_TR8_Msk                   (0x1U << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
+#define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos                   (9U)
+#define EXTI_FTSR_TR9_Msk                   (0x1U << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
+#define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos                  (10U)
+#define EXTI_FTSR_TR10_Msk                  (0x1U << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
+#define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos                  (11U)
+#define EXTI_FTSR_TR11_Msk                  (0x1U << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
+#define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos                  (12U)
+#define EXTI_FTSR_TR12_Msk                  (0x1U << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
+#define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos                  (13U)
+#define EXTI_FTSR_TR13_Msk                  (0x1U << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
+#define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos                  (14U)
+#define EXTI_FTSR_TR14_Msk                  (0x1U << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
+#define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos                  (15U)
+#define EXTI_FTSR_TR15_Msk                  (0x1U << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
+#define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos                  (16U)
+#define EXTI_FTSR_TR16_Msk                  (0x1U << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
+#define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos                  (17U)
+#define EXTI_FTSR_TR17_Msk                  (0x1U << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
+#define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos                  (18U)
+#define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
+#define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos                  (19U)
+#define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
+#define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos                  (20U)
+#define EXTI_FTSR_TR20_Msk                  (0x1U << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
+#define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos                  (21U)
+#define EXTI_FTSR_TR21_Msk                  (0x1U << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
+#define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos                  (22U)
+#define EXTI_FTSR_TR22_Msk                  (0x1U << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
+#define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
+
+/* References Defines */
+#define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
+#define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
+#define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
+#define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
+#define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
+#define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
+#define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
+#define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
+#define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
+#define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
+#define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
+#define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
+#define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
+#define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
+#define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
+#define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
+#define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
+#define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
+#define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
+#define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
+#define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
+#define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
+#define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define EXTI_SWIER_SWIER0_Pos               (0U)
+#define EXTI_SWIER_SWIER0_Msk               (0x1U << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos               (1U)
+#define EXTI_SWIER_SWIER1_Msk               (0x1U << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos               (2U)
+#define EXTI_SWIER_SWIER2_Msk               (0x1U << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos               (3U)
+#define EXTI_SWIER_SWIER3_Msk               (0x1U << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos               (4U)
+#define EXTI_SWIER_SWIER4_Msk               (0x1U << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos               (5U)
+#define EXTI_SWIER_SWIER5_Msk               (0x1U << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos               (6U)
+#define EXTI_SWIER_SWIER6_Msk               (0x1U << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos               (7U)
+#define EXTI_SWIER_SWIER7_Msk               (0x1U << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos               (8U)
+#define EXTI_SWIER_SWIER8_Msk               (0x1U << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos               (9U)
+#define EXTI_SWIER_SWIER9_Msk               (0x1U << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos              (10U)
+#define EXTI_SWIER_SWIER10_Msk              (0x1U << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos              (11U)
+#define EXTI_SWIER_SWIER11_Msk              (0x1U << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos              (12U)
+#define EXTI_SWIER_SWIER12_Msk              (0x1U << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos              (13U)
+#define EXTI_SWIER_SWIER13_Msk              (0x1U << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos              (14U)
+#define EXTI_SWIER_SWIER14_Msk              (0x1U << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos              (15U)
+#define EXTI_SWIER_SWIER15_Msk              (0x1U << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos              (16U)
+#define EXTI_SWIER_SWIER16_Msk              (0x1U << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos              (17U)
+#define EXTI_SWIER_SWIER17_Msk              (0x1U << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos              (18U)
+#define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos              (19U)
+#define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos              (20U)
+#define EXTI_SWIER_SWIER20_Msk              (0x1U << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos              (21U)
+#define EXTI_SWIER_SWIER21_Msk              (0x1U << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos              (22U)
+#define EXTI_SWIER_SWIER22_Msk              (0x1U << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
+
+/* References Defines */
+#define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
+#define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
+#define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
+#define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
+#define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
+#define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
+#define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
+#define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
+#define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
+#define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
+#define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
+#define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
+#define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
+#define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
+#define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
+#define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
+#define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
+#define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
+#define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
+#define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
+#define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
+#define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
+#define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define EXTI_PR_PR0_Pos                     (0U)
+#define EXTI_PR_PR0_Msk                     (0x1U << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
+#define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos                     (1U)
+#define EXTI_PR_PR1_Msk                     (0x1U << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
+#define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos                     (2U)
+#define EXTI_PR_PR2_Msk                     (0x1U << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
+#define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos                     (3U)
+#define EXTI_PR_PR3_Msk                     (0x1U << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
+#define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos                     (4U)
+#define EXTI_PR_PR4_Msk                     (0x1U << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
+#define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos                     (5U)
+#define EXTI_PR_PR5_Msk                     (0x1U << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
+#define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos                     (6U)
+#define EXTI_PR_PR6_Msk                     (0x1U << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
+#define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos                     (7U)
+#define EXTI_PR_PR7_Msk                     (0x1U << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
+#define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos                     (8U)
+#define EXTI_PR_PR8_Msk                     (0x1U << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
+#define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos                     (9U)
+#define EXTI_PR_PR9_Msk                     (0x1U << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
+#define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos                    (10U)
+#define EXTI_PR_PR10_Msk                    (0x1U << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
+#define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos                    (11U)
+#define EXTI_PR_PR11_Msk                    (0x1U << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
+#define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos                    (12U)
+#define EXTI_PR_PR12_Msk                    (0x1U << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
+#define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos                    (13U)
+#define EXTI_PR_PR13_Msk                    (0x1U << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
+#define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos                    (14U)
+#define EXTI_PR_PR14_Msk                    (0x1U << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
+#define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos                    (15U)
+#define EXTI_PR_PR15_Msk                    (0x1U << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
+#define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos                    (16U)
+#define EXTI_PR_PR16_Msk                    (0x1U << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
+#define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos                    (17U)
+#define EXTI_PR_PR17_Msk                    (0x1U << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
+#define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos                    (18U)
+#define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
+#define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos                    (19U)
+#define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
+#define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos                    (20U)
+#define EXTI_PR_PR20_Msk                    (0x1U << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
+#define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos                    (21U)
+#define EXTI_PR_PR21_Msk                    (0x1U << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
+#define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos                    (22U)
+#define EXTI_PR_PR22_Msk                    (0x1U << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
+#define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
+
+/* References Defines */
+#define  EXTI_PR_PIF0 EXTI_PR_PR0
+#define  EXTI_PR_PIF1 EXTI_PR_PR1
+#define  EXTI_PR_PIF2 EXTI_PR_PR2
+#define  EXTI_PR_PIF3 EXTI_PR_PR3
+#define  EXTI_PR_PIF4 EXTI_PR_PR4
+#define  EXTI_PR_PIF5 EXTI_PR_PR5
+#define  EXTI_PR_PIF6 EXTI_PR_PR6
+#define  EXTI_PR_PIF7 EXTI_PR_PR7
+#define  EXTI_PR_PIF8 EXTI_PR_PR8
+#define  EXTI_PR_PIF9 EXTI_PR_PR9
+#define  EXTI_PR_PIF10 EXTI_PR_PR10
+#define  EXTI_PR_PIF11 EXTI_PR_PR11
+#define  EXTI_PR_PIF12 EXTI_PR_PR12
+#define  EXTI_PR_PIF13 EXTI_PR_PR13
+#define  EXTI_PR_PIF14 EXTI_PR_PR14
+#define  EXTI_PR_PIF15 EXTI_PR_PR15
+#define  EXTI_PR_PIF16 EXTI_PR_PR16
+#define  EXTI_PR_PIF17 EXTI_PR_PR17
+#define  EXTI_PR_PIF18 EXTI_PR_PR18
+#define  EXTI_PR_PIF19 EXTI_PR_PR19
+#define  EXTI_PR_PIF20 EXTI_PR_PR20
+#define  EXTI_PR_PIF21 EXTI_PR_PR21
+#define  EXTI_PR_PIF22 EXTI_PR_PR22
+
+/******************************************************************************/
+/*                                                                            */
+/*                FLASH, DATA EEPROM and Option Bytes Registers               */
+/*                        (FLASH, DATA_EEPROM, OB)                            */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACR register  ******************/
+#define FLASH_ACR_LATENCY_Pos                (0U)
+#define FLASH_ACR_LATENCY_Msk                (0x1U << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
+#define FLASH_ACR_PRFTEN_Pos                 (1U)
+#define FLASH_ACR_PRFTEN_Msk                 (0x1U << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
+#define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_ACC64_Pos                  (2U)
+#define FLASH_ACR_ACC64_Msk                  (0x1U << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
+#define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
+#define FLASH_ACR_SLEEP_PD_Pos               (3U)
+#define FLASH_ACR_SLEEP_PD_Msk               (0x1U << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
+#define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD_Pos                 (4U)
+#define FLASH_ACR_RUN_PD_Msk                 (0x1U << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
+#define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
+
+/*******************  Bit definition for FLASH_PECR register  ******************/
+#define FLASH_PECR_PELOCK_Pos                (0U)
+#define FLASH_PECR_PELOCK_Msk                (0x1U << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
+#define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK_Pos               (1U)
+#define FLASH_PECR_PRGLOCK_Msk               (0x1U << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
+#define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK_Pos               (2U)
+#define FLASH_PECR_OPTLOCK_Msk               (0x1U << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
+#define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG_Pos                  (3U)
+#define FLASH_PECR_PROG_Msk                  (0x1U << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
+#define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
+#define FLASH_PECR_DATA_Pos                  (4U)
+#define FLASH_PECR_DATA_Msk                  (0x1U << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
+#define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
+#define FLASH_PECR_FTDW_Pos                  (8U)
+#define FLASH_PECR_FTDW_Msk                  (0x1U << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
+#define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE_Pos                 (9U)
+#define FLASH_PECR_ERASE_Msk                 (0x1U << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
+#define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
+#define FLASH_PECR_FPRG_Pos                  (10U)
+#define FLASH_PECR_FPRG_Msk                  (0x1U << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
+#define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_EOPIE_Pos                 (16U)
+#define FLASH_PECR_EOPIE_Msk                 (0x1U << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
+#define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE_Pos                 (17U)
+#define FLASH_PECR_ERRIE_Msk                 (0x1U << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
+#define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH_Pos            (18U)
+#define FLASH_PECR_OBL_LAUNCH_Msk            (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
+#define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */
+
+/******************  Bit definition for FLASH_PDKEYR register  ******************/
+#define FLASH_PDKEYR_PDKEYR_Pos              (0U)
+#define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
+
+/******************  Bit definition for FLASH_PEKEYR register  ******************/
+#define FLASH_PEKEYR_PEKEYR_Pos              (0U)
+#define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
+
+/******************  Bit definition for FLASH_PRGKEYR register  ******************/
+#define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)
+#define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
+
+/******************  Bit definition for FLASH_OPTKEYR register  ******************/
+#define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)
+#define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
+
+/******************  Bit definition for FLASH_SR register  *******************/
+#define FLASH_SR_BSY_Pos                     (0U)
+#define FLASH_SR_BSY_Msk                     (0x1U << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
+#define FLASH_SR_EOP_Pos                     (1U)
+#define FLASH_SR_EOP_Msk                     (0x1U << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
+#define FLASH_SR_ENDHV_Pos                   (2U)
+#define FLASH_SR_ENDHV_Msk                   (0x1U << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
+#define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
+#define FLASH_SR_READY_Pos                   (3U)
+#define FLASH_SR_READY_Msk                   (0x1U << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
+#define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR_Pos                  (8U)
+#define FLASH_SR_WRPERR_Msk                  (0x1U << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
+#define FLASH_SR_PGAERR_Pos                  (9U)
+#define FLASH_SR_PGAERR_Msk                  (0x1U << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
+#define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR_Pos                  (10U)
+#define FLASH_SR_SIZERR_Msk                  (0x1U << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
+#define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
+#define FLASH_SR_OPTVERR_Pos                 (11U)
+#define FLASH_SR_OPTVERR_Msk                 (0x1U << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
+#define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
+#define FLASH_SR_RDERR_Pos                   (13U)
+#define FLASH_SR_RDERR_Msk                   (0x1U << FLASH_SR_RDERR_Pos)      /*!< 0x00002000 */
+#define FLASH_SR_RDERR                       FLASH_SR_RDERR_Msk                /*!< Read protected error */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define FLASH_OBR_RDPRT_Pos                  (0U)
+#define FLASH_OBR_RDPRT_Msk                  (0xFFU << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
+#define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
+#define FLASH_OBR_SPRMOD_Pos                 (8U)
+#define FLASH_OBR_SPRMOD_Msk                 (0x1U << FLASH_OBR_SPRMOD_Pos)    /*!< 0x00000100 */
+#define FLASH_OBR_SPRMOD                     FLASH_OBR_SPRMOD_Msk              /*!< Selection of protection mode of WPRi bits */
+#define FLASH_OBR_BOR_LEV_Pos                (16U)
+#define FLASH_OBR_BOR_LEV_Msk                (0xFU << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
+#define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OBR_USER_Pos                   (20U)
+#define FLASH_OBR_USER_Msk                   (0x7U << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
+#define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW_Pos                (20U)
+#define FLASH_OBR_IWDG_SW_Msk                (0x1U << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
+#define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
+#define FLASH_OBR_nRST_STOP_Pos              (21U)
+#define FLASH_OBR_nRST_STOP_Msk              (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
+#define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY_Pos             (22U)
+#define FLASH_OBR_nRST_STDBY_Msk             (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
+#define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
+
+/******************  Bit definition for FLASH_WRPR register  ******************/
+#define FLASH_WRPR1_WRP_Pos                  (0U)
+#define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFU << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
+#define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0_Pos                (0U)
+#define GPIO_MODER_MODER0_Msk                (0x3U << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
+#define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODER0_0                  (0x1U << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1                  (0x2U << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
+
+#define GPIO_MODER_MODER1_Pos                (2U)
+#define GPIO_MODER_MODER1_Msk                (0x3U << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
+#define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODER1_0                  (0x1U << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1                  (0x2U << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
+
+#define GPIO_MODER_MODER2_Pos                (4U)
+#define GPIO_MODER_MODER2_Msk                (0x3U << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
+#define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODER2_0                  (0x1U << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1                  (0x2U << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
+
+#define GPIO_MODER_MODER3_Pos                (6U)
+#define GPIO_MODER_MODER3_Msk                (0x3U << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODER3_0                  (0x1U << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1                  (0x2U << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
+
+#define GPIO_MODER_MODER4_Pos                (8U)
+#define GPIO_MODER_MODER4_Msk                (0x3U << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
+#define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODER4_0                  (0x1U << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1                  (0x2U << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
+
+#define GPIO_MODER_MODER5_Pos                (10U)
+#define GPIO_MODER_MODER5_Msk                (0x3U << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODER5_0                  (0x1U << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1                  (0x2U << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
+
+#define GPIO_MODER_MODER6_Pos                (12U)
+#define GPIO_MODER_MODER6_Msk                (0x3U << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
+#define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODER6_0                  (0x1U << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1                  (0x2U << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
+
+#define GPIO_MODER_MODER7_Pos                (14U)
+#define GPIO_MODER_MODER7_Msk                (0x3U << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODER7_0                  (0x1U << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1                  (0x2U << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
+
+#define GPIO_MODER_MODER8_Pos                (16U)
+#define GPIO_MODER_MODER8_Msk                (0x3U << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
+#define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODER8_0                  (0x1U << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1                  (0x2U << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
+
+#define GPIO_MODER_MODER9_Pos                (18U)
+#define GPIO_MODER_MODER9_Msk                (0x3U << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODER9_0                  (0x1U << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1                  (0x2U << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
+
+#define GPIO_MODER_MODER10_Pos               (20U)
+#define GPIO_MODER_MODER10_Msk               (0x3U << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
+#define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODER10_0                 (0x1U << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1                 (0x2U << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
+
+#define GPIO_MODER_MODER11_Pos               (22U)
+#define GPIO_MODER_MODER11_Msk               (0x3U << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODER11_0                 (0x1U << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1                 (0x2U << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
+
+#define GPIO_MODER_MODER12_Pos               (24U)
+#define GPIO_MODER_MODER12_Msk               (0x3U << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
+#define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODER12_0                 (0x1U << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1                 (0x2U << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
+
+#define GPIO_MODER_MODER13_Pos               (26U)
+#define GPIO_MODER_MODER13_Msk               (0x3U << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODER13_0                 (0x1U << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1                 (0x2U << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
+
+#define GPIO_MODER_MODER14_Pos               (28U)
+#define GPIO_MODER_MODER14_Msk               (0x3U << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
+#define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODER14_0                 (0x1U << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1                 (0x2U << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
+
+#define GPIO_MODER_MODER15_Pos               (30U)
+#define GPIO_MODER_MODER15_Msk               (0x3U << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODER15_0                 (0x1U << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1                 (0x2U << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT_0                     (0x00000001U)
+#define GPIO_OTYPER_OT_1                     (0x00000002U)
+#define GPIO_OTYPER_OT_2                     (0x00000004U)
+#define GPIO_OTYPER_OT_3                     (0x00000008U)
+#define GPIO_OTYPER_OT_4                     (0x00000010U)
+#define GPIO_OTYPER_OT_5                     (0x00000020U)
+#define GPIO_OTYPER_OT_6                     (0x00000040U)
+#define GPIO_OTYPER_OT_7                     (0x00000080U)
+#define GPIO_OTYPER_OT_8                     (0x00000100U)
+#define GPIO_OTYPER_OT_9                     (0x00000200U)
+#define GPIO_OTYPER_OT_10                    (0x00000400U)
+#define GPIO_OTYPER_OT_11                    (0x00000800U)
+#define GPIO_OTYPER_OT_12                    (0x00001000U)
+#define GPIO_OTYPER_OT_13                    (0x00002000U)
+#define GPIO_OTYPER_OT_14                    (0x00004000U)
+#define GPIO_OTYPER_OT_15                    (0x00008000U)
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)
+#define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
+#define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk
+#define GPIO_OSPEEDER_OSPEEDR0_0             (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
+#define GPIO_OSPEEDER_OSPEEDR0_1             (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
+
+#define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)
+#define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
+#define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk
+#define GPIO_OSPEEDER_OSPEEDR1_0             (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
+#define GPIO_OSPEEDER_OSPEEDR1_1             (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
+
+#define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)
+#define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
+#define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk
+#define GPIO_OSPEEDER_OSPEEDR2_0             (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
+#define GPIO_OSPEEDER_OSPEEDR2_1             (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
+
+#define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)
+#define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
+#define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk
+#define GPIO_OSPEEDER_OSPEEDR3_0             (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
+#define GPIO_OSPEEDER_OSPEEDR3_1             (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
+
+#define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)
+#define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
+#define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk
+#define GPIO_OSPEEDER_OSPEEDR4_0             (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
+#define GPIO_OSPEEDER_OSPEEDR4_1             (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
+
+#define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)
+#define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
+#define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk
+#define GPIO_OSPEEDER_OSPEEDR5_0             (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
+#define GPIO_OSPEEDER_OSPEEDR5_1             (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
+
+#define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)
+#define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
+#define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk
+#define GPIO_OSPEEDER_OSPEEDR6_0             (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
+#define GPIO_OSPEEDER_OSPEEDR6_1             (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
+
+#define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)
+#define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
+#define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk
+#define GPIO_OSPEEDER_OSPEEDR7_0             (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
+#define GPIO_OSPEEDER_OSPEEDR7_1             (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
+
+#define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)
+#define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
+#define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk
+#define GPIO_OSPEEDER_OSPEEDR8_0             (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
+#define GPIO_OSPEEDER_OSPEEDR8_1             (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
+
+#define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)
+#define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
+#define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk
+#define GPIO_OSPEEDER_OSPEEDR9_0             (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
+#define GPIO_OSPEEDER_OSPEEDR9_1             (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
+
+#define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)
+#define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
+#define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk
+#define GPIO_OSPEEDER_OSPEEDR10_0            (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
+#define GPIO_OSPEEDER_OSPEEDR10_1            (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
+
+#define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)
+#define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
+#define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk
+#define GPIO_OSPEEDER_OSPEEDR11_0            (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
+#define GPIO_OSPEEDER_OSPEEDR11_1            (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
+
+#define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)
+#define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
+#define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk
+#define GPIO_OSPEEDER_OSPEEDR12_0            (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
+#define GPIO_OSPEEDER_OSPEEDR12_1            (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
+
+#define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)
+#define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
+#define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk
+#define GPIO_OSPEEDER_OSPEEDR13_0            (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
+#define GPIO_OSPEEDER_OSPEEDR13_1            (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
+
+#define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)
+#define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
+#define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk
+#define GPIO_OSPEEDER_OSPEEDR14_0            (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
+#define GPIO_OSPEEDER_OSPEEDR14_1            (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
+
+#define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)
+#define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
+#define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk
+#define GPIO_OSPEEDER_OSPEEDR15_0            (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
+#define GPIO_OSPEEDER_OSPEEDR15_1            (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPDR0_Pos                (0U)
+#define GPIO_PUPDR_PUPDR0_Msk                (0x3U << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk
+#define GPIO_PUPDR_PUPDR0_0                  (0x1U << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPDR0_1                  (0x2U << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
+
+#define GPIO_PUPDR_PUPDR1_Pos                (2U)
+#define GPIO_PUPDR_PUPDR1_Msk                (0x3U << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk
+#define GPIO_PUPDR_PUPDR1_0                  (0x1U << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPDR1_1                  (0x2U << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
+
+#define GPIO_PUPDR_PUPDR2_Pos                (4U)
+#define GPIO_PUPDR_PUPDR2_Msk                (0x3U << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk
+#define GPIO_PUPDR_PUPDR2_0                  (0x1U << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPDR2_1                  (0x2U << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
+
+#define GPIO_PUPDR_PUPDR3_Pos                (6U)
+#define GPIO_PUPDR_PUPDR3_Msk                (0x3U << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk
+#define GPIO_PUPDR_PUPDR3_0                  (0x1U << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPDR3_1                  (0x2U << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
+
+#define GPIO_PUPDR_PUPDR4_Pos                (8U)
+#define GPIO_PUPDR_PUPDR4_Msk                (0x3U << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk
+#define GPIO_PUPDR_PUPDR4_0                  (0x1U << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPDR4_1                  (0x2U << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
+
+#define GPIO_PUPDR_PUPDR5_Pos                (10U)
+#define GPIO_PUPDR_PUPDR5_Msk                (0x3U << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk
+#define GPIO_PUPDR_PUPDR5_0                  (0x1U << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPDR5_1                  (0x2U << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
+
+#define GPIO_PUPDR_PUPDR6_Pos                (12U)
+#define GPIO_PUPDR_PUPDR6_Msk                (0x3U << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk
+#define GPIO_PUPDR_PUPDR6_0                  (0x1U << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPDR6_1                  (0x2U << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
+
+#define GPIO_PUPDR_PUPDR7_Pos                (14U)
+#define GPIO_PUPDR_PUPDR7_Msk                (0x3U << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk
+#define GPIO_PUPDR_PUPDR7_0                  (0x1U << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPDR7_1                  (0x2U << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
+
+#define GPIO_PUPDR_PUPDR8_Pos                (16U)
+#define GPIO_PUPDR_PUPDR8_Msk                (0x3U << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk
+#define GPIO_PUPDR_PUPDR8_0                  (0x1U << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPDR8_1                  (0x2U << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
+
+#define GPIO_PUPDR_PUPDR9_Pos                (18U)
+#define GPIO_PUPDR_PUPDR9_Msk                (0x3U << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk
+#define GPIO_PUPDR_PUPDR9_0                  (0x1U << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPDR9_1                  (0x2U << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
+
+#define GPIO_PUPDR_PUPDR10_Pos               (20U)
+#define GPIO_PUPDR_PUPDR10_Msk               (0x3U << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk
+#define GPIO_PUPDR_PUPDR10_0                 (0x1U << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPDR10_1                 (0x2U << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
+
+#define GPIO_PUPDR_PUPDR11_Pos               (22U)
+#define GPIO_PUPDR_PUPDR11_Msk               (0x3U << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk
+#define GPIO_PUPDR_PUPDR11_0                 (0x1U << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPDR11_1                 (0x2U << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
+
+#define GPIO_PUPDR_PUPDR12_Pos               (24U)
+#define GPIO_PUPDR_PUPDR12_Msk               (0x3U << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk
+#define GPIO_PUPDR_PUPDR12_0                 (0x1U << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPDR12_1                 (0x2U << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
+
+#define GPIO_PUPDR_PUPDR13_Pos               (26U)
+#define GPIO_PUPDR_PUPDR13_Msk               (0x3U << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk
+#define GPIO_PUPDR_PUPDR13_0                 (0x1U << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPDR13_1                 (0x2U << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
+
+#define GPIO_PUPDR_PUPDR14_Pos               (28U)
+#define GPIO_PUPDR_PUPDR14_Msk               (0x3U << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk
+#define GPIO_PUPDR_PUPDR14_0                 (0x1U << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPDR14_1                 (0x2U << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPDR15_Pos               (30U)
+#define GPIO_PUPDR_PUPDR15_Msk               (0x3U << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk
+#define GPIO_PUPDR_PUPDR15_0                 (0x1U << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPDR15_1                 (0x2U << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_IDR_0                       (0x00000001U)
+#define GPIO_IDR_IDR_1                       (0x00000002U)
+#define GPIO_IDR_IDR_2                       (0x00000004U)
+#define GPIO_IDR_IDR_3                       (0x00000008U)
+#define GPIO_IDR_IDR_4                       (0x00000010U)
+#define GPIO_IDR_IDR_5                       (0x00000020U)
+#define GPIO_IDR_IDR_6                       (0x00000040U)
+#define GPIO_IDR_IDR_7                       (0x00000080U)
+#define GPIO_IDR_IDR_8                       (0x00000100U)
+#define GPIO_IDR_IDR_9                       (0x00000200U)
+#define GPIO_IDR_IDR_10                      (0x00000400U)
+#define GPIO_IDR_IDR_11                      (0x00000800U)
+#define GPIO_IDR_IDR_12                      (0x00001000U)
+#define GPIO_IDR_IDR_13                      (0x00002000U)
+#define GPIO_IDR_IDR_14                      (0x00004000U)
+#define GPIO_IDR_IDR_15                      (0x00008000U)
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_ODR_0                       (0x00000001U)
+#define GPIO_ODR_ODR_1                       (0x00000002U)
+#define GPIO_ODR_ODR_2                       (0x00000004U)
+#define GPIO_ODR_ODR_3                       (0x00000008U)
+#define GPIO_ODR_ODR_4                       (0x00000010U)
+#define GPIO_ODR_ODR_5                       (0x00000020U)
+#define GPIO_ODR_ODR_6                       (0x00000040U)
+#define GPIO_ODR_ODR_7                       (0x00000080U)
+#define GPIO_ODR_ODR_8                       (0x00000100U)
+#define GPIO_ODR_ODR_9                       (0x00000200U)
+#define GPIO_ODR_ODR_10                      (0x00000400U)
+#define GPIO_ODR_ODR_11                      (0x00000800U)
+#define GPIO_ODR_ODR_12                      (0x00001000U)
+#define GPIO_ODR_ODR_13                      (0x00002000U)
+#define GPIO_ODR_ODR_14                      (0x00004000U)
+#define GPIO_ODR_ODR_15                      (0x00008000U)
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS_0                       (0x00000001U)
+#define GPIO_BSRR_BS_1                       (0x00000002U)
+#define GPIO_BSRR_BS_2                       (0x00000004U)
+#define GPIO_BSRR_BS_3                       (0x00000008U)
+#define GPIO_BSRR_BS_4                       (0x00000010U)
+#define GPIO_BSRR_BS_5                       (0x00000020U)
+#define GPIO_BSRR_BS_6                       (0x00000040U)
+#define GPIO_BSRR_BS_7                       (0x00000080U)
+#define GPIO_BSRR_BS_8                       (0x00000100U)
+#define GPIO_BSRR_BS_9                       (0x00000200U)
+#define GPIO_BSRR_BS_10                      (0x00000400U)
+#define GPIO_BSRR_BS_11                      (0x00000800U)
+#define GPIO_BSRR_BS_12                      (0x00001000U)
+#define GPIO_BSRR_BS_13                      (0x00002000U)
+#define GPIO_BSRR_BS_14                      (0x00004000U)
+#define GPIO_BSRR_BS_15                      (0x00008000U)
+#define GPIO_BSRR_BR_0                       (0x00010000U)
+#define GPIO_BSRR_BR_1                       (0x00020000U)
+#define GPIO_BSRR_BR_2                       (0x00040000U)
+#define GPIO_BSRR_BR_3                       (0x00080000U)
+#define GPIO_BSRR_BR_4                       (0x00100000U)
+#define GPIO_BSRR_BR_5                       (0x00200000U)
+#define GPIO_BSRR_BR_6                       (0x00400000U)
+#define GPIO_BSRR_BR_7                       (0x00800000U)
+#define GPIO_BSRR_BR_8                       (0x01000000U)
+#define GPIO_BSRR_BR_9                       (0x02000000U)
+#define GPIO_BSRR_BR_10                      (0x04000000U)
+#define GPIO_BSRR_BR_11                      (0x08000000U)
+#define GPIO_BSRR_BR_12                      (0x10000000U)
+#define GPIO_BSRR_BR_13                      (0x20000000U)
+#define GPIO_BSRR_BR_14                      (0x40000000U)
+#define GPIO_BSRR_BR_15                      (0x80000000U)
+
+/****************** Bit definition for GPIO_LCKR register  ********************/
+#define GPIO_LCKR_LCK0_Pos                   (0U)
+#define GPIO_LCKR_LCK0_Msk                   (0x1U << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk
+#define GPIO_LCKR_LCK1_Pos                   (1U)
+#define GPIO_LCKR_LCK1_Msk                   (0x1U << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk
+#define GPIO_LCKR_LCK2_Pos                   (2U)
+#define GPIO_LCKR_LCK2_Msk                   (0x1U << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk
+#define GPIO_LCKR_LCK3_Pos                   (3U)
+#define GPIO_LCKR_LCK3_Msk                   (0x1U << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk
+#define GPIO_LCKR_LCK4_Pos                   (4U)
+#define GPIO_LCKR_LCK4_Msk                   (0x1U << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk
+#define GPIO_LCKR_LCK5_Pos                   (5U)
+#define GPIO_LCKR_LCK5_Msk                   (0x1U << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk
+#define GPIO_LCKR_LCK6_Pos                   (6U)
+#define GPIO_LCKR_LCK6_Msk                   (0x1U << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk
+#define GPIO_LCKR_LCK7_Pos                   (7U)
+#define GPIO_LCKR_LCK7_Msk                   (0x1U << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk
+#define GPIO_LCKR_LCK8_Pos                   (8U)
+#define GPIO_LCKR_LCK8_Msk                   (0x1U << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk
+#define GPIO_LCKR_LCK9_Pos                   (9U)
+#define GPIO_LCKR_LCK9_Msk                   (0x1U << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk
+#define GPIO_LCKR_LCK10_Pos                  (10U)
+#define GPIO_LCKR_LCK10_Msk                  (0x1U << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk
+#define GPIO_LCKR_LCK11_Pos                  (11U)
+#define GPIO_LCKR_LCK11_Msk                  (0x1U << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk
+#define GPIO_LCKR_LCK12_Pos                  (12U)
+#define GPIO_LCKR_LCK12_Msk                  (0x1U << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk
+#define GPIO_LCKR_LCK13_Pos                  (13U)
+#define GPIO_LCKR_LCK13_Msk                  (0x1U << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk
+#define GPIO_LCKR_LCK14_Pos                  (14U)
+#define GPIO_LCKR_LCK14_Msk                  (0x1U << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk
+#define GPIO_LCKR_LCK15_Pos                  (15U)
+#define GPIO_LCKR_LCK15_Msk                  (0x1U << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk
+#define GPIO_LCKR_LCKK_Pos                   (16U)
+#define GPIO_LCKR_LCKK_Msk                   (0x1U << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk
+
+/****************** Bit definition for GPIO_AFRL register  ********************/
+#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
+#define GPIO_AFRL_AFSEL0_Msk                  (0xFU << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
+#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
+#define GPIO_AFRL_AFSEL1_Msk                  (0xFU << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
+#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
+#define GPIO_AFRL_AFSEL2_Msk                  (0xFU << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
+#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
+#define GPIO_AFRL_AFSEL3_Msk                  (0xFU << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
+#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
+#define GPIO_AFRL_AFSEL4_Msk                  (0xFU << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
+#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
+#define GPIO_AFRL_AFSEL5_Msk                  (0xFU << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
+#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
+#define GPIO_AFRL_AFSEL6_Msk                  (0xFU << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
+#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
+#define GPIO_AFRL_AFSEL7_Msk                  (0xFU << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
+
+/****************** Bit definition for GPIO_AFRH register  ********************/
+#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
+#define GPIO_AFRH_AFSEL8_Msk                  (0xFU << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
+#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
+#define GPIO_AFRH_AFSEL9_Msk                  (0xFU << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
+#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
+#define GPIO_AFRH_AFSEL10_Msk                  (0xFU << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
+#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
+#define GPIO_AFRH_AFSEL11_Msk                  (0xFU << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
+#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
+#define GPIO_AFRH_AFSEL12_Msk                  (0xFU << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
+#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
+#define GPIO_AFRH_AFSEL13_Msk                  (0xFU << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
+#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
+#define GPIO_AFRH_AFSEL14_Msk                  (0xFU << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
+#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
+#define GPIO_AFRH_AFSEL15_Msk                  (0xFU << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Inter-integrated Circuit Interface (I2C)                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define I2C_CR1_PE_Pos                      (0U)
+#define I2C_CR1_PE_Msk                      (0x1U << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
+#define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS_Pos                   (1U)
+#define I2C_CR1_SMBUS_Msk                   (0x1U << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
+#define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE_Pos                 (3U)
+#define I2C_CR1_SMBTYPE_Msk                 (0x1U << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
+#define I2C_CR1_ENARP_Pos                   (4U)
+#define I2C_CR1_ENARP_Msk                   (0x1U << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
+#define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
+#define I2C_CR1_ENPEC_Pos                   (5U)
+#define I2C_CR1_ENPEC_Msk                   (0x1U << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
+#define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
+#define I2C_CR1_ENGC_Pos                    (6U)
+#define I2C_CR1_ENGC_Msk                    (0x1U << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
+#define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH_Pos               (7U)
+#define I2C_CR1_NOSTRETCH_Msk               (0x1U << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START_Pos                   (8U)
+#define I2C_CR1_START_Msk                   (0x1U << I2C_CR1_START_Pos)        /*!< 0x00000100 */
+#define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
+#define I2C_CR1_STOP_Pos                    (9U)
+#define I2C_CR1_STOP_Msk                    (0x1U << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
+#define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
+#define I2C_CR1_ACK_Pos                     (10U)
+#define I2C_CR1_ACK_Msk                     (0x1U << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
+#define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
+#define I2C_CR1_POS_Pos                     (11U)
+#define I2C_CR1_POS_Msk                     (0x1U << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
+#define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos                     (12U)
+#define I2C_CR1_PEC_Msk                     (0x1U << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
+#define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
+#define I2C_CR1_ALERT_Pos                   (13U)
+#define I2C_CR1_ALERT_Msk                   (0x1U << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
+#define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
+#define I2C_CR1_SWRST_Pos                   (15U)
+#define I2C_CR1_SWRST_Msk                   (0x1U << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
+#define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_FREQ_Pos                    (0U)
+#define I2C_CR2_FREQ_Msk                    (0x3FU << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
+#define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0                      (0x01U << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1                      (0x02U << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2                      (0x04U << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3                      (0x08U << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4                      (0x10U << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5                      (0x20U << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos                 (8U)
+#define I2C_CR2_ITERREN_Msk                 (0x1U << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
+#define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN_Pos                 (9U)
+#define I2C_CR2_ITEVTEN_Msk                 (0x1U << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN_Pos                 (10U)
+#define I2C_CR2_ITBUFEN_Msk                 (0x1U << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos                   (11U)
+#define I2C_CR2_DMAEN_Msk                   (0x1U << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
+#define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
+#define I2C_CR2_LAST_Pos                    (12U)
+#define I2C_CR2_LAST_Msk                    (0x1U << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
+#define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
+#define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
+
+#define I2C_OAR1_ADD0_Pos                   (0U)
+#define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
+#define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
+#define I2C_OAR1_ADD1_Pos                   (1U)
+#define I2C_OAR1_ADD1_Msk                   (0x1U << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
+#define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
+#define I2C_OAR1_ADD2_Pos                   (2U)
+#define I2C_OAR1_ADD2_Msk                   (0x1U << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
+#define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
+#define I2C_OAR1_ADD3_Pos                   (3U)
+#define I2C_OAR1_ADD3_Msk                   (0x1U << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
+#define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
+#define I2C_OAR1_ADD4_Pos                   (4U)
+#define I2C_OAR1_ADD4_Msk                   (0x1U << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
+#define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
+#define I2C_OAR1_ADD5_Pos                   (5U)
+#define I2C_OAR1_ADD5_Msk                   (0x1U << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
+#define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
+#define I2C_OAR1_ADD6_Pos                   (6U)
+#define I2C_OAR1_ADD6_Msk                   (0x1U << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
+#define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
+#define I2C_OAR1_ADD7_Pos                   (7U)
+#define I2C_OAR1_ADD7_Msk                   (0x1U << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
+#define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
+#define I2C_OAR1_ADD8_Pos                   (8U)
+#define I2C_OAR1_ADD8_Msk                   (0x1U << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
+#define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
+#define I2C_OAR1_ADD9_Pos                   (9U)
+#define I2C_OAR1_ADD9_Msk                   (0x1U << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
+#define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos                (15U)
+#define I2C_OAR1_ADDMODE_Msk                (0x1U << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define I2C_OAR2_ENDUAL_Pos                 (0U)
+#define I2C_OAR2_ENDUAL_Msk                 (0x1U << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos                   (1U)
+#define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
+#define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define I2C_DR_DR_Pos                       (0U)
+#define I2C_DR_DR_Msk                       (0xFFU << I2C_DR_DR_Pos)           /*!< 0x000000FF */
+#define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define I2C_SR1_SB_Pos                      (0U)
+#define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
+#define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR_Pos                    (1U)
+#define I2C_SR1_ADDR_Msk                    (0x1U << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
+#define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos                     (2U)
+#define I2C_SR1_BTF_Msk                     (0x1U << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
+#define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10_Pos                   (3U)
+#define I2C_SR1_ADD10_Msk                   (0x1U << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
+#define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF_Pos                   (4U)
+#define I2C_SR1_STOPF_Msk                   (0x1U << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
+#define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE_Pos                    (6U)
+#define I2C_SR1_RXNE_Msk                    (0x1U << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
+#define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE_Pos                     (7U)
+#define I2C_SR1_TXE_Msk                     (0x1U << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
+#define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR_Pos                    (8U)
+#define I2C_SR1_BERR_Msk                    (0x1U << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
+#define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
+#define I2C_SR1_ARLO_Pos                    (9U)
+#define I2C_SR1_ARLO_Msk                    (0x1U << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
+#define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF_Pos                      (10U)
+#define I2C_SR1_AF_Msk                      (0x1U << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
+#define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
+#define I2C_SR1_OVR_Pos                     (11U)
+#define I2C_SR1_OVR_Msk                     (0x1U << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
+#define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR_Pos                  (12U)
+#define I2C_SR1_PECERR_Msk                  (0x1U << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
+#define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT_Pos                 (14U)
+#define I2C_SR1_TIMEOUT_Msk                 (0x1U << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT_Pos                (15U)
+#define I2C_SR1_SMBALERT_Msk                (0x1U << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define I2C_SR2_MSL_Pos                     (0U)
+#define I2C_SR2_MSL_Msk                     (0x1U << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
+#define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
+#define I2C_SR2_BUSY_Pos                    (1U)
+#define I2C_SR2_BUSY_Msk                    (0x1U << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
+#define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
+#define I2C_SR2_TRA_Pos                     (2U)
+#define I2C_SR2_TRA_Msk                     (0x1U << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
+#define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL_Pos                 (4U)
+#define I2C_SR2_GENCALL_Msk                 (0x1U << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
+#define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT_Pos              (5U)
+#define I2C_SR2_SMBDEFAULT_Msk              (0x1U << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST_Pos                 (6U)
+#define I2C_SR2_SMBHOST_Msk                 (0x1U << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF_Pos                   (7U)
+#define I2C_SR2_DUALF_Msk                   (0x1U << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
+#define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC_Pos                     (8U)
+#define I2C_SR2_PEC_Msk                     (0xFFU << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
+#define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define I2C_CCR_CCR_Pos                     (0U)
+#define I2C_CCR_CCR_Msk                     (0xFFFU << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
+#define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos                    (14U)
+#define I2C_CCR_DUTY_Msk                    (0x1U << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
+#define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS_Pos                      (15U)
+#define I2C_CCR_FS_Msk                      (0x1U << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
+#define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define I2C_TRISE_TRISE_Pos                 (0U)
+#define I2C_TRISE_TRISE_Msk                 (0x3FU << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
+#define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Independent WATCHDOG (IWDG)                         */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos                     (0U)
+#define IWDG_KR_KEY_Msk                     (0xFFFFU << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
+#define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos                      (0U)
+#define IWDG_PR_PR_Msk                      (0x7U << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
+#define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0                        (0x1U << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
+#define IWDG_PR_PR_1                        (0x2U << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
+#define IWDG_PR_PR_2                        (0x4U << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos                     (0U)
+#define IWDG_RLR_RL_Msk                     (0xFFFU << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
+#define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos                     (0U)
+#define IWDG_SR_PVU_Msk                     (0x1U << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
+#define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU_Pos                     (1U)
+#define IWDG_SR_RVU_Msk                     (0x1U << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
+#define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          Power Control (PWR)                               */
+/*                                                                            */
+/******************************************************************************/
+
+#define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
+
+/********************  Bit definition for PWR_CR register  ********************/
+#define PWR_CR_LPSDSR_Pos                   (0U)
+#define PWR_CR_LPSDSR_Msk                   (0x1U << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
+#define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS_Pos                     (1U)
+#define PWR_CR_PDDS_Msk                     (0x1U << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
+#define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF_Pos                     (2U)
+#define PWR_CR_CWUF_Msk                     (0x1U << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
+#define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF_Pos                     (3U)
+#define PWR_CR_CSBF_Msk                     (0x1U << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
+#define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
+#define PWR_CR_PVDE_Pos                     (4U)
+#define PWR_CR_PVDE_Msk                     (0x1U << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
+#define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS_Pos                      (5U)
+#define PWR_CR_PLS_Msk                      (0x7U << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
+#define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0                        (0x1U << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
+#define PWR_CR_PLS_1                        (0x2U << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
+#define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
+
+#define PWR_CR_DBP_Pos                      (8U)
+#define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
+#define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP_Pos                      (9U)
+#define PWR_CR_ULP_Msk                      (0x1U << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
+#define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
+#define PWR_CR_FWU_Pos                      (10U)
+#define PWR_CR_FWU_Msk                      (0x1U << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
+#define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
+
+#define PWR_CR_VOS_Pos                      (11U)
+#define PWR_CR_VOS_Msk                      (0x3U << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
+#define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0                        (0x1U << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
+#define PWR_CR_VOS_1                        (0x2U << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
+#define PWR_CR_LPRUN_Pos                    (14U)
+#define PWR_CR_LPRUN_Msk                    (0x1U << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
+#define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define PWR_CSR_WUF_Pos                     (0U)
+#define PWR_CSR_WUF_Msk                     (0x1U << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
+#define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
+#define PWR_CSR_SBF_Pos                     (1U)
+#define PWR_CSR_SBF_Msk                     (0x1U << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
+#define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
+#define PWR_CSR_PVDO_Pos                    (2U)
+#define PWR_CSR_PVDO_Msk                    (0x1U << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
+#define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF_Pos             (3U)
+#define PWR_CSR_VREFINTRDYF_Msk             (0x1U << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
+#define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF_Pos                    (4U)
+#define PWR_CSR_VOSF_Msk                    (0x1U << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
+#define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF_Pos                  (5U)
+#define PWR_CSR_REGLPF_Msk                  (0x1U << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
+#define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1_Pos                   (8U)
+#define PWR_CSR_EWUP1_Msk                   (0x1U << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
+#define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2_Pos                   (9U)
+#define PWR_CSR_EWUP2_Msk                   (0x1U << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
+#define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3_Pos                   (10U)
+#define PWR_CSR_EWUP3_Msk                   (0x1U << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
+#define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Reset and Clock Control (RCC)                         */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
+*/
+#define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
+
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                    (0U)
+#define RCC_CR_HSION_Msk                    (0x1U << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
+#define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY_Pos                   (1U)
+#define RCC_CR_HSIRDY_Msk                   (0x1U << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
+#define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
+
+#define RCC_CR_MSION_Pos                    (8U)
+#define RCC_CR_MSION_Msk                    (0x1U << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
+#define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY_Pos                   (9U)
+#define RCC_CR_MSIRDY_Msk                   (0x1U << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
+#define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
+
+#define RCC_CR_HSEON_Pos                    (16U)
+#define RCC_CR_HSEON_Msk                    (0x1U << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
+#define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY_Pos                   (17U)
+#define RCC_CR_HSERDY_Msk                   (0x1U << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
+#define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP_Pos                   (18U)
+#define RCC_CR_HSEBYP_Msk                   (0x1U << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
+
+#define RCC_CR_PLLON_Pos                    (24U)
+#define RCC_CR_PLLON_Msk                    (0x1U << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
+#define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
+#define RCC_CR_PLLRDY_Pos                   (25U)
+#define RCC_CR_PLLRDY_Msk                   (0x1U << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
+#define RCC_CR_CSSON_Pos                    (28U)
+#define RCC_CR_CSSON_Msk                    (0x1U << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
+#define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
+
+#define RCC_CR_RTCPRE_Pos                   (29U)
+#define RCC_CR_RTCPRE_Msk                   (0x3U << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
+#define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC Prescaler */
+#define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
+#define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
+
+/********************  Bit definition for RCC_ICSCR register  *****************/
+#define RCC_ICSCR_HSICAL_Pos                (0U)
+#define RCC_ICSCR_HSICAL_Msk                (0xFFU << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
+#define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM_Pos               (8U)
+#define RCC_ICSCR_HSITRIM_Msk               (0x1FU << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
+#define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE_Pos              (13U)
+#define RCC_ICSCR_MSIRANGE_Msk              (0x7U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
+#define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0                (0x0U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
+#define RCC_ICSCR_MSIRANGE_1                (0x1U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
+#define RCC_ICSCR_MSIRANGE_2                (0x2U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
+#define RCC_ICSCR_MSIRANGE_3                (0x3U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
+#define RCC_ICSCR_MSIRANGE_4                (0x4U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
+#define RCC_ICSCR_MSIRANGE_5                (0x5U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
+#define RCC_ICSCR_MSIRANGE_6                (0x6U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
+#define RCC_ICSCR_MSICAL_Pos                (16U)
+#define RCC_ICSCR_MSICAL_Msk                (0xFFU << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
+#define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM_Pos               (24U)
+#define RCC_ICSCR_MSITRIM_Msk               (0xFFU << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
+#define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+#define RCC_CFGR_SW_Pos                     (0U)
+#define RCC_CFGR_SW_Msk                     (0x3U << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
+#define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                       (0x1U << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                       (0x2U << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
+
+/*!< SW configuration */
+#define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
+
+#define RCC_CFGR_SWS_Pos                    (2U)
+#define RCC_CFGR_SWS_Msk                    (0x3U << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
+#define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                      (0x1U << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                      (0x2U << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
+
+#define RCC_CFGR_HPRE_Pos                   (4U)
+#define RCC_CFGR_HPRE_Msk                   (0xFU << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                     (0x1U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                     (0x2U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                     (0x4U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                     (0x8U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
+
+#define RCC_CFGR_PPRE1_Pos                  (8U)
+#define RCC_CFGR_PPRE1_Msk                  (0x7U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
+#define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0                    (0x1U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
+#define RCC_CFGR_PPRE1_1                    (0x2U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
+#define RCC_CFGR_PPRE1_2                    (0x4U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_PPRE2_Pos                  (11U)
+#define RCC_CFGR_PPRE2_Msk                  (0x7U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
+#define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                    (0x1U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
+#define RCC_CFGR_PPRE2_1                    (0x2U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
+#define RCC_CFGR_PPRE2_2                    (0x4U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC_Pos                 (16U)
+#define RCC_CFGR_PLLSRC_Msk                 (0x1U << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
+#define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
+
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL_Pos                 (18U)
+#define RCC_CFGR_PLLMUL_Msk                 (0xFU << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
+#define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0                   (0x1U << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
+#define RCC_CFGR_PLLMUL_1                   (0x2U << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
+#define RCC_CFGR_PLLMUL_2                   (0x4U << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
+#define RCC_CFGR_PLLMUL_3                   (0x8U << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV_Pos                 (22U)
+#define RCC_CFGR_PLLDIV_Msk                 (0x3U << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0                   (0x1U << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV_1                   (0x2U << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
+
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
+#define RCC_CFGR_PLLDIV2_Pos                (22U)
+#define RCC_CFGR_PLLDIV2_Msk                (0x1U << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
+#define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3_Pos                (23U)
+#define RCC_CFGR_PLLDIV3_Msk                (0x1U << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
+#define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4_Pos                (22U)
+#define RCC_CFGR_PLLDIV4_Msk                (0x3U << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
+#define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
+
+
+#define RCC_CFGR_MCOSEL_Pos                 (24U)
+#define RCC_CFGR_MCOSEL_Msk                 (0x7U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0                   (0x1U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_1                   (0x2U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_2                   (0x4U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
+#define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)
+#define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
+#define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
+#define RCC_CFGR_MCOSEL_HSI_Pos             (25U)
+#define RCC_CFGR_MCOSEL_HSI_Msk             (0x1U << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
+#define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_MSI_Pos             (24U)
+#define RCC_CFGR_MCOSEL_MSI_Msk             (0x3U << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
+#define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCOSEL_HSE_Pos             (26U)
+#define RCC_CFGR_MCOSEL_HSE_Msk             (0x1U << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
+#define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCOSEL_PLL_Pos             (24U)
+#define RCC_CFGR_MCOSEL_PLL_Msk             (0x5U << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
+#define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
+#define RCC_CFGR_MCOSEL_LSI_Pos             (25U)
+#define RCC_CFGR_MCOSEL_LSI_Msk             (0x3U << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
+#define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
+#define RCC_CFGR_MCOSEL_LSE_Pos             (24U)
+#define RCC_CFGR_MCOSEL_LSE_Msk             (0x7U << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
+#define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE_Pos                 (28U)
+#define RCC_CFGR_MCOPRE_Msk                 (0x7U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
+#define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
+#define RCC_CFGR_MCOPRE_0                   (0x1U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
+#define RCC_CFGR_MCOPRE_1                   (0x2U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
+#define RCC_CFGR_MCOPRE_2                   (0x4U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
+
+/*!< MCO Prescaler configuration */
+#define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
+#define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
+#define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
+#define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
+#define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
+
+/* Legacy aliases */
+#define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
+#define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
+#define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
+#define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
+#define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
+#define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
+#define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
+#define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
+#define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
+#define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
+#define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
+#define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
+#define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
+
+/*!<******************  Bit definition for RCC_CIR register  ********************/
+#define RCC_CIR_LSIRDYF_Pos                 (0U)
+#define RCC_CIR_LSIRDYF_Msk                 (0x1U << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF_Pos                 (1U)
+#define RCC_CIR_LSERDYF_Msk                 (0x1U << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF_Pos                 (2U)
+#define RCC_CIR_HSIRDYF_Msk                 (0x1U << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF_Pos                 (3U)
+#define RCC_CIR_HSERDYF_Msk                 (0x1U << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF_Pos                 (4U)
+#define RCC_CIR_PLLRDYF_Msk                 (0x1U << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_MSIRDYF_Pos                 (5U)
+#define RCC_CIR_MSIRDYF_Msk                 (0x1U << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
+#define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
+#define RCC_CIR_LSECSSF_Pos                 (6U)
+#define RCC_CIR_LSECSSF_Msk                 (0x1U << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
+#define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
+#define RCC_CIR_CSSF_Pos                    (7U)
+#define RCC_CIR_CSSF_Msk                    (0x1U << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
+#define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
+
+#define RCC_CIR_LSIRDYIE_Pos                (8U)
+#define RCC_CIR_LSIRDYIE_Msk                (0x1U << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE_Pos                (9U)
+#define RCC_CIR_LSERDYIE_Msk                (0x1U << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE_Pos                (10U)
+#define RCC_CIR_HSIRDYIE_Msk                (0x1U << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE_Pos                (11U)
+#define RCC_CIR_HSERDYIE_Msk                (0x1U << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE_Pos                (12U)
+#define RCC_CIR_PLLRDYIE_Msk                (0x1U << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_MSIRDYIE_Pos                (13U)
+#define RCC_CIR_MSIRDYIE_Msk                (0x1U << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
+#define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
+#define RCC_CIR_LSECSSIE_Pos                (14U)
+#define RCC_CIR_LSECSSIE_Msk                (0x1U << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
+#define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
+
+#define RCC_CIR_LSIRDYC_Pos                 (16U)
+#define RCC_CIR_LSIRDYC_Msk                 (0x1U << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC_Pos                 (17U)
+#define RCC_CIR_LSERDYC_Msk                 (0x1U << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC_Pos                 (18U)
+#define RCC_CIR_HSIRDYC_Msk                 (0x1U << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC_Pos                 (19U)
+#define RCC_CIR_HSERDYC_Msk                 (0x1U << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC_Pos                 (20U)
+#define RCC_CIR_PLLRDYC_Msk                 (0x1U << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_MSIRDYC_Pos                 (21U)
+#define RCC_CIR_MSIRDYC_Msk                 (0x1U << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
+#define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
+#define RCC_CIR_LSECSSC_Pos                 (22U)
+#define RCC_CIR_LSECSSC_Msk                 (0x1U << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
+#define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
+#define RCC_CIR_CSSC_Pos                    (23U)
+#define RCC_CIR_CSSC_Msk                    (0x1U << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
+#define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_AHBRSTR register  ******************/
+#define RCC_AHBRSTR_GPIOARST_Pos            (0U)
+#define RCC_AHBRSTR_GPIOARST_Msk            (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
+#define RCC_AHBRSTR_GPIOBRST_Pos            (1U)
+#define RCC_AHBRSTR_GPIOBRST_Msk            (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
+#define RCC_AHBRSTR_GPIOCRST_Pos            (2U)
+#define RCC_AHBRSTR_GPIOCRST_Msk            (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
+#define RCC_AHBRSTR_GPIODRST_Pos            (3U)
+#define RCC_AHBRSTR_GPIODRST_Msk            (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
+#define RCC_AHBRSTR_GPIOERST_Pos            (4U)
+#define RCC_AHBRSTR_GPIOERST_Msk            (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
+#define RCC_AHBRSTR_GPIOHRST_Pos            (5U)
+#define RCC_AHBRSTR_GPIOHRST_Msk            (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
+#define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
+#define RCC_AHBRSTR_CRCRST_Pos              (12U)
+#define RCC_AHBRSTR_CRCRST_Msk              (0x1U << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
+#define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
+#define RCC_AHBRSTR_FLITFRST_Pos            (15U)
+#define RCC_AHBRSTR_FLITFRST_Msk            (0x1U << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
+#define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
+#define RCC_AHBRSTR_DMA1RST_Pos             (24U)
+#define RCC_AHBRSTR_DMA1RST_Msk             (0x1U << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
+#define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
+
+/*****************  Bit definition for RCC_APB2RSTR register  *****************/
+#define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)
+#define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
+#define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
+#define RCC_APB2RSTR_TIM9RST_Pos            (2U)
+#define RCC_APB2RSTR_TIM9RST_Msk            (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
+#define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
+#define RCC_APB2RSTR_TIM10RST_Pos           (3U)
+#define RCC_APB2RSTR_TIM10RST_Msk           (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
+#define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
+#define RCC_APB2RSTR_TIM11RST_Pos           (4U)
+#define RCC_APB2RSTR_TIM11RST_Msk           (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
+#define RCC_APB2RSTR_ADC1RST_Pos            (9U)
+#define RCC_APB2RSTR_ADC1RST_Msk            (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
+#define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
+#define RCC_APB2RSTR_SPI1RST_Pos            (12U)
+#define RCC_APB2RSTR_SPI1RST_Msk            (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST_Pos          (14U)
+#define RCC_APB2RSTR_USART1RST_Msk          (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
+
+/*****************  Bit definition for RCC_APB1RSTR register  *****************/
+#define RCC_APB1RSTR_TIM2RST_Pos            (0U)
+#define RCC_APB1RSTR_TIM2RST_Msk            (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST_Pos            (1U)
+#define RCC_APB1RSTR_TIM3RST_Msk            (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM4RST_Pos            (2U)
+#define RCC_APB1RSTR_TIM4RST_Msk            (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
+#define RCC_APB1RSTR_TIM6RST_Pos            (4U)
+#define RCC_APB1RSTR_TIM6RST_Msk            (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST_Pos            (5U)
+#define RCC_APB1RSTR_TIM7RST_Msk            (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
+#define RCC_APB1RSTR_WWDGRST_Pos            (11U)
+#define RCC_APB1RSTR_WWDGRST_Msk            (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST_Pos            (14U)
+#define RCC_APB1RSTR_SPI2RST_Msk            (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
+#define RCC_APB1RSTR_USART2RST_Pos          (17U)
+#define RCC_APB1RSTR_USART2RST_Msk          (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
+#define RCC_APB1RSTR_USART3RST_Pos          (18U)
+#define RCC_APB1RSTR_USART3RST_Msk          (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
+#define RCC_APB1RSTR_I2C1RST_Pos            (21U)
+#define RCC_APB1RSTR_I2C1RST_Msk            (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST_Pos            (22U)
+#define RCC_APB1RSTR_I2C2RST_Msk            (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST_Pos             (23U)
+#define RCC_APB1RSTR_USBRST_Msk             (0x1U << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
+#define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
+#define RCC_APB1RSTR_PWRRST_Pos             (28U)
+#define RCC_APB1RSTR_PWRRST_Msk             (0x1U << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
+#define RCC_APB1RSTR_DACRST_Pos             (29U)
+#define RCC_APB1RSTR_DACRST_Msk             (0x1U << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
+#define RCC_APB1RSTR_COMPRST_Pos            (31U)
+#define RCC_APB1RSTR_COMPRST_Msk            (0x1U << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
+#define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
+
+/******************  Bit definition for RCC_AHBENR register  ******************/
+#define RCC_AHBENR_GPIOAEN_Pos              (0U)
+#define RCC_AHBENR_GPIOAEN_Msk              (0x1U << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
+#define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
+#define RCC_AHBENR_GPIOBEN_Pos              (1U)
+#define RCC_AHBENR_GPIOBEN_Msk              (0x1U << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
+#define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
+#define RCC_AHBENR_GPIOCEN_Pos              (2U)
+#define RCC_AHBENR_GPIOCEN_Msk              (0x1U << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
+#define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
+#define RCC_AHBENR_GPIODEN_Pos              (3U)
+#define RCC_AHBENR_GPIODEN_Msk              (0x1U << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
+#define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
+#define RCC_AHBENR_GPIOEEN_Pos              (4U)
+#define RCC_AHBENR_GPIOEEN_Msk              (0x1U << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
+#define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
+#define RCC_AHBENR_GPIOHEN_Pos              (5U)
+#define RCC_AHBENR_GPIOHEN_Msk              (0x1U << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
+#define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
+#define RCC_AHBENR_CRCEN_Pos                (12U)
+#define RCC_AHBENR_CRCEN_Msk                (0x1U << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
+#define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
+#define RCC_AHBENR_FLITFEN_Pos              (15U)
+#define RCC_AHBENR_FLITFEN_Msk              (0x1U << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
+#define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
+                                                                                the Flash memory is in power down mode) */
+#define RCC_AHBENR_DMA1EN_Pos               (24U)
+#define RCC_AHBENR_DMA1EN_Msk               (0x1U << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
+#define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
+
+/******************  Bit definition for RCC_APB2ENR register  *****************/
+#define RCC_APB2ENR_SYSCFGEN_Pos            (0U)
+#define RCC_APB2ENR_SYSCFGEN_Msk            (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
+#define RCC_APB2ENR_TIM9EN_Pos              (2U)
+#define RCC_APB2ENR_TIM9EN_Msk              (0x1U << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
+#define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
+#define RCC_APB2ENR_TIM10EN_Pos             (3U)
+#define RCC_APB2ENR_TIM10EN_Msk             (0x1U << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
+#define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
+#define RCC_APB2ENR_TIM11EN_Pos             (4U)
+#define RCC_APB2ENR_TIM11EN_Msk             (0x1U << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
+#define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
+#define RCC_APB2ENR_ADC1EN_Pos              (9U)
+#define RCC_APB2ENR_ADC1EN_Msk              (0x1U << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SPI1EN_Pos              (12U)
+#define RCC_APB2ENR_SPI1EN_Msk              (0x1U << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN_Pos            (14U)
+#define RCC_APB2ENR_USART1EN_Msk            (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
+#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
+
+/*****************  Bit definition for RCC_APB1ENR register  ******************/
+#define RCC_APB1ENR_TIM2EN_Pos              (0U)
+#define RCC_APB1ENR_TIM2EN_Msk              (0x1U << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN_Pos              (1U)
+#define RCC_APB1ENR_TIM3EN_Msk              (0x1U << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM4EN_Pos              (2U)
+#define RCC_APB1ENR_TIM4EN_Msk              (0x1U << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_TIM6EN_Pos              (4U)
+#define RCC_APB1ENR_TIM6EN_Msk              (0x1U << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN_Pos              (5U)
+#define RCC_APB1ENR_TIM7EN_Msk              (0x1U << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_WWDGEN_Pos              (11U)
+#define RCC_APB1ENR_WWDGEN_Msk              (0x1U << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN_Pos              (14U)
+#define RCC_APB1ENR_SPI2EN_Msk              (0x1U << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_USART2EN_Pos            (17U)
+#define RCC_APB1ENR_USART2EN_Msk            (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN_Pos            (18U)
+#define RCC_APB1ENR_USART3EN_Msk            (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
+#define RCC_APB1ENR_I2C1EN_Pos              (21U)
+#define RCC_APB1ENR_I2C1EN_Msk              (0x1U << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_I2C2EN_Pos              (22U)
+#define RCC_APB1ENR_I2C2EN_Msk              (0x1U << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
+#define RCC_APB1ENR_USBEN_Pos               (23U)
+#define RCC_APB1ENR_USBEN_Msk               (0x1U << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
+#define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
+#define RCC_APB1ENR_PWREN_Pos               (28U)
+#define RCC_APB1ENR_PWREN_Msk               (0x1U << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
+#define RCC_APB1ENR_DACEN_Pos               (29U)
+#define RCC_APB1ENR_DACEN_Msk               (0x1U << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
+#define RCC_APB1ENR_COMPEN_Pos              (31U)
+#define RCC_APB1ENR_COMPEN_Msk              (0x1U << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
+#define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
+
+/******************  Bit definition for RCC_AHBLPENR register  ****************/
+#define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)
+#define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1U << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)
+#define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1U << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)
+#define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1U << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)
+#define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1U << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)
+#define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1U << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)
+#define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1U << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
+#define RCC_AHBLPENR_CRCLPEN_Pos            (12U)
+#define RCC_AHBLPENR_CRCLPEN_Msk            (0x1U << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)
+#define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1U << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
+                                                                                (has effect only when the Flash memory is
+                                                                                 in power down mode) */
+#define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)
+#define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1U << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)
+#define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1U << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
+#define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
+
+/******************  Bit definition for RCC_APB2LPENR register  ***************/
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
+#define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)
+#define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
+#define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)
+#define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
+#define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)
+#define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
+#define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)
+#define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)
+#define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2LPENR_USART1LPEN_Pos        (14U)
+#define RCC_APB2LPENR_USART1LPEN_Msk        (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
+
+/*****************  Bit definition for RCC_APB1LPENR register  ****************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)
+#define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)
+#define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)
+#define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)
+#define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)
+#define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
+#define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)
+#define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)
+#define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_USART2LPEN_Pos        (17U)
+#define RCC_APB1LPENR_USART2LPEN_Msk        (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_USART3LPEN_Pos        (18U)
+#define RCC_APB1LPENR_USART3LPEN_Msk        (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
+#define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)
+#define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
+#define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)
+#define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_USBLPEN_Pos           (23U)
+#define RCC_APB1LPENR_USBLPEN_Msk           (0x1U << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
+#define RCC_APB1LPENR_PWRLPEN_Pos           (28U)
+#define RCC_APB1LPENR_PWRLPEN_Msk           (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
+#define RCC_APB1LPENR_DACLPEN_Pos           (29U)
+#define RCC_APB1LPENR_DACLPEN_Msk           (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
+#define RCC_APB1LPENR_COMPLPEN_Pos          (31U)
+#define RCC_APB1LPENR_COMPLPEN_Msk          (0x1U << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
+#define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
+
+/*******************  Bit definition for RCC_CSR register  ********************/
+#define RCC_CSR_LSION_Pos                   (0U)
+#define RCC_CSR_LSION_Msk                   (0x1U << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
+#define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY_Pos                  (1U)
+#define RCC_CSR_LSIRDY_Msk                  (0x1U << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON_Pos                   (8U)
+#define RCC_CSR_LSEON_Msk                   (0x1U << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
+#define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY_Pos                  (9U)
+#define RCC_CSR_LSERDY_Msk                  (0x1U << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
+#define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP_Pos                  (10U)
+#define RCC_CSR_LSEBYP_Msk                  (0x1U << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
+#define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
+
+#define RCC_CSR_LSECSSON_Pos                (11U)
+#define RCC_CSR_LSECSSON_Msk                (0x1U << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
+#define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD_Pos                 (12U)
+#define RCC_CSR_LSECSSD_Msk                 (0x1U << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
+#define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
+
+#define RCC_CSR_RTCSEL_Pos                  (16U)
+#define RCC_CSR_RTCSEL_Msk                  (0x3U << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0                    (0x1U << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_1                    (0x2U << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE_Pos              (16U)
+#define RCC_CSR_RTCSEL_LSE_Msk              (0x1U << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
+#define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI_Pos              (17U)
+#define RCC_CSR_RTCSEL_LSI_Msk              (0x1U << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
+#define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE_Pos              (16U)
+#define RCC_CSR_RTCSEL_HSE_Msk              (0x3U << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
+#define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
+
+#define RCC_CSR_RTCEN_Pos                   (22U)
+#define RCC_CSR_RTCEN_Msk                   (0x1U << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
+#define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
+#define RCC_CSR_RTCRST_Pos                  (23U)
+#define RCC_CSR_RTCRST_Msk                  (0x1U << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
+#define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
+
+#define RCC_CSR_RMVF_Pos                    (24U)
+#define RCC_CSR_RMVF_Msk                    (0x1U << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
+#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF_Pos                 (25U)
+#define RCC_CSR_OBLRSTF_Msk                 (0x1U << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
+#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
+#define RCC_CSR_PINRSTF_Pos                 (26U)
+#define RCC_CSR_PINRSTF_Msk                 (0x1U << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF_Pos                 (27U)
+#define RCC_CSR_PORRSTF_Msk                 (0x1U << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF_Pos                 (28U)
+#define RCC_CSR_SFTRSTF_Msk                 (0x1U << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF_Pos                (29U)
+#define RCC_CSR_IWDGRSTF_Msk                (0x1U << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF_Pos                (30U)
+#define RCC_CSR_WWDGRSTF_Msk                (0x1U << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF_Pos                (31U)
+#define RCC_CSR_LPWRRSTF_Msk                (0x1U << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+* @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
+*/
+#define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
+#define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
+#define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
+#define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
+#define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
+#define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
+#define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
+
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                        (22U)
+#define RTC_TR_PM_Msk                        (0x1U << RTC_TR_PM_Pos)           /*!< 0x00400000 */
+#define RTC_TR_PM                            RTC_TR_PM_Msk
+#define RTC_TR_HT_Pos                        (20U)
+#define RTC_TR_HT_Msk                        (0x3U << RTC_TR_HT_Pos)           /*!< 0x00300000 */
+#define RTC_TR_HT                            RTC_TR_HT_Msk
+#define RTC_TR_HT_0                          (0x1U << RTC_TR_HT_Pos)           /*!< 0x00100000 */
+#define RTC_TR_HT_1                          (0x2U << RTC_TR_HT_Pos)           /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                        (16U)
+#define RTC_TR_HU_Msk                        (0xFU << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
+#define RTC_TR_HU                            RTC_TR_HU_Msk
+#define RTC_TR_HU_0                          (0x1U << RTC_TR_HU_Pos)           /*!< 0x00010000 */
+#define RTC_TR_HU_1                          (0x2U << RTC_TR_HU_Pos)           /*!< 0x00020000 */
+#define RTC_TR_HU_2                          (0x4U << RTC_TR_HU_Pos)           /*!< 0x00040000 */
+#define RTC_TR_HU_3                          (0x8U << RTC_TR_HU_Pos)           /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                       (12U)
+#define RTC_TR_MNT_Msk                       (0x7U << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
+#define RTC_TR_MNT                           RTC_TR_MNT_Msk
+#define RTC_TR_MNT_0                         (0x1U << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
+#define RTC_TR_MNT_1                         (0x2U << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
+#define RTC_TR_MNT_2                         (0x4U << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                       (8U)
+#define RTC_TR_MNU_Msk                       (0xFU << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
+#define RTC_TR_MNU                           RTC_TR_MNU_Msk
+#define RTC_TR_MNU_0                         (0x1U << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
+#define RTC_TR_MNU_1                         (0x2U << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
+#define RTC_TR_MNU_2                         (0x4U << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
+#define RTC_TR_MNU_3                         (0x8U << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                        (4U)
+#define RTC_TR_ST_Msk                        (0x7U << RTC_TR_ST_Pos)           /*!< 0x00000070 */
+#define RTC_TR_ST                            RTC_TR_ST_Msk
+#define RTC_TR_ST_0                          (0x1U << RTC_TR_ST_Pos)           /*!< 0x00000010 */
+#define RTC_TR_ST_1                          (0x2U << RTC_TR_ST_Pos)           /*!< 0x00000020 */
+#define RTC_TR_ST_2                          (0x4U << RTC_TR_ST_Pos)           /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                        (0U)
+#define RTC_TR_SU_Msk                        (0xFU << RTC_TR_SU_Pos)           /*!< 0x0000000F */
+#define RTC_TR_SU                            RTC_TR_SU_Msk
+#define RTC_TR_SU_0                          (0x1U << RTC_TR_SU_Pos)           /*!< 0x00000001 */
+#define RTC_TR_SU_1                          (0x2U << RTC_TR_SU_Pos)           /*!< 0x00000002 */
+#define RTC_TR_SU_2                          (0x4U << RTC_TR_SU_Pos)           /*!< 0x00000004 */
+#define RTC_TR_SU_3                          (0x8U << RTC_TR_SU_Pos)           /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                        (20U)
+#define RTC_DR_YT_Msk                        (0xFU << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
+#define RTC_DR_YT                            RTC_DR_YT_Msk
+#define RTC_DR_YT_0                          (0x1U << RTC_DR_YT_Pos)           /*!< 0x00100000 */
+#define RTC_DR_YT_1                          (0x2U << RTC_DR_YT_Pos)           /*!< 0x00200000 */
+#define RTC_DR_YT_2                          (0x4U << RTC_DR_YT_Pos)           /*!< 0x00400000 */
+#define RTC_DR_YT_3                          (0x8U << RTC_DR_YT_Pos)           /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                        (16U)
+#define RTC_DR_YU_Msk                        (0xFU << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
+#define RTC_DR_YU                            RTC_DR_YU_Msk
+#define RTC_DR_YU_0                          (0x1U << RTC_DR_YU_Pos)           /*!< 0x00010000 */
+#define RTC_DR_YU_1                          (0x2U << RTC_DR_YU_Pos)           /*!< 0x00020000 */
+#define RTC_DR_YU_2                          (0x4U << RTC_DR_YU_Pos)           /*!< 0x00040000 */
+#define RTC_DR_YU_3                          (0x8U << RTC_DR_YU_Pos)           /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                       (13U)
+#define RTC_DR_WDU_Msk                       (0x7U << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
+#define RTC_DR_WDU                           RTC_DR_WDU_Msk
+#define RTC_DR_WDU_0                         (0x1U << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
+#define RTC_DR_WDU_1                         (0x2U << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
+#define RTC_DR_WDU_2                         (0x4U << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                        (12U)
+#define RTC_DR_MT_Msk                        (0x1U << RTC_DR_MT_Pos)           /*!< 0x00001000 */
+#define RTC_DR_MT                            RTC_DR_MT_Msk
+#define RTC_DR_MU_Pos                        (8U)
+#define RTC_DR_MU_Msk                        (0xFU << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
+#define RTC_DR_MU                            RTC_DR_MU_Msk
+#define RTC_DR_MU_0                          (0x1U << RTC_DR_MU_Pos)           /*!< 0x00000100 */
+#define RTC_DR_MU_1                          (0x2U << RTC_DR_MU_Pos)           /*!< 0x00000200 */
+#define RTC_DR_MU_2                          (0x4U << RTC_DR_MU_Pos)           /*!< 0x00000400 */
+#define RTC_DR_MU_3                          (0x8U << RTC_DR_MU_Pos)           /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                        (4U)
+#define RTC_DR_DT_Msk                        (0x3U << RTC_DR_DT_Pos)           /*!< 0x00000030 */
+#define RTC_DR_DT                            RTC_DR_DT_Msk
+#define RTC_DR_DT_0                          (0x1U << RTC_DR_DT_Pos)           /*!< 0x00000010 */
+#define RTC_DR_DT_1                          (0x2U << RTC_DR_DT_Pos)           /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                        (0U)
+#define RTC_DR_DU_Msk                        (0xFU << RTC_DR_DU_Pos)           /*!< 0x0000000F */
+#define RTC_DR_DU                            RTC_DR_DU_Msk
+#define RTC_DR_DU_0                          (0x1U << RTC_DR_DU_Pos)           /*!< 0x00000001 */
+#define RTC_DR_DU_1                          (0x2U << RTC_DR_DU_Pos)           /*!< 0x00000002 */
+#define RTC_DR_DU_2                          (0x4U << RTC_DR_DU_Pos)           /*!< 0x00000004 */
+#define RTC_DR_DU_3                          (0x8U << RTC_DR_DU_Pos)           /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE_Pos                       (23U)
+#define RTC_CR_COE_Msk                       (0x1U << RTC_CR_COE_Pos)          /*!< 0x00800000 */
+#define RTC_CR_COE                           RTC_CR_COE_Msk
+#define RTC_CR_OSEL_Pos                      (21U)
+#define RTC_CR_OSEL_Msk                      (0x3U << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
+#define RTC_CR_OSEL                          RTC_CR_OSEL_Msk
+#define RTC_CR_OSEL_0                        (0x1U << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                        (0x2U << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                       (20U)
+#define RTC_CR_POL_Msk                       (0x1U << RTC_CR_POL_Pos)          /*!< 0x00100000 */
+#define RTC_CR_POL                           RTC_CR_POL_Msk
+#define RTC_CR_COSEL_Pos                     (19U)
+#define RTC_CR_COSEL_Msk                     (0x1U << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
+#define RTC_CR_COSEL                         RTC_CR_COSEL_Msk
+#define RTC_CR_BKP_Pos                       (18U)
+#define RTC_CR_BKP_Msk                       (0x1U << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
+#define RTC_CR_BKP                           RTC_CR_BKP_Msk
+#define RTC_CR_SUB1H_Pos                     (17U)
+#define RTC_CR_SUB1H_Msk                     (0x1U << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
+#define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk
+#define RTC_CR_ADD1H_Pos                     (16U)
+#define RTC_CR_ADD1H_Msk                     (0x1U << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
+#define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk
+#define RTC_CR_TSIE_Pos                      (15U)
+#define RTC_CR_TSIE_Msk                      (0x1U << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
+#define RTC_CR_TSIE                          RTC_CR_TSIE_Msk
+#define RTC_CR_WUTIE_Pos                     (14U)
+#define RTC_CR_WUTIE_Msk                     (0x1U << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
+#define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk
+#define RTC_CR_ALRBIE_Pos                    (13U)
+#define RTC_CR_ALRBIE_Msk                    (0x1U << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk
+#define RTC_CR_ALRAIE_Pos                    (12U)
+#define RTC_CR_ALRAIE_Msk                    (0x1U << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk
+#define RTC_CR_TSE_Pos                       (11U)
+#define RTC_CR_TSE_Msk                       (0x1U << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
+#define RTC_CR_TSE                           RTC_CR_TSE_Msk
+#define RTC_CR_WUTE_Pos                      (10U)
+#define RTC_CR_WUTE_Msk                      (0x1U << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
+#define RTC_CR_WUTE                          RTC_CR_WUTE_Msk
+#define RTC_CR_ALRBE_Pos                     (9U)
+#define RTC_CR_ALRBE_Msk                     (0x1U << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
+#define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk
+#define RTC_CR_ALRAE_Pos                     (8U)
+#define RTC_CR_ALRAE_Msk                     (0x1U << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
+#define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk
+#define RTC_CR_DCE_Pos                       (7U)
+#define RTC_CR_DCE_Msk                       (0x1U << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
+#define RTC_CR_DCE                           RTC_CR_DCE_Msk
+#define RTC_CR_FMT_Pos                       (6U)
+#define RTC_CR_FMT_Msk                       (0x1U << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
+#define RTC_CR_FMT                           RTC_CR_FMT_Msk
+#define RTC_CR_BYPSHAD_Pos                   (5U)
+#define RTC_CR_BYPSHAD_Msk                   (0x1U << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk
+#define RTC_CR_REFCKON_Pos                   (4U)
+#define RTC_CR_REFCKON_Msk                   (0x1U << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
+#define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk
+#define RTC_CR_TSEDGE_Pos                    (3U)
+#define RTC_CR_TSEDGE_Msk                    (0x1U << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk
+#define RTC_CR_WUCKSEL_Pos                   (0U)
+#define RTC_CR_WUCKSEL_Msk                   (0x7U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk
+#define RTC_CR_WUCKSEL_0                     (0x1U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1                     (0x2U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2                     (0x4U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
+
+/* Legacy defines */
+#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
+#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
+#define  RTC_CR_BCK     RTC_CR_BKP
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF_Pos                  (16U)
+#define RTC_ISR_RECALPF_Msk                  (0x1U << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
+#define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk
+#define RTC_ISR_TAMP3F_Pos                   (15U)
+#define RTC_ISR_TAMP3F_Msk                   (0x1U << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
+#define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk
+#define RTC_ISR_TAMP2F_Pos                   (14U)
+#define RTC_ISR_TAMP2F_Msk                   (0x1U << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk
+#define RTC_ISR_TAMP1F_Pos                   (13U)
+#define RTC_ISR_TAMP1F_Msk                   (0x1U << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk
+#define RTC_ISR_TSOVF_Pos                    (12U)
+#define RTC_ISR_TSOVF_Msk                    (0x1U << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk
+#define RTC_ISR_TSF_Pos                      (11U)
+#define RTC_ISR_TSF_Msk                      (0x1U << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
+#define RTC_ISR_TSF                          RTC_ISR_TSF_Msk
+#define RTC_ISR_WUTF_Pos                     (10U)
+#define RTC_ISR_WUTF_Msk                     (0x1U << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
+#define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk
+#define RTC_ISR_ALRBF_Pos                    (9U)
+#define RTC_ISR_ALRBF_Msk                    (0x1U << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk
+#define RTC_ISR_ALRAF_Pos                    (8U)
+#define RTC_ISR_ALRAF_Msk                    (0x1U << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk
+#define RTC_ISR_INIT_Pos                     (7U)
+#define RTC_ISR_INIT_Msk                     (0x1U << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
+#define RTC_ISR_INIT                         RTC_ISR_INIT_Msk
+#define RTC_ISR_INITF_Pos                    (6U)
+#define RTC_ISR_INITF_Msk                    (0x1U << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
+#define RTC_ISR_INITF                        RTC_ISR_INITF_Msk
+#define RTC_ISR_RSF_Pos                      (5U)
+#define RTC_ISR_RSF_Msk                      (0x1U << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
+#define RTC_ISR_RSF                          RTC_ISR_RSF_Msk
+#define RTC_ISR_INITS_Pos                    (4U)
+#define RTC_ISR_INITS_Msk                    (0x1U << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
+#define RTC_ISR_INITS                        RTC_ISR_INITS_Msk
+#define RTC_ISR_SHPF_Pos                     (3U)
+#define RTC_ISR_SHPF_Msk                     (0x1U << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
+#define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk
+#define RTC_ISR_WUTWF_Pos                    (2U)
+#define RTC_ISR_WUTWF_Msk                    (0x1U << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk
+#define RTC_ISR_ALRBWF_Pos                   (1U)
+#define RTC_ISR_ALRBWF_Msk                   (0x1U << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk
+#define RTC_ISR_ALRAWF_Pos                   (0U)
+#define RTC_ISR_ALRAWF_Msk                   (0x1U << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos                (16U)
+#define RTC_PRER_PREDIV_A_Msk                (0x7FU << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk
+#define RTC_PRER_PREDIV_S_Pos                (0U)
+#define RTC_PRER_PREDIV_S_Msk                (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos                     (0U)
+#define RTC_WUTR_WUT_Msk                     (0xFFFFU << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk
+
+/********************  Bits definition for RTC_CALIBR register  ***************/
+#define RTC_CALIBR_DCS_Pos                   (7U)
+#define RTC_CALIBR_DCS_Msk                   (0x1U << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
+#define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk
+#define RTC_CALIBR_DC_Pos                    (0U)
+#define RTC_CALIBR_DC_Msk                    (0x1FU << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
+#define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos                  (31U)
+#define RTC_ALRMAR_MSK4_Msk                  (0x1U << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk
+#define RTC_ALRMAR_WDSEL_Pos                 (30U)
+#define RTC_ALRMAR_WDSEL_Msk                 (0x1U << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk
+#define RTC_ALRMAR_DT_Pos                    (28U)
+#define RTC_ALRMAR_DT_Msk                    (0x3U << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk
+#define RTC_ALRMAR_DT_0                      (0x1U << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1                      (0x2U << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos                    (24U)
+#define RTC_ALRMAR_DU_Msk                    (0xFU << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk
+#define RTC_ALRMAR_DU_0                      (0x1U << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1                      (0x2U << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2                      (0x4U << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3                      (0x8U << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos                  (23U)
+#define RTC_ALRMAR_MSK3_Msk                  (0x1U << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk
+#define RTC_ALRMAR_PM_Pos                    (22U)
+#define RTC_ALRMAR_PM_Msk                    (0x1U << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk
+#define RTC_ALRMAR_HT_Pos                    (20U)
+#define RTC_ALRMAR_HT_Msk                    (0x3U << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk
+#define RTC_ALRMAR_HT_0                      (0x1U << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1                      (0x2U << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos                    (16U)
+#define RTC_ALRMAR_HU_Msk                    (0xFU << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk
+#define RTC_ALRMAR_HU_0                      (0x1U << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1                      (0x2U << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2                      (0x4U << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3                      (0x8U << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos                  (15U)
+#define RTC_ALRMAR_MSK2_Msk                  (0x1U << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk
+#define RTC_ALRMAR_MNT_Pos                   (12U)
+#define RTC_ALRMAR_MNT_Msk                   (0x7U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk
+#define RTC_ALRMAR_MNT_0                     (0x1U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1                     (0x2U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2                     (0x4U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos                   (8U)
+#define RTC_ALRMAR_MNU_Msk                   (0xFU << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk
+#define RTC_ALRMAR_MNU_0                     (0x1U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1                     (0x2U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2                     (0x4U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3                     (0x8U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos                  (7U)
+#define RTC_ALRMAR_MSK1_Msk                  (0x1U << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk
+#define RTC_ALRMAR_ST_Pos                    (4U)
+#define RTC_ALRMAR_ST_Msk                    (0x7U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk
+#define RTC_ALRMAR_ST_0                      (0x1U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1                      (0x2U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2                      (0x4U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos                    (0U)
+#define RTC_ALRMAR_SU_Msk                    (0xFU << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk
+#define RTC_ALRMAR_SU_0                      (0x1U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1                      (0x2U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2                      (0x4U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3                      (0x8U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos                  (31U)
+#define RTC_ALRMBR_MSK4_Msk                  (0x1U << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk
+#define RTC_ALRMBR_WDSEL_Pos                 (30U)
+#define RTC_ALRMBR_WDSEL_Msk                 (0x1U << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk
+#define RTC_ALRMBR_DT_Pos                    (28U)
+#define RTC_ALRMBR_DT_Msk                    (0x3U << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk
+#define RTC_ALRMBR_DT_0                      (0x1U << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1                      (0x2U << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos                    (24U)
+#define RTC_ALRMBR_DU_Msk                    (0xFU << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk
+#define RTC_ALRMBR_DU_0                      (0x1U << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1                      (0x2U << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2                      (0x4U << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3                      (0x8U << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos                  (23U)
+#define RTC_ALRMBR_MSK3_Msk                  (0x1U << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk
+#define RTC_ALRMBR_PM_Pos                    (22U)
+#define RTC_ALRMBR_PM_Msk                    (0x1U << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk
+#define RTC_ALRMBR_HT_Pos                    (20U)
+#define RTC_ALRMBR_HT_Msk                    (0x3U << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk
+#define RTC_ALRMBR_HT_0                      (0x1U << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1                      (0x2U << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos                    (16U)
+#define RTC_ALRMBR_HU_Msk                    (0xFU << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk
+#define RTC_ALRMBR_HU_0                      (0x1U << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1                      (0x2U << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2                      (0x4U << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3                      (0x8U << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos                  (15U)
+#define RTC_ALRMBR_MSK2_Msk                  (0x1U << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk
+#define RTC_ALRMBR_MNT_Pos                   (12U)
+#define RTC_ALRMBR_MNT_Msk                   (0x7U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk
+#define RTC_ALRMBR_MNT_0                     (0x1U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1                     (0x2U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2                     (0x4U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos                   (8U)
+#define RTC_ALRMBR_MNU_Msk                   (0xFU << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk
+#define RTC_ALRMBR_MNU_0                     (0x1U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1                     (0x2U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2                     (0x4U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3                     (0x8U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos                  (7U)
+#define RTC_ALRMBR_MSK1_Msk                  (0x1U << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk
+#define RTC_ALRMBR_ST_Pos                    (4U)
+#define RTC_ALRMBR_ST_Msk                    (0x7U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk
+#define RTC_ALRMBR_ST_0                      (0x1U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1                      (0x2U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2                      (0x4U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos                    (0U)
+#define RTC_ALRMBR_SU_Msk                    (0xFU << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk
+#define RTC_ALRMBR_SU_0                      (0x1U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1                      (0x2U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2                      (0x4U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3                      (0x8U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos                      (0U)
+#define RTC_WPR_KEY_Msk                      (0xFFU << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
+#define RTC_WPR_KEY                          RTC_WPR_KEY_Msk
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                       (0U)
+#define RTC_SSR_SS_Msk                       (0xFFFFU << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
+#define RTC_SSR_SS                           RTC_SSR_SS_Msk
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos                 (0U)
+#define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk
+#define RTC_SHIFTR_ADD1S_Pos                 (31U)
+#define RTC_SHIFTR_ADD1S_Msk                 (0x1U << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos                      (22U)
+#define RTC_TSTR_PM_Msk                      (0x1U << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
+#define RTC_TSTR_PM                          RTC_TSTR_PM_Msk
+#define RTC_TSTR_HT_Pos                      (20U)
+#define RTC_TSTR_HT_Msk                      (0x3U << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
+#define RTC_TSTR_HT                          RTC_TSTR_HT_Msk
+#define RTC_TSTR_HT_0                        (0x1U << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                        (0x2U << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos                      (16U)
+#define RTC_TSTR_HU_Msk                      (0xFU << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
+#define RTC_TSTR_HU                          RTC_TSTR_HU_Msk
+#define RTC_TSTR_HU_0                        (0x1U << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                        (0x2U << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                        (0x4U << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                        (0x8U << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos                     (12U)
+#define RTC_TSTR_MNT_Msk                     (0x7U << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
+#define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk
+#define RTC_TSTR_MNT_0                       (0x1U << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                       (0x2U << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                       (0x4U << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos                     (8U)
+#define RTC_TSTR_MNU_Msk                     (0xFU << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk
+#define RTC_TSTR_MNU_0                       (0x1U << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                       (0x2U << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                       (0x4U << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                       (0x8U << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos                      (4U)
+#define RTC_TSTR_ST_Msk                      (0x7U << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
+#define RTC_TSTR_ST                          RTC_TSTR_ST_Msk
+#define RTC_TSTR_ST_0                        (0x1U << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                        (0x2U << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                        (0x4U << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos                      (0U)
+#define RTC_TSTR_SU_Msk                      (0xFU << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
+#define RTC_TSTR_SU                          RTC_TSTR_SU_Msk
+#define RTC_TSTR_SU_0                        (0x1U << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                        (0x2U << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                        (0x4U << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                        (0x8U << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos                     (13U)
+#define RTC_TSDR_WDU_Msk                     (0x7U << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk
+#define RTC_TSDR_WDU_0                       (0x1U << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                       (0x2U << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                       (0x4U << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos                      (12U)
+#define RTC_TSDR_MT_Msk                      (0x1U << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
+#define RTC_TSDR_MT                          RTC_TSDR_MT_Msk
+#define RTC_TSDR_MU_Pos                      (8U)
+#define RTC_TSDR_MU_Msk                      (0xFU << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
+#define RTC_TSDR_MU                          RTC_TSDR_MU_Msk
+#define RTC_TSDR_MU_0                        (0x1U << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                        (0x2U << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                        (0x4U << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                        (0x8U << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos                      (4U)
+#define RTC_TSDR_DT_Msk                      (0x3U << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
+#define RTC_TSDR_DT                          RTC_TSDR_DT_Msk
+#define RTC_TSDR_DT_0                        (0x1U << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                        (0x2U << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos                      (0U)
+#define RTC_TSDR_DU_Msk                      (0xFU << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
+#define RTC_TSDR_DU                          RTC_TSDR_DU_Msk
+#define RTC_TSDR_DU_0                        (0x1U << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                        (0x2U << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                        (0x4U << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                        (0x8U << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos                     (0U)
+#define RTC_TSSSR_SS_Msk                     (0xFFFFU << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos                    (15U)
+#define RTC_CALR_CALP_Msk                    (0x1U << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
+#define RTC_CALR_CALP                        RTC_CALR_CALP_Msk
+#define RTC_CALR_CALW8_Pos                   (14U)
+#define RTC_CALR_CALW8_Msk                   (0x1U << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
+#define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk
+#define RTC_CALR_CALW16_Pos                  (13U)
+#define RTC_CALR_CALW16_Msk                  (0x1U << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
+#define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk
+#define RTC_CALR_CALM_Pos                    (0U)
+#define RTC_CALR_CALM_Msk                    (0x1FFU << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
+#define RTC_CALR_CALM                        RTC_CALR_CALM_Msk
+#define RTC_CALR_CALM_0                      (0x001U << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
+#define RTC_CALR_CALM_1                      (0x002U << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
+#define RTC_CALR_CALM_2                      (0x004U << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
+#define RTC_CALR_CALM_3                      (0x008U << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
+#define RTC_CALR_CALM_4                      (0x010U << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
+#define RTC_CALR_CALM_5                      (0x020U << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
+#define RTC_CALR_CALM_6                      (0x040U << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
+#define RTC_CALR_CALM_7                      (0x080U << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
+#define RTC_CALR_CALM_8                      (0x100U << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)
+#define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk
+#define RTC_TAFCR_TAMPPUDIS_Pos              (15U)
+#define RTC_TAFCR_TAMPPUDIS_Msk              (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk
+#define RTC_TAFCR_TAMPPRCH_Pos               (13U)
+#define RTC_TAFCR_TAMPPRCH_Msk               (0x3U << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk
+#define RTC_TAFCR_TAMPPRCH_0                 (0x1U << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1                 (0x2U << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos                (11U)
+#define RTC_TAFCR_TAMPFLT_Msk                (0x3U << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk
+#define RTC_TAFCR_TAMPFLT_0                  (0x1U << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1                  (0x2U << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos               (8U)
+#define RTC_TAFCR_TAMPFREQ_Msk               (0x7U << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk
+#define RTC_TAFCR_TAMPFREQ_0                 (0x1U << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1                 (0x2U << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2                 (0x4U << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos                 (7U)
+#define RTC_TAFCR_TAMPTS_Msk                 (0x1U << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk
+#define RTC_TAFCR_TAMP3TRG_Pos               (6U)
+#define RTC_TAFCR_TAMP3TRG_Msk               (0x1U << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
+#define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk
+#define RTC_TAFCR_TAMP3E_Pos                 (5U)
+#define RTC_TAFCR_TAMP3E_Msk                 (0x1U << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
+#define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk
+#define RTC_TAFCR_TAMP2TRG_Pos               (4U)
+#define RTC_TAFCR_TAMP2TRG_Msk               (0x1U << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk
+#define RTC_TAFCR_TAMP2E_Pos                 (3U)
+#define RTC_TAFCR_TAMP2E_Msk                 (0x1U << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk
+#define RTC_TAFCR_TAMPIE_Pos                 (2U)
+#define RTC_TAFCR_TAMPIE_Msk                 (0x1U << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk
+#define RTC_TAFCR_TAMP1TRG_Pos               (1U)
+#define RTC_TAFCR_TAMP1TRG_Msk               (0x1U << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk
+#define RTC_TAFCR_TAMP1E_Pos                 (0U)
+#define RTC_TAFCR_TAMP1E_Msk                 (0x1U << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos              (24U)
+#define RTC_ALRMASSR_MASKSS_Msk              (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk
+#define RTC_ALRMASSR_MASKSS_0                (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1                (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2                (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3                (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos                  (0U)
+#define RTC_ALRMASSR_SS_Msk                  (0x7FFFU << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos              (24U)
+#define RTC_ALRMBSSR_MASKSS_Msk              (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk
+#define RTC_ALRMBSSR_MASKSS_0                (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1                (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2                (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3                (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos                  (0U)
+#define RTC_ALRMBSSR_SS_Msk                  (0x7FFFU << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                        (0U)
+#define RTC_BKP0R_Msk                        (0xFFFFFFFFU << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                            RTC_BKP0R_Msk
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                        (0U)
+#define RTC_BKP1R_Msk                        (0xFFFFFFFFU << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                            RTC_BKP1R_Msk
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                        (0U)
+#define RTC_BKP2R_Msk                        (0xFFFFFFFFU << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                            RTC_BKP2R_Msk
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                        (0U)
+#define RTC_BKP3R_Msk                        (0xFFFFFFFFU << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                            RTC_BKP3R_Msk
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                        (0U)
+#define RTC_BKP4R_Msk                        (0xFFFFFFFFU << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                            RTC_BKP4R_Msk
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER 5
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Serial Peripheral Interface (SPI)                      */
+/*                                                                            */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
+ */
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos                    (0U)
+#define SPI_CR1_CPHA_Msk                    (0x1U << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
+#define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
+#define SPI_CR1_CPOL_Pos                    (1U)
+#define SPI_CR1_CPOL_Msk                    (0x1U << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
+#define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
+#define SPI_CR1_MSTR_Pos                    (2U)
+#define SPI_CR1_MSTR_Msk                    (0x1U << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
+#define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
+
+#define SPI_CR1_BR_Pos                      (3U)
+#define SPI_CR1_BR_Msk                      (0x7U << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
+#define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0                        (0x1U << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
+#define SPI_CR1_BR_1                        (0x2U << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
+#define SPI_CR1_BR_2                        (0x4U << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos                     (6U)
+#define SPI_CR1_SPE_Msk                     (0x1U << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
+#define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST_Pos                (7U)
+#define SPI_CR1_LSBFIRST_Msk                (0x1U << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
+#define SPI_CR1_SSI_Pos                     (8U)
+#define SPI_CR1_SSI_Msk                     (0x1U << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
+#define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
+#define SPI_CR1_SSM_Pos                     (9U)
+#define SPI_CR1_SSM_Msk                     (0x1U << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
+#define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
+#define SPI_CR1_RXONLY_Pos                  (10U)
+#define SPI_CR1_RXONLY_Msk                  (0x1U << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
+#define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
+#define SPI_CR1_DFF_Pos                     (11U)
+#define SPI_CR1_DFF_Msk                     (0x1U << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
+#define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT_Pos                 (12U)
+#define SPI_CR1_CRCNEXT_Msk                 (0x1U << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN_Pos                   (13U)
+#define SPI_CR1_CRCEN_Msk                   (0x1U << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
+#define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE_Pos                  (14U)
+#define SPI_CR1_BIDIOE_Msk                  (0x1U << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos                (15U)
+#define SPI_CR1_BIDIMODE_Msk                (0x1U << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos                 (0U)
+#define SPI_CR2_RXDMAEN_Msk                 (0x1U << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN_Pos                 (1U)
+#define SPI_CR2_TXDMAEN_Msk                 (0x1U << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE_Pos                    (2U)
+#define SPI_CR2_SSOE_Msk                    (0x1U << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
+#define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
+#define SPI_CR2_ERRIE_Pos                   (5U)
+#define SPI_CR2_ERRIE_Msk                   (0x1U << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
+#define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE_Pos                  (6U)
+#define SPI_CR2_RXNEIE_Msk                  (0x1U << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos                   (7U)
+#define SPI_CR2_TXEIE_Msk                   (0x1U << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
+#define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos                     (0U)
+#define SPI_SR_RXNE_Msk                     (0x1U << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
+#define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos                      (1U)
+#define SPI_SR_TXE_Msk                      (0x1U << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
+#define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE_Pos                   (2U)
+#define SPI_SR_CHSIDE_Msk                   (0x1U << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
+#define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
+#define SPI_SR_UDR_Pos                      (3U)
+#define SPI_SR_UDR_Msk                      (0x1U << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
+#define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
+#define SPI_SR_CRCERR_Pos                   (4U)
+#define SPI_SR_CRCERR_Msk                   (0x1U << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
+#define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
+#define SPI_SR_MODF_Pos                     (5U)
+#define SPI_SR_MODF_Msk                     (0x1U << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
+#define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
+#define SPI_SR_OVR_Pos                      (6U)
+#define SPI_SR_OVR_Msk                      (0x1U << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
+#define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
+#define SPI_SR_BSY_Pos                      (7U)
+#define SPI_SR_BSY_Msk                      (0x1U << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
+#define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
+#define SPI_SR_FRE_Pos                      (8U)
+#define SPI_SR_FRE_Msk                      (0x1U << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
+#define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos                       (0U)
+#define SPI_DR_DR_Msk                       (0xFFFFU << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
+#define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos               (0U)
+#define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos                (0U)
+#define SPI_RXCRCR_RXCRC_Msk                (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos                (0U)
+#define SPI_TXCRCR_TXCRC_Msk                (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       System Configuration (SYSCFG)                        */
+/*                                                                            */
+/******************************************************************************/
+/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
+#define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0        (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1        (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
+#define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)
+#define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3U << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
+#define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
+#define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1U << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
+#define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2U << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
+
+/*****************  Bit definition for SYSCFG_PMC register  *******************/
+#define SYSCFG_PMC_USB_PU_Pos           (0U)
+#define SYSCFG_PMC_USB_PU_Msk           (0x1U << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
+#define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFU << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFU << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFU << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFU << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
+
+/**
+  * @brief  EXTI0 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
+
+/**
+  * @brief  EXTI1 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
+
+/**
+  * @brief  EXTI2 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
+
+/**
+  * @brief  EXTI3 configuration
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF         (0x00003000U)                          /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG         (0x00004000U)                          /*!< PG[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFU << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFU << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFU << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFU << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
+
+/**
+  * @brief  EXTI4 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
+
+/**
+  * @brief  EXTI5 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
+
+/**
+  * @brief  EXTI6 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
+
+/**
+  * @brief  EXTI7 configuration
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFU << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFU << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFU << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFU << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
+
+/**
+  * @brief  EXTI8 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
+
+/**
+  * @brief  EXTI9 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
+
+/**
+  * @brief  EXTI10 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
+
+/**
+  * @brief  EXTI11 configuration
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFU << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFU << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFU << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFU << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
+
+/**
+  * @brief  EXTI12 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
+
+/**
+  * @brief  EXTI13 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
+
+/**
+  * @brief  EXTI14 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
+
+/**
+  * @brief  EXTI15 configuration
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
+
+/******************************************************************************/
+/*                                                                            */
+/*                       Routing Interface (RI)                               */
+/*                                                                            */
+/******************************************************************************/
+
+/********************  Bit definition for RI_ICR register  ********************/
+#define RI_ICR_IC1OS_Pos                (0U)
+#define RI_ICR_IC1OS_Msk                (0xFU << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
+#define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
+#define RI_ICR_IC1OS_0                  (0x1U << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
+#define RI_ICR_IC1OS_1                  (0x2U << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
+#define RI_ICR_IC1OS_2                  (0x4U << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
+#define RI_ICR_IC1OS_3                  (0x8U << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
+
+#define RI_ICR_IC2OS_Pos                (4U)
+#define RI_ICR_IC2OS_Msk                (0xFU << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
+#define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
+#define RI_ICR_IC2OS_0                  (0x1U << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
+#define RI_ICR_IC2OS_1                  (0x2U << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
+#define RI_ICR_IC2OS_2                  (0x4U << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
+#define RI_ICR_IC2OS_3                  (0x8U << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
+
+#define RI_ICR_IC3OS_Pos                (8U)
+#define RI_ICR_IC3OS_Msk                (0xFU << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
+#define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
+#define RI_ICR_IC3OS_0                  (0x1U << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
+#define RI_ICR_IC3OS_1                  (0x2U << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
+#define RI_ICR_IC3OS_2                  (0x4U << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
+#define RI_ICR_IC3OS_3                  (0x8U << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
+
+#define RI_ICR_IC4OS_Pos                (12U)
+#define RI_ICR_IC4OS_Msk                (0xFU << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
+#define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
+#define RI_ICR_IC4OS_0                  (0x1U << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
+#define RI_ICR_IC4OS_1                  (0x2U << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
+#define RI_ICR_IC4OS_2                  (0x4U << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
+#define RI_ICR_IC4OS_3                  (0x8U << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
+
+#define RI_ICR_TIM_Pos                  (16U)
+#define RI_ICR_TIM_Msk                  (0x3U << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
+#define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
+#define RI_ICR_TIM_0                    (0x1U << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
+#define RI_ICR_TIM_1                    (0x2U << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
+
+#define RI_ICR_IC1_Pos                  (18U)
+#define RI_ICR_IC1_Msk                  (0x1U << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
+#define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
+#define RI_ICR_IC2_Pos                  (19U)
+#define RI_ICR_IC2_Msk                  (0x1U << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
+#define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
+#define RI_ICR_IC3_Pos                  (20U)
+#define RI_ICR_IC3_Msk                  (0x1U << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
+#define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
+#define RI_ICR_IC4_Pos                  (21U)
+#define RI_ICR_IC4_Msk                  (0x1U << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
+#define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
+
+/********************  Bit definition for RI_ASCR1 register  ********************/
+#define RI_ASCR1_CH_Pos                 (0U)
+#define RI_ASCR1_CH_Msk                 (0x3FCFFFFU << RI_ASCR1_CH_Pos)        /*!< 0x03FCFFFF */
+#define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
+#define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
+#define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
+#define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
+#define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
+#define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
+#define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
+#define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
+#define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
+#define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
+#define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
+#define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
+#define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
+#define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
+#define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
+#define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
+#define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
+#define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
+#define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
+#define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
+#define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
+#define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
+#define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
+#define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
+#define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
+#define RI_ASCR1_VCOMP_Pos              (26U)
+#define RI_ASCR1_VCOMP_Msk              (0x1U << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
+#define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
+#define RI_ASCR1_SCM_Pos                (31U)
+#define RI_ASCR1_SCM_Msk                (0x1U << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
+#define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
+
+/********************  Bit definition for RI_ASCR2 register  ********************/
+#define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
+#define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
+#define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
+#define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
+#define RI_ASCR2_GR6_Pos                (4U)
+#define RI_ASCR2_GR6_Msk                (0x3U << RI_ASCR2_GR6_Pos)             /*!< 0x00000030 */
+#define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
+#define RI_ASCR2_GR6_1                  (0x1U << RI_ASCR2_GR6_Pos)             /*!< 0x00000010 */
+#define RI_ASCR2_GR6_2                  (0x2U << RI_ASCR2_GR6_Pos)             /*!< 0x00000020 */
+#define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
+#define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
+#define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
+#define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
+#define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
+#define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
+#define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
+
+/********************  Bit definition for RI_HYSCR1 register  ********************/
+#define RI_HYSCR1_PA_Pos                (0U)
+#define RI_HYSCR1_PA_Msk                (0xFFFFU << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
+#define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
+#define RI_HYSCR1_PA_0                  (0x0001U << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
+#define RI_HYSCR1_PA_1                  (0x0002U << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
+#define RI_HYSCR1_PA_2                  (0x0004U << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
+#define RI_HYSCR1_PA_3                  (0x0008U << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
+#define RI_HYSCR1_PA_4                  (0x0010U << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
+#define RI_HYSCR1_PA_5                  (0x0020U << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
+#define RI_HYSCR1_PA_6                  (0x0040U << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
+#define RI_HYSCR1_PA_7                  (0x0080U << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
+#define RI_HYSCR1_PA_8                  (0x0100U << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
+#define RI_HYSCR1_PA_9                  (0x0200U << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
+#define RI_HYSCR1_PA_10                 (0x0400U << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
+#define RI_HYSCR1_PA_11                 (0x0800U << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
+#define RI_HYSCR1_PA_12                 (0x1000U << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
+#define RI_HYSCR1_PA_13                 (0x2000U << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
+#define RI_HYSCR1_PA_14                 (0x4000U << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
+#define RI_HYSCR1_PA_15                 (0x8000U << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
+
+#define RI_HYSCR1_PB_Pos                (16U)
+#define RI_HYSCR1_PB_Msk                (0xFFFFU << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
+#define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
+#define RI_HYSCR1_PB_0                  (0x0001U << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
+#define RI_HYSCR1_PB_1                  (0x0002U << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
+#define RI_HYSCR1_PB_2                  (0x0004U << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
+#define RI_HYSCR1_PB_3                  (0x0008U << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
+#define RI_HYSCR1_PB_4                  (0x0010U << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
+#define RI_HYSCR1_PB_5                  (0x0020U << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
+#define RI_HYSCR1_PB_6                  (0x0040U << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
+#define RI_HYSCR1_PB_7                  (0x0080U << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
+#define RI_HYSCR1_PB_8                  (0x0100U << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
+#define RI_HYSCR1_PB_9                  (0x0200U << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
+#define RI_HYSCR1_PB_10                 (0x0400U << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
+#define RI_HYSCR1_PB_11                 (0x0800U << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
+#define RI_HYSCR1_PB_12                 (0x1000U << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
+#define RI_HYSCR1_PB_13                 (0x2000U << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
+#define RI_HYSCR1_PB_14                 (0x4000U << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
+#define RI_HYSCR1_PB_15                 (0x8000U << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
+
+/********************  Bit definition for RI_HYSCR2 register  ********************/
+#define RI_HYSCR2_PC_Pos                (0U)
+#define RI_HYSCR2_PC_Msk                (0xFFFFU << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
+#define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
+#define RI_HYSCR2_PC_0                  (0x0001U << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
+#define RI_HYSCR2_PC_1                  (0x0002U << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
+#define RI_HYSCR2_PC_2                  (0x0004U << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
+#define RI_HYSCR2_PC_3                  (0x0008U << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
+#define RI_HYSCR2_PC_4                  (0x0010U << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
+#define RI_HYSCR2_PC_5                  (0x0020U << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
+#define RI_HYSCR2_PC_6                  (0x0040U << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
+#define RI_HYSCR2_PC_7                  (0x0080U << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
+#define RI_HYSCR2_PC_8                  (0x0100U << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
+#define RI_HYSCR2_PC_9                  (0x0200U << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
+#define RI_HYSCR2_PC_10                 (0x0400U << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
+#define RI_HYSCR2_PC_11                 (0x0800U << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
+#define RI_HYSCR2_PC_12                 (0x1000U << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
+#define RI_HYSCR2_PC_13                 (0x2000U << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
+#define RI_HYSCR2_PC_14                 (0x4000U << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
+#define RI_HYSCR2_PC_15                 (0x8000U << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
+
+#define RI_HYSCR2_PD_Pos                (16U)
+#define RI_HYSCR2_PD_Msk                (0xFFFFU << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
+#define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
+#define RI_HYSCR2_PD_0                  (0x0001U << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
+#define RI_HYSCR2_PD_1                  (0x0002U << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
+#define RI_HYSCR2_PD_2                  (0x0004U << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
+#define RI_HYSCR2_PD_3                  (0x0008U << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
+#define RI_HYSCR2_PD_4                  (0x0010U << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
+#define RI_HYSCR2_PD_5                  (0x0020U << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
+#define RI_HYSCR2_PD_6                  (0x0040U << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
+#define RI_HYSCR2_PD_7                  (0x0080U << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
+#define RI_HYSCR2_PD_8                  (0x0100U << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
+#define RI_HYSCR2_PD_9                  (0x0200U << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
+#define RI_HYSCR2_PD_10                 (0x0400U << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
+#define RI_HYSCR2_PD_11                 (0x0800U << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
+#define RI_HYSCR2_PD_12                 (0x1000U << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
+#define RI_HYSCR2_PD_13                 (0x2000U << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
+#define RI_HYSCR2_PD_14                 (0x4000U << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
+#define RI_HYSCR2_PD_15                 (0x8000U << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
+
+/********************  Bit definition for RI_HYSCR3 register  ********************/
+#define RI_HYSCR3_PE_Pos                (0U)
+#define RI_HYSCR3_PE_Msk                (0xFFFFU << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
+#define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
+#define RI_HYSCR3_PE_0                  (0x0001U << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
+#define RI_HYSCR3_PE_1                  (0x0002U << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
+#define RI_HYSCR3_PE_2                  (0x0004U << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
+#define RI_HYSCR3_PE_3                  (0x0008U << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
+#define RI_HYSCR3_PE_4                  (0x0010U << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
+#define RI_HYSCR3_PE_5                  (0x0020U << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
+#define RI_HYSCR3_PE_6                  (0x0040U << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
+#define RI_HYSCR3_PE_7                  (0x0080U << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
+#define RI_HYSCR3_PE_8                  (0x0100U << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
+#define RI_HYSCR3_PE_9                  (0x0200U << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
+#define RI_HYSCR3_PE_10                 (0x0400U << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
+#define RI_HYSCR3_PE_11                 (0x0800U << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
+#define RI_HYSCR3_PE_12                 (0x1000U << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
+#define RI_HYSCR3_PE_13                 (0x2000U << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
+#define RI_HYSCR3_PE_14                 (0x4000U << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
+#define RI_HYSCR3_PE_15                 (0x8000U << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                               Timers (TIM)                                 */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos                     (0U)
+#define TIM_CR1_CEN_Msk                     (0x1U << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
+#define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
+#define TIM_CR1_UDIS_Pos                    (1U)
+#define TIM_CR1_UDIS_Msk                    (0x1U << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
+#define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
+#define TIM_CR1_URS_Pos                     (2U)
+#define TIM_CR1_URS_Msk                     (0x1U << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
+#define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
+#define TIM_CR1_OPM_Pos                     (3U)
+#define TIM_CR1_OPM_Msk                     (0x1U << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
+#define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
+#define TIM_CR1_DIR_Pos                     (4U)
+#define TIM_CR1_DIR_Msk                     (0x1U << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
+#define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
+
+#define TIM_CR1_CMS_Pos                     (5U)
+#define TIM_CR1_CMS_Msk                     (0x3U << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
+#define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0                       (0x1U << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
+#define TIM_CR1_CMS_1                       (0x2U << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
+
+#define TIM_CR1_ARPE_Pos                    (7U)
+#define TIM_CR1_ARPE_Msk                    (0x1U << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
+#define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD_Pos                     (8U)
+#define TIM_CR1_CKD_Msk                     (0x3U << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
+#define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0                       (0x1U << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
+#define TIM_CR1_CKD_1                       (0x2U << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCDS_Pos                    (3U)
+#define TIM_CR2_CCDS_Msk                    (0x1U << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
+#define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS_Pos                     (4U)
+#define TIM_CR2_MMS_Msk                     (0x7U << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
+#define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0                       (0x1U << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
+#define TIM_CR2_MMS_1                       (0x2U << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
+#define TIM_CR2_MMS_2                       (0x4U << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
+
+#define TIM_CR2_TI1S_Pos                    (7U)
+#define TIM_CR2_TI1S_Msk                    (0x1U << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
+#define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos                    (0U)
+#define TIM_SMCR_SMS_Msk                    (0x7U << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
+#define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0                      (0x1U << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
+#define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
+#define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
+
+#define TIM_SMCR_OCCS_Pos                   (3U)
+#define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
+#define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
+
+#define TIM_SMCR_TS_Pos                     (4U)
+#define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
+#define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0                       (0x1U << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
+#define TIM_SMCR_TS_1                       (0x2U << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
+#define TIM_SMCR_TS_2                       (0x4U << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
+
+#define TIM_SMCR_MSM_Pos                    (7U)
+#define TIM_SMCR_MSM_Msk                    (0x1U << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
+#define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF_Pos                    (8U)
+#define TIM_SMCR_ETF_Msk                    (0xFU << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
+#define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0                      (0x1U << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
+#define TIM_SMCR_ETF_1                      (0x2U << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
+#define TIM_SMCR_ETF_2                      (0x4U << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
+#define TIM_SMCR_ETF_3                      (0x8U << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
+
+#define TIM_SMCR_ETPS_Pos                   (12U)
+#define TIM_SMCR_ETPS_Msk                   (0x3U << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
+#define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0                     (0x1U << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
+#define TIM_SMCR_ETPS_1                     (0x2U << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
+
+#define TIM_SMCR_ECE_Pos                    (14U)
+#define TIM_SMCR_ECE_Msk                    (0x1U << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
+#define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
+#define TIM_SMCR_ETP_Pos                    (15U)
+#define TIM_SMCR_ETP_Msk                    (0x1U << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
+#define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos                    (0U)
+#define TIM_DIER_UIE_Msk                    (0x1U << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
+#define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos                  (1U)
+#define TIM_DIER_CC1IE_Msk                  (0x1U << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
+#define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE_Pos                  (2U)
+#define TIM_DIER_CC2IE_Msk                  (0x1U << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
+#define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE_Pos                  (3U)
+#define TIM_DIER_CC3IE_Msk                  (0x1U << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
+#define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE_Pos                  (4U)
+#define TIM_DIER_CC4IE_Msk                  (0x1U << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
+#define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE_Pos                    (6U)
+#define TIM_DIER_TIE_Msk                    (0x1U << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
+#define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE_Pos                    (8U)
+#define TIM_DIER_UDE_Msk                    (0x1U << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
+#define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE_Pos                  (9U)
+#define TIM_DIER_CC1DE_Msk                  (0x1U << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
+#define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos                  (10U)
+#define TIM_DIER_CC2DE_Msk                  (0x1U << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
+#define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos                  (11U)
+#define TIM_DIER_CC3DE_Msk                  (0x1U << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
+#define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos                  (12U)
+#define TIM_DIER_CC4DE_Msk                  (0x1U << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
+#define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
+#define TIM_DIER_TDE_Pos                    (14U)
+#define TIM_DIER_TDE_Msk                    (0x1U << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
+#define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos                      (0U)
+#define TIM_SR_UIF_Msk                      (0x1U << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
+#define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF_Pos                    (1U)
+#define TIM_SR_CC1IF_Msk                    (0x1U << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
+#define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF_Pos                    (2U)
+#define TIM_SR_CC2IF_Msk                    (0x1U << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
+#define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF_Pos                    (3U)
+#define TIM_SR_CC3IF_Msk                    (0x1U << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
+#define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF_Pos                    (4U)
+#define TIM_SR_CC4IF_Msk                    (0x1U << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
+#define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF_Pos                      (6U)
+#define TIM_SR_TIF_Msk                      (0x1U << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
+#define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF_Pos                    (9U)
+#define TIM_SR_CC1OF_Msk                    (0x1U << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
+#define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos                    (10U)
+#define TIM_SR_CC2OF_Msk                    (0x1U << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
+#define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos                    (11U)
+#define TIM_SR_CC3OF_Msk                    (0x1U << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
+#define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos                    (12U)
+#define TIM_SR_CC4OF_Msk                    (0x1U << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
+#define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos                      (0U)
+#define TIM_EGR_UG_Msk                      (0x1U << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
+#define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
+#define TIM_EGR_CC1G_Pos                    (1U)
+#define TIM_EGR_CC1G_Msk                    (0x1U << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
+#define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G_Pos                    (2U)
+#define TIM_EGR_CC2G_Msk                    (0x1U << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
+#define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G_Pos                    (3U)
+#define TIM_EGR_CC3G_Msk                    (0x1U << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
+#define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G_Pos                    (4U)
+#define TIM_EGR_CC4G_Msk                    (0x1U << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
+#define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG_Pos                      (6U)
+#define TIM_EGR_TG_Msk                      (0x1U << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
+#define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos                  (0U)
+#define TIM_CCMR1_CC1S_Msk                  (0x3U << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0                    (0x1U << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
+#define TIM_CCMR1_CC1S_1                    (0x2U << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
+
+#define TIM_CCMR1_OC1FE_Pos                 (2U)
+#define TIM_CCMR1_OC1FE_Msk                 (0x1U << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE_Pos                 (3U)
+#define TIM_CCMR1_OC1PE_Msk                 (0x1U << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M_Pos                  (4U)
+#define TIM_CCMR1_OC1M_Msk                  (0x7U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0                    (0x1U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
+#define TIM_CCMR1_OC1M_1                    (0x2U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
+#define TIM_CCMR1_OC1M_2                    (0x4U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
+
+#define TIM_CCMR1_OC1CE_Pos                 (7U)
+#define TIM_CCMR1_OC1CE_Msk                 (0x1U << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S_Pos                  (8U)
+#define TIM_CCMR1_CC2S_Msk                  (0x3U << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0                    (0x1U << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
+#define TIM_CCMR1_CC2S_1                    (0x2U << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
+
+#define TIM_CCMR1_OC2FE_Pos                 (10U)
+#define TIM_CCMR1_OC2FE_Msk                 (0x1U << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE_Pos                 (11U)
+#define TIM_CCMR1_OC2PE_Msk                 (0x1U << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M_Pos                  (12U)
+#define TIM_CCMR1_OC2M_Msk                  (0x7U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0                    (0x1U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
+#define TIM_CCMR1_OC2M_1                    (0x2U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
+#define TIM_CCMR1_OC2M_2                    (0x4U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
+
+#define TIM_CCMR1_OC2CE_Pos                 (15U)
+#define TIM_CCMR1_OC2CE_Msk                 (0x1U << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos                (2U)
+#define TIM_CCMR1_IC1PSC_Msk                (0x3U << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0                  (0x1U << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
+#define TIM_CCMR1_IC1PSC_1                  (0x2U << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
+
+#define TIM_CCMR1_IC1F_Pos                  (4U)
+#define TIM_CCMR1_IC1F_Msk                  (0xFU << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0                    (0x1U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
+#define TIM_CCMR1_IC1F_1                    (0x2U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
+#define TIM_CCMR1_IC1F_2                    (0x4U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
+#define TIM_CCMR1_IC1F_3                    (0x8U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
+
+#define TIM_CCMR1_IC2PSC_Pos                (10U)
+#define TIM_CCMR1_IC2PSC_Msk                (0x3U << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0                  (0x1U << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
+#define TIM_CCMR1_IC2PSC_1                  (0x2U << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
+
+#define TIM_CCMR1_IC2F_Pos                  (12U)
+#define TIM_CCMR1_IC2F_Msk                  (0xFU << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0                    (0x1U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
+#define TIM_CCMR1_IC2F_1                    (0x2U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
+#define TIM_CCMR1_IC2F_2                    (0x4U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
+#define TIM_CCMR1_IC2F_3                    (0x8U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos                  (0U)
+#define TIM_CCMR2_CC3S_Msk                  (0x3U << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0                    (0x1U << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
+#define TIM_CCMR2_CC3S_1                    (0x2U << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
+
+#define TIM_CCMR2_OC3FE_Pos                 (2U)
+#define TIM_CCMR2_OC3FE_Msk                 (0x1U << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE_Pos                 (3U)
+#define TIM_CCMR2_OC3PE_Msk                 (0x1U << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M_Pos                  (4U)
+#define TIM_CCMR2_OC3M_Msk                  (0x7U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0                    (0x1U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
+#define TIM_CCMR2_OC3M_1                    (0x2U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
+#define TIM_CCMR2_OC3M_2                    (0x4U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
+
+#define TIM_CCMR2_OC3CE_Pos                 (7U)
+#define TIM_CCMR2_OC3CE_Msk                 (0x1U << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos                  (8U)
+#define TIM_CCMR2_CC4S_Msk                  (0x3U << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0                    (0x1U << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
+#define TIM_CCMR2_CC4S_1                    (0x2U << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
+
+#define TIM_CCMR2_OC4FE_Pos                 (10U)
+#define TIM_CCMR2_OC4FE_Msk                 (0x1U << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE_Pos                 (11U)
+#define TIM_CCMR2_OC4PE_Msk                 (0x1U << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos                  (12U)
+#define TIM_CCMR2_OC4M_Msk                  (0x7U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0                    (0x1U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
+#define TIM_CCMR2_OC4M_1                    (0x2U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
+#define TIM_CCMR2_OC4M_2                    (0x4U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
+
+#define TIM_CCMR2_OC4CE_Pos                 (15U)
+#define TIM_CCMR2_OC4CE_Msk                 (0x1U << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos                (2U)
+#define TIM_CCMR2_IC3PSC_Msk                (0x3U << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0                  (0x1U << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
+#define TIM_CCMR2_IC3PSC_1                  (0x2U << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
+
+#define TIM_CCMR2_IC3F_Pos                  (4U)
+#define TIM_CCMR2_IC3F_Msk                  (0xFU << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0                    (0x1U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
+#define TIM_CCMR2_IC3F_1                    (0x2U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
+#define TIM_CCMR2_IC3F_2                    (0x4U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
+#define TIM_CCMR2_IC3F_3                    (0x8U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
+
+#define TIM_CCMR2_IC4PSC_Pos                (10U)
+#define TIM_CCMR2_IC4PSC_Msk                (0x3U << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0                  (0x1U << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
+#define TIM_CCMR2_IC4PSC_1                  (0x2U << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
+
+#define TIM_CCMR2_IC4F_Pos                  (12U)
+#define TIM_CCMR2_IC4F_Msk                  (0xFU << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0                    (0x1U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
+#define TIM_CCMR2_IC4F_1                    (0x2U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
+#define TIM_CCMR2_IC4F_2                    (0x4U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
+#define TIM_CCMR2_IC4F_3                    (0x8U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos                   (0U)
+#define TIM_CCER_CC1E_Msk                   (0x1U << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
+#define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P_Pos                   (1U)
+#define TIM_CCER_CC1P_Msk                   (0x1U << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
+#define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP_Pos                  (3U)
+#define TIM_CCER_CC1NP_Msk                  (0x1U << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
+#define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos                   (4U)
+#define TIM_CCER_CC2E_Msk                   (0x1U << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
+#define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P_Pos                   (5U)
+#define TIM_CCER_CC2P_Msk                   (0x1U << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
+#define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP_Pos                  (7U)
+#define TIM_CCER_CC2NP_Msk                  (0x1U << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
+#define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos                   (8U)
+#define TIM_CCER_CC3E_Msk                   (0x1U << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
+#define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P_Pos                   (9U)
+#define TIM_CCER_CC3P_Msk                   (0x1U << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
+#define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP_Pos                  (11U)
+#define TIM_CCER_CC3NP_Msk                  (0x1U << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
+#define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos                   (12U)
+#define TIM_CCER_CC4E_Msk                   (0x1U << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
+#define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P_Pos                   (13U)
+#define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
+#define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP_Pos                  (15U)
+#define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
+#define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos                     (0U)
+#define TIM_CNT_CNT_Msk                     (0xFFFFFFFFU << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos                     (0U)
+#define TIM_PSC_PSC_Msk                     (0xFFFFU << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
+#define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos                     (0U)
+#define TIM_ARR_ARR_Msk                     (0xFFFFFFFFU << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos                   (0U)
+#define TIM_CCR1_CCR1_Msk                   (0xFFFFU << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos                   (0U)
+#define TIM_CCR2_CCR2_Msk                   (0xFFFFU << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos                   (0U)
+#define TIM_CCR3_CCR3_Msk                   (0xFFFFU << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos                   (0U)
+#define TIM_CCR4_CCR4_Msk                   (0xFFFFU << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos                     (0U)
+#define TIM_DCR_DBA_Msk                     (0x1FU << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
+#define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0                       (0x01U << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
+#define TIM_DCR_DBA_1                       (0x02U << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
+#define TIM_DCR_DBA_2                       (0x04U << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
+#define TIM_DCR_DBA_3                       (0x08U << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
+#define TIM_DCR_DBA_4                       (0x10U << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
+
+#define TIM_DCR_DBL_Pos                     (8U)
+#define TIM_DCR_DBL_Msk                     (0x1FU << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
+#define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0                       (0x01U << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
+#define TIM_DCR_DBL_1                       (0x02U << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
+#define TIM_DCR_DBL_2                       (0x04U << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
+#define TIM_DCR_DBL_3                       (0x08U << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
+#define TIM_DCR_DBL_4                       (0x10U << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos                   (0U)
+#define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM_OR_TI1RMP_Pos                   (0U)
+#define TIM_OR_TI1RMP_Msk                   (0x3U << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
+#define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
+#define TIM_OR_TI1RMP_0                     (0x1U << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
+#define TIM_OR_TI1RMP_1                     (0x2U << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
+
+#define TIM_OR_ETR_RMP_Pos                  (2U)
+#define TIM_OR_ETR_RMP_Msk                  (0x1U << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
+#define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
+#define TIM_OR_TI1_RMP_RI_Pos               (3U)
+#define TIM_OR_TI1_RMP_RI_Msk               (0x1U << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
+#define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_SR register  *******************/
+#define USART_SR_PE_Pos                     (0U)
+#define USART_SR_PE_Msk                     (0x1U << USART_SR_PE_Pos)          /*!< 0x00000001 */
+#define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
+#define USART_SR_FE_Pos                     (1U)
+#define USART_SR_FE_Msk                     (0x1U << USART_SR_FE_Pos)          /*!< 0x00000002 */
+#define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
+#define USART_SR_NE_Pos                     (2U)
+#define USART_SR_NE_Msk                     (0x1U << USART_SR_NE_Pos)          /*!< 0x00000004 */
+#define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
+#define USART_SR_ORE_Pos                    (3U)
+#define USART_SR_ORE_Msk                    (0x1U << USART_SR_ORE_Pos)         /*!< 0x00000008 */
+#define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
+#define USART_SR_IDLE_Pos                   (4U)
+#define USART_SR_IDLE_Msk                   (0x1U << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
+#define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
+#define USART_SR_RXNE_Pos                   (5U)
+#define USART_SR_RXNE_Msk                   (0x1U << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
+#define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
+#define USART_SR_TC_Pos                     (6U)
+#define USART_SR_TC_Msk                     (0x1U << USART_SR_TC_Pos)          /*!< 0x00000040 */
+#define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
+#define USART_SR_TXE_Pos                    (7U)
+#define USART_SR_TXE_Msk                    (0x1U << USART_SR_TXE_Pos)         /*!< 0x00000080 */
+#define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
+#define USART_SR_LBD_Pos                    (8U)
+#define USART_SR_LBD_Msk                    (0x1U << USART_SR_LBD_Pos)         /*!< 0x00000100 */
+#define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
+#define USART_SR_CTS_Pos                    (9U)
+#define USART_SR_CTS_Msk                    (0x1U << USART_SR_CTS_Pos)         /*!< 0x00000200 */
+#define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define USART_DR_DR_Pos                     (0U)
+#define USART_DR_DR_Msk                     (0x1FFU << USART_DR_DR_Pos)        /*!< 0x000001FF */
+#define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_FRACTION_Pos          (0U)
+#define USART_BRR_DIV_FRACTION_Msk          (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
+#define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA_Pos          (4U)
+#define USART_BRR_DIV_MANTISSA_Msk          (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_SBK_Pos                   (0U)
+#define USART_CR1_SBK_Msk                   (0x1U << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
+#define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
+#define USART_CR1_RWU_Pos                   (1U)
+#define USART_CR1_RWU_Msk                   (0x1U << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
+#define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
+#define USART_CR1_RE_Pos                    (2U)
+#define USART_CR1_RE_Msk                    (0x1U << USART_CR1_RE_Pos)         /*!< 0x00000004 */
+#define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
+#define USART_CR1_TE_Pos                    (3U)
+#define USART_CR1_TE_Msk                    (0x1U << USART_CR1_TE_Pos)         /*!< 0x00000008 */
+#define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE_Pos                (4U)
+#define USART_CR1_IDLEIE_Msk                (0x1U << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
+#define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE_Pos                (5U)
+#define USART_CR1_RXNEIE_Msk                (0x1U << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
+#define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE_Pos                  (6U)
+#define USART_CR1_TCIE_Msk                  (0x1U << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
+#define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos                 (7U)
+#define USART_CR1_TXEIE_Msk                 (0x1U << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
+#define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE_Pos                  (8U)
+#define USART_CR1_PEIE_Msk                  (0x1U << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
+#define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
+#define USART_CR1_PS_Pos                    (9U)
+#define USART_CR1_PS_Msk                    (0x1U << USART_CR1_PS_Pos)         /*!< 0x00000200 */
+#define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
+#define USART_CR1_PCE_Pos                   (10U)
+#define USART_CR1_PCE_Msk                   (0x1U << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
+#define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
+#define USART_CR1_WAKE_Pos                  (11U)
+#define USART_CR1_WAKE_Msk                  (0x1U << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
+#define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
+#define USART_CR1_M_Pos                     (12U)
+#define USART_CR1_M_Msk                     (0x1U << USART_CR1_M_Pos)          /*!< 0x00001000 */
+#define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
+#define USART_CR1_UE_Pos                    (13U)
+#define USART_CR1_UE_Msk                    (0x1U << USART_CR1_UE_Pos)         /*!< 0x00002000 */
+#define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
+#define USART_CR1_OVER8_Pos                 (15U)
+#define USART_CR1_OVER8_Msk                 (0x1U << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
+#define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADD_Pos                   (0U)
+#define USART_CR2_ADD_Msk                   (0xFU << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
+#define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
+#define USART_CR2_LBDL_Pos                  (5U)
+#define USART_CR2_LBDL_Msk                  (0x1U << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
+#define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE_Pos                 (6U)
+#define USART_CR2_LBDIE_Msk                 (0x1U << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
+#define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos                  (8U)
+#define USART_CR2_LBCL_Msk                  (0x1U << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
+#define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA_Pos                  (9U)
+#define USART_CR2_CPHA_Msk                  (0x1U << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
+#define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
+#define USART_CR2_CPOL_Pos                  (10U)
+#define USART_CR2_CPOL_Msk                  (0x1U << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
+#define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
+#define USART_CR2_CLKEN_Pos                 (11U)
+#define USART_CR2_CLKEN_Msk                 (0x1U << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
+#define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
+
+#define USART_CR2_STOP_Pos                  (12U)
+#define USART_CR2_STOP_Msk                  (0x3U << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
+#define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0                    (0x1U << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
+#define USART_CR2_STOP_1                    (0x2U << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
+
+#define USART_CR2_LINEN_Pos                 (14U)
+#define USART_CR2_LINEN_Msk                 (0x1U << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
+#define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos                   (0U)
+#define USART_CR3_EIE_Msk                   (0x1U << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
+#define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
+#define USART_CR3_IREN_Pos                  (1U)
+#define USART_CR3_IREN_Msk                  (0x1U << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
+#define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
+#define USART_CR3_IRLP_Pos                  (2U)
+#define USART_CR3_IRLP_Msk                  (0x1U << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
+#define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL_Pos                 (3U)
+#define USART_CR3_HDSEL_Msk                 (0x1U << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
+#define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
+#define USART_CR3_NACK_Pos                  (4U)
+#define USART_CR3_NACK_Msk                  (0x1U << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
+#define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN_Pos                  (5U)
+#define USART_CR3_SCEN_Msk                  (0x1U << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
+#define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
+#define USART_CR3_DMAR_Pos                  (6U)
+#define USART_CR3_DMAR_Msk                  (0x1U << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
+#define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT_Pos                  (7U)
+#define USART_CR3_DMAT_Msk                  (0x1U << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
+#define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE_Pos                  (8U)
+#define USART_CR3_RTSE_Msk                  (0x1U << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
+#define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
+#define USART_CR3_CTSE_Pos                  (9U)
+#define USART_CR3_CTSE_Msk                  (0x1U << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
+#define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
+#define USART_CR3_CTSIE_Pos                 (10U)
+#define USART_CR3_CTSIE_Msk                 (0x1U << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
+#define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT_Pos                (11U)
+#define USART_CR3_ONEBIT_Msk                (0x1U << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
+#define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos                  (0U)
+#define USART_GTPR_PSC_Msk                  (0xFFU << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
+#define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0                    (0x01U << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
+#define USART_GTPR_PSC_1                    (0x02U << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
+#define USART_GTPR_PSC_2                    (0x04U << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
+#define USART_GTPR_PSC_3                    (0x08U << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
+#define USART_GTPR_PSC_4                    (0x10U << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
+#define USART_GTPR_PSC_5                    (0x20U << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
+#define USART_GTPR_PSC_6                    (0x40U << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
+#define USART_GTPR_PSC_7                    (0x80U << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
+
+#define USART_GTPR_GT_Pos                   (8U)
+#define USART_GTPR_GT_Msk                   (0xFFU << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
+#define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                     Universal Serial Bus (USB)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*!<Endpoint-specific registers */
+
+#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
+#define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
+#define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
+#define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
+#define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
+#define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
+#define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
+#define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
+
+/* bit positions */
+#define USB_EP_CTR_RX_Pos                     (15U)
+#define USB_EP_CTR_RX_Msk                     (0x1U << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
+#define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
+#define USB_EP_DTOG_RX_Pos                    (14U)
+#define USB_EP_DTOG_RX_Msk                    (0x1U << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
+#define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
+#define USB_EPRX_STAT_Pos                     (12U)
+#define USB_EPRX_STAT_Msk                     (0x3U << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
+#define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
+#define USB_EP_SETUP_Pos                      (11U)
+#define USB_EP_SETUP_Msk                      (0x1U << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
+#define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
+#define USB_EP_T_FIELD_Pos                    (9U)
+#define USB_EP_T_FIELD_Msk                    (0x3U << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
+#define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
+#define USB_EP_KIND_Pos                       (8U)
+#define USB_EP_KIND_Msk                       (0x1U << USB_EP_KIND_Pos)        /*!< 0x00000100 */
+#define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
+#define USB_EP_CTR_TX_Pos                     (7U)
+#define USB_EP_CTR_TX_Msk                     (0x1U << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
+#define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
+#define USB_EP_DTOG_TX_Pos                    (6U)
+#define USB_EP_DTOG_TX_Msk                    (0x1U << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
+#define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
+#define USB_EPTX_STAT_Pos                     (4U)
+#define USB_EPTX_STAT_Msk                     (0x3U << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
+#define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
+#define USB_EPADDR_FIELD_Pos                  (0U)
+#define USB_EPADDR_FIELD_Msk                  (0xFU << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
+#define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
+
+/* EndPoint REGister MASK (no toggle fields) */
+#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
+                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
+#define USB_EP_TYPE_MASK_Pos                  (9U)
+#define USB_EP_TYPE_MASK_Msk                  (0x3U << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
+#define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
+#define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
+#define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
+#define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
+#define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
+#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
+
+#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
+                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
+#define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
+#define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
+#define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
+#define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
+#define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
+#define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
+#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
+                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
+#define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
+#define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
+#define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
+#define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
+#define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
+#define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
+#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
+
+/*******************  Bit definition for USB_EP0R register  *******************/
+#define USB_EP0R_EA_Pos                       (0U)
+#define USB_EP0R_EA_Msk                       (0xFU << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
+#define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
+
+#define USB_EP0R_STAT_TX_Pos                  (4U)
+#define USB_EP0R_STAT_TX_Msk                  (0x3U << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
+#define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0                    (0x1U << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
+#define USB_EP0R_STAT_TX_1                    (0x2U << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
+
+#define USB_EP0R_DTOG_TX_Pos                  (6U)
+#define USB_EP0R_DTOG_TX_Msk                  (0x1U << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
+#define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX_Pos                   (7U)
+#define USB_EP0R_CTR_TX_Msk                   (0x1U << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
+#define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND_Pos                  (8U)
+#define USB_EP0R_EP_KIND_Msk                  (0x1U << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
+#define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE_Pos                  (9U)
+#define USB_EP0R_EP_TYPE_Msk                  (0x3U << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
+#define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0                    (0x1U << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
+#define USB_EP0R_EP_TYPE_1                    (0x2U << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
+
+#define USB_EP0R_SETUP_Pos                    (11U)
+#define USB_EP0R_SETUP_Msk                    (0x1U << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
+#define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
+
+#define USB_EP0R_STAT_RX_Pos                  (12U)
+#define USB_EP0R_STAT_RX_Msk                  (0x3U << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
+#define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0                    (0x1U << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
+#define USB_EP0R_STAT_RX_1                    (0x2U << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
+
+#define USB_EP0R_DTOG_RX_Pos                  (14U)
+#define USB_EP0R_DTOG_RX_Msk                  (0x1U << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
+#define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX_Pos                   (15U)
+#define USB_EP0R_CTR_RX_Msk                   (0x1U << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
+#define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP1R register  *******************/
+#define USB_EP1R_EA_Pos                       (0U)
+#define USB_EP1R_EA_Msk                       (0xFU << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
+#define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
+
+#define USB_EP1R_STAT_TX_Pos                  (4U)
+#define USB_EP1R_STAT_TX_Msk                  (0x3U << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
+#define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0                    (0x1U << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
+#define USB_EP1R_STAT_TX_1                    (0x2U << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
+
+#define USB_EP1R_DTOG_TX_Pos                  (6U)
+#define USB_EP1R_DTOG_TX_Msk                  (0x1U << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
+#define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX_Pos                   (7U)
+#define USB_EP1R_CTR_TX_Msk                   (0x1U << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
+#define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND_Pos                  (8U)
+#define USB_EP1R_EP_KIND_Msk                  (0x1U << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
+#define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE_Pos                  (9U)
+#define USB_EP1R_EP_TYPE_Msk                  (0x3U << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
+#define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0                    (0x1U << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
+#define USB_EP1R_EP_TYPE_1                    (0x2U << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
+
+#define USB_EP1R_SETUP_Pos                    (11U)
+#define USB_EP1R_SETUP_Msk                    (0x1U << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
+#define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
+
+#define USB_EP1R_STAT_RX_Pos                  (12U)
+#define USB_EP1R_STAT_RX_Msk                  (0x3U << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
+#define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0                    (0x1U << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
+#define USB_EP1R_STAT_RX_1                    (0x2U << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
+
+#define USB_EP1R_DTOG_RX_Pos                  (14U)
+#define USB_EP1R_DTOG_RX_Msk                  (0x1U << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
+#define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX_Pos                   (15U)
+#define USB_EP1R_CTR_RX_Msk                   (0x1U << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
+#define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP2R register  *******************/
+#define USB_EP2R_EA_Pos                       (0U)
+#define USB_EP2R_EA_Msk                       (0xFU << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
+#define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
+
+#define USB_EP2R_STAT_TX_Pos                  (4U)
+#define USB_EP2R_STAT_TX_Msk                  (0x3U << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
+#define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0                    (0x1U << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
+#define USB_EP2R_STAT_TX_1                    (0x2U << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
+
+#define USB_EP2R_DTOG_TX_Pos                  (6U)
+#define USB_EP2R_DTOG_TX_Msk                  (0x1U << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
+#define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX_Pos                   (7U)
+#define USB_EP2R_CTR_TX_Msk                   (0x1U << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
+#define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND_Pos                  (8U)
+#define USB_EP2R_EP_KIND_Msk                  (0x1U << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
+#define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE_Pos                  (9U)
+#define USB_EP2R_EP_TYPE_Msk                  (0x3U << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
+#define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0                    (0x1U << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
+#define USB_EP2R_EP_TYPE_1                    (0x2U << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
+
+#define USB_EP2R_SETUP_Pos                    (11U)
+#define USB_EP2R_SETUP_Msk                    (0x1U << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
+#define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
+
+#define USB_EP2R_STAT_RX_Pos                  (12U)
+#define USB_EP2R_STAT_RX_Msk                  (0x3U << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
+#define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0                    (0x1U << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
+#define USB_EP2R_STAT_RX_1                    (0x2U << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
+
+#define USB_EP2R_DTOG_RX_Pos                  (14U)
+#define USB_EP2R_DTOG_RX_Msk                  (0x1U << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
+#define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX_Pos                   (15U)
+#define USB_EP2R_CTR_RX_Msk                   (0x1U << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
+#define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP3R register  *******************/
+#define USB_EP3R_EA_Pos                       (0U)
+#define USB_EP3R_EA_Msk                       (0xFU << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
+#define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
+
+#define USB_EP3R_STAT_TX_Pos                  (4U)
+#define USB_EP3R_STAT_TX_Msk                  (0x3U << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
+#define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0                    (0x1U << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
+#define USB_EP3R_STAT_TX_1                    (0x2U << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
+
+#define USB_EP3R_DTOG_TX_Pos                  (6U)
+#define USB_EP3R_DTOG_TX_Msk                  (0x1U << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
+#define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX_Pos                   (7U)
+#define USB_EP3R_CTR_TX_Msk                   (0x1U << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
+#define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND_Pos                  (8U)
+#define USB_EP3R_EP_KIND_Msk                  (0x1U << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
+#define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE_Pos                  (9U)
+#define USB_EP3R_EP_TYPE_Msk                  (0x3U << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
+#define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0                    (0x1U << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
+#define USB_EP3R_EP_TYPE_1                    (0x2U << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
+
+#define USB_EP3R_SETUP_Pos                    (11U)
+#define USB_EP3R_SETUP_Msk                    (0x1U << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
+#define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
+
+#define USB_EP3R_STAT_RX_Pos                  (12U)
+#define USB_EP3R_STAT_RX_Msk                  (0x3U << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
+#define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0                    (0x1U << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
+#define USB_EP3R_STAT_RX_1                    (0x2U << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
+
+#define USB_EP3R_DTOG_RX_Pos                  (14U)
+#define USB_EP3R_DTOG_RX_Msk                  (0x1U << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
+#define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX_Pos                   (15U)
+#define USB_EP3R_CTR_RX_Msk                   (0x1U << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
+#define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP4R register  *******************/
+#define USB_EP4R_EA_Pos                       (0U)
+#define USB_EP4R_EA_Msk                       (0xFU << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
+#define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
+
+#define USB_EP4R_STAT_TX_Pos                  (4U)
+#define USB_EP4R_STAT_TX_Msk                  (0x3U << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
+#define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0                    (0x1U << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
+#define USB_EP4R_STAT_TX_1                    (0x2U << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
+
+#define USB_EP4R_DTOG_TX_Pos                  (6U)
+#define USB_EP4R_DTOG_TX_Msk                  (0x1U << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
+#define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX_Pos                   (7U)
+#define USB_EP4R_CTR_TX_Msk                   (0x1U << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
+#define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND_Pos                  (8U)
+#define USB_EP4R_EP_KIND_Msk                  (0x1U << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
+#define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE_Pos                  (9U)
+#define USB_EP4R_EP_TYPE_Msk                  (0x3U << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
+#define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0                    (0x1U << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
+#define USB_EP4R_EP_TYPE_1                    (0x2U << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
+
+#define USB_EP4R_SETUP_Pos                    (11U)
+#define USB_EP4R_SETUP_Msk                    (0x1U << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
+#define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
+
+#define USB_EP4R_STAT_RX_Pos                  (12U)
+#define USB_EP4R_STAT_RX_Msk                  (0x3U << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
+#define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0                    (0x1U << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
+#define USB_EP4R_STAT_RX_1                    (0x2U << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
+
+#define USB_EP4R_DTOG_RX_Pos                  (14U)
+#define USB_EP4R_DTOG_RX_Msk                  (0x1U << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
+#define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX_Pos                   (15U)
+#define USB_EP4R_CTR_RX_Msk                   (0x1U << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
+#define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP5R register  *******************/
+#define USB_EP5R_EA_Pos                       (0U)
+#define USB_EP5R_EA_Msk                       (0xFU << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
+#define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
+
+#define USB_EP5R_STAT_TX_Pos                  (4U)
+#define USB_EP5R_STAT_TX_Msk                  (0x3U << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
+#define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0                    (0x1U << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
+#define USB_EP5R_STAT_TX_1                    (0x2U << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
+
+#define USB_EP5R_DTOG_TX_Pos                  (6U)
+#define USB_EP5R_DTOG_TX_Msk                  (0x1U << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
+#define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX_Pos                   (7U)
+#define USB_EP5R_CTR_TX_Msk                   (0x1U << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
+#define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND_Pos                  (8U)
+#define USB_EP5R_EP_KIND_Msk                  (0x1U << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
+#define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE_Pos                  (9U)
+#define USB_EP5R_EP_TYPE_Msk                  (0x3U << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
+#define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0                    (0x1U << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
+#define USB_EP5R_EP_TYPE_1                    (0x2U << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
+
+#define USB_EP5R_SETUP_Pos                    (11U)
+#define USB_EP5R_SETUP_Msk                    (0x1U << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
+#define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
+
+#define USB_EP5R_STAT_RX_Pos                  (12U)
+#define USB_EP5R_STAT_RX_Msk                  (0x3U << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
+#define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0                    (0x1U << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
+#define USB_EP5R_STAT_RX_1                    (0x2U << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
+
+#define USB_EP5R_DTOG_RX_Pos                  (14U)
+#define USB_EP5R_DTOG_RX_Msk                  (0x1U << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
+#define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX_Pos                   (15U)
+#define USB_EP5R_CTR_RX_Msk                   (0x1U << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
+#define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP6R register  *******************/
+#define USB_EP6R_EA_Pos                       (0U)
+#define USB_EP6R_EA_Msk                       (0xFU << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
+#define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
+
+#define USB_EP6R_STAT_TX_Pos                  (4U)
+#define USB_EP6R_STAT_TX_Msk                  (0x3U << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
+#define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0                    (0x1U << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
+#define USB_EP6R_STAT_TX_1                    (0x2U << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
+
+#define USB_EP6R_DTOG_TX_Pos                  (6U)
+#define USB_EP6R_DTOG_TX_Msk                  (0x1U << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
+#define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX_Pos                   (7U)
+#define USB_EP6R_CTR_TX_Msk                   (0x1U << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
+#define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND_Pos                  (8U)
+#define USB_EP6R_EP_KIND_Msk                  (0x1U << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
+#define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE_Pos                  (9U)
+#define USB_EP6R_EP_TYPE_Msk                  (0x3U << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
+#define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0                    (0x1U << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
+#define USB_EP6R_EP_TYPE_1                    (0x2U << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
+
+#define USB_EP6R_SETUP_Pos                    (11U)
+#define USB_EP6R_SETUP_Msk                    (0x1U << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
+#define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
+
+#define USB_EP6R_STAT_RX_Pos                  (12U)
+#define USB_EP6R_STAT_RX_Msk                  (0x3U << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
+#define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0                    (0x1U << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
+#define USB_EP6R_STAT_RX_1                    (0x2U << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
+
+#define USB_EP6R_DTOG_RX_Pos                  (14U)
+#define USB_EP6R_DTOG_RX_Msk                  (0x1U << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
+#define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX_Pos                   (15U)
+#define USB_EP6R_CTR_RX_Msk                   (0x1U << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
+#define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
+
+/*******************  Bit definition for USB_EP7R register  *******************/
+#define USB_EP7R_EA_Pos                       (0U)
+#define USB_EP7R_EA_Msk                       (0xFU << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
+#define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
+
+#define USB_EP7R_STAT_TX_Pos                  (4U)
+#define USB_EP7R_STAT_TX_Msk                  (0x3U << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
+#define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0                    (0x1U << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
+#define USB_EP7R_STAT_TX_1                    (0x2U << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
+
+#define USB_EP7R_DTOG_TX_Pos                  (6U)
+#define USB_EP7R_DTOG_TX_Msk                  (0x1U << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
+#define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX_Pos                   (7U)
+#define USB_EP7R_CTR_TX_Msk                   (0x1U << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
+#define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND_Pos                  (8U)
+#define USB_EP7R_EP_KIND_Msk                  (0x1U << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
+#define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE_Pos                  (9U)
+#define USB_EP7R_EP_TYPE_Msk                  (0x3U << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
+#define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0                    (0x1U << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
+#define USB_EP7R_EP_TYPE_1                    (0x2U << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
+
+#define USB_EP7R_SETUP_Pos                    (11U)
+#define USB_EP7R_SETUP_Msk                    (0x1U << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
+#define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
+
+#define USB_EP7R_STAT_RX_Pos                  (12U)
+#define USB_EP7R_STAT_RX_Msk                  (0x3U << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
+#define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0                    (0x1U << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
+#define USB_EP7R_STAT_RX_1                    (0x2U << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
+
+#define USB_EP7R_DTOG_RX_Pos                  (14U)
+#define USB_EP7R_DTOG_RX_Msk                  (0x1U << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
+#define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX_Pos                   (15U)
+#define USB_EP7R_CTR_RX_Msk                   (0x1U << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
+#define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
+
+/*!<Common registers */
+
+#define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
+#define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
+#define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
+#define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
+#define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
+
+
+
+/*******************  Bit definition for USB_CNTR register  *******************/
+#define USB_CNTR_FRES_Pos                     (0U)
+#define USB_CNTR_FRES_Msk                     (0x1U << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
+#define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
+#define USB_CNTR_PDWN_Pos                     (1U)
+#define USB_CNTR_PDWN_Msk                     (0x1U << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
+#define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
+#define USB_CNTR_LPMODE_Pos                   (2U)
+#define USB_CNTR_LPMODE_Msk                   (0x1U << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
+#define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
+#define USB_CNTR_FSUSP_Pos                    (3U)
+#define USB_CNTR_FSUSP_Msk                    (0x1U << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
+#define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
+#define USB_CNTR_RESUME_Pos                   (4U)
+#define USB_CNTR_RESUME_Msk                   (0x1U << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
+#define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
+#define USB_CNTR_ESOFM_Pos                    (8U)
+#define USB_CNTR_ESOFM_Msk                    (0x1U << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
+#define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM_Pos                     (9U)
+#define USB_CNTR_SOFM_Msk                     (0x1U << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
+#define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM_Pos                   (10U)
+#define USB_CNTR_RESETM_Msk                   (0x1U << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
+#define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
+#define USB_CNTR_SUSPM_Pos                    (11U)
+#define USB_CNTR_SUSPM_Msk                    (0x1U << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
+#define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM_Pos                    (12U)
+#define USB_CNTR_WKUPM_Msk                    (0x1U << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
+#define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM_Pos                     (13U)
+#define USB_CNTR_ERRM_Msk                     (0x1U << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
+#define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM_Pos                  (14U)
+#define USB_CNTR_PMAOVRM_Msk                  (0x1U << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
+#define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM_Pos                     (15U)
+#define USB_CNTR_CTRM_Msk                     (0x1U << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
+#define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
+
+/*******************  Bit definition for USB_ISTR register  *******************/
+#define USB_ISTR_EP_ID_Pos                    (0U)
+#define USB_ISTR_EP_ID_Msk                    (0xFU << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
+#define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
+#define USB_ISTR_DIR_Pos                      (4U)
+#define USB_ISTR_DIR_Msk                      (0x1U << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
+#define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
+#define USB_ISTR_ESOF_Pos                     (8U)
+#define USB_ISTR_ESOF_Msk                     (0x1U << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
+#define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
+#define USB_ISTR_SOF_Pos                      (9U)
+#define USB_ISTR_SOF_Msk                      (0x1U << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
+#define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
+#define USB_ISTR_RESET_Pos                    (10U)
+#define USB_ISTR_RESET_Msk                    (0x1U << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
+#define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
+#define USB_ISTR_SUSP_Pos                     (11U)
+#define USB_ISTR_SUSP_Msk                     (0x1U << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
+#define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
+#define USB_ISTR_WKUP_Pos                     (12U)
+#define USB_ISTR_WKUP_Msk                     (0x1U << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
+#define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
+#define USB_ISTR_ERR_Pos                      (13U)
+#define USB_ISTR_ERR_Msk                      (0x1U << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
+#define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
+#define USB_ISTR_PMAOVR_Pos                   (14U)
+#define USB_ISTR_PMAOVR_Msk                   (0x1U << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
+#define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR_Pos                      (15U)
+#define USB_ISTR_CTR_Msk                      (0x1U << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
+#define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
+
+#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
+#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
+#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
+#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
+#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
+#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
+#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
+#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
+
+
+/*******************  Bit definition for USB_FNR register  ********************/
+#define USB_FNR_FN_Pos                        (0U)
+#define USB_FNR_FN_Msk                        (0x7FFU << USB_FNR_FN_Pos)       /*!< 0x000007FF */
+#define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
+#define USB_FNR_LSOF_Pos                      (11U)
+#define USB_FNR_LSOF_Msk                      (0x3U << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
+#define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
+#define USB_FNR_LCK_Pos                       (13U)
+#define USB_FNR_LCK_Msk                       (0x1U << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
+#define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
+#define USB_FNR_RXDM_Pos                      (14U)
+#define USB_FNR_RXDM_Msk                      (0x1U << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
+#define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
+#define USB_FNR_RXDP_Pos                      (15U)
+#define USB_FNR_RXDP_Msk                      (0x1U << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
+#define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
+
+/******************  Bit definition for USB_DADDR register  *******************/
+#define USB_DADDR_ADD_Pos                     (0U)
+#define USB_DADDR_ADD_Msk                     (0x7FU << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
+#define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0_Pos                    (0U)
+#define USB_DADDR_ADD0_Msk                    (0x1U << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
+#define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
+#define USB_DADDR_ADD1_Pos                    (1U)
+#define USB_DADDR_ADD1_Msk                    (0x1U << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
+#define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
+#define USB_DADDR_ADD2_Pos                    (2U)
+#define USB_DADDR_ADD2_Msk                    (0x1U << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
+#define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
+#define USB_DADDR_ADD3_Pos                    (3U)
+#define USB_DADDR_ADD3_Msk                    (0x1U << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
+#define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
+#define USB_DADDR_ADD4_Pos                    (4U)
+#define USB_DADDR_ADD4_Msk                    (0x1U << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
+#define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
+#define USB_DADDR_ADD5_Pos                    (5U)
+#define USB_DADDR_ADD5_Msk                    (0x1U << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
+#define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
+#define USB_DADDR_ADD6_Pos                    (6U)
+#define USB_DADDR_ADD6_Msk                    (0x1U << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
+#define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
+
+#define USB_DADDR_EF_Pos                      (7U)
+#define USB_DADDR_EF_Msk                      (0x1U << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
+#define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
+
+/******************  Bit definition for USB_BTABLE register  ******************/
+#define USB_BTABLE_BTABLE_Pos                 (3U)
+#define USB_BTABLE_BTABLE_Msk                 (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
+#define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
+
+/*!< Buffer descriptor table */
+/*****************  Bit definition for USB_ADDR0_TX register  *****************/
+#define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)
+#define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_TX register  *****************/
+#define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)
+#define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_TX register  *****************/
+#define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)
+#define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_TX register  *****************/
+#define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)
+#define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_TX register  *****************/
+#define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)
+#define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_TX register  *****************/
+#define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)
+#define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_TX register  *****************/
+#define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)
+#define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_TX register  *****************/
+#define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)
+#define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_TX register  ****************/
+#define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)
+#define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
+
+/*****************  Bit definition for USB_COUNT1_TX register  ****************/
+#define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)
+#define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
+
+/*****************  Bit definition for USB_COUNT2_TX register  ****************/
+#define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)
+#define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
+
+/*****************  Bit definition for USB_COUNT3_TX register  ****************/
+#define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)
+#define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
+
+/*****************  Bit definition for USB_COUNT4_TX register  ****************/
+#define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)
+#define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
+
+/*****************  Bit definition for USB_COUNT5_TX register  ****************/
+#define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)
+#define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
+
+/*****************  Bit definition for USB_COUNT6_TX register  ****************/
+#define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)
+#define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
+
+/*****************  Bit definition for USB_COUNT7_TX register  ****************/
+#define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)
+#define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
+
+/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
+
+/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
+
+/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
+
+/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
+
+/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
+
+/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
+#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint32_t)0x00000000U03FF)        /*!< Transmission Byte Count 3 (low) */
+
+/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
+#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint32_t)0x000003FFU0000)        /*!< Transmission Byte Count 3 (high) */
+
+/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
+
+/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
+
+/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
+
+/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
+
+/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
+
+/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
+
+/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
+
+/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_ADDR0_RX register  *****************/
+#define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)
+#define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
+
+/*****************  Bit definition for USB_ADDR1_RX register  *****************/
+#define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)
+#define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
+
+/*****************  Bit definition for USB_ADDR2_RX register  *****************/
+#define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)
+#define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
+
+/*****************  Bit definition for USB_ADDR3_RX register  *****************/
+#define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)
+#define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
+
+/*****************  Bit definition for USB_ADDR4_RX register  *****************/
+#define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)
+#define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
+
+/*****************  Bit definition for USB_ADDR5_RX register  *****************/
+#define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)
+#define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
+
+/*****************  Bit definition for USB_ADDR6_RX register  *****************/
+#define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)
+#define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
+
+/*****************  Bit definition for USB_ADDR7_RX register  *****************/
+#define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)
+#define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
+#define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/*****************  Bit definition for USB_COUNT0_RX register  ****************/
+#define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)
+#define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)
+#define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0             (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT0_RX_NUM_BLOCK_1             (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT0_RX_NUM_BLOCK_2             (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT0_RX_NUM_BLOCK_3             (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT0_RX_NUM_BLOCK_4             (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT0_RX_BLSIZE_Pos              (15U)
+#define USB_COUNT0_RX_BLSIZE_Msk              (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT1_RX register  ****************/
+#define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)
+#define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)
+#define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0             (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT1_RX_NUM_BLOCK_1             (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT1_RX_NUM_BLOCK_2             (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT1_RX_NUM_BLOCK_3             (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT1_RX_NUM_BLOCK_4             (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT1_RX_BLSIZE_Pos              (15U)
+#define USB_COUNT1_RX_BLSIZE_Msk              (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT2_RX register  ****************/
+#define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)
+#define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)
+#define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0             (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT2_RX_NUM_BLOCK_1             (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT2_RX_NUM_BLOCK_2             (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT2_RX_NUM_BLOCK_3             (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT2_RX_NUM_BLOCK_4             (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT2_RX_BLSIZE_Pos              (15U)
+#define USB_COUNT2_RX_BLSIZE_Msk              (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT3_RX register  ****************/
+#define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)
+#define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)
+#define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0             (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT3_RX_NUM_BLOCK_1             (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT3_RX_NUM_BLOCK_2             (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT3_RX_NUM_BLOCK_3             (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT3_RX_NUM_BLOCK_4             (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT3_RX_BLSIZE_Pos              (15U)
+#define USB_COUNT3_RX_BLSIZE_Msk              (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT4_RX register  ****************/
+#define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)
+#define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)
+#define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0             (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT4_RX_NUM_BLOCK_1             (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT4_RX_NUM_BLOCK_2             (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT4_RX_NUM_BLOCK_3             (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT4_RX_NUM_BLOCK_4             (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT4_RX_BLSIZE_Pos              (15U)
+#define USB_COUNT4_RX_BLSIZE_Msk              (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT5_RX register  ****************/
+#define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)
+#define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)
+#define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0             (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT5_RX_NUM_BLOCK_1             (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT5_RX_NUM_BLOCK_2             (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT5_RX_NUM_BLOCK_3             (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT5_RX_NUM_BLOCK_4             (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT5_RX_BLSIZE_Pos              (15U)
+#define USB_COUNT5_RX_BLSIZE_Msk              (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT6_RX register  ****************/
+#define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)
+#define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)
+#define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0             (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT6_RX_NUM_BLOCK_1             (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT6_RX_NUM_BLOCK_2             (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT6_RX_NUM_BLOCK_3             (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT6_RX_NUM_BLOCK_4             (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT6_RX_BLSIZE_Pos              (15U)
+#define USB_COUNT6_RX_BLSIZE_Msk              (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
+
+/*****************  Bit definition for USB_COUNT7_RX register  ****************/
+#define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)
+#define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
+#define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)
+#define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
+#define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0             (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
+#define USB_COUNT7_RX_NUM_BLOCK_1             (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
+#define USB_COUNT7_RX_NUM_BLOCK_2             (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
+#define USB_COUNT7_RX_NUM_BLOCK_3             (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
+#define USB_COUNT7_RX_NUM_BLOCK_4             (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
+
+#define USB_COUNT7_RX_BLSIZE_Pos              (15U)
+#define USB_COUNT7_RX_BLSIZE_Msk              (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
+#define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
+
+/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
+
+/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
+
+/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
+
+/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Window WATCHDOG (WWDG)                             */
+/*                                                                            */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos                       (0U)
+#define WWDG_CR_T_Msk                       (0x7FU << WWDG_CR_T_Pos)           /*!< 0x0000007F */
+#define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0                         (0x01U << WWDG_CR_T_Pos)           /*!< 0x00000001 */
+#define WWDG_CR_T_1                         (0x02U << WWDG_CR_T_Pos)           /*!< 0x00000002 */
+#define WWDG_CR_T_2                         (0x04U << WWDG_CR_T_Pos)           /*!< 0x00000004 */
+#define WWDG_CR_T_3                         (0x08U << WWDG_CR_T_Pos)           /*!< 0x00000008 */
+#define WWDG_CR_T_4                         (0x10U << WWDG_CR_T_Pos)           /*!< 0x00000010 */
+#define WWDG_CR_T_5                         (0x20U << WWDG_CR_T_Pos)           /*!< 0x00000020 */
+#define WWDG_CR_T_6                         (0x40U << WWDG_CR_T_Pos)           /*!< 0x00000040 */
+
+/* Legacy defines */
+#define  WWDG_CR_T0 WWDG_CR_T_0
+#define  WWDG_CR_T1 WWDG_CR_T_1
+#define  WWDG_CR_T2 WWDG_CR_T_2
+#define  WWDG_CR_T3 WWDG_CR_T_3
+#define  WWDG_CR_T4 WWDG_CR_T_4
+#define  WWDG_CR_T5 WWDG_CR_T_5
+#define  WWDG_CR_T6 WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos                    (7U)
+#define WWDG_CR_WDGA_Msk                    (0x1U << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
+#define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos                      (0U)
+#define WWDG_CFR_W_Msk                      (0x7FU << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
+#define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0                        (0x01U << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
+#define WWDG_CFR_W_1                        (0x02U << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
+#define WWDG_CFR_W_2                        (0x04U << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
+#define WWDG_CFR_W_3                        (0x08U << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
+#define WWDG_CFR_W_4                        (0x10U << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
+#define WWDG_CFR_W_5                        (0x20U << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
+#define WWDG_CFR_W_6                        (0x40U << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
+
+/* Legacy defines */
+#define  WWDG_CFR_W0 WWDG_CFR_W_0
+#define  WWDG_CFR_W1 WWDG_CFR_W_1
+#define  WWDG_CFR_W2 WWDG_CFR_W_2
+#define  WWDG_CFR_W3 WWDG_CFR_W_3
+#define  WWDG_CFR_W4 WWDG_CFR_W_4
+#define  WWDG_CFR_W5 WWDG_CFR_W_5
+#define  WWDG_CFR_W6 WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos                  (7U)
+#define WWDG_CFR_WDGTB_Msk                  (0x3U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0                    (0x1U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
+#define WWDG_CFR_WDGTB_1                    (0x2U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
+
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos                    (9U)
+#define WWDG_CFR_EWI_Msk                    (0x1U << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
+#define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos                    (0U)
+#define WWDG_SR_EWIF_Msk                    (0x1U << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
+#define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        SystemTick (SysTick)                                */
+/*                                                                            */
+/******************************************************************************/
+
+/*****************  Bit definition for SysTick_CTRL register  *****************/
+#define SysTick_CTRL_ENABLE                 (0x00000001U)                      /*!< Counter enable */
+#define SysTick_CTRL_TICKINT                (0x00000002U)                      /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE              (0x00000004U)                      /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG              (0x00010000U)                      /*!< Count Flag */
+
+/*****************  Bit definition for SysTick_LOAD register  *****************/
+#define SysTick_LOAD_RELOAD                 (0x00FFFFFFU)                      /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/*****************  Bit definition for SysTick_VAL register  ******************/
+#define SysTick_VAL_CURRENT                 (0x00FFFFFFU)                      /*!< Current value at the time the register is accessed */
+
+/*****************  Bit definition for SysTick_CALIB register  ****************/
+#define SysTick_CALIB_TENMS                 (0x00FFFFFFU)                      /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW                  (0x40000000U)                      /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF                 (0x80000000U)                      /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/*                                                                            */
+/*               Nested Vectored Interrupt Controller (NVIC)                  */
+/*                                                                            */
+/******************************************************************************/
+
+/******************  Bit definition for NVIC_ISER register  *******************/
+#define NVIC_ISER_SETENA_Pos                (0U)
+#define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
+#define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
+#define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
+#define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
+#define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
+#define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
+#define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
+#define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
+#define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
+#define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
+#define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
+#define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
+#define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
+#define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
+#define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
+#define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
+#define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
+#define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
+#define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
+#define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
+#define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
+#define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
+#define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
+#define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
+#define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
+#define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
+#define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
+#define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
+#define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
+#define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
+#define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
+#define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
+
+/******************  Bit definition for NVIC_ICER register  *******************/
+#define NVIC_ICER_CLRENA_Pos                (0U)
+#define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
+#define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
+#define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
+#define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
+#define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
+#define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
+#define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
+#define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
+#define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
+#define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
+#define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
+#define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
+#define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
+#define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
+#define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
+#define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
+#define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
+#define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
+#define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
+#define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
+#define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
+#define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
+#define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
+#define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
+#define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
+#define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
+#define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
+#define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
+#define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
+#define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
+#define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
+#define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
+
+/******************  Bit definition for NVIC_ISPR register  *******************/
+#define NVIC_ISPR_SETPEND_Pos               (0U)
+#define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
+
+/******************  Bit definition for NVIC_ICPR register  *******************/
+#define NVIC_ICPR_CLRPEND_Pos               (0U)
+#define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
+#define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
+#define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
+#define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
+#define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
+#define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
+#define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
+#define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
+#define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
+#define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
+#define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
+#define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
+#define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
+#define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
+#define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
+#define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
+#define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
+#define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
+#define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
+#define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
+#define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
+#define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
+#define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
+#define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
+#define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
+#define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
+#define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
+#define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
+#define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
+#define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
+#define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
+#define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
+
+/******************  Bit definition for NVIC_IABR register  *******************/
+#define NVIC_IABR_ACTIVE_Pos                (0U)
+#define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
+#define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
+#define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
+#define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
+#define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
+#define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
+#define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
+#define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
+#define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
+#define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
+#define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
+#define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
+#define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
+#define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
+#define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
+#define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
+#define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
+#define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
+#define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
+#define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
+#define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
+#define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
+#define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
+#define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
+#define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
+#define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
+#define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
+#define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
+#define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
+#define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
+#define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
+#define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
+#define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
+
+/******************  Bit definition for NVIC_PRI0 register  *******************/
+#define NVIC_IPR0_PRI_0                     (0x000000FFU)                      /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1                     (0x0000FF00U)                      /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2                     (0x00FF0000U)                      /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3                     (0xFF000000U)                      /*!< Priority of interrupt 3 */
+
+/******************  Bit definition for NVIC_PRI1 register  *******************/
+#define NVIC_IPR1_PRI_4                     (0x000000FFU)                      /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5                     (0x0000FF00U)                      /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6                     (0x00FF0000U)                      /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7                     (0xFF000000U)                      /*!< Priority of interrupt 7 */
+
+/******************  Bit definition for NVIC_PRI2 register  *******************/
+#define NVIC_IPR2_PRI_8                     (0x000000FFU)                      /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9                     (0x0000FF00U)                      /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10                    (0x00FF0000U)                      /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11                    (0xFF000000U)                      /*!< Priority of interrupt 11 */
+
+/******************  Bit definition for NVIC_PRI3 register  *******************/
+#define NVIC_IPR3_PRI_12                    (0x000000FFU)                      /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13                    (0x0000FF00U)                      /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14                    (0x00FF0000U)                      /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15                    (0xFF000000U)                      /*!< Priority of interrupt 15 */
+
+/******************  Bit definition for NVIC_PRI4 register  *******************/
+#define NVIC_IPR4_PRI_16                    (0x000000FFU)                      /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17                    (0x0000FF00U)                      /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18                    (0x00FF0000U)                      /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19                    (0xFF000000U)                      /*!< Priority of interrupt 19 */
+
+/******************  Bit definition for NVIC_PRI5 register  *******************/
+#define NVIC_IPR5_PRI_20                    (0x000000FFU)                      /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21                    (0x0000FF00U)                      /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22                    (0x00FF0000U)                      /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23                    (0xFF000000U)                      /*!< Priority of interrupt 23 */
+
+/******************  Bit definition for NVIC_PRI6 register  *******************/
+#define NVIC_IPR6_PRI_24                    (0x000000FFU)                      /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25                    (0x0000FF00U)                      /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26                    (0x00FF0000U)                      /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27                    (0xFF000000U)                      /*!< Priority of interrupt 27 */
+
+/******************  Bit definition for NVIC_PRI7 register  *******************/
+#define NVIC_IPR7_PRI_28                    (0x000000FFU)                      /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29                    (0x0000FF00U)                      /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30                    (0x00FF0000U)                      /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31                    (0xFF000000U)                      /*!< Priority of interrupt 31 */
+
+/******************  Bit definition for SCB_CPUID register  *******************/
+#define SCB_CPUID_REVISION                  (0x0000000FU)                      /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO                    (0x0000FFF0U)                      /*!< Number of processor within serie */
+#define SCB_CPUID_Constant                  (0x000F0000U)                      /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT                   (0x00F00000U)                      /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER               (0xFF000000U)                      /*!< Implementer code. ARM is 0x41 */
+
+/*******************  Bit definition for SCB_ICSR register  *******************/
+#define SCB_ICSR_VECTACTIVE                 (0x000001FFU)                      /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE                  (0x00000800U)                      /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING                (0x003FF000U)                      /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING                 (0x00400000U)                      /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT                 (0x00800000U)                      /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR                  (0x02000000U)                      /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET                  (0x04000000U)                      /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR                  (0x08000000U)                      /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET                  (0x10000000U)                      /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET                 (0x80000000U)                      /*!< Set pending NMI bit */
+
+/*******************  Bit definition for SCB_VTOR register  *******************/
+#define SCB_VTOR_TBLOFF                     (0x1FFFFF80U)                      /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE                    (0x20000000U)                      /*!< Table base in code(0) or RAM(1) */
+
+/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
+#define SCB_AIRCR_VECTRESET                 (0x00000001U)                      /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE             (0x00000002U)                      /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ               (0x00000004U)                      /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP                  (0x00000700U)                      /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0                (0x00000100U)                      /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1                (0x00000200U)                      /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2                (0x00000400U)                      /*!< Bit 2  */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0                 (0x00000000U)                      /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1                 (0x00000100U)                      /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2                 (0x00000200U)                      /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3                 (0x00000300U)                      /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4                 (0x00000400U)                      /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5                 (0x00000500U)                      /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6                 (0x00000600U)                      /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7                 (0x00000700U)                      /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS                 (0x00008000U)                      /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY                   (0xFFFF0000U)                      /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/*******************  Bit definition for SCB_SCR register  ********************/
+#define SCB_SCR_SLEEPONEXIT                 (0x00000002U)                      /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP                   (0x00000004U)                      /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND                   (0x00000010U)                      /*!< Wake up from WFE */
+
+/********************  Bit definition for SCB_CCR register  *******************/
+#define SCB_CCR_NONBASETHRDENA              (0x00000001U)                      /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND                (0x00000002U)                      /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP                 (0x00000008U)                      /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP                   (0x00000010U)                      /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN                   (0x00000100U)                      /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN                    (0x00000200U)                      /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/*******************  Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N_Pos                  (0U)
+#define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */
+#define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1_Pos                 (8U)
+#define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */
+#define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2_Pos                 (16U)
+#define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */
+#define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3_Pos                 (24U)
+#define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */
+#define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/******************  Bit definition for SCB_SHCSR register  *******************/
+#define SCB_SHCSR_MEMFAULTACT               (0x00000001U)                      /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT               (0x00000002U)                      /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT               (0x00000008U)                      /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT                 (0x00000080U)                      /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT                (0x00000100U)                      /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT                 (0x00000400U)                      /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT                (0x00000800U)                      /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED            (0x00001000U)                      /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED            (0x00002000U)                      /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED            (0x00004000U)                      /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED              (0x00008000U)                      /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA               (0x00010000U)                      /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA               (0x00020000U)                      /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA               (0x00040000U)                      /*!< UsageFault enable */
+
+/*******************  Bit definition for SCB_CFSR register  *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)    /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)  /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+#define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)    /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)      /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+#define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)    /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)     /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+#define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)    /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)       /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+#define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)    /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)     /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+#define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)       /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)        /*!< SCB CFSR (BFSR): IBUSERR Mask */
+#define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)       /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)      /*!< SCB CFSR (BFSR): PRECISERR Mask */
+#define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)       /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)    /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+#define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)       /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)       /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+#define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)       /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)         /*!< SCB CFSR (BFSR): STKERR Mask */
+#define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)       /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)      /*!< SCB CFSR (BFSR): BFARVALID Mask */
+#define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)       /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)     /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+#define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)       /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)       /*!< SCB CFSR (UFSR): INVSTATE Mask */
+#define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)       /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)          /*!< SCB CFSR (UFSR): INVPC Mask */
+#define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)       /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)           /*!< SCB CFSR (UFSR): NOCP Mask */
+#define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)       /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)      /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+#define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)       /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)      /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+#define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/*******************  Bit definition for SCB_HFSR register  *******************/
+#define SCB_HFSR_VECTTBL                    (0x00000002U)                      /*!< Fault occures because of vector table read on exception processing */
+#define SCB_HFSR_FORCED                     (0x40000000U)                      /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT                   (0x80000000U)                      /*!< Fault related to debug */
+
+/*******************  Bit definition for SCB_DFSR register  *******************/
+#define SCB_DFSR_HALTED                     (0x00000001U)                      /*!< Halt request flag */
+#define SCB_DFSR_BKPT                       (0x00000002U)                      /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP                    (0x00000004U)                      /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH                     (0x00000008U)                      /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL                   (0x00000010U)                      /*!< External debug request flag */
+
+/*******************  Bit definition for SCB_MMFAR register  ******************/
+#define SCB_MMFAR_ADDRESS_Pos               (0U)
+#define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */
+
+/*******************  Bit definition for SCB_BFAR register  *******************/
+#define SCB_BFAR_ADDRESS_Pos                (0U)
+#define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
+#define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */
+
+/*******************  Bit definition for SCB_afsr register  *******************/
+#define SCB_AFSR_IMPDEF_Pos                 (0U)
+#define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
+#define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */
+/**
+  * @}
+  */
+
+ /**
+  * @}
+  */
+/** @addtogroup Exported_macro
+  * @{
+  */
+
+/****************************** ADC Instances *********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
+
+/******************************** COMP Instances ******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
+                                        ((INSTANCE) == COMP2))
+
+#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
+
+/****************************** CRC Instances *********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/****************************** DAC Instances *********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
+
+/****************************** DMA Instances *********************************/
+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
+                                       ((INSTANCE) == DMA1_Channel2) || \
+                                       ((INSTANCE) == DMA1_Channel3) || \
+                                       ((INSTANCE) == DMA1_Channel4) || \
+                                       ((INSTANCE) == DMA1_Channel5) || \
+                                       ((INSTANCE) == DMA1_Channel6) || \
+                                       ((INSTANCE) == DMA1_Channel7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOH))
+
+/**************************** GPIO Alternate Function Instances ***************/
+#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/**************************** GPIO Lock Instances *****************************/
+/* On L1, all GPIO Bank support the Lock mechanism */
+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2))
+
+/****************************** SMBUS Instances *******************************/
+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2))
+
+/****************************** TIM Instances *********************************/
+
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
+                                   ((INSTANCE) == TIM3)    || \
+                                   ((INSTANCE) == TIM4)    || \
+                                   ((INSTANCE) == TIM6)    || \
+                                   ((INSTANCE) == TIM7)    || \
+                                   ((INSTANCE) == TIM9)    || \
+                                   ((INSTANCE) == TIM10)   || \
+                                   ((INSTANCE) == TIM11))
+
+#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                       ((INSTANCE) == TIM3)  || \
+                                       ((INSTANCE) == TIM4)  || \
+                                       ((INSTANCE) == TIM9)  || \
+                                       ((INSTANCE) == TIM10) || \
+                                       ((INSTANCE) == TIM11))
+
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                       ((INSTANCE) == TIM3)  || \
+                                       ((INSTANCE) == TIM4)  || \
+                                       ((INSTANCE) == TIM9))
+
+#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                       ((INSTANCE) == TIM3)  || \
+                                       ((INSTANCE) == TIM4))
+
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                       ((INSTANCE) == TIM3)  || \
+                                       ((INSTANCE) == TIM4))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                                        ((INSTANCE) == TIM3)  || \
+                                                        ((INSTANCE) == TIM4)  || \
+                                                        ((INSTANCE) == TIM9))
+
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                                        ((INSTANCE) == TIM3)  || \
+                                                        ((INSTANCE) == TIM4)  || \
+                                                        ((INSTANCE) == TIM9)  || \
+                                                        ((INSTANCE) == TIM10) || \
+                                                        ((INSTANCE) == TIM11))
+
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                                   ((INSTANCE) == TIM3)  || \
+                                                   ((INSTANCE) == TIM4)  || \
+                                                   ((INSTANCE) == TIM9))
+
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                                    ((INSTANCE) == TIM3)  || \
+                                                    ((INSTANCE) == TIM4)  || \
+                                                    ((INSTANCE) == TIM9))
+
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                                ((INSTANCE) == TIM3)  || \
+                                                ((INSTANCE) == TIM4))
+
+#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                       ((INSTANCE) == TIM3)  || \
+                                       ((INSTANCE) == TIM4))
+
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                          ((INSTANCE) == TIM3)  || \
+                                          ((INSTANCE) == TIM4)  || \
+                                          ((INSTANCE) == TIM6)  || \
+                                          ((INSTANCE) == TIM7)  || \
+                                          ((INSTANCE) == TIM9))
+
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM3)  || \
+                                         ((INSTANCE) == TIM4)  || \
+                                         ((INSTANCE) == TIM9))
+
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                            ((INSTANCE) == TIM3)  || \
+                                            ((INSTANCE) == TIM4))
+
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM2) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM3) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM4) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM9) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM10) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM11) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                                  ((INSTANCE) == TIM3)  || \
+                                                  ((INSTANCE) == TIM4)  || \
+                                                  ((INSTANCE) == TIM9)  || \
+                                                  ((INSTANCE) == TIM10) || \
+                                                  ((INSTANCE) == TIM11))
+
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
+                                       ((INSTANCE) == TIM3)    || \
+                                       ((INSTANCE) == TIM4)    || \
+                                       ((INSTANCE) == TIM6)    || \
+                                       ((INSTANCE) == TIM7))
+
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                          ((INSTANCE) == TIM3)  || \
+                                          ((INSTANCE) == TIM4))
+
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
+                                                       ((INSTANCE) == TIM3)    || \
+                                                       ((INSTANCE) == TIM4))
+
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                                     ((INSTANCE) == TIM3)  || \
+                                                     ((INSTANCE) == TIM4))
+
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM9)    || \
+                                         ((INSTANCE) == TIM10)   || \
+                                         ((INSTANCE) == TIM11))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3))
+
+/******************** UART Instances : Asynchronous mode **********************/
+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                 ((INSTANCE) == USART2) || \
+                                                 ((INSTANCE) == USART3))
+
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                          ((INSTANCE) == USART2) || \
+                                          ((INSTANCE) == USART3))
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3))
+
+/********************* UART Instances : Smard card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3))
+
+/***************** UART Instances : Multi-Processor mode **********************/
+#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
+                                                     ((INSTANCE) == USART2) || \
+                                                     ((INSTANCE) == USART3))
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/****************************** USB Instances ********************************/
+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
+
+/**
+  * @}
+  */
+
+/******************************************************************************/
+/*  For a painless codes migration between the STM32L1xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */
+/*  product lines within the same STM32L1 Family                              */
+/******************************************************************************/
+
+/* Aliases for __IRQn */
+
+/* Aliases for __IRQHandler */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L151xBA_H */
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,276 @@
+/**
+  ******************************************************************************
+  * @file    stm32l1xx.h
+  * @author  MCD Application Team
+  * @version V2.2.0
+  * @date    01-July-2016
+  * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *            - Configuration section that allows to select:
+  *              - The STM32L1xx device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx
+  * @{
+  */
+    
+#ifndef __STM32L1XX_H
+#define __STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L1)
+#define STM32L1
+#endif /* STM32L1 */
+
+//MODTRONIX BEGIN - HAL Defines ///////////////////////////////////////////////
+//Provide place for adding HAL defines. Alternative to adding them in IDE project properties.
+//Add project defines here, or add them to your toolchain compiler preprocessor
+
+//Defines what ports to use for default serial port.
+//0 = B10/B11
+//1 = A2/A3
+#if !defined  (MX_DEFAULT_SERIAL_PINS)
+#define MX_DEFAULT_SERIAL_PINS   0          /*!< Use B10/B11 for default serial port, in stead of A2/A3 */
+#endif
+
+//MODTRONIX END ///////////////////////////////////////////////////////////////
+
+/* Uncomment the line below according to the target STM32L device used in your 
+   application 
+  */
+
+#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \
+    !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \
+    !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \
+    !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE)
+  /* #define STM32L100xB  */   /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */
+  /* #define STM32L100xBA */   /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */
+  /* #define STM32L100xC  */   /*!< STM32L100RC Devices */
+  /* #define STM32L151xB  */   /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */
+     #define STM32L151xBA      /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ 
+  /* #define STM32L151xC  */   /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
+  /* #define STM32L151xCA */   /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
+  /* #define STM32L151xD  */   /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
+  /* #define STM32L151xDX  */  /*!< STM32L151VD-X Devices */
+  /* #define STM32L151xE  */   /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
+  /* #define STM32L152xB  */   /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
+  /* #define STM32L152xBA */   /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
+  /* #define STM32L152xC  */   /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
+  /* #define STM32L152xCA */   /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
+  /* #define STM32L152xD  */   /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */  
+  /* #define STM32L152xDX  */  /*!< STM32L152VD-X Devices */
+  /* #define STM32L152xE  */   /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
+  /* #define STM32L162xC  */   /*!< STM32L162RC and STM32L162VC */
+  /* #define STM32L162xCA */   /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
+  /* #define STM32L162xD  */   /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
+  /* #define STM32L162xDX  */  /*!< STM32L162VD-X Devices */
+  /* #define STM32L162xE  */   /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+  
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+#define USE_HAL_DRIVER
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number
+  */
+#define __STM32L1xx_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
+#define __STM32L1xx_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
+#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L1xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
+#define __STM32L1xx_CMSIS_VERSION        ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
+                                         |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\
+                                         |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\
+                                         |(__STM32L1xx_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L100xB)
+  #include "stm32l100xb.h"
+#elif defined(STM32L100xBA)
+  #include "stm32l100xba.h"
+#elif defined(STM32L100xC)
+  #include "stm32l100xc.h"
+#elif defined(STM32L151xB)
+  #include "stm32l151xb.h"
+#elif defined(STM32L151xBA)
+  #include "stm32l151xba.h"
+#elif defined(STM32L151xC)
+  #include "stm32l151xc.h"
+#elif defined(STM32L151xCA)
+  #include "stm32l151xca.h"
+#elif defined(STM32L151xD)
+  #include "stm32l151xd.h"
+#elif defined(STM32L151xDX)
+  #include "stm32l151xdx.h"
+#elif defined(STM32L151xE)
+  #include "stm32l151xe.h"
+#elif defined(STM32L152xB)
+  #include "stm32l152xb.h"
+#elif defined(STM32L152xBA)
+  #include "stm32l152xba.h"
+#elif defined(STM32L152xC)
+  #include "stm32l152xc.h"
+#elif defined(STM32L152xCA)
+  #include "stm32l152xca.h"
+#elif defined(STM32L152xD)
+  #include "stm32l152xd.h"
+#elif defined(STM32L152xDX)
+  #include "stm32l152xdx.h"
+#elif defined(STM32L152xE)
+  #include "stm32l152xe.h"
+#elif defined(STM32L162xC)
+  #include "stm32l162xc.h"
+#elif defined(STM32L162xCA)
+  #include "stm32l162xca.h"
+#elif defined(STM32L162xD)
+  #include "stm32l162xd.h"
+#elif defined(STM32L162xDX)
+  #include "stm32l162xdx.h"
+#elif defined(STM32L162xE)
+  #include "stm32l162xe.h"
+#else
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum 
+{
+  ERROR = 0, 
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l1xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L1xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/system_clock.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,154 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source                | 1- PLL_HSE_EXTC         | 3- PLL_HSI
+  *                                    | (external 16 MHz clock) | (internal 16 MHz)
+  *                                    | 2- PLL_HSE_XTAL         |
+  *                                    | (external 16 MHz xtal)  |
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)                        | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * AHBCLK (MHz)                       | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * APB1CLK (MHz)                      | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * APB2CLK (MHz)                      | 32                     | 32
+  *-----------------------------------------------------------------------------
+  * USB capable (48 MHz precise clock) | YES                    | NO
+  *-----------------------------------------------------------------------------
+  ******************************************************************************
+  */
+
+#include "stm32l1xx.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field.
+                                  This value must be a multiple of 0x200. */
+
+uint8_t SetSysClock_PLL_HSI(void);
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         SystemCoreClock variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit (void)
+{
+    /*!< Set MSION bit */
+    RCC->CR |= (uint32_t)0x00000100;
+
+    /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+    RCC->CFGR &= (uint32_t)0x88FFC00C;
+
+    /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+    RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+    /*!< Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+    RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+    /*!< Disable all interrupts */
+    RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+    SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+void SetSysClock(void)
+{
+    if (SetSysClock_PLL_HSI() == 0) {
+        while(1) {
+            // [TODO] Put something here to tell the user that a problem occured...
+        }
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+}
+
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+
+    /* The voltage scaling allows optimizing the power consumption when the device is
+       clocked below the maximum system frequency, to update the voltage scaling value
+       regarding system frequency refer to product datasheet. */
+    __PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+    /* Enable HSI oscillator and activate PLL with HSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+    // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
+    // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
+    RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
+    RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
+    while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
+
+    /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Output clock on MCO1 pin(PA8) for debugging purpose */
+    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+    return 1; // OK
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/device/system_stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,128 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l1xx.h
+  * @author  MCD Application Team
+  * @version V2.2.0
+  * @date    01-July-2016
+  * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l1xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L1XX_H
+#define __SYSTEM_STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32L1xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L1xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+/*
+*/
+extern const uint8_t AHBPrescTable[16];   /*!< AHB prescalers table values */
+extern const uint8_t APBPrescTable[8];    /*!< APB prescalers table values */
+extern const uint8_t PLLMulTable[9];      /*!< PLL multipiers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L1xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+extern void SetSysClock(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L1XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MTB_RAK811/objects.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2016, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+#define GPIO_IP_WITHOUT_BRR
+#include "common_objects.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l152xe.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L152XE Devices vector for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* COPYRIGHT(c) 2016 STMicroelectronics
+;* COPYRIGHT(c) 2017 STMicroelectronics
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_ARM_STD/startup_stm32l152xe.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_ARM_STD/startup_stm32l152xe.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l152xe.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L152XE Devices vector for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* COPYRIGHT(c) 2016 STMicroelectronics
+;* COPYRIGHT(c) 2017 STMicroelectronics
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l152xe.s
   * @author    MCD Application Team
-  * @version   V2.2.0
-  * @date      01-July-2016
   * @brief     STM32L152XE Devices vector table for 
   *            Atollic toolchain.
   *            This module performs:
@@ -17,7 +15,7 @@
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_IAR/startup_stm32l152xe.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/TOOLCHAIN_IAR/startup_stm32l152xe.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l152xe.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L152XE Devices vector for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+;* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/stm32l152xe.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/stm32l152xe.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l152xe.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32L1xx devices.            
@@ -16,7 +14,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -463,27 +461,27 @@
 typedef struct
 {
   __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,       Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,        Address offset: 0x08 */
+  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
+  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
   __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,               Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,               Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,               Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,         Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                   Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,  Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,         Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                   Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,  Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,         Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                   Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,  Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,         Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                   Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,  Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,         Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                   Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,  Address offset: 0x54 */
+  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
+  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
+  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
+  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
+  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
+  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
+  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
+  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
+  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
+  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
+  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
+  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
+  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
+  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
+  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
+  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
+  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
+  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
 } RI_TypeDef;
 
 /** 
@@ -3656,56 +3654,56 @@
 #define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFRL0_Msk                  (0xFU << GPIO_AFRL_AFRL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFRL0_Msk               
-#define GPIO_AFRL_AFRL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFRL1_Msk                  (0xFU << GPIO_AFRL_AFRL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFRL1_Msk               
-#define GPIO_AFRL_AFRL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFRL2_Msk                  (0xFU << GPIO_AFRL_AFRL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFRL2_Msk               
-#define GPIO_AFRL_AFRL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFRL3_Msk                  (0xFU << GPIO_AFRL_AFRL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFRL3_Msk               
-#define GPIO_AFRL_AFRL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFRL4_Msk                  (0xFU << GPIO_AFRL_AFRL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFRL4_Msk               
-#define GPIO_AFRL_AFRL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFRL5_Msk                  (0xFU << GPIO_AFRL_AFRL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFRL5_Msk               
-#define GPIO_AFRL_AFRL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFRL6_Msk                  (0xFU << GPIO_AFRL_AFRL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFRL6_Msk               
-#define GPIO_AFRL_AFRL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFRL7_Msk                  (0xFU << GPIO_AFRL_AFRL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFRL7_Msk               
+#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
+#define GPIO_AFRL_AFSEL0_Msk                  (0xFU << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
+#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
+#define GPIO_AFRL_AFSEL1_Msk                  (0xFU << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
+#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
+#define GPIO_AFRL_AFSEL2_Msk                  (0xFU << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
+#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
+#define GPIO_AFRL_AFSEL3_Msk                  (0xFU << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
+#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
+#define GPIO_AFRL_AFSEL4_Msk                  (0xFU << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
+#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
+#define GPIO_AFRL_AFSEL5_Msk                  (0xFU << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
+#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
+#define GPIO_AFRL_AFSEL6_Msk                  (0xFU << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
+#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
+#define GPIO_AFRL_AFSEL7_Msk                  (0xFU << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos                  (0U)                              
-#define GPIO_AFRH_AFRH0_Msk                  (0xFU << GPIO_AFRH_AFRH0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFRH0_Msk               
-#define GPIO_AFRH_AFRH1_Pos                  (4U)                              
-#define GPIO_AFRH_AFRH1_Msk                  (0xFU << GPIO_AFRH_AFRH1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFRH1_Msk               
-#define GPIO_AFRH_AFRH2_Pos                  (8U)                              
-#define GPIO_AFRH_AFRH2_Msk                  (0xFU << GPIO_AFRH_AFRH2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFRH2_Msk               
-#define GPIO_AFRH_AFRH3_Pos                  (12U)                             
-#define GPIO_AFRH_AFRH3_Msk                  (0xFU << GPIO_AFRH_AFRH3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFRH3_Msk               
-#define GPIO_AFRH_AFRH4_Pos                  (16U)                             
-#define GPIO_AFRH_AFRH4_Msk                  (0xFU << GPIO_AFRH_AFRH4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFRH4_Msk               
-#define GPIO_AFRH_AFRH5_Pos                  (20U)                             
-#define GPIO_AFRH_AFRH5_Msk                  (0xFU << GPIO_AFRH_AFRH5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFRH5_Msk               
-#define GPIO_AFRH_AFRH6_Pos                  (24U)                             
-#define GPIO_AFRH_AFRH6_Msk                  (0xFU << GPIO_AFRH_AFRH6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFRH6_Msk               
-#define GPIO_AFRH_AFRH7_Pos                  (28U)                             
-#define GPIO_AFRH_AFRH7_Msk                  (0xFU << GPIO_AFRH_AFRH7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFRH7_Msk               
+#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
+#define GPIO_AFRH_AFSEL8_Msk                  (0xFU << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
+#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
+#define GPIO_AFRH_AFSEL9_Msk                  (0xFU << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
+#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
+#define GPIO_AFRH_AFSEL10_Msk                  (0xFU << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
+#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
+#define GPIO_AFRH_AFSEL11_Msk                  (0xFU << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
+#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
+#define GPIO_AFRH_AFSEL12_Msk                  (0xFU << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
+#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
+#define GPIO_AFRH_AFSEL13_Msk                  (0xFU << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
+#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
+#define GPIO_AFRH_AFSEL14_Msk                  (0xFU << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
+#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
+#define GPIO_AFRH_AFSEL15_Msk                  (0xFU << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                        (0x00000001U)                     
@@ -5078,9 +5076,9 @@
 #define RTC_CR_COSEL_Pos                     (19U)                             
 #define RTC_CR_COSEL_Msk                     (0x1U << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
 #define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BCK_Pos                       (18U)                             
-#define RTC_CR_BCK_Msk                       (0x1U << RTC_CR_BCK_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BCK                           RTC_CR_BCK_Msk                    
+#define RTC_CR_BKP_Pos                       (18U)                             
+#define RTC_CR_BKP_Msk                       (0x1U << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
+#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
 #define RTC_CR_SUB1H_Pos                     (17U)                             
 #define RTC_CR_SUB1H_Msk                     (0x1U << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
 #define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
@@ -5133,6 +5131,11 @@
 #define RTC_CR_WUCKSEL_1                     (0x2U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2                     (0x4U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
 
+/* Legacy defines */
+#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
+#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
+#define  RTC_CR_BCK     RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF_Pos                  (16U)                             
 #define RTC_ISR_RECALPF_Msk                  (0x1U << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
@@ -6419,7 +6422,6 @@
 #define RI_HYSCR3_PF_13                 (0x2000U << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
 #define RI_HYSCR3_PF_14                 (0x4000U << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
 #define RI_HYSCR3_PF_15                 (0x8000U << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
-
 /********************  Bit definition for RI_HYSCR4 register  ********************/
 #define RI_HYSCR4_PG_Pos                (0U)                                   
 #define RI_HYSCR4_PG_Msk                (0xFFFFU << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
@@ -8933,24 +8935,58 @@
 
 /*******************  Bit definition for SCB_CFSR register  *******************/
 /*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)    /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)  /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
 #define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)    /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)      /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
 #define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)    /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)     /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
 #define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)    /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)       /*!< SCB CFSR (MMFSR): MSTKERR Mask */
 #define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)    /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)     /*!< SCB CFSR (MMFSR): MMARVALID Mask */
 #define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */
 /*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)       /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)        /*!< SCB CFSR (BFSR): IBUSERR Mask */
 #define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)       /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)      /*!< SCB CFSR (BFSR): PRECISERR Mask */
 #define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)       /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)    /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
 #define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)       /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)       /*!< SCB CFSR (BFSR): UNSTKERR Mask */
 #define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)       /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)         /*!< SCB CFSR (BFSR): STKERR Mask */
 #define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)       /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)      /*!< SCB CFSR (BFSR): BFARVALID Mask */
 #define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */
 /*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)       /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)     /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
 #define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)       /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)       /*!< SCB CFSR (UFSR): INVSTATE Mask */
 #define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)       /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)          /*!< SCB CFSR (UFSR): INVPC Mask */
 #define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)       /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)           /*!< SCB CFSR (UFSR): NOCP Mask */
 #define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)       /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)      /*!< SCB CFSR (UFSR): UNALIGNED Mask */
 #define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)       /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)      /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
 #define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
 
 /*******************  Bit definition for SCB_HFSR register  *******************/

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/stm32l1xx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
   *
   *          The file is the unique include file that the application programmer
@@ -18,7 +16,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -122,7 +120,7 @@
   */
 #define __STM32L1xx_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
 #define __STM32L1xx_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32L1xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32L1xx_CMSIS_VERSION        ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/system_stm32l1xx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/system_stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    system_stm32l1xx.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l151xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L151XC Devices vector for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* COPYRIGHT(c) 2016 STMicroelectronics
+;* COPYRIGHT(c) 2017 STMicroelectronics
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l151xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L151XC Devices vector for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* COPYRIGHT(c) 2016 STMicroelectronics
+;* COPYRIGHT(c) 2017 STMicroelectronics
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l151xc.s
   * @author    MCD Application Team
-  * @version   V2.2.0
-  * @date      01-July-2016
   * @brief     STM32L151XC Devices vector table for 
   *            Atollic toolchain.
   *            This module performs:
@@ -17,7 +15,7 @@
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/stm32l151xc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/stm32l151xc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l151xc.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32L1xx devices.            
@@ -16,7 +14,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -439,21 +437,27 @@
 typedef struct
 {
   __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,       Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,        Address offset: 0x08 */
+  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
+  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
   __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,               Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,               Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved, 0x18                                                                  */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,         Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                   Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,  Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,         Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                   Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,  Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,         Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                   Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,  Address offset: 0x3C */
+  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
+  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
+  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
+  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
+  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
+  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
+  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
+  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
+  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
+  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
+  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
+  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
+  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
+  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
+  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
+  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
+  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
+  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
 } RI_TypeDef;
 
 /** 
@@ -3569,56 +3573,56 @@
 #define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFRL0_Msk                  (0xFU << GPIO_AFRL_AFRL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFRL0_Msk               
-#define GPIO_AFRL_AFRL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFRL1_Msk                  (0xFU << GPIO_AFRL_AFRL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFRL1_Msk               
-#define GPIO_AFRL_AFRL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFRL2_Msk                  (0xFU << GPIO_AFRL_AFRL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFRL2_Msk               
-#define GPIO_AFRL_AFRL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFRL3_Msk                  (0xFU << GPIO_AFRL_AFRL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFRL3_Msk               
-#define GPIO_AFRL_AFRL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFRL4_Msk                  (0xFU << GPIO_AFRL_AFRL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFRL4_Msk               
-#define GPIO_AFRL_AFRL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFRL5_Msk                  (0xFU << GPIO_AFRL_AFRL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFRL5_Msk               
-#define GPIO_AFRL_AFRL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFRL6_Msk                  (0xFU << GPIO_AFRL_AFRL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFRL6_Msk               
-#define GPIO_AFRL_AFRL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFRL7_Msk                  (0xFU << GPIO_AFRL_AFRL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFRL7_Msk               
+#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
+#define GPIO_AFRL_AFSEL0_Msk                  (0xFU << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
+#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
+#define GPIO_AFRL_AFSEL1_Msk                  (0xFU << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
+#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
+#define GPIO_AFRL_AFSEL2_Msk                  (0xFU << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
+#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
+#define GPIO_AFRL_AFSEL3_Msk                  (0xFU << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
+#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
+#define GPIO_AFRL_AFSEL4_Msk                  (0xFU << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
+#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
+#define GPIO_AFRL_AFSEL5_Msk                  (0xFU << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
+#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
+#define GPIO_AFRL_AFSEL6_Msk                  (0xFU << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
+#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
+#define GPIO_AFRL_AFSEL7_Msk                  (0xFU << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos                  (0U)                              
-#define GPIO_AFRH_AFRH0_Msk                  (0xFU << GPIO_AFRH_AFRH0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFRH0_Msk               
-#define GPIO_AFRH_AFRH1_Pos                  (4U)                              
-#define GPIO_AFRH_AFRH1_Msk                  (0xFU << GPIO_AFRH_AFRH1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFRH1_Msk               
-#define GPIO_AFRH_AFRH2_Pos                  (8U)                              
-#define GPIO_AFRH_AFRH2_Msk                  (0xFU << GPIO_AFRH_AFRH2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFRH2_Msk               
-#define GPIO_AFRH_AFRH3_Pos                  (12U)                             
-#define GPIO_AFRH_AFRH3_Msk                  (0xFU << GPIO_AFRH_AFRH3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFRH3_Msk               
-#define GPIO_AFRH_AFRH4_Pos                  (16U)                             
-#define GPIO_AFRH_AFRH4_Msk                  (0xFU << GPIO_AFRH_AFRH4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFRH4_Msk               
-#define GPIO_AFRH_AFRH5_Pos                  (20U)                             
-#define GPIO_AFRH_AFRH5_Msk                  (0xFU << GPIO_AFRH_AFRH5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFRH5_Msk               
-#define GPIO_AFRH_AFRH6_Pos                  (24U)                             
-#define GPIO_AFRH_AFRH6_Msk                  (0xFU << GPIO_AFRH_AFRH6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFRH6_Msk               
-#define GPIO_AFRH_AFRH7_Pos                  (28U)                             
-#define GPIO_AFRH_AFRH7_Msk                  (0xFU << GPIO_AFRH_AFRH7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFRH7_Msk               
+#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
+#define GPIO_AFRH_AFSEL8_Msk                  (0xFU << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
+#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
+#define GPIO_AFRH_AFSEL9_Msk                  (0xFU << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
+#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
+#define GPIO_AFRH_AFSEL10_Msk                  (0xFU << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
+#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
+#define GPIO_AFRH_AFSEL11_Msk                  (0xFU << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
+#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
+#define GPIO_AFRH_AFSEL12_Msk                  (0xFU << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
+#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
+#define GPIO_AFRH_AFSEL13_Msk                  (0xFU << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
+#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
+#define GPIO_AFRH_AFSEL14_Msk                  (0xFU << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
+#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
+#define GPIO_AFRH_AFSEL15_Msk                  (0xFU << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                        (0x00000001U)                     
@@ -4830,9 +4834,9 @@
 #define RTC_CR_COSEL_Pos                     (19U)                             
 #define RTC_CR_COSEL_Msk                     (0x1U << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
 #define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BCK_Pos                       (18U)                             
-#define RTC_CR_BCK_Msk                       (0x1U << RTC_CR_BCK_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BCK                           RTC_CR_BCK_Msk                    
+#define RTC_CR_BKP_Pos                       (18U)                             
+#define RTC_CR_BKP_Msk                       (0x1U << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
+#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
 #define RTC_CR_SUB1H_Pos                     (17U)                             
 #define RTC_CR_SUB1H_Msk                     (0x1U << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
 #define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
@@ -4885,6 +4889,11 @@
 #define RTC_CR_WUCKSEL_1                     (0x2U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2                     (0x4U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
 
+/* Legacy defines */
+#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
+#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
+#define  RTC_CR_BCK     RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF_Pos                  (16U)                             
 #define RTC_ISR_RECALPF_Msk                  (0x1U << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
@@ -6114,6 +6123,45 @@
 #define RI_HYSCR3_PE_13                 (0x2000U << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
 #define RI_HYSCR3_PE_14                 (0x4000U << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
 #define RI_HYSCR3_PE_15                 (0x8000U << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
+#define RI_HYSCR3_PF_Pos                (16U)                                  
+#define RI_HYSCR3_PF_Msk                (0xFFFFU << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
+#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
+#define RI_HYSCR3_PF_0                  (0x0001U << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
+#define RI_HYSCR3_PF_1                  (0x0002U << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
+#define RI_HYSCR3_PF_2                  (0x0004U << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
+#define RI_HYSCR3_PF_3                  (0x0008U << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
+#define RI_HYSCR3_PF_4                  (0x0010U << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
+#define RI_HYSCR3_PF_5                  (0x0020U << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
+#define RI_HYSCR3_PF_6                  (0x0040U << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
+#define RI_HYSCR3_PF_7                  (0x0080U << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
+#define RI_HYSCR3_PF_8                  (0x0100U << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
+#define RI_HYSCR3_PF_9                  (0x0200U << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
+#define RI_HYSCR3_PF_10                 (0x0400U << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
+#define RI_HYSCR3_PF_11                 (0x0800U << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
+#define RI_HYSCR3_PF_12                 (0x1000U << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
+#define RI_HYSCR3_PF_13                 (0x2000U << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
+#define RI_HYSCR3_PF_14                 (0x4000U << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
+#define RI_HYSCR3_PF_15                 (0x8000U << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
+/********************  Bit definition for RI_HYSCR4 register  ********************/
+#define RI_HYSCR4_PG_Pos                (0U)                                   
+#define RI_HYSCR4_PG_Msk                (0xFFFFU << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
+#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
+#define RI_HYSCR4_PG_0                  (0x0001U << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
+#define RI_HYSCR4_PG_1                  (0x0002U << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
+#define RI_HYSCR4_PG_2                  (0x0004U << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
+#define RI_HYSCR4_PG_3                  (0x0008U << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
+#define RI_HYSCR4_PG_4                  (0x0010U << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
+#define RI_HYSCR4_PG_5                  (0x0020U << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
+#define RI_HYSCR4_PG_6                  (0x0040U << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
+#define RI_HYSCR4_PG_7                  (0x0080U << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
+#define RI_HYSCR4_PG_8                  (0x0100U << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
+#define RI_HYSCR4_PG_9                  (0x0200U << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
+#define RI_HYSCR4_PG_10                 (0x0400U << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
+#define RI_HYSCR4_PG_11                 (0x0800U << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
+#define RI_HYSCR4_PG_12                 (0x1000U << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
+#define RI_HYSCR4_PG_13                 (0x2000U << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
+#define RI_HYSCR4_PG_14                 (0x4000U << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
+#define RI_HYSCR4_PG_15                 (0x8000U << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
 
 /********************  Bit definition for RI_ASMR1 register  ********************/
 #define RI_ASMR1_PA_Pos                 (0U)                                   
@@ -6304,6 +6352,132 @@
 #define RI_CICR3_PC_14                  (0x4000U << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
 #define RI_CICR3_PC_15                  (0x8000U << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
 
+/********************  Bit definition for RI_ASMR4 register  ********************/
+#define RI_ASMR4_PF_Pos                 (0U)                                   
+#define RI_ASMR4_PF_Msk                 (0xFFFFU << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
+#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
+#define RI_ASMR4_PF_0                   (0x0001U << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
+#define RI_ASMR4_PF_1                   (0x0002U << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
+#define RI_ASMR4_PF_2                   (0x0004U << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
+#define RI_ASMR4_PF_3                   (0x0008U << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
+#define RI_ASMR4_PF_4                   (0x0010U << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
+#define RI_ASMR4_PF_5                   (0x0020U << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
+#define RI_ASMR4_PF_6                   (0x0040U << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
+#define RI_ASMR4_PF_7                   (0x0080U << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
+#define RI_ASMR4_PF_8                   (0x0100U << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
+#define RI_ASMR4_PF_9                   (0x0200U << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
+#define RI_ASMR4_PF_10                  (0x0400U << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
+#define RI_ASMR4_PF_11                  (0x0800U << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
+#define RI_ASMR4_PF_12                  (0x1000U << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
+#define RI_ASMR4_PF_13                  (0x2000U << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
+#define RI_ASMR4_PF_14                  (0x4000U << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
+#define RI_ASMR4_PF_15                  (0x8000U << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CMR4 register  ********************/
+#define RI_CMR4_PF_Pos                  (0U)                                   
+#define RI_CMR4_PF_Msk                  (0xFFFFU << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
+#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
+#define RI_CMR4_PF_0                    (0x0001U << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
+#define RI_CMR4_PF_1                    (0x0002U << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
+#define RI_CMR4_PF_2                    (0x0004U << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
+#define RI_CMR4_PF_3                    (0x0008U << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
+#define RI_CMR4_PF_4                    (0x0010U << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
+#define RI_CMR4_PF_5                    (0x0020U << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
+#define RI_CMR4_PF_6                    (0x0040U << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
+#define RI_CMR4_PF_7                    (0x0080U << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
+#define RI_CMR4_PF_8                    (0x0100U << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
+#define RI_CMR4_PF_9                    (0x0200U << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
+#define RI_CMR4_PF_10                   (0x0400U << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
+#define RI_CMR4_PF_11                   (0x0800U << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
+#define RI_CMR4_PF_12                   (0x1000U << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
+#define RI_CMR4_PF_13                   (0x2000U << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
+#define RI_CMR4_PF_14                   (0x4000U << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
+#define RI_CMR4_PF_15                   (0x8000U << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CICR4 register  ********************/
+#define RI_CICR4_PF_Pos                 (0U)                                   
+#define RI_CICR4_PF_Msk                 (0xFFFFU << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
+#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
+#define RI_CICR4_PF_0                   (0x0001U << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
+#define RI_CICR4_PF_1                   (0x0002U << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
+#define RI_CICR4_PF_2                   (0x0004U << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
+#define RI_CICR4_PF_3                   (0x0008U << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
+#define RI_CICR4_PF_4                   (0x0010U << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
+#define RI_CICR4_PF_5                   (0x0020U << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
+#define RI_CICR4_PF_6                   (0x0040U << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
+#define RI_CICR4_PF_7                   (0x0080U << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
+#define RI_CICR4_PF_8                   (0x0100U << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
+#define RI_CICR4_PF_9                   (0x0200U << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
+#define RI_CICR4_PF_10                  (0x0400U << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
+#define RI_CICR4_PF_11                  (0x0800U << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
+#define RI_CICR4_PF_12                  (0x1000U << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
+#define RI_CICR4_PF_13                  (0x2000U << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
+#define RI_CICR4_PF_14                  (0x4000U << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
+#define RI_CICR4_PF_15                  (0x8000U << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_ASMR5 register  ********************/
+#define RI_ASMR5_PG_Pos                 (0U)                                   
+#define RI_ASMR5_PG_Msk                 (0xFFFFU << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
+#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
+#define RI_ASMR5_PG_0                   (0x0001U << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
+#define RI_ASMR5_PG_1                   (0x0002U << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
+#define RI_ASMR5_PG_2                   (0x0004U << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
+#define RI_ASMR5_PG_3                   (0x0008U << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
+#define RI_ASMR5_PG_4                   (0x0010U << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
+#define RI_ASMR5_PG_5                   (0x0020U << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
+#define RI_ASMR5_PG_6                   (0x0040U << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
+#define RI_ASMR5_PG_7                   (0x0080U << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
+#define RI_ASMR5_PG_8                   (0x0100U << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
+#define RI_ASMR5_PG_9                   (0x0200U << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
+#define RI_ASMR5_PG_10                  (0x0400U << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
+#define RI_ASMR5_PG_11                  (0x0800U << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
+#define RI_ASMR5_PG_12                  (0x1000U << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
+#define RI_ASMR5_PG_13                  (0x2000U << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
+#define RI_ASMR5_PG_14                  (0x4000U << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
+#define RI_ASMR5_PG_15                  (0x8000U << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CMR5 register  ********************/
+#define RI_CMR5_PG_Pos                  (0U)                                   
+#define RI_CMR5_PG_Msk                  (0xFFFFU << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
+#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
+#define RI_CMR5_PG_0                    (0x0001U << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
+#define RI_CMR5_PG_1                    (0x0002U << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
+#define RI_CMR5_PG_2                    (0x0004U << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
+#define RI_CMR5_PG_3                    (0x0008U << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
+#define RI_CMR5_PG_4                    (0x0010U << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
+#define RI_CMR5_PG_5                    (0x0020U << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
+#define RI_CMR5_PG_6                    (0x0040U << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
+#define RI_CMR5_PG_7                    (0x0080U << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
+#define RI_CMR5_PG_8                    (0x0100U << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
+#define RI_CMR5_PG_9                    (0x0200U << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
+#define RI_CMR5_PG_10                   (0x0400U << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
+#define RI_CMR5_PG_11                   (0x0800U << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
+#define RI_CMR5_PG_12                   (0x1000U << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
+#define RI_CMR5_PG_13                   (0x2000U << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
+#define RI_CMR5_PG_14                   (0x4000U << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
+#define RI_CMR5_PG_15                   (0x8000U << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CICR5 register  ********************/
+#define RI_CICR5_PG_Pos                 (0U)                                   
+#define RI_CICR5_PG_Msk                 (0xFFFFU << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
+#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
+#define RI_CICR5_PG_0                   (0x0001U << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
+#define RI_CICR5_PG_1                   (0x0002U << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
+#define RI_CICR5_PG_2                   (0x0004U << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
+#define RI_CICR5_PG_3                   (0x0008U << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
+#define RI_CICR5_PG_4                   (0x0010U << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
+#define RI_CICR5_PG_5                   (0x0020U << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
+#define RI_CICR5_PG_6                   (0x0040U << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
+#define RI_CICR5_PG_7                   (0x0080U << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
+#define RI_CICR5_PG_8                   (0x0100U << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
+#define RI_CICR5_PG_9                   (0x0200U << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
+#define RI_CICR5_PG_10                  (0x0400U << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
+#define RI_CICR5_PG_11                  (0x0800U << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
+#define RI_CICR5_PG_12                  (0x1000U << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
+#define RI_CICR5_PG_13                  (0x2000U << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
+#define RI_CICR5_PG_14                  (0x4000U << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
+#define RI_CICR5_PG_15                  (0x8000U << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
+
 /******************************************************************************/
 /*                                                                            */
 /*                               Timers (TIM)                                 */
@@ -8481,24 +8655,58 @@
 
 /*******************  Bit definition for SCB_CFSR register  *******************/
 /*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)    /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)  /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
 #define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)    /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)      /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
 #define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)    /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)     /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
 #define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)    /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)       /*!< SCB CFSR (MMFSR): MSTKERR Mask */
 #define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)    /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)     /*!< SCB CFSR (MMFSR): MMARVALID Mask */
 #define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */
 /*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)       /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)        /*!< SCB CFSR (BFSR): IBUSERR Mask */
 #define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)       /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)      /*!< SCB CFSR (BFSR): PRECISERR Mask */
 #define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)       /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)    /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
 #define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)       /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)       /*!< SCB CFSR (BFSR): UNSTKERR Mask */
 #define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)       /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)         /*!< SCB CFSR (BFSR): STKERR Mask */
 #define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)       /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)      /*!< SCB CFSR (BFSR): BFARVALID Mask */
 #define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */
 /*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)       /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)     /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
 #define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)       /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)       /*!< SCB CFSR (UFSR): INVSTATE Mask */
 #define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)       /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)          /*!< SCB CFSR (UFSR): INVPC Mask */
 #define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)       /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)           /*!< SCB CFSR (UFSR): NOCP Mask */
 #define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)       /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)      /*!< SCB CFSR (UFSR): UNALIGNED Mask */
 #define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)       /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)      /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
 #define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
 
 /*******************  Bit definition for SCB_HFSR register  *******************/

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/stm32l1xx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
   *
   *          The file is the unique include file that the application programmer
@@ -18,7 +16,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -134,7 +132,7 @@
   */
 #define __STM32L1xx_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
 #define __STM32L1xx_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32L1xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32L1xx_CMSIS_VERSION        ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_stm32l1xx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/system_stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    system_stm32l1xx.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l151xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L151XC Devices vector for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* COPYRIGHT(c) 2016 STMicroelectronics
+;* COPYRIGHT(c) 2017 STMicroelectronics
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l151xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L151XC Devices vector for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* COPYRIGHT(c) 2016 STMicroelectronics
+;* COPYRIGHT(c) 2017 STMicroelectronics
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file      startup_stm32l151xc.s
   * @author    MCD Application Team
-  * @version   V2.2.0
-  * @date      01-July-2016
   * @brief     STM32L151XC Devices vector table for 
   *            Atollic toolchain.
   *            This module performs:
@@ -17,7 +15,7 @@
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_IAR/startup_stm32l152xc.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/TOOLCHAIN_IAR/startup_stm32l152xc.S	Thu Apr 19 17:12:19 2018 +0100
@@ -1,8 +1,8 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;********************* (C) COPYRIGHT 2017 STMicroelectronics ********************
 ;* File Name          : startup_stm32l152xc.s
 ;* Author             : MCD Application Team
-;* Version            : V2.2.0
-;* Date               : 01-July-2016
+;* Version            : 21-April-2017
+;* Date               : V2.2.1
 ;* Description        : STM32L152XC Devices vector for EWARM toolchain. 
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -16,7 +16,7 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+;* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
 ;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/stm32l151xc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/stm32l151xc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l151xc.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
   *          This file contains all the peripheral register's definitions, bits 
   *          definitions and memory mapping for STM32L1xx devices.            
@@ -16,7 +14,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -439,21 +437,27 @@
 typedef struct
 {
   __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,       Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,        Address offset: 0x08 */
+  __IO uint32_t ASCR1;      /*!< RI analog switches control register,           Address offset: 0x04 */
+  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,           Address offset: 0x08 */
   __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,               Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,               Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved, 0x18                                                                  */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,         Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                   Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,  Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,         Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                   Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,  Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,         Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                   Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,  Address offset: 0x3C */
+  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,                Address offset: 0x10 */
+  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,                Address offset: 0x14 */
+  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,                Address offset: 0x18 */
+  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,              Address offset: 0x1C */
+  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                    Address offset: 0x20 */
+  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,        Address offset: 0x24 */
+  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,              Address offset: 0x28 */
+  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                    Address offset: 0x2C */
+  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,        Address offset: 0x30 */
+  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,              Address offset: 0x34 */
+  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                    Address offset: 0x38 */
+  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,        Address offset: 0x3C */
+  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,              Address offset: 0x40 */
+  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                    Address offset: 0x44 */
+  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,        Address offset: 0x48 */
+  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,              Address offset: 0x4C */
+  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                    Address offset: 0x50 */
+  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,        Address offset: 0x54 */
 } RI_TypeDef;
 
 /** 
@@ -3569,56 +3573,56 @@
 #define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk                
 
 /****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0_Pos                  (0U)                              
-#define GPIO_AFRL_AFRL0_Msk                  (0xFU << GPIO_AFRL_AFRL0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFRL0_Msk               
-#define GPIO_AFRL_AFRL1_Pos                  (4U)                              
-#define GPIO_AFRL_AFRL1_Msk                  (0xFU << GPIO_AFRL_AFRL1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFRL1_Msk               
-#define GPIO_AFRL_AFRL2_Pos                  (8U)                              
-#define GPIO_AFRL_AFRL2_Msk                  (0xFU << GPIO_AFRL_AFRL2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFRL2_Msk               
-#define GPIO_AFRL_AFRL3_Pos                  (12U)                             
-#define GPIO_AFRL_AFRL3_Msk                  (0xFU << GPIO_AFRL_AFRL3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFRL3_Msk               
-#define GPIO_AFRL_AFRL4_Pos                  (16U)                             
-#define GPIO_AFRL_AFRL4_Msk                  (0xFU << GPIO_AFRL_AFRL4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFRL4_Msk               
-#define GPIO_AFRL_AFRL5_Pos                  (20U)                             
-#define GPIO_AFRL_AFRL5_Msk                  (0xFU << GPIO_AFRL_AFRL5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFRL5_Msk               
-#define GPIO_AFRL_AFRL6_Pos                  (24U)                             
-#define GPIO_AFRL_AFRL6_Msk                  (0xFU << GPIO_AFRL_AFRL6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFRL6_Msk               
-#define GPIO_AFRL_AFRL7_Pos                  (28U)                             
-#define GPIO_AFRL_AFRL7_Msk                  (0xFU << GPIO_AFRL_AFRL7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFRL7_Msk               
+#define GPIO_AFRL_AFSEL0_Pos                  (0U)                              
+#define GPIO_AFRL_AFSEL0_Msk                  (0xFU << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk               
+#define GPIO_AFRL_AFSEL1_Pos                  (4U)                              
+#define GPIO_AFRL_AFSEL1_Msk                  (0xFU << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk               
+#define GPIO_AFRL_AFSEL2_Pos                  (8U)                              
+#define GPIO_AFRL_AFSEL2_Msk                  (0xFU << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk               
+#define GPIO_AFRL_AFSEL3_Pos                  (12U)                             
+#define GPIO_AFRL_AFSEL3_Msk                  (0xFU << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk               
+#define GPIO_AFRL_AFSEL4_Pos                  (16U)                             
+#define GPIO_AFRL_AFSEL4_Msk                  (0xFU << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk               
+#define GPIO_AFRL_AFSEL5_Pos                  (20U)                             
+#define GPIO_AFRL_AFSEL5_Msk                  (0xFU << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk               
+#define GPIO_AFRL_AFSEL6_Pos                  (24U)                             
+#define GPIO_AFRL_AFSEL6_Msk                  (0xFU << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk               
+#define GPIO_AFRL_AFSEL7_Pos                  (28U)                             
+#define GPIO_AFRL_AFSEL7_Msk                  (0xFU << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk               
 
 /****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0_Pos                  (0U)                              
-#define GPIO_AFRH_AFRH0_Msk                  (0xFU << GPIO_AFRH_AFRH0_Pos)     /*!< 0x0000000F */
-#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFRH0_Msk               
-#define GPIO_AFRH_AFRH1_Pos                  (4U)                              
-#define GPIO_AFRH_AFRH1_Msk                  (0xFU << GPIO_AFRH_AFRH1_Pos)     /*!< 0x000000F0 */
-#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFRH1_Msk               
-#define GPIO_AFRH_AFRH2_Pos                  (8U)                              
-#define GPIO_AFRH_AFRH2_Msk                  (0xFU << GPIO_AFRH_AFRH2_Pos)     /*!< 0x00000F00 */
-#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFRH2_Msk               
-#define GPIO_AFRH_AFRH3_Pos                  (12U)                             
-#define GPIO_AFRH_AFRH3_Msk                  (0xFU << GPIO_AFRH_AFRH3_Pos)     /*!< 0x0000F000 */
-#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFRH3_Msk               
-#define GPIO_AFRH_AFRH4_Pos                  (16U)                             
-#define GPIO_AFRH_AFRH4_Msk                  (0xFU << GPIO_AFRH_AFRH4_Pos)     /*!< 0x000F0000 */
-#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFRH4_Msk               
-#define GPIO_AFRH_AFRH5_Pos                  (20U)                             
-#define GPIO_AFRH_AFRH5_Msk                  (0xFU << GPIO_AFRH_AFRH5_Pos)     /*!< 0x00F00000 */
-#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFRH5_Msk               
-#define GPIO_AFRH_AFRH6_Pos                  (24U)                             
-#define GPIO_AFRH_AFRH6_Msk                  (0xFU << GPIO_AFRH_AFRH6_Pos)     /*!< 0x0F000000 */
-#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFRH6_Msk               
-#define GPIO_AFRH_AFRH7_Pos                  (28U)                             
-#define GPIO_AFRH_AFRH7_Msk                  (0xFU << GPIO_AFRH_AFRH7_Pos)     /*!< 0xF0000000 */
-#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFRH7_Msk               
+#define GPIO_AFRH_AFSEL8_Pos                  (0U)                              
+#define GPIO_AFRH_AFSEL8_Msk                  (0xFU << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk               
+#define GPIO_AFRH_AFSEL9_Pos                  (4U)                              
+#define GPIO_AFRH_AFSEL9_Msk                  (0xFU << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk               
+#define GPIO_AFRH_AFSEL10_Pos                  (8U)                              
+#define GPIO_AFRH_AFSEL10_Msk                  (0xFU << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk               
+#define GPIO_AFRH_AFSEL11_Pos                  (12U)                             
+#define GPIO_AFRH_AFSEL11_Msk                  (0xFU << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk               
+#define GPIO_AFRH_AFSEL12_Pos                  (16U)                             
+#define GPIO_AFRH_AFSEL12_Msk                  (0xFU << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk               
+#define GPIO_AFRH_AFSEL13_Pos                  (20U)                             
+#define GPIO_AFRH_AFSEL13_Msk                  (0xFU << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk               
+#define GPIO_AFRH_AFSEL14_Pos                  (24U)                             
+#define GPIO_AFRH_AFSEL14_Msk                  (0xFU << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk               
+#define GPIO_AFRH_AFSEL15_Pos                  (28U)                             
+#define GPIO_AFRH_AFSEL15_Msk                  (0xFU << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk               
 
 /****************** Bit definition for GPIO_BRR register  *********************/
 #define GPIO_BRR_BR_0                        (0x00000001U)                     
@@ -4830,9 +4834,9 @@
 #define RTC_CR_COSEL_Pos                     (19U)                             
 #define RTC_CR_COSEL_Msk                     (0x1U << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
 #define RTC_CR_COSEL                         RTC_CR_COSEL_Msk                  
-#define RTC_CR_BCK_Pos                       (18U)                             
-#define RTC_CR_BCK_Msk                       (0x1U << RTC_CR_BCK_Pos)          /*!< 0x00040000 */
-#define RTC_CR_BCK                           RTC_CR_BCK_Msk                    
+#define RTC_CR_BKP_Pos                       (18U)                             
+#define RTC_CR_BKP_Msk                       (0x1U << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
+#define RTC_CR_BKP                           RTC_CR_BKP_Msk                    
 #define RTC_CR_SUB1H_Pos                     (17U)                             
 #define RTC_CR_SUB1H_Msk                     (0x1U << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
 #define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk                  
@@ -4885,6 +4889,11 @@
 #define RTC_CR_WUCKSEL_1                     (0x2U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2                     (0x4U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
 
+/* Legacy defines */
+#define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
+#define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
+#define  RTC_CR_BCK     RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF_Pos                  (16U)                             
 #define RTC_ISR_RECALPF_Msk                  (0x1U << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
@@ -6114,6 +6123,45 @@
 #define RI_HYSCR3_PE_13                 (0x2000U << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
 #define RI_HYSCR3_PE_14                 (0x4000U << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
 #define RI_HYSCR3_PE_15                 (0x8000U << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
+#define RI_HYSCR3_PF_Pos                (16U)                                  
+#define RI_HYSCR3_PF_Msk                (0xFFFFU << RI_HYSCR3_PF_Pos)          /*!< 0xFFFF0000 */
+#define RI_HYSCR3_PF                    RI_HYSCR3_PF_Msk                       /*!< PF[15:0] Port F Hysteresis selection */
+#define RI_HYSCR3_PF_0                  (0x0001U << RI_HYSCR3_PF_Pos)          /*!< 0x00010000 */
+#define RI_HYSCR3_PF_1                  (0x0002U << RI_HYSCR3_PF_Pos)          /*!< 0x00020000 */
+#define RI_HYSCR3_PF_2                  (0x0004U << RI_HYSCR3_PF_Pos)          /*!< 0x00040000 */
+#define RI_HYSCR3_PF_3                  (0x0008U << RI_HYSCR3_PF_Pos)          /*!< 0x00080000 */
+#define RI_HYSCR3_PF_4                  (0x0010U << RI_HYSCR3_PF_Pos)          /*!< 0x00100000 */
+#define RI_HYSCR3_PF_5                  (0x0020U << RI_HYSCR3_PF_Pos)          /*!< 0x00200000 */
+#define RI_HYSCR3_PF_6                  (0x0040U << RI_HYSCR3_PF_Pos)          /*!< 0x00400000 */
+#define RI_HYSCR3_PF_7                  (0x0080U << RI_HYSCR3_PF_Pos)          /*!< 0x00800000 */
+#define RI_HYSCR3_PF_8                  (0x0100U << RI_HYSCR3_PF_Pos)          /*!< 0x01000000 */
+#define RI_HYSCR3_PF_9                  (0x0200U << RI_HYSCR3_PF_Pos)          /*!< 0x02000000 */
+#define RI_HYSCR3_PF_10                 (0x0400U << RI_HYSCR3_PF_Pos)          /*!< 0x04000000 */
+#define RI_HYSCR3_PF_11                 (0x0800U << RI_HYSCR3_PF_Pos)          /*!< 0x08000000 */
+#define RI_HYSCR3_PF_12                 (0x1000U << RI_HYSCR3_PF_Pos)          /*!< 0x10000000 */
+#define RI_HYSCR3_PF_13                 (0x2000U << RI_HYSCR3_PF_Pos)          /*!< 0x20000000 */
+#define RI_HYSCR3_PF_14                 (0x4000U << RI_HYSCR3_PF_Pos)          /*!< 0x40000000 */
+#define RI_HYSCR3_PF_15                 (0x8000U << RI_HYSCR3_PF_Pos)          /*!< 0x80000000 */
+/********************  Bit definition for RI_HYSCR4 register  ********************/
+#define RI_HYSCR4_PG_Pos                (0U)                                   
+#define RI_HYSCR4_PG_Msk                (0xFFFFU << RI_HYSCR4_PG_Pos)          /*!< 0x0000FFFF */
+#define RI_HYSCR4_PG                    RI_HYSCR4_PG_Msk                       /*!< PG[15:0] Port G Hysteresis selection */
+#define RI_HYSCR4_PG_0                  (0x0001U << RI_HYSCR4_PG_Pos)          /*!< 0x00000001 */
+#define RI_HYSCR4_PG_1                  (0x0002U << RI_HYSCR4_PG_Pos)          /*!< 0x00000002 */
+#define RI_HYSCR4_PG_2                  (0x0004U << RI_HYSCR4_PG_Pos)          /*!< 0x00000004 */
+#define RI_HYSCR4_PG_3                  (0x0008U << RI_HYSCR4_PG_Pos)          /*!< 0x00000008 */
+#define RI_HYSCR4_PG_4                  (0x0010U << RI_HYSCR4_PG_Pos)          /*!< 0x00000010 */
+#define RI_HYSCR4_PG_5                  (0x0020U << RI_HYSCR4_PG_Pos)          /*!< 0x00000020 */
+#define RI_HYSCR4_PG_6                  (0x0040U << RI_HYSCR4_PG_Pos)          /*!< 0x00000040 */
+#define RI_HYSCR4_PG_7                  (0x0080U << RI_HYSCR4_PG_Pos)          /*!< 0x00000080 */
+#define RI_HYSCR4_PG_8                  (0x0100U << RI_HYSCR4_PG_Pos)          /*!< 0x00000100 */
+#define RI_HYSCR4_PG_9                  (0x0200U << RI_HYSCR4_PG_Pos)          /*!< 0x00000200 */
+#define RI_HYSCR4_PG_10                 (0x0400U << RI_HYSCR4_PG_Pos)          /*!< 0x00000400 */
+#define RI_HYSCR4_PG_11                 (0x0800U << RI_HYSCR4_PG_Pos)          /*!< 0x00000800 */
+#define RI_HYSCR4_PG_12                 (0x1000U << RI_HYSCR4_PG_Pos)          /*!< 0x00001000 */
+#define RI_HYSCR4_PG_13                 (0x2000U << RI_HYSCR4_PG_Pos)          /*!< 0x00002000 */
+#define RI_HYSCR4_PG_14                 (0x4000U << RI_HYSCR4_PG_Pos)          /*!< 0x00004000 */
+#define RI_HYSCR4_PG_15                 (0x8000U << RI_HYSCR4_PG_Pos)          /*!< 0x00008000 */
 
 /********************  Bit definition for RI_ASMR1 register  ********************/
 #define RI_ASMR1_PA_Pos                 (0U)                                   
@@ -6304,6 +6352,132 @@
 #define RI_CICR3_PC_14                  (0x4000U << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
 #define RI_CICR3_PC_15                  (0x8000U << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
 
+/********************  Bit definition for RI_ASMR4 register  ********************/
+#define RI_ASMR4_PF_Pos                 (0U)                                   
+#define RI_ASMR4_PF_Msk                 (0xFFFFU << RI_ASMR4_PF_Pos)           /*!< 0x0000FFFF */
+#define RI_ASMR4_PF                     RI_ASMR4_PF_Msk                        /*!< PF[15:0] Port F selection */
+#define RI_ASMR4_PF_0                   (0x0001U << RI_ASMR4_PF_Pos)           /*!< 0x00000001 */
+#define RI_ASMR4_PF_1                   (0x0002U << RI_ASMR4_PF_Pos)           /*!< 0x00000002 */
+#define RI_ASMR4_PF_2                   (0x0004U << RI_ASMR4_PF_Pos)           /*!< 0x00000004 */
+#define RI_ASMR4_PF_3                   (0x0008U << RI_ASMR4_PF_Pos)           /*!< 0x00000008 */
+#define RI_ASMR4_PF_4                   (0x0010U << RI_ASMR4_PF_Pos)           /*!< 0x00000010 */
+#define RI_ASMR4_PF_5                   (0x0020U << RI_ASMR4_PF_Pos)           /*!< 0x00000020 */
+#define RI_ASMR4_PF_6                   (0x0040U << RI_ASMR4_PF_Pos)           /*!< 0x00000040 */
+#define RI_ASMR4_PF_7                   (0x0080U << RI_ASMR4_PF_Pos)           /*!< 0x00000080 */
+#define RI_ASMR4_PF_8                   (0x0100U << RI_ASMR4_PF_Pos)           /*!< 0x00000100 */
+#define RI_ASMR4_PF_9                   (0x0200U << RI_ASMR4_PF_Pos)           /*!< 0x00000200 */
+#define RI_ASMR4_PF_10                  (0x0400U << RI_ASMR4_PF_Pos)           /*!< 0x00000400 */
+#define RI_ASMR4_PF_11                  (0x0800U << RI_ASMR4_PF_Pos)           /*!< 0x00000800 */
+#define RI_ASMR4_PF_12                  (0x1000U << RI_ASMR4_PF_Pos)           /*!< 0x00001000 */
+#define RI_ASMR4_PF_13                  (0x2000U << RI_ASMR4_PF_Pos)           /*!< 0x00002000 */
+#define RI_ASMR4_PF_14                  (0x4000U << RI_ASMR4_PF_Pos)           /*!< 0x00004000 */
+#define RI_ASMR4_PF_15                  (0x8000U << RI_ASMR4_PF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CMR4 register  ********************/
+#define RI_CMR4_PF_Pos                  (0U)                                   
+#define RI_CMR4_PF_Msk                  (0xFFFFU << RI_CMR4_PF_Pos)            /*!< 0x0000FFFF */
+#define RI_CMR4_PF                      RI_CMR4_PF_Msk                         /*!< PF[15:0] Port F selection */
+#define RI_CMR4_PF_0                    (0x0001U << RI_CMR4_PF_Pos)            /*!< 0x00000001 */
+#define RI_CMR4_PF_1                    (0x0002U << RI_CMR4_PF_Pos)            /*!< 0x00000002 */
+#define RI_CMR4_PF_2                    (0x0004U << RI_CMR4_PF_Pos)            /*!< 0x00000004 */
+#define RI_CMR4_PF_3                    (0x0008U << RI_CMR4_PF_Pos)            /*!< 0x00000008 */
+#define RI_CMR4_PF_4                    (0x0010U << RI_CMR4_PF_Pos)            /*!< 0x00000010 */
+#define RI_CMR4_PF_5                    (0x0020U << RI_CMR4_PF_Pos)            /*!< 0x00000020 */
+#define RI_CMR4_PF_6                    (0x0040U << RI_CMR4_PF_Pos)            /*!< 0x00000040 */
+#define RI_CMR4_PF_7                    (0x0080U << RI_CMR4_PF_Pos)            /*!< 0x00000080 */
+#define RI_CMR4_PF_8                    (0x0100U << RI_CMR4_PF_Pos)            /*!< 0x00000100 */
+#define RI_CMR4_PF_9                    (0x0200U << RI_CMR4_PF_Pos)            /*!< 0x00000200 */
+#define RI_CMR4_PF_10                   (0x0400U << RI_CMR4_PF_Pos)            /*!< 0x00000400 */
+#define RI_CMR4_PF_11                   (0x0800U << RI_CMR4_PF_Pos)            /*!< 0x00000800 */
+#define RI_CMR4_PF_12                   (0x1000U << RI_CMR4_PF_Pos)            /*!< 0x00001000 */
+#define RI_CMR4_PF_13                   (0x2000U << RI_CMR4_PF_Pos)            /*!< 0x00002000 */
+#define RI_CMR4_PF_14                   (0x4000U << RI_CMR4_PF_Pos)            /*!< 0x00004000 */
+#define RI_CMR4_PF_15                   (0x8000U << RI_CMR4_PF_Pos)            /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CICR4 register  ********************/
+#define RI_CICR4_PF_Pos                 (0U)                                   
+#define RI_CICR4_PF_Msk                 (0xFFFFU << RI_CICR4_PF_Pos)           /*!< 0x0000FFFF */
+#define RI_CICR4_PF                     RI_CICR4_PF_Msk                        /*!< PF[15:0] Port F selection */
+#define RI_CICR4_PF_0                   (0x0001U << RI_CICR4_PF_Pos)           /*!< 0x00000001 */
+#define RI_CICR4_PF_1                   (0x0002U << RI_CICR4_PF_Pos)           /*!< 0x00000002 */
+#define RI_CICR4_PF_2                   (0x0004U << RI_CICR4_PF_Pos)           /*!< 0x00000004 */
+#define RI_CICR4_PF_3                   (0x0008U << RI_CICR4_PF_Pos)           /*!< 0x00000008 */
+#define RI_CICR4_PF_4                   (0x0010U << RI_CICR4_PF_Pos)           /*!< 0x00000010 */
+#define RI_CICR4_PF_5                   (0x0020U << RI_CICR4_PF_Pos)           /*!< 0x00000020 */
+#define RI_CICR4_PF_6                   (0x0040U << RI_CICR4_PF_Pos)           /*!< 0x00000040 */
+#define RI_CICR4_PF_7                   (0x0080U << RI_CICR4_PF_Pos)           /*!< 0x00000080 */
+#define RI_CICR4_PF_8                   (0x0100U << RI_CICR4_PF_Pos)           /*!< 0x00000100 */
+#define RI_CICR4_PF_9                   (0x0200U << RI_CICR4_PF_Pos)           /*!< 0x00000200 */
+#define RI_CICR4_PF_10                  (0x0400U << RI_CICR4_PF_Pos)           /*!< 0x00000400 */
+#define RI_CICR4_PF_11                  (0x0800U << RI_CICR4_PF_Pos)           /*!< 0x00000800 */
+#define RI_CICR4_PF_12                  (0x1000U << RI_CICR4_PF_Pos)           /*!< 0x00001000 */
+#define RI_CICR4_PF_13                  (0x2000U << RI_CICR4_PF_Pos)           /*!< 0x00002000 */
+#define RI_CICR4_PF_14                  (0x4000U << RI_CICR4_PF_Pos)           /*!< 0x00004000 */
+#define RI_CICR4_PF_15                  (0x8000U << RI_CICR4_PF_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_ASMR5 register  ********************/
+#define RI_ASMR5_PG_Pos                 (0U)                                   
+#define RI_ASMR5_PG_Msk                 (0xFFFFU << RI_ASMR5_PG_Pos)           /*!< 0x0000FFFF */
+#define RI_ASMR5_PG                     RI_ASMR5_PG_Msk                        /*!< PG[15:0] Port G selection */
+#define RI_ASMR5_PG_0                   (0x0001U << RI_ASMR5_PG_Pos)           /*!< 0x00000001 */
+#define RI_ASMR5_PG_1                   (0x0002U << RI_ASMR5_PG_Pos)           /*!< 0x00000002 */
+#define RI_ASMR5_PG_2                   (0x0004U << RI_ASMR5_PG_Pos)           /*!< 0x00000004 */
+#define RI_ASMR5_PG_3                   (0x0008U << RI_ASMR5_PG_Pos)           /*!< 0x00000008 */
+#define RI_ASMR5_PG_4                   (0x0010U << RI_ASMR5_PG_Pos)           /*!< 0x00000010 */
+#define RI_ASMR5_PG_5                   (0x0020U << RI_ASMR5_PG_Pos)           /*!< 0x00000020 */
+#define RI_ASMR5_PG_6                   (0x0040U << RI_ASMR5_PG_Pos)           /*!< 0x00000040 */
+#define RI_ASMR5_PG_7                   (0x0080U << RI_ASMR5_PG_Pos)           /*!< 0x00000080 */
+#define RI_ASMR5_PG_8                   (0x0100U << RI_ASMR5_PG_Pos)           /*!< 0x00000100 */
+#define RI_ASMR5_PG_9                   (0x0200U << RI_ASMR5_PG_Pos)           /*!< 0x00000200 */
+#define RI_ASMR5_PG_10                  (0x0400U << RI_ASMR5_PG_Pos)           /*!< 0x00000400 */
+#define RI_ASMR5_PG_11                  (0x0800U << RI_ASMR5_PG_Pos)           /*!< 0x00000800 */
+#define RI_ASMR5_PG_12                  (0x1000U << RI_ASMR5_PG_Pos)           /*!< 0x00001000 */
+#define RI_ASMR5_PG_13                  (0x2000U << RI_ASMR5_PG_Pos)           /*!< 0x00002000 */
+#define RI_ASMR5_PG_14                  (0x4000U << RI_ASMR5_PG_Pos)           /*!< 0x00004000 */
+#define RI_ASMR5_PG_15                  (0x8000U << RI_ASMR5_PG_Pos)           /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CMR5 register  ********************/
+#define RI_CMR5_PG_Pos                  (0U)                                   
+#define RI_CMR5_PG_Msk                  (0xFFFFU << RI_CMR5_PG_Pos)            /*!< 0x0000FFFF */
+#define RI_CMR5_PG                      RI_CMR5_PG_Msk                         /*!< PG[15:0] Port G selection */
+#define RI_CMR5_PG_0                    (0x0001U << RI_CMR5_PG_Pos)            /*!< 0x00000001 */
+#define RI_CMR5_PG_1                    (0x0002U << RI_CMR5_PG_Pos)            /*!< 0x00000002 */
+#define RI_CMR5_PG_2                    (0x0004U << RI_CMR5_PG_Pos)            /*!< 0x00000004 */
+#define RI_CMR5_PG_3                    (0x0008U << RI_CMR5_PG_Pos)            /*!< 0x00000008 */
+#define RI_CMR5_PG_4                    (0x0010U << RI_CMR5_PG_Pos)            /*!< 0x00000010 */
+#define RI_CMR5_PG_5                    (0x0020U << RI_CMR5_PG_Pos)            /*!< 0x00000020 */
+#define RI_CMR5_PG_6                    (0x0040U << RI_CMR5_PG_Pos)            /*!< 0x00000040 */
+#define RI_CMR5_PG_7                    (0x0080U << RI_CMR5_PG_Pos)            /*!< 0x00000080 */
+#define RI_CMR5_PG_8                    (0x0100U << RI_CMR5_PG_Pos)            /*!< 0x00000100 */
+#define RI_CMR5_PG_9                    (0x0200U << RI_CMR5_PG_Pos)            /*!< 0x00000200 */
+#define RI_CMR5_PG_10                   (0x0400U << RI_CMR5_PG_Pos)            /*!< 0x00000400 */
+#define RI_CMR5_PG_11                   (0x0800U << RI_CMR5_PG_Pos)            /*!< 0x00000800 */
+#define RI_CMR5_PG_12                   (0x1000U << RI_CMR5_PG_Pos)            /*!< 0x00001000 */
+#define RI_CMR5_PG_13                   (0x2000U << RI_CMR5_PG_Pos)            /*!< 0x00002000 */
+#define RI_CMR5_PG_14                   (0x4000U << RI_CMR5_PG_Pos)            /*!< 0x00004000 */
+#define RI_CMR5_PG_15                   (0x8000U << RI_CMR5_PG_Pos)            /*!< 0x00008000 */
+
+/********************  Bit definition for RI_CICR5 register  ********************/
+#define RI_CICR5_PG_Pos                 (0U)                                   
+#define RI_CICR5_PG_Msk                 (0xFFFFU << RI_CICR5_PG_Pos)           /*!< 0x0000FFFF */
+#define RI_CICR5_PG                     RI_CICR5_PG_Msk                        /*!< PG[15:0] Port G selection */
+#define RI_CICR5_PG_0                   (0x0001U << RI_CICR5_PG_Pos)           /*!< 0x00000001 */
+#define RI_CICR5_PG_1                   (0x0002U << RI_CICR5_PG_Pos)           /*!< 0x00000002 */
+#define RI_CICR5_PG_2                   (0x0004U << RI_CICR5_PG_Pos)           /*!< 0x00000004 */
+#define RI_CICR5_PG_3                   (0x0008U << RI_CICR5_PG_Pos)           /*!< 0x00000008 */
+#define RI_CICR5_PG_4                   (0x0010U << RI_CICR5_PG_Pos)           /*!< 0x00000010 */
+#define RI_CICR5_PG_5                   (0x0020U << RI_CICR5_PG_Pos)           /*!< 0x00000020 */
+#define RI_CICR5_PG_6                   (0x0040U << RI_CICR5_PG_Pos)           /*!< 0x00000040 */
+#define RI_CICR5_PG_7                   (0x0080U << RI_CICR5_PG_Pos)           /*!< 0x00000080 */
+#define RI_CICR5_PG_8                   (0x0100U << RI_CICR5_PG_Pos)           /*!< 0x00000100 */
+#define RI_CICR5_PG_9                   (0x0200U << RI_CICR5_PG_Pos)           /*!< 0x00000200 */
+#define RI_CICR5_PG_10                  (0x0400U << RI_CICR5_PG_Pos)           /*!< 0x00000400 */
+#define RI_CICR5_PG_11                  (0x0800U << RI_CICR5_PG_Pos)           /*!< 0x00000800 */
+#define RI_CICR5_PG_12                  (0x1000U << RI_CICR5_PG_Pos)           /*!< 0x00001000 */
+#define RI_CICR5_PG_13                  (0x2000U << RI_CICR5_PG_Pos)           /*!< 0x00002000 */
+#define RI_CICR5_PG_14                  (0x4000U << RI_CICR5_PG_Pos)           /*!< 0x00004000 */
+#define RI_CICR5_PG_15                  (0x8000U << RI_CICR5_PG_Pos)           /*!< 0x00008000 */
+
 /******************************************************************************/
 /*                                                                            */
 /*                               Timers (TIM)                                 */
@@ -8481,24 +8655,58 @@
 
 /*******************  Bit definition for SCB_CFSR register  *******************/
 /*!< MFSR */
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)    /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)  /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
 #define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)    /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)      /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
 #define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)    /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)     /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
 #define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)    /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)       /*!< SCB CFSR (MMFSR): MSTKERR Mask */
 #define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)    /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)     /*!< SCB CFSR (MMFSR): MMARVALID Mask */
 #define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */
 /*!< BFSR */
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)       /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)        /*!< SCB CFSR (BFSR): IBUSERR Mask */
 #define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)       /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)      /*!< SCB CFSR (BFSR): PRECISERR Mask */
 #define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)       /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)    /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
 #define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)       /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)       /*!< SCB CFSR (BFSR): UNSTKERR Mask */
 #define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)       /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)         /*!< SCB CFSR (BFSR): STKERR Mask */
 #define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)       /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)      /*!< SCB CFSR (BFSR): BFARVALID Mask */
 #define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */
 /*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)       /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)     /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
 #define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)       /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)       /*!< SCB CFSR (UFSR): INVSTATE Mask */
 #define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)       /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)          /*!< SCB CFSR (UFSR): INVPC Mask */
 #define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)       /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)           /*!< SCB CFSR (UFSR): NOCP Mask */
 #define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)       /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)      /*!< SCB CFSR (UFSR): UNALIGNED Mask */
 #define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)       /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)      /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
 #define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
 
 /*******************  Bit definition for SCB_HFSR register  *******************/

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/stm32l1xx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
   *
   *          The file is the unique include file that the application programmer
@@ -18,7 +16,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -121,7 +119,7 @@
   */
 #define __STM32L1xx_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
 #define __STM32L1xx_CMSIS_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L1xx_CMSIS_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
 #define __STM32L1xx_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
 #define __STM32L1xx_CMSIS_VERSION        ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c	Thu Apr 19 17:12:19 2018 +0100
@@ -249,12 +249,4 @@
     return 1; // OK
 }
 
-/******************************************************************************/
-/*            Hard Fault Handler                                              */
-/******************************************************************************/
-void HardFault_Handler(void)
-{
-    debug("Hard Fault\n");
-    NVIC_SystemReset();
-}
 

--- a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_stm32l1xx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_stm32l1xx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    system_stm32l1xx.h
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32_hal_legacy.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32_hal_legacy.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,14 +2,12 @@
   ******************************************************************************
   * @file    stm32_hal_legacy.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   This file contains aliases definition for the STM32Cube HAL constants 
   *          macros and functions maintained for legacy purpose.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -138,6 +136,9 @@
 #define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
 #define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
 #define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
 #define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
 #if defined(STM32F373xC) || defined(STM32F378xx)
 #define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
@@ -240,9 +241,9 @@
 #define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
 #define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
 #define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   ((uint32_t)0x00000000U)
-#define DAC_WAVE_NOISE                                  ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE                               ((uint32_t)DAC_CR_WAVE1_1)                           
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
 #define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
 #define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
 #define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
@@ -264,7 +265,6 @@
 #define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7      
 #define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67  
 #define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67 
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32  
 #define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76   
 #define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6     
 #define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7      
@@ -355,6 +355,7 @@
 #define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
 #define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
 #define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+
 /**
   * @}
   */
@@ -380,7 +381,7 @@
 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
   * @{
   */
-#if defined(STM32L4) || defined(STM32F7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
@@ -455,6 +456,78 @@
   * @}
   */
 
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+  
+#if defined(STM32H7)
+ #define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+ #define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+ #define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+ #define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+ #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+ #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+
+  #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 
+  #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 
+
+ #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+ #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+ #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+ #define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+ #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+ #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+ #define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+ #define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+ #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+
+#endif /* STM32H7  */
+  
+  
+/**
+  * @}
+  */ 
+  
+  
 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
   * @{
   */
@@ -668,7 +741,6 @@
 #define FORMAT_BCD                  RTC_FORMAT_BCD
 
 #define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
 #define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
 #define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
 #define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
@@ -676,9 +748,6 @@
 #define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
 #define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE 
 #define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE 
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE 
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
 #define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT 
 #define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT 
 
@@ -852,6 +921,8 @@
 #define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
 #define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
 
+#define __DIV_LPUART                    UART_DIV_LPUART
+
 #define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
 #define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
 
@@ -913,48 +984,48 @@
 #define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
 #define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
 
-#define ETH_MMCCR              ((uint32_t)0x00000100U)  
-#define ETH_MMCRIR             ((uint32_t)0x00000104U)  
-#define ETH_MMCTIR             ((uint32_t)0x00000108U)  
-#define ETH_MMCRIMR            ((uint32_t)0x0000010CU)  
-#define ETH_MMCTIMR            ((uint32_t)0x00000110U)  
-#define ETH_MMCTGFSCCR         ((uint32_t)0x0000014CU)  
-#define ETH_MMCTGFMSCCR        ((uint32_t)0x00000150U)  
-#define ETH_MMCTGFCR           ((uint32_t)0x00000168U)  
-#define ETH_MMCRFCECR          ((uint32_t)0x00000194U)  
-#define ETH_MMCRFAECR          ((uint32_t)0x00000198U)  
-#define ETH_MMCRGUFCR          ((uint32_t)0x000001C4U)
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
  
-#define ETH_MAC_TXFIFO_FULL          ((uint32_t)0x02000000)  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY      ((uint32_t)0x01000000)  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE  ((uint32_t)0x00400000)  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE     ((uint32_t)0x00000000)  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ     ((uint32_t)0x00100000)  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING  ((uint32_t)0x00200000)  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING  ((uint32_t)0x00300000)  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE     ((uint32_t)0x00080000)  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            ((uint32_t)0x00000000)  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         ((uint32_t)0x00020000)  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   ((uint32_t)0x00040000)  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    ((uint32_t)0x00060000)  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE      ((uint32_t)0x00010000)  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY             ((uint32_t)0x00000000)  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   ((uint32_t)0x00000100)  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   ((uint32_t)0x00000200)  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL              ((uint32_t)0x00000300)  /* Rx FIFO fill level: full */
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
 #if defined(STM32F1)
 #else
-#define ETH_MAC_READCONTROLLER_IDLE               ((uint32_t)0x00000000)  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA       ((uint32_t)0x00000020)  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS     ((uint32_t)0x00000040)  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
 #endif
-#define ETH_MAC_READCONTROLLER_FLUSHING           ((uint32_t)0x00000060)  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE     ((uint32_t)0x00000010)  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE    ((uint32_t)0x00000000)  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE  ((uint32_t)0x00000002)  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004)  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE    ((uint32_t)0x00000006)  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   ((uint32_t)0x00000001)  /* MAC MII receive protocol engine active */
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
 
 /**
   * @}
@@ -976,7 +1047,7 @@
   * @}
   */  
   
-#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
     defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
   * @{
@@ -1001,7 +1072,7 @@
 /**
   * @}
   */    
-#endif  /* STM32L4xx ||  STM32F7*/
+#endif  /* STM32L4 ||  STM32F7*/
 
 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
   * @{
@@ -1186,6 +1257,9 @@
   * @{
   */ 
 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
 /**
   * @}
   */  
@@ -1227,6 +1301,7 @@
 #define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
 #define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
 #define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
 
 #define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
 #define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
@@ -1308,7 +1383,6 @@
 #define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
 #define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
 #define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
 #define __HAL_ADC_JSQR                                   ADC_JSQR
 
 #define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
@@ -1621,7 +1695,11 @@
   
 #define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
 #define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
 #define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
 #define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
 #define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
 #define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
@@ -1781,20 +1859,20 @@
 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
 
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE        __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE         __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET        __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET      __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE   __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  
-#define __ADC1_CLK_SLEEP_DISABLE  __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE  
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE  
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
@@ -1811,7 +1889,7 @@
 #define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
 #define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
 #define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET  __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
 #define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
@@ -2227,26 +2305,26 @@
 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_USART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_USART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_USART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_USART4_CLK_SLEEP_DISABLE 
-#define __USART4_FORCE_RESET        __HAL_RCC_USART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_USART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_USART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_USART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_USART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_USART5_CLK_SLEEP_DISABLE 
-#define __USART5_FORCE_RESET        __HAL_RCC_USART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_USART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_USART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_USART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_USART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_USART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_USART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_USART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_USART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_USART8_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE 
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE 
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
 #define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
 #define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
 #define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
@@ -2406,7 +2484,6 @@
 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE 
 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED   
-#define __CRYP_FORCE_RESET             __HAL_RCC_CRYP_FORCE_RESET  
 #define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE  
 #define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
 #define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE  
@@ -2439,8 +2516,6 @@
 #define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
 #define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
 #define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
 #define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
 #define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
 #define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
@@ -2462,8 +2537,6 @@
 #define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
 #define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
 #define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
 #define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
 #define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
 #define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
@@ -2635,6 +2708,30 @@
 #define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
 #endif
 
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
 #define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
 #define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
 
@@ -2648,10 +2745,22 @@
 
 #define RCC_IT_HSI14                RCC_IT_HSI14RDY
 
-#if defined(STM32L0)
-#define RCC_IT_LSECSS              RCC_IT_CSSLSE 
-#define RCC_IT_CSS                 RCC_IT_CSSHSE
-#endif
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
 
 #define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
 #define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
@@ -2676,7 +2785,10 @@
 #define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
 #define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
 
+#if defined(STM32WB) || defined(STM32G0)
+#else
 #define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
 
 #define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
 #define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
@@ -2768,10 +2880,22 @@
 #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
 #define DfsdmClockSelection         Dfsdm1ClockSelection
 #define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
 #define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
 #define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
 #define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
 
 /**
   * @}
@@ -2789,8 +2913,10 @@
 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
   * @{
   */
-  
+#if defined (STM32G0)
+#else
 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
 #define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
 #define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
 
@@ -2851,7 +2977,7 @@
 #define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
 #define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
 
-#if defined(STM32F4)
+#if defined(STM32F4) || defined(STM32F2)
 #define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
 #define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY     
 #define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED   
@@ -2902,6 +3028,14 @@
 #define  SDIO_IRQn                  SDMMC1_IRQn
 #define  SDIO_IRQHandler            SDMMC1_IRQHandler
 #endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
 /**
   * @}
   */
@@ -3090,6 +3224,7 @@
   * @{
   */
 #define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   HAL module driver.
   *          This is the common part of the HAL initialization
   *
@@ -23,7 +21,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -75,15 +73,15 @@
  * @brief STM32L1xx HAL Driver version number
    */
 #define __STM32L1xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L1xx_HAL_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32L1xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L1xx_HAL_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32L1xx_HAL_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
 #define __STM32L1xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32L1xx_HAL_VERSION         ((__STM32L1xx_HAL_VERSION_MAIN << 24)\
                                         |(__STM32L1xx_HAL_VERSION_SUB1 << 16)\
                                         |(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\
                                         |(__STM32L1xx_HAL_VERSION_RC))
 
-#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+#define IDCODE_DEVID_MASK    (0x00000FFFU)
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,14 +2,12 @@
   ******************************************************************************
   * @file    stm32l1xx_hal.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   This file contains all the functions prototypes for the HAL 
   *          module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_adc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC)
   *          peripheral:
@@ -256,7 +254,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -309,18 +307,18 @@
   /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
   /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits.     */
   /* Unit: ms                                                                 */
-  #define ADC_ENABLE_TIMEOUT              ((uint32_t) 2)
-  #define ADC_DISABLE_TIMEOUT             ((uint32_t) 2)
+  #define ADC_ENABLE_TIMEOUT              (2U)
+  #define ADC_DISABLE_TIMEOUT             (2U)
 
   /* Delay for ADC stabilization time.                                        */
   /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB).       */
   /* Unit: us                                                                 */
-  #define ADC_STAB_DELAY_US               ((uint32_t) 3)
+  #define ADC_STAB_DELAY_US               (3U)
 
   /* Delay for temperature sensor stabilization time.                         */
   /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
   /* Unit: us                                                                 */
-  #define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10)
+  #define ADC_TEMPSENSOR_DELAY_US         (10U)
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file containing functions prototypes of ADC HAL library.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -201,36 +199,36 @@
   * @brief  HAL ADC state machine: ADC states definition (bitfields)
   */ 
 /* States of ADC global scope */
-#define HAL_ADC_STATE_RESET             ((uint32_t)0x00000000)    /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY             ((uint32_t)0x00000001)    /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL     ((uint32_t)0x00000002)    /*!< ADC is busy to internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT           ((uint32_t)0x00000004)    /*!< TimeOut occurrence */
+#define HAL_ADC_STATE_RESET             (0x00000000U)    /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             (0x00000001U)    /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002U)    /*!< ADC is busy to internal process (initialization, calibration) */
+#define HAL_ADC_STATE_TIMEOUT           (0x00000004U)    /*!< TimeOut occurrence */
 
 /* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL    ((uint32_t)0x00000010)    /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG      ((uint32_t)0x00000020)    /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA         ((uint32_t)0x00000040)    /*!< DMA error occurrence */
+#define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010U)    /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020U)    /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         (0x00000040U)    /*!< DMA error occurrence */
 
 /* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY          ((uint32_t)0x00000100)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
+#define HAL_ADC_STATE_REG_BUSY          (0x00000100U)    /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC           ((uint32_t)0x00000200)    /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR           ((uint32_t)0x00000400)    /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP         ((uint32_t)0x00000800)    /*!< Not available on STM32L1 device: End Of Sampling flag raised  */
+#define HAL_ADC_STATE_REG_EOC           (0x00000200U)    /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           (0x00000400U)    /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP         (0x00000800U)    /*!< Not available on STM32L1 device: End Of Sampling flag raised  */
 
 /* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY          ((uint32_t)0x00001000)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
+#define HAL_ADC_STATE_INJ_BUSY          (0x00001000U)    /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
                                                                        external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_INJ_EOC           ((uint32_t)0x00002000)    /*!< Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF         ((uint32_t)0x00004000)    /*!< Not available on STM32L1 device: Injected queue overflow occurrence */
+#define HAL_ADC_STATE_INJ_EOC           (0x00002000U)    /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF         (0x00004000U)    /*!< Not available on STM32L1 device: Injected queue overflow occurrence */
 
 /* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1              ((uint32_t)0x00010000)    /*!< Out-of-window occurrence of analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2              ((uint32_t)0x00020000)    /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3              ((uint32_t)0x00040000)    /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */
+#define HAL_ADC_STATE_AWD1              (0x00010000U)    /*!< Out-of-window occurrence of analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2              (0x00020000U)    /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3              (0x00040000U)    /*!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 */
 
 /* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE   ((uint32_t)0x00100000)    /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000U)    /*!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( */
 
 
 /** 
@@ -267,11 +265,11 @@
 /** @defgroup ADC_Error_Code ADC Error Code
   * @{
   */
-#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error                                              */
-#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01)   /*!< ADC IP internal error: if problem of clocking, 
+#define HAL_ADC_ERROR_NONE        (0x00U)   /*!< No error                                              */
+#define HAL_ADC_ERROR_INTERNAL    (0x01U)   /*!< ADC IP internal error: if problem of clocking, 
                                                           enable/disable, erroneous state                       */
-#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02)   /*!< Overrun error                                         */
-#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04)   /*!< DMA transfer error                                    */
+#define HAL_ADC_ERROR_OVR         (0x02U)   /*!< Overrun error                                         */
+#define HAL_ADC_ERROR_DMA         (0x04U)   /*!< DMA transfer error                                    */
 /**
   * @}
   */
@@ -279,7 +277,7 @@
 /** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
   * @{
   */
-#define ADC_CLOCK_ASYNC_DIV1          ((uint32_t)0x00000000)          /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
+#define ADC_CLOCK_ASYNC_DIV1          (0x00000000U)                   /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
 #define ADC_CLOCK_ASYNC_DIV2          ((uint32_t)ADC_CCR_ADCPRE_0)    /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */
 #define ADC_CLOCK_ASYNC_DIV4          ((uint32_t)ADC_CCR_ADCPRE_1)    /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */
 /**
@@ -289,7 +287,7 @@
 /** @defgroup ADC_Resolution ADC Resolution
   * @{
   */
-#define ADC_RESOLUTION_12B      ((uint32_t)0x00000000)          /*!<  ADC 12-bit resolution */
+#define ADC_RESOLUTION_12B      (0x00000000U)                   /*!<  ADC 12-bit resolution */
 #define ADC_RESOLUTION_10B      ((uint32_t)ADC_CR1_RES_0)       /*!<  ADC 10-bit resolution */
 #define ADC_RESOLUTION_8B       ((uint32_t)ADC_CR1_RES_1)       /*!<  ADC 8-bit resolution */
 #define ADC_RESOLUTION_6B       ((uint32_t)ADC_CR1_RES)         /*!<  ADC 6-bit resolution */
@@ -300,7 +298,7 @@
 /** @defgroup ADC_Data_align ADC Data_align
   * @{
   */
-#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_RIGHT      (0x00000000U)
 #define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
 /**
   * @}
@@ -309,7 +307,7 @@
 /** @defgroup ADC_Scan_mode ADC Scan mode
   * @{
   */
-#define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)
+#define ADC_SCAN_DISABLE         (0x00000000U)
 #define ADC_SCAN_ENABLE          ((uint32_t)ADC_CR1_SCAN)
 /**
   * @}
@@ -318,7 +316,7 @@
 /** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
   * @{
   */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000U)
 #define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)
 #define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
@@ -345,7 +343,7 @@
 #define ADC_EXTERNALTRIGCONV_T9_CC2      ADC_EXTERNALTRIG_T9_CC2
 #define ADC_EXTERNALTRIGCONV_T9_TRGO     ADC_EXTERNALTRIG_T9_TRGO
 #define ADC_EXTERNALTRIGCONV_EXT_IT11    ADC_EXTERNALTRIG_EXT_IT11
-#define ADC_SOFTWARE_START               ((uint32_t)0x00000010)
+#define ADC_SOFTWARE_START               (0x00000010U)
 /**
   * @}
   */
@@ -353,7 +351,7 @@
 /** @defgroup ADC_EOCSelection ADC EOCSelection
   * @{
   */
-#define ADC_EOC_SEQ_CONV            ((uint32_t)0x00000000)
+#define ADC_EOC_SEQ_CONV            (0x00000000U)
 #define ADC_EOC_SINGLE_CONV         ((uint32_t)ADC_CR2_EOCS)
 /**
   * @}
@@ -366,7 +364,7 @@
 /* feature limited to enable or disable settings:                             */
 /* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE".          */
 
-#define ADC_AUTOWAIT_DISABLE                ((uint32_t)0x00000000)
+#define ADC_AUTOWAIT_DISABLE                (0x00000000U)
 #define ADC_AUTOWAIT_UNTIL_DATA_READ        ((uint32_t)(                                  ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */
 #define ADC_AUTOWAIT_7_APBCLOCKCYCLES       ((uint32_t)(                 ADC_CR2_DELS_1                 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */
 #define ADC_AUTOWAIT_15_APBCLOCKCYCLES      ((uint32_t)(                 ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */
@@ -382,7 +380,7 @@
 /** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
   * @{
   */
-#define ADC_AUTOPOWEROFF_DISABLE            ((uint32_t)0x00000000)
+#define ADC_AUTOPOWEROFF_DISABLE            (0x00000000U)
 #define ADC_AUTOPOWEROFF_IDLE_PHASE         ((uint32_t)ADC_CR1_PDI)                     /*!< ADC power off when ADC is not converting (idle phase) */
 #define ADC_AUTOPOWEROFF_DELAY_PHASE        ((uint32_t)ADC_CR1_PDD)                     /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */
 #define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES  ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD))     /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */
@@ -395,13 +393,13 @@
   * @{
   */
 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_CHANNELS_BANK_A                 ((uint32_t)0x00000000)
+#define ADC_CHANNELS_BANK_A                 (0x00000000U)
 #define ADC_CHANNELS_BANK_B                 ((uint32_t)ADC_CR2_CFG)
 
 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
                                    ((BANK) == ADC_CHANNELS_BANK_B)   )
 #else
-#define ADC_CHANNELS_BANK_A                 ((uint32_t)0x00000000)
+#define ADC_CHANNELS_BANK_A                 (0x00000000U)
 
 #define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
@@ -414,7 +412,7 @@
   */
 /* Note: Depending on devices, some channels may not be available on package  */
 /*       pins. Refer to device datasheet for channels availability.           */
-#define ADC_CHANNEL_0           ((uint32_t)0x00000000)                                                                            /* Channel different in bank A and bank B */
+#define ADC_CHANNEL_0           (0x00000000U)                                                                                     /* Channel different in bank A and bank B */
 #define ADC_CHANNEL_1           ((uint32_t)(                                                                    ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
 #define ADC_CHANNEL_2           ((uint32_t)(                                                   ADC_SQR5_SQ1_1                 ))  /* Channel different in bank A and bank B */
 #define ADC_CHANNEL_3           ((uint32_t)(                                                   ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
@@ -467,7 +465,7 @@
 /** @defgroup ADC_sampling_times ADC sampling times
   * @{
   */
-#define ADC_SAMPLETIME_4CYCLES      ((uint32_t)0x00000000)                            /*!< Sampling time 4 ADC clock cycles */
+#define ADC_SAMPLETIME_4CYCLES      (0x00000000U)                                     /*!< Sampling time 4 ADC clock cycles */
 #define ADC_SAMPLETIME_9CYCLES      ((uint32_t) ADC_SMPR3_SMP0_0)                     /*!< Sampling time 9 ADC clock cycles */
 #define ADC_SAMPLETIME_16CYCLES     ((uint32_t) ADC_SMPR3_SMP0_1)                     /*!< Sampling time 16 ADC clock cycles */
 #define ADC_SAMPLETIME_24CYCLES     ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */
@@ -554,35 +552,35 @@
 /** @defgroup ADC_regular_rank ADC rank into regular group
   * @{
   */
-#define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)
-#define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)
-#define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)
-#define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)
-#define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)
-#define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)
-#define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)
-#define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)
-#define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)
-#define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)
-#define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)
-#define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)
-#define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)
-#define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)
-#define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)
-#define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)
-#define ADC_REGULAR_RANK_17   ((uint32_t)0x00000011)
-#define ADC_REGULAR_RANK_18   ((uint32_t)0x00000012)
-#define ADC_REGULAR_RANK_19   ((uint32_t)0x00000013)
-#define ADC_REGULAR_RANK_20   ((uint32_t)0x00000014)
-#define ADC_REGULAR_RANK_21   ((uint32_t)0x00000015)
-#define ADC_REGULAR_RANK_22   ((uint32_t)0x00000016)
-#define ADC_REGULAR_RANK_23   ((uint32_t)0x00000017)
-#define ADC_REGULAR_RANK_24   ((uint32_t)0x00000018)
-#define ADC_REGULAR_RANK_25   ((uint32_t)0x00000019)
-#define ADC_REGULAR_RANK_26   ((uint32_t)0x0000001A)
-#define ADC_REGULAR_RANK_27   ((uint32_t)0x0000001B)
+#define ADC_REGULAR_RANK_1    (0x00000001U)
+#define ADC_REGULAR_RANK_2    (0x00000002U)
+#define ADC_REGULAR_RANK_3    (0x00000003U)
+#define ADC_REGULAR_RANK_4    (0x00000004U)
+#define ADC_REGULAR_RANK_5    (0x00000005U)
+#define ADC_REGULAR_RANK_6    (0x00000006U)
+#define ADC_REGULAR_RANK_7    (0x00000007U)
+#define ADC_REGULAR_RANK_8    (0x00000008U)
+#define ADC_REGULAR_RANK_9    (0x00000009U)
+#define ADC_REGULAR_RANK_10   (0x0000000AU)
+#define ADC_REGULAR_RANK_11   (0x0000000BU)
+#define ADC_REGULAR_RANK_12   (0x0000000CU)
+#define ADC_REGULAR_RANK_13   (0x0000000DU)
+#define ADC_REGULAR_RANK_14   (0x0000000EU)
+#define ADC_REGULAR_RANK_15   (0x0000000FU)
+#define ADC_REGULAR_RANK_16   (0x00000010U)
+#define ADC_REGULAR_RANK_17   (0x00000011U)
+#define ADC_REGULAR_RANK_18   (0x00000012U)
+#define ADC_REGULAR_RANK_19   (0x00000013U)
+#define ADC_REGULAR_RANK_20   (0x00000014U)
+#define ADC_REGULAR_RANK_21   (0x00000015U)
+#define ADC_REGULAR_RANK_22   (0x00000016U)
+#define ADC_REGULAR_RANK_23   (0x00000017U)
+#define ADC_REGULAR_RANK_24   (0x00000018U)
+#define ADC_REGULAR_RANK_25   (0x00000019U)
+#define ADC_REGULAR_RANK_26   (0x0000001AU)
+#define ADC_REGULAR_RANK_27   (0x0000001BU)
 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define ADC_REGULAR_RANK_28   ((uint32_t)0x0000001C)
+#define ADC_REGULAR_RANK_28   (0x0000001CU)
 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 /**
   * @}
@@ -591,7 +589,7 @@
 /** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
   * @{
   */
-#define ADC_ANALOGWATCHDOG_NONE                 ((uint32_t)0x00000000)
+#define ADC_ANALOGWATCHDOG_NONE                 (0x00000000U)
 #define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
@@ -663,7 +661,7 @@
 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
 
 /* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIG_T9_CC2         ((uint32_t) 0x00000000)
+#define ADC_EXTERNALTRIG_T9_CC2         (0x00000000U)
 #define ADC_EXTERNALTRIG_T9_TRGO        ((uint32_t)(                                                         ADC_CR2_EXTSEL_0))
 #define ADC_EXTERNALTRIG_T2_CC3         ((uint32_t)(                                      ADC_CR2_EXTSEL_1                   ))
 #define ADC_EXTERNALTRIG_T2_CC2         ((uint32_t)(                                      ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
@@ -1200,19 +1198,19 @@
   *
   */  
 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__)                                          \
-   ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= ((uint32_t)0x0FFF))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= ((uint32_t)0x03FF))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_DATA__) <= ((uint32_t)0x00FF))) || \
-    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_DATA__) <= ((uint32_t)0x003F)))   )
+   ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= (0x0FFFU))) || \
+    (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= (0x03FFU))) || \
+    (((__RESOLUTION__) == ADC_RESOLUTION_8B)  && ((__ADC_DATA__) <= (0x00FFU))) || \
+    (((__RESOLUTION__) == ADC_RESOLUTION_6B)  && ((__ADC_DATA__) <= (0x003FU)))   )
 
 
 #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28)))
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (28U)))
 #else
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27)))
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (27U)))
 #endif
 
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U)))
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_adc_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC)
   *          peripheral:
@@ -25,7 +23,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -75,19 +73,19 @@
   /* ADC conversion cycles (unit: ADC clock cycles)                           */
   /* (selected sampling time + conversion time of 12 ADC clock cycles, with   */
   /* resolution 12 bits)                                                      */
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5   ((uint32_t) 16)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES   ((uint32_t) 21)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES  ((uint32_t) 28)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES  ((uint32_t) 36)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES  ((uint32_t) 60)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES  ((uint32_t)108)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES ((uint32_t)204)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES ((uint32_t)396)
+  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5   ( 16U)
+  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES   ( 21U)
+  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES  ( 28U)
+  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES  ( 36U)
+  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES  ( 60U)
+  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES  (108U)
+  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES (204U)
+  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES (396U)
 
   /* Delay for temperature sensor stabilization time.                         */
   /* Maximum delay is 10us (refer to device datasheet, parameter tSTART).     */
   /* Unit: us                                                                 */
-  #define ADC_TEMPSENSOR_DELAY_US         ((uint32_t) 10)
+  #define ADC_TEMPSENSOR_DELAY_US         (10U)
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_adc_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of ADC HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -140,10 +138,10 @@
 /** @defgroup ADCEx_injected_rank ADCEx rank into injected group
   * @{
   */
-#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)
-#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)
-#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)
-#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)
+#define ADC_INJECTED_RANK_1    (0x00000001U)
+#define ADC_INJECTED_RANK_2    (0x00000002U)
+#define ADC_INJECTED_RANK_3    (0x00000003U)
+#define ADC_INJECTED_RANK_4    (0x00000004U)
 /**
   * @}
   */
@@ -151,7 +149,7 @@
 /** @defgroup ADCEx_External_trigger_edge_Injected ADCEx external trigger enable for injected group
   * @{
   */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           ((uint32_t)0x00000000)
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000U)
 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
@@ -175,7 +173,7 @@
 #define ADC_EXTERNALTRIGINJECCONV_T9_TRGO     ADC_EXTERNALTRIGINJEC_T9_TRGO
 #define ADC_EXTERNALTRIGINJECCONV_T10_CC1     ADC_EXTERNALTRIGINJEC_T10_CC1
 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15    ADC_EXTERNALTRIGINJEC_EXT_IT15
-#define ADC_INJECTED_SOFTWARE_START      ((uint32_t)0x00000010)
+#define ADC_INJECTED_SOFTWARE_START      (0x00000010U)
 /**
   * @}
   */
@@ -197,7 +195,7 @@
 
 /* List of external triggers of injected group for ADC1:                      */
 /* (used internally by HAL driver. To not use into HAL structure parameters)  */
-#define ADC_EXTERNALTRIGINJEC_T9_CC1         ((uint32_t) 0x00000000)
+#define ADC_EXTERNALTRIGINJEC_T9_CC1         (0x00000000U)
 #define ADC_EXTERNALTRIGINJEC_T9_TRGO        ((uint32_t)(                                                         ADC_CR2_JEXTSEL_0))
 #define ADC_EXTERNALTRIGINJEC_T2_TRGO        ((uint32_t)(                                      ADC_CR2_JEXTSEL_1                   ))
 #define ADC_EXTERNALTRIGINJEC_T2_CC1         ((uint32_t)(                                      ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
@@ -333,7 +331,7 @@
   ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30)))
 #else
 #define ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_)                                   \
-  ((uint32_t)0x00000000)
+  (0x00000000U)
 #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 
 #if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
@@ -517,7 +515,7 @@
 /** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
   * @{
   */
-#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
+#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= (1U)) && ((LENGTH) <= (4U)))
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_comp.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_comp.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_comp.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   COMP HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the COMP peripheral:
@@ -92,7 +90,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -192,13 +190,13 @@
   /*  - Comparator 2: delay minimum of 800 CPU cycles. Wait loop takes 3 CPU  */
   /*                 cycles per iteration, therefore total wait iterations    */
   /*                 number must be initialized at 266 iterations.            */
-#define COMP1_START_DELAY_CPU_CYCLES       ((uint32_t)106)
-#define COMP2_START_DELAY_CPU_CYCLES       ((uint32_t)266)
+#define COMP1_START_DELAY_CPU_CYCLES       (106U)
+#define COMP2_START_DELAY_CPU_CYCLES       (266U)
 
   /* Comparator status "locked": to update COMP handle state (software lock   */
   /* only on COMP of STM32L1xx devices) by bitfield:                          */
   /* states HAL_COMP_STATE_READY_LOCKED, HAL_COMP_STATE_BUSY_LOCKED.          */
-#define COMP_STATE_BIT_LOCK     ((uint32_t) 0x00000010)  
+#define COMP_STATE_BIT_LOCK     (0x00000010U)  
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_comp.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_comp.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_comp.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of COMP HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_comp_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_comp_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_comp_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of COMP HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_conf.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_conf.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_conf.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
-  * @brief   HAL configuration file.
+  * @brief   HAL configuration template file. 
+  *          This file should be copied to the application folder and renamed
+  *          to stm32l1xx_hal_conf.h.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -33,14 +33,14 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */
+  */ 
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L1xx_HAL_CONF_H
 #define __STM32L1xx_HAL_CONF_H
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 /* Exported types ------------------------------------------------------------*/
@@ -48,9 +48,9 @@
 
 /* ########################## Module Selection ############################## */
 /**
-  * @brief This is the list of modules to be used in the HAL driver
+  * @brief This is the list of modules to be used in the HAL driver 
   */
-#define HAL_MODULE_ENABLED
+#define HAL_MODULE_ENABLED  
 #define HAL_ADC_MODULE_ENABLED
 #define HAL_COMP_MODULE_ENABLED
 #define HAL_CORTEX_MODULE_ENABLED
@@ -84,14 +84,14 @@
 /**
   * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
+  *        (when HSE is used as system clock source, directly or through the PLL).  
   */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    (8000000U) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSE_STARTUP_TIMEOUT)
-#define HSE_STARTUP_TIMEOUT    ((uint32_t)200)   /*!< Time out for HSE start up, in ms */
+  #define HSE_STARTUP_TIMEOUT    (200U)   /*!< Time out for HSE start up, in ms */
 #endif /* HSE_STARTUP_TIMEOUT */
 
 /**
@@ -99,177 +99,189 @@
   *        This value is the default MSI range value after Reset.
   */
 #if !defined  (MSI_VALUE)
-#define MSI_VALUE    ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/
+  #define MSI_VALUE    (2097000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* MSI_VALUE */
 /**
   * @brief Internal High Speed oscillator (HSI) value.
   *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
+  *        (when HSI is used as system clock source, directly or through the PLL). 
   */
 #if !defined  (HSI_VALUE)
-#define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+  #define HSI_VALUE    (16000000U) /*!< Value of the Internal oscillator in Hz*/
 #endif /* HSI_VALUE */
 
 /**
   * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
   */
 #if !defined  (LSE_VALUE)
-#define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
+  #define LSE_VALUE    (32768U) /*!< Value of the External Low Speed oscillator in Hz*/
 #endif /* LSE_VALUE */
 
-
+/**
+  * @brief Time out for LSE start up value in ms.
+  */
 #if !defined  (LSE_STARTUP_TIMEOUT)
-#define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
+  #define LSE_STARTUP_TIMEOUT    (5000U)   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
 
-
+   
 /* Tip: To avoid modifying this file each time you need to use different HSE,
    ===  you can define the HSE value in your toolchain compiler preprocessor. */
 
 /* ########################### System Configuration ######################### */
 /**
   * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            ((uint32_t)0x000F)    /*!< tick interrupt priority */
-#define  USE_RTOS                     0
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     0
-#define  DATA_CACHE_ENABLE            0
+  */     
+#define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */          
+#define  TICK_INT_PRIORITY            (0x000FU)    /*!< tick interrupt priority */            
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     0U
+#define  DATA_CACHE_ENABLE            0U
 
 /* ########################## Assert Selection ############################## */
 /**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
   *        HAL drivers code
   */
-/*#define USE_FULL_ASSERT    1*/
+/*#define USE_FULL_ASSERT    1U*/ 
 
 /* Includes ------------------------------------------------------------------*/
 /**
-  * @brief Include module's header file
+  * @brief Include module's header file 
   */
 
 #ifdef HAL_RCC_MODULE_ENABLED
-#include "stm32l1xx_hal_rcc.h"
+ #include "stm32l1xx_hal_rcc.h"
 #endif /* HAL_RCC_MODULE_ENABLED */
-
+  
 #ifdef HAL_GPIO_MODULE_ENABLED
-#include "stm32l1xx_hal_gpio.h"
+ #include "stm32l1xx_hal_gpio.h"
 #endif /* HAL_GPIO_MODULE_ENABLED */
 
 #ifdef HAL_DMA_MODULE_ENABLED
-#include "stm32l1xx_hal_dma.h"
+  #include "stm32l1xx_hal_dma.h"
 #endif /* HAL_DMA_MODULE_ENABLED */
 
 #ifdef HAL_CORTEX_MODULE_ENABLED
-#include "stm32l1xx_hal_cortex.h"
+ #include "stm32l1xx_hal_cortex.h"
 #endif /* HAL_CORTEX_MODULE_ENABLED */
 
 #ifdef HAL_ADC_MODULE_ENABLED
-#include "stm32l1xx_hal_adc.h"
+ #include "stm32l1xx_hal_adc.h"
 #endif /* HAL_ADC_MODULE_ENABLED */
 
 #ifdef HAL_COMP_MODULE_ENABLED
-#include "stm32l1xx_hal_comp.h"
+  #include "stm32l1xx_hal_comp.h"
 #endif /* HAL_COMP_MODULE_ENABLED */
 
 #ifdef HAL_CRC_MODULE_ENABLED
-#include "stm32l1xx_hal_crc.h"
+ #include "stm32l1xx_hal_crc.h"
 #endif /* HAL_CRC_MODULE_ENABLED */
 
 #ifdef HAL_CRYP_MODULE_ENABLED
-#include "stm32l1xx_hal_cryp.h"
+ #include "stm32l1xx_hal_cryp.h"
 #endif /* HAL_CRYP_MODULE_ENABLED */
 
 #ifdef HAL_DAC_MODULE_ENABLED
-#include "stm32l1xx_hal_dac.h"
+ #include "stm32l1xx_hal_dac.h"
 #endif /* HAL_DAC_MODULE_ENABLED */
 
 #ifdef HAL_FLASH_MODULE_ENABLED
-#include "stm32l1xx_hal_flash.h"
+ #include "stm32l1xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
 
 #ifdef HAL_SRAM_MODULE_ENABLED
-#include "stm32l1xx_hal_sram.h"
+ #include "stm32l1xx_hal_sram.h"
 #endif /* HAL_SRAM_MODULE_ENABLED */
 
 #ifdef HAL_NOR_MODULE_ENABLED
-#include "stm32l1xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
+ #include "stm32l1xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */ 
 
 #ifdef HAL_I2C_MODULE_ENABLED
-#include "stm32l1xx_hal_i2c.h"
+ #include "stm32l1xx_hal_i2c.h"
 #endif /* HAL_I2C_MODULE_ENABLED */
 
 #ifdef HAL_I2S_MODULE_ENABLED
-#include "stm32l1xx_hal_i2s.h"
+ #include "stm32l1xx_hal_i2s.h"
 #endif /* HAL_I2S_MODULE_ENABLED */
 
 #ifdef HAL_IWDG_MODULE_ENABLED
-#include "stm32l1xx_hal_iwdg.h"
+ #include "stm32l1xx_hal_iwdg.h"
 #endif /* HAL_IWDG_MODULE_ENABLED */
 
 #ifdef HAL_LCD_MODULE_ENABLED
-#include "stm32l1xx_hal_lcd.h"
+ #include "stm32l1xx_hal_lcd.h"
 #endif /* HAL_LCD_MODULE_ENABLED */
-
+   
 #ifdef HAL_OPAMP_MODULE_ENABLED
-#include "stm32l1xx_hal_opamp.h"
+ #include "stm32l1xx_hal_opamp.h"
 #endif /* HAL_OPAMP_MODULE_ENABLED */
 
 #ifdef HAL_PWR_MODULE_ENABLED
-#include "stm32l1xx_hal_pwr.h"
+ #include "stm32l1xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */
 
 #ifdef HAL_RTC_MODULE_ENABLED
-#include "stm32l1xx_hal_rtc.h"
+ #include "stm32l1xx_hal_rtc.h"
 #endif /* HAL_RTC_MODULE_ENABLED */
 
 #ifdef HAL_SD_MODULE_ENABLED
-#include "stm32l1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
+ #include "stm32l1xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */     
 
 #ifdef HAL_SPI_MODULE_ENABLED
-#include "stm32l1xx_hal_spi.h"
+ #include "stm32l1xx_hal_spi.h"
 #endif /* HAL_SPI_MODULE_ENABLED */
 
 #ifdef HAL_TIM_MODULE_ENABLED
-#include "stm32l1xx_hal_tim.h"
+ #include "stm32l1xx_hal_tim.h"
 #endif /* HAL_TIM_MODULE_ENABLED */
 
 #ifdef HAL_UART_MODULE_ENABLED
-#include "stm32l1xx_hal_uart.h"
+ #include "stm32l1xx_hal_uart.h"
 #endif /* HAL_UART_MODULE_ENABLED */
 
 #ifdef HAL_USART_MODULE_ENABLED
-#include "stm32l1xx_hal_usart.h"
+ #include "stm32l1xx_hal_usart.h"
 #endif /* HAL_USART_MODULE_ENABLED */
 
 #ifdef HAL_IRDA_MODULE_ENABLED
-#include "stm32l1xx_hal_irda.h"
+ #include "stm32l1xx_hal_irda.h"
 #endif /* HAL_IRDA_MODULE_ENABLED */
 
 #ifdef HAL_SMARTCARD_MODULE_ENABLED
-#include "stm32l1xx_hal_smartcard.h"
+ #include "stm32l1xx_hal_smartcard.h"
 #endif /* HAL_SMARTCARD_MODULE_ENABLED */
 
 #ifdef HAL_WWDG_MODULE_ENABLED
-#include "stm32l1xx_hal_wwdg.h"
+ #include "stm32l1xx_hal_wwdg.h"
 #endif /* HAL_WWDG_MODULE_ENABLED */
 
 #ifdef HAL_PCD_MODULE_ENABLED
-#include "stm32l1xx_hal_pcd.h"
+ #include "stm32l1xx_hal_pcd.h"
 #endif /* HAL_PCD_MODULE_ENABLED */
-
+   
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
-/* ALL MBED targets use same stm32_assert.h */
+// ALL MBED targets use same stm32_assert.h
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  //#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  //void assert_failed(uint8_t* file, uint32_t line);
 #include "stm32_assert.h"
 #else
-#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */   
+   
 #ifdef __cplusplus
 }
 #endif

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cortex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cortex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_cortex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   CORTEX HAL module driver.
   *
   *          This file provides firmware functions to manage the following
@@ -23,29 +21,8 @@
     This section provide functions allowing to configure the NVIC interrupts (IRQ).
     The Cortex-M3 exceptions are managed by CMSIS functions.
    
-    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
-        function according to the following table.
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
 
-     The table below gives the allowed values of the pre-emption priority and subpriority according
-     to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
-       ==========================================================================================================================
-         NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
-       ==========================================================================================================================
-        NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bits for pre-emption priority
-                              |                                   |                             | 4 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------
-        NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
-                              |                                   |                             | 3 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------    
-        NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
-                              |                                   |                             | 2 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------    
-        NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
-                              |                                   |                             | 1 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------    
-        NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
-                              |                                   |                             | 0 bits for subpriority                       
-       ==========================================================================================================================
      (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() 
 
      (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() 
@@ -93,7 +70,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -120,6 +97,30 @@
   ******************************************************************************
   */
 
+/*
+  Additional Tables: CORTEX_NVIC_Priority_Table
+     The table below gives the allowed values of the pre-emption priority and subpriority according
+     to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
+       ==========================================================================================================================
+         NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+       ==========================================================================================================================
+        NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bits for pre-emption priority
+                              |                                   |                             | 4 bits for subpriority
+       --------------------------------------------------------------------------------------------------------------------------
+        NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
+                              |                                   |                             | 3 bits for subpriority
+       --------------------------------------------------------------------------------------------------------------------------    
+        NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+                              |                                   |                             | 2 bits for subpriority
+       --------------------------------------------------------------------------------------------------------------------------    
+        NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+                              |                                   |                             | 1 bits for subpriority
+       --------------------------------------------------------------------------------------------------------------------------    
+        NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
+                              |                                   |                             | 0 bits for subpriority                       
+       ==========================================================================================================================
+*/
+
 /* Includes ------------------------------------------------------------------*/
 #include "stm32l1xx_hal.h"
 
@@ -293,6 +294,40 @@
 
 #if (__MPU_PRESENT == 1)
 /**
+  * @brief  Enable the MPU.
+  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
+  *          NMI, FAULTMASK and privileged accessto the default memory 
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
+
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+
+/**
+  * @brief  Disable the MPU.
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL  = 0;
+}
+
+/**
   * @brief  Initializes and configures the Region and the memory to be protected.
   * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
   *                the initialization and configuration information.

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cortex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cortex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_cortex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of CORTEX HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -108,16 +106,16 @@
   * @{
   */
 
-#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
-                                                                 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
-                                                                 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
-                                                                 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
-                                                                 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
-                                                                 0 bits for subpriority */
+#define NVIC_PRIORITYGROUP_0         (0x00000007U) /*!< 0 bits for pre-emption priority
+                                                        4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         (0x00000006U) /*!< 1 bits for pre-emption priority
+                                                        3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         (0x00000005U) /*!< 2 bits for pre-emption priority
+                                                        2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         (0x00000004U) /*!< 3 bits for pre-emption priority
+                                                        1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         (0x00000003U) /*!< 4 bits for pre-emption priority
+                                                        0 bits for subpriority */
 /**
   * @}
   */
@@ -125,8 +123,8 @@
 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
   * @{
   */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
-#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    (0x00000000U)
+#define SYSTICK_CLKSOURCE_HCLK         (0x00000004U)
 
 /**
   * @}
@@ -136,10 +134,11 @@
 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
   * @{
   */
-#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)  
-#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
-#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
-#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
+#define  MPU_HFNMI_PRIVDEF_NONE      (0x00000000U)  
+#define  MPU_HARDFAULT_NMI           (MPU_CTRL_HFNMIENA_Msk)
+#define  MPU_PRIVILEGED_DEFAULT      (MPU_CTRL_PRIVDEFENA_Msk)
+#define  MPU_HFNMI_PRIVDEF           (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+
 /**
   * @}
   */
@@ -386,40 +385,6 @@
   * @{
   */
 
-#if (__MPU_PRESENT == 1)
-/**
-  * @brief  Disables the MPU
-  * @retval None
-  */
-__STATIC_INLINE void HAL_MPU_Disable(void)
-{
-  /* Disable fault exceptions */
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-  
-  /* Disable the MPU */
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/**
-  * @brief  Enables the MPU
-  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
-  *          NMI, FAULTMASK and privileged accessto the default memory 
-  *          This parameter can be one of the following values:
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
-{
-  /* Enable the MPU */
-  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
-  
-  /* Enable fault exceptions */
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-}
-#endif /* __MPU_PRESENT */
 
 /**
   * @}
@@ -449,6 +414,8 @@
   */ 
 /* Peripheral Control functions ***********************************************/
 #if (__MPU_PRESENT == 1)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
 #endif /* __MPU_PRESENT */
 uint32_t HAL_NVIC_GetPriorityGrouping(void);

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_crc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_crc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_crc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   CRC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -32,7 +30,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_crc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_crc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_crc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of CRC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cryp.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cryp.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_cryp.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   CRYP HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -70,7 +68,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cryp.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cryp.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_cryp.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of CRYP HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -143,7 +141,7 @@
 /** @defgroup CRYP_Data_Type CRYP Data Type
   * @{
   */
-#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)
+#define CRYP_DATATYPE_32B         (0x00000000U)
 #define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0
 #define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1
 #define CRYP_DATATYPE_1B          AES_CR_DATATYPE
@@ -161,7 +159,7 @@
   */ 
 #define CRYP_CR_ALGOMODE_DIRECTION              (uint32_t)(AES_CR_MODE|AES_CR_CHMOD)
 
-#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT        ((uint32_t)0x00000000)
+#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT        (0x00000000U)
 #define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT  (AES_CR_MODE)
 #define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT        (AES_CR_CHMOD_0)
 #define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT  ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE))

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cryp_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cryp_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_cryp_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   CRYPEx HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -13,7 +11,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cryp_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cryp_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_cryp_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of CRYPEx HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dac.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dac.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_dac.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -173,7 +171,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dac.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dac.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of DAC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -129,7 +127,7 @@
 /** @defgroup DAC_trigger_selection DAC trigger selection
   * @{
   */
-#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+#define DAC_TRIGGER_NONE                   (0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
                                                                        has been loaded, and not by external trigger */
 #define DAC_TRIGGER_T6_TRGO                ((uint32_t)                                                    DAC_CR_TEN1)  /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
 #define DAC_TRIGGER_T7_TRGO                ((uint32_t)(                 DAC_CR_TSEL1_1                  | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
@@ -146,7 +144,7 @@
 /** @defgroup DAC_output_buffer DAC output buffer
   * @{
   */
-#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_ENABLE            (0x00000000U)
 #define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
 
 /**
@@ -156,8 +154,8 @@
 /** @defgroup DAC_Channel_selection DAC Channel selection
   * @{
   */
-#define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
-#define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
+#define DAC_CHANNEL_1                      (0x00000000U)
+#define DAC_CHANNEL_2                      (0x00000010U)
 
 /**
   * @}
@@ -166,9 +164,9 @@
 /** @defgroup DAC_data_alignement DAC data alignement
   * @{
   */
-#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
-#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
-#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
+#define DAC_ALIGN_12B_R                    (0x00000000U)
+#define DAC_ALIGN_12B_L                    (0x00000004U)
+#define DAC_ALIGN_8B_R                     (0x00000008U)
 
 /**
   * @}
@@ -307,11 +305,11 @@
 
 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
 
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
 
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
 
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dac_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dac_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_dac_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of DAC extension peripheral:
@@ -25,7 +23,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dac_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dac_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_dac_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of DAC HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -65,7 +63,7 @@
 /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
   * @{
   */
-#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BIT0                (0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
 #define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
 #define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
 #define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
@@ -77,7 +75,7 @@
 #define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
 #define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
 #define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_1            (0x00000000U) /*!< Select max triangle amplitude of 1 */
 #define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
 #define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
 #define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
@@ -121,8 +119,8 @@
 /** @defgroup DACEx_wave_generation DACEx wave generation
   * @{
   */
-#define DAC_WAVE_NOISE                     ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE                  ((uint32_t)DAC_CR_WAVE1_1)
+#define DAC_WAVE_NOISE                     DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                  DAC_CR_WAVE1_1
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_def.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_def.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,14 +2,12 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_def.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   This file contains HAL common defines, enumeration, macros and 
   *          structures definitions. 
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dma.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dma.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_dma.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   DMA HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Direct Memory Access (DMA) peripheral:
@@ -72,7 +70,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dma.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dma.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_dma.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -167,11 +165,11 @@
 /** @defgroup DMA_Error_Code DMA Error Code
   * @{
   */
-#define HAL_DMA_ERROR_NONE          ((uint32_t)0x00000000)    /*!< No error */
-#define HAL_DMA_ERROR_TE            ((uint32_t)0x00000001)    /*!< Transfer error */
-#define HAL_DMA_ERROR_NO_XFER       ((uint32_t)0x00000004)    /*!< no ongoing transfer */
-#define HAL_DMA_ERROR_TIMEOUT       ((uint32_t)0x00000020)    /*!< Timeout error */
-#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100)    /*!< Not supported mode */     
+#define HAL_DMA_ERROR_NONE          (0x00000000U)    /*!< No error */
+#define HAL_DMA_ERROR_TE            (0x00000001U)    /*!< Transfer error */
+#define HAL_DMA_ERROR_NO_XFER       (0x00000004U)    /*!< no ongoing transfer */
+#define HAL_DMA_ERROR_TIMEOUT       (0x00000020U)    /*!< Timeout error */
+#define HAL_DMA_ERROR_NOT_SUPPORTED (0x00000100U)    /*!< Not supported mode */     
 /**
   * @}
   */
@@ -179,14 +177,14 @@
 /** @defgroup DMA_request DMA request
   * @{
   */
-#define DMA_REQUEST_0                     ((uint32_t)0x00000000)
-#define DMA_REQUEST_1                     ((uint32_t)0x00000001)
-#define DMA_REQUEST_2                     ((uint32_t)0x00000002)
-#define DMA_REQUEST_3                     ((uint32_t)0x00000003)
-#define DMA_REQUEST_4                     ((uint32_t)0x00000004)
-#define DMA_REQUEST_5                     ((uint32_t)0x00000005)
-#define DMA_REQUEST_6                     ((uint32_t)0x00000006)
-#define DMA_REQUEST_7                     ((uint32_t)0x00000007)
+#define DMA_REQUEST_0                     (0x00000000U)
+#define DMA_REQUEST_1                     (0x00000001U)
+#define DMA_REQUEST_2                     (0x00000002U)
+#define DMA_REQUEST_3                     (0x00000003U)
+#define DMA_REQUEST_4                     (0x00000004U)
+#define DMA_REQUEST_5                     (0x00000005U)
+#define DMA_REQUEST_6                     (0x00000006U)
+#define DMA_REQUEST_7                     (0x00000007U)
 
 /**
   * @}
@@ -195,7 +193,7 @@
 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
   * @{
   */ 
-#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
+#define DMA_PERIPH_TO_MEMORY         (0x00000000U)               /*!< Peripheral to memory direction */
 #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
 #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
 
@@ -207,7 +205,7 @@
   * @{
   */ 
 #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)   /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode Disable */
+#define DMA_PINC_DISABLE       (0x00000000U)              /*!< Peripheral increment mode Disable */
 /**
   * @}
   */ 
@@ -216,7 +214,7 @@
   * @{
   */ 
 #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)   /*!< Memory increment mode Enable  */
-#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode Disable */
+#define DMA_MINC_DISABLE        (0x00000000U)              /*!< Memory increment mode Disable */
 /**
   * @}
   */
@@ -224,7 +222,7 @@
 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
   * @{
   */ 
-#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_BYTE          (0x00000000U)                 /*!< Peripheral data alignment: Byte     */
 #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)   /*!< Peripheral data alignment: HalfWord */
 #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)   /*!< Peripheral data alignment: Word     */
 /**
@@ -234,7 +232,7 @@
 /** @defgroup DMA_Memory_data_size DMA Memory data size
   * @{ 
   */
-#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_BYTE          (0x00000000U)                 /*!< Memory data alignment: Byte     */
 #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)   /*!< Memory data alignment: HalfWord */
 #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)   /*!< Memory data alignment: Word     */
 /**
@@ -244,7 +242,7 @@
 /** @defgroup DMA_mode DMA mode
   * @{
   */ 
-#define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
+#define DMA_NORMAL         (0x00000000U)                /*!< Normal mode                  */
 #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
 /**
   * @}
@@ -253,7 +251,7 @@
 /** @defgroup DMA_Priority_level DMA Priority level
   * @{
   */
-#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level : Low       */
+#define DMA_PRIORITY_LOW             (0x00000000U)              /*!< Priority level : Low       */
 #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)   /*!< Priority level : Medium    */
 #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)   /*!< Priority level : High      */
 #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)     /*!< Priority level : Very_High */
@@ -275,34 +273,34 @@
 /** @defgroup DMA_flag_definitions DMA flag definitions
   * @{
   */ 
-#define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
-#define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
-#define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
-#define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
-#define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
-#define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
-#define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
-#define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
-#define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
-#define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
-#define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
-#define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
-#define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
-#define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
-#define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
-#define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
-#define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
-#define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
-#define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
-#define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
-#define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
-#define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
-#define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
-#define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
-#define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
-#define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
-#define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
-#define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
+#define DMA_FLAG_GL1                      (0x00000001U)
+#define DMA_FLAG_TC1                      (0x00000002U)
+#define DMA_FLAG_HT1                      (0x00000004U)
+#define DMA_FLAG_TE1                      (0x00000008U)
+#define DMA_FLAG_GL2                      (0x00000010U)
+#define DMA_FLAG_TC2                      (0x00000020U)
+#define DMA_FLAG_HT2                      (0x00000040U)
+#define DMA_FLAG_TE2                      (0x00000080U)
+#define DMA_FLAG_GL3                      (0x00000100U)
+#define DMA_FLAG_TC3                      (0x00000200U)
+#define DMA_FLAG_HT3                      (0x00000400U)
+#define DMA_FLAG_TE3                      (0x00000800U)
+#define DMA_FLAG_GL4                      (0x00001000U)
+#define DMA_FLAG_TC4                      (0x00002000U)
+#define DMA_FLAG_HT4                      (0x00004000U)
+#define DMA_FLAG_TE4                      (0x00008000U)
+#define DMA_FLAG_GL5                      (0x00010000U)
+#define DMA_FLAG_TC5                      (0x00020000U)
+#define DMA_FLAG_HT5                      (0x00040000U)
+#define DMA_FLAG_TE5                      (0x00080000U)
+#define DMA_FLAG_GL6                      (0x00100000U)
+#define DMA_FLAG_TC6                      (0x00200000U)
+#define DMA_FLAG_HT6                      (0x00400000U)
+#define DMA_FLAG_TE6                      (0x00800000U)
+#define DMA_FLAG_GL7                      (0x01000000U)
+#define DMA_FLAG_TC7                      (0x02000000U)
+#define DMA_FLAG_HT7                      (0x04000000U)
+#define DMA_FLAG_TE7                      (0x08000000U)
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_flash.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the internal FLASH memory:
@@ -140,7 +138,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -239,10 +237,10 @@
   *         Call the HAL_FLASH_Lock() to disable the flash memory access
   *         (recommended to protect the FLASH memory against possible unwanted operation).
   *
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
+  * @param  TypeProgram   Indicate the way to program at a specified address.
   *                       This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:      Specifies the address to be programmed.
-  * @param  Data:         Specifies the data to be programmed
+  * @param  Address       Specifie the address to be programmed.
+  * @param  Data          Specifie the data to be programmed
   * 
   * @retval HAL_StatusTypeDef HAL Status
   */
@@ -281,10 +279,10 @@
 /**
   * @brief   Program word at a specified address  with interrupt enabled.
   *
-  * @param  TypeProgram: Indicate the way to program at a specified address.
+  * @param  TypeProgram  Indicate the way to program at a specified address.
   *                      This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:     Specifies the address to be programmed.
-  * @param  Data:        Specifies the data to be programmed
+  * @param  Address      Specifie the address to be programmed.
+  * @param  Data         Specifie the data to be programmed
   * 
   * @retval HAL_StatusTypeDef HAL Status
   */
@@ -321,7 +319,7 @@
   */
 void HAL_FLASH_IRQHandler(void)
 {
-  uint32_t addresstmp = 0;
+  uint32_t addresstmp = 0U;
   
   /* Check FLASH operation error flags */
   if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)     || 
@@ -371,7 +369,7 @@
         pFlash.NbPagesToErase--;
 
         /* Check if there are still pages to erase */
-        if(pFlash.NbPagesToErase != 0)
+        if(pFlash.NbPagesToErase != 0U)
         {
           addresstmp = pFlash.Page;
           /*Indicate user which sector has been erased */
@@ -630,7 +628,7 @@
   { 
     if (Timeout != HAL_MAX_DELAY)
     {
-      if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
+      if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
       {
         return HAL_TIMEOUT;
       }
@@ -670,7 +668,7 @@
   */
 static void FLASH_SetErrorCode(void)
 {
-  uint32_t flags = 0;
+  uint32_t flags = 0U;
   
   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
   {

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_flash.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of Flash HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -57,7 +55,7 @@
 /** @addtogroup FLASH_Private_Constants
   * @{
   */
-#define FLASH_TIMEOUT_VALUE   ((uint32_t)50000U) /* 50 s */
+#define FLASH_TIMEOUT_VALUE      (50000U) /* 50 s */
 /**
   * @}
   */
@@ -66,7 +64,7 @@
   * @{
   */
 
-#define IS_FLASH_TYPEPROGRAM(_VALUE_)   (((_VALUE_) == FLASH_TYPEPROGRAM_WORD))
+#define IS_FLASH_TYPEPROGRAM(_VALUE_)   ((_VALUE_) == FLASH_TYPEPROGRAM_WORD)
 
 #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
                                        ((__LATENCY__) == FLASH_LATENCY_1))
@@ -85,9 +83,9 @@
   */
 typedef enum 
 {
-  FLASH_PROC_NONE              = 0, 
-  FLASH_PROC_PAGEERASE         = 1,
-  FLASH_PROC_PROGRAM           = 2,
+  FLASH_PROC_NONE              = 0U, 
+  FLASH_PROC_PAGEERASE         = 1U,
+  FLASH_PROC_PROGRAM           = 2U,
 } FLASH_ProcedureTypeDef;
 
 /** 
@@ -139,8 +137,10 @@
   * @{
   */ 
 
-#define FLASH_SIZE                (uint32_t)(*((uint16_t *)FLASHSIZE_BASE) * 1024U)
-#define FLASH_PAGE_SIZE           ((uint32_t)256U)  /*!< FLASH Page Size in bytes */
+#ifndef FLASH_SIZE // MBED
+#define FLASH_SIZE                (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) * 1024U)
+#endif // MBED
+#define FLASH_PAGE_SIZE           (256U)  /*!< FLASH Page Size in bytes */
 
 /**
   * @}
@@ -149,7 +149,7 @@
 /** @defgroup FLASH_Type_Program FLASH Type Program
   * @{
   */ 
-#define FLASH_TYPEPROGRAM_WORD       ((uint32_t)0x02U)  /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_WORD       (0x02U)  /*!<Program a word (32-bit) at a specified address.*/
 
 /**
   * @}
@@ -158,7 +158,7 @@
 /** @defgroup FLASH_Latency FLASH Latency
   * @{
   */ 
-#define FLASH_LATENCY_0            ((uint32_t)0x00000000U)    /*!< FLASH Zero Latency cycle */
+#define FLASH_LATENCY_0            (0x00000000U)    /*!< FLASH Zero Latency cycle */
 #define FLASH_LATENCY_1            FLASH_ACR_LATENCY         /*!< FLASH One Latency cycle */
 
 /**
@@ -168,7 +168,7 @@
 /** @defgroup FLASH_Interrupts FLASH Interrupts 
   * @{
   */
-   
+
 #define FLASH_IT_EOP               FLASH_PECR_EOPIE  /*!< End of programming interrupt source */
 #define FLASH_IT_ERR               FLASH_PECR_ERRIE  /*!< Error interrupt source */
 /**
@@ -204,21 +204,21 @@
   * @{
   */ 
 
-#define FLASH_PDKEY1               ((uint32_t)0x04152637U) /*!< Flash power down key1 */
-#define FLASH_PDKEY2               ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 
+#define FLASH_PDKEY1               (0x04152637U) /*!< Flash power down key1 */
+#define FLASH_PDKEY2               (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 
                                                               to unlock the RUN_PD bit in FLASH_ACR */
 
-#define FLASH_PEKEY1               ((uint32_t)0x89ABCDEFU) /*!< Flash program erase key1 */
-#define FLASH_PEKEY2               ((uint32_t)0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2
+#define FLASH_PEKEY1               (0x89ABCDEFU) /*!< Flash program erase key1 */
+#define FLASH_PEKEY2               (0x02030405U) /*!< Flash program erase key: used with FLASH_PEKEY2
                                                                to unlock the write access to the FLASH_PECR register and
                                                                data EEPROM */
 
-#define FLASH_PRGKEY1              ((uint32_t)0x8C9DAEBFU) /*!< Flash program memory key1 */
-#define FLASH_PRGKEY2              ((uint32_t)0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2
+#define FLASH_PRGKEY1              (0x8C9DAEBFU) /*!< Flash program memory key1 */
+#define FLASH_PRGKEY2              (0x13141516U) /*!< Flash program memory key2: used with FLASH_PRGKEY2
                                                                to unlock the program memory */
 
-#define FLASH_OPTKEY1              ((uint32_t)0xFBEAD9C8U) /*!< Flash option key1 */
-#define FLASH_OPTKEY2              ((uint32_t)0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to
+#define FLASH_OPTKEY1              (0xFBEAD9C8U) /*!< Flash option key1 */
+#define FLASH_OPTKEY2              (0x24252627U) /*!< Flash option key2: used with FLASH_OPTKEY1 to
                                                               unlock the write access to the option byte block */
 /**
   * @}
@@ -305,8 +305,6 @@
   * @param  __FLAG__ specifies the FLASH flags to clear.
   *          This parameter can be any combination of the following values:
   *            @arg @ref FLASH_FLAG_EOP         FLASH End of Operation flag 
-  *            @arg @ref FLASH_FLAG_ENDHV       FLASH End of High Voltage flag
-  *            @arg @ref FLASH_FLAG_READY       FLASH Ready flag after low power mode
   *            @arg @ref FLASH_FLAG_PGAERR      FLASH Programming Alignment error flag
   *            @arg @ref FLASH_FLAG_SIZERR      FLASH Size error flag
   *            @arg @ref FLASH_FLAG_OPTVERR     FLASH Option validity error error flag

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_flash_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Extended FLASH HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -38,7 +36,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -205,7 +203,7 @@
 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
 {
   HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t address = 0;
+  uint32_t address = 0U;
   
   /* Process Locked */
   __HAL_LOCK(&pFlash);
@@ -222,7 +220,7 @@
     assert_param(IS_NBPAGES(pEraseInit->NbPages));
     assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
     assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
-    assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
+    assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));
 
 #if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX)
     /* Check on which bank belongs the 1st address to erase */
@@ -230,7 +228,7 @@
     {
       /* BANK1 */
       /* Check that last page to erase still belongs to BANK1 */
-      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK1_END)
+      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END)
       {
         /*  Last page does not belong to BANK1, erase procedure cannot be performed because memory is not
             continuous */
@@ -243,7 +241,7 @@
     {
       /* BANK2 */
       /* Check that last page to erase still belongs to BANK2 */
-      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK2_END)
+      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END)
       {
         /*  Last page does not belong to BANK2, erase procedure cannot be performed because memory is not
             continuous */
@@ -300,7 +298,7 @@
   */
 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
 {
-  HAL_StatusTypeDef status = HAL_OK;
+  HAL_StatusTypeDef status = HAL_ERROR;
 
   /* If procedure already ongoing, reject the next one */
   if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
@@ -312,7 +310,7 @@
   assert_param(IS_NBPAGES(pEraseInit->NbPages));
   assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
   assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
+  assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U));
 
   /* Process Locked */
   __HAL_LOCK(&pFlash);
@@ -323,7 +321,7 @@
     {
       /* BANK1 */
       /* Check that last page to erase still belongs to BANK1 */
-      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK1_END)
+      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END)
       {
         /*  Last page does not belong to BANK1, erase procedure cannot be performed because memory is not
             continuous */
@@ -336,7 +334,7 @@
     {
       /* BANK2 */
       /* Check that last page to erase still belongs to BANK2 */
-      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1) > FLASH_BANK2_END)
+      if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END)
       {
         /*  Last page does not belong to BANK2, erase procedure cannot be performed because memory is not
             continuous */
@@ -347,15 +345,26 @@
     }
 #endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */
 
-  /* Enable End of FLASH Operation and Error source interrupts */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
   
-  pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
-  pFlash.NbPagesToErase = pEraseInit->NbPages;
-  pFlash.Page = pEraseInit->PageAddress;
+  if (status == HAL_OK)
+  {
+    /* Enable End of FLASH Operation and Error source interrupts */
+    __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
+    
+    pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
+    pFlash.NbPagesToErase = pEraseInit->NbPages;
+    pFlash.Page = pEraseInit->PageAddress;
 
-  /*Erase 1st page and wait for IT*/
-  FLASH_PageErase(pEraseInit->PageAddress);
+    /*Erase 1st page and wait for IT*/
+    FLASH_PageErase(pEraseInit->PageAddress);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
 
   return status;
 }
@@ -605,7 +614,7 @@
   */
 void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
 {
-  pAdvOBInit->OptionType = 0;
+  pAdvOBInit->OptionType = 0U;
   
 #if defined(FLASH_OBR_SPRMOD)
       
@@ -630,7 +639,7 @@
   pAdvOBInit->OptionType |= OPTIONBYTE_BOOTCONFIG;
 
   /* Get Boot config OB */
-  pAdvOBInit->BootConfig = (FLASH->OBR & FLASH_OBR_nRST_BFB2) >> 16;
+  pAdvOBInit->BootConfig = (FLASH->OBR & FLASH_OBR_nRST_BFB2) >> 16U;
 
 #endif /* FLASH_OBR_nRST_BFB2 */
 }
@@ -649,10 +658,10 @@
 HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  uint16_t tmp1 = 0;
-  uint32_t tmp2 = 0;
-  uint8_t optiontmp = 0;
-  uint16_t optiontmp2 = 0;
+  uint16_t tmp1 = 0U;
+  uint32_t tmp2 = 0U;
+  uint8_t optiontmp = 0U;
+  uint16_t optiontmp2 = 0U;
   
   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
   
@@ -664,7 +673,7 @@
   
   /* calculate the option byte to write */
   tmp1 = (uint16_t)(~(optiontmp2 ));
-  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2));
+  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2));
   
   if(status == HAL_OK)
   {         
@@ -692,10 +701,10 @@
 HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  uint16_t tmp1 = 0;
-  uint32_t tmp2 = 0;
-  uint8_t optiontmp = 0;
-  uint16_t optiontmp2 = 0;
+  uint16_t tmp1 = 0U;
+  uint32_t tmp2 = 0U;
+  uint8_t optiontmp = 0U;
+  uint16_t optiontmp2 = 0U;
   
   status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
   
@@ -707,7 +716,7 @@
   
   /* calculate the option byte to write */
   tmp1 = (uint16_t)(~(optiontmp2 ));
-  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2));
+  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2));
   
   if(status == HAL_OK)
   {         
@@ -813,7 +822,7 @@
     if(TypeErase == FLASH_TYPEERASEDATA_WORD)
     {
       /* Write 00000000h to valid address in the data memory */
-      *(__IO uint32_t *) Address = 0x00000000;
+      *(__IO uint32_t *) Address = 0x00000000U;
     }
 
     if(TypeErase == FLASH_TYPEERASEDATA_HALFWORD)
@@ -846,8 +855,8 @@
   *         this function to configure the Fixed Time Programming.
   * @param  TypeProgram  Indicate the way to program at a specified address.
   *         This parameter can be a value of @ref FLASHEx_Type_Program_Data
-  * @param  Address  specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed
+  * @param  Address  specifie the address to be programmed.
+  * @param  Data     specifie the data to be programmed
   * 
   * @retval HAL_StatusTypeDef HAL Status
   */
@@ -870,43 +879,43 @@
     /* Clean the error context */
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
-    if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTBYTE)
-    {
-      /*Program word (8-bit) at a specified address.*/
-      status = FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data);
-    }
-    
-    if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTHALFWORD)
-    {
-      /* Program halfword (16-bit) at a specified address.*/
-      status = FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data);
-    }    
-    
-    if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTWORD)
-    {
-      /* Program word (32-bit) at a specified address.*/
-      status = FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data);
-    }
-    
     if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD)
     {
       /* Program word (32-bit) at a specified address.*/
       status = FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data);
     }
-       
-    if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD)
+    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD)
     {
       /* Program halfword (16-bit) at a specified address.*/
       status = FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data);
     }
-        
-    if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE)
+    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE)
     {
       /* Program byte (8-bit) at a specified address.*/
       status = FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data);
     }
+    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTBYTE)
+    {
+      /*Program word (8-bit) at a specified address.*/
+      status = FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data);
+    }
+    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTHALFWORD)
+    {
+      /* Program halfword (16-bit) at a specified address.*/
+      status = FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data);
+    }    
+    else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTWORD)
+    {
+      /* Program word (32-bit) at a specified address.*/
+      status = FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data);
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+
   }
-  
+
   /* Process Unlocked */
   __HAL_UNLOCK(&pFlash);
 
@@ -965,7 +974,7 @@
 static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
+  uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
   
   /* Check the parameters */
   assert_param(IS_OB_RDP(OB_RDP));
@@ -991,7 +1000,7 @@
 
     /* calculate the option byte to write */
     tmp1 = (~((uint32_t)(OB_RDP | tmp3)));
-    tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)(OB_RDP | tmp3)));
+    tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)(OB_RDP | tmp3)));
 
     /* Wait for last operation to be completed */
     status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@@ -1029,16 +1038,16 @@
 static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
 {
   HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp = 0, tmp1 = 0;
+  uint32_t tmp = 0U, tmp1 = 0U;
 
   /* Check the parameters */
   assert_param(IS_OB_BOR_LEVEL(OB_BOR));
 
   /* Get the User Option byte register */
-  tmp1 = OB->USER & ((~FLASH_OBR_BOR_LEV) >> 16);
+  tmp1 = OB->USER & ((~FLASH_OBR_BOR_LEV) >> 16U);
 
-  /* Calculate the option byte to write - [0xFF | nUSER | 0x00 | USER]*/
-  tmp = (uint32_t)~((OB_BOR | tmp1)) << 16;
+  /* Calculate the option byte to write - [0xFFU | nUSER | 0x00U | USER]*/
+  tmp = (uint32_t)~((OB_BOR | tmp1)) << 16U;
   tmp |= (OB_BOR | tmp1);
     
   /* Wait for last operation to be completed */
@@ -1067,7 +1076,7 @@
 static uint8_t FLASH_OB_GetUser(void)
 {
   /* Return the User Option Byte */
-  return (uint8_t)((FLASH->OBR & FLASH_OBR_USER) >> 16);
+  return (uint8_t)((FLASH->OBR & FLASH_OBR_USER) >> 16U);
 }
 
 /**
@@ -1090,7 +1099,7 @@
 static uint8_t FLASH_OB_GetBOR(void)
 {
   /* Return the BOR level */
-  return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> 16);
+  return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> 16U);
 }
 
 /**
@@ -1114,7 +1123,7 @@
     pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
 
     /* WRP for sector between 0 to 31 */
-    if (pOBInit->WRPSector0To31 != 0)
+    if (pOBInit->WRPSector0To31 != 0U)
     {
       FLASH_OB_WRPConfigWRP1OrPCROP1(pOBInit->WRPSector0To31, NewState);
     }
@@ -1126,7 +1135,7 @@
       
     /* Pages for Cat3, Cat4 & Cat5 devices*/
     /* WRP for sector between 32 to 63 */
-    if (pOBInit->WRPSector32To63 != 0)
+    if (pOBInit->WRPSector32To63 != 0U)
     {
       FLASH_OB_WRPConfigWRP2OrPCROP2(pOBInit->WRPSector32To63, NewState);
     }
@@ -1139,7 +1148,7 @@
       
     /* Pages for devices with FLASH >= 256KB*/
     /* WRP for sector between 64 to 95 */
-    if (pOBInit->WRPSector64To95 != 0)
+    if (pOBInit->WRPSector64To95 != 0U)
     {
       FLASH_OB_WRPConfigWRP3(pOBInit->WRPSector64To95, NewState);
     }
@@ -1151,7 +1160,7 @@
 
     /* Pages for Cat5 devices*/
     /* WRP for sector between 96 to 127 */
-    if (pOBInit->WRPSector96To127 != 0)
+    if (pOBInit->WRPSector96To127 != 0U)
     {
       FLASH_OB_WRPConfigWRP4(pOBInit->WRPSector96To127, NewState);
     }
@@ -1199,7 +1208,7 @@
 
     /* Pages for Cat2 devices*/
     /* PCROP for sector between 0 to 31 */
-    if (pAdvOBInit->PCROPSector0To31 != 0)
+    if (pAdvOBInit->PCROPSector0To31 != 0U)
     {
       FLASH_OB_WRPConfigWRP1OrPCROP1(pAdvOBInit->PCROPSector0To31, pcropstate);
     }
@@ -1208,7 +1217,7 @@
 
     /* Pages for Cat3 devices*/
     /* WRP for sector between 32 to 63 */
-    if (pAdvOBInit->PCROPSector32To63 != 0)
+    if (pAdvOBInit->PCROPSector32To63 != 0U)
     {
       FLASH_OB_WRPConfigWRP2OrPCROP2(pAdvOBInit->PCROPSector32To63, pcropstate);
     }
@@ -1234,9 +1243,9 @@
   */
 static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState)
 {
-  uint32_t wrp01data = 0, wrp23data = 0;
+  uint32_t wrp01data = 0U, wrp23data = 0U;
   
-  uint32_t tmp1 = 0, tmp2 = 0;
+  uint32_t tmp1 = 0U, tmp2 = 0U;
   
   /* Check the parameters */
   assert_param(IS_OB_WRP(WRP1OrPCROP1));
@@ -1245,22 +1254,22 @@
   if (NewState != DISABLE)
   {
     wrp01data = (uint16_t)(((WRP1OrPCROP1 & WRP_MASK_LOW) | OB->WRP01));
-    wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16 | OB->WRP23))); 
-    tmp1 = (uint32_t)(~(wrp01data) << 16)|(wrp01data);
+    wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U | OB->WRP23))); 
+    tmp1 = (uint32_t)(~(wrp01data) << 16U)|(wrp01data);
     OB->WRP01 = tmp1;
 
-    tmp2 = (uint32_t)(~(wrp23data) << 16)|(wrp23data);
+    tmp2 = (uint32_t)(~(wrp23data) << 16U)|(wrp23data);
     OB->WRP23 = tmp2;      
   }
   else
   {
     wrp01data = (uint16_t)(~WRP1OrPCROP1 & (WRP_MASK_LOW & OB->WRP01));
-    wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16 & OB->WRP23))); 
+    wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U & OB->WRP23))); 
 
-    tmp1 = (uint32_t)((~wrp01data) << 16)|(wrp01data);
+    tmp1 = (uint32_t)((~wrp01data) << 16U)|(wrp01data);
     OB->WRP01 = tmp1;
     
-    tmp2 = (uint32_t)((~wrp23data) << 16)|(wrp23data);
+    tmp2 = (uint32_t)((~wrp23data) << 16U)|(wrp23data);
     OB->WRP23 = tmp2;
   }
 }
@@ -1280,9 +1289,9 @@
   */
 static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState)
 {
-  uint32_t wrp45data = 0, wrp67data = 0;
+  uint32_t wrp45data = 0U, wrp67data = 0U;
   
-  uint32_t tmp1 = 0, tmp2 = 0;
+  uint32_t tmp1 = 0U, tmp2 = 0U;
   
   /* Check the parameters */
   assert_param(IS_OB_WRP(WRP2OrPCROP2));
@@ -1291,22 +1300,22 @@
   if (NewState != DISABLE)
   {
     wrp45data = (uint16_t)(((WRP2OrPCROP2 & WRP_MASK_LOW) | OB->WRP45));
-    wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16 | OB->WRP67))); 
-    tmp1 = (uint32_t)(~(wrp45data) << 16)|(wrp45data);
+    wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U | OB->WRP67))); 
+    tmp1 = (uint32_t)(~(wrp45data) << 16U)|(wrp45data);
     OB->WRP45 = tmp1;
     
-    tmp2 = (uint32_t)(~(wrp67data) << 16)|(wrp67data);
+    tmp2 = (uint32_t)(~(wrp67data) << 16U)|(wrp67data);
     OB->WRP67 = tmp2;
   }
   else
   {
     wrp45data = (uint16_t)(~WRP2OrPCROP2 & (WRP_MASK_LOW & OB->WRP45));
-    wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16 & OB->WRP67))); 
+    wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U & OB->WRP67))); 
     
-    tmp1 = (uint32_t)((~wrp45data) << 16)|(wrp45data);
+    tmp1 = (uint32_t)((~wrp45data) << 16U)|(wrp45data);
     OB->WRP45 = tmp1;
     
-    tmp2 = (uint32_t)((~wrp67data) << 16)|(wrp67data);
+    tmp2 = (uint32_t)((~wrp67data) << 16U)|(wrp67data);
     OB->WRP67 = tmp2;
   }
 }
@@ -1326,9 +1335,9 @@
   */
 static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState)
 {
-  uint32_t wrp89data = 0, wrp1011data = 0;
+  uint32_t wrp89data = 0U, wrp1011data = 0U;
   
-  uint32_t tmp1 = 0, tmp2 = 0;
+  uint32_t tmp1 = 0U, tmp2 = 0U;
   
   /* Check the parameters */
   assert_param(IS_OB_WRP(WRP3));
@@ -1337,22 +1346,22 @@
   if (NewState != DISABLE)
   {
     wrp89data = (uint16_t)(((WRP3 & WRP_MASK_LOW) | OB->WRP89));
-    wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16 | OB->WRP1011))); 
-    tmp1 = (uint32_t)(~(wrp89data) << 16)|(wrp89data);
+    wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16U | OB->WRP1011))); 
+    tmp1 = (uint32_t)(~(wrp89data) << 16U)|(wrp89data);
     OB->WRP89 = tmp1;
 
-    tmp2 = (uint32_t)(~(wrp1011data) << 16)|(wrp1011data);
+    tmp2 = (uint32_t)(~(wrp1011data) << 16U)|(wrp1011data);
     OB->WRP1011 = tmp2;      
   }
   else
   {
     wrp89data = (uint16_t)(~WRP3 & (WRP_MASK_LOW & OB->WRP89));
-    wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16 & OB->WRP1011))); 
+    wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16U & OB->WRP1011))); 
 
-    tmp1 = (uint32_t)((~wrp89data) << 16)|(wrp89data);
+    tmp1 = (uint32_t)((~wrp89data) << 16U)|(wrp89data);
     OB->WRP89 = tmp1;
 
-    tmp2 = (uint32_t)((~wrp1011data) << 16)|(wrp1011data);
+    tmp2 = (uint32_t)((~wrp1011data) << 16U)|(wrp1011data);
     OB->WRP1011 = tmp2;
   }
 }
@@ -1371,9 +1380,9 @@
   */
 static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState)
 {
-  uint32_t wrp1213data = 0, wrp1415data = 0;
+  uint32_t wrp1213data = 0U, wrp1415data = 0U;
   
-  uint32_t tmp1 = 0, tmp2 = 0;
+  uint32_t tmp1 = 0U, tmp2 = 0U;
   
   /* Check the parameters */
   assert_param(IS_OB_WRP(WRP4));
@@ -1382,22 +1391,22 @@
   if (NewState != DISABLE)
   {
     wrp1213data = (uint16_t)(((WRP4 & WRP_MASK_LOW) | OB->WRP1213));
-    wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16 | OB->WRP1415))); 
-    tmp1 = (uint32_t)(~(wrp1213data) << 16)|(wrp1213data);
+    wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16U | OB->WRP1415))); 
+    tmp1 = (uint32_t)(~(wrp1213data) << 16U)|(wrp1213data);
     OB->WRP1213 = tmp1;
 
-    tmp2 = (uint32_t)(~(wrp1415data) << 16)|(wrp1415data);
+    tmp2 = (uint32_t)(~(wrp1415data) << 16U)|(wrp1415data);
     OB->WRP1415 = tmp2;      
   }
   else
   {
     wrp1213data = (uint16_t)(~WRP4 & (WRP_MASK_LOW & OB->WRP1213));
-    wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16 & OB->WRP1415))); 
+    wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16U & OB->WRP1415))); 
 
-    tmp1 = (uint32_t)((~wrp1213data) << 16)|(wrp1213data);
+    tmp1 = (uint32_t)((~wrp1213data) << 16U)|(wrp1213data);
     OB->WRP1213 = tmp1;
 
-    tmp2 = (uint32_t)((~wrp1415data) << 16)|(wrp1415data);
+    tmp2 = (uint32_t)((~wrp1415data) << 16U)|(wrp1415data);
     OB->WRP1415 = tmp2;
   }
 }
@@ -1422,7 +1431,7 @@
 static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
 {
   HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t tmp = 0, tmp1 = 0;
+  uint32_t tmp = 0U, tmp1 = 0U;
 
   /* Check the parameters */
   assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
@@ -1430,10 +1439,10 @@
   assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
 
   /* Get the User Option byte register */
-  tmp1 = OB->USER & ((~FLASH_OBR_USER) >> 16);
+  tmp1 = OB->USER & ((~FLASH_OBR_USER) >> 16U);
 
   /* Calculate the user option byte to write */ 
-  tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16);
+  tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16U);
   tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);
   
   /* Wait for last operation to be completed */
@@ -1475,16 +1484,16 @@
 static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT)
 {
   HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t tmp = 0, tmp1 = 0;
+  uint32_t tmp = 0U, tmp1 = 0U;
 
   /* Check the parameters */
   assert_param(IS_OB_BOOT_BANK(OB_BOOT));
 
   /* Get the User Option byte register  and BOR Level*/
-  tmp1 = OB->USER & ((~FLASH_OBR_nRST_BFB2) >> 16);
+  tmp1 = OB->USER & ((~FLASH_OBR_nRST_BFB2) >> 16U);
 
   /* Calculate the option byte to write */
-  tmp = (uint32_t)~(OB_BOOT | tmp1) << 16;
+  tmp = (uint32_t)~(OB_BOOT | tmp1) << 16U;
   tmp |= (OB_BOOT | tmp1);
 
   /* Wait for last operation to be completed */
@@ -1525,7 +1534,7 @@
 {
   HAL_StatusTypeDef status = HAL_OK;
 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-  uint32_t tmp = 0, tmpaddr = 0;
+  uint32_t tmp = 0U, tmpaddr = 0U;
 #endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
   
   /* Check the parameters */
@@ -1541,7 +1550,7 @@
 
 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
     /* Possible only on Cat1 devices */
-    if(Data != (uint8_t)0x00) 
+    if(Data != (uint8_t)0x00U) 
     {
       /* If the previous operation is completed, proceed to write the new Data */
       *(__IO uint8_t *)Address = Data;
@@ -1551,14 +1560,14 @@
     }
     else
     {
-      tmpaddr = Address & 0xFFFFFFFC;
+      tmpaddr = Address & 0xFFFFFFFCU;
       tmp = * (__IO uint32_t *) tmpaddr;
-      tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));
+      tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
       tmp &= ~tmpaddr;
-      status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
+      status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
       /* Process Unlocked */
       __HAL_UNLOCK(&pFlash);
-      status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
+      status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
       /* Process Locked */
       __HAL_LOCK(&pFlash);
     }
@@ -1585,7 +1594,7 @@
 {
   HAL_StatusTypeDef status = HAL_OK;
 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-  uint32_t tmp = 0, tmpaddr = 0;
+  uint32_t tmp = 0U, tmpaddr = 0U;
 #endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
   
   /* Check the parameters */
@@ -1601,7 +1610,7 @@
 
 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
     /* Possible only on Cat1 devices */
-    if(Data != (uint16_t)0x0000) 
+    if(Data != (uint16_t)0x0000U) 
     {
       /* If the previous operation is completed, proceed to write the new data */
       *(__IO uint16_t *)Address = Data;
@@ -1613,19 +1622,19 @@
     {
       /* Process Unlocked */
       __HAL_UNLOCK(&pFlash);
-      if((Address & 0x3) != 0x3)
+      if((Address & 0x3U) != 0x3U)
       {
-        tmpaddr = Address & 0xFFFFFFFC;
+        tmpaddr = Address & 0xFFFFFFFCU;
         tmp = * (__IO uint32_t *) tmpaddr;
-        tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));
+        tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
         tmp &= ~tmpaddr;        
-        status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
-        status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
+        status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
+        status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
       }
       else
       {
-        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00);
-        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00);
+        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U);
+        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U);
       }
       /* Process Locked */
       __HAL_LOCK(&pFlash);
@@ -1684,7 +1693,7 @@
 {
   HAL_StatusTypeDef status = HAL_OK;
 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-  uint32_t tmp = 0, tmpaddr = 0;
+  uint32_t tmp = 0U, tmpaddr = 0U;
 #endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
   
   /* Check the parameters */
@@ -1696,7 +1705,7 @@
   if(status == HAL_OK)
   {
 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-    if(Data != (uint8_t) 0x00)
+    if(Data != (uint8_t) 0x00U)
     {  
       *(__IO uint8_t *)Address = Data;
     
@@ -1706,14 +1715,14 @@
     }
     else
     {
-      tmpaddr = Address & 0xFFFFFFFC;
+      tmpaddr = Address & 0xFFFFFFFCU;
       tmp = * (__IO uint32_t *) tmpaddr;
-      tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));
+      tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
       tmp &= ~tmpaddr;        
-      status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
+      status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
       /* Process Unlocked */
       __HAL_UNLOCK(&pFlash);
-      status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
+      status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
       /* Process Locked */
       __HAL_LOCK(&pFlash);
     }
@@ -1738,7 +1747,7 @@
 {
   HAL_StatusTypeDef status = HAL_OK;
 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-  uint32_t tmp = 0, tmpaddr = 0;
+  uint32_t tmp = 0U, tmpaddr = 0U;
 #endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
   
   /* Check the parameters */
@@ -1750,7 +1759,7 @@
   if(status == HAL_OK)
   {
 #if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB)
-    if(Data != (uint16_t)0x0000)
+    if(Data != (uint16_t)0x0000U)
     {
       *(__IO uint16_t *)Address = Data;
    
@@ -1761,19 +1770,19 @@
     {
       /* Process Unlocked */
       __HAL_UNLOCK(&pFlash);
-      if((Address & 0x3) != 0x3)
+      if((Address & 0x3U) != 0x3U)
       {
-        tmpaddr = Address & 0xFFFFFFFC;
+        tmpaddr = Address & 0xFFFFFFFCU;
         tmp = * (__IO uint32_t *) tmpaddr;
-        tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));
+        tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U)));
         tmp &= ~tmpaddr;          
-        status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
-        status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
+        status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU);
+        status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp);
       }
       else
       {
-        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00);
-        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00);
+        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U);
+        HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U);
       }
       /* Process Locked */
       __HAL_LOCK(&pFlash);

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -1,14 +1,12 @@
 /**
   ******************************************************************************
-  * @file    stm32l1xx_hal_flash.h
+  * @file    stm32l1xx_hal_flash_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
-  * @brief   Header file of Flash HAL module.
+  * @brief   Header file of Flash HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -86,29 +84,29 @@
  || defined(STM32L151xBA) || defined(STM32L152xBA)
      
 /******* Devices with FLASH 128K *******/
-#define FLASH_NBPAGES_MAX       512 /* 512 pages from page 0 to page 511 */
+#define FLASH_NBPAGES_MAX       512U /* 512 pages from page 0 to page 511U */
 
 #elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \
    || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA)
 
 /******* Devices with FLASH 256K *******/
-#define FLASH_NBPAGES_MAX       1025 /* 1025 pages from page 0 to page 1024 */
+#define FLASH_NBPAGES_MAX       1025U /* 1025 pages from page 0 to page 1024U */
 
 #elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \
    || defined(STM32L162xD) || defined(STM32L162xDX)
 
 /******* Devices with FLASH 384K *******/
-#define FLASH_NBPAGES_MAX       1536 /* 1536 pages from page 0 to page 1535 */
+#define FLASH_NBPAGES_MAX       1536U /* 1536 pages from page 0 to page 1535U */
 
 #elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
 
 /******* Devices with FLASH 512K *******/
-#define FLASH_NBPAGES_MAX       2048 /* 2048 pages from page 0 to page 2047 */
+#define FLASH_NBPAGES_MAX       2048U /* 2048 pages from page 0 to page 2047U */
 
 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
 
-#define WRP_MASK_LOW                 ((uint32_t)0x0000FFFFU)
-#define WRP_MASK_HIGH                 ((uint32_t)0xFFFF0000U)
+#define WRP_MASK_LOW                 (0x0000FFFFU)
+#define WRP_MASK_HIGH                (0xFFFF0000U)
 
 /**
   * @}
@@ -175,7 +173,6 @@
 #define IS_TYPEERASEDATA(__VALUE__)     (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \
                                          ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \
                                          ((__VALUE__) == FLASH_TYPEERASEDATA_WORD))
-
 #define IS_TYPEPROGRAMDATA(__VALUE__)   (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \
                                          ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \
                                          ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \
@@ -183,6 +180,7 @@
                                          ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \
                                          ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD))
 
+
 /** @defgroup FLASHEx_Address FLASHEx Address
   * @{
   */
@@ -204,7 +202,7 @@
 
 #endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */
 
-#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX)) 
+#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1U) && ((__PAGES__) <= FLASH_NBPAGES_MAX)) 
 
 /**
   * @}
@@ -325,8 +323,8 @@
 /** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
   * @{
   */
-#define FLASH_TYPEERASE_PAGES           ((uint32_t)0x00U)  /*!<Page erase only*/
- 
+#define FLASH_TYPEERASE_PAGES           (0x00U)  /*!<Page erase only*/
+
 /**
   * @}
   */
@@ -334,10 +332,10 @@
 /** @defgroup FLASHEx_Option_Type FLASHEx Option Type
   * @{
   */
-#define OPTIONBYTE_WRP            ((uint32_t)0x01U)  /*!<WRP option byte configuration*/
-#define OPTIONBYTE_RDP            ((uint32_t)0x02U)  /*!<RDP option byte configuration*/
-#define OPTIONBYTE_USER           ((uint32_t)0x04U)  /*!<USER option byte configuration*/
-#define OPTIONBYTE_BOR            ((uint32_t)0x08U)  /*!<BOR option byte configuration*/
+#define OPTIONBYTE_WRP            (0x01U)  /*!<WRP option byte configuration*/
+#define OPTIONBYTE_RDP            (0x02U)  /*!<RDP option byte configuration*/
+#define OPTIONBYTE_USER           (0x04U)  /*!<USER option byte configuration*/
+#define OPTIONBYTE_BOR            (0x08U)  /*!<BOR option byte configuration*/
 
 /**
   * @}
@@ -346,8 +344,8 @@
 /** @defgroup FLASHEx_WRP_State FLASHEx WRP State
   * @{
   */
-#define OB_WRPSTATE_DISABLE        ((uint32_t)0x00U)  /*!<Disable the write protection of the desired sectors*/
-#define OB_WRPSTATE_ENABLE         ((uint32_t)0x01U)  /*!<Enable the write protection of the desired sectors*/
+#define OB_WRPSTATE_DISABLE        (0x00U)  /*!<Disable the write protection of the desired sectors*/
+#define OB_WRPSTATE_ENABLE         (0x01U)  /*!<Enable the write protection of the desired sectors*/
 
 /**
   * @}
@@ -358,38 +356,38 @@
   */
   
 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
-#define OB_WRP1_PAGES0TO15    ((uint32_t)0x00000001) /* Write protection of Sector0 */  
-#define OB_WRP1_PAGES16TO31   ((uint32_t)0x00000002) /* Write protection of Sector1 */  
-#define OB_WRP1_PAGES32TO47   ((uint32_t)0x00000004) /* Write protection of Sector2 */  
-#define OB_WRP1_PAGES48TO63   ((uint32_t)0x00000008) /* Write protection of Sector3 */  
-#define OB_WRP1_PAGES64TO79   ((uint32_t)0x00000010) /* Write protection of Sector4 */  
-#define OB_WRP1_PAGES80TO95   ((uint32_t)0x00000020) /* Write protection of Sector5 */  
-#define OB_WRP1_PAGES96TO111  ((uint32_t)0x00000040) /* Write protection of Sector6 */  
-#define OB_WRP1_PAGES112TO127 ((uint32_t)0x00000080) /* Write protection of Sector7 */  
-#define OB_WRP1_PAGES128TO143 ((uint32_t)0x00000100) /* Write protection of Sector8 */  
-#define OB_WRP1_PAGES144TO159 ((uint32_t)0x00000200) /* Write protection of Sector9 */  
-#define OB_WRP1_PAGES160TO175 ((uint32_t)0x00000400) /* Write protection of Sector10 */ 
-#define OB_WRP1_PAGES176TO191 ((uint32_t)0x00000800) /* Write protection of Sector11 */ 
-#define OB_WRP1_PAGES192TO207 ((uint32_t)0x00001000) /* Write protection of Sector12 */ 
-#define OB_WRP1_PAGES208TO223 ((uint32_t)0x00002000) /* Write protection of Sector13 */ 
-#define OB_WRP1_PAGES224TO239 ((uint32_t)0x00004000) /* Write protection of Sector14 */ 
-#define OB_WRP1_PAGES240TO255 ((uint32_t)0x00008000) /* Write protection of Sector15 */ 
-#define OB_WRP1_PAGES256TO271 ((uint32_t)0x00010000) /* Write protection of Sector16 */ 
-#define OB_WRP1_PAGES272TO287 ((uint32_t)0x00020000) /* Write protection of Sector17 */ 
-#define OB_WRP1_PAGES288TO303 ((uint32_t)0x00040000) /* Write protection of Sector18 */ 
-#define OB_WRP1_PAGES304TO319 ((uint32_t)0x00080000) /* Write protection of Sector19 */ 
-#define OB_WRP1_PAGES320TO335 ((uint32_t)0x00100000) /* Write protection of Sector20 */ 
-#define OB_WRP1_PAGES336TO351 ((uint32_t)0x00200000) /* Write protection of Sector21 */ 
-#define OB_WRP1_PAGES352TO367 ((uint32_t)0x00400000) /* Write protection of Sector22 */ 
-#define OB_WRP1_PAGES368TO383 ((uint32_t)0x00800000) /* Write protection of Sector23 */ 
-#define OB_WRP1_PAGES384TO399 ((uint32_t)0x01000000) /* Write protection of Sector24 */ 
-#define OB_WRP1_PAGES400TO415 ((uint32_t)0x02000000) /* Write protection of Sector25 */ 
-#define OB_WRP1_PAGES416TO431 ((uint32_t)0x04000000) /* Write protection of Sector26 */ 
-#define OB_WRP1_PAGES432TO447 ((uint32_t)0x08000000) /* Write protection of Sector27 */ 
-#define OB_WRP1_PAGES448TO463 ((uint32_t)0x10000000) /* Write protection of Sector28 */ 
-#define OB_WRP1_PAGES464TO479 ((uint32_t)0x20000000) /* Write protection of Sector29 */ 
-#define OB_WRP1_PAGES480TO495 ((uint32_t)0x40000000) /* Write protection of Sector30 */ 
-#define OB_WRP1_PAGES496TO511 ((uint32_t)0x80000000U) /* Write protection of Sector31 */ 
+#define OB_WRP1_PAGES0TO15    (0x00000001U) /* Write protection of Sector0 */  
+#define OB_WRP1_PAGES16TO31   (0x00000002U) /* Write protection of Sector1 */  
+#define OB_WRP1_PAGES32TO47   (0x00000004U) /* Write protection of Sector2 */  
+#define OB_WRP1_PAGES48TO63   (0x00000008U) /* Write protection of Sector3 */  
+#define OB_WRP1_PAGES64TO79   (0x00000010U) /* Write protection of Sector4 */  
+#define OB_WRP1_PAGES80TO95   (0x00000020U) /* Write protection of Sector5 */  
+#define OB_WRP1_PAGES96TO111  (0x00000040U) /* Write protection of Sector6 */  
+#define OB_WRP1_PAGES112TO127 (0x00000080U) /* Write protection of Sector7 */  
+#define OB_WRP1_PAGES128TO143 (0x00000100U) /* Write protection of Sector8 */  
+#define OB_WRP1_PAGES144TO159 (0x00000200U) /* Write protection of Sector9 */  
+#define OB_WRP1_PAGES160TO175 (0x00000400U) /* Write protection of Sector10 */ 
+#define OB_WRP1_PAGES176TO191 (0x00000800U) /* Write protection of Sector11 */ 
+#define OB_WRP1_PAGES192TO207 (0x00001000U) /* Write protection of Sector12 */ 
+#define OB_WRP1_PAGES208TO223 (0x00002000U) /* Write protection of Sector13 */ 
+#define OB_WRP1_PAGES224TO239 (0x00004000U) /* Write protection of Sector14 */ 
+#define OB_WRP1_PAGES240TO255 (0x00008000U) /* Write protection of Sector15 */ 
+#define OB_WRP1_PAGES256TO271 (0x00010000U) /* Write protection of Sector16 */ 
+#define OB_WRP1_PAGES272TO287 (0x00020000U) /* Write protection of Sector17 */ 
+#define OB_WRP1_PAGES288TO303 (0x00040000U) /* Write protection of Sector18 */ 
+#define OB_WRP1_PAGES304TO319 (0x00080000U) /* Write protection of Sector19 */ 
+#define OB_WRP1_PAGES320TO335 (0x00100000U) /* Write protection of Sector20 */ 
+#define OB_WRP1_PAGES336TO351 (0x00200000U) /* Write protection of Sector21 */ 
+#define OB_WRP1_PAGES352TO367 (0x00400000U) /* Write protection of Sector22 */ 
+#define OB_WRP1_PAGES368TO383 (0x00800000U) /* Write protection of Sector23 */ 
+#define OB_WRP1_PAGES384TO399 (0x01000000U) /* Write protection of Sector24 */ 
+#define OB_WRP1_PAGES400TO415 (0x02000000U) /* Write protection of Sector25 */ 
+#define OB_WRP1_PAGES416TO431 (0x04000000U) /* Write protection of Sector26 */ 
+#define OB_WRP1_PAGES432TO447 (0x08000000U) /* Write protection of Sector27 */ 
+#define OB_WRP1_PAGES448TO463 (0x10000000U) /* Write protection of Sector28 */ 
+#define OB_WRP1_PAGES464TO479 (0x20000000U) /* Write protection of Sector29 */ 
+#define OB_WRP1_PAGES480TO495 (0x40000000U) /* Write protection of Sector30 */ 
+#define OB_WRP1_PAGES496TO511 (0x80000000U) /* Write protection of Sector31 */ 
   
 #define OB_WRP1_ALLPAGES      ((uint32_t)FLASH_WRPR1_WRP) /*!< Write protection of all Sectors */
   
@@ -407,44 +405,44 @@
   */
   
 /* Pages for Cat3, Cat4 & Cat5 devices*/
-#define OB_WRP2_PAGES512TO527   ((uint32_t)0x00000001) /* Write protection of Sector32 */  
-#define OB_WRP2_PAGES528TO543   ((uint32_t)0x00000002) /* Write protection of Sector33 */  
-#define OB_WRP2_PAGES544TO559   ((uint32_t)0x00000004) /* Write protection of Sector34 */  
-#define OB_WRP2_PAGES560TO575   ((uint32_t)0x00000008) /* Write protection of Sector35 */  
-#define OB_WRP2_PAGES576TO591   ((uint32_t)0x00000010) /* Write protection of Sector36 */  
-#define OB_WRP2_PAGES592TO607   ((uint32_t)0x00000020) /* Write protection of Sector37 */  
-#define OB_WRP2_PAGES608TO623   ((uint32_t)0x00000040) /* Write protection of Sector38 */  
-#define OB_WRP2_PAGES624TO639   ((uint32_t)0x00000080) /* Write protection of Sector39 */  
-#define OB_WRP2_PAGES640TO655   ((uint32_t)0x00000100) /* Write protection of Sector40 */  
-#define OB_WRP2_PAGES656TO671   ((uint32_t)0x00000200) /* Write protection of Sector41 */  
-#define OB_WRP2_PAGES672TO687   ((uint32_t)0x00000400) /* Write protection of Sector42 */  
-#define OB_WRP2_PAGES688TO703   ((uint32_t)0x00000800) /* Write protection of Sector43 */  
-#define OB_WRP2_PAGES704TO719   ((uint32_t)0x00001000) /* Write protection of Sector44 */  
-#define OB_WRP2_PAGES720TO735   ((uint32_t)0x00002000) /* Write protection of Sector45 */  
-#define OB_WRP2_PAGES736TO751   ((uint32_t)0x00004000) /* Write protection of Sector46 */  
-#define OB_WRP2_PAGES752TO767   ((uint32_t)0x00008000) /* Write protection of Sector47 */  
+#define OB_WRP2_PAGES512TO527   (0x00000001U) /* Write protection of Sector32 */  
+#define OB_WRP2_PAGES528TO543   (0x00000002U) /* Write protection of Sector33 */  
+#define OB_WRP2_PAGES544TO559   (0x00000004U) /* Write protection of Sector34 */  
+#define OB_WRP2_PAGES560TO575   (0x00000008U) /* Write protection of Sector35 */  
+#define OB_WRP2_PAGES576TO591   (0x00000010U) /* Write protection of Sector36 */  
+#define OB_WRP2_PAGES592TO607   (0x00000020U) /* Write protection of Sector37 */  
+#define OB_WRP2_PAGES608TO623   (0x00000040U) /* Write protection of Sector38 */  
+#define OB_WRP2_PAGES624TO639   (0x00000080U) /* Write protection of Sector39 */  
+#define OB_WRP2_PAGES640TO655   (0x00000100U) /* Write protection of Sector40 */  
+#define OB_WRP2_PAGES656TO671   (0x00000200U) /* Write protection of Sector41 */  
+#define OB_WRP2_PAGES672TO687   (0x00000400U) /* Write protection of Sector42 */  
+#define OB_WRP2_PAGES688TO703   (0x00000800U) /* Write protection of Sector43 */  
+#define OB_WRP2_PAGES704TO719   (0x00001000U) /* Write protection of Sector44 */  
+#define OB_WRP2_PAGES720TO735   (0x00002000U) /* Write protection of Sector45 */  
+#define OB_WRP2_PAGES736TO751   (0x00004000U) /* Write protection of Sector46 */  
+#define OB_WRP2_PAGES752TO767   (0x00008000U) /* Write protection of Sector47 */  
 
 #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)   \
  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA) || defined(STM32L152xD) \
  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L152xE)  \
  || defined(STM32L162xE)
 
-#define OB_WRP2_PAGES768TO783   ((uint32_t)0x00010000) /* Write protection of Sector48 */  
-#define OB_WRP2_PAGES784TO799   ((uint32_t)0x00020000) /* Write protection of Sector49 */  
-#define OB_WRP2_PAGES800TO815   ((uint32_t)0x00040000) /* Write protection of Sector50 */  
-#define OB_WRP2_PAGES816TO831   ((uint32_t)0x00080000) /* Write protection of Sector51 */  
-#define OB_WRP2_PAGES832TO847   ((uint32_t)0x00100000) /* Write protection of Sector52 */  
-#define OB_WRP2_PAGES848TO863   ((uint32_t)0x00200000) /* Write protection of Sector53 */  
-#define OB_WRP2_PAGES864TO879   ((uint32_t)0x00400000) /* Write protection of Sector54 */  
-#define OB_WRP2_PAGES880TO895   ((uint32_t)0x00800000) /* Write protection of Sector55 */  
-#define OB_WRP2_PAGES896TO911   ((uint32_t)0x01000000) /* Write protection of Sector56 */  
-#define OB_WRP2_PAGES912TO927   ((uint32_t)0x02000000) /* Write protection of Sector57 */  
-#define OB_WRP2_PAGES928TO943   ((uint32_t)0x04000000) /* Write protection of Sector58 */  
-#define OB_WRP2_PAGES944TO959   ((uint32_t)0x08000000) /* Write protection of Sector59 */  
-#define OB_WRP2_PAGES960TO975   ((uint32_t)0x10000000) /* Write protection of Sector60 */  
-#define OB_WRP2_PAGES976TO991   ((uint32_t)0x20000000) /* Write protection of Sector61 */  
-#define OB_WRP2_PAGES992TO1007  ((uint32_t)0x40000000) /* Write protection of Sector62 */
-#define OB_WRP2_PAGES1008TO1023 ((uint32_t)0x80000000U) /* Write protection of Sector63 */
+#define OB_WRP2_PAGES768TO783   (0x00010000U) /* Write protection of Sector48 */  
+#define OB_WRP2_PAGES784TO799   (0x00020000U) /* Write protection of Sector49 */  
+#define OB_WRP2_PAGES800TO815   (0x00040000U) /* Write protection of Sector50 */  
+#define OB_WRP2_PAGES816TO831   (0x00080000U) /* Write protection of Sector51 */  
+#define OB_WRP2_PAGES832TO847   (0x00100000U) /* Write protection of Sector52 */  
+#define OB_WRP2_PAGES848TO863   (0x00200000U) /* Write protection of Sector53 */  
+#define OB_WRP2_PAGES864TO879   (0x00400000U) /* Write protection of Sector54 */  
+#define OB_WRP2_PAGES880TO895   (0x00800000U) /* Write protection of Sector55 */  
+#define OB_WRP2_PAGES896TO911   (0x01000000U) /* Write protection of Sector56 */  
+#define OB_WRP2_PAGES912TO927   (0x02000000U) /* Write protection of Sector57 */  
+#define OB_WRP2_PAGES928TO943   (0x04000000U) /* Write protection of Sector58 */  
+#define OB_WRP2_PAGES944TO959   (0x08000000U) /* Write protection of Sector59 */  
+#define OB_WRP2_PAGES960TO975   (0x10000000U) /* Write protection of Sector60 */  
+#define OB_WRP2_PAGES976TO991   (0x20000000U) /* Write protection of Sector61 */  
+#define OB_WRP2_PAGES992TO1007  (0x40000000U) /* Write protection of Sector62 */
+#define OB_WRP2_PAGES1008TO1023 (0x80000000U) /* Write protection of Sector63 */
 
 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
       
@@ -465,38 +463,38 @@
   */
   
 /* Pages for devices with FLASH >= 256KB*/
-#define OB_WRP3_PAGES1024TO1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */
-#define OB_WRP3_PAGES1040TO1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */
-#define OB_WRP3_PAGES1056TO1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */
-#define OB_WRP3_PAGES1072TO1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */
-#define OB_WRP3_PAGES1088TO1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */
-#define OB_WRP3_PAGES1104TO1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */
-#define OB_WRP3_PAGES1120TO1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */
-#define OB_WRP3_PAGES1136TO1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */
-#define OB_WRP3_PAGES1152TO1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */
-#define OB_WRP3_PAGES1168TO1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */
-#define OB_WRP3_PAGES1184TO1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */
-#define OB_WRP3_PAGES1200TO1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */
-#define OB_WRP3_PAGES1216TO1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */
-#define OB_WRP3_PAGES1232TO1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */
-#define OB_WRP3_PAGES1248TO1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */
-#define OB_WRP3_PAGES1264TO1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */
-#define OB_WRP3_PAGES1280TO1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */
-#define OB_WRP3_PAGES1296TO1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */
-#define OB_WRP3_PAGES1312TO1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */
-#define OB_WRP3_PAGES1328TO1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */
-#define OB_WRP3_PAGES1344TO1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */
-#define OB_WRP3_PAGES1360TO1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */
-#define OB_WRP3_PAGES1376TO1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */
-#define OB_WRP3_PAGES1392TO1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */
-#define OB_WRP3_PAGES1408TO1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */
-#define OB_WRP3_PAGES1424TO1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */
-#define OB_WRP3_PAGES1440TO1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */
-#define OB_WRP3_PAGES1456TO1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */
-#define OB_WRP3_PAGES1472TO1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
-#define OB_WRP3_PAGES1488TO1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
-#define OB_WRP3_PAGES1504TO1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
-#define OB_WRP3_PAGES1520TO1535 ((uint32_t)0x80000000U) /* Write protection of Sector95 */
+#define OB_WRP3_PAGES1024TO1039 (0x00000001U) /* Write protection of Sector64 */
+#define OB_WRP3_PAGES1040TO1055 (0x00000002U) /* Write protection of Sector65 */
+#define OB_WRP3_PAGES1056TO1071 (0x00000004U) /* Write protection of Sector66 */
+#define OB_WRP3_PAGES1072TO1087 (0x00000008U) /* Write protection of Sector67 */
+#define OB_WRP3_PAGES1088TO1103 (0x00000010U) /* Write protection of Sector68 */
+#define OB_WRP3_PAGES1104TO1119 (0x00000020U) /* Write protection of Sector69 */
+#define OB_WRP3_PAGES1120TO1135 (0x00000040U) /* Write protection of Sector70 */
+#define OB_WRP3_PAGES1136TO1151 (0x00000080U) /* Write protection of Sector71 */
+#define OB_WRP3_PAGES1152TO1167 (0x00000100U) /* Write protection of Sector72 */
+#define OB_WRP3_PAGES1168TO1183 (0x00000200U) /* Write protection of Sector73 */
+#define OB_WRP3_PAGES1184TO1199 (0x00000400U) /* Write protection of Sector74 */
+#define OB_WRP3_PAGES1200TO1215 (0x00000800U) /* Write protection of Sector75 */
+#define OB_WRP3_PAGES1216TO1231 (0x00001000U) /* Write protection of Sector76 */
+#define OB_WRP3_PAGES1232TO1247 (0x00002000U) /* Write protection of Sector77 */
+#define OB_WRP3_PAGES1248TO1263 (0x00004000U) /* Write protection of Sector78 */
+#define OB_WRP3_PAGES1264TO1279 (0x00008000U) /* Write protection of Sector79 */
+#define OB_WRP3_PAGES1280TO1295 (0x00010000U) /* Write protection of Sector80 */
+#define OB_WRP3_PAGES1296TO1311 (0x00020000U) /* Write protection of Sector81 */
+#define OB_WRP3_PAGES1312TO1327 (0x00040000U) /* Write protection of Sector82 */
+#define OB_WRP3_PAGES1328TO1343 (0x00080000U) /* Write protection of Sector83 */
+#define OB_WRP3_PAGES1344TO1359 (0x00100000U) /* Write protection of Sector84 */
+#define OB_WRP3_PAGES1360TO1375 (0x00200000U) /* Write protection of Sector85 */
+#define OB_WRP3_PAGES1376TO1391 (0x00400000U) /* Write protection of Sector86 */
+#define OB_WRP3_PAGES1392TO1407 (0x00800000U) /* Write protection of Sector87 */
+#define OB_WRP3_PAGES1408TO1423 (0x01000000U) /* Write protection of Sector88 */
+#define OB_WRP3_PAGES1424TO1439 (0x02000000U) /* Write protection of Sector89 */
+#define OB_WRP3_PAGES1440TO1455 (0x04000000U) /* Write protection of Sector90 */
+#define OB_WRP3_PAGES1456TO1471 (0x08000000U) /* Write protection of Sector91 */
+#define OB_WRP3_PAGES1472TO1487 (0x10000000U) /* Write protection of Sector92 */
+#define OB_WRP3_PAGES1488TO1503 (0x20000000U) /* Write protection of Sector93 */
+#define OB_WRP3_PAGES1504TO1519 (0x40000000U) /* Write protection of Sector94 */
+#define OB_WRP3_PAGES1520TO1535 (0x80000000U) /* Write protection of Sector95 */
 
 #define OB_WRP3_ALLPAGES        ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */
 
@@ -514,41 +512,41 @@
   */
   
 /* Pages for Cat5 devices*/
-#define OB_WRP4_PAGES1536TO1551 ((uint32_t)0x00000001)/* Write protection of Sector96*/   
-#define OB_WRP4_PAGES1552TO1567 ((uint32_t)0x00000002)/* Write protection of Sector97*/   
-#define OB_WRP4_PAGES1568TO1583 ((uint32_t)0x00000004)/* Write protection of Sector98*/   
-#define OB_WRP4_PAGES1584TO1599 ((uint32_t)0x00000008)/* Write protection of Sector99*/   
-#define OB_WRP4_PAGES1600TO1615 ((uint32_t)0x00000010) /* Write protection of Sector100*/ 
-#define OB_WRP4_PAGES1616TO1631 ((uint32_t)0x00000020) /* Write protection of Sector101*/ 
-#define OB_WRP4_PAGES1632TO1647 ((uint32_t)0x00000040) /* Write protection of Sector102*/ 
-#define OB_WRP4_PAGES1648TO1663 ((uint32_t)0x00000080) /* Write protection of Sector103*/ 
-#define OB_WRP4_PAGES1664TO1679 ((uint32_t)0x00000100) /* Write protection of Sector104*/ 
-#define OB_WRP4_PAGES1680TO1695 ((uint32_t)0x00000200) /* Write protection of Sector105*/ 
-#define OB_WRP4_PAGES1696TO1711 ((uint32_t)0x00000400) /* Write protection of Sector106*/ 
-#define OB_WRP4_PAGES1712TO1727 ((uint32_t)0x00000800) /* Write protection of Sector107*/ 
-#define OB_WRP4_PAGES1728TO1743 ((uint32_t)0x00001000) /* Write protection of Sector108*/ 
-#define OB_WRP4_PAGES1744TO1759 ((uint32_t)0x00002000) /* Write protection of Sector109*/ 
-#define OB_WRP4_PAGES1760TO1775 ((uint32_t)0x00004000) /* Write protection of Sector110*/ 
-#define OB_WRP4_PAGES1776TO1791 ((uint32_t)0x00008000) /* Write protection of Sector111*/ 
+#define OB_WRP4_PAGES1536TO1551 (0x00000001U)/* Write protection of Sector96*/   
+#define OB_WRP4_PAGES1552TO1567 (0x00000002U)/* Write protection of Sector97*/   
+#define OB_WRP4_PAGES1568TO1583 (0x00000004U)/* Write protection of Sector98*/   
+#define OB_WRP4_PAGES1584TO1599 (0x00000008U)/* Write protection of Sector99*/   
+#define OB_WRP4_PAGES1600TO1615 (0x00000010U) /* Write protection of Sector100*/ 
+#define OB_WRP4_PAGES1616TO1631 (0x00000020U) /* Write protection of Sector101*/ 
+#define OB_WRP4_PAGES1632TO1647 (0x00000040U) /* Write protection of Sector102*/ 
+#define OB_WRP4_PAGES1648TO1663 (0x00000080U) /* Write protection of Sector103*/ 
+#define OB_WRP4_PAGES1664TO1679 (0x00000100U) /* Write protection of Sector104*/ 
+#define OB_WRP4_PAGES1680TO1695 (0x00000200U) /* Write protection of Sector105*/ 
+#define OB_WRP4_PAGES1696TO1711 (0x00000400U) /* Write protection of Sector106*/ 
+#define OB_WRP4_PAGES1712TO1727 (0x00000800U) /* Write protection of Sector107*/ 
+#define OB_WRP4_PAGES1728TO1743 (0x00001000U) /* Write protection of Sector108*/ 
+#define OB_WRP4_PAGES1744TO1759 (0x00002000U) /* Write protection of Sector109*/ 
+#define OB_WRP4_PAGES1760TO1775 (0x00004000U) /* Write protection of Sector110*/ 
+#define OB_WRP4_PAGES1776TO1791 (0x00008000U) /* Write protection of Sector111*/ 
 
 #if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE)
 
-#define OB_WRP4_PAGES1792TO1807 ((uint32_t)0x00010000) /* Write protection of Sector112*/ 
-#define OB_WRP4_PAGES1808TO1823 ((uint32_t)0x00020000) /* Write protection of Sector113*/ 
-#define OB_WRP4_PAGES1824TO1839 ((uint32_t)0x00040000) /* Write protection of Sector114*/ 
-#define OB_WRP4_PAGES1840TO1855 ((uint32_t)0x00080000) /* Write protection of Sector115*/ 
-#define OB_WRP4_PAGES1856TO1871 ((uint32_t)0x00100000) /* Write protection of Sector116*/ 
-#define OB_WRP4_PAGES1872TO1887 ((uint32_t)0x00200000) /* Write protection of Sector117*/ 
-#define OB_WRP4_PAGES1888TO1903 ((uint32_t)0x00400000) /* Write protection of Sector118*/ 
-#define OB_WRP4_PAGES1904TO1919 ((uint32_t)0x00800000) /* Write protection of Sector119*/ 
-#define OB_WRP4_PAGES1920TO1935 ((uint32_t)0x01000000) /* Write protection of Sector120*/ 
-#define OB_WRP4_PAGES1936TO1951 ((uint32_t)0x02000000) /* Write protection of Sector121*/ 
-#define OB_WRP4_PAGES1952TO1967 ((uint32_t)0x04000000) /* Write protection of Sector122*/ 
-#define OB_WRP4_PAGES1968TO1983 ((uint32_t)0x08000000) /* Write protection of Sector123*/ 
-#define OB_WRP4_PAGES1984TO1999 ((uint32_t)0x10000000) /* Write protection of Sector124*/ 
-#define OB_WRP4_PAGES2000TO2015 ((uint32_t)0x20000000) /* Write protection of Sector125*/ 
-#define OB_WRP4_PAGES2016TO2031 ((uint32_t)0x40000000) /* Write protection of Sector126*/ 
-#define OB_WRP4_PAGES2032TO2047 ((uint32_t)0x80000000U) /* Write protection of Sector127*/ 
+#define OB_WRP4_PAGES1792TO1807 (0x00010000U) /* Write protection of Sector112*/ 
+#define OB_WRP4_PAGES1808TO1823 (0x00020000U) /* Write protection of Sector113*/ 
+#define OB_WRP4_PAGES1824TO1839 (0x00040000U) /* Write protection of Sector114*/ 
+#define OB_WRP4_PAGES1840TO1855 (0x00080000U) /* Write protection of Sector115*/ 
+#define OB_WRP4_PAGES1856TO1871 (0x00100000U) /* Write protection of Sector116*/ 
+#define OB_WRP4_PAGES1872TO1887 (0x00200000U) /* Write protection of Sector117*/ 
+#define OB_WRP4_PAGES1888TO1903 (0x00400000U) /* Write protection of Sector118*/ 
+#define OB_WRP4_PAGES1904TO1919 (0x00800000U) /* Write protection of Sector119*/ 
+#define OB_WRP4_PAGES1920TO1935 (0x01000000U) /* Write protection of Sector120*/ 
+#define OB_WRP4_PAGES1936TO1951 (0x02000000U) /* Write protection of Sector121*/ 
+#define OB_WRP4_PAGES1952TO1967 (0x04000000U) /* Write protection of Sector122*/ 
+#define OB_WRP4_PAGES1968TO1983 (0x08000000U) /* Write protection of Sector123*/ 
+#define OB_WRP4_PAGES1984TO1999 (0x10000000U) /* Write protection of Sector124*/ 
+#define OB_WRP4_PAGES2000TO2015 (0x20000000U) /* Write protection of Sector125*/ 
+#define OB_WRP4_PAGES2016TO2031 (0x40000000U) /* Write protection of Sector126*/ 
+#define OB_WRP4_PAGES2032TO2047 (0x80000000U) /* Write protection of Sector127*/ 
 
 #endif /* STM32L151xE || STM32L152xE || STM32L162xE */
 
@@ -626,7 +624,7 @@
   * @{
   */ 
   
-#define OPTIONBYTE_PCROP        ((uint32_t)0x01U)  /*!<PCROP option byte configuration*/
+#define OPTIONBYTE_PCROP        (0x01U)  /*!<PCROP option byte configuration*/
 
 /**
   * @}
@@ -640,7 +638,7 @@
   * @{
   */ 
   
-#define OPTIONBYTE_BOOTCONFIG   ((uint32_t)0x02U)  /*!<BOOTConfig option byte configuration*/
+#define OPTIONBYTE_BOOTCONFIG   (0x02U)  /*!<BOOTConfig option byte configuration*/
 
 /**
   * @}
@@ -653,8 +651,8 @@
 /** @defgroup  FLASHEx_PCROP_State FLASHEx PCROP State
   * @{
   */
-#define OB_PCROP_STATE_DISABLE        ((uint32_t)0x00U)  /*!<Disable PCROP for selected sectors */
-#define OB_PCROP_STATE_ENABLE         ((uint32_t)0x01U)  /*!<Enable PCROP for selected sectors */
+#define OB_PCROP_STATE_DISABLE        (0x00U)  /*!<Disable PCROP for selected sectors */
+#define OB_PCROP_STATE_ENABLE         (0x01U)  /*!<Enable PCROP for selected sectors */
     
 /**
   * @}
@@ -678,40 +676,40 @@
   */
   
 /* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
-#define OB_PCROP1_PAGES0TO15    ((uint32_t)0x00000001U) /* PC Read/Write  protection of Sector0 */  
-#define OB_PCROP1_PAGES16TO31   ((uint32_t)0x00000002U) /* PC Read/Write  protection of Sector1 */  
-#define OB_PCROP1_PAGES32TO47   ((uint32_t)0x00000004U) /* PC Read/Write  protection of Sector2 */  
-#define OB_PCROP1_PAGES48TO63   ((uint32_t)0x00000008U) /* PC Read/Write  protection of Sector3 */  
-#define OB_PCROP1_PAGES64TO79   ((uint32_t)0x00000010U) /* PC Read/Write  protection of Sector4 */  
-#define OB_PCROP1_PAGES80TO95   ((uint32_t)0x00000020U) /* PC Read/Write  protection of Sector5 */  
-#define OB_PCROP1_PAGES96TO111  ((uint32_t)0x00000040U) /* PC Read/Write  protection of Sector6 */  
-#define OB_PCROP1_PAGES112TO127 ((uint32_t)0x00000080U) /* PC Read/Write  protection of Sector7 */  
-#define OB_PCROP1_PAGES128TO143 ((uint32_t)0x00000100U) /* PC Read/Write  protection of Sector8 */  
-#define OB_PCROP1_PAGES144TO159 ((uint32_t)0x00000200U) /* PC Read/Write  protection of Sector9 */  
-#define OB_PCROP1_PAGES160TO175 ((uint32_t)0x00000400U) /* PC Read/Write  protection of Sector10 */ 
-#define OB_PCROP1_PAGES176TO191 ((uint32_t)0x00000800U) /* PC Read/Write  protection of Sector11 */ 
-#define OB_PCROP1_PAGES192TO207 ((uint32_t)0x00001000U) /* PC Read/Write  protection of Sector12 */ 
-#define OB_PCROP1_PAGES208TO223 ((uint32_t)0x00002000U) /* PC Read/Write  protection of Sector13 */ 
-#define OB_PCROP1_PAGES224TO239 ((uint32_t)0x00004000U) /* PC Read/Write  protection of Sector14 */ 
-#define OB_PCROP1_PAGES240TO255 ((uint32_t)0x00008000U) /* PC Read/Write  protection of Sector15 */ 
-#define OB_PCROP1_PAGES256TO271 ((uint32_t)0x00010000U) /* PC Read/Write  protection of Sector16 */ 
-#define OB_PCROP1_PAGES272TO287 ((uint32_t)0x00020000U) /* PC Read/Write  protection of Sector17 */ 
-#define OB_PCROP1_PAGES288TO303 ((uint32_t)0x00040000U) /* PC Read/Write  protection of Sector18 */ 
-#define OB_PCROP1_PAGES304TO319 ((uint32_t)0x00080000U) /* PC Read/Write  protection of Sector19 */ 
-#define OB_PCROP1_PAGES320TO335 ((uint32_t)0x00100000U) /* PC Read/Write  protection of Sector20 */ 
-#define OB_PCROP1_PAGES336TO351 ((uint32_t)0x00200000U) /* PC Read/Write  protection of Sector21 */ 
-#define OB_PCROP1_PAGES352TO367 ((uint32_t)0x00400000U) /* PC Read/Write  protection of Sector22 */ 
-#define OB_PCROP1_PAGES368TO383 ((uint32_t)0x00800000U) /* PC Read/Write  protection of Sector23 */ 
-#define OB_PCROP1_PAGES384TO399 ((uint32_t)0x01000000U) /* PC Read/Write  protection of Sector24 */ 
-#define OB_PCROP1_PAGES400TO415 ((uint32_t)0x02000000U) /* PC Read/Write  protection of Sector25 */ 
-#define OB_PCROP1_PAGES416TO431 ((uint32_t)0x04000000U) /* PC Read/Write  protection of Sector26 */ 
-#define OB_PCROP1_PAGES432TO447 ((uint32_t)0x08000000U) /* PC Read/Write  protection of Sector27 */ 
-#define OB_PCROP1_PAGES448TO463 ((uint32_t)0x10000000U) /* PC Read/Write  protection of Sector28 */ 
-#define OB_PCROP1_PAGES464TO479 ((uint32_t)0x20000000U) /* PC Read/Write  protection of Sector29 */ 
-#define OB_PCROP1_PAGES480TO495 ((uint32_t)0x40000000U) /* PC Read/Write  protection of Sector30 */ 
-#define OB_PCROP1_PAGES496TO511 ((uint32_t)0x80000000U) /* PC Read/Write  protection of Sector31 */ 
+#define OB_PCROP1_PAGES0TO15    (0x00000001U) /* PC Read/Write  protection of Sector0 */  
+#define OB_PCROP1_PAGES16TO31   (0x00000002U) /* PC Read/Write  protection of Sector1 */  
+#define OB_PCROP1_PAGES32TO47   (0x00000004U) /* PC Read/Write  protection of Sector2 */  
+#define OB_PCROP1_PAGES48TO63   (0x00000008U) /* PC Read/Write  protection of Sector3 */  
+#define OB_PCROP1_PAGES64TO79   (0x00000010U) /* PC Read/Write  protection of Sector4 */  
+#define OB_PCROP1_PAGES80TO95   (0x00000020U) /* PC Read/Write  protection of Sector5 */  
+#define OB_PCROP1_PAGES96TO111  (0x00000040U) /* PC Read/Write  protection of Sector6 */  
+#define OB_PCROP1_PAGES112TO127 (0x00000080U) /* PC Read/Write  protection of Sector7 */  
+#define OB_PCROP1_PAGES128TO143 (0x00000100U) /* PC Read/Write  protection of Sector8 */  
+#define OB_PCROP1_PAGES144TO159 (0x00000200U) /* PC Read/Write  protection of Sector9 */  
+#define OB_PCROP1_PAGES160TO175 (0x00000400U) /* PC Read/Write  protection of Sector10 */ 
+#define OB_PCROP1_PAGES176TO191 (0x00000800U) /* PC Read/Write  protection of Sector11 */ 
+#define OB_PCROP1_PAGES192TO207 (0x00001000U) /* PC Read/Write  protection of Sector12 */ 
+#define OB_PCROP1_PAGES208TO223 (0x00002000U) /* PC Read/Write  protection of Sector13 */ 
+#define OB_PCROP1_PAGES224TO239 (0x00004000U) /* PC Read/Write  protection of Sector14 */ 
+#define OB_PCROP1_PAGES240TO255 (0x00008000U) /* PC Read/Write  protection of Sector15 */ 
+#define OB_PCROP1_PAGES256TO271 (0x00010000U) /* PC Read/Write  protection of Sector16 */ 
+#define OB_PCROP1_PAGES272TO287 (0x00020000U) /* PC Read/Write  protection of Sector17 */ 
+#define OB_PCROP1_PAGES288TO303 (0x00040000U) /* PC Read/Write  protection of Sector18 */ 
+#define OB_PCROP1_PAGES304TO319 (0x00080000U) /* PC Read/Write  protection of Sector19 */ 
+#define OB_PCROP1_PAGES320TO335 (0x00100000U) /* PC Read/Write  protection of Sector20 */ 
+#define OB_PCROP1_PAGES336TO351 (0x00200000U) /* PC Read/Write  protection of Sector21 */ 
+#define OB_PCROP1_PAGES352TO367 (0x00400000U) /* PC Read/Write  protection of Sector22 */ 
+#define OB_PCROP1_PAGES368TO383 (0x00800000U) /* PC Read/Write  protection of Sector23 */ 
+#define OB_PCROP1_PAGES384TO399 (0x01000000U) /* PC Read/Write  protection of Sector24 */ 
+#define OB_PCROP1_PAGES400TO415 (0x02000000U) /* PC Read/Write  protection of Sector25 */ 
+#define OB_PCROP1_PAGES416TO431 (0x04000000U) /* PC Read/Write  protection of Sector26 */ 
+#define OB_PCROP1_PAGES432TO447 (0x08000000U) /* PC Read/Write  protection of Sector27 */ 
+#define OB_PCROP1_PAGES448TO463 (0x10000000U) /* PC Read/Write  protection of Sector28 */ 
+#define OB_PCROP1_PAGES464TO479 (0x20000000U) /* PC Read/Write  protection of Sector29 */ 
+#define OB_PCROP1_PAGES480TO495 (0x40000000U) /* PC Read/Write  protection of Sector30 */ 
+#define OB_PCROP1_PAGES496TO511 (0x80000000U) /* PC Read/Write  protection of Sector31 */ 
   
-#define OB_PCROP1_ALLPAGES      ((uint32_t)0xFFFFFFFFU) /*!< PC Read/Write  protection of all Sectors */
+#define OB_PCROP1_ALLPAGES      (0xFFFFFFFFU) /*!< PC Read/Write  protection of all Sectors */
   
 /**
   * @}
@@ -725,40 +723,40 @@
   */
   
 /* Pages for Cat3, Cat4 & Cat5 devices*/
-#define OB_PCROP2_PAGES512TO527   ((uint32_t)0x00000001U) /* PC Read/Write  protection of Sector32 */  
-#define OB_PCROP2_PAGES528TO543   ((uint32_t)0x00000002U) /* PC Read/Write  protection of Sector33 */  
-#define OB_PCROP2_PAGES544TO559   ((uint32_t)0x00000004U) /* PC Read/Write  protection of Sector34 */  
-#define OB_PCROP2_PAGES560TO575   ((uint32_t)0x00000008U) /* PC Read/Write  protection of Sector35 */  
-#define OB_PCROP2_PAGES576TO591   ((uint32_t)0x00000010U) /* PC Read/Write  protection of Sector36 */  
-#define OB_PCROP2_PAGES592TO607   ((uint32_t)0x00000020U) /* PC Read/Write  protection of Sector37 */  
-#define OB_PCROP2_PAGES608TO623   ((uint32_t)0x00000040U) /* PC Read/Write  protection of Sector38 */  
-#define OB_PCROP2_PAGES624TO639   ((uint32_t)0x00000080U) /* PC Read/Write  protection of Sector39 */  
-#define OB_PCROP2_PAGES640TO655   ((uint32_t)0x00000100U) /* PC Read/Write  protection of Sector40 */  
-#define OB_PCROP2_PAGES656TO671   ((uint32_t)0x00000200U) /* PC Read/Write  protection of Sector41 */  
-#define OB_PCROP2_PAGES672TO687   ((uint32_t)0x00000400U) /* PC Read/Write  protection of Sector42 */  
-#define OB_PCROP2_PAGES688TO703   ((uint32_t)0x00000800U) /* PC Read/Write  protection of Sector43 */  
-#define OB_PCROP2_PAGES704TO719   ((uint32_t)0x00001000U) /* PC Read/Write  protection of Sector44 */  
-#define OB_PCROP2_PAGES720TO735   ((uint32_t)0x00002000U) /* PC Read/Write  protection of Sector45 */  
-#define OB_PCROP2_PAGES736TO751   ((uint32_t)0x00004000U) /* PC Read/Write  protection of Sector46 */  
-#define OB_PCROP2_PAGES752TO767   ((uint32_t)0x00008000U) /* PC Read/Write  protection of Sector47 */  
-#define OB_PCROP2_PAGES768TO783   ((uint32_t)0x00010000U) /* PC Read/Write  protection of Sector48 */  
-#define OB_PCROP2_PAGES784TO799   ((uint32_t)0x00020000U) /* PC Read/Write  protection of Sector49 */  
-#define OB_PCROP2_PAGES800TO815   ((uint32_t)0x00040000U) /* PC Read/Write  protection of Sector50 */  
-#define OB_PCROP2_PAGES816TO831   ((uint32_t)0x00080000U) /* PC Read/Write  protection of Sector51 */  
-#define OB_PCROP2_PAGES832TO847   ((uint32_t)0x00100000U) /* PC Read/Write  protection of Sector52 */  
-#define OB_PCROP2_PAGES848TO863   ((uint32_t)0x00200000U) /* PC Read/Write  protection of Sector53 */  
-#define OB_PCROP2_PAGES864TO879   ((uint32_t)0x00400000U) /* PC Read/Write  protection of Sector54 */  
-#define OB_PCROP2_PAGES880TO895   ((uint32_t)0x00800000U) /* PC Read/Write  protection of Sector55 */  
-#define OB_PCROP2_PAGES896TO911   ((uint32_t)0x01000000U) /* PC Read/Write  protection of Sector56 */  
-#define OB_PCROP2_PAGES912TO927   ((uint32_t)0x02000000U) /* PC Read/Write  protection of Sector57 */  
-#define OB_PCROP2_PAGES928TO943   ((uint32_t)0x04000000U) /* PC Read/Write  protection of Sector58 */  
-#define OB_PCROP2_PAGES944TO959   ((uint32_t)0x08000000U) /* PC Read/Write  protection of Sector59 */  
-#define OB_PCROP2_PAGES960TO975   ((uint32_t)0x10000000U) /* PC Read/Write  protection of Sector60 */  
-#define OB_PCROP2_PAGES976TO991   ((uint32_t)0x20000000U) /* PC Read/Write  protection of Sector61 */  
-#define OB_PCROP2_PAGES992TO1007  ((uint32_t)0x40000000U) /* PC Read/Write  protection of Sector62 */
-#define OB_PCROP2_PAGES1008TO1023 ((uint32_t)0x80000000U) /* PC Read/Write  protection of Sector63 */
+#define OB_PCROP2_PAGES512TO527   (0x00000001U) /* PC Read/Write  protection of Sector32 */  
+#define OB_PCROP2_PAGES528TO543   (0x00000002U) /* PC Read/Write  protection of Sector33 */  
+#define OB_PCROP2_PAGES544TO559   (0x00000004U) /* PC Read/Write  protection of Sector34 */  
+#define OB_PCROP2_PAGES560TO575   (0x00000008U) /* PC Read/Write  protection of Sector35 */  
+#define OB_PCROP2_PAGES576TO591   (0x00000010U) /* PC Read/Write  protection of Sector36 */  
+#define OB_PCROP2_PAGES592TO607   (0x00000020U) /* PC Read/Write  protection of Sector37 */  
+#define OB_PCROP2_PAGES608TO623   (0x00000040U) /* PC Read/Write  protection of Sector38 */  
+#define OB_PCROP2_PAGES624TO639   (0x00000080U) /* PC Read/Write  protection of Sector39 */  
+#define OB_PCROP2_PAGES640TO655   (0x00000100U) /* PC Read/Write  protection of Sector40 */  
+#define OB_PCROP2_PAGES656TO671   (0x00000200U) /* PC Read/Write  protection of Sector41 */  
+#define OB_PCROP2_PAGES672TO687   (0x00000400U) /* PC Read/Write  protection of Sector42 */  
+#define OB_PCROP2_PAGES688TO703   (0x00000800U) /* PC Read/Write  protection of Sector43 */  
+#define OB_PCROP2_PAGES704TO719   (0x00001000U) /* PC Read/Write  protection of Sector44 */  
+#define OB_PCROP2_PAGES720TO735   (0x00002000U) /* PC Read/Write  protection of Sector45 */  
+#define OB_PCROP2_PAGES736TO751   (0x00004000U) /* PC Read/Write  protection of Sector46 */  
+#define OB_PCROP2_PAGES752TO767   (0x00008000U) /* PC Read/Write  protection of Sector47 */  
+#define OB_PCROP2_PAGES768TO783   (0x00010000U) /* PC Read/Write  protection of Sector48 */  
+#define OB_PCROP2_PAGES784TO799   (0x00020000U) /* PC Read/Write  protection of Sector49 */  
+#define OB_PCROP2_PAGES800TO815   (0x00040000U) /* PC Read/Write  protection of Sector50 */  
+#define OB_PCROP2_PAGES816TO831   (0x00080000U) /* PC Read/Write  protection of Sector51 */  
+#define OB_PCROP2_PAGES832TO847   (0x00100000U) /* PC Read/Write  protection of Sector52 */  
+#define OB_PCROP2_PAGES848TO863   (0x00200000U) /* PC Read/Write  protection of Sector53 */  
+#define OB_PCROP2_PAGES864TO879   (0x00400000U) /* PC Read/Write  protection of Sector54 */  
+#define OB_PCROP2_PAGES880TO895   (0x00800000U) /* PC Read/Write  protection of Sector55 */  
+#define OB_PCROP2_PAGES896TO911   (0x01000000U) /* PC Read/Write  protection of Sector56 */  
+#define OB_PCROP2_PAGES912TO927   (0x02000000U) /* PC Read/Write  protection of Sector57 */  
+#define OB_PCROP2_PAGES928TO943   (0x04000000U) /* PC Read/Write  protection of Sector58 */  
+#define OB_PCROP2_PAGES944TO959   (0x08000000U) /* PC Read/Write  protection of Sector59 */  
+#define OB_PCROP2_PAGES960TO975   (0x10000000U) /* PC Read/Write  protection of Sector60 */  
+#define OB_PCROP2_PAGES976TO991   (0x20000000U) /* PC Read/Write  protection of Sector61 */  
+#define OB_PCROP2_PAGES992TO1007  (0x40000000U) /* PC Read/Write  protection of Sector62 */
+#define OB_PCROP2_PAGES1008TO1023 (0x80000000U) /* PC Read/Write  protection of Sector63 */
 
-#define OB_PCROP2_ALLPAGES        ((uint32_t)0xFFFFFFFFU) /*!< PC Read/Write  protection of all Sectors */
+#define OB_PCROP2_ALLPAGES        (0xFFFFFFFFU) /*!< PC Read/Write  protection of all Sectors */
 
 /**
   * @}
@@ -768,9 +766,9 @@
 /** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data
   * @{
   */
-#define FLASH_TYPEERASEDATA_BYTE            ((uint32_t)0x00U)  /*!<Erase byte (8-bit) at a specified address.*/
-#define FLASH_TYPEERASEDATA_HALFWORD        ((uint32_t)0x01U)  /*!<Erase a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEERASEDATA_WORD            ((uint32_t)0x02U)  /*!<Erase a word (32-bit) at a specified address.*/
+#define FLASH_TYPEERASEDATA_BYTE            (0x00U)  /*!<Erase byte (8-bit) at a specified address.*/
+#define FLASH_TYPEERASEDATA_HALFWORD        (0x01U)  /*!<Erase a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEERASEDATA_WORD            (0x02U)  /*!<Erase a word (32-bit) at a specified address.*/
 
 /**
   * @}
@@ -779,12 +777,12 @@
 /** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
   * @{
   */
-#define FLASH_TYPEPROGRAMDATA_BYTE            ((uint32_t)0x00U)  /*!<Program byte (8-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_HALFWORD        ((uint32_t)0x01U)  /*!<Program a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_WORD            ((uint32_t)0x02U)  /*!<Program a word (32-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_FASTBYTE        ((uint32_t)0x04U)  /*!<Fast Program byte (8-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_FASTHALFWORD    ((uint32_t)0x08U)  /*!<Fast Program a half-word (16-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAMDATA_FASTWORD        ((uint32_t)0x10U)  /*!<Fast Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAMDATA_BYTE            (0x00U)  /*!<Program byte (8-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAMDATA_HALFWORD        (0x01U)  /*!<Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAMDATA_WORD            (0x02U)  /*!<Program a word (32-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAMDATA_FASTBYTE        (0x04U)  /*!<Fast Program byte (8-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAMDATA_FASTHALFWORD    (0x08U)  /*!<Fast Program a half-word (16-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAMDATA_FASTWORD        (0x10U)  /*!<Fast Program a word (32-bit) at a specified address.*/
 
 /**
   * @}
@@ -799,7 +797,7 @@
 #define OB_BOOT_BANK2                 ((uint8_t)0x00U) /*!< At startup, if boot pins are set in boot from user Flash position
                                                             and this parameter is selected the device will boot from Bank 2 
                                                             or Bank 1, depending on the activation of the bank */
-#define OB_BOOT_BANK1                 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16)) /*!< At startup, if boot pins are set in boot from user Flash position
+#define OB_BOOT_BANK1                 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16U)) /*!< At startup, if boot pins are set in boot from user Flash position
                                                             and this parameter is selected the device will boot from Bank1(Default) */
 
 /**
@@ -828,7 +826,7 @@
 #define __HAL_FLASH_SET_LATENCY(__LATENCY__)  do  { \
                                                   if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \
                                                   MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \
-                                              } while(0)
+                                              } while(0U)
 
 /**
   * @brief  Get the FLASH Latency.
@@ -863,7 +861,7 @@
   */ 
 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    do  { __HAL_FLASH_ACC64_ENABLE(); \
                                                   SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \
-                                                } while(0)
+                                                } while(0U)
 
 /**
   * @brief  Disable the FLASH prefetch buffer.
@@ -891,7 +889,7 @@
 #define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1;    \
                                              FLASH->PDKEYR = FLASH_PDKEY2;    \
                                              SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD);  \
-                                           } while (0)
+                                           } while (0U)
 
 /**
   * @brief  Disable the Flash Run power down mode.
@@ -901,7 +899,7 @@
 #define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1;    \
                                               FLASH->PDKEYR = FLASH_PDKEY2;    \
                                              CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD);  \
-                                            } while (0)
+                                            } while (0U)
                                             
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ramfunc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ramfunc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_flash_ramfunc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   FLASH RAMFUNC driver.
   *          This file provides a Flash firmware functions which should be 
   *          executed from internal SRAM
@@ -32,7 +30,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -195,9 +193,9 @@
     SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
   
     /* Write 00000000h to the first word of the first program page to erase */
-    *(__IO uint32_t *)Page_Address1 = 0x00000000;
+    *(__IO uint32_t *)Page_Address1 = 0x00000000U;
     /* Write 00000000h to the first word of the second program page to erase */    
-    *(__IO uint32_t *)Page_Address2 = 0x00000000;    
+    *(__IO uint32_t *)Page_Address2 = 0x00000000U;
  
     /* Wait for last operation to be completed */
     status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@@ -243,10 +241,10 @@
   */
 __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
 {
-  uint32_t count = 0; 
+  uint32_t count = 0U; 
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) 
+  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U) 
      This bit prevents the interruption of multicycle instructions and therefore 
      will increase the interrupt latency. of Cortex-M3. */
   SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
@@ -269,7 +267,7 @@
       __disable_irq();
 
       /* Write the first half page directly with 32 different words */
-      while(count < 32)
+      while(count < 32U)
       {
         *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1;
         pBuffer1++;
@@ -277,8 +275,8 @@
       }
 
       /* Write the second half page directly with 32 different words */
-      count = 0;
-      while(count < 32)
+      count = 0U;
+      while(count < 32U)
       {
         *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2;
         pBuffer2++;
@@ -331,10 +329,10 @@
   */
 __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
 {
-  uint32_t count = 0; 
+  uint32_t count = 0U; 
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) 
+  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U) 
      This bit prevents the interruption of multicycle instructions and therefore 
      will increase the interrupt latency. of Cortex-M3. */
   SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
@@ -352,18 +350,18 @@
     __disable_irq();
 
     /* Write one half page directly with 32 different words */
-    while(count < 32)
+    while(count < 32U)
     {
       *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer;
       pBuffer++;
       count ++;  
     }
 
+    /* Wait for last operation to be completed */
+    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
+
     /* Enable IRQs */
     __enable_irq();
-
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
  
     /* If the write operation is completed, disable the PROG and FPRG bits */
     CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
@@ -462,7 +460,7 @@
 {
   HAL_StatusTypeDef status = HAL_OK;
   
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) 
+  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U) 
      This bit prevents the interruption of multicycle instructions and therefore 
      will increase the interrupt latency. of Cortex-M3. */
   SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
@@ -480,9 +478,9 @@
     SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
    
     /* Write 00000000h to the 2 words to erase */
-    *(__IO uint32_t *)Address = 0x00000000;
-    Address += 4;
-    *(__IO uint32_t *)Address = 0x00000000;
+    *(__IO uint32_t *)Address = 0x00000000U;
+    Address += 4U;
+    *(__IO uint32_t *)Address = 0x00000000U;
    
     /* Wait for last operation to be completed */
     status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
@@ -520,7 +518,7 @@
 {
   HAL_StatusTypeDef status = HAL_OK;
 
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) 
+  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U) 
      This bit prevents the interruption of multicycle instructions and therefore 
      will increase the interrupt latency. of Cortex-M3. */
   SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
@@ -536,7 +534,7 @@
     
     /* Write the 2 words */  
      *(__IO uint32_t *)Address = (uint32_t) Data;
-     Address += 4;
+     Address += 4U;
      *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
     
     /* Wait for last operation to be completed */
@@ -571,7 +569,7 @@
   */
 static __RAM_FUNC FLASHRAM_SetErrorCode(void)
 {
-  uint32_t flags = 0;
+  uint32_t flags = 0U;
   
   if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
   {
@@ -621,12 +619,12 @@
        Even if the FLASH operation fails, the BUSY flag will be reset and an error
        flag will be set */
        
-    while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00)) 
+    while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U)) 
     { 
       Timeout--;
     }
     
-    if(Timeout == 0x00 )
+    if(Timeout == 0x00U)
     {
       return HAL_TIMEOUT;
     }

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ramfunc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ramfunc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_flash_ramfunc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of FLASH RAMFUNC driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_gpio.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_gpio.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_gpio.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   GPIO HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -105,7 +103,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -151,15 +149,15 @@
 /** @addtogroup GPIO_Private_Constants
   * @{
   */
-#define GPIO_MODE             ((uint32_t)0x00000003)
-#define EXTI_MODE             ((uint32_t)0x10000000)
-#define GPIO_MODE_IT          ((uint32_t)0x00010000)
-#define GPIO_MODE_EVT         ((uint32_t)0x00020000)
-#define RISING_EDGE           ((uint32_t)0x00100000)
-#define FALLING_EDGE          ((uint32_t)0x00200000)
-#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
+#define GPIO_MODE             (0x00000003U)
+#define EXTI_MODE             (0x10000000U)
+#define GPIO_MODE_IT          (0x00010000U)
+#define GPIO_MODE_EVT         (0x00020000U)
+#define RISING_EDGE           (0x00100000U)
+#define FALLING_EDGE          (0x00200000U)
+#define GPIO_OUTPUT_TYPE      (0x00000010U)
 
-#define GPIO_NUMBER           ((uint32_t)16)
+#define GPIO_NUMBER           (16U)
  
 /**
   * @}
@@ -209,7 +207,7 @@
   while (((GPIO_Init->Pin) >> position) != 0)
   {
     /* Get current io position */
-    iocurrent = (GPIO_Init->Pin) & ((uint32_t)1 << position);
+    iocurrent = (GPIO_Init->Pin) & (1U << position);
     
     if(iocurrent)
     {
@@ -224,8 +222,8 @@
         /* Configure Alternate function mapped with the current IO */ 
         /* Identify AFRL or AFRH register based on IO position*/
         temp = GPIOx->AFR[position >> 3];
-        CLEAR_BIT(temp, (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;      
-        SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));       
+        CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)) ;      
+        SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));       
         GPIOx->AFR[position >> 3] = temp;
       }
 
@@ -268,7 +266,7 @@
         __HAL_RCC_SYSCFG_CLK_ENABLE();
         
         temp = SYSCFG->EXTICR[position >> 2];
-        CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03)));
+        CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
         SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
         SYSCFG->EXTICR[position >> 2] = temp;
                   
@@ -333,7 +331,7 @@
   while ((GPIO_Pin >> position) != 0)
   {
     /* Get current io position */
-    iocurrent = (GPIO_Pin) & ((uint32_t)1 << position);
+    iocurrent = (GPIO_Pin) & (1U << position);
 
     if (iocurrent)
     {
@@ -342,7 +340,7 @@
       CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2)); 
   
       /* Configure the default Alternate Function in current IO */ 
-      CLEAR_BIT(GPIOx->AFR[position >> 3], (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+      CLEAR_BIT(GPIOx->AFR[position >> 3], 0xFU << ((uint32_t)(position & 0x07U) * 4)) ;
   
       /* Configure the default value for IO Speed */
       CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
@@ -357,10 +355,10 @@
       /* Clear the External Interrupt or Event for the current IO */
       
       tmp = SYSCFG->EXTICR[position >> 2];
-      tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+      tmp &= ((0x0FU) << (4 * (position & 0x03)));
       if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
       {
-        tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+        tmp = (0x0FU) << (4 * (position & 0x03));
         CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp);
         
         /* Clear EXTI line configuration */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_gpio.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_gpio.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_gpio.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of GPIO HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -103,25 +101,25 @@
 /** @defgroup GPIO_pins GPIO pins
   * @{
   */
-#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
-#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
-#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
-#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
-#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
-#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
-#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
-#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
-#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
-#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
-#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
-#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
-#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
-#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
-#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
-#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
-#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+#define GPIO_PIN_0                 ((uint16_t)0x0001U)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002U)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004U)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008U)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010U)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020U)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040U)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080U)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100U)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200U)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400U)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800U)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000U)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000U)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000U)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000U)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFFU)  /* All pins selected */
 
-#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+#define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */
 /**
   * @}
   */
@@ -136,21 +134,21 @@
   *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
   * @{
   */ 
-#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
+#define  GPIO_MODE_INPUT                        (0x00000000U)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    (0x00000001U)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    (0x00000011U)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        (0x00000002U)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        (0x00000012U)   /*!< Alternate Function Open Drain Mode    */
 
-#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
+#define  GPIO_MODE_ANALOG                       (0x00000003U)   /*!< Analog Mode  */
     
-#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+#define  GPIO_MODE_IT_RISING                    (0x10110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   (0x10210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            (0x10310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
 
-#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
-#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
-#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+#define  GPIO_MODE_EVT_RISING                   (0x10120000U)   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  (0x10220000U)   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           (0x10320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
 
 /**
   * @}
@@ -160,10 +158,10 @@
   * @brief GPIO Output Maximum frequency
   * @{
   */  
-#define  GPIO_SPEED_FREQ_LOW       ((uint32_t)0x00000000) /*!< max: 400 KHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_MEDIUM    ((uint32_t)0x00000001) /*!< max: 1 MHz to 2 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_HIGH      ((uint32_t)0x00000002) /*!< max: 2 MHz to 10 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< max: 8 MHz to 50 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_LOW       (0x00000000U) /*!< max: 400 KHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_MEDIUM    (0x00000001U) /*!< max: 1 MHz to 2 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_HIGH      (0x00000002U) /*!< max: 2 MHz to 10 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< max: 8 MHz to 50 MHz, please refer to the product datasheet */
 
 /**
   * @}
@@ -173,9 +171,9 @@
    * @brief GPIO Pull-Up or Pull-Down Activation
    * @{
    */  
-#define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
+#define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */
 
 /**
   * @}
@@ -201,8 +199,8 @@
 
 #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
 
-#define IS_GPIO_PIN(__PIN__)        ((((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00) &&\
-                                     (((__PIN__) & ~GPIO_PIN_MASK) == (uint32_t)0x00))
+#define IS_GPIO_PIN(__PIN__)        ((((__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
+                                     (((__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
 
 #define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
                             ((PULL) == GPIO_PULLDOWN))

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_gpio_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_gpio_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_gpio_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of GPIO HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_i2c.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   I2C HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -211,7 +209,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -257,12 +255,12 @@
 /** @defgroup I2C_Private_Define I2C Private Define
   * @{
   */
-#define I2C_TIMEOUT_FLAG          ((uint32_t)35U)         /*!< Timeout 35 ms             */
-#define I2C_TIMEOUT_ADDR_SLAVE    ((uint32_t)10000U)      /*!< Timeout 10 s              */
-#define I2C_TIMEOUT_BUSY_FLAG     ((uint32_t)25U)         /*!< Timeout 25 ms             */
-#define I2C_NO_OPTION_FRAME       ((uint32_t)0xFFFF0000U) /*!< XferOptions default value */
-
-#define I2C_MIN_PCLK_FREQ         ((uint32_t)2000000U)    /*!< 2 MHz                     */
+#define I2C_TIMEOUT_FLAG          (35U)         /*!< Timeout 35 ms             */
+#define I2C_TIMEOUT_ADDR_SLAVE    (10000U)      /*!< Timeout 10 s              */
+#define I2C_TIMEOUT_BUSY_FLAG     (25U)         /*!< Timeout 25 ms             */
+#define I2C_NO_OPTION_FRAME       (0xFFFF0000U) /*!< XferOptions default value */
+
+#define I2C_MIN_PCLK_FREQ         (2000000U)    /*!< 2 MHz                     */
 
 /* Private define for @ref PreviousState usage */
 #define I2C_STATE_MSK             ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /*!< Mask State define, keep only RX and TX bits            */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2c.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_i2c.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of I2C HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -179,13 +177,13 @@
   * @brief  I2C Error Code definition  
   * @{
   */ 
-#define HAL_I2C_ERROR_NONE       ((uint32_t)0x00000000U)    /*!< No error           */
-#define HAL_I2C_ERROR_BERR       ((uint32_t)0x00000001U)    /*!< BERR error         */
-#define HAL_I2C_ERROR_ARLO       ((uint32_t)0x00000002U)    /*!< ARLO error         */
-#define HAL_I2C_ERROR_AF         ((uint32_t)0x00000004U)    /*!< AF error           */
-#define HAL_I2C_ERROR_OVR        ((uint32_t)0x00000008U)    /*!< OVR error          */
-#define HAL_I2C_ERROR_DMA        ((uint32_t)0x00000010U)    /*!< DMA transfer error */
-#define HAL_I2C_ERROR_TIMEOUT    ((uint32_t)0x00000020U)    /*!< Timeout Error      */
+#define HAL_I2C_ERROR_NONE       (0x00000000U)    /*!< No error           */
+#define HAL_I2C_ERROR_BERR       (0x00000001U)    /*!< BERR error         */
+#define HAL_I2C_ERROR_ARLO       (0x00000002U)    /*!< ARLO error         */
+#define HAL_I2C_ERROR_AF         (0x00000004U)    /*!< AF error           */
+#define HAL_I2C_ERROR_OVR        (0x00000008U)    /*!< OVR error          */
+#define HAL_I2C_ERROR_DMA        (0x00000010U)    /*!< DMA transfer error */
+#define HAL_I2C_ERROR_TIMEOUT    (0x00000020U)    /*!< Timeout Error      */
 /**
   * @}
   */
@@ -248,7 +246,7 @@
 /** @defgroup I2C_duty_cycle_in_fast_mode I2C duty cycle in fast mode
   * @{
   */
-#define I2C_DUTYCYCLE_2                 ((uint32_t)0x00000000U)
+#define I2C_DUTYCYCLE_2                 (0x00000000U)
 #define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
 /**
   * @}
@@ -257,8 +255,8 @@
 /** @defgroup I2C_addressing_mode I2C addressing mode
   * @{
   */
-#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00004000U)
-#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000U))
+#define I2C_ADDRESSINGMODE_7BIT         (0x00004000U)
+#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | (0x00004000U))
 /**
   * @}
   */
@@ -266,7 +264,7 @@
 /** @defgroup I2C_dual_addressing_mode  I2C dual addressing mode
   * @{
   */
-#define I2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000U)
+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
 #define I2C_DUALADDRESS_ENABLE          I2C_OAR2_ENDUAL
 /**
   * @}
@@ -275,7 +273,7 @@
 /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
   * @{
   */
-#define I2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000U)
+#define I2C_GENERALCALL_DISABLE         (0x00000000U)
 #define I2C_GENERALCALL_ENABLE          I2C_CR1_ENGC
 /**
   * @}
@@ -284,7 +282,7 @@
 /** @defgroup I2C_nostretch_mode I2C nostretch mode
   * @{
   */
-#define I2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000U)
+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
 #define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
 /**
   * @}
@@ -293,8 +291,8 @@
 /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
   * @{
   */
-#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001U)
-#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000010U)
+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
+#define I2C_MEMADD_SIZE_16BIT           (0x00000010U)
 /**
   * @}
   */
@@ -302,8 +300,8 @@
 /** @defgroup I2C_XferDirection_definition I2C XferDirection definition Master Point of View
   * @{
   */
-#define I2C_DIRECTION_RECEIVE           ((uint32_t)0x00000000U) 
-#define I2C_DIRECTION_TRANSMIT          ((uint32_t)0x00000001U)
+#define I2C_DIRECTION_RECEIVE           (0x00000000U) 
+#define I2C_DIRECTION_TRANSMIT          (0x00000001U)
 /**
   * @}
   */
@@ -311,10 +309,10 @@
 /** @defgroup I2C_XferOptions_definition I2C XferOptions definition
   * @{
   */
-#define  I2C_FIRST_FRAME                ((uint32_t)0x00000001U)
-#define  I2C_NEXT_FRAME                 ((uint32_t)0x00000002U)
-#define  I2C_FIRST_AND_LAST_FRAME       ((uint32_t)0x00000004U)
-#define  I2C_LAST_FRAME                 ((uint32_t)0x00000008U)
+#define  I2C_FIRST_FRAME                (0x00000001U)
+#define  I2C_NEXT_FRAME                 (0x00000002U)
+#define  I2C_FIRST_AND_LAST_FRAME       (0x00000004U)
+#define  I2C_LAST_FRAME                 (0x00000008U)
 /**
   * @}
   */
@@ -581,7 +579,7 @@
 /** @defgroup I2C_Private_Constants I2C Private Constants
   * @{
   */
-#define I2C_FLAG_MASK  ((uint32_t)0x0000FFFFU)
+#define I2C_FLAG_MASK  (0x0000FFFFU)
 /**
   * @}
   */ 

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_i2s.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   I2S HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -108,7 +106,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -279,7 +277,7 @@
     tmp = tmp / 10;  
 
     /* Check the parity of the divider */
-    i2sodd = (uint32_t)(tmp & (uint32_t)1);
+    i2sodd = (uint32_t)(tmp & 1U);
 
     /* Compute the i2sdiv prescaler */
     i2sdiv = (uint32_t)((tmp - i2sodd) / 2);

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_i2s.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_i2s.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of I2S HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -153,11 +151,11 @@
   * @{
   */
 
-#define HAL_I2S_ERROR_NONE      ((uint32_t)0x00)    /*!< No error                    */
-#define HAL_I2S_ERROR_UDR       ((uint32_t)0x01)    /*!< I2S Underrun error          */
-#define HAL_I2S_ERROR_OVR       ((uint32_t)0x02)    /*!< I2S Overrun error           */
-#define HAL_I2S_ERROR_FRE       ((uint32_t)0x04)    /*!< I2S Frame format error      */
-#define HAL_I2S_ERROR_DMA       ((uint32_t)0x08)    /*!< DMA transfer error          */
+#define HAL_I2S_ERROR_NONE      (0x00U)    /*!< No error                    */
+#define HAL_I2S_ERROR_UDR       (0x01U)    /*!< I2S Underrun error          */
+#define HAL_I2S_ERROR_OVR       (0x02U)    /*!< I2S Overrun error           */
+#define HAL_I2S_ERROR_FRE       (0x04U)    /*!< I2S Frame format error      */
+#define HAL_I2S_ERROR_DMA       (0x08U)    /*!< DMA transfer error          */
 
 /**
   * @}
@@ -166,10 +164,10 @@
 /** @defgroup I2S_Mode I2S Mode
   * @{
   */
-#define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000)
-#define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100)
-#define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200)
-#define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300)
+#define I2S_MODE_SLAVE_TX                (0x00000000U)
+#define I2S_MODE_SLAVE_RX                (0x00000100U)
+#define I2S_MODE_MASTER_TX               (0x00000200U)
+#define I2S_MODE_MASTER_RX               (0x00000300U)
 
 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX)  || \
                            ((MODE) == I2S_MODE_SLAVE_RX)  || \
@@ -182,7 +180,7 @@
 /** @defgroup I2S_Standard I2S Standard
   * @{
   */
-#define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000)
+#define I2S_STANDARD_PHILIPS             (0x00000000U)
 #define I2S_STANDARD_MSB                 ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
 #define I2S_STANDARD_LSB                 ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
 #define I2S_STANDARD_PCM_SHORT           ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
@@ -204,7 +202,7 @@
 /** @defgroup I2S_Data_Format I2S Data Format
   * @{
   */
-#define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000)
+#define I2S_DATAFORMAT_16B               (0x00000000U)
 #define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t) SPI_I2SCFGR_CHLEN)
 #define I2S_DATAFORMAT_24B               ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
 #define I2S_DATAFORMAT_32B               ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
@@ -221,7 +219,7 @@
   * @{
   */
 #define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000)
+#define I2S_MCLKOUTPUT_DISABLE          (0x00000000U)
 
 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
                                     ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
@@ -232,16 +230,16 @@
 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
   * @{
   */
-#define I2S_AUDIOFREQ_192K               ((uint32_t)192000)
-#define I2S_AUDIOFREQ_96K                ((uint32_t)96000)
-#define I2S_AUDIOFREQ_48K                ((uint32_t)48000)
-#define I2S_AUDIOFREQ_44K                ((uint32_t)44100)
-#define I2S_AUDIOFREQ_32K                ((uint32_t)32000)
-#define I2S_AUDIOFREQ_22K                ((uint32_t)22050)
-#define I2S_AUDIOFREQ_16K                ((uint32_t)16000)
-#define I2S_AUDIOFREQ_11K                ((uint32_t)11025)
-#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000)
-#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2)
+#define I2S_AUDIOFREQ_192K               (192000U)
+#define I2S_AUDIOFREQ_96K                (96000U)
+#define I2S_AUDIOFREQ_48K                (48000U)
+#define I2S_AUDIOFREQ_44K                (44100U)
+#define I2S_AUDIOFREQ_32K                (32000U)
+#define I2S_AUDIOFREQ_22K                (22050U)
+#define I2S_AUDIOFREQ_16K                (16000U)
+#define I2S_AUDIOFREQ_11K                (11025U)
+#define I2S_AUDIOFREQ_8K                 (8000U)
+#define I2S_AUDIOFREQ_DEFAULT            (2U)
 
 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K)    && \
                                   ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
@@ -253,7 +251,7 @@
 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
   * @{
   */
-#define I2S_CPOL_LOW                    ((uint32_t)0x00000000)
+#define I2S_CPOL_LOW                    (0x00000000U)
 #define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
 
 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_irda.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_irda.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_irda.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   IRDA HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the IrDA SIR ENDEC block (IrDA):
@@ -103,7 +101,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_irda.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_irda.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,14 +2,12 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_irda.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   This file contains all the functions prototypes for the IRDA 
   *          firmware library.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -154,12 +152,12 @@
 /** @defgroup IRDA_Error_Codes IRDA Error Codes
   * @{
   */
-#define HAL_IRDA_ERROR_NONE      ((uint32_t)0x00)    /*!< No error            */
-#define HAL_IRDA_ERROR_PE        ((uint32_t)0x01)    /*!< Parity error        */
-#define HAL_IRDA_ERROR_NE        ((uint32_t)0x02)    /*!< Noise error         */
-#define HAL_IRDA_ERROR_FE        ((uint32_t)0x04)    /*!< frame error         */
-#define HAL_IRDA_ERROR_ORE       ((uint32_t)0x08)    /*!< Overrun error       */
-#define HAL_IRDA_ERROR_DMA       ((uint32_t)0x10)    /*!< DMA transfer error  */
+#define HAL_IRDA_ERROR_NONE      (0x00U)    /*!< No error            */
+#define HAL_IRDA_ERROR_PE        (0x01U)    /*!< Parity error        */
+#define HAL_IRDA_ERROR_NE        (0x02U)    /*!< Noise error         */
+#define HAL_IRDA_ERROR_FE        (0x04U)    /*!< frame error         */
+#define HAL_IRDA_ERROR_ORE       (0x08U)    /*!< Overrun error       */
+#define HAL_IRDA_ERROR_DMA       (0x10U)    /*!< DMA transfer error  */
 
 /**
   * @}
@@ -169,7 +167,7 @@
 /** @defgroup IRDA_Word_Length IRDA Word Length
   * @{
   */
-#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)
+#define IRDA_WORDLENGTH_8B                  (0x00000000U)
 #define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
 /**
   * @}
@@ -178,7 +176,7 @@
 /** @defgroup IRDA_Parity IRDA Parity
   * @{
   */
-#define IRDA_PARITY_NONE                    ((uint32_t)0x00000000)
+#define IRDA_PARITY_NONE                    (0x00000000U)
 #define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
 #define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
 /**
@@ -199,7 +197,7 @@
   * @{
   */
 #define IRDA_POWERMODE_LOWPOWER             ((uint32_t)USART_CR3_IRLP)
-#define IRDA_POWERMODE_NORMAL               ((uint32_t)0x00000000)
+#define IRDA_POWERMODE_NORMAL               (0x00000000U)
 /**
   * @}
   */
@@ -207,7 +205,7 @@
 /** @defgroup IRDA_One_Bit  IRDA One Bit Sampling
   * @{
   */
-#define IRDA_ONE_BIT_SAMPLE_DISABLE         ((uint32_t)0x00000000)
+#define IRDA_ONE_BIT_SAMPLE_DISABLE         (0x00000000U)
 #define IRDA_ONE_BIT_SAMPLE_ENABLE          ((uint32_t)USART_CR3_ONEBIT)
 /**
   * @}
@@ -485,7 +483,7 @@
                                         ((PARITY) == IRDA_PARITY_ODD))
 
 #define IS_IRDA_MODE(MODE)             ((((MODE) & (~((uint32_t)IRDA_MODE_TX_RX))) == 0x00) && \
-                                        ((MODE) != (uint32_t)0x00000000))
+                                        ((MODE) != 0x00000000U))
 
 #define IS_IRDA_POWERMODE(MODE)        (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
                                         ((MODE) == IRDA_POWERMODE_NORMAL))

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_iwdg.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_iwdg.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_iwdg.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   IWDG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Independent Watchdog (IWDG) peripheral:
@@ -75,7 +73,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_iwdg.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_iwdg.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_iwdg.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of IWDG HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_lcd.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_lcd.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_lcd.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   LCD Controller HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the LCD Controller (LCD) peripheral:
@@ -63,7 +61,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_lcd.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_lcd.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_lcd.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of LCD Controller HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -139,12 +137,12 @@
   * @{
   */
 
-#define HAL_LCD_ERROR_NONE      ((uint32_t)0x00)    /*!< No error */
-#define HAL_LCD_ERROR_FCRSF     ((uint32_t)0x01)    /*!< Synchro flag timeout error */
-#define HAL_LCD_ERROR_UDR       ((uint32_t)0x02)    /*!< Update display request flag timeout error */
-#define HAL_LCD_ERROR_UDD       ((uint32_t)0x04)    /*!< Update display done flag timeout error */
-#define HAL_LCD_ERROR_ENS       ((uint32_t)0x08)    /*!< LCD enabled status flag timeout error */
-#define HAL_LCD_ERROR_RDY       ((uint32_t)0x10)    /*!< LCD Booster ready timeout error */
+#define HAL_LCD_ERROR_NONE      (0x00U)    /*!< No error */
+#define HAL_LCD_ERROR_FCRSF     (0x01U)    /*!< Synchro flag timeout error */
+#define HAL_LCD_ERROR_UDR       (0x02U)    /*!< Update display request flag timeout error */
+#define HAL_LCD_ERROR_UDD       (0x04U)    /*!< Update display done flag timeout error */
+#define HAL_LCD_ERROR_ENS       (0x08U)    /*!< LCD enabled status flag timeout error */
+#define HAL_LCD_ERROR_RDY       (0x10U)    /*!< LCD Booster ready timeout error */
 
 /**
   * @}
@@ -154,21 +152,21 @@
   * @{
   */
 
-#define LCD_PRESCALER_1        ((uint32_t)0x00000000)  /*!< CLKPS = LCDCLK        */
-#define LCD_PRESCALER_2        ((uint32_t)0x00400000)  /*!< CLKPS = LCDCLK/2      */
-#define LCD_PRESCALER_4        ((uint32_t)0x00800000)  /*!< CLKPS = LCDCLK/4      */
-#define LCD_PRESCALER_8        ((uint32_t)0x00C00000)  /*!< CLKPS = LCDCLK/8      */
-#define LCD_PRESCALER_16       ((uint32_t)0x01000000)  /*!< CLKPS = LCDCLK/16     */
-#define LCD_PRESCALER_32       ((uint32_t)0x01400000)  /*!< CLKPS = LCDCLK/32     */
-#define LCD_PRESCALER_64       ((uint32_t)0x01800000)  /*!< CLKPS = LCDCLK/64     */
-#define LCD_PRESCALER_128      ((uint32_t)0x01C00000)  /*!< CLKPS = LCDCLK/128    */
-#define LCD_PRESCALER_256      ((uint32_t)0x02000000)  /*!< CLKPS = LCDCLK/256    */
-#define LCD_PRESCALER_512      ((uint32_t)0x02400000)  /*!< CLKPS = LCDCLK/512    */
-#define LCD_PRESCALER_1024     ((uint32_t)0x02800000)  /*!< CLKPS = LCDCLK/1024   */
-#define LCD_PRESCALER_2048     ((uint32_t)0x02C00000)  /*!< CLKPS = LCDCLK/2048   */
-#define LCD_PRESCALER_4096     ((uint32_t)0x03000000)  /*!< CLKPS = LCDCLK/4096   */
-#define LCD_PRESCALER_8192     ((uint32_t)0x03400000)  /*!< CLKPS = LCDCLK/8192   */
-#define LCD_PRESCALER_16384    ((uint32_t)0x03800000)  /*!< CLKPS = LCDCLK/16384  */
+#define LCD_PRESCALER_1        (0x00000000U)           /*!< CLKPS = LCDCLK        */
+#define LCD_PRESCALER_2        (0x00400000U)           /*!< CLKPS = LCDCLK/2      */
+#define LCD_PRESCALER_4        (0x00800000U)           /*!< CLKPS = LCDCLK/4      */
+#define LCD_PRESCALER_8        (0x00C00000U)           /*!< CLKPS = LCDCLK/8      */
+#define LCD_PRESCALER_16       (0x01000000U)           /*!< CLKPS = LCDCLK/16     */
+#define LCD_PRESCALER_32       (0x01400000U)           /*!< CLKPS = LCDCLK/32     */
+#define LCD_PRESCALER_64       (0x01800000U)           /*!< CLKPS = LCDCLK/64     */
+#define LCD_PRESCALER_128      (0x01C00000U)           /*!< CLKPS = LCDCLK/128    */
+#define LCD_PRESCALER_256      (0x02000000U)           /*!< CLKPS = LCDCLK/256    */
+#define LCD_PRESCALER_512      (0x02400000U)           /*!< CLKPS = LCDCLK/512    */
+#define LCD_PRESCALER_1024     (0x02800000U)           /*!< CLKPS = LCDCLK/1024   */
+#define LCD_PRESCALER_2048     (0x02C00000U)           /*!< CLKPS = LCDCLK/2048   */
+#define LCD_PRESCALER_4096     (0x03000000U)           /*!< CLKPS = LCDCLK/4096   */
+#define LCD_PRESCALER_8192     (0x03400000U)           /*!< CLKPS = LCDCLK/8192   */
+#define LCD_PRESCALER_16384    (0x03800000U)           /*!< CLKPS = LCDCLK/16384  */
 #define LCD_PRESCALER_32768    ((uint32_t)LCD_FCR_PS)  /*!< CLKPS = LCDCLK/32768  */
 
 #define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1)     || \
@@ -196,21 +194,21 @@
   * @{
   */
 
-#define LCD_DIVIDER_16    ((uint32_t)0x00000000)  /*!< LCD frequency = CLKPS/16 */
-#define LCD_DIVIDER_17    ((uint32_t)0x00040000)  /*!< LCD frequency = CLKPS/17 */
-#define LCD_DIVIDER_18    ((uint32_t)0x00080000)  /*!< LCD frequency = CLKPS/18 */
-#define LCD_DIVIDER_19    ((uint32_t)0x000C0000)  /*!< LCD frequency = CLKPS/19 */
-#define LCD_DIVIDER_20    ((uint32_t)0x00100000)  /*!< LCD frequency = CLKPS/20 */
-#define LCD_DIVIDER_21    ((uint32_t)0x00140000)  /*!< LCD frequency = CLKPS/21 */
-#define LCD_DIVIDER_22    ((uint32_t)0x00180000)  /*!< LCD frequency = CLKPS/22 */
-#define LCD_DIVIDER_23    ((uint32_t)0x001C0000)  /*!< LCD frequency = CLKPS/23 */
-#define LCD_DIVIDER_24    ((uint32_t)0x00200000)  /*!< LCD frequency = CLKPS/24 */
-#define LCD_DIVIDER_25    ((uint32_t)0x00240000)  /*!< LCD frequency = CLKPS/25 */
-#define LCD_DIVIDER_26    ((uint32_t)0x00280000)  /*!< LCD frequency = CLKPS/26 */
-#define LCD_DIVIDER_27    ((uint32_t)0x002C0000)  /*!< LCD frequency = CLKPS/27 */
-#define LCD_DIVIDER_28    ((uint32_t)0x00300000)  /*!< LCD frequency = CLKPS/28 */
-#define LCD_DIVIDER_29    ((uint32_t)0x00340000)  /*!< LCD frequency = CLKPS/29 */
-#define LCD_DIVIDER_30    ((uint32_t)0x00380000)  /*!< LCD frequency = CLKPS/30 */
+#define LCD_DIVIDER_16    (0x00000000U)           /*!< LCD frequency = CLKPS/16 */
+#define LCD_DIVIDER_17    (0x00040000U)           /*!< LCD frequency = CLKPS/17 */
+#define LCD_DIVIDER_18    (0x00080000U)           /*!< LCD frequency = CLKPS/18 */
+#define LCD_DIVIDER_19    (0x000C0000U)           /*!< LCD frequency = CLKPS/19 */
+#define LCD_DIVIDER_20    (0x00100000U)           /*!< LCD frequency = CLKPS/20 */
+#define LCD_DIVIDER_21    (0x00140000U)           /*!< LCD frequency = CLKPS/21 */
+#define LCD_DIVIDER_22    (0x00180000U)           /*!< LCD frequency = CLKPS/22 */
+#define LCD_DIVIDER_23    (0x001C0000U)           /*!< LCD frequency = CLKPS/23 */
+#define LCD_DIVIDER_24    (0x00200000U)           /*!< LCD frequency = CLKPS/24 */
+#define LCD_DIVIDER_25    (0x00240000U)           /*!< LCD frequency = CLKPS/25 */
+#define LCD_DIVIDER_26    (0x00280000U)           /*!< LCD frequency = CLKPS/26 */
+#define LCD_DIVIDER_27    (0x002C0000U)           /*!< LCD frequency = CLKPS/27 */
+#define LCD_DIVIDER_28    (0x00300000U)           /*!< LCD frequency = CLKPS/28 */
+#define LCD_DIVIDER_29    (0x00340000U)           /*!< LCD frequency = CLKPS/29 */
+#define LCD_DIVIDER_30    (0x00380000U)           /*!< LCD frequency = CLKPS/30 */
 #define LCD_DIVIDER_31    ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */
 
 #define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
@@ -239,7 +237,7 @@
   * @{
   */
   
-#define LCD_DUTY_STATIC                 ((uint32_t)0x00000000)            /*!< Static duty */
+#define LCD_DUTY_STATIC                 (0x00000000U)                     /*!< Static duty */
 #define LCD_DUTY_1_2                    (LCD_CR_DUTY_0)                   /*!< 1/2 duty    */
 #define LCD_DUTY_1_3                    (LCD_CR_DUTY_1)                   /*!< 1/3 duty    */
 #define LCD_DUTY_1_4                    ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty    */
@@ -260,7 +258,7 @@
   * @{
   */
   
-#define LCD_BIAS_1_4                    ((uint32_t)0x00000000)  /*!< 1/4 Bias */
+#define LCD_BIAS_1_4                    (0x00000000U)           /*!< 1/4 Bias */
 #define LCD_BIAS_1_2                    LCD_CR_BIAS_0           /*!< 1/2 Bias */
 #define LCD_BIAS_1_3                    LCD_CR_BIAS_1           /*!< 1/3 Bias */
 
@@ -275,7 +273,7 @@
   * @{
   */
   
-#define LCD_VOLTAGESOURCE_INTERNAL      ((uint32_t)0x00000000)  /*!< Internal voltage source for the LCD */
+#define LCD_VOLTAGESOURCE_INTERNAL      (0x00000000U)           /*!< Internal voltage source for the LCD */
 #define LCD_VOLTAGESOURCE_EXTERNAL      LCD_CR_VSEL             /*!< External voltage source for the LCD */
 
 #define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
@@ -299,7 +297,7 @@
   * @{
   */
 
-#define LCD_PULSEONDURATION_0           ((uint32_t)0x00000000)          /*!< Pulse ON duration = 0 pulse   */
+#define LCD_PULSEONDURATION_0           (0x00000000U)                   /*!< Pulse ON duration = 0 pulse   */
 #define LCD_PULSEONDURATION_1           (LCD_FCR_PON_0)                 /*!< Pulse ON duration = 1/CK_PS  */
 #define LCD_PULSEONDURATION_2           (LCD_FCR_PON_1)                 /*!< Pulse ON duration = 2/CK_PS  */
 #define LCD_PULSEONDURATION_3           (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS  */
@@ -324,7 +322,7 @@
   * @{
   */
 
-#define LCD_HIGHDRIVE_0           ((uint32_t)0x00000000)          /*!< Low resistance Drive   */
+#define LCD_HIGHDRIVE_0           (0x00000000U)                   /*!< Low resistance Drive   */
 #define LCD_HIGHDRIVE_1           (LCD_FCR_HD)                    /*!< High resistance Drive  */
 
 #define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \
@@ -337,7 +335,7 @@
   * @{
   */
 
-#define LCD_DEADTIME_0                  ((uint32_t)0x00000000)            /*!< No dead Time  */
+#define LCD_DEADTIME_0                  (0x00000000U)                     /*!< No dead Time  */
 #define LCD_DEADTIME_1                  (LCD_FCR_DEAD_0)                  /*!< One Phase between different couple of Frame   */
 #define LCD_DEADTIME_2                  (LCD_FCR_DEAD_1)                  /*!< Two Phase between different couple of Frame   */
 #define LCD_DEADTIME_3                  (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
@@ -362,7 +360,7 @@
   * @{
   */
 
-#define LCD_BLINKMODE_OFF               ((uint32_t)0x00000000)  /*!< Blink disabled            */
+#define LCD_BLINKMODE_OFF               (0x00000000U)           /*!< Blink disabled            */
 #define LCD_BLINKMODE_SEG0_COM0         (LCD_FCR_BLINK_0)       /*!< Blink enabled on SEG[0], COM[0] (1 pixel)   */
 #define LCD_BLINKMODE_SEG0_ALLCOM       (LCD_FCR_BLINK_1)       /*!< Blink enabled on SEG[0], all COM (up to 
                                                                     8 pixels according to the programmed duty)  */
@@ -380,7 +378,7 @@
   * @{
   */
 
-#define LCD_BLINKFREQUENCY_DIV8         ((uint32_t)0x00000000)                /*!< The Blink frequency = fLCD/8    */
+#define LCD_BLINKFREQUENCY_DIV8         (0x00000000U)                         /*!< The Blink frequency = fLCD/8    */
 #define LCD_BLINKFREQUENCY_DIV16        (LCD_FCR_BLINKF_0)                    /*!< The Blink frequency = fLCD/16   */
 #define LCD_BLINKFREQUENCY_DIV32        (LCD_FCR_BLINKF_1)                    /*!< The Blink frequency = fLCD/32   */
 #define LCD_BLINKFREQUENCY_DIV64        (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64   */
@@ -405,7 +403,7 @@
   * @{
   */
 
-#define LCD_CONTRASTLEVEL_0               ((uint32_t)0x00000000)        /*!< Maximum Voltage = 2.60V    */
+#define LCD_CONTRASTLEVEL_0               (0x00000000U)                 /*!< Maximum Voltage = 2.60V    */
 #define LCD_CONTRASTLEVEL_1               (LCD_FCR_CC_0)                /*!< Maximum Voltage = 2.73V    */
 #define LCD_CONTRASTLEVEL_2               (LCD_FCR_CC_1)                /*!< Maximum Voltage = 2.86V    */
 #define LCD_CONTRASTLEVEL_3               (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V    */
@@ -430,7 +428,7 @@
   * @{
   */
 
-#define LCD_MUXSEGMENT_DISABLE            ((uint32_t)0x00000000)        /*!< SEG pin multiplexing disabled */
+#define LCD_MUXSEGMENT_DISABLE            (0x00000000U)                 /*!< SEG pin multiplexing disabled */
 #define LCD_MUXSEGMENT_ENABLE             (LCD_CR_MUX_SEG)              /*!< SEG[31:28] are multiplexed with SEG[43:40]    */
 
 #define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
@@ -458,22 +456,22 @@
   * @{
   */
 
-#define LCD_RAM_REGISTER0               ((uint32_t)0x00000000) /*!< LCD RAM Register 0  */
-#define LCD_RAM_REGISTER1               ((uint32_t)0x00000001) /*!< LCD RAM Register 1  */
-#define LCD_RAM_REGISTER2               ((uint32_t)0x00000002) /*!< LCD RAM Register 2  */
-#define LCD_RAM_REGISTER3               ((uint32_t)0x00000003) /*!< LCD RAM Register 3  */
-#define LCD_RAM_REGISTER4               ((uint32_t)0x00000004) /*!< LCD RAM Register 4  */
-#define LCD_RAM_REGISTER5               ((uint32_t)0x00000005) /*!< LCD RAM Register 5  */
-#define LCD_RAM_REGISTER6               ((uint32_t)0x00000006) /*!< LCD RAM Register 6  */
-#define LCD_RAM_REGISTER7               ((uint32_t)0x00000007) /*!< LCD RAM Register 7  */
-#define LCD_RAM_REGISTER8               ((uint32_t)0x00000008) /*!< LCD RAM Register 8  */
-#define LCD_RAM_REGISTER9               ((uint32_t)0x00000009) /*!< LCD RAM Register 9  */
-#define LCD_RAM_REGISTER10              ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
-#define LCD_RAM_REGISTER11              ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
-#define LCD_RAM_REGISTER12              ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
-#define LCD_RAM_REGISTER13              ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
-#define LCD_RAM_REGISTER14              ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
-#define LCD_RAM_REGISTER15              ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
+#define LCD_RAM_REGISTER0               (0x00000000U) /*!< LCD RAM Register 0  */
+#define LCD_RAM_REGISTER1               (0x00000001U) /*!< LCD RAM Register 1  */
+#define LCD_RAM_REGISTER2               (0x00000002U) /*!< LCD RAM Register 2  */
+#define LCD_RAM_REGISTER3               (0x00000003U) /*!< LCD RAM Register 3  */
+#define LCD_RAM_REGISTER4               (0x00000004U) /*!< LCD RAM Register 4  */
+#define LCD_RAM_REGISTER5               (0x00000005U) /*!< LCD RAM Register 5  */
+#define LCD_RAM_REGISTER6               (0x00000006U) /*!< LCD RAM Register 6  */
+#define LCD_RAM_REGISTER7               (0x00000007U) /*!< LCD RAM Register 7  */
+#define LCD_RAM_REGISTER8               (0x00000008U) /*!< LCD RAM Register 8  */
+#define LCD_RAM_REGISTER9               (0x00000009U) /*!< LCD RAM Register 9  */
+#define LCD_RAM_REGISTER10              (0x0000000AU) /*!< LCD RAM Register 10 */
+#define LCD_RAM_REGISTER11              (0x0000000BU) /*!< LCD RAM Register 11 */
+#define LCD_RAM_REGISTER12              (0x0000000CU) /*!< LCD RAM Register 12 */
+#define LCD_RAM_REGISTER13              (0x0000000DU) /*!< LCD RAM Register 13 */
+#define LCD_RAM_REGISTER14              (0x0000000EU) /*!< LCD RAM Register 14 */
+#define LCD_RAM_REGISTER15              (0x0000000FU) /*!< LCD RAM Register 15 */
 
 #define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0)  || \
                                            ((__REGISTER__) == LCD_RAM_REGISTER1)  || \

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_nor.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_nor.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_nor.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   NOR HAL module driver.
   *          This file provides a generic firmware to drive NOR memories mounted 
   *          as external device.
@@ -55,7 +53,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_nor.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_nor.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_nor.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of NOR HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_opamp.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_opamp.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_opamp.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   OPAMP HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the operational amplifier(s)(OPAMP1, OPAMP2 etc) 
@@ -138,7 +136,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_opamp.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_opamp.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_opamp.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of OPAMP HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -174,15 +172,15 @@
 /**
   * CSR register Mask 
   */
-#define OPAMP_CSR_INSTANCE_OFFSET   ((uint32_t)  8) /* Offset of each OPAMP instance into register CSR */
-#define OPAMP_OTR_INSTANCE_OFFSET   ((uint32_t) 10) /* Offset of each OPAMP instance into register OTR */
+#define OPAMP_CSR_INSTANCE_OFFSET   ( 8U) /* Offset of each OPAMP instance into register CSR */
+#define OPAMP_OTR_INSTANCE_OFFSET   (10U) /* Offset of each OPAMP instance into register OTR */
     
         
 /** @defgroup OPAMP_Mode OPAMP Mode
   * @{
   */
-#define OPAMP_STANDALONE_MODE            ((uint32_t)0x00000000) /*!< OPAMP standalone mode */
-#define OPAMP_FOLLOWER_MODE              ((uint32_t)0x00000001) /*!< OPAMP follower mode */
+#define OPAMP_STANDALONE_MODE            (0x00000000U) /*!< OPAMP standalone mode */
+#define OPAMP_FOLLOWER_MODE              (0x00000001U) /*!< OPAMP follower mode */
 
 /**
   * @}
@@ -191,9 +189,9 @@
 /** @defgroup OPAMP_NonInvertingInput OPAMP NonInvertingInput
   * @{
   */
-#define OPAMP_NONINVERTINGINPUT_IO0      ((uint32_t)0x00000000)  /*!< Comparator non-inverting input connected to dedicated IO pin low-leakage */
-#define OPAMP_NONINVERTINGINPUT_DAC_CH1  ((uint32_t)0x00000001)  /*!< Comparator non-inverting input connected internally to DAC channel 1. Available only on OPAMP1 and OPAMP2. */
-#define OPAMP_NONINVERTINGINPUT_DAC_CH2  ((uint32_t)0x00000002)  /*!< Comparator non-inverting input connected internally to DAC channel 2. Available only on OPAMP2 and OPAMP3 (OPAMP3 availability depends on STM32L1 devices). */
+#define OPAMP_NONINVERTINGINPUT_IO0      (0x00000000U)  /*!< Comparator non-inverting input connected to dedicated IO pin low-leakage */
+#define OPAMP_NONINVERTINGINPUT_DAC_CH1  (0x00000001U)  /*!< Comparator non-inverting input connected internally to DAC channel 1. Available only on OPAMP1 and OPAMP2. */
+#define OPAMP_NONINVERTINGINPUT_DAC_CH2  (0x00000002U)  /*!< Comparator non-inverting input connected internally to DAC channel 2. Available only on OPAMP2 and OPAMP3 (OPAMP3 availability depends on STM32L1 devices). */
 
 /**
   * @}
@@ -203,8 +201,8 @@
   * @{
   */
 /* Note: Literal "OPAMP_SEC_INVERTINGINPUT_IO1" is a legacy naming of "OPAMP_INVERTINGINPUT_IO1". It is equivalent and must be replaced by "OPAMP_INVERTINGINPUT_IO1". */
-#define OPAMP_INVERTINGINPUT_IO0         ((uint32_t)0x00000000)  /*!< Comparator inverting input connected to dedicated IO pin low-leakage */
-#define OPAMP_INVERTINGINPUT_IO1         ((uint32_t)0x00000001)  /*!< Comparator inverting input connected to alternative IO pin available on some device packages */
+#define OPAMP_INVERTINGINPUT_IO0         (0x00000000U)  /*!< Comparator inverting input connected to dedicated IO pin low-leakage */
+#define OPAMP_INVERTINGINPUT_IO1         (0x00000001U)  /*!< Comparator inverting input connected to alternative IO pin available on some device packages */
 
 /**
   * @}
@@ -213,8 +211,8 @@
 /** @defgroup OPAMP_PowerMode OPAMP PowerMode
   * @{
   */
-#define OPAMP_POWERMODE_NORMAL        ((uint32_t)0x00000000)
-#define OPAMP_POWERMODE_LOWPOWER      ((uint32_t)0x00000001)
+#define OPAMP_POWERMODE_NORMAL        (0x00000000U)
+#define OPAMP_POWERMODE_LOWPOWER      (0x00000001U)
 
 /**
   * @}
@@ -223,7 +221,7 @@
 /** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange
   * @{
   */
-#define OPAMP_POWERSUPPLY_LOW          ((uint32_t)0x00000000)  /*!< Power supply range low (VDDA lower than 2.4V) */
+#define OPAMP_POWERSUPPLY_LOW          (0x00000000U)           /*!< Power supply range low (VDDA lower than 2.4V) */
 #define OPAMP_POWERSUPPLY_HIGH         OPAMP_CSR_AOP_RANGE     /*!< Power supply range high (VDDA higher than 2.4V) */
 
 /**
@@ -233,8 +231,8 @@
 /** @defgroup OPAMP_UserTrimming OPAMP User Trimming
   * @{
   */
-#define OPAMP_TRIMMING_FACTORY        ((uint32_t)0x00000000)                          /*!< Factory trimming */
-#define OPAMP_TRIMMING_USER           OPAMP_OTR_OT_USER                               /*!< User trimming */
+#define OPAMP_TRIMMING_FACTORY        (0x00000000U)                          /*!< Factory trimming */
+#define OPAMP_TRIMMING_USER           OPAMP_OTR_OT_USER                      /*!< User trimming */
 
 /**
   * @}
@@ -243,9 +241,9 @@
 /** @defgroup OPAMP_FactoryTrimming OPAMP FactoryTrimming
   * @{
   */
-#define OPAMP_FACTORYTRIMMING_DUMMY    ((uint32_t)0xFFFFFFFF)                           /*!< Dummy value if trimming value could not be retrieved */
+#define OPAMP_FACTORYTRIMMING_DUMMY    (0xFFFFFFFFU)                                    /*!< Dummy value if trimming value could not be retrieved */
 
-#define OPAMP_FACTORYTRIMMING_P        ((uint32_t)0x00000000)                           /*!< Offset trimming P */
+#define OPAMP_FACTORYTRIMMING_P        (0x00000000U)                                    /*!< Offset trimming P */
 #define OPAMP_FACTORYTRIMMING_N        POSITION_VAL(OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH) /*!< Offset trimming N */
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_opamp_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_opamp_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_opamp_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Extended OPAMP HAL module driver.
   *
   *          This file provides firmware functions to manage the following
@@ -15,7 +13,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_opamp_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_opamp_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_opamp_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of OPAMP HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pcd.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pcd.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_pcd.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   PCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
@@ -44,7 +42,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -195,19 +193,19 @@
  /*Clear pending interrupts*/
  hpcd->Instance->ISTR = 0;
  
-  /*Set Btable Adress*/
+ /*Set Btable Adress*/
  hpcd->Instance->BTABLE = BTABLE_ADDRESS;
-  
-  /*set wInterrupt_Mask global variable*/
-  wInterrupt_Mask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
-    | USB_CNTR_ESOFM | USB_CNTR_RESETM;
-  
-  /*Set interrupt mask*/
-  hpcd->Instance->CNTR = wInterrupt_Mask;
-  
-  hpcd->USB_Address = 0;
-  hpcd->State= HAL_PCD_STATE_READY;
-
+ 
+ /*set wInterrupt_Mask global variable*/
+ wInterrupt_Mask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
+   | USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
+ 
+ /*Set interrupt mask*/
+ hpcd->Instance->CNTR = wInterrupt_Mask;
+ 
+ hpcd->USB_Address = 0;
+ hpcd->State= HAL_PCD_STATE_READY;
+ 
  return HAL_OK;
 }
 
@@ -413,8 +411,8 @@
           /* Process Control Data OUT Packet*/
            HAL_PCD_DataOutStageCallback(hpcd, 0);
           
-          PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
-          PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
+          PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket)
+          PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID)
         }
       }
     }
@@ -442,7 +440,7 @@
         }
         else
         {
-          if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
+          if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_RX) == USB_EP_DTOG_RX)
           {
             /*read from endpoint BUF0Addr buffer*/
             count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
@@ -460,7 +458,7 @@
               PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
             }
           }
-          PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);  
+          PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT)  
         }
         /*multi-packet on the NON control OUT endpoint*/
         ep->xfer_count+=count;
@@ -496,7 +494,7 @@
         }
         else
         {
-          if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
+          if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
           {
             /*read from endpoint BUF0Addr buffer*/
             ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
@@ -514,7 +512,7 @@
               PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
             }
           }
-          PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);  
+          PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN)  
         }
         /*multi-packet on the NON control IN endpoint*/
         ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
@@ -546,15 +544,17 @@
   */
 static void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
 {
-  uint32_t n = (wNBytes + 1) >> 1;   /* n = (wNBytes + 1) / 2 */
+  uint32_t n =  ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
+  
   uint32_t i, temp1, temp2;
   uint16_t *pdwVal;
-  pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
+  pdwVal = (uint16_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
+  
   for (i = n; i != 0; i--)
   {
     temp1 = (uint16_t) * pbUsrBuf;
     pbUsrBuf++;
-    temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
+    temp2 = temp1 | ((uint16_t)((uint16_t)  * pbUsrBuf << 8U)) ;
     *pdwVal++ = temp2;
     pdwVal++;
     pbUsrBuf++;
@@ -571,13 +571,19 @@
   */
 static void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
 {
-  uint32_t n = (wNBytes + 1) >> 1;/* /2*/
+  uint32_t n =  ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
   uint32_t i;
   uint32_t *pdwVal;
-  pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
+
+  pdwVal = (uint32_t *)((uint32_t)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400U));
+  uint32_t tmp = *pdwVal++;
+  *pbUsrBuf++ = (uint16_t)((tmp >> 0) & 0xFF);
+  *pbUsrBuf++ = (uint16_t)((tmp >> 8) & 0xFF);
+  
+  
   for (i = n; i != 0; i--)
   {
-    *(uint16_t*)pbUsrBuf++ = *pdwVal++;
+    *(uint16_t*)((uint32_t)pbUsrBuf++) = *pdwVal++;
     pbUsrBuf++;
   }
 }
@@ -971,19 +977,19 @@
     {
       /*Set the endpoint Transmit buffer address */
       PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
       /* Configure NAK status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); 
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK) 
     }
     else
     {
       /*Set the endpoint Receive buffer address */
       PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
       /*Set the endpoint Receive buffer counter*/
-      PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket);
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+      PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket)
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
       /* Configure VALID status for the Endpoint*/
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
     }
   }
   /*Double Buffer*/
@@ -992,29 +998,29 @@
     /*Set the endpoint as double buffered*/
     PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
     /*Set buffer address for double buffered mode*/
-    PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1);
+    PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1)
     
     if (ep->is_in==0)
     {
       /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
       
       /* Reset value of the data toggle bits for the endpoint out*/
       PCD_TX_DTOG(hpcd->Instance, ep->num);
       
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
     }
     else
     {
       /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
       PCD_RX_DTOG(hpcd->Instance, ep->num);
       /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
     }
   } 
   
@@ -1051,15 +1057,15 @@
   {
     if (ep->is_in)
     {
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
       /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); 
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS) 
     }
     else
     {
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
       /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
     }
   }
   /*Double Buffer*/
@@ -1068,24 +1074,24 @@
     if (ep->is_in==0)
     {
       /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
       
       /* Reset value of the data toggle bits for the endpoint out*/
       PCD_TX_DTOG(hpcd->Instance, ep->num);
       
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
     }
     else
     {
       /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
+      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
       PCD_RX_DTOG(hpcd->Instance, ep->num);
       /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS)
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS)
     }
   } 
   
@@ -1116,8 +1122,6 @@
   ep->is_in = 0;
   ep->num = ep_addr & 0x7F;
    
-  __HAL_LOCK(hpcd); 
-   
   /* Multi packet transfer*/
   if (ep->xfer_len > ep->maxpacket)
   {
@@ -1134,18 +1138,16 @@
   if (ep->doublebuffer == 0) 
   {
     /*Set RX buffer count*/
-    PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len);
+    PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len)
   }
   else
   {
     /*Set the Double buffer counter*/
-    PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len);
+    PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len)
   } 
   
-  PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
-  
-  __HAL_UNLOCK(hpcd); 
-  
+  PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
+
   return HAL_OK;
 }
 
@@ -1180,9 +1182,7 @@
   ep->xfer_count = 0;
   ep->is_in = 1;
   ep->num = ep_addr & 0x7F;
-  
-  __HAL_LOCK(hpcd); 
-  
+
   /*Multi packet transfer*/
   if (ep->xfer_len > ep->maxpacket)
   {
@@ -1203,27 +1203,26 @@
   }
   else
   {
-    /*Set the Double buffer counter */
-    PCD_SET_EP_DBUF_CNT(hpcd->Instance, ep->num, ep->is_in, len);
-    
     /*Write the data to the USB endpoint*/
-    if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX)
+    if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX) == USB_EP_DTOG_TX)
     {
+      /*Set the Double buffer counter for pmabuffer1*/
+      PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len)
       pmabuffer = ep->pmaaddr1;
     }
     else
     {
+      /*Set the Double buffer counter for pmabuffer0*/
+      PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len)
       pmabuffer = ep->pmaaddr0;
     }
 
     PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
-    PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in);
+    PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in)
   }
 
-  PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
-  
-  __HAL_UNLOCK(hpcd);
-     
+  PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
+
   return HAL_OK;
 }
 
@@ -1255,17 +1254,17 @@
   if (ep->num == 0)
   {
     /* This macro sets STALL status for RX & TX*/ 
-    PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); 
+    PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL) 
   }
   else
   {
     if (ep->is_in)
     {
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL); 
+      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL)
     }
     else
     {
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL);
+      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL)
     }
   }
   __HAL_UNLOCK(hpcd); 
@@ -1300,13 +1299,13 @@
   
   if (ep->is_in)
   {
-    PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
-    PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
+    PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num)
+    PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID)
   }
   else
   {
-    PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-    PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
+    PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num)
+    PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID)
   }
   __HAL_UNLOCK(hpcd); 
     

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pcd.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pcd.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_pcd.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -198,7 +196,7 @@
   * @{
   */
 
-#define  USB_WAKEUP_EXTI_LINE              ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
+#define  USB_WAKEUP_EXTI_LINE              (0x00040000U)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
 /**
   * @}
   */
@@ -328,10 +326,11 @@
  */
 
 /* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue)  (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
+/* SetENDPOINT */
+#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue)  (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
 
 /* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum)        (*(&(USBx)->EP0R + (bEpNum) * 2))
+#define PCD_GET_ENDPOINT(USBx, bEpNum)            (*((uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
 
 
 
@@ -343,7 +342,7 @@
   * @retval None
   */
 #define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
-                                  ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
+                                  ((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType)) )))
 
 /**
   * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
@@ -351,7 +350,7 @@
   * @param  bEpNum: Endpoint Number.
   * @retval Endpoint Type
   */
-#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
+#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
 
 
 /**
@@ -400,18 +399,18 @@
   */
 #define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
+    _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
    /* toggle first bit ? */     \
    if((USB_EPTX_DTOG1 & (wState))!= 0)      \
    {                                                                            \
-     _wRegVal ^= USB_EPTX_DTOG1;        \
+     _wRegVal ^=(uint16_t) USB_EPTX_DTOG1;        \
    }                                                                            \
    /* toggle second bit ?  */         \
-   if((USB_EPTX_DTOG2 & (wState))!= 0)      \
+   if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U)      \
    {                                                                            \
-     _wRegVal ^= USB_EPTX_DTOG2;        \
+     _wRegVal ^=(uint16_t) USB_EPTX_DTOG2;        \
    }                                                                            \
-   PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));    \
+   PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
   } /* PCD_SET_EP_TX_STATUS */
 
 /**
@@ -424,18 +423,18 @@
 #define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
     register uint16_t _wRegVal;   \
     \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
+    _wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
     /* toggle first bit ? */  \
     if((USB_EPRX_DTOG1 & (wState))!= 0) \
     {                                                                             \
-      _wRegVal ^= USB_EPRX_DTOG1;  \
+      _wRegVal ^= (uint16_t) USB_EPRX_DTOG1;  \
     }                                                                             \
     /* toggle second bit ? */  \
-    if((USB_EPRX_DTOG2 & (wState))!= 0) \
+    if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
     {                                                                             \
-      _wRegVal ^= USB_EPRX_DTOG2;  \
+      _wRegVal ^= (uint16_t) USB_EPRX_DTOG2;  \
     }                                                                             \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
+    PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
   } /* PCD_SET_EP_RX_STATUS */
 
 /**
@@ -480,9 +479,8 @@
   * @param  bEpNum: Endpoint Number.
   * @retval status
   */
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
-
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
+#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_STAT)
+#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_STAT)
 
 /**
   * @brief  sets directly the VALID tx/rx-status into the endpoint register
@@ -512,9 +510,9 @@
   * @retval None
   */
 #define PCD_SET_EP_KIND(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
+                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
 #define PCD_CLEAR_EP_KIND(USBx, bEpNum)  (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
+                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK))))
 
 /**
   * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
@@ -541,9 +539,9 @@
   * @retval None
   */
 #define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
-                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
+                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
 #define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
-                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
+                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
 
 /**
   * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
@@ -552,9 +550,9 @@
   * @retval None
   */
 #define PCD_RX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
 #define PCD_TX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
+                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
 
 /**
   * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
@@ -562,13 +560,13 @@
   * @param  bEpNum: Endpoint Number.
   * @retval None
   */
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
+#define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
                                          {                                                              \
-                                           PCD_RX_DTOG((USBx), (bEpNum));                               \
+                                           PCD_RX_DTOG((USBx),(bEpNum));\
                                          }
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
-                                         {                                                              \
-                                            PCD_TX_DTOG((USBx), (bEpNum));                              \
+#define PCD_CLEAR_TX_DTOG(USBx, bEpNum)  if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
+                                         {\
+                                           PCD_TX_DTOG((USBx),(bEpNum));\
                                          }
       
 /**
@@ -579,18 +577,18 @@
   * @retval None
   */
 #define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
-    USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
+    USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
 
 #define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
 
-#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8)*2+     ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+  ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+  ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+  ((uint32_t)(USBx) + 0x400)))
+#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8)*2+     ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+2)*2+  ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+4)*2+ ((uint32_t)(USBx) + 0x400U)))))
+#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((uint32_t)((((USBx)->BTABLE+(bEpNum)*8+6)*2+  ((uint32_t)(USBx) + 0x400U)))))
       
 #define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
-    uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
-    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
+    uint16_t *pdwReg =PCD_EP_RX_CNT((USBx),(bEpNum)); \
+    PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
   }
 
 /**
@@ -625,7 +623,7 @@
     {                                                  \
       (wNBlocks)--;\
     }                                                  \
-    *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \
+    *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
   }/* PCD_CALC_BLK32 */
 
 #define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
@@ -641,17 +639,17 @@
     uint16_t wNBlocks;\
     if((wCount) > 62)                                \
     {                                                \
-      PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);     \
+      PCD_CALC_BLK32((dwReg),(wCount),wNBlocks)     \
     }                                                \
     else                                             \
     {                                                \
-      PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);      \
+      PCD_CALC_BLK2((dwReg),(wCount),wNBlocks)     \
     }                                                \
   }/* PCD_SET_EP_CNT_RX_REG */
 
 #define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
-    uint32_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
-    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
+    uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
+    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount))\
   }
 /**
   * @brief  sets counter for the tx/rx buffer.
@@ -679,8 +677,8 @@
   * @param  wBuf0Addr: buffer 0 address.
   * @retval Counter value
   */
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
+#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) (PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)))
+#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) (PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)))
 
 /**
   * @brief  Sets addresses in a double buffer endpoint.
@@ -716,7 +714,7 @@
 #define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)  { \
     if((bDir) == PCD_EP_DBUF_OUT)\
       /* OUT endpoint */ \
-    {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
+    {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount))} \
     else if((bDir) == PCD_EP_DBUF_IN)\
       /* IN endpoint */ \
       *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount);  \
@@ -725,17 +723,17 @@
 #define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)  { \
     if((bDir) == PCD_EP_DBUF_OUT)\
     {/* OUT endpoint */                                       \
-      PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));           \
+      PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount))           \
     }                                                         \
     else if((bDir) == PCD_EP_DBUF_IN)\
     {/* IN endpoint */                                        \
-      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
+      *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
     }                                                         \
   } /* SetEPDblBuf1Count */
 
 #define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
-    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
-    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
+    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)) \
+    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)) \
   } /* PCD_SET_EP_DBUF_CNT  */
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pcd_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pcd_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_pcd_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Extended PCD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the USB Peripheral Controller:
@@ -12,7 +10,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pcd_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pcd_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_pcd_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of PCD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pwr.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pwr.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_pwr.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   PWR HAL module driver.
   *
   *          This file provides firmware functions to manage the following
@@ -14,7 +12,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -57,10 +55,10 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-#define PVD_MODE_IT               ((uint32_t)0x00010000)
-#define PVD_MODE_EVT              ((uint32_t)0x00020000)
-#define PVD_RISING_EDGE           ((uint32_t)0x00000001)
-#define PVD_FALLING_EDGE          ((uint32_t)0x00000002)
+#define PVD_MODE_IT               (0x00010000U)
+#define PVD_MODE_EVT              (0x00020000U)
+#define PVD_RISING_EDGE           (0x00000001U)
+#define PVD_FALLING_EDGE          (0x00000002U)
 
 /* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pwr.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pwr.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_pwr.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of PWR HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -81,7 +79,7 @@
 /** @addtogroup PWR_Private_Constants
   * @{
   */ 
-#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+#define PWR_EXTI_LINE_PVD  (0x00010000U)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
 
 /**
   * @}
@@ -170,13 +168,13 @@
 /** @defgroup PWR_PVD_Mode PWR PVD Mode
   * @{
   */
-#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_NORMAL                 (0x00000000U)   /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           (0x00020001U)   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          (0x00020002U)   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection */
 
  /**
  * @}
@@ -185,7 +183,7 @@
 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
   * @{
   */
-#define PWR_MAINREGULATOR_ON           ((uint32_t)0x00000000)
+#define PWR_MAINREGULATOR_ON           (0x00000000U)
 #define PWR_LOWPOWERREGULATOR_ON       PWR_CR_LPSDSR
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pwr_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pwr_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_pwr_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Extended PWR HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Power Controller (PWR) peripheral:
@@ -13,7 +11,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pwr_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_pwr_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_pwr_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of PWR HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_rcc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Reset and Clock Control (RCC) peripheral:
@@ -51,7 +49,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -272,10 +270,10 @@
   CLEAR_REG(RCC->CFGR);
   
   /* Set MSIClockRange & MSITRIM[4:0] bits to the reset value */
-  MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << RCC_ICSCR_MSITRIM_BITNUMBER) | RCC_ICSCR_MSIRANGE_5));
+  MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), ((0U << RCC_ICSCR_MSITRIM_BITNUMBER) | RCC_ICSCR_MSIRANGE_5));
   
   /* Set HSITRIM bits to the reset value */
-  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_ICSCR_HSITRIM)));
+  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (0x10U << POSITION_VAL(RCC_ICSCR_HSITRIM)));
   
   /* Disable all interrupts */
   CLEAR_REG(RCC->CIR);
@@ -903,7 +901,7 @@
   if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
   {
     assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
   }
  
   /* Update the SystemCoreClock global variable */
@@ -961,7 +959,7 @@
   */
 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
 {
-  GPIO_InitTypeDef gpio = {0};
+  GPIO_InitTypeDef gpio;
 
   /* Check the parameters */
   assert_param(IS_RCC_MCO(RCC_MCOx));
@@ -1039,8 +1037,8 @@
   */
 uint32_t HAL_RCC_GetSysClockFreq(void)
 {
-  uint32_t tmpreg = 0, pllm = 0, plld = 0, pllvco = 0, msiclkrange = 0;
-  uint32_t sysclockfreq = 0;
+  uint32_t tmpreg = 0U, pllm = 0U, plld = 0U, pllvco = 0U, msiclkrange = 0U;
+  uint32_t sysclockfreq = 0U;
   
   tmpreg = RCC->CFGR;
   
@@ -1060,7 +1058,7 @@
     case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
     {
       pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
-      plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_BITNUMBER) + 1;
+      plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_BITNUMBER) + 1U;
       if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
       {
         /* HSE used as PLL clock source */
@@ -1078,7 +1076,7 @@
     default: /* MSI used as system clock */
     {
       msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_BITNUMBER;
-      sysclockfreq = (32768 * (1 << (msiclkrange + 1)));
+      sysclockfreq = (32768U * (1U << (msiclkrange + 1U)));
       break;
     }
   }
@@ -1245,7 +1243,7 @@
   RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);   
   
   /* Get the APB2 configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
   
   /* Get the Flash Wait State (Latency) configuration ------------------------*/   
   *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 
@@ -1300,7 +1298,7 @@
   */
 static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
 {
-  uint32_t vos = 0;
+  uint32_t vos = 0U;
   uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
 
   /* HCLK can reach 4 MHz only if AHB prescaler = 1 */
@@ -1308,12 +1306,12 @@
   {
     if(__HAL_RCC_PWR_IS_CLK_ENABLED())
     {
-      vos = HAL_PWREx_GetVoltageRange();
+      vos = READ_BIT(PWR->CR, PWR_CR_VOS);
     }
     else
     {
       __HAL_RCC_PWR_CLK_ENABLE();
-      vos = HAL_PWREx_GetVoltageRange();
+      vos = READ_BIT(PWR->CR, PWR_CR_VOS);
       __HAL_RCC_PWR_CLK_DISABLE();
     }
     

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_rcc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of RCC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -68,10 +66,10 @@
 #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
 #define CLOCKSWITCH_TIMEOUT_VALUE  (5000U)  /* 5 s    */
 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define MSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
-#define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1) */
+#define MSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
+#define HSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
+#define LSI_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
+#define PLL_TIMEOUT_VALUE          (2U)      /* 2 ms (minimum Tick + 1U) */
 /**
   * @}
   */
@@ -100,63 +98,63 @@
 /* --- CR Register ---*/
 /* Alias word address of HSION bit */
 #define RCC_HSION_BIT_NUMBER      POSITION_VAL(RCC_CR_HSION)
-#define RCC_CR_HSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSION_BIT_NUMBER * 4)))
+#define RCC_CR_HSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
 /* Alias word address of MSION bit */
 #define RCC_MSION_BIT_NUMBER      POSITION_VAL(RCC_CR_MSION)
-#define RCC_CR_MSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_MSION_BIT_NUMBER * 4)))
+#define RCC_CR_MSION_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U)))
 /* Alias word address of HSEON bit */
 #define RCC_HSEON_BIT_NUMBER      POSITION_VAL(RCC_CR_HSEON)
-#define RCC_CR_HSEON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_HSEON_BIT_NUMBER * 4)))
+#define RCC_CR_HSEON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
 /* Alias word address of CSSON bit */
 #define RCC_CSSON_BIT_NUMBER      POSITION_VAL(RCC_CR_CSSON)
-#define RCC_CR_CSSON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_CSSON_BIT_NUMBER * 4)))
+#define RCC_CR_CSSON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
 /* Alias word address of PLLON bit */
 #define RCC_PLLON_BIT_NUMBER      POSITION_VAL(RCC_CR_PLLON)
-#define RCC_CR_PLLON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (RCC_PLLON_BIT_NUMBER * 4)))
+#define RCC_CR_PLLON_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
 
 /* --- CSR Register ---*/
 /* Alias word address of LSION bit */
 #define RCC_LSION_BIT_NUMBER      POSITION_VAL(RCC_CSR_LSION)
-#define RCC_CSR_LSION_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSION_BIT_NUMBER * 4)))
+#define RCC_CSR_LSION_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
 
 /* Alias word address of RMVF bit */
 #define RCC_RMVF_BIT_NUMBER       POSITION_VAL(RCC_CSR_RMVF)
-#define RCC_CSR_RMVF_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RMVF_BIT_NUMBER * 4)))
+#define RCC_CSR_RMVF_BB           ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
 
 /* Alias word address of LSEON bit */
 #define RCC_LSEON_BIT_NUMBER      POSITION_VAL(RCC_CSR_LSEON)
-#define RCC_CSR_LSEON_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSEON_BIT_NUMBER * 4)))
+#define RCC_CSR_LSEON_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
 
 /* Alias word address of LSEON bit */
 #define RCC_LSEBYP_BIT_NUMBER     POSITION_VAL(RCC_CSR_LSEBYP)
-#define RCC_CSR_LSEBYP_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_LSEBYP_BIT_NUMBER * 4)))
+#define RCC_CSR_LSEBYP_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
 
 /* Alias word address of RTCEN bit */
 #define RCC_RTCEN_BIT_NUMBER      POSITION_VAL(RCC_CSR_RTCEN)
-#define RCC_CSR_RTCEN_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RTCEN_BIT_NUMBER * 4)))
+#define RCC_CSR_RTCEN_BB          ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
 
 /* Alias word address of RTCRST bit */
 #define RCC_RTCRST_BIT_NUMBER     POSITION_VAL(RCC_CSR_RTCRST)
-#define RCC_CSR_RTCRST_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RCC_RTCRST_BIT_NUMBER * 4)))
+#define RCC_CSR_RTCRST_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U)))
 
 /**
   * @}
   */
   
 /* CR register byte 2 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
+#define RCC_CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
 
 /* CIR register byte 1 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
+#define RCC_CIR_BYTE1_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
 
 /* CIR register byte 2 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
+#define RCC_CIR_BYTE2_ADDRESS     ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
 
 /* Defines used for Flags */
-#define CR_REG_INDEX                     ((uint8_t)1)
-#define CSR_REG_INDEX                    ((uint8_t)2)
+#define CR_REG_INDEX                     ((uint8_t)1U)
+#define CSR_REG_INDEX                    ((uint8_t)2U)
 
-#define RCC_FLAG_MASK                    ((uint8_t)0x1F)
+#define RCC_FLAG_MASK                    ((uint8_t)0x1FU)
 
 /**
   * @}
@@ -178,8 +176,8 @@
 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
                              ((__LSE__) == RCC_LSE_BYPASS))
 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
-#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
+#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
+#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU)
 #define IS_RCC_MSI_CLOCK_RANGE(__RANGE__)  (((__RANGE__) == RCC_MSIRANGE_0) || \
                                             ((__RANGE__) == RCC_MSIRANGE_1) || \
                                             ((__RANGE__) == RCC_MSIRANGE_2) || \
@@ -282,7 +280,7 @@
                                        This parameter can be a value of @ref RCC_HSI_Config */
 
   uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */
 
   uint32_t LSIState;              /*!< The new state of the LSI.
                                        This parameter can be a value of @ref RCC_LSI_Config */
@@ -291,7 +289,7 @@
                                        This parameter can be a value of @ref RCC_MSI_Config */
 
   uint32_t MSICalibrationValue;   /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
+                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */
 
   uint32_t MSIClockRange;         /*!< The MSI  frequency  range.
                                         This parameter can be a value of @ref RCC_MSI_Clock_Range */
@@ -344,12 +342,12 @@
 /** @defgroup RCC_Oscillator_Type Oscillator Type
   * @{
   */
-#define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
-#define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
-#define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
-#define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
-#define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
-#define RCC_OSCILLATORTYPE_MSI             ((uint32_t)0x00000010)
+#define RCC_OSCILLATORTYPE_NONE            (0x00000000U)
+#define RCC_OSCILLATORTYPE_HSE             (0x00000001U)
+#define RCC_OSCILLATORTYPE_HSI             (0x00000002U)
+#define RCC_OSCILLATORTYPE_LSE             (0x00000004U)
+#define RCC_OSCILLATORTYPE_LSI             (0x00000008U)
+#define RCC_OSCILLATORTYPE_MSI             (0x00000010U)
 /**
   * @}
   */
@@ -357,9 +355,9 @@
 /** @defgroup RCC_HSE_Config HSE Config
   * @{
   */
-#define RCC_HSE_OFF                      ((uint32_t)0x00000000)                     /*!< HSE clock deactivation */
-#define RCC_HSE_ON                       ((uint32_t)0x00000001)                     /*!< HSE clock activation */
-#define RCC_HSE_BYPASS                   ((uint32_t)0x00000005)                     /*!< External clock source for HSE clock */
+#define RCC_HSE_OFF                      (0x00000000U)                     /*!< HSE clock deactivation */
+#define RCC_HSE_ON                       (0x00000001U)                     /*!< HSE clock activation */
+#define RCC_HSE_BYPASS                   (0x00000005U)                     /*!< External clock source for HSE clock */
 /**
   * @}
   */
@@ -367,9 +365,9 @@
 /** @defgroup RCC_LSE_Config LSE Config
   * @{
   */
-#define RCC_LSE_OFF                      ((uint32_t)0x00000000)                       /*!< LSE clock deactivation */
-#define RCC_LSE_ON                       ((uint32_t)0x00000001)                       /*!< LSE clock activation */
-#define RCC_LSE_BYPASS                   ((uint32_t)0x00000005)                       /*!< External clock source for LSE clock */
+#define RCC_LSE_OFF                      (0x00000000U)                       /*!< LSE clock deactivation */
+#define RCC_LSE_ON                       (0x00000001U)                       /*!< LSE clock activation */
+#define RCC_LSE_BYPASS                   (0x00000005U)                       /*!< External clock source for LSE clock */
 
 /**
   * @}
@@ -378,10 +376,10 @@
 /** @defgroup RCC_HSI_Config HSI Config
   * @{
   */
-#define RCC_HSI_OFF                      ((uint32_t)0x00000000)           /*!< HSI clock deactivation */
+#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */
 #define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
 
-#define RCC_HSICALIBRATION_DEFAULT       ((uint32_t)0x10)         /* Default HSI calibration trimming value */
+#define RCC_HSICALIBRATION_DEFAULT       (0x10U)         /* Default HSI calibration trimming value */
 
 /**
   * @}
@@ -406,7 +404,7 @@
 /** @defgroup RCC_LSI_Config LSI Config
   * @{
   */
-#define RCC_LSI_OFF                      ((uint32_t)0x00000000)   /*!< LSI clock deactivation */
+#define RCC_LSI_OFF                      (0x00000000U)   /*!< LSI clock deactivation */
 #define RCC_LSI_ON                       RCC_CSR_LSION            /*!< LSI clock activation */
 
 /**
@@ -416,10 +414,10 @@
 /** @defgroup RCC_MSI_Config MSI Config
   * @{
   */
-#define RCC_MSI_OFF                      ((uint32_t)0x00000000)
-#define RCC_MSI_ON                       ((uint32_t)0x00000001)
+#define RCC_MSI_OFF                      (0x00000000U)
+#define RCC_MSI_ON                       (0x00000001U)
 
-#define RCC_MSICALIBRATION_DEFAULT       ((uint32_t)0x00000000U)   /* Default MSI calibration trimming value */
+#define RCC_MSICALIBRATION_DEFAULT       (0x00000000U)   /* Default MSI calibration trimming value */
 
 /**
   * @}
@@ -428,9 +426,9 @@
 /** @defgroup RCC_PLL_Config PLL Config
   * @{
   */
-#define RCC_PLL_NONE                      ((uint32_t)0x00000000)  /*!< PLL is not configured */
-#define RCC_PLL_OFF                       ((uint32_t)0x00000001)  /*!< PLL deactivation */
-#define RCC_PLL_ON                        ((uint32_t)0x00000002)  /*!< PLL activation */
+#define RCC_PLL_NONE                      (0x00000000U)  /*!< PLL is not configured */
+#define RCC_PLL_OFF                       (0x00000001U)  /*!< PLL deactivation */
+#define RCC_PLL_ON                        (0x00000002U)  /*!< PLL activation */
 
 /**
   * @}
@@ -439,10 +437,10 @@
 /** @defgroup RCC_System_Clock_Type System Clock Type
   * @{
   */
-#define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001) /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002) /*!< HCLK to configure */
-#define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004) /*!< PCLK1 to configure */
-#define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008) /*!< PCLK2 to configure */
+#define RCC_CLOCKTYPE_SYSCLK             (0x00000001U) /*!< SYSCLK to configure */
+#define RCC_CLOCKTYPE_HCLK               (0x00000002U) /*!< HCLK to configure */
+#define RCC_CLOCKTYPE_PCLK1              (0x00000004U) /*!< PCLK1 to configure */
+#define RCC_CLOCKTYPE_PCLK2              (0x00000008U) /*!< PCLK2 to configure */
 
 /**
   * @}
@@ -505,7 +503,7 @@
 /** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler
   * @{
   */
-#define RCC_RTC_HSE_DIV_2               (uint32_t)0x00000000U /*!< HSE is divided by 2 for RTC clock  */
+#define RCC_RTC_HSE_DIV_2               0x00000000U /*!< HSE is divided by 2 for RTC clock  */
 #define RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0       /*!< HSE is divided by 4 for RTC clock  */
 #define RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1       /*!< HSE is divided by 8 for RTC clock  */
 #define RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE         /*!< HSE is divided by 16 for RTC clock */
@@ -516,7 +514,7 @@
 /** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source
   * @{
   */
-#define RCC_RTCCLKSOURCE_NO_CLK          ((uint32_t)0x00000000)                 /*!< No clock */
+#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)                 /*!< No clock */
 #define RCC_RTCCLKSOURCE_LSE             RCC_CSR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
 #define RCC_RTCCLKSOURCE_LSI             RCC_CSR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
 #define RCC_RTCCLKSOURCE_HSE_DIVX        RCC_CSR_RTCSEL_HSE                         /*!< HSE oscillator clock divided by X used as RTC clock */
@@ -561,7 +559,7 @@
 /** @defgroup RCC_MCO_Index MCO Index
   * @{
   */
-#define RCC_MCO1                         ((uint32_t)0x00000000)
+#define RCC_MCO1                         (0x00000000U)
 #define RCC_MCO                          RCC_MCO1               /*!< MCO1 to be compliant with other families with 2 MCOs*/
 
 /**
@@ -620,22 +618,22 @@
   * @{
   */
 /* Flags in the CR register */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
-#define RCC_FLAG_MSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI clock ready flag */
-#define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
-#define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSIRDY))) /*!< Internal High Speed clock ready flag */
+#define RCC_FLAG_MSIRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_MSIRDY))) /*!< MSI clock ready flag */
+#define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
+#define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5U) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
 
 /* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< Internal Low Speed oscillator Ready */
-#define RCC_FLAG_LSECSS                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD)))  /*!< CSS on LSE failure Detection */
-#define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF)))  /*!< Options bytes loading reset flag */
-#define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
-#define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF)))  /*!< POR/PDR reset flag */
-#define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
-#define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
-#define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
-#define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
-#define RCC_FLAG_LSERDY                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSERDY))) /*!< External Low Speed oscillator Ready */
+#define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< Internal Low Speed oscillator Ready */
+#define RCC_FLAG_LSECSS                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSECSSD)))  /*!< CSS on LSE failure Detection */
+#define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_OBLRSTF)))  /*!< Options bytes loading reset flag */
+#define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
+#define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_PORRSTF)))  /*!< POR/PDR reset flag */
+#define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
+#define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
+#define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
+#define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LPWRRSTF))) /*!< Low-Power reset flag */
+#define RCC_FLAG_LSERDY                  ((uint8_t)((CSR_REG_INDEX << 5U) | POSITION_VAL(RCC_CSR_LSERDY))) /*!< External Low Speed oscillator Ready */
 
 /**
   * @}
@@ -664,56 +662,56 @@
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_CRC_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_FLITF_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_DMA1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_GPIOA_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
 #define __HAL_RCC_GPIOB_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
@@ -742,105 +740,105 @@
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM3_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM4_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_WWDG_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_SPI2_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_USART2_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_USART3_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_I2C1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_I2C2_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_USB_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_PWR_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_DAC_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_COMP_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 
 #define __HAL_RCC_TIM2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
@@ -876,49 +874,49 @@
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM9_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM10_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM11_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_ADC1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_SPI1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_USART1_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                         /* Delay after an RCC peripheral clock enabling */\
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_SYSCFG_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
 #define __HAL_RCC_TIM9_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
@@ -1422,7 +1420,7 @@
                         CLEAR_BIT(RCC->CR, RCC_CR_HSEON);                   \
                         CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);                  \
                       }                                                     \
-                    }while(0)
+                    }while(0U)
 
 /**
   * @}
@@ -1470,7 +1468,7 @@
                         CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON);                 \
                         CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP);                \
                       }                                                     \
-                    }while(0)
+                    }while(0U)
 
 /**
   * @}
@@ -1701,12 +1699,12 @@
             {                                                                             \
               MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE));  \
             }                                                                             \
-          } while (0)
+          } while (0U)
 
 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
                                       __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__);      \
                                       RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
-                                    } while (0)
+                                    } while (0U)
                                                    
 /** @brief Macro to get the RTC clock source.
   * @retval The clock source can be one of the following values:
@@ -1840,7 +1838,7 @@
   * @note (*) This bit is available in high and medium+ density devices only.
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))   
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))   
 
 /**
   * @}
@@ -1878,6 +1876,10 @@
 /* Peripheral Control functions  ************************************************/
 void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
 void              HAL_RCC_EnableCSS(void);
+/* CSS NMI IRQ handler */
+void              HAL_RCC_NMI_IRQHandler(void);
+/* User Callbacks in non blocking mode (IT mode) */
+void              HAL_RCC_CSSCallback(void);
 void              HAL_RCC_DisableCSS(void);
 uint32_t          HAL_RCC_GetSysClockFreq(void);
 uint32_t          HAL_RCC_GetHCLKFreq(void);
@@ -1886,12 +1888,6 @@
 void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
 void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
 
-/* CSS NMI IRQ handler */
-void              HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */
-void              HAL_RCC_CSSCallback(void);
-
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_rcc_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Extended RCC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities RCC extension peripheral:
@@ -12,7 +10,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -235,7 +233,7 @@
   */
 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 {
-  uint32_t srcclk = 0;
+  uint32_t srcclk = 0U;
   
   /* Set all possible values for the extended clock type parameter------------*/
   PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rcc_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_rcc_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of RCC HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -58,7 +56,7 @@
  * @{
  */
 
-#define LSI_VALUE                  ((uint32_t)37000)  /* ~37kHz */
+#define LSI_VALUE                  (37000U)  /* ~37kHz */
 
 #if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\
  || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\
@@ -69,7 +67,7 @@
 
 /* Alias word address of LSECSSON bit */
 #define LSECSSON_BITNUMBER      POSITION_VAL(RCC_CSR_LSECSSON)
-#define CSR_LSECSSON_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4)))
+#define CSR_LSECSSON_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U)))
 
 #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/
 
@@ -132,11 +130,11 @@
 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
   * @{
   */
-#define RCC_PERIPHCLK_RTC           ((uint32_t)0x00000001)
+#define RCC_PERIPHCLK_RTC           (0x00000001U)
 
 #if defined(LCD)
 
-#define RCC_PERIPHCLK_LCD           ((uint32_t)0x00000002)
+#define RCC_PERIPHCLK_LCD           (0x00000002U)
 
 #endif /* LCD */
 
@@ -183,7 +181,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_GPIOE_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
 
 #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
@@ -198,14 +196,14 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_GPIOF_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
 #define __HAL_RCC_GPIOG_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
@@ -224,7 +222,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_DMA2_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
 
@@ -239,7 +237,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_CRYP_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))
 
 #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */
@@ -252,7 +250,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
 
 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
@@ -269,7 +267,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_LCD_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
 
 #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
@@ -290,7 +288,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_TIM5_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
 
 #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
@@ -307,7 +305,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
 
 #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
@@ -321,14 +319,14 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_UART5_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 
 #define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
 #define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
@@ -359,7 +357,7 @@
                                         /* Delay after an RCC peripheral clock enabling */ \
                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
                                         UNUSED(tmpreg); \
-                                      } while(0)
+                                      } while(0U)
 #define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
 
 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
@@ -927,7 +925,7 @@
   do {                                                      \
     __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
     __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)  
+  } while(0U)  
   
 /**
   * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
@@ -937,7 +935,7 @@
   do {                                                       \
     __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
     __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)  
+  } while(0U)  
 
 /**
   * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
@@ -1035,7 +1033,7 @@
 /**
   * @}
   */
-
+  
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_rtc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   RTC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Real Time Clock (RTC) peripheral:
@@ -102,7 +100,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -421,7 +419,7 @@
     hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
      
     /* Clear the bits to be configured */
-    hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
+    hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP;
     
     /* Configure the RTC_CR register */
     hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_rtc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of RTC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -187,7 +185,7 @@
 /** @defgroup RTC_Asynchronous_Predivider Asynchronous Predivider 
   * @{
   */ 
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7F)
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7FU)
 /**
   * @}
   */ 
@@ -195,10 +193,10 @@
 /** @defgroup RTC_Time_Definitions Time Definitions 
   * @{
   */ 
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23)
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59)
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59)
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0U) && ((HOUR) <= 12U))
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23U)
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59U)
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59U)
 /**
   * @}
   */ 
@@ -254,7 +252,7 @@
 /** @defgroup RTC_Year_Date_Definitions Year Definitions
   * @{
   */ 
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99)
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99U)
 /**
   * @}
   */ 
@@ -277,8 +275,8 @@
 #define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
 #define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
 
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
-#define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1U) && ((MONTH) <= 12U))
+#define IS_RTC_DATE(DATE)              (((DATE) >= 1U) && ((DATE) <= 31U))
 /**
   * @}
   */ 
@@ -308,7 +306,7 @@
 /** @defgroup RTC_Alarm_Definitions Alarm Definitions
   * @{
   */ 
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U))
 #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                                     ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
                                                     ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_rtc_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Extended RTC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -63,7 +61,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -153,10 +151,10 @@
   else
   {
     /* Reset TR, DR and CR registers */
-    hrtc->Instance->TR = (uint32_t)0x00000000;
-    hrtc->Instance->DR = (uint32_t)0x00002101;
+    hrtc->Instance->TR = 0x00000000U;
+    hrtc->Instance->DR = 0x00002101U;
     /* Reset All CR bits except CR[2:0] */
-    hrtc->Instance->CR &= (uint32_t)0x00000007;
+    hrtc->Instance->CR &= 0x00000007U;
     
     tickstart = HAL_GetTick();
     
@@ -176,23 +174,23 @@
     }
     
     /* Reset all RTC CR register bits */
-    hrtc->Instance->CR &= (uint32_t)0x00000000;
-    hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;
-    hrtc->Instance->PRER = (uint32_t)0x007F00FF;
-    hrtc->Instance->CALIBR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
+    hrtc->Instance->CR &= 0x00000000U;
+    hrtc->Instance->WUTR = 0x0000FFFFU;
+    hrtc->Instance->PRER = 0x007F00FFU;
+    hrtc->Instance->CALIBR = 0x00000000U;
+    hrtc->Instance->ALRMAR = 0x00000000U;
+    hrtc->Instance->ALRMBR = 0x00000000U;
 #if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) 
-    hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
-    hrtc->Instance->CALR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
+    hrtc->Instance->SHIFTR = 0x00000000U;
+    hrtc->Instance->CALR = 0x00000000U;
+    hrtc->Instance->ALRMASSR = 0x00000000U;
+    hrtc->Instance->ALRMBSSR = 0x00000000U;
 #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
     /* Reset ISR register and exit initialization mode */
-    hrtc->Instance->ISR = (uint32_t)0x00000000;
+    hrtc->Instance->ISR = 0x00000000U;
     
     /* Reset Tamper and alternate functions configuration register */
-    hrtc->Instance->TAFCR = 0x00000000;
+    hrtc->Instance->TAFCR = 0x00000000U;
     
     /* Wait for synchro */
     if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_rtc_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_rtc_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of RTC HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -121,7 +119,7 @@
   uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. 
                                  This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
   
-  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit 
+  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BKP bit 
                                  in CR register to store the operation.
                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
 }RTC_TimeTypeDef; 
@@ -165,8 +163,8 @@
   */  
 #define RTC_TR_RESERVED_MASK    (0x007F7F7FU)
 #define RTC_DR_RESERVED_MASK    (0x00FFFF3FU) 
-#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)  
-#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)
+#define RTC_INIT_MASK           (0xFFFFFFFFU)  
+#define RTC_RSF_MASK            (0xFFFFFF5FU)
 
 #if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)   
 #define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \
@@ -192,9 +190,9 @@
   * @{
   */ 
 #if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)   
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFF)
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFFU)
 #elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x1FFF)
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x1FFFU)
 #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_sd.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   SD card HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Secure Digital (SD) peripheral:
@@ -153,7 +151,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -1853,7 +1851,7 @@
   if (SD_SPEC != SD_ALLZERO)
   {
     /* Set Block Size for Card */
-    sdio_cmdinitstructure.Argument         = (uint32_t)64;
+    sdio_cmdinitstructure.Argument         = 64U;
     sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
     sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
     sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
@@ -3183,7 +3181,7 @@
   
   /* Set Block Size To 8 Bytes */
   /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdio_cmdinitstructure.Argument         = (uint32_t)8;
+  sdio_cmdinitstructure.Argument         = 8U;
   sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
   sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
   sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sd.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_sd.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of SD HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -290,15 +288,15 @@
   */  
 typedef enum
 {
-  SD_CARD_READY                  = ((uint32_t)0x00000001),  /*!< Card state is ready                     */
-  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),  /*!< Card is in identification state         */
-  SD_CARD_STANDBY                = ((uint32_t)0x00000003),  /*!< Card is in standby state                */
-  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),  /*!< Card is in transfer state               */  
-  SD_CARD_SENDING                = ((uint32_t)0x00000005),  /*!< Card is sending an operation            */
-  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),  /*!< Card is receiving operation information */
-  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),  /*!< Card is in programming state            */
-  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),  /*!< Card is disconnected                    */
-  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)   /*!< Card is in error state                  */
+  SD_CARD_READY                  = (0x00000001U),  /*!< Card state is ready                     */
+  SD_CARD_IDENTIFICATION         = (0x00000002U),  /*!< Card is in identification state         */
+  SD_CARD_STANDBY                = (0x00000003U),  /*!< Card is in standby state                */
+  SD_CARD_TRANSFER               = (0x00000004U),  /*!< Card is in transfer state               */  
+  SD_CARD_SENDING                = (0x00000005U),  /*!< Card is sending an operation            */
+  SD_CARD_RECEIVING              = (0x00000006U),  /*!< Card is receiving operation information */
+  SD_CARD_PROGRAMMING            = (0x00000007U),  /*!< Card is in programming state            */
+  SD_CARD_DISCONNECTED           = (0x00000008U),  /*!< Card is disconnected                    */
+  SD_CARD_ERROR                  = (0x000000FFU)   /*!< Card is in error state                  */
 
 }HAL_SD_CardStateTypedef;
 /** 
@@ -420,14 +418,14 @@
 /** 
   * @brief Supported SD Memory Cards 
   */
-#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
-#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
-#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
-#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
-#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
-#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
-#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
-#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
+#define STD_CAPACITY_SD_CARD_V1_1             (0x00000000U)
+#define STD_CAPACITY_SD_CARD_V2_0             (0x00000001U)
+#define HIGH_CAPACITY_SD_CARD                 (0x00000002U)
+#define MULTIMEDIA_CARD                       (0x00000003U)
+#define SECURE_DIGITAL_IO_CARD                (0x00000004U)
+#define HIGH_SPEED_MULTIMEDIA_CARD            (0x00000005U)
+#define SECURE_DIGITAL_IO_COMBO_CARD          (0x00000006U)
+#define HIGH_CAPACITY_MMC_CARD                (0x00000007U)
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_smartcard.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_smartcard.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_smartcard.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   SMARTCARD HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the SMARTCARD peripheral:
@@ -103,7 +101,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_smartcard.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_smartcard.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,14 +2,12 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_smartcard.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   This file contains all the functions prototypes for the SMARTCARD 
   *          firmware library.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -170,12 +168,12 @@
 /** @defgroup SMARTCARD_Error_Codes SMARTCARD Error Codes
   * @{
   */
-#define HAL_SMARTCARD_ERROR_NONE      ((uint32_t)0x00)    /*!< No error            */
-#define HAL_SMARTCARD_ERROR_PE        ((uint32_t)0x01)    /*!< Parity error        */
-#define HAL_SMARTCARD_ERROR_NE        ((uint32_t)0x02)    /*!< Noise error         */
-#define HAL_SMARTCARD_ERROR_FE        ((uint32_t)0x04)    /*!< frame error         */
-#define HAL_SMARTCARD_ERROR_ORE       ((uint32_t)0x08)    /*!< Overrun error       */
-#define HAL_SMARTCARD_ERROR_DMA       ((uint32_t)0x10)    /*!< DMA transfer error  */
+#define HAL_SMARTCARD_ERROR_NONE      (0x00U)    /*!< No error            */
+#define HAL_SMARTCARD_ERROR_PE        (0x01U)    /*!< Parity error        */
+#define HAL_SMARTCARD_ERROR_NE        (0x02U)    /*!< Noise error         */
+#define HAL_SMARTCARD_ERROR_FE        (0x04U)    /*!< frame error         */
+#define HAL_SMARTCARD_ERROR_ORE       (0x08U)    /*!< Overrun error       */
+#define HAL_SMARTCARD_ERROR_DMA       (0x10U)    /*!< DMA transfer error  */
 
 /**
   * @}
@@ -222,7 +220,7 @@
 /** @defgroup SMARTCARD_Clock_Polarity  SMARTCARD Clock Polarity
   * @{
   */
-#define SMARTCARD_POLARITY_LOW                   ((uint32_t)0x00000000)
+#define SMARTCARD_POLARITY_LOW                   (0x00000000U)
 #define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
 /**
   * @}
@@ -231,7 +229,7 @@
 /** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
   * @{
   */
-#define SMARTCARD_PHASE_1EDGE                    ((uint32_t)0x00000000)
+#define SMARTCARD_PHASE_1EDGE                    (0x00000000U)
 #define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
 /**
   * @}
@@ -240,7 +238,7 @@
 /** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit
   * @{
   */
-#define SMARTCARD_LASTBIT_DISABLE                ((uint32_t)0x00000000)
+#define SMARTCARD_LASTBIT_DISABLE                (0x00000000U)
 #define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
 /**
   * @}
@@ -249,7 +247,7 @@
 /** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
   * @{
   */
-#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    ((uint32_t)0x00000000)
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    (0x00000000U)
 #define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     ((uint32_t)USART_CR3_ONEBIT)
 /**
   * @}
@@ -259,7 +257,7 @@
   * @{
   */
 #define SMARTCARD_NACK_ENABLE                     ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLE                    ((uint32_t)0x00000000)
+#define SMARTCARD_NACK_DISABLE                    (0x00000000U)
 /**
   * @}
   */
@@ -278,37 +276,37 @@
 /** @defgroup SMARTCARD_Prescaler SMARTCARD Prescaler
   * @{
   */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV2         ((uint32_t)0x00000001)          /*!< SYSCLK divided by 2 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV4         ((uint32_t)0x00000002)          /*!< SYSCLK divided by 4 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV6         ((uint32_t)0x00000003)          /*!< SYSCLK divided by 6 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV8         ((uint32_t)0x00000004)          /*!< SYSCLK divided by 8 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV10        ((uint32_t)0x00000005)          /*!< SYSCLK divided by 10 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV12        ((uint32_t)0x00000006)          /*!< SYSCLK divided by 12 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV14        ((uint32_t)0x00000007)          /*!< SYSCLK divided by 14 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV16        ((uint32_t)0x00000008)          /*!< SYSCLK divided by 16 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV18        ((uint32_t)0x00000009)          /*!< SYSCLK divided by 18 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV20        ((uint32_t)0x0000000A)          /*!< SYSCLK divided by 20 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV22        ((uint32_t)0x0000000B)          /*!< SYSCLK divided by 22 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV24        ((uint32_t)0x0000000C)          /*!< SYSCLK divided by 24 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV26        ((uint32_t)0x0000000D)          /*!< SYSCLK divided by 26 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV28        ((uint32_t)0x0000000E)          /*!< SYSCLK divided by 28 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV30        ((uint32_t)0x0000000F)          /*!< SYSCLK divided by 30 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV32        ((uint32_t)0x00000010)          /*!< SYSCLK divided by 32 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV34        ((uint32_t)0x00000011)          /*!< SYSCLK divided by 34 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV36        ((uint32_t)0x00000012)          /*!< SYSCLK divided by 36 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV38        ((uint32_t)0x00000013)          /*!< SYSCLK divided by 38 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV40        ((uint32_t)0x00000014)          /*!< SYSCLK divided by 40 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV42        ((uint32_t)0x00000015)          /*!< SYSCLK divided by 42 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV44        ((uint32_t)0x00000016)          /*!< SYSCLK divided by 44 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV46        ((uint32_t)0x00000017)          /*!< SYSCLK divided by 46 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV48        ((uint32_t)0x00000018)          /*!< SYSCLK divided by 48 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV50        ((uint32_t)0x00000019)          /*!< SYSCLK divided by 50 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV52        ((uint32_t)0x0000001A)          /*!< SYSCLK divided by 52 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV54        ((uint32_t)0x0000001B)          /*!< SYSCLK divided by 54 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV56        ((uint32_t)0x0000001C)          /*!< SYSCLK divided by 56 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV58        ((uint32_t)0x0000001D)          /*!< SYSCLK divided by 58 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV60        ((uint32_t)0x0000001E)          /*!< SYSCLK divided by 60 */
-#define SMARTCARD_PRESCALER_SYSCLK_DIV62        ((uint32_t)0x0000001F)          /*!< SYSCLK divided by 62 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV2         (0x00000001U)          /*!< SYSCLK divided by 2 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV4         (0x00000002U)          /*!< SYSCLK divided by 4 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV6         (0x00000003U)          /*!< SYSCLK divided by 6 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV8         (0x00000004U)          /*!< SYSCLK divided by 8 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV10        (0x00000005U)          /*!< SYSCLK divided by 10 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV12        (0x00000006U)          /*!< SYSCLK divided by 12 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV14        (0x00000007U)          /*!< SYSCLK divided by 14 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV16        (0x00000008U)          /*!< SYSCLK divided by 16 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV18        (0x00000009U)          /*!< SYSCLK divided by 18 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV20        (0x0000000AU)          /*!< SYSCLK divided by 20 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV22        (0x0000000BU)          /*!< SYSCLK divided by 22 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV24        (0x0000000CU)          /*!< SYSCLK divided by 24 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV26        (0x0000000DU)          /*!< SYSCLK divided by 26 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV28        (0x0000000EU)          /*!< SYSCLK divided by 28 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV30        (0x0000000FU)          /*!< SYSCLK divided by 30 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV32        (0x00000010U)          /*!< SYSCLK divided by 32 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV34        (0x00000011U)          /*!< SYSCLK divided by 34 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV36        (0x00000012U)          /*!< SYSCLK divided by 36 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV38        (0x00000013U)          /*!< SYSCLK divided by 38 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV40        (0x00000014U)          /*!< SYSCLK divided by 40 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV42        (0x00000015U)          /*!< SYSCLK divided by 42 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV44        (0x00000016U)          /*!< SYSCLK divided by 44 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV46        (0x00000017U)          /*!< SYSCLK divided by 46 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV48        (0x00000018U)          /*!< SYSCLK divided by 48 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV50        (0x00000019U)          /*!< SYSCLK divided by 50 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV52        (0x0000001AU)          /*!< SYSCLK divided by 52 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV54        (0x0000001BU)          /*!< SYSCLK divided by 54 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV56        (0x0000001CU)          /*!< SYSCLK divided by 56 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV58        (0x0000001DU)          /*!< SYSCLK divided by 58 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV60        (0x0000001EU)          /*!< SYSCLK divided by 60 */
+#define SMARTCARD_PRESCALER_SYSCLK_DIV62        (0x0000001FU)          /*!< SYSCLK divided by 62 */
 /**
   * @}
   */
@@ -594,8 +592,8 @@
 #define IS_SMARTCARD_PARITY(PARITY)         (((PARITY) == SMARTCARD_PARITY_EVEN) || \
                                              ((PARITY) == SMARTCARD_PARITY_ODD))
 
-#define IS_SMARTCARD_MODE(MODE)             ((((MODE) & (~((uint32_t)SMARTCARD_MODE_TX_RX))) == 0x00) && \
-                                             ((MODE) != (uint32_t)0x00000000))
+#define IS_SMARTCARD_MODE(MODE)             ((((MODE) & (~((uint32_t)SMARTCARD_MODE_TX_RX))) == 0x00U) && \
+                                             ((MODE) != 0x00000000U))
 
 #define IS_SMARTCARD_POLARITY(CPOL)         (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
 

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_spi.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   SPI HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -59,7 +57,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_spi.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of SPI HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -168,13 +166,13 @@
 /** @defgroup SPI_Error_Codes SPI Error Codes
   * @{
   */ 
-#define HAL_SPI_ERROR_NONE      ((uint32_t)0x00)    /*!< No error             */
-#define HAL_SPI_ERROR_MODF      ((uint32_t)0x01)    /*!< MODF error           */
-#define HAL_SPI_ERROR_CRC       ((uint32_t)0x02)    /*!< CRC error            */
-#define HAL_SPI_ERROR_OVR       ((uint32_t)0x04)    /*!< OVR error            */
-#define HAL_SPI_ERROR_FRE       ((uint32_t)0x08)    /*!< FRE error            */
-#define HAL_SPI_ERROR_DMA       ((uint32_t)0x10)    /*!< DMA transfer error   */
-#define HAL_SPI_ERROR_FLAG      ((uint32_t)0x20)    /*!< Flag: RXNE,TXE, BSY  */
+#define HAL_SPI_ERROR_NONE      (0x00U)    /*!< No error             */
+#define HAL_SPI_ERROR_MODF      (0x01U)    /*!< MODF error           */
+#define HAL_SPI_ERROR_CRC       (0x02U)    /*!< CRC error            */
+#define HAL_SPI_ERROR_OVR       (0x04U)    /*!< OVR error            */
+#define HAL_SPI_ERROR_FRE       (0x08U)    /*!< FRE error            */
+#define HAL_SPI_ERROR_DMA       (0x10U)    /*!< DMA transfer error   */
+#define HAL_SPI_ERROR_FLAG      (0x20U)    /*!< Flag: RXNE,TXE, BSY  */
 
 /**
   * @}
@@ -183,7 +181,7 @@
 /** @defgroup SPI_mode SPI mode
   * @{
   */
-#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
+#define SPI_MODE_SLAVE                  (0x00000000U)
 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
 
 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
@@ -195,7 +193,7 @@
 /** @defgroup SPI_Direction_mode SPI Direction mode
   * @{
   */
-#define SPI_DIRECTION_2LINES             ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES             (0x00000000U)
 #define SPI_DIRECTION_2LINES_RXONLY      SPI_CR1_RXONLY
 #define SPI_DIRECTION_1LINE              SPI_CR1_BIDIMODE
 
@@ -215,7 +213,7 @@
 /** @defgroup SPI_data_size SPI data size
   * @{
   */
-#define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000)
+#define SPI_DATASIZE_8BIT               (0x00000000U)
 #define SPI_DATASIZE_16BIT              SPI_CR1_DFF
 
 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
@@ -227,7 +225,7 @@
 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
   * @{
   */
-#define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
+#define SPI_POLARITY_LOW                (0x00000000U)
 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
 
 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
@@ -239,7 +237,7 @@
 /** @defgroup SPI_Clock_Phase SPI Clock Phase
   * @{
   */
-#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
+#define SPI_PHASE_1EDGE                 (0x00000000U)
 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
 
 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
@@ -252,7 +250,7 @@
   * @{
   */
 #define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_INPUT              (0x00000000U)
 #define SPI_NSS_HARD_OUTPUT             ((uint32_t)(SPI_CR2_SSOE << 16))
 
 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
@@ -265,7 +263,7 @@
 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
   * @{
   */
-#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
+#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
 #define SPI_BAUDRATEPRESCALER_4         ((uint32_t)SPI_CR1_BR_0)
 #define SPI_BAUDRATEPRESCALER_8         ((uint32_t)SPI_CR1_BR_1)
 #define SPI_BAUDRATEPRESCALER_16        ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0)
@@ -289,7 +287,7 @@
 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
   * @{
   */
-#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_MSB                (0x00000000U)
 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
 
 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
@@ -301,7 +299,7 @@
 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
   * @{
   */
-#define SPI_CRCCALCULATION_DISABLE     ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_DISABLE     (0x00000000U)
 #define SPI_CRCCALCULATION_ENABLE      SPI_CR1_CRCEN
 
 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,18 +2,15 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_spi_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Extended SPI HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities SPI extension peripheral:
-  *           + Extended Peripheral Control functions
-  *  
+  *          This file provides firmware functions to manage the following
+  *          SPI peripheral extended functionalities :
+  *           + IO operation functions
+  *
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -53,11 +50,11 @@
 #ifdef HAL_SPI_MODULE_ENABLED
 
 /* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
 
 /** @addtogroup SPI_Exported_Functions
   * @{
@@ -69,16 +66,16 @@
   */
 
 /**
-  * @brief  Initializes the SPI according to the specified parameters 
+  * @brief  Initializes the SPI according to the specified parameters
   *         in the SPI_InitTypeDef and create the associated handle.
   * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
+  *               the configuration information for SPI module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
 {
   /* Check the SPI handle allocation */
-  if(hspi == NULL)
+  if (hspi == NULL)
   {
     return HAL_ERROR;
   }
@@ -97,7 +94,7 @@
   assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
   assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
 
-  if(hspi->State == HAL_SPI_STATE_RESET)
+  if (hspi->State == HAL_SPI_STATE_RESET)
   {
     /* Allocate lock resource and initialize it */
     hspi->Lock = HAL_UNLOCKED;
@@ -105,7 +102,7 @@
     /* Init the low level hardware : GPIO, CLOCK, NVIC... */
     HAL_SPI_MspInit(hspi);
   }
-  
+
   hspi->State = HAL_SPI_STATE_BUSY;
 
   /* Disble the selected SPI peripheral */
@@ -119,7 +116,7 @@
                          hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation);
 
   /* Configure : NSS management */
-  hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode);
+  hspi->Instance->CR2 = (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | hspi->Init.TIMode);
 
   /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
   /* Configure : CRC Polynomial */
@@ -132,7 +129,7 @@
 
   hspi->ErrorCode = HAL_SPI_ERROR_NONE;
   hspi->State = HAL_SPI_STATE_READY;
-  
+
   return HAL_OK;
 }
 
@@ -145,6 +142,7 @@
   */
 
 #endif /* HAL_SPI_MODULE_ENABLED */
+
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_spi_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_spi_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
-  * @brief   Header file of SPI HAL module.
+  * @brief   Header file of SPI HAL Extended module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -33,74 +31,78 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
 #ifndef __STM32L1xx_HAL_SPI_EX_H
 #define __STM32L1xx_HAL_SPI_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"  
+#include "stm32l1xx_hal_def.h"
 
 /** @addtogroup STM32L1xx_HAL_Driver
   * @{
   */
 
-/** @addtogroup SPI
+/** @addtogroup SPIEx
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
-
 /* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
+/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants
   * @{
-  */ 
+  */
 #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
 /** @defgroup SPI_TI_mode SPI TI mode
   * @{
   */
-#define SPI_TIMODE_DISABLE             ((uint32_t)0x00000000)
+#define SPI_TIMODE_DISABLE             (0x00000000U)
 #define SPI_TIMODE_ENABLE              SPI_CR2_FRF
 
 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
                              ((MODE) == SPI_TIMODE_ENABLE))
-#else
-/** @defgroup SPI_TI_mode SPI TI mode disable
-  * @brief  SPI TI Mode not supported for Category 1 and 2 
-  * @{
-  */
-#define SPI_TIMODE_DISABLE             ((uint32_t)0x00000000)
-
-#define IS_SPI_TIMODE(MODE) ((MODE) == SPI_TIMODE_DISABLE)
-
-#endif
 /**
   * @}
   */
-  
+#else
+/** @defgroup SPI_TI_mode SPI TI mode disable
+  * @brief  SPI TI Mode not supported for Category 1 and 2
+  * @{
+  */
+#define SPI_TIMODE_DISABLE             (0x00000000U)
+
+#define IS_SPI_TIMODE(MODE) ((MODE) == SPI_TIMODE_DISABLE)
+/**
+  * @}
+  */
+#endif
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
 /**
   * @}
   */
 
-
 /**
   * @}
-  */ 
+  */
 
 /**
   * @}
   */
-  
+
+/**
+  * @}
+  */
+
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* __STM32L1xx_HAL_SPI_H */
+#endif /* __STM32L1xx_HAL_SPI_EX_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sram.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sram.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_sram.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   SRAM HAL module driver.
   *          This file provides a generic firmware to drive SRAM memories  
   *          mounted as external device.
@@ -64,7 +62,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sram.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_sram.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_sram.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of SRAM HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_tim.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   TIM HAL module driver
   *          This file provides firmware functions to manage the following
   *          functionalities of the Timer (TIM) peripheral:
@@ -102,7 +100,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_tim.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of TIM HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -279,7 +277,7 @@
 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
   * @{
   */
-#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
+#define  TIM_INPUTCHANNELPOLARITY_RISING      (0x00000000U)                     /*!< Polarity for TIx source */
 #define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
 #define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
 /**
@@ -290,7 +288,7 @@
   * @{
   */
 #define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
+#define TIM_ETRPOLARITY_NONINVERTED           (0x0000U)                         /*!< Polarity for ETR source */
 /**
   * @}
   */
@@ -298,7 +296,7 @@
 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
   * @{
   */
-#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
+#define TIM_ETRPRESCALER_DIV1                 (0x0000U)                         /*!< No prescaler is used */
 #define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
 #define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
 #define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
@@ -309,7 +307,7 @@
 /** @defgroup TIM_Counter_Mode TIM Counter Mode
   * @{
   */
-#define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
+#define TIM_COUNTERMODE_UP                 (0x0000U)
 #define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
 #define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
 #define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
@@ -321,7 +319,7 @@
 /** @defgroup TIM_ClockDivision TIM ClockDivision
   * @{
   */
-#define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000)
+#define TIM_CLOCKDIVISION_DIV1                       (0x0000U)
 #define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
 #define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
 /**
@@ -331,7 +329,7 @@
 /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
   * @{
   */
-#define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
+#define TIM_OCMODE_TIMING                   (0x0000U)
 #define TIM_OCMODE_ACTIVE                   (TIM_CCMR1_OC1M_0)
 #define TIM_OCMODE_INACTIVE                 (TIM_CCMR1_OC1M_1)
 #define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
@@ -346,7 +344,7 @@
 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
   * @{
   */
-#define TIM_OCFAST_DISABLE                ((uint32_t)0x0000)
+#define TIM_OCFAST_DISABLE                (0x0000U)
 #define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
 /**
   * @}
@@ -355,7 +353,7 @@
 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
   * @{
   */
-#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
+#define TIM_OCPOLARITY_HIGH                (0x0000U)
 #define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
 /**
   * @}
@@ -365,7 +363,7 @@
   * @{
   */
 #define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
+#define TIM_OCIDLESTATE_RESET              (0x0000U)
 /**
   * @}
   */
@@ -373,11 +371,11 @@
 /** @defgroup TIM_Channel TIM Channel
   * @{
   */
-#define TIM_CHANNEL_1                      ((uint32_t)0x0000)
-#define TIM_CHANNEL_2                      ((uint32_t)0x0004)
-#define TIM_CHANNEL_3                      ((uint32_t)0x0008)
-#define TIM_CHANNEL_4                      ((uint32_t)0x000C)
-#define TIM_CHANNEL_ALL                    ((uint32_t)0x0018)
+#define TIM_CHANNEL_1                      (0x0000U)
+#define TIM_CHANNEL_2                      (0x0004U)
+#define TIM_CHANNEL_3                      (0x0008U)
+#define TIM_CHANNEL_4                      (0x000CU)
+#define TIM_CHANNEL_ALL                    (0x0018U)
 /**
   * @}
   */
@@ -407,7 +405,7 @@
 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
   * @{
   */
-#define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)       /*!< Capture performed each time an edge is detected on the capture input */
+#define TIM_ICPSC_DIV1                     (0x0000U)                /*!< Capture performed each time an edge is detected on the capture input */
 #define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
 #define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
 #define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
@@ -419,7 +417,7 @@
   * @{
   */
 #define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
+#define TIM_OPMODE_REPETITIVE              (0x0000U)
 /**
   * @}
   */
@@ -495,7 +493,7 @@
   */
 #define  TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
 #define  TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
-#define  TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
+#define  TIM_CLOCKSOURCE_ITR0        (0x0000U)
 #define  TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
 #define  TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
 #define  TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
@@ -533,9 +531,9 @@
 /** @defgroup TIM_ClearInput_Source TIM ClearInput Source
   * @{
   */
-#define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001) 
-#define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002) 
-#define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000)
+#define TIM_CLEARINPUTSOURCE_ETR            (0x0001U) 
+#define TIM_CLEARINPUTSOURCE_OCREFCLR       (0x0002U) 
+#define TIM_CLEARINPUTSOURCE_NONE           (0x0000U)
 /**
   * @}
   */
@@ -564,7 +562,7 @@
   * @{
   */
 #define TIM_OSSR_ENABLE         (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE              ((uint32_t)0x0000)
+#define TIM_OSSR_DISABLE        (0x0000U)
 /**
   * @}
   */
@@ -573,7 +571,7 @@
   * @{
   */
 #define TIM_OSSI_ENABLE         (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE            ((uint32_t)0x0000)
+#define TIM_OSSI_DISABLE        (0x0000U)
 /**
   * @}
   */
@@ -581,10 +579,10 @@
 /** @defgroup TIM_Lock_level TIM Lock level
   * @{
   */
-#define TIM_LOCKLEVEL_OFF     ((uint32_t)0x0000)
-#define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
+#define TIM_LOCKLEVEL_OFF       (0x0000U)
+#define TIM_LOCKLEVEL_1         (TIM_BDTR_LOCK_0)
+#define TIM_LOCKLEVEL_2         (TIM_BDTR_LOCK_1)
+#define TIM_LOCKLEVEL_3         (TIM_BDTR_LOCK)
 /**
   * @}
   */
@@ -593,7 +591,7 @@
   * @{
   */
 #define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
-#define  TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000)
+#define TIM_AUTOMATICOUTPUT_DISABLE          (0x0000U)
 /**
   * @}
   */
@@ -601,7 +599,7 @@
 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
   * @{
   */
-#define  TIM_TRGO_RESET            ((uint32_t)0x0000)
+#define  TIM_TRGO_RESET            (0x0000U)
 #define  TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
 #define  TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
 #define  TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
@@ -616,11 +614,11 @@
 /** @defgroup TIM_Slave_Mode TIM Slave Mode
   * @{
   */
-#define TIM_SLAVEMODE_DISABLE              ((uint32_t)0x0000)
-#define TIM_SLAVEMODE_RESET                ((uint32_t)0x0004)
-#define TIM_SLAVEMODE_GATED                ((uint32_t)0x0005)
-#define TIM_SLAVEMODE_TRIGGER              ((uint32_t)0x0006)
-#define TIM_SLAVEMODE_EXTERNAL1            ((uint32_t)0x0007)
+#define TIM_SLAVEMODE_DISABLE              (0x0000U)
+#define TIM_SLAVEMODE_RESET                (0x0004U)
+#define TIM_SLAVEMODE_GATED                (0x0005U)
+#define TIM_SLAVEMODE_TRIGGER              (0x0006U)
+#define TIM_SLAVEMODE_EXTERNAL1            (0x0007U)
 /**
   * @}
   */
@@ -628,8 +626,8 @@
 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
   * @{
   */
-#define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000)
+#define TIM_MASTERSLAVEMODE_ENABLE          (0x0080U)
+#define TIM_MASTERSLAVEMODE_DISABLE         (0x0000U)
 /**
   * @}
   */
@@ -637,15 +635,15 @@
 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
   * @{
   */
-#define TIM_TS_ITR0                        ((uint32_t)0x0000)
-#define TIM_TS_ITR1                        ((uint32_t)0x0010)
-#define TIM_TS_ITR2                        ((uint32_t)0x0020)
-#define TIM_TS_ITR3                        ((uint32_t)0x0030)
-#define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
-#define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
-#define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
-#define TIM_TS_ETRF                        ((uint32_t)0x0070)
-#define TIM_TS_NONE                        ((uint32_t)0xFFFF)
+#define TIM_TS_ITR0                        (0x0000U)
+#define TIM_TS_ITR1                        (0x0010U)
+#define TIM_TS_ITR2                        (0x0020U)
+#define TIM_TS_ITR3                        (0x0030U)
+#define TIM_TS_TI1F_ED                     (0x0040U)
+#define TIM_TS_TI1FP1                      (0x0050U)
+#define TIM_TS_TI2FP2                      (0x0060U)
+#define TIM_TS_ETRF                        (0x0070U)
+#define TIM_TS_NONE                        (0xFFFFU)
 /**
   * @}
   */
@@ -676,7 +674,7 @@
 /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
   * @{
   */
-#define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000)
+#define TIM_TI1SELECTION_CH1                (0x0000U)
 #define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
 /**
   * @}
@@ -685,24 +683,24 @@
 /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
   * @{
   */
-#define TIM_DMABASE_CR1                    (0x00000000)
-#define TIM_DMABASE_CR2                    (0x00000001)
-#define TIM_DMABASE_SMCR                   (0x00000002)
-#define TIM_DMABASE_DIER                   (0x00000003)
-#define TIM_DMABASE_SR                     (0x00000004)
-#define TIM_DMABASE_EGR                    (0x00000005)
-#define TIM_DMABASE_CCMR1                  (0x00000006)
-#define TIM_DMABASE_CCMR2                  (0x00000007)
-#define TIM_DMABASE_CCER                   (0x00000008)
-#define TIM_DMABASE_CNT                    (0x00000009)
-#define TIM_DMABASE_PSC                    (0x0000000A)
-#define TIM_DMABASE_ARR                    (0x0000000B)
-#define TIM_DMABASE_CCR1                   (0x0000000D)
-#define TIM_DMABASE_CCR2                   (0x0000000E)
-#define TIM_DMABASE_CCR3                   (0x0000000F)
-#define TIM_DMABASE_CCR4                   (0x00000010)
-#define TIM_DMABASE_DCR                    (0x00000012)
-#define TIM_DMABASE_OR                     (0x00000013)
+#define TIM_DMABASE_CR1                    (0x00000000U)
+#define TIM_DMABASE_CR2                    (0x00000001U)
+#define TIM_DMABASE_SMCR                   (0x00000002U)
+#define TIM_DMABASE_DIER                   (0x00000003U)
+#define TIM_DMABASE_SR                     (0x00000004U)
+#define TIM_DMABASE_EGR                    (0x00000005U)
+#define TIM_DMABASE_CCMR1                  (0x00000006U)
+#define TIM_DMABASE_CCMR2                  (0x00000007U)
+#define TIM_DMABASE_CCER                   (0x00000008U)
+#define TIM_DMABASE_CNT                    (0x00000009U)
+#define TIM_DMABASE_PSC                    (0x0000000AU)
+#define TIM_DMABASE_ARR                    (0x0000000BU)
+#define TIM_DMABASE_CCR1                   (0x0000000DU)
+#define TIM_DMABASE_CCR2                   (0x0000000EU)
+#define TIM_DMABASE_CCR3                   (0x0000000FU)
+#define TIM_DMABASE_CCR4                   (0x00000010U)
+#define TIM_DMABASE_DCR                    (0x00000012U)
+#define TIM_DMABASE_OR                     (0x00000013U)
 /**
   * @}
   */
@@ -748,8 +746,8 @@
 /** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
   * @{
   */
-#define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
-#define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
+#define TIM_CCx_ENABLE                   (0x0001U)
+#define TIM_CCx_DISABLE                  (0x0000U)
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim_ex.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim_ex.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_tim_ex.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   TIM HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Timer extension peripheral:
@@ -23,7 +21,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim_ex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_tim_ex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_tim_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of TIM HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_uart.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_uart.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_uart.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   UART HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -127,7 +125,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_uart.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_uart.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,14 +2,12 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_uart.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   This file contains all the functions prototypes for the UART 
   *          firmware library.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -157,12 +155,12 @@
   * @{
   */
 
-#define HAL_UART_ERROR_NONE      ((uint32_t)0x00)    /*!< No error            */
-#define HAL_UART_ERROR_PE        ((uint32_t)0x01)    /*!< Parity error        */
-#define HAL_UART_ERROR_NE        ((uint32_t)0x02)    /*!< Noise error         */
-#define HAL_UART_ERROR_FE        ((uint32_t)0x04)    /*!< frame error         */
-#define HAL_UART_ERROR_ORE       ((uint32_t)0x08)    /*!< Overrun error       */
-#define HAL_UART_ERROR_DMA       ((uint32_t)0x10)    /*!< DMA transfer error  */
+#define HAL_UART_ERROR_NONE      (0x00U)    /*!< No error            */
+#define HAL_UART_ERROR_PE        (0x01U)    /*!< Parity error        */
+#define HAL_UART_ERROR_NE        (0x02U)    /*!< Noise error         */
+#define HAL_UART_ERROR_FE        (0x04U)    /*!< frame error         */
+#define HAL_UART_ERROR_ORE       (0x08U)    /*!< Overrun error       */
+#define HAL_UART_ERROR_DMA       (0x10U)    /*!< DMA transfer error  */
 
 /**
   * @}
@@ -171,7 +169,7 @@
 /** @defgroup UART_Word_Length   UART Word Length
   * @{
   */
-#define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
+#define UART_WORDLENGTH_8B                  (0x00000000U)
 #define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
 /**
   * @}
@@ -180,7 +178,7 @@
 /** @defgroup UART_Stop_Bits   UART Number of Stop Bits
   * @{
   */
-#define UART_STOPBITS_1                     ((uint32_t)0x00000000)
+#define UART_STOPBITS_1                     (0x00000000U)
 #define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
 /**
   * @}
@@ -189,7 +187,7 @@
 /** @defgroup UART_Parity  UART Parity
   * @{
   */ 
-#define UART_PARITY_NONE                    ((uint32_t)0x00000000)
+#define UART_PARITY_NONE                    (0x00000000U)
 #define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
 #define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
 /**
@@ -199,7 +197,7 @@
 /** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
   * @{
   */ 
-#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000)
+#define UART_HWCONTROL_NONE                  (0x00000000U)
 #define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
 #define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
 #define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
@@ -221,7 +219,7 @@
  /** @defgroup UART_State  UART State
   * @{
   */ 
-#define UART_STATE_DISABLE                  ((uint32_t)0x00000000)
+#define UART_STATE_DISABLE                  (0x00000000U)
 #define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
 /**
   * @}
@@ -230,7 +228,7 @@
 /** @defgroup UART_Over_Sampling UART Over Sampling
   * @{
   */
-#define UART_OVERSAMPLING_16                    ((uint32_t)0x00000000)
+#define UART_OVERSAMPLING_16                    (0x00000000U)
 #define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
 /**
   * @}
@@ -239,7 +237,7 @@
 /** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
   * @{
   */  
-#define UART_LINBREAKDETECTLENGTH_10B      ((uint32_t)0x00000000)
+#define UART_LINBREAKDETECTLENGTH_10B      (0x00000000U)
 #define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)
 /**
   * @}
@@ -248,7 +246,7 @@
 /** @defgroup UART_WakeUp_functions UART Wakeup Functions
   * @{
   */
-#define UART_WAKEUPMETHOD_IDLELINE                ((uint32_t)0x00000000)
+#define UART_WAKEUPMETHOD_IDLELINE                (0x00000000U)
 #define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)USART_CR1_WAKE)
 /**
   * @}
@@ -628,8 +626,8 @@
                                         ((CONTROL) == UART_HWCONTROL_CTS) || \
                                         ((CONTROL) == UART_HWCONTROL_RTS_CTS))
 
-#define IS_UART_MODE(MODE)             ((((MODE) & (~((uint32_t)UART_MODE_TX_RX))) == 0x00) && \
-                                        ((MODE) != (uint32_t)0x00000000))
+#define IS_UART_MODE(MODE)             ((((MODE) & (~((uint32_t)UART_MODE_TX_RX))) == 0x00U) && \
+                                        ((MODE) != 0x00000000U))
 
 #define IS_UART_STATE(STATE)           (((STATE) == UART_STATE_DISABLE) || \
                                         ((STATE) == UART_STATE_ENABLE))

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_usart.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_usart.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_usart.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   USART HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
@@ -109,7 +107,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_usart.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_usart.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,14 +2,12 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_usart.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   This file contains all the functions prototypes for the USART 
   *          firmware library.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -159,12 +157,12 @@
 /** @defgroup USART_Error_Codes USART Error Codes
   * @{
   */
-#define HAL_USART_ERROR_NONE      ((uint32_t)0x00)    /*!< No error            */
-#define HAL_USART_ERROR_PE        ((uint32_t)0x01)    /*!< Parity error        */
-#define HAL_USART_ERROR_NE        ((uint32_t)0x02)    /*!< Noise error         */
-#define HAL_USART_ERROR_FE        ((uint32_t)0x04)    /*!< frame error         */
-#define HAL_USART_ERROR_ORE       ((uint32_t)0x08)    /*!< Overrun error       */
-#define HAL_USART_ERROR_DMA       ((uint32_t)0x10)     /*!< DMA transfer error  */
+#define HAL_USART_ERROR_NONE      (0x00U)    /*!< No error            */
+#define HAL_USART_ERROR_PE        (0x01U)    /*!< Parity error        */
+#define HAL_USART_ERROR_NE        (0x02U)    /*!< Noise error         */
+#define HAL_USART_ERROR_FE        (0x04U)    /*!< frame error         */
+#define HAL_USART_ERROR_ORE       (0x08U)    /*!< Overrun error       */
+#define HAL_USART_ERROR_DMA       (0x10U)     /*!< DMA transfer error  */
 /**
   * @}
   */
@@ -172,7 +170,7 @@
 /** @defgroup USART_Word_Length USART Word Length
   * @{
   */
-#define USART_WORDLENGTH_8B             ((uint32_t)0x00000000)
+#define USART_WORDLENGTH_8B             (0x00000000U)
 #define USART_WORDLENGTH_9B             ((uint32_t)USART_CR1_M)
 /**
   * @}
@@ -181,7 +179,7 @@
 /** @defgroup USART_Stop_Bits USART Number of Stop Bits
   * @{
   */
-#define USART_STOPBITS_1                ((uint32_t)0x00000000)
+#define USART_STOPBITS_1                (0x00000000U)
 #define USART_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)
 #define USART_STOPBITS_2                ((uint32_t)USART_CR2_STOP_1)
 #define USART_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
@@ -192,7 +190,7 @@
 /** @defgroup USART_Parity USART Parity
   * @{
   */ 
-#define USART_PARITY_NONE               ((uint32_t)0x00000000)
+#define USART_PARITY_NONE               (0x00000000U)
 #define USART_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)
 #define USART_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
 /**
@@ -213,7 +211,7 @@
 /** @defgroup USART_Clock USART Clock
   * @{
   */ 
-#define USART_CLOCK_DISABLE             ((uint32_t)0x00000000)
+#define USART_CLOCK_DISABLE             (0x00000000U)
 #define USART_CLOCK_ENABLE              ((uint32_t)USART_CR2_CLKEN)
 /**
   * @}
@@ -222,7 +220,7 @@
 /** @defgroup USART_Clock_Polarity USART Clock Polarity
   * @{
   */
-#define USART_POLARITY_LOW              ((uint32_t)0x00000000)
+#define USART_POLARITY_LOW              (0x00000000U)
 #define USART_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)
 /**
   * @}
@@ -231,7 +229,7 @@
 /** @defgroup USART_Clock_Phase USART Clock Phase
   * @{
   */
-#define USART_PHASE_1EDGE               ((uint32_t)0x00000000)
+#define USART_PHASE_1EDGE               (0x00000000U)
 #define USART_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)
 /**
   * @}
@@ -240,7 +238,7 @@
 /** @defgroup USART_Last_Bit USART Last Bit
   * @{
   */
-#define USART_LASTBIT_DISABLE           ((uint32_t)0x00000000)
+#define USART_LASTBIT_DISABLE           (0x00000000U)
 #define USART_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)
 /**
   * @}
@@ -250,7 +248,7 @@
   * @{
   */
 #define USART_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)
-#define USART_NACK_DISABLE              ((uint32_t)0x00000000)
+#define USART_NACK_DISABLE              (0x00000000U)
 /**
   * @}
   */
@@ -520,7 +518,7 @@
                                          ((PARITY) == USART_PARITY_EVEN) || \
                                          ((PARITY) == USART_PARITY_ODD))
 
-#define IS_USART_MODE(MODE)             ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00) && ((MODE) != (uint32_t)0x00000000))
+#define IS_USART_MODE(MODE)             ((((MODE) & (~((uint32_t)USART_MODE_TX_RX))) == 0x00U) && ((MODE) != 0x00000000U))
 
 #define IS_USART_CLOCK(CLOCK)           (((CLOCK) == USART_CLOCK_DISABLE) || \
                                          ((CLOCK) == USART_CLOCK_ENABLE))

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_wwdg.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_wwdg.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_wwdg.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   WWDG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Window Watchdog (WWDG) peripheral:
@@ -96,7 +94,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_wwdg.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_wwdg.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_hal_wwdg.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of WWDG HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_adc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_adc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_adc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   ADC LL module driver
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_adc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_adc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_adc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of ADC LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -71,46 +69,46 @@
 
 /* Internal register offset for ADC group regular sequencer configuration */
 /* (offset placed into a spare area of literal definition) */
-#define ADC_SQR1_REGOFFSET                 ((uint32_t)0x00000000U)
-#define ADC_SQR2_REGOFFSET                 ((uint32_t)0x00000100U)
-#define ADC_SQR3_REGOFFSET                 ((uint32_t)0x00000200U)
-#define ADC_SQR4_REGOFFSET                 ((uint32_t)0x00000300U)
-#define ADC_SQR5_REGOFFSET                 ((uint32_t)0x00000400U)
+#define ADC_SQR1_REGOFFSET                 0x00000000U
+#define ADC_SQR2_REGOFFSET                 0x00000100U
+#define ADC_SQR3_REGOFFSET                 0x00000200U
+#define ADC_SQR4_REGOFFSET                 0x00000300U
+#define ADC_SQR5_REGOFFSET                 0x00000400U
 
 #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET | ADC_SQR5_REGOFFSET)
 #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
 
 /* Definition of ADC group regular sequencer bits information to be inserted  */
 /* into ADC group regular sequencer ranks literals definition.                */
-#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ1) */
-#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ2) */
-#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ3) */
-#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ4) */
-#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ5) */
-#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ6) */
-#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ7) */
-#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ8) */
-#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ9) */
-#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ10) */
-#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ11) */
-#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ12) */
-#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
-#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
-#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ15) */
-#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ16) */
-#define ADC_REG_RANK_17_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ17) */
-#define ADC_REG_RANK_18_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ18) */
-#define ADC_REG_RANK_19_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ29) */
-#define ADC_REG_RANK_20_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ20) */
-#define ADC_REG_RANK_21_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ21) */
-#define ADC_REG_RANK_22_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ22) */
-#define ADC_REG_RANK_23_SQRX_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ23) */
-#define ADC_REG_RANK_24_SQRX_BITOFFSET_POS ((uint32_t)25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ24) */
-#define ADC_REG_RANK_25_SQRX_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ25) */
-#define ADC_REG_RANK_26_SQRX_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ26) */
-#define ADC_REG_RANK_27_SQRX_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ27) */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ1) */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ2) */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ3) */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (15U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ4) */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (20U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ5) */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (25U) /* Value equivalent to POSITION_VAL(ADC_SQR5_SQ6) */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ7) */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ8) */
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ9) */
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ10) */
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ11) */
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR4_SQ12) */
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ13) */
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ14) */
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ15) */
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ16) */
+#define ADC_REG_RANK_17_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ17) */
+#define ADC_REG_RANK_18_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ18) */
+#define ADC_REG_RANK_19_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ29) */
+#define ADC_REG_RANK_20_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ20) */
+#define ADC_REG_RANK_21_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ21) */
+#define ADC_REG_RANK_22_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ22) */
+#define ADC_REG_RANK_23_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ23) */
+#define ADC_REG_RANK_24_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ24) */
+#define ADC_REG_RANK_25_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ25) */
+#define ADC_REG_RANK_26_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ26) */
+#define ADC_REG_RANK_27_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ27) */
 #if defined(ADC_SQR1_SQ28)
-#define ADC_REG_RANK_28_SQRX_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ28) */
+#define ADC_REG_RANK_28_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ28) */
 #endif
 
 
@@ -123,17 +121,17 @@
 
 /* Internal register offset for ADC group injected data register */
 /* (offset placed into a spare area of literal definition) */
-#define ADC_JDR1_REGOFFSET                 ((uint32_t)0x00000000U)
-#define ADC_JDR2_REGOFFSET                 ((uint32_t)0x00000100U)
-#define ADC_JDR3_REGOFFSET                 ((uint32_t)0x00000200U)
-#define ADC_JDR4_REGOFFSET                 ((uint32_t)0x00000300U)
+#define ADC_JDR1_REGOFFSET                 0x00000000U
+#define ADC_JDR2_REGOFFSET                 0x00000100U
+#define ADC_JDR3_REGOFFSET                 0x00000200U
+#define ADC_JDR4_REGOFFSET                 0x00000300U
 
 /* Internal register offset for ADC group injected offset configuration */
 /* (offset placed into a spare area of literal definition) */
-#define ADC_JOFR1_REGOFFSET                ((uint32_t)0x00000000U)
-#define ADC_JOFR2_REGOFFSET                ((uint32_t)0x00001000U)
-#define ADC_JOFR3_REGOFFSET                ((uint32_t)0x00002000U)
-#define ADC_JOFR4_REGOFFSET                ((uint32_t)0x00003000U)
+#define ADC_JOFR1_REGOFFSET                0x00000000U
+#define ADC_JOFR2_REGOFFSET                0x00001000U
+#define ADC_JOFR3_REGOFFSET                0x00002000U
+#define ADC_JOFR4_REGOFFSET                0x00003000U
 
 #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
 #define ADC_INJ_JOFRX_REGOFFSET_MASK       (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
@@ -141,10 +139,10 @@
 
 /* Definition of ADC group injected sequencer bits information to be inserted */
 /* into ADC group injected sequencer ranks literals definition.               */
-#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
-#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
-#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
-#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ1) */
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ2) */
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ3) */
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (15U) /* Value equivalent to POSITION_VAL(ADC_JSQR_JSQ4) */
 
 
 
@@ -160,7 +158,7 @@
 #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \
                                              ((ADC_CR2_EXTSEL)                            >> (4U * 1U)) | \
                                              ((ADC_CR2_EXTSEL)                            >> (4U * 2U)) | \
-                                             ((ADC_CR2_EXTSEL)                            >> (4U * 3U))  )
+                                             ((ADC_CR2_EXTSEL)                            >> (4U * 3U)))
 
 /* Mask containing trigger edge masks for each of possible                    */
 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
@@ -168,11 +166,11 @@
 #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \
                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 1U)) | \
                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 2U)) | \
-                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 3U))  )
+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 3U)))
 
 /* Definition of ADC group regular trigger bits information.                  */
-#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
-#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   ((uint32_t)28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
 
 
 
@@ -188,7 +186,7 @@
 #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \
                                              ((ADC_CR2_JEXTSEL)                            >> (4U * 1U)) | \
                                              ((ADC_CR2_JEXTSEL)                            >> (4U * 2U)) | \
-                                             ((ADC_CR2_JEXTSEL)                            >> (4U * 3U))  )
+                                             ((ADC_CR2_JEXTSEL)                            >> (4U * 3U)))
 
 /* Mask containing trigger edge masks for each of possible                    */
 /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
@@ -196,11 +194,11 @@
 #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \
                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 1U)) | \
                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 2U)) | \
-                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 3U))  )
+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 3U)))
 
 /* Definition of ADC group injected trigger bits information.                 */
-#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
-#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ((uint32_t)20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
 
 
 
@@ -215,33 +213,33 @@
 /* - channel sampling time defined by SMPRx register offset                   */
 /*   and SMPx bits positions into SMPRx register                              */
 #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CR1_AWDCH)
-#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t) 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
 #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
-#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
 
 /* Channel differentiation between external and internal channels */
-#define ADC_CHANNEL_ID_INTERNAL_CH         ((uint32_t)0x80000000U) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH         0x80000000U   /* Marker of internal channel */
 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)
 
 /* Internal register offset for ADC channel sampling time configuration */
 /* (offset placed into a spare area of literal definition) */
-#define ADC_SMPR1_REGOFFSET                ((uint32_t)0x00000000U)
-#define ADC_SMPR2_REGOFFSET                ((uint32_t)0x02000000U)
-#define ADC_SMPR3_REGOFFSET                ((uint32_t)0x04000000U)
+#define ADC_SMPR1_REGOFFSET                0x00000000U
+#define ADC_SMPR2_REGOFFSET                0x02000000U
+#define ADC_SMPR3_REGOFFSET                0x04000000U
 #if defined(ADC_SMPR0_SMP31)
-#define ADC_SMPR0_REGOFFSET                ((uint32_t)0x28000000U) /* SMPR0 register offset from SMPR1 is 20 registers. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
+#define ADC_SMPR0_REGOFFSET                0x28000000U   /* SMPR0 register offset from SMPR1 is 20 registers. On STM32L1, parameter not available on all devices: only on STM32L1 Cat.4 and Cat.5. */
 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET | ADC_SMPR0_REGOFFSET)
 #else
 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET | ADC_SMPR3_REGOFFSET)
 #endif /* ADC_SMPR0_SMP31 */
 
-#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    ((uint32_t)0x01F00000U)
-#define ADC_CHANNEL_SMPx_BITOFFSET_POS     ((uint32_t)20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    0x01F00000U
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
 
 /* Definition of channels ID number information to be inserted into           */
 /* channels literals definition.                                              */
-#define ADC_CHANNEL_0_NUMBER               ((uint32_t)0x00000000U)
+#define ADC_CHANNEL_0_NUMBER               0x00000000U
 #define ADC_CHANNEL_1_NUMBER               (                                                                        ADC_CR1_AWDCH_0)
 #define ADC_CHANNEL_2_NUMBER               (                                                      ADC_CR1_AWDCH_1                  )
 #define ADC_CHANNEL_3_NUMBER               (                                                      ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
@@ -278,39 +276,39 @@
 
 /* Definition of channels sampling time information to be inserted into       */
 /* channels literals definition.                                              */
-#define ADC_CHANNEL_0_SMP                  (ADC_SMPR3_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP0) */
-#define ADC_CHANNEL_1_SMP                  (ADC_SMPR3_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP1) */
-#define ADC_CHANNEL_2_SMP                  (ADC_SMPR3_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP2) */
-#define ADC_CHANNEL_3_SMP                  (ADC_SMPR3_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP3) */
-#define ADC_CHANNEL_4_SMP                  (ADC_SMPR3_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP4) */
-#define ADC_CHANNEL_5_SMP                  (ADC_SMPR3_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP5) */
-#define ADC_CHANNEL_6_SMP                  (ADC_SMPR3_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP6) */
-#define ADC_CHANNEL_7_SMP                  (ADC_SMPR3_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP7) */
-#define ADC_CHANNEL_8_SMP                  (ADC_SMPR3_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP8) */
-#define ADC_CHANNEL_9_SMP                  (ADC_SMPR3_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP9) */
-#define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
-#define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
-#define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
-#define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
-#define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
-#define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
-#define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
-#define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
-#define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
-#define ADC_CHANNEL_19_SMP                 (ADC_SMPR2_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP19) */
-#define ADC_CHANNEL_20_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP20) */
-#define ADC_CHANNEL_21_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP21) */
-#define ADC_CHANNEL_22_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t) 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP22) */
-#define ADC_CHANNEL_23_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t) 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP23) */
-#define ADC_CHANNEL_24_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t)12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP24) */
-#define ADC_CHANNEL_25_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t)15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP25) */
-#define ADC_CHANNEL_26_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t)18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP26) */
+#define ADC_CHANNEL_0_SMP                  (ADC_SMPR3_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP0) */
+#define ADC_CHANNEL_1_SMP                  (ADC_SMPR3_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP1) */
+#define ADC_CHANNEL_2_SMP                  (ADC_SMPR3_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP2) */
+#define ADC_CHANNEL_3_SMP                  (ADC_SMPR3_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP3) */
+#define ADC_CHANNEL_4_SMP                  (ADC_SMPR3_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP4) */
+#define ADC_CHANNEL_5_SMP                  (ADC_SMPR3_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP5) */
+#define ADC_CHANNEL_6_SMP                  (ADC_SMPR3_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP6) */
+#define ADC_CHANNEL_7_SMP                  (ADC_SMPR3_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP7) */
+#define ADC_CHANNEL_8_SMP                  (ADC_SMPR3_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP8) */
+#define ADC_CHANNEL_9_SMP                  (ADC_SMPR3_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR3_SMP9) */
+#define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP10) */
+#define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP11) */
+#define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP12) */
+#define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP13) */
+#define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP14) */
+#define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP15) */
+#define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP16) */
+#define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP17) */
+#define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP18) */
+#define ADC_CHANNEL_19_SMP                 (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP19) */
+#define ADC_CHANNEL_20_SMP                 (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP20) */
+#define ADC_CHANNEL_21_SMP                 (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP21) */
+#define ADC_CHANNEL_22_SMP                 (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP22) */
+#define ADC_CHANNEL_23_SMP                 (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP23) */
+#define ADC_CHANNEL_24_SMP                 (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP24) */
+#define ADC_CHANNEL_25_SMP                 (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP25) */
+#define ADC_CHANNEL_26_SMP                 (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP26) */
 #if defined(ADC_SMPR0_SMP31)
-#define ADC_CHANNEL_27_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t)21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP27) */
-#define ADC_CHANNEL_28_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t)24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP28) */
-#define ADC_CHANNEL_29_SMP                 (ADC_SMPR1_REGOFFSET | (((uint32_t)27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP19) */
-#define ADC_CHANNEL_30_SMP                 (ADC_SMPR0_REGOFFSET | (((uint32_t) 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP30) */
-#define ADC_CHANNEL_31_SMP                 (ADC_SMPR0_REGOFFSET | (((uint32_t) 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP31) */
+#define ADC_CHANNEL_27_SMP                 (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP27) */
+#define ADC_CHANNEL_28_SMP                 (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP28) */
+#define ADC_CHANNEL_29_SMP                 (ADC_SMPR1_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP19) */
+#define ADC_CHANNEL_30_SMP                 (ADC_SMPR0_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP30) */
+#define ADC_CHANNEL_31_SMP                 (ADC_SMPR0_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR0_SMP31) */
 #endif /* ADC_SMPR0_SMP31 */
 
 
@@ -322,7 +320,7 @@
 /*   selection of ADC group (ADC groups regular and-or injected).             */
 
 /* Internal register offset for ADC analog watchdog channel configuration */
-#define ADC_AWD_CR1_REGOFFSET              ((uint32_t)0x00000000U)
+#define ADC_AWD_CR1_REGOFFSET              0x00000000U
 
 #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)
 
@@ -330,26 +328,26 @@
 #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)
 
 /* Internal register offset for ADC analog watchdog threshold configuration */
-#define ADC_AWD_TR1_HIGH_REGOFFSET         ((uint32_t)0x00000000U)
-#define ADC_AWD_TR1_LOW_REGOFFSET          ((uint32_t)0x00000001U)
+#define ADC_AWD_TR1_HIGH_REGOFFSET         0x00000000U
+#define ADC_AWD_TR1_LOW_REGOFFSET          0x00000001U
 #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
 
 
 /* ADC registers bits positions */
-#define ADC_CR1_RES_BITOFFSET_POS          ((uint32_t)24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
-#define ADC_TR_HT_BITOFFSET_POS            ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
+#define ADC_CR1_RES_BITOFFSET_POS          (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
+#define ADC_TR_HT_BITOFFSET_POS            (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
 
 
 /* ADC internal channels related definitions */
 /* Internal voltage reference VrefInt */
-#define VREFINT_CAL_ADDR                   ((uint16_t*) ((uint32_t)0x1FF800F8U)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define VREFINT_CAL_VREF                   ((uint32_t) 3000U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
+#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FF800F8U)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF                   ( 3000U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
 /* Temperature sensor */
-#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) ((uint32_t)0x1FF800FAU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) ((uint32_t)0x1FF800FEU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
-#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)                     /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
-#define TEMPSENSOR_CAL_VREFANALOG          ((uint32_t) 3000U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
+#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FF800FAU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32L1, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FF800FEU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32L1, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG          ( 3000U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
 
 
 /**
@@ -611,7 +609,7 @@
 /* List of ADC registers intended to be used (most commonly) with             */
 /* DMA transfer.                                                              */
 /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
-#define LL_ADC_DMA_REG_REGULAR_DATA          ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
+#define LL_ADC_DMA_REG_REGULAR_DATA          0x00000000U   /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
 /**
   * @}
   */
@@ -619,7 +617,7 @@
 /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
   * @{
   */
-#define LL_ADC_CLOCK_ASYNC_DIV1            ((uint32_t)0x00000000U)                               /*!< ADC asynchronous clock without prescaler */
+#define LL_ADC_CLOCK_ASYNC_DIV1            0x00000000U                                           /*!< ADC asynchronous clock without prescaler */
 #define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_ADCPRE_0)                                    /*!< ADC asynchronous clock with prescaler division by 2   */
 #define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_ADCPRE_1)                                    /*!< ADC asynchronous clock with prescaler division by 4   */
 /**
@@ -634,7 +632,7 @@
 /*       If they are not listed below, they do not require any specific       */
 /*       path enable. In this case, Access to measurement path is done        */
 /*       only by selecting the corresponding ADC internal channel.            */
-#define LL_ADC_PATH_INTERNAL_NONE          ((uint32_t)0x00000000U)/*!< ADC measurement pathes all disabled */
+#define LL_ADC_PATH_INTERNAL_NONE          0x00000000U            /*!< ADC measurement pathes all disabled */
 #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel VrefInt */
 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel temperature sensor */
 /**
@@ -644,7 +642,7 @@
 /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
   * @{
   */
-#define LL_ADC_RESOLUTION_12B              ((uint32_t)0x00000000U)             /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_12B              0x00000000U                         /*!< ADC resolution 12 bits */
 #define LL_ADC_RESOLUTION_10B              (                ADC_CR1_RES_0)     /*!< ADC resolution 10 bits */
 #define LL_ADC_RESOLUTION_8B               (ADC_CR1_RES_1                )     /*!< ADC resolution  8 bits */
 #define LL_ADC_RESOLUTION_6B               (ADC_CR1_RES_1 | ADC_CR1_RES_0)     /*!< ADC resolution  6 bits */
@@ -655,7 +653,7 @@
 /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
   * @{
   */
-#define LL_ADC_DATA_ALIGN_RIGHT            ((uint32_t)0x00000000U)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_RIGHT            0x00000000U            /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
 #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CR2_ALIGN)        /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
 /**
   * @}
@@ -664,7 +662,7 @@
 /** @defgroup ADC_LL_EC_LP_MODE_AUTOWAIT  ADC instance - Low power mode auto wait (auto delay)
   * @{
   */
-#define LL_ADC_LP_AUTOWAIT_NONE               ((uint32_t)0x00000000U)                            /*!< ADC low power mode auto wait not activated */
+#define LL_ADC_LP_AUTOWAIT_NONE               0x00000000U                                        /*!< ADC low power mode auto wait not activated */
 #define LL_ADC_LP_AUTOWAIT                    (                                  ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerModeAutoWait(). */
 #define LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES   (                 ADC_CR2_DELS_1                 ) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 7 APB clock cycles */
 #define LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES  (                 ADC_CR2_DELS_1 | ADC_CR2_DELS_0) /*!< ADC low power mode auto wait: Insert a delay between ADC conversions: 15 APB clock cycles */
@@ -679,7 +677,7 @@
 /** @defgroup ADC_LL_EC_LP_MODE_AUTOPOWEROFF  ADC instance - Low power mode auto power-off
   * @{
   */
-#define LL_ADC_LP_AUTOPOWEROFF_NONE                 ((uint32_t)0x00000000U)                      /*!< ADC low power mode auto power-off not activated */
+#define LL_ADC_LP_AUTOPOWEROFF_NONE                 0x00000000U                                  /*!< ADC low power mode auto power-off not activated */
 #define LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE           (ADC_CR1_PDI)                                /*!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) */
 #define LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE       (ADC_CR1_PDD)                                /*!< ADC low power mode auto power-off: ADC power off when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) */
 #define LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES (ADC_CR1_PDI | ADC_CR1_PDD)                  /*!< ADC low power mode auto power-off: ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions (refer to function @ref LL_ADC_SetLowPowerModeAutoWait() ) */
@@ -690,8 +688,8 @@
 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
   * @{
   */
-#define LL_ADC_SEQ_SCAN_DISABLE            ((uint32_t)0x00000000U)  /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
-#define LL_ADC_SEQ_SCAN_ENABLE             ((uint32_t)ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
+#define LL_ADC_SEQ_SCAN_DISABLE            0x00000000U    /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
+#define LL_ADC_SEQ_SCAN_ENABLE             (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
 /**
   * @}
   */
@@ -700,8 +698,8 @@
 /** @defgroup ADC_LL_EC_CHANNELS_BANK ADC instance - Channels bank
   * @{
   */
-#define LL_ADC_CHANNELS_BANK_A             ((uint32_t)0x00000000U) /*!< ADC channels bank A */
-#define LL_ADC_CHANNELS_BANK_B             ((uint32_t)ADC_CR2_CFG) /*!< ADC channels bank B, available in devices categories 3, 4, 5. */
+#define LL_ADC_CHANNELS_BANK_A             0x00000000U   /*!< ADC channels bank A */
+#define LL_ADC_CHANNELS_BANK_B             (ADC_CR2_CFG) /*!< ADC channels bank B, available in devices categories 3, 4, 5. */
 /**
   * @}
   */
@@ -710,9 +708,9 @@
 /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
   * @{
   */
-#define LL_ADC_GROUP_REGULAR               ((uint32_t)0x00000001U) /*!< ADC group regular (available on all STM32 devices) */
-#define LL_ADC_GROUP_INJECTED              ((uint32_t)0x00000002U) /*!< ADC group injected (not available on all STM32 devices)*/
-#define LL_ADC_GROUP_REGULAR_INJECTED      ((uint32_t)0x00000003U) /*!< ADC both groups regular and injected */
+#define LL_ADC_GROUP_REGULAR               0x00000001U   /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED              0x00000002U   /*!< ADC group injected (not available on all STM32 devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED      0x00000003U   /*!< ADC both groups regular and injected */
 /**
   * @}
   */
@@ -771,7 +769,7 @@
 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
   * @{
   */
-#define LL_ADC_REG_TRIG_SOFTWARE           ((uint32_t)0x00000000U)                                                                                     /*!< ADC group regular conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_SOFTWARE           0x00000000U                                                                                                 /*!< ADC group regular conversion trigger internal: SW start. */
 #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
@@ -783,7 +781,7 @@
 #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
 #define LL_ADC_REG_TRIG_EXT_TIM9_CH2       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                             /*!< ADC group regular conversion trigger from external IP: TIM9 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
 #define LL_ADC_REG_TRIG_EXT_TIM9_TRGO      (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger external interrupt line 11. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
 /**
   * @}
   */
@@ -801,7 +799,7 @@
 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
 * @{
 */
-#define LL_ADC_REG_CONV_SINGLE             ((uint32_t)0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */
+#define LL_ADC_REG_CONV_SINGLE             0x00000000U             /*!< ADC conversions are performed in single mode: one conversion per trigger */
 #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CR2_CONT)          /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
 /**
   * @}
@@ -810,7 +808,7 @@
 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
   * @{
   */
-#define LL_ADC_REG_DMA_TRANSFER_NONE       ((uint32_t)0x00000000U)              /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_NONE       0x00000000U              /*!< ADC conversions are not transferred by DMA */
 #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (              ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CR2_DDS | ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
 /**
@@ -820,8 +818,8 @@
 /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)
   * @{
   */
-#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV       ((uint32_t)0x00000000U)  /*!< ADC flag EOC (end of unitary conversion) selected */
-#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV        ((uint32_t)ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
+#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV       0x00000000U    /*!< ADC flag EOC (end of unitary conversion) selected */
+#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV        (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */
 /**
   * @}
   */
@@ -829,7 +827,7 @@
 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
   * @{
   */
-#define LL_ADC_REG_SEQ_SCAN_DISABLE        ((uint32_t)0x00000000U)                                     /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE        0x00000000U                                                 /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
@@ -852,7 +850,7 @@
 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
   * @{
   */
-#define LL_ADC_REG_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000U)                                                          /*!< ADC group regular sequencer discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE     0x00000000U                                                                  /*!< ADC group regular sequencer discontinuous mode disable */
 #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                            ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
 #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                        ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
 #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                    ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
@@ -905,7 +903,7 @@
 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
   * @{
   */
-#define LL_ADC_INJ_TRIG_SOFTWARE           ((uint32_t)0x00000000U)                                                                                         /*!< ADC group injected conversion trigger internal: SW start. */
+#define LL_ADC_INJ_TRIG_SOFTWARE           0x00000000U                                                                                                     /*!< ADC group injected conversion trigger internal: SW start. */
 #define LL_ADC_INJ_TRIG_EXT_TIM9_CH1       (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group injected conversion trigger from external IP: TIM9 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
 #define LL_ADC_INJ_TRIG_EXT_TIM9_TRGO      (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM9 TRGO. Trigger edge set to rising edge (default setting). */
 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
@@ -917,7 +915,7 @@
 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3       (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
 #define LL_ADC_INJ_TRIG_EXT_TIM10_CH1      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM10 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
 #define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
-#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger external interrupt line 15. Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
 /**
   * @}
   */
@@ -935,7 +933,7 @@
 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
 * @{
 */
-#define LL_ADC_INJ_TRIG_INDEPENDENT        ((uint32_t)0x00000000U)/*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
+#define LL_ADC_INJ_TRIG_INDEPENDENT        0x00000000U            /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CR1_JAUTO)        /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
 /**
   * @}
@@ -945,7 +943,7 @@
 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
   * @{
   */
-#define LL_ADC_INJ_SEQ_SCAN_DISABLE        ((uint32_t)0x00000000U)         /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE        0x00000000U                     /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
@@ -956,7 +954,7 @@
 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
   * @{
   */
-#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     ((uint32_t)0x00000000U)/*!< ADC group injected sequencer discontinuous mode disable */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     0x00000000U            /*!< ADC group injected sequencer discontinuous mode disable */
 #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CR1_JDISCEN)      /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
 /**
   * @}
@@ -976,7 +974,7 @@
 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
   * @{
   */
-#define LL_ADC_SAMPLINGTIME_4CYCLES        ((uint32_t)0x00000000U)                                  /*!< Sampling time 4 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_4CYCLES        0x00000000U                                              /*!< Sampling time 4 ADC clock cycles */
 #define LL_ADC_SAMPLINGTIME_9CYCLES        (ADC_SMPR3_SMP0_0)                                       /*!< Sampling time 9 ADC clock cycles */
 #define LL_ADC_SAMPLINGTIME_16CYCLES       (ADC_SMPR3_SMP0_1)                                       /*!< Sampling time 16 ADC clock cycles */
 #define LL_ADC_SAMPLINGTIME_24CYCLES       (ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)                    /*!< Sampling time 24 ADC clock cycles */
@@ -1002,8 +1000,8 @@
 /** @defgroup ADC_LL_EC_CHANNEL_ROUTING_SELECTION  Channel - Routing selection
   * @{
   */
-#define LL_ADC_CHANNEL_ROUTING_DEFAULT     ((uint32_t)0x00000000U) /*!< ADC channel routing default: slow channel */
-#define LL_ADC_CHANNEL_ROUTING_DIRECT      ((uint32_t)0x00000001U) /*!< ADC channel routing direct: fast channel. */
+#define LL_ADC_CHANNEL_ROUTING_DEFAULT     0x00000000U  /*!< ADC channel routing default: slow channel */
+#define LL_ADC_CHANNEL_ROUTING_DIRECT      0x00000001U  /*!< ADC channel routing direct: fast channel. */
 /**
   * @}
   */
@@ -1020,7 +1018,7 @@
 /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
   * @{
   */
-#define LL_ADC_AWD_DISABLE                 ((uint32_t)0x00000000U)                                                                       /*!< ADC analog watchdog monitoring disabled */
+#define LL_ADC_AWD_DISABLE                 0x00000000U                                                                                   /*!< ADC analog watchdog monitoring disabled */
 #define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                             ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
 #define LL_ADC_AWD_ALL_CHANNELS_INJ        (                                            ADC_CR1_JAWDEN                                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (                                            ADC_CR1_JAWDEN | ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
@@ -1183,13 +1181,13 @@
 /* Delay set to maximum value (refer to device datasheet,                     */
 /* parameter "TADC_BUF").                                                     */
 /* Unit: us                                                                   */
-#define LL_ADC_DELAY_VREFINT_STAB_US       ((uint32_t)  10U)  /*!< Delay for internal voltage reference stabilization time */
+#define LL_ADC_DELAY_VREFINT_STAB_US       (  10U)  /*!< Delay for internal voltage reference stabilization time */
 
 /* Delay for temperature sensor stabilization time.                           */
 /* Literal set to maximum value (refer to device datasheet,                   */
 /* parameter "tSTART").                                                       */
 /* Unit: us                                                                   */
-#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ((uint32_t)  10U)  /*!< Delay for internal voltage reference stabilization time */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    (  10U)  /*!< Delay for internal voltage reference stabilization time */
 
 /**
   * @}
@@ -1893,7 +1891,7 @@
   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
   */
 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
-  (((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
+  (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))
 
 /**
   * @brief  Helper macro to convert the ADC conversion data from

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_bus.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_bus.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_bus.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of BUS LL module.
 
   @verbatim                
@@ -25,7 +23,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -89,7 +87,7 @@
 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
   * @{
   */
-#define LL_AHB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
 #define LL_AHB1_GRP1_PERIPH_GPIOA          RCC_AHBENR_GPIOAEN
 #define LL_AHB1_GRP1_PERIPH_GPIOB          RCC_AHBENR_GPIOBEN
 #define LL_AHB1_GRP1_PERIPH_GPIOC          RCC_AHBENR_GPIOCEN
@@ -124,7 +122,7 @@
 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
   * @{
   */
-#define LL_APB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
+#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
 #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
 #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
 #define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
@@ -166,7 +164,7 @@
 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
   * @{
   */
-#define LL_APB2_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
 #define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN
 #define LL_APB2_GRP1_PERIPH_TIM9           RCC_APB2ENR_TIM9EN
 #define LL_APB2_GRP1_PERIPH_TIM10          RCC_APB2ENR_TIM10EN

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_comp.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_comp.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_comp.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   COMP LL module driver
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_comp.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_comp.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_comp.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of COMP LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -64,9 +62,9 @@
   */
 
 /* COMP registers bits positions */
-#define LL_COMP_OUTPUT_LEVEL_COMP1_BITOFFSET_POS ((uint32_t) 7U) /* Value equivalent to POSITION_VAL(COMP_CSR_CMP1OUT) */
-#define LL_COMP_OUTPUT_LEVEL_COMP2_BITOFFSET_POS ((uint32_t)13U) /* Value equivalent to POSITION_VAL(COMP_CSR_CMP2OUT) */
-#define LL_COMP_ENABLE_COMP1_BITOFFSET_POS       ((uint32_t) 4U) /* Value equivalent to POSITION_VAL(COMP_CSR_CMP1EN) */
+#define LL_COMP_OUTPUT_LEVEL_COMP1_BITOFFSET_POS ( 7U) /* Value equivalent to POSITION_VAL(COMP_CSR_CMP1OUT) */
+#define LL_COMP_OUTPUT_LEVEL_COMP2_BITOFFSET_POS (13U) /* Value equivalent to POSITION_VAL(COMP_CSR_CMP2OUT) */
+#define LL_COMP_ENABLE_COMP1_BITOFFSET_POS       ( 4U) /* Value equivalent to POSITION_VAL(COMP_CSR_CMP1EN) */
 
 /**
   * @}
@@ -145,7 +143,7 @@
 /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode
   * @{
   */
-#define LL_COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000U) /*!< Window mode disable: Comparators 1 and 2 are independent */
+#define LL_COMP_WINDOWMODE_DISABLE                 (0x00000000U)           /*!< Window mode disable: Comparators 1 and 2 are independent */
 #define LL_COMP_WINDOWMODE_COMP2_INPUT_PLUS_COMMON (COMP_CSR_WNDWE)        /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP2 input plus (COMP1 input plus is no more accessible, either from GPIO and from ADC channel VCOMP). */
 /**
   * @}
@@ -154,7 +152,7 @@
 /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode
   * @{
   */
-#define LL_COMP_POWERMODE_ULTRALOWPOWER   ((uint32_t)0x00000000U)     /*!< COMP power mode to low speed (specific to COMP instance: COMP2) */
+#define LL_COMP_POWERMODE_ULTRALOWPOWER   (0x00000000U)               /*!< COMP power mode to low speed (specific to COMP instance: COMP2) */
 #define LL_COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_SPEED)            /*!< COMP power mode to fast speed (specific to COMP instance: COMP2) */
 /**
   * @}
@@ -163,7 +161,7 @@
 /** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
   * @{
   */
-#define LL_COMP_INPUT_PLUS_NONE         ((uint32_t)0x00000000U) /*!< Comparator input plus connected not connected */
+#define LL_COMP_INPUT_PLUS_NONE         (0x00000000U)           /*!< Comparator input plus connected not connected */
 #define LL_COMP_INPUT_PLUS_IO1          (RI_ASCR2_GR6_1)        /*!< Comparator input plus connected to IO1 (pin PB4 for COMP2) (specific to COMP instance: COMP2) */
 #define LL_COMP_INPUT_PLUS_IO2          (RI_ASCR2_GR6_2)        /*!< Comparator input plus connected to IO1 (pin PB5 for COMP2) (specific to COMP instance: COMP2) */
 #if defined(RI_ASCR1_CH_31)
@@ -229,7 +227,7 @@
 /** @defgroup COMP_LL_EC_INPUT_PULLING_RESISTOR Comparator input - Pulling resistor
   * @{
   */
-#define LL_COMP_INPUT_MINUS_PULL_NO        ((uint32_t)0x00000000U) /*!< Comparator input minus not connected to any pulling resistor */
+#define LL_COMP_INPUT_MINUS_PULL_NO        (0x00000000U)           /*!< Comparator input minus not connected to any pulling resistor */
 #define LL_COMP_INPUT_MINUS_PULL_UP_10K    (COMP_CSR_10KPU)        /*!< Comparator input minus connected to pull-up resistor of 10kOhm (specific to COMP instance: COMP1) */
 #define LL_COMP_INPUT_MINUS_PULL_UP_400K   (COMP_CSR_400KPU)       /*!< Comparator input minus connected to pull-up resistor of 400kOhm (specific to COMP instance: COMP1) */
 #define LL_COMP_INPUT_MINUS_PULL_DOWN_10K  (COMP_CSR_10KPD)        /*!< Comparator input minus connected to pull-down resistor of 10kOhm (specific to COMP instance: COMP1) */
@@ -243,7 +241,7 @@
   * @{
   */
 #define LL_COMP_OUTPUT_NONE             (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP output is not connected to other peripherals (except GPIO and EXTI that are always connected to COMP output) (specific to COMP instance: COMP2) */
-#define LL_COMP_OUTPUT_TIM2_IC4         ((uint32_t)0x00000000)                                      /*!< COMP output connected to TIM2 input capture 4  (specific to COMP instance: COMP2) */
+#define LL_COMP_OUTPUT_TIM2_IC4         (0x00000000)                                                /*!< COMP output connected to TIM2 input capture 4  (specific to COMP instance: COMP2) */
 #define LL_COMP_OUTPUT_TIM2_OCREFCLR    (                                        COMP_CSR_OUTSEL_0) /*!< COMP output connected to TIM2 OCREF clear      (specific to COMP instance: COMP2) */
 #define LL_COMP_OUTPUT_TIM3_IC4         (                    COMP_CSR_OUTSEL_1                    ) /*!< COMP output connected to TIM3 input capture 4  (specific to COMP instance: COMP2) */
 #define LL_COMP_OUTPUT_TIM3_OCREFCLR    (                    COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP output connected to TIM3 OCREF clear      (specific to COMP instance: COMP2) */
@@ -257,8 +255,8 @@
 /** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
   * @{
   */
-#define LL_COMP_OUTPUT_LEVEL_LOW        ((uint32_t)0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
-#define LL_COMP_OUTPUT_LEVEL_HIGH       ((uint32_t)0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
+#define LL_COMP_OUTPUT_LEVEL_LOW        (0x00000000U) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
+#define LL_COMP_OUTPUT_LEVEL_HIGH       (0x00000001U) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
 /**
   * @}
   */
@@ -276,7 +274,7 @@
 /* Literal set to maximum value (refer to device datasheet,                   */
 /* parameter "tSTART").                                                       */
 /* Unit: us                                                                   */
-#define LL_COMP_DELAY_STARTUP_US          ((uint32_t) 25U)  /*!< Delay for COMP startup time */
+#define LL_COMP_DELAY_STARTUP_US          (25U)  /*!< Delay for COMP startup time */
 
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_cortex.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_cortex.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_cortex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of CORTEX LL module.
   @verbatim
   ==============================================================================
@@ -23,7 +21,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -85,8 +83,8 @@
 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
   * @{
   */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     ((uint32_t)0x00000000U)                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK          ((uint32_t)SysTick_CTRL_CLKSOURCE_Msk) /*!< AHB clock selected as SysTick clock source. */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
 /**
   * @}
   */
@@ -106,7 +104,7 @@
 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
   * @{
   */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     ((uint32_t)0x00000000U)                            /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
 #define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
 #define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
@@ -117,14 +115,14 @@
 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
   * @{
   */
-#define LL_MPU_REGION_NUMBER0              ((uint32_t)0x00U) /*!< REGION Number 0 */
-#define LL_MPU_REGION_NUMBER1              ((uint32_t)0x01U) /*!< REGION Number 1 */
-#define LL_MPU_REGION_NUMBER2              ((uint32_t)0x02U) /*!< REGION Number 2 */
-#define LL_MPU_REGION_NUMBER3              ((uint32_t)0x03U) /*!< REGION Number 3 */
-#define LL_MPU_REGION_NUMBER4              ((uint32_t)0x04U) /*!< REGION Number 4 */
-#define LL_MPU_REGION_NUMBER5              ((uint32_t)0x05U) /*!< REGION Number 5 */
-#define LL_MPU_REGION_NUMBER6              ((uint32_t)0x06U) /*!< REGION Number 6 */
-#define LL_MPU_REGION_NUMBER7              ((uint32_t)0x07U) /*!< REGION Number 7 */
+#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
 /**
   * @}
   */
@@ -132,34 +130,34 @@
 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
   * @{
   */
-#define LL_MPU_REGION_SIZE_32B             ((uint32_t)(0x04U << MPU_RASR_SIZE_Pos)) /*!< 32B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64B             ((uint32_t)(0x05U << MPU_RASR_SIZE_Pos)) /*!< 64B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128B            ((uint32_t)(0x06U << MPU_RASR_SIZE_Pos)) /*!< 128B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256B            ((uint32_t)(0x07U << MPU_RASR_SIZE_Pos)) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B            ((uint32_t)(0x08U << MPU_RASR_SIZE_Pos)) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB             ((uint32_t)(0x09U << MPU_RASR_SIZE_Pos)) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB             ((uint32_t)(0x0AU << MPU_RASR_SIZE_Pos)) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB             ((uint32_t)(0x0BU << MPU_RASR_SIZE_Pos)) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB             ((uint32_t)(0x0CU << MPU_RASR_SIZE_Pos)) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB            ((uint32_t)(0x0DU << MPU_RASR_SIZE_Pos)) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB            ((uint32_t)(0x0EU << MPU_RASR_SIZE_Pos)) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB            ((uint32_t)(0x0FU << MPU_RASR_SIZE_Pos)) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB           ((uint32_t)(0x10U << MPU_RASR_SIZE_Pos)) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB           ((uint32_t)(0x11U << MPU_RASR_SIZE_Pos)) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB           ((uint32_t)(0x12U << MPU_RASR_SIZE_Pos)) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB             ((uint32_t)(0x13U << MPU_RASR_SIZE_Pos)) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB             ((uint32_t)(0x14U << MPU_RASR_SIZE_Pos)) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB             ((uint32_t)(0x15U << MPU_RASR_SIZE_Pos)) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB             ((uint32_t)(0x16U << MPU_RASR_SIZE_Pos)) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB            ((uint32_t)(0x17U << MPU_RASR_SIZE_Pos)) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB            ((uint32_t)(0x18U << MPU_RASR_SIZE_Pos)) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB            ((uint32_t)(0x19U << MPU_RASR_SIZE_Pos)) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB           ((uint32_t)(0x1AU << MPU_RASR_SIZE_Pos)) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB           ((uint32_t)(0x1BU << MPU_RASR_SIZE_Pos)) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB           ((uint32_t)(0x1CU << MPU_RASR_SIZE_Pos)) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB             ((uint32_t)(0x1DU << MPU_RASR_SIZE_Pos)) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB             ((uint32_t)(0x1EU << MPU_RASR_SIZE_Pos)) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB             ((uint32_t)(0x1FU << MPU_RASR_SIZE_Pos)) /*!< 4GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
 /**
   * @}
   */
@@ -167,12 +165,12 @@
 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
   * @{
   */
-#define LL_MPU_REGION_NO_ACCESS            ((uint32_t)(0x00U << MPU_RASR_AP_Pos)) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW              ((uint32_t)(0x01U << MPU_RASR_AP_Pos)) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO          ((uint32_t)(0x02U << MPU_RASR_AP_Pos)) /*!< RW privileged - RO user (Write in a user program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS          ((uint32_t)(0x03U << MPU_RASR_AP_Pos)) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO              ((uint32_t)(0x05U << MPU_RASR_AP_Pos)) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO          ((uint32_t)(0x06U << MPU_RASR_AP_Pos)) /*!< RO privileged & user (read only) */
+#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
 /**
   * @}
   */
@@ -180,10 +178,10 @@
 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
   * @{
   */
-#define LL_MPU_TEX_LEVEL0                  ((uint32_t)(0x00U << MPU_RASR_TEX_Pos)) /*!< b000 for TEX bits */
-#define LL_MPU_TEX_LEVEL1                  ((uint32_t)(0x01U << MPU_RASR_TEX_Pos)) /*!< b001 for TEX bits */
-#define LL_MPU_TEX_LEVEL2                  ((uint32_t)(0x02U << MPU_RASR_TEX_Pos)) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4                  ((uint32_t)(0x04U << MPU_RASR_TEX_Pos)) /*!< b100 for TEX bits */
+#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
 /**
   * @}
   */
@@ -191,7 +189,7 @@
 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
   * @{
   */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   ((uint32_t)0x00U) /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
 /**
   * @}
@@ -201,7 +199,7 @@
   * @{
   */
 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE        ((uint32_t)0x00U) /*!< Not Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
 /**
   * @}
   */
@@ -210,7 +208,7 @@
   * @{
   */
 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE        ((uint32_t)0x00U) /*!< Not Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
 /**
   * @}
   */
@@ -219,7 +217,7 @@
   * @{
   */
 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE       ((uint32_t)0x00U) /*!< Not Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_crc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_crc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_crc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   CRC LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_crc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_crc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_crc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of CRC LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dac.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dac.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_dac.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   DAC LL module driver
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -40,7 +38,7 @@
 #include "stm32l1xx_ll_dac.h"
 #include "stm32l1xx_ll_bus.h"
 
-#ifdef  USE_FULL_ASSERT
+#ifdef USE_FULL_ASSERT
   #include "stm32_assert.h"
 #else
   #define assert_param(expr) ((void)0U)

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dac.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dac.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_dac.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of DAC LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -70,36 +68,36 @@
 /* - channel bits position into register SWTRIG                               */
 /* - channel register offset of data holding register DHRx                    */
 /* - channel register offset of data output register DORx                     */
-#define DAC_CR_CH1_BITOFFSET           ((uint32_t) 0U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
-#define DAC_CR_CH2_BITOFFSET           ((uint32_t)16U) /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
+#define DAC_CR_CH1_BITOFFSET           0U    /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET           16U   /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */
 #define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
 
 #define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
 #define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */
 #define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
 
-#define DAC_REG_DHR12R1_REGOFFSET      ((uint32_t)0x00000000U) /* Register DHR12Rx channel 1 taken as reference */
-#define DAC_REG_DHR12L1_REGOFFSET      ((uint32_t)0x00100000U) /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R1_REGOFFSET       ((uint32_t)0x02000000U) /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DHR12R2_REGOFFSET      ((uint32_t)0x00030000U) /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
-#define DAC_REG_DHR12L2_REGOFFSET      ((uint32_t)0x00400000U) /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
-#define DAC_REG_DHR8R2_REGOFFSET       ((uint32_t)0x05000000U) /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
-#define DAC_REG_DHR12RX_REGOFFSET_MASK ((uint32_t)0x000F0000U)
-#define DAC_REG_DHR12LX_REGOFFSET_MASK ((uint32_t)0x00F00000U)
-#define DAC_REG_DHR8RX_REGOFFSET_MASK  ((uint32_t)0x0F000000U)
+#define DAC_REG_DHR12R1_REGOFFSET      0x00000000U             /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET      0x00100000U             /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R1_REGOFFSET       0x02000000U             /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12R2_REGOFFSET      0x00030000U             /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */
+#define DAC_REG_DHR12L2_REGOFFSET      0x00400000U             /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */
+#define DAC_REG_DHR8R2_REGOFFSET       0x05000000U             /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U
+#define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000U
 #define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
 
-#define DAC_REG_DOR1_REGOFFSET         ((uint32_t)0x00000000U) /* Register DORx channel 1 taken as reference */
-#define DAC_REG_DOR2_REGOFFSET         ((uint32_t)0x10000000U)/* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
+#define DAC_REG_DOR1_REGOFFSET         0x00000000U             /* Register DORx channel 1 taken as reference */
+#define DAC_REG_DOR2_REGOFFSET         0x10000000U             /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */
 #define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
 
 /* DAC registers bits positions */
-#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
-#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS ((uint32_t)20U) /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
-#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS  ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                16U  /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                20U  /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                  8U  /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */
 
 /* Miscellaneous data */
-#define DAC_DIGITAL_SCALE_12BITS           ((uint32_t)4095U)                     /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
+#define DAC_DIGITAL_SCALE_12BITS                        4095U  /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */
 
 /**
   * @}
@@ -221,7 +219,7 @@
 #define LL_DAC_TRIG_SOFTWARE               (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */
 #define LL_DAC_TRIG_EXT_TIM2_TRGO          (DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM4_TRGO          (DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */
-#define LL_DAC_TRIG_EXT_TIM6_TRGO          ((uint32_t)0x00000000U)                            /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO          0x00000000U                                        /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */
 #define LL_DAC_TRIG_EXT_TIM9_TRGO          (                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */
 #define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */
@@ -232,7 +230,7 @@
 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
   * @{
   */
-#define LL_DAC_WAVE_AUTO_GENERATION_NONE     ((uint32_t)0x00000000U) /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000U             /*!< DAC channel wave auto generation mode disabled. */
 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (DAC_CR_WAVE1_0)        /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1)        /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
 /**
@@ -242,7 +240,7 @@
 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
   * @{
   */
-#define LL_DAC_NOISE_LFSR_UNMASK_BIT0      ((uint32_t)0x00000000U)                                             /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000U                                                         /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
@@ -261,7 +259,7 @@
 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
   * @{
   */
-#define LL_DAC_TRIANGLE_AMPLITUDE_1        ((uint32_t)0x00000000U)                                             /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000U                                                         /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
 #define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
 #define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
 #define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
@@ -280,7 +278,7 @@
 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
   * @{
   */
-#define LL_DAC_OUTPUT_BUFFER_ENABLE        ((uint32_t)0x00000000U) /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000U             /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
 #define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_CR_BOFF1)          /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
 /**
   * @}
@@ -290,8 +288,8 @@
 /** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
   * @{
   */
-#define LL_DAC_RESOLUTION_12B              ((uint32_t)0x00000000U) /*!< DAC channel resolution 12 bits */
-#define LL_DAC_RESOLUTION_8B               ((uint32_t)0x00000002U) /*!< DAC channel resolution 8 bits */
+#define LL_DAC_RESOLUTION_12B              0x00000000U             /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B               0x00000002U             /*!< DAC channel resolution 8 bits */
 /**
   * @}
   */
@@ -329,7 +327,7 @@
 /* Literal set to maximum value (refer to device datasheet,                   */
 /* parameter "tWAKEUP").                                                      */
 /* Unit: us                                                                   */
-#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US ((uint32_t) 15U)  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             15U  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
 
 /* Delay for DAC channel voltage settling time.                               */
 /* Note: DAC channel startup time depends on board application environment:   */
@@ -342,7 +340,7 @@
 /* Literal set to maximum value (refer to device datasheet,                   */
 /* parameter "tSETTLING").                                                    */
 /* Unit: us                                                                   */
-#define LL_DAC_DELAY_VOLTAGE_SETTLING_US  ((uint32_t) 12U)  /*!< Delay for DAC channel voltage settling time */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US                    12U  /*!< Delay for DAC channel voltage settling time */
 /**
   * @}
   */
@@ -443,7 +441,7 @@
   * @retval ADC conversion data equivalent voltage value (unit: mVolt)
   */
 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
-  (((uint32_t)0xFFFU) >> ((__DAC_RESOLUTION__) << 1U))
+  ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U))
 
 /**
   * @brief  Helper macro to calculate the DAC conversion data (unit: digital

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dma.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dma.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_dma.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   DMA LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -83,7 +81,7 @@
                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD)  || \
                                                  ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
 
-#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= (uint32_t)0x0000FFFFU)
+#define IS_LL_DMA_NBDATA(__VALUE__)             ((__VALUE__)  <= 0x0000FFFFU)
 
 
 #define IS_LL_DMA_PRIORITY(__VALUE__)           (((__VALUE__) == LL_DMA_PRIORITY_LOW)    || \
@@ -348,15 +346,15 @@
 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
 {
   /* Set DMA_InitStruct fields to default values */
-  DMA_InitStruct->PeriphOrM2MSrcAddress  = (uint32_t)0x00000000U;
-  DMA_InitStruct->MemoryOrM2MDstAddress  = (uint32_t)0x00000000U;
+  DMA_InitStruct->PeriphOrM2MSrcAddress  = 0x00000000U;
+  DMA_InitStruct->MemoryOrM2MDstAddress  = 0x00000000U;
   DMA_InitStruct->Direction              = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
   DMA_InitStruct->Mode                   = LL_DMA_MODE_NORMAL;
   DMA_InitStruct->PeriphOrM2MSrcIncMode  = LL_DMA_PERIPH_NOINCREMENT;
   DMA_InitStruct->MemoryOrM2MDstIncMode  = LL_DMA_MEMORY_NOINCREMENT;
   DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
   DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
-  DMA_InitStruct->NbData                 = (uint32_t)0x00000000U;
+  DMA_InitStruct->NbData                 = 0x00000000U;
   DMA_InitStruct->Priority               = LL_DMA_PRIORITY_LOW;
 }
 

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dma.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_dma.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_dma.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of DMA LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -77,17 +75,6 @@
   */
 
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Constants DMA Private Constants
-  * @{
-  */
-/* Define used to get CSELR register offset */
-#define DMA_CSELR_OFFSET                  (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
-
-/* Defines used for the bit position in the register and perform offsets */
-#define DMA_POSITION_CSELR_CXS            POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
-/**
-  * @}
-  */
 
 /* Private macros ------------------------------------------------------------*/
 #if defined(USE_FULL_LL_DRIVER)
@@ -261,15 +248,15 @@
 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
   * @{
   */
-#define LL_DMA_CHANNEL_1                  ((uint32_t)0x00000001U) /*!< DMA Channel 1 */
-#define LL_DMA_CHANNEL_2                  ((uint32_t)0x00000002U) /*!< DMA Channel 2 */
-#define LL_DMA_CHANNEL_3                  ((uint32_t)0x00000003U) /*!< DMA Channel 3 */
-#define LL_DMA_CHANNEL_4                  ((uint32_t)0x00000004U) /*!< DMA Channel 4 */
-#define LL_DMA_CHANNEL_5                  ((uint32_t)0x00000005U) /*!< DMA Channel 5 */
-#define LL_DMA_CHANNEL_6                  ((uint32_t)0x00000006U) /*!< DMA Channel 6 */
-#define LL_DMA_CHANNEL_7                  ((uint32_t)0x00000007U) /*!< DMA Channel 7 */
+#define LL_DMA_CHANNEL_1                  0x00000001U /*!< DMA Channel 1 */
+#define LL_DMA_CHANNEL_2                  0x00000002U /*!< DMA Channel 2 */
+#define LL_DMA_CHANNEL_3                  0x00000003U /*!< DMA Channel 3 */
+#define LL_DMA_CHANNEL_4                  0x00000004U /*!< DMA Channel 4 */
+#define LL_DMA_CHANNEL_5                  0x00000005U /*!< DMA Channel 5 */
+#define LL_DMA_CHANNEL_6                  0x00000006U /*!< DMA Channel 6 */
+#define LL_DMA_CHANNEL_7                  0x00000007U /*!< DMA Channel 7 */
 #if defined(USE_FULL_LL_DRIVER)
-#define LL_DMA_CHANNEL_ALL                ((uint32_t)0xFFFF0000U) /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
+#define LL_DMA_CHANNEL_ALL                0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
 #endif /*USE_FULL_LL_DRIVER*/
 /**
   * @}
@@ -278,7 +265,7 @@
 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
   * @{
   */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U             /*!< Peripheral to memory direction */
 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR             /*!< Memory to peripheral direction */
 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM         /*!< Memory to memory direction     */
 /**
@@ -288,7 +275,7 @@
 /** @defgroup DMA_LL_EC_MODE Transfer mode
   * @{
   */
-#define LL_DMA_MODE_NORMAL                ((uint32_t)0x00000000U) /*!< Normal Mode                  */
+#define LL_DMA_MODE_NORMAL                0x00000000U             /*!< Normal Mode                  */
 #define LL_DMA_MODE_CIRCULAR              DMA_CCR_CIRC            /*!< Circular Mode                */
 /**
   * @}
@@ -298,7 +285,7 @@
   * @{
   */
 #define LL_DMA_PERIPH_INCREMENT           DMA_CCR_PINC            /*!< Peripheral increment mode Enable */
-#define LL_DMA_PERIPH_NOINCREMENT         ((uint32_t)0x00000000U) /*!< Peripheral increment mode Disable */
+#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U             /*!< Peripheral increment mode Disable */
 /**
   * @}
   */
@@ -307,7 +294,7 @@
   * @{
   */
 #define LL_DMA_MEMORY_INCREMENT           DMA_CCR_MINC            /*!< Memory increment mode Enable  */
-#define LL_DMA_MEMORY_NOINCREMENT         ((uint32_t)0x00000000U) /*!< Memory increment mode Disable */
+#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U             /*!< Memory increment mode Disable */
 /**
   * @}
   */
@@ -315,7 +302,7 @@
 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
   * @{
   */
-#define LL_DMA_PDATAALIGN_BYTE            ((uint32_t)0x00000000U) /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_BYTE            0x00000000U             /*!< Peripheral data alignment : Byte     */
 #define LL_DMA_PDATAALIGN_HALFWORD        DMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */
 #define LL_DMA_PDATAALIGN_WORD            DMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */
 /**
@@ -325,7 +312,7 @@
 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
   * @{
   */
-#define LL_DMA_MDATAALIGN_BYTE            ((uint32_t)0x00000000U) /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_BYTE            0x00000000U             /*!< Memory data alignment : Byte     */
 #define LL_DMA_MDATAALIGN_HALFWORD        DMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord */
 #define LL_DMA_MDATAALIGN_WORD            DMA_CCR_MSIZE_1         /*!< Memory data alignment : Word     */
 /**
@@ -335,7 +322,7 @@
 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
   * @{
   */
-#define LL_DMA_PRIORITY_LOW               ((uint32_t)0x00000000U) /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_LOW               0x00000000U             /*!< Priority level : Low       */
 #define LL_DMA_PRIORITY_MEDIUM            DMA_CCR_PL_0            /*!< Priority level : Medium    */
 #define LL_DMA_PRIORITY_HIGH              DMA_CCR_PL_1            /*!< Priority level : High      */
 #define LL_DMA_PRIORITY_VERYHIGH          DMA_CCR_PL              /*!< Priority level : Very_High */
@@ -973,7 +960,8 @@
 
 /**
   * @brief  Configure the Source and Destination addresses.
-  * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr)
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @note   Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
   * @rmtoll CPAR         PA            LL_DMA_ConfigAddresses\n
   *         CMAR         MA            LL_DMA_ConfigAddresses
   * @param  DMAx DMAx Instance
@@ -999,24 +987,21 @@
   /* Direction Memory to Periph */
   if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
   {
-    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
-               SrcAddress);
-    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
-               DstAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
   }
   /* Direction Periph to Memory and Memory to Memory */
   else
   {
-    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
-               SrcAddress);
-    MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
-               DstAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
+    WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
   }
 }
 
 /**
   * @brief  Set the Memory address.
   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
   * @rmtoll CMAR         MA            LL_DMA_SetMemoryAddress
   * @param  DMAx DMAx Instance
   * @param  Channel This parameter can be one of the following values:
@@ -1032,13 +1017,13 @@
   */
 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
 {
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
-             MemoryAddress);
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
 }
 
 /**
   * @brief  Set the Peripheral address.
   * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
   * @rmtoll CPAR         PA            LL_DMA_SetPeriphAddress
   * @param  DMAx DMAx Instance
   * @param  Channel This parameter can be one of the following values:
@@ -1054,8 +1039,7 @@
   */
 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
 {
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
-             PeriphAddress);
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
 }
 
 /**
@@ -1075,8 +1059,7 @@
   */
 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
 {
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
-                   DMA_CMAR_MA));
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
 }
 
 /**
@@ -1096,13 +1079,13 @@
   */
 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
 {
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
-                   DMA_CPAR_PA));
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
 }
 
 /**
   * @brief  Set the Memory to Memory Source address.
   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
   * @rmtoll CPAR         PA            LL_DMA_SetM2MSrcAddress
   * @param  DMAx DMAx Instance
   * @param  Channel This parameter can be one of the following values:
@@ -1118,13 +1101,13 @@
   */
 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
 {
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DMA_CPAR_PA,
-             MemoryAddress);
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
 }
 
 /**
   * @brief  Set the Memory to Memory Destination address.
   * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
   * @rmtoll CMAR         MA            LL_DMA_SetM2MDstAddress
   * @param  DMAx DMAx Instance
   * @param  Channel This parameter can be one of the following values:
@@ -1140,8 +1123,7 @@
   */
 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
 {
-  MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DMA_CMAR_MA,
-             MemoryAddress);
+  WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
 }
 
 /**
@@ -1161,8 +1143,7 @@
   */
 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
 {
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR,
-                   DMA_CPAR_PA));
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
 }
 
 /**
@@ -1182,8 +1163,7 @@
   */
 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
 {
-  return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR,
-                   DMA_CMAR_MA));
+  return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
 }
 
 

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_exti.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_exti.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_exti.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   EXTI LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -107,7 +105,7 @@
   LL_EXTI_WriteReg(FTSR,  0x00000000U);
   /* Software interrupt event register set to default reset values */
   LL_EXTI_WriteReg(SWIER, 0x00000000U);
-  /* Pending register set to default reset values */
+  /* Pending register clear */
   LL_EXTI_WriteReg(PR,    0x00FFFFFFU);
 
   return SUCCESS;

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_exti.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_exti.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_exti.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of EXTI LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -122,7 +120,9 @@
 #define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
 #endif
 #define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
 #define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
+#endif
 #define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
 #if defined(EXTI_IMR_IM20)
 #define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
@@ -161,10 +161,10 @@
 #define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
 
 
-#define LL_EXTI_LINE_ALL               ((uint32_t)0xFFFFFFFFU)  /*!< All Extended line */
+#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */
 
 #if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE              ((uint32_t)0x00000000U)  /*!< None Extended line */
+#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */
 #endif /*USE_FULL_LL_DRIVER*/
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_fsmc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_fsmc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_fsmc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   FSMC Low Layer HAL module driver.
   *
   *          This file provides firmware functions to manage the following
@@ -39,7 +37,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_fsmc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_fsmc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_fsmc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of FSMC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -303,10 +301,10 @@
 /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
   * @{
   */
-#define FSMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)
-#define FSMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)
-#define FSMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)
-#define FSMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)
+#define FSMC_NORSRAM_BANK1                       (0x00000000U)
+#define FSMC_NORSRAM_BANK2                       (0x00000002U)
+#define FSMC_NORSRAM_BANK3                       (0x00000004U)
+#define FSMC_NORSRAM_BANK4                       (0x00000006U)
 
 /**
   * @}
@@ -316,7 +314,7 @@
   * @{
   */
 
-#define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
+#define FSMC_DATA_ADDRESS_MUX_DISABLE            (0x00000000U)
 #define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FSMC_BCRx_MUXEN)
 
 /**
@@ -327,7 +325,7 @@
   * @{
   */
 
-#define FSMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
+#define FSMC_MEMORY_TYPE_SRAM                    (0x00000000U)
 #define FSMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FSMC_BCRx_MTYP_0)
 #define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)FSMC_BCRx_MTYP_1)
 
@@ -339,7 +337,7 @@
   * @{
   */
 
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_MEM_BUS_WIDTH_8             (0x00000000U)
 #define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FSMC_BCRx_MWID_0)
 #define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FSMC_BCRx_MWID_1)
 
@@ -352,7 +350,7 @@
   */
 
 #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FSMC_BCRx_FACCEN)
-#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
+#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        (0x00000000U)
 /**
   * @}
   */
@@ -361,7 +359,7 @@
   * @{
   */
 
-#define FSMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000)
+#define FSMC_BURST_ACCESS_MODE_DISABLE           (0x00000000U)
 #define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FSMC_BCRx_BURSTEN)
 
 /**
@@ -373,7 +371,7 @@
   * @{
   */
 
-#define FSMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_POLARITY_LOW            (0x00000000U)
 #define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FSMC_BCRx_WAITPOL)
 
 /**
@@ -384,7 +382,7 @@
   * @{
   */
 
-#define FSMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
+#define FSMC_WRAP_MODE_DISABLE                   (0x00000000U)
 #define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)FSMC_BCRx_WRAPMOD)
 
 /**
@@ -395,7 +393,7 @@
   * @{
   */
 
-#define FSMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
+#define FSMC_WAIT_TIMING_BEFORE_WS               (0x00000000U)
 #define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)FSMC_BCRx_WAITCFG)
 
 /**
@@ -406,7 +404,7 @@
   * @{
   */
 
-#define FSMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
+#define FSMC_WRITE_OPERATION_DISABLE             (0x00000000U)
 #define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)FSMC_BCRx_WREN)
 
 /**
@@ -417,7 +415,7 @@
   * @{
   */
 
-#define FSMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
+#define FSMC_WAIT_SIGNAL_DISABLE                 (0x00000000U)
 #define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FSMC_BCRx_WAITEN)
 
 /**
@@ -428,7 +426,7 @@
   * @{
   */
 
-#define FSMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
+#define FSMC_EXTENDED_MODE_DISABLE               (0x00000000U)
 #define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)FSMC_BCRx_EXTMOD)
 
 /**
@@ -439,7 +437,7 @@
   * @{
   */
 
-#define FSMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
+#define FSMC_ASYNCHRONOUS_WAIT_DISABLE           (0x00000000U)
 #define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FSMC_BCRx_ASYNCWAIT)
 
 /**
@@ -450,7 +448,7 @@
   * @{
   */
 
-#define FSMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
+#define FSMC_WRITE_BURST_DISABLE                 (0x00000000U)
 #define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)FSMC_BCRx_CBURSTRW)
 
 /**
@@ -461,7 +459,7 @@
   * @{
   */
 
-#define FSMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
+#define FSMC_ACCESS_MODE_A                        (0x00000000U)
 #define FSMC_ACCESS_MODE_B                        ((uint32_t)FSMC_BTRx_ACCMOD_0)
 #define FSMC_ACCESS_MODE_C                        ((uint32_t)FSMC_BTRx_ACCMOD_1)
 #define FSMC_ACCESS_MODE_D                        ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_gpio.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_gpio.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_gpio.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   GPIO LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -62,7 +60,7 @@
 /** @addtogroup GPIO_LL_Private_Macros
   * @{
   */
-#define IS_LL_GPIO_PIN(__VALUE__)          ((((uint32_t)0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
+#define IS_LL_GPIO_PIN(__VALUE__)          (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
 
 #define IS_LL_GPIO_MODE(__VALUE__)         (((__VALUE__) == LL_GPIO_MODE_INPUT)     ||\
                                             ((__VALUE__) == LL_GPIO_MODE_OUTPUT)    ||\
@@ -302,4 +300,3 @@
 #endif /* USE_FULL_LL_DRIVER */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_gpio.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_gpio.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_gpio.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of GPIO LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -152,7 +150,7 @@
 /** @defgroup GPIO_LL_EC_MODE Mode
   * @{
   */
-#define LL_GPIO_MODE_INPUT                 ((uint32_t)0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
 #define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */
 #define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode */
 #define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */
@@ -163,7 +161,7 @@
 /** @defgroup GPIO_LL_EC_OUTPUT Output Type
   * @{
   */
-#define LL_GPIO_OUTPUT_PUSHPULL            ((uint32_t)0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
 #define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
 /**
   * @}
@@ -172,7 +170,7 @@
 /** @defgroup GPIO_LL_EC_SPEED Output Speed
   * @{
   */
-#define LL_GPIO_SPEED_FREQ_LOW             ((uint32_t)0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
 #define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
 #define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed   */
 #define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEEDR0   /*!< Select I/O high output speed   */
@@ -183,7 +181,7 @@
 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
   * @{
   */
-#define LL_GPIO_PULL_NO                    ((uint32_t)0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
 #define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
 #define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
 /**
@@ -193,22 +191,22 @@
 /** @defgroup GPIO_LL_EC_AF Alternate Function
   * @{
   */
-#define LL_GPIO_AF_0                       ((uint32_t)0x0000000U) /*!< Select alternate function 0 */
-#define LL_GPIO_AF_1                       ((uint32_t)0x0000001U) /*!< Select alternate function 1 */
-#define LL_GPIO_AF_2                       ((uint32_t)0x0000002U) /*!< Select alternate function 2 */
-#define LL_GPIO_AF_3                       ((uint32_t)0x0000003U) /*!< Select alternate function 3 */
-#define LL_GPIO_AF_4                       ((uint32_t)0x0000004U) /*!< Select alternate function 4 */
-#define LL_GPIO_AF_5                       ((uint32_t)0x0000005U) /*!< Select alternate function 5 */
-#define LL_GPIO_AF_6                       ((uint32_t)0x0000006U) /*!< Select alternate function 6 */
-#define LL_GPIO_AF_7                       ((uint32_t)0x0000007U) /*!< Select alternate function 7 */
-#define LL_GPIO_AF_8                       ((uint32_t)0x0000008U) /*!< Select alternate function 8 */
-#define LL_GPIO_AF_9                       ((uint32_t)0x0000009U) /*!< Select alternate function 9 */
-#define LL_GPIO_AF_10                      ((uint32_t)0x000000AU) /*!< Select alternate function 10 */
-#define LL_GPIO_AF_11                      ((uint32_t)0x000000BU) /*!< Select alternate function 11 */
-#define LL_GPIO_AF_12                      ((uint32_t)0x000000CU) /*!< Select alternate function 12 */
-#define LL_GPIO_AF_13                      ((uint32_t)0x000000DU) /*!< Select alternate function 13 */
-#define LL_GPIO_AF_14                      ((uint32_t)0x000000EU) /*!< Select alternate function 14 */
-#define LL_GPIO_AF_15                      ((uint32_t)0x000000FU) /*!< Select alternate function 15 */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
 /**
   * @}
   */
@@ -574,7 +572,7 @@
   */
 __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
 {
-  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)),
+  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
              (Alternate << (POSITION_VAL(Pin) * 4U)));
 }
 
@@ -612,7 +610,7 @@
 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
 {
   return (uint32_t)(READ_BIT(GPIOx->AFR[0],
-                             (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+                             (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
 }
 
 /**
@@ -651,7 +649,7 @@
   */
 __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
 {
-  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)),
+  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
              (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
 }
 
@@ -690,7 +688,7 @@
 __STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
 {
   return (uint32_t)(READ_BIT(GPIOx->AFR[1],
-                             (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+                             (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
 }
 
 

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_i2c.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   I2C LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -69,12 +67,12 @@
                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
                                                  ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
 
-#define IS_I2C_CLOCK_SPEED(__VALUE__)           (((__VALUE__) > 0) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
+#define IS_I2C_CLOCK_SPEED(__VALUE__)           (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
 
 #define IS_I2C_DUTY_CYCLE(__VALUE__)            (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
                                                  ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
 
-#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= (uint32_t)0x000003FFU)
+#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__)       ((__VALUE__) <= 0x000003FFU)
 
 #define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__)   (((__VALUE__) == LL_I2C_ACK) || \
                                                  ((__VALUE__) == LL_I2C_NACK))

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_i2c.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_i2c.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of I2C LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -63,8 +61,6 @@
 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
   * @{
   */
-/* Defines used for the bit position in the register and perform offsets */
-#define LL_I2C_POSITION_SR2_PEC             (uint32_t)POSITION_VAL(I2C_SR2_PEC)
 
 /* Defines used to perform compute and check in the macros */
 #define LL_I2C_MAX_SPEED_STANDARD           100000U
@@ -1540,6 +1536,17 @@
 }
 
 /**
+  * @brief  Disable Reset of I2C peripheral.
+  * @rmtoll CR1          SWRST         LL_I2C_DisableReset
+  * @param  I2Cx I2C Instance.
+  * @retval None
+  */
+__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
+{
+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
+}
+
+/**
   * @brief  Check if the I2C peripheral is under reset state or not.
   * @rmtoll CR1          SWRST         LL_I2C_IsResetEnabled
   * @param  I2Cx I2C Instance.
@@ -1725,7 +1732,7 @@
   */
 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
 {
-  return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> LL_I2C_POSITION_SR2_PEC);
+  return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_iwdg.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_iwdg.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_iwdg.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of IWDG LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -64,10 +62,10 @@
   * @{
   */
 
-#define LL_IWDG_KEY_RELOAD                 ((uint32_t)0x0000AAAAU)               /*!< IWDG Reload Counter Enable   */
-#define LL_IWDG_KEY_ENABLE                 ((uint32_t)0x0000CCCCU)               /*!< IWDG Peripheral Enable       */
-#define LL_IWDG_KEY_WR_ACCESS_ENABLE       ((uint32_t)0x00005555U)               /*!< IWDG KR Write Access Enable  */
-#define LL_IWDG_KEY_WR_ACCESS_DISABLE      ((uint32_t)0x00000000U)               /*!< IWDG KR Write Access Disable */
+#define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */
+#define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */
+#define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */
+#define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */
 
 /**
   * @}
@@ -95,7 +93,7 @@
 /** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider
   * @{
   */
-#define LL_IWDG_PRESCALER_4                ((uint32_t)0x00000000U)               /*!< Divider by 4   */
+#define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */
 #define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */
 #define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */
 #define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_opamp.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_opamp.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_opamp.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   OPAMP LL module driver
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_opamp.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_opamp.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_opamp.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of OPAMP LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -70,8 +68,8 @@
 /* - OPAMP trimming register offset                                           */
 
 /* Internal register offset for OPAMP trimming configuration */
-#define OPAMP_POWERMODE_OTR_REGOFFSET       ((uint32_t)0x00000000U)
-#define OPAMP_POWERMODE_LPOTR_REGOFFSET     ((uint32_t)0x00000001U)
+#define OPAMP_POWERMODE_OTR_REGOFFSET       (0x00000000U)
+#define OPAMP_POWERMODE_LPOTR_REGOFFSET     (0x00000001U)
 #define OPAMP_POWERMODE_OTR_REGOFFSET_MASK  (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_LPOTR_REGOFFSET)
 
 /* Mask for OPAMP power mode into control register */
@@ -82,7 +80,7 @@
 /* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for:          */
 /* - OPAMP trimming selection of transistors differential pair                */
 /* - OPAMP trimming values of transistors differential pair                   */
-#define OPAMP_TRIMMING_SELECT_SW_OFFSET     ((uint32_t)16U)
+#define OPAMP_TRIMMING_SELECT_SW_OFFSET     (16U)
 #define OPAMP_TRIMMING_SELECT_MASK          ((OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA1CAL_L) << OPAMP_TRIMMING_SELECT_SW_OFFSET)
 #define OPAMP_TRIMMING_VALUE_MASK           (OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH | OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW)
 
@@ -193,7 +191,7 @@
 /** @defgroup OPAMP_LL_EC_POWERSUPPLY_RANGE OPAMP power supply range
   * @{
   */
-#define LL_OPAMP_POWERSUPPLY_RANGE_LOW  ((uint32_t)0x00000000U) /*!< Power supply range low. On STM32L1 serie: Vdda lower than 2.4V. */
+#define LL_OPAMP_POWERSUPPLY_RANGE_LOW  (0x00000000U)           /*!< Power supply range low. On STM32L1 serie: Vdda lower than 2.4V. */
 #define LL_OPAMP_POWERSUPPLY_RANGE_HIGH (OPAMP_CSR_AOP_RANGE)   /*!< Power supply range high. On STM32L1 serie: Vdda higher than 2.4V. */
 /**
   * @}
@@ -211,7 +209,7 @@
 /** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
   * @{
   */
-#define LL_OPAMP_MODE_FUNCTIONAL        ((uint32_t)0x00000000U)                                                                        /*!< OPAMP functional mode */
+#define LL_OPAMP_MODE_FUNCTIONAL        (0x00000000U)                                                                                  /*!< OPAMP functional mode */
 #define LL_OPAMP_MODE_CALIBRATION       (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | OPAMP_CSR_S7SEL2) /*!< OPAMP calibration mode (on STM32L1 serie, it corresponds to all OPAMP input internal switches opened) */
 /**
   * @}
@@ -220,7 +218,7 @@
 /** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
   * @{
   */
-#define LL_OPAMP_MODE_STANDALONE        ((uint32_t)0x00000000U) /*!< OPAMP functional mode, OPAMP operation in standalone (on STM32L1 serie, it corresponds to OPAMP internal switches S3 opened (switch SanB state depends on switch S4 state)) */
+#define LL_OPAMP_MODE_STANDALONE        (0x00000000U)           /*!< OPAMP functional mode, OPAMP operation in standalone (on STM32L1 serie, it corresponds to OPAMP internal switches S3 opened (switch SanB state depends on switch S4 state)) */
 #define LL_OPAMP_MODE_FOLLOWER          (OPAMP_CSR_S3SEL1)      /*!< OPAMP functional mode, OPAMP operation in follower (on STM32L1 serie, it corresponds to OPAMP internal switches S3 and SanB closed) */
 /**
   * @}
@@ -244,7 +242,7 @@
   */
 #define LL_OPAMP_INPUT_INVERT_IO0        (OPAMP_CSR_S4SEL1)      /*!< OPAMP inverting input connected to GPIO pin (low leakage input). Note: OPAMP inverting input is used with OPAMP in mode standalone. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
 #define LL_OPAMP_INPUT_INVERT_IO1        (OPAMP_CSR_ANAWSEL1)    /*!< OPAMP inverting input connected to GPIO pin (alternative IO pin, not low leakage, availability depends on STM32L1 serie devices packages). Note: OPAMP inverting input is used with OPAMP in mode standalone. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin). */
-#define LL_OPAMP_INPUT_INVERT_CONNECT_NO ((uint32_t)0x00000000U) /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower) */
+#define LL_OPAMP_INPUT_INVERT_CONNECT_NO (0x00000000U)           /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower) */
 /**
   * @}
   */
@@ -252,7 +250,7 @@
 /** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
   * @{
   */
-#define LL_OPAMP_TRIMMING_FACTORY       ((uint32_t)0x00000000U) /*!< OPAMP trimming factors set to factory values */
+#define LL_OPAMP_TRIMMING_FACTORY       (0x00000000U)           /*!< OPAMP trimming factors set to factory values */
 #define LL_OPAMP_TRIMMING_USER          (OPAMP_OTR_OT_USER)     /*!< OPAMP trimming factors set to user values */
 /**
   * @}
@@ -263,7 +261,7 @@
   */
 #define LL_OPAMP_TRIMMING_NMOS          (OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH | (OPAMP_CSR_OPA1CAL_H << OPAMP_TRIMMING_SELECT_SW_OFFSET)) /*!< OPAMP trimming of transistors differential pair NMOS */
 #define LL_OPAMP_TRIMMING_PMOS          (OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW  | (OPAMP_CSR_OPA1CAL_L << OPAMP_TRIMMING_SELECT_SW_OFFSET)) /*!< OPAMP trimming of transistors differential pair PMOS */
-#define LL_OPAMP_TRIMMING_NONE          ((uint32_t)0x00000000U)                                                                         /*!< OPAMP trimming unselect transistors differential pair NMOS and PMOs */
+#define LL_OPAMP_TRIMMING_NONE          (0x00000000U)                                                                                   /*!< OPAMP trimming unselect transistors differential pair NMOS and PMOs */
 /**
   * @}
   */
@@ -285,7 +283,7 @@
 /* Literal set to maximum value (refer to device datasheet,                   */
 /* parameter "tWAKEUP").                                                      */
 /* Unit: us                                                                   */
-#define LL_OPAMP_DELAY_STARTUP_US         ((uint32_t) 30U)  /*!< Delay for OPAMP startup time */
+#define LL_OPAMP_DELAY_STARTUP_US         (30U)  /*!< Delay for OPAMP startup time */
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_pwr.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_pwr.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_pwr.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   PWR LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_pwr.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_pwr.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_pwr.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of PWR LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -58,11 +56,8 @@
 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-
 /* Private constants ---------------------------------------------------------*/
-
 /* Private macros ------------------------------------------------------------*/
-
 /* Exported types ------------------------------------------------------------*/
 /* Exported constants --------------------------------------------------------*/
 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
@@ -85,17 +80,17 @@
   */
 #define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
 #define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
-#if defined (PWR_PVD_SUPPORT)
+#if defined(PWR_PVD_SUPPORT)
 #define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
-#endif
-#if defined (PWR_CSR_VREFINTRDYF)
+#endif /* PWR_PVD_SUPPORT */
+#if defined(PWR_CSR_VREFINTRDYF)
 #define LL_PWR_CSR_VREFINTRDYF             PWR_CSR_VREFINTRDYF    /*!< VREFINT ready flag */
-#endif
-#define LL_PWR_CSR_VOSF                    PWR_CSR_VOSF           /*!< Voltage scaling select flag */
+#endif /* PWR_CSR_VREFINTRDYF */
+#define LL_PWR_CSR_VOS                     PWR_CSR_VOSF           /*!< Voltage scaling select flag */
 #define LL_PWR_CSR_REGLPF                  PWR_CSR_REGLPF         /*!< Regulator low power flag */
 #define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
 #define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
-#if defined (PWR_CSR_EWUP3)
+#if defined(PWR_CSR_EWUP3)
 #define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
 #endif /* PWR_CSR_EWUP3 */
 /**
@@ -115,8 +110,8 @@
 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
   * @{
   */
-#define LL_PWR_MODE_STOP                   ((uint32_t)0x00000000U)        /*!< Enter Stop mode when the CPU enters deepsleep */
-#define LL_PWR_MODE_STANDBY                (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP                      0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
 /**
   * @}
   */
@@ -124,24 +119,23 @@
 /** @defgroup PWR_LL_EC_REGU_MODE_LP_MODES  Regulator Mode In Low Power Modes
   * @{
   */
-#define LL_PWR_REGU_LPMODES_MAIN           ((uint32_t)0x00000000U)        /*!< Voltage regulator in main mode during deepsleep/sleep/low-power run mode */
-#define LL_PWR_REGU_LPMODES_LOW_POWER      (PWR_CR_LPSDSR)                /*!< Voltage regulator in low-power mode during deepsleep/sleep/low-power run mode */
+#define LL_PWR_REGU_LPMODES_MAIN           0x00000000U        /*!< Voltage Regulator in main mode during deepsleep/sleep/low-power run mode */
+#define LL_PWR_REGU_LPMODES_LOW_POWER      (PWR_CR_LPSDSR)    /*!< Voltage Regulator in low-power mode during deepsleep/sleep/low-power run mode */
 /**
   * @}
   */
-
 #if defined(PWR_CR_LPDS)
 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
  * @{
  */
-#define LL_PWR_REGU_DSMODE_MAIN       ((uint32_t)0x00000000U)        /*!< Voltage regulator in main mode during deepsleep mode */
-#define LL_PWR_REGU_DSMODE_LOW_POWER  (PWR_CR_LPDS)                  /*!< Voltage regulator in low-power mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
 /**
- * @}
- */
+  * @}
+  */
 #endif /* PWR_CR_LPDS */
 
-#if defined (PWR_PVD_SUPPORT)
+#if defined(PWR_PVD_SUPPORT)
 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
   * @{
   */
@@ -156,14 +150,13 @@
 /**
   * @}
   */
-#endif
-
+#endif /* PWR_PVD_SUPPORT */
 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
-* @{
-*/
+  * @{
+  */
 #define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
 #define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC13 */
-#if defined (PWR_CSR_EWUP3)
+#if defined(PWR_CSR_EWUP3)
 #define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PE6 or PA2 according to device */
 #endif /* PWR_CSR_EWUP3 */
 /**
@@ -206,7 +199,6 @@
   * @}
   */
 
-
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
   * @{
@@ -215,11 +207,10 @@
 /** @defgroup PWR_LL_EF_Configuration Configuration
   * @{
   */
-
 /**
-  * @brief  Switch the regulator from main mode to low-power mode
+  * @brief  Switch the Regulator from main mode to low-power mode
   * @rmtoll CR    LPRUN       LL_PWR_EnableLowPowerRunMode
-  * @note   Remind to set the regulator to low power before enabling
+  * @note   Remind to set the Regulator to low power before enabling
   *         LowPower run mode (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER).
   * @retval None
   */
@@ -229,7 +220,7 @@
 }
 
 /**
-  * @brief  Switch the regulator from low-power mode to main mode
+  * @brief  Switch the Regulator from low-power mode to main mode
   * @rmtoll CR    LPRUN       LL_PWR_DisableLowPowerRunMode
   * @retval None
   */
@@ -239,7 +230,7 @@
 }
 
 /**
-  * @brief  Check if the regulator is in low-power mode
+  * @brief  Check if the Regulator is in low-power mode
   * @rmtoll CR    LPRUN       LL_PWR_IsEnabledLowPowerRunMode
   * @retval State of bit (1 or 0).
   */
@@ -249,7 +240,7 @@
 }
 
 /**
-  * @brief  Set voltage regulator to low-power and switch from 
+  * @brief  Set voltage Regulator to low-power and switch from 
   *         run main mode to run low-power mode.
   * @rmtoll CR    LPSDSR       LL_PWR_EnterLowPowerRunMode\n
   *         CR    LPRUN        LL_PWR_EnterLowPowerRunMode
@@ -268,7 +259,7 @@
 }
 
 /**
-  * @brief  Set voltage regulator to main and switch from 
+  * @brief  Set voltage Regulator to main and switch from 
   *         run main mode to low-power mode.
   * @rmtoll CR    LPSDSR       LL_PWR_ExitLowPowerRunMode\n
   *         CR    LPRUN        LL_PWR_ExitLowPowerRunMode
@@ -285,9 +276,8 @@
   CLEAR_BIT(PWR->CR, PWR_CR_LPRUN);   /* => LL_PWR_DisableLowPowerRunMode() */
   CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR);  /* => LL_PWR_SetRegulModeLP(LL_PWR_REGU_LPMODES_MAIN) */
 }
-
 /**
-  * @brief  Set the main internal regulator output voltage
+  * @brief  Set the main internal Regulator output voltage
   * @rmtoll CR    VOS       LL_PWR_SetRegulVoltageScaling
   * @param  VoltageScaling This parameter can be one of the following values:
   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
@@ -301,7 +291,7 @@
 }
 
 /**
-  * @brief  Get the main internal regulator output voltage
+  * @brief  Get the main internal Regulator output voltage
   * @rmtoll CR    VOS       LL_PWR_GetRegulVoltageScaling
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
@@ -344,7 +334,7 @@
 }
 
 /**
-  * @brief  Set voltage regulator mode during low power modes
+  * @brief  Set voltage Regulator mode during low power modes
   * @rmtoll CR    LPSDSR       LL_PWR_SetRegulModeLP
   * @param  RegulMode This parameter can be one of the following values:
   *         @arg @ref LL_PWR_REGU_LPMODES_MAIN
@@ -357,7 +347,7 @@
 }
 
 /**
-  * @brief  Get voltage regulator mode during low power modes
+  * @brief  Get voltage Regulator mode during low power modes
   * @rmtoll CR    LPSDSR       LL_PWR_GetRegulModeLP
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_PWR_REGU_LPMODES_MAIN
@@ -370,7 +360,7 @@
 
 #if defined(PWR_CR_LPDS)
 /**
-  * @brief  Set voltage regulator mode during deep sleep mode
+  * @brief  Set voltage Regulator mode during deep sleep mode
   * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
   * @param  RegulMode This parameter can be one of the following values:
   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
@@ -383,7 +373,7 @@
 }
 
 /**
-  * @brief  Get voltage regulator mode during deep sleep mode
+  * @brief  Get voltage Regulator mode during deep sleep mode
   * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
@@ -396,15 +386,15 @@
 #endif /* PWR_CR_LPDS */
 
 /**
-  * @brief  Set power down mode when CPU enters deepsleep
+  * @brief  Set Power Down mode when CPU enters deepsleep
   * @rmtoll CR    PDDS         LL_PWR_SetPowerMode
   * @param  PDMode This parameter can be one of the following values:
   *         @arg @ref LL_PWR_MODE_STOP
   *         @arg @ref LL_PWR_MODE_STANDBY
-  * @note   Set the regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER)  
-  *         before setting MODE_STOP. If the regulator remains in "main mode",   
+  * @note   Set the Regulator to low power (bit @ref LL_PWR_REGU_LPMODES_LOW_POWER)  
+  *         before setting MODE_STOP. If the Regulator remains in "main mode",   
   *         it consumes more power without providing any additional feature. 
-  *         In MODE_STANDBY the regulator is automatically off.
+  *         In MODE_STANDBY the Regulator is automatically off.
   * @retval None
   */
 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
@@ -413,7 +403,7 @@
 }
 
 /**
-  * @brief  Get power down mode when CPU enters deepsleep
+  * @brief  Get Power Down mode when CPU enters deepsleep
   * @rmtoll CR    PDDS         LL_PWR_GetPowerMode
   * @retval Returned value can be one of the following values:
   *         @arg @ref LL_PWR_MODE_STOP
@@ -424,7 +414,7 @@
   return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PDDS));
 }
 
-#if defined (PWR_PVD_SUPPORT)
+#if defined(PWR_PVD_SUPPORT)
 /**
   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
   * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
@@ -491,13 +481,13 @@
 {
   return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
 }
-#endif
+#endif /* PWR_PVD_SUPPORT */
 
 /**
   * @brief  Enable the WakeUp PINx functionality
   * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
-  *         CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
-  *         CSR   EWUP3       LL_PWR_EnableWakeUpPin
+  * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
@@ -514,8 +504,8 @@
 /**
   * @brief  Disable the WakeUp PINx functionality
   * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
-  *         CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
-  *         CSR   EWUP3       LL_PWR_DisableWakeUpPin
+  * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
@@ -532,8 +522,8 @@
 /**
   * @brief  Check if the WakeUp PINx functionality is enabled
   * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
-  *         CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
-  *         CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
+  * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
   * @param  WakeUpPin This parameter can be one of the following values:
   *         @arg @ref LL_PWR_WAKEUP_PIN1
   *         @arg @ref LL_PWR_WAKEUP_PIN2
@@ -609,6 +599,7 @@
   return (READ_BIT(PWR->CR, PWR_CR_FWU) == (PWR_CR_FWU));
 }
 
+
 /**
   * @}
   */
@@ -637,7 +628,7 @@
   return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
 }
 
-#if defined (PWR_PVD_SUPPORT)
+#if defined(PWR_PVD_SUPPORT)
 /**
   * @brief  Indicate whether VDD voltage is below the selected PVD threshold
   * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
@@ -647,9 +638,9 @@
 {
   return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
 }
-#endif
+#endif /* PWR_PVD_SUPPORT */
 
-#if defined (PWR_CSR_VREFINTRDYF)
+#if defined(PWR_CSR_VREFINTRDYF)
 /**
   * @brief  Get Internal Reference VrefInt Flag
   * @rmtoll CSR   VREFINTRDYF       LL_PWR_IsActiveFlag_VREFINTRDY
@@ -659,29 +650,26 @@
 {
   return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
 }
-#endif
-
+#endif /* PWR_CSR_VREFINTRDYF */
 /**
-  * @brief  Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
-  * @rmtoll CSR   VOSF       LL_PWR_IsActiveFlag_VOSF
+  * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
+  * @rmtoll CSR   VOSF       LL_PWR_IsActiveFlag_VOS
   * @retval State of bit (1 or 0).
   */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOSF(void)
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
 {
-  return (READ_BIT(PWR->CSR, PWR_CSR_VOSF) == (PWR_CSR_VOSF));
+  return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
 }
-
 /**
-  * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
+  * @brief Indicate whether the Regulator is ready in main mode or is in low-power mode
   * @rmtoll CSR   REGLPF       LL_PWR_IsActiveFlag_REGLPF
-  * @note Take care, return value "0" means the regulator is ready.  Return value "1" means the output voltage range is still changing.
+  * @note Take care, return value "0" means the Regulator is ready.  Return value "1" means the output voltage range is still changing.
   * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
 {
   return (READ_BIT(PWR->CSR, PWR_CSR_REGLPF) == (PWR_CSR_REGLPF));
 }
-
 /**
   * @brief  Clear Standby Flag
   * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
@@ -702,6 +690,9 @@
   SET_BIT(PWR->CR, PWR_CR_CWUF);
 }
 
+/**
+  * @}
+  */
 
 #if defined(USE_FULL_LL_DRIVER)
 /** @defgroup PWR_LL_EF_Init De-initialization function
@@ -713,6 +704,12 @@
   */
 #endif /* USE_FULL_LL_DRIVER */
 
+/** @defgroup PWR_LL_EF_Legacy_Functions PWR legacy functions name
+  * @{
+  */
+/* Old functions name kept for legacy purpose, to be replaced by the          */
+/* current functions name.                                                    */
+#define LL_PWR_IsActiveFlag_VOSF  LL_PWR_IsActiveFlag_VOS
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_rcc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   RCC LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -124,7 +122,7 @@
 
   /* Reset HSEBYP bit */
   LL_RCC_HSE_DisableBypass();
- 
+
   /* Reset CFGR register */
   LL_RCC_WriteReg(CFGR, 0x00000000U);
 

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rcc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_rcc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of RCC LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -58,27 +56,19 @@
 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Variables RCC Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup RCC_LL_Private_Constants RCC Private Constants
   * @{
   */
 /* Defines used for the bit position in the register and perform offsets*/
+#define RCC_POSITION_MSICAL     (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL)  /*!< field position in register RCC_ICSCR */
+#define RCC_POSITION_MSITRIM    (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM) /*!< field position in register RCC_ICSCR */
+#define RCC_POSITION_MSIRANGE   (uint32_t)POSITION_VAL(RCC_ICSCR_MSIRANGE) /*!< field position in register RCC_ICSCR */
 #define RCC_POSITION_HPRE       (uint32_t)POSITION_VAL(RCC_CFGR_HPRE)     /*!< field position in register RCC_CFGR */
 #define RCC_POSITION_PPRE1      (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1)    /*!< field position in register RCC_CFGR */
 #define RCC_POSITION_PPRE2      (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2)    /*!< field position in register RCC_CFGR */
 #define RCC_POSITION_HSICAL     (uint32_t)POSITION_VAL(RCC_ICSCR_HSICAL)     /*!< field position in register RCC_ICSCR */
 #define RCC_POSITION_HSITRIM    (uint32_t)POSITION_VAL(RCC_ICSCR_HSITRIM)    /*!< field position in register RCC_ICSCR */
-#define RCC_POSITION_MSICAL     (uint32_t)POSITION_VAL(RCC_ICSCR_MSICAL)  /*!< field position in register RCC_ICSCR */
-#define RCC_POSITION_MSITRIM    (uint32_t)POSITION_VAL(RCC_ICSCR_MSITRIM) /*!< field position in register RCC_ICSCR */
-#define RCC_POSITION_MSIRANGE   (uint32_t)POSITION_VAL(RCC_ICSCR_MSIRANGE) /*!< field position in register RCC_ICSCR */
 #define RCC_POSITION_PLLMUL     (uint32_t)POSITION_VAL(RCC_CFGR_PLLMUL)   /*!< field position in register RCC_CFGR */
 #define RCC_POSITION_PLLDIV     (uint32_t)POSITION_VAL(RCC_CFGR_PLLDIV)   /*!< field position in register RCC_CFGR */
 
@@ -129,19 +119,19 @@
   * @{
   */
 #if !defined  (HSE_VALUE)
-#define HSE_VALUE    ((uint32_t)8000000U)  /*!< Value of the HSE oscillator in Hz */
+#define HSE_VALUE    8000000U  /*!< Value of the HSE oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSI_VALUE)
-#define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the HSI oscillator in Hz */
+#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
 #endif /* HSI_VALUE */
 
 #if !defined  (LSE_VALUE)
-#define LSE_VALUE    ((uint32_t)32768U)    /*!< Value of the LSE oscillator in Hz */
+#define LSE_VALUE    32768U    /*!< Value of the LSE oscillator in Hz */
 #endif /* LSE_VALUE */
 
 #if !defined  (LSI_VALUE)
-#define LSI_VALUE    ((uint32_t)32000U)    /*!< Value of the LSI oscillator in Hz */
+#define LSI_VALUE    32000U    /*!< Value of the LSI oscillator in Hz */
 #endif /* LSI_VALUE */
 /**
   * @}
@@ -210,7 +200,7 @@
 /** @defgroup RCC_LL_EC_RTC_HSE_DIV RTC HSE Prescaler
   * @{
   */
-#define LL_RCC_RTC_HSE_DIV_2               (uint32_t)0x00000000U/*!< HSE is divided by 2 for RTC clock  */
+#define LL_RCC_RTC_HSE_DIV_2               0x00000000U          /*!< HSE is divided by 2 for RTC clock  */
 #define LL_RCC_RTC_HSE_DIV_4               RCC_CR_RTCPRE_0      /*!< HSE is divided by 4 for RTC clock  */
 #define LL_RCC_RTC_HSE_DIV_8               RCC_CR_RTCPRE_1      /*!< HSE is divided by 8 for RTC clock  */
 #define LL_RCC_RTC_HSE_DIV_16              RCC_CR_RTCPRE        /*!< HSE is divided by 16 for RTC clock */
@@ -324,8 +314,8 @@
 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
   * @{
   */
-#define LL_RCC_PERIPH_FREQUENCY_NO         (uint32_t)0x00000000U      /*!< No clock enabled for the peripheral            */
-#define LL_RCC_PERIPH_FREQUENCY_NA         (uint32_t)0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U      /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU      /*!< Frequency cannot be provided as external clock */
 /**
   * @}
   */
@@ -336,7 +326,7 @@
 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
   * @{
   */
-#define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)0x00000000U         /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
 #define LL_RCC_RTC_CLKSOURCE_LSE           RCC_CSR_RTCSEL_LSE            /*!< LSE oscillator clock used as RTC clock */
 #define LL_RCC_RTC_CLKSOURCE_LSI           RCC_CSR_RTCSEL_LSI            /*!< LSI oscillator clock used as RTC clock */
 #define LL_RCC_RTC_CLKSOURCE_HSE           RCC_CSR_RTCSEL_HSE            /*!< HSE oscillator clock divided by a programmable prescaler 
@@ -456,7 +446,7 @@
   *         @arg @ref LL_RCC_SYSCLK_DIV_512
   * @retval HCLK clock frequency (in Hz)
   */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_POSITION_HPRE])
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
 
 /**
   * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
@@ -471,7 +461,7 @@
   *         @arg @ref LL_RCC_APB1_DIV_16
   * @retval PCLK1 clock frequency (in Hz)
   */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_POSITION_PPRE1])
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
 
 /**
   * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
@@ -486,7 +476,7 @@
   *         @arg @ref LL_RCC_APB2_DIV_16
   * @retval PCLK2 clock frequency (in Hz)
   */
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_POSITION_PPRE2])
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
 
 /**
   * @brief  Helper macro to calculate the MSI frequency (in Hz)
@@ -668,7 +658,7 @@
   */
 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
 {
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_POSITION_HSICAL);
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
 }
 
 /**
@@ -682,7 +672,7 @@
   */
 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
 {
-  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_POSITION_HSITRIM);
+  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
 }
 
 /**
@@ -692,7 +682,7 @@
   */
 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
 {
-  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_POSITION_HSITRIM);
+  return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rtc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rtc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_rtc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   RTC LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -62,12 +60,12 @@
   * @{
   */
 /* Default values used for prescaler */
-#define RTC_ASYNCH_PRESC_DEFAULT     ((uint32_t) 0x0000007FU)
-#define RTC_SYNCH_PRESC_DEFAULT      ((uint32_t) 0x000000FFU)
+#define RTC_ASYNCH_PRESC_DEFAULT     0x0000007FU
+#define RTC_SYNCH_PRESC_DEFAULT      0x000000FFU
 
 /* Values used for timeout */
-#define RTC_INITMODE_TIMEOUT         ((uint32_t) 1000U) /* 1s when tick set to 1ms */
-#define RTC_SYNCHRO_TIMEOUT          ((uint32_t) 1000U) /* 1s when tick set to 1ms */
+#define RTC_INITMODE_TIMEOUT         1000U /* 1s when tick set to 1ms */
+#define RTC_SYNCHRO_TIMEOUT          1000U /* 1s when tick set to 1ms */
 /**
   * @}
   */
@@ -80,9 +78,9 @@
 #define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
                                       || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
 
-#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= (uint32_t)0x7FU)
+#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__)   ((__VALUE__) <= 0x7FU)
 
-#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= (uint32_t)0x7FFFU)
+#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__)    ((__VALUE__) <= 0x7FFFU)
 
 #define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
                                   || ((__VALUE__) == LL_RTC_FORMAT_BCD))
@@ -103,7 +101,7 @@
                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
                                    || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
 
-#define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= (uint32_t)1U) && ((__DAY__) <= (uint32_t)31U))
+#define IS_LL_RTC_DAY(__DAY__)    (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
 
 #define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
                                  || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rtc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_rtc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_rtc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of RTC LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -63,58 +61,20 @@
   * @{
   */
 /* Masks Definition */
-#define RTC_INIT_MASK                 ((uint32_t)0xFFFFFFFFU)
-#define RTC_RSF_MASK                  ((uint32_t)0xFFFFFF5FU)
+#define RTC_INIT_MASK                 (0xFFFFFFFFU)
+#define RTC_RSF_MASK                  (0xFFFFFF5FU)
 
 /* Write protection defines */
 #define RTC_WRITE_PROTECTION_DISABLE  ((uint8_t)0xFFU)
 #define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU)
 #define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U)
 
-/* Defines used for the bit position in the register and perform offsets */
-#define RTC_POSITION_TR_HT            (uint32_t)POSITION_VAL(RTC_TR_HT)
-#define RTC_POSITION_TR_HU            (uint32_t)POSITION_VAL(RTC_TR_HU)
-#define RTC_POSITION_TR_MT            (uint32_t)POSITION_VAL(RTC_TR_MNT)
-#define RTC_POSITION_TR_MU            (uint32_t)POSITION_VAL(RTC_TR_MNU)
-#define RTC_POSITION_TR_ST            (uint32_t)POSITION_VAL(RTC_TR_ST)
-#define RTC_POSITION_TR_SU            (uint32_t)POSITION_VAL(RTC_TR_SU)
-#define RTC_POSITION_DR_YT            (uint32_t)POSITION_VAL(RTC_DR_YT)
-#define RTC_POSITION_DR_YU            (uint32_t)POSITION_VAL(RTC_DR_YU)
-#define RTC_POSITION_DR_MT            (uint32_t)POSITION_VAL(RTC_DR_MT)
-#define RTC_POSITION_DR_MU            (uint32_t)POSITION_VAL(RTC_DR_MU)
-#define RTC_POSITION_DR_DT            (uint32_t)POSITION_VAL(RTC_DR_DT)
-#define RTC_POSITION_DR_DU            (uint32_t)POSITION_VAL(RTC_DR_DU)
-#define RTC_POSITION_DR_WDU           (uint32_t)POSITION_VAL(RTC_DR_WDU)
-#define RTC_POSITION_ALMA_DT          (uint32_t)POSITION_VAL(RTC_ALRMAR_DT)
-#define RTC_POSITION_ALMA_DU          (uint32_t)POSITION_VAL(RTC_ALRMAR_DU)
-#define RTC_POSITION_ALMA_HT          (uint32_t)POSITION_VAL(RTC_ALRMAR_HT)
-#define RTC_POSITION_ALMA_HU          (uint32_t)POSITION_VAL(RTC_ALRMAR_HU)
-#define RTC_POSITION_ALMA_MT          (uint32_t)POSITION_VAL(RTC_ALRMAR_MNT)
-#define RTC_POSITION_ALMA_MU          (uint32_t)POSITION_VAL(RTC_ALRMAR_MNU)
-#define RTC_POSITION_ALMA_SU          (uint32_t)POSITION_VAL(RTC_ALRMAR_SU)
-#define RTC_POSITION_ALMA_ST          (uint32_t)POSITION_VAL(RTC_ALRMAR_ST)
-#define RTC_POSITION_ALMB_DT          (uint32_t)POSITION_VAL(RTC_ALRMBR_DT)
-#define RTC_POSITION_ALMB_DU          (uint32_t)POSITION_VAL(RTC_ALRMBR_DU)
-#define RTC_POSITION_ALMB_HT          (uint32_t)POSITION_VAL(RTC_ALRMBR_HT)
-#define RTC_POSITION_ALMB_HU          (uint32_t)POSITION_VAL(RTC_ALRMBR_HU)
-#define RTC_POSITION_ALMB_MT          (uint32_t)POSITION_VAL(RTC_ALRMBR_MNT)
-#define RTC_POSITION_ALMB_MU          (uint32_t)POSITION_VAL(RTC_ALRMBR_MNU)
-#define RTC_POSITION_ALMB_SU          (uint32_t)POSITION_VAL(RTC_ALRMBR_SU)
-#define RTC_POSITION_ALMB_ST          (uint32_t)POSITION_VAL(RTC_ALRMBR_ST)
-#define RTC_POSITION_PRER_PREDIV_A    (uint32_t)POSITION_VAL(RTC_PRER_PREDIV_A)
-#define RTC_POSITION_ALMA_MASKSS      (uint32_t)POSITION_VAL(RTC_ALRMASSR_MASKSS)
-#define RTC_POSITION_ALMB_MASKSS      (uint32_t)POSITION_VAL(RTC_ALRMBSSR_MASKSS)
-#define RTC_POSITION_TS_HU            (uint32_t)POSITION_VAL(RTC_TSTR_HU)
-#define RTC_POSITION_TS_MNU           (uint32_t)POSITION_VAL(RTC_TSTR_MNU)
-#define RTC_POSITION_TS_WDU           (uint32_t)POSITION_VAL(RTC_TSDR_WDU)
-#define RTC_POSITION_TS_MU            (uint32_t)POSITION_VAL(RTC_TSDR_MU)
-
 /* Defines used to combine date & time */
-#define RTC_OFFSET_WEEKDAY            (uint32_t)24U
-#define RTC_OFFSET_DAY                (uint32_t)16U
-#define RTC_OFFSET_MONTH              (uint32_t)8U
-#define RTC_OFFSET_HOUR               (uint32_t)16U
-#define RTC_OFFSET_MINUTE             (uint32_t)8U
+#define RTC_OFFSET_WEEKDAY            24U
+#define RTC_OFFSET_DAY                16U
+#define RTC_OFFSET_MONTH              8U
+#define RTC_OFFSET_HOUR               16U
+#define RTC_OFFSET_MINUTE             8U
 
 /**
   * @}
@@ -261,8 +221,8 @@
 /** @defgroup RTC_LL_EC_FORMAT FORMAT
   * @{
   */
-#define LL_RTC_FORMAT_BIN                  ((uint32_t)0x000000000U) /*!< Binary data format */
-#define LL_RTC_FORMAT_BCD                  ((uint32_t)0x000000001U) /*!< BCD data format */
+#define LL_RTC_FORMAT_BIN                  0x000000000U /*!< Binary data format */
+#define LL_RTC_FORMAT_BCD                  0x000000001U /*!< BCD data format */
 /**
   * @}
   */
@@ -270,7 +230,7 @@
 /** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
   * @{
   */
-#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    ((uint32_t)0x00000000U) /*!< Alarm A Date is selected */
+#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */
 #define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */
 /**
   * @}
@@ -279,7 +239,7 @@
 /** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
   * @{
   */
-#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    ((uint32_t)0x00000000U) /*!< Alarm B Date is selected */
+#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm B Date is selected */
 #define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */
 /**
   * @}
@@ -362,7 +322,7 @@
 /** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT
   * @{
   */
-#define LL_RTC_HOURFORMAT_24HOUR           (uint32_t)0x00000000U /*!< 24 hour/day format */
+#define LL_RTC_HOURFORMAT_24HOUR           0x00000000U           /*!< 24 hour/day format */
 #define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */
 /**
   * @}
@@ -371,7 +331,7 @@
 /** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT
   * @{
   */
-#define LL_RTC_ALARMOUT_DISABLE            ((uint32_t)0x00000000U) /*!< Output disabled */
+#define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */
 #define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */
 #define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */
 #define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */
@@ -382,7 +342,7 @@
 /** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE
   * @{
   */
-#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  (uint32_t)0x00000000U  /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  0x00000000U                          /*!< RTC_ALARM, when mapped on PC13, is open-drain output */
 #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_TAFCR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */
 /**
   * @}
@@ -391,7 +351,7 @@
 /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN
   * @{
   */
-#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     (uint32_t)0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
+#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
 #define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
 /**
   * @}
@@ -400,7 +360,7 @@
 /** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
   * @{
   */
-#define LL_RTC_TIME_FORMAT_AM_OR_24        (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */
 #define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */
 /**
   * @}
@@ -410,7 +370,7 @@
 /** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND
   * @{
   */
-#define LL_RTC_SHIFT_SECOND_DELAY          (uint32_t)0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
+#define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
 #define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
 /**
   * @}
@@ -420,7 +380,7 @@
 /** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK
   * @{
   */
-#define LL_RTC_ALMA_MASK_NONE              ((uint32_t)0x00000000U) /*!< No masks applied on Alarm A*/
+#define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/
 #define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */
 #define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */
 #define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */
@@ -433,7 +393,7 @@
 /** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT
   * @{
   */
-#define LL_RTC_ALMA_TIME_FORMAT_AM         (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
 #define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */
 /**
   * @}
@@ -442,7 +402,7 @@
 /** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK
   * @{
   */
-#define LL_RTC_ALMB_MASK_NONE              ((uint32_t)0x00000000U) /*!< No masks applied on Alarm B*/
+#define LL_RTC_ALMB_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm B*/
 #define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */
 #define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */
 #define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */
@@ -455,7 +415,7 @@
 /** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT
   * @{
   */
-#define LL_RTC_ALMB_TIME_FORMAT_AM         (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_ALMB_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */
 #define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */
 /**
   * @}
@@ -464,7 +424,7 @@
 /** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE
   * @{
   */
-#define LL_RTC_TIMESTAMP_EDGE_RISING       (uint32_t)0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
+#define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */
 #define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */
 /**
   * @}
@@ -473,7 +433,7 @@
 /** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT
   * @{
   */
-#define LL_RTC_TS_TIME_FORMAT_AM           (uint32_t)0x00000000U /*!< AM or 24-hour format */
+#define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */
 #define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */
 /**
   * @}
@@ -531,7 +491,7 @@
 /** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION
   * @{
   */
-#define LL_RTC_TAMPER_DURATION_1RTCCLK     ((uint32_t)0x00000000U) /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
+#define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U                             /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */
 #define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAFCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
 #define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAFCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
 #define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAFCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
@@ -544,7 +504,7 @@
 /** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER
   * @{
   */
-#define LL_RTC_TAMPER_FILTER_DISABLE       ((uint32_t)0x00000000U)  /*!< Tamper filter is disabled */
+#define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U                              /*!< Tamper filter is disabled */
 #define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAFCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */
 #define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAFCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */
 #define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAFCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */
@@ -557,7 +517,7 @@
 /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER
   * @{
   */
-#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   ((uint32_t)0x00000000U)                          /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                                      /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */
 #define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAFCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */
 #define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAFCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */
 #define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */
@@ -589,7 +549,7 @@
 /** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV
   * @{
   */
-#define LL_RTC_WAKEUPCLOCK_DIV_16          ((uint32_t)0x00000000U)               /*!< RTC/16 clock is selected */
+#define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */
 #define LL_RTC_WAKEUPCLOCK_DIV_8           (RTC_CR_WUCKSEL_0)                    /*!< RTC/8 clock is selected */
 #define LL_RTC_WAKEUPCLOCK_DIV_4           (RTC_CR_WUCKSEL_1)                    /*!< RTC/4 clock is selected */
 #define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
@@ -603,45 +563,45 @@
 /** @defgroup RTC_LL_EC_BKP  BACKUP
   * @{
   */
-#define LL_RTC_BKP_DR0                     ((uint32_t)0x00000000U)
-#define LL_RTC_BKP_DR1                     ((uint32_t)0x00000001U)
-#define LL_RTC_BKP_DR2                     ((uint32_t)0x00000002U)
-#define LL_RTC_BKP_DR3                     ((uint32_t)0x00000003U)
-#define LL_RTC_BKP_DR4                     ((uint32_t)0x00000004U)
+#define LL_RTC_BKP_DR0                     0x00000000U
+#define LL_RTC_BKP_DR1                     0x00000001U
+#define LL_RTC_BKP_DR2                     0x00000002U
+#define LL_RTC_BKP_DR3                     0x00000003U
+#define LL_RTC_BKP_DR4                     0x00000004U
 #if RTC_BKP_NUMBER > 5
-#define LL_RTC_BKP_DR5                     ((uint32_t)0x00000005U)
-#define LL_RTC_BKP_DR6                     ((uint32_t)0x00000006U)
-#define LL_RTC_BKP_DR7                     ((uint32_t)0x00000007U)
-#define LL_RTC_BKP_DR8                     ((uint32_t)0x00000008U)
-#define LL_RTC_BKP_DR9                     ((uint32_t)0x00000009U)
-#define LL_RTC_BKP_DR10                    ((uint32_t)0x0000000AU)
-#define LL_RTC_BKP_DR11                    ((uint32_t)0x0000000BU)
-#define LL_RTC_BKP_DR12                    ((uint32_t)0x0000000CU)
-#define LL_RTC_BKP_DR13                    ((uint32_t)0x0000000DU)
-#define LL_RTC_BKP_DR14                    ((uint32_t)0x0000000EU)
-#define LL_RTC_BKP_DR15                    ((uint32_t)0x0000000FU)
+#define LL_RTC_BKP_DR5                     0x00000005U
+#define LL_RTC_BKP_DR6                     0x00000006U
+#define LL_RTC_BKP_DR7                     0x00000007U
+#define LL_RTC_BKP_DR8                     0x00000008U
+#define LL_RTC_BKP_DR9                     0x00000009U
+#define LL_RTC_BKP_DR10                    0x0000000AU
+#define LL_RTC_BKP_DR11                    0x0000000BU
+#define LL_RTC_BKP_DR12                    0x0000000CU
+#define LL_RTC_BKP_DR13                    0x0000000DU
+#define LL_RTC_BKP_DR14                    0x0000000EU
+#define LL_RTC_BKP_DR15                    0x0000000FU
 #endif /* RTC_BKP_NUMBER > 5 */
 
 #if RTC_BKP_NUMBER > 16
-#define LL_RTC_BKP_DR16                    ((uint32_t)0x00000010U)
-#define LL_RTC_BKP_DR17                    ((uint32_t)0x00000011U)
-#define LL_RTC_BKP_DR18                    ((uint32_t)0x00000012U)
-#define LL_RTC_BKP_DR19                    ((uint32_t)0x00000013U)
+#define LL_RTC_BKP_DR16                    0x00000010U
+#define LL_RTC_BKP_DR17                    0x00000011U
+#define LL_RTC_BKP_DR18                    0x00000012U
+#define LL_RTC_BKP_DR19                    0x00000013U
 #endif /* RTC_BKP_NUMBER > 16 */
 
 #if RTC_BKP_NUMBER > 20
-#define LL_RTC_BKP_DR20                    ((uint32_t)0x00000014U)
-#define LL_RTC_BKP_DR21                    ((uint32_t)0x00000015U)
-#define LL_RTC_BKP_DR22                    ((uint32_t)0x00000016U)
-#define LL_RTC_BKP_DR23                    ((uint32_t)0x00000017U)
-#define LL_RTC_BKP_DR24                    ((uint32_t)0x00000018U)
-#define LL_RTC_BKP_DR25                    ((uint32_t)0x00000019U)
-#define LL_RTC_BKP_DR26                    ((uint32_t)0x0000001AU)
-#define LL_RTC_BKP_DR27                    ((uint32_t)0x0000001BU)
-#define LL_RTC_BKP_DR28                    ((uint32_t)0x0000001CU)
-#define LL_RTC_BKP_DR29                    ((uint32_t)0x0000001DU)
-#define LL_RTC_BKP_DR30                    ((uint32_t)0x0000001EU)
-#define LL_RTC_BKP_DR31                    ((uint32_t)0x0000001FU)
+#define LL_RTC_BKP_DR20                    0x00000014U
+#define LL_RTC_BKP_DR21                    0x00000015U
+#define LL_RTC_BKP_DR22                    0x00000016U
+#define LL_RTC_BKP_DR23                    0x00000017U
+#define LL_RTC_BKP_DR24                    0x00000018U
+#define LL_RTC_BKP_DR25                    0x00000019U
+#define LL_RTC_BKP_DR26                    0x0000001AU
+#define LL_RTC_BKP_DR27                    0x0000001BU
+#define LL_RTC_BKP_DR28                    0x0000001CU
+#define LL_RTC_BKP_DR29                    0x0000001DU
+#define LL_RTC_BKP_DR30                    0x0000001EU
+#define LL_RTC_BKP_DR31                    0x0000001FU
 #endif /* RTC_BKP_NUMBER > 20 */
 /**
   * @}
@@ -651,11 +611,11 @@
 /** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output
   * @{
   */
-#define LL_RTC_CALIB_OUTPUT_NONE           (uint32_t)0x00000000U       /*!< Calibration output disabled */
+#define LL_RTC_CALIB_OUTPUT_NONE           0x00000000U                 /*!< Calibration output disabled */
 #if defined(RTC_CR_COSEL)
-#define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 512 Hz */
+#define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
 #endif
-#define LL_RTC_CALIB_OUTPUT_512HZ          (RTC_CR_COE)                /*!< Calibration output is 1 Hz */
+#define LL_RTC_CALIB_OUTPUT_512HZ          (RTC_CR_COE)                /*!< Calibration output is 512 Hz */
 /**
   * @}
   */
@@ -663,7 +623,7 @@
 /** @defgroup RTC_LL_EC_CALIB_SIGN Coarse digital calibration sign
   * @{
   */
-#define LL_RTC_CALIB_SIGN_POSITIVE         (uint32_t)0x00000000U /*!< Positive calibration: calendar update frequency is increased */
+#define LL_RTC_CALIB_SIGN_POSITIVE         0x00000000U           /*!< Positive calibration: calendar update frequency is increased */
 #define LL_RTC_CALIB_SIGN_NEGATIVE         RTC_CALIBR_DCS        /*!< Negative calibration: calendar update frequency is decreased */
 /**
   * @}
@@ -672,7 +632,7 @@
 /** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion 
   * @{
   */
-#define LL_RTC_CALIB_INSERTPULSE_NONE      (uint32_t)0x00000000U /*!< No RTCCLK pulses are added */
+#define LL_RTC_CALIB_INSERTPULSE_NONE      0x00000000U           /*!< No RTCCLK pulses are added */
 #define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
 /**
   * @}
@@ -681,7 +641,7 @@
 /** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period
   * @{
   */
-#define LL_RTC_CALIB_PERIOD_32SEC          (uint32_t)0x00000000U /*!< Use a 32-second calibration cycle period */
+#define LL_RTC_CALIB_PERIOD_32SEC          0x00000000U           /*!< Use a 32-second calibration cycle period */
 #define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */
 #define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */
 /**
@@ -1056,7 +1016,7 @@
   */
 __STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
 {
-  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_POSITION_PRER_PREDIV_A);
+  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
 }
 
 /**
@@ -1079,7 +1039,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_POSITION_PRER_PREDIV_A);
+  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
 }
 
 /**
@@ -1171,7 +1131,7 @@
 __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
 {
   MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
-             (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU)));
+             (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
 }
 
 /**
@@ -1192,7 +1152,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU));
-  return (uint32_t)((((temp & RTC_TR_HT) >> RTC_POSITION_TR_HT) << 4U) | ((temp & RTC_TR_HU) >> RTC_POSITION_TR_HU));
+  return (uint32_t)((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos));
 }
 
 /**
@@ -1209,7 +1169,7 @@
 __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
 {
   MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
-             (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)));
+             (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
 }
 
 /**
@@ -1230,7 +1190,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU));
-  return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_POSITION_TR_MT) << 4U) | ((temp & RTC_TR_MNU) >> RTC_POSITION_TR_MU));
+  return (uint32_t)((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos));
 }
 
 /**
@@ -1247,7 +1207,7 @@
 __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
 {
   MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
-             (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU)));
+             (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
 }
 
 /**
@@ -1268,7 +1228,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU));
-  return (uint32_t)((((temp & RTC_TR_ST) >> RTC_POSITION_TR_ST) << 4U) | ((temp & RTC_TR_SU) >> RTC_POSITION_TR_SU));
+  return (uint32_t)((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos));
 }
 
 /**
@@ -1297,9 +1257,9 @@
   register uint32_t temp = 0U;
 
   temp = Format12_24                                                                                    | \
-         (((Hours & 0xF0U) << (RTC_POSITION_TR_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_TR_HU))     | \
-         (((Minutes & 0xF0U) << (RTC_POSITION_TR_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_TR_MU)) | \
-         (((Seconds & 0xF0U) << (RTC_POSITION_TR_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_TR_SU));
+         (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \
+         (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
   MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
 }
 
@@ -1328,36 +1288,36 @@
 /**
   * @brief  Memorize whether the daylight saving time change has been performed
   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           BCK           LL_RTC_TIME_EnableDayLightStore
+  * @rmtoll CR           BKP           LL_RTC_TIME_EnableDayLightStore
   * @param  RTCx RTC Instance
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
 {
-  SET_BIT(RTCx->CR, RTC_CR_BCK);
+  SET_BIT(RTCx->CR, RTC_CR_BKP);
 }
 
 /**
   * @brief  Disable memorization whether the daylight saving time change has been performed.
   * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
-  * @rmtoll CR           BCK           LL_RTC_TIME_DisableDayLightStore
+  * @rmtoll CR           BKP           LL_RTC_TIME_DisableDayLightStore
   * @param  RTCx RTC Instance
   * @retval None
   */
 __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
 {
-  CLEAR_BIT(RTCx->CR, RTC_CR_BCK);
+  CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
 }
 
 /**
   * @brief  Check if RTC Day Light Saving stored operation has been enabled or not
-  * @rmtoll CR           BCK           LL_RTC_TIME_IsDayLightStoreEnabled
+  * @rmtoll CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled
   * @param  RTCx RTC Instance
   * @retval State of bit (1 or 0).
   */
 __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
 {
-  return (READ_BIT(RTCx->CR, RTC_CR_BCK) == (RTC_CR_BCK));
+  return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP));
 }
 
 /**
@@ -1445,7 +1405,7 @@
 __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
 {
   MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
-             (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU)));
+             (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
 }
 
 /**
@@ -1463,7 +1423,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU));
-  return (uint32_t)((((temp & RTC_DR_YT) >> RTC_POSITION_DR_YT) << 4U) | ((temp & RTC_DR_YU) >> RTC_POSITION_DR_YU));
+  return (uint32_t)((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos));
 }
 
 /**
@@ -1482,7 +1442,7 @@
   */
 __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
 {
-  MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_POSITION_DR_WDU);
+  MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
 }
 
 /**
@@ -1502,7 +1462,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_POSITION_DR_WDU);
+  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
 }
 
 /**
@@ -1529,7 +1489,7 @@
 __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
 {
   MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
-             (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)));
+             (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
 }
 
 /**
@@ -1559,7 +1519,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU));
-  return (uint32_t)((((temp & RTC_DR_MT) >> RTC_POSITION_DR_MT) << 4U) | ((temp & RTC_DR_MU) >> RTC_POSITION_DR_MU));
+  return (uint32_t)((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos));
 }
 
 /**
@@ -1574,7 +1534,7 @@
 __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
 {
   MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
-             (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU)));
+             (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
 }
 
 /**
@@ -1592,7 +1552,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU));
-  return (uint32_t)((((temp & RTC_DR_DT) >> RTC_POSITION_DR_DT) << 4U) | ((temp & RTC_DR_DU) >> RTC_POSITION_DR_DU));
+  return (uint32_t)((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos));
 }
 
 /**
@@ -1634,10 +1594,10 @@
 {
   register uint32_t temp = 0U;
 
-  temp = (WeekDay << RTC_POSITION_DR_WDU)                                                        | \
-         (((Year & 0xF0U) << (RTC_POSITION_DR_YT - 4U)) | ((Year & 0x0FU) << RTC_POSITION_DR_YU))   | \
-         (((Month & 0xF0U) << (RTC_POSITION_DR_MT - 4U)) | ((Month & 0x0FU) << RTC_POSITION_DR_MU)) | \
-         (((Day & 0xF0U) << (RTC_POSITION_DR_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_DR_DU));
+  temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \
+         (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \
+         (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
+         (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
 
   MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
 }
@@ -1770,7 +1730,7 @@
 __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
 {
   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
-             (((Day & 0xF0U) << (RTC_POSITION_ALMA_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMA_DU)));
+             (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
 }
 
 /**
@@ -1786,7 +1746,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU));
-  return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_POSITION_ALMA_DT) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU));
+  return (uint32_t)((((temp & RTC_ALRMAR_DT) >> RTC_ALRMAR_DT_Pos) << 4U) | ((temp & RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos));
 }
 
 /**
@@ -1805,7 +1765,7 @@
   */
 __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
 {
-  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_POSITION_ALMA_DU);
+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
 }
 
 /**
@@ -1823,7 +1783,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_POSITION_ALMA_DU);
+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
 }
 
 /**
@@ -1865,7 +1825,7 @@
 __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
 {
   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
-             (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU)));
+             (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
 }
 
 /**
@@ -1881,7 +1841,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU));
-  return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_POSITION_ALMA_HT) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_POSITION_ALMA_HU));
+  return (uint32_t)((((temp & RTC_ALRMAR_HT) >> RTC_ALRMAR_HT_Pos) << 4U) | ((temp & RTC_ALRMAR_HU) >> RTC_ALRMAR_HU_Pos));
 }
 
 /**
@@ -1896,7 +1856,7 @@
 __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
 {
   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
-             (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)));
+             (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
 }
 
 /**
@@ -1912,7 +1872,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU));
-  return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_POSITION_ALMA_MT) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_POSITION_ALMA_MU));
+  return (uint32_t)((((temp & RTC_ALRMAR_MNT) >> RTC_ALRMAR_MNT_Pos) << 4U) | ((temp & RTC_ALRMAR_MNU) >> RTC_ALRMAR_MNU_Pos));
 }
 
 /**
@@ -1927,7 +1887,7 @@
 __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
 {
   MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
-             (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU)));
+             (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
 }
 
 /**
@@ -1943,7 +1903,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
-  return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_POSITION_ALMA_ST) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_POSITION_ALMA_SU));
+  return (uint32_t)((((temp & RTC_ALRMAR_ST) >> RTC_ALRMAR_ST_Pos) << 4U) | ((temp & RTC_ALRMAR_SU) >> RTC_ALRMAR_SU_Pos));
 }
 
 /**
@@ -1968,9 +1928,9 @@
 {
   register uint32_t temp = 0U;
 
-  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMA_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMA_HU))    | \
-         (((Minutes & 0xF0U) << (RTC_POSITION_ALMA_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMA_MU)) | \
-         (((Seconds & 0xF0U) << (RTC_POSITION_ALMA_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMA_SU));
+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \
+         (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
 
   MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);
 }
@@ -2005,7 +1965,7 @@
   */
 __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
 {
-  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_POSITION_ALMA_MASKSS);
+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
 }
 
 /**
@@ -2016,7 +1976,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_POSITION_ALMA_MASKSS);
+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
 }
 
 /**
@@ -2150,7 +2110,7 @@
 __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
 {
   MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
-             (((Day & 0xF0U) << (RTC_POSITION_ALMB_DT - 4U)) | ((Day & 0x0FU) << RTC_POSITION_ALMB_DU)));
+             (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
 }
 
 /**
@@ -2166,7 +2126,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU));
-  return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_POSITION_ALMB_DT) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_POSITION_ALMB_DU));
+  return (uint32_t)((((temp & RTC_ALRMBR_DT) >> RTC_ALRMBR_DT_Pos) << 4U) | ((temp & RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos));
 }
 
 /**
@@ -2185,7 +2145,7 @@
   */
 __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
 {
-  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_POSITION_ALMB_DU);
+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
 }
 
 /**
@@ -2203,7 +2163,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_POSITION_ALMB_DU);
+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
 }
 
 /**
@@ -2245,7 +2205,7 @@
 __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
 {
   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
-             (((Hours & 0xF0U) << (RTC_POSITION_ALMB_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMB_HU)));
+             (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
 }
 
 /**
@@ -2261,7 +2221,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU));
-  return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_POSITION_ALMB_HT) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_POSITION_ALMB_HU));
+  return (uint32_t)((((temp & RTC_ALRMBR_HT) >> RTC_ALRMBR_HT_Pos) << 4U) | ((temp & RTC_ALRMBR_HU) >> RTC_ALRMBR_HU_Pos));
 }
 
 /**
@@ -2276,7 +2236,7 @@
 __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
 {
   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
-             (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMB_MU)));
+             (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
 }
 
 /**
@@ -2292,7 +2252,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU));
-  return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_POSITION_ALMB_MT) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_POSITION_ALMB_MU));
+  return (uint32_t)((((temp & RTC_ALRMBR_MNT) >> RTC_ALRMBR_MNT_Pos) << 4U) | ((temp & RTC_ALRMBR_MNU) >> RTC_ALRMBR_MNU_Pos));
 }
 
 /**
@@ -2307,7 +2267,7 @@
 __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
 {
   MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
-             (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMB_SU)));
+             (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
 }
 
 /**
@@ -2323,7 +2283,7 @@
   register uint32_t temp = 0U;
 
   temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU));
-  return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_POSITION_ALMB_ST) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_POSITION_ALMB_SU));
+  return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos));
 }
 
 /**
@@ -2348,9 +2308,9 @@
 {
   register uint32_t temp = 0U;
 
-  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_POSITION_ALMB_HT - 4U)) | ((Hours & 0x0FU) << RTC_POSITION_ALMB_HU))    | \
-         (((Minutes & 0xF0U) << (RTC_POSITION_ALMB_MT - 4U)) | ((Minutes & 0x0FU) << RTC_POSITION_ALMB_MU)) | \
-         (((Seconds & 0xF0U) << (RTC_POSITION_ALMB_ST - 4U)) | ((Seconds & 0x0FU) << RTC_POSITION_ALMB_SU));
+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \
+         (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
+         (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
 
   MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);
 }
@@ -2385,7 +2345,7 @@
   */
 __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
 {
-  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_POSITION_ALMB_MASKSS);
+  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
 }
 
 /**
@@ -2396,7 +2356,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_POSITION_ALMB_MASKSS);
+  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);
 }
 
 /**
@@ -2508,7 +2468,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_POSITION_TS_HU);
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
 }
 
 /**
@@ -2521,7 +2481,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_POSITION_TS_MNU);
+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
 }
 
 /**
@@ -2571,7 +2531,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_POSITION_TS_WDU);
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
 }
 
 /**
@@ -2596,7 +2556,7 @@
   */
 __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
 {
-  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_POSITION_TS_MU);
+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_sdmmc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_sdmmc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_sdmmc.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   SDMMC Low Layer HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -137,7 +135,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -323,7 +321,7 @@
 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
 {
   /* Set power state to OFF */
-  SDIOx->POWER = (uint32_t)0x00000000;
+  SDIOx->POWER = 0x00000000U;
   
   return HAL_OK;
 }

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_sdmmc.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_sdmmc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_sdmmc.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of SDMMC HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -151,7 +149,7 @@
 /** @defgroup SDIO_Clock_Edge Clock Edge
   * @{
   */
-#define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
+#define SDIO_CLOCK_EDGE_RISING               (0x00000000U)
 #define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
 
 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
@@ -163,7 +161,7 @@
 /** @defgroup SDIO_Clock_Bypass Clock Bypass
   * @{
   */
-#define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
+#define SDIO_CLOCK_BYPASS_DISABLE             (0x00000000U)
 #define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS   
 
 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
@@ -175,7 +173,7 @@
 /** @defgroup SDIO_Clock_Power_Save Clock Power Saving
   * @{
   */
-#define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
+#define SDIO_CLOCK_POWER_SAVE_DISABLE         (0x00000000U)
 #define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
 
 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
@@ -187,7 +185,7 @@
 /** @defgroup SDIO_Bus_Wide Bus Width
   * @{
   */
-#define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000)
+#define SDIO_BUS_WIDE_1B                      (0x00000000U)
 #define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
 #define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
 
@@ -201,7 +199,7 @@
 /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
   * @{
   */
-#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
+#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    (0x00000000U)
 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
 
 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
@@ -229,7 +227,7 @@
 /** @defgroup SDIO_Response_Type Response Type
   * @{
   */
-#define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000)
+#define SDIO_RESPONSE_NO                    (0x00000000U)
 #define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
 #define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
 
@@ -243,7 +241,7 @@
 /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
   * @{
   */
-#define SDIO_WAIT_NO                        ((uint32_t)0x00000000)
+#define SDIO_WAIT_NO                        (0x00000000U)
 #define SDIO_WAIT_IT                        SDIO_CMD_WAITINT 
 #define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
 
@@ -257,7 +255,7 @@
 /** @defgroup SDIO_CPSM_State CPSM State
   * @{
   */
-#define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000)
+#define SDIO_CPSM_DISABLE                   (0x00000000U)
 #define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
 
 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
@@ -269,10 +267,10 @@
 /** @defgroup SDIO_Response_Registers Response Register
   * @{
   */
-#define SDIO_RESP1                          ((uint32_t)0x00000000)
-#define SDIO_RESP2                          ((uint32_t)0x00000004)
-#define SDIO_RESP3                          ((uint32_t)0x00000008)
-#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+#define SDIO_RESP1                          (0x00000000U)
+#define SDIO_RESP2                          (0x00000004U)
+#define SDIO_RESP3                          (0x00000008U)
+#define SDIO_RESP4                          (0x0000000CU)
 
 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
                             ((RESP) == SDIO_RESP2) || \
@@ -293,21 +291,21 @@
 /** @defgroup SDIO_Data_Block_Size Data Block Size
   * @{
   */
-#define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
+#define SDIO_DATABLOCK_SIZE_1B               (0x00000000U)
 #define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
 #define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
-#define SDIO_DATABLOCK_SIZE_8B               ((uint32_t)0x00000030)
+#define SDIO_DATABLOCK_SIZE_8B               (0x00000030U)
 #define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
-#define SDIO_DATABLOCK_SIZE_32B              ((uint32_t)0x00000050)
-#define SDIO_DATABLOCK_SIZE_64B              ((uint32_t)0x00000060)
-#define SDIO_DATABLOCK_SIZE_128B             ((uint32_t)0x00000070)
+#define SDIO_DATABLOCK_SIZE_32B              (0x00000050U)
+#define SDIO_DATABLOCK_SIZE_64B              (0x00000060U)
+#define SDIO_DATABLOCK_SIZE_128B             (0x00000070U)
 #define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
-#define SDIO_DATABLOCK_SIZE_512B             ((uint32_t)0x00000090)
-#define SDIO_DATABLOCK_SIZE_1024B            ((uint32_t)0x000000A0)
-#define SDIO_DATABLOCK_SIZE_2048B            ((uint32_t)0x000000B0)
-#define SDIO_DATABLOCK_SIZE_4096B            ((uint32_t)0x000000C0)
-#define SDIO_DATABLOCK_SIZE_8192B            ((uint32_t)0x000000D0)
-#define SDIO_DATABLOCK_SIZE_16384B           ((uint32_t)0x000000E0)
+#define SDIO_DATABLOCK_SIZE_512B             (0x00000090U)
+#define SDIO_DATABLOCK_SIZE_1024B            (0x000000A0U)
+#define SDIO_DATABLOCK_SIZE_2048B            (0x000000B0U)
+#define SDIO_DATABLOCK_SIZE_4096B            (0x000000C0U)
+#define SDIO_DATABLOCK_SIZE_8192B            (0x000000D0U)
+#define SDIO_DATABLOCK_SIZE_16384B           (0x000000E0U)
 
 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
                                   ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
@@ -331,7 +329,7 @@
 /** @defgroup SDIO_Transfer_Direction Transfer Direction
   * @{
   */
-#define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_DIR_TO_CARD            (0x00000000U)
 #define SDIO_TRANSFER_DIR_TO_SDIO            SDIO_DCTRL_DTDIR
 
 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
@@ -343,7 +341,7 @@
 /** @defgroup SDIO_Transfer_Type Transfer Type
   * @{
   */
-#define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
+#define SDIO_TRANSFER_MODE_BLOCK             (0x00000000U)
 #define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
 
 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
@@ -355,7 +353,7 @@
 /** @defgroup SDIO_DPSM_State DPSM State
   * @{
   */
-#define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_DISABLE                    (0x00000000U)
 #define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
 
 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
@@ -367,8 +365,8 @@
 /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
   * @{
   */
-#define SDIO_READ_WAIT_MODE_DATA2             ((uint32_t)0x00000000)
-#define SDIO_READ_WAIT_MODE_CLK               ((uint32_t)0x00000001)
+#define SDIO_READ_WAIT_MODE_DATA2             (0x00000000U)
+#define SDIO_READ_WAIT_MODE_CLK               (0x00000001U)
 
 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
                                      ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
@@ -811,13 +809,13 @@
   * @brief  Enable the CE-ATA interrupt.
   * @retval None
   */    
-#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
+#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = 0U)
 
 /**
   * @brief  Disable the CE-ATA interrupt.
   * @retval None
   */  
-#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
+#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = 1U)
 
 /**
   * @brief  Enable send CE-ATA command (CMD61).

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_spi.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_spi.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_spi.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   SPI LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -422,22 +420,15 @@
      * - AudioFreq:     SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
      */
 
-    /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
-    if (I2S_InitStruct->AudioFreq == LL_I2S_AUDIOFREQ_DEFAULT)
+    /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
+     * else, default values are used:  i2sodd = 0U, i2sdiv = 2U.
+     */
+    if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
     {
-      i2sodd = 0U;
-      i2sdiv = 2U;
-    }
-    /* If the requested audio frequency is not the default, compute the prescaler */
-    else
-    {
-      /* Check the frame length (For the Prescaler computing) */
-      if (I2S_InitStruct->DataFormat == LL_I2S_DATAFORMAT_16B)
-      {
-        /* Packet length is 16 bits */
-        packetlength = 1U;
-      }
-      else
+      /* Check the frame length (For the Prescaler computing)
+       * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
+       */
+      if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
       {
         /* Packet length is 32 bits */
         packetlength = 2U;

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_spi.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_spi.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_spi.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of SPI LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -141,7 +139,6 @@
 #define LL_SPI_SR_RXNE                     SPI_SR_RXNE               /*!< Rx buffer not empty flag         */
 #define LL_SPI_SR_TXE                      SPI_SR_TXE                /*!< Tx buffer empty flag             */
 #define LL_SPI_SR_BSY                      SPI_SR_BSY                /*!< Busy flag                        */
-#define LL_SPI_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
 #define LL_SPI_SR_CRCERR                   SPI_SR_CRCERR             /*!< CRC error flag                   */
 #define LL_SPI_SR_MODF                     SPI_SR_MODF               /*!< Mode fault flag                  */
 #define LL_SPI_SR_OVR                      SPI_SR_OVR                /*!< Overrun flag                     */
@@ -165,7 +162,7 @@
   * @{
   */
 #define LL_SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)    /*!< Master configuration  */
-#define LL_SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)         /*!< Slave configuration   */
+#define LL_SPI_MODE_SLAVE                  0x00000000U                    /*!< Slave configuration   */
 /**
   * @}
   */
@@ -174,7 +171,7 @@
 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
   * @{
   */
-#define LL_SPI_PROTOCOL_MOTOROLA           ((uint32_t)0x00000000U)   /*!< Motorola mode. Used as default value */
+#define LL_SPI_PROTOCOL_MOTOROLA           0x00000000U               /*!< Motorola mode. Used as default value */
 #define LL_SPI_PROTOCOL_TI                 (SPI_CR2_FRF)             /*!< TI mode                              */
 /**
   * @}
@@ -184,7 +181,7 @@
 /** @defgroup SPI_LL_EC_PHASE Clock Phase
   * @{
   */
-#define LL_SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)   /*!< First clock transition is the first data capture edge  */
+#define LL_SPI_PHASE_1EDGE                 0x00000000U               /*!< First clock transition is the first data capture edge  */
 #define LL_SPI_PHASE_2EDGE                 (SPI_CR1_CPHA)            /*!< Second clock transition is the first data capture edge */
 /**
   * @}
@@ -193,7 +190,7 @@
 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity
   * @{
   */
-#define LL_SPI_POLARITY_LOW                ((uint32_t)0x00000000U)   /*!< Clock to 0 when idle */
+#define LL_SPI_POLARITY_LOW                0x00000000U               /*!< Clock to 0 when idle */
 #define LL_SPI_POLARITY_HIGH               (SPI_CR1_CPOL)            /*!< Clock to 1 when idle */
 /**
   * @}
@@ -202,7 +199,7 @@
 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
   * @{
   */
-#define LL_SPI_BAUDRATEPRESCALER_DIV2      ((uint32_t)0x00000000U)                        /*!< BaudRate control equal to fPCLK/2   */
+#define LL_SPI_BAUDRATEPRESCALER_DIV2      0x00000000U                                    /*!< BaudRate control equal to fPCLK/2   */
 #define LL_SPI_BAUDRATEPRESCALER_DIV4      (SPI_CR1_BR_0)                                 /*!< BaudRate control equal to fPCLK/4   */
 #define LL_SPI_BAUDRATEPRESCALER_DIV8      (SPI_CR1_BR_1)                                 /*!< BaudRate control equal to fPCLK/8   */
 #define LL_SPI_BAUDRATEPRESCALER_DIV16     (SPI_CR1_BR_1 | SPI_CR1_BR_0)                  /*!< BaudRate control equal to fPCLK/16  */
@@ -218,7 +215,7 @@
   * @{
   */
 #define LL_SPI_LSB_FIRST                   (SPI_CR1_LSBFIRST)        /*!< Data is transmitted/received with the LSB first */
-#define LL_SPI_MSB_FIRST                   ((uint32_t)0x00000000U)   /*!< Data is transmitted/received with the MSB first */
+#define LL_SPI_MSB_FIRST                   0x00000000U               /*!< Data is transmitted/received with the MSB first */
 /**
   * @}
   */
@@ -226,7 +223,7 @@
 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
   * @{
   */
-#define LL_SPI_FULL_DUPLEX                 ((uint32_t)0x00000000U)              /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
+#define LL_SPI_FULL_DUPLEX                 0x00000000U                          /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
 #define LL_SPI_SIMPLEX_RX                  (SPI_CR1_RXONLY)                     /*!< Simplex Rx mode.  Rx transfer only on 1 line    */
 #define LL_SPI_HALF_DUPLEX_RX              (SPI_CR1_BIDIMODE)                   /*!< Half-Duplex Rx mode. Rx transfer on 1 line      */
 #define LL_SPI_HALF_DUPLEX_TX              (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)  /*!< Half-Duplex Tx mode. Tx transfer on 1 line      */
@@ -238,7 +235,7 @@
   * @{
   */
 #define LL_SPI_NSS_SOFT                    (SPI_CR1_SSM)                     /*!< NSS managed internally. NSS pin not used and free              */
-#define LL_SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)           /*!< NSS pin used in Input. Only used in Master mode                */
+#define LL_SPI_NSS_HARD_INPUT              0x00000000U                       /*!< NSS pin used in Input. Only used in Master mode                */
 #define LL_SPI_NSS_HARD_OUTPUT             (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
 /**
   * @}
@@ -247,7 +244,7 @@
 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
   * @{
   */
-#define LL_SPI_DATAWIDTH_8BIT              ((uint32_t)0x00000000U)           /*!< Data length for SPI transfer:  8 bits */
+#define LL_SPI_DATAWIDTH_8BIT              0x00000000U                       /*!< Data length for SPI transfer:  8 bits */
 #define LL_SPI_DATAWIDTH_16BIT             (SPI_CR1_DFF)                     /*!< Data length for SPI transfer:  16 bits */
 /**
   * @}
@@ -257,7 +254,7 @@
 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
   * @{
   */
-#define LL_SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000U)           /*!< CRC calculation disabled */
+#define LL_SPI_CRCCALCULATION_DISABLE      0x00000000U                       /*!< CRC calculation disabled */
 #define LL_SPI_CRCCALCULATION_ENABLE       (SPI_CR1_CRCEN)                   /*!< CRC calculation enabled  */
 /**
   * @}
@@ -1122,7 +1119,8 @@
   */
 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
 {
-  *((__IO uint8_t *)&SPIx->DR) = TxData;
+  __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
+  *spidr = TxData;
 }
 
 /**
@@ -1134,7 +1132,8 @@
   */
 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
 {
-  *((__IO uint16_t *)&SPIx->DR) = TxData;
+  __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
+  *spidr = TxData;
 }
 
 /**
@@ -1236,7 +1235,7 @@
 #define LL_I2S_SR_RXNE                     LL_SPI_SR_RXNE            /*!< Rx buffer not empty flag         */
 #define LL_I2S_SR_TXE                      LL_SPI_SR_TXE             /*!< Tx buffer empty flag             */
 #define LL_I2S_SR_BSY                      LL_SPI_SR_BSY             /*!< Busy flag                        */
-#define LL_I2S_SR_UDR                      LL_SPI_SR_UDR             /*!< Underrun flag                    */
+#define LL_I2S_SR_UDR                      SPI_SR_UDR                /*!< Underrun flag                    */
 #define LL_I2S_SR_OVR                      LL_SPI_SR_OVR             /*!< Overrun flag                     */
 #define LL_I2S_SR_FRE                      LL_SPI_SR_FRE             /*!< TI mode frame format error flag  */
 /**
@@ -1257,7 +1256,7 @@
 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format
   * @{
   */
-#define LL_I2S_DATAFORMAT_16B              ((uint32_t)0x00000000U)                       /*!< Data length 16 bits, Channel lenght 16bit */
+#define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel lenght 16bit */
 #define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel lenght 32bit */
 #define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel lenght 32bit */
 #define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel lenght 32bit */
@@ -1268,7 +1267,7 @@
 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
   * @{
   */
-#define LL_I2S_POLARITY_LOW                ((uint32_t)0x00000000U)   /*!< Clock steady state is low level  */
+#define LL_I2S_POLARITY_LOW                0x00000000U               /*!< Clock steady state is low level  */
 #define LL_I2S_POLARITY_HIGH               (SPI_I2SCFGR_CKPOL)       /*!< Clock steady state is high level */
 /**
   * @}
@@ -1277,7 +1276,7 @@
 /** @defgroup I2S_LL_EC_STANDARD I2s Standard
   * @{
   */
-#define LL_I2S_STANDARD_PHILIPS            ((uint32_t)0x00000000U)                                             /*!< I2S standard philips                      */
+#define LL_I2S_STANDARD_PHILIPS            0x00000000U                                                         /*!< I2S standard philips                      */
 #define LL_I2S_STANDARD_MSB                (SPI_I2SCFGR_I2SSTD_0)                                              /*!< MSB justified standard (left justified)   */
 #define LL_I2S_STANDARD_LSB                (SPI_I2SCFGR_I2SSTD_1)                                              /*!< LSB justified standard (right justified)  */
 #define LL_I2S_STANDARD_PCM_SHORT          (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)                       /*!< PCM standard, short frame synchronization */
@@ -1289,7 +1288,7 @@
 /** @defgroup I2S_LL_EC_MODE Operation Mode
   * @{
   */
-#define LL_I2S_MODE_SLAVE_TX               ((uint32_t)0x00000000U)                       /*!< Slave Tx configuration  */
+#define LL_I2S_MODE_SLAVE_TX               0x00000000U                                   /*!< Slave Tx configuration  */
 #define LL_I2S_MODE_SLAVE_RX               (SPI_I2SCFGR_I2SCFG_0)                        /*!< Slave Rx configuration  */
 #define LL_I2S_MODE_MASTER_TX              (SPI_I2SCFGR_I2SCFG_1)                        /*!< Master Tx configuration */
 #define LL_I2S_MODE_MASTER_RX              (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
@@ -1300,7 +1299,7 @@
 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
   * @{
   */
-#define LL_I2S_PRESCALER_PARITY_EVEN       ((uint32_t)0x00000000U)   /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
+#define LL_I2S_PRESCALER_PARITY_EVEN       0x00000000U               /*!< Odd factor: Real divider value is =  I2SDIV * 2    */
 #define LL_I2S_PRESCALER_PARITY_ODD        (SPI_I2SPR_ODD >> 8U)     /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
 /**
   * @}
@@ -1311,7 +1310,7 @@
 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
   * @{
   */
-#define LL_I2S_MCLK_OUTPUT_DISABLE         ((uint32_t)0x00000000U)   /*!< Master clock output is disabled */
+#define LL_I2S_MCLK_OUTPUT_DISABLE         0x00000000U               /*!< Master clock output is disabled */
 #define LL_I2S_MCLK_OUTPUT_ENABLE          (SPI_I2SPR_MCKOE)         /*!< Master clock output is enabled  */
 /**
   * @}
@@ -1321,16 +1320,16 @@
   * @{
   */
 
-#define LL_I2S_AUDIOFREQ_192K              ((uint32_t)192000)        /*!< Audio Frequency configuration 192000 Hz       */
-#define LL_I2S_AUDIOFREQ_96K               ((uint32_t) 96000)        /*!< Audio Frequency configuration  96000 Hz       */
-#define LL_I2S_AUDIOFREQ_48K               ((uint32_t) 48000)        /*!< Audio Frequency configuration  48000 Hz       */
-#define LL_I2S_AUDIOFREQ_44K               ((uint32_t) 44100)        /*!< Audio Frequency configuration  44100 Hz       */
-#define LL_I2S_AUDIOFREQ_32K               ((uint32_t) 32000)        /*!< Audio Frequency configuration  32000 Hz       */
-#define LL_I2S_AUDIOFREQ_22K               ((uint32_t) 22050)        /*!< Audio Frequency configuration  22050 Hz       */
-#define LL_I2S_AUDIOFREQ_16K               ((uint32_t) 16000)        /*!< Audio Frequency configuration  16000 Hz       */
-#define LL_I2S_AUDIOFREQ_11K               ((uint32_t) 11025)        /*!< Audio Frequency configuration  11025 Hz       */
-#define LL_I2S_AUDIOFREQ_8K                ((uint32_t)  8000)        /*!< Audio Frequency configuration   8000 Hz       */
-#define LL_I2S_AUDIOFREQ_DEFAULT           ((uint32_t)     2)        /*!< Audio Freq not specified. Register I2SDIV = 2 */
+#define LL_I2S_AUDIOFREQ_192K              192000U      /*!< Audio Frequency configuration 192000 Hz       */
+#define LL_I2S_AUDIOFREQ_96K               96000U       /*!< Audio Frequency configuration  96000 Hz       */
+#define LL_I2S_AUDIOFREQ_48K               48000U       /*!< Audio Frequency configuration  48000 Hz       */
+#define LL_I2S_AUDIOFREQ_44K               44100U       /*!< Audio Frequency configuration  44100 Hz       */
+#define LL_I2S_AUDIOFREQ_32K               32000U       /*!< Audio Frequency configuration  32000 Hz       */
+#define LL_I2S_AUDIOFREQ_22K               22050U       /*!< Audio Frequency configuration  22050 Hz       */
+#define LL_I2S_AUDIOFREQ_16K               16000U       /*!< Audio Frequency configuration  16000 Hz       */
+#define LL_I2S_AUDIOFREQ_11K               11025U       /*!< Audio Frequency configuration  11025 Hz       */
+#define LL_I2S_AUDIOFREQ_8K                8000U        /*!< Audio Frequency configuration   8000 Hz       */
+#define LL_I2S_AUDIOFREQ_DEFAULT           2U           /*!< Audio Freq not specified. Register I2SDIV = 2 */
 /**
   * @}
   */
@@ -1419,7 +1418,7 @@
 }
 
 /**
-  * @brief  Set I2S Data frame length
+  * @brief  Set I2S data frame length
   * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n
   *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat
   * @param  SPIx SPI Instance
@@ -1436,7 +1435,7 @@
 }
 
 /**
-  * @brief  Get I2S Data frame length
+  * @brief  Get I2S data frame length
   * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n
   *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat
   * @param  SPIx SPI Instance
@@ -1479,7 +1478,7 @@
 }
 
 /**
-  * @brief  Set I2S Standard Protocol
+  * @brief  Set I2S standard protocol
   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n
   *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard
   * @param  SPIx SPI Instance
@@ -1497,7 +1496,7 @@
 }
 
 /**
-  * @brief  Get I2S Standard Protocol
+  * @brief  Get I2S standard protocol
   * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n
   *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard
   * @param  SPIx SPI Instance
@@ -1514,7 +1513,7 @@
 }
 
 /**
-  * @brief  Set I2S Transfer Mode
+  * @brief  Set I2S transfer mode
   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode
   * @param  SPIx SPI Instance
   * @param  Mode This parameter can be one of the following values:
@@ -1530,7 +1529,7 @@
 }
 
 /**
-  * @brief  Get I2S Transfer Mode
+  * @brief  Get I2S transfer mode
   * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode
   * @param  SPIx SPI Instance
   * @retval Returned value can be one of the following values:
@@ -1595,7 +1594,7 @@
 }
 
 /**
-  * @brief  Enable the Master Clock Ouput (Pin MCK)
+  * @brief  Enable the master clock ouput (Pin MCK)
   * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
   * @param  SPIx SPI Instance
   * @retval None
@@ -1606,7 +1605,7 @@
 }
 
 /**
-  * @brief  Disable the Master Clock Ouput (Pin MCK)
+  * @brief  Disable the master clock ouput (Pin MCK)
   * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
   * @param  SPIx SPI Instance
   * @retval None
@@ -1617,7 +1616,7 @@
 }
 
 /**
-  * @brief  Check if the Master Clock Ouput (Pin MCK) is enabled
+  * @brief  Check if the master clock ouput (Pin MCK) is enabled
   * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
@@ -1658,7 +1657,7 @@
 }
 
 /**
-  * @brief  Get Busy flag
+  * @brief  Get busy flag
   * @rmtoll SR           BSY           LL_I2S_IsActiveFlag_BSY
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
@@ -1669,7 +1668,7 @@
 }
 
 /**
-  * @brief  Get Overrun error flag
+  * @brief  Get overrun error flag
   * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
@@ -1680,7 +1679,7 @@
 }
 
 /**
-  * @brief  Get Underrun error flag
+  * @brief  Get underrun error flag
   * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
@@ -1691,7 +1690,7 @@
 }
 
 /**
-  * @brief  Get Frame format error flag
+  * @brief  Get frame format error flag
   * @rmtoll SR           FRE           LL_I2S_IsActiveFlag_FRE
   * @param  SPIx SPI Instance
   * @retval State of bit (1 or 0).
@@ -1702,7 +1701,7 @@
 }
 
 /**
-  * @brief  Get Channel side flag.
+  * @brief  Get channel side flag.
   * @note   0: Channel Left has to be transmitted or has been received\n
   *         1: Channel Right has to be transmitted or has been received\n
   *         It has no significance in PCM mode.
@@ -1716,7 +1715,7 @@
 }
 
 /**
-  * @brief  Clear Overrun error flag
+  * @brief  Clear overrun error flag
   * @rmtoll SR           OVR           LL_I2S_ClearFlag_OVR
   * @param  SPIx SPI Instance
   * @retval None
@@ -1727,7 +1726,7 @@
 }
 
 /**
-  * @brief  Clear Underrun error flag
+  * @brief  Clear underrun error flag
   * @rmtoll SR           UDR           LL_I2S_ClearFlag_UDR
   * @param  SPIx SPI Instance
   * @retval None
@@ -1740,7 +1739,7 @@
 }
 
 /**
-  * @brief  Clear Frame format error flag
+  * @brief  Clear frame format error flag
   * @rmtoll SR           FRE           LL_I2S_ClearFlag_FRE
   * @param  SPIx SPI Instance
   * @retval None
@@ -1793,7 +1792,7 @@
 }
 
 /**
-  * @brief  Disable Error IT
+  * @brief  Disable error IT
   * @note   This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
   * @rmtoll CR2          ERRIE         LL_I2S_DisableIT_ERR
   * @param  SPIx SPI Instance

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_system.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_system.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_system.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of SYSTEM LL module.
   @verbatim
   ==============================================================================
@@ -21,7 +19,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -77,15 +75,12 @@
   * @{
   */
 
-/* Defines used for position in the register */
-#define DBGMCU_REVID_POSITION         (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
-
 /**
  * @brief Power-down in Run mode Flash key
  */
-#define FLASH_PDKEY1                  ((uint32_t)0x04152637U) /*!< Flash power down key1 */
-#define FLASH_PDKEY2                  ((uint32_t)0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 
-                                                                   to unlock the RUN_PD bit in FLASH_ACR */
+#define FLASH_PDKEY1                  (0x04152637U) /*!< Flash power down key1 */
+#define FLASH_PDKEY2                  (0xFAFBFCFDU) /*!< Flash power down key2: used with FLASH_PDKEY1 
+                                                       to unlock the RUN_PD bit in FLASH_ACR */
 
 /**
   * @}
@@ -102,7 +97,7 @@
 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
 * @{
 */
-#define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000U                                  /*<! Main Flash memory mapped at 0x00000000 */
+#define LL_SYSCFG_REMAP_FLASH              (0x00000000U)                                         /*<! Main Flash memory mapped at 0x00000000 */
 #define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*<! System Flash memory mapped at 0x00000000 */
 #define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*<! Embedded SRAM mapped at 0x00000000 */
 #if defined(FSMC_R_BASE)
@@ -115,7 +110,7 @@
 /** @defgroup SYSTEM_LL_EC_BOOT SYSCFG BOOT MODE
   * @{
   */
-#define LL_SYSCFG_BOOTMODE_FLASH               ((uint32_t)0x00000000U)   /*<! Main Flash memory boot mode */
+#define LL_SYSCFG_BOOTMODE_FLASH               (0x00000000U)             /*<! Main Flash memory boot mode */
 #define LL_SYSCFG_BOOTMODE_SYSTEMFLASH         SYSCFG_MEMRMP_BOOT_MODE_0 /*<! System Flash memory boot mode */
 #if defined(FSMC_BANK1)
 #define LL_SYSCFG_BOOTMODE_FSMC                SYSCFG_MEMRMP_BOOT_MODE_1 /*<! FSMC boot mode */
@@ -143,20 +138,20 @@
 /** @defgroup SYSTEM_LL_EC_EXTI SYSCFG EXTI PORT
   * @{
   */
-#define LL_SYSCFG_EXTI_PORTA               (uint32_t)0U /*!< EXTI PORT A                        */
-#define LL_SYSCFG_EXTI_PORTB               (uint32_t)1U /*!< EXTI PORT B                        */
-#define LL_SYSCFG_EXTI_PORTC               (uint32_t)2U /*!< EXTI PORT C                        */
-#define LL_SYSCFG_EXTI_PORTD               (uint32_t)3U /*!< EXTI PORT D                        */
+#define LL_SYSCFG_EXTI_PORTA               0U /*!< EXTI PORT A                        */
+#define LL_SYSCFG_EXTI_PORTB               1U /*!< EXTI PORT B                        */
+#define LL_SYSCFG_EXTI_PORTC               2U /*!< EXTI PORT C                        */
+#define LL_SYSCFG_EXTI_PORTD               3U /*!< EXTI PORT D                        */
 #if defined(GPIOE)
-#define LL_SYSCFG_EXTI_PORTE               (uint32_t)4U /*!< EXTI PORT E                        */
+#define LL_SYSCFG_EXTI_PORTE               4U /*!< EXTI PORT E                        */
 #endif /* GPIOE */
 #if defined(GPIOF)
-#define LL_SYSCFG_EXTI_PORTF               (uint32_t)6U /*!< EXTI PORT F                        */
+#define LL_SYSCFG_EXTI_PORTF               6U /*!< EXTI PORT F                        */
 #endif /* GPIOF */
 #if defined(GPIOG)
-#define LL_SYSCFG_EXTI_PORTG               (uint32_t)7U /*!< EXTI PORT G                        */
+#define LL_SYSCFG_EXTI_PORTG               7U /*!< EXTI PORT G                        */
 #endif /* GPIOG */
-#define LL_SYSCFG_EXTI_PORTH               (uint32_t)5U /*!< EXTI PORT H                        */
+#define LL_SYSCFG_EXTI_PORTH               5U /*!< EXTI PORT H                        */
 /**
   * @}
   */
@@ -187,7 +182,7 @@
 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
   * @{
   */
-#define LL_DBGMCU_TRACE_NONE               (uint32_t)0x00000000U                           /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
 #define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
 #define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
 #define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
@@ -231,7 +226,7 @@
 /** @defgroup SYSTEM_LL_EC_TIM_SELECT RI TIM selection
   * @{
   */
-#define LL_RI_TIM_SELECT_NONE              ((uint32_t)0x00000000U) /*!< No timer selected */
+#define LL_RI_TIM_SELECT_NONE              (0x00000000U)           /*!< No timer selected */
 #define LL_RI_TIM_SELECT_TIM2              RI_ICR_TIM_0            /*!< Timer 2 selected */
 #define LL_RI_TIM_SELECT_TIM3              RI_ICR_TIM_1            /*!< Timer 3 selected */
 #define LL_RI_TIM_SELECT_TIM4              RI_ICR_TIM              /*!< Timer 4 selected */
@@ -253,24 +248,24 @@
 /** @defgroup SYSTEM_LL_EC_INPUTCAPTUREROUTING RI Input Capture Routing
   * @{
   */
-                                                                   /* TIMx_IC1 TIMx_IC2  TIMx_IC3  TIMx_IC4   */  
-#define LL_RI_INPUTCAPTUREROUTING_0        ((uint32_t)0x00000000U) /*!< PA0       PA1      PA2       PA3      */
-#define LL_RI_INPUTCAPTUREROUTING_1        ((uint32_t)0x00000001U) /*!< PA4       PA5      PA6       PA7      */
-#define LL_RI_INPUTCAPTUREROUTING_2        ((uint32_t)0x00000002U) /*!< PA8       PA9      PA10      PA11     */
-#define LL_RI_INPUTCAPTUREROUTING_3        ((uint32_t)0x00000003U) /*!< PA12      PA13     PA14      PA15     */
-#define LL_RI_INPUTCAPTUREROUTING_4        ((uint32_t)0x00000004U) /*!< PC0       PC1      PC2       PC3      */
-#define LL_RI_INPUTCAPTUREROUTING_5        ((uint32_t)0x00000005U) /*!< PC4       PC5      PC6       PC7      */
-#define LL_RI_INPUTCAPTUREROUTING_6        ((uint32_t)0x00000006U) /*!< PC8       PC9      PC10      PC11     */
-#define LL_RI_INPUTCAPTUREROUTING_7        ((uint32_t)0x00000007U) /*!< PC12      PC13     PC14      PC15     */
-#define LL_RI_INPUTCAPTUREROUTING_8        ((uint32_t)0x00000008U) /*!< PD0       PD1      PD2       PD3      */
-#define LL_RI_INPUTCAPTUREROUTING_9        ((uint32_t)0x00000009U) /*!< PD4       PD5      PD6       PD7      */
-#define LL_RI_INPUTCAPTUREROUTING_10       ((uint32_t)0x0000000AU) /*!< PD8       PD9      PD10      PD11     */
-#define LL_RI_INPUTCAPTUREROUTING_11       ((uint32_t)0x0000000BU) /*!< PD12      PD13     PD14      PD15     */
+                                                         /* TIMx_IC1 TIMx_IC2  TIMx_IC3  TIMx_IC4   */  
+#define LL_RI_INPUTCAPTUREROUTING_0        (0x00000000U) /*!< PA0       PA1      PA2       PA3      */
+#define LL_RI_INPUTCAPTUREROUTING_1        (0x00000001U) /*!< PA4       PA5      PA6       PA7      */
+#define LL_RI_INPUTCAPTUREROUTING_2        (0x00000002U) /*!< PA8       PA9      PA10      PA11     */
+#define LL_RI_INPUTCAPTUREROUTING_3        (0x00000003U) /*!< PA12      PA13     PA14      PA15     */
+#define LL_RI_INPUTCAPTUREROUTING_4        (0x00000004U) /*!< PC0       PC1      PC2       PC3      */
+#define LL_RI_INPUTCAPTUREROUTING_5        (0x00000005U) /*!< PC4       PC5      PC6       PC7      */
+#define LL_RI_INPUTCAPTUREROUTING_6        (0x00000006U) /*!< PC8       PC9      PC10      PC11     */
+#define LL_RI_INPUTCAPTUREROUTING_7        (0x00000007U) /*!< PC12      PC13     PC14      PC15     */
+#define LL_RI_INPUTCAPTUREROUTING_8        (0x00000008U) /*!< PD0       PD1      PD2       PD3      */
+#define LL_RI_INPUTCAPTUREROUTING_9        (0x00000009U) /*!< PD4       PD5      PD6       PD7      */
+#define LL_RI_INPUTCAPTUREROUTING_10       (0x0000000AU) /*!< PD8       PD9      PD10      PD11     */
+#define LL_RI_INPUTCAPTUREROUTING_11       (0x0000000BU) /*!< PD12      PD13     PD14      PD15     */
 #if defined(GPIOE)
-#define LL_RI_INPUTCAPTUREROUTING_12       ((uint32_t)0x0000000CU) /*!< PE0       PE1      PE2       PE3      */
-#define LL_RI_INPUTCAPTUREROUTING_13       ((uint32_t)0x0000000DU) /*!< PE4       PE5      PE6       PE7      */
-#define LL_RI_INPUTCAPTUREROUTING_14       ((uint32_t)0x0000000EU) /*!< PE8       PE9      PE10      PE11     */
-#define LL_RI_INPUTCAPTUREROUTING_15       ((uint32_t)0x0000000FU) /*!< PE12      PE13     PE14      PE15     */
+#define LL_RI_INPUTCAPTUREROUTING_12       (0x0000000CU) /*!< PE0       PE1      PE2       PE3      */
+#define LL_RI_INPUTCAPTUREROUTING_13       (0x0000000DU) /*!< PE4       PE5      PE6       PE7      */
+#define LL_RI_INPUTCAPTUREROUTING_14       (0x0000000EU) /*!< PE8       PE9      PE10      PE11     */
+#define LL_RI_INPUTCAPTUREROUTING_15       (0x0000000FU) /*!< PE12      PE13     PE14      PE15     */
 #endif /* GPIOE */
 /**
   * @}
@@ -355,18 +350,18 @@
 /** @defgroup SYSTEM_LL_EC_HSYTERESIS_PORT RI HSYTERESIS PORT
   * @{
   */
-#define LL_RI_HSYTERESIS_PORT_A            (uint32_t)0U         /*!< HYSTERESIS PORT A  */
-#define LL_RI_HSYTERESIS_PORT_B            (uint32_t)1U         /*!< HYSTERESIS PORT B  */
-#define LL_RI_HSYTERESIS_PORT_C            (uint32_t)2U         /*!< HYSTERESIS PORT C  */
-#define LL_RI_HSYTERESIS_PORT_D            (uint32_t)3U         /*!< HYSTERESIS PORT D  */
+#define LL_RI_HSYTERESIS_PORT_A            0U         /*!< HYSTERESIS PORT A  */
+#define LL_RI_HSYTERESIS_PORT_B            1U         /*!< HYSTERESIS PORT B  */
+#define LL_RI_HSYTERESIS_PORT_C            2U         /*!< HYSTERESIS PORT C  */
+#define LL_RI_HSYTERESIS_PORT_D            3U         /*!< HYSTERESIS PORT D  */
 #if defined(GPIOE)
-#define LL_RI_HSYTERESIS_PORT_E            (uint32_t)4U         /*!< HYSTERESIS PORT E  */
+#define LL_RI_HSYTERESIS_PORT_E            4U         /*!< HYSTERESIS PORT E  */
 #endif /* GPIOE */
 #if defined(GPIOF)
-#define LL_RI_HSYTERESIS_PORT_F            (uint32_t)5U         /*!< HYSTERESIS PORT F  */
+#define LL_RI_HSYTERESIS_PORT_F            5U         /*!< HYSTERESIS PORT F  */
 #endif /* GPIOF */
 #if defined(GPIOG)
-#define LL_RI_HSYTERESIS_PORT_G            (uint32_t)6U         /*!< HYSTERESIS PORT G  */
+#define LL_RI_HSYTERESIS_PORT_G            6U         /*!< HYSTERESIS PORT G  */
 #endif /* GPIOG */
 /**
   * @}
@@ -400,14 +395,14 @@
 /** @defgroup SYSTEM_LL_EC_PORT RI PORT
   * @{
   */
-#define LL_RI_PORT_A                       (uint32_t)0U         /*!< PORT A   */
-#define LL_RI_PORT_B                       (uint32_t)1U         /*!< PORT B   */
-#define LL_RI_PORT_C                       (uint32_t)2U         /*!< PORT C   */
+#define LL_RI_PORT_A                       0U         /*!< PORT A   */
+#define LL_RI_PORT_B                       1U         /*!< PORT B   */
+#define LL_RI_PORT_C                       2U         /*!< PORT C   */
 #if defined(GPIOF)
-#define LL_RI_PORT_F                       (uint32_t)3U         /*!< PORT F   */
+#define LL_RI_PORT_F                       3U         /*!< PORT F   */
 #endif /* GPIOF */
 #if defined(GPIOG)
-#define LL_RI_PORT_G                       (uint32_t)4U         /*!< PORT G   */
+#define LL_RI_PORT_G                       4U         /*!< PORT G   */
 #endif /* GPIOG */
 /**
   * @}
@@ -419,7 +414,7 @@
 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
   * @{
   */
-#define LL_FLASH_LATENCY_0                 ((uint32_t)0x00000000U) /*!< FLASH Zero Latency cycle */
+#define LL_FLASH_LATENCY_0                 0x00000000U             /*!< FLASH Zero Latency cycle */
 #define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY       /*!< FLASH One Latency cycle */
 /**
   * @}
@@ -779,7 +774,7 @@
   */
 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
 {
-  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_REVID_POSITION);
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_tim.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_tim.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_tim.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   TIM LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -248,7 +246,7 @@
   /* Set the default configuration */
   TIM_InitStruct->Prescaler         = (uint16_t)0x0000U;
   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
-  TIM_InitStruct->Autoreload        = (uint32_t)0xFFFFFFFFU;
+  TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
 }
 
@@ -309,7 +307,7 @@
   /* Set the default configuration */
   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
-  TIM_OC_InitStruct->CompareValue = (uint32_t)0x00000000U;
+  TIM_OC_InitStruct->CompareValue = 0x00000000U;
   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
 }
 
@@ -487,7 +485,6 @@
   return SUCCESS;
 }
 
-
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_tim.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_tim.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_tim.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of TIM LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -116,12 +114,12 @@
   */
 
 
-#define TIMx_OR_RMP_SHIFT  ((uint32_t)16U)
-#define TIMx_OR_RMP_MASK   ((uint32_t)0x0000FFFFU)
-#define TIM_OR_RMP_MASK    ((uint32_t)((TIM_OR_TI1RMP | TIM_OR_ETR_RMP | TIM_OR_TI1_RMP_RI)  << TIMx_OR_RMP_SHIFT))
-#define TIM9_OR_RMP_MASK   ((uint32_t)((TIM_OR_TI1RMP | TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT))
-#define TIM2_OR_RMP_MASK   ((uint32_t)(TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT))
-#define TIM3_OR_RMP_MASK   ((uint32_t)(TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT))
+#define TIMx_OR_RMP_SHIFT  16U
+#define TIMx_OR_RMP_MASK   0x0000FFFFU
+#define TIM_OR_RMP_MASK    ((TIM_OR_TI1RMP | TIM_OR_ETR_RMP | TIM_OR_TI1_RMP_RI) << TIMx_OR_RMP_SHIFT)
+#define TIM9_OR_RMP_MASK   ((TIM_OR_TI1RMP | TIM9_OR_ITR1_RMP) << TIMx_OR_RMP_SHIFT)
+#define TIM2_OR_RMP_MASK   (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
+#define TIM3_OR_RMP_MASK   (TIM3_OR_ITR2_RMP << TIMx_OR_RMP_SHIFT)
 
 
 
@@ -129,7 +127,6 @@
   * @}
   */
 
-
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
   * @{
@@ -173,7 +170,7 @@
 
                                    This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
 
-  uint32_t Autoreload;       /*!< Specifies the auto reload value to be loaded into the active
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
                                    Auto-Reload Register at the next update event.
                                    This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
                                    Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
@@ -211,6 +208,7 @@
 
                                This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
 
+
 } LL_TIM_OC_InitTypeDef;
 
 /**
@@ -340,8 +338,8 @@
 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
   * @{
   */
-#define LL_TIM_UPDATESOURCE_REGULAR            ((uint32_t)0x00000000U) /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
-#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS            /*!< Only counter overflow/underflow generates an update request */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
 /**
   * @}
   */
@@ -349,8 +347,8 @@
 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
   * @{
   */
-#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM            /*!< Counter is not stopped at update event */
-#define LL_TIM_ONEPULSEMODE_REPETITIVE         ((uint32_t)0x00000000U) /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter is not stopped at update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter stops counting at the next update event */
 /**
   * @}
   */
@@ -358,11 +356,11 @@
 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
   * @{
   */
-#define LL_TIM_COUNTERMODE_UP                  ((uint32_t)0x00000000U) /*!<Counter used as upcounter */
-#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR             /*!< Counter used as downcounter */
-#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0           /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
-#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1           /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
-#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS             /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
 /**
   * @}
   */
@@ -370,9 +368,9 @@
 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
   * @{
   */
-#define LL_TIM_CLOCKDIVISION_DIV1              ((uint32_t)0x00000000U) /*!< tDTS=tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0           /*!< tDTS=2*tCK_INT */
-#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1           /*!< tDTS=4*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
 /**
   * @}
   */
@@ -380,8 +378,8 @@
 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
   * @{
   */
-#define LL_TIM_COUNTERDIRECTION_UP             ((uint32_t)0x00000000U) /*!< Timer counter counts up */
-#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR             /*!< Timer counter counts down */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
 /**
   * @}
   */
@@ -390,8 +388,8 @@
 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
   * @{
   */
-#define LL_TIM_CCDMAREQUEST_CC                 ((uint32_t)0x00000000U) /*!< CCx DMA request sent when CCx event occurs */
-#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS            /*!< CCx DMA requests sent when update event occurs */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
 /**
   * @}
   */
@@ -412,7 +410,7 @@
 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
   * @{
   */
-#define LL_TIM_OCSTATE_DISABLE                 ((uint32_t)0x00000000U) /*!< OCx is not active */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
 #define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
 /**
   * @}
@@ -422,11 +420,11 @@
 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
   * @{
   */
-#define LL_TIM_OCMODE_FROZEN                   ((uint32_t)0x00000000U)                                  /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
 #define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
 #define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
 #define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
-#define LL_TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)                                       /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                       /*!<OCyREF is forced low*/
 #define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
 #define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
 #define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
@@ -437,7 +435,7 @@
 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
   * @{
   */
-#define LL_TIM_OCPOLARITY_HIGH                 ((uint32_t)0x00000000U)     /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
 #define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
 /**
   * @}
@@ -448,9 +446,9 @@
 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
   * @{
   */
-#define LL_TIM_ACTIVEINPUT_DIRECTTI            (uint32_t)(TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
-#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (uint32_t)(TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
-#define LL_TIM_ACTIVEINPUT_TRC                 (uint32_t)(TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
 /**
   * @}
   */
@@ -458,10 +456,10 @@
 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
   * @{
   */
-#define LL_TIM_ICPSC_DIV1                      ((uint32_t)0x00000000U) /*!< No prescaler, capture is done each time an edge is detected on the capture input */
-#define LL_TIM_ICPSC_DIV2                      (uint32_t)(TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
-#define LL_TIM_ICPSC_DIV4                      (uint32_t)(TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
-#define LL_TIM_ICPSC_DIV8                      (uint32_t)(TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                              /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
 /**
   * @}
   */
@@ -469,22 +467,22 @@
 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
   * @{
   */
-#define LL_TIM_IC_FILTER_FDIV1                 ((uint32_t)0x00000000U)                                         /*!< No filter, sampling is done at fDTS */
-#define LL_TIM_IC_FILTER_FDIV1_N2              (uint32_t)(TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
-#define LL_TIM_IC_FILTER_FDIV1_N4              (uint32_t)(TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
-#define LL_TIM_IC_FILTER_FDIV1_N8              (uint32_t)((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
-#define LL_TIM_IC_FILTER_FDIV2_N6              (uint32_t)(TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
-#define LL_TIM_IC_FILTER_FDIV2_N8              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_IC_FILTER_FDIV4_N6              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
-#define LL_TIM_IC_FILTER_FDIV4_N8              (uint32_t)((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
-#define LL_TIM_IC_FILTER_FDIV8_N6              (uint32_t)(TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
-#define LL_TIM_IC_FILTER_FDIV8_N8              (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
-#define LL_TIM_IC_FILTER_FDIV16_N5             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_IC_FILTER_FDIV16_N6             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
-#define LL_TIM_IC_FILTER_FDIV16_N8             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_IC_FILTER_FDIV32_N5             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_IC_FILTER_FDIV32_N6             (uint32_t)((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
-#define LL_TIM_IC_FILTER_FDIV32_N8             (uint32_t)(TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
 /**
   * @}
   */
@@ -492,7 +490,7 @@
 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
   * @{
   */
-#define LL_TIM_IC_POLARITY_RISING              ((uint32_t)0x00000000U)          /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
 #define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
 #define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
 /**
@@ -502,9 +500,9 @@
 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
   * @{
   */
-#define LL_TIM_CLOCKSOURCE_INTERNAL            ((uint32_t)0x00000000U)                              /*!< The timer is clocked by the internal clock provided from the RCC */
-#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0 ) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
-#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                        /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected inpu t*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
 /**
   * @}
   */
@@ -522,7 +520,7 @@
 /** @defgroup TIM_LL_EC_TRGO Trigger Output
   * @{
   */
-#define LL_TIM_TRGO_RESET                      ((uint32_t)0x00000000U)                         /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
 #define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
 #define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
 #define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
@@ -538,7 +536,7 @@
 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
   * @{
   */
-#define LL_TIM_SLAVEMODE_DISABLED              ((uint32_t)0x00000000U)             /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
 #define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
 #define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
 #define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
@@ -549,14 +547,14 @@
 /** @defgroup TIM_LL_EC_TS Trigger Selection
   * @{
   */
-#define LL_TIM_TS_ITR0                         ((uint32_t)0x00000000U)         /*!< Internal Trigger 0 (ITR0) is used as trigger input */
-#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
-#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
-#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
-#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
-#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
-#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
-#define LL_TIM_TS_ETRF                         TIM_SMCR_TS                     /*!< Filtered external Trigger (ETRF) is used as trigger input */
+#define LL_TIM_TS_ITR0                         0x00000000U                                      /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                    /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                    /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                  /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                    /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                  /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                  /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)  /*!< Filtered external Trigger (ETRF) is used as trigger input */
 /**
   * @}
   */
@@ -564,7 +562,7 @@
 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
   * @{
   */
-#define LL_TIM_ETR_POLARITY_NONINVERTED        ((uint32_t)0x00000000U) /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
 #define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
 /**
   * @}
@@ -573,7 +571,7 @@
 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
   * @{
   */
-#define LL_TIM_ETR_PRESCALER_DIV1              ((uint32_t)0x00000000U) /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
 #define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
 #define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
 #define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
@@ -584,21 +582,21 @@
 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
   * @{
   */
-#define LL_TIM_ETR_FILTER_FDIV1                ((uint32_t)0x00000000U)                              /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
 #define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
 #define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
 #define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
 #define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
 #define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 )                   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
 #define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
 #define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */
 #define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 )                   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */
 #define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */
-#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 )                   /*!< fSAMPLING=fDTS/16, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2  | TIM_SMCR_ETF_0)  /*!< fSAMPLING=fDTS/32, N=5 */
-#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2  | TIM_SMCR_ETF_1)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
 #define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
 /**
   * @}
@@ -613,7 +611,7 @@
 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
   * @{
   */
-#define LL_TIM_DMABURST_BASEADDR_CR1           ((uint32_t)0x00000000U)                                          /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
 #define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
 #define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
 #define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
@@ -637,7 +635,7 @@
 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
   * @{
   */
-#define LL_TIM_DMABURST_LENGTH_1TRANSFER       ((uint32_t)0x00000000U)                                         /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
@@ -660,9 +658,9 @@
   */
 
 /** @defgroup TIM_LL_EC_TIM10_TI1_RMP  TIM10 input 1 remapping capability
-* @{
-*/
-#define LL_TIM_TIM10_TI1_RMP_GPIO   ((uint32_t)0x00000000U | TIM_OR_RMP_MASK)               /*!< TIM10 channel1 is connected to GPIO */
+  * @{
+  */
+#define LL_TIM_TIM10_TI1_RMP_GPIO   TIM_OR_RMP_MASK                                         /*!< TIM10 channel1 is connected to GPIO */
 #define LL_TIM_TIM10_TI1_RMP_LSI    (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK)                     /*!< TIM10 channel1 is connected to LSI internal clock */
 #define LL_TIM_TIM10_TI1_RMP_LSE    (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK)                     /*!< TIM10 channel1 is connected to LSE internal clock */
 #define LL_TIM_TIM10_TI1_RMP_RTC    (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK)   /*!< TIM10 channel1 is connected to RTC wakeup interrupt signal */
@@ -671,9 +669,9 @@
   */
 
 /** @defgroup TIM_LL_EC_TIM10_ETR_RMP  TIM10 ETR remap
-* @{
-*/
-#define LL_TIM_TIM10_ETR_RMP_LSE      ((uint32_t)0x00000000U | TIM_OR_RMP_MASK)               /*!< TIM10 ETR input is connected to LSE */
+  * @{
+  */
+#define LL_TIM_TIM10_ETR_RMP_LSE      TIM_OR_RMP_MASK                                         /*!< TIM10 ETR input is connected to LSE */
 #define LL_TIM_TIM10_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK)                      /*!< TIM10 ETR input is connected to TIM9 TGO */
 /**
   * @}
@@ -682,16 +680,16 @@
 /** @defgroup TIM_LL_EC_TIM10_TI1_RMP_RI TIM10 Input 1 remap for Routing Interface (RI)
 * @{
 */
-#define LL_TIM_TIM10_TI1_RMP          ((uint32_t)0x00000000U | TIM_OR_RMP_MASK)               /*!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values */
+#define LL_TIM_TIM10_TI1_RMP          TIM_OR_RMP_MASK                                         /*!< TIM10 Channel1 connection depends on TI1_RMP[1:0] bit values */
 #define LL_TIM_TIM10_TI1_RMP_RI       (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK)                   /*!< TIM10 channel1 is connected to RI */
 /**
   * @}
   */
 
 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP  TIM11 input 1 remapping capability
-* @{
-*/
-#define LL_TIM_TIM11_TI1_RMP_GPIO       ((uint32_t)0x00000000U | TIM_OR_RMP_MASK)             /*!< TIM11 channel1 is connected to GPIO */
+  * @{
+  */
+#define LL_TIM_TIM11_TI1_RMP_GPIO       TIM_OR_RMP_MASK                                       /*!< TIM11 channel1 is connected to GPIO */
 #define LL_TIM_TIM11_TI1_RMP_MSI        (TIM_OR_TI1RMP_0 | TIM_OR_RMP_MASK)                   /*!< TIM11 channel1 is connected to MSI internal clock */
 #define LL_TIM_TIM11_TI1_RMP_HSE_RTC    (TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK)                   /*!< TIM11 channel1 is connected to HSE RTC clock */
 #define LL_TIM_TIM11_TI1_RMP_GPIO1      (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM_OR_RMP_MASK) /*!< TIM11 channel1 is connected to GPIO */
@@ -700,27 +698,27 @@
   */
 
 /** @defgroup TIM_LL_EC_TIM11_ETR_RMP  TIM11 ETR remap
-* @{
-*/
-#define LL_TIM_TIM11_ETR_RMP_LSE      ((uint32_t)0x00000000U | TIM_OR_RMP_MASK)               /*!< TIM11 ETR input is connected to LSE */
+  * @{
+  */
+#define LL_TIM_TIM11_ETR_RMP_LSE      TIM_OR_RMP_MASK                                         /*!< TIM11 ETR input is connected to LSE */
 #define LL_TIM_TIM11_ETR_RMP_TIM9_TGO (TIM_OR_ETR_RMP | TIM_OR_RMP_MASK)                      /*!< TIM11 ETR input is connected to TIM9 TGO clock */
 /**
   * @}
   */
 
 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP_RI TIM11 Input 1 remap for Routing Interface (RI)
-* @{
-*/
-#define LL_TIM_TIM11_TI1_RMP          ((uint32_t)0x00000000U | TIM_OR_RMP_MASK)               /*!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values */
+  * @{
+  */
+#define LL_TIM_TIM11_TI1_RMP          TIM_OR_RMP_MASK                                         /*!< TIM11 Channel1 connection depends on TI1_RMP[1:0] bit values */
 #define LL_TIM_TIM11_TI1_RMP_RI       (TIM_OR_TI1_RMP_RI | TIM_OR_RMP_MASK)                   /*!< TIM11 channel1 is connected to RI */
 /**
   * @}
   */
 
 /** @defgroup TIM_LL_EC_TIM9_TI1_RMP TIM9 Input 1 remap
-* @{
-*/
-#define LL_TIM_TIM9_TI1_RMP_GPIO     ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK)                /*!< TIM9 channel1 is connected to GPIO */
+  * @{
+  */
+#define LL_TIM_TIM9_TI1_RMP_GPIO     TIM9_OR_RMP_MASK                                          /*!< TIM9 channel1 is connected to GPIO */
 #define LL_TIM_TIM9_TI1_RMP_LSE      (TIM_OR_TI1RMP_0 | TIM9_OR_RMP_MASK)                      /*!< TIM9 channel1 is connected to LSE internal clock */
 #define LL_TIM_TIM9_TI1_RMP_GPIO1    (TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK)                      /*!< TIM9 channel1 is connected to GPIO */
 #define LL_TIM_TIM9_TI1_RMP_GPIO2    (TIM_OR_TI1RMP_0 | TIM_OR_TI1RMP_1 | TIM9_OR_RMP_MASK)    /*!< TIM9 channel1 is connected to GPIO */
@@ -729,9 +727,9 @@
   */
 
 /** @defgroup TIM_LL_EC_TIM9_ITR1_RMP  TIM9 ITR1 remap
-* @{
-*/
-#define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO   ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK)           /*!< TIM9 channel1 is connected to TIM3 TGO signal */
+  * @{
+  */
+#define LL_TIM_TIM9_ITR1_RMP_TIM3_TGO   TIM9_OR_RMP_MASK                                     /*!< TIM9 channel1 is connected to TIM3 TGO signal */
 #define LL_TIM_TIM9_ITR1_RMP_TOUCH_IO   (TIM9_OR_ITR1_RMP | TIM9_OR_RMP_MASK)                /*!< TIM9 channel1 is connected to touch sensing I/O */
 /**
   * @}
@@ -740,16 +738,16 @@
 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP  TIM2 internal trigger 1 remap
 * @{
 */
-#define LL_TIM_TIM2_TIR1_RMP_TIM10_OC    ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK)           /*!< TIM2 ITR1 input is connected to TIM10 OC*/
+#define LL_TIM_TIM2_TIR1_RMP_TIM10_OC    TIM9_OR_RMP_MASK                                     /*!< TIM2 ITR1 input is connected to TIM10 OC*/
 #define LL_TIM_TIM2_TIR1_RMP_TIM5_TGO    (TIM2_OR_ITR1_RMP | TIM9_OR_RMP_MASK)                /*!< TIM2 ITR1 input is connected to TIM5 TGO */
 /**
   * @}
   */
 
 /** @defgroup TIM_LL_EC_TIM3_ITR2_RMP  TIM3 internal trigger 2 remap
-* @{
-*/
-#define LL_TIM_TIM3_TIR2_RMP_TIM11_OC    ((uint32_t)0x00000000U | TIM9_OR_RMP_MASK)           /*!< TIM3 ITR2 input is connected to TIM11 OC */
+  * @{
+  */
+#define LL_TIM_TIM3_TIR2_RMP_TIM11_OC    TIM9_OR_RMP_MASK                                     /*!< TIM3 ITR2 input is connected to TIM11 OC */
 #define LL_TIM_TIM3_TIR2_RMP_TIM5_TGO    (TIM3_OR_ITR2_RMP | TIM9_OR_RMP_MASK)                /*!< TIM3 ITR2 input is connected to TIM5 TGO */
 /**
   * @}
@@ -759,13 +757,12 @@
 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
   * @{
   */
-#define LL_TIM_OCREF_CLR_INT_OCREF_CLR     ((uint32_t)0x00000000U ) /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
-#define LL_TIM_OCREF_CLR_INT_ETR           TIM_SMCR_OCCS            /*!< OCREF_CLR_INT is connected to ETRF */
+#define LL_TIM_OCREF_CLR_INT_OCREF_CLR     0x00000000U         /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
+#define LL_TIM_OCREF_CLR_INT_ETR           TIM_SMCR_OCCS       /*!< OCREF_CLR_INT is connected to ETRF */
 /**
   * @}
   */
 
-
 /**
   * @}
   */
@@ -860,7 +857,7 @@
   * @retval Input capture prescaler ratio (1, 2, 4 or 8)
   */
 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
-   ((uint32_t)((uint32_t)0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+   ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
 
 
 /**
@@ -921,7 +918,7 @@
   */
 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
 {
-  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
 }
 
 /**
@@ -932,7 +929,7 @@
   */
 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
 {
-  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
 }
 
 /**
@@ -2560,11 +2557,11 @@
   * @{
   */
 /**
-  * @brief  Set the OCREF clear source
+  * @brief  Set the OCREF clear input source
   * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
   * @note This function can only be used in Output compare and PWM modes.
   * @note the ETR signal can be connected to the output of a comparator to be used for current handling
-  * @rmtoll SMCR          OCCS           LL_TIM_SetOCRefClearInputSource
+  * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
   * @param  TIMx Timer instance
   * @param  OCRefClearInputSource This parameter can be one of the following values:
   *         @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
@@ -3327,5 +3324,4 @@
 #endif
 
 #endif /* __STM32L1xx_LL_TIM_H */
-
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_usart.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_usart.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_usart.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   USART LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_usart.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_usart.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_usart.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of USART LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -58,17 +56,7 @@
 
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
-
 /* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Constants USART Private Constants
-  * @{
-  */
-
-/* Defines used for the bit position in the register and perform offsets*/
-#define USART_POSITION_GTPR_GT                  USART_GTPR_GT_Pos
-/**
-  * @}
-  */
 
 /* Private macros ------------------------------------------------------------*/
 #if defined(USE_FULL_LL_DRIVER)
@@ -207,7 +195,7 @@
 /** @defgroup USART_LL_EC_DIRECTION Communication Direction
   * @{
   */
-#define LL_USART_DIRECTION_NONE                 (uint32_t)0x00000000U              /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
 #define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
 #define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
 #define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
@@ -218,7 +206,7 @@
 /** @defgroup USART_LL_EC_PARITY Parity Control
   * @{
   */
-#define LL_USART_PARITY_NONE                    (uint32_t)0x00000000U                /*!< Parity control disabled */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
 #define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
 #define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
 /**
@@ -228,7 +216,7 @@
 /** @defgroup USART_LL_EC_WAKEUP Wakeup
   * @{
   */
-#define LL_USART_WAKEUP_IDLELINE                (uint32_t)0x00000000U /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
 #define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
 /**
   * @}
@@ -237,7 +225,7 @@
 /** @defgroup USART_LL_EC_DATAWIDTH Datawidth
   * @{
   */
-#define LL_USART_DATAWIDTH_8B                   (uint32_t)0x00000000U   /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
 #define LL_USART_DATAWIDTH_9B                   USART_CR1_M             /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
 /**
   * @}
@@ -246,7 +234,7 @@
 /** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
   * @{
   */
-#define LL_USART_OVERSAMPLING_16                (uint32_t)0x00000000U  /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
 #define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
 /**
   * @}
@@ -257,7 +245,7 @@
   * @{
   */
 
-#define LL_USART_CLOCK_DISABLE                  (uint32_t)0x00000000U  /*!< Clock signal not provided */
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
 #define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
 /**
   * @}
@@ -267,7 +255,7 @@
 /** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
   * @{
   */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT         (uint32_t)0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
 #define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
 /**
   * @}
@@ -276,7 +264,7 @@
 /** @defgroup USART_LL_EC_PHASE Clock Phase
   * @{
   */
-#define LL_USART_PHASE_1EDGE                    (uint32_t)0x00000000U /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
 #define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
 /**
   * @}
@@ -285,7 +273,7 @@
 /** @defgroup USART_LL_EC_POLARITY Clock Polarity
   * @{
   */
-#define LL_USART_POLARITY_LOW                   (uint32_t)0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
 #define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
 /**
   * @}
@@ -295,7 +283,7 @@
   * @{
   */
 #define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
-#define LL_USART_STOPBITS_1                     (uint32_t)0x00000000U                      /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
 #define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
 #define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
 /**
@@ -305,7 +293,7 @@
 /** @defgroup USART_LL_EC_HWCONTROL Hardware Control
   * @{
   */
-#define LL_USART_HWCONTROL_NONE                 (uint32_t)0x00000000U                /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
 #define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
 #define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
 #define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
@@ -316,7 +304,7 @@
 /** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
   * @{
   */
-#define LL_USART_IRDA_POWER_NORMAL              (uint32_t)0x00000000U /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
 #define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
 /**
   * @}
@@ -325,7 +313,7 @@
 /** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
   * @{
   */
-#define LL_USART_LINBREAK_DETECT_10B            (uint32_t)0x00000000U /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
 #define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
 /**
   * @}
@@ -1318,7 +1306,7 @@
   */
 __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
 {
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_GTPR_GT_Pos);
 }
 
 /**
@@ -1332,7 +1320,7 @@
   */
 __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
 {
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
 }
 
 /**

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_utils.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_utils.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_utils.c
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   UTILS LL module driver.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -54,23 +52,23 @@
 /** @addtogroup UTILS_LL_Private_Constants
   * @{
   */
-#define UTILS_MAX_FREQUENCY_SCALE1  ((uint32_t)32000000U)        /*!< Maximum frequency for system clock at power scale1, in Hz */
-#define UTILS_MAX_FREQUENCY_SCALE2  ((uint32_t)16000000U)        /*!< Maximum frequency for system clock at power scale2, in Hz */
-#define UTILS_MAX_FREQUENCY_SCALE3  ((uint32_t)4000000U)         /*!< Maximum frequency for system clock at power scale3, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE1  32000000U        /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE2  16000000U        /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define UTILS_MAX_FREQUENCY_SCALE3   4000000U        /*!< Maximum frequency for system clock at power scale3, in Hz */
 
 /* Defines used for PLL range */
-#define UTILS_PLLVCO_OUTPUT_SCALE1  ((uint32_t)96000000U)        /*!< Frequency max for PLLVCO output at power scale1, in Hz  */
-#define UTILS_PLLVCO_OUTPUT_SCALE2  ((uint32_t)48000000U)        /*!< Frequency max for PLLVCO output at power scale2, in Hz  */
-#define UTILS_PLLVCO_OUTPUT_SCALE3  ((uint32_t)24000000U)        /*!< Frequency max for PLLVCO output at power scale3, in Hz  */
+#define UTILS_PLLVCO_OUTPUT_SCALE1  96000000U        /*!< Frequency max for PLLVCO output at power scale1, in Hz  */
+#define UTILS_PLLVCO_OUTPUT_SCALE2  48000000U        /*!< Frequency max for PLLVCO output at power scale2, in Hz  */
+#define UTILS_PLLVCO_OUTPUT_SCALE3  24000000U        /*!< Frequency max for PLLVCO output at power scale3, in Hz  */
 
 /* Defines used for HSE range */
-#define UTILS_HSE_FREQUENCY_MIN     ((uint32_t)1000000U)         /*!< Frequency min for HSE frequency, in Hz   */
-#define UTILS_HSE_FREQUENCY_MAX     ((uint32_t)24000000U)        /*!< Frequency max for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MIN      1000000U       /*!< Frequency min for HSE frequency, in Hz   */
+#define UTILS_HSE_FREQUENCY_MAX     24000000U       /*!< Frequency max for HSE frequency, in Hz   */
 
 /* Defines used for FLASH latency according to HCLK Frequency */
-#define UTILS_SCALE1_LATENCY1_FREQ  ((uint32_t)16000000U)        /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
-#define UTILS_SCALE2_LATENCY1_FREQ  ((uint32_t)8000000U)         /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
-#define UTILS_SCALE3_LATENCY1_FREQ  ((uint32_t)2000000U)         /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
+#define UTILS_SCALE1_LATENCY1_FREQ  16000000U        /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
+#define UTILS_SCALE2_LATENCY1_FREQ   8000000U        /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
+#define UTILS_SCALE3_LATENCY1_FREQ   2000000U        /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
 /**
   * @}
   */
@@ -134,7 +132,9 @@
   */
 static uint32_t    UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
                                                LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
+#if defined(FLASH_ACR_LATENCY)
 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency);
+#endif /* FLASH_ACR_LATENCY */
 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
 static ErrorStatus UTILS_PLL_IsBusy(void);
 /**
@@ -338,6 +338,7 @@
   /* Check if one of the PLL is enabled */
   if (UTILS_PLL_IsBusy() == SUCCESS)
   {
+
     /* Calculate the new PLL output frequency */
     pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
 
@@ -396,6 +397,7 @@
   *          - SUCCESS: Latency has been modified
   *          - ERROR: Latency cannot be modified
   */
+#if defined(FLASH_ACR_LATENCY)
 static ErrorStatus UTILS_SetFlashLatency(uint32_t Frequency)
 {
   ErrorStatus status = SUCCESS;
@@ -454,6 +456,7 @@
   }
   return status;
 }
+#endif /* FLASH_ACR_LATENCY */
 
 /**
   * @brief  Function to check that PLL can be modified
@@ -503,7 +506,6 @@
     status = ERROR;
   }
 
-
   return status;
 }
 

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_utils.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_utils.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_utils.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of UTILS LL module.
   @verbatim
   ==============================================================================
@@ -20,7 +18,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -75,7 +73,7 @@
   */
 
 /* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY                  (uint32_t)0xFFFFFFFFU
+#define LL_MAX_DELAY                  0xFFFFFFFFU
 
 /**
  * @brief Unique device ID register base address
@@ -157,8 +155,8 @@
 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
   * @{
   */
-#define LL_UTILS_HSEBYPASS_OFF        (uint32_t)0x00000000U       /*!< HSE Bypass is not enabled                */
-#define LL_UTILS_HSEBYPASS_ON         (uint32_t)0x00000001U       /*!< HSE Bypass is enabled                    */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
 /**
   * @}
   */
@@ -220,6 +218,7 @@
   return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
 }
 
+
 /**
   * @}
   */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_wwdg.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_wwdg.h	Thu Apr 19 17:12:19 2018 +0100
@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32l1xx_ll_wwdg.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    01-July-2016
   * @brief   Header file of WWDG LL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -82,7 +80,7 @@
 /** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER
 * @{
 */
-#define LL_WWDG_PRESCALER_1                (uint32_t)0x00000000U                                   /*!< WWDG counter clock = (PCLK1/4096)/1 */
+#define LL_WWDG_PRESCALER_1                0x00000000U                                             /*!< WWDG counter clock = (PCLK1/4096)/1 */
 #define LL_WWDG_PRESCALER_2                WWDG_CFR_WDGTB_0                                        /*!< WWDG counter clock = (PCLK1/4096)/2 */
 #define LL_WWDG_PRESCALER_4                WWDG_CFR_WDGTB_1                                        /*!< WWDG counter clock = (PCLK1/4096)/4 */
 #define LL_WWDG_PRESCALER_8                (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                   /*!< WWDG counter clock = (PCLK1/4096)/8 */

--- a/targets/TARGET_STM/TARGET_STM32L1/device/system_stm32l1xx.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/device/system_stm32l1xx.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32l1xx.c
   * @author  MCD Application Team
-  * @version V2.2.0
-  * @date    01-July-2016
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *             
   *   This file provides two functions and one global variable to be called from 
@@ -23,7 +21,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -80,12 +78,12 @@
   * @{
   */
 #if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
+  #define HSE_VALUE    ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz.
                                                 This value can be provided and adapted by the user application. */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
+  #define HSI_VALUE    ((uint32_t)8000000U) /*!< Default value of the Internal oscillator in Hz.
                                                 This value can be provided and adapted by the user application. */
 #endif /* HSI_VALUE */
 
@@ -96,7 +94,7 @@
 /*!< Uncomment the following line if you need to relocate your vector Table in
      Internal SRAM. */ 
 /* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
+#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field. 
                                   This value must be a multiple of 0x200. */
 /**
   * @}
@@ -121,10 +119,10 @@
                is no need to call the 2 first functions listed above, since SystemCoreClock
                variable is updated automatically.
   */
-uint32_t SystemCoreClock        = 2097000;
-const uint8_t PLLMulTable[9]    = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
+uint32_t SystemCoreClock        = 2097000U;
+const uint8_t PLLMulTable[9]    = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U};
+const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
+const uint8_t APBPrescTable[8]  = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
 
 /**
   * @}

--- a/targets/TARGET_STM/TARGET_STM32L1/spi_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L1/spi_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -59,7 +59,9 @@
 			spi_hz = HAL_RCC_GetPCLK2Freq();
 			break;
 		case SPI_2:
-		case SPI_3:
+#ifdef SPI_3
+        case SPI_3:
+#endif
 			/* SPI_2, SPI_3. Source CLK is PCKL1 */
 			spi_hz = HAL_RCC_GetPCLK1Freq();
 			break;

--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L433xC/TARGET_NUCLEO_L433RC_P/PinNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -111,7 +111,6 @@
   PC_14 = 0x2E,
   PC_15 = 0x2F,
 
-    
   PD_2  = 0x32,
 #ifdef STM32L433_100PINS // LQFP100 or UFBGA100 versions
   PD_0  = 0x30,
@@ -165,10 +164,6 @@
   A3          = PC_2,
   A4          = PC_1,
   A5          = PC_0,
-    
-  A6          = PA_7,
-  A7          = PA_2,
-    
   D0          = PA_2,
   D1          = PA_3,
   D2          = PA_12,
@@ -183,8 +178,10 @@
   D11         = PB_15,
   D12         = PB_14,
   D13         = PB_13,
+  D14         = PB_7,
+  D15         = PB_8,
 
-    // STDIO for console print
+  // STDIO for console print
 #ifdef MBED_CONF_TARGET_STDIO_UART_TX
     STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
 #else
@@ -197,12 +194,12 @@
 #endif
 
   // Generic signals namings
-  LED1        = PA_5,
-  LED2        = PA_5,
-  LED3        = PA_5,
-  LED4        = PA_5,
+  LED1        = PB_13,
+  LED2        = PB_13,
+  LED3        = PB_13,
+  LED4        = PB_13,
   USER_BUTTON = PC_13,
-  BUTTON1 = USER_BUTTON,
+  BUTTON1     = USER_BUTTON,
   SERIAL_TX   = STDIO_UART_TX,
   SERIAL_RX   = STDIO_UART_RX,
   USBTX       = STDIO_UART_TX,
@@ -215,7 +212,7 @@
   SPI_CS      = D10,
   PWM_OUT     = D9,
 
-  //USB pins
+  // USB pins
   USB_DM = PA_11,
   USB_DP = PA_12,
   USB_NOE = PA_13,

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,96 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE,
+    ADC_2 = (int)ADC2_BASE,
+    ADC_3 = (int)ADC3_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1 = (int)USART1_BASE,
+    UART_2 = (int)USART2_BASE,
+    UART_3 = (int)USART3_BASE,
+    UART_4 = (int)UART4_BASE,
+    UART_5 = (int)UART5_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE,
+    SPI_3 = (int)SPI3_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE,
+    I2C_3 = (int)I2C3_BASE,
+    I2C_4 = (int)I2C4_BASE
+} I2CName;
+
+typedef enum {
+    PWM_1  = (int)TIM1_BASE,
+    PWM_2  = (int)TIM2_BASE,
+    PWM_3  = (int)TIM3_BASE,
+    PWM_4  = (int)TIM4_BASE,
+    PWM_5  = (int)TIM5_BASE,
+    PWM_8  = (int)TIM8_BASE,
+    PWM_15 = (int)TIM15_BASE,
+    PWM_16 = (int)TIM16_BASE,
+    PWM_17 = (int)TIM17_BASE
+} PWMName;
+
+typedef enum {
+    CAN_1 = (int)CAN1_BASE,
+    CAN_2 = (int)CAN2_BASE
+} CANName;
+
+typedef enum {
+    QSPI_1 = (int)QSPI_BASE
+} QSPIName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PeripheralPins.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,476 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentioned Px_y_ALTz are alternative possibilities which use other
+//   HW peripheral instances. You can use them the same way as any other "normal"
+//   pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+//   pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+//   the comment "Connected to xxx". The pin function may not work properly in this
+//   case. These pins may not be displayed on the board pinout image on mbed.org.
+//   Please read the board reference manual and schematic for more information.
+//
+// - Warning: some pins are connected to the default STDIO_UART_TX and STDIO_UART_RX pins.
+//   See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//==============================================================================
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+    {PA_0,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+    {PA_0_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_IN5
+    {PA_1,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6 - ARDUINO_A4
+    {PA_1_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_IN6 - ARDUINO_A4
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+    {PA_2,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7 - Connected to STDIO_UART_TX
+    {PA_2_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_IN7 - Connected to STDIO_UART_TX
+#endif
+    {PA_3,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+    {PA_3_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_IN8
+    {PA_4,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+    {PA_4_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_IN9
+    {PA_5,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10 - ARDUINO_D13
+    {PA_5_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_IN10 - ARDUINO_D13
+    {PA_6,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+    {PA_6_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_IN11
+    {PA_7,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+    {PA_7_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_IN12
+    {PB_0,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {PB_0_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_IN15
+    {PB_1,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_IN16
+    {PB_1_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC2_IN16
+    {PC_0,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1 - ARDUINO_A5
+    {PC_0_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_IN1 - ARDUINO_A5
+    {PC_0_ALT1,  ADC_3,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_IN1 - ARDUINO_A5
+    {PC_1,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2 - ARDUINO_A1
+    {PC_1_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_IN2 - ARDUINO_A1
+    {PC_1_ALT1,  ADC_3,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_IN2 - ARDUINO_A1
+    {PC_2,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+    {PC_2_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_IN3
+    {PC_2_ALT1,  ADC_3,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_IN3
+    {PC_3,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4 - ARDUINO_A2
+    {PC_3_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_IN4 - ARDUINO_A2
+    {PC_3_ALT1,  ADC_3,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4 - ARDUINO_A2
+    {PC_4,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13 - ARDUINO_A0
+    {PC_4_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_IN13 - ARDUINO_A0
+    {PC_5,       ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+    {PC_5_ALT0,  ADC_2,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_IN14
+    {PF_3,       ADC_3,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6
+    {PF_4,       ADC_3,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7
+    {PF_5,       ADC_3,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8
+    {PF_10,      ADC_3,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_IN13 - ARDUINO_A3
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+    {ADC_VREF,   ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0,  0, 0)},
+    {ADC_TEMP,   ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)},
+    {ADC_VBAT,   ADC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)},
+    {NC, NC, 0}
+};
+
+//*** DAC ***
+
+MBED_WEAK const PinMap PinMap_DAC[] = {
+    {PA_4,       DAC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1
+    {PA_5,       DAC_1,    STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 - ARDUINO_D13
+    {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+    {PB_4,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO_D12
+    {PB_7,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO_D14
+    {PB_7_ALT0,  I2C_4,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)}, // ARDUINO_D14
+    {PB_9,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO_D5
+    {PB_11,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_11_ALT0, I2C_4,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)},
+    {PB_14,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PC_1,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO_A1
+    {PC_1_ALT0,  I2C_4,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)}, // ARDUINO_A1
+    {PC_9,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C3)},
+    {PD_13,      I2C_4,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+    {PF_0,       I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PF_15,      I2C_4,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+    {PG_8,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO_D0
+    {PG_13,      I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO_D2
+    {PH_5,       I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PH_8,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+    {PA_7,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {PB_6,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_6_ALT0,  I2C_4,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C4)},
+    {PB_8,       I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, // ARDUINO_D15
+    {PB_10,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PB_10_ALT0, I2C_4,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF3_I2C4)},
+    {PB_13,      I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, // Connected to LED1
+    {PC_0,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO_A5
+    {PC_0_ALT0,  I2C_4,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF2_I2C4)}, // ARDUINO_A5
+    {PD_12,      I2C_4,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+    {PF_1,       I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PF_14,      I2C_4,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)},
+    {PG_7,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, // ARDUINO_D1
+    {PG_14,      I2C_1,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PH_4,       I2C_2,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+    {PH_7,       I2C_3,    STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+    {NC, NC, 0}
+};
+
+//*** PWM ***
+// Warning: Pins using PWM_5 cannot be used as TIMER5 is already used by the ticker.
+MBED_WEAK const PinMap PinMap_PWM[] = {
+    {PA_0,       PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+//  {PA_0,       PWM_5,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - already used by the ticker
+    {PA_1,       PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 - ARDUINO_A4
+//  {PA_1,       PWM_5,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - already used by the ticker
+    {PA_1_ALT0,  PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N - ARDUINO_A4
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+    {PA_2,       PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 - Connected to STDIO_UART_TX
+//  {PA_2,       PWM_5,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - already used by the ticker
+    {PA_2_ALT0,  PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1 - Connected to STDIO_UART_TX
+#endif
+    {PA_3,       PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+//  {PA_3,       PWM_5,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - already used by the ticker
+    {PA_3_ALT0,  PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+    {PA_5,       PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - ARDUINO_D13
+    {PA_5_ALT0,  PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - ARDUINO_D13
+    {PA_6,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+    {PA_6_ALT0,  PWM_16,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+    {PA_7,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+    {PA_7_ALT0,  PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+    {PA_7_ALT1,  PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
+    {PA_7_ALT2,  PWM_17,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
+    {PA_8,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+    {PA_9,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+    {PA_10,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+    {PA_11,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+    {PA_15,      PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 - ARDUINO_D10
+    {PB_0,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+    {PB_0_ALT0,  PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+    {PB_0_ALT1,  PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+    {PB_1,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+    {PB_1_ALT0,  PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+    {PB_1_ALT1,  PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+    {PB_3,       PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+    {PB_4,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 - ARDUINO_D12
+    {PB_5,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 - ARDUINO_D11
+    {PB_6,       PWM_4,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+    {PB_6_ALT0,  PWM_16,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 1)}, // TIM16_CH1N
+    {PB_7,       PWM_4,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 - ARDUINO_D14
+    {PB_7_ALT0,  PWM_17,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 1)}, // TIM17_CH1N - ARDUINO_D14
+    {PB_8,       PWM_4,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 - ARDUINO_D15
+    {PB_8_ALT0,  PWM_16,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1 - ARDUINO_D15
+    {PB_9,       PWM_4,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 - ARDUINO_D5
+    {PB_9_ALT0,  PWM_17,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1 - ARDUINO_D5
+    {PB_10,      PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+    {PB_11,      PWM_2,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+    {PB_13,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N - Connected to LED1
+    {PB_13_ALT0, PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N - Connected to LED1
+    {PB_14,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+    {PB_14_ALT0, PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+    {PB_14_ALT1, PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+    {PB_15,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+    {PB_15_ALT0, PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
+    {PB_15_ALT1, PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+    {PC_6,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+    {PC_6_ALT0,  PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+    {PC_7,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+    {PC_7_ALT0,  PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
+    {PC_8,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+    {PC_8_ALT0,  PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+    {PC_9,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+    {PC_9_ALT0,  PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+    {PD_12,      PWM_4,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+    {PD_13,      PWM_4,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+    {PD_14,      PWM_4,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+    {PD_15,      PWM_4,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+    {PE_0,       PWM_16,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM16, 1, 0)}, // TIM16_CH1
+    {PE_1,       PWM_17,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM17, 1, 0)}, // TIM17_CH1
+    {PE_3,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+    {PE_4,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+    {PE_5,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+    {PE_6,       PWM_3,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+    {PE_8,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+    {PE_9,       PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+    {PE_10,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+    {PE_11,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+    {PE_12,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+    {PE_13,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+    {PE_14,      PWM_1,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+    {PF_10,      PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2 - ARDUINO_A3
+    {PG_9,       PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 1)}, // TIM15_CH1N
+    {PG_10,      PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 1, 0)}, // TIM15_CH1
+    {PG_11,      PWM_15,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_TIM15, 2, 0)}, // TIM15_CH2
+//  {PH_10,      PWM_5,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 - already used by the ticker
+//  {PH_11,      PWM_5,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 - already used by the ticker
+//  {PH_12,      PWM_5,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 - already used by the ticker
+    {PH_13,      PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N - ARDUINO_D9
+    {PH_14,      PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
+    {PH_15,      PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N - ARDUINO_D3
+//  {PI_0,       PWM_5,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 - already used by the ticker
+    {PI_2,       PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4
+    {PI_5,       PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
+    {PI_6,       PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 - ARDUINO_D6
+    {PI_7,       PWM_8,    STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3
+    {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+    {PA_0,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PA_2,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_TX (default)
+    {PA_2_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to STDIO_UART_TX
+    {PA_9,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_6,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_10,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_11,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PC_1,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO_A1
+    {PC_4,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO_A0
+    {PC_10,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_10_ALT0, UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PC_12,      UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PD_5,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_8,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PG_7,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO_D1
+    {PG_9,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+    {PA_1,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // ARDUINO_A4
+    {PA_3,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_3_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PA_10,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15,      UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_USART2)}, // ARDUINO_D10
+    {PB_7,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // ARDUINO_D14
+    {PB_10,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_11,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_0,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO_A5
+    {PC_5,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_11,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PC_11_ALT0, UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
+    {PD_2,       UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
+    {PD_6,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // Connected to STDIO_UART_RX (default)
+    {PD_9,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PG_8,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO_D0
+    {PG_10,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+    {PA_1,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, // ARDUINO_A4
+    {PA_12,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PA_15,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // ARDUINO_D10
+    {PA_15_ALT0, UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // ARDUINO_D10
+    {PB_1,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PB_1_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_3,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,       UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // ARDUINO_D12
+    {PB_12,      LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PB_14,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_2,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PD_4,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_12,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PG_6,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // ARDUINO_D7
+    {PG_12,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+    {PA_0,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PA_6,       UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PA_6_ALT0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PA_11,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {PB_4,       UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // ARDUINO_D12
+    {PB_5,       UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, // ARDUINO_D11
+    {PB_7,       UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, // ARDUINO_D14
+    {PB_13,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, // Connected to LED1
+    {PB_13_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)}, // Connected to LED1
+    {PD_3,       UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+    {PD_11,      UART_3,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
+    {PG_5,       LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART1)},
+    {PG_11,      UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+    {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_12,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_5,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO_D11
+    {PB_5_ALT0,  SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // ARDUINO_D11
+    {PB_15,      SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_1,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)}, // ARDUINO_A1
+    {PC_3,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO_A2
+    {PC_12,      SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PD_4,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PE_15,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_4,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_11,      SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PI_3,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_11,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_4,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO_D12
+    {PB_4_ALT0,  SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // ARDUINO_D12
+    {PB_14,      SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_2,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PC_11,      SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PD_3,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PE_14,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_3,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_10,      SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PI_2,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+    {PA_1,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO_A4
+    {PA_5,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO_D13
+    {PA_9,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)},
+    {PB_3,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_3_ALT0,  SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PB_10,      SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13,      SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // Connected to LED1
+    {PC_10,      SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PD_1,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PD_3,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_SPI2)},
+    {PE_13,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_2,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_9,       SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PI_1,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PA_4,       SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PA_15,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)}, // ARDUINO_D10
+    {PA_15_ALT0, SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)}, // ARDUINO_D10
+    {PB_0,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PB_9,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)}, // ARDUINO_D5
+    {PB_12,      SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PD_0,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PE_12,      SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_5,       SPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+    {PG_12,      SPI_3,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+    {PI_0,       SPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {NC, NC, 0}
+};
+
+//*** CAN ***
+
+MBED_WEAK const PinMap PinMap_CAN_RD[] = {
+    {PA_11,      CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PB_5,       CAN_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF3_CAN2)}, // ARDUINO_D11
+    {PB_8,       CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO_D15
+    {PB_12,      CAN_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)},
+    {PD_0,       CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PI_9,       CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to JOYSTICK_LEFT
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_CAN_TD[] = {
+    {PA_12,      CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PB_6,       CAN_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_CAN2)},
+    {PB_9,       CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO_D5
+    {PB_13,      CAN_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_CAN2)}, // Connected to LED1
+    {PD_1,       CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)},
+    {PH_13,      CAN_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // ARDUINO_D9
+    {NC, NC, 0}
+};
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA[] = {
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+    {PA_2,       QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // Connected to STDIO_UART_TX
+#endif
+    {PA_6,       QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PA_7,       QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PB_0,       QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PB_1,       QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PB_11,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+//  {PC_1,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A1
+//  {PC_2,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+//  {PC_3,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A2
+//  {PC_4,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // ARDUINO_A0
+//  {PC_11,      QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)},
+//  {PD_3,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+//  {PD_4,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+//  {PD_5,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+//  {PD_6,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)}, // Connected to STDIO_UART_RX
+//  {PD_6_ALT0,  QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // Connected to STDIO_UART_RX
+#endif
+//  {PD_7,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PE_11,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PE_12,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PE_13,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PE_14,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PE_15,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+//  {PH_2,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)},
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+    {PA_3,       QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PB_10,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PE_10,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PF_10,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_QUADSPI)}, // ARDUINO_A3
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+    {PA_2,       QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // Connected to STDIO_UART_TX
+#endif
+    {PB_11,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+//  {PC_11,      QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_QUADSPI)},
+//  {PD_3,       QSPI_2,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {PE_11,      QSPI_1,    STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)},
+    {NC, NC, 0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/PinNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,313 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2018, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ALT0  = 0x100,
+    ALT1  = 0x200,
+    ALT2  = 0x300,
+    ALT3  = 0x400
+} ALTx;
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_0_ALT0 = PA_0|ALT0,
+    PA_1  = 0x01,
+    PA_1_ALT0 = PA_1|ALT0,
+    PA_1_ALT1 = PA_1|ALT1,
+    PA_2  = 0x02,
+    PA_2_ALT0 = PA_2|ALT0,
+    PA_2_ALT1 = PA_2|ALT1,
+    PA_3  = 0x03,
+    PA_3_ALT0 = PA_3|ALT0,
+    PA_3_ALT1 = PA_3|ALT1,
+    PA_4  = 0x04,
+    PA_4_ALT0 = PA_4|ALT0,
+    PA_5  = 0x05,
+    PA_5_ALT0 = PA_5|ALT0,
+    PA_6  = 0x06,
+    PA_6_ALT0 = PA_6|ALT0,
+    PA_7  = 0x07,
+    PA_7_ALT0 = PA_7|ALT0,
+    PA_7_ALT1 = PA_7|ALT1,
+    PA_7_ALT2 = PA_7|ALT2,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+    PA_15_ALT0 = PA_15|ALT0,
+
+    PB_0  = 0x10,
+    PB_0_ALT0 = PB_0|ALT0,
+    PB_0_ALT1 = PB_0|ALT1,
+    PB_1  = 0x11,
+    PB_1_ALT0 = PB_1|ALT0,
+    PB_1_ALT1 = PB_1|ALT1,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_3_ALT0 = PB_3|ALT0,
+    PB_4  = 0x14,
+    PB_4_ALT0 = PB_4|ALT0,
+    PB_5  = 0x15,
+    PB_5_ALT0 = PB_5|ALT0,
+    PB_6  = 0x16,
+    PB_6_ALT0 = PB_6|ALT0,
+    PB_7  = 0x17,
+    PB_7_ALT0 = PB_7|ALT0,
+    PB_8  = 0x18,
+    PB_8_ALT0 = PB_8|ALT0,
+    PB_9  = 0x19,
+    PB_9_ALT0 = PB_9|ALT0,
+    PB_10 = 0x1A,
+    PB_10_ALT0 = PB_10|ALT0,
+    PB_11 = 0x1B,
+    PB_11_ALT0 = PB_11|ALT0,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_13_ALT0 = PB_13|ALT0,
+    PB_14 = 0x1E,
+    PB_14_ALT0 = PB_14|ALT0,
+    PB_14_ALT1 = PB_14|ALT1,
+    PB_15 = 0x1F,
+    PB_15_ALT0 = PB_15|ALT0,
+    PB_15_ALT1 = PB_15|ALT1,
+
+    PC_0  = 0x20,
+    PC_0_ALT0 = PC_0|ALT0,
+    PC_0_ALT1 = PC_0|ALT1,
+    PC_1  = 0x21,
+    PC_1_ALT0 = PC_1|ALT0,
+    PC_1_ALT1 = PC_1|ALT1,
+    PC_2  = 0x22,
+    PC_2_ALT0 = PC_2|ALT0,
+    PC_2_ALT1 = PC_2|ALT1,
+    PC_3  = 0x23,
+    PC_3_ALT0 = PC_3|ALT0,
+    PC_3_ALT1 = PC_3|ALT1,
+    PC_4  = 0x24,
+    PC_4_ALT0 = PC_4|ALT0,
+    PC_5  = 0x25,
+    PC_5_ALT0 = PC_5|ALT0,
+    PC_6  = 0x26,
+    PC_6_ALT0 = PC_6|ALT0,
+    PC_7  = 0x27,
+    PC_7_ALT0 = PC_7|ALT0,
+    PC_8  = 0x28,
+    PC_8_ALT0 = PC_8|ALT0,
+    PC_9  = 0x29,
+    PC_9_ALT0 = PC_9|ALT0,
+    PC_10 = 0x2A,
+    PC_10_ALT0 = PC_10|ALT0,
+    PC_11 = 0x2B,
+    PC_11_ALT0 = PC_11|ALT0,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_0  = 0x30,
+    PD_1  = 0x31,
+    PD_2  = 0x32,
+    PD_3  = 0x33,
+    PD_4  = 0x34,
+    PD_5  = 0x35,
+    PD_6  = 0x36,
+    PD_7  = 0x37,
+    PD_8  = 0x38,
+    PD_9  = 0x39,
+    PD_10 = 0x3A,
+    PD_11 = 0x3B,
+    PD_12 = 0x3C,
+    PD_13 = 0x3D,
+    PD_14 = 0x3E,
+    PD_15 = 0x3F,
+
+    PE_0  = 0x40,
+    PE_1  = 0x41,
+    PE_2  = 0x42,
+    PE_3  = 0x43,
+    PE_4  = 0x44,
+    PE_5  = 0x45,
+    PE_6  = 0x46,
+    PE_7  = 0x47,
+    PE_8  = 0x48,
+    PE_9  = 0x49,
+    PE_10 = 0x4A,
+    PE_11 = 0x4B,
+    PE_12 = 0x4C,
+    PE_13 = 0x4D,
+    PE_14 = 0x4E,
+    PE_15 = 0x4F,
+
+    PF_0  = 0x50,
+    PF_1  = 0x51,
+    PF_2  = 0x52,
+    PF_3  = 0x53,
+    PF_4  = 0x54,
+    PF_5  = 0x55,
+    PF_10 = 0x5A,
+    PF_11 = 0x5B,
+    PF_12 = 0x5C,
+    PF_13 = 0x5D,
+    PF_14 = 0x5E,
+    PF_15 = 0x5F,
+
+    PG_0  = 0x60,
+    PG_1  = 0x61,
+    PG_2  = 0x62,
+    PG_3  = 0x63,
+    PG_4  = 0x64,
+    PG_5  = 0x65,
+    PG_6  = 0x66,
+    PG_7  = 0x67,
+    PG_8  = 0x68,
+    PG_9  = 0x69,
+    PG_10 = 0x6A,
+    PG_11 = 0x6B,
+    PG_12 = 0x6C,
+    PG_13 = 0x6D,
+    PG_14 = 0x6E,
+    PG_15 = 0x6F,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+    PH_2  = 0x72,
+    PH_3  = 0x73,
+    PH_4  = 0x74,
+    PH_5  = 0x75,
+    PH_6  = 0x76,
+    PH_7  = 0x77,
+    PH_8  = 0x78,
+    PH_9  = 0x79,
+    PH_10 = 0x7A,
+    PH_11 = 0x7B,
+    PH_12 = 0x7C,
+    PH_13 = 0x7D,
+    PH_14 = 0x7E,
+    PH_15 = 0x7F,
+
+    PI_0  = 0x80,
+    PI_1  = 0x81,
+    PI_2  = 0x82,
+    PI_3  = 0x83,
+    PI_4  = 0x84,
+    PI_5  = 0x85,
+    PI_6  = 0x86,
+    PI_7  = 0x87,
+    PI_8  = 0x88,
+    PI_9  = 0x89,
+    PI_10 = 0x8A,
+    PI_11 = 0x8B,
+    PI_12 = 0x8C,
+    PI_13 = 0x8D,
+    PI_14 = 0x8E,
+    PI_15 = 0x8F,
+
+    // ADC internal channels
+    ADC_TEMP = 0xF0,
+    ADC_VREF = 0xF1,
+    ADC_VBAT = 0xF2,
+
+    // Arduino connector
+    A0          = PC_4,
+    A1          = PC_1,
+    A2          = PC_3,
+    A3          = PF_10,
+    A4          = PA_1, 
+    A5          = PC_0, 
+    D0          = PG_8,
+    D1          = PG_7,
+    D2          = PG_13,
+    D3          = PH_15,
+    D4          = PI_11,
+    D5          = PB_9,
+    D6          = PI_6,
+    D7          = PG_6,
+    D8          = PG_15,
+    D9          = PH_13,
+    D10         = PA_15,
+    D11         = PB_5,
+    D12         = PB_4,
+    D13         = PA_5,
+    D14         = PB_7,
+    D15         = PB_8,
+
+    // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+    STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+    STDIO_UART_TX = PA_2,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+    STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+    STDIO_UART_RX = PD_6,
+#endif
+
+    // Generic signals
+    LED1        = PB_13, // Green LD2 on board
+    LED2        = LED1,
+    LED3        = LED1,
+    LED4        = LED1,
+    USER_BUTTON = PC_13, // Joystick Center
+    BUTTON1 = USER_BUTTON,
+    SERIAL_TX   = STDIO_UART_TX, // Virtual Com Port 
+    SERIAL_RX   = STDIO_UART_RX, // Virtual Com Port
+    USBTX       = STDIO_UART_TX, // Virtual Com Port
+    USBRX       = STDIO_UART_RX, // Virtual Com Port
+    I2C_SCL     = D15, 
+    I2C_SDA     = D14,
+    SPI_MOSI    = D11,
+    SPI_MISO    = D12,
+    SPI_SCK     = D13,
+    SPI_CS      = D10,
+    PWM_OUT     = D9,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_DISCO_L496AG/system_clock.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,382 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+  *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+  *                     | 3- USE_PLL_HSI (internal 16 MHz)
+  *                     | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 80
+  * AHBCLK (MHz)        | 80
+  * APB1CLK (MHz)       | 80
+  * APB2CLK (MHz)       | 80
+  * USB capable         | YES
+  *-----------------------------------------------------------------------------
+**/
+
+#include "stm32l4xx.h"
+#include "nvic_addr.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI      0x2 // Use HSI internal clock
+#define USE_PLL_MSI      0x1 // Use MSI internal clock
+
+#define DEBUG_MCO        (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI)
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+uint8_t SetSysClock_PLL_MSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
+
+
+/**
+  * @brief  Setup the microcontroller system.
+  * @param  None
+  * @retval None
+  */
+
+void SystemInit(void)
+{
+    /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
+#endif
+    /* Reset the RCC clock configuration to the default reset state ------------*/
+    /* Set MSION bit */
+    RCC->CR |= RCC_CR_MSION;
+
+    /* Reset CFGR register */
+    RCC->CFGR = 0x00000000;
+
+    /* Reset HSEON, CSSON , HSION, and PLLON bits */
+    RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+    /* Reset PLLCFGR register */
+    RCC->PLLCFGR = 0x00001000;
+
+    /* Reset HSEBYP bit */
+    RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+    /* Disable all interrupts */
+    RCC->CIER = 0x00000000;
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
+  *               AHB/APBx prescalers and Flash settings
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+    /* 1- Try to start with HSE and external clock */
+    if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+    {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+        /* 2- If fail try to start with HSE and external xtal */
+        if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+        {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+            /* 3- If fail start with HSI clock */
+            if (SetSysClock_PLL_HSI()==0)
+#endif
+            {
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+                /* 4- If fail start with MSI clock */
+                if (SetSysClock_PLL_MSI() == 0)
+#endif
+                {
+                    while(1) {
+                        MBED_ASSERT(1);
+                    }
+                }
+            }
+        }
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 1
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
+#endif
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Used to gain time after DeepSleep in case HSI is used
+    if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
+        return 0;
+    }
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSE oscillator and activate PLL with HSE as source
+    RCC_OscInitStruct.OscillatorType        = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+    if (bypass == 0) {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+    } else {
+        RCC_OscInitStruct.HSEState            = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+    }
+    RCC_OscInitStruct.HSIState              = RCC_HSI_OFF;
+    RCC_OscInitStruct.PLL.PLLSource         = RCC_PLLSOURCE_HSE; // 8 MHz
+    RCC_OscInitStruct.PLL.PLLState          = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLM              = 1; // VCO input clock = 8 MHz (8 MHz / 1)
+    RCC_OscInitStruct.PLL.PLLN              = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP              = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ              = 2;
+    RCC_OscInitStruct.PLL.PLLR              = 2; // PLL clock = 80 MHz (160 MHz / 2)
+
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    /* Select HSI as clock source for LPUART1 */
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+    RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 2
+    if (bypass == 0)
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+    else
+        HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/*            PLL (clocked by HSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0};
+
+    // Select MSI as system clock source to allow modification of the PLL configuration
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
+
+    // Enable HSI oscillator and activate PLL with HSI as source
+    RCC_OscInitStruct.OscillatorType       = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue  = RCC_HSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.PLL.PLLState         = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource        = RCC_PLLSOURCE_HSI; // 16 MHz
+    RCC_OscInitStruct.PLL.PLLM             = 2; // VCO input clock = 8 MHz (16 MHz / 2)
+    RCC_OscInitStruct.PLL.PLLN             = 20; // VCO output clock = 160 MHz (8 MHz * 20)
+    RCC_OscInitStruct.PLL.PLLP             = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7)
+    RCC_OscInitStruct.PLL.PLLQ             = 2;
+    RCC_OscInitStruct.PLL.PLLR             = 2; // PLL clock = 80 MHz (160 MHz / 2)
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 80 MHz
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 80 MHz
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
+    RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Disable MSI Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState       = RCC_MSI_OFF;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    /* Select HSI as clock source for LPUART1 */
+    RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+    RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+    if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 3
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_MSI)
+/******************************************************************************/
+/*            PLL (clocked by MSI) used as System clock source                */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_MSI(void)
+{
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+    // Enable LSE Oscillator to automatically calibrate the MSI clock
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // No PLL update
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
+    }
+
+    HAL_RCCEx_DisableLSECSS();
+    /* Enable MSI Oscillator and activate PLL with MSI as source */
+    RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.MSIState             = RCC_MSI_ON;
+    RCC_OscInitStruct.HSEState             = RCC_HSE_OFF;
+    RCC_OscInitStruct.HSIState             = RCC_HSI_OFF;
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange       = RCC_MSIRANGE_11; /* 48 MHz */
+    RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_MSI;
+    RCC_OscInitStruct.PLL.PLLM            = 6;    /* 8 MHz */
+    RCC_OscInitStruct.PLL.PLLN            = 40;   /* 320 MHz */
+    RCC_OscInitStruct.PLL.PLLP            = 7;    /* 45 MHz */
+    RCC_OscInitStruct.PLL.PLLQ            = 4;    /* 80 MHz */
+    RCC_OscInitStruct.PLL.PLLR            = 4;    /* 80 MHz */
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+    /* Enable MSI Auto-calibration through LSE */
+    HAL_RCCEx_EnableMSIPLLMode();
+    /* Select MSI output as USB clock source */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */
+    HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+
+    // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+    RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+    RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */
+    RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         /* 80 MHz */
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           /* 80 MHz */
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    /* Select LSE as clock source for LPUART1 */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+    PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+        return 0; // FAIL
+    }
+
+    // Output clock on MCO1 pin(PA8) for debugging purpose
+#if DEBUG_MCO == 4
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz
+#endif
+
+    return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

--- a/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/analogin_device.c	Thu Apr 19 17:12:19 2018 +0100
@@ -105,9 +105,16 @@
     ADC_ChannelConfTypeDef sConfig = {0};
 
     // Configure ADC channel
+    sConfig.Rank         = ADC_REGULAR_RANK_1;
+    sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5; //  default value (1.5 us for 80MHz clock)
+    sConfig.SingleDiff   = ADC_SINGLE_ENDED;
+    sConfig.OffsetNumber = ADC_OFFSET_NONE;
+    sConfig.Offset       = 0;
+
     switch (obj->channel) {
         case 0:
             sConfig.Channel = ADC_CHANNEL_VREFINT;
+            sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; // Minimum ADC sampling time when reading the internal reference voltage is 4us
             break;
         case 1:
             sConfig.Channel = ADC_CHANNEL_1;
@@ -159,20 +166,16 @@
             break;
         case 17:
             sConfig.Channel = ADC_CHANNEL_TEMPSENSOR;
+            sConfig.SamplingTime = ADC_SAMPLETIME_247CYCLES_5; // Minimum ADC sampling time when reading the temperature is 5us
             break;
         case 18:
             sConfig.Channel = ADC_CHANNEL_VBAT;
+            sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5; // Minimum ADC sampling time when reading the VBAT is 12us
             break;
         default:
             return 0;
     }
 
-    sConfig.Rank         = ADC_REGULAR_RANK_1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_47CYCLES_5;
-    sConfig.SingleDiff   = ADC_SINGLE_ENDED;
-    sConfig.OffsetNumber = ADC_OFFSET_NONE;
-    sConfig.Offset       = 0;
-
     HAL_ADC_ConfigChannel(&obj->handle, &sConfig);
 
     HAL_ADC_Start(&obj->handle); // Start conversion

--- a/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -2312,7 +2312,6 @@
     /* Parameters update conditioned to ADC state:                              */
     /* Parameters that can be updated only when ADC is disabled:                */
     /*  - Single or differential mode                                           */
-    /*  - Internal measurement channels: Vbat/VrefInt/TempSensor                */
     if (ADC_IS_ENABLE(hadc) == RESET)
     {
       /* Set mode single-ended or differential input of the selected ADC channel */
@@ -2325,71 +2324,56 @@
         LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime);
       }
       
-      /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
-      /* If internal channel selected, enable dedicated internal buffers and    */
-      /* paths.                                                                 */
-      /* Note: these internal measurement paths can be disabled using           */
-      /* HAL_ADC_DeInit().                                                      */
-         
-      /* Configuration of common ADC parameters                                 */
-      /* If the requested internal measurement path has already been enabled,   */
-      /* bypass the configuration processing.                                   */
-      if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
-            ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) ||
-          ( (sConfig->Channel == ADC_CHANNEL_VBAT)       &&
-            ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U))       ||
-          ( (sConfig->Channel == ADC_CHANNEL_VREFINT)    &&
-            ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U))
-         )
+    }
+
+    /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
+    /* If internal channel selected, enable dedicated internal buffers and    */
+    /* paths.                                                                 */
+    /* Note: these internal measurement paths can be disabled using           */
+    /* HAL_ADC_DeInit().                                                      */
+
+    /* Configuration of common ADC parameters                                 */
+    /* If the requested internal measurement path has already been enabled,   */
+    /* bypass the configuration processing.                                   */
+    if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
+          ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) ||
+        ( (sConfig->Channel == ADC_CHANNEL_VBAT)       &&
+          ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U))       ||
+        ( (sConfig->Channel == ADC_CHANNEL_VREFINT)    &&
+          ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U))
+       )
+    {
+      /* Configuration of common ADC parameters (continuation)                */
+
+      if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
       {
-        /* Configuration of common ADC parameters (continuation)                */
-  
-        /* Software is allowed to change common parameters only when all ADCs   */
-        /* of the common group are disabled.                                    */
-        if ((ADC_IS_ENABLE(hadc) == RESET)   &&
-           (ADC_ANY_OTHER_ENABLED(hadc) == RESET) )
+        if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
         {
-          if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
+
+          /* Delay for temperature sensor stabilization time */
+          /* Wait loop initialization and execution */
+          /* Note: Variable divided by 2 to compensate partially          */
+          /*       CPU processing cycles.                                 */
+          wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2)));
+          while(wait_loop_index != 0)
           {
-            if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 
-            {
-              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
-              
-              /* Delay for temperature sensor stabilization time */
-              /* Wait loop initialization and execution */
-              /* Note: Variable divided by 2 to compensate partially          */
-              /*       CPU processing cycles.                                 */
-              wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2)));
-              while(wait_loop_index != 0)
-              {
-                wait_loop_index--;
-              }
-            }
-          }
-          else if (sConfig->Channel == ADC_CHANNEL_VBAT)
-          {
-            if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
-            {
-              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
-            }
-          }
-          else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
-          {
-            if (ADC_VREFINT_INSTANCE(hadc))
-            {
-              LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
-            }
+            wait_loop_index--;
           }
         }
-        /* If the requested internal measurement path has already been          */
-        /* enabled and other ADC of the common group are enabled, internal      */
-        /* measurement paths cannot be enabled.                                 */
-        else  
+      }
+      else if (sConfig->Channel == ADC_CHANNEL_VBAT)
+      {
+        if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
         {
-          /* Update ADC state machine to error */
-          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
-          
-          tmp_hal_status = HAL_ERROR;
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
+        }
+      }
+      else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+      {
+        if (ADC_VREFINT_INSTANCE(hadc))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)));
         }
       }
     }

--- a/targets/TARGET_STM/hal_tick_16b.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/hal_tick_16b.c	Thu Apr 19 17:12:19 2018 +0100
@@ -105,7 +105,7 @@
     TimMasterHandle.Init.Prescaler     = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
     TimMasterHandle.Init.ClockDivision = 0;
     TimMasterHandle.Init.CounterMode   = TIM_COUNTERMODE_UP;
-#if !defined(TARGET_STM32L0)
+#if !defined(TARGET_STM32L0) && !defined(TARGET_STM32L1)
     TimMasterHandle.Init.RepetitionCounter = 0;
 #endif
 #ifdef TIM_AUTORELOAD_PRELOAD_DISABLE

--- a/targets/TARGET_STM/mbed_rtx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/mbed_rtx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -59,6 +59,7 @@
 
 #elif (defined(TARGET_STM32F091RC) ||\
        defined(TARGET_STM32F410RB) ||\
+       defined(TARGET_STM32L151CBA)||\
        defined(TARGET_STM32L151CC) ||\
        defined(TARGET_STM32L151RC) ||\
        defined(TARGET_STM32L152RC))
@@ -108,6 +109,7 @@
        defined(TARGET_STM32F746NG) ||\
        defined(TARGET_STM32F746ZG) ||\
        defined(TARGET_STM32F756ZG) ||\
+       defined(TARGET_STM32L496AG) ||\
        defined(TARGET_STM32L496ZG))
 #define INITIAL_SP              (0x20050000UL)
 

--- a/targets/TARGET_STM/rtc_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_STM/rtc_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -58,10 +58,9 @@
     }
 
 #if MBED_CONF_TARGET_LSE_AVAILABLE
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
     RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
     RCC_OscInitStruct.LSEState       = RCC_LSE_ON;
-    RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
 
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         error("Cannot initialize RTC with LSE\n");
@@ -81,9 +80,8 @@
     __HAL_RCC_BACKUPRESET_RELEASE();
 
     // Enable LSI clock
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
     RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-    RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
     RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         error("Cannot initialize RTC with LSI\n");
@@ -228,7 +226,10 @@
     timeinfo.tm_sec  = timeStruct.Seconds;
 
     // Convert to timestamp
-    time_t t = _rtc_mktime(&timeinfo);
+    time_t t;
+    if (_rtc_maketime(&timeinfo, &t, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
+        return 0;
+    }
 
     return t;
 }
@@ -242,7 +243,7 @@
 
     // Convert the time into a tm
     struct tm timeinfo;
-    if (_rtc_localtime(t, &timeinfo) == false) {
+    if (_rtc_localtime(t, &timeinfo, RTC_4_YEAR_LEAP_YEAR_SUPPORT) == false) {
         return;
     }
 
@@ -329,6 +330,11 @@
 
 void rtc_set_wake_up_timer(uint32_t delta)
 {
+#define RTC_CLOCK_US (((uint64_t)RTC_CLOCK << 32 ) / 1000000)
+
+    uint32_t WakeUpCounter;
+    uint32_t WakeUpClock;
+
     /* Ex for Wakeup period resolution with RTCCLK=32768 Hz :
     *    RTCCLK_DIV2: ~122us < wakeup period < ~4s
     *    RTCCLK_DIV4: ~244us < wakeup period < ~8s
@@ -337,19 +343,21 @@
     *    CK_SPRE_16BITS: 1s < wakeup period < (0xFFFF+ 1) x 1 s = 65536 s (18 hours)
     *    CK_SPRE_17BITS: 18h+1s < wakeup period < (0x1FFFF+ 1) x 1 s = 131072 s (36 hours)
     */
-    uint32_t WakeUpClock[6] = {RTC_WAKEUPCLOCK_RTCCLK_DIV2, RTC_WAKEUPCLOCK_RTCCLK_DIV4, RTC_WAKEUPCLOCK_RTCCLK_DIV8, RTC_WAKEUPCLOCK_RTCCLK_DIV16, RTC_WAKEUPCLOCK_CK_SPRE_16BITS, RTC_WAKEUPCLOCK_CK_SPRE_17BITS};
-    uint8_t ClockDiv[4] = {2, 4, 8, 16};
-    uint32_t WakeUpCounter;
-    uint8_t DivIndex = 0;
-
-    do {
-        WakeUpCounter = delta / (ClockDiv[DivIndex] * 1000000 / RTC_CLOCK);
-        DivIndex++;
-    } while ( (WakeUpCounter > 0xFFFF) && (DivIndex < 4) );
-
-    if (WakeUpCounter > 0xFFFF) {
-        WakeUpCounter = delta / 1000000;
-        DivIndex++;
+    if (delta < (0x10000 * 2 / RTC_CLOCK * 1000000) ) { // (0xFFFF + 1) * RTCCLK_DIV2 / RTC_CLOCK * 1s
+        WakeUpCounter = (((uint64_t)delta * RTC_CLOCK_US) >> 32) >> 1 ;
+        WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV2;
+    } else if (delta < (0x10000 * 4 / RTC_CLOCK * 1000000) ) {
+        WakeUpCounter = (((uint64_t)delta * RTC_CLOCK_US) >> 32) >> 2 ;
+        WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV4;
+    } else if (delta < (0x10000 * 8 / RTC_CLOCK * 1000000) ) {
+        WakeUpCounter = (((uint64_t)delta * RTC_CLOCK_US) >> 32) >> 3 ;
+        WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV8;
+    } else if (delta < (0x10000 * 16 / RTC_CLOCK * 1000000) ) {
+        WakeUpCounter = (((uint64_t)delta * RTC_CLOCK_US) >> 32) >> 4 ;
+        WakeUpClock = RTC_WAKEUPCLOCK_RTCCLK_DIV16;
+    } else {
+        WakeUpCounter = (delta / 1000000) ;
+        WakeUpClock = RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
     }
 
     irq_handler = (void (*)(void))lp_ticker_irq_handler;
@@ -357,8 +365,8 @@
     NVIC_EnableIRQ(RTC_WKUP_IRQn);
 
     RtcHandle.Instance = RTC;
-    if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, 0xFFFF & WakeUpCounter, WakeUpClock[DivIndex - 1]) != HAL_OK) {
-        error("rtc_set_wake_up_timer init error (%d)\n", DivIndex);
+    if (HAL_RTCEx_SetWakeUpTimer_IT(&RtcHandle, (uint32_t)WakeUpCounter, WakeUpClock) != HAL_OK) {
+        error("rtc_set_wake_up_timer init error\n");
     }
 }
 

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.S	Thu Apr 19 17:12:19 2018 +0100
@@ -36,7 +36,7 @@
 
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
-__initial_sp
+__initial_sp    EQU     0x20040000
 
 
 ; <h> Heap Configuration

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_ARM_STD/startup_efr32mg1p.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_ARM_STD/startup_efr32mg1p.S	Thu Apr 19 17:12:19 2018 +0100
@@ -33,7 +33,7 @@
 
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
-__initial_sp
+__initial_sp    EQU     0x20008000
 
 
 ; <h> Heap Configuration

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/startup_efr32mg12p.S	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_ARM_STD/startup_efr32mg12p.S	Thu Apr 19 17:12:19 2018 +0100
@@ -33,7 +33,7 @@
 
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 Stack_Mem       SPACE   Stack_Size
-__initial_sp
+__initial_sp    EQU     0x20040000
 
 
 ; <h> Heap Configuration

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/gpio_irq_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -61,15 +61,11 @@
         return;
     }
 
-    //we are storing two ports in each uint8, so we must aquire the one we want.
-    // If pin is odd, the port is encoded in the 4 most significant bits. If pin is even, the port is encoded in the 4 least significant bits
-    uint8_t isRise = GPIO_PinInGet((pin & 0x1) ? channel_ports[(pin>>1) & 0x7] >> 4 & 0xF : channel_ports[(pin>>1) & 0x7] & 0xF, pin);
-
     // Get trigger event
     gpio_irq_event event = IRQ_NONE;
-    if ((GPIO->EXTIFALL & (1 << pin)) && !isRise) {
+    if (GPIO->EXTIFALL & (1 << pin)) {
         event = IRQ_FALL;
-    } else if ((GPIO->EXTIRISE & (1 << pin)) && isRise) {
+    } else if (GPIO->EXTIRISE & (1 << pin)) {
         event = IRQ_RISE;
     }
     GPIO_IntClear(pin);

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/i2c_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -28,7 +28,7 @@
 #if DEVICE_I2C
 
 #include "mbed_assert.h"
-#include "mbed_sleep.h"
+#include "mbed_power_mgmt.h"
 #include "i2c_api.h"
 #include "PeripheralPins.h"
 #include "pinmap_function.h"

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/itm_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(DEVICE_ITM)
+
+#include "hal/itm_api.h"
+#include "cmsis.h"
+#include "em_cmu.h"
+
+#include <stdbool.h>
+
+/* SWO frequency: 875 kHz */
+static void setupSWOForPrint(void)
+{
+#if defined( _GPIO_ROUTE_SWOPEN_MASK ) || defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
+    // Enable GPIO clock.
+#if defined( _CMU_HFPERCLKEN0_GPIO_MASK )
+    CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
+#elif defined( _CMU_HFBUSCLKEN0_GPIO_MASK )
+    CMU->HFBUSCLKEN0 |= CMU_HFBUSCLKEN0_GPIO;
+#endif
+  
+    // Enable Serial wire output pin
+#if defined( _GPIO_ROUTE_SWOPEN_MASK )
+    GPIO->ROUTE |= GPIO_ROUTE_SWOPEN;
+#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
+    GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN;
+#endif
+#endif
+  
+#if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_LEOPARD_FAMILY) || defined(_EFM32_WONDER_FAMILY) || defined(_EFM32_PEARL_FAMILY)
+    // Set location 0
+#if defined( _GPIO_ROUTE_SWOPEN_MASK )
+    GPIO->ROUTE = (GPIO->ROUTE & ~(_GPIO_ROUTE_SWLOCATION_MASK)) | GPIO_ROUTE_SWLOCATION_LOC0;
+#elif defined( _GPIO_ROUTEPEN_SWVPEN_MASK )
+    GPIO->ROUTELOC0 = (GPIO->ROUTELOC0 & ~(_GPIO_ROUTELOC0_SWVLOC_MASK)) | GPIO_ROUTELOC0_SWVLOC_LOC0;
+#endif
+
+    // Enable output on pin - GPIO Port F, Pin 2
+    GPIO->P[5].MODEL &= ~(_GPIO_P_MODEL_MODE2_MASK);
+    GPIO->P[5].MODEL |= GPIO_P_MODEL_MODE2_PUSHPULL;
+#else
+    // Set location 1
+    GPIO->ROUTE = (GPIO->ROUTE & ~(_GPIO_ROUTE_SWLOCATION_MASK)) | GPIO_ROUTE_SWLOCATION_LOC1;
+
+    // Enable output on pin
+    GPIO->P[2].MODEH &= ~(_GPIO_P_MODEH_MODE15_MASK);
+    GPIO->P[2].MODEH |= GPIO_P_MODEH_MODE15_PUSHPULL;
+#endif
+  
+    // Enable debug clock AUXHFRCO
+    CMU->OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;
+  
+    // Wait until clock is ready
+    while (!(CMU->STATUS & CMU_STATUS_AUXHFRCORDY));
+  
+    // Enable trace in core debug
+    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+
+    /* Set TPIU prescaler for the current debug clock frequency. Target frequency
+       is 875 kHz so we choose a divider that gives us the closest match.
+       Actual divider is TPI->ACPR + 1. */
+    uint32_t freq = CMU_ClockFreqGet(cmuClock_DBG) + (875000 / 2);
+    uint32_t div  = freq / 875000;
+    TPI->ACPR = div - 1;
+}
+
+static bool swoIsInitd()
+{
+#if defined( _CMU_HFPERCLKEN0_GPIO_MASK )
+    return ((CMU->HFPERCLKEN0 & CMU_HFPERCLKEN0_GPIO) &&
+            (GPIO->ROUTE & GPIO_ROUTE_SWOPEN) &&
+            (CMU->STATUS & CMU_STATUS_AUXHFRCORDY) &&
+            (CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk));
+#elif defined( _CMU_HFBUSCLKEN0_GPIO_MASK )
+    return ((CMU->HFBUSCLKEN0 & CMU_HFBUSCLKEN0_GPIO) &&
+            (GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN) &&
+            (CMU->STATUS & CMU_STATUS_AUXHFRCORDY) &&
+            (CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk));
+#endif
+}
+
+// As SWO has to be accessible everywhere, including ISRs, we can't easily
+// communicate the dependency on clocks etc. to other components - so this
+// function checks that things appear to be set up, and if not re-configures
+// everything
+void itm_init(void)
+{
+    if(!swoIsInitd()) {
+        setupSWOForPrint();
+    }
+}
+
+#endif

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/pwmout_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -26,7 +26,7 @@
 #if DEVICE_PWMOUT
 
 #include "mbed_assert.h"
-#include "mbed_sleep.h"
+#include "mbed_power_mgmt.h"
 #include "pwmout_api.h"
 #include "pinmap.h"
 #include "PeripheralPins.h"

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/serial_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -26,7 +26,7 @@
 #if DEVICE_SERIAL
 
 #include "mbed_assert.h"
-#include "mbed_sleep.h"
+#include "mbed_power_mgmt.h"
 #include "serial_api.h"
 #include "serial_api_HAL.h"
 #include <string.h>

--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/spi_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -26,7 +26,7 @@
 #if DEVICE_SPI
 
 #include "mbed_assert.h"
-#include "mbed_sleep.h"
+#include "mbed_power_mgmt.h"
 #include "PeripheralPins.h"
 #include "pinmap.h"
 #include "pinmap_function.h"

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_adc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,236 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_adc.h
+ * @brief   This file provides all the functions prototypes for ADC driver.
+ * @version V2.0.2.1
+ * @date    2015/02/11
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_ADC_H
+#define __TMPM46B_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Types
+  * @{
+  */
+#define IS_ADC_UNIT(param)          (((param) == TSB_AD))
+
+#define ADC_CONVERSION_CLK_10           ((uint32_t)0x00000000)
+#define ADC_CONVERSION_CLK_20           ((uint32_t)0x00000010)
+#define ADC_CONVERSION_CLK_30           ((uint32_t)0x00000020)
+#define ADC_CONVERSION_CLK_40           ((uint32_t)0x00000030)
+#define ADC_CONVERSION_CLK_80           ((uint32_t)0x00000040)
+#define ADC_CONVERSION_CLK_160          ((uint32_t)0x00000050)
+#define ADC_CONVERSION_CLK_320          ((uint32_t)0x00000060)
+#define IS_ADC_HOLD_TIME(param)         (((param) == ADC_CONVERSION_CLK_10) || \
+                                         ((param) == ADC_CONVERSION_CLK_20) || \
+                                         ((param) == ADC_CONVERSION_CLK_30) || \
+                                         ((param) == ADC_CONVERSION_CLK_40) || \
+                                         ((param) == ADC_CONVERSION_CLK_80) || \
+                                         ((param) == ADC_CONVERSION_CLK_160)|| \
+                                         ((param) == ADC_CONVERSION_CLK_320))
+
+#define ADC_FC_DIVIDE_LEVEL_1           ((uint32_t)0x00000000)
+#define ADC_FC_DIVIDE_LEVEL_2           ((uint32_t)0x00000001)
+#define ADC_FC_DIVIDE_LEVEL_4           ((uint32_t)0x00000002)
+#define ADC_FC_DIVIDE_LEVEL_8           ((uint32_t)0x00000003)
+#define ADC_FC_DIVIDE_LEVEL_16          ((uint32_t)0x00000004)
+#define IS_ADC_PRESCALER(param)         ((param) <= ADC_FC_DIVIDE_LEVEL_16)
+
+/* Interrupt generation timing in fixed channel mode */
+#define ADC_INT_SINGLE                  ((uint32_t)0x00000000)
+#define ADC_INT_CONVERSION_2            ((uint32_t)0x00000010)
+#define ADC_INT_CONVERSION_3            ((uint32_t)0x00000020)
+#define ADC_INT_CONVERSION_4            ((uint32_t)0x00000030)
+#define ADC_INT_CONVERSION_5            ((uint32_t)0x00000040)
+#define ADC_INT_CONVERSION_6            ((uint32_t)0x00000050)
+#define ADC_INT_CONVERSION_7            ((uint32_t)0x00000060)
+#define ADC_INT_CONVERSION_8            ((uint32_t)0x00000070)
+#define IS_ADC_INT_MODE(param)          (((param) == ADC_INT_SINGLE)       || \
+                                         ((param) == ADC_INT_CONVERSION_2) || \
+                                         ((param) == ADC_INT_CONVERSION_3) || \
+                                         ((param) == ADC_INT_CONVERSION_4) || \
+                                         ((param) == ADC_INT_CONVERSION_5) || \
+                                         ((param) == ADC_INT_CONVERSION_6) || \
+                                         ((param) == ADC_INT_CONVERSION_7) || \
+                                         ((param) == ADC_INT_CONVERSION_8))
+
+    typedef enum {
+        ADC_AN_00 = 0U,         /*!< define for Analog Input channel */
+        ADC_AN_01 = 1U,
+        ADC_AN_02 = 2U,
+        ADC_AN_03 = 3U,
+        ADC_AN_04 = 4U,
+        ADC_AN_05 = 5U,
+        ADC_AN_06 = 6U,
+        ADC_AN_07 = 7U,
+    } ADC_AINx;
+#define IS_ADC_INPUT_CHANNEL(param)           ((param) <= ADC_AN_07)
+#define IS_ADC_SCAN_CHANNEL(start, range)     (((start) <= ADC_AN_07) && \
+                                               ((range) >= 1U) && \
+                                               (((start) + (range)) <= 8U))
+
+
+    typedef enum {
+        ADC_REG_00 = 0U,
+        ADC_REG_01 = 1U,
+        ADC_REG_02 = 2U,
+        ADC_REG_03 = 3U,
+        ADC_REG_04 = 4U,
+        ADC_REG_05 = 5U,
+        ADC_REG_06 = 6U,
+        ADC_REG_07 = 7U,
+        ADC_REG_SP = 8U
+    } ADC_REGx;
+#define IS_ADC_REG(param)               ((param) <= ADC_REG_SP)
+
+#define ADC_APPLY_VREF_IN_CONVERSION    ((uint32_t)0x00000000)
+#define ADC_APPLY_VREF_AT_ANY_TIME      ((uint32_t)0x00000001)
+#define IS_ADC_VREF_CTRL(param)         (((param) == ADC_APPLY_VREF_IN_CONVERSION) || \
+                                         ((param) == ADC_APPLY_VREF_AT_ANY_TIME))
+
+    typedef enum {
+        ADC_CMPCR_0 = 0U,
+        ADC_CMPCR_1 = 1U
+    } ADC_CMPCRx;
+#define IS_ADC_CMPCRx(param)            ((param) <= ADC_CMPCR_1)
+
+#define ADC_EXTERADTRG                  ((uint32_t)0x00000000)
+#define ADC_INTERTRIGGER                ((uint32_t)0x00000001)
+#define IS_ADC_EXTERADTRG(param)        (((param) == ADC_EXTERADTRG)|| \
+                                         ((param) == ADC_INTERTRIGGER))
+
+#define IS_ADC_EXTERADTRG_TOP(param)    (((param) == ADC_EXTERADTRG)|| \
+                                         ((param) == ADC_INTERTRIGGER))
+
+
+    typedef enum {
+        ADC_LARGER_THAN_CMP_REG = 0U,
+        ADC_SMALLER_THAN_CMP_REG = 1U
+    } ADC_CmpCondition;
+#define IS_ADC_CMPCONDITION(param)      ((param) <= ADC_SMALLER_THAN_CMP_REG)
+
+    typedef enum {
+        ADC_SEQUENCE_CMP_MODE = 0U,
+        ADC_CUMULATION_CMP_MODE = 1U
+    } ADC_CmpCntMode;
+#define IS_ADC_CMPMODE(param)           ((param) <= ADC_CUMULATION_CMP_MODE)
+
+    typedef enum {
+        ADC_TRG_00 = 0U,
+        ADC_TRG_01 = 1U,
+        ADC_TRG_02 = 2U,
+        ADC_TRG_03 = 3U,
+        ADC_TRG_04 = 4U,
+        ADC_TRG_05 = 5U,
+        ADC_TRG_06 = 6U,
+        ADC_TRG_07 = 7U,
+        ADC_TRG_08 = 8U,
+        ADC_TRG_09 = 9U
+    } ADC_TRGx;
+#define IS_ADC_TRG(param)              ((param) <= ADC_TRG_09)
+
+/**
+  * @brief  ADC Monitor Configuration Structure definition
+  */
+    typedef struct {
+        ADC_AINx CmpChannel;            /*!< Select which ADC channel will be used */
+        uint32_t CmpCnt;                /*!< How many times will valid comparisons be counted, range from 1 to 16 */
+        ADC_CmpCondition Condition;     /*!< Condition to compare ADC channel with Compare Register */
+        ADC_CmpCntMode CntMode;         /*!< Mode to compare ADC channel with Compare Register */
+        uint32_t CmpValue;              /*!< Comparison value to be set in Compare Register, max value is 4095 */
+    } ADC_MonitorTypeDef;
+
+#define IS_ADC_CMPCNT(param)            (((param) >= 1U) && ((param) <= 16U))
+#define IS_ADC_CMPVALUE_12BIT(param)    ((param) <= 4095U)
+
+/**
+  * @brief Union to store ADC state
+  */
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t NormalBusy:1;      /*!< bit0, Normal A/D conversion busy flag (ADBF) */
+            uint32_t NormalComplete:1;  /*!< bit1, Normal AD conversion complete flag (EOCF) */
+            uint32_t TopBusy:1;         /*!< bit2, Top-priority A/D conversion busy flag (HPADBF) */
+            uint32_t TopComplete:1;     /*!< bit3, Top-priority AD conversion complete flag (HPEOCF) */
+            uint32_t Reserved:28;       /*!< bit4 to bit 31, reserved */
+        } Bit;
+    } ADC_State;
+
+/**
+  * @brief Union to store ADC result
+  */
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t ADResult:12;       /*!< bit0 to bit11, store AD result */
+            uint32_t Stored:1;          /*!< bit12, AD result has been stored */
+            uint32_t OverRun:1;         /*!< bit13, new AD result is stored before the old one is read */
+            uint32_t Reserved:18;       /*!< bit14 to bit31, reserved */
+        } Bit;
+    } ADC_Result;
+
+
+/** @} */
+/* End of group ADC_Exported_Types */
+
+/** @defgroup ADC_Exported_FunctionPrototypes
+  * @{
+  */
+
+    void ADC_SWReset(TSB_AD_TypeDef * ADx);
+    void ADC_SetClk(TSB_AD_TypeDef * ADx, uint32_t Sample_HoldTime, uint32_t Prescaler_Output);
+    void ADC_Start(TSB_AD_TypeDef * ADx);
+    void ADC_SetScanMode(TSB_AD_TypeDef * ADx, FunctionalState NewState);
+    void ADC_SetRepeatMode(TSB_AD_TypeDef * ADx, FunctionalState NewState);
+    void ADC_SetINTMode(TSB_AD_TypeDef * ADx, uint32_t INTMode);
+    void ADC_SetInputChannel(TSB_AD_TypeDef * ADx, ADC_AINx InputChannel);
+    void ADC_SetScanChannel(TSB_AD_TypeDef * ADx, ADC_AINx StartChannel, uint32_t Range);
+    void ADC_SetVrefCut(TSB_AD_TypeDef * ADx, uint32_t VrefCtrl);
+    void ADC_SetIdleMode(TSB_AD_TypeDef * ADx, FunctionalState NewState);
+    void ADC_SetVref(TSB_AD_TypeDef * ADx, FunctionalState NewState);
+    void ADC_SetInputChannelTop(TSB_AD_TypeDef * ADx, ADC_AINx TopInputChannel);
+    void ADC_StartTopConvert(TSB_AD_TypeDef * ADx);
+    void ADC_SetMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, FunctionalState NewState);
+    void ADC_ConfigMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, ADC_MonitorTypeDef * Monitor);
+    void ADC_SetHWTrg(TSB_AD_TypeDef * ADx, uint32_t HWSrc, FunctionalState NewState);
+    void ADC_SetHWTrgTop(TSB_AD_TypeDef * ADx, uint32_t HWSrc, FunctionalState NewState);
+    ADC_State ADC_GetConvertState(TSB_AD_TypeDef * ADx);
+    ADC_Result ADC_GetConvertResult(TSB_AD_TypeDef * ADx, ADC_REGx ADREGx);
+    void ADC_EnableTrigger(void);
+    void ADC_DisableTrigger(void);
+    void ADC_SetTriggerStartup(ADC_TRGx TriggerStartup);
+    void ADC_SetTriggerStartupTop(ADC_TRGx TopTriggerStartup);
+
+/** @} */
+/* End of group ADC_Exported_FunctionPrototypes */
+/** @} */
+/* End of group ADC */
+/** @} */
+/* End of group TX04_Periph_Driver */
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM46B_ADC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_cg.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,342 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_cg.h
+ * @brief   This file provides all the functions prototypes for CG driver.
+ * @version V2.0.2.1
+ * @date    2015/02/26
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_CG_H
+#define __TMPM46B_CG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup CG
+  * @{
+  */
+
+/** @addtogroup CG_Exported_types
+  * @{
+  */
+
+    typedef enum {
+        CG_DIVIDE_1 = 0U,
+        CG_DIVIDE_2 = 1U,
+        CG_DIVIDE_4 = 2U,
+        CG_DIVIDE_8 = 3U,
+        CG_DIVIDE_16 = 4U,
+        CG_DIVIDE_32 = 5U,
+        CG_DIVIDE_64 = 6U,
+        CG_DIVIDE_128 = 7U,
+        CG_DIVIDE_256 = 8U,
+        CG_DIVIDE_512 = 9U,
+        CG_DIVIDE_UNKNOWN = 10U,
+        CG_DIVIDE_MAX = 11U
+    } CG_DivideLevel;
+#define IS_CG_GEAR_DIVIDE_LEVEL(param)  (((param) == CG_DIVIDE_1) || \
+                                         ((param) == CG_DIVIDE_2) || \
+                                         ((param) == CG_DIVIDE_4) || \
+                                         ((param) == CG_DIVIDE_8) || \
+                                         ((param) == CG_DIVIDE_16))
+
+#define IS_CG_FC_DIVIDE_LEVEL(param)    (((param) == CG_DIVIDE_1) || \
+                                         ((param) == CG_DIVIDE_2) || \
+                                         ((param) == CG_DIVIDE_4) || \
+                                         ((param) == CG_DIVIDE_8) || \
+                                         ((param) == CG_DIVIDE_16)|| \
+                                         ((param) == CG_DIVIDE_32))
+
+#define IS_CG_DIVIDE_FC_LEVEL(param)    (((param) == CG_DIVIDE_1) || \
+                                         ((param) == CG_DIVIDE_2) || \
+                                         ((param) == CG_DIVIDE_4) || \
+                                         ((param) == CG_DIVIDE_8) || \
+                                         ((param) == CG_DIVIDE_16) || \
+                                         ((param) == CG_DIVIDE_32) || \
+                                         ((param) == CG_DIVIDE_64)|| \
+                                         ((param) == CG_DIVIDE_128) || \
+                                         ((param) == CG_DIVIDE_256) || \
+                                         ((param) == CG_DIVIDE_512))
+
+    typedef enum {
+        CG_FOSC_OSC_EXT = 0U,
+        CG_FOSC_OSC_INT = 1U,
+        CG_FOSC_CLKIN_EXT = 2U
+    } CG_FoscSrc;
+#define IS_CG_FOSC_SRC(param)           (((param) == CG_FOSC_OSC_EXT) || \
+                                         ((param) == CG_FOSC_OSC_INT) || \
+                                         ((param) == CG_FOSC_CLKIN_EXT))
+
+#define IS_CG_FOSC_STATE(param)         (((param) == CG_FOSC_OSC_EXT) || \
+                                         ((param) == CG_FOSC_OSC_INT) )
+
+    typedef enum {
+        CG_SCOUT_SRC_FS = 0U,
+        CG_SCOUT_SRC_FSYS_DIVIDE_8 = 1U,
+        CG_SCOUT_SRC_FSYS_DIVIDE_4 = 2U,
+        CG_SCOUT_SRC_FOSC = 3U
+    } CG_SCOUTSrc;
+#define IS_CG_SCOUT_SRC(param)          (((param) == CG_SCOUT_SRC_FS)            || \
+                                         ((param) == CG_SCOUT_SRC_FSYS_DIVIDE_8) || \
+                                         ((param) == CG_SCOUT_SRC_FSYS_DIVIDE_4) || \
+                                         ((param) == CG_SCOUT_SRC_FOSC))
+
+    typedef enum {
+        CG_WARM_UP_SRC_OSC_INT_HIGH = 0U,
+        CG_WARM_UP_SRC_OSC_EXT_HIGH = 1U,
+        CG_WARM_UP_SRC_OSC_EXT_LOW = 2U
+    } CG_WarmUpSrc;
+#define IS_CG_WARM_UP_SRC(param)        (((param) == CG_WARM_UP_SRC_OSC_INT_HIGH) || \
+                                         ((param) == CG_WARM_UP_SRC_OSC_EXT_HIGH) || \
+                                         ((param) == CG_WARM_UP_SRC_OSC_EXT_LOW))
+
+    typedef enum {
+        CG_FC_SRC_FOSC = 0U,
+        CG_FC_SRC_FPLL = 1U
+    } CG_FcSrc;
+#define IS_CG_FC_SRC(param)    (((param) == CG_FC_SRC_FOSC) || \
+                                ((param) == CG_FC_SRC_FPLL))
+
+#define CG_8M_MUL_4_FPLL        (0x00006A0FUL<<1U)      /* 4 fold,  input 8MHz,  output 32MHz  */
+#define CG_8M_MUL_5_FPLL        (0x00006A13UL<<1U)      /* 5 fold,  input 8MHz,  output 40MHz  */
+#define CG_8M_MUL_6_FPLL        (0x00006917UL<<1U)      /* 6 fold,  input 8MHz,  output 48MHz  */
+#define CG_8M_MUL_8_FPLL        (0x0000691FUL<<1U)      /* 8 fold,  input 8MHz,  output 64MHz  */
+#define CG_8M_MUL_10_FPLL       (0x00006A26UL<<1U)      /* 10 fold, input 8MHz,  output 80MHz  */
+#define CG_8M_MUL_12_FPLL       (0x0000692EUL<<1U)      /* 12 fold, input 8MHz,  output 96MHz  */
+#define CG_10M_MUL_4_FPLL       (0x00006A0FUL<<1U)      /* 4 fold,  input 10MHz, output 40MHz  */
+#define CG_10M_MUL_5_FPLL       (0x00006A13UL<<1U)      /* 5 fold,  input 10MHz, output 50MHz  */
+#define CG_10M_MUL_6_FPLL       (0x00006917UL<<1U)      /* 6 fold,  input 10MHz, output 60MHz  */
+#define CG_10M_MUL_8_FPLL       (0x0000691FUL<<1U)      /* 8 fold,  input 10MHz, output 80MHz  */
+#define CG_10M_MUL_10_FPLL      (0x00006A26UL<<1U)      /* 10 fold, input 10MHz, output 100MHz */
+#define CG_10M_MUL_12_FPLL      (0x0000692EUL<<1U)      /* 12 fold, input 10MHz, output 120MHz */
+#define CG_12M_MUL_4_FPLL       (0x00006A0FUL<<1U)      /* 4 fold,  input 12MHz, output 48MHz  */
+#define CG_12M_MUL_5_FPLL       (0x00006A13UL<<1U)      /* 5 fold,  input 12MHz, output 60MHz  */
+#define CG_12M_MUL_6_FPLL       (0x00006917UL<<1U)      /* 6 fold,  input 12MHz, output 72MHz  */
+#define CG_12M_MUL_8_FPLL       (0x0000691FUL<<1U)      /* 8 fold,  input 12MHz, output 96MHz  */
+#define CG_12M_MUL_10_FPLL      (0x00006A26UL<<1U)      /* 10 fold, input 12MHz, output 120MHz */
+#define CG_16M_MUL_4_FPLL       (0x00006A0FUL<<1U)      /* 4 fold,  input 16MHz, output 64MHz  */
+#define CG_16M_MUL_5_FPLL       (0x00006A13UL<<1U)      /* 5 fold,  input 16MHz, output 80MHz  */
+#define IS_CG_FPLL_VALUE(param)        (((param) == CG_8M_MUL_4_FPLL)   || \
+                                        ((param) == CG_8M_MUL_5_FPLL)   || \
+                                        ((param) == CG_8M_MUL_6_FPLL)   || \
+                                        ((param) == CG_8M_MUL_8_FPLL)   || \
+                                        ((param) == CG_8M_MUL_10_FPLL)  || \
+                                        ((param) == CG_8M_MUL_12_FPLL)  || \
+                                        ((param) == CG_10M_MUL_4_FPLL)  || \
+                                        ((param) == CG_10M_MUL_5_FPLL)  || \
+                                        ((param) == CG_10M_MUL_6_FPLL)  || \
+                                        ((param) == CG_10M_MUL_8_FPLL)  || \
+                                        ((param) == CG_10M_MUL_10_FPLL) || \
+                                        ((param) == CG_10M_MUL_12_FPLL) || \
+                                        ((param) == CG_12M_MUL_4_FPLL)  || \
+                                        ((param) == CG_12M_MUL_5_FPLL)  || \
+                                        ((param) == CG_12M_MUL_6_FPLL)  || \
+                                        ((param) == CG_12M_MUL_8_FPLL)  || \
+                                        ((param) == CG_12M_MUL_10_FPLL) || \
+                                        ((param) == CG_16M_MUL_4_FPLL)  || \
+                                        ((param) == CG_16M_MUL_5_FPLL))
+
+    typedef enum {
+        CG_STBY_MODE_UNKNOWN = 0U,
+        CG_STBY_MODE_STOP1 = 1U,
+        CG_STBY_MODE_IDLE = 3U,
+        CG_STBY_MODE_STOP2 = 5U,
+        CG_STBY_MODE_MAX = 8U
+    } CG_STBYMode;
+#define IS_CG_STBY_MODE(param)         (((param) == CG_STBY_MODE_STOP1) || \
+                                        ((param) == CG_STBY_MODE_IDLE)|| \
+                                        ((param) == CG_STBY_MODE_STOP2))
+
+    typedef enum {
+        CG_PHIT0_SRC_FGEAR = 0U,
+        CG_PHIT0_SRC_FC = 1U,
+        CG_PHIT0_SRC_MAX = 2U
+    } CG_PhiT0Src;
+#define IS_CG_PHIT0_SRC(param)  (((param) == CG_PHIT0_SRC_FGEAR) || \
+                                 ((param) == CG_PHIT0_SRC_FC))
+
+    typedef enum {
+        CG_INT_SRC_1 = 0U,
+        CG_INT_SRC_2 = 1U,
+        CG_INT_SRC_7 = 2U,
+        CG_INT_SRC_8 = 3U,
+        CG_INT_SRC_D = 4U,
+        CG_INT_SRC_E = 5U,
+        CG_INT_SRC_F = 6U,
+        CG_INT_SRC_RTC = 7U
+    } CG_INTSrc;
+
+#define IS_CG_INT_SRC(param)    (((param) == CG_INT_SRC_1) || \
+                                 ((param) == CG_INT_SRC_2) || \
+                                 ((param) == CG_INT_SRC_7) || \
+                                 ((param) == CG_INT_SRC_8) || \
+                                 ((param) == CG_INT_SRC_D) || \
+                                 ((param) == CG_INT_SRC_E) || \
+                                 ((param) == CG_INT_SRC_F) || \
+                                 ((param) == CG_INT_SRC_RTC))
+
+    typedef enum {
+        CG_INT_ACTIVE_STATE_L = 0x00U,
+        CG_INT_ACTIVE_STATE_H = 0x10U,
+        CG_INT_ACTIVE_STATE_FALLING = 0x20U,
+        CG_INT_ACTIVE_STATE_RISING = 0x30U,
+        CG_INT_ACTIVE_STATE_BOTH_EDGES = 0x40U,
+        CG_INT_ACTIVE_STATE_INVALID = 0x50U
+    } CG_INTActiveState;
+#define IS_CG_INT_ACTIVE_STATE(param)        (((param) == CG_INT_ACTIVE_STATE_L) || \
+                                              ((param) == CG_INT_ACTIVE_STATE_H) || \
+                                              ((param) == CG_INT_ACTIVE_STATE_FALLING) || \
+                                              ((param) == CG_INT_ACTIVE_STATE_RISING) || \
+                                              ((param) == CG_INT_ACTIVE_STATE_BOTH_EDGES))
+
+#define IS_CG_INT_RTC_ACTIVE_STATE(param)    ((param) == CG_INT_ACTIVE_STATE_FALLING)
+
+#define CG_FC_PERIPH_PORTA          (0x00000001U << 0U)
+#define CG_FC_PERIPH_PORTB          (0x00000001U << 1U)
+#define CG_FC_PERIPH_PORTC          (0x00000001U << 2U)
+#define CG_FC_PERIPH_PORTD          (0x00000001U << 3U)
+#define CG_FC_PERIPH_PORTE          (0x00000001U << 4U)
+#define CG_FC_PERIPH_PORTF          (0x00000001U << 5U)
+#define CG_FC_PERIPH_PORTG          (0x00000001U << 6U)
+#define CG_FC_PERIPH_PORTH          (0x00000001U << 7U)
+#define CG_FC_PERIPH_PORTJ          (0x00000001U << 8U)
+#define CG_FC_PERIPH_PORTK          (0x00000001U << 9U)
+#define CG_FC_PERIPH_PORTL          (0x00000001U << 10U)
+#define CG_FC_PERIPH_TMRB0          (0x00000001U << 13U)
+#define CG_FC_PERIPH_TMRB1          (0x00000001U << 14U)
+#define CG_FC_PERIPH_TMRB2          (0x00000001U << 15U)
+#define CG_FC_PERIPH_TMRB3          (0x00000001U << 16U)
+#define CG_FC_PERIPH_TMRB4          (0x00000001U << 17U)
+#define CG_FC_PERIPH_TMRB5          (0x00000001U << 18U)
+#define CG_FC_PERIPH_TMRB6          (0x00000001U << 19U)
+#define CG_FC_PERIPH_TMRB7          (0x00000001U << 20U)
+#define CG_FC_PERIPH_MPT0           (0x00000001U << 27U)
+#define CG_FC_PERIPH_MPT1           (0x00000001U << 28U)
+#define CG_FC_PERIPH_MPT2           (0x00000001U << 29U)
+#define CG_FC_PERIPH_MPT3           (0x00000001U << 30U)
+#define CG_FC_PERIPH_TRACE          (0x00000001U << 31U)
+#define CG_FC_PERIPHA_ALL           (0xF81FE7FFU)
+#define IS_CG_FC_PERIPHA(param)     ((param) > 0U)
+
+#define CG_FC_PERIPH_SIO_UART0      (0x00000001U << 0U)
+#define CG_FC_PERIPH_SIO_UART1      (0x00000001U << 1U)
+#define CG_FC_PERIPH_SIO_UART2      (0x00000001U << 2U)
+#define CG_FC_PERIPH_SIO_UART3      (0x00000001U << 3U)
+#define CG_FC_PERIPH_UART0          (0x00000001U << 10U)
+#define CG_FC_PERIPH_UART1          (0x00000001U << 11U)
+#define CG_FC_PERIPH_I2C0           (0x00000001U << 12U)
+#define CG_FC_PERIPH_I2C1           (0x00000001U << 13U)
+#define CG_FC_PERIPH_I2C2           (0x00000001U << 14U)
+#define CG_FC_PERIPH_SSP0           (0x00000001U << 17U)
+#define CG_FC_PERIPH_SSP1           (0x00000001U << 18U)
+#define CG_FC_PERIPH_SSP2           (0x00000001U << 19U)
+#define CG_FC_PERIPH_EBIF           (0x00000001U << 20U)
+#define CG_FC_PERIPH_DMACA          (0x00000001U << 21U)
+#define CG_FC_PERIPH_DMACB          (0x00000001U << 22U)
+#define CG_FC_PERIPH_DMACC          (0x00000001U << 23U)
+#define CG_FC_PERIPH_DMAIF          (0x00000001U << 24U)
+#define CG_FC_PERIPH_ADC            (0x00000001U << 25U)
+#define CG_FC_PERIPH_WDT            (0x00000001U << 26U)
+#define CG_FC_PERIPH_MLA            (0x00000001U << 28U)
+#define CG_FC_PERIPH_ESG            (0x00000001U << 29U)
+#define CG_FC_PERIPH_SHA            (0x00000001U << 30U)
+#define CG_FC_PERIPH_AES            (0x00000001U << 31U)
+#define CG_FC_PERIPHB_ALL           (0xF7FE7C0FU)
+#define IS_CG_FC_PERIPHB(param)     (((param) > 0U) && ((param) <= CG_FC_PERIPHB_ALL))
+
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t WDT:1;
+            uint32_t Reserved0:1;
+            uint32_t DetectLowVoltage:1;
+            uint32_t Reserved1:29;
+        } Bit;
+    } CG_NMIFactor;
+
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t PinReset:1;
+            uint32_t OSCFLF:1;
+            uint32_t WDTReset:1;
+            uint32_t STOP2Reset:1;
+            uint32_t DebugReset:1;
+            uint32_t Reserved0:1;
+            uint32_t LVDReset:1;
+            uint32_t Reserved1:25;
+        } Bit;
+    } CG_ResetFlag;
+
+/** @} */
+/* End of group CG_Exported_types */
+
+/** @defgroup CG_Exported_FunctionPrototypes
+  * @{
+  */
+    void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc);
+    CG_DivideLevel CG_GetFgearLevel(void);
+    void CG_SetPhiT0Src(CG_PhiT0Src PhiT0Src);
+    CG_PhiT0Src CG_GetPhiT0Src(void);
+    Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc);
+    CG_DivideLevel CG_GetPhiT0Level(void);
+    void CG_SetSCOUTSrc(CG_SCOUTSrc Source);
+    CG_SCOUTSrc CG_GetSCOUTSrc(void);
+    void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time);
+    void CG_StartWarmUp(void);
+    WorkState CG_GetWarmUpState(void);
+    Result CG_SetFPLLValue(uint32_t NewValue);
+    uint32_t CG_GetFPLLValue(void);
+    Result CG_SetPLL(FunctionalState NewState);
+    FunctionalState CG_GetPLLState(void);
+    Result CG_SetFosc(CG_FoscSrc Source, FunctionalState NewState);
+    void CG_SetFoscSrc(CG_FoscSrc Source);
+    CG_FoscSrc CG_GetFoscSrc(void);
+    FunctionalState CG_GetFoscState(CG_FoscSrc Source);
+    void CG_SetSTBYMode(CG_STBYMode Mode);
+    CG_STBYMode CG_GetSTBYMode(void);
+    void CG_SetPortKeepInStop2Mode(FunctionalState NewState);
+    FunctionalState CG_GetPortKeepInStop2Mode(void);
+    Result CG_SetFcSrc(CG_FcSrc Source);
+    CG_FcSrc CG_GetFcSrc(void);
+    void CG_SetProtectCtrl(FunctionalState NewState);
+    void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource,
+                                 CG_INTActiveState ActiveState, FunctionalState NewState);
+    CG_INTActiveState CG_GetSTBYReleaseINTState(CG_INTSrc INTSource);
+    void CG_ClearINTReq(CG_INTSrc INTSource);
+    CG_NMIFactor CG_GetNMIFlag(void);
+    FunctionalState CG_GetIOSCFlashFlag(void);
+    CG_ResetFlag CG_GetResetFlag(void);
+    void CG_SetADCClkSupply(FunctionalState NewState);
+    void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState);
+    void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState);
+    void CG_SetFs(FunctionalState NewState);
+
+/** @} */
+/* End of group CG_Exported_FunctionPrototype */
+
+/** @} */
+/* End of group CG */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM46B_CG_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_esg.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,109 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_esg.h
+ * @brief   This file provides all the functions prototypes for ESG driver.
+ * @version V2.0.2.1
+ * @date    2015/02/04
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_ESG_H
+#define __TMPM46B_ESG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"     
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup ESG
+  * @{
+  */
+
+/** @defgroup ESG_Exported_Constants
+  * @{
+  */
+
+/** @} */
+/* End of ESG_Exported_Constants */
+
+/** @defgroup ESG_Exported_Types 
+  * @{
+  */
+    typedef enum {
+        ESG_CALCULATION_COMPLETE = 0U,
+        ESG_CALCULATION_PROCESS = 1U
+    } ESG_CalculationStatus;
+
+    typedef enum {
+        ESG_LATCH_TIMING_1 = 0U,
+        ESG_LATCH_TIMING_2 = 1U,
+        ESG_LATCH_TIMING_3 = 2U,
+        ESG_LATCH_TIMING_4 = 3U,
+        ESG_LATCH_TIMING_5 = 4U,
+        ESG_LATCH_TIMING_6 = 5U,
+        ESG_LATCH_TIMING_7 = 6U,
+        ESG_LATCH_TIMING_8 = 7U,
+        ESG_LATCH_TIMING_9 = 8U,
+        ESG_LATCH_TIMING_10 = 9U,
+        ESG_LATCH_TIMING_11 = 10U,
+        ESG_LATCH_TIMING_12 = 11U,
+        ESG_LATCH_TIMING_13 = 12U,
+        ESG_LATCH_TIMING_14 = 13U,
+        ESG_LATCH_TIMING_15 = 14U,
+        ESG_LATCH_TIMING_16 = 15U
+    } ESG_LatchTiming;
+#define IS_ESG_LATCH_TIMING(param)       ((param) <= ESG_LATCH_TIMING_16)
+
+/** @} */
+/* End of ESG_Exported_types */
+
+/** @addtogroup ESG_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief ESG Init Structure definition
+  */
+/** @} */
+/* End of group ESG_Exported_Types */
+
+/** @defgroup ESG_Exported_FunctionPrototypes
+  * @{
+  */
+  
+    Result ESG_Startup(void);
+    Result ESG_SetLatchTiming(ESG_LatchTiming Value);
+    uint32_t ESG_GetLatchTiming(void);
+    Result ESG_SetFintiming(uint16_t Fintming);
+    uint16_t ESG_GetFintiming(void);
+    Result ESG_ClrInt(void);
+    FunctionalState ESG_GetIntStatus(void);
+    void ESG_IPReset(void);
+    ESG_CalculationStatus ESG_GetCalculationStatus(void);
+    void ESG_GetResult(uint32_t Seed[16U]);
+
+/** @} */
+/* End of ESG_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group ESG */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+#endif                          /* __TMPM46B_ESG_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_fc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,256 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_fc.h
+ * @brief   This file provides all the functions prototypes for FC driver.
+ * @version V2.0.2.1
+ * @date    2015/02/27
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_FC_H
+#define __TMPM46B_FC_H
+
+
+/* #define SINGLE_BOOT_MODE */
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup FC
+  * @{
+  */
+
+/** @defgroup FC_Exported_Types
+  * @{
+  */
+    typedef enum {
+        FC_SUCCESS = 0U,
+        FC_ERROR_PROTECTED = 1U,
+        FC_ERROR_OVER_TIME = 2U
+    } FC_Result;
+
+/** @} */
+/* End of group FC_Exported_Types */
+
+/** @defgroup FC_Exported_Constants
+  * @{
+  */
+
+#define FLASH_PAGE_SIZE                 ((uint32_t)0x00001000)  /* Page Size 4096 Bytes/1024 words */
+#define PROGRAM_UNIT                    4U      /* Page program could be written 16 bytes/4 words once */
+
+#define FC_PAGE_0                       ((uint8_t)0x00)
+#define FC_PAGE_1                       ((uint8_t)0x01)
+#define FC_PAGE_2                       ((uint8_t)0x02)
+#define FC_PAGE_3                       ((uint8_t)0x03)
+#define FC_PAGE_4                       ((uint8_t)0x04)
+#define FC_PAGE_5                       ((uint8_t)0x05)
+#define FC_PAGE_6                       ((uint8_t)0x06)
+#define FC_PAGE_7                       ((uint8_t)0x07)
+
+#define FC_PAGE_MAX                     FC_PAGE_7
+#define IS_FC_PAGE_NUM(param)           ((param) <= FC_PAGE_MAX)
+
+#define FC_BLOCK_0                      ((uint8_t)0x00)
+#define FC_BLOCK_1                      ((uint8_t)0x01)
+#define FC_BLOCK_2                      ((uint8_t)0x02)
+#define FC_BLOCK_3                      ((uint8_t)0x03)
+#define FC_BLOCK_4                      ((uint8_t)0x04)
+#define FC_BLOCK_5                      ((uint8_t)0x05)
+#define FC_BLOCK_6                      ((uint8_t)0x06)
+#define FC_BLOCK_7                      ((uint8_t)0x07)
+#define FC_BLOCK_8                      ((uint8_t)0x08)
+#define FC_BLOCK_9                      ((uint8_t)0x09)
+#define FC_BLOCK_10                     ((uint8_t)0x0A)
+#define FC_BLOCK_11                     ((uint8_t)0x0B)
+#define FC_BLOCK_12                     ((uint8_t)0x0C)
+#define FC_BLOCK_13                     ((uint8_t)0x0D)
+#define FC_BLOCK_14                     ((uint8_t)0x0E)
+#define FC_BLOCK_15                     ((uint8_t)0x0F)
+#define FC_BLOCK_16                     ((uint8_t)0x10)
+#define FC_BLOCK_17                     ((uint8_t)0x11)
+#define FC_BLOCK_18                     ((uint8_t)0x12)
+#define FC_BLOCK_19                     ((uint8_t)0x13)
+#define FC_BLOCK_20                     ((uint8_t)0x14)
+#define FC_BLOCK_21                     ((uint8_t)0x15)
+#define FC_BLOCK_22                     ((uint8_t)0x16)
+#define FC_BLOCK_23                     ((uint8_t)0x17)
+#define FC_BLOCK_24                     ((uint8_t)0x18)
+#define FC_BLOCK_25                     ((uint8_t)0x19)
+#define FC_BLOCK_26                     ((uint8_t)0x1A)
+#define FC_BLOCK_27                     ((uint8_t)0x1B)
+#define FC_BLOCK_28                     ((uint8_t)0x1C)
+#define FC_BLOCK_29                     ((uint8_t)0x1D)
+#define FC_BLOCK_30                     ((uint8_t)0x1E)
+#define FC_BLOCK_31                     ((uint8_t)0x1F)
+
+#define FLASH_CHIP_SIZE                 ((uint32_t)0x00100000)  /* Flash chip size is 1024KByte */
+#define FC_BLOCK_MAX                    FC_BLOCK_31
+
+#define IS_FC_BLOCK_NUM(param)          (((param) <= FC_BLOCK_MAX) && ((param) >= FC_BLOCK_1))
+
+#define FC_AREA_ALL                     ((uint8_t)0x00)
+#define FC_AREA_0                       ((uint8_t)0x01)
+#define FC_AREA_1                       ((uint8_t)0x02)
+
+#define IS_FC_AREA(param)               ((param) <= FC_AREA_1)
+
+#define FC_SWAP_SIZE_4K                 ((uint32_t)0x00000000)
+#define FC_SWAP_SIZE_8K                 ((uint32_t)0x00000001)
+#define FC_SWAP_SIZE_16K                ((uint32_t)0x00000002)
+#define FC_SWAP_SIZE_32K                ((uint32_t)0x00000003)
+#define FC_SWAP_SIZE_512K               ((uint32_t)0x00000004)
+
+#define FC_SWAP_INITIAL                 ((uint32_t)0x00000000)
+#define FC_SWAPPING                     ((uint32_t)0x00000001)
+#define FC_SWAP_PROHIBIT                ((uint32_t)0x00000002)
+#define FC_SWAP_RELEASE                 ((uint32_t)0x00000003)
+
+#define FC_Clk_Div_1                    ((uint8_t) 0x00)
+#define FC_Clk_Div_2                    ((uint8_t) 0x01)
+#define FC_Clk_Div_3                    ((uint8_t) 0x02)
+#define FC_Clk_Div_4                    ((uint8_t) 0x03)
+#define FC_Clk_Div_5                    ((uint8_t) 0x04)
+#define FC_Clk_Div_6                    ((uint8_t) 0x05)
+#define FC_Clk_Div_7                    ((uint8_t) 0x06)
+#define FC_Clk_Div_8                    ((uint8_t) 0x07)
+#define FC_Clk_Div_9                    ((uint8_t) 0x08)
+#define FC_Clk_Div_10                   ((uint8_t) 0x09)
+#define FC_Clk_Div_11                   ((uint8_t) 0x0A)
+#define FC_Clk_Div_12                   ((uint8_t) 0x0B)
+#define FC_Clk_Div_13                   ((uint8_t) 0x0C)
+#define FC_Clk_Div_14                   ((uint8_t) 0x0D)
+#define FC_Clk_Div_15                   ((uint8_t) 0x0E)
+#define FC_Clk_Div_16                   ((uint8_t) 0x0F)
+#define FC_Clk_Div_17                   ((uint8_t) 0x10)
+#define FC_Clk_Div_18                   ((uint8_t) 0x11)
+#define FC_Clk_Div_19                   ((uint8_t) 0x12)
+#define FC_Clk_Div_20                   ((uint8_t) 0x13)
+#define FC_Clk_Div_21                   ((uint8_t) 0x14)
+#define FC_Clk_Div_22                   ((uint8_t) 0x15)
+#define FC_Clk_Div_23                   ((uint8_t) 0x16)
+#define FC_Clk_Div_24                   ((uint8_t) 0x17)
+#define FC_Clk_Div_25                   ((uint8_t) 0x18)
+#define FC_Clk_Div_26                   ((uint8_t) 0x19)
+#define FC_Clk_Div_27                   ((uint8_t) 0x1A)
+#define FC_Clk_Div_28                   ((uint8_t) 0x1B)
+#define FC_Clk_Div_29                   ((uint8_t) 0x1C)
+#define FC_Clk_Div_30                   ((uint8_t) 0x1D)
+#define FC_Clk_Div_31                   ((uint8_t) 0x1E)
+#define FC_Clk_Div_32                   ((uint8_t) 0x1F)
+#define IS_FC_WCLK_DIV(param)           ((param) <= FC_Clk_Div_32)
+
+#define FC_PROG_CNT_250                 ((uint8_t) 0x00)
+#define FC_PROG_CNT_300                 ((uint8_t) 0x01)
+#define FC_PROG_CNT_350                 ((uint8_t) 0x02)
+#define IS_FC_PROG_CNT(param)           ((param) <= (FC_PROG_CNT_350))
+
+#define FC_ERAS_CNT_85                  ((uint8_t) 0x00)
+#define FC_ERAS_CNT_90                  ((uint8_t) 0x01)
+#define FC_ERAS_CNT_95                  ((uint8_t) 0x02)
+#define FC_ERAS_CNT_100                 ((uint8_t) 0x03)
+#define FC_ERAS_CNT_105                 ((uint8_t) 0x04)
+#define FC_ERAS_CNT_110                 ((uint8_t) 0x05)
+#define FC_ERAS_CNT_115                 ((uint8_t) 0x06)
+#define FC_ERAS_CNT_120                 ((uint8_t) 0x07)
+#define FC_ERAS_CNT_125                 ((uint8_t) 0x08)
+#define FC_ERAS_CNT_130                 ((uint8_t) 0x09)
+#define FC_ERAS_CNT_135                 ((uint8_t) 0x0A)
+#define FC_ERAS_CNT_140                 ((uint8_t) 0x0B)
+#define IS_FC_ERASE_CNT(param)          ((param) <= FC_ERAS_CNT_140)
+
+#define FC_SWPSR_BIT_0                  ((uint8_t) 0x00)
+#define FC_SWPSR_BIT_1                  ((uint8_t) 0x01)
+#define FC_SWPSR_BIT_2                  ((uint8_t) 0x02)
+#define FC_SWPSR_BIT_3                  ((uint8_t) 0x03)
+#define FC_SWPSR_BIT_4                  ((uint8_t) 0x04)
+#define FC_SWPSR_BIT_5                  ((uint8_t) 0x05)
+#define FC_SWPSR_BIT_6                  ((uint8_t) 0x06)
+#define FC_SWPSR_BIT_7                  ((uint8_t) 0x07)
+#define FC_SWPSR_BIT_8                  ((uint8_t) 0x08)
+#define FC_SWPSR_BIT_9                  ((uint8_t) 0x09)
+#define FC_SWPSR_BIT_10                 ((uint8_t) 0x0A)
+#define IS_FC_SWPSR_BIT_NUM(param)      ((param) <= FC_SWPSR_BIT_10)
+
+#define FC_BIT_VALUE_0                  ((uint32_t)0x00000000)
+#define FC_BIT_VALUE_1                  ((uint32_t)0x00000001)
+
+#ifdef SINGLE_BOOT_MODE
+#define FLASH_START_ADDR                ((uint32_t)0x5E000000)  /* SINGLE_BOOT_MODE */
+#else
+#define FLASH_START_ADDR                ((uint32_t)0x00000000)  /* User Boot Mode As Default */
+#endif
+
+#define FLASH_END_ADDR                  (FLASH_START_ADDR + FLASH_CHIP_SIZE - 1U)
+
+#ifdef SINGLE_BOOT_MODE
+#define IS_FC_ADDR(param)               (((param) >= FLASH_START_ADDR) && \
+                                         ((param) <= FLASH_END_ADDR))
+#else
+#define IS_FC_ADDR(param)               ((param) <= FLASH_END_ADDR)
+#endif
+
+#define IS_FC_PAGE_ADDR(param)          ((((param) > FLASH_START_ADDR) || ((param) == FLASH_START_ADDR)) && \
+                                         ((param) <= (FLASH_END_ADDR - PROGRAM_UNIT)))
+
+
+/** @} */
+/* End of group FC_Exported_Constants */
+
+
+/** @defgroup FC_Exported_FunctionPrototypes
+  * @{
+  */
+
+    void FC_SetSecurityBit(FunctionalState NewState);
+    FunctionalState FC_GetSecurityBit(void);
+    WorkState FC_GetBusyState(void);
+    FunctionalState FC_GetBlockProtectState(uint8_t BlockNum);
+    FunctionalState FC_GetPageProtectState(uint8_t PageNum);
+    FunctionalState FC_GetAbortState(void);
+    uint32_t FC_GetSwapSize(void);
+    uint32_t FC_GetSwapState(void);
+    void FC_SelectArea(uint8_t AreaNum, FunctionalState NewState);
+    void FC_SetAbortion(void);
+    void FC_ClearAbortion(void);
+    void FC_SetClkDiv(uint8_t ClkDiv);
+    void FC_SetProgramCount(uint8_t ProgramCount);
+    void FC_SetEraseCounter(uint8_t EraseCounter);
+    FC_Result FC_ProgramBlockProtectState(uint8_t BlockNum);
+    FC_Result FC_ProgramPageProtectState(uint8_t PageNum);
+    FC_Result FC_EraseProtectState(void);
+    FC_Result FC_WritePage(uint32_t PageAddr, uint32_t * Data);
+    FC_Result FC_EraseBlock(uint32_t BlockAddr);
+    FC_Result FC_EraseArea(uint32_t AreaAddr);
+    FC_Result FC_ErasePage(uint32_t PageAddr);
+    FC_Result FC_EraseChip(void);
+    FC_Result FC_SetSwpsrBit(uint8_t BitNum);
+    uint32_t FC_GetSwpsrBitValue(uint8_t BitNum);
+
+/** @} */
+/* End of group FC_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group FC */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM46B_FC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_fuart.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,281 @@
+/** 
+ *******************************************************************************
+ * @file    tmpm46b_fuart.h
+ * @brief   This file provides all the functions prototypes for Full UART driver.
+ * @version V2.0.2.1
+ * @date    2015/02/26
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_FUART_H
+#define __TMPM46B_FUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup FUART
+  * @{
+  */
+
+/** @defgroup FUART_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  FUART Init Structure definition
+  */
+
+    typedef struct {
+        uint32_t BaudRate;      /*!< This member configures the Full UART communication
+                                   baud rate. */
+        uint32_t DataBits;      /*!< Specifies FUART transfer mode, which could be 
+                                   5-bit mode, 6-bit mode, 7-bit mode or 8-bit mode. */
+        uint32_t StopBits;      /*!< Specifies the length of stop bit transmission
+                                   in Full UART. */
+        uint32_t Parity;        /*!< Specifies the parity mode which could be  0 parity,
+                                   1 parity, odd parity, even parity or no parity. */
+        uint32_t Mode;          /*!< Enables or disables Receive, Transmit or 
+                                   both. */
+        uint32_t FlowCtrl;      /*!< Specifies the hardware flow control mode, which can be
+                                   CTS flow control, RTS flow control or none flow control. */
+    } FUART_InitTypeDef;
+
+/** @} */
+/* End of group FUART_Exported_Types */
+
+/** @defgroup FUART_Exported_Constants
+  * @{
+  */
+#define FUART0                                 TSB_UART0
+#define FUART1                                 TSB_UART1
+#define TSB_FUART_TypeDef                      TSB_UART_TypeDef
+
+#define IS_FUART_PERIPH(param)                 (((param) == FUART0) || \
+                                                ((param) == FUART1))
+
+#define IS_FUART_BAUDRATE(param)               (((param) != 0U) && \
+                                                ((param) <= 2950000U))
+
+#define FUART_DATA_BITS_5                      ((uint32_t)0x00000000)
+#define FUART_DATA_BITS_6                      ((uint32_t)0x00000020)
+#define FUART_DATA_BITS_7                      ((uint32_t)0x00000040)
+#define FUART_DATA_BITS_8                      ((uint32_t)0x00000060)
+
+#define IS_FUART_DATA_BITS(param)              (((param) == FUART_DATA_BITS_5) || \
+                                                ((param) == FUART_DATA_BITS_6) || \
+                                                ((param) == FUART_DATA_BITS_7) || \
+                                                ((param) == FUART_DATA_BITS_8))
+
+#define FUART_STOP_BITS_1                      ((uint32_t)0x00000000)
+#define FUART_STOP_BITS_2                      ((uint32_t)0x00000008)
+#define IS_FUART_STOPBITS(param)               (((param) == FUART_STOP_BITS_1) || \
+                                                ((param) == FUART_STOP_BITS_2))
+
+#define FUART_NO_PARITY                        ((uint32_t)0x00000000)
+#define FUART_0_PARITY                         ((uint32_t)0x00000086)
+#define FUART_1_PARITY                         ((uint32_t)0x00000082)
+#define FUART_EVEN_PARITY                      ((uint32_t)0x00000006)
+#define FUART_ODD_PARITY                       ((uint32_t)0x00000002)
+#define IS_FUART_PARITY(param)                 (((param) == FUART_NO_PARITY) || \
+                                                ((param) == FUART_0_PARITY) || \
+                                                ((param) == FUART_1_PARITY) || \
+                                                ((param) == FUART_EVEN_PARITY) || \
+                                                ((param) == FUART_ODD_PARITY))
+
+#define FUART_ENABLE_RX                         ((uint32_t)0x00000200)
+#define FUART_ENABLE_TX                         ((uint32_t)0x00000100)
+#define IS_FUART_MODE(param)                    (((param) == FUART_ENABLE_RX) || \
+                                                 ((param) == FUART_ENABLE_TX) || \
+                                                 ((param) == (FUART_ENABLE_TX | FUART_ENABLE_RX)))
+
+#define FUART_NONE_FLOW_CTRL                   ((uint32_t)0x00000000)
+#define FUART_CTS_FLOW_CTRL                    ((uint32_t)0x00008000)
+#define FUART_RTS_FLOW_CTRL                    ((uint32_t)0x00004000)
+#define IS_FUART_FLOW_CTRL(param)              (((param) == FUART_NONE_FLOW_CTRL) || \
+                                                ((param) == FUART_CTS_FLOW_CTRL) || \
+                                                ((param) == FUART_RTS_FLOW_CTRL) || \
+                                                ((param) == (FUART_CTS_FLOW_CTRL | FUART_RTS_FLOW_CTRL)))
+
+#define FUART_IRDA_3_16_BIT_PERIOD_MODE        ((uint32_t)0x00000000)
+#define FUART_IRDA_3_TIMES_IRLPBAUD16_MODE     ((uint32_t)0x00000004)
+#define IS_IRDA_ENCODE_MODE(param)             (((param) == FUART_IRDA_3_16_BIT_PERIOD_MODE) || \
+                                                ((param) == FUART_IRDA_3_TIMES_IRLPBAUD16_MODE))
+
+#define FUART_RX_FIFO_LEVEL_4                  ((uint32_t)0x00000000)
+#define FUART_RX_FIFO_LEVEL_8                  ((uint32_t)0x00000008)
+#define FUART_RX_FIFO_LEVEL_16                 ((uint32_t)0x00000010)
+#define FUART_RX_FIFO_LEVEL_24                 ((uint32_t)0x00000018)
+#define FUART_RX_FIFO_LEVEL_28                 ((uint32_t)0x00000020)
+#define IS_FUART_RX_FIFO_LEVEL(param)          (((param) == FUART_RX_FIFO_LEVEL_4) || \
+                                                ((param) == FUART_RX_FIFO_LEVEL_8) || \
+                                                ((param) == FUART_RX_FIFO_LEVEL_16) || \
+                                                ((param) == FUART_RX_FIFO_LEVEL_24) || \
+                                                ((param) == FUART_RX_FIFO_LEVEL_28))
+
+#define FUART_TX_FIFO_LEVEL_4                  ((uint32_t)0x00000000)
+#define FUART_TX_FIFO_LEVEL_8                  ((uint32_t)0x00000001)
+#define FUART_TX_FIFO_LEVEL_16                 ((uint32_t)0x00000002)
+#define FUART_TX_FIFO_LEVEL_24                 ((uint32_t)0x00000003)
+#define FUART_TX_FIFO_LEVEL_28                 ((uint32_t)0x00000004)
+#define IS_FUART_TX_FIFO_LEVEL(param)          (((param) == FUART_TX_FIFO_LEVEL_4) || \
+                                                ((param) == FUART_TX_FIFO_LEVEL_8) || \
+                                                ((param) == FUART_TX_FIFO_LEVEL_16) || \
+                                                ((param) == FUART_TX_FIFO_LEVEL_24) || \
+                                                ((param) == FUART_TX_FIFO_LEVEL_28))
+
+
+#define FUART_NONE_INT_MASK                    ((uint32_t)0x00000000)
+#define FUART_RIN_MODEM_INT_MASK               ((uint32_t)0x00000001)
+#define FUART_CTS_MODEM_INT_MASK               ((uint32_t)0x00000002)
+#define FUART_DCD_MODEM_INT_MASK               ((uint32_t)0x00000004)
+#define FUART_DSR_MODEM_INT_MASK               ((uint32_t)0x00000008)
+#define FUART_RX_FIFO_INT_MASK                 ((uint32_t)0x00000010)
+#define FUART_TX_FIFO_INT_MASK                 ((uint32_t)0x00000020)
+#define FUART_RX_TIMEOUT_INT_MASK              ((uint32_t)0x00000040)
+#define FUART_FRAMING_ERR_INT_MASK             ((uint32_t)0x00000080)
+#define FUART_PARITY_ERR_INT_MASK              ((uint32_t)0x00000100)
+#define FUART_BREAK_ERR_INT_MASK               ((uint32_t)0x00000200)
+#define FUART_OVERRUN_ERR_INT_MASK             ((uint32_t)0x00000400)
+#define FUART_ALL_INT_MASK                     ((uint32_t)0x000007FF)
+
+#define IS_INT_MASK_SRC(param)                 ((param) <= FUART_ALL_INT_MASK)
+
+#define IS_FUART_DATA(param)                   ((param) <= (uint32_t)0x000000FF)
+
+#define IS_FUART_IRDA_DIVISOR(param)           (((param) != (uint32_t)0x00000000) && \
+                                                ((param) <= (uint32_t)0x000000FF))
+/** @} */
+/* End of group FUART_Exported_Constants */
+
+/** @addtogroup FUART_Exported_Types
+  * @{
+  */
+    typedef enum {
+        FUART_STORAGE_EMPTY = 0U,
+        FUART_STORAGE_NORMAL = 1U,
+        FUART_STORAGE_INVALID = 2U,
+        FUART_STORAGE_FULL = 3U
+    } FUART_StorageStatus;
+
+    typedef enum {
+        FUART_RX = 0U,
+        FUART_TX = 1U
+    } FUART_Direction;
+
+#define IS_FUART_DIRECTION(param)              (((param) == FUART_RX) || \
+                                                ((param) == FUART_TX))
+
+    typedef enum {
+        FUART_NO_ERR = 0U,
+        FUART_OVERRUN = 1U,
+        FUART_PARITY_ERR = 2U,
+        FUART_FRAMING_ERR = 3U,
+        FUART_BREAK_ERR = 4U,
+        FUART_ERRS = 5U
+    } FUART_Err;
+
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t RIN:1;     /* bit 0 */
+            uint32_t CTS:1;     /* bit 1 */
+            uint32_t DCD:1;     /* bit 2 */
+            uint32_t DSR:1;     /* bit 3 */
+            uint32_t RxFIFO:1;  /* bit 4 */
+            uint32_t TxFIFO:1;  /* bit 5 */
+            uint32_t RxTimeout:1;       /* bit 6 */
+            uint32_t FramingErr:1;      /* bit 7 */
+            uint32_t ParityErr:1;       /* bit 8 */
+            uint32_t BreakErr:1;        /* bit 9 */
+            uint32_t OverrunErr:1;      /* bit 10 */
+            uint32_t Reserved:21;       /* bit 11~31 */
+        } Bit;
+    } FUART_INTStatus;
+
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t CTS:1;     /* bit 0 */
+            uint32_t DSR:1;     /* bit 1 */
+            uint32_t DCD:1;     /* bit 2 */
+            uint32_t Reserved1:5;       /* bit 3~7 */
+            uint32_t RI:1;      /* bit 8 */
+            uint32_t Reserved2:1;       /* bit 9 */
+            uint32_t DTR:1;     /* bit 10 */
+            uint32_t RTS:1;     /* bit 11 */
+            uint32_t Reserved3:20;      /* bit 12~31 */
+        } Bit;
+    } FUART_AllModemStatus;
+
+    typedef enum {
+        FUART_MODEM_STATUS_1 = 0U,
+        FUART_MODEM_STATUS_0 = 1U
+    } FUART_ModemStatus;
+
+#define IS_MODEM_STATUS(param)                 (((param) == FUART_MODEM_STATUS_1) || \
+                                                ((param) == FUART_MODEM_STATUS_0))
+
+/** @} */
+/* End of group FUART_Exported_Types */
+
+/** @defgroup FUART_Exported_FunctionPrototypes
+  * @{
+  */
+
+    void FUART_Enable(TSB_FUART_TypeDef * FUARTx);
+    void FUART_Disable(TSB_FUART_TypeDef * FUARTx);
+    uint32_t FUART_GetRxData(TSB_FUART_TypeDef * FUARTx);
+    void FUART_SetTxData(TSB_FUART_TypeDef * FUARTx, uint32_t Data);
+    FUART_Err FUART_GetErrStatus(TSB_FUART_TypeDef * FUARTx);
+    void FUART_ClearErrStatus(TSB_FUART_TypeDef * FUARTx);
+    WorkState FUART_GetBusyState(TSB_FUART_TypeDef * FUARTx);
+    FUART_StorageStatus FUART_GetStorageStatus(TSB_FUART_TypeDef * FUARTx,
+                                               FUART_Direction Direction);
+    void FUART_SetIrDADivisor(TSB_FUART_TypeDef * FUARTx, uint32_t Divisor);
+    void FUART_Init(TSB_FUART_TypeDef * FUARTx, FUART_InitTypeDef * InitStruct);
+    void FUART_EnableFIFO(TSB_FUART_TypeDef * FUARTx);
+    void FUART_DisableFIFO(TSB_FUART_TypeDef * FUARTx);
+    void FUART_SetSendBreak(TSB_FUART_TypeDef * FUARTx, FunctionalState NewState);
+    void FUART_SetIrDAEncodeMode(TSB_FUART_TypeDef * FUARTx, uint32_t Mode);
+    Result FUART_EnableIrDA(TSB_FUART_TypeDef * FUARTx);
+    void FUART_DisableIrDA(TSB_FUART_TypeDef * FUARTx);
+    void FUART_SetINTFIFOLevel(TSB_FUART_TypeDef * FUARTx, uint32_t RxLevel, uint32_t TxLevel);
+    void FUART_SetINTMask(TSB_FUART_TypeDef * FUARTx, uint32_t IntMaskSrc);
+    FUART_INTStatus FUART_GetINTMask(TSB_FUART_TypeDef * FUARTx);
+    FUART_INTStatus FUART_GetRawINTStatus(TSB_FUART_TypeDef * FUARTx);
+    FUART_INTStatus FUART_GetMaskedINTStatus(TSB_FUART_TypeDef * FUARTx);
+    void FUART_ClearINT(TSB_FUART_TypeDef * FUARTx, FUART_INTStatus INTStatus);
+    void FUART_SetDMAOnErr(TSB_FUART_TypeDef * FUARTx, FunctionalState NewState);
+    void FUART_SetFIFODMA(TSB_FUART_TypeDef * FUARTx, FUART_Direction Direction,
+                          FunctionalState NewState);
+    FUART_AllModemStatus FUART_GetModemStatus(TSB_FUART_TypeDef * FUARTx);
+    void FUART_SetRTSStatus(TSB_FUART_TypeDef * FUARTx, FUART_ModemStatus Status);
+    void FUART_SetDTRStatus(TSB_FUART_TypeDef * FUARTx, FUART_ModemStatus Status);
+
+/** @} */
+/* End of group FUART_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group FUART */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM46B_FUART_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_gpio.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,217 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_gpio.h
+ * @brief   This file provides all the functions prototypes for GPIO driver. 
+ * @version V2.0.2.1
+ * @date    2015/02/09
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_GPIO_H
+#define __TMPM46B_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+/** @addtogroup GPIO
+  * @{
+  */
+/** @addtogroup  GPIO_Parameter_Definition
+  * @{
+  */
+
+/** @brief :The maximum number of the Function Register
+  * Note for porting:
+  * If function register 6 is the maximum number in 
+  * all the GPIO port,then define FRMAX (6U)
+  */
+#define FRMAX  (6U)             /* the max number of Port I/O function register is 6 */
+
+/** @brief: define for function register
+  * Note for porting:
+  * If the maximum number of the function Register is 6,
+  * then you need to define 6 GPIO_FUNC_REG_x ,
+  * the value should be increased from 0 to 5
+  */
+#define GPIO_FUNC_REG_1                 ((uint8_t)0x00)
+#define GPIO_FUNC_REG_2                 ((uint8_t)0x01)
+#define GPIO_FUNC_REG_3                 ((uint8_t)0x02)
+#define GPIO_FUNC_REG_4                 ((uint8_t)0x03)
+#define GPIO_FUNC_REG_5                 ((uint8_t)0x04)
+#define GPIO_FUNC_REG_6                 ((uint8_t)0x05)
+
+/** @brief :The GPIO_Port enum
+  * Note for porting:
+  * the port value order from low to high with '1' step
+  * and begin with "0".
+  */
+    typedef enum {
+        GPIO_PA = 0U,
+        GPIO_PB = 1U,
+        GPIO_PC = 2U,
+        GPIO_PD = 3U,
+        GPIO_PE = 4U,
+        GPIO_PF = 5U,
+        GPIO_PG = 6U,
+        GPIO_PH = 7U,
+        GPIO_PJ = 8U,
+        GPIO_PK = 9U,
+        GPIO_PL = 10U
+    } GPIO_Port;
+
+#define IS_GPIO_PORT(param)             ((param) <= GPIO_PL)    /* parameter checking for port number */
+
+#define RESER  (8U-(FRMAX))
+
+    typedef struct {
+        __IO uint32_t DATA;
+        __IO uint32_t CR;
+        __IO uint32_t FR[FRMAX];
+        uint32_t RESERVED0[RESER];
+        __IO uint32_t OD;
+        __IO uint32_t PUP;
+        __IO uint32_t PDN;
+        uint32_t RESERVED1;
+        __IO uint32_t IE;
+    } TSB_Port_TypeDef;
+
+    typedef struct {
+        uint8_t PinDATA;
+        uint8_t PinCR;
+        uint8_t PinFR[FRMAX];
+        uint8_t PinOD;
+        uint8_t PinPUP;
+        uint8_t PinPDN;
+        uint8_t PinIE;
+    } GPIO_RegTypeDef;
+
+    typedef struct {
+        uint8_t IOMode;        /* Set the port input or output mode     */
+        uint8_t PullUp;        /* Enable or disable Pull-up function    */
+        uint8_t OpenDrain;     /* Enable or disable open drain function */
+        uint8_t PullDown;      /* Enable or disable Pull-down function  */
+    } GPIO_InitTypeDef;
+
+#define GPIO_INPUT_MODE                 ((uint8_t)0x00)
+#define GPIO_OUTPUT_MODE                ((uint8_t)0x01)
+#define GPIO_IO_MODE_NONE               ((uint8_t)0x02)
+#define IS_GPIO_IO_MODE_STATE(param)    (((param) == GPIO_INPUT_MODE) || \
+                                         ((param) == GPIO_OUTPUT_MODE) || \
+                                         ((param) == GPIO_IO_MODE_NONE))
+
+#define GPIO_PULLUP_DISABLE             ((uint8_t)0x00)
+#define GPIO_PULLUP_ENABLE              ((uint8_t)0x01)
+#define GPIO_PULLUP_NONE                ((uint8_t)0x02)
+#define IS_GPIO_PULLUP_STATE(param)     (((param) == GPIO_PULLUP_ENABLE) || \
+                                         ((param) == GPIO_PULLUP_DISABLE) || \
+                                         ((param) == GPIO_PULLUP_NONE))
+
+#define GPIO_PULLDOWN_DISABLE           ((uint8_t)0x00)
+#define GPIO_PULLDOWN_ENABLE            ((uint8_t)0x01)
+#define GPIO_PULLDOWN_NONE              ((uint8_t)0x02)
+#define IS_GPIO_PULLDOWN_STATE(param)   (((param) == GPIO_PULLDOWN_ENABLE) || \
+                                         ((param) == GPIO_PULLDOWN_DISABLE) || \
+                                         ((param) == GPIO_PULLDOWN_NONE))
+
+#define GPIO_OPEN_DRAIN_DISABLE         ((uint8_t)0x00)
+#define GPIO_OPEN_DRAIN_ENABLE          ((uint8_t)0x01)
+#define GPIO_OPEN_DRAIN_NONE            ((uint8_t)0x02)
+#define IS_GPIO_OPEN_DRAIN_STATE(param) (((param) == GPIO_OPEN_DRAIN_ENABLE) || \
+                                         ((param) == GPIO_OPEN_DRAIN_DISABLE) || \
+                                         ((param) == GPIO_OPEN_DRAIN_NONE))
+
+#define GPIO_BIT_VALUE_1                ((uint8_t)0x01)
+#define GPIO_BIT_VALUE_0                ((uint8_t)0x00)
+
+#define IS_GPIO_BIT_VALUE(BitValue)     (((BitValue) == GPIO_BIT_VALUE_1)|| \
+                                         ((BitValue) == GPIO_BIT_VALUE_0))
+
+#define GPIO_BIT_0                      ((uint8_t)0x01)
+#define GPIO_BIT_1                      ((uint8_t)0x02)
+#define GPIO_BIT_2                      ((uint8_t)0x04)
+#define GPIO_BIT_3                      ((uint8_t)0x08)
+#define GPIO_BIT_4                      ((uint8_t)0x10)
+#define GPIO_BIT_5                      ((uint8_t)0x20)
+#define GPIO_BIT_6                      ((uint8_t)0x40)
+#define GPIO_BIT_7                      ((uint8_t)0x80)
+#define GPIO_BIT_ALL                    ((uint8_t)0xFF)
+
+#define IS_GPIO_WRITE(GPIO_x)                       (GPIO_SFRs[(GPIO_x)].PinCR)
+
+#define IS_GPIO_BIT_DATA(GPIO_x,Bit_x)              ((((GPIO_SFRs[(GPIO_x)].PinDATA) & (Bit_x))&&\
+                                                    (!((uint8_t)(~(GPIO_SFRs[(GPIO_x)].PinDATA))&(Bit_x)))))
+
+#define IS_GPIO_BIT_OUT(GPIO_x,Bit_x)               (((GPIO_SFRs[(GPIO_x)].PinCR &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinCR)&(Bit_x)))))
+
+#define IS_GPIO_BIT_IN(GPIO_x,Bit_x)                (((GPIO_SFRs[(GPIO_x)].PinIE &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinIE)&(Bit_x)))))
+
+#define IS_GPIO_BIT_PUP(GPIO_x,Bit_x)               (((GPIO_SFRs[(GPIO_x)].PinPUP &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPUP)&(Bit_x)))))
+
+#define IS_GPIO_BIT_PDN(GPIO_x,Bit_x)               (((GPIO_SFRs[(GPIO_x)].PinPDN &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinPDN)&(Bit_x)))))
+
+#define IS_GPIO_BIT_OD(GPIO_x,Bit_x)                (((GPIO_SFRs[(GPIO_x)].PinOD &(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinOD)&(Bit_x)))))
+
+#define IS_GPIO_BIT_FR(GPIO_x,FuncReg_x,Bit_x)      (((GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)]&(Bit_x))&&\
+                                                    (!((uint8_t)(~GPIO_SFRs[(GPIO_x)].PinFR[(FuncReg_x)])&(Bit_x)))))
+
+#define IS_GPIO_FUNCTION_REG(param)     ((param) < (FRMAX))
+
+#define IS_GPIO_BIT(param)              (((param) == GPIO_BIT_0)|| \
+                                         ((param) == GPIO_BIT_1)|| \
+                                         ((param) == GPIO_BIT_2)|| \
+                                         ((param) == GPIO_BIT_3)|| \
+                                         ((param) == GPIO_BIT_4)|| \
+                                         ((param) == GPIO_BIT_5)|| \
+                                         ((param) == GPIO_BIT_6)|| \
+                                         ((param) == GPIO_BIT_7))
+/** @} */
+/* End of group GPIO_Bit_Define */
+
+/** @defgroup GPIO_Exported_FunctionPrototypes
+  * @{
+  */
+
+    uint8_t GPIO_ReadData(GPIO_Port GPIO_x);
+    uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x);
+    void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data);
+    void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue);
+    void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct);
+    void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x);
+    void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x);
+    void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
+    void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
+    void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
+    void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
+    void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState);
+    void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x);
+    void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x);
+
+/** @} */
+/* End of group GPIO_Exported_FunctionPrototypes */
+/** @} */
+/* End of group GPIO */
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif                          
+#endif                          /* __TMPM46B_GPIO_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_i2c.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,176 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_i2c.h
+ * @brief   This file provides all the functions prototypes for I2C driver.
+ * @version V2.0.2.1
+ * @date    2015/02/13
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_I2C_H
+#define __TMPM46B_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif  /*__cplusplus*/
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/** @defgroup I2C_Exported_Types
+  * @{
+  */
+    typedef struct {
+        uint32_t I2CSelfAddr;           /*!< Specify self-address of the I2C channel in I2C mode */
+        uint32_t I2CDataLen;            /*!< Specify data length of the I2C channel in I2C mode */
+        FunctionalState I2CACKState;    /*!< Enable or disable the generation of ACK clock */
+        uint32_t I2CClkDiv;             /*!< Select the division of the prescaler clock for generating the serial clock */
+        uint32_t PrescalerClkDiv;       /*!< Select the division of fsys for generating the fprsck */
+    } I2C_InitTypeDef;
+
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t LastRxBit:1;
+            uint32_t GeneralCall:1;
+            uint32_t SlaveAddrMatch:1;
+            uint32_t ArbitrationLost:1;
+            uint32_t INTReq:1;
+            uint32_t BusState:1;
+            uint32_t TRx:1;
+            uint32_t MasterSlave:1;
+        } Bit;
+    } I2C_State;
+
+#define I2C_CHANNEL_NUMBER              3U
+#define IS_I2C_PERIPH(param)      (((param) == TSB_I2C0) || \
+                                   ((param) == TSB_I2C1) || \
+                                   ((param) == TSB_I2C2))
+
+#define I2C_DATA_LEN_8              ((uint32_t)0x00000000)
+#define I2C_DATA_LEN_1              ((uint32_t)0x00000001)
+#define I2C_DATA_LEN_2              ((uint32_t)0x00000002)
+#define I2C_DATA_LEN_3              ((uint32_t)0x00000003)
+#define I2C_DATA_LEN_4              ((uint32_t)0x00000004)
+#define I2C_DATA_LEN_5              ((uint32_t)0x00000005)
+#define I2C_DATA_LEN_6              ((uint32_t)0x00000006)
+#define I2C_DATA_LEN_7              ((uint32_t)0x00000007)
+
+#define I2C_SCK_CLK_DIV_20              ((uint32_t)0x00000000)
+#define I2C_SCK_CLK_DIV_24              ((uint32_t)0x00000001)
+#define I2C_SCK_CLK_DIV_32              ((uint32_t)0x00000002)
+#define I2C_SCK_CLK_DIV_48              ((uint32_t)0x00000003)
+#define I2C_SCK_CLK_DIV_80              ((uint32_t)0x00000004)
+#define I2C_SCK_CLK_DIV_144             ((uint32_t)0x00000005)
+#define I2C_SCK_CLK_DIV_272             ((uint32_t)0x00000006)
+#define I2C_SCK_CLK_DIV_528             ((uint32_t)0x00000007)
+#define IS_I2C_SCK_CLK_DIV(param)       (((param) == I2C_SCK_CLK_DIV_20) || \
+                                         ((param) == I2C_SCK_CLK_DIV_24) || \
+                                         ((param) == I2C_SCK_CLK_DIV_32) || \
+                                         ((param) == I2C_SCK_CLK_DIV_48) || \
+                                         ((param) == I2C_SCK_CLK_DIV_80) || \
+                                         ((param) == I2C_SCK_CLK_DIV_144) || \
+                                         ((param) == I2C_SCK_CLK_DIV_272) || \
+                                         ((param) == I2C_SCK_CLK_DIV_528))
+
+#define I2C_PRESCALER_DIV_1              ((uint32_t)0x00000001)
+#define I2C_PRESCALER_DIV_2              ((uint32_t)0x00000002)
+#define I2C_PRESCALER_DIV_3              ((uint32_t)0x00000003)
+#define I2C_PRESCALER_DIV_4              ((uint32_t)0x00000004)
+#define I2C_PRESCALER_DIV_5              ((uint32_t)0x00000005)
+#define I2C_PRESCALER_DIV_6              ((uint32_t)0x00000006)
+#define I2C_PRESCALER_DIV_7              ((uint32_t)0x00000007)
+#define I2C_PRESCALER_DIV_8              ((uint32_t)0x00000008)
+#define I2C_PRESCALER_DIV_9              ((uint32_t)0x00000009)
+#define I2C_PRESCALER_DIV_10             ((uint32_t)0x0000000A)
+#define I2C_PRESCALER_DIV_11             ((uint32_t)0x0000000B)
+#define I2C_PRESCALER_DIV_12             ((uint32_t)0x0000000C)
+#define I2C_PRESCALER_DIV_13             ((uint32_t)0x0000000D)
+#define I2C_PRESCALER_DIV_14             ((uint32_t)0x0000000E)
+#define I2C_PRESCALER_DIV_15             ((uint32_t)0x0000000F)
+#define I2C_PRESCALER_DIV_16             ((uint32_t)0x00000010)
+#define I2C_PRESCALER_DIV_17             ((uint32_t)0x00000011)
+#define I2C_PRESCALER_DIV_18             ((uint32_t)0x00000012)
+#define I2C_PRESCALER_DIV_19             ((uint32_t)0x00000013)
+#define I2C_PRESCALER_DIV_20             ((uint32_t)0x00000014)
+#define I2C_PRESCALER_DIV_21             ((uint32_t)0x00000015)
+#define I2C_PRESCALER_DIV_22             ((uint32_t)0x00000016)
+#define I2C_PRESCALER_DIV_23             ((uint32_t)0x00000017)
+#define I2C_PRESCALER_DIV_24             ((uint32_t)0x00000018)
+#define I2C_PRESCALER_DIV_25             ((uint32_t)0x00000019)
+#define I2C_PRESCALER_DIV_26             ((uint32_t)0x0000001A)
+#define I2C_PRESCALER_DIV_27             ((uint32_t)0x0000001B)
+#define I2C_PRESCALER_DIV_28             ((uint32_t)0x0000001C)
+#define I2C_PRESCALER_DIV_29             ((uint32_t)0x0000001D)
+#define I2C_PRESCALER_DIV_30             ((uint32_t)0x0000001E)
+#define I2C_PRESCALER_DIV_31             ((uint32_t)0x0000001F)
+#define I2C_PRESCALER_DIV_32             ((uint32_t)0x00000020)
+
+/** @} */
+/* End of group I2C_Exported_Types */
+
+/** @defgroup I2C_Exported_Macros 
+  * @{
+  */
+#define IS_PRESCALER_CLK_VALID(param1, param2)     (((param1) >= I2C_PRESCALER_DIV_1) && \
+                                                    ((param1) <= I2C_PRESCALER_DIV_32) && \
+                                                    (((param2) / (param1)) > 666666U) && \
+                                                    (((param2) / (param1)) < 20000000U))
+
+#define IS_I2C_DATA(param)              ((param) <= (uint32_t)0x000000FF)
+
+#define IS_I2C_BIT_NUM(param)           ((param) <= (uint32_t)0x00000007)
+
+#define IS_I2C_ADDR(param)              (((param) < (uint32_t)0x000000FF) && \
+                                         (!((param) & (uint32_t)0x00000001)))
+
+/** @} */
+/* End of group I2C_Exported_Macros */
+
+/** @defgroup I2C_Exported_FunctionPrototypes
+  * @{
+  */
+
+    void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct);
+    void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum);
+    void I2C_SWReset(TSB_I2C_TypeDef * I2Cx);
+    void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx);
+    void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx);
+    void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx);
+    I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx);
+    void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data);
+    uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx);
+    void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx);
+    void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock);
+    void I2C_SetINTReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState);
+    FunctionalState I2C_GetINTStatus(TSB_I2C_TypeDef * I2Cx);
+    void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx);
+/** @} */
+/* End of group I2C_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group I2C */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM46B_I2C_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_rtc.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,237 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_rtc.h
+ * @brief   This file provides all the functions prototypes for RTC driver.
+ * @version V2.0.2.1
+ * @date    2015/02/11
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_RTC_H
+#define __TMPM46B_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */
+
+/** @defgroup RTC_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  RTC Structure definition  
+  */
+
+    typedef struct {
+        uint8_t HourMode;       /*!< Select RTC 12-Hour mode or 24-Hour mode */
+        uint8_t Hour;           /*!< Set RTC hour value                      */
+        uint8_t AmPm;           /*!< Select AM/PM mode in 12H mode           */
+        uint8_t Min;            /*!< Set RTC minute value                    */
+        uint8_t Sec;            /*!< Set RTC second value                    */
+    } RTC_TimeTypeDef;
+
+    typedef struct {
+        uint8_t LeapYear;       /*!< Select RTC Leap-Year status */
+        uint8_t Year;           /*!< Set RTC year value          */
+        uint8_t Month;          /*!< Set RTC month value         */
+        uint8_t Date;           /*!< Set RTC date value          */
+        uint8_t Day;            /*!< Set RTC day value           */
+    } RTC_DateTypeDef;
+
+    typedef struct {
+        uint8_t Date;           /*!< Set alarm date value          */
+        uint8_t Day;            /*!< Set alarm day value           */
+        uint8_t Hour;           /*!< Set alarm hour value          */
+        uint8_t AmPm;           /*!< Select AM/PM mode in 12H mode */
+        uint8_t Min;            /*!< Set alarm minute value        */
+    } RTC_AlarmTypeDef;
+
+/** @} */
+/* End of group RTC_Exported_Types */
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */
+
+#define RTC_24_HOUR_MODE      ((uint8_t)0x01)
+#define RTC_12_HOUR_MODE      ((uint8_t)0x00)
+#define IS_RTC_HOUR_MODE(param)      (((param) == RTC_24_HOUR_MODE) || \
+                                      ((param) == RTC_12_HOUR_MODE))
+
+#define RTC_AM_MODE      ((uint8_t)0x00)
+#define RTC_PM_MODE      ((uint8_t)0x01)
+#define RTC_AMPM_INVALID ((uint8_t)0x02)
+#define IS_RTC_AMPM_MODE(param)      (((param) == RTC_AM_MODE) || \
+                                      ((param) == RTC_PM_MODE))
+
+#define RTC_LEAP_YEAR_0             ((uint8_t)0x00)
+#define RTC_LEAP_YEAR_1             ((uint8_t)0x01)
+#define RTC_LEAP_YEAR_2             ((uint8_t)0x02)
+#define RTC_LEAP_YEAR_3             ((uint8_t)0x03)
+#define IS_RTC_LEAP_YEAR(param)   (((param) == RTC_LEAP_YEAR_0) || \
+                                   ((param) == RTC_LEAP_YEAR_1) || \
+                                   ((param) == RTC_LEAP_YEAR_2) || \
+                                   ((param) == RTC_LEAP_YEAR_3))
+
+#define RTC_SUN             ((uint8_t)0x00)
+#define RTC_MON             ((uint8_t)0x01)
+#define RTC_TUE             ((uint8_t)0x02)
+#define RTC_WED             ((uint8_t)0x03)
+#define RTC_THU             ((uint8_t)0x04)
+#define RTC_FRI             ((uint8_t)0x05)
+#define RTC_SAT             ((uint8_t)0x06)
+#define IS_RTC_DAY(param)  (((param) == RTC_SUN) || \
+                            ((param) == RTC_MON) || \
+                            ((param) == RTC_TUE) || \
+                            ((param) == RTC_WED) || \
+                            ((param) == RTC_THU) || \
+                            ((param) == RTC_FRI) || \
+                            ((param) == RTC_SAT))
+
+#define RTC_LOW_LEVEL               ((uint8_t)0x00)
+#define RTC_PULSE_1_HZ              ((uint8_t)0x01)
+#define RTC_PULSE_16_HZ             ((uint8_t)0x02)
+#define RTC_PULSE_2_HZ              ((uint8_t)0x03)
+#define RTC_PULSE_4_HZ              ((uint8_t)0x04)
+#define RTC_PULSE_8_HZ              ((uint8_t)0x05)
+#define IS_RTC_ALARM_OUTPUT(param)   (((param) == RTC_LOW_LEVEL) || \
+                                      ((param) == RTC_PULSE_1_HZ) || \
+                                      ((param) == RTC_PULSE_16_HZ)|| \
+                                      ((param) == RTC_PULSE_2_HZ) || \
+                                      ((param) == RTC_PULSE_4_HZ) || \
+                                      ((param) == RTC_PULSE_8_HZ))
+
+#define IS_RTC_YEAR(param)        ((param) <= 99U)
+
+#define IS_RTC_MONTH(param)       (((param) >= 1U)&&((param) <= 12U))
+
+#define IS_RTC_DATE(param)        (((param) >= 1U)&&((param) <= 31U))
+
+#define IS_RTC_HOUR_24(param)     ((param) <= 23U)
+
+#define IS_RTC_HOUR_12(param)     ((param) <= 11U)
+
+#define IS_RTC_MINUTE(param)      ((param) <= 59U)
+
+#define IS_RTC_SECOND(param)      ((param) <= 59U)
+
+#define RTC_ADJ_TIME_1_SEC          ((uint8_t)0x00)
+#define RTC_ADJ_TIME_10_SEC         ((uint8_t)0x02)
+#define RTC_ADJ_TIME_20_SEC         ((uint8_t)0x04)
+#define RTC_ADJ_TIME_30_SEC         ((uint8_t)0x06)
+#define RTC_ADJ_TIME_1_MIN          ((uint8_t)0x08)
+#define IS_RTC_ADJ_TIME(param)      (((param) == RTC_ADJ_TIME_1_SEC)  || \
+                                     ((param) == RTC_ADJ_TIME_10_SEC) || \
+                                     ((param) == RTC_ADJ_TIME_20_SEC) || \
+                                     ((param) == RTC_ADJ_TIME_30_SEC) || \
+                                     ((param) == RTC_ADJ_TIME_1_MIN))
+/** @} */
+/* End of group RTC_Exported_Constants */
+
+/** @defgroup RTC_Exported_Types
+  * @{
+  */
+
+    typedef enum {
+        RTC_NO_REQ = 0U,
+        RTC_REQ = 1U
+    } RTC_ReqState;
+
+    typedef enum {
+        RTC_CLOCK_MODE = 0U,
+        RTC_ALARM_MODE = 1U
+    } RTC_FuncMode;
+#define IS_RTC_FUNC_MODE(param)       (((param) == RTC_CLOCK_MODE) || \
+                                       ((param) == RTC_ALARM_MODE))
+
+    typedef enum {
+        RTC_CORRECTION_PLUS = 0U,
+        RTC_CORRECTION_MINUS = 1U
+    } RTC_CorrectionMode;
+#define IS_RTC_CORRECTION_MODE(param)  (((param) == RTC_CORRECTION_PLUS) || \
+                                        ((param) == RTC_CORRECTION_MINUS))
+
+#define IS_RTC_PLUS_VALUE(param)        ((param) <= 255U)
+#define IS_RTC_MINUS_VALUE(param)       (((param) >= 1U)&&((param) <= 256U))
+/** @} */
+/* End of group RTC_Exported_Types */
+
+/** @defgroup RTC_Exported_FunctionPrototypes
+  * @{
+  */
+
+    void RTC_SetSec(uint8_t Sec);
+    uint8_t RTC_GetSec(void);
+    void RTC_SetMin(RTC_FuncMode NewMode, uint8_t Min);
+    uint8_t RTC_GetMin(RTC_FuncMode NewMode);
+    uint8_t RTC_GetAMPM(RTC_FuncMode NewMode);
+    void RTC_SetHour24(RTC_FuncMode NewMode, uint8_t Hour);
+    void RTC_SetHour12(RTC_FuncMode NewMode, uint8_t Hour, uint8_t AmPm);
+    uint8_t RTC_GetHour(RTC_FuncMode NewMode);
+    void RTC_SetDay(RTC_FuncMode NewMode, uint8_t Day);
+    uint8_t RTC_GetDay(RTC_FuncMode NewMode);
+    void RTC_SetDate(RTC_FuncMode NewMode, uint8_t Date);
+    uint8_t RTC_GetDate(RTC_FuncMode NewMode);
+    void RTC_SetMonth(uint8_t Month);
+    uint8_t RTC_GetMonth(void);
+    void RTC_SetYear(uint8_t Year);
+    uint8_t RTC_GetYear(void);
+    void RTC_SetHourMode(uint8_t HourMode);
+    uint8_t RTC_GetHourMode(void);
+    void RTC_SetLeapYear(uint8_t LeapYear);
+    uint8_t RTC_GetLeapYear(void);
+    void RTC_SetTimeAdjustReq(void);
+    RTC_ReqState RTC_GetTimeAdjustReq(void);
+    void RTC_EnableClock(void);
+    void RTC_DisableClock(void);
+    void RTC_EnableAlarm(void);
+    void RTC_DisableAlarm(void);
+    void RTC_SetRTCINT(FunctionalState NewState);
+    void RTC_SetAlarmOutput(uint8_t Output);
+    void RTC_ResetAlarm(void);
+    void RTC_ResetClockSec(void);
+    RTC_ReqState RTC_GetResetClockSecReq(void);
+    void RTC_SetDateValue(RTC_DateTypeDef * DateStruct);
+    void RTC_GetDateValue(RTC_DateTypeDef * DateStruct);
+    void RTC_SetTimeValue(RTC_TimeTypeDef * TimeStruct);
+    void RTC_GetTimeValue(RTC_TimeTypeDef * TimeStruct);
+    void RTC_SetClockValue(RTC_DateTypeDef * DateStruct, RTC_TimeTypeDef * TimeStruct);
+    void RTC_GetClockValue(RTC_DateTypeDef * DateStruct, RTC_TimeTypeDef * TimeStruct);
+    void RTC_SetAlarmValue(RTC_AlarmTypeDef * AlarmStruct);
+    void RTC_GetAlarmValue(RTC_AlarmTypeDef * AlarmStruct);
+    void RTC_SetProtectCtrl(FunctionalState NewState);
+    void RTC_EnableCorrection(void);
+    void RTC_DisableCorrection(void);
+    void RTC_SetCorrectionTime(uint8_t Time);
+    void RTC_SetCorrectionValue(RTC_CorrectionMode Mode, uint16_t Cnt);
+
+/** @} */
+/* End of group RTC_Exported_FunctionPrototype */
+
+/** @} */
+/* End of group RTC */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+#endif                          /* __TMPM46B_RTC_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_ssp.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,163 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_ssp.h
+ * @brief   This file provides all the functions prototypes for SSP driver.
+ * @version V2.0.2.1
+ * @date    2015/02/05
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_SSP_H
+#define __TMPM46B_SSP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup SSP
+  * @{
+  */
+
+/** @addtogroup SSP_Exported_types
+  * @{
+  */
+
+#define IS_SSP_PERIPH(param)     (((param) == TSB_SSP0)  || \
+                                  ((param) == TSB_SSP1)  || \
+                                  ((param) == TSB_SSP2) )
+
+    typedef enum {
+        SSP_FORMAT_SPI = 0U,
+        SSP_FORMAT_SSI = 1U,
+        SSP_FORMAT_MICROWIRE = 2U
+    } SSP_FrameFormat;
+#define IS_SSP_FRAME_FORMAT(param)  (((param) == SSP_FORMAT_SPI) || \
+                                     ((param) == SSP_FORMAT_SSI) || \
+                                     ((param) == SSP_FORMAT_MICROWIRE))
+
+    typedef enum {
+        SSP_POLARITY_LOW = 0U,
+        SSP_POLARITY_HIGH = 1U
+    } SSP_ClkPolarity;
+#define IS_SSP_CLK_POLARITY(param)  (((param) == SSP_POLARITY_LOW) || \
+                                     ((param) == SSP_POLARITY_HIGH))
+
+    typedef enum {
+        SSP_PHASE_FIRST_EDGE = 0U,
+        SSP_PHASE_SECOND_EDGE = 1U
+    } SSP_ClkPhase;
+#define IS_SSP_CLK_PHASE(param)  (((param) == SSP_PHASE_FIRST_EDGE) || \
+                                  ((param) == SSP_PHASE_SECOND_EDGE))
+
+    typedef enum {
+        SSP_MASTER = 0U,
+        SSP_SLAVE = 1U
+    } SSP_MS_Mode;
+#define IS_SSP_MS_MODE(param)  (((param) == SSP_MASTER) || \
+                                ((param) == SSP_SLAVE))
+
+    typedef enum {
+        SSP_FIFO_EMPTY = 0U,
+        SSP_FIFO_NORMAL = 1U,
+        SSP_FIFO_INVALID = 2U,
+        SSP_FIFO_FULL = 3U
+    } SSP_FIFOState;
+
+#define IS_SSP_PRE_SCALE(param)          (((param)>=2U)&&((param)<=254U)&&(((param)%2U)==0U))
+#define IS_SSP_DATA_BIT_SIZE(param)      (((param)>=4U)&&((param)<=16U))
+
+    typedef enum {
+        SSP_RX = 0U,
+        SSP_TX = 1U
+    } SSP_Direction;
+#define IS_SSP_DIRECTION(param)  (((param) == SSP_RX) || \
+                                  ((param) == SSP_TX))
+
+    typedef struct {
+        SSP_FrameFormat FrameFormat;
+        uint8_t PreScale;
+        uint8_t ClkRate;
+        SSP_ClkPolarity ClkPolarity;
+        SSP_ClkPhase ClkPhase;
+        uint8_t DataSize;
+        SSP_MS_Mode Mode;
+    } SSP_InitTypeDef;
+
+/* Parameter to configure SSP interrupt enable/disable Register */
+#define SSP_INTCFG_NONE         ((uint32_t)0x00000000)
+#define SSP_INTCFG_RX_OVERRUN   ((uint32_t)0x00000001)
+#define SSP_INTCFG_RX_TIMEOUT   ((uint32_t)0x00000002)
+#define SSP_INTCFG_RX           ((uint32_t)0x00000004)
+#define SSP_INTCFG_TX           ((uint32_t)0x00000008)
+#define SSP_INTCFG_ALL          ((uint32_t)0x0000000F)
+
+#define IS_SSP_INT_SRC(param)  ((param) <= SSP_INTCFG_ALL )
+
+#define IS_SSP_CLEAR_INT_SRC(param)  (((param) == SSP_INTCFG_RX_OVERRUN) || \
+                                      ((param) == SSP_INTCFG_RX_TIMEOUT) || \
+                                      ((param) == SSP_INTCFG_ALL) )
+
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t OverRun:1;    /* Bit 0 , for TSB-M4 in IAR EWARM */
+            uint32_t TimeOut:1;
+            uint32_t Rx:1;
+            uint32_t Tx:1;
+            uint32_t Reserved:28;  /* Bit 4 to 31 */
+        } Bit;
+    } SSP_INTState;
+
+/** @} */
+/* End of group SSP_Exported_types */
+
+/** @defgroup SSP_Exported_FunctionPrototypes
+  * @{
+  */
+    void SSP_Enable(TSB_SSP_TypeDef * SSPx);
+    void SSP_Disable(TSB_SSP_TypeDef * SSPx);
+    void SSP_Init(TSB_SSP_TypeDef * SSPx, SSP_InitTypeDef * InitStruct);
+    void SSP_SetClkPreScale(TSB_SSP_TypeDef * SSPx, uint8_t PreScale, uint8_t ClkRate);
+    void SSP_SetFrameFormat(TSB_SSP_TypeDef * SSPx, SSP_FrameFormat FrameFormat);
+    void SSP_SetClkPolarity(TSB_SSP_TypeDef * SSPx, SSP_ClkPolarity ClkPolarity);
+    void SSP_SetClkPhase(TSB_SSP_TypeDef * SSPx, SSP_ClkPhase ClkPhase);
+    void SSP_SetDataSize(TSB_SSP_TypeDef * SSPx, uint8_t DataSize);
+    void SSP_SetSlaveOutputCtrl(TSB_SSP_TypeDef * SSPx, FunctionalState NewState);
+    void SSP_SetMSMode(TSB_SSP_TypeDef * SSPx, SSP_MS_Mode Mode);
+    void SSP_SetLoopBackMode(TSB_SSP_TypeDef * SSPx, FunctionalState NewState);
+    void SSP_SetTxData(TSB_SSP_TypeDef * SSPx, uint16_t Data);
+    uint16_t SSP_GetRxData(TSB_SSP_TypeDef * SSPx);
+    WorkState SSP_GetWorkState(TSB_SSP_TypeDef * SSPx);
+    SSP_FIFOState SSP_GetFIFOState(TSB_SSP_TypeDef * SSPx, SSP_Direction Direction);
+    void SSP_SetINTConfig(TSB_SSP_TypeDef * SSPx, uint32_t IntSrc);
+    SSP_INTState SSP_GetINTConfig(TSB_SSP_TypeDef * SSPx);
+    SSP_INTState SSP_GetPreEnableINTState(TSB_SSP_TypeDef * SSPx);
+    SSP_INTState SSP_GetPostEnableINTState(TSB_SSP_TypeDef * SSPx);
+    void SSP_ClearINTFlag(TSB_SSP_TypeDef * SSPx, uint32_t IntSrc);
+    void SSP_SetDMACtrl(TSB_SSP_TypeDef * SSPx, SSP_Direction Direction, FunctionalState NewState);
+/** @} */
+/* End of group SSP_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group SSP */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /*__TMPM46B_SSP_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_tmrb.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,283 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_tmrb.h
+ * @brief   This file provides all the functions prototypes for TMRB driver.
+ * @version V2.0.2.1
+ * @date    2015/02/27
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_TMRB_H
+#define __TMPM46B_TMRB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif                          /* __cplusplus */
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup TMRB
+  * @{
+  */
+
+/** @defgroup TMRB_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief TMRB Init Structure definition
+  */
+
+    typedef struct {
+        uint32_t Mode;                /*!< Select TMRB mode between internal interval
+                                           timer mode and external event counter */
+        uint32_t ClkDiv;              /*!< Select the division for TMRB source clock */
+        uint32_t TrailingTiming;      /*!< Specify the trailingTiming value to be written 
+                                           into TBnRG1 */
+        uint32_t UpCntCtrl;           /*!< Select up-counter work mode between 
+                                           freerun and auto-reload */
+        uint32_t LeadingTiming;       /*!< Specify the LeadingTiming value to be written 
+                                           into TBnRG0 */
+    } TMRB_InitTypeDef;
+
+/**
+  * @brief TMRB Flip-flop Structure definition
+  */
+
+    typedef struct {
+        uint32_t FlipflopCtrl;        /*!< Select TMRB flip-flop output level */
+        uint32_t FlipflopReverseTrg;  /*!< Specify TMRB flip-flop reverse trigger */
+    } TMRB_FFOutputTypeDef;
+
+/**
+  * @brief TMRB Interrupt factor Union definition
+  */
+    typedef union {
+        uint32_t All;
+        struct {
+            uint32_t MatchLeadingTiming:1;
+            uint32_t MatchTrailingTiming:1;
+            uint32_t OverFlow:1;
+            uint32_t Reserverd:29;
+        } Bit;
+    } TMRB_INTFactor;
+
+/** @} */
+/* End of group TMRB_Exported_Types */
+
+/** @defgroup TMRB_Exported_Constants
+  * @{
+  */
+#define TSB_TB_MPT0                  ((TSB_TB_TypeDef *)TSB_MT0)
+#define TSB_TB_MPT1                  ((TSB_TB_TypeDef *)TSB_MT1)
+#define TSB_TB_MPT2                  ((TSB_TB_TypeDef *)TSB_MT2)
+#define TSB_TB_MPT3                  ((TSB_TB_TypeDef *)TSB_MT3)
+#define IS_TMRB_ALL_PERIPH(param)    (((param) == TSB_TB0) || \
+                                      ((param) == TSB_TB1) || \
+                                      ((param) == TSB_TB2) || \
+                                      ((param) == TSB_TB3) || \
+                                      ((param) == TSB_TB4) || \
+                                      ((param) == TSB_TB5) || \
+                                      ((param) == TSB_TB6) || \
+                                      ((param) == TSB_TB7) || \
+                                      ((param) == TSB_TB_MPT0) || \
+                                      ((param) == TSB_TB_MPT1) || \
+                                      ((param) == TSB_TB_MPT2) || \
+                                      ((param) == TSB_TB_MPT3))
+
+#define IS_TMRB_TMRB_PERIPH(param)   (((param) == TSB_TB0) || \
+                                      ((param) == TSB_TB1) || \
+                                      ((param) == TSB_TB2) || \
+                                      ((param) == TSB_TB3) || \
+                                      ((param) == TSB_TB4) || \
+                                      ((param) == TSB_TB5) || \
+                                      ((param) == TSB_TB6) || \
+                                      ((param) == TSB_TB7))
+
+#define IS_TMRB_MPT_PERIPH(param)    (((param) == TSB_TB_MPT0) || \
+                                      ((param) == TSB_TB_MPT1) || \
+                                      ((param) == TSB_TB_MPT2) || \
+                                      ((param) == TSB_TB_MPT3))
+
+#define IS_TMRB_SYNC_PERIPH(param)   (((param) == TSB_TB1) || \
+                                      ((param) == TSB_TB2) || \
+                                      ((param) == TSB_TB3) || \
+                                      ((param) == TSB_TB5) || \
+                                      ((param) == TSB_TB6) || \
+                                      ((param) == TSB_TB7))
+
+#define TMRB_INTERVAL_TIMER          ((uint32_t)0x00000001)
+#define TMRB_EVENT_CNT               ((uint32_t)0x00000000)
+#define IS_TMRB_MODE(param)          (((param) == TMRB_INTERVAL_TIMER) || \
+                                      ((param) == TMRB_EVENT_CNT))
+
+#define TMRB_CLK_DIV_2               ((uint32_t)0x00000001)
+#define TMRB_CLK_DIV_8               ((uint32_t)0x00000002)
+#define TMRB_CLK_DIV_32              ((uint32_t)0x00000003)
+#define TMRB_CLK_DIV_64              ((uint32_t)0x00000004)
+#define TMRB_CLK_DIV_128             ((uint32_t)0x00000005)
+#define TMRB_CLK_DIV_256             ((uint32_t)0x00000006)
+#define TMRB_CLK_DIV_512             ((uint32_t)0x00000007)
+#define IS_TMRB_CLK_DIV(param)       (((param) == TMRB_CLK_DIV_2) || \
+                                      ((param) == TMRB_CLK_DIV_8) || \
+                                      ((param) == TMRB_CLK_DIV_32) || \
+                                      ((param) == TMRB_CLK_DIV_64) || \
+                                      ((param) == TMRB_CLK_DIV_128) || \
+                                      ((param) == TMRB_CLK_DIV_256) || \
+                                      ((param) == TMRB_CLK_DIV_512))
+
+#define IS_MPT_CLK_DIV(param)        (((param) == TMRB_CLK_DIV_2) || \
+                                      ((param) == TMRB_CLK_DIV_8) || \
+                                      ((param) == TMRB_CLK_DIV_32))
+
+#define TMRB_FREE_RUN                ((uint32_t)0x00000000)
+#define TMRB_AUTO_CLEAR              ((uint32_t)0x00000008)
+#define IS_TMRB_UC_CTRL(param)       (((param) == TMRB_FREE_RUN) || \
+                                      ((param) == TMRB_AUTO_CLEAR))
+
+#define MPT_FREE_RUN                 ((uint32_t)0x00000000)
+#define MPT_AUTO_CLEAR               ((uint32_t)0x00000004)
+#define IS_MPT_UC_CTRL(param)        (((param) == MPT_FREE_RUN) || \
+                                      ((param) == MPT_AUTO_CLEAR))
+
+#define TMRB_FLIPFLOP_INVERT         ((uint32_t)0x00000000)
+#define TMRB_FLIPFLOP_SET            ((uint32_t)0x00000001)
+#define TMRB_FLIPFLOP_CLEAR          ((uint32_t)0x00000002)
+#define IS_TMRB_FLIPFLOP_CTRL(param) (((param) == TMRB_FLIPFLOP_INVERT) || \
+                                      ((param) == TMRB_FLIPFLOP_SET) || \
+                                      ((param) == TMRB_FLIPFLOP_CLEAR))
+
+#define TMRB_DISABLE_FLIPFLOP        ((uint32_t)0x00000000)
+#define TMRB_FLIPFLOP_TAKE_CAPTURE_0 ((uint32_t)0x00000010)
+#define TMRB_FLIPFLOP_TAKE_CAPTURE_1 ((uint32_t)0x00000020)
+#define TMRB_FLIPFLOP_MATCH_TRAILING ((uint32_t)0x00000008)
+#define TMRB_FLIPFLOP_MATCH_LEADING  ((uint32_t)0x00000004)
+#define IS_TMRB_FLIPFLOP_TRG(param)  (((param) == TMRB_DISABLE_FLIPFLOP) || \
+                                      ((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_0) || \
+                                      ((param) == TMRB_FLIPFLOP_TAKE_CAPTURE_1) || \
+                                      ((param) == TMRB_FLIPFLOP_MATCH_TRAILING) || \
+                                      ((param) == TMRB_FLIPFLOP_MATCH_LEADING) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_LEADING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_LEADING)) || \
+                                      ((param) == (TMRB_FLIPFLOP_TAKE_CAPTURE_0 | TMRB_FLIPFLOP_TAKE_CAPTURE_1 | TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING)))
+
+#define TMRB_DISABLE_CAPTURE                          ((uint32_t)0x00000000)
+#define TMRB_CAPTURE_TBIN0_TBIN1_RISING               ((uint32_t)0x00000100)
+#define TMRB_CAPTURE_TBIN0_RISING_FALLING             ((uint32_t)0x00000200)
+#define TMRB_CAPTURE_TBFF0_EDGE                       ((uint32_t)0x00000300)
+#define TMRB_CLEAR_TBIN1_RISING                       ((uint32_t)0x00000400)
+#define TMRB_CAPTURE_TBIN0_RISING_CLEAR_TBIN1_RISING  ((uint32_t)0x00000500)
+#define IS_TMRB_CAPTURE_TIMING_ALL(param)             (((param) == TMRB_DISABLE_CAPTURE) || \
+                                                       ((param) == TMRB_CAPTURE_TBIN0_TBIN1_RISING) || \
+                                                       ((param) == TMRB_CAPTURE_TBIN0_RISING_FALLING) || \
+                                                       ((param) == TMRB_CAPTURE_TBFF0_EDGE) || \
+                                                       ((param) == TMRB_CLEAR_TBIN1_RISING) || \
+                                                       ((param) == TMRB_CAPTURE_TBIN0_RISING_CLEAR_TBIN1_RISING))
+
+#define IS_TMRB_CAPTURE_TIMING_NONE_TBIN1(param)      (((param) == TMRB_DISABLE_CAPTURE) || \
+                                                       ((param) == TMRB_CAPTURE_TBIN0_RISING_FALLING) || \
+                                                       ((param) == TMRB_CAPTURE_TBFF0_EDGE))
+
+#define MPT_DISABLE_CAPTURE              ((uint32_t)0x00000000)
+#define MPT_CAPTURE_IN_RISING            ((uint32_t)0x00000008)
+#define MPT_CAPTURE_IN_RISING_FALLING    ((uint32_t)0x00000010)
+#define IS_MPT_CAPTURE_TIMING(param)     (((param) == MPT_DISABLE_CAPTURE) || \
+                                          ((param) == MPT_CAPTURE_IN_RISING) || \
+                                          ((param) == MPT_CAPTURE_IN_RISING_FALLING))
+
+#define TMRB_RUN                         ((uint32_t)0x00000005)
+#define TMRB_STOP                        ((uint32_t)0x00000000)
+#define IS_TMRB_CMD(param)               (((param) == TMRB_RUN) || ((param) == TMRB_STOP))
+
+#define TMRB_CAPTURE_0                   ((uint8_t)0x00)
+#define TMRB_CAPTURE_1                   ((uint8_t)0x01)
+#define IS_TMRB_CAPTURE_REG(param)       (((param) == TMRB_CAPTURE_0) || ((param) == TMRB_CAPTURE_1))
+
+#define TMRB_NO_INT_MASK                 ((uint32_t)0x00000000)
+#define TMRB_MASK_MATCH_LEADING_INT      ((uint32_t)0x00000001)
+#define TMRB_MASK_MATCH_TRAILING_INT     ((uint32_t)0x00000002)
+#define TMRB_MASK_OVERFLOW_INT           ((uint32_t)0x00000004)
+#define IS_TMRB_INT_MASK(param)          (((param) == TMRB_NO_INT_MASK) || \
+                                          ((param) == TMRB_MASK_MATCH_LEADING_INT) || \
+                                          ((param) == TMRB_MASK_MATCH_TRAILING_INT) || \
+                                          ((param) == TMRB_MASK_OVERFLOW_INT) || \
+                                          ((param) == (TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT)) || \
+                                          ((param) == (TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_OVERFLOW_INT)) || \
+                                          ((param) == (TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT)) || \
+                                          ((param) == (TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT)))
+
+#define TMRB_TRG_EDGE_RISING             ((uint8_t)0x00)
+#define TMRB_TRG_EDGE_FALLING            ((uint8_t)0x02)
+#define IS_TMRB_TRG_EDGE(param)          (((param) == TMRB_TRG_EDGE_RISING) || \
+                                          ((param) == TMRB_TRG_EDGE_FALLING))
+
+#define TMRB_WRITE_REG_SEPARATE          ((uint8_t)0x00)
+#define TMRB_WRITE_REG_SIMULTANEOUS      ((uint8_t)0x40)
+#define IS_TMRB_WRITE_REG_MODE(param)    (((param) == TMRB_WRITE_REG_SEPARATE) || \
+                                          ((param) == TMRB_WRITE_REG_SIMULTANEOUS))
+
+#define TMRB_RUNNING_IN_CORE_HALT        ((uint8_t)0x00)
+#define TMRB_STOP_IN_CORE_HALT           ((uint8_t)0x40)
+#define IS_TMRB_CLK_IN_CORE_HALT(param)  (((param) == TMRB_RUNNING_IN_CORE_HALT) || \
+                                          ((param) == TMRB_STOP_IN_CORE_HALT))
+
+#define TMRB_NO_INT                      ((uint32_t)0x00000000)
+#define IS_TMRB_VALUE(param)             ((param) <= 0x0000FFFFU)
+#define IS_VALID_LEADING(param1, param2) ((param1) <= (param2))
+
+/** @} */
+/* End of group TMRB_Exported_Constants */
+/** @defgroup TMRB_Exported_FunctionPrototypes
+  * @{
+  */
+    void TMRB_Enable(TSB_TB_TypeDef * TBx);
+    void TMRB_Disable(TSB_TB_TypeDef * TBx);
+    void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd);
+    void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct);
+    void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming);
+    void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct);
+    TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx);
+    void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask);
+    void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming);
+    void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming);
+    uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx);
+    uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg);
+    void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx);
+    void TMRB_SetIdleMode(TSB_TB_TypeDef * TBx, FunctionalState NewState);
+    void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState);
+    void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t WriteRegMode);
+    void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode);
+    void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState);
+
+/** @} */
+/* End of group TMRB_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group TMRB */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif                          /* __cplusplus */
+#endif                          /* __TMPM46B_TMRB_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_uart.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,390 @@
+/** 
+ *******************************************************************************
+ * @file    tmpm46b_uart.h
+ * @brief   This file provides all the functions prototypes for UART driver.
+ * @version V2.0.2.1
+ * @date    2015/02/26
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TMPM46B_UART_H
+#define __TMPM46B_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "TMPM46B.h"
+#include "tx04_common.h"
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/** @defgroup UART_Exported_Types
+  * @{
+  */
+
+/** 
+  * @brief  UART Init Structure definition
+  */
+
+    typedef struct {
+        uint32_t BaudRate;      /*!< This member configures the UART communication
+                                   baud rate. */
+        uint32_t DataBits;      /*!< Specifies UART transfer mode, which could be 
+                                   7-bit mode, 8-bit mode or 9-bit mode. */
+        uint32_t StopBits;      /*!< Specifies the length of stop bit transmission
+                                   in UART mode. */
+        uint32_t Parity;        /*!< Specifies the parity mode which could be odd 
+                                   parity, even parity or no parity. */
+        uint32_t Mode;          /*!< Enables or disables Receive, Transmit or 
+                                   both. */
+        uint32_t FlowCtrl;      /*!< Specifies whether the hardware flow control 
+                                   mode is enabled or disabled. */
+    } UART_InitTypeDef;
+
+    typedef struct {
+        uint32_t InputClkEdge;  /*!< Select the input clock edge.on the SCLK output mode
+                                   this bit only can set to be 0(SIO_SCLKS_TXDF_RXDR) */
+        uint32_t TIDLE;         /*!< The status of TXDx pin after output of the
+                                   last bit */
+        uint32_t TXDEMP;        /*!< The status of TXDx pin when an under run error 
+                                   is  occurred in SCLK input mode */
+        uint32_t EHOLDTime;     /*!< The last bit hold time of TXDx pin in SCLK
+                                   input mode */
+        uint32_t IntervalTime;  /*!< Setting interval time of continuous transmission which 
+                                   could be None,1*SCLK,2*SCLK,4*SCLK,8*SCLK,16*SCLK,32*SCLK,64*SCLK.
+                                   this bit is valid only for SCLK output mode and double 
+                                   buffer is enabled. */
+        uint32_t TransferMode;  /*!< Setting transfer mode which could be transfer prohibited, 
+                                   half duplex(Receive),half duplex(Transmit) or full duplex. */
+        uint32_t TransferDir;   /*!< Setting transfer direction which could be
+                                   LSB_FRIST or MSB_FRIST. */
+        uint32_t Mode;          /*!< Enables or disables Receive, Transmit or both. */
+        uint32_t DoubleBuffer;  /*!< Double Buffer mode is enabled or disabled. */
+        uint32_t BaudRateClock; /*!< Select the input clock for baud rate generator */
+        uint32_t Divider;       /*!< Division ratio "N" */
+    } SIO_InitTypeDef;
+
+/** @} */
+/* End of group UART_Exported_Types */
+
+/** @defgroup UART_Exported_Constants
+  * @{
+  */
+
+#define UART0  TSB_SC0
+#define UART1  TSB_SC1
+#define UART2  TSB_SC2
+#define UART3  TSB_SC3
+#define IS_UART_PERIPH(param)      (((param) == UART0) || \
+                                     ((param) == UART1) || \
+                                     ((param) == UART2) || \
+                                     ((param) == UART3))
+
+#define SIO0  TSB_SC0
+#define SIO1  TSB_SC1
+#define SIO2  TSB_SC2
+#define SIO3  TSB_SC3
+#define IS_SIO_PERIPH(param)        (((param) == SIO0)|| \
+                                     ((param) == SIO1) || \
+                                     ((param) == SIO2) || \
+                                     ((param) == SIO3))
+
+#define UART_DATA_BITS_7            ((uint32_t)0x00000004)
+#define UART_DATA_BITS_8            ((uint32_t)0x00000008)
+#define UART_DATA_BITS_9            ((uint32_t)0x0000000C)
+#define IS_UART_DATA_BITS(param)    (((param) == UART_DATA_BITS_7) || \
+                                     ((param) == UART_DATA_BITS_8) || \
+                                     ((param) == UART_DATA_BITS_9))
+
+#define UART_STOP_BITS_1            ((uint32_t)0x00000000)
+#define UART_STOP_BITS_2            ((uint32_t)0x00000010)
+#define IS_UART_STOPBITS(param)     (((param) == UART_STOP_BITS_1) || \
+                                     ((param) == UART_STOP_BITS_2))
+
+#define UART_NO_PARITY              ((uint32_t)0x00000000)
+#define UART_EVEN_PARITY            ((uint32_t)0x00000060)
+#define UART_ODD_PARITY             ((uint32_t)0x00000020)
+#define IS_UART_PARITY(param)       (((param) == UART_NO_PARITY) || \
+                                     ((param) == UART_EVEN_PARITY) || \
+                                     ((param) == UART_ODD_PARITY))
+
+#define SIO_CLK_SCLKOUTPUT          ((uint32_t)0x00000000)
+#define SIO_CLK_SCLKINPUT           ((uint32_t)0x00000001)
+#define IS_SIO_CLK_SEL(param)       (((param) == SIO_CLK_SCLKOUTPUT) || \
+                                     ((param) == SIO_CLK_SCLKINPUT))
+
+#define SIO_SCLKS_TXDF_RXDR         ((uint32_t)0x00000000)
+#define SIO_SCLKS_TXDR_RXDF         ((uint32_t)0x00000002)
+#define IS_SIO_SCLKS_TRXD(param)    (((param) == SIO_SCLKS_TXDF_RXDR) || \
+                                     ((param) == SIO_SCLKS_TXDR_RXDF))
+
+#define SIO_TIDLE_LOW               ((uint32_t)0x00000000)
+#define SIO_TIDLE_HIGH              ((uint32_t)0x00000100)
+#define SIO_TIDLE_LAST              ((uint32_t)0x00000200)
+#define IS_SIO_TIDLE_LEVEL(param)   (((param) == SIO_TIDLE_LOW) || \
+                                     ((param) == SIO_TIDLE_HIGH) || \
+                                     ((param) == SIO_TIDLE_LAST))
+
+#define SIO_TXDEMP_LOW               ((uint32_t)0x00000000)
+#define SIO_TXDEMP_HIGH              ((uint32_t)0x00000400)
+#define IS_SIO_TXDEMP_LEVEL(param)  (((param) == SIO_TXDEMP_LOW) || \
+                                     ((param) == SIO_TXDEMP_HIGH))
+
+#define SIO_EHOLD_FC_2               ((uint32_t)0x00000000)
+#define SIO_EHOLD_FC_4               ((uint32_t)0x00001000)
+#define SIO_EHOLD_FC_8               ((uint32_t)0x00002000)
+#define SIO_EHOLD_FC_16              ((uint32_t)0x00003000)
+#define SIO_EHOLD_FC_32              ((uint32_t)0x00004000)
+#define SIO_EHOLD_FC_64              ((uint32_t)0x00005000)
+#define SIO_EHOLD_FC_128             ((uint32_t)0x00006000)
+#define IS_SIO_EHOLD_TIME(param)    (((param) == SIO_EHOLD_FC_2) ||   \
+                                     ((param) == SIO_EHOLD_FC_4) || \
+                                     ((param) == SIO_EHOLD_FC_8) || \
+                                     ((param) == SIO_EHOLD_FC_16) || \
+                                     ((param) == SIO_EHOLD_FC_32) || \
+                                     ((param) == SIO_EHOLD_FC_64) || \
+                                     ((param) == SIO_EHOLD_FC_128))
+
+#define SIO_SINT_TIME_NONE           ((uint32_t)0x00000000)
+#define SIO_SINT_TIME_SCLK_1         ((uint32_t)0x00000002)
+#define SIO_SINT_TIME_SCLK_2         ((uint32_t)0x00000004)
+#define SIO_SINT_TIME_SCLK_4         ((uint32_t)0x00000006)
+#define SIO_SINT_TIME_SCLK_8         ((uint32_t)0x00000008)
+#define SIO_SINT_TIME_SCLK_16        ((uint32_t)0x0000000A)
+#define SIO_SINT_TIME_SCLK_32        ((uint32_t)0x0000000C)
+#define SIO_SINT_TIME_SCLK_64        ((uint32_t)0x0000000E)
+#define IS_SIO_SINT_TIME(param)     (((param) == SIO_SINT_TIME_NONE) ||   \
+                                     ((param) == SIO_SINT_TIME_SCLK_1) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_2) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_4) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_8) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_16) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_32) || \
+                                     ((param) == SIO_SINT_TIME_SCLK_64))
+
+#define SIO_TRANSFER_PROHIBIT        ((uint32_t)0x00000000)
+#define SIO_TRANSFER_HALFDPX_RX      ((uint32_t)0x00000020)
+#define SIO_TRANSFER_HALFDPX_TX      ((uint32_t)0x00000040)
+#define SIO_TRANSFER_FULLDPX         ((uint32_t)0x00000060)
+#define IS_SIO_TRANSFER_MODE(param) (((param) == SIO_TRANSFER_PROHIBIT) || \
+                                     ((param) == SIO_TRANSFER_HALFDPX_RX) || \
+                                     ((param) == SIO_TRANSFER_HALFDPX_TX) || \
+                                     ((param) == SIO_TRANSFER_FULLDPX))
+
+#define SIO_ENABLE_RX              ((uint32_t)0x00000020)
+#define SIO_ENABLE_TX              ((uint32_t)0x00000010)
+#define IS_SIO_MODE(param)         (((param) == SIO_ENABLE_RX) || \
+                                     ((param) == SIO_ENABLE_TX) || \
+                                     ((param) == (SIO_ENABLE_TX | SIO_ENABLE_RX)))
+
+#define SIO_LSB_FRIST              ((uint32_t)0x00000000)
+#define SIO_MSB_FRIST              ((uint32_t)0x00000008)
+#define IS_SIO_TRANS_DIR(param)     (((param) == SIO_LSB_FRIST) || \
+                                     ((param) == SIO_MSB_FRIST))
+
+#define SIO_WBUF_DISABLE             ((uint32_t)0x00000000)
+#define SIO_WBUF_ENABLE              ((uint32_t)0x00000004)
+#define IS_SIO_WBUF_SET(param)      (((param) == SIO_WBUF_DISABLE) || \
+                                     ((param) == SIO_WBUF_ENABLE))
+
+#define SIO_BR_CLOCK_TS0             ((uint32_t)0x00000000)
+#define SIO_BR_CLOCK_TS2             ((uint32_t)0x00000010)
+#define SIO_BR_CLOCK_TS8             ((uint32_t)0x00000020)
+#define SIO_BR_CLOCK_TS32            ((uint32_t)0x00000030)
+#define IS_SIO_BR_CLOCK(param)      (((param) == SIO_BR_CLOCK_TS0) || \
+                                     ((param) == SIO_BR_CLOCK_TS2) || \
+                                     ((param) == SIO_BR_CLOCK_TS8) || \
+                                     ((param) == SIO_BR_CLOCK_TS32))
+
+#define SIO_BR_DIVIDER_16            ((uint32_t)0x00000000)
+#define SIO_BR_DIVIDER_1             ((uint32_t)0x00000001)
+#define SIO_BR_DIVIDER_2             ((uint32_t)0x00000002)
+#define SIO_BR_DIVIDER_3             ((uint32_t)0x00000003)
+#define SIO_BR_DIVIDER_4             ((uint32_t)0x00000004)
+#define SIO_BR_DIVIDER_5             ((uint32_t)0x00000005)
+#define SIO_BR_DIVIDER_6             ((uint32_t)0x00000006)
+#define SIO_BR_DIVIDER_7             ((uint32_t)0x00000007)
+#define SIO_BR_DIVIDER_8             ((uint32_t)0x00000008)
+#define SIO_BR_DIVIDER_9             ((uint32_t)0x00000009)
+#define SIO_BR_DIVIDER_10            ((uint32_t)0x0000000A)
+#define SIO_BR_DIVIDER_11            ((uint32_t)0x0000000B)
+#define SIO_BR_DIVIDER_12            ((uint32_t)0x0000000C)
+#define SIO_BR_DIVIDER_13            ((uint32_t)0x0000000D)
+#define SIO_BR_DIVIDER_14            ((uint32_t)0x0000000E)
+#define SIO_BR_DIVIDER_15            ((uint32_t)0x0000000F)
+#define IS_SIO_BR_DIVIDER(param)    ((param) <= SIO_BR_DIVIDER_15)
+
+#define IS_SIO_DATA(param)          ((param) <= 0xFFU)
+
+#define SIO_CLOCK_T0_HALF           ((uint32_t)0x00000000)
+#define SIO_CLOCK_T0                ((uint32_t)0x00000002)
+#define IS_SIO_CLOCK(param)        (((param) == SIO_CLOCK_T0_HALF) || \
+                                    ((param) == SIO_CLOCK_T0))
+
+#define UART_ENABLE_RX              ((uint32_t)0x00000020)
+#define UART_ENABLE_TX              ((uint32_t)0x00000010)
+#define IS_UART_MODE(param)         (((param) == UART_ENABLE_RX) || \
+                                     ((param) == UART_ENABLE_TX) || \
+                                     ((param) == (UART_ENABLE_TX | UART_ENABLE_RX)))
+
+#define UART_NONE_FLOW_CTRL         ((uint32_t)0x00000000)
+#define IS_UART_FLOW_CONTROL(param) ((param) == UART_NONE_FLOW_CTRL)
+
+#ifdef USE_STK
+#define IS_UART_BAUDRATE(param)     (((param) >= 3663U) && \
+                                     ((param) <= 921600U))
+#else
+#define IS_UART_BAUDRATE(param)     (((param) >= 2929U) && \
+                                     ((param) <= 921600U))
+#endif
+
+#define IS_UART_DATA(param)         ((param) <= 0x01FFU)
+
+#define IS_UART_CLOCK(param)        ((param) <= ((uint32_t)0x00000001))
+#define IS_UART_TIME(param)         ((param) <= ((uint32_t)0x00000006))
+#define UART_RX                     ((uint32_t)0x00000020)
+#define UART_TX                     ((uint32_t)0x00000040)
+#define IS_UART_TRX(param)          (((param) == UART_RX) || \
+                                     ((param) == UART_TX))
+
+#define UART_TRANSFER_PROHIBIT               ((uint32_t)0x00000000)
+#define UART_TRANSFER_HALFDPX_RX             ((uint32_t)0x00000020)
+#define UART_TRANSFER_HALFDPX_TX             ((uint32_t)0x00000040)
+#define UART_TRANSFER_FULLDPX                ((uint32_t)0x00000060)
+#define IS_UART_TRANSFER_MODE(param)        (((param) == UART_TRANSFER_PROHIBIT) || \
+                                             ((param) == UART_TRANSFER_HALFDPX_RX) || \
+                                             ((param) == UART_TRANSFER_HALFDPX_TX) || \
+                                             ((param) == UART_TRANSFER_FULLDPX))
+
+#define UART_RXFIFO_MAX                      ((uint32_t)0x00000000)
+#define UART_RXFIFO_RXFLEVEL                 ((uint32_t)0x00000010)
+#define IS_UATR_RXFIFO_BYTESUSED(param)     (((param) == UART_RXFIFO_MAX) || \
+                                             ((param) == UART_RXFIFO_RXFLEVEL))
+
+#define UART_RXFIFO4B_FLEVLE_4_2B              ((uint32_t)0x00000000)
+#define UART_RXFIFO4B_FLEVLE_1_1B              ((uint32_t)0x00000001)
+#define UART_RXFIFO4B_FLEVLE_2_2B              ((uint32_t)0x00000002)
+#define UART_RXFIFO4B_FLEVLE_3_1B              ((uint32_t)0x00000003)
+#define IS_UART_RXFIFO4B_FLEVLE(param)        (((param) == UART_RXFIFO4B_FLEVLE_4_2B) || \
+                                               ((param) == UART_RXFIFO4B_FLEVLE_1_1B) || \
+                                               ((param) == UART_RXFIFO4B_FLEVLE_2_2B) || \
+                                               ((param) == UART_RXFIFO4B_FLEVLE_3_1B))
+
+#define UART_RFIS_REACH_FLEVEL               ((uint32_t)0x00000000)
+#define UART_RFIS_REACH_EXCEED_FLEVEL        ((uint32_t)0x00000040)
+#define IS_UATR_RFIS_CONDITION(param)       (((param) == UART_RFIS_REACH_FLEVEL) || \
+                                             ((param) == UART_RFIS_REACH_EXCEED_FLEVEL))
+
+#define UART_TXFIFO4B_FLEVLE_0_0B              ((uint32_t)0x00000000)
+#define UART_TXFIFO4B_FLEVLE_1_1B              ((uint32_t)0x00000001)
+#define UART_TXFIFO4B_FLEVLE_2_0B              ((uint32_t)0x00000002)
+#define UART_TXFIFO4B_FLEVLE_3_1B              ((uint32_t)0x00000003)
+#define IS_UART_TXFIFO4B_FLEVLE(param)        (((param) == UART_TXFIFO4B_FLEVLE_0_0B) || \
+                                               ((param) == UART_TXFIFO4B_FLEVLE_1_1B) || \
+                                               ((param) == UART_TXFIFO4B_FLEVLE_2_0B) || \
+                                               ((param) == UART_TXFIFO4B_FLEVLE_3_1B))
+
+#define UART_TRXFIFO_EMPTY         ((uint32_t)0x00000000)
+#define UART_TRXFIFO_1B            ((uint32_t)0x00000001)
+#define UART_TRXFIFO_2B            ((uint32_t)0x00000002)
+#define UART_TRXFIFO_3B            ((uint32_t)0x00000003)
+#define UART_TRXFIFO_4B            ((uint32_t)0x00000004)
+
+#define UART_TFIS_REACH_FLEVEL               ((uint32_t)0x00000000)
+#define UART_TFIS_REACH_NOREACH_FLEVEL       ((uint32_t)0x00000040)
+#define IS_UATR_TFIS_CONDITION(param)       (((param) == UART_TFIS_REACH_FLEVEL) || \
+                                             ((param) == UART_TFIS_REACH_NOREACH_FLEVEL))
+
+#define UART_RXFIFO_OVERRUN                  ((uint32_t)0x00000001)
+
+#define UART_TXFIFO_UNDERRUN                 ((uint32_t)0x00000001)
+
+/** @} */
+/* End of group UART_Exported_Constants */
+
+/** @addtogroup UART_Exported_Types
+  * @{
+  */
+    typedef enum {
+        UART_NO_ERR = 0U,
+        UART_OVERRUN = 1U,
+        UART_PARITY_ERR = 2U,
+        UART_FRAMING_ERR = 3U,
+        UART_ERRS = 4U
+    } UART_Err;
+
+    typedef enum {
+        UART_RXTXCNT_NONE = 0U,
+        UART_RXTXCNT_AUTODISABLE = 1U
+    } UART_TRxDisable;
+#define IS_UATR_TRX_AUTODISABLE(param)  (((param) == UART_RXTXCNT_NONE) || \
+                                         ((param) == UART_RXTXCNT_AUTODISABLE))
+
+/** @} */
+/* End of group UART_Exported_Types */
+
+/** @defgroup UART_Exported_FunctionPrototypes
+  * @{
+  */
+
+    void UART_Enable(TSB_SC_TypeDef * UARTx);
+    void UART_Disable(TSB_SC_TypeDef * UARTx);
+    WorkState UART_GetBufState(TSB_SC_TypeDef * UARTx, uint8_t Direction);
+    void UART_SWReset(TSB_SC_TypeDef * UARTx);
+    void UART_Init(TSB_SC_TypeDef * UARTx, UART_InitTypeDef * InitStruct);
+    uint32_t UART_GetRxData(TSB_SC_TypeDef * UARTx);
+    void UART_SetTxData(TSB_SC_TypeDef * UARTx, uint32_t Data);
+    void UART_DefaultConfig(TSB_SC_TypeDef * UARTx);
+    UART_Err UART_GetErrState(TSB_SC_TypeDef * UARTx);
+    void UART_SetWakeUpFunc(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_SetIdleMode(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_SetInputClock(TSB_SC_TypeDef * UARTx, uint32_t clock);
+    void UART_FIFOConfig(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_SetFIFOTransferMode(TSB_SC_TypeDef * UARTx, uint32_t TransferMode);
+    void UART_TRxAutoDisable(TSB_SC_TypeDef * UARTx, UART_TRxDisable TRxAutoDisable);
+    void UART_RxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_TxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState);
+    void UART_RxFIFOByteSel(TSB_SC_TypeDef * UARTx, uint32_t BytesUsed);
+    void UART_RxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t RxFIFOLevel);
+    void UART_RxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t RxINTCondition);
+    void UART_RxFIFOClear(TSB_SC_TypeDef * UARTx);
+    void UART_TxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t TxFIFOLevel);
+    void UART_TxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t TxINTCondition);
+    void UART_TxFIFOClear(TSB_SC_TypeDef * UARTx);
+    void UART_TxBufferClear(TSB_SC_TypeDef * UARTx);
+    uint32_t UART_GetRxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx);
+    uint32_t UART_GetRxFIFOOverRunStatus(TSB_SC_TypeDef * UARTx);
+    uint32_t UART_GetTxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx);
+    uint32_t UART_GetTxFIFOUnderRunStatus(TSB_SC_TypeDef * UARTx);
+    void SIO_SetInputClock(TSB_SC_TypeDef * SIOx, uint32_t Clock);
+    void SIO_Enable(TSB_SC_TypeDef * SIOx);
+    void SIO_Disable(TSB_SC_TypeDef * SIOx);
+    uint8_t SIO_GetRxData(TSB_SC_TypeDef * SIOx);
+    void SIO_SetTxData(TSB_SC_TypeDef * SIOx, uint8_t Data);
+    void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitStruct);
+/** @} */
+/* End of group UART_Exported_FunctionPrototypes */
+
+/** @} */
+/* End of group UART */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#ifdef __cplusplus
+}
+#endif
+#endif                          /* __TMPM46B_UART_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tx04_common.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,50 @@
+/**
+ *******************************************************************************
+ * @file    tx04_common.h
+ * @brief   All common macro and definition for TX04 peripheral drivers
+ * @version V2.0.2.1
+ * @date    2015/02/04
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TX04_COMMON_H
+#define __TX04_COMMON_H
+
+typedef enum {
+    SUCCESS = 0U,
+    ERROR = 1U,
+    FAIL = -1
+} Result;
+
+typedef enum {
+    BUSY = 0U,
+    DONE = 1U
+} WorkState;
+
+typedef enum {
+    DISABLE = 0U,
+    ENABLE = 1U
+} FunctionalState;
+
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+#define IS_POINTER_NOT_NULL(param) ((void*)(param) != (void*)0)
+
+/* 
+ * To report the name of the source file and source line number where the
+ * assert_param error has occurred, "DEBUG" must be defined. And detailed
+ * definition of assert_failed() is needed to be implemented, which can be
+ * done, for example, in the main.c file.
+ */
+#ifdef DEBUG
+void assert_failed(char *file, int32_t line);
+#define assert_param(expr) ((expr) ? (void)0 : assert_failed((char *)__FILE__, __LINE__))
+#else
+#define assert_param(expr)
+#endif                          /* DEBUG */
+
+#endif                          /* __TX04_COMMON_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_adc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,621 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_adc.c
+ * @brief   This file provides API functions for ADC driver.
+ * @version V2.0.2.1
+ * @date    2015/02/11
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm46b_adc.h"
+
+#if defined(__TMPM46B_ADC_H)
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */
+
+/** @defgroup ADC_Private_Defines
+  * @{
+  */
+#define MOD6_ADRST_10           ((uint32_t)0x00000002)
+#define MOD6_ADRST_01           ((uint32_t)0x00000001)
+
+#define MOD3_ITM_CLEAR          ((uint32_t)0x00000003)
+
+#define MOD2_ADCH_CLEAR         ((uint32_t)0x000000F0)
+#define MOD2_HPADCH_CLEAR       ((uint32_t)0x0000000F)
+
+#define MOD1_ADHWE_CLEAR        ((uint32_t)0x000000EE)
+#define MOD1_ADHWE_SET          ((uint32_t)0x00000001)
+#define MOD1_ADHWS_CLEAR        ((uint32_t)0x000000ED)
+#define MOD1_HPADHWE_CLEAR      ((uint32_t)0x000000EB)
+#define MOD1_HPADHWE_SET        ((uint32_t)0x00000004)
+#define MOD1_HPADHWS_CLEAR      ((uint32_t)0x000000E7)
+
+#define ADILV_TRGSEL_CLEAR      ((uint32_t)0x0000F0FF)
+#define ADILV_HPTRGSEL_CLEAR    ((uint32_t)0x00000FFF)
+
+
+/** @} */
+/* End of group ADC_Private_Defines */
+
+/** @defgroup ADC_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group ADC_Private_FunctionPrototypes */
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group ADC_Private_Functions */
+
+/** @defgroup ADC_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Software reset ADC.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @retval None.
+  */
+void ADC_SWReset(TSB_AD_TypeDef * ADx)
+{
+    assert_param(IS_ADC_UNIT(ADx));
+
+    ADC_SetVref(ADx, ENABLE);
+    ADx->MOD6 = MOD6_ADRST_10;
+    ADx->MOD6 = MOD6_ADRST_01;
+}
+
+/**
+  * @brief  Set AD sample hold time and prescaler clock.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @param  Sample_HoldTime: Select the AD sample hold time.
+  *   This parameter can be one of the following values:
+  *   ADC_CONVERSION_CLK_10, ADC_CONVERSION_CLK_20,
+  *   ADC_CONVERSION_CLK_30, ADC_CONVERSION_CLK_40,
+  *   ADC_CONVERSION_CLK_80, ADC_CONVERSION_CLK_160,
+  *   ADC_CONVERSION_CLK_320
+  * @param  Prescaler_Output: Select the AD prescaler clock.
+  *   This parameter can be one of the following values:
+  *   ADC_FC_DIVIDE_LEVEL_1, ADC_FC_DIVIDE_LEVEL_2,
+  *   ADC_FC_DIVIDE_LEVEL_4, ADC_FC_DIVIDE_LEVEL_8,
+  *   ADC_FC_DIVIDE_LEVEL_16.  
+  * @retval None.
+  */
+void ADC_SetClk(TSB_AD_TypeDef * ADx, uint32_t Sample_HoldTime, uint32_t Prescaler_Output)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_HOLD_TIME(Sample_HoldTime));
+    assert_param(IS_ADC_PRESCALER(Prescaler_Output));
+
+    /* Set ADCLK */
+    ADx->CLK = Sample_HoldTime + Prescaler_Output;
+}
+
+/**
+  * @brief  Start AD conversion.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @retval None.
+  */
+void ADC_Start(TSB_AD_TypeDef * ADx)
+{
+    assert_param(IS_ADC_UNIT(ADx));
+
+    /* Set ADMOD0<ADS> = 1 to start AD conversion */
+    TSB_AD_MOD0_ADS = 1U;
+}
+
+/**
+  * @brief  Enable or disable ADC scan mode.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @param  NewState: Specify ADC scan mode state.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetScanMode(TSB_AD_TypeDef * ADx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Set ADMOD3<SCAN> */
+    TSB_AD_MOD3_SCAN = NewState;
+}
+
+/**
+  * @brief  Enable or disable ADC repeat mode.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @param  NewState: Specify ADC repeat mode state.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetRepeatMode(TSB_AD_TypeDef * ADx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Set ADMOD3<REPEAT> */
+    TSB_AD_MOD3_REPEAT = NewState;
+}
+
+/**
+  * @brief  Set ADC interrupt mode in fixed channel repeat conversion mode.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @param  INTMode: Specify AD conversion interrupt mode.
+  *   This parameter can be one of the following values:
+  *   ADC_INT_SINGLE,       ADC_INT_CONVERSION_2,
+  *   ADC_INT_CONVERSION_3, ADC_INT_CONVERSION_4,
+  *   ADC_INT_CONVERSION_5, ADC_INT_CONVERSION_6,
+  *   ADC_INT_CONVERSION_7, ADC_INT_CONVERSION_8.
+  * @retval None.
+  */
+void ADC_SetINTMode(TSB_AD_TypeDef * ADx, uint32_t INTMode)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_INT_MODE(INTMode));
+
+    /* Set ADMOD3<ITM[2:0]> */
+    tmp = ADx->MOD3;
+    tmp &= MOD3_ITM_CLEAR;
+    tmp |= INTMode;
+    ADx->MOD3 = tmp;
+}
+
+/**
+  * @brief  Set ADC input channel.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD  
+  * @param  InputChannel: Analog input channel.
+  *   This parameter can be one of the following values:
+  *   ADC_AN_00, ADC_AN_01, ADC_AN_02, ADC_AN_03,
+  *   ADC_AN_04, ADC_AN_05, ADC_AN_06, ADC_AN_07.
+  * @retval None.
+  */
+void ADC_SetInputChannel(TSB_AD_TypeDef * ADx, ADC_AINx InputChannel)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_INPUT_CHANNEL(InputChannel));
+
+    /* Set ADMOD2<ADCH[3:0]> */
+    tmp = ADx->MOD2;
+    tmp &= MOD2_ADCH_CLEAR;
+    tmp |= InputChannel;
+    ADx->MOD2 = tmp;
+}
+
+/**
+  * @brief  Set ADC scan channel.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @param  StartChannel: Specify the start channel to be scanned.
+  *   This parameter can be one of the following values:
+  *   ADC_AN_00, ADC_AN_01, ADC_AN_02, ADC_AN_03,
+  *   ADC_AN_04, ADC_AN_05, ADC_AN_06, ADC_AN_07.
+  * @param  Range: Specify the range of assignable channel scan value.
+  *   This parameter can be one of the following values:
+  *   1, 2, 3, 4, 5, 6, 7, 8 (note: StartChannel + Range  <= 8 )
+  * @retval None.
+  */
+void ADC_SetScanChannel(TSB_AD_TypeDef * ADx, ADC_AINx StartChannel, uint32_t Range)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_SCAN_CHANNEL(StartChannel, Range));
+
+    /* Set ADMOD4<SCANAREA> */
+    ADx->MOD4 = (uint32_t) (StartChannel | ((Range - 1U) << 4U));
+}
+
+/**
+  * @brief  Control AVREFH-AVREFL current.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD 
+  * @param  VrefCtrl: Specify how to apply AVREFH-AVREFL current.
+  *   This parameter can be one of the following values:
+  *   ADC_APPLY_VREF_IN_CONVERSION or ADC_APPLY_VREF_AT_ANY_TIME.
+  * @retval None.
+  */
+void ADC_SetVrefCut(TSB_AD_TypeDef * ADx, uint32_t VrefCtrl)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_VREF_CTRL(VrefCtrl));
+
+    /* Set ADMOD1<RCUT> */
+    TSB_AD_MOD1_RCUT = VrefCtrl;
+
+}
+
+/**
+  * @brief  Set ADC operation in IDLE mode.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD 
+  * @param  NewState: Specify ADC operation state in IDLE mode.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetIdleMode(TSB_AD_TypeDef * ADx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Set ADMOD1<I2AD> */
+    TSB_AD_MOD1_I2AD = NewState;
+
+}
+
+/**
+  * @brief  Set ADC VREF application.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD 
+  * @param  NewState: Specify ADC Vref application state.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetVref(TSB_AD_TypeDef * ADx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Set ADMOD1<VREFON> */
+    TSB_AD_MOD1_DACON = NewState;
+
+}
+
+/**
+  * @brief  Select ADC top-priority conversion analog input channel.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following values:
+  *   TSB_AD  
+  * @param  TopInputChannel: Analog input channel for top-priority conversion.
+  *   This parameter can be one of the following values:
+  *   ADC_AN_00, ADC_AN_01, ADC_AN_02, ADC_AN_03,
+  *   ADC_AN_04, ADC_AN_05, ADC_AN_06, ADC_AN_07.
+  * @retval None.
+  */
+void ADC_SetInputChannelTop(TSB_AD_TypeDef * ADx, ADC_AINx TopInputChannel)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_INPUT_CHANNEL(TopInputChannel));
+
+    /* Set ADMOD2<HPADCH[3:0]> */
+    tmp = ADx->MOD2;
+    tmp &= MOD2_HPADCH_CLEAR;
+    tmp |= ((uint32_t) TopInputChannel << 4U);
+    ADx->MOD2 = tmp;
+}
+
+/**
+  * @brief  Start top-priority AD conversion.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @retval None.
+  */
+void ADC_StartTopConvert(TSB_AD_TypeDef * ADx)
+{
+    assert_param(IS_ADC_UNIT(ADx));
+
+    /* Set ADMOD0<HPADS> = 1 to start top-priority AD conversion */
+    TSB_AD_MOD0_HPADS = 1U;
+
+}
+
+/**
+  * @brief  Enable or disable the specified ADC monitor module.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @param  ADCMPx: Select which compare control register will be used.
+  *   This parameter can be one of the following values:
+  *   ADC_CMPCR_0 or ADC_CMPCR_1.
+  * @param  NewState: Specify ADC monitor function state.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_CMPCRx(ADCMPx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (ADCMPx == ADC_CMPCR_0) {
+        /* Set ADCMPCR0<CMP0EN> */
+        TSB_AD_CMPCR0_CMP0EN = NewState;
+    } else {
+        /* Set ADCMPCR1<CMP1EN> */
+        TSB_AD_CMPCR1_CMP1EN = NewState;
+    }
+}
+
+/**
+  * @brief  Configure the specified ADC monitor module.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD 
+  * @param  ADCMPx: Select which compare control register will be used.
+  *   This parameter can be one of the following values:
+  *   ADC_CMPCR_0 or ADC_CMPCR_1.
+  * @param  Monitor: The structure containing ADC monitor configuration.
+  * @retval None.
+  */
+void ADC_ConfigMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, ADC_MonitorTypeDef * Monitor)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_CMPCRx(ADCMPx));
+    assert_param(IS_POINTER_NOT_NULL(Monitor));
+    assert_param(IS_ADC_INPUT_CHANNEL(Monitor->CmpChannel));
+    assert_param(IS_ADC_CMPCNT(Monitor->CmpCnt));
+    assert_param(IS_ADC_CMPCONDITION(Monitor->Condition));
+    assert_param(IS_ADC_CMPMODE(Monitor->CntMode));
+    assert_param(IS_ADC_CMPVALUE_12BIT(Monitor->CmpValue));
+
+    tmp |= (uint32_t) (Monitor->CmpChannel);
+    tmp |= (uint32_t) (Monitor->Condition) << 4U;
+    tmp |= (uint32_t) (Monitor->CntMode) << 5U;
+    tmp |= (uint32_t) (Monitor->CmpCnt - 1U) << 8U;
+
+    if (ADCMPx == ADC_CMPCR_0) {
+        ADx->CMPCR0 = tmp;
+        ADx->CMP0 = Monitor->CmpValue;
+    } else {
+        ADx->CMPCR1 = tmp;
+        ADx->CMP1 = Monitor->CmpValue;
+    }
+}
+
+/**
+  * @brief  Set hardware trigger for normal AD conversion.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @param  HWSrc: Hardware source for activating normal AD conversion.
+  *   This parameter can be one of the following values:
+  *   ADC_EXTERADTRG,ADC_INTERTRIGGER
+  * @param  NewState: Specify state of hardware source for activating normal AD conversion.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetHWTrg(TSB_AD_TypeDef * ADx, uint32_t HWSrc, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_EXTERADTRG(HWSrc));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Set ADMOD1<ADHWS> */
+    tmp = ADx->MOD1;
+    tmp &= MOD1_ADHWS_CLEAR;
+    tmp |= (HWSrc << 1U);
+
+    /* Set ADMOD1<ADHWE> */
+    if (NewState == ENABLE) {
+        tmp |= MOD1_ADHWE_SET;
+    } else {
+        tmp &= MOD1_ADHWE_CLEAR;
+    }
+
+    ADx->MOD1 = tmp;
+}
+
+/**
+  * @brief  Set hardware trigger for top-priority AD conversion.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @param  HWSrc: Hardware source for activating top-priority AD conversion.
+  *   This parameter can be one of the following values:
+  *   ADC_EXTERADTRG,ADC_INTERTRIGGER
+  * @param   NewState: Specify state of hardware source for activating top-priority AD conversion.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void ADC_SetHWTrgTop(TSB_AD_TypeDef * ADx, uint32_t HWSrc, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_EXTERADTRG_TOP(HWSrc));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Set ADMOD1<HPADHWS> */
+    tmp = ADx->MOD1;
+    tmp &= MOD1_HPADHWS_CLEAR;
+    tmp |= (HWSrc << 3U);
+
+    /* Set ADMOD1<HPADHWE> */
+    if (NewState == ENABLE) {
+        tmp |= MOD1_HPADHWE_SET;
+    } else {
+        tmp &= MOD1_HPADHWE_CLEAR;
+    }
+
+    ADx->MOD1 = tmp;
+}
+
+/**
+  * @brief  Read AD conversion completion/busy flag (normal and top-priority).
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD
+  * @retval A union with the state of AD conversion.
+  */
+ADC_State ADC_GetConvertState(TSB_AD_TypeDef * ADx)
+{
+    ADC_State retval = { 0U };
+
+    assert_param(IS_ADC_UNIT(ADx));
+
+    retval.All = ADx->MOD5;
+    return retval;
+}
+
+/**
+  * @brief  Read AD conversion result.
+  * @param  ADx: Select ADC unit.
+  *   This parameter can be the following value:
+  *   TSB_AD 
+  * @param  ADREGx: ADC result register.
+  *   This parameter can be one of the following values:
+  *   ADC_REG_00, ADC_REG_01, ADC_REG_02, ADC_REG_03,
+  *   ADC_REG_04, ADC_REG_05, ADC_REG_06, ADC_REG_07,
+  *   ADC_REG_SP.
+  * @retval A union with AD result and 2 bits of extra information.
+  */
+ADC_Result ADC_GetConvertResult(TSB_AD_TypeDef * ADx, ADC_REGx ADREGx)
+{
+    ADC_Result retval = { 0U };
+    uint32_t tmpAddr = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_UNIT(ADx));
+    assert_param(IS_ADC_REG(ADREGx));
+
+    if (ADREGx == ADC_REG_SP) {
+        retval.All = ADx->REGSP;
+    } else {
+        tmpAddr = (uint32_t) (&ADx->REG00);
+        tmpAddr += (0x4U * (uint32_t) ADREGx);
+        retval.All = *((uint32_t *) (tmpAddr));
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Enable the trigger.
+  * @param  None
+  * @retval None
+  */
+void ADC_EnableTrigger(void)
+{
+    /* Set TRGSEL<TRGSELEN> to enable trigger */
+    TSB_ADILV_TRGSEL_TRGSELEN = 1U;
+}
+
+/**
+  * @brief  Disable the trigger.
+  * @param  None
+  * @retval None
+  */
+void ADC_DisableTrigger(void)
+{
+    /* Set TRGSEL<TRGSELEN> to disable trigger */
+    TSB_ADILV_TRGSEL_TRGSELEN = 0U;
+}
+
+ /**
+  * @brief  Selects a trigger for startup of normal AD conversion
+  * @param  TriggerStartup: trigger for startup of normal AD conversion
+  *   This parameter can be one of the following values:
+  *   ADC_TRG_00, ADC_TRG_01, ADC_TRG_02, ADC_TRG_03,
+  *   ADC_TRG_04, ADC_TRG_05, ADC_TRG_06, ADC_TRG_07,
+  *   ADC_TRG_08, ADC_TRG_09.
+  * @retval None.
+  */
+void ADC_SetTriggerStartup(ADC_TRGx TriggerStartup)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_TRG(TriggerStartup));
+
+    /* Set TRGSEL<TRGSEL[3:0]> */
+    tmp = TSB_ADILV->TRGSEL;
+    tmp &= ADILV_TRGSEL_CLEAR;
+    tmp |= ((uint32_t) TriggerStartup << 8U);
+    TSB_ADILV->TRGSEL = tmp;
+}
+
+ /**
+  * @brief  Selects a trigger for startup of top-priority AD conversion
+  * @param  TopTriggerStartup: trigger for startup of top-priority AD conversion
+  *   This parameter can be one of the following values:
+  *   ADC_TRG_00, ADC_TRG_01, ADC_TRG_02, ADC_TRG_03,
+  *   ADC_TRG_04, ADC_TRG_05, ADC_TRG_06, ADC_TRG_07,
+  *   ADC_TRG_08, ADC_TRG_09.
+  * @retval None.
+  */
+void ADC_SetTriggerStartupTop(ADC_TRGx TopTriggerStartup)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_ADC_TRG(TopTriggerStartup));
+
+    /* Set TRGSEL<HPTRGSEL[3:0]> */
+    tmp = TSB_ADILV->TRGSEL;
+    tmp &= ADILV_HPTRGSEL_CLEAR;
+    tmp |= ((uint32_t) TopTriggerStartup << 12U);
+    TSB_ADILV->TRGSEL = tmp;
+}
+
+/** @} */
+/* End of group ADC_Exported_Functions */
+
+/** @} */
+/* End of group ADC */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#endif                          /* defined(__TMPM46B_ADC_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_cg.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,1302 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_cg.c
+ * @brief   This file provides all the functions prototypes for CG driver.
+ * @version V2.0.2.1
+ * @date    2015/02/26
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm46b_cg.h"
+
+#if defined(__TMPM46B_CG_H)
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @defgroup CG
+  * @brief CG driver modules
+  * @{
+  */
+
+/** @defgroup CG_Private_Defines
+  * @{
+  */
+
+#define CG_SYSCR_FCSTOP_CLEAR                ((uint32_t)0xFFEFFFFF)
+#define CG_SYSCR_FCSTOP_SET                  ((uint32_t)0x00100000)
+
+#define ADC_MOD5_BUSY_MASK                   ((uint32_t)0x00000005)
+
+#define CG_FC_GEAR_MASK                      ((uint32_t)0xFFFFFFF8)
+#define CG_PRCK_MASK                         ((uint32_t)0xFFFFF8FF)
+#define CG_SCOUT_MASK                        ((uint32_t)0xFFFCFFFF)
+#define CG_WUP_TIME_MASK                     ((uint32_t)0x0003FFFF)
+#define CG_WUP_COUNTER_MASK                  ((uint32_t)0xFFFCFFFF)
+#define CG_WUP_START_SET                     ((uint32_t)0x00004000)
+#define CG_WUEF_VALUE_MASK                   ((uint32_t)0x00008000)
+#define CG_OSCCR_XEN1_SET                    ((uint32_t)0x00000001)
+#define CG_OSCCR_XEN1_CLEAR                  ((uint32_t)0xFFFFFFFE)
+#define CG_OSCCR_XEN2_SET                    ((uint32_t)0x00000002)
+#define CG_OSCCR_XEN2_CLEAR                  ((uint32_t)0xFFFFFFFD)
+#define CG_OSCCR_XTEN_SET                    ((uint32_t)0x00000008)
+#define CG_OSCCR_XTEN_CLEAR                  ((uint32_t)0xFFFFFFF7)
+#define CG_OSCCR_DRVOSCL_SET                 ((uint32_t)0x00000080)
+#define CG_OSCCR_DRVOSCL_CLEAR               ((uint32_t)0xFFFFFF7F)
+#define CG_OSCCR_HOSCON_SET                  ((uint32_t)0x00000400)
+#define CG_OSCCR_HOSCON_CLEAR                ((uint32_t)0xFFFFFBFF)
+#define CG_OSCCR_OSCSEL_SET                  ((uint32_t)0x00000100)
+#define CG_OSCCR_OSCSEL_CLEAR                ((uint32_t)0xFFFFFEFF)
+#define CG_OSCCR_OSCF_SET                    ((uint32_t)0x00000200)
+#define CG_OSCCR_WUPT_MASK                   ((uint32_t)0x0000FFF0)
+#define CG_OSCCR_WUPTL_MASK                  ((uint32_t)0x0000FFFC)
+
+#define CG_STBYCR_PTKEEP_SET                 ((uint32_t)0x00020000)
+#define CG_STBYCR_PTKEEP_CLEAR               ((uint32_t)0xFFFDFFFF)
+
+#define CG_PLLSEL_PLLON_SET                  ((uint32_t)0x00010000)
+#define CG_PLLSEL_PLLON_CLEAR                ((uint32_t)0xFFFEFFFF)
+#define CG_PLLSEL_PLLSEL_SET                 ((uint32_t)0x00020000)
+#define CG_PLLSEL_PLLSEL_CLEAR               ((uint32_t)0xFFFDFFFF)
+#define CG_PLLSEL_PLLST_SET                  ((uint32_t)0x00040000)
+
+#define CG_PLLSET_VALUE_MASK                 ((uint32_t)0x0000FFFE)
+#define CG_PLLSEL_PLLSET_MASK                ((uint32_t)0xFFFF0001)
+
+#define CG_STBY_MODE_MASK                    ((uint32_t)0xFFFFFFF8)
+#define CG_NMIFLG_MASK                       ((uint32_t)0xFFFFFFFA)
+#define CG_RESET_FLAG_MASK                   ((uint32_t)0xFFFFFFA2)
+#define CG_IOSC_FLASH_MASK                   ((uint32_t)0x00000002)
+#define CG_FPSEL_MASK                        ((uint32_t)0xFFFFEFFF)
+
+#define FC_GEAR_1_1                          ((uint32_t)0x00000000)
+#define FC_GEAR_1_2                          ((uint32_t)0x00000004)
+#define FC_GEAR_1_4                          ((uint32_t)0x00000005)
+#define FC_GEAR_1_8                          ((uint32_t)0x00000006)
+#define FC_GEAR_1_16                         ((uint32_t)0x00000007)
+
+#define WARM_UP_SEL_OSC_INT_HIGH             ((uint32_t)0x00000000)
+#define WARM_UP_SEL_OSC_EXT_HIGH             ((uint32_t)0x00020000)
+#define WARM_UP_SEL_OSC_EXT_LOW              ((uint32_t)0x00030000)
+
+#define SCOUT_SRC_FS                         ((uint32_t)0x00000000)
+#define SCOUT_SRC_FSYS_DIVIDE_8              ((uint32_t)0x00010000)
+#define SCOUT_SRC_FSYS_DIVIDE_4              ((uint32_t)0x00020000)
+#define SCOUT_SRC_FOSC                       ((uint32_t)0x00030000)
+
+#define CG_PROTECT_SET                       ((uint32_t)0x000000C1)
+#define CG_PROTECT_CLEAR                     ((uint32_t)0x0000003E)
+
+#define CG_OSC_OFD_SET                       ((uint32_t)0x00000004)
+#define CG_OSC_OFD_CLEAR                     ((uint32_t)0xFFFFFFFB)
+
+typedef union {
+    uint32_t byte4;
+    uint8_t byte[4];
+} CG_Byte4;
+
+static CG_DivideLevel numToDivideLevel_table[CG_DIVIDE_MAX] = {
+    CG_DIVIDE_1,
+    CG_DIVIDE_2,
+    CG_DIVIDE_4,
+    CG_DIVIDE_8,
+    CG_DIVIDE_16,
+    CG_DIVIDE_32,
+    CG_DIVIDE_64,
+    CG_DIVIDE_128,
+    CG_DIVIDE_256,
+    CG_DIVIDE_512,
+    CG_DIVIDE_UNKNOWN,
+};
+
+static CG_PhiT0Src numPhiT0Src_table[CG_PHIT0_SRC_MAX] = {
+    CG_PHIT0_SRC_FGEAR,
+    CG_PHIT0_SRC_FC,
+};
+
+static CG_STBYMode numToSTBYMode_table[CG_STBY_MODE_MAX] = {
+    CG_STBY_MODE_UNKNOWN,
+    CG_STBY_MODE_STOP1,
+    CG_STBY_MODE_UNKNOWN,
+    CG_STBY_MODE_IDLE,
+    CG_STBY_MODE_UNKNOWN,
+    CG_STBY_MODE_STOP2,
+    CG_STBY_MODE_UNKNOWN,
+    CG_STBY_MODE_UNKNOWN,
+};
+
+/** @} */
+/* End of group CG_Private_Defines */
+
+/** @defgroup CG_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group CG_Private_FunctionPrototypes */
+
+/** @defgroup CG_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group CG_Private_Functions */
+
+/** @defgroup CG_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set dividing level between clock fgear and fc.
+  * @param  DivideFgearFromFc: Dividing level between fgear and fc.
+  *   This parameter can be one of the following values:
+  *   CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8, CG_DIVIDE_16
+  * @retval None
+  */
+void CG_SetFgearLevel(CG_DivideLevel DivideFgearFromFc)
+{
+    uint32_t gear = FC_GEAR_1_1;
+    uint32_t regval = TSB_CG->SYSCR;
+
+    /* Check the parameters */
+    assert_param(IS_CG_GEAR_DIVIDE_LEVEL(DivideFgearFromFc));
+
+    /* Set the value of fgear */
+    switch (DivideFgearFromFc) {
+    case CG_DIVIDE_1:
+        gear = FC_GEAR_1_1;
+        break;
+    case CG_DIVIDE_2:
+        gear = FC_GEAR_1_2;
+        break;
+    case CG_DIVIDE_4:
+        gear = FC_GEAR_1_4;
+        break;
+    case CG_DIVIDE_8:
+        gear = FC_GEAR_1_8;
+        break;
+    case CG_DIVIDE_16:
+        gear = FC_GEAR_1_16;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+
+    regval &= CG_FC_GEAR_MASK;
+    regval |= gear;
+    TSB_CG->SYSCR = regval;
+}
+
+/**
+  * @brief  Get dividing level between clock fgear and fc.
+  * @param  None
+  * @retval The dividing level between clock fgear and fc
+  *   The value returned can be one of the following values:
+  *   CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4,
+  *   CG_DIVIDE_8, CG_DIVIDE_16 or CG_DIVIDE_UNKNOWN
+  */
+CG_DivideLevel CG_GetFgearLevel(void)
+{
+    CG_DivideLevel DivideFgearFromFc = CG_DIVIDE_UNKNOWN;
+    uint32_t syscr = TSB_CG->SYSCR;
+    syscr &= (~CG_FC_GEAR_MASK);
+
+    switch (syscr) {
+    case FC_GEAR_1_1:
+        DivideFgearFromFc = CG_DIVIDE_1;
+        break;
+    case FC_GEAR_1_2:
+        DivideFgearFromFc = CG_DIVIDE_2;
+        break;
+    case FC_GEAR_1_4:
+        DivideFgearFromFc = CG_DIVIDE_4;
+        break;
+    case FC_GEAR_1_8:
+        DivideFgearFromFc = CG_DIVIDE_8;
+        break;
+    case FC_GEAR_1_16:
+        DivideFgearFromFc = CG_DIVIDE_16;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+
+    return DivideFgearFromFc;
+}
+
+/**
+  * @brief  Set fperiph for PhiT0
+  * @param  PhiT0Src: Set PhiT0 Source
+  *   This parameter can be one of the following values:
+  *   CG_PHIT0_SRC_FGEAR or CG_PHIT0_SRC_FC
+  * @retval None
+  */
+void CG_SetPhiT0Src(CG_PhiT0Src PhiT0Src)
+{
+    uint32_t regval = 0U;
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_CG_PHIT0_SRC(PhiT0Src));
+
+    regval = TSB_CG->SYSCR;
+    regval &= CG_FPSEL_MASK;
+    tmp = (uint32_t) PhiT0Src;
+    regval |= (tmp << 12U);
+
+    TSB_CG->SYSCR = regval;
+}
+
+/**
+  * @brief  Get PhiT0 Source
+  * @param  None
+  * @retval The source of PhiT0
+  *   The value returned can be one of the following values:
+  *   CG_PHIT0_SRC_FGEAR or CG_PHIT0_SRC_FC
+  */
+CG_PhiT0Src CG_GetPhiT0Src(void)
+{
+    uint32_t regval = 0U;
+    CG_PhiT0Src source = CG_PHIT0_SRC_FGEAR;
+
+    regval = TSB_CG->SYSCR;
+    regval &= (~CG_FPSEL_MASK);
+    regval = (regval >> 12U);
+    source = numPhiT0Src_table[regval];
+
+    return source;
+}
+
+/**
+  * @brief  Set dividing level between clock PhiT0 and fc.
+  * @param  DividePhiT0FromFc: Dividing level between PhiT0 and fc.
+  *   This parameter can be one of the following values:
+  *   CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8,
+  *   CG_DIVIDE_16, CG_DIVIDE_32, CG_DIVIDE_64, CG_DIVIDE_128,
+  *   CG_DIVIDE_256 or CG_DIVIDE_512
+  * @retval  Success or not
+  *   The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  */
+Result CG_SetPhiT0Level(CG_DivideLevel DividePhiT0FromFc)
+{
+    uint32_t fprclk = 0U;
+    CG_DivideLevel fgear = CG_DIVIDE_UNKNOWN;
+    CG_PhiT0Src PhiT0_src = CG_PHIT0_SRC_FGEAR;
+    Result retval = ERROR;
+    uint32_t regval = TSB_CG->SYSCR;
+
+    PhiT0_src = CG_GetPhiT0Src();
+    if (PhiT0_src == CG_PHIT0_SRC_FC) { /* phiT0 src == fc , max divider: 32 */
+        /* Check the parameters */
+        assert_param(IS_CG_FC_DIVIDE_LEVEL(DividePhiT0FromFc));
+
+        fprclk = (uint32_t) DividePhiT0FromFc;
+        regval &= CG_PRCK_MASK;
+        fprclk <<= 8U;
+        regval |= fprclk;
+        TSB_CG->SYSCR = regval;
+        retval = SUCCESS;
+    } else {                    /* phiT0 src == fgear, max divider: 512 */
+        /* Check the parameters */
+        assert_param(IS_CG_DIVIDE_FC_LEVEL(DividePhiT0FromFc));
+
+        fgear = CG_GetFgearLevel();
+        if (fgear != CG_DIVIDE_UNKNOWN) {
+            if (DividePhiT0FromFc >= fgear) {
+                fprclk = (uint32_t) DividePhiT0FromFc - (uint32_t) fgear;
+                if (fprclk < CG_DIVIDE_64) {
+                    regval &= CG_PRCK_MASK;
+                    fprclk <<= 8U;
+                    regval |= fprclk;
+                    TSB_CG->SYSCR = regval;
+                    retval = SUCCESS;
+                } else {
+                    /* Do nothing */
+                }
+            } else {
+                /* Do nothing */
+            }
+        } else {
+            /* Do nothing */
+        }
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Get dividing level between clock phiT0 and fc.
+  * @param  None
+  * @retval The divide level between clock phiT0 and fc
+  *   The value returned can be one of the following values:
+  *   CG_DIVIDE_1, CG_DIVIDE_2, CG_DIVIDE_4, CG_DIVIDE_8,
+  *   CG_DIVIDE_16, CG_DIVIDE_32, CG_DIVIDE_64, CG_DIVIDE_128,
+  *   CG_DIVIDE_256, CG_DIVIDE_512 or CG_DIVIDE_UNKNOWN
+  */
+CG_DivideLevel CG_GetPhiT0Level(void)
+{
+    uint32_t fprclk = 0U;
+    CG_DivideLevel fgear = CG_DIVIDE_UNKNOWN;
+    CG_DivideLevel phiT0Level = CG_DIVIDE_UNKNOWN;
+    CG_PhiT0Src PhiT0_src = CG_PHIT0_SRC_FGEAR;
+
+    fprclk = TSB_CG->SYSCR & (~CG_PRCK_MASK);
+    fprclk = (uint32_t) (fprclk >> 8U);
+    PhiT0_src = CG_GetPhiT0Src();
+
+    if (PhiT0_src == CG_PHIT0_SRC_FC) {
+        phiT0Level = numToDivideLevel_table[fprclk];
+    } else {
+        fgear = CG_GetFgearLevel();
+        if (fgear != CG_DIVIDE_UNKNOWN) {
+            fprclk = fprclk + fgear;
+            if (fprclk < CG_DIVIDE_UNKNOWN) {
+                phiT0Level = numToDivideLevel_table[fprclk];
+            } else {
+                /* Do nothing */
+            }
+        } else {
+            /* Do nothing */
+        }
+    }
+
+    return phiT0Level;
+}
+
+/**
+  * @brief Set the source of SCOUT output
+  * @param Source: Select source of SCOUT
+  *   This parameter can be one of the following values:
+  *   CG_SCOUT_SRC_FS, CG_SCOUT_SRC_FSYS_DIVIDE_8,
+  *   CG_SCOUT_SRC_FSYS_DIVIDE_4 or CG_SCOUT_SRC_FOSC
+  * @retval None
+  */
+void CG_SetSCOUTSrc(CG_SCOUTSrc Source)
+{
+    /* Get the original SCOUT SRC value */
+    uint32_t tmp = 0U;
+    uint32_t regval = TSB_CG->SYSCR;
+
+    /* Check the parameters */
+    assert_param(IS_CG_SCOUT_SRC(Source));
+
+    switch (Source) {
+    case CG_SCOUT_SRC_FS:
+        tmp = SCOUT_SRC_FS;
+        break;
+    case CG_SCOUT_SRC_FSYS_DIVIDE_8:
+        tmp = SCOUT_SRC_FSYS_DIVIDE_8;
+        break;
+    case CG_SCOUT_SRC_FSYS_DIVIDE_4:
+        tmp = SCOUT_SRC_FSYS_DIVIDE_4;
+        break;
+    case CG_SCOUT_SRC_FOSC:
+        tmp = SCOUT_SRC_FOSC;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+
+    regval &= CG_SCOUT_MASK;
+    regval |= tmp;
+    TSB_CG->SYSCR = regval;
+}
+
+/**
+  * @brief  Get the source of SCOUT output.
+  * @param  None
+  * @retval Source of SCOUT output
+  *   The value returned can be one of the following values:
+  *   CG_SCOUT_SRC_FS, CG_SCOUT_SRC_FSYS_DIVIDE_8,
+  *   CG_SCOUT_SRC_FSYS_DIVIDE_4 or CG_SCOUT_SRC_FOSC
+  */
+CG_SCOUTSrc CG_GetSCOUTSrc(void)
+{
+    uint32_t tmp = 0U;
+    CG_SCOUTSrc source = CG_SCOUT_SRC_FS;
+    tmp = TSB_CG->SYSCR & (~CG_SCOUT_MASK);
+
+    switch (tmp) {
+    case SCOUT_SRC_FS:
+        source = CG_SCOUT_SRC_FS;
+        break;
+    case SCOUT_SRC_FSYS_DIVIDE_8:
+        source = CG_SCOUT_SRC_FSYS_DIVIDE_8;
+        break;
+    case SCOUT_SRC_FSYS_DIVIDE_4:
+        source = CG_SCOUT_SRC_FSYS_DIVIDE_4;
+        break;
+    case SCOUT_SRC_FOSC:
+        source = CG_SCOUT_SRC_FOSC;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+
+    return source;
+}
+
+/**
+  * @brief  Set the warm up time
+  * @param  Source: Select source of warm-up counter
+  *   This parameter can be one of the following values:
+  *   CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WARM_UP_SRC_OSC_EXT_HIGH, CG_WARM_UP_SRC_OSC_EXT_LOW
+  *   Warm-up function is not necessary when using stable external clock.
+  * @param  Time: Set number of warm-up cycle. It is between 0x0000 and 0xFFFF.
+  * @retval None
+  */
+void CG_SetWarmUpTime(CG_WarmUpSrc Source, uint16_t Time)
+{
+    uint32_t wupt = 0U;
+    uint32_t wuptl = 0U;
+    uint32_t regval = TSB_CG->OSCCR;
+
+    /* Check the parameters */
+    assert_param(IS_CG_WARM_UP_SRC(Source));
+
+    /* Get high 12 bits of warm-up time */
+    wupt = (((uint32_t) Time) & CG_OSCCR_WUPT_MASK) << 16U;
+    /* Get high 12 bits and low 2 bits of warm-up time */
+    wuptl = (((uint32_t) Time) & CG_OSCCR_WUPTL_MASK) << 16U;
+
+    regval &= CG_WUP_TIME_MASK;
+    regval &= CG_WUP_COUNTER_MASK;
+
+    switch (Source) {
+    case CG_WARM_UP_SRC_OSC_INT_HIGH:
+        regval |= wupt;
+        regval |= WARM_UP_SEL_OSC_INT_HIGH;
+        break;
+    case CG_WARM_UP_SRC_OSC_EXT_HIGH:
+        regval |= wupt;
+        regval |= WARM_UP_SEL_OSC_EXT_HIGH;
+        break;
+    case CG_WARM_UP_SRC_OSC_EXT_LOW:
+        /* Set high 12 bits and low 2 bits of warm-up time */
+        regval |= wuptl;
+        regval |= WARM_UP_SEL_OSC_EXT_LOW;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+
+    TSB_CG->OSCCR = regval;
+}
+
+/**
+  * @brief  Start operation of warm up timer for oscillator.
+  * @param  None
+  * @retval None
+  */
+void CG_StartWarmUp(void)
+{
+    uint32_t regval = TSB_CG->OSCCR;
+    regval |= CG_WUP_START_SET;
+    TSB_CG->OSCCR = regval;
+}
+
+/**
+  * @brief Check whether warm up is completed or not.
+  * @param  None
+  * @retval The state of warm-up
+  *   The value returned can be one of the following values:
+  *   DONE or BUSY
+  */
+WorkState CG_GetWarmUpState(void)
+{
+    WorkState state = BUSY;
+    uint32_t wuef = 0U;
+    uint32_t regval = TSB_CG->OSCCR;
+
+    wuef = regval & CG_WUEF_VALUE_MASK;
+    if (wuef == 0U) {
+        state = DONE;
+    } else {
+        /* Do nothing */
+    }
+
+    return state;
+}
+
+/**
+  * @brief  Set PLL multiplying value
+  * @param  NewValue: PLL multiplying value
+  *   This parameter can be one of the following values:
+  *   CG_8M_MUL_4_FPLL, CG_8M_MUL_5_FPLL, CG_8M_MUL_6_FPLL, CG_8M_MUL_8_FPLL,
+  *   CG_8M_MUL_10_FPLL, CG_8M_MUL_12_FPLL, CG_10M_MUL_4_FPLL, CG_10M_MUL_5_FPLL,
+  *   CG_10M_MUL_6_FPLL, CG_10M_MUL_8_FPLL, CG_10M_MUL_10_FPLL, CG_10M_MUL_12_FPLL,
+  *   CG_12M_MUL_4_FPLL, CG_12M_MUL_5_FPLL, CG_12M_MUL_6_FPLL, CG_12M_MUL_8_FPLL,
+  *   CG_12M_MUL_10_FPLL, CG_16M_MUL_4_FPLL or CG_16M_MUL_5_FPLL.
+  * @retval Success or not
+  *   The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  */
+Result CG_SetFPLLValue(uint32_t NewValue)
+{
+    Result retval = SUCCESS;
+
+    /* read PLLSEL and clear PLLSET(bit14:0) */
+    uint32_t tmp = TSB_CG->PLLSEL & CG_PLLSEL_PLLSET_MASK;
+
+    /* Check the parameters */
+    assert_param(IS_CG_FPLL_VALUE(NewValue));
+
+    /* Don't use the PLL when internal high-speed oscillator (IHOSC) is used as system clock */
+    /* When PLL is on, don't change the PLL setting value */
+    if (CG_FOSC_OSC_INT == CG_GetFoscSrc()) {
+        retval = ERROR;
+    } else if (ENABLE == CG_GetPLLState()) {
+        retval = ERROR;
+    } else {
+        tmp |= NewValue;
+        TSB_CG->PLLSEL = tmp;
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Get the value of PLL setting
+  * @param  None
+  * @retval Get the value of PLL setting.
+  *   CG_8M_MUL_4_FPLL, CG_8M_MUL_5_FPLL, CG_8M_MUL_6_FPLL, CG_8M_MUL_8_FPLL,
+  *   CG_8M_MUL_10_FPLL, CG_8M_MUL_12_FPLL, CG_10M_MUL_4_FPLL, CG_10M_MUL_5_FPLL,
+  *   CG_10M_MUL_6_FPLL, CG_10M_MUL_8_FPLL, CG_10M_MUL_10_FPLL, CG_10M_MUL_12_FPLL,
+  *   CG_12M_MUL_4_FPLL, CG_12M_MUL_5_FPLL, CG_12M_MUL_6_FPLL, CG_12M_MUL_8_FPLL,
+  *   CG_12M_MUL_10_FPLL, CG_16M_MUL_4_FPLL or CG_16M_MUL_5_FPLL.
+  */
+uint32_t CG_GetFPLLValue(void)
+{
+    uint32_t pllsel = TSB_CG->PLLSEL & CG_PLLSET_VALUE_MASK;
+
+    return pllsel;
+}
+
+/**
+  * @brief  Enable PLL or disable it.
+  * @param  NewState: New state of PLL
+  *   This parameter can be one of the following values:
+  *   DISABLE or ENABLE
+  * @retval Success or not
+  *   The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  */
+Result CG_SetPLL(FunctionalState NewState)
+{
+    Result retval = ERROR;
+    uint32_t regval = TSB_CG->PLLSEL;
+    CG_FcSrc fcsrc = CG_FC_SRC_FPLL;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        regval |= CG_PLLSEL_PLLON_SET;
+        retval = SUCCESS;
+    } else {
+        fcsrc = CG_GetFcSrc();
+        if (fcsrc == CG_FC_SRC_FOSC) {  /* PLL is not used. So it can be shut off */
+            /* Set register to disable PLL */
+            regval &= CG_PLLSEL_PLLON_CLEAR;
+            retval = SUCCESS;
+        } else {                /*fcsrc == CG_FC_SRC_FPLL. PLL is in use, so disabling it should be invalid */
+            /* Do nothing */
+        }
+    }
+    TSB_CG->PLLSEL = regval;
+    return retval;
+}
+
+/**
+  * @brief  Get the status of PLL operation
+  * @param  None
+  * @retval Run or stop
+  *   The value returned can be one of the following values:
+  *   ENABLE or DISABLE
+  */
+FunctionalState CG_GetPLLState(void)
+{
+    FunctionalState pllstate = DISABLE;
+    uint32_t regval = TSB_CG->PLLSEL;
+
+    regval &= CG_PLLSEL_PLLON_SET;
+    if (regval == CG_PLLSEL_PLLON_SET) {
+        pllstate = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+
+    return pllstate;
+}
+
+/**
+  * @brief  Enable or disable high-speed oscillator (fosc)
+  * @param  Source: Select clock source for fosc
+  *   This parameter can be one of the following values:
+  *   CG_FOSC_OSC_EXT or CG_FOSC_OSC_INT
+  * @param  NewState: oscillator is enabled or disabled
+  *   This parameter can be one of the following values:
+  *   DISABLE or ENABLE
+  * @retval Success or failure
+  *   The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  */
+Result CG_SetFosc(CG_FoscSrc Source, FunctionalState NewState)
+{
+    CG_FoscSrc fosc_src = CG_FOSC_OSC_INT;
+    Result retval = ERROR;
+    uint32_t regval = TSB_CG->OSCCR;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_CG_FOSC_STATE(Source));
+
+    switch (Source) {
+    case CG_FOSC_OSC_EXT:
+        if (NewState == ENABLE) {
+            /* Enable external high-speed oscillator */
+            regval |= CG_OSCCR_XEN1_SET;
+            /*Selects external high-speed oscillator */
+            regval |= CG_OSCCR_HOSCON_SET;
+            retval = SUCCESS;
+        } else {
+            fosc_src = CG_GetFoscSrc();
+            if (fosc_src == CG_FOSC_OSC_EXT) {
+                /* external oscillator is in  use, so it can't be disabled */
+                retval = ERROR;
+            } else {
+                /* Disable external high-speed oscillator */
+                regval &= CG_OSCCR_XEN1_CLEAR;
+                retval = SUCCESS;
+            }
+        }
+
+        break;
+    case CG_FOSC_OSC_INT:
+        if (NewState == ENABLE) {
+            /* Enable internal high-speed oscillator */
+            regval |= CG_OSCCR_XEN2_SET;
+            retval = SUCCESS;
+        } else {
+            fosc_src = CG_GetFoscSrc();
+            if (fosc_src == CG_FOSC_OSC_INT) {
+                /* internal high-speed oscillator is in  use, so it can't be disabled */
+                retval = ERROR;
+            } else {
+                /* Disable internal high-speed oscillator */
+                regval &= CG_OSCCR_XEN2_CLEAR;
+                retval = SUCCESS;
+            }
+        }
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+    TSB_CG->OSCCR = regval;
+    return retval;
+}
+
+/**
+  * @brief  Set the source of high-speed oscillator (fosc)
+  * @param  Source: Select clock source for fosc
+  *   This parameter can be one of the following values:
+  *   CG_FOSC_OSC_EXT , CG_FOSC_CLKIN_EXT or CG_FOSC_OSC_INT
+  * @retval None
+  */
+void CG_SetFoscSrc(CG_FoscSrc Source)
+{
+    /* Check the parameters */
+    assert_param(IS_CG_FOSC_SRC(Source));
+
+    if (Source == CG_FOSC_OSC_INT) {
+        /*Selects internal high-speed oscillator */
+        TSB_CG->OSCCR &= CG_OSCCR_OSCSEL_CLEAR;
+    } else {
+        if (Source == CG_FOSC_OSC_EXT) {
+            /*Selects external high-speed oscillator */
+            TSB_CG->OSCCR |= CG_OSCCR_HOSCON_SET;
+            /*Selects external high-speed oscillator */
+            TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
+        } else {
+            /*Selects an external clock input */
+            TSB_CG->OSCCR &= CG_OSCCR_HOSCON_CLEAR;
+            /*Selects external high-speed oscillator */
+            TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
+        }
+    }
+}
+
+/**
+  * @brief  Get the source of high-speed oscillator (fosc)
+  * @param  None
+  * @retval Source of fosc
+  *   The value returned can be one of the following values:
+  *   CG_FOSC_OSC_EXT , CG_FOSC_CLKIN_EXT or CG_FOSC_OSC_INT
+  */
+CG_FoscSrc CG_GetFoscSrc(void)
+{
+    uint32_t regval = TSB_CG->OSCCR;
+    uint32_t oscf = 0U;
+    uint32_t hoscon = 0U;
+    CG_FoscSrc fosc_src = CG_FOSC_CLKIN_EXT;
+
+    oscf = regval & CG_OSCCR_OSCF_SET;
+    hoscon = regval & CG_OSCCR_HOSCON_SET;
+    if (oscf == 0U) {
+        fosc_src = CG_FOSC_OSC_INT;
+    } else {
+        if (hoscon == CG_OSCCR_HOSCON_SET) {
+            fosc_src = CG_FOSC_OSC_EXT;
+        } else {
+            /* Do nothing */
+        }
+    }
+
+    return fosc_src;
+}
+
+/**
+  * @brief  Get the state of high-speed oscillator (fosc)
+  * @param  Source: Select fosc source
+  *   This parameter can be one of the following values:
+  *   CG_FOSC_OSC_EXT or CG_FOSC_OSC_INT
+  * @retval State of fosc
+  *   The value returned can be one of the following values:
+  *   ENABLE or DISABLE
+  */
+FunctionalState CG_GetFoscState(CG_FoscSrc Source)
+{
+    uint32_t regval = TSB_CG->OSCCR;
+    uint32_t xen1 = 0U;
+    uint32_t xen2 = 0U;
+    FunctionalState state = DISABLE;
+
+    /* Check the parameters */
+    assert_param(IS_CG_FOSC_STATE(Source));
+
+    xen1 = regval & CG_OSCCR_XEN1_SET;
+    xen2 = regval & CG_OSCCR_XEN2_SET;
+
+    if (Source == CG_FOSC_OSC_EXT) {
+        if (xen1 == CG_OSCCR_XEN1_SET) {
+            state = ENABLE;
+        } else {
+            /* Do nothing */
+        }
+    } else if (xen2 == CG_OSCCR_XEN2_SET) {
+        state = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+
+    return state;
+}
+
+
+/**
+  * @brief  Set to the specified low-power mode
+  * @param  Low power mode
+  *   The value can be one of the following values:
+  *   CG_STBY_MODE_STOP1, CG_STBY_MODE_IDLE, CG_STBY_MODE_STOP2
+  * @retval None
+  */
+void CG_SetSTBYMode(CG_STBYMode Mode)
+{
+    uint32_t regval = TSB_CG->STBYCR;
+
+    /* Check the parameter */
+    assert_param(IS_CG_STBY_MODE(Mode));
+
+    regval &= CG_STBY_MODE_MASK;
+    regval |= (uint32_t) Mode;
+
+    TSB_CG->STBYCR = regval;
+}
+
+/**
+  * @brief  Get the low-power consumption mode
+  * @param  None
+  * @retval Low power mode
+  *   The value returned can be one of the following values:
+  *   CG_STBY_MODE_STOP1, CG_STBY_MODE_IDLE,
+  *   CG_STBY_MODE_STOP2, CG_STBY_MODE_UNKNOWN
+  */
+CG_STBYMode CG_GetSTBYMode(void)
+{
+    CG_STBYMode stby_mode = CG_STBY_MODE_UNKNOWN;
+    uint8_t regval = (uint8_t) (TSB_CG->STBYCR & (~CG_STBY_MODE_MASK));
+
+    stby_mode = numToSTBYMode_table[regval];
+
+    return stby_mode;
+}
+
+/**
+  * @brief  Enable or disable to keep IO control signal in stop2 mode
+  * @param  NewState: enable or disable
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE
+  * @retval None
+  */
+void CG_SetPortKeepInStop2Mode(FunctionalState NewState)
+{
+    uint32_t regval = TSB_CG->STBYCR;
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        regval |= CG_STBYCR_PTKEEP_SET;
+    } else {
+        regval &= CG_STBYCR_PTKEEP_CLEAR;
+    }
+    TSB_CG->STBYCR = regval;
+}
+
+/**
+  * @brief  Get the status of  IO control signal in stop2 mode
+  * @param  None
+  * @retval State of IO control signal in stop2 mode
+  *   The value returned can be one of the following values:
+  *   DISABLE or ENABLE
+  */
+FunctionalState CG_GetPortKeepInStop2Mode(void)
+{
+    uint32_t regval = TSB_CG->STBYCR;
+    FunctionalState state = DISABLE;
+
+    regval &= CG_STBYCR_PTKEEP_SET;
+    if (regval == CG_STBYCR_PTKEEP_SET) {
+        /* Pin status in stop mode is active */
+        state = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+    return state;
+}
+
+/**
+  * @brief  Set the source of fc
+  * @param  Source:  The source of fc
+  *   This parameter can be one of the following values:
+  *   CG_FC_SRC_FOSC or CG_FC_SRC_FPLL
+  * @retval success or failure
+  *   The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  */
+Result CG_SetFcSrc(CG_FcSrc Source)
+{
+    Result retval = ERROR;
+    FunctionalState fosc_on = DISABLE;
+    FunctionalState pllon = DISABLE;
+    CG_FoscSrc fosc_src = CG_FOSC_OSC_EXT;
+    uint32_t regval = TSB_CG->PLLSEL;
+
+    /* Check the parameters */
+    assert_param(IS_CG_FC_SRC(Source));
+
+    if (Source == CG_FC_SRC_FOSC) {
+        fosc_src = CG_GetFoscSrc();
+        switch (fosc_src) {
+        case CG_FOSC_OSC_EXT:
+            fosc_on = CG_GetFoscState(CG_FOSC_OSC_EXT);
+            if (fosc_on == ENABLE) {
+                regval &= CG_PLLSEL_PLLSEL_CLEAR;
+                retval = SUCCESS;
+            } else {
+                /* Do nothing */
+            }
+            break;
+        case CG_FOSC_OSC_INT:
+            fosc_on = CG_GetFoscState(CG_FOSC_OSC_INT);
+            if (fosc_on == ENABLE) {
+                regval &= CG_PLLSEL_PLLSEL_CLEAR;
+                retval = SUCCESS;
+            } else {
+                /* Do nothing */
+            }
+            break;
+        case CG_FOSC_CLKIN_EXT:
+            regval &= CG_PLLSEL_PLLSEL_CLEAR;
+            retval = SUCCESS;
+            break;
+        default:
+            /* Do nothing */
+            break;
+        }
+
+    } else {
+        pllon = CG_GetPLLState();
+        if (pllon == ENABLE) {
+            regval |= CG_PLLSEL_PLLSEL_SET;
+            retval = SUCCESS;
+        } else {
+            /* Do nothing */
+        }
+    }
+    TSB_CG->PLLSEL = regval;
+    return retval;
+}
+
+/**
+  * @brief  Get the source of fc
+  * @param  None
+  * @retval The source of fc
+  *   The value returned can be one of the following values:
+  *   CG_FC_SRC_FOSC or CG_FC_SRC_FPLL
+  */
+CG_FcSrc CG_GetFcSrc(void)
+{
+    uint32_t regval = TSB_CG->PLLSEL;
+    CG_FcSrc fcsrc = CG_FC_SRC_FOSC;
+
+    regval &= CG_PLLSEL_PLLST_SET;
+    if (regval == CG_PLLSEL_PLLST_SET) {
+        fcsrc = CG_FC_SRC_FPLL;
+    } else {
+        /* Do nothing */
+    }
+
+    return fcsrc;
+}
+
+/**
+  * @brief  Enable or disable to protect CG registers
+  * @param  NewState: New state of the CG protect register
+  *   This parameter can be one of the following values:
+  *   DISABLE or ENABLE
+  * @retval None
+  */
+void CG_SetProtectCtrl(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        TSB_CG->PROTECT = CG_PROTECT_SET;
+    } else {
+        TSB_CG->PROTECT = CG_PROTECT_CLEAR;
+    }
+}
+
+/**
+  * @brief  Setup the INT source for releasing low power mode.
+  * @param  INTSource: Select the release INT source
+  *   This parameter can be one of the following values:
+  *   CG_INT_SRC_1, CG_INT_SRC_2, CG_INT_SRC_7, CG_INT_SRC_8,
+  *   CG_INT_SRC_D, CG_INT_SRC_E, CG_INT_SRC_F or CG_INT_SRC_RTC.
+  * @param  ActiveState: select the active state for release trigger
+  *   For CG_INT_SRC_RTC, this parameter can only be
+  *   CG_INT_ACTIVE_STATE_FALLING
+  *   For the other interrupt source, this parameter can be one of 
+  *   the following values:
+  *   CG_INT_ACTIVE_STATE_L, CG_INT_ACTIVE_STATE_H,
+  *   CG_INT_ACTIVE_STATE_FALLING, CG_INT_ACTIVE_STATE_RISING or
+  *   CG_INT_ACTIVE_STATE_BOTH_EDGES.
+  * @param  NewState: Enable or disable this release trigger
+  *   This parameter can be one of the following values:
+  *   DISABLE or ENABLE
+  * @retval None
+  */
+void CG_SetSTBYReleaseINTSrc(CG_INTSrc INTSource,
+                             CG_INTActiveState ActiveState, FunctionalState NewState)
+{
+    uint32_t num = 0U;
+    uint8_t i = 0U;
+    uint8_t j = 0U;
+    CG_Byte4 regval = { 0U };
+
+    /* Check the parameters */
+    assert_param(IS_CG_INT_SRC(INTSource));
+    assert_param(IS_CG_INT_ACTIVE_STATE(ActiveState));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (INTSource == CG_INT_SRC_RTC) {
+        assert_param(IS_CG_INT_RTC_ACTIVE_STATE(ActiveState));
+    } else {
+        /* Do nothing */
+    }
+
+    num = (uint32_t) INTSource;
+    i = (uint8_t) (num / 4U);
+    j = (uint8_t) (num % 4U);
+
+    switch (i) {
+    case 0U:                   /* IMCGA */
+        regval.byte4 = TSB_CG->IMCGA;
+        regval.byte[j] &= 0x8CU;
+        regval.byte[j] |= ActiveState;
+        TSB_CG->IMCGA = regval.byte4;
+        regval.byte[j] |= NewState;
+        TSB_CG->IMCGA = regval.byte4;
+        break;
+    case 1U:                   /* IMCGB */
+        regval.byte4 = TSB_CG->IMCGB;
+        regval.byte[j] &= 0x8CU;
+        regval.byte[j] |= ActiveState;
+        TSB_CG->IMCGB = regval.byte4;
+        regval.byte[j] |= NewState;
+        TSB_CG->IMCGB = regval.byte4;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+}
+
+/**
+  * @brief  Get the active state of INT source standby clear request
+  * @param  INTSource: Select the release INT source
+  *   This parameter can be one of the following values:
+  *   CG_INT_SRC_1, CG_INT_SRC_2, CG_INT_SRC_7, CG_INT_SRC_8,
+  *   CG_INT_SRC_D, CG_INT_SRC_E, CG_INT_SRC_F or CG_INT_SRC_RTC.
+  * @retval Active state of the input INT
+  *   The value returned can be one of the following values:
+  *   CG_INT_ACTIVE_STATE_FALLING, CG_INT_ACTIVE_STATE_RISING,
+  *   CG_INT_ACTIVE_STATE_BOTH_EDGES or CG_INT_ACTIVE_STATE_INVALID
+  */
+CG_INTActiveState CG_GetSTBYReleaseINTState(CG_INTSrc INTSource)
+{
+    CG_INTActiveState int_active_state = CG_INT_ACTIVE_STATE_INVALID;
+    uint8_t i = 0U;
+    uint8_t j = 0U;
+    uint8_t tmp = 0U;
+    uint32_t num = 0U;
+    CG_Byte4 regval[6] = { {0U}
+    , {0U}
+    , {0U}
+    , {0U}
+    , {0U}
+    , {0U}
+    };
+
+    /* Check the parameters */
+    assert_param(IS_CG_INT_SRC(INTSource));
+
+    regval[0].byte4 = TSB_CG->IMCGA;
+    regval[1].byte4 = TSB_CG->IMCGB;
+
+    num = (uint32_t) INTSource;
+    i = (uint8_t) (num / 4U);
+    j = (uint8_t) (num % 4U);
+    tmp = regval[i].byte[j];
+    tmp &= 0x0CU;
+
+    switch (tmp) {
+    case 0x04U:
+        int_active_state = CG_INT_ACTIVE_STATE_RISING;
+        break;
+    case 0x08U:
+        int_active_state = CG_INT_ACTIVE_STATE_FALLING;
+        break;
+    case 0x0CU:
+        int_active_state = CG_INT_ACTIVE_STATE_BOTH_EDGES;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+
+    return (int_active_state);
+}
+
+/**
+  * @brief  Clears the input INT request.
+  * @param  INTSource: Select the release INT source
+  *   This parameter can be one of the following values:
+  *   CG_INT_SRC_1, CG_INT_SRC_2, CG_INT_SRC_7, CG_INT_SRC_8,
+  *   CG_INT_SRC_D, CG_INT_SRC_E, CG_INT_SRC_F or CG_INT_SRC_RTC.
+  * @retval None
+  */
+void CG_ClearINTReq(CG_INTSrc INTSource)
+{
+    uint32_t regval = INTSource;
+
+    /* Check the parameters */
+    assert_param(IS_CG_INT_SRC(INTSource));
+
+    TSB_CG->ICRCG = regval;
+}
+
+/**
+  * @brief  Get the NMI flag that shows who triggered NMI.
+  * @param  None
+  * @retval NMI flag
+  */
+CG_NMIFactor CG_GetNMIFlag(void)
+{
+    CG_NMIFactor cg_nmi_factor = { 0U };
+
+    cg_nmi_factor.All = TSB_CG->NMIFLG & (~CG_NMIFLG_MASK);
+
+    return cg_nmi_factor;
+}
+
+/**
+  * @brief  Get the flag for stopping of the internal high-speed oscillator or writing to the flash memory.
+  * @param  None
+  * @retval Flag for stopping of the internal high-speed oscillator or writing to the flash memory.
+  *   The value returned can be one of the following values:
+  *   ENABLE or DISABLE
+  */
+FunctionalState CG_GetIOSCFlashFlag(void)
+{
+    uint32_t tmp = TSB_CG->RSTFLG;
+    FunctionalState state = DISABLE;
+
+    tmp &= CG_IOSC_FLASH_MASK;
+    if (tmp == CG_IOSC_FLASH_MASK) {
+        state = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+
+    return state;
+}
+
+/**
+  * @brief  Get the type of reset reason and clear the reset flag.
+  * @param  None
+  * @retval Reset flag
+  */
+CG_ResetFlag CG_GetResetFlag(void)
+{
+    CG_ResetFlag reset_flag = { 0U };
+
+    reset_flag.All = TSB_CG->RSTFLG & (~CG_RESET_FLAG_MASK);
+    TSB_CG->RSTFLG = CG_IOSC_FLASH_MASK;
+
+    return reset_flag;
+}
+
+/**
+  * @brief  Enable or disable supplying clock fsys for ADC.
+  * @param  NewState: New state of clock fsys supply setting for ADC.
+  *   This parameter can be one of the following values:
+  *   ENABLE or DISABLE.
+  * @retval None.
+  */
+void CG_SetADCClkSupply(FunctionalState NewState)
+{
+    volatile uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Check ADC is not during conversion */
+    do {
+        tmp = TSB_AD->MOD5 & ADC_MOD5_BUSY_MASK;
+    }
+    while (tmp);
+
+    /* Set CGSYSCR<FCSTOP>  */
+    tmp = TSB_CG->SYSCR;
+    if (NewState == ENABLE) {
+        tmp &= CG_SYSCR_FCSTOP_CLEAR;
+    } else {
+        tmp |= CG_SYSCR_FCSTOP_SET;
+    }
+    TSB_CG->SYSCR = tmp;
+}
+
+ /**
+   * @brief  Enable or disable supplying clock fsys to peripheries
+   * @param  Periph: The target peripheral of CG supplies clock
+   *   This parameter can be one of the following values or their combination:
+   *   CG_FC_PERIPH_PORTA,  CG_FC_PERIPH_PORTB,  CG_FC_PERIPH_PORTC,
+   *   CG_FC_PERIPH_PORTD,  CG_FC_PERIPH_PORTE,  CG_FC_PERIPH_PORTF,
+   *   CG_FC_PERIPH_PORTG,  CG_FC_PERIPH_PORTH,  CG_FC_PERIPH_PORTJ,
+   *   CG_FC_PERIPH_PORTK,  CG_FC_PERIPH_PORTL,  CG_FC_PERIPH_TMRB0,
+   *   CG_FC_PERIPH_TMRB1,  CG_FC_PERIPH_TMRB2,  CG_FC_PERIPH_TMRB3,
+   *   CG_FC_PERIPH_TMRB4,  CG_FC_PERIPH_TMRB5,  CG_FC_PERIPH_TMRB6,
+   *   CG_FC_PERIPH_TMRB7,  CG_FC_PERIPH_MPT0,   CG_FC_PERIPH_MPT1,
+   *   CG_FC_PERIPH_MPT2,   CG_FC_PERIPH_MPT3,   CG_FC_PERIPH_TRACE,
+   *   CG_FC_PERIPHA_ALL.
+   * @param  NewState: New state of clock supply setting.
+   *   This parameter can be one of the following values:
+   *   DISABLE or ENABLE
+   * @retval None
+   */
+void CG_SetFcPeriphA(uint32_t Periph, FunctionalState NewState)
+{
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_CG_FC_PERIPHA(Periph));
+    if (NewState == ENABLE) {   /* clear to '0' to enable */
+        TSB_CG->FSYSMSKA &= ~Periph;
+    } else {                    /* write '1' to disable   */
+        TSB_CG->FSYSMSKA |= Periph;
+    }
+}
+
+ /**
+   * @brief  Enable or disable supplying clock fsys to peripheries
+   * @param  Periph: The target peripheral of CG supplies clock
+   *   This parameter can be one of the following values or their combination:
+   *   CG_FC_PERIPH_SIO_UART0, CG_FC_PERIPH_SIO_UART1, CG_FC_PERIPH_SIO_UART2,
+   *   CG_FC_PERIPH_SIO_UART3, CG_FC_PERIPH_UART0, CG_FC_PERIPH_UART1,
+   *   CG_FC_PERIPH_I2C0,      CG_FC_PERIPH_I2C1,  CG_FC_PERIPH_I2C2,
+   *   CG_FC_PERIPH_SSP0,      CG_FC_PERIPH_SSP1,  CG_FC_PERIPH_SSP2,
+   *   CG_FC_PERIPH_EBIF,      CG_FC_PERIPH_DMACA, CG_FC_PERIPH_DMACB,
+   *   CG_FC_PERIPH_DMACC,     CG_FC_PERIPH_DMAIF, CG_FC_PERIPH_ADC,
+   *   CG_FC_PERIPH_WDT,       CG_FC_PERIPH_MLA,   CG_FC_PERIPH_ESG,
+   *   CG_FC_PERIPH_SHA,       CG_FC_PERIPH_AES,   CG_FC_PERIPHB_ALL.
+   * @param  NewState: New state of clock supply setting.
+   *   This parameter can be one of the following values:
+   *   DISABLE or ENABLE
+   * @retval None
+   */
+void CG_SetFcPeriphB(uint32_t Periph, FunctionalState NewState)
+{
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_CG_FC_PERIPHB(Periph));
+    if (NewState == ENABLE) {   /* clear to '0' to enable */
+        TSB_CG->FSYSMSKB &= ~Periph;
+    } else {                    /* write '1' to disable   */
+        TSB_CG->FSYSMSKB |= Periph;
+    }
+}
+
+/**
+  * @brief  Enable or disable low-speed oscillator (fs) for RTC
+  * @param  NewState: oscillator is enabled or disabled
+  *   This parameter can be one of the following values:
+  *   DISABLE or ENABLE
+  * @retval None
+  */
+void CG_SetFs(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Enable low-speed oscillator */
+        TSB_CG->OSCCR |= CG_OSCCR_XTEN_SET;
+        TSB_CG->OSCCR |= CG_OSCCR_DRVOSCL_SET;
+    } else {
+        /* Disable low-speed oscillator */
+        TSB_CG->OSCCR &= CG_OSCCR_XTEN_CLEAR;
+        TSB_CG->OSCCR &= CG_OSCCR_DRVOSCL_CLEAR;
+    }
+}
+
+/** @} */
+/* End of group CG_Exported_Functions */
+
+/** @} */
+/* End of group CG */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#endif                          /* defined(__TMPM46B_CG_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_esg.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,308 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46B_esg.c
+ * @brief   This file provides API functions for ESG driver.
+ * @version V2.0.2.2
+ * @date    2018/03/15
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *******************************************************************************
+ */
+ 
+ /* Includes ------------------------------------------------------------------ */
+#include "tmpm46b_esg.h"
+
+#if defined(__TMPM46B_ESG_H)
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @defgroup ESG 
+  * @brief ESG driver modules
+  * @{
+  */
+/** @defgroup ESG_Private_Defines
+  * @{
+  */
+#define ESG_START_SET                 (0x00000001U)
+#define ESG_FINTIMING_CLEAR           (0xFFFF0000U)
+#define ESG_FINTIMING_SET             (0x0000FFFFU)
+#define ESG_LATCHTIMING_SET           (0x000F0000U)
+#define ESG_LATCHTIMING_CLEAR         (0xFFF0FFFFU)
+#define ESG_BUSY_SET                  (0x00000001U)
+#define ESG_INT_SET                   (0x00000001U)
+#define SRST_IPRST_3_SET              (0x00000008U)
+#define SRST_IPRST_3_CLEAR            (0xFFFFFFF7U)
+#define SRST_PROTECT_DISABLE          (0x0000006BU)
+#define SRST_PROTECT_ENABLE           (0x00000000U)
+#define NUM_BLK                       (16U)
+
+static const volatile uint32_t *const ESG_Blk[NUM_BLK] = {
+    &TSB_ESG->BLK00, &TSB_ESG->BLK01, &TSB_ESG->BLK02, &TSB_ESG->BLK03,
+    &TSB_ESG->BLK04, &TSB_ESG->BLK05, &TSB_ESG->BLK06, &TSB_ESG->BLK07,
+    &TSB_ESG->BLK08, &TSB_ESG->BLK09, &TSB_ESG->BLK10, &TSB_ESG->BLK11,
+    &TSB_ESG->BLK12, &TSB_ESG->BLK13, &TSB_ESG->BLK14, &TSB_ESG->BLK15
+};
+
+/** @} */
+/* End of group ESG_Private_Defines */
+
+/** @defgroup ESG_Private_FunctionPrototypes
+    * @{
+    */
+
+/** @} */
+/* End of group ESG_Private_FunctionPrototypes */
+
+/** @defgroup ESG_Private_Functions
+    * @{
+    */
+
+/** @} */
+/* End of group ESG_Private_Functions */
+
+/** @defgroup ESG_Exported_Functions
+  * @{
+  */
+
+/** 
+  * @brief  Start-up ESG operation.
+  * @param  None
+  * @retval The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  * @register The used registers:
+  *   ESGCR<START> 
+  */
+Result ESG_Startup(void)
+{
+    Result retval = ERROR;
+
+    if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
+        /* Write '1' to ESGCR<START> to enable  */
+        TSB_ESG->CR = ESG_START_SET;
+        retval = SUCCESS;
+    } else {
+        /* Do nothing */
+    }
+
+    return retval;
+}
+
+/** 
+  * @brief  Set entropy seed latch timing.
+  * @param  Value: The latch timing for ESG
+  *   This parameter can be one of the following values:  
+  *   ESG_LATCH_TIMING_1, ESG_LATCH_TIMING_2, ESG_LATCH_TIMING_3,
+  *   ESG_LATCH_TIMING_4, ESG_LATCH_TIMING_5, ESG_LATCH_TIMING_6,
+  *   ESG_LATCH_TIMING_7, ESG_LATCH_TIMING_8, ESG_LATCH_TIMING_9,
+  *   ESG_LATCH_TIMING_10, ESG_LATCH_TIMING_11, ESG_LATCH_TIMING_12,
+  *   ESG_LATCH_TIMING_13, ESG_LATCH_TIMING_14, ESG_LATCH_TIMING_15,
+  *   ESG_LATCH_TIMING_16.
+  * @retval The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  * @register The used registers:
+  *   ESGOUTCR<LATCHTIMING[19:16]> 
+  */
+Result ESG_SetLatchTiming(ESG_LatchTiming Value)
+{
+    /*  Read OUTCR, keep bit 15 to 0, clear bit 19 to 16 */
+    uint32_t tmp = TSB_ESG->OUTCR & ESG_LATCHTIMING_CLEAR;
+    Result retval = ERROR;
+
+    /* Check the parameters */
+    assert_param(IS_ESG_LATCH_TIMING(Value));
+
+    if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
+        tmp |= (uint32_t) Value << 16;
+        TSB_ESG->OUTCR = tmp;
+        retval = SUCCESS;
+    } else {
+        /* Do nothing */
+    }
+
+    return retval;
+}
+
+/** 
+  * @brief  Get entropy seed latch timing.
+  * @param  None
+  * @retval tmp: the value of entropy seed latch timing
+  * @register The used registers:
+  *   ESGOUTCR<LATCHTIMING[19:16]> 
+  */
+uint32_t ESG_GetLatchTiming(void)
+{
+    uint32_t tmp;
+
+    tmp = (TSB_ESG->OUTCR & ESG_LATCHTIMING_SET) >> 16;
+
+    return tmp;
+}
+
+/** 
+  * @brief  Set Entropy seed output timing.
+  * @param  Fintming: the value of entropy seed output timing
+  * @retval The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  * @register The used registers:
+  *   ESGOUTCR<FINTIMING[15:0]> 
+  */
+Result ESG_SetFintiming(uint16_t Fintming)
+{
+    /* Read OUTCR, keep bit 19 to 16, clear bit 15 to 0 */
+    uint32_t tmp = TSB_ESG->OUTCR & ESG_FINTIMING_CLEAR;
+    Result retval = ERROR;
+
+    /* Get latchtiming value */
+    uint16_t latchtiming = (uint16_t) ESG_GetLatchTiming();
+
+    if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
+        if (Fintming >= 512U * (latchtiming + 1U) + 3U) {
+            tmp |= (uint32_t) Fintming;
+            TSB_ESG->OUTCR = tmp;
+            retval = SUCCESS;
+        } else {
+            /* Do nothing */
+        }
+    } else {
+        /* Do nothing */
+    }
+
+    return retval;
+}
+
+/** 
+  * @brief  Get entropy seed  Fintiming.
+  * @param  None
+  * @retval tmp: the value of entropy seed Fintiming
+  * @register The used registers:
+  *   ESGOUTCR<FINTIMING[15:0]> 
+  */
+uint16_t ESG_GetFintiming(void)
+{
+    uint16_t tmp;
+
+    tmp = (uint16_t) TSB_ESG->OUTCR & ESG_FINTIMING_SET;
+
+    return tmp;
+}
+
+/** 
+  * @brief  Clear the ESG interrupt.
+  * @param  None
+  * @retval The value returned can be one of the following values:
+  *   SUCCESS or ERROR
+  * @register The used registers:
+  *   ESGINT<INT> 
+  */
+Result ESG_ClrInt(void)
+{
+    Result retval = ERROR;
+
+    if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
+        /* Write '1' to ESGINT<INT> to clear the interrupt */
+        TSB_ESG->INT = ESG_INT_SET;
+        retval = SUCCESS;
+    } else {
+        /* Do nothing */
+    }
+
+    return retval;
+}
+
+/** 
+  * @brief  Get the ESG interrupt status.
+  * @param  None
+  * @retval The value returned can be one of the following values:
+  *   ENABLE: interrupt occurs 
+  *   DISABLE: no interrupt
+  * @register The used registers:
+  *   ESGINT<INT> 
+  */
+FunctionalState ESG_GetIntStatus(void)
+{
+    FunctionalState retval = DISABLE;
+
+    if (TSB_ESG->INT == ESG_INT_SET) {
+        retval = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Reset ESG by peripheral function.
+  * @param  None
+  * @retval None
+  * @register The used register:
+  *   SRSTIPRST<IPRST3>
+  *   SRSTPROTECT
+  */
+void ESG_IPReset(void)
+{
+    uint32_t iprst3 = 0U;
+
+    /* Disable write protection state of SRSTIPRST */
+    TSB_SRST->PROTECT = SRST_PROTECT_DISABLE;
+
+    TSB_SRST->IPRST |= SRST_IPRST_3_SET;
+
+    /* Release reset state */
+    TSB_SRST->IPRST &= SRST_IPRST_3_CLEAR;
+
+    /* Enable write protection state of SRSTIPRST */
+    TSB_SRST->PROTECT = SRST_PROTECT_ENABLE;
+}
+
+/**
+  * @brief  Get the calculation status.
+  * @param  None
+  * @retval The calculation status.
+  *   The value returned can be one of the following values:
+  *   ESG_CALCULATION_COMPLETE, ESG_CALCULATION_PROCESS.
+  * @note  Do not write any value to ESG registers when calculation is in process.
+  * @register The used register:
+  *   ESGST<BUSY>
+  */
+ESG_CalculationStatus ESG_GetCalculationStatus(void)
+{
+    ESG_CalculationStatus retval = ESG_CALCULATION_COMPLETE;
+
+    if (TSB_ESG->ST == ESG_BUSY_SET) {
+        retval = ESG_CALCULATION_PROCESS;
+    } else {
+        /* Do nothing */
+    }
+
+    return retval;
+}
+
+/** 
+  * @brief  Get the calculation result.
+  * @param  Seed[16U]: A point that points to the value of calculation result.
+  * @retval None  
+  * @register The used registers:
+  *   ESGBLK00 to ESGBLK15
+  */
+void ESG_GetResult(uint32_t Seed[NUM_BLK])
+{
+    uint32_t i = 0U;
+
+    for (i = 0U; i < NUM_BLK; i++) {
+        Seed[i] = *ESG_Blk[i];
+    }
+}
+
+/** @} */
+/* End of group ESG_Exported_Functions */
+
+/** @} */
+/* End of group ESG */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+#endif                          /* defined(__TMPM46B_ESG_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_fc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,1129 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_fc.c
+ * @brief   This file provides API functions for FC driver.
+ * @version V2.0.2.1
+ * @date    2015/02/27
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm46b_fc.h"
+
+#if defined(__TMPM46B_FC_H)
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @defgroup FC 
+  * @brief FC driver modules
+  * @{
+  */
+
+/** @defgroup FC_Private_Defines
+  * @{
+  */
+
+#define BASE_ADDR_H                         ((uint32_t)0x00080000)
+
+#define SECBIT_SECBIT_PASSWORD              ((uint32_t)0xA74A9D23)
+#define SECBIT_SECBIT_SET                   ((uint32_t)0x00000001)
+#define SECBIT_SECBIT_CLEAR                 ((uint32_t)0xFFFFFFFE)
+
+#define SECBIT_SECURITY_MASK                ((uint32_t)0x00000001)
+#define SECBIT_DISABLE_FLAG                 ((uint32_t)0x00000000)
+
+#define FLCS_BUSY_MASK                      ((uint32_t)0x00000001)
+#define FLCS_BUSY_FLAG                      ((uint32_t)0x00000000)
+
+#define FC_PROTECT_MASK                     ((uint32_t)0x00000001)
+
+#define FC_BLOCK_FLAG                       ((uint32_t)0x00000000)
+
+#define FC_PAGE_FLAG                        ((uint32_t)0x00000000)
+
+#define FC_ABORT_MASK                       ((uint32_t)0x01000000)
+#define FC_ABORT_FLAG                       ((uint32_t)0x00000000)
+
+#define FC_SWAP_SIZE_MASK                   ((uint32_t)0x00000700)
+
+#define FC_SWAP_STATE_MASK                  ((uint32_t)0x00000003)
+
+#define FC_SWAP_BIT_VALUE_MASK              ((uint32_t)0x00000001)
+
+#define FC_AREA_CLEAR                       ((uint32_t)0x00000000)
+#define FC_AREA_0_SET                       ((uint32_t)0x00000007)
+#define FC_AREA_1_SET                       ((uint32_t)0x00000070)
+#define FC_AREA_ALL_SET                     ((uint32_t)0x00000077)
+
+#define FC_CR_ABORT_SET                     ((uint32_t)0x00000007)
+#define FC_STSCLR_ABORT_CLEAR               ((uint32_t)0x00000007)
+
+#define FLASH_AREA                          ((uint32_t)(FLASH_START_ADDR & 0xFFF00000U))
+
+#define FC_CMD_BC1_ADDR                     ((uint32_t)(0x5E005400))
+#define FC_CMD_BC2_ADDR                     ((uint32_t)(0x5E00AA00))
+#define FC_CMD_BC3_ADDR                     ((uint32_t)(0x5E000000))
+
+#define FC_CMD_BC1_ADDR_H                   ((uint32_t)(FC_CMD_BC1_ADDR + BASE_ADDR_H))
+#define FC_CMD_BC2_ADDR_H                   ((uint32_t)(FC_CMD_BC2_ADDR + BASE_ADDR_H))
+
+#define FC_ERASE_CHIP_OVER_TIME             ((uint32_t)0x005FFFFF)      /* FC_ERASE_CHIP_OVER_TIME > 345ms */
+
+#define FC_ERASE_BLOCK_OVER_TIME            ((uint32_t)0x00CFFFFF)      /* FC_ERASE_BLOCK_OVER_TIME > 920ms */
+#define FC_ERASE_PAGE_OVER_TIME             ((uint32_t)0x0016FFFF)      /* FC_ERASE_PAGE_OVER_TIME > 115ms */
+#define FC_ERASE_AREA_OVER_TIME             ((uint32_t)0x0016FFFF)
+#define FC_WRITE_PAGE_OVER_TIME             ((uint32_t)0x0007FFFF)      /* FC_WRITE_PAGE_OVER_TIME > 30.7ms */
+#define FC_SET_PROTECT_STATE_OVER_TIME      ((uint32_t)0x000FFFFF)
+#define FC_SWAP_SET_OVER_TIME               ((uint32_t)0x0016FFFF)      /* FC_SWAP_SET_OVER_TIME > 115ms */
+
+
+#define FC_PBA_ADDR_SHIFT                   4U  /*PBA address shift 4 Bits */
+
+#define FC_SWPSR_BIT_START                  ((uint32_t)0x5E000880)
+
+#define FC_PSR0_MASK                        ((uint32_t)0xFFFFFF00)
+#define FC_PSR1_PSR2_MASK                   ((uint32_t)0xFFFF0000)
+
+#define FC_BLOCK_ADDR_MASK                  ((uint32_t)0x001FE000)
+#define FC_PAGE_ADDR_MASK                   ((uint32_t)0x001FF000)
+
+#define FC_AREA_1_START_ADDR                ((uint32_t)(FLASH_AREA + 0x00080000UL))
+#define FC_PAGE_SIZE                        ((uint32_t)(FLASH_PAGE_SIZE/4U))
+
+typedef struct {
+    uint32_t Start_Addr;
+    uint32_t End_Addr;
+} Block_AddrDef;
+
+Block_AddrDef block_addr[] = {
+    {0U, 8U}, {8U, 16U}, {16U, 24U}, {24U, 32U}, {32U, 40U},
+    {40U, 48U}, {48U, 56U}, {56U, 64U}, {64U, 72U}, {72U, 80U},
+    {80U, 88U}, {88U, 96U}, {96U, 104U}, {104U, 112U}, {112U, 120U},
+    {120U, 128U}, {128U, 136U}, {136U, 144U}, {144U, 152U}, {152U, 160U},
+    {160U, 168U}, {168U, 176U}, {176U, 184U}, {184U, 192U}, {192U, 200U},
+    {200U, 208U}, {208U, 216U}, {216U, 224U}, {224U, 232U}, {232U, 240U},
+    {240U, 248U}, {248U, 256U},
+};
+
+/** @} */
+/* End of group FC_Private_Defines */
+
+/** @defgroup FC_Private_FunctionPrototypes
+  * @{
+  */
+static uint8_t FC_AddrToBlockNum(uint32_t Addr);
+static void FC_SetAreaSelection(uint8_t BlockNum);
+static void FC_ClearAreaSelection(uint8_t BlockNum);
+/** @} */
+/* End of group FC_Private_FunctionPrototypes */
+
+/** @defgroup FC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Convert address to block number.
+  * @param  Addr
+  * @retval BlockNum
+   */
+#if defined ( __GNUC__ )    /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+static uint8_t FC_AddrToBlockNum(uint32_t Addr)
+{
+    uint8_t BlockNum = 0U;
+    uint8_t i = 0U;
+    uint32_t temp = (Addr - FLASH_START_ADDR) / FLASH_PAGE_SIZE;
+
+    for (i = 0U; i <= FC_BLOCK_MAX; ++i) {
+        if ((temp >= block_addr[i].Start_Addr) && (temp < block_addr[i].End_Addr)) {
+            BlockNum = i;
+            break;
+        }
+    }
+
+    return BlockNum;
+}
+
+/**
+  * @brief  Set an area selection bit according to block number.
+  * @param  BlockNum
+  * @retval None
+   */
+#if defined ( __GNUC__ )    /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+static void FC_SetAreaSelection(uint8_t BlockNum)
+{
+    uint32_t tmp = 0U;
+    tmp = TSB_FC->AREASEL;
+    if (BlockNum <= 15U) {
+        tmp |= FC_AREA_0_SET;
+    } else if (BlockNum <= 31U) {
+        tmp |= FC_AREA_1_SET;
+    } else {
+        /* Do nothing */
+    }
+    TSB_FC->AREASEL = tmp;
+    while (TSB_FC->AREASEL != tmp) {
+        /* Do nothing */
+    }
+}
+
+/**
+  * @brief  Clear an area selection bit according to block number.
+  * @param  BlockNum
+  * @retval None
+   */
+#if defined ( __GNUC__ )    /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+static void FC_ClearAreaSelection(uint8_t BlockNum)
+{
+    uint32_t tmp = 0U;
+    tmp = TSB_FC->AREASEL;
+    if (BlockNum <= 15U) {
+        tmp &= ~FC_AREA_0_SET;
+    } else if (BlockNum <= 31U) {
+        tmp &= ~FC_AREA_1_SET;
+    } else {
+        /* Do nothing */
+    }
+    TSB_FC->AREASEL = tmp;
+    while (TSB_FC->AREASEL != tmp) {
+        /* Do nothing */
+    }
+}
+
+/** @} */
+/* End of group FC_Private_Functions */
+
+/** @defgroup FC_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the value of SECBIT register.
+  * @param  NewState: The value of SECBIT register.
+  *   This parameter can be one of the following values:
+  *   DISABLE or ENABLE.
+  * @retval None.
+  * @register The used register:
+  *   FCSECBIT <SECBIT>
+  */
+void FC_SetSecurityBit(FunctionalState NewState)
+{
+    uint32_t tmp = TSB_FC->SECBIT;
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set FCSECBIT<SECBIT> to "1" that enable security function  */
+        tmp |= SECBIT_SECBIT_SET;
+    } else {
+        /* Set FCSECBIT<SECBIT> to "0" that disable security function  */
+        tmp &= SECBIT_SECBIT_CLEAR;
+    }
+    TSB_FC->SECBIT = SECBIT_SECBIT_PASSWORD;
+    TSB_FC->SECBIT = tmp;
+}
+
+/**
+  * @brief  Get the value of SECBIT register.
+  * @param  None.
+  * @retval DISABLE or ENABLE.
+  * @register The used register:
+  *   FCSECBIT <SECBIT>
+  */
+FunctionalState FC_GetSecurityBit(void)
+{
+    uint32_t tmp = 0U;
+    FunctionalState retval = ENABLE;
+
+    tmp = TSB_FC->SECBIT & SECBIT_SECURITY_MASK;
+
+    /* Check disable flag */
+    if (tmp == SECBIT_DISABLE_FLAG) {
+        retval = DISABLE;
+    } else {                    /* Check enable flag */
+        retval = ENABLE;
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Get the status of the flash auto operation.
+  * @param  None.
+  * @retval BUSY or DONE.
+  * @register The used register:
+  *   FCPSR0<RDY_BSY>
+  */
+#if defined ( __GNUC__ )    /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+WorkState FC_GetBusyState(void)
+{
+    uint32_t tmp = 0U;
+    WorkState retval = DONE;
+
+    tmp = TSB_FC->PSR0 & FLCS_BUSY_MASK;
+
+    /* Check busy flag */
+    if (tmp == FLCS_BUSY_FLAG) {
+        retval = BUSY;
+    } else {                    /* Check ready flag */
+        retval = DONE;
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Get the specified block protection state.
+  * @param  BlockNum: The flash block number.
+  *   This parameter can be one of the following values:
+  *   FC_BLOCK_1 to FC_BLOCK_31
+  * @retval DISABLE or ENABLE.
+  * @register The used registers:
+  *   FCPSR0<31:17>
+  *   FCPSR1<31:16>
+  *   FCPSR2<31:16>
+  */
+#if defined ( __GNUC__ )    /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+FunctionalState FC_GetBlockProtectState(uint8_t BlockNum)
+{
+    uint32_t tmp = FC_PROTECT_MASK;
+    FunctionalState retval = ENABLE;
+
+    /* Check the parameters */
+    assert_param(IS_FC_BLOCK_NUM(BlockNum));
+    if (BlockNum <= FC_BLOCK_15) {
+        tmp = tmp << ((uint32_t) BlockNum + 16U);
+        tmp &= TSB_FC->PSR0;
+    } else {
+        tmp = tmp << BlockNum;
+        tmp &= TSB_FC->PSR1;
+    }
+    if (tmp == FC_BLOCK_FLAG) {
+        /* Return protection status of each block */
+        retval = DISABLE;
+    } else {
+        retval = ENABLE;
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Get the specified page protection state.
+  * @param  PageNum: The flash page number.
+  *   This parameter can be one of the following values:
+  *   FC_PAGE_0 to FC_PAGE_7
+  * @retval DISABLE or ENABLE.
+  * @register The used register:
+  *   FCPSR0<15:8>
+  */
+#if defined ( __GNUC__ )    /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+FunctionalState FC_GetPageProtectState(uint8_t PageNum)
+{
+    uint32_t tmp = FC_PROTECT_MASK;
+    FunctionalState retval = ENABLE;
+
+    /* Check the parameters */
+    assert_param(IS_FC_PAGE_NUM(PageNum));
+    tmp = tmp << ((uint32_t) PageNum + 8U);
+    tmp &= TSB_FC->PSR0;
+
+    if (tmp == FC_PAGE_FLAG) {
+        /* Return protection status of each block */
+        retval = DISABLE;
+    } else {
+        retval = ENABLE;
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Get the status of the auto operation is aborted or not.
+  * @param  None.
+  * @retval DISABLE or ENABLE.
+  *   DISABLE: Aborted is disable.
+  *   ENABLE: Aborted is enable.
+  * @register The used register:
+  *   FCSR<WEABORT>
+  */
+FunctionalState FC_GetAbortState(void)
+{
+    uint32_t tmp = 0U;
+    FunctionalState retval = DISABLE;
+
+    tmp = TSB_FC->SR & FC_ABORT_MASK;
+
+    /* Check  flag */
+    if (tmp == FC_ABORT_FLAG) {
+        retval = DISABLE;
+    } else {                    /* Check flag */
+        retval = ENABLE;
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Get the swap size.
+  * @param  None.
+  * @retval the swap size.
+  *   The value returned can be one of the following values:
+  *   FC_SWAP_SIZE_4K, FC_SWAP_SIZE_8K, FC_SWAP_SIZE_16K,
+  *   FC_SWAP_SIZE_32K, FC_SWAP_SIZE_512K
+  * @register The used register:
+  *   FCSWPSR <SIZE[2:0]>
+  */
+uint32_t FC_GetSwapSize(void)
+{
+    uint32_t tmp = 0U;
+
+    tmp = TSB_FC->SWPSR & FC_SWAP_SIZE_MASK;
+    tmp = (tmp >> 8U);
+
+    return tmp;
+}
+
+/**
+  * @brief  Get the swap state.
+  * @param  None.
+  * @retval the swap state.
+  *   The value returned can be one of the following values:
+  *   FC_SWAP_RELEASE, FC_SWAP_PROHIBIT,
+  *   FC_SWAPPING, FC_SWAP_INITIAL.
+  * @register The used register:
+  *   FCSWPSR <SWP[1:0]>
+  */
+uint32_t FC_GetSwapState(void)
+{
+    uint32_t tmp = 0U;
+
+    tmp = TSB_FC->SWPSR & FC_SWAP_STATE_MASK;
+
+    return tmp;
+}
+
+/**
+  * @brief  Specifies an "area" in the Flash memory that is targeted by Flash memory 
+  *  operation command.
+  * @param  AreaNum: the flash area number.
+  *   This parameter can be one of the following values:
+  *   FC_AREA_0, FC_AREA_1, FC_AREA_ALL.
+  * @param  NewState: Specify area state.
+  *   This parameter can be one of the following values:
+  *   ENABLE:Select the area.
+  *   DISABLE:Unselect the area.
+  * @retval None
+  * @register The used register:
+  *   FCAREASEL <AREA0><AREA1>
+  */
+void FC_SelectArea(uint8_t AreaNum, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FC_AREA(AreaNum));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    switch (AreaNum) {
+    case FC_AREA_0:
+        (NewState == ENABLE) ? (TSB_FC->AREASEL |= FC_AREA_0_SET) : (TSB_FC->AREASEL &=
+                                                                     ~FC_AREA_0_SET);
+        break;
+    case FC_AREA_1:
+        (NewState == ENABLE) ? (TSB_FC->AREASEL |= FC_AREA_1_SET) : (TSB_FC->AREASEL &=
+                                                                     ~FC_AREA_1_SET);
+        break;
+    case FC_AREA_ALL:
+        (NewState == ENABLE) ? (TSB_FC->AREASEL |= FC_AREA_ALL_SET) : (TSB_FC->AREASEL &=
+                                                                       ~FC_AREA_ALL_SET);
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+}
+
+/**
+  * @brief  Set abortion of auto operation command
+  * @param  None
+  * @retval None
+  * @register The used register:
+  *   FCCR <WEABORT>
+  */
+void FC_SetAbortion(void)
+{
+    /* Set abortion of auto operation command */
+    TSB_FC->CR |= FC_CR_ABORT_SET;
+}
+
+/**
+  * @brief  Clear FCSR<WEABORT> to "0" command
+  * @param  None
+  * @retval None
+  * @register The used register:
+  *   FCSTSCLR <WEABORT>
+  */
+void FC_ClearAbortion(void)
+{
+    /* Clear FCSR<WEABORT> to "0" command */
+    TSB_FC->STSCLR |= FC_STSCLR_ABORT_CLEAR;
+}
+
+/**
+  * @brief  Set Frequency division ratio to change the clock (WCLK: fsys/(DIV+1))
+  *  in automatic operation to 8 to 12MHz
+  * @param  ClkDiv: the divisor of the system clock.
+  *   the parameter is can be one of the following values:
+  *   FC_Clk_Div_1, FC_Clk_Div_2, FC_Clk_Div_3, FC_Clk_Div_4, 
+  *   FC_Clk_Div_5, FC_Clk_Div_6, FC_Clk_Div_7, FC_Clk_Div_8, 
+  *   FC_Clk_Div_9, FC_Clk_Div_10, FC_Clk_Div_11, FC_Clk_Div_12, 
+  *   FC_Clk_Div_13, FC_Clk_Div_14, FC_Clk_Div_15, FC_Clk_Div_16,
+  *   FC_Clk_Div_17, FC_Clk_Div_18, FC_Clk_Div_19, FC_Clk_Div_20, 
+  *   FC_Clk_Div_21, FC_Clk_Div_22, FC_Clk_Div_23, FC_Clk_Div_24, 
+  *   FC_Clk_Div_25, FC_Clk_Div_26, FC_Clk_Div_27, FC_Clk_Div_28, 
+  *   FC_Clk_Div_29, FC_Clk_Div_30, FC_Clk_Div_31, FC_Clk_Div_32.
+  * @retval None
+  * @register The used register:
+  *   FCWCLKCR <DIV>
+  */
+void FC_SetClkDiv(uint8_t ClkDiv)
+{
+    /* Check the parameters */
+    assert_param(IS_FC_WCLK_DIV(ClkDiv));
+
+    TSB_FC->WCLKCR = (uint32_t) ClkDiv;
+}
+
+/**
+  * @brief  Set the number of counts that makes a programming time (CNT/WCLK) by automatic program
+  *  execution command be within the range of 20 to 40 micro-sec.
+  * @param  ProgramCount: the counter of the divided system clock for flash program
+  *   This parameter can be one of the following values:
+  *   FC_PROG_CNT_250, FC_PROG_CNT_300, FC_PROG_CNT_350.
+  * @retval None
+  * @register The used register:
+  *   FCPROGCR <CNT>
+  */
+void FC_SetProgramCount(uint8_t ProgramCount)
+{
+    /* Check the parameters */
+    assert_param(IS_FC_PROG_CNT(ProgramCount));
+
+    TSB_FC->PROGCR = (uint32_t) ProgramCount;
+}
+
+/**
+  * @brief  Set the number of counts until erase time (CNT/WCLK) will be 100 ~ 130msec 
+  *  using each auto erase command
+  * @param  EraseCounter: the counter of the divided system clock for flash program
+  *   This parameter can be one of the following values:
+  *   FC_ERAS_CNT_85, FC_ERAS_CNT_90, FC_ERAS_CNT_95, FC_ERAS_CNT_100, 
+  *   FC_ERAS_CNT_105, FC_ERAS_CNT_110, FC_ERAS_CNT_115, FC_ERAS_CNT_120, 
+  *   FC_ERAS_CNT_125, FC_ERAS_CNT_130, FC_ERAS_CNT_135, FC_ERAS_CNT_140.
+  * @retval None
+  * @register The used register:
+  *   FCERASECR <CNT>
+  */
+void FC_SetEraseCounter(uint8_t EraseCounter)
+{
+    /* Check the parameters */
+    assert_param(IS_FC_ERASE_CNT(EraseCounter));
+
+    TSB_FC->ERASECR = (uint32_t) EraseCounter;
+}
+
+/**
+  * @brief  Program the protection bit to make the specified block protected.
+  * @param  BlockNum: The flash block number.
+  *   This parameter can be one of the following values:
+  *   FC_BLOCK_1 to FC_BLOCK_31
+  * @retval FC_SUCCESS, FC_ERROR_PROTECTED, FC_ERROR_OVER_TIME.
+  * @register The used registers:
+  *   FCPSR0<31:17>
+  *   FCPSR1<31:16>
+  *   FCPSR2<31:16>
+  */
+FC_Result FC_ProgramBlockProtectState(uint8_t BlockNum)
+{
+    FC_Result retval = FC_SUCCESS;
+    volatile uint32_t *addr1 = (uint32_t *) FC_CMD_BC1_ADDR;
+    volatile uint32_t *addr2 = (uint32_t *) FC_CMD_BC2_ADDR;
+    volatile uint32_t *PBA;
+    uint32_t counter = FC_SET_PROTECT_STATE_OVER_TIME;
+    volatile uint32_t PBA_data;
+
+    /* Check the parameters */
+    assert_param(IS_FC_BLOCK_NUM(BlockNum));
+
+    PBA_data = ((uint32_t) BlockNum + 7U) << FC_PBA_ADDR_SHIFT;
+
+    PBA_data += (uint32_t) 0x5E000000;
+    PBA = (uint32_t *) PBA_data;
+
+    if (ENABLE == FC_GetBlockProtectState(BlockNum)) {
+        retval = FC_ERROR_PROTECTED;
+    } else {
+        TSB_FC->AREASEL |= FC_AREA_ALL_SET;
+        while (TSB_FC->AREASEL != FC_AREA_ALL_SET) {
+            /* Do nothing */
+        }
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 1 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 2 */
+        *addr1 = (uint32_t) 0x0000009A; /* bus cycle 3 */
+        *PBA = (uint32_t) 0x0000009A;   /* bus cycle 4 */
+        __DSB();
+
+        while (BUSY == FC_GetBusyState()) {     /* check if FLASH is busy with overtime counter */
+            if (!(counter--)) { /* check overtime */
+                retval = FC_ERROR_OVER_TIME;
+                break;
+            } else {
+                /* Do nothing */
+            }
+        }
+        TSB_FC->AREASEL &= ~FC_AREA_ALL_SET;
+        while (TSB_FC->AREASEL != FC_AREA_CLEAR) {
+            /* Do nothing */
+        }
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Program the protection bit to make the specified page protected.
+  * @param  PageNum: The flash page number.
+  *   This parameter can be one of the following values:
+  *   FC_PAGE_0 to FC_PAGE_7
+  * @retval FC_SUCCESS, FC_ERROR_PROTECTED, FC_ERROR_OVER_TIME.
+  * @register The used register:
+  *   FCPSR0<15:8>
+  */
+FC_Result FC_ProgramPageProtectState(uint8_t PageNum)
+{
+    FC_Result retval = FC_SUCCESS;
+    volatile uint32_t *addr1 = (uint32_t *) FC_CMD_BC1_ADDR;
+    volatile uint32_t *addr2 = (uint32_t *) FC_CMD_BC2_ADDR;
+    volatile uint32_t *PBA = 0U;
+    uint32_t counter = FC_SET_PROTECT_STATE_OVER_TIME;
+    volatile uint32_t PBA_data;
+
+    /* Check the parameters */
+    assert_param(IS_FC_PAGE_NUM(PageNum));
+
+    PBA_data = (uint32_t) PageNum << FC_PBA_ADDR_SHIFT;
+
+    PBA_data += (uint32_t) 0x5E000000;
+    PBA = (uint32_t *) PBA_data;
+
+    if (ENABLE == FC_GetPageProtectState(PageNum)) {
+        retval = FC_ERROR_PROTECTED;
+    } else {
+        TSB_FC->AREASEL |= FC_AREA_ALL_SET;
+        while (TSB_FC->AREASEL != FC_AREA_ALL_SET) {
+            /* Do nothing */
+        }
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 1 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 2 */
+        *addr1 = (uint32_t) 0x0000009A; /* bus cycle 3 */
+        *PBA = (uint32_t) 0x0000009A;   /* bus cycle 4 */
+        __DSB();
+
+        while (BUSY == FC_GetBusyState()) {     /* check if FLASH is busy with overtime counter */
+            if (!(counter--)) { /* check overtime */
+                retval = FC_ERROR_OVER_TIME;
+                break;
+            } else {
+                /* Do nothing */
+            }
+        }
+        TSB_FC->AREASEL &= ~FC_AREA_ALL_SET;
+        while (TSB_FC->AREASEL != FC_AREA_CLEAR) {
+            /* Do nothing */
+        }
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Erase the protection bits to make the whole flash unprotected.
+  * @param  None   
+  * @retval FC_SUCCESS, FC_ERROR_OVER_TIME.
+  * @register The used registers:
+  *   FCPSR0<15:8><31:17>
+  *   FCPSR1<31:16>
+  */
+FC_Result FC_EraseProtectState(void)
+{
+    FC_Result retval = FC_SUCCESS;
+    volatile uint32_t *addr1 = (uint32_t *) FC_CMD_BC1_ADDR;
+    volatile uint32_t *addr2 = (uint32_t *) FC_CMD_BC2_ADDR;
+    volatile uint32_t *addr3 = (uint32_t *) FC_CMD_BC3_ADDR;
+    uint32_t counter = FC_SET_PROTECT_STATE_OVER_TIME;
+
+    TSB_FC->AREASEL |= FC_AREA_ALL_SET;
+    while (TSB_FC->AREASEL != FC_AREA_ALL_SET) {
+        /* Do nothing */
+    }
+    *addr1 = (uint32_t) 0x000000AA;     /* bus cycle 1 */
+    *addr2 = (uint32_t) 0x00000055;     /* bus cycle 2 */
+    *addr1 = (uint32_t) 0x0000006A;     /* bus cycle 3 */
+    *addr3 = (uint32_t) 0x0000006A;     /* bus cycle 4 */
+    __DSB();
+
+    while (BUSY == FC_GetBusyState()) { /* check if FLASH is busy with overtime counter */
+        if (!(counter--)) {     /* check overtime */
+            retval = FC_ERROR_OVER_TIME;
+            break;
+        } else {
+            /* Do nothing */
+        }
+    }
+    TSB_FC->AREASEL &= ~FC_AREA_ALL_SET;
+    while (TSB_FC->AREASEL != FC_AREA_CLEAR) {
+        /* Do nothing */
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Write data to the specified page.
+  * @param  PageAddr: The page start address.
+  * @param  Data: The pointer to data buffer to be written into the page.
+  *   The data size should be FC_PAGE_SIZE.
+  * @retval FC_SUCCESS, FC_ERROR_PROTECTED, FC_ERROR_OVER_TIME.
+  * @register The used register:
+  *   None
+  */
+#if defined ( __GNUC__ )    /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+FC_Result FC_WritePage(uint32_t PageAddr, uint32_t * Data)
+{
+    uint32_t tmpAddr = 0U;
+    uint32_t i = 0U;
+    uint32_t *source = Data;
+    uint8_t BlockNum = 0U;
+    volatile uint8_t PageNum = 0U;
+    volatile uint32_t *addr1 = (uint32_t *) FC_CMD_BC1_ADDR;
+    volatile uint32_t *addr2 = (uint32_t *) FC_CMD_BC2_ADDR;
+    volatile uint32_t *PA = 0U;
+    uint32_t counter = FC_WRITE_PAGE_OVER_TIME;
+    FC_Result retval = FC_SUCCESS;
+    FunctionalState state1 = DISABLE;
+    FunctionalState state2 = DISABLE;
+
+    BlockNum = FC_AddrToBlockNum(PageAddr);
+
+    tmpAddr = (PageAddr & (uint32_t) 0x00FFFFF8) | (uint32_t) 0x5E000000;
+    PA = (uint32_t *) tmpAddr;
+
+    assert_param(IS_FC_PAGE_ADDR(PageAddr));
+    assert_param(IS_POINTER_NOT_NULL(Data));
+
+    if (BlockNum >= FC_BLOCK_16) {
+        addr1 = (uint32_t *) FC_CMD_BC1_ADDR_H;
+        addr2 = (uint32_t *) FC_CMD_BC2_ADDR_H;
+    } else {
+        /* Do nothing */
+    }
+    if (BlockNum == 0U) {
+        PageNum = (uint8_t) ((PageAddr - FLASH_START_ADDR) / FLASH_PAGE_SIZE);
+        state1 = FC_GetPageProtectState(PageNum);
+    } else {
+        state2 = FC_GetBlockProtectState(BlockNum);
+    }
+    if ((ENABLE == state1) || (ENABLE == state2)) {
+        retval = FC_ERROR_PROTECTED;
+    } else {
+        FC_SetAreaSelection(BlockNum);
+        /* page program */
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 1 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 2 */
+        *addr1 = (uint32_t) 0x000000A0; /* bus cycle 3 */
+        for (i = 0U; i < PROGRAM_UNIT; i++) {
+            *PA = *source;
+            source++;
+        }
+        __DSB();
+
+        while (BUSY == FC_GetBusyState()) {     /* check if FLASH is busy with overtime counter */
+            if (!(counter--)) { /* check overtime */
+                retval = FC_ERROR_OVER_TIME;
+                break;
+            } else {
+                /* Do nothing */
+            }
+        }
+        FC_ClearAreaSelection(BlockNum);
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Erase the contents of the specified block.
+  * @param  BlockAddr: The block start address.
+  * @retval FC_SUCCESS, FC_ERROR_PROTECTED, FC_ERROR_OVER_TIME.
+  * @register The used register:
+  *   None
+  */
+#if defined ( __GNUC__ )    /* GCC Compiler */
+__attribute__((section(".ram_func")))
+#endif
+FC_Result FC_EraseBlock(uint32_t BlockAddr)
+{
+    FC_Result retval = FC_SUCCESS;
+    volatile uint32_t *addr1 = (uint32_t *) FC_CMD_BC1_ADDR;
+    volatile uint32_t *addr2 = (uint32_t *) FC_CMD_BC2_ADDR;
+    volatile uint32_t *BA = 0U;
+    uint32_t counter = FC_ERASE_BLOCK_OVER_TIME;
+    uint8_t BlockNum = 0U;
+    FunctionalState state1 = DISABLE;
+
+    BlockNum = FC_AddrToBlockNum(BlockAddr);
+
+    assert_param(IS_FC_ADDR(BlockAddr));
+
+    if (BlockNum >= FC_BLOCK_16) {
+        addr1 = (uint32_t *) FC_CMD_BC1_ADDR_H;
+        addr2 = (uint32_t *) FC_CMD_BC2_ADDR_H;
+    } else {
+        /* Do nothing */
+    }
+    BlockAddr &= FC_BLOCK_ADDR_MASK;
+    BlockAddr |= (uint32_t) 0x5E000000;
+
+    BA = (uint32_t *) BlockAddr;
+    if (BlockNum >= FC_BLOCK_1) {
+        state1 = FC_GetBlockProtectState(BlockNum);
+    } else {
+        state1 = FC_GetPageProtectState(FC_PAGE_0);
+        state1 |= FC_GetPageProtectState(FC_PAGE_1);
+        state1 |= FC_GetPageProtectState(FC_PAGE_2);
+        state1 |= FC_GetPageProtectState(FC_PAGE_3);
+        state1 |= FC_GetPageProtectState(FC_PAGE_4);
+        state1 |= FC_GetPageProtectState(FC_PAGE_5);
+        state1 |= FC_GetPageProtectState(FC_PAGE_6);
+        state1 |= FC_GetPageProtectState(FC_PAGE_7);
+    }
+    if (ENABLE == state1) {
+        retval = FC_ERROR_PROTECTED;
+    } else {
+        FC_SetAreaSelection(BlockNum);
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 1 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 2 */
+        *addr1 = (uint32_t) 0x00000080; /* bus cycle 3 */
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 4 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 5 */
+        *BA = (uint32_t) 0x00000030;    /* bus cycle 6 */
+        __DSB();
+
+        while (BUSY == FC_GetBusyState()) {     /* check if FLASH is busy with overtime counter */
+            if (!(counter--)) { /* check overtime */
+                retval = FC_ERROR_OVER_TIME;
+                break;
+            } else {
+                /* Do nothing */
+            }
+        }
+        FC_ClearAreaSelection(BlockNum);
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Erase the contents of the specified area.
+  * @param  AreaAddr: The area start address.
+  * @retval FC_SUCCESS, FC_ERROR_PROTECTED, FC_ERROR_OVER_TIME.
+  * @register The used register:
+  *   None
+  */
+FC_Result FC_EraseArea(uint32_t AreaAddr)
+{
+    FC_Result retval = FC_SUCCESS;
+    volatile uint32_t *addr1 = (uint32_t *) FC_CMD_BC1_ADDR;
+    volatile uint32_t *addr2 = (uint32_t *) FC_CMD_BC2_ADDR;
+    volatile uint32_t *AA = 0U;
+    uint32_t tmp = 0U;
+    uint8_t BlockNum = 0U;
+    uint32_t counter = FC_ERASE_AREA_OVER_TIME;
+    BlockNum = FC_AddrToBlockNum(AreaAddr);
+
+    assert_param(IS_FC_ADDR(AreaAddr)); /* Check whether it is in the flash address range */
+
+    if (BlockNum >= FC_BLOCK_16) {
+        addr1 = (uint32_t *) FC_CMD_BC1_ADDR_H;
+        addr2 = (uint32_t *) FC_CMD_BC2_ADDR_H;
+    } else {
+        /* Do nothing */
+    }
+
+    if (BlockNum < FC_BLOCK_16) {
+        AA = (uint32_t *) 0x5E000000;
+        tmp = TSB_FC->PSR0;
+        tmp &= FC_PSR0_MASK;
+    } else {
+        AA = (uint32_t *) (FC_AREA_1_START_ADDR | (uint32_t) 0x5E000000);
+        tmp = TSB_FC->PSR1;
+        tmp &= FC_PSR1_PSR2_MASK;
+    }
+
+    if (tmp) {
+        retval = FC_ERROR_PROTECTED;
+    } else {
+        FC_SetAreaSelection(BlockNum);
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 1 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 2 */
+        *addr1 = (uint32_t) 0x00000080; /* bus cycle 3 */
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 4 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 5 */
+        *AA = (uint32_t) 0x00000020;    /* bus cycle 6 */
+        __DSB();
+
+        while (BUSY == FC_GetBusyState()) {     /* check if FLASH is busy with overtime counter */
+            if (!(counter--)) { /* check overtime */
+                retval = FC_ERROR_OVER_TIME;
+                break;
+            } else {
+                /* Do nothing */
+            }
+        }
+        FC_ClearAreaSelection(BlockNum);
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Erase the contents of the specified page.
+  * @param  PageAddr: The page start address.
+  * @retval FC_SUCCESS, FC_ERROR_PROTECTED, FC_ERROR_OVER_TIME.
+  * @register The used register:
+  *   None
+  */
+FC_Result FC_ErasePage(uint32_t PageAddr)
+{
+    FC_Result retval = FC_SUCCESS;
+    volatile uint32_t *addr1 = (uint32_t *) FC_CMD_BC1_ADDR;
+    volatile uint32_t *addr2 = (uint32_t *) FC_CMD_BC2_ADDR;
+    volatile uint32_t *PGA = 0U;
+    uint32_t counter = FC_ERASE_PAGE_OVER_TIME;
+    uint8_t BlockNum = 0U;
+    uint8_t PageNum = 0U;
+    FunctionalState state1 = DISABLE;
+    FunctionalState state2 = DISABLE;
+    BlockNum = FC_AddrToBlockNum(PageAddr);
+
+    assert_param(IS_FC_PAGE_ADDR(PageAddr));
+
+    if (BlockNum >= FC_BLOCK_16) {
+        addr1 = (uint32_t *) FC_CMD_BC1_ADDR_H;
+        addr2 = (uint32_t *) FC_CMD_BC2_ADDR_H;
+    } else {
+        /* Do nothing */
+    }
+
+    PageAddr &= FC_PAGE_ADDR_MASK;
+    PageAddr |= (uint32_t) 0x5E000000;
+
+    PGA = (uint32_t *) PageAddr;
+    PageNum = (uint8_t) ((PageAddr - FLASH_START_ADDR) / FLASH_PAGE_SIZE);
+    if (BlockNum == 0U) {
+        state1 = FC_GetPageProtectState(PageNum);
+    } else {
+        state2 = FC_GetBlockProtectState(BlockNum);
+    }
+    if ((ENABLE == state1) || (ENABLE == state2)) {
+        retval = FC_ERROR_PROTECTED;
+    } else {
+        FC_SetAreaSelection(BlockNum);
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 1 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 2 */
+        *addr1 = (uint32_t) 0x00000080; /* bus cycle 3 */
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 4 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 5 */
+        *PGA = (uint32_t) 0x00000040;   /* bus cycle 6 */
+        __DSB();
+
+        while (BUSY == FC_GetBusyState()) {     /* check if FLASH is busy with overtime counter */
+            if (!(counter--)) { /* check overtime */
+                retval = FC_ERROR_OVER_TIME;
+                break;
+            } else {
+                /* Do nothing */
+            }
+        }
+        FC_ClearAreaSelection(BlockNum);
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Erase the contents of the entire chip.
+  * @param  None.
+  * @retval FC_SUCCESS, FC_ERROR_PROTECTED, FC_ERROR_OVER_TIME.
+  * @register The used register:
+  *   None
+  */
+FC_Result FC_EraseChip(void)
+{
+    FC_Result retval = FC_SUCCESS;
+    volatile uint32_t *addr1 = (uint32_t *) FC_CMD_BC1_ADDR;
+    volatile uint32_t *addr2 = (uint32_t *) FC_CMD_BC2_ADDR;
+    uint32_t counter = FC_ERASE_CHIP_OVER_TIME;
+    FunctionalState result;
+    uint8_t PageNum = FC_PAGE_0;
+    uint8_t BlockNum = FC_BLOCK_1;
+    for (PageNum = FC_PAGE_0; PageNum <= FC_PAGE_MAX; ++PageNum) {
+        result = FC_GetPageProtectState(PageNum);
+        if (result == ENABLE) {
+            break;
+        } else {
+            /* Do nothing */
+        }
+    }
+
+    for (BlockNum = FC_BLOCK_1; BlockNum <= FC_BLOCK_MAX; ++BlockNum) {
+        if (result == ENABLE) {
+            break;
+        } else {
+            result = FC_GetBlockProtectState(BlockNum);
+        }
+    }
+
+    if (ENABLE == result) {
+        retval = FC_ERROR_PROTECTED;
+    } else {
+        TSB_FC->AREASEL |= FC_AREA_ALL_SET;
+        while (TSB_FC->AREASEL != FC_AREA_ALL_SET) {
+            /* Do nothing */
+        }
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 1 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 2 */
+        *addr1 = (uint32_t) 0x00000080; /* bus cycle 3 */
+        *addr1 = (uint32_t) 0x000000AA; /* bus cycle 4 */
+        *addr2 = (uint32_t) 0x00000055; /* bus cycle 5 */
+        *addr1 = (uint32_t) 0x00000010; /* bus cycle 6 */
+        __DSB();
+
+        while (BUSY == FC_GetBusyState()) {     /* check if FLASH is busy with overtime counter */
+            if (!(counter--)) { /* check overtime */
+                retval = FC_ERROR_OVER_TIME;
+                break;
+            } else {
+                /* Do nothing */
+            }
+        }
+        TSB_FC->AREASEL &= ~FC_AREA_ALL_SET;
+        while (TSB_FC->AREASEL != FC_AREA_CLEAR) {
+            /* Do nothing */
+        }
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Setting values of FCSWPSR[10:0] by memory swap command.
+  * @param  BitNum: The FCSWPSR bit number to be set.
+  *   This parameter can be one of the following values:
+  *   FC_SWPSR_BIT_0 to FC_SWPSR_BIT_10
+  * @retval FC_SUCCESS, FC_ERROR_OVER_TIME.
+  * @register The used register:
+  *   FCSWPSR<SIZE><FLG><SWP>
+  */
+FC_Result FC_SetSwpsrBit(uint8_t BitNum)
+{
+    FC_Result retval = FC_SUCCESS;
+    uint32_t counter = FC_SWAP_SET_OVER_TIME;
+    volatile uint32_t *addr1 = (uint32_t *) FC_CMD_BC1_ADDR;
+    volatile uint32_t *addr2 = (uint32_t *) FC_CMD_BC2_ADDR;
+    volatile uint32_t *MSA = 0U;
+    uint32_t MSA_data;
+
+    /* Check the parameters */
+    assert_param(IS_FC_SWPSR_BIT_NUM(BitNum));
+
+    MSA_data = (uint32_t) BitNum << FC_PBA_ADDR_SHIFT;
+    MSA_data += FC_SWPSR_BIT_START;
+    MSA = (uint32_t *) MSA_data;
+
+    TSB_FC->AREASEL |= FC_AREA_ALL_SET;
+    while (TSB_FC->AREASEL != FC_AREA_ALL_SET) {
+        /* Do nothing */
+    }
+    *addr1 = (uint32_t) 0x000000AA;     /* bus cycle 1 */
+    *addr2 = (uint32_t) 0x00000055;     /* bus cycle 2 */
+    *addr1 = (uint32_t) 0x0000009A;     /* bus cycle 3 */
+    *MSA = (uint32_t) 0x0000009A;       /* bus cycle 4 */
+    __DSB();
+    while (BUSY == FC_GetBusyState()) { /* check if FLASH is busy with overtime counter */
+        if (!(counter--)) {     /* check overtime */
+            retval = FC_ERROR_OVER_TIME;
+            break;
+        } else {
+            /* Do nothing */
+        }
+    }
+    TSB_FC->AREASEL &= ~FC_AREA_ALL_SET;
+    while (TSB_FC->AREASEL != FC_AREA_CLEAR) {
+        /* Do nothing */
+    }
+
+    return retval;
+}
+
+/**
+* @brief  Get the value of the special bit of FCSWPSR[10:0].
+  * @param  BitNum: The special bit of SWPSR.
+  *   This parameter can be one of the following values:
+  *   FC_SWPSR_BIT_0 to FC_SWPSR_BIT_10.
+  * @retval The value of the special bit.
+  *   The value returned can be one of the following values:
+  *   FC_BIT_VALUE_0, FC_BIT_VALUE_1.
+  * @register The used register:
+  *   FCSWPSR<SIZE><FLG><SWP>
+  */
+uint32_t FC_GetSwpsrBitValue(uint8_t BitNum)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_FC_SWPSR_BIT_NUM(BitNum));
+
+    tmp = TSB_FC->SWPSR;
+    tmp = (tmp >> (uint32_t) BitNum);
+    tmp &= FC_SWAP_BIT_VALUE_MASK;
+
+    return tmp;
+}
+
+/** @} */
+/* End of group FC_Exported_Functions */
+
+/** @} */
+/* End of group FC */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#endif                          /*(__TMPM46B_FC_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_fuart.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,881 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46B_fuart.c
+ * @brief   This file provides API functions for Full UART driver.
+ * @version V2.0.2.1
+ * @date    2015/02/26
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm46b_fuart.h"
+
+#if defined(__TMPM46B_FUART_H)
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @defgroup FUART
+  * @brief FUART driver modules
+  * @{
+  */
+
+/** @defgroup FUART_Private_Defines
+  * @{
+  */
+#define CR_UARTEN_SET                          ((uint32_t)0x00000001)
+#define CR_UARTEN_CLEAR                        ((uint32_t)0xFFFFFF7E)
+
+#define RSR_ERROR_MASK                         ((uint32_t)0x0000000F)
+#define RSR_FERR_FLAG                          ((uint32_t)0x00000001)
+#define RSR_PERR_FLAG                          ((uint32_t)0x00000002)
+#define RSR_BERR_FLAG                          ((uint32_t)0x00000004)
+#define RSR_OERR_FLAG                          ((uint32_t)0x00000008)
+
+#define ECR_ERROR_CLEAR                        ((uint32_t)0x00000000)
+
+#define FR_BUSY_FLAG                           ((uint32_t)0x00000008)
+
+#define LCR_H_FIFO_EN_FLAG                     ((uint32_t)0x00000010)
+#define LCR_H_FIFO_EN_SET                      ((uint32_t)0x00000010)
+#define LCR_H_FIFO_EN_CLEAR                    ((uint32_t)0xFFFFFFEF)
+#define FR_TX_STORAGE_MASK                     ((uint32_t)0x000000A0)
+#define FR_RX_STORAGE_MASK                     ((uint32_t)0x00000050)
+
+#define FR_TX_STORAGE_NORMAL                   ((uint32_t)0x00000000)
+#define FR_TX_STORAGE_FULL                     ((uint32_t)0x00000020)
+#define FR_TX_STORAGE_EMPTY                    ((uint32_t)0x00000080)
+#define FR_TX_STORAGE_INVALID                  ((uint32_t)0x000000A0)
+
+#define FR_RX_STORAGE_NORMAL                   ((uint32_t)0x00000000)
+#define FR_RX_STORAGE_EMPTY                    ((uint32_t)0x00000010)
+#define FR_RX_STORAGE_FULL                     ((uint32_t)0x00000040)
+#define FR_RX_STORAGE_INVALID                  ((uint32_t)0x00000050)
+
+#define LCR_H_WLEN_MASK                        ((uint32_t)0xFFFFFF9F)
+#define LCR_H_STP2_MASK                        ((uint32_t)0xFFFFFFF7)
+#define LCR_H_PARITY_MASK                      ((uint32_t)0xFFFFFF79)
+#define CR_FLOW_CTRL_MASK                      ((uint32_t)0x00000F07)
+#define CR_MODE_MASK                           ((uint32_t)0x0000CC07)
+
+#define LCR_H_BRK_SET                          ((uint32_t)0x00000001)
+#define LCR_H_BRK_CLEAR                        ((uint32_t)0xFFFFFFFE)
+
+#define CR_SIRLP_MASK                          ((uint32_t)0xFFFFFFFB)
+
+#define CR_UARTEN_MASK                         ((uint32_t)0x00000001)
+#define CR_SIREN_SET                           ((uint32_t)0x00000002)
+#define CR_SIREN_CLEAR                         ((uint32_t)0xFFFFFFFD)
+
+#define FUART_INT_BITS                         ((uint32_t)0x000007FF)
+
+#define DMACR_DMAONERR_CLEAR                   ((uint32_t)0x00000003)
+#define DMACR_DMAONERR_SET                     ((uint32_t)0x00000004)
+
+#define DMACR_TXDMAE_CLEAR                     ((uint32_t)0x00000005)
+#define DMACR_TXDMAE_SET                       ((uint32_t)0x00000002)
+#define DMACR_RXDMAE_CLEAR                     ((uint32_t)0x00000006)
+#define DMACR_RXDMAE_SET                       ((uint32_t)0x00000001)
+
+#define FR_MODEM_STATUS_MASK                   ((uint32_t)0x00000107)
+#define CR_MODEM_STATUS_MASK                   ((uint32_t)0x00000C00)
+
+#define CR_RTS_OUTPUT_0                        ((uint32_t)0x00000800)
+#define CR_RTS_OUTPUT_1                        ((uint32_t)0xFFFFF77F)
+
+#define CR_DTR_OUTPUT_0                        ((uint32_t)0x00000400)
+#define CR_DTR_OUTPUT_1                        ((uint32_t)0xFFFFFB7F)
+
+/** @} */
+/* End of group FUART_Private_Defines */
+
+/** @defgroup FUART_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group FUART_Private_FunctionPrototypes */
+
+/** @defgroup FUART_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group FUART_Private_Functions */
+
+/** @defgroup FUART_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified Full UART channel.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval None
+  */
+void FUART_Enable(TSB_FUART_TypeDef * FUARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    tmp = FUARTx->CR | CR_UARTEN_SET;
+    FUARTx->CR = tmp;
+}
+
+/**
+  * @brief  Disable the specified Full UART channel.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval None
+  */
+void FUART_Disable(TSB_FUART_TypeDef * FUARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    FUARTx->CR &= CR_UARTEN_CLEAR;
+}
+
+/**
+  * @brief  Get received data from the specified Full UART channel.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval The data received from FUARTx
+  */
+uint32_t FUART_GetRxData(TSB_FUART_TypeDef * FUARTx)
+{
+    uint32_t retval = 0U;
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    /* Return received data */
+    retval = FUARTx->DR & 0xFFU;
+
+    return retval;
+}
+
+/**
+  * @brief  Set data to be sent and start transmitting via the specified Full UART channel.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  Data: The data to be sent.
+  *   The Data range is 0x00 to 0xFF.
+  * @retval None
+  */
+void FUART_SetTxData(TSB_FUART_TypeDef * FUARTx, uint32_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_FUART_DATA(Data));
+
+    FUARTx->DR = Data & 0xFFU;
+}
+
+/**
+  * @brief  Get receive error status.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval The error flag.
+  *   The value returned can be one of the followings:
+  *   FUART_NO_ERR, FUART_OVERRUN, FUART_PARITY_ERR, 
+  *   FUART_FRAMING_ERR, FUART_BREAK_ERR, FUART_ERRS.
+  */
+FUART_Err FUART_GetErrStatus(TSB_FUART_TypeDef * FUARTx)
+{
+    FUART_Err retval = FUART_NO_ERR;
+    uint32_t tmp = 0U;
+
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    tmp = (FUARTx->RSR & RSR_ERROR_MASK);
+    switch (tmp) {
+    case RSR_FERR_FLAG:        /* Check overrun flag */
+        retval = FUART_FRAMING_ERR;
+        break;
+    case RSR_PERR_FLAG:        /* Check parity flag */
+        retval = FUART_PARITY_ERR;
+        break;
+    case RSR_BERR_FLAG:        /* Check break flag */
+        retval = FUART_BREAK_ERR;
+        break;
+    case RSR_OERR_FLAG:        /* Check overrun flag */
+        retval = FUART_OVERRUN;
+        break;
+    default:
+        if (tmp != 0U) {
+            /* more than one error */
+            retval = FUART_ERRS;
+        } else {
+            /* Do nothing */
+        }
+        break;
+    }
+    return retval;
+}
+
+/**
+  * @brief  Clear receive error status.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval None
+  */
+void FUART_ClearErrStatus(TSB_FUART_TypeDef * FUARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    /* Clear the receive error status */
+    FUARTx->ECR &= ECR_ERROR_CLEAR;
+}
+
+/**
+  * @brief  Get the state that whether the specified Full UART channel
+  *         is transmitting data or stopped.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval The work state of specified Full UART channel
+  *   This parameter can be one of the following values:
+  *   BUSY: The Full UART is transmitting data
+  *   DONE: The Full UART has stopped transmitting data
+  */
+WorkState FUART_GetBusyState(TSB_FUART_TypeDef * FUARTx)
+{
+    uint32_t tmp = 0U;
+    WorkState retval = DONE;
+
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    tmp = FUARTx->FR & FR_BUSY_FLAG;
+
+    /* Check busy flag */
+    if (tmp == FR_BUSY_FLAG) {
+        retval = BUSY;
+    } else {
+        /* Do nothing */
+    }
+    return retval;
+
+}
+
+/**
+  * @brief  Get the FIFO or hold register status.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param Direction: The direction of Full UART.
+  *   This parameter can be one of the following values:
+  *   FUART_RX, FUART_TX
+  * @retval The storage status.
+  *   When FIFO is enabled, FUART_StorageStatus indicates the FIFO status.
+  *   When FIFO is disabled, FUART_StorageStatus indicates the hold register status.
+  */
+FUART_StorageStatus FUART_GetStorageStatus(TSB_FUART_TypeDef * FUARTx, FUART_Direction Direction)
+{
+    uint32_t fen = 0U;
+    uint32_t src = 0U;
+    FUART_StorageStatus retval = FUART_STORAGE_EMPTY;
+
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_FUART_DIRECTION(Direction));
+
+    fen = FUARTx->LCR_H & LCR_H_FIFO_EN_FLAG;
+    src = FUARTx->FR;
+    if (fen == LCR_H_FIFO_EN_FLAG) {    /* FIFO mode */
+        if (Direction == FUART_TX) {    /* Get Transmit FIFO status */
+            src = FUARTx->FR & FR_TX_STORAGE_MASK;
+            switch (src) {
+            case FR_TX_STORAGE_NORMAL:
+                retval = FUART_STORAGE_NORMAL;
+                break;
+            case FR_TX_STORAGE_FULL:
+                retval = FUART_STORAGE_FULL;
+                break;
+            case FR_TX_STORAGE_EMPTY:
+                retval = FUART_STORAGE_EMPTY;
+                break;
+            case FR_TX_STORAGE_INVALID:
+                retval = FUART_STORAGE_INVALID;
+                break;
+            default:
+                /* Do nothing */
+                break;
+            }
+        } else {                /* Get Receive FIFO status */
+            src = FUARTx->FR & FR_RX_STORAGE_MASK;
+            switch (src) {
+            case FR_RX_STORAGE_NORMAL:
+                retval = FUART_STORAGE_NORMAL;
+                break;
+            case FR_RX_STORAGE_EMPTY:
+                retval = FUART_STORAGE_EMPTY;
+                break;
+            case FR_RX_STORAGE_FULL:
+                retval = FUART_STORAGE_FULL;
+                break;
+            case FR_RX_STORAGE_INVALID:
+                retval = FUART_STORAGE_INVALID;
+                break;
+            default:
+                /* Do nothing */
+                break;
+            }
+        }
+    } else {                    /* character mode */
+        if (Direction == FUART_TX) {    /* Get Transmit hold register status */
+            src = FUARTx->FR & FR_TX_STORAGE_MASK;
+            switch (src) {
+            case FR_TX_STORAGE_NORMAL:
+            case FR_TX_STORAGE_INVALID:
+                retval = FUART_STORAGE_INVALID;
+                break;
+            case FR_TX_STORAGE_FULL:
+                retval = FUART_STORAGE_FULL;
+                break;
+            case FR_TX_STORAGE_EMPTY:
+                retval = FUART_STORAGE_EMPTY;
+                break;
+            default:
+                /* Do nothing */
+                break;
+            }
+        } else {                /* Get Receive hold register status */
+            src = FUARTx->FR & FR_RX_STORAGE_MASK;
+            switch (src) {
+            case FR_RX_STORAGE_NORMAL:
+            case FR_RX_STORAGE_INVALID:
+                retval = FUART_STORAGE_INVALID;
+                break;
+            case FR_RX_STORAGE_EMPTY:
+                retval = FUART_STORAGE_EMPTY;
+                break;
+            case FR_RX_STORAGE_FULL:
+                retval = FUART_STORAGE_FULL;
+                break;
+            default:
+                /* Do nothing */
+                break;
+            }
+        }
+    }
+    return retval;
+}
+
+/**
+  * @brief  Set IrDA lower-power divisor.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  Divisor: The IrDA Low-power divisor (from 0x01 to 0xFF)
+  * @retval None
+  */
+void FUART_SetIrDADivisor(TSB_FUART_TypeDef * FUARTx, uint32_t Divisor)
+{
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_FUART_IRDA_DIVISOR(Divisor));
+
+    FUARTx->ILPR = Divisor & 0xFFU;
+}
+
+/**
+  * @brief  Initialize and configure the specified Full UART channel.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  InitStruct: The structure containing basic Full UART configuration
+  * @retval None
+  */
+void FUART_Init(TSB_FUART_TypeDef * FUARTx, FUART_InitTypeDef * InitStruct)
+{
+    uint32_t tmp = 0U;
+    uint32_t fuartclk = 0U;
+    uint32_t ibd = 0U;          /* Integer part of baud rate divisor */
+    uint32_t fbd = 0U;          /* Fractional part of baud rate divisor */
+    uint32_t br = InitStruct->BaudRate; /* BaudRate */
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(InitStruct));
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_FUART_BAUDRATE(InitStruct->BaudRate));
+    assert_param(IS_FUART_DATA_BITS(InitStruct->DataBits));
+    assert_param(IS_FUART_STOPBITS(InitStruct->StopBits));
+    assert_param(IS_FUART_PARITY(InitStruct->Parity));
+    assert_param(IS_FUART_MODE(InitStruct->Mode));
+    assert_param(IS_FUART_FLOW_CTRL(InitStruct->FlowCtrl));
+
+    /* Get UARTCLK */
+    SystemCoreClockUpdate();
+    fuartclk = SystemCoreClock; /* UARTCLK = fsys */
+
+    ibd = fuartclk / (16U * br);
+    fbd = (8U * fuartclk + br - 128U * ibd * br) / (2U * br);
+
+    if (fbd == 0U) {
+        fbd = 1U;               /* Fractional part of baud rate divisor can not be 0x00 */
+    } else {
+        /* Do nothing */
+    }
+
+    FUARTx->IBRD = ibd;         /* Set integer part of baud rate divisor */
+    FUARTx->FBRD = fbd;         /* Set fractional part of baud rate divisor */
+
+    tmp = FUARTx->LCR_H;
+
+    tmp &= LCR_H_WLEN_MASK;
+    tmp |= InitStruct->DataBits;
+
+    tmp &= LCR_H_STP2_MASK;
+    tmp |= InitStruct->StopBits;
+
+    tmp &= LCR_H_PARITY_MASK;
+    tmp |= InitStruct->Parity;
+
+    FUARTx->LCR_H = tmp;        /* Set DataBits, StopBits, Parity */
+
+    tmp = FUARTx->CR;
+    tmp &= CR_FLOW_CTRL_MASK;
+    tmp |= InitStruct->FlowCtrl;
+
+    tmp &= CR_MODE_MASK;
+    tmp |= InitStruct->Mode;
+
+    FUARTx->CR = tmp;           /* Set Flow Control, Mode */
+}
+
+/**
+  * @brief  Enable the transmit and receive FIFO.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval None
+  */
+void FUART_EnableFIFO(TSB_FUART_TypeDef * FUARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    FUARTx->LCR_H |= LCR_H_FIFO_EN_SET;
+}
+
+/**
+  * @brief  Disable the transmit and receive FIFO and the mode will be changed to character mode.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval None
+  */
+void FUART_DisableFIFO(TSB_FUART_TypeDef * FUARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    FUARTx->LCR_H &= LCR_H_FIFO_EN_CLEAR;
+}
+
+/**
+  * @brief  Generate the break condition for Full UART.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  NewState: New state of the FUART Send break.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void FUART_SetSendBreak(TSB_FUART_TypeDef * FUARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set UARTxLCR_H<BRK> to  enable the send break to generate transmit break condition */
+        FUARTx->LCR_H |= LCR_H_BRK_SET;
+    } else {
+        /* Clear UARTxLCR_H<BRK> to disable the send break */
+        FUARTx->LCR_H &= LCR_H_BRK_CLEAR;
+    }
+}
+
+/**
+  * @brief  Select IrDA encoding mode for transmitting 0 bits.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  Mode: IrDA encoding mode select for transmitting 0 bits.
+  *   This parameter can be one of the following values:
+  *   FUART_IRDA_3_16_BIT_PERIOD_MODE
+  *   FUART_IRDA_3_TIMES_IRLPBAUD16_MODE  
+  * @retval None
+  */
+void FUART_SetIrDAEncodeMode(TSB_FUART_TypeDef * FUARTx, uint32_t Mode)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_IRDA_ENCODE_MODE(Mode));
+
+    /* read UARTCR register then clear bit<SIRLP> as FUART_IRDA_3_16_BIT_PERIOD_MODE */
+    tmp = FUARTx->CR & CR_SIRLP_MASK;
+
+    if (Mode == FUART_IRDA_3_TIMES_IRLPBAUD16_MODE) {
+        /* Set mode as FUART_IRDA_3_TIMES_IRLPBAUD16_MODE */
+        tmp |= FUART_IRDA_3_TIMES_IRLPBAUD16_MODE;
+    } else {
+        /* Do nothing */
+    }
+
+    FUARTx->CR = tmp;
+}
+
+/**
+  * @brief  Enable the IrDA circuit
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval The result of enabling IrDA circuit
+  *   This parameter can be one of the following values:
+  *   SUCCESS: Enable IrDA circuit successfully.
+  *   ERROR: The UART channel is disabled, can not enable IrDA circuit.
+  */
+Result FUART_EnableIrDA(TSB_FUART_TypeDef * FUARTx)
+{
+    uint32_t tmp = 0U;
+    Result retval = SUCCESS;
+
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    /* Get UARTCR<UARTEN> to check if Full UART channel is enabled */
+    tmp = FUARTx->CR & CR_UARTEN_MASK;
+
+    if (tmp == CR_UARTEN_SET) { /* Full UART is enabled */
+        tmp = FUARTx->CR | CR_SIREN_SET;
+        FUARTx->CR = tmp;
+    } else {                    /* Full UART is disabled */
+        retval = ERROR;         /* Can not enable IrDA circuit */
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Disable the IrDA circuit
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval None
+  */
+void FUART_DisableIrDA(TSB_FUART_TypeDef * FUARTx)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    /* Get UARTCR<UARTEN> to check if Full UART channel is enabled */
+    tmp = FUARTx->CR & CR_UARTEN_MASK;
+
+    if (tmp == CR_UARTEN_SET) { /* Full UART is enabled */
+        tmp = FUARTx->CR & CR_SIREN_CLEAR;
+        FUARTx->CR = tmp;
+    } else {                    /* Full UART is disabled */
+        /* Do nothing */
+    }
+}
+
+/**
+  * @brief  Set the Receive and Transmit interrupt FIFO level.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  RxLevel: Receive interrupt FIFO level.
+  *   This parameter can be one of the following values:
+  *   FUART_RX_FIFO_LEVEL_4:  The data in Receive FIFO become >= 4 words
+  *   FUART_RX_FIFO_LEVEL_8:  The data in Receive FIFO become >= 8 words
+  *   FUART_RX_FIFO_LEVEL_16: The data in Receive FIFO become >= 16 words
+  *   FUART_RX_FIFO_LEVEL_24: The data in Receive FIFO become >= 24 words
+  *   FUART_RX_FIFO_LEVEL_28: The data in Receive FIFO become >= 28 words
+  * @param  TxLevel: Transmit interrupt FIFO level.
+  *   This parameter can be one of the following values:
+  *   FUART_TX_FIFO_LEVEL_4:  The data in Transmit FIFO become <= 4 words
+  *   FUART_TX_FIFO_LEVEL_8:  The data in Transmit FIFO become <= 8 words
+  *   FUART_TX_FIFO_LEVEL_16: The data in Transmit FIFO become <= 16 words
+  *   FUART_TX_FIFO_LEVEL_24: The data in Transmit FIFO become <= 24 words
+  *   FUART_TX_FIFO_LEVEL_28: The data in Transmit FIFO become <= 28 words
+  * @retval None
+  */
+void FUART_SetINTFIFOLevel(TSB_FUART_TypeDef * FUARTx, uint32_t RxLevel, uint32_t TxLevel)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_FUART_RX_FIFO_LEVEL(RxLevel));
+    assert_param(IS_FUART_TX_FIFO_LEVEL(TxLevel));
+
+    tmp = RxLevel | TxLevel;
+
+    FUARTx->IFLS = tmp;
+}
+
+/**
+  * @brief  Mask(Enable) interrupt source of the specified channel.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  IntMaskSrc: The interrupt source to be masked(enabled).
+  * @retval None
+  */
+void FUART_SetINTMask(TSB_FUART_TypeDef * FUARTx, uint32_t IntMaskSrc)
+{
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_INT_MASK_SRC(IntMaskSrc));
+
+    FUARTx->IMSC = IntMaskSrc;
+}
+
+/**
+  * @brief  Get the mask(enable) setting for each interrupt source.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval A data with union that it indicates the mask setting.
+  */
+FUART_INTStatus FUART_GetINTMask(TSB_FUART_TypeDef * FUARTx)
+{
+    FUART_INTStatus retval = { 0U };
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    retval.All = FUARTx->IMSC & FUART_INT_BITS;
+    return retval;
+}
+
+/**
+  * @brief  Get the raw interrupt status of the specified Full UART channel.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval A data with union that indicates the raw interrupt status.
+  */
+FUART_INTStatus FUART_GetRawINTStatus(TSB_FUART_TypeDef * FUARTx)
+{
+    FUART_INTStatus retval = { 0U };
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    retval.All = FUARTx->RIS & FUART_INT_BITS;
+    return retval;
+}
+
+/**
+  * @brief  Get the masked interrupt status of the specified Full UART channel.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval A data with union that indicates the masked interrupt status.
+  */
+FUART_INTStatus FUART_GetMaskedINTStatus(TSB_FUART_TypeDef * FUARTx)
+{
+    FUART_INTStatus retval = { 0U };
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    retval.All = FUARTx->MIS & FUART_INT_BITS;
+
+    return retval;
+}
+
+/**
+  * @brief  Clear the interrupts of the specified Full UART channel.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  INTStatus: A data with union that indicates the interrupts to be cleared.
+  * @retval None
+  */
+void FUART_ClearINT(TSB_FUART_TypeDef * FUARTx, FUART_INTStatus INTStatus)
+{
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_INT_MASK_SRC(INTStatus.All));
+
+    FUARTx->ICR = INTStatus.All;
+}
+
+/**
+  * @brief  Enable or disable the DMA receive request output 
+  *         on assertion of a UART error interrupt.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  NewState: New state of the DMA receive request output 
+  *         on assertion of a UART error interrupt.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void FUART_SetDMAOnErr(TSB_FUART_TypeDef * FUARTx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* read UARTDMACR then clear bit2 as disable it */
+    tmp = FUARTx->DMACR & DMACR_DMAONERR_CLEAR;
+
+    if (NewState == ENABLE) {
+        /* if enable, Set bit2: UARTDMACR<DMAONERR> */
+        tmp |= DMACR_DMAONERR_SET;
+    } else {
+        /* Do nothing */
+    }
+
+    FUARTx->DMACR = tmp;
+}
+
+/**
+  * @brief  Enable or Disable the Transmit FIFO DMA or Receive FIFO DMA.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param Direction: The direction of Full UART.
+  *   This parameter can be one of the following values:
+  *   FUART_RX, FUART_TX
+  * @param  NewState: New state of Transmit or Receive FIFO DMA.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void FUART_SetFIFODMA(TSB_FUART_TypeDef * FUARTx, FUART_Direction Direction,
+                      FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_FUART_DIRECTION(Direction));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Direction == FUART_TX) {        /* Configure Transmit FIFO DMA */
+        tmp = FUARTx->DMACR & DMACR_TXDMAE_CLEAR;
+        if (NewState == ENABLE) {
+            /* if enable, Set bit1: UARTDMACR<TXDMAE> */
+            tmp |= DMACR_TXDMAE_SET;
+        } else {
+            /* Do nothing */
+        }
+    } else {                    /* Configure Receive FIFO DMA */
+        tmp = FUARTx->DMACR & DMACR_RXDMAE_CLEAR;
+        if (NewState == ENABLE) {
+            /* if enable, Set bit0: UARTDMACR<RXDMAE> */
+            tmp |= DMACR_RXDMAE_SET;
+        } else {
+            /* Do nothing */
+        }
+    }
+
+    FUARTx->DMACR = tmp;
+}
+
+/**
+  * @brief  Get all the Modem Status, include: CTS, DSR, DCD, RIN, DTR, and RTS.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @retval A data with union that indicates all the modem status.
+  */
+FUART_AllModemStatus FUART_GetModemStatus(TSB_FUART_TypeDef * FUARTx)
+{
+    uint32_t tmpfr = 0U;
+    uint32_t tmpcr = 0U;
+    FUART_AllModemStatus retval = { 0U };
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+
+    tmpfr = FUARTx->FR & FR_MODEM_STATUS_MASK;  /* Get RI, DCD, DSR, CTS status */
+    tmpcr = FUARTx->CR & CR_MODEM_STATUS_MASK;  /* Get RTS,DTS status */
+
+    tmpfr |= tmpcr;
+    retval.All = tmpfr;
+    return retval;
+}
+
+/**
+  * @brief  Set the Full UART RTS(Request To Send) modem status output.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  Status: RTS modem status output.
+  *   This parameter can be one of the following values:
+  *   FUART_MODEM_STATUS_0: The modem status output is 0
+  *   FUART_MODEM_STATUS_1: The modem status output is 1
+  * @retval None
+  */
+void FUART_SetRTSStatus(TSB_FUART_TypeDef * FUARTx, FUART_ModemStatus Status)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_MODEM_STATUS(Status));
+
+    if (Status == FUART_MODEM_STATUS_1) {
+        /* Set UARTxCR<RTS> to make RTS modem status output be 1 */
+        FUARTx->CR &= CR_RTS_OUTPUT_1;
+    } else {
+        /* Set UARTxCR<RTS> to make RTS modem status output be 0 */
+        tmp = FUARTx->CR | CR_RTS_OUTPUT_0;
+        FUARTx->CR = tmp;
+    }
+}
+
+/**
+  * @brief  Set the Full UART DTR(Data Transmit Ready) modem status output.
+  * @param  FUARTx: Select the Full UART channel.
+  *   This parameter can be one of the following values:
+  *   FUART0, FUART1.
+  * @param  Status: DTR modem status output.
+  *   This parameter can be one of the following values:
+  *   FUART_MODEM_STATUS_0: The modem status output is 0
+  *   FUART_MODEM_STATUS_1: The modem status output is 1
+  * @retval None
+  */
+void FUART_SetDTRStatus(TSB_FUART_TypeDef * FUARTx, FUART_ModemStatus Status)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_FUART_PERIPH(FUARTx));
+    assert_param(IS_MODEM_STATUS(Status));
+
+    if (Status == FUART_MODEM_STATUS_1) {
+        /* Set UARTxCR<DTR> to make DTR modem status output be 1 */
+        FUARTx->CR &= CR_DTR_OUTPUT_1;
+    } else {
+        /* Set UARTxCR<DTR> to make DTR modem status output be 0 */
+        tmp = FUARTx->CR | CR_DTR_OUTPUT_0;
+        FUARTx->CR = tmp;
+    }
+}
+
+/** @} */
+/* End of group FUART_Exported_Functions */
+
+/** @} */
+/* End of group FUART */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#endif                          /* defined(__TMPM46B_FUART_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_gpio.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,659 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_gpio.c
+ * @brief   This file provides API functions for GPIO driver.
+ * @version V2.0.2.1
+ * @date    2015/02/09
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm46b_gpio.h"
+
+#if defined(__TMPM46B_GPIO_H)
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+/** @defgroup GPIO
+  * @brief GPIO driver modules
+  * @{
+  */
+
+#define GPIO_NUM (11U)          /* total number of gpio */
+
+/**
+  * @brief the base address of GPIO port.
+  */
+const uint32_t GPIO_Base[GPIO_NUM] = {
+    TSB_PA_BASE, TSB_PB_BASE, TSB_PC_BASE, TSB_PD_BASE, TSB_PE_BASE,
+    TSB_PF_BASE, TSB_PG_BASE, TSB_PH_BASE, TSB_PJ_BASE, TSB_PK_BASE,
+    TSB_PL_BASE
+};
+
+/**
+  * @brief:Information of gpio port.
+  * Note: for bit0 to bit7 of each member below, its value '0' or '1' has the means:
+  *          '0': that bit is not available
+  *          '1': that bit is available
+  * For example, if DATA = 0x7F, it mean the bit0 to bit6 of DATA register are available.
+*/
+const GPIO_RegTypeDef GPIO_SFRs[GPIO_NUM] = {
+/*        DATA    CR      FR1    FR2    FR3    FR4    FR5    FR6     OD     PUP    PDN    IE      */
+/* PA */ {0xFFU, 0xFFU, {0xFFU, 0xFFU, 0xE0U, 0x80U, 0x80U, 0x00U}, 0xFFU, 0xFBU, 0x04U, 0xFFU},
+/* PB */ {0xFFU, 0xFFU, {0x7FU, 0x40U, 0x3FU, 0x4CU, 0xFCU, 0x00U}, 0xFFU, 0xFFU, 0x00U, 0xBFU},
+/* PC */ {0x3FU, 0x3FU, {0x3CU, 0x20U, 0x00U, 0x00U, 0x00U, 0x00U}, 0x3FU, 0x3FU, 0x00U, 0x3FU},
+/* PD */ {0x1FU, 0x1FU, {0x1FU, 0x00U, 0x00U, 0x00U, 0x00U, 0x00U}, 0x1FU, 0x1FU, 0x00U, 0x1FU},
+/* PE */ {0xFFU, 0xFFU, {0x7EU, 0x00U, 0xFFU, 0x18U, 0x9FU, 0x00U}, 0xFFU, 0xFFU, 0x00U, 0xFFU},
+/* PF */ {0xFFU, 0xFFU, {0xFFU, 0x00U, 0xFFU, 0xC6U, 0x78U, 0x00U}, 0xFFU, 0xFFU, 0x00U, 0xFFU},
+/* PG */ {0xFFU, 0xFFU, {0xFFU, 0x00U, 0x0FU, 0x0CU, 0xFFU, 0x00U}, 0xFFU, 0xFFU, 0x00U, 0xFFU},
+/* PH */ {0x0FU, 0x0FU, {0x0FU, 0x03U, 0x0FU, 0x0FU, 0x00U, 0x00U}, 0x0FU, 0x0FU, 0x00U, 0x0FU},
+/* PJ */ {0xFFU, 0xFFU, {0x80U, 0x80U, 0x80U, 0x00U, 0x00U, 0x00U}, 0xFFU, 0xFFU, 0x00U, 0xFFU},
+/* PK */ {0x1FU, 0x1FU, {0x00U, 0x1EU, 0x0CU, 0x02U, 0x00U, 0x00U}, 0x1FU, 0x1FU, 0x00U, 0x1FU},
+/* PL */ {0x0FU, 0x0FU, {0x00U, 0x00U, 0x0FU, 0x0DU, 0x0EU, 0x08U}, 0x0FU, 0x0FU, 0x00U, 0x0FU}
+};
+
+/** @defgroup GPIO_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Read GPIO Data register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
+  *   GPIO_PL
+  * @retval Data:The value of DATA register.
+  */
+uint8_t GPIO_ReadData(GPIO_Port GPIO_x)
+{
+    uint8_t Data = 0U;
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    Data = (uint8_t) PORT->DATA;
+
+    return Data;
+}
+
+/**
+  * @brief  Read Bit of GPIO Data register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
+  *   GPIO_PL
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0,  GPIO_BIT_1,  GPIO_BIT_2,  GPIO_BIT_3,
+  *   GPIO_BIT_4,  GPIO_BIT_5,  GPIO_BIT_6,  GPIO_BIT_7.
+  * @retval BitValue:The value of specified Bit.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1
+  */
+uint8_t GPIO_ReadDataBit(GPIO_Port GPIO_x, uint8_t Bit_x)
+{
+    uint8_t Data = 0U;
+    uint8_t tmp = 0U;
+    uint8_t BitValue = 0U;
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_GPIO_BIT(Bit_x));
+    assert_param(IS_GPIO_BIT_DATA(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    Data = (uint8_t) PORT->DATA;
+    tmp = (uint8_t) (Data & Bit_x);
+    if (tmp) {
+        BitValue = GPIO_BIT_VALUE_1;
+    } else {
+        BitValue = GPIO_BIT_VALUE_0;
+    }
+
+    return (BitValue);
+}
+
+/**
+  * @brief  Write specified value to GPIO DATA register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
+  *   GPIO_PL.
+  * @param  Data: specified value will be written to GPIO DATA register.
+  * @retval None
+  */
+void GPIO_WriteData(GPIO_Port GPIO_x, uint8_t Data)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_GPIO_WRITE(GPIO_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    PORT->DATA = Data;
+}
+
+/**
+  * @brief  Write to specified Bit of GPIO DATA register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
+  *   GPIO_PL.
+  * @param  Bit_x: Select GPIO pin,which can set as output.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param BitValue:The value of specified Bit.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_VALUE_0, GPIO_BIT_VALUE_1
+  * @retval None
+  */
+void GPIO_WriteDataBit(GPIO_Port GPIO_x, uint8_t Bit_x, uint8_t BitValue)
+{
+    uint8_t tmp = 0U;
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_GPIO_BIT_VALUE(BitValue));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinCR;
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    tmp = GPIO_ReadData(GPIO_x);
+    if (BitValue) {
+        tmp |= Bit_x;
+    } else {
+        Bit_x = (~Bit_x);
+        tmp &= Bit_x;
+    }
+    PORT->DATA = tmp;
+}
+
+/**
+  * @brief  Initialize the specified GPIO pin.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
+  *   GPIO_PL.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param  GPIO_InitStruct: The structure containing basic GPIO configuration.
+  * @retval None
+  */
+void GPIO_Init(GPIO_Port GPIO_x, uint8_t Bit_x, GPIO_InitTypeDef * GPIO_InitStruct)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_POINTER_NOT_NULL(GPIO_InitStruct));
+    assert_param(IS_GPIO_IO_MODE_STATE(GPIO_InitStruct->IOMode));
+    assert_param(IS_GPIO_PULLUP_STATE(GPIO_InitStruct->PullUp));
+    assert_param(IS_GPIO_PULLDOWN_STATE(GPIO_InitStruct->PullDown));
+    assert_param(IS_GPIO_OPEN_DRAIN_STATE(GPIO_InitStruct->OpenDrain));
+
+    tmp = GPIO_InitStruct->IOMode;
+    switch (tmp) {
+    case GPIO_INPUT_MODE:
+        GPIO_SetInput(GPIO_x, Bit_x);
+        break;
+    case GPIO_OUTPUT_MODE:
+        GPIO_SetOutput(GPIO_x, Bit_x);
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+    tmp = GPIO_InitStruct->PullUp;
+    switch (tmp) {
+    case GPIO_PULLUP_ENABLE:
+        GPIO_SetPullUp(GPIO_x, Bit_x, ENABLE);
+        break;
+    case GPIO_PULLUP_DISABLE:
+        GPIO_SetPullUp(GPIO_x, Bit_x, DISABLE);
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+    tmp = GPIO_InitStruct->PullDown;
+    switch (tmp) {
+    case GPIO_PULLDOWN_ENABLE:
+        GPIO_SetPullDown(GPIO_x, Bit_x, ENABLE);
+        break;
+    case GPIO_PULLDOWN_DISABLE:
+        GPIO_SetPullDown(GPIO_x, Bit_x, DISABLE);
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+    tmp = GPIO_InitStruct->OpenDrain;
+    switch (tmp) {
+    case GPIO_OPEN_DRAIN_ENABLE:
+        GPIO_SetOpenDrain(GPIO_x, Bit_x, ENABLE);
+        break;
+    case GPIO_OPEN_DRAIN_DISABLE:
+        GPIO_SetOpenDrain(GPIO_x, Bit_x, DISABLE);
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+}
+
+/**
+  * @brief  Set specified GPIO Pin as output port.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
+  *   GPIO_PL.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @retval None
+  */
+void GPIO_SetOutput(GPIO_Port GPIO_x, uint8_t Bit_x)
+{
+    uint8_t tmp = 0U;
+    uint32_t i;
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinCR;
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    tmp = (~Bit_x);
+    for (i = 0U; i < FRMAX; i++) {
+        if (GPIO_SFRs[GPIO_x].PinFR[i]) {
+            PORT->FR[i] &= tmp;
+        } else {
+            /* Do nothing */
+        }
+    }
+    if (GPIO_SFRs[GPIO_x].PinIE) {
+        PORT->IE &= tmp;
+    } else {
+        /* Do nothing */
+    }
+    PORT->CR |= Bit_x;
+}
+
+/**
+  * @brief  Set specified GPIO Pin as input port.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
+  *   GPIO_PL.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @retval None
+  */
+void GPIO_SetInput(GPIO_Port GPIO_x, uint8_t Bit_x)
+{
+    uint8_t tmp = 0U;
+    uint32_t i;
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinIE;
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    tmp = (~Bit_x);
+    for (i = 0U; i < FRMAX; i++) {
+        if (GPIO_SFRs[GPIO_x].PinFR[i]) {
+            PORT->FR[i] &= tmp;
+        } else {
+            /* Do nothing */
+        }
+    }
+    if (GPIO_SFRs[GPIO_x].PinCR) {
+        PORT->CR &= tmp;
+    } else {
+        /* Do nothing */
+    }
+    PORT->IE |= Bit_x;
+}
+
+/**
+  * @brief  Set or clear the bit setting in output control register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
+  *   GPIO_PL.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param NewState: The output state of the pin.
+  *   This parameter can be one of the following values:
+  *   ENABLE , DISABLE.
+  * @retval None
+  */
+void GPIO_SetOutputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinCR;
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_OUT(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    if (NewState == ENABLE) {
+        PORT->CR |= Bit_x;
+    } else {
+        PORT->CR &= (~(uint32_t) Bit_x);
+    }
+}
+
+/**
+  * @brief  Set or clear the bit setting in input control register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
+  *   GPIO_PL.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param NewState: The input state of the pin.
+  *   This parameter can be one of the following values:
+  *   ENABLE , DISABLE.
+  * @retval None
+  */
+void GPIO_SetInputEnableReg(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinIE;
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_IN(GPIO_x, Bit_x));
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+
+    if (NewState == ENABLE) {
+        PORT->IE |= Bit_x;
+    } else {
+        PORT->IE &= (~(uint32_t) Bit_x);
+    }
+}
+
+/**
+  * @brief  Enable or Disable pull-up function of specified GPIO Pin.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK,
+  *   GPIO_PL.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param  NewState: New state of the Pull-Up function.
+  *   This parameter can be one of the following values:
+  *   ENABLE , DISABLE.
+  * @retval None
+  */
+void GPIO_SetPullUp(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinPUP;
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_PUP(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    if (NewState == ENABLE) {
+        PORT->PUP |= Bit_x;
+    } else {
+        PORT->PUP &= (~(uint32_t) Bit_x);
+    }
+}
+
+/**
+  * @brief  Enable or Disable pull-down function of specified GPIO Pin.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_2, GPIO_BIT_ALL, or combination of the effective bits. 
+  * @param  NewState: New state of the Pull-Down function.
+  *   This parameter can be one of the following values:
+  *   ENABLE , DISABLE.
+  * @retval None
+  */
+void GPIO_SetPullDown(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinPDN;
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_PDN(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    if (NewState == ENABLE) {
+        PORT->PDN |= Bit_x;
+    } else {
+        PORT->PDN &= (~(uint32_t) Bit_x);
+    }
+}
+
+/**
+  * @brief  Set specified GPIO Pin as open drain port or CMOS port.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK, 
+  *   GPIO_PL.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @param  NewState: New state of the Open Drain function.
+  *   This parameter can be one of the following values:
+  *   ENABLE , DISABLE.
+  * @retval None
+  */
+void GPIO_SetOpenDrain(GPIO_Port GPIO_x, uint8_t Bit_x, FunctionalState NewState)
+{
+
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinOD;
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_OD(GPIO_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    if (NewState == ENABLE) {
+        PORT->OD |= Bit_x;
+    } else {
+        PORT->OD &= (~(uint32_t) Bit_x);
+    }
+}
+
+/**
+  * @brief  Enable specified GPIO Function register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK
+  *   GPIO_PL.  
+  * @param  FuncReg_x: Select Function register of GPIO.
+  *   This parameter can be one of the following values:
+  *   GPIO_FUNC_REG_1, GPIO_FUNC_REG_2, GPIO_FUNC_REG_3,
+  *   GPIO_FUNC_REG_4, GPIO_FUNC_REG_5, GPIO_FUNC_REG_6.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @retval None
+  */
+void GPIO_EnableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x];
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    PORT->FR[FuncReg_x] |= Bit_x;
+}
+
+/**
+  * @brief  Disable specified GPIO Function register.
+  * @param  GPIO_x: Select GPIO port.
+  *   This parameter can be one of the following values:
+  *   GPIO_PA, GPIO_PB, GPIO_PC, GPIO_PD, GPIO_PE,
+  *   GPIO_PF, GPIO_PG, GPIO_PH, GPIO_PJ, GPIO_PK, 
+  *   GPIO_PL.  
+  * @param  FuncReg_x: Select Function register of GPIO.
+  *   This parameter can be one of the following values:
+  *   GPIO_FUNC_REG_1, GPIO_FUNC_REG_2, GPIO_FUNC_REG_3,
+  *   GPIO_FUNC_REG_4, GPIO_FUNC_REG_5, GPIO_FUNC_REG_6.
+  * @param  Bit_x: Select GPIO pin.
+  *   This parameter can be one of the following values:
+  *   GPIO_BIT_0, GPIO_BIT_1, GPIO_BIT_2, GPIO_BIT_3,
+  *   GPIO_BIT_4, GPIO_BIT_5, GPIO_BIT_6, GPIO_BIT_7, GPIO_BIT_ALL,
+  *   or combination of the effective bits.
+  * @retval None
+  */
+void GPIO_DisableFuncReg(GPIO_Port GPIO_x, uint8_t FuncReg_x, uint8_t Bit_x)
+{
+    TSB_Port_TypeDef *PORT = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_PORT(GPIO_x));
+    assert_param(IS_GPIO_FUNCTION_REG(FuncReg_x));
+
+    if (Bit_x == GPIO_BIT_ALL) {
+        Bit_x = GPIO_SFRs[GPIO_x].PinFR[FuncReg_x];
+    } else {
+        /* Do nothing */
+    }
+
+    /* Check the parameters */
+    assert_param(IS_GPIO_BIT_FR(GPIO_x, FuncReg_x, Bit_x));
+
+    PORT = (TSB_Port_TypeDef *) GPIO_Base[GPIO_x];
+    PORT->FR[FuncReg_x] &= (~(uint32_t) Bit_x);
+}
+
+/** @} */
+/* End of group GPIO_Exported_Functions */
+/** @} */
+/* End of group GPIO */
+/** @} */
+/* End of group TX04_Periph_Driver */
+#endif                          /* defined(__TMPM46B_GPIO_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_i2c.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,450 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_i2c.c
+ * @brief   This file provides API functions for I2C driver.
+ * @version V2.0.2.1
+ * @date    2015/02/13
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm46b_i2c.h"
+
+#if defined(__TMPM46B_I2C_H)
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @defgroup I2C 
+  * @brief I2C driver modules
+  * @{
+  */
+
+/** @defgroup I2C_Private_Defines
+  * @{
+  */
+
+#define I2CCR1_BC_MASK                  ((uint32_t)0x0000001F)
+#define I2CCR1_ACK_SET                  ((uint32_t)0x00000010)
+#define I2CCR1_ACK_CLEAR                ((uint32_t)0x000000EF)
+#define I2CCR1_SCK_MASK                 ((uint32_t)0x000000F8)
+#define I2CCR1_NOACK_MASK               ((uint32_t)0x00000008)
+#define I2CCR1_NOACK_ENABLE             ((uint32_t)0x00000000)
+
+#define I2CCR2_PIN_SET                  ((uint32_t)0x00000010)
+#define I2CCR2_I2CM_I2C                 ((uint32_t)0x00000008)
+#define I2CCR2_SWRST_MASK               ((uint32_t)0xFFFFFFFC)
+#define I2CCR2_SWRST_CMD1               ((uint32_t)0x00000002)
+#define I2CCR2_SWRST_CMD2               ((uint32_t)0x00000001)
+#define I2CCR2_START_CONDITION          ((uint32_t)0x000000F0)
+#define I2CCR2_STOP_CONDITION           ((uint32_t)0x000000D0)
+
+
+#define I2CAR_SA_MASK                   ((uint32_t)0x000000FE)
+#define I2CAR_ALS_SET                   ((uint32_t)0x00000001)
+#define I2CAR_ALS_CLEAR                 ((uint32_t)0xFFFFFFFE)
+#define I2C_DATA_MASK                   ((uint32_t)0x000000FF)
+
+#define I2CIE_IE_SET                    ((uint32_t)0x00000001)
+#define I2CIE_IE_CLEAR                  ((uint32_t)0xFFFFFFFE)
+
+#define I2CIR_ISIC_MASK                 ((uint32_t)0x00000001)
+#define I2CIR_ISIC_SET                  ((uint32_t)0x00000001)
+
+/** @} */
+/* End of group I2C_Private_Defines */
+
+/** @defgroup I2C_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enable or disable the generation of ACK clock. 
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @param  NewState: New state of ACK clock.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetACK(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = I2Cx->CR1;
+    if (NewState == ENABLE) {
+        /* Set I2CxCR1<ACK> to enable generation of ACK clock */
+        tmp |= I2CCR1_ACK_SET;
+    } else {
+        /* Clear I2CxCR1<ACK> to disable generation of ACK clock */
+        tmp &= I2CCR1_ACK_CLEAR;
+    }
+    I2Cx->CR1 = tmp;
+}
+
+/**
+  * @brief  Initialize the specified I2C channel in I2C mode.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @param  InitI2CStruct: The structure containing I2C in I2C mode configuration.
+  * @retval None
+  */
+void I2C_Init(TSB_I2C_TypeDef * I2Cx, I2C_InitTypeDef * InitI2CStruct)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_POINTER_NOT_NULL(InitI2CStruct));
+    assert_param(IS_I2C_ADDR(InitI2CStruct->I2CSelfAddr));
+    assert_param(IS_I2C_BIT_NUM(InitI2CStruct->I2CDataLen));
+    assert_param(IS_I2C_SCK_CLK_DIV(InitI2CStruct->I2CClkDiv));
+    assert_param(IS_FUNCTIONAL_STATE(InitI2CStruct->I2CACKState));
+
+    /* Get the system clock frequency */
+    SystemCoreClockUpdate();
+
+    /* Check the prescaler clock in the range between 50ns and 150ns */
+    assert_param(IS_PRESCALER_CLK_VALID(InitI2CStruct->PrescalerClkDiv, SystemCoreClock));
+
+    /* Set prescaler clock */
+    I2Cx->PRS = InitI2CStruct->PrescalerClkDiv % I2C_PRESCALER_DIV_32;
+
+    /* Set selfaddress for I2Cx */
+    I2Cx->AR = InitI2CStruct->I2CSelfAddr & I2CAR_SA_MASK;
+
+    /* Set I2C bit length of transfer data  */
+    tmp = I2Cx->CR1 & I2CCR1_BC_MASK;
+    tmp |= (InitI2CStruct->I2CDataLen << 5U);
+    /* Set I2C clock division */
+    tmp &= I2CCR1_SCK_MASK;
+    tmp |= InitI2CStruct->I2CClkDiv;
+    if (InitI2CStruct->I2CACKState) {
+        /* Set I2CxCR1<ACK> to enable generation of ACK clock */
+        tmp |= I2CCR1_ACK_SET;
+    } else {
+        /* Clear I2CxCR1<ACK> to disable generation of ACK clock */
+        tmp &= I2CCR1_ACK_CLEAR;
+    }
+    I2Cx->CR1 = tmp;
+
+    /* Initialize I2C to I2C Slave-Rx mode  */
+    I2Cx->CR2 = I2CCR2_PIN_SET | I2CCR2_I2CM_I2C;
+}
+
+/**
+  * @brief  Specify the number of bits per transfer.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @param  I2CBitNum: Specify the number of bits.
+  *   This parameter can be one of the following values:
+  *   I2C_DATA_LEN_8, I2C_DATA_LEN_1,I2C_DATA_LEN_2,I2C_DATA_LEN_3,
+  *   I2C_DATA_LEN_4, I2C_DATA_LEN_5,I2C_DATA_LEN_6 and I2C_DATA_LEN_7.
+  * @retval None
+  */
+void I2C_SetBitNum(TSB_I2C_TypeDef * I2Cx, uint32_t I2CBitNum)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_BIT_NUM(I2CBitNum));
+
+    /* Write number of bits per transfer into I2CxCR1<BC> */
+    tmp = I2Cx->CR1 & I2CCR1_BC_MASK;
+    tmp |= ((uint32_t) I2CBitNum << 5U);
+
+    I2Cx->CR1 = tmp;
+}
+
+/**
+  * @brief  Reset the state of the specified I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @retval None
+  */
+void I2C_SWReset(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->CR2 & I2CCR2_SWRST_MASK;
+    I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD1;
+    I2Cx->CR2 = tmp | I2CCR2_SWRST_CMD2;
+}
+
+/**
+  * @brief  Clear I2C interrupt request in I2C mode.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @retval None
+  */
+void I2C_ClearINTReq(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxCR2<PIN> to clear request, and Set I2CxCR2<I2CM> to enable  I2C operation */
+    tmp = I2Cx->SR;
+    tmp &= (uint32_t) 0x000000E0;
+    tmp |= (I2CCR2_PIN_SET | I2CCR2_I2CM_I2C);
+    I2Cx->CR2 = tmp;
+}
+
+/**
+  * @brief  Set I2c bus to Master mode and Generate start condition in I2C mode.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @retval None
+  */
+void I2C_GenerateStart(TSB_I2C_TypeDef * I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxCR2<MST>, <TRX>, <BB> and <PIN> to generate start condition */
+    I2Cx->CR2 = I2CCR2_START_CONDITION | I2CCR2_I2CM_I2C;
+}
+
+/**
+  * @brief  Set I2c bus to Master mode and Generate stop condition in I2C mode.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @retval None
+  */
+void I2C_GenerateStop(TSB_I2C_TypeDef * I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxCR2<MST>, <TRX>, <PIN> and clear <BB> to generate stop condition */
+    I2Cx->CR2 = I2CCR2_STOP_CONDITION | I2CCR2_I2CM_I2C;
+}
+
+/**
+  * @brief  Get the I2C channel state in I2C mode
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @retval The state of the I2C channel in I2C bus.
+  */
+I2C_State I2C_GetState(TSB_I2C_TypeDef * I2Cx)
+{
+    I2C_State state;
+    state.All = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    state.All = I2Cx->SR;
+    state.All &= I2C_DATA_MASK;
+    return state;
+}
+
+/**
+  * @brief  Set data to be sent and MCU starts transmission.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @param  Data: The data to be sent, max 0xFF.
+  * @retval None
+  */
+void I2C_SetSendData(TSB_I2C_TypeDef * I2Cx, uint32_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_I2C_DATA(Data));
+
+    /* Write data into I2CxDBR */
+    I2Cx->DBR = Data;
+}
+
+/**
+  * @brief  Get data having been received.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @retval The data having been received
+  */
+uint32_t I2C_GetReceiveData(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t retval = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Save the received data */
+    retval = I2Cx->DBR;
+    retval &= I2C_DATA_MASK;
+
+    return retval;
+}
+
+/**
+  * @brief  Enable or disable I2C free data mode of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @param  NewState: New state of free data mode.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetFreeDataMode(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxI2CAR<ALS> to use free data mode transfer in I2C mode */
+        I2Cx->AR |= I2CAR_ALS_SET;
+    } else {
+        /* Clear I2CxI2CAR<ALS> to not use free data mode transfer in I2C mode */
+        I2Cx->AR &= I2CAR_ALS_CLEAR;
+    }
+}
+
+/**
+  * @brief  Get slave address match detection state.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @retval DISABLE or ENABLE.
+  */
+FunctionalState I2C_GetSlaveAddrMatchState(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+    FunctionalState retval = DISABLE;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->CR1 & I2CCR1_NOACK_MASK;
+    if (tmp == I2CCR1_NOACK_ENABLE) {
+        /* the slave address match or general call detection are enabled. */
+        retval = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+    return retval;
+}
+
+/**
+  * @brief  Set prescaler clock of the specified I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @param  PrescalerClock: the prescaler clock value.
+  *   This parameter can be one of the following values:
+  *   I2C_PRESCALER_DIV_1 to I2C_PRESCALER_DIV_32
+  * @retval None
+  */
+void I2C_SetPrescalerClock(TSB_I2C_TypeDef * I2Cx, uint32_t PrescalerClock)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Get the system clock frequency */
+    SystemCoreClockUpdate();
+
+    /* Check the prescaler clock in the range between 50ns and 150ns */
+    assert_param(IS_PRESCALER_CLK_VALID(PrescalerClock, SystemCoreClock));
+
+    /* Write prescaler clock into I2CxPRS<PRSCK> */
+    I2Cx->PRS = PrescalerClock % I2C_PRESCALER_DIV_32;
+}
+
+/**
+  * @brief  Enable or disable interrupt request of the I2C channel.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @param  NewState: Specify I2C interrupt setting.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SetINTReq(TSB_I2C_TypeDef * I2Cx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set I2CxIE<IE> to enable interrupt request */
+        I2Cx->IE |= I2CIE_IE_SET;
+    } else {
+        /* Clear I2CxIE<IE> to disable interrupt request */
+        I2Cx->IE &= I2CIE_IE_CLEAR;
+    }
+}
+
+/**
+  * @brief  Get interrupt generation state.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @retval DISABLE or ENABLE.
+  */
+FunctionalState I2C_GetINTStatus(TSB_I2C_TypeDef * I2Cx)
+{
+    uint32_t tmp = 0U;
+    FunctionalState retval = DISABLE;
+
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    tmp = I2Cx->IR & I2CIR_ISIC_MASK;
+    if (tmp == I2CIR_ISIC_SET) {
+        /* the I2C interrupt has been generated */
+        retval = ENABLE;
+    } else {
+        /* Do nothing */
+    }
+    return retval;
+}
+
+/**
+  * @brief  Clear the I2C interrupt output.
+  * @param  I2Cx: Select the I2C channel.
+  *   This parameter can be one of the following values:
+  *   TSB_I2C0,TSB_I2C1,TSB_I2C2
+  * @retval None
+  */
+void I2C_ClearINTOutput(TSB_I2C_TypeDef * I2Cx)
+{
+    /* Check the parameters */
+    assert_param(IS_I2C_PERIPH(I2Cx));
+
+    /* Set I2CxIR<ISIC> to clear the I2C interrupt output(INTI2Cx) */
+    I2Cx->IR = I2CIR_ISIC_SET;
+}
+
+/** @} */
+/* End of group I2C_Exported_Functions */
+
+/** @} */
+/* End of group I2C */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#endif                          /*   defined(__TMPM46B_I2C_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_rtc.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,1440 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_rtc.c
+ * @brief   This file provides API functions for RTC driver.
+ * @version V2.0.2.1
+ * @date    2015/02/11
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm46b_rtc.h"
+
+#if defined(__TMPM46B_RTC_H)
+
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @defgroup RTC 
+  * @brief RTC driver modules
+  * @{
+  */
+
+/** @defgroup RTC_Private_Defines
+  * @{
+  */
+
+#define PAGER_PAGE_SET         ((uint8_t)0x01)
+#define PAGER_PAGE_CLEAR       ((uint8_t)0xFE)
+#define PAGER_ADJUST_SET       ((uint8_t)0x10)
+#define PAGER_ADJUST_CLEAR     ((uint8_t)0xEF)
+#define PAGER_ENATMR_SET       ((uint8_t)0x08)
+#define PAGER_ENATMR_CLEAR     ((uint8_t)0xF7)
+#define PAGER_ENAALM_SET       ((uint8_t)0x04)
+#define PAGER_ENAALM_CLEAR     ((uint8_t)0xFB)
+#define PAGER_INTENA_SET       ((uint8_t)0x80)
+#define PAGER_INTENA_CLEAR     ((uint8_t)0x7F)
+
+#define RESTR_DIS_CLEAR        ((uint8_t)0x38)
+#define RESTR_DIS_SET          ((uint8_t)0xC7)
+#define RESTR_DIS1HZ_SET       ((uint8_t)0x80)
+#define RESTR_DIS16HZ_SET      ((uint8_t)0x40)
+#define RESTR_DIS2HZ_SET       ((uint8_t)0x04)
+#define RESTR_DIS4HZ_SET       ((uint8_t)0x02)
+#define RESTR_DIS8HZ_SET       ((uint8_t)0x01)
+#define RESTR_RSTTMR_SET       ((uint8_t)0x20)
+#define RESTR_RSTTMR_CLEAR     ((uint8_t)0xDF)
+#define RESTR_RSTALM_SET       ((uint8_t)0x10)
+#define RESTR_RSTALM_CLEAR     ((uint8_t)0xEF)
+
+#define HOURR_HO5_SET          ((uint8_t)0x20)
+#define HOURR_HO5_CLEAR        ((uint8_t)0xDF)
+
+#define MONTHR_MO0_MASK        ((uint8_t)0x01)
+
+#define RTC_PROTECT_SET        ((uint8_t)0xC1)
+#define RTC_PROTECT_CLEAR      ((uint8_t)0x3E)
+
+#define ADJCTL_AJEN_CLEAR      ((uint8_t)0xFE)
+#define ADJCTL_AJEN_SET        ((uint8_t)0x01)
+
+#define ADJCTL_AJSEL_CLEAR     ((uint8_t)0xF1)
+
+#define ADJDAT_CLEAR           ((uint16_t)0x01FF)
+#define ADJDAT_MODE_SET        ((uint16_t)0x0100)
+
+/** @} */
+/* End of group RTC_Private_Defines */
+
+
+/** @defgroup RTC_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group RTC_Private_FunctionPrototypes */
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group RTC_Private_Functions */
+
+/** @defgroup RTC_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set second value.
+  * @param  Sec: New second value, max 59
+  *   This parameter can be one of the following values:
+  *   0, 1, 2, ...59 
+  * @retval None
+  */
+void RTC_SetSec(uint8_t Sec)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_SECOND(Sec));
+
+    /* Select PAGE0 */
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+    TSB_RTC->PAGER = tmp;
+    tmp = (uint8_t) ((Sec / 10U) * 16U + Sec % 10U);
+    /* Write sec value into SECR register */
+    TSB_RTC->SECR = tmp;
+}
+
+/**
+  * @brief  Get second value.
+  * @param  None
+  * @retval The second value.
+  */
+uint8_t RTC_GetSec(void)
+{
+    uint8_t sec = 0U;
+    uint8_t tmp = 0U;
+
+    /* Select PAGE0 */
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+    TSB_RTC->PAGER = tmp;
+
+    do {
+        tmp = TSB_RTC->SECR;
+        sec = TSB_RTC->SECR;
+    }
+    while (tmp != sec);
+
+    sec = (uint8_t) ((tmp >> 4U) * 10U + tmp % 16U);
+
+    /* return second value  */
+    return sec;
+}
+
+/**
+  * @brief  Set minute value.
+  * @param  NewMode: New mode of RTC
+  *   This parameter can be one of the following values:
+  *   RTC_CLOCK_MODE, RTC_ALARM_MODE 
+  * @param  Min: New minute value, max 59
+  *   This parameter can be one of the following values:
+  *   0, 1, 2, ...59 
+  * @retval None
+  */
+void RTC_SetMin(RTC_FuncMode NewMode, uint8_t Min)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_MINUTE(Min));
+    assert_param(IS_RTC_FUNC_MODE(NewMode));
+
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+
+    if (NewMode == RTC_ALARM_MODE) {
+        /* Select PAGE1 */
+        tmp |= PAGER_PAGE_SET;
+    } else {
+        /* Select PAGE0 */
+        /* Do nothing */
+    }
+
+    TSB_RTC->PAGER = tmp;
+    tmp = (uint8_t) ((Min / 10U) * 16U + Min % 10U);
+    /* Write min value into MINR register */
+    TSB_RTC->MINR = tmp;
+}
+
+/**
+  * @brief  Get minute value.
+  * @param  NewMode: New mode of RTC
+  *   This parameter can be one of the following values:
+  *   RTC_CLOCK_MODE, RTC_ALARM_MODE 
+  * @retval The minute value.
+  */
+uint8_t RTC_GetMin(RTC_FuncMode NewMode)
+{
+    uint8_t min = 0U;
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FUNC_MODE(NewMode));
+
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+
+    if (NewMode == RTC_CLOCK_MODE) {
+        /* Select PAGE0 */
+        TSB_RTC->PAGER = tmp;
+
+        do {
+            tmp = TSB_RTC->MINR;
+            min = TSB_RTC->MINR;
+        }
+        while (tmp != min);
+
+    } else {
+        /* Select PAGE1 */
+        tmp |= PAGER_PAGE_SET;
+        TSB_RTC->PAGER = tmp;
+        tmp = TSB_RTC->MINR;
+    }
+
+    min = (uint8_t) ((tmp >> 4U) * 10U + tmp % 16U);
+
+    /* return minute value  */
+    return min;
+}
+
+/**
+  * @brief  Get AM or PM state in the 12 Hour mode.
+  * @param  NewMode: New mode of RTC
+  *   This parameter can be one of the following values:
+  *   RTC_CLOCK_MODE, RTC_ALARM_MODE
+  * @retval mode: The mode of the time.
+  *   This parameter can be one of the following values:
+  *   RTC_AM_MODE, RTC_PM_MODE 
+  */
+uint8_t RTC_GetAMPM(RTC_FuncMode NewMode)
+{
+    uint8_t tmp = 0U;
+    uint8_t mode = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FUNC_MODE(NewMode));
+
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+
+    if (NewMode == RTC_CLOCK_MODE) {
+        /* Select PAGE0 */
+        TSB_RTC->PAGER = tmp;
+
+        do {
+            tmp = TSB_RTC->HOURR;
+            mode = TSB_RTC->HOURR;
+        }
+        while (tmp != mode);
+
+    } else {
+        /* Select PAGE1 */
+        tmp |= PAGER_PAGE_SET;
+        TSB_RTC->PAGER = tmp;
+        tmp = TSB_RTC->HOURR;
+    }
+
+    tmp &= HOURR_HO5_SET;
+
+    if (tmp == HOURR_HO5_SET) {
+        mode = RTC_PM_MODE;
+    } else {
+        mode = RTC_AM_MODE;
+    }
+
+    return (mode);
+}
+
+/**
+  * @brief  Set hour value in the 24 Hour mode.
+  * @param  NewMode: New mode of RTC
+  *   This parameter can be one of the following values:
+  *   RTC_CLOCK_MODE, RTC_ALARM_MODE 
+  * @param  Hour: New hour value, max 23
+  *   This parameter can be one of the following values:
+  *   0, 1, 2, ...23 
+  * @retval None
+  */
+void RTC_SetHour24(RTC_FuncMode NewMode, uint8_t Hour)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_HOUR_24(Hour));
+    assert_param(IS_RTC_FUNC_MODE(NewMode));
+
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+
+    if (NewMode == RTC_ALARM_MODE) {
+        /* Select PAGE1 */
+        tmp |= PAGER_PAGE_SET;
+    } else {
+        /* Select PAGE0 */
+        /* Do nothing */
+    }
+
+    TSB_RTC->PAGER = tmp;
+    tmp = (uint8_t) ((Hour / 10U) * 16U + Hour % 10U);
+    /* Write hour value into HOURR register */
+    TSB_RTC->HOURR = tmp;
+
+    /* Wait for setting hour successfully */
+    while (TSB_RTC->HOURR != tmp) {
+        /* Do nothing */
+    }
+}
+
+/**
+  * @brief  Set hour value in the 12 Hour mode.
+  * @param  NewMode: New mode of RTC
+  *   This parameter can be one of the following values:
+  *   RTC_CLOCK_MODE, RTC_ALARM_MODE 
+  * @param  Hour: New hour value, max 11
+  *   This parameter can be one of the following values:
+  *   0, 1, 2, ...11
+  * @param  AmPm: New time mode
+  *   This parameter can be one of the following values:
+  *   RTC_AM_MODE or RTC_PM_MODE
+  * @retval None
+  */
+void RTC_SetHour12(RTC_FuncMode NewMode, uint8_t Hour, uint8_t AmPm)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_HOUR_12(Hour));
+    assert_param(IS_RTC_FUNC_MODE(NewMode));
+    assert_param(IS_RTC_AMPM_MODE(AmPm));
+
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+
+    if (NewMode == RTC_ALARM_MODE) {
+        /* Select PAGE1 */
+        tmp |= PAGER_PAGE_SET;
+    } else {
+        /* Select PAGE0 */
+        /* Do nothing */
+    }
+
+    TSB_RTC->PAGER = tmp;
+    tmp = (uint8_t) ((Hour / 10U) * 16U + Hour % 10U);
+
+    if (AmPm == RTC_PM_MODE) {
+        tmp |= HOURR_HO5_SET;
+    } else {
+        /* Do nothing */
+    }
+
+    /* Write hour value into HOURR register */
+    TSB_RTC->HOURR = tmp;
+
+    /* Wait for setting hour successfully */
+    while (TSB_RTC->HOURR != tmp) {
+        /* Do nothing */
+    }
+}
+
+/**
+  * @brief  Get the hour value.
+  * @param  NewMode: New mode of RTC
+  *   This parameter can be one of the following values:
+  *   RTC_CLOCK_MODE, RTC_ALARM_MODE 
+  * @retval The hour value.
+  */
+uint8_t RTC_GetHour(RTC_FuncMode NewMode)
+{
+    uint8_t HourMode = 0U;
+    uint8_t hour = 0U;
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FUNC_MODE(NewMode));
+
+    /* Get hour mode */
+    HourMode = RTC_GetHourMode();
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+
+    if (NewMode == RTC_CLOCK_MODE) {
+        /* Select PAGE0 */
+        TSB_RTC->PAGER = tmp;
+
+        /* Get hour value */
+        do {
+            tmp = TSB_RTC->HOURR;
+            hour = TSB_RTC->HOURR;
+        }
+        while (tmp != hour);
+
+    } else {
+        /* Select PAGE1 */
+        tmp |= PAGER_PAGE_SET;
+        TSB_RTC->PAGER = tmp;
+        tmp = TSB_RTC->HOURR;
+    }
+
+    if (HourMode == RTC_12_HOUR_MODE) {
+        tmp &= HOURR_HO5_CLEAR;
+    } else {
+        /* Do nothing */
+    }
+
+    hour = (uint8_t) ((tmp >> 4U) * 10U + tmp % 16U);
+
+    /* return hour value  */
+    return hour;
+}
+
+/**
+  * @brief  Set the day of the week.
+  * @param  NewMode: New mode of RTC
+  *   This parameter can be one of the following values:
+  *   RTC_CLOCK_MODE, RTC_ALARM_MODE 
+  * @param  Day: New day value
+  *   This parameter can be one of the following values:
+  *   RTC_SUN, RTC_MON, RTC_TUE, RTC_WED, RTC_THU, RTC_FRI, RTC_SAT 
+  * @retval None
+  */
+void RTC_SetDay(RTC_FuncMode NewMode, uint8_t Day)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_DAY(Day));
+    assert_param(IS_RTC_FUNC_MODE(NewMode));
+
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+
+    if (NewMode == RTC_ALARM_MODE) {
+        /* Select PAGE1 */
+        tmp |= PAGER_PAGE_SET;
+    } else {
+        /* Select PAGE0 */
+        /* Do nothing */
+    }
+
+    TSB_RTC->PAGER = tmp;
+    /* Write day value into DAYR register */
+    TSB_RTC->DAYR = Day;
+}
+
+/**
+  * @brief  Get the day of the week.
+  * @param  NewMode: New mode of RTC
+  *   This parameter can be one of the following values:
+  *   RTC_CLOCK_MODE, RTC_ALARM_MODE 
+  * @retval The day value.
+  */
+uint8_t RTC_GetDay(RTC_FuncMode NewMode)
+{
+    uint8_t day = 0U;
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FUNC_MODE(NewMode));
+
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+
+    if (NewMode == RTC_CLOCK_MODE) {
+        /* Select PAGE0 */
+        TSB_RTC->PAGER = tmp;
+
+        /* Get day value */
+        do {
+            tmp = TSB_RTC->DAYR;
+            day = TSB_RTC->DAYR;
+        }
+        while (tmp != day);
+
+    } else {
+        /* Select PAGE1 */
+        tmp |= PAGER_PAGE_SET;
+        TSB_RTC->PAGER = tmp;
+        day = TSB_RTC->DAYR;
+    }
+
+    /* return day value  */
+    return day;
+}
+
+/**
+  * @brief  Set the date value.
+  * @param  NewMode: New mode of RTC
+  *   This parameter can be one of the following values:
+  *   RTC_CLOCK_MODE, RTC_ALARM_MODE 
+  * @param  Date: New date value, Max 31
+  *   This parameter can be one of the following values:
+  *   1, 2, ...31 
+  * @retval None
+  */
+void RTC_SetDate(RTC_FuncMode NewMode, uint8_t Date)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_DATE(Date));
+    assert_param(IS_RTC_FUNC_MODE(NewMode));
+
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+
+    if (NewMode == RTC_ALARM_MODE) {
+        /* Select PAGE1 */
+        tmp |= PAGER_PAGE_SET;
+    } else {
+        /* Select PAGE0 */
+        /* Do nothing */
+    }
+
+    TSB_RTC->PAGER = tmp;
+    tmp = (uint8_t) ((Date / 10U) * 16U + Date % 10U);
+    /* Write date value into DAYR register */
+    TSB_RTC->DATER = tmp;
+}
+
+/**
+  * @brief  Get the date value.
+  * @param  NewMode: New mode of RTC
+  *   This parameter can be one of the following values:
+  *   RTC_CLOCK_MODE, RTC_ALARM_MODE 
+  * @retval The date value.
+  */
+uint8_t RTC_GetDate(RTC_FuncMode NewMode)
+{
+    uint8_t tmp = 0U;
+    uint8_t date = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_FUNC_MODE(NewMode));
+
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+
+    if (NewMode == RTC_CLOCK_MODE) {
+        /* Select PAGE0 */
+        TSB_RTC->PAGER = tmp;
+
+        /* Get date value */
+        do {
+            tmp = TSB_RTC->DATER;
+            date = TSB_RTC->DATER;
+        }
+        while (tmp != date);
+
+    } else {
+        /* Select PAGE1 */
+        tmp |= PAGER_PAGE_SET;
+        TSB_RTC->PAGER = tmp;
+        tmp = TSB_RTC->DATER;
+    }
+
+    date = (uint8_t) ((tmp >> 4U) * 10U + tmp % 16U);
+
+    /* return day value  */
+    return date;
+}
+
+/**
+  * @brief  Set the month value.
+  * @param  Month: New month value, Max 12
+  *   This parameter can be one of the following values:
+  *   1, 2, 3, ...12 
+  * @retval None
+  */
+void RTC_SetMonth(uint8_t Month)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_MONTH(Month));
+
+    /* Select PAGE0 */
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+    TSB_RTC->PAGER = tmp;
+    tmp = (uint8_t) ((Month / 10U) * 16U + Month % 10U);
+    /* Write month value into MONTHR register */
+    TSB_RTC->MONTHR = tmp;
+}
+
+/**
+  * @brief  Get the month value.
+  * @param  None
+  * @retval The month value.
+  */
+uint8_t RTC_GetMonth(void)
+{
+    uint8_t tmp = 0U;
+    uint8_t month = 0U;
+
+    /* Select PAGE0 */
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+    TSB_RTC->PAGER = tmp;
+
+    /* Get month value */
+    do {
+        tmp = TSB_RTC->MONTHR;
+        month = TSB_RTC->MONTHR;
+    }
+    while (tmp != month);
+
+    month = (uint8_t) ((tmp >> 4U) * 10U + tmp % 16U);
+
+    /* return month value */
+    return month;
+}
+
+/**
+  * @brief  Set the year value.
+  * @param  Year: New year value, Max 99
+  *   This parameter can be one of the following values:
+  *   0, 1, 2, 3, ...99
+  * @retval None
+  */
+void RTC_SetYear(uint8_t Year)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_YEAR(Year));
+
+    /* Select PAGE0 */
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+    TSB_RTC->PAGER = tmp;
+    tmp = (uint8_t) ((Year / 10U) * 16U + Year % 10U);
+    /* Write year value into YEARR register */
+    TSB_RTC->YEARR = tmp;
+}
+
+/**
+  * @brief  Get the year value.
+  * @param  None
+  * @retval The year value.
+  */
+uint8_t RTC_GetYear(void)
+{
+    uint8_t tmp = 0U;
+    uint8_t year = 0U;
+
+    /* Select PAGE0 */
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_PAGE_CLEAR;
+    TSB_RTC->PAGER = tmp;
+
+    /* Get year value */
+    do {
+        tmp = TSB_RTC->YEARR;
+        year = TSB_RTC->YEARR;
+    }
+    while (tmp != year);
+
+    year = (uint8_t) ((tmp >> 4U) * 10U + tmp % 16U);
+
+    /* return year value  */
+    return year;
+}
+
+/**
+  * @brief  Select 24-hour clock or 12-hour clock.
+  * @param  HourMode: Select 24-hour clock or 12-hour clock 
+  *   This parameter can be one of the following values:
+  *   RTC_12_HOUR_MODE, RTC_24_HOUR_MODE
+  * @retval None
+  */
+void RTC_SetHourMode(uint8_t HourMode)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_HOUR_MODE(HourMode));
+
+    /* Select PAGE1 */
+    tmp = TSB_RTC->PAGER;
+    tmp |= PAGER_PAGE_SET;
+    TSB_RTC->PAGER = tmp;
+
+    /* Set MONTHR<MO0> to select 24-hour mode/12-hour mode */
+    if (HourMode == RTC_12_HOUR_MODE) {
+        TSB_RTC->MONTHR &= RTC_12_HOUR_MODE;
+    } else {
+        TSB_RTC->MONTHR |= RTC_24_HOUR_MODE;
+    }
+}
+
+/**
+  * @brief  Get hour mode.
+  * @param  None
+  * @retval mode: The mode of the hour.
+  *   This parameter can be one of the following values:
+  *   RTC_12_HOUR_MODE, RTC_24_HOUR_MODE 
+  */
+uint8_t RTC_GetHourMode(void)
+{
+    uint8_t mode = 0U;
+
+    /* Select PAGE1 */
+    mode = TSB_RTC->PAGER;
+    mode |= PAGER_PAGE_SET;
+    TSB_RTC->PAGER = mode;
+
+    mode = TSB_RTC->MONTHR;
+    mode &= MONTHR_MO0_MASK;
+    if (mode == MONTHR_MO0_MASK) {
+        mode = RTC_24_HOUR_MODE;
+    } else {
+        mode = RTC_12_HOUR_MODE;
+    }
+
+    return (mode);
+}
+
+/**
+  * @brief  Set leap-year state.
+  * @param  LeapYear: Set leap-year 
+  *   This parameter can be one of the following values:
+  *   RTC_LEAP_YEAR_0, RTC_LEAP_YEAR_1,
+  *   RTC_LEAP_YEAR_2 or RTC_LEAP_YEAR_3 
+  * @retval None
+  */
+void RTC_SetLeapYear(uint8_t LeapYear)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_LEAP_YEAR(LeapYear));
+
+    /* Select PAGE1 */
+    tmp = TSB_RTC->PAGER;
+    tmp |= PAGER_PAGE_SET;
+    TSB_RTC->PAGER = tmp;
+
+    /* Set <LEAP1> and <LEAP0> to select leap year state */
+    TSB_RTC->YEARR = LeapYear;
+
+    /* Wait for setting leap year successfully */
+    while (TSB_RTC->YEARR != LeapYear) {
+        /* Do nothing */
+    }
+}
+
+/**
+  * @brief  Get leap-year state.
+  * @param  None 
+  * @retval The state of leap year.
+  */
+uint8_t RTC_GetLeapYear(void)
+{
+    uint8_t tmp = 0U;
+    uint8_t leapyear = 0U;
+
+    /* Select PAGE1 */
+    tmp = TSB_RTC->PAGER;
+    tmp |= PAGER_PAGE_SET;
+    TSB_RTC->PAGER = tmp;
+
+    /* Get leap year state */
+    do {
+        tmp = TSB_RTC->YEARR;
+        leapyear = TSB_RTC->YEARR;
+    }
+    while (tmp != leapyear);
+
+    /* return leap year state  */
+    return (leapyear);
+}
+
+/**
+  * @brief  Set time adjustment + or - 30 seconds.
+  * @param  None
+  * @retval None
+  */
+void RTC_SetTimeAdjustReq(void)
+{
+    uint8_t tmp = 0U;
+
+    /* Set PAGER<ADJUST> */
+    tmp = TSB_RTC->PAGER;
+    tmp |= PAGER_ADJUST_SET;
+    TSB_RTC->PAGER = tmp;
+}
+
+/**
+  * @brief  Get request state for time adjust.
+  * @param  None
+  * @retval The state of time adjustment.
+  * This parameter can be one of the following values:
+  * RTC_REQ or RTC_NO_REQ
+  */
+RTC_ReqState RTC_GetTimeAdjustReq(void)
+{
+    uint8_t tmp0 = 0U;
+    RTC_ReqState tmp1 = RTC_NO_REQ;
+
+    tmp0 = TSB_RTC->PAGER;
+    tmp0 &= PAGER_ADJUST_SET;
+
+    if (tmp0 == PAGER_ADJUST_SET) {
+        tmp1 = RTC_REQ;
+    } else {
+        tmp1 = RTC_NO_REQ;
+    }
+
+    return (tmp1);
+}
+
+/**
+  * @brief  Enable RTC clock function.
+  * @param  None
+  * @retval None
+  */
+void RTC_EnableClock(void)
+{
+    uint8_t tmp = 0U;
+
+    /* Set PAGER<ENATMR> to enable clock function */
+    tmp = TSB_RTC->PAGER;
+    tmp |= PAGER_ENATMR_SET;
+    TSB_RTC->PAGER = tmp;
+}
+
+/**
+  * @brief  Disable RTC clock function.
+  * @param  None
+  * @retval None
+  */
+void RTC_DisableClock(void)
+{
+    uint8_t tmp = 0U;
+
+    /* Clear PAGER<ENATMR> to disable clock function */
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_ENATMR_CLEAR;
+    TSB_RTC->PAGER = tmp;
+}
+
+/**
+  * @brief  Enable RTC alarm function.
+  * @param  None
+  * @retval None
+  */
+void RTC_EnableAlarm(void)
+{
+    uint8_t tmp = 0U;
+
+    /* Set PAGER<ENAALM> to enable alarm function */
+    tmp = TSB_RTC->PAGER;
+    tmp |= PAGER_ENAALM_SET;
+    TSB_RTC->PAGER = tmp;
+}
+
+/**
+  * @brief  Disable RTC alarm function.
+  * @param  None
+  * @retval None
+  */
+void RTC_DisableAlarm(void)
+{
+    uint8_t tmp = 0U;
+
+    /* Clear PAGER<ENAALM> to disable alarm function */
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_ENAALM_CLEAR;
+    TSB_RTC->PAGER = tmp;
+}
+
+/**
+  * @brief  Enable or disable INTRTC.
+  * @param  NewState: New state of RTCINT.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_SetRTCINT(FunctionalState NewState)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Set PAGER<INTENA> to enable or disable INTRTC */
+    tmp = TSB_RTC->PAGER;
+    tmp &= PAGER_INTENA_CLEAR;
+
+    if (NewState == ENABLE) {
+        tmp |= PAGER_INTENA_SET;
+    } else {
+        /* Do nothing */
+    }
+
+    TSB_RTC->PAGER = tmp;
+}
+
+/**
+  * @brief  Set output signals from ALARM pin.
+  * @param  Output: Set ALARM pin output.
+  *   This parameter can be RTC_LOW_LEVEL, RTC_PULSE_1_HZ
+  *   or RTC_PULSE_16_HZ,RTC_PULSE_2_HZ,RTC_PULSE_4_HZ,RTC_PULSE_8_HZ.
+  * @retval None
+  */
+void RTC_SetAlarmOutput(uint8_t Output)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_ALARM_OUTPUT(Output));
+
+    switch (Output) {
+    case RTC_LOW_LEVEL:
+        /* Set PAGER<ENAALM> = 1 to enable alarm function */
+        tmp = TSB_RTC->PAGER;
+        tmp |= PAGER_ENAALM_SET;
+        TSB_RTC->PAGER = tmp;
+        /* Set All DIS bits = 1  */
+        tmp = TSB_RTC->RESTR;
+        tmp &= RESTR_DIS_CLEAR;
+        tmp |= RESTR_DIS_SET;
+        TSB_RTC->RESTR = tmp;
+        break;
+    case RTC_PULSE_1_HZ:
+        /* Set PAGER<ENAALM> = 0 to disable alarm function */
+        tmp = TSB_RTC->PAGER;
+        tmp &= PAGER_ENAALM_CLEAR;
+        TSB_RTC->PAGER = tmp;
+        /* Set RESTR<DIS1HZ> = 0 and others DIS bit = 1  */
+        tmp = TSB_RTC->RESTR;
+        tmp &= RESTR_DIS_CLEAR;
+        tmp |= (uint8_t) (RESTR_DIS16HZ_SET | RESTR_DIS2HZ_SET);
+        tmp |= (uint8_t) (RESTR_DIS4HZ_SET | RESTR_DIS8HZ_SET);
+        TSB_RTC->RESTR = tmp;
+        break;
+    case RTC_PULSE_16_HZ:
+        /* Set PAGER<ENAALM> = 0 to disable alarm function */
+        tmp = TSB_RTC->PAGER;
+        tmp &= PAGER_ENAALM_CLEAR;
+        TSB_RTC->PAGER = tmp;
+        /* Set RESTR<DIS16HZ> = 0 and others DIS bit = 1 */
+        tmp = TSB_RTC->RESTR;
+        tmp &= RESTR_DIS_CLEAR;
+        tmp |= (uint8_t) (RESTR_DIS1HZ_SET | RESTR_DIS2HZ_SET);
+        tmp |= (uint8_t) (RESTR_DIS4HZ_SET | RESTR_DIS8HZ_SET);
+        TSB_RTC->RESTR = tmp;
+        break;
+    case RTC_PULSE_2_HZ:
+        /* Set PAGER<ENAALM> = 0 to disable alarm function */
+        tmp = TSB_RTC->PAGER;
+        tmp &= PAGER_ENAALM_CLEAR;
+        TSB_RTC->PAGER = tmp;
+        /* Set RESTR<DIS2HZ> = 0 and others DIS bit = 1  */
+        tmp = TSB_RTC->RESTR;
+        tmp &= RESTR_DIS_CLEAR;
+        tmp |= (uint8_t) (RESTR_DIS16HZ_SET | RESTR_DIS1HZ_SET);
+        tmp |= (uint8_t) (RESTR_DIS4HZ_SET | RESTR_DIS8HZ_SET);
+        TSB_RTC->RESTR = tmp;
+        break;
+    case RTC_PULSE_4_HZ:
+        /* Set PAGER<ENAALM> = 0 to disable alarm function */
+        tmp = TSB_RTC->PAGER;
+        tmp &= PAGER_ENAALM_CLEAR;
+        TSB_RTC->PAGER = tmp;
+        /* Set RESTR<DIS4HZ> = 0 and others DIS bit = 1 */
+        tmp = TSB_RTC->RESTR;
+        tmp &= RESTR_DIS_CLEAR;
+        tmp |= (uint8_t) (RESTR_DIS16HZ_SET | RESTR_DIS2HZ_SET);
+        tmp |= (uint8_t) (RESTR_DIS1HZ_SET | RESTR_DIS8HZ_SET);
+        TSB_RTC->RESTR = tmp;
+        break;
+    case RTC_PULSE_8_HZ:
+        /* Set PAGER<ENAALM> = 0 to disable alarm function */
+        tmp = TSB_RTC->PAGER;
+        tmp &= PAGER_ENAALM_CLEAR;
+        TSB_RTC->PAGER = tmp;
+        /* Set RESTR<DIS8HZ> = 0 and others DIS bit = 1  */
+        tmp = TSB_RTC->RESTR;
+        tmp &= RESTR_DIS_CLEAR;
+        tmp |= (uint8_t) (RESTR_DIS16HZ_SET | RESTR_DIS2HZ_SET);
+        tmp |= (uint8_t) (RESTR_DIS4HZ_SET | RESTR_DIS1HZ_SET);
+        TSB_RTC->RESTR = tmp;
+        break;
+    default:
+        /* Do nothing */
+        break;
+    }
+}
+
+/**
+  * @brief  Reset alarm function.
+  * @param  None
+  * @retval None
+  */
+void RTC_ResetAlarm(void)
+{
+    uint8_t tmp = 0U;
+
+    /* Set RESTR<RSTALM> = 1 to reset alarm */
+    tmp = TSB_RTC->RESTR;
+    tmp &= RESTR_RSTALM_CLEAR;
+    tmp |= RESTR_RSTALM_SET;
+    TSB_RTC->RESTR = tmp;
+}
+
+/**
+  * @brief  Reset RTC clock second counter.
+  * @param  None
+  * @retval None
+  */
+void RTC_ResetClockSec(void)
+{
+    uint8_t tmp = 0U;
+
+    /* Set RESTR<RSTTMR> = 1 to reset clock sec counter */
+    tmp = TSB_RTC->RESTR;
+    tmp &= RESTR_RSTTMR_CLEAR;
+    tmp |= RESTR_RSTTMR_SET;
+    TSB_RTC->RESTR = tmp;
+}
+
+/**
+  * @brief  Get request state for reset RTC clock second counter.
+  * @param  None
+  * @retval The state of reset clock request.
+  * This parameter can be one of the following values:
+  * RTC_REQ or RTC_NO_REQ
+  */
+RTC_ReqState RTC_GetResetClockSecReq(void)
+{
+    uint8_t tmp0 = 0U;
+    RTC_ReqState tmp1 = RTC_NO_REQ;
+
+    tmp0 = TSB_RTC->RESTR;
+    tmp0 &= RESTR_RSTTMR_SET;
+
+    if (tmp0 == RESTR_RSTTMR_SET) {
+        tmp1 = RTC_REQ;
+    } else {
+        tmp1 = RTC_NO_REQ;
+    }
+
+    return (tmp1);
+}
+
+/**
+  * @brief  Set the RTC date.
+  * @param  DateStruct: The structure containing basic Date configuration.
+  * @retval None
+  */
+void RTC_SetDateValue(RTC_DateTypeDef * DateStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(DateStruct));
+    assert_param(IS_RTC_LEAP_YEAR(DateStruct->LeapYear));
+    assert_param(IS_RTC_YEAR(DateStruct->Year));
+    assert_param(IS_RTC_MONTH(DateStruct->Month));
+    assert_param(IS_RTC_DATE(DateStruct->Date));
+    assert_param(IS_RTC_DAY(DateStruct->Day));
+
+    /* Set LeapYear */
+    RTC_SetLeapYear(DateStruct->LeapYear);
+    /* Set year value */
+    RTC_SetYear(DateStruct->Year);
+    /* Set month value */
+    RTC_SetMonth(DateStruct->Month);
+    /* Set date value */
+    RTC_SetDate(RTC_CLOCK_MODE, DateStruct->Date);
+    /* Set day value */
+    RTC_SetDay(RTC_CLOCK_MODE, DateStruct->Day);
+}
+
+/**
+  * @brief  Get the RTC date.
+  * @param  DateStruct: The structure containing basic Date configuration will be modified.
+  * @retval None
+  */
+void RTC_GetDateValue(RTC_DateTypeDef * DateStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(DateStruct));
+
+    /* Get LeapYear */
+    DateStruct->LeapYear = RTC_GetLeapYear();
+    /* Get year value */
+    DateStruct->Year = RTC_GetYear();
+    /* Get month value */
+    DateStruct->Month = RTC_GetMonth();
+    /* Get date value */
+    DateStruct->Date = RTC_GetDate(RTC_CLOCK_MODE);
+    /* Get day value */
+    DateStruct->Day = RTC_GetDay(RTC_CLOCK_MODE);
+}
+
+/**
+  * @brief  Set the RTC time.
+  * @param  TimeStruct: The structure containing basic Time configuration.
+  * @retval None
+  */
+void RTC_SetTimeValue(RTC_TimeTypeDef * TimeStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(TimeStruct));
+    assert_param(IS_RTC_HOUR_MODE(TimeStruct->HourMode));
+
+    if (TimeStruct->HourMode) {
+        assert_param(IS_RTC_HOUR_24(TimeStruct->Hour));
+    } else {
+        assert_param(IS_RTC_HOUR_12(TimeStruct->Hour));
+        assert_param(IS_RTC_AMPM_MODE(TimeStruct->AmPm));
+    }
+
+    assert_param(IS_RTC_MINUTE(TimeStruct->Min));
+    assert_param(IS_RTC_SECOND(TimeStruct->Sec));
+
+    /* Set hour mode */
+    RTC_SetHourMode(TimeStruct->HourMode);
+
+    /* Set hour value */
+    if (TimeStruct->HourMode == RTC_24_HOUR_MODE) {
+        RTC_SetHour24(RTC_CLOCK_MODE, TimeStruct->Hour);
+    } else {
+        RTC_SetHour12(RTC_CLOCK_MODE, TimeStruct->Hour, TimeStruct->AmPm);
+    }
+
+    /* Set minute value */
+    RTC_SetMin(RTC_CLOCK_MODE, TimeStruct->Min);
+    /* Set second value */
+    RTC_SetSec(TimeStruct->Sec);
+}
+
+/**
+  * @brief  Get the RTC time.
+  * @param  TimeStruct: The structure containing basic Time configuration will be modified.
+  * @retval None
+  */
+void RTC_GetTimeValue(RTC_TimeTypeDef * TimeStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(TimeStruct));
+
+    /* Get hour mode */
+    TimeStruct->HourMode = RTC_GetHourMode();
+    /* Get hour value */
+    TimeStruct->Hour = RTC_GetHour(RTC_CLOCK_MODE);
+
+    if (TimeStruct->HourMode == RTC_12_HOUR_MODE) {
+        /* Get AM/PM mode */
+        TimeStruct->AmPm = RTC_GetAMPM(RTC_CLOCK_MODE);
+    } else {
+        TimeStruct->AmPm = RTC_AMPM_INVALID;
+    }
+
+    /* Get minute value */
+    TimeStruct->Min = RTC_GetMin(RTC_CLOCK_MODE);
+    /* Get second value */
+    TimeStruct->Sec = RTC_GetSec();
+}
+
+/**
+  * @brief  Set the RTC date and time.
+  * @param  DateStruct: The structure containing basic Date configuration.
+  * @param  TimeStruct: The structure containing basic Time configuration.
+  * @retval None
+  */
+void RTC_SetClockValue(RTC_DateTypeDef * DateStruct, RTC_TimeTypeDef * TimeStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(DateStruct));
+    assert_param(IS_POINTER_NOT_NULL(TimeStruct));
+    assert_param(IS_RTC_LEAP_YEAR(DateStruct->LeapYear));
+    assert_param(IS_RTC_YEAR(DateStruct->Year));
+    assert_param(IS_RTC_MONTH(DateStruct->Month));
+    assert_param(IS_RTC_DATE(DateStruct->Date));
+    assert_param(IS_RTC_DAY(DateStruct->Day));
+    assert_param(IS_RTC_HOUR_MODE(TimeStruct->HourMode));
+
+    if (TimeStruct->HourMode == RTC_24_HOUR_MODE) {
+        assert_param(IS_RTC_HOUR_24(TimeStruct->Hour));
+    } else {
+        assert_param(IS_RTC_HOUR_12(TimeStruct->Hour));
+        assert_param(IS_RTC_AMPM_MODE(TimeStruct->AmPm));
+    }
+
+    assert_param(IS_RTC_MINUTE(TimeStruct->Min));
+    assert_param(IS_RTC_SECOND(TimeStruct->Sec));
+
+    /* Set hour mode */
+    RTC_SetHourMode(TimeStruct->HourMode);
+
+    /* Set hour value */
+    if (TimeStruct->HourMode == RTC_24_HOUR_MODE) {
+        RTC_SetHour24(RTC_CLOCK_MODE, TimeStruct->Hour);
+    } else {
+        RTC_SetHour12(RTC_CLOCK_MODE, TimeStruct->Hour, TimeStruct->AmPm);
+    }
+
+    /* Set minute value */
+    RTC_SetMin(RTC_CLOCK_MODE, TimeStruct->Min);
+    /* Set second value */
+    RTC_SetSec(TimeStruct->Sec);
+
+    /* Set LeapYear */
+    RTC_SetLeapYear(DateStruct->LeapYear);
+    /* Set year value */
+    RTC_SetYear(DateStruct->Year);
+    /* Set month value */
+    RTC_SetMonth(DateStruct->Month);
+    /* Set date value */
+    RTC_SetDate(RTC_CLOCK_MODE, DateStruct->Date);
+    /* Set day value */
+    RTC_SetDay(RTC_CLOCK_MODE, DateStruct->Day);
+}
+
+/**
+  * @brief  Get the RTC date and time.
+  * @param  DateStruct: The structure containing basic Date configuration will be modified.
+  * @param  TimeStruct: The structure containing basic Time configuration will be modified.
+  * @retval None
+  */
+void RTC_GetClockValue(RTC_DateTypeDef * DateStruct, RTC_TimeTypeDef * TimeStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(DateStruct));
+    assert_param(IS_POINTER_NOT_NULL(TimeStruct));
+
+    /* Get LeapYear */
+    DateStruct->LeapYear = RTC_GetLeapYear();
+    /* Get year value */
+    DateStruct->Year = RTC_GetYear();
+    /* Get month value */
+    DateStruct->Month = RTC_GetMonth();
+    /* Get date value */
+    DateStruct->Date = RTC_GetDate(RTC_CLOCK_MODE);
+    /* Get day value */
+    DateStruct->Day = RTC_GetDay(RTC_CLOCK_MODE);
+    /* Get hour mode */
+    TimeStruct->HourMode = RTC_GetHourMode();
+    /* Get hour value */
+    TimeStruct->Hour = RTC_GetHour(RTC_CLOCK_MODE);
+
+    if (TimeStruct->HourMode == RTC_12_HOUR_MODE) {
+        /* Get AM/PM mode */
+        TimeStruct->AmPm = RTC_GetAMPM(RTC_CLOCK_MODE);
+    } else {
+        TimeStruct->AmPm = RTC_AMPM_INVALID;
+    }
+
+    /* Get minute value */
+    TimeStruct->Min = RTC_GetMin(RTC_CLOCK_MODE);
+    /* Get second value */
+    TimeStruct->Sec = RTC_GetSec();
+}
+
+/**
+  * @brief  Set the RTC alarm date and time.
+  * @param  AlarmStruct: The structure containing basic alarm configuration.
+  * @retval None
+  */
+void RTC_SetAlarmValue(RTC_AlarmTypeDef * AlarmStruct)
+{
+    uint8_t HourMode;
+    HourMode = RTC_GetHourMode();
+
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(AlarmStruct));
+    assert_param(IS_RTC_DATE(AlarmStruct->Date));
+    assert_param(IS_RTC_DAY(AlarmStruct->Day));
+
+    if (HourMode == RTC_24_HOUR_MODE) {
+        assert_param(IS_RTC_HOUR_24(AlarmStruct->Hour));
+    } else {
+        assert_param(IS_RTC_HOUR_12(AlarmStruct->Hour));
+        assert_param(IS_RTC_AMPM_MODE(AlarmStruct->AmPm));
+    }
+
+    assert_param(IS_RTC_MINUTE(AlarmStruct->Min));
+
+    /* Set date value */
+    RTC_SetDate(RTC_ALARM_MODE, AlarmStruct->Date);
+    /* Set day value */
+    RTC_SetDay(RTC_ALARM_MODE, AlarmStruct->Day);
+
+    /* Set hour value */
+    if (HourMode == RTC_12_HOUR_MODE) {
+        RTC_SetHour12(RTC_ALARM_MODE, AlarmStruct->Hour, AlarmStruct->AmPm);
+    } else {
+        RTC_SetHour24(RTC_ALARM_MODE, AlarmStruct->Hour);
+    }
+
+    /* Set minute value */
+    RTC_SetMin(RTC_ALARM_MODE, AlarmStruct->Min);
+}
+
+/**
+  * @brief  Get the RTC alarm date and time.
+  * @param  AlarmStruct: The structure containing basic alarm configuration will be modified.
+  * @retval None
+  */
+void RTC_GetAlarmValue(RTC_AlarmTypeDef * AlarmStruct)
+{
+    uint8_t HourMode;
+
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(AlarmStruct));
+
+    HourMode = RTC_GetHourMode();
+
+    /* Get date value */
+    AlarmStruct->Date = RTC_GetDate(RTC_ALARM_MODE);
+    /* Get day value */
+    AlarmStruct->Day = RTC_GetDay(RTC_ALARM_MODE);
+    /* Get hour value */
+    AlarmStruct->Hour = RTC_GetHour(RTC_ALARM_MODE);
+
+    if (HourMode == RTC_12_HOUR_MODE) {
+        /* Get AM/PM mode */
+        AlarmStruct->AmPm = RTC_GetAMPM(RTC_ALARM_MODE);
+    } else {
+        AlarmStruct->AmPm = RTC_AMPM_INVALID;
+    }
+
+    /* Get minute value */
+    AlarmStruct->Min = RTC_GetMin(RTC_ALARM_MODE);
+}
+
+/**
+  * @brief  Enable or disable Clock correction function register protection
+  * @param  NewState: New state of the RTC protect register
+  *   This parameter can be one of the following values:
+  *   DISABLE or ENABLE
+  * @retval None
+  */
+void RTC_SetProtectCtrl(FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Set RTCPROTECT */
+    if (NewState == ENABLE) {
+        TSB_RTC->PROTECT = RTC_PROTECT_SET;
+    } else {
+        TSB_RTC->PROTECT = RTC_PROTECT_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable RTC correction function.
+  * @param  None
+  * @retval None
+  */
+void RTC_EnableCorrection(void)
+{
+    uint8_t tmp = 0U;
+
+    /* Set RTCADJCTL<AJEN> to enable correction function */
+    tmp = TSB_RTC->ADJCTL;
+    tmp |= ADJCTL_AJEN_SET;
+    TSB_RTC->ADJCTL = tmp;
+}
+
+/**
+  * @brief  Disable RTC correction function.
+  * @param  None
+  * @retval None
+  */
+void RTC_DisableCorrection(void)
+{
+    uint8_t tmp = 0U;
+
+    /* Clear RTCADJCTL<AJEN> to disable correction function */
+    tmp = TSB_RTC->ADJCTL;
+    tmp &= ADJCTL_AJEN_CLEAR;
+    TSB_RTC->ADJCTL = tmp;
+}
+
+/**
+  * @brief  Set correction reference time.
+  * @param  Time: Correction reference time
+  *   This parameter can be one of following values:
+  *   RTC_ADJ_TIME_1_SEC, RTC_ADJ_TIME_10_SEC, 
+  *   RTC_ADJ_TIME_20_SEC, RTC_ADJ_TIME_30_SEC,
+  *   RTC_ADJ_TIME_1_MIN
+  * @retval None
+  */
+void RTC_SetCorrectionTime(uint8_t Time)
+{
+    uint8_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_ADJ_TIME(Time));
+
+    /* Set RTCADJCTL<AJSEL> */
+    tmp = TSB_RTC->ADJCTL;
+    tmp &= ADJCTL_AJSEL_CLEAR;
+    tmp |= Time;
+    TSB_RTC->ADJCTL = tmp;
+}
+
+/**
+  * @brief  Set correction value.
+  * @param  Mode: The mode of correction 
+  *   This parameter can be one of following values:
+  *   RTC_CORRECTION_PLUS, RTC_CORRECTION_MINUS
+  * @param  Cnt:The value of correction
+  *   This parameter can be 0~255 when Mode is RTC_CORRECTION_PLUS.
+  *   This parameter can be 1~256 when Mode is RTC_CORRECTION_MINUS.
+  * @retval None
+  */
+void RTC_SetCorrectionValue(RTC_CorrectionMode Mode, uint16_t Cnt)
+{
+    uint16_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_RTC_CORRECTION_MODE(Mode));
+    if (Mode == RTC_CORRECTION_PLUS) {
+        /* Check the parameters */
+        assert_param(IS_RTC_PLUS_VALUE(Cnt));
+
+        /* Set RTCADJDAT<ADJDAT> */
+        TSB_RTC->ADJDAT = Cnt;
+    } else {
+        /* Check the parameters */
+        assert_param(IS_RTC_MINUS_VALUE(Cnt));
+
+        /* Set RTCADJDAT<ADJDAT> */
+        tmp = ADJDAT_MODE_SET;
+        tmp |= (~(Cnt - 1U));
+        tmp &= ADJDAT_CLEAR;
+        TSB_RTC->ADJDAT = tmp;
+    }
+}
+
+/** @} */
+/* End of group RTC_Exported_Functions */
+
+/** @} */
+/* End of group RTC */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+#endif                          /* defined(__TMPM46B_RTC_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_ssp.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,661 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_ssp.c
+ * @brief   This file provides API functions for SSP driver.
+ * @version V2.0.2.1
+ * @date    2015/02/05
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ ******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm46b_ssp.h"
+
+#if defined(__TMPM46B_SSP_H)
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @defgroup SSP
+  * @brief SSP driver modules
+  * @{
+  */
+
+/** @defgroup SSP_Private_Defines
+  * @{
+  */
+
+#define SSP_ENABLE_SET                 ((uint32_t)0x00000002)
+#define SSP_CR1_MASK                   ((uint32_t)0x0000000F)
+#define SSP_ENABLE_CLEAR               ((uint32_t)0x0000000D)
+
+#define SSP_SCR_MASK                   ((uint32_t)0x000000FF)
+#define SSP_FORMAT_MASK                ((uint32_t)0x0000FFCF)
+#define SSP_SPO_MASK                   ((uint32_t)0x0000FFBF)
+#define SSP_SPH_MASK                   ((uint32_t)0x0000FF7F)
+#define SSP_DSS_MASK                   ((uint32_t)0x0000FFF0)
+#define SSP_SOD_SET                    ((uint32_t)0x00000008)
+#define SSP_SOD_CLEAR                  ((uint32_t)0x00000007)
+
+#define SSP_MS_SETSLAVE                ((uint32_t)0x00000004)
+#define SSP_MS_MASK                    ((uint32_t)0x0000000B)
+
+#define SSP_LBM_SET                    ((uint32_t)0x00000001)
+#define SSP_LBM_CLEAR                  ((uint32_t)0x0000000E)
+
+#define SSP_BSY_MASK                   ((uint32_t)0x00000010)
+
+#define SSP_TXFIFO_SR_MASK             ((uint32_t)0x00000003)
+#define SSP_RXFIFO_SR_MASK             ((uint32_t)0x0000000C)
+
+#define SSP_IMSC_MASK                  ((uint32_t)0x0000000F)
+#define SSP_RIS_MASK                   ((uint32_t)0x0000000F)
+#define SSP_MIS_MASK                   ((uint32_t)0x0000000F)
+
+#define SSP_DMA_MASK                   ((uint32_t)0x00000003)
+
+#define SSP_TXFIFO_FULL       0U
+#define SSP_TXFIFO_INVALID    1U
+#define SSP_TXFIFO_NORMAL     2U
+#define SSP_TXFIFO_EMPTY      3U
+
+#define SSP_RXFIFO_FULL       3U
+#define SSP_RXFIFO_INVALID    2U
+#define SSP_RXFIFO_NORMAL     1U
+#define SSP_RXFIFO_EMPTY      0U
+
+/** @} */
+/* End of group SSP_Private_Defines */
+
+/** @defgroup SSP_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group SSP_Private_FunctionPrototypes */
+
+/** @defgroup SSP_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group SSP_Private_Functions */
+
+/** @defgroup SSP_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief Enable the specified SSP channel
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @retval None
+  */
+void SSP_Enable(TSB_SSP_TypeDef * SSPx)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+
+    /* Set SSPxCR1<SSE> to enable SSP module */
+    tmp = SSPx->CR1 & SSP_CR1_MASK;
+    tmp |= SSP_ENABLE_SET;
+    SSPx->CR1 = tmp;
+}
+
+/**
+  * @brief Disable the specified SSP channel
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @retval None
+  */
+void SSP_Disable(TSB_SSP_TypeDef * SSPx)
+{
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+
+    /* Clear SSPxCR1<SSE> to disable SSP module */
+    SSPx->CR1 &= SSP_ENABLE_CLEAR;
+}
+
+/**
+  * @brief Initialize the specified SSP channel through the data in structure SSP_InitTypeDef
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param  InitStruct:  Parameters to configure SSP module,
+  *   It includes data to set Frame Format, Clock prescale divider, Clock Rate,Clock Phase and Polarity, DataSize and Mode.
+  * @retval None
+  */
+void SSP_Init(TSB_SSP_TypeDef * SSPx, SSP_InitTypeDef * InitStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_POINTER_NOT_NULL(InitStruct));
+
+    SSP_SetFrameFormat(SSPx, InitStruct->FrameFormat);
+    SSP_SetClkPreScale(SSPx, InitStruct->PreScale, InitStruct->ClkRate);
+    SSP_SetClkPolarity(SSPx, InitStruct->ClkPolarity);
+    SSP_SetClkPhase(SSPx, InitStruct->ClkPhase);
+    SSP_SetDataSize(SSPx, InitStruct->DataSize);
+    SSP_SetMSMode(SSPx, InitStruct->Mode);
+}
+
+/**
+  * @brief Set the bit rate for transmit and receive for the specified SSP channel.
+  *   BitRate = fSYS / (PreScale x (1 + ClkRate))
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param  PreScale: Clock prescale divider(even number from 2 to 254)
+  * @param  ClkRate: Serial clock rate (From 0 to 255)
+  * @retval None
+  */
+void SSP_SetClkPreScale(TSB_SSP_TypeDef * SSPx, uint8_t PreScale, uint8_t ClkRate)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_SSP_PRE_SCALE(PreScale));
+
+    /* Set serial clock rate */
+    tmp = SSPx->CR0 & SSP_SCR_MASK;
+    tmp |= (((uint32_t) ClkRate) << 8U);
+    SSPx->CR0 = tmp;
+
+    /* Set clock prescale divider */
+    SSPx->CPSR = (uint32_t) PreScale;
+}
+
+/**
+  * @brief Specify the Frame Format of specified SSP channel.
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param  FrameFormat: Frame Format of SSP
+  *   This parameter can be one of the following values:
+  *   SSP_FORMAT_SPI,
+  *   SSP_FORMAT_SSI,
+  *   SSP_FORMAT_MICROWIRE
+  * @retval None
+  */
+void SSP_SetFrameFormat(TSB_SSP_TypeDef * SSPx, SSP_FrameFormat FrameFormat)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_SSP_FRAME_FORMAT(FrameFormat));
+    
+    /* Set Frame Format */
+    tmp = SSPx->CR0 & SSP_FORMAT_MASK;
+    tmp |= (((uint32_t) FrameFormat) << 4U);
+    SSPx->CR0 = tmp;
+}
+
+/**
+  * @brief When specified SSP channel is configured as SPI mode, specify the clock polarity in its idle state.
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param  ClkPolarity: SPI clock polarity
+  *  This parameter can be one of the following values:
+  *   SSP_POLARITY_LOW,
+  *   SSP_POLARITY_HIGH
+  * @retval None
+  */
+void SSP_SetClkPolarity(TSB_SSP_TypeDef * SSPx, SSP_ClkPolarity ClkPolarity)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_SSP_CLK_POLARITY(ClkPolarity));
+    
+    /* Set clock polarity */
+    tmp = SSPx->CR0 & SSP_SPO_MASK;
+    tmp |= (((uint32_t) ClkPolarity) << 6U);
+    SSPx->CR0 = tmp;
+}
+
+/**
+  * @brief When specified SSP channel is configured as SPI mode, specify its clock phase.
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param  ClkPolarity: SPI clock phase
+  *   This parameter can be one of the following values:
+  *   SSP_PHASE_FIRST_EDGE : To captures serial data on the first clock transition of a frame.
+  *   SSP_PHASE_SECOND_EDGE : To captures serial data on the second clock transition of a frame
+  * @retval None
+  */
+void SSP_SetClkPhase(TSB_SSP_TypeDef * SSPx, SSP_ClkPhase ClkPhase)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_SSP_CLK_PHASE(ClkPhase));
+    
+    /* Set clock phase */
+    tmp = SSPx->CR0 & SSP_SPH_MASK;
+    tmp |= (((uint32_t) ClkPhase) << 7U);
+    SSPx->CR0 = tmp;
+}
+
+/**
+  * @brief Set the Rx/Tx data size for the specified SSP channel.
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param  DataSize: Data size select. From 4 to 16
+  * @retval None
+  */
+void SSP_SetDataSize(TSB_SSP_TypeDef * SSPx, uint8_t DataSize)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_SSP_DATA_BIT_SIZE(DataSize));
+    
+    /* Set Rx/Tx Data Size */
+    tmp = SSPx->CR0 & SSP_DSS_MASK;
+    tmp |= ((uint32_t) DataSize - 1U);
+    SSPx->CR0 = tmp;
+}
+
+/**
+  * @brief Enable/Disable slave mode, SPDO pin output for the specified SSP channel.
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param  NewState: New state of slave mode output setting.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void SSP_SetSlaveOutputCtrl(TSB_SSP_TypeDef * SSPx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Read SFR(Special Function Register)then clear other bits, also clear SSPxCR1<SOD>), bit3 as enable it */
+    tmp = SSPx->CR1 & SSP_SOD_CLEAR;
+    
+    /* Set SSPxCR1<SOD>, bit3 */
+    if (NewState == DISABLE) {
+        tmp |= SSP_SOD_SET;
+    } else {
+        /* Do nothing */
+    }
+
+    SSPx->CR1 = tmp;
+}
+
+/**
+  * @brief Select Master or Slave mode for the specified SSP channel.
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param  Mode: SSP device mode
+  *   This parameter can be SSP_MASTER or SSP_SLAVE.
+  * @retval None
+  */
+void SSP_SetMSMode(TSB_SSP_TypeDef * SSPx, SSP_MS_Mode Mode)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_SSP_MS_MODE(Mode));
+
+    /* Read SFR(Special Function Register)then clear other bits, also clear(SSPxCR1<MS>), bit2 as select master mode */
+    tmp = SSPx->CR1 & SSP_MS_MASK;
+    
+    /* Set SSPxCR1<MS>, bit2 */
+    if (Mode == SSP_SLAVE) {
+        tmp |= SSP_MS_SETSLAVE;
+    } else {
+        /* Do nothing */
+    }
+
+    SSPx->CR1 = tmp;
+}
+
+/**
+  * @brief Set loop back mode for the specified SSP channel.
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param  NewState: New state of loop back mode.
+  *   This parameter can be one of the following values:
+  *   ENABLE,
+  *   DISABLE
+  * @retval None
+  */
+void SSP_SetLoopBackMode(TSB_SSP_TypeDef * SSPx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    /* Read SFR(Special Function Register)then clear other bits, also clear (SSPxCR1<LBM>), bit0 as disable it */
+    tmp = SSPx->CR1 & SSP_LBM_CLEAR;
+    
+    /* Set SSPxCR1<LBM>, bit0 */
+    if (NewState == ENABLE) {
+        tmp |= SSP_LBM_SET;
+    } else {
+        /* Do nothing */
+    }
+
+    SSPx->CR1 = tmp;
+}
+
+/**
+  * @brief Set the data to be sent into Tx FIFO of the specified SSP channel.
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param  Data: the 4~16bit data to be send
+  * @retval None
+  */
+void SSP_SetTxData(TSB_SSP_TypeDef * SSPx, uint16_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+
+    SSPx->DR = (uint32_t) Data;
+}
+
+/**
+  * @brief Read the data received from Rx FIFO of the specified SSP channel.
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @retval The 4~16bit data received from FIFO.
+  */
+uint16_t SSP_GetRxData(TSB_SSP_TypeDef * SSPx)
+{
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+
+    return ((uint16_t) (SSPx->DR));
+}
+
+/**
+  * @brief Get the Busy or Idle state of the specified SSP channel
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @retval The state of SSP, which can be BUSY or DONE
+  */
+WorkState SSP_GetWorkState(TSB_SSP_TypeDef * SSPx)
+{
+    WorkState tmp = DONE;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+
+    /* Check the bit 'BSY'(bit4) of register SSPSR, */
+    /* 1 == busy, 0 == idle or done */
+    if ((SSPx->SR & SSP_BSY_MASK) == SSP_BSY_MASK) {
+        tmp = BUSY;
+    } else {
+        /* Do nothing */
+    }
+
+    return tmp;
+}
+
+/**
+  * @brief Get the Rx/Tx FIFO state of the specified SSP channel
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param Direction: the communication direction which will be check.
+  *   This parameter can be one of the following values:
+  *   SSP_TX
+      SSP_RX
+  * @retval The state of Rx/Tx FIFO,
+  *   This parameter can be one of the following values:
+  *   SSP_FIFO_EMPTY   : FIFO is empty
+  *   SSP_FIFO_NORMAL  : FIFO is not full and not empty
+  *   SSP_FIFO_INVALID : FIFO is invalid state
+  *   SSP_FIFO_FULL    : FIFO is full
+  */
+SSP_FIFOState SSP_GetFIFOState(TSB_SSP_TypeDef * SSPx, SSP_Direction Direction)
+{
+    uint32_t src = 0U;
+    SSP_FIFOState tgt = SSP_FIFO_EMPTY;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_SSP_DIRECTION(Direction));
+
+    src = SSPx->SR;
+    if (Direction == SSP_TX) {
+        src &= SSP_TXFIFO_SR_MASK;
+        switch (src) {
+        case SSP_TXFIFO_FULL:
+            tgt = SSP_FIFO_FULL;
+            break;
+        case SSP_TXFIFO_INVALID:
+            tgt = SSP_FIFO_INVALID;
+            break;
+        case SSP_TXFIFO_NORMAL:
+            tgt = SSP_FIFO_NORMAL;
+            break;
+        case SSP_TXFIFO_EMPTY:
+            tgt = SSP_FIFO_EMPTY;
+            break;
+        default:
+            /* Do nothing */
+            break;
+        }
+    } else {
+        src &= SSP_RXFIFO_SR_MASK;
+        src >>= 2U;
+        switch (src) {
+        case SSP_RXFIFO_FULL:
+            tgt = SSP_FIFO_FULL;
+            break;
+        case SSP_RXFIFO_INVALID:
+            tgt = SSP_FIFO_INVALID;
+            break;
+        case SSP_RXFIFO_NORMAL:
+            tgt = SSP_FIFO_NORMAL;
+            break;
+        case SSP_RXFIFO_EMPTY:
+            tgt = SSP_FIFO_EMPTY;
+            break;
+        default:
+            /* Do nothing */
+            break;
+        }
+    }
+
+    return tgt;
+}
+
+/**
+  * @brief Enable/Disable interrupt source of the specified SSP channel
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param INTSrc: The interrupt source for SSP to be enable or disable.
+  *     To disable all interrupt source,use the parameter:
+  *             SSP_INTCFG_NONE
+  *     To enable the interrupt one by one, use the "OR" operation with below parameter:
+  *             SSP_INTCFG_RX_OVERRUN  Receive overrun interrupt
+  *             SSP_INTCFG_RX_TIMEOUT  Receive timeout interrupt
+  *             SSP_INTCFG_RX          Receive FIFO interrupt(at least half full)
+  *             SSP_INTCFG_TX          Transmit FIFO interrupt(at least half empty)
+  *     To enable all the 4 interrupt above together, use the parameter:
+  *             SSP_INTCFG_ALL
+  * @retval None
+  */
+void SSP_SetINTConfig(TSB_SSP_TypeDef * SSPx, uint32_t IntSrc)
+{
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_SSP_INT_SRC(IntSrc));
+
+    SSPx->IMSC = IntSrc & SSP_IMSC_MASK;
+}
+
+/**
+  * @brief Get the Enable/Disable mask setting for each Interrupt source in the specified SSP channel
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @retval A data with union SSP_INTState type.
+  */
+SSP_INTState SSP_GetINTConfig(TSB_SSP_TypeDef * SSPx)
+{
+    SSP_INTState state = { 0U };
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+
+    state.All = SSPx->IMSC & SSP_IMSC_MASK;
+
+    return state;
+}
+
+/**
+  * @brief Get the SSP pre-enable interrupt status of the specified SSP channel.  
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @retval A data with union SSP_INTState type.
+  */
+SSP_INTState SSP_GetPreEnableINTState(TSB_SSP_TypeDef * SSPx)
+{
+    SSP_INTState state = { 0U };
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+
+    state.All = SSPx->RIS & SSP_RIS_MASK;
+
+    return state;
+}
+
+/**
+  * @brief Get the SSP post-enable interrupt status of the specified SSP channel.( after masked)
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @retval A data with union SSP_INTState type.
+  */
+SSP_INTState SSP_GetPostEnableINTState(TSB_SSP_TypeDef * SSPx)
+{
+    SSP_INTState state = { 0U };
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+
+    state.All = SSPx->MIS & SSP_MIS_MASK;
+
+    return state;
+}
+
+/**
+  * @brief Clear interrupt flag of specified SSP channel by writing '1' to correspond bit.
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param INTSrc: The interrupt source to be cleared.
+  *   This parameter can be one of the following values:
+  *   SSP_INTCFG_RX_OVERRUN  Receive overrun interrupt
+  *   SSP_INTCFG_RX_TIMEOUT  Receive timeout interrupt
+  *   SSP_INTCFG_ALL         All interrupt flags above
+  * @retval None
+  */
+void SSP_ClearINTFlag(TSB_SSP_TypeDef * SSPx, uint32_t IntSrc)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_SSP_CLEAR_INT_SRC(IntSrc));
+
+    if (IntSrc == SSP_INTCFG_RX_OVERRUN) {
+        tmp = 1U;
+    } else if (IntSrc == SSP_INTCFG_RX_TIMEOUT) {
+        tmp = 2U;
+    } else {
+        tmp = 3U;
+    }
+
+    SSPx->ICR = tmp;
+}
+
+/**
+  * @brief Enable/Disable the Rx/Tx DMA FIFO of the specified SSP channel
+  * @param SSPx: Select the SSP channel.
+  *   This parameter can be one of the following values:
+  *   TSB_SSP0, TSB_SSP1, TSB_SSP2
+  * @param Direction: The Direction of SSP,
+  *   This parameter can be one of the following values:
+  *   SSP_RX,
+  *   SSP_TX
+  * @param  NewState: New state of DMA FIFO Rx/Tx.
+  *   This parameter can be one of the following values:
+  *   ENABLE,
+  *   DISABLE
+  * @retval None
+  */
+void SSP_SetDMACtrl(TSB_SSP_TypeDef * SSPx, SSP_Direction Direction, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+    uint32_t tmpDMASet = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_SSP_PERIPH(SSPx));
+    assert_param(IS_SSP_DIRECTION(Direction));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (Direction == SSP_RX) {
+        /* Bit0 is for Rx */
+        tmp = 1U;
+    } else {
+        /* Bit1 is for Tx */
+        tmp = 2U;
+    }
+
+    /* Read, then clear all bits except bit0 and bit1  */
+    tmpDMASet = SSPx->DMACR & SSP_DMA_MASK;
+
+    if (NewState == ENABLE) {
+        tmpDMASet |= tmp;
+    } else {
+        /* Disable, clear bit */
+        tmpDMASet &= ((uint32_t) ~tmp & SSP_DMA_MASK);
+    }
+
+    SSPx->DMACR = tmpDMASet;
+}
+
+/** @} */
+/* End of group SSP_Exported_Functions */
+
+/** @} */
+/* End of group SSP */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#endif                          /* defined(__TMPM46B_SSP_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_tmrb.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,547 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_tmrb.c
+ * @brief   This file provides API functions for TMRB driver.
+ * @version V2.0.2.1
+ * @date    2015/02/27
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm46b_tmrb.h"
+
+#if defined(__TMPM46B_TMRB_H)
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @defgroup TMRB
+  * @brief TMRB driver modules
+  * @{
+  */
+
+/** @defgroup TMRB_Private_Defines
+  * @{
+  */
+
+#define EN_TBEN_SET            ((uint32_t)0x00000080)
+#define EN_TBEN_CLEAR          ((uint32_t)0xFFFFFF7F)
+
+#define MPT_TIMER_MODE         ((uint32_t)0xFFFFFFFE)
+
+#define CR_I2TB_SET            ((uint32_t)0x00000008)
+#define CR_I2TB_CLEAR          ((uint32_t)0xFFFFFFF7)
+#define CR_TBSYNC_SET          ((uint32_t)0x00000020)
+#define CR_TBSYNC_CLEAR        ((uint32_t)0xFFFFFFDF)
+#define CR_TBWBF_SET           ((uint32_t)0x00000080)
+#define CR_TBWBF_CLEAR         ((uint32_t)0xFFFFFF7F)
+#define CR_CSSEL_SET           ((uint32_t)0x00000001)
+#define CR_CSSEL_CLEAR         ((uint32_t)0xFFFFFFFE)
+#define CR_TRGSEL_CLEAR        ((uint32_t)0xFFFFFFBD)
+
+#define MOD_CLK_CLE_CLEAR_MPT  ((uint32_t)0xFFFFFFF8)
+#define MOD_CLK_CLE_CLEAR_TMRB ((uint32_t)0xFFFFFFF0)
+#define MOD_TBCPM_CLEAR_MPT    ((uint32_t)0xFFFFFFE7)
+#define MOD_TBCPM_CLEAR_TMRB   ((uint32_t)0xFFFFF8FF)
+#define MOD_TBCP_CLEAR_MPT     ((uint32_t)0xFFFFFFDF)
+#define MOD_TBCP_CLEAR_TMRB    ((uint32_t)0xFFFFFFBF)
+#define MOD_TBRSWR_CLEAR       ((uint32_t)0xFFFFFFBF)
+
+#define TB_ST_MASK             ((uint32_t)0x00000007)
+
+/** @} */
+/* End of group TMRB_Private_Defines */
+
+/** @defgroup TMRB_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group TMRB_Private_FunctionPrototypes */
+
+/** @defgroup TMRB_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group TMRB_Private_Functions */
+
+/** @defgroup TMRB_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified TMRB channel.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @retval None
+  */
+void TMRB_Enable(TSB_TB_TypeDef * TBx)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    /* Clear MPTxEN<MTMODE> to Timer mode */
+    if ((TBx == TSB_TB_MPT0) || (TBx == TSB_TB_MPT1) || (TBx == TSB_TB_MPT2) || (TBx == TSB_TB_MPT3)) {
+        TBx->EN &= MPT_TIMER_MODE;
+    } else {
+        /* Do nothing */
+    }
+    /* Set TBxEN<TBEN> to enable TBx */
+    TBx->EN |= EN_TBEN_SET;
+}
+
+/**
+  * @brief  Disable the specified TMRB channel.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @retval None
+  */
+void TMRB_Disable(TSB_TB_TypeDef * TBx)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    /* Clear TBxEN<TBEN> to disable TBx */
+    TBx->EN &= EN_TBEN_CLEAR;
+}
+
+
+/**
+  * @brief  Start or stop counter of the specified TMRB channel.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  Cmd: The command for the counter.
+  *   This parameter can be TMRB_RUN or TMRB_STOP.
+  * @retval None
+  */
+void TMRB_SetRunState(TSB_TB_TypeDef * TBx, uint32_t Cmd)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_CMD(Cmd));
+
+    /* Write command into RUN register */
+    TBx->RUN = Cmd;
+}
+
+/**
+  * @brief  Initialize the specified TMRB channel.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  InitStruct: The structure containing basic TMRB configuration.
+  * @retval None
+  */
+void TMRB_Init(TSB_TB_TypeDef * TBx, TMRB_InitTypeDef * InitStruct)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(InitStruct));
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_MODE(InitStruct->Mode));
+    assert_param(IS_TMRB_VALUE(InitStruct->TrailingTiming));
+    assert_param(IS_TMRB_VALUE(InitStruct->LeadingTiming));
+    assert_param(IS_VALID_LEADING(InitStruct->LeadingTiming, InitStruct->TrailingTiming));
+    tmp = TBx->MOD;
+
+    if ((TBx == TSB_TB_MPT0) || (TBx == TSB_TB_MPT1) || (TBx == TSB_TB_MPT2) || (TBx == TSB_TB_MPT3)) {
+        assert_param(IS_MPT_CLK_DIV(InitStruct->ClkDiv));
+        assert_param(IS_MPT_UC_CTRL(InitStruct->UpCntCtrl));
+        tmp &= MOD_CLK_CLE_CLEAR_MPT;
+    } else {
+        assert_param(IS_TMRB_CLK_DIV(InitStruct->ClkDiv));
+        assert_param(IS_TMRB_UC_CTRL(InitStruct->UpCntCtrl));
+        tmp &= MOD_CLK_CLE_CLEAR_TMRB;
+    }
+
+    if (InitStruct->Mode != 0U) {
+        /* Use internal clock, set the prescaler */
+        tmp |= InitStruct->ClkDiv;
+    } else {
+        /* Use external clock */
+        /* Do nothing */
+    }
+    /* Set up-counter running mode */
+    tmp |= InitStruct->UpCntCtrl;
+    TBx->MOD = tmp;
+
+    /* Write leading-timing into RG0 */
+    TBx->RG0 = InitStruct->LeadingTiming;
+
+    /* Write trailing-timing into RG1 */
+    TBx->RG1 = InitStruct->TrailingTiming;
+}
+
+/**
+  * @brief  Configure the capture timing and up-counter clearing timing.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  CaptureTiming: Specify TMRB capture timing.
+  *    This parameter can be one of the following values:
+  *    TBx = TSB_TB_MPT0 or TSB_TB_MPT1 or TSB_TB_MPT2 or TSB_TB_MPT3:
+  *    MPT_DISABLE_CAPTURE, MPT_CAPTURE_IN_RISING, MPT_CAPTURE_IN_RISING_FALLING.
+  *    TBx = TSB_TB0 to TSB_TB3:
+  *    TMRB_DISABLE_CAPTURE, TMRB_CAPTURE_TBIN0_RISING_FALLING,
+  *    TMRB_CAPTURE_TBFF0_EDGE.
+  *    TBx = TSB_TB4 to TSB_TB7:
+  *    TMRB_DISABLE_CAPTURE, TMRB_CAPTURE_TBIN0_TBIN1_RISING, 
+  *    TMRB_CAPTURE_TBIN0_RISING_FALLING, TMRB_CAPTURE_TBFF0_EDGE,
+  *    TMRB_CLEAR_TBIN1_RISING, TMRB_CAPTURE_TBIN0_RISING_CLEAR_TBIN1_RISING.
+  * @retval None
+  */
+void TMRB_SetCaptureTiming(TSB_TB_TypeDef * TBx, uint32_t CaptureTiming)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+
+    /* Configure capture timing */
+    if ((TBx == TSB_TB_MPT0) || (TBx == TSB_TB_MPT1) || (TBx == TSB_TB_MPT2) || (TBx == TSB_TB_MPT3)) {
+        assert_param(IS_MPT_CAPTURE_TIMING(CaptureTiming));
+        tmp = TBx->MOD & MOD_TBCPM_CLEAR_MPT;
+    } else {
+        if ((TBx == TSB_TB0) || (TBx == TSB_TB1) || (TBx == TSB_TB2) || (TBx == TSB_TB3)) {
+            assert_param(IS_TMRB_CAPTURE_TIMING_NONE_TBIN1(CaptureTiming));
+        } else {
+            assert_param(IS_TMRB_CAPTURE_TIMING_ALL(CaptureTiming));
+        }
+        tmp = TBx->MOD & MOD_TBCPM_CLEAR_TMRB;
+    }
+    tmp |= CaptureTiming;
+    TBx->MOD = tmp;
+}
+
+/**
+  * @brief  Configure the flip-flop function.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param FFStruct: The structure containing TMRB flip-flop configuration
+  * @retval None
+  */
+void TMRB_SetFlipFlop(TSB_TB_TypeDef * TBx, TMRB_FFOutputTypeDef * FFStruct)
+{
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(FFStruct));
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_FLIPFLOP_CTRL(FFStruct->FlipflopCtrl));
+    assert_param(IS_TMRB_FLIPFLOP_TRG(FFStruct->FlipflopReverseTrg));
+
+    /* Configure the flip-flop function of TBx */
+    TBx->FFCR = (FFStruct->FlipflopCtrl | FFStruct->FlipflopReverseTrg);
+}
+
+/**
+  * @brief  Indicate what causes the interrupt.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @retval The interrupt factor of TBx.
+  */
+TMRB_INTFactor TMRB_GetINTFactor(TSB_TB_TypeDef * TBx)
+{
+    TMRB_INTFactor retval;
+
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+
+    retval.All = 0U;
+    retval.All = TBx->ST & TB_ST_MASK;
+    return retval;
+}
+
+/**
+  * @brief  Mask some TMRB interrupt.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  INTMask: Select the mask of TMRB interrupt.
+  *   This parameter can be one of the following values:
+  *   TMRB_NO_INT_MASK, TMRB_MASK_MATCH_LEADING_INT, TMRB_MASK_MATCH_TRAILING_INT,
+  *   TMRB_MASK_OVERFLOW_INT, TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT,
+  *   TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_OVERFLOW_INT,
+  *   TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT,
+  *   TMRB_MASK_MATCH_LEADING_INT | TMRB_MASK_MATCH_TRAILING_INT | TMRB_MASK_OVERFLOW_INT.
+  * @retval None
+  */
+void TMRB_SetINTMask(TSB_TB_TypeDef * TBx, uint32_t INTMask)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_INT_MASK(INTMask));
+
+    /* Mask the specified interrupt */
+    TBx->IM = INTMask;
+}
+
+/**
+  * @brief  Change leadingtiming value of TBx.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  LeadingTiming: New leadingtiming value, max 0xFFFF.
+  * @retval None
+  */
+void TMRB_ChangeLeadingTiming(TSB_TB_TypeDef * TBx, uint32_t LeadingTiming)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_VALUE(LeadingTiming));
+    assert_param(IS_VALID_LEADING(LeadingTiming, TBx->RG1));
+
+    /* Write leadingtiming into RG0 */
+    TBx->RG0 = LeadingTiming;
+}
+
+/**
+  * @brief  Change trailingtiming value of TBx.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  TrailingTiming: New trailingtiming value, max 0xFFFF.
+  * @retval None
+  */
+void TMRB_ChangeTrailingTiming(TSB_TB_TypeDef * TBx, uint32_t TrailingTiming)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_VALUE(TrailingTiming));
+    assert_param(IS_VALID_LEADING(TBx->RG0, TrailingTiming));
+
+    /* Write trailingtiming into RG1 */
+    TBx->RG1 = TrailingTiming;
+}
+
+/**
+  * @brief  Get up-counter value of TBx.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @retval Up-counter value of TBx
+  */
+uint16_t TMRB_GetUpCntValue(TSB_TB_TypeDef * TBx)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+
+    /* Return up-counter value */
+    return (uint16_t) TBx->UC;
+}
+
+/**
+  * @brief  Get TMRB capture value of TBx.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  CapReg: Select the capture register to read.
+  *   This parameter can be: TMRB_CAPTURE_0 or TMRB_CAPTURE_1.
+  * @retval Capture value of TBx
+  */
+uint16_t TMRB_GetCaptureValue(TSB_TB_TypeDef * TBx, uint8_t CapReg)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_CAPTURE_REG(CapReg));
+
+    return CapReg ? (uint16_t) TBx->CP1 : (uint16_t) TBx->CP0;
+}
+
+/**
+  * @brief  Capture counter by software and take them into capture register 0.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @retval None
+  */
+void TMRB_ExecuteSWCapture(TSB_TB_TypeDef * TBx)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+
+    /* Set software capture */
+
+    if ((TBx == TSB_TB_MPT0) || (TBx == TSB_TB_MPT1) || (TBx == TSB_TB_MPT2) || (TBx == TSB_TB_MPT3)) {
+        TBx->MOD &= MOD_TBCP_CLEAR_MPT;
+    } else {
+        TBx->MOD &= MOD_TBCP_CLEAR_TMRB;
+    }
+}
+
+/**
+  * @brief  Enable or disable TMRB when system is in idle mode.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  NewState: New state of TMRB in system idle mode.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TMRB_SetIdleMode(TSB_TB_TypeDef * TBx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set TBxCR<I2TB> to enable TBx in system idle mode */
+        TBx->CR |= CR_I2TB_SET;
+    } else {
+        /* Clear TBxCR<I2TB> to disable TBx in system idle mode */
+        TBx->CR &= CR_I2TB_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable the synchronous mode of specified TMRB channel.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB5, TSB_TB6, TSB_TB7.
+  * @param  NewState: New state of TBx synchronous mode.
+  *   This parameter can be ENABLE or DISABLE.
+  * @retval None
+  */
+void TMRB_SetSyncMode(TSB_TB_TypeDef * TBx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_SYNC_PERIPH(TBx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set TBxCR<TBSYNC> to make TBx running in synchronous mode */
+        TBx->CR |= CR_TBSYNC_SET;
+    } else {
+        /* Clear TBxCR<TBSYNC> to make TBx running in individual mode */
+        TBx->CR &= CR_TBSYNC_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable double buffer of TBx and set the timing to write to timer register.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  NewState: New state of TBx double buffer.
+  *   This parameter can be ENABLE or DISABLE.
+  * @param  WriteRegMode: Timing to write to timer register.
+  *   This parameter can be TMRB_WRITE_REG_SEPARATE or TMRB_WRITE_REG_SIMULTANEOUS.
+  * @retval None
+  */
+void TMRB_SetDoubleBuf(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t WriteRegMode)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_TMRB_WRITE_REG_MODE(WriteRegMode));
+
+    if (NewState == ENABLE) {
+        /* Set TBxCR<TBWBF> to enable TBx double buffer */
+        TBx->CR |= CR_TBWBF_SET;
+        if ((TBx == TSB_TB_MPT0) || (TBx == TSB_TB_MPT1) || (TBx == TSB_TB_MPT2) || (TBx == TSB_TB_MPT3)) {
+            /* Write timer register timing */
+            tmp = TBx->MOD & MOD_TBRSWR_CLEAR;
+            tmp |= (uint32_t) WriteRegMode;
+            TBx->MOD = tmp;
+        } else {
+            /* Do nothing */
+        }
+    } else {
+        /* Clear TBxCR<TBWBF> to disable TBx double buffer */
+        TBx->CR &= CR_TBWBF_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable external trigger to start count and set the active edge.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  NewState: New state of external trigger.
+  *   This parameter can be ENABLE or DISABLE.
+  * @param  TrgMode: Active edge of the external trigger signal.
+  *   This parameter can be TMRB_TRG_EDGE_RISING or TMRB_TRG_EDGE_FALLING.
+  * @retval None
+  */
+void TMRB_SetExtStartTrg(TSB_TB_TypeDef * TBx, FunctionalState NewState, uint8_t TrgMode)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+    assert_param(IS_TMRB_TRG_EDGE(TrgMode));
+
+    if (NewState == ENABLE) {
+        /* Set TBxCR<CSSEL> to choose external trigger */
+        TBx->CR |= CR_CSSEL_SET;
+    } else {
+        /* Clear TBxCR<CSSEL> to choose software start */
+        TBx->CR &= CR_CSSEL_CLEAR;
+    }
+
+    /* external trigger selection */
+    tmp = TBx->CR & CR_TRGSEL_CLEAR;
+    tmp |= (uint32_t) TrgMode;
+    TBx->CR = tmp;
+}
+
+/**
+  * @brief  Enable or disable clock operation during debug HALT.
+  * @param  TBx: Select the TMRB channel.
+  *   This parameter can be one of the following values:
+  *   TSB_TB0, TSB_TB1, TSB_TB2, TSB_TB3, TSB_TB4, TSB_TB5, TSB_TB6, TSB_TB7,
+  *   TSB_TB_MPT0, TSB_TB_MPT1, TSB_TB_MPT2, TSB_TB_MPT3.
+  * @param  ClkState: Timer state in HALT mode.
+  *   This parameter can be TMRB_RUNNING_IN_CORE_HALT or TMRB_STOP_IN_CORE_HALT.
+  * @retval None
+  */
+void TMRB_SetClkInCoreHalt(TSB_TB_TypeDef * TBx, uint8_t ClkState)
+{
+    /* Check the parameters */
+    assert_param(IS_TMRB_ALL_PERIPH(TBx));
+    assert_param(IS_TMRB_CLK_IN_CORE_HALT(ClkState));
+
+    if (ClkState == TMRB_STOP_IN_CORE_HALT) {
+        /* Set TBEN<TBHALT> */
+        TBx->EN |= (uint32_t) TMRB_STOP_IN_CORE_HALT;
+    } else {
+        /* Clear TBEN<TBHALT> */
+        TBx->EN &= ~(uint32_t) TMRB_STOP_IN_CORE_HALT;
+    }
+}
+
+/** @} */
+/* End of group TMRB_Exported_Functions */
+
+/** @} */
+/* End of group TMRB */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#endif                          /* defined(__TMPM46B_TMRB_H) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/src/tmpm46b_uart.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,1148 @@
+/**
+ *******************************************************************************
+ * @file    tmpm46b_uart.c
+ * @brief   This file provides API functions for UART driver.
+ * @version V2.0.2.1
+ * @date    2015/02/26
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "tmpm46b_uart.h"
+
+#if defined(__TMPM46B_UART_H)
+/** @addtogroup TX04_Periph_Driver
+  * @{
+  */
+
+/** @defgroup UART
+  * @brief UART driver modules
+  * @{
+  */
+
+/** @defgroup UART_Private_Defines
+  * @{
+  */
+#define EN_SIOE_SET            ((uint32_t)0x00000001)
+#define EN_SIOE_CLEAR          ((uint32_t)0xFFFFFFFE)
+#define EN_BRCKSEL_MASK        ((uint32_t)0xFFFFFFFD)
+
+#define CR_PARITY_MASK         ((uint32_t)0x0000779F)
+#define CR_ERROR_MASK          ((uint32_t)0x0000001C)
+#define CR_OERR_FLAG           ((uint8_t)0x10)
+#define CR_PERR_FLAG           ((uint8_t)0x08)
+#define CR_FERR_FLAG           ((uint8_t)0x04)
+#define CR_IOC_MASK            ((uint32_t)0x000077FE)
+#define CR_SCLKS_MASK          ((uint32_t)0x000077FD)
+#define CR_TIDLE_MASK          ((uint32_t)0x000074FF)
+#define CR_TXDEMP_MASK         ((uint32_t)0x000073FF)
+#define CR_EHOLD_MASK          ((uint32_t)0x000007FF)
+
+#define MOD0_CTSE_MASK         ((uint32_t)0x000000BF)
+#define MOD0_RXE_CLEAR         ((uint32_t)0x000000DF)
+#define MOD0_WU_SET            ((uint32_t)0x00000010)
+#define MOD0_WU_CLEAR          ((uint32_t)0x000000EF)
+#define MOD0_SM_MASK           ((uint32_t)0x000000F3)
+#define MOD0_SC_MASK           ((uint32_t)0x000000FC)
+#define MOD0_SC_BRG            ((uint32_t)0x00000001)
+
+#define MOD1_I2SC_SET          ((uint32_t)0x00000080)
+#define MOD1_I2SC_CLEAR        ((uint32_t)0x0000007F)
+#define MOD1_TXE_CLEAR         ((uint32_t)0x000000EF)
+#define MOD1_CLEAR             ((uint32_t)0x000000FE)
+#define MOD1_FDPX_CLEAR        ((uint32_t)0x0000009F)
+#define MOD1_SINT_MASK         ((uint32_t)0x000000F1)
+
+#define MOD2_BUF_MASK          ((uint32_t)0x000000C0)
+#define MOD2_TBEMP_FLAG        ((uint8_t)0x80)
+#define MOD2_RBFLL_FLAG        ((uint8_t)0x40)
+#define MOD2_SBLEN_MASK        ((uint32_t)0x000000EF)
+#define MOD2_DRCHG_MASK        ((uint32_t)0x000000F7)
+#define MOD2_WBUF_SET          ((uint32_t)0x00000004)
+#define MOD2_WBUF_MASK         ((uint32_t)0x000000FB)
+#define MOD2_SWRST_MASK        ((uint32_t)0x000000FC)
+#define MOD2_SWRST_CMD1        ((uint32_t)0x00000002)
+#define MOD2_SWRST_CMD2        ((uint32_t)0x00000001)
+
+#define BRCR_BRADDE_SET        ((uint32_t)0x00000040)
+#define BRCR_BRCK_MASK         ((uint32_t)0x000000CF)
+#define BRCR_BRS_MASK          ((uint32_t)0x000000F0)
+#define BRCR_CLEAR             ((uint32_t)0x0000007F)
+
+#define BRADD_BRK_MASK         ((uint32_t)0x00000000)
+
+#define FCNF_BIT567_CLEAR      ((uint32_t)0x0000001F)
+#define FCNF_RFST_CLEAR        ((uint32_t)0x000000EF)
+#define FCNF_TFIE_SET          ((uint32_t)0x00000008)
+#define FCNF_TFIE_CLEAR        ((uint32_t)0x00000017)
+#define FCNF_RFIE_SET          ((uint32_t)0x00000004)
+#define FCNF_RFIE_CLEAR        ((uint32_t)0x0000001B)
+#define FCNF_RXTXCNT_SET       ((uint32_t)0x00000002)
+#define FCNF_RXTXCNT_CLEAR     ((uint32_t)0x0000001D)
+#define FCNF_CNFG_SET          ((uint32_t)0x00000001)
+#define FCNF_CNFG_CLEAR        ((uint32_t)0x0000001E)
+
+#define RFC_4B_RIL_CLEAR       ((uint32_t)0x000000FC)
+#define TFC_4B_TIL_CLEAR       ((uint32_t)0x000001FC)
+#define RFC_RFIS_CLEAR         ((uint32_t)0x000000BF)
+#define TFC_TFIS_CLEAR         ((uint32_t)0x000001BF)
+#define TRFC_TRFCS_SET         ((uint32_t)0x00000080)
+#define TFC_TBCLR_SET          ((uint32_t)0x00000100)
+
+#define TRXST_TUR_ROR_MASK     ((uint32_t)0x00000080)
+#define TRXST_4B_TRLVL_MASK    ((uint32_t)0x00000007)
+
+
+/** @} */
+/* End of group UART_Private_Defines */
+
+/** @defgroup UART_Private_FunctionPrototypes
+  * @{
+  */
+
+/** @} */
+/* End of group UART_Private_FunctionPrototypes */
+
+/** @defgroup UART_Private_Functions
+  * @{
+  */
+
+/** @} */
+/* End of group UART_Private_Functions */
+
+/** @defgroup UART_Exported_Functions
+  * @{
+  */
+
+/**
+  * @brief  Enable the specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval None
+  */
+void UART_Enable(TSB_SC_TypeDef * UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    /* Set SCxEN<SIOE> to enable UARTx */
+    UARTx->EN |= EN_SIOE_SET;
+}
+
+/**
+  * @brief  Disable the specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval None
+  */
+void UART_Disable(TSB_SC_TypeDef * UARTx)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    /* Clear SCxEN<SIOE> to disable UARTx */
+    UARTx->EN &= EN_SIOE_CLEAR;
+}
+
+/**
+  * @brief  Indicate whether the transfer buffer is full or not.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  Direction: Select the direction of transfer.
+  *   This parameter can be UART_RX or UART_TX.
+  * @retval The transfer buffer status.
+  *   The value returned can be one of the followings:
+  *   BUSY or DONE.
+  */
+WorkState UART_GetBufState(TSB_SC_TypeDef * UARTx, uint8_t Direction)
+{
+    uint8_t tmp = 0U;
+    WorkState retval = BUSY;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_TRX(Direction));
+
+    tmp = ((uint8_t) (UARTx->MOD2 & MOD2_BUF_MASK));
+    switch (Direction) {
+    case UART_TX:
+        if ((tmp & MOD2_TBEMP_FLAG) == MOD2_TBEMP_FLAG) {
+            /* Return Tx buffer empty if the flag is set */
+            retval = DONE;
+        } else {
+            /* Do nothing */
+        }
+        break;
+    case UART_RX:
+        if ((tmp & MOD2_RBFLL_FLAG) == MOD2_RBFLL_FLAG) {
+            /* Return Rx buffer full if the flag is set */
+            retval = DONE;
+        } else {
+            /* Do nothing */
+        }
+        break;
+    default:        
+        /* Do nothing */
+        break;
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Reset the specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval None
+  */
+void UART_SWReset(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    /* Write software-reset command */
+    tmp = UARTx->MOD2;
+    tmp &= MOD2_SWRST_MASK;
+    UARTx->MOD2 = tmp | MOD2_SWRST_CMD1;
+    tmp &= MOD2_SWRST_MASK;
+    UARTx->MOD2 = tmp | MOD2_SWRST_CMD2;
+}
+
+/**
+  * @brief  Initialize the specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  InitStruct: The structure containing basic UART configuration.
+  * @retval None
+  * @note UART_SetInputClock need to use before UART_Init.
+  */
+void UART_Init(TSB_SC_TypeDef * UARTx, UART_InitTypeDef * InitStruct)
+{
+    uint32_t T0 = 0U;
+    uint32_t T = 0U;
+    uint32_t t = 0U;
+    uint32_t N = 0U;
+    uint32_t K = 0U;
+    uint32_t tmp = 0U;
+    uint32_t divider = 0U;
+    const uint32_t a = 1U;
+    const uint32_t b = 4U;
+
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(InitStruct));
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_BAUDRATE(InitStruct->BaudRate));
+    assert_param(IS_UART_DATA_BITS(InitStruct->DataBits));
+    assert_param(IS_UART_STOPBITS(InitStruct->StopBits));
+    assert_param(IS_UART_PARITY(InitStruct->Parity));
+    assert_param(IS_UART_MODE(InitStruct->Mode));
+    assert_param(IS_UART_FLOW_CONTROL(InitStruct->FlowCtrl));
+
+    /* Configure the flow control */
+    tmp = UARTx->MOD0;
+    tmp &= MOD0_SM_MASK;
+    tmp &= MOD0_CTSE_MASK;
+    tmp &= MOD0_SC_MASK;
+    tmp |= (InitStruct->DataBits | InitStruct->FlowCtrl);
+    /* Use baud rate generator */
+    tmp |= MOD0_SC_BRG;
+    UARTx->MOD0 = tmp;
+
+    /* Set the stop bit */
+    tmp = UARTx->MOD2;
+    tmp &= MOD2_SBLEN_MASK;
+    tmp |= InitStruct->StopBits;
+    tmp |= MOD2_WBUF_SET;
+    UARTx->MOD2 = tmp;
+
+    /* Enable or disable parity check */
+    tmp = UARTx->CR;
+    tmp &= CR_PARITY_MASK;
+    tmp |= InitStruct->Parity;
+    UARTx->CR = tmp;
+
+    /* Get the peripheral I/O clock frequency */
+    SystemCoreClockUpdate();
+
+    T0 = SystemCoreClock / (a << ((TSB_CG->SYSCR >> 8U) & 7U));
+    if (UARTx->EN & (0x1U << 1)) {
+        /* Do nothing */
+    } else {
+        T0 /= 2U;
+    }
+    /* Baud rate setting */
+    while ((divider < 200U) || (divider > 1600U)) {
+        if (t == 0U) {
+            T = 1U;
+        } else {
+            if (T < 128U) {
+                T = T * b;
+            } else {
+                /* Do nothing */
+            }
+        }
+        divider = (100U * (T0 >> 4U)) / (InitStruct->BaudRate * T);
+        t++;
+    }
+    N = divider / 100U;
+    tmp = UARTx->BRCR;
+    if ((divider - (N * 100U)) == 0) {
+        tmp &= ~BRCR_BRADDE_SET;
+    } else {
+        tmp |= BRCR_BRADDE_SET;
+    }
+    tmp &= BRCR_BRCK_MASK;
+    tmp &= BRCR_BRS_MASK;
+    tmp |= (((t - 1U) & 3U) << 4U);
+    tmp |= (N & 0x0FU);
+    tmp &= BRCR_CLEAR;
+    UARTx->BRCR = tmp;
+    if ((divider - (N * 100U)) == 0) {
+        /* Do nothing */
+    } else {
+        K = (16U * (100U - (divider - (N * 100U)))) / 100U;
+        if (K < 1U) {
+            K = 1U;
+        } else {
+            /* Do nothing */
+        }
+        tmp = UARTx->BRADD;
+        tmp &= BRADD_BRK_MASK;
+        tmp |= (K & 0x0FU);
+        UARTx->BRADD = tmp;
+    }
+
+    tmp = UARTx->MOD1;
+    /* Enable or disable transmission or reception */
+    switch (InitStruct->Mode) {
+    case UART_ENABLE_RX:
+        UARTx->MOD0 |= InitStruct->Mode;
+        tmp &= MOD1_TXE_CLEAR;
+        break;
+    case UART_ENABLE_TX:
+        UARTx->MOD0 &= MOD0_RXE_CLEAR;
+        while ((UARTx->MOD0 & 0x20U) != 0){
+            /* Wait until MOD0<RXE> is cleared */
+        }
+        tmp |= InitStruct->Mode;
+        break;
+    default:
+        UARTx->MOD0 |= UART_ENABLE_RX;
+        tmp |= UART_ENABLE_TX;
+        break;
+    }
+    tmp &= MOD1_CLEAR;
+    UARTx->MOD1 = tmp;
+}
+
+/**
+  * @brief  Get received data of the specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval The received data
+  */
+uint32_t UART_GetRxData(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t retval = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    /* Return received data */
+    retval = (UARTx->CR & 0x80U) << 1U;
+    retval = retval | (UARTx->BUF & 0xFFU);
+
+    return retval;
+}
+
+/**
+  * @brief  Set data to be sent and start transmitting via the specified
+      UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  Data: the data to be sent.
+  * @retval None
+  */
+void UART_SetTxData(TSB_SC_TypeDef * UARTx, uint32_t Data)
+{
+    uint32_t tmp = UARTx->MOD0 & 0x7FU;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_DATA(Data));
+
+    /* Write MSB to SCxMOD0<TB8> at first if in 9-bit mode */
+    tmp |= ((Data & 0x100U) >> 1U);
+    UARTx->MOD0 = tmp;
+
+    UARTx->BUF = Data & 0xFFU;
+}
+
+/**
+  * @brief  Initialize the specified UART channel in default configuration.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval None
+  */
+void UART_DefaultConfig(TSB_SC_TypeDef * UARTx)
+{
+    UART_InitTypeDef uartdefault;
+    uartdefault.BaudRate = 115200U;
+    uartdefault.DataBits = UART_DATA_BITS_8;
+    uartdefault.StopBits = UART_STOP_BITS_1;
+    uartdefault.Parity = UART_NO_PARITY;
+    uartdefault.Mode = UART_ENABLE_RX | UART_ENABLE_TX;
+    uartdefault.FlowCtrl = UART_NONE_FLOW_CTRL;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    /* Enable the selected UART channel */
+    UART_Enable(UARTx);
+    /* Select baud rate generator as UART source clock */
+    /* Set baud rate as 115200bps */
+    /* Select 8-bit UART mode */
+    /* Select 1-bit stop */
+    /* No parity check */
+    /* No flow control */
+    /* Enable both transmission and reception */
+    UART_Init(UARTx, &uartdefault);
+}
+
+/**
+  * @brief  Indicate UART transfer error.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval The error flag.
+  *   The value returned can be one of the followings:
+  *   UART_NO_ERR, UART_OVERRUN, UART_PARITY_ERR, UART_FRAMING_ERR or UART_ERRS.
+  */
+UART_Err UART_GetErrState(TSB_SC_TypeDef * UARTx)
+{
+    uint8_t tmp = 0U;
+    UART_Err retval = UART_NO_ERR;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = ((uint8_t) (UARTx->CR & CR_ERROR_MASK));
+    switch (tmp) {
+    case CR_OERR_FLAG:         /* Check overrun flag */
+        retval = UART_OVERRUN;
+        break;
+    case CR_PERR_FLAG:         /* Check parity flag */
+        retval = UART_PARITY_ERR;
+        break;
+    case CR_FERR_FLAG:         /* Check framing flag */
+        retval = UART_FRAMING_ERR;
+        break;
+    default:
+        if (tmp != 0U) {
+            /* more than one error */
+            retval = UART_ERRS;
+        } else {
+            /* Do nothing */
+        }
+        break;
+    }
+
+    return retval;
+}
+
+/**
+  * @brief  Enable or disable the wake-up function in 9-bit UART mode
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  NewState: New state of this function.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_SetWakeUpFunc(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    if (NewState == ENABLE) {
+        /* Set SCxMOD0<WU> to enable wake-up function */
+        UARTx->MOD0 |= MOD0_WU_SET;
+    } else {
+        /* Clear SCxMOD0<WU> to disable wake-up function */
+        UARTx->MOD0 &= MOD0_WU_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable the specified UART channel when system is in IDLE
+      mode.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  NewState: New state of the UART channel in IDLE.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_SetIdleMode(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = UARTx->MOD1;
+    if (NewState == ENABLE) {
+        /* Set SCxMOD1<I2SC> to enable UARTx running in IDLE */
+        tmp |= MOD1_I2SC_SET;
+    } else {
+        /* Clear SCxMOD1<I2SC> to disable UARTx running in IDLE */
+        tmp &= MOD1_I2SC_CLEAR;
+    }
+    tmp &= MOD1_CLEAR;
+    UARTx->MOD1 = tmp;
+}
+
+/**
+  * @brief  Selects input clock for prescaler.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  clock: Selects input clock for prescaler as PhiT0/2 or PhiT0.
+  *   This parameter can be:
+  *         0: PhiT0/2
+  *         1: PhiT0
+  * @retval None
+  * @note UART_SetInputClock need to use before UART_Init.
+  */
+void UART_SetInputClock(TSB_SC_TypeDef * UARTx, uint32_t clock)
+{
+    uint32_t tmp = 0U;
+
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_CLOCK(clock));
+
+    tmp = UARTx->EN;
+    tmp &= EN_BRCKSEL_MASK;
+    tmp |= (uint32_t) (clock << 1U);
+    UARTx->EN = tmp;
+}
+
+/**
+  * @brief  Enable or disable the FIFO of specified UART channel.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  NewState: New state of the UART FIFO.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_FIFOConfig(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = UARTx->FCNF;
+    tmp &= FCNF_BIT567_CLEAR;
+    if (NewState == ENABLE) {
+        /* Set SCxFCNF<CNFG> to enable UARTx FIFO */
+        UARTx->FCNF = tmp | FCNF_CNFG_SET;
+    } else {
+        /* Clear SCxFCNF<CNFG> to disable UARTx FIFO */
+        UARTx->FCNF = tmp & FCNF_CNFG_CLEAR;
+    }
+}
+
+/**
+  * @brief  Transfer mode setting.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  TransferMode: Transfer mode.
+  *   This parameter can be: UART_TRANSFER_PROHIBIT, UART_TRANSFER_HALFDPX_RX,
+  *   UART_TRANSFER_HALFDPX_TX or UART_TRANSFER_FULLDPX.
+  * @retval None
+  */
+void UART_SetFIFOTransferMode(TSB_SC_TypeDef * UARTx, uint32_t TransferMode)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_TRANSFER_MODE(TransferMode));
+
+    tmp = UARTx->MOD1;
+    tmp &= MOD1_FDPX_CLEAR;
+    tmp |= TransferMode;
+    UARTx->MOD1 = tmp;
+}
+
+/**
+  * @brief  Controls automatic disabling of transmission and reception.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  TRxAutoDisable: Disabling transmission and reception or not.
+  *   This parameter can be: UART_RXTXCNT_NONE or UART_RXTXCNT_AUTODISABLE .
+  * @retval None
+  */
+void UART_TRxAutoDisable(TSB_SC_TypeDef * UARTx, UART_TRxDisable TRxAutoDisable)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UATR_TRX_AUTODISABLE(TRxAutoDisable));
+
+    tmp = UARTx->FCNF;
+    tmp &= FCNF_BIT567_CLEAR;
+    if (TRxAutoDisable == UART_RXTXCNT_AUTODISABLE) {
+        /* Set SCxFCNF<RXTXCNT> to automatic disabling of transmission and reception */
+        UARTx->FCNF = tmp | FCNF_RXTXCNT_SET;
+    } else {
+        /* Clear SCxFCNF<RXTXCNT> to do none */
+        UARTx->FCNF = tmp & FCNF_RXTXCNT_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable receive interrupt for receive FIFO.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  NewState: New state of receive interrupt for receive FIFO.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_RxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = UARTx->FCNF;
+    tmp &= FCNF_BIT567_CLEAR;
+    if (NewState == ENABLE) {
+        /* Set SCxFCNF<RFIE> to enable receive FIFO interrupt */
+        UARTx->FCNF = tmp | FCNF_RFIE_SET;
+    } else {
+        /* Clear SCxFCNF<RFIE> to disable receive FIFO interrupt */
+        UARTx->FCNF = tmp & FCNF_RFIE_CLEAR;
+    }
+}
+
+/**
+  * @brief  Enable or disable transmit interrupt for transmit FIFO.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  NewState: New state of transmit interrupt for transmit FIFO.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void UART_TxFIFOINTCtrl(TSB_SC_TypeDef * UARTx, FunctionalState NewState)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+    tmp = UARTx->FCNF;
+    tmp &= FCNF_BIT567_CLEAR;
+    if (NewState == ENABLE) {
+        /* Set SCxFCNF<TFIE> to enable transmit FIFO interrupt */
+        UARTx->FCNF = tmp | FCNF_TFIE_SET;
+    } else {
+        /* Clear SCxFCNF<TFIE> to disable transmit FIFO interrupt */
+        UARTx->FCNF = tmp & FCNF_TFIE_CLEAR;
+    }
+}
+
+/**
+  * @brief  Bytes used in receive FIFO.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  BytesUsed: Bytes used in receive FIFO.
+  *   This parameter can be: UART_RXFIFO_MAX or UART_RXFIFO_RXFLEVEL.
+  * @retval None
+  */
+void UART_RxFIFOByteSel(TSB_SC_TypeDef * UARTx, uint32_t BytesUsed)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UATR_RXFIFO_BYTESUSED(BytesUsed));
+
+    tmp = UARTx->FCNF;
+    tmp &= FCNF_BIT567_CLEAR;
+    tmp &= FCNF_RFST_CLEAR;
+    tmp |= BytesUsed;
+    UARTx->FCNF = tmp;
+}
+
+/**
+  * @brief  Receive FIFO fill level to generate receive interrupts.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  RxFIFOLevel: Receive FIFO fill level.
+  *   This parameter can be one of the following values:
+  *   UART_RXFIFO4B_FLEVLE_4_2B, UART_RXFIFO4B_FLEVLE_1_1B,
+  *   UART_RXFIFO4B_FLEVLE_2_2B or UART_RXFIFO4B_FLEVLE_3_1B.
+  *   This parameter can be one of the following values:
+  * @retval None
+  */
+void UART_RxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t RxFIFOLevel)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_RXFIFO4B_FLEVLE(RxFIFOLevel));
+
+    tmp = UARTx->RFC;
+    tmp &= RFC_4B_RIL_CLEAR;
+    tmp |= RxFIFOLevel;
+    UARTx->RFC = tmp;
+}
+
+/**
+  * @brief  Select RX interrupt generation condition.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  RxINTCondition: RX interrupt generation condition.
+  *   This parameter can be: UART_RFIS_REACH_FLEVEL or UART_RFIS_REACH_EXCEED_FLEVEL.
+  * @retval None
+  */
+void UART_RxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t RxINTCondition)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UATR_RFIS_CONDITION(RxINTCondition));
+
+    tmp = UARTx->RFC;
+    tmp &= RFC_RFIS_CLEAR;
+    tmp |= RxINTCondition;
+    UARTx->RFC = tmp;
+}
+
+/**
+  * @brief  Receive FIFO clear.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval None
+  */
+void UART_RxFIFOClear(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->RFC;
+    tmp |= TRFC_TRFCS_SET;
+    UARTx->RFC = tmp;
+}
+
+/**
+  * @brief  Transmit FIFO fill level to generate transmit interrupts.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  TxFIFOLevel: Transmit FIFO fill level.
+  *   This parameter can be one of the following values:
+  *   UART_TXFIFO4B_FLEVLE_0_0B, UART_TXFIFO4B_FLEVLE_1_1B,
+  *   UART_TXFIFO4B_FLEVLE_2_0B or UART_TXFIFO4B_FLEVLE_3_1B.
+  * @retval None
+  */
+void UART_TxFIFOFillLevel(TSB_SC_TypeDef * UARTx, uint32_t TxFIFOLevel)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UART_TXFIFO4B_FLEVLE(TxFIFOLevel));
+
+    tmp = UARTx->TFC;
+    tmp &= TFC_4B_TIL_CLEAR;
+    tmp |= TxFIFOLevel;
+    UARTx->TFC = tmp;
+}
+
+/**
+  * @brief  Select TX interrupt generation condition.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @param  TxINTCondition: TX interrupt generation condition.
+  *   This parameter can be: UART_TFIS_REACH_FLEVEL or UART_TFIS_REACH_NOREACH_FLEVEL.
+  * @retval None
+  */
+void UART_TxFIFOINTSel(TSB_SC_TypeDef * UARTx, uint32_t TxINTCondition)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+    assert_param(IS_UATR_TFIS_CONDITION(TxINTCondition));
+
+    tmp = UARTx->TFC;
+    tmp &= TFC_TFIS_CLEAR;
+    tmp |= TxINTCondition;
+    UARTx->TFC = tmp;
+}
+
+/**
+  * @brief  Transmit FIFO clear.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval None
+  */
+void UART_TxFIFOClear(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->TFC;
+    tmp |= TRFC_TRFCS_SET;
+    UARTx->TFC = tmp;
+}
+
+/**
+  * @brief  Transmit buffer clear.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval None
+  */
+void UART_TxBufferClear(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->TFC;
+    tmp |= TFC_TBCLR_SET;
+    UARTx->TFC = tmp;
+}
+
+/**
+  * @brief  Status of receive FIFO fill level.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval Receive FIFO fill level status.
+  */
+uint32_t UART_GetRxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->RST;
+    tmp &= TRXST_4B_TRLVL_MASK;
+
+    return tmp;
+}
+
+/**
+  * @brief  Receive FIFO overrun.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval Receive FIFO overrun status.
+  */
+uint32_t UART_GetRxFIFOOverRunStatus(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    uint32_t regval = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->RST;
+    if ((tmp & TRXST_TUR_ROR_MASK) == TRXST_TUR_ROR_MASK) {
+        regval = UART_RXFIFO_OVERRUN;
+    } else {
+        /* Do nothing */
+    }
+
+    return regval;
+}
+
+/**
+  * @brief  Status of transmit FIFO fill level.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval Transmit FIFO fill level status.
+  */
+uint32_t UART_GetTxFIFOFillLevelStatus(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->TST;
+    tmp &= TRXST_4B_TRLVL_MASK;
+
+    return tmp;
+}
+
+/**
+  * @brief  Transmit FIFO under run.
+  * @param  UARTx: Select the UART channel.
+  *   This parameter can be one of the following values:
+  *   UART0, UART1, UART2, UART3.
+  * @retval Transmit FIFO under run status.
+  */
+uint32_t UART_GetTxFIFOUnderRunStatus(TSB_SC_TypeDef * UARTx)
+{
+    uint32_t tmp = 0U;
+    uint32_t regval = 0U;
+    /* Check the parameters */
+    assert_param(IS_UART_PERIPH(UARTx));
+
+    tmp = UARTx->TST;
+    if ((tmp & TRXST_TUR_ROR_MASK) == TRXST_TUR_ROR_MASK) {
+        regval = UART_TXFIFO_UNDERRUN;
+    } else {
+        /* Do nothing */
+    }
+
+    return regval;
+}
+
+/**
+  * @brief  Selects input clock for prescaler.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0, SIO1, SIO2, SIO3.
+  * @param  clock: Selects input clock for prescaler as PhiT0/2 or PhiT0.
+  *   This parameter can be:
+  *   SIO_CLOCK_T0_HALF (PhiT0/2)or SIO_CLOCK_T0(PhiT0)
+  * @retval None
+  * @note SIO_SetInputClock need to use before SIO_Init.
+  */
+void SIO_SetInputClock(TSB_SC_TypeDef * SIOx, uint32_t Clock)
+{
+    uint32_t tmp = 0U;
+    assert_param(IS_SIO_PERIPH(SIOx));
+    assert_param(IS_SIO_CLOCK(Clock));
+
+    tmp = SIOx->EN;
+    tmp &= EN_BRCKSEL_MASK;
+    tmp |= Clock;
+    SIOx->EN = tmp;
+}
+
+/**
+  * @brief  Enable the specified SIO channel.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0, SIO1, SIO2, SIO3.
+  * @retval None
+  */
+void SIO_Enable(TSB_SC_TypeDef * SIOx)
+{
+    /* Check the parameters */
+    assert_param(IS_SIO_PERIPH(SIOx));
+    /* Set SCxEN<SIOE> to enable SIOx */
+    SIOx->EN |= EN_SIOE_SET;
+}
+
+/**
+  * @brief  Disable the specified SIO channel.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0, SIO1, SIO2, SIO3.
+  * @retval None
+  */
+void SIO_Disable(TSB_SC_TypeDef * SIOx)
+{
+    /* Check the parameters */
+    assert_param(IS_SIO_PERIPH(SIOx));
+    /* Clear SCxEN<SIOE> to disable SIOx */
+    SIOx->EN &= EN_SIOE_CLEAR;
+}
+
+/**
+  * @brief  Get received data of the specified SIO channel.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0, SIO1, SIO2, SIO3.
+  * @retval The received data
+  */
+uint8_t SIO_GetRxData(TSB_SC_TypeDef * SIOx)
+{
+    uint8_t retval = 0U;
+    /* Check the parameters */
+    assert_param(IS_SIO_PERIPH(SIOx));
+
+    /* Return received data */
+    retval = (uint8_t) SIOx->BUF;
+
+    return retval;
+}
+
+/**
+  * @brief  Set data to be sent and start transmitting via the specified
+      SIO channel.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0, SIO1, SIO2, SIO3.
+  * @param  Data: the data to be sent.
+  * @retval None
+  */
+void SIO_SetTxData(TSB_SC_TypeDef * SIOx, uint8_t Data)
+{
+    /* Check the parameters */
+    assert_param(IS_SIO_PERIPH(SIOx));
+
+    SIOx->BUF = (uint32_t) Data;
+}
+
+/**
+  * @brief  Initialize the specified SIO channel.
+  * @param  SIOx: Select the SIO channel.
+  *   This parameter can be one of the following values:
+  *   SIO0, SIO1, SIO2, SIO3.
+  * @param  IOClkSel: Selecting clock.
+  *   This parameter can be one of the following values:
+  *   SIO_CLK_SCLKOUTPUT or SIO_CLK_SCLKINPUT.
+  * @param  InitStruct: The structure containing basic SIO configuration.
+  * @retval None
+  * @note SIO_SetInputClock need to use before SIO_Init.
+  */
+void SIO_Init(TSB_SC_TypeDef * SIOx, uint32_t IOClkSel, SIO_InitTypeDef * InitStruct)
+{
+    uint32_t tmp = 0U;
+
+    /* Check the parameters */
+    assert_param(IS_POINTER_NOT_NULL(InitStruct));
+    assert_param(IS_SIO_PERIPH(SIOx));
+    assert_param(IS_SIO_CLK_SEL(IOClkSel));
+    assert_param(IS_SIO_SCLKS_TRXD(InitStruct->InputClkEdge));
+    assert_param(IS_SIO_TIDLE_LEVEL(InitStruct->TIDLE));
+    assert_param(IS_SIO_TRANSFER_MODE(InitStruct->TransferMode));
+    assert_param(IS_SIO_TRANS_DIR(InitStruct->TransferDir));
+    assert_param(IS_SIO_MODE(InitStruct->Mode));
+    assert_param(IS_SIO_WBUF_SET(InitStruct->DoubleBuffer));
+    if (IOClkSel == SIO_CLK_SCLKINPUT) {
+        /* Only used for SCLK pin input mode */
+        assert_param(IS_SIO_TXDEMP_LEVEL(InitStruct->TXDEMP));
+        assert_param(IS_SIO_EHOLD_TIME(InitStruct->EHOLDTime));
+    } else {
+        /* Only used for baud rate generator(SCLK pin output) mode */
+        assert_param(IS_SIO_SINT_TIME(InitStruct->IntervalTime));
+        assert_param(IS_SIO_BR_CLOCK(InitStruct->BaudRateClock));
+        assert_param(IS_SIO_BR_DIVIDER(InitStruct->Divider));
+    }
+
+    /* Configure the transfer mode to I/O interface mode */
+    tmp = SIOx->MOD0;
+    tmp &= MOD0_SM_MASK;
+    SIOx->MOD0 = tmp;
+
+    /* Selecting the clock(SCLK input or output),input clock edge
+       for I/O interface mode */
+    tmp = SIOx->CR;
+    tmp &= (CR_IOC_MASK & CR_SCLKS_MASK & CR_TIDLE_MASK);
+    tmp |= (IOClkSel | InitStruct->InputClkEdge | InitStruct->TIDLE);
+
+    /* Set status of TXDx pin when an under run error is occurred
+       and the last bit hold time of TXDx pin in SCLK input mode */
+    if (IOClkSel == SIO_CLK_SCLKINPUT) {
+        tmp &= (CR_TXDEMP_MASK & CR_EHOLD_MASK);
+        tmp |= (InitStruct->TXDEMP | InitStruct->EHOLDTime);
+    } else {
+        /* Do nothing */
+    }
+    SIOx->CR = tmp;
+
+    /* Set the transfer mode and interval time */
+    tmp = SIOx->MOD1;
+    tmp &= MOD1_FDPX_CLEAR;
+    tmp |= InitStruct->TransferMode;
+    /* Set the interval time that valid only for SCLK output mode and double
+       buffer is enabled */
+    if ((IOClkSel == SIO_CLK_SCLKOUTPUT) && (InitStruct->DoubleBuffer == SIO_WBUF_ENABLE)) {
+        tmp &= MOD1_SINT_MASK;
+        tmp |= InitStruct->IntervalTime;
+    } else {
+        /* Do nothing */
+    }
+    tmp &= MOD1_CLEAR;
+    SIOx->MOD1 = tmp;
+
+    /* Set the transfer direction and double buffer */
+    tmp = SIOx->MOD2;
+    tmp &= MOD2_DRCHG_MASK;
+    tmp &= MOD2_WBUF_MASK;
+    tmp |= (InitStruct->TransferDir | InitStruct->DoubleBuffer);
+    SIOx->MOD2 = tmp;
+
+    /* Select the input clock for baud rate generator and setting
+       Division ratio "N"  */
+    tmp = SIOx->BRCR;
+    if (IOClkSel == SIO_CLK_SCLKOUTPUT) {
+        tmp &= BRCR_BRCK_MASK;
+        tmp &= BRCR_BRS_MASK;
+        tmp |= (InitStruct->BaudRateClock | InitStruct->Divider);
+    } else {
+        /* Do nothing */
+    }
+    tmp &= BRCR_CLEAR;
+    SIOx->BRCR = tmp;
+
+    /* Enable or disable transmission or reception and both */
+    tmp = SIOx->MOD1;
+    switch (InitStruct->Mode) {
+    case SIO_ENABLE_RX:
+        SIOx->MOD0 |= InitStruct->Mode;
+        tmp &= MOD1_TXE_CLEAR;
+        break;
+    case SIO_ENABLE_TX:
+        tmp |= InitStruct->Mode;
+        SIOx->MOD0 &= MOD0_RXE_CLEAR;
+        break;
+    default:
+        SIOx->MOD0 |= SIO_ENABLE_RX;
+        tmp |= SIO_ENABLE_TX;
+        break;
+    }
+    tmp &= MOD1_CLEAR;
+    SIOx->MOD1 = tmp;
+}
+
+/** @} */
+/* End of group UART_Exported_Functions */
+
+/** @} */
+/* End of group UART */
+
+/** @} */
+/* End of group TX04_Periph_Driver */
+
+#endif                          /* defined(__TMPM46B_UART_H)) */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/PeripheralNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    SERIAL_0 = 0,
+    SERIAL_1,
+    SERIAL_2,
+    SERIAL_3,
+    SERIAL_4,
+    SERIAL_5,
+    INVALID_SERIAL = (int)NC
+} UARTName;
+
+typedef enum {
+    ADC_A0,
+    ADC_A1,
+    ADC_A2,
+    ADC_A3,
+    ADC_A4,
+    ADC_A5,
+    ADC_A6,
+    ADC_A7,
+    INVALID_ADC = (int)NC
+} ADCName;
+
+typedef enum {
+    SPI_0 = 0,
+    SPI_1,
+    SPI_2,
+    INVALID_SPI = (int)NC
+} SPIName;
+
+typedef enum {
+    I2C_0 = 0,
+    I2C_1,
+    I2C_2,
+    INVALID_I2C = (int)NC
+} I2CName;
+
+typedef enum {
+    PWM_0 = 0,
+    PWM_1,
+    PWM_2,
+    PWM_3,
+    PWM_4,
+    PWM_5,
+    INVALID_PWM = (int)NC
+} PWMName;
+
+typedef enum {
+    GPIO_IRQ_0 = 1,
+    GPIO_IRQ_1 = 2,
+    GPIO_IRQ_2 = 7,
+    GPIO_IRQ_3 = 8,
+    GPIO_IRQ_4 = 13,
+    GPIO_IRQ_5 = 14,
+    GPIO_IRQ_6 = 15,
+    INVALID_GPIO_IRQ = (int)NC
+} GPIO_IRQName;
+
+#define STDIO_UART_TX     PE5
+#define STDIO_UART_RX     PE6
+#define STDIO_UART        SERIAL_1
+
+#define MBED_SPI0         PK3, PK2, PK4, PK1
+#define MBED_SPI1         PF4, PF5, PF3, PF6
+#define MBED_SPI2         PD2, PD1, PD3, PD0
+
+#define MBED_UART0        PE2, PE1
+#define MBED_UART1        PE5, PE6
+#define MBED_UART2        PL2, PL1
+#define MBED_UART3        PB0, PB1
+#define MBED_UART4        PF1, PF2
+#define MBED_UART5        PA6, PA5
+#define MBED_UARTUSB      USBTX, USBRX
+
+#define MBED_I2C0         PK2, PK3
+#define MBED_I2C1         PF7, PF6
+#define MBED_I2C2         PH0, PH1
+
+#define MBED_ANALOGIN0    A0
+#define MBED_ANALOGIN1    A1
+#define MBED_ANALOGIN2    A2
+#define MBED_ANALOGIN3    A3
+#define MBED_ANALOGIN4    A4
+#define MBED_ANALOGIN5    A5
+
+#define MBED_PWMOUT0      PE4
+#define MBED_PWMOUT1      PB6
+#define MBED_PWMOUT2      PH1
+#define MBED_PWMOUT3      PH0
+#define MBED_PWMOUT4      PA7
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/PinNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,122 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PIN_PORT(X)         (((uint32_t)(X) >> 3) & 0xF)
+#define PIN_POS(X)          ((uint32_t)(X) & 0x7)
+
+// Pin data, bit 31..16: Pin Function, bit 15..0: Pin Direction
+#define PIN_DATA(FUNC, DIR) (int)(((FUNC) << 16) | ((DIR) << 0))
+#define PIN_FUNC(X)         (((X) & 0xffff0000) >> 16)
+#define PIN_DIR(X)          ((X) & 0xffff)
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT,
+    PIN_INOUT
+} PinDirection;
+
+typedef enum {
+    // TMPM46B Pin Names
+    PA0 = 0  << 3, PA1, PA2, PA3, PA4, PA5, PA6, PA7,
+    PB0 = 1  << 3, PB1, PB2, PB3, PB4, PB5, PB6, PB7,
+    PC0 = 2  << 3, PC1, PC2, PC3, PC4, PC5,
+    PD0 = 3  << 3, PD1, PD2, PD3, PD4,
+    PE0 = 4  << 3, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PF0 = 5  << 3, PF1, PF2, PF3, PF4, PF5, PF6, PF7,
+    PG0 = 6  << 3, PG1, PG2, PG3, PG4, PG5, PG6, PG7,
+    PH0 = 7  << 3, PH1, PH2, PH3,
+    PJ0 = 8  << 3, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7,
+    PK0 = 9  << 3, PK1, PK2, PK3, PK4,
+    PL0 = 10 << 3, PL1, PL2, PL3,
+
+    // Other mbed Pin Names
+    LED1 = PF4,
+    LED2 = PF5,
+    LED3 = PF6,
+    LED4 = PF7,
+
+    // External data bus Pin Names
+    D0 = PL1,
+    D1 = PL2,
+    D2 = PC0,
+    D3 = PE3,
+    D4 = PC1,
+    D5 = PE4,
+    D6 = PH1,
+    D7 = PC2,
+    D8 = PC3,
+    D9 = PH0,
+    D10 = PD0,
+    D11 = PD2,
+    D12 = PD1,
+    D13 = PD3,
+    D14 = PK2,
+    D15 = PK3,
+
+    // Analogue out pins
+    A0 = PJ2,
+    A1 = PJ3,
+    A2 = PJ4,
+    A3 = PJ5,
+    A4 = PJ6,
+    A5 = PJ7,
+
+    // DAP_UART
+    USBTX = PE5,
+    USBRX = PE6,
+    MBEDIF_TXD = USBTX,
+    MBEDIF_RXD = USBRX,
+
+    MBED_CONF_APP_UART0_TX = PE2,
+    MBED_CONF_APP_UART0_RX = PE1,
+
+    // Switches
+    SW1 = PF0,
+    SW2 = PF1,
+    SW3 = PF2,
+    SW4 = PF3,
+
+    // I2C pins
+    SDA = PK2,
+    SCL = PK3,
+    I2C_SDA = SDA,
+    I2C_SCL = SCL,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF,
+} PinName;
+
+typedef enum {
+    PullUp = 0,
+    PullDown,
+    PullNone,
+    OpenDrain,
+    PullDefault = PullDown
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/PortNames.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB,
+    PortC,
+    PortD,
+    PortE,
+    PortF,
+    PortG,
+    PortH,
+    PortJ,
+    PortK,
+    PortL
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/analogin_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "analogin_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "mbed_wait_api.h"
+
+static uint8_t adc_reset_init = 0;  // Is ADC Reset happened yet?
+#define ADC_12BIT_RANGE   0xFFF
+
+static const PinMap PinMap_ADC[] = {
+    {PJ0, ADC_A0,  PIN_DATA(2, 0)},
+    {PJ1, ADC_A1,  PIN_DATA(2, 0)},
+    {PJ2, ADC_A2,  PIN_DATA(2, 0)},
+    {PJ3, ADC_A3,  PIN_DATA(2, 0)},
+    {PJ4, ADC_A4,  PIN_DATA(2, 0)},
+    {PJ5, ADC_A5,  PIN_DATA(2, 0)},
+    {PJ6, ADC_A6,  PIN_DATA(2, 0)},
+    {PJ7, ADC_A7,  PIN_DATA(2, 0)},
+    {NC,  NC,     0}
+};
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    // Check that pin belong to ADC module
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+
+    // Enable clock supply
+    CG_SetADCClkSupply(ENABLE);
+    // Set pin function as ADC
+    pinmap_pinout(pin, PinMap_ADC);
+    if (!adc_reset_init) {
+        // Software reset ADC
+        ADC_SWReset(TSB_AD);
+        adc_reset_init = 1;
+    }
+    // Set sample hold time and pre-scale clock
+    ADC_SetClk(TSB_AD, ADC_CONVERSION_CLK_80, ADC_FC_DIVIDE_LEVEL_8);
+    // Set input channel
+    ADC_SetInputChannel(TSB_AD, (ADC_AINx)obj->adc);
+    // Turn VREF on
+    ADC_SetVref(TSB_AD, ENABLE);
+    // Use fixed-channel single conversion mode
+    ADC_SetRepeatMode(TSB_AD, DISABLE);
+    ADC_SetScanMode(TSB_AD, DISABLE);
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    ADC_Result ret = {0x00};
+
+    // Assert that ADC channel is valid
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+    wait_us(300); // Wait for register to update with convert value
+
+    // Set input channel
+    ADC_SetInputChannel(TSB_AD, (ADC_AINx)obj->adc);
+    // Enable Vref
+    ADC_SetVref(TSB_AD, ENABLE);
+    // Wait at least 3us to ensure the voltage is stable
+    wait_us(10U);
+    // Start ADC conversion
+    ADC_Start(TSB_AD);
+    // Wait until AD conversion complete
+    while(ADC_GetConvertState(TSB_AD).Bit.NormalComplete != 1) {
+        // Do nothing
+    }
+    wait_us(30);
+    // Convert result
+    ret = ADC_GetConvertResult(TSB_AD, (ADC_REGx)obj->adc);
+    // Disable Vref to go into standby mode
+    ADC_SetVref(TSB_AD, DISABLE);
+    return (uint16_t)ret.Bit.ADResult;
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = analogin_read_u16(obj);
+    return (float)(value * (1.0f / (float)ADC_12BIT_RANGE));
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,24 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_ID_LENGTH    32
+
+#include "objects.h"
+#include <stddef.h>
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/TMPM46B.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,2838 @@
+/**
+ *******************************************************************************
+ * @file    TMPM46B.h
+ * @brief   CMSIS Cortex-M4 Core Peripheral Access Layer Header File for the
+ *          TOSHIBA 'TMPM46B' Device Series
+ * @version V2.0.2.4
+ * @date    2015/03/13
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+/** @addtogroup TOSHIBA_TX04_MICROCONTROLLER
+  * @{
+  */
+  
+/** @addtogroup TMPM46B
+  * @{
+  */
+
+#ifndef __TMPM46B_H__
+#define __TMPM46B_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+/** Interrupt Number Definition */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ***************************************************************/
+  NonMaskableInt_IRQn           = -14,       /*!< 2 Non Maskable Interrupt                                    */
+  HardFault_IRQn                = -13,       /*!< 3 Cortex-M4 Hard Fault Interrupt                            */
+  MemoryManagement_IRQn         = -12,       /*!< 4 Cortex-M4 Memory Management Interrupt                     */
+  BusFault_IRQn                 = -11,       /*!< 5 Cortex-M4 Bus Fault Interrupt                             */
+  UsageFault_IRQn               = -10,       /*!< 6 Cortex-M4 Usage Fault Interrupt                           */
+  SVCall_IRQn                   = -5,        /*!< 11 Cortex-M4 SV Call Interrupt                              */
+  DebugMonitor_IRQn             = -4,        /*!< 12 Cortex-M4 Debug Monitor Interrupt                        */
+  PendSV_IRQn                   = -2,        /*!< 14 Cortex-M4 Pend SV Interrupt                              */
+  SysTick_IRQn                  = -1,        /*!< 15 Cortex-M4 System Tick Interrupt                          */
+
+/******  TMPM46B Specific Interrupt Numbers *******************************************************************/
+  INT0_IRQn                     = 0,         /*!< Interrupt pin 0                                             */
+  INT1_IRQn                     = 1,         /*!< Interrupt pin 1                                             */
+  INT2_IRQn                     = 2,         /*!< Interrupt pin 2                                             */
+  INT3_IRQn                     = 3,         /*!< Interrupt pin 3                                             */
+  INT4_IRQn                     = 4,         /*!< Interrupt pin 4                                             */
+  INT5_IRQn                     = 5,         /*!< Interrupt pin 5                                             */
+  INT6_IRQn                     = 6,         /*!< Interrupt pin 6                                             */
+  INT7_IRQn                     = 7,         /*!< Interrupt pin 7                                             */
+  INT8_IRQn                     = 8,         /*!< Interrupt pin 8                                             */
+  INT9_IRQn                     = 9,         /*!< Interrupt pin 9                                             */
+  INTA_IRQn                     = 10,        /*!< Interrupt pin A                                             */
+  INTB_IRQn                     = 11,        /*!< Interrupt pin B                                             */
+  INTC_IRQn                     = 12,        /*!< Interrupt pin C                                             */
+  INTD_IRQn                     = 13,        /*!< Interrupt pin D                                             */
+  INTE_IRQn                     = 14,        /*!< Interrupt pin E                                             */
+  INTF_IRQn                     = 15,        /*!< Interrupt pin F                                             */
+  INTRX0_IRQn                   = 16,        /*!< Serial0 reception interrupt                                 */
+  INTTX0_IRQn                   = 17,        /*!< Serial0 transmission interrupt                              */
+  INTRX1_IRQn                   = 18,        /*!< Serial1 reception interrupt                                 */
+  INTTX1_IRQn                   = 19,        /*!< Serial1 transmission interrupt                              */
+  INTRX2_IRQn                   = 20,        /*!< Serial2 reception interrupt                                 */
+  INTTX2_IRQn                   = 21,        /*!< Serial2 transmission interrupt                              */
+  INTRX3_IRQn                   = 22,        /*!< Serial3 reception interrupt                                 */
+  INTTX3_IRQn                   = 23,        /*!< Serial3 transmission interrupt                              */
+  INTUART0_IRQn                 = 24,        /*!< Full UART0 transmission and reception interrupt             */
+  INTUART1_IRQn                 = 25,        /*!< Full UART1 transmission and reception interrupt             */
+  INTI2C0_IRQn                  = 26,        /*!< I2C0 transmission and reception interrupt                   */
+  INTI2C1_IRQn                  = 27,        /*!< I2C1 transmission and reception interrupt                   */
+  INTI2C2_IRQn                  = 28,        /*!< I2C2 transmission and reception interrupt                   */
+  INTSSP0_IRQn                  = 29,        /*!< SSP(SPI) Serial interface 0 interrupt                       */
+  INTSSP1_IRQn                  = 30,        /*!< SSP(SPI) Serial interface 1 interrupt                       */
+  INTSSP2_IRQn                  = 31,        /*!< SSP(SPI) Serial interface 2 interrupt                       */
+  INTADHP_IRQn                  = 32,        /*!< High Priority AD conversion interrupt                       */
+  INTADM0_IRQn                  = 33,        /*!< AD conversion monitor interrupt 0                           */
+  INTADM1_IRQn                  = 34,        /*!< AD conversion monitor interrupt 1                           */
+  INTAD_IRQn                    = 35,        /*!< AD conversion interrupt                                     */
+  INTAES_IRQn                   = 36,        /*!< AES completion interrupt                                    */
+  INTSHA_IRQn                   = 37,        /*!< SHA completion interrupt                                    */
+  INTMLA_IRQn                   = 38,        /*!< MLA completion interrupt                                    */
+  INTESG_IRQn                   = 39,        /*!< ESG completion interrupt                                    */
+  INTSNFCSEQ_IRQn               = 40,        /*!< SNFC command sequence end interrupt                         */
+  INTSNFCPRTAE_IRQn             = 41,        /*!< SNFC page lead RAM transfer end interrupt                   */
+  INTSNFCPRTCE_IRQn             = 42,        /*!< SNFC decode data RAM transmission end interrupt             */
+  INTSNFCFAIL_IRQn              = 43,        /*!< SNFC decode fail interrupt                                  */
+  INTMTEMG0_IRQn                = 47,        /*!< MPT0 EMG interrupt                                          */
+  INTMTPTB00_IRQn               = 48,        /*!< MPT0 compare match0/overflow,IGBT cycle interrupt           */
+  INTMTPTB01_IRQn               = 49,        /*!< MPT0 compare match1/overflow,IGBT cycle interrupt           */
+  INTMTCAP00_IRQn               = 50,        /*!< MPT0 input capture0 interrupt                               */
+  INTMTCAP01_IRQn               = 51,        /*!< MPT0 input capture1 interrupt                               */
+  INTMTEMG1_IRQn                = 52,        /*!< MPT1 EMG interrupt                                          */
+  INTMTPTB10_IRQn               = 53,        /*!< MPT1 compare match0/overflow,IGBT cycle interrupt           */
+  INTMTPTB11_IRQn               = 54,        /*!< MPT1 compare match1/overflow,IGBT cycle interrupt           */
+  INTMTCAP10_IRQn               = 55,        /*!< MPT1 input capture0 interrupt                               */
+  INTMTCAP11_IRQn               = 56,        /*!< MPT1 input capture1 interrupt                               */
+  INTMTEMG2_IRQn                = 57,        /*!< MPT2 EMG interrupt                                          */
+  INTMTPTB20_IRQn               = 58,        /*!< MPT2 compare match0/overflow,IGBT cycle interrupt           */
+  INTMTTTB21_IRQn               = 59,        /*!< MPT2 compare match1/overflow,IGBT cycle interrupt           */
+  INTMTCAP20_IRQn               = 60,        /*!< MPT2 input capture0 interrupt                               */
+  INTMTCAP21_IRQn               = 61,        /*!< MPT2 input capture1 interrupt                               */
+  INTMTEMG3_IRQn                = 62,        /*!< MPT3 EMG interrupt                                          */
+  INTMTPTB30_IRQn               = 63,        /*!< MPT3 compare match0/overflow,IGBT cycle interrupt           */
+  INTMTTTB31_IRQn               = 64,        /*!< MPT3 compare match1/overflow,IGBT cycle interrupt           */
+  INTMTCAP30_IRQn               = 65,        /*!< MPT3 input capture0 interrupt                               */
+  INTMTCAP31_IRQn               = 66,        /*!< MPT3 input capture1 interrupt                               */
+  INTTB0_IRQn                   = 67,        /*!< TMRB0 compare match detection interrupt                     */
+  INTCAP00_IRQn                 = 68,        /*!< TMRB0 input capture 0 interrupt                             */
+  INTCAP01_IRQn                 = 69,        /*!< TMRB0 input capture 1 interrupt                             */
+  INTTB1_IRQn                   = 70,        /*!< TMRB1 compare match detection interrupt                     */
+  INTCAP10_IRQn                 = 71,        /*!< TMRB1 input capture 0 interrupt                             */
+  INTCAP11_IRQn                 = 72,        /*!< TMRB1 input capture 1 interrupt                             */
+  INTTB2_IRQn                   = 73,        /*!< TMRB2 compare match detection interrupt                     */
+  INTCAP20_IRQn                 = 74,        /*!< TMRB2 input capture 0 interrupt                             */
+  INTCAP21_IRQn                 = 75,        /*!< TMRB2 input capture 1 interrupt                             */
+  INTTB3_IRQn                   = 76,        /*!< TMRB3 compare match detection interrupt                     */
+  INTCAP30_IRQn                 = 77,        /*!< TMRB3 input capture 0 interrupt                             */
+  INTCAP31_IRQn                 = 78,        /*!< TMRB3 input capture 1 interrupt                             */
+  INTTB4_IRQn                   = 79,        /*!< TMRB4 compare match detection interrupt                     */
+  INTCAP40_IRQn                 = 80,        /*!< TMRB4 input capture 0 interrupt                             */
+  INTCAP41_IRQn                 = 81,        /*!< TMRB4 input capture 1 interrupt                             */
+  INTTB5_IRQn                   = 82,        /*!< TMRB5 compare match detection interrupt                     */
+  INTCAP50_IRQn                 = 83,        /*!< TMRB5 input capture 0 interrupt                             */
+  INTCAP51_IRQn                 = 84,        /*!< TMRB5 input capture 1 interrupt                             */
+  INTTB6_IRQn                   = 85,        /*!< TMRB6 compare match detection interrupt                     */
+  INTCAP60_IRQn                 = 86,        /*!< TMRB6 input capture 0 interrupt                             */
+  INTCAP61_IRQn                 = 87,        /*!< TMRB6 input capture 1 interrupt                             */
+  INTTB7_IRQn                   = 88,        /*!< TMRB7 compare match detection interrupt                     */
+  INTCAP70_IRQn                 = 89,        /*!< TMRB7 input capture 0 interrupt                             */
+  INTCAP71_IRQn                 = 90,        /*!< TMRB7 input capture 1 interrupt                             */
+  INTRTC_IRQn                   = 91,        /*!< Real time clock interrupt                                   */
+  INTDMAA_IRQn                  = 92,        /*!< DMAC unitA transmission completion interrupt(ch4-31)        */
+  INTDMAB_IRQn                  = 93,        /*!< DMAC unitB transmission completion interrupt(ch24-31)       */
+  INTDMAC_IRQn                  = 94,        /*!< DMAC unitC transmission completion interrupt(ch12-31)       */
+  INTDMACTC8_IRQn               = 95,        /*!< DMAC unitC transmission completion interrupt(ch8)           */
+  INTDMACTC9_IRQn               = 96,        /*!< DMAC unitC transmission completion interrupt(ch9)           */
+  INTDMACTC10_IRQn              = 97,        /*!< DMAC unitC transmission completion interrupt(ch10)          */
+  INTDMACTC11_IRQn              = 98,        /*!< DMAC unitC transmission completion interrupt(ch11)          */
+  INTDMAAERR_IRQn               = 99,        /*!< DMAC transmission error interrupt(unitA)                    */
+  INTDMABERR_IRQn               = 100,       /*!< DMAC transmission error interrupt(unitB)                    */
+  INTDMACERR_IRQn               = 101,       /*!< DMAC transmission error interrupt(unitC)                    */
+  INTFLRDY_IRQn                 = 102        /*!< Flash Ready interrupt                                       */
+} IRQn_Type;
+
+/** Processor and Core Peripheral Section */
+
+/* Configuration of the Cortex-M4 Processor and Core Peripherals */
+#define __CM4_REV              0x0001       /*!< Cortex-M4 Core Revision                           */
+#define __MPU_PRESENT             0         /*!< MPU present or not                                */
+#define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels           */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used      */
+#define __FPU_PRESENT							1					/*!< FPU present or not                                */
+
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h"                       /* Cortex-M4 processor and core peripherals            */
+#include "system_TMPM46B.h"                 /* TMPM46B System                                      */
+
+/** @addtogroup Device_Peripheral_registers
+  * @{
+  */
+
+/** Device Specific Peripheral registers structures */
+
+/**
+  * @brief Synchronous Serial Port
+  */
+typedef struct
+{
+  __IO uint32_t CR0;               /*!< SSP Control Register 0                       */
+  __IO uint32_t CR1;               /*!< SSP Control Register 1                       */
+  __IO uint32_t DR;                /*!< SSP Data Register                            */
+  __I  uint32_t SR;                /*!< SSP Status Register                          */
+  __IO uint32_t CPSR;              /*!< SSP Clock Prescaler Register                 */
+  __IO uint32_t IMSC;              /*!< SSP Interrupt Mask Set and Clear Register    */
+  __I  uint32_t RIS;               /*!< SSP Raw Interrupt Status Register            */
+  __I  uint32_t MIS;               /*!< SSP Masked Interrupt Status Register         */
+  __O  uint32_t ICR;               /*!< SSP Interrupt Clear Register                 */
+  __IO uint32_t DMACR;             /*!< SSP DMA Control Register                     */
+} TSB_SSP_TypeDef;
+
+#if defined ( __CC_ARM   )           /* RealView Compiler */
+#pragma anon_unions
+#elif (defined (__ICCARM__))         /*  ICC Compiler     */
+#pragma language=extended
+#endif
+
+/**
+  * @brief UART
+  */
+typedef struct
+{
+  __IO uint32_t DR;                /*!< Data Register                                */
+union {
+  __I  uint32_t RSR;               /*!< Receive Status Register                      */
+  __O  uint32_t ECR;               /*!< Error Clear Register                         */
+  };
+       uint32_t RESERVED0[4];
+  __I  uint32_t FR;                /*!< Flag Register                                */
+       uint32_t RESERVED1;
+  __IO uint32_t ILPR;              /*!< UART IrDA lowPower count register            */
+  __IO uint32_t IBRD;              /*!< Integer Baud Rate Register                   */
+  __IO uint32_t FBRD;              /*!< Fractional Baud Rate Register                */
+  __IO uint32_t LCR_H;             /*!< Line Control Register                        */
+  __IO uint32_t CR;                /*!< Control Register                             */
+  __IO uint32_t IFLS;              /*!< Interrupt FIFO Level Selection Register      */
+  __IO uint32_t IMSC;              /*!< Interrupt Mask Set/Clear Register            */
+  __I  uint32_t RIS;               /*!< Raw Interrupt Status Register                */
+  __I  uint32_t MIS;               /*!< Masked Interrupt Status Register             */
+  __O  uint32_t ICR;               /*!< Interrupt Clear Register                     */
+  __IO uint32_t DMACR;             /*!< DMA Control Register                         */
+} TSB_UART_TypeDef;
+
+/**
+  * @brief DMA Controller
+  */
+typedef struct
+{
+  __I  uint32_t STATUS;            /*!< DMA Status Register                          */
+  __O  uint32_t CFG;               /*!< DMA Configuration Register                   */
+  __IO uint32_t CTRLBASEPTR;       /*!< DMA Control Data Base Pointer Register       */
+  __I  uint32_t ALTCTRLBASEPTR;    /*!< DMA Channel Alternate Control Data Base Pointer Register*/
+       uint32_t RESERVED0;
+  __O  uint32_t CHNLSWREQUEST;     /*!< DMA Channel Software Request Register        */
+  __IO uint32_t CHNLUSEBURSTSET;   /*!< DMA Channel Useburst Set Register            */
+  __O  uint32_t CHNLUSEBURSTCLR;   /*!< DMA Channel Useburst Clear Register          */
+  __IO uint32_t CHNLREQMASKSET;    /*!< DMA Channel Request Mask Set Register        */
+  __O  uint32_t CHNLREQMASKCLR;    /*!< DMA Channel Request Mask Clear Register      */
+  __IO uint32_t CHNLENABLESET;     /*!< DMA Channel Enable Set Register              */
+  __O  uint32_t CHNLENABLECLR;     /*!< DMA Channel Enable Clear Register            */
+  __IO uint32_t CHNLPRIALTSET;     /*!< DMA Channel Primary-Alternate Set Register   */
+  __O  uint32_t CHNLPRIALTCLR;     /*!< DMA Channel Primary-Alternate Clear Register */
+  __IO uint32_t CHNLPRIORITYSET;   /*!< DMA Channel Priority Set Register            */
+  __O  uint32_t CHNLPRIORITYCLR;   /*!< DMA Channel Priority Clear Register          */
+       uint32_t RESERVED1[3];
+  __IO uint32_t ERRCLR;            /*!< DMA Bus Error Clear Register                 */
+} TSB_DMA_TypeDef;
+
+/**
+  * @brief 12bit A/D Converter
+  */
+typedef struct
+{
+  __IO uint32_t CLK;               /*!< Conversion Clock Setting Register            */
+  __O  uint32_t MOD0;              /*!< Mode Control Register0                       */
+  __IO uint32_t MOD1;              /*!< Mode Control Register1                       */
+  __IO uint32_t MOD2;              /*!< Mode Control Register2                       */
+  __IO uint32_t MOD3;              /*!< Mode Control Register3                       */
+  __IO uint32_t MOD4;              /*!< Mode Control Register4                       */
+  __I  uint32_t MOD5;              /*!< Mode Control Register5                       */
+  __O  uint32_t MOD6;              /*!< Mode Control Register6                       */
+       uint32_t RESERVED0;
+  __IO uint32_t CMPCR0;            /*!< Monitoring Interrupt Control Register0       */
+  __IO uint32_t CMPCR1;            /*!< Monitoring Interrupt Control Register1       */
+  __IO uint32_t CMP0;              /*!< Conversion Result Compare Register0          */
+  __IO uint32_t CMP1;              /*!< Conversion Result Compare Register1          */
+  __I  uint32_t REG00;             /*!< Conversion Result Store Register0            */
+  __I  uint32_t REG01;             /*!< Conversion Result Store Register1            */
+  __I  uint32_t REG02;             /*!< Conversion Result Store Register2            */
+  __I  uint32_t REG03;             /*!< Conversion Result Store Register3            */
+  __I  uint32_t REG04;             /*!< Conversion Result Store Register4            */
+  __I  uint32_t REG05;             /*!< Conversion Result Store Register5            */
+  __I  uint32_t REG06;             /*!< Conversion Result Store Register6            */
+  __I  uint32_t REG07;             /*!< Conversion Result Store Register7            */
+       uint32_t RESERVED1[8];
+  __I  uint32_t REGSP;             /*!< Highest Priority Conversion Result Store Register*/
+} TSB_AD_TypeDef;
+
+/**
+  * @brief External Bus Interface(EXB)
+  */
+typedef struct
+{
+  __IO uint32_t MOD;               /*!< External Bus Mode Control Register           */
+       uint32_t RESERVED0[3];
+  __IO uint32_t AS0;               /*!< External Bus Base Address and CS Space setting Register 0*/
+  __IO uint32_t AS1;               /*!< External Bus Base Address and CS Space setting Register 1 */
+  __IO uint32_t AS2;               /*!< External Bus Base Address and CS Space setting Register 2*/
+  __IO uint32_t AS3;               /*!< External Bus Base Address and CS Space setting Register 3*/
+       uint32_t RESERVED1[8];
+  __IO uint32_t CS0;               /*!< Chip Select and Wait Controller Register 0   */
+  __IO uint32_t CS1;               /*!< Chip Select and Wait Controller Register 1   */
+  __IO uint32_t CS2;               /*!< Chip Select and Wait Controller Register 2   */
+  __IO uint32_t CS3;               /*!< Chip Select and Wait Controller Register 3   */
+} TSB_EXB_TypeDef;
+
+/**
+  * @brief SNFC (SLC NAND Flash Controller) 
+  */
+typedef struct
+{
+  __IO uint32_t ENC;               /*!< SNFC Enable Control Register                 */
+  __IO uint32_t ECCMOD;            /*!< SNFC Ecc Mode Register                       */
+  __IO uint32_t IE;                /*!< SNFC Interrupt Enable Register               */
+       uint32_t RESERVED0;
+  __IO uint32_t PS;                /*!< SNFC Page Size Register                      */
+  __IO uint32_t PRCS;              /*!< SNFC Page Read Column Status Register        */
+  __IO uint32_t S;                 /*!< SNFC Sector Register                         */
+  __IO uint32_t SS;                /*!< SNFC Sector Status Register                  */
+  __IO uint32_t DIC;               /*!< SNFC Decode Input Count Register             */
+  __IO uint32_t DOC;               /*!< SNFC Decode Output Count Register            */
+  __IO uint32_t EIC;               /*!< SNFC Encode Input Count Register             */
+       uint32_t RESERVED1;
+  __IO uint32_t A1;                /*!< SNFC Address Register 1                      */
+  __IO uint32_t A2;                /*!< SNFC Address Register 2                      */
+  __IO uint32_t W;                 /*!< SNFC Write Register                          */
+  __IO uint32_t BIC;               /*!< SNFC Bus Interface Control Register          */
+  __IO uint32_t CS1;               /*!< SNFC Command Sequence Register 1             */
+  __IO uint32_t CS2;               /*!< SNFC Command Sequence Register 2             */
+  __IO uint32_t CS3;               /*!< SNFC Command Sequence Register 3             */
+  __IO uint32_t CS4;               /*!< SNFC Command Sequence Register 4             */
+  __IO uint32_t CSE;               /*!< SNFC Command Sequence Enable Register        */
+       uint32_t RESERVED2[43];
+  __I  uint32_t PRDB;              /*!< SNFC Page Read Buffer Registerer             */
+  __I  uint32_t IR1;               /*!< SNFC Id Read Register 1                      */
+  __I  uint32_t IR2;               /*!< SNFC Id Read Register 2                      */
+       uint32_t RESERVED3;
+  __I  uint32_t EP1;               /*!< SNFC Ecc Parity Register 1                   */
+  __I  uint32_t EP2;               /*!< SNFC Ecc Parity Register 2                   */
+  __I  uint32_t EP3;               /*!< SNFC Ecc Parity Register 3                   */
+  __I  uint32_t EP4;               /*!< SNFC Ecc Parity Register 4                   */
+  __I  uint32_t EC;                /*!< SNFC Ecc Crc Register                        */
+       uint32_t RESERVED4[183];
+  __IO uint32_t EWRB;              /*!< SNFC Ecc Write Buffer Register               */
+       uint32_t RESERVED5[255];
+  __I  uint32_t CDRB;              /*!< SNFC Correction Data Read Buffer Register    */
+  __I  uint32_t EOC;               /*!< SNFC Ecc Output Control Register             */
+  __I  uint32_t EBS;               /*!< SNFC Ecc Busy Status Register                */
+       uint32_t RESERVED6[5];
+  __I  uint32_t EES;               /*!< SNFC Ecc Error Status Register               */
+       uint32_t RESERVED7[7];
+  __I  uint32_t EDS1;              /*!< SNFC Ecc Decode State Register 1             */
+  __I  uint32_t EDS2;              /*!< SNFC Ecc Decode State Register 2             */
+  __I  uint32_t EDS3;              /*!< SNFC Ecc Decode State Register 3             */
+  __I  uint32_t EDS4;              /*!< SNFC Ecc Decode State Register 4             */
+  __I  uint32_t EDS5;              /*!< SNFC Ecc Decode State Register 5             */
+  __I  uint32_t EDS6;              /*!< SNFC Ecc Decode State Register 6             */
+  __I  uint32_t EDS7;              /*!< SNFC Ecc Decode State Register 7             */
+  __I  uint32_t EDS8;              /*!< SNFC Ecc Decode State Register 8             */
+       uint32_t RESERVED8[8];
+  __I  uint32_t S1EE1PI;           /*!< SNFC Sector 1 Ecc Error 1  Positional Information Register*/
+  __I  uint32_t S1EE2PI;           /*!< SNFC Sector 1 Ecc Error 2  Positional Information Register*/
+  __I  uint32_t S1EE3PI;           /*!< SNFC Sector 1 Ecc Error 3  Positional Information Register*/
+  __I  uint32_t S1EE4PI;           /*!< SNFC Sector 1 Ecc Error 4  Positional Information Register*/
+  __I  uint32_t S2EE1PI;           /*!< SNFC Sector 2 Ecc Error 1  Positional Information Register*/
+  __I  uint32_t S2EE2PI;           /*!< SNFC Sector 2 Ecc Error 2  Positional Information Register*/
+  __I  uint32_t S2EE3PI;           /*!< SNFC Sector 2 Ecc Error 3  Positional Information Register*/
+  __I  uint32_t S2EE4PI;           /*!< SNFC Sector 2 Ecc Error 4  Positional Information Register*/
+  __I  uint32_t S3EE1PI;           /*!< SNFC Sector 3 Ecc Error 1  Positional Information Register*/
+  __I  uint32_t S3EE2PI;           /*!< SNFC Sector 3 Ecc Error 2  Positional Information Register*/
+  __I  uint32_t S3EE3PI;           /*!< SNFC Sector 3 Ecc Error 3  Positional Information Register*/
+  __I  uint32_t S3EE4PI;           /*!< SNFC Sector 3 Ecc Error 4  Positional Information Register*/
+  __I  uint32_t S4EE1PI;           /*!< SNFC Sector 4 Ecc Error 1  Positional Information Register*/
+  __I  uint32_t S4EE2PI;           /*!< SNFC Sector 4 Ecc Error 2  Positional Information Register*/
+  __I  uint32_t S4EE3PI;           /*!< SNFC Sector 4 Ecc Error 3  Positional Information Register*/
+  __I  uint32_t S4EE4PI;           /*!< SNFC Sector 4 Ecc Error 4  Positional Information Register*/
+  __I  uint32_t S5EE1PI;           /*!< SNFC Sector 5 Ecc Error 1  Positional Information Register*/
+  __I  uint32_t S5EE2PI;           /*!< SNFC Sector 5 Ecc Error 2  Positional Information Register*/
+  __I  uint32_t S5EE3PI;           /*!< SNFC Sector 5 Ecc Error 3  Positional Information Register*/
+  __I  uint32_t S5EE4PI;           /*!< SNFC Sector 5 Ecc Error 4  Positional Information Register*/
+  __I  uint32_t S6EE1PI;           /*!< SNFC Sector 6 Ecc Error 1  Positional Information Register*/
+  __I  uint32_t S6EE2PI;           /*!< SNFC Sector 6 Ecc Error 2  Positional Information Register*/
+  __I  uint32_t S6EE3PI;           /*!< SNFC Sector 6 Ecc Error 3  Positional Information Register*/
+  __I  uint32_t S6EE4PI;           /*!< SNFC Sector 6 Ecc Error 4  Positional Information Register*/
+  __I  uint32_t S7EE1PI;           /*!< SNFC Sector 7 Ecc Error 1  Positional Information Register*/
+  __I  uint32_t S7EE2PI;           /*!< SNFC Sector 7 Ecc Error 2  Positional Information Register*/
+  __I  uint32_t S7EE3PI;           /*!< SNFC Sector 7 Ecc Error 3  Positional Information Register*/
+  __I  uint32_t S7EE4PI;           /*!< SNFC Sector 7 Ecc Error 4  Positional Information Register*/
+  __I  uint32_t S8EE1PI;           /*!< SNFC Sector 8 Ecc Error 1  Positional Information Register*/
+  __I  uint32_t S8EE2PI;           /*!< SNFC Sector 8 Ecc Error 2  Positional Information Register*/
+  __I  uint32_t S8EE3PI;           /*!< SNFC Sector 8 Ecc Error 3  Positional Information Register*/
+  __I  uint32_t S8EE4PI;           /*!< SNFC Sector 8 Ecc Error 4  Positional Information Register*/
+} TSB_SNFC_TypeDef;
+
+/**
+  * @brief DMA Interrupt Flag
+  */
+typedef struct
+{
+  __I  uint32_t FLGA;              /*!< DMA Flag Register A                          */
+  __I  uint32_t FLGB;              /*!< DMA Flag Register B                          */
+  __I  uint32_t FLGC;              /*!< DMA Flag Register C                          */
+} TSB_DMAIF_TypeDef;
+
+/**
+  * @brief ADC infterface Register
+  */
+typedef struct
+{
+       uint32_t RESERVED0[4];
+  __IO uint32_t TRGSEL;            /*!< Trigger Selection Register                   */
+} TSB_ADILV_TypeDef;
+
+/**
+  * @brief I2C Bus Interface (I2C)
+  */
+typedef struct
+{
+  __IO uint32_t CR1;               /*!< I2C Control Register 1                       */
+  __IO uint32_t DBR;               /*!< Data Buffer Register                         */
+  __IO uint32_t AR;                /*!< Bus address Register                         */
+union {
+  __O  uint32_t CR2;               /*!<  Control Register 1                          */
+  __I  uint32_t SR;                /*!< Status Register                              */
+  };
+  __IO uint32_t PRS;               /*!< Prescaler clcok setting Register             */
+  __IO uint32_t IE;                /*!< Interrupt Enable Register                    */
+  __IO uint32_t IR;                /*!< Interrupt Register                           */
+} TSB_I2C_TypeDef;
+
+/**
+  * @brief Advanced Encryption Standard (AES)
+  */
+typedef struct
+{
+  __O  uint32_t DT;                /*!< Plaintext/encrypted text data Register       */
+  __IO uint32_t KEY7;              /*!< Input Key Data Register (bit 31 - 0)         */
+  __IO uint32_t KEY6;              /*!< Input Key Data Register (bit 63 - 32)        */
+  __IO uint32_t KEY5;              /*!< Input Key Data Register (bit 95 - 64)        */
+  __IO uint32_t KEY4;              /*!< Input Key Data Register (bit 127 - 96)       */
+  __IO uint32_t KEY3;              /*!< Input Key Data Register (bit 159 - 128)      */
+  __IO uint32_t KEY2;              /*!< Input Key Data Register (bit 191 - 160)      */
+  __IO uint32_t KEY1;              /*!< Input Key Data Register (bit 223 - 192)      */
+  __IO uint32_t KEY0;              /*!< Input Key Data Register (bit 255 - 224)      */
+  __IO uint32_t CNT3;              /*!< Counter Initial Value Register (bit 31 - 0)  */
+  __IO uint32_t CNT2;              /*!< Counter Initial Value Register (bit 63 - 32) */
+  __IO uint32_t CNT1;              /*!< Counter Initial Value Register (bit 95 - 64) */
+  __IO uint32_t CNT0;              /*!< Counter Initial Value Register (bit 127 - 96)*/
+  __IO uint32_t IV3;               /*!< Initial Vector Register (bit 31 - 0)         */
+  __IO uint32_t IV2;               /*!< Initial Vector Register (bit 63 - 32)        */
+  __IO uint32_t IV1;               /*!< Initial Vector Register (bit 95 - 64)        */
+  __IO uint32_t IV0;               /*!< Initial Vector Register (bit 127 - 96)       */
+  __I  uint32_t ODT;               /*!< Calculation Result Store Register            */
+  __I  uint32_t RKEY7;             /*!< Output Key Store Register (bit 31 - 0)       */
+  __I  uint32_t RKEY6;             /*!< Output Key Store Register (bit 63 - 32)      */
+  __I  uint32_t RKEY5;             /*!< Output Key Store Register (bit 95 - 64)      */
+  __I  uint32_t RKEY4;             /*!< Output Key Store Register (bit 127 - 96)     */
+  __I  uint32_t RKEY3;             /*!< Output Key Store Register (bit 159 - 128)    */
+  __I  uint32_t RKEY2;             /*!< Output Key Store Register (bit 191 - 160)    */
+  __I  uint32_t RKEY1;             /*!< Output Key Store Register (bit 223 - 192)    */
+  __I  uint32_t RKEY0;             /*!< Output Key Store Register (bit 255 - 224)    */
+  __O  uint32_t CLR;               /*!< FIFO Clear Register                          */
+  __IO uint32_t MOD;               /*!< Mode Setting Register                        */
+  __I  uint32_t STATUS;            /*!< Status Register                              */
+} TSB_AES_TypeDef;
+
+/**
+  * @brief Secure Hash Algorithm Processor (SHA)
+  */
+typedef struct
+{
+  __O  uint32_t START;             /*!< Process Start Register                       */
+  __IO uint32_t CR;                /*!< Control Register                             */
+  __IO uint32_t DMAEN;             /*!< DMA Enable Register                          */
+  __IO uint32_t MSGLEN0;           /*!< Whole Message Length Register (bit 31 - 0)   */
+  __IO uint32_t MSGLEN1;           /*!< Whole Message Length Register (bit 60 - 32)  */
+  __IO uint32_t REMAIN0;           /*!< Unhandled Message Length Register (bit 31 - 0)*/
+  __IO uint32_t REMAIN1;           /*!< Unhandled Message Length Register (bit 60 - 32)*/
+  __IO uint32_t MSG00;             /*!< Message Register (bit 31 - 0)                */
+  __IO uint32_t MSG01;             /*!< Message Register (bit 63 - 32)               */
+  __IO uint32_t MSG02;             /*!< Message Register (bit 95 - 64)               */
+  __IO uint32_t MSG03;             /*!< Message Register (bit 127 - 96)              */
+  __IO uint32_t MSG04;             /*!< Message Register (bit 159 - 128)             */
+  __IO uint32_t MSG05;             /*!< Message Register (bit 191 - 160)             */
+  __IO uint32_t MSG06;             /*!< Message Register (bit 223 - 192)             */
+  __IO uint32_t MSG07;             /*!< Message Register (bit 255 - 224)             */
+  __IO uint32_t MSG08;             /*!< Message Register (bit 287 - 256)             */
+  __IO uint32_t MSG09;             /*!< Message Register (bit 319 - 288)             */
+  __IO uint32_t MSG10;             /*!< Message Register (bit 351 - 320)             */
+  __IO uint32_t MSG11;             /*!< Message Register (bit 383 - 352)             */
+  __IO uint32_t MSG12;             /*!< Message Register (bit 415 - 384)             */
+  __IO uint32_t MSG13;             /*!< Message Register (bit 447 - 416)             */
+  __IO uint32_t MSG14;             /*!< Message Register (bit 479 - 448)             */
+  __IO uint32_t MSG15;             /*!< Message Register (bit 511 - 480)             */
+  __IO uint32_t INIT0;             /*!< Hash Initial Value Register (bit 31 - 0)     */
+  __IO uint32_t INIT1;             /*!< Hash Initial Value Register (bit 63 - 32)    */
+  __IO uint32_t INIT2;             /*!< Hash Initial Value Register (bit 95 - 64)    */
+  __IO uint32_t INIT3;             /*!< Hash Initial Value Register (bit 127 - 96)   */
+  __IO uint32_t INIT4;             /*!< Hash Initial Value Register (bit 159 - 128)  */
+  __IO uint32_t INIT5;             /*!< Hash Initial Value Register (bit 191 - 160)  */
+  __IO uint32_t INIT6;             /*!< Hash Initial Value Register (bit 223 - 192)  */
+  __IO uint32_t INIT7;             /*!< Hash Initial Value Register (bit 255 - 224)  */
+  __I  uint32_t RESULT0;           /*!< Calculation Result Register (bit 31 - 0)     */
+  __I  uint32_t RESULT1;           /*!< Calculation Result Register (bit 63 - 32)    */
+  __I  uint32_t RESULT2;           /*!< Calculation Result Register (bit 95 - 64)    */
+  __I  uint32_t RESULT3;           /*!< Calculation Result Register (bit 127 - 96)   */
+  __I  uint32_t RESULT4;           /*!< Calculation Result Register (bit 159 - 128)  */
+  __I  uint32_t RESULT5;           /*!< Calculation Result Register (bit 191 - 160)  */
+  __I  uint32_t RESULT6;           /*!< Calculation Result Register (bit 223 - 192)  */
+  __I  uint32_t RESULT7;           /*!< Calculation Result Register (bit 255 - 224)  */
+  __I  uint32_t STATUS;            /*!< Status Register                              */
+} TSB_SHA_TypeDef;
+
+/**
+  * @brief Entropy Seed Generator (ESG)
+  */
+typedef struct
+{
+  __O  uint32_t CR;                /*!< Control Register                             */
+  __I  uint32_t ST;                /*!< Status Register                              */
+  __IO uint32_t OUTCR;             /*!< Output Control Register                      */
+  __IO uint32_t INT;               /*!< Interrupt Status Register                    */
+  __I  uint32_t BLK00;             /*!< Entropy Seed Store Block 00                  */
+  __I  uint32_t BLK01;             /*!< Entropy Seed Store Block 01                  */
+  __I  uint32_t BLK02;             /*!< Entropy Seed Store Block 02                  */
+  __I  uint32_t BLK03;             /*!< Entropy Seed Store Block 03                  */
+  __I  uint32_t BLK04;             /*!< Entropy Seed Store Block 04                  */
+  __I  uint32_t BLK05;             /*!< Entropy Seed Store Block 05                  */
+  __I  uint32_t BLK06;             /*!< Entropy Seed Store Block 06                  */
+  __I  uint32_t BLK07;             /*!< Entropy Seed Store Block 07                  */
+  __I  uint32_t BLK08;             /*!< Entropy Seed Store Block 08                  */
+  __I  uint32_t BLK09;             /*!< Entropy Seed Store Block 09                  */
+  __I  uint32_t BLK10;             /*!< Entropy Seed Store Block 10                  */
+  __I  uint32_t BLK11;             /*!< Entropy Seed Store Block 11                  */
+  __I  uint32_t BLK12;             /*!< Entropy Seed Store Block 12                  */
+  __I  uint32_t BLK13;             /*!< Entropy Seed Store Block 13                  */
+  __I  uint32_t BLK14;             /*!< Entropy Seed Store Block 14                  */
+  __I  uint32_t BLK15;             /*!< Entropy Seed Store Block 15                  */
+} TSB_ESG_TypeDef;
+
+/**
+  * @brief Soft Reset
+  */
+typedef struct
+{
+  __IO uint32_t PROTECT;           /*!< Soft reset protect Register                  */
+  __IO uint32_t IPRST;             /*!< Soft reset Register                          */
+} TSB_SRST_TypeDef;
+
+/**
+  * @brief Multiple Length Arithmetic Coprocessor (MLA)
+  */
+typedef struct
+{
+  __IO uint32_t CR;                /*!< Control Register                             */
+  __IO uint32_t ST;                /*!< Status Register                              */
+       uint32_t RESERVED0;
+  __IO uint32_t PARA;              /*!< Montgomery Parameter Register                */
+  __IO uint32_t BLK1_0;            /*!< General-purpose Register Block 1 (bit 31 - 0)*/
+  __IO uint32_t BLK1_1;            /*!< General-purpose Register Block 1 (bit 63 - 32)*/
+  __IO uint32_t BLK1_2;            /*!< General-purpose Register Block 1 (bit 95 - 64)*/
+  __IO uint32_t BLK1_3;            /*!< General-purpose Register Block 1 (bit 127 - 96)*/
+  __IO uint32_t BLK1_4;            /*!< General-purpose Register Block 1 (bit 159 - 128)*/
+  __IO uint32_t BLK1_5;            /*!< General-purpose Register Block 1 (bit 191 - 160)*/
+  __IO uint32_t BLK1_6;            /*!< General-purpose Register Block 1 (bit 223 - 192)*/
+  __IO uint32_t BLK1_7;            /*!< General-purpose Register Block 1 (bit 255 - 224)*/
+  __IO uint32_t BLK2_0;            /*!< General-purpose Register Block 2 (bit 31 - 0)*/
+  __IO uint32_t BLK2_1;            /*!< General-purpose Register Block 2 (bit 63 - 32)*/
+  __IO uint32_t BLK2_2;            /*!< General-purpose Register Block 2 (bit 95 - 64)*/
+  __IO uint32_t BLK2_3;            /*!< General-purpose Register Block 2 (bit 127 - 96)*/
+  __IO uint32_t BLK2_4;            /*!< General-purpose Register Block 2 (bit 159 - 128)*/
+  __IO uint32_t BLK2_5;            /*!< General-purpose Register Block 2 (bit 191 - 160)*/
+  __IO uint32_t BLK2_6;            /*!< General-purpose Register Block 2 (bit 223 - 192)*/
+  __IO uint32_t BLK2_7;            /*!< General-purpose Register Block 2 (bit 255 - 224)*/
+  __IO uint32_t BLK3_0;            /*!< General-purpose Register Block 3 (bit 31 - 0)*/
+  __IO uint32_t BLK3_1;            /*!< General-purpose Register Block 3 (bit 63 - 32)*/
+  __IO uint32_t BLK3_2;            /*!< General-purpose Register Block 3 (bit 95 - 64)*/
+  __IO uint32_t BLK3_3;            /*!< General-purpose Register Block 3 (bit 127 - 96)*/
+  __IO uint32_t BLK3_4;            /*!< General-purpose Register Block 3 (bit 159 - 128)*/
+  __IO uint32_t BLK3_5;            /*!< General-purpose Register Block 3 (bit 191 - 160)*/
+  __IO uint32_t BLK3_6;            /*!< General-purpose Register Block 3 (bit 223 - 192)*/
+  __IO uint32_t BLK3_7;            /*!< General-purpose Register Block 3 (bit 255 - 224)*/
+  __IO uint32_t BLK4_0;            /*!< General-purpose Register Block 4 (bit 31 - 0)*/
+  __IO uint32_t BLK4_1;            /*!< General-purpose Register Block 4 (bit 63 - 32)*/
+  __IO uint32_t BLK4_2;            /*!< General-purpose Register Block 4 (bit 95 - 64)*/
+  __IO uint32_t BLK4_3;            /*!< General-purpose Register Block 4 (bit 127 - 96)*/
+  __IO uint32_t BLK4_4;            /*!< General-purpose Register Block 4 (bit 159 - 128)*/
+  __IO uint32_t BLK4_5;            /*!< General-purpose Register Block 4 (bit 191 - 160)*/
+  __IO uint32_t BLK4_6;            /*!< General-purpose Register Block 4 (bit 223 - 192)*/
+  __IO uint32_t BLK4_7;            /*!< General-purpose Register Block 4 (bit 255 - 224)*/
+  __IO uint32_t BLK5_0;            /*!< General-purpose Register Block 5 (bit 31 - 0)*/
+  __IO uint32_t BLK5_1;            /*!< General-purpose Register Block 5 (bit 63 - 32)*/
+  __IO uint32_t BLK5_2;            /*!< General-purpose Register Block 5 (bit 95 - 64)*/
+  __IO uint32_t BLK5_3;            /*!< General-purpose Register Block 5 (bit 127 - 96)*/
+  __IO uint32_t BLK5_4;            /*!< General-purpose Register Block 5 (bit 159 - 128)*/
+  __IO uint32_t BLK5_5;            /*!< General-purpose Register Block 5 (bit 191 - 160)*/
+  __IO uint32_t BLK5_6;            /*!< General-purpose Register Block 5 (bit 223 - 192)*/
+  __IO uint32_t BLK5_7;            /*!< General-purpose Register Block 5 (bit 255 - 224)*/
+  __IO uint32_t BLK6_0;            /*!< General-purpose Register Block 6 (bit 31 - 0)*/
+  __IO uint32_t BLK6_1;            /*!< General-purpose Register Block 6 (bit 63 - 32)*/
+  __IO uint32_t BLK6_2;            /*!< General-purpose Register Block 6 (bit 95 - 64)*/
+  __IO uint32_t BLK6_3;            /*!< General-purpose Register Block 6 (bit 127 - 96)*/
+  __IO uint32_t BLK6_4;            /*!< General-purpose Register Block 6 (bit 159 - 128)*/
+  __IO uint32_t BLK6_5;            /*!< General-purpose Register Block 6 (bit 191 - 160)*/
+  __IO uint32_t BLK6_6;            /*!< General-purpose Register Block 6 (bit 223 - 192)*/
+  __IO uint32_t BLK6_7;            /*!< General-purpose Register Block 6 (bit 255 - 224)*/
+  __IO uint32_t BLK7_0;            /*!< General-purpose Register Block 7 (bit 31 - 0)*/
+  __IO uint32_t BLK7_1;            /*!< General-purpose Register Block 7 (bit 63 - 32)*/
+  __IO uint32_t BLK7_2;            /*!< General-purpose Register Block 7 (bit 95 - 64)*/
+  __IO uint32_t BLK7_3;            /*!< General-purpose Register Block 7 (bit 127 - 96)*/
+  __IO uint32_t BLK7_4;            /*!< General-purpose Register Block 7 (bit 159 - 128)*/
+  __IO uint32_t BLK7_5;            /*!< General-purpose Register Block 7 (bit 191 - 160)*/
+  __IO uint32_t BLK7_6;            /*!< General-purpose Register Block 7 (bit 223 - 192)*/
+  __IO uint32_t BLK7_7;            /*!< General-purpose Register Block 7 (bit 255 - 224)*/
+  __IO uint32_t BLK8_0;            /*!< General-purpose Register Block 8 (bit 31 - 0)*/
+  __IO uint32_t BLK8_1;            /*!< General-purpose Register Block 8 (bit 63 - 32)*/
+  __IO uint32_t BLK8_2;            /*!< General-purpose Register Block 8 (bit 95 - 64)*/
+  __IO uint32_t BLK8_3;            /*!< General-purpose Register Block 8 (bit 127 - 96)*/
+  __IO uint32_t BLK8_4;            /*!< General-purpose Register Block 8 (bit 159 - 128)*/
+  __IO uint32_t BLK8_5;            /*!< General-purpose Register Block 8 (bit 191 - 160)*/
+  __IO uint32_t BLK8_6;            /*!< General-purpose Register Block 8 (bit 223 - 192)*/
+  __IO uint32_t BLK8_7;            /*!< General-purpose Register Block 8 (bit 255 - 224)*/
+  __IO uint32_t BLK9_0;            /*!< General-purpose Register Block 9 (bit 31 - 0)*/
+  __IO uint32_t BLK9_1;            /*!< General-purpose Register Block 9 (bit 63 - 32)*/
+  __IO uint32_t BLK9_2;            /*!< General-purpose Register Block 9 (bit 95 - 64)*/
+  __IO uint32_t BLK9_3;            /*!< General-purpose Register Block 9 (bit 127 - 96)*/
+  __IO uint32_t BLK9_4;            /*!< General-purpose Register Block 9 (bit 159 - 128)*/
+  __IO uint32_t BLK9_5;            /*!< General-purpose Register Block 9 (bit 191 - 160)*/
+  __IO uint32_t BLK9_6;            /*!< General-purpose Register Block 9 (bit 223 - 192)*/
+  __IO uint32_t BLK9_7;            /*!< General-purpose Register Block 9 (bit 255 - 224)*/
+  __IO uint32_t BLK10_0;           /*!< General-purpose Register Block 10 (bit 31 - 0)*/
+  __IO uint32_t BLK10_1;           /*!< General-purpose Register Block 10 (bit 63 - 32)*/
+  __IO uint32_t BLK10_2;           /*!< General-purpose Register Block 10 (bit 95 - 64)*/
+  __IO uint32_t BLK10_3;           /*!< General-purpose Register Block 10 (bit 127 - 96)*/
+  __IO uint32_t BLK10_4;           /*!< General-purpose Register Block 10 (bit 159 - 128)*/
+  __IO uint32_t BLK10_5;           /*!< General-purpose Register Block 10 (bit 191 - 160)*/
+  __IO uint32_t BLK10_6;           /*!< General-purpose Register Block 10 (bit 223 - 192)*/
+  __IO uint32_t BLK10_7;           /*!< General-purpose Register Block 10 (bit 255 - 224)*/
+  __IO uint32_t BLK11_0;           /*!< General-purpose Register Block 11 (bit 31 - 0)*/
+  __IO uint32_t BLK11_1;           /*!< General-purpose Register Block 11 (bit 63 - 32)*/
+  __IO uint32_t BLK11_2;           /*!< General-purpose Register Block 11 (bit 95 - 64)*/
+  __IO uint32_t BLK11_3;           /*!< General-purpose Register Block 11 (bit 127 - 96)*/
+  __IO uint32_t BLK11_4;           /*!< General-purpose Register Block 11 (bit 159 - 128)*/
+  __IO uint32_t BLK11_5;           /*!< General-purpose Register Block 11 (bit 191 - 160)*/
+  __IO uint32_t BLK11_6;           /*!< General-purpose Register Block 11 (bit 223 - 192)*/
+  __IO uint32_t BLK11_7;           /*!< General-purpose Register Block 11 (bit 255 - 224)*/
+  __IO uint32_t BLK12_0;           /*!< General-purpose Register Block 12 (bit 31 - 0)*/
+  __IO uint32_t BLK12_1;           /*!< General-purpose Register Block 12 (bit 63 - 32)*/
+  __IO uint32_t BLK12_2;           /*!< General-purpose Register Block 12 (bit 95 - 64)*/
+  __IO uint32_t BLK12_3;           /*!< General-purpose Register Block 12 (bit 127 - 96)*/
+  __IO uint32_t BLK12_4;           /*!< General-purpose Register Block 12 (bit 159 - 128)*/
+  __IO uint32_t BLK12_5;           /*!< General-purpose Register Block 12 (bit 191 - 160)*/
+  __IO uint32_t BLK12_6;           /*!< General-purpose Register Block 12 (bit 223 - 192)*/
+  __IO uint32_t BLK12_7;           /*!< General-purpose Register Block 12 (bit 255 - 224)*/
+  __IO uint32_t BLK13_0;           /*!< General-purpose Register Block 13 (bit 31 - 0)*/
+  __IO uint32_t BLK13_1;           /*!< General-purpose Register Block 13 (bit 63 - 32)*/
+  __IO uint32_t BLK13_2;           /*!< General-purpose Register Block 13 (bit 95 - 64)*/
+  __IO uint32_t BLK13_3;           /*!< General-purpose Register Block 13 (bit 127 - 96)*/
+  __IO uint32_t BLK13_4;           /*!< General-purpose Register Block 13 (bit 159 - 128)*/
+  __IO uint32_t BLK13_5;           /*!< General-purpose Register Block 13 (bit 191 - 160)*/
+  __IO uint32_t BLK13_6;           /*!< General-purpose Register Block 13 (bit 223 - 192)*/
+  __IO uint32_t BLK13_7;           /*!< General-purpose Register Block 13 (bit 255 - 224)*/
+  __IO uint32_t BLK14_0;           /*!< General-purpose Register Block 14 (bit 31 - 0)*/
+  __IO uint32_t BLK14_1;           /*!< General-purpose Register Block 14 (bit 63 - 32)*/
+  __IO uint32_t BLK14_2;           /*!< General-purpose Register Block 14 (bit 95 - 64)*/
+  __IO uint32_t BLK14_3;           /*!< General-purpose Register Block 14 (bit 127 - 96)*/
+  __IO uint32_t BLK14_4;           /*!< General-purpose Register Block 14 (bit 159 - 128)*/
+  __IO uint32_t BLK14_5;           /*!< General-purpose Register Block 14 (bit 191 - 160)*/
+  __IO uint32_t BLK14_6;           /*!< General-purpose Register Block 14 (bit 223 - 192)*/
+  __IO uint32_t BLK14_7;           /*!< General-purpose Register Block 14 (bit 255 - 224)*/
+  __IO uint32_t BLK15_0;           /*!< General-purpose Register Block 15 (bit 31 - 0)*/
+  __IO uint32_t BLK15_1;           /*!< General-purpose Register Block 15 (bit 63 - 32)*/
+  __IO uint32_t BLK15_2;           /*!< General-purpose Register Block 15 (bit 95 - 64)*/
+  __IO uint32_t BLK15_3;           /*!< General-purpose Register Block 15 (bit 127 - 96)*/
+  __IO uint32_t BLK15_4;           /*!< General-purpose Register Block 15 (bit 159 - 128)*/
+  __IO uint32_t BLK15_5;           /*!< General-purpose Register Block 15 (bit 191 - 160)*/
+  __IO uint32_t BLK15_6;           /*!< General-purpose Register Block 15 (bit 223 - 192)*/
+  __IO uint32_t BLK15_7;           /*!< General-purpose Register Block 15 (bit 255 - 224)*/
+  __IO uint32_t BLK16_0;           /*!< General-purpose Register Block 16 (bit 31 - 0)*/
+  __IO uint32_t BLK16_1;           /*!< General-purpose Register Block 16 (bit 63 - 32)*/
+  __IO uint32_t BLK16_2;           /*!< General-purpose Register Block 16 (bit 95 - 64)*/
+  __IO uint32_t BLK16_3;           /*!< General-purpose Register Block 16 (bit 127 - 96)*/
+  __IO uint32_t BLK16_4;           /*!< General-purpose Register Block 16 (bit 159 - 128)*/
+  __IO uint32_t BLK16_5;           /*!< General-purpose Register Block 16 (bit 191 - 160)*/
+  __IO uint32_t BLK16_6;           /*!< General-purpose Register Block 16 (bit 223 - 192)*/
+  __IO uint32_t BLK16_7;           /*!< General-purpose Register Block 16 (bit 255 - 224)*/
+  __IO uint32_t BLK17_0;           /*!< General-purpose Register Block 17 (bit 31 - 0)*/
+  __IO uint32_t BLK17_1;           /*!< General-purpose Register Block 17 (bit 63 - 32)*/
+  __IO uint32_t BLK17_2;           /*!< General-purpose Register Block 17 (bit 95 - 64)*/
+  __IO uint32_t BLK17_3;           /*!< General-purpose Register Block 17 (bit 127 - 96)*/
+  __IO uint32_t BLK17_4;           /*!< General-purpose Register Block 17 (bit 159 - 128)*/
+  __IO uint32_t BLK17_5;           /*!< General-purpose Register Block 17 (bit 191 - 160)*/
+  __IO uint32_t BLK17_6;           /*!< General-purpose Register Block 17 (bit 223 - 192)*/
+  __IO uint32_t BLK17_7;           /*!< General-purpose Register Block 17 (bit 255 - 224)*/
+  __IO uint32_t BLK18_0;           /*!< General-purpose Register Block 18 (bit 31 - 0)*/
+  __IO uint32_t BLK18_1;           /*!< General-purpose Register Block 18 (bit 63 - 32)*/
+  __IO uint32_t BLK18_2;           /*!< General-purpose Register Block 18 (bit 95 - 64)*/
+  __IO uint32_t BLK18_3;           /*!< General-purpose Register Block 18 (bit 127 - 96)*/
+  __IO uint32_t BLK18_4;           /*!< General-purpose Register Block 18 (bit 159 - 128)*/
+  __IO uint32_t BLK18_5;           /*!< General-purpose Register Block 18 (bit 191 - 160)*/
+  __IO uint32_t BLK18_6;           /*!< General-purpose Register Block 18 (bit 223 - 192)*/
+  __IO uint32_t BLK18_7;           /*!< General-purpose Register Block 18 (bit 255 - 224)*/
+  __IO uint32_t BLK19_0;           /*!< General-purpose Register Block 19 (bit 31 - 0)*/
+  __IO uint32_t BLK19_1;           /*!< General-purpose Register Block 19 (bit 63 - 32)*/
+  __IO uint32_t BLK19_2;           /*!< General-purpose Register Block 19 (bit 95 - 64)*/
+  __IO uint32_t BLK19_3;           /*!< General-purpose Register Block 19 (bit 127 - 96)*/
+  __IO uint32_t BLK19_4;           /*!< General-purpose Register Block 19 (bit 159 - 128)*/
+  __IO uint32_t BLK19_5;           /*!< General-purpose Register Block 19 (bit 191 - 160)*/
+  __IO uint32_t BLK19_6;           /*!< General-purpose Register Block 19 (bit 223 - 192)*/
+  __IO uint32_t BLK19_7;           /*!< General-purpose Register Block 19 (bit 255 - 224)*/
+  __IO uint32_t BLK20_0;           /*!< General-purpose Register Block 20 (bit 31 - 0)*/
+  __IO uint32_t BLK20_1;           /*!< General-purpose Register Block 20 (bit 63 - 32)*/
+  __IO uint32_t BLK20_2;           /*!< General-purpose Register Block 20 (bit 95 - 64)*/
+  __IO uint32_t BLK20_3;           /*!< General-purpose Register Block 20 (bit 127 - 96)*/
+  __IO uint32_t BLK20_4;           /*!< General-purpose Register Block 20 (bit 159 - 128)*/
+  __IO uint32_t BLK20_5;           /*!< General-purpose Register Block 20 (bit 191 - 160)*/
+  __IO uint32_t BLK20_6;           /*!< General-purpose Register Block 20 (bit 223 - 192)*/
+  __IO uint32_t BLK20_7;           /*!< General-purpose Register Block 20 (bit 255 - 224)*/
+  __IO uint32_t BLK21_0;           /*!< General-purpose Register Block 21 (bit 31 - 0)*/
+  __IO uint32_t BLK21_1;           /*!< General-purpose Register Block 21 (bit 63 - 32)*/
+  __IO uint32_t BLK21_2;           /*!< General-purpose Register Block 21 (bit 95 - 64)*/
+  __IO uint32_t BLK21_3;           /*!< General-purpose Register Block 21 (bit 127 - 96)*/
+  __IO uint32_t BLK21_4;           /*!< General-purpose Register Block 21 (bit 159 - 128)*/
+  __IO uint32_t BLK21_5;           /*!< General-purpose Register Block 21 (bit 191 - 160)*/
+  __IO uint32_t BLK21_6;           /*!< General-purpose Register Block 21 (bit 223 - 192)*/
+  __IO uint32_t BLK21_7;           /*!< General-purpose Register Block 21 (bit 255 - 224)*/
+  __IO uint32_t BLK22_0;           /*!< General-purpose Register Block 22 (bit 31 - 0)*/
+  __IO uint32_t BLK22_1;           /*!< General-purpose Register Block 22 (bit 63 - 32)*/
+  __IO uint32_t BLK22_2;           /*!< General-purpose Register Block 22 (bit 95 - 64)*/
+  __IO uint32_t BLK22_3;           /*!< General-purpose Register Block 22 (bit 127 - 96)*/
+  __IO uint32_t BLK22_4;           /*!< General-purpose Register Block 22 (bit 159 - 128)*/
+  __IO uint32_t BLK22_5;           /*!< General-purpose Register Block 22 (bit 191 - 160)*/
+  __IO uint32_t BLK22_6;           /*!< General-purpose Register Block 22 (bit 223 - 192)*/
+  __IO uint32_t BLK22_7;           /*!< General-purpose Register Block 22 (bit 255 - 224)*/
+  __IO uint32_t BLK23_0;           /*!< General-purpose Register Block 23 (bit 31 - 0)*/
+  __IO uint32_t BLK23_1;           /*!< General-purpose Register Block 23 (bit 63 - 32)*/
+  __IO uint32_t BLK23_2;           /*!< General-purpose Register Block 23 (bit 95 - 64)*/
+  __IO uint32_t BLK23_3;           /*!< General-purpose Register Block 23 (bit 127 - 96)*/
+  __IO uint32_t BLK23_4;           /*!< General-purpose Register Block 23 (bit 159 - 128)*/
+  __IO uint32_t BLK23_5;           /*!< General-purpose Register Block 23 (bit 191 - 160)*/
+  __IO uint32_t BLK23_6;           /*!< General-purpose Register Block 23 (bit 223 - 192)*/
+  __IO uint32_t BLK23_7;           /*!< General-purpose Register Block 23 (bit 255 - 224)*/
+  __IO uint32_t BLK24_0;           /*!< General-purpose Register Block 24 (bit 31 - 0)*/
+  __IO uint32_t BLK24_1;           /*!< General-purpose Register Block 24 (bit 63 - 32)*/
+  __IO uint32_t BLK24_2;           /*!< General-purpose Register Block 24 (bit 95 - 64)*/
+  __IO uint32_t BLK24_3;           /*!< General-purpose Register Block 24 (bit 127 - 96)*/
+  __IO uint32_t BLK24_4;           /*!< General-purpose Register Block 24 (bit 159 - 128)*/
+  __IO uint32_t BLK24_5;           /*!< General-purpose Register Block 24 (bit 191 - 160)*/
+  __IO uint32_t BLK24_6;           /*!< General-purpose Register Block 24 (bit 223 - 192)*/
+  __IO uint32_t BLK24_7;           /*!< General-purpose Register Block 24 (bit 255 - 224)*/
+  __IO uint32_t BLK25_0;           /*!< General-purpose Register Block 25 (bit 31 - 0)*/
+  __IO uint32_t BLK25_1;           /*!< General-purpose Register Block 25 (bit 63 - 32)*/
+  __IO uint32_t BLK25_2;           /*!< General-purpose Register Block 25 (bit 95 - 64)*/
+  __IO uint32_t BLK25_3;           /*!< General-purpose Register Block 25 (bit 127 - 96)*/
+  __IO uint32_t BLK25_4;           /*!< General-purpose Register Block 25 (bit 159 - 128)*/
+  __IO uint32_t BLK25_5;           /*!< General-purpose Register Block 25 (bit 191 - 160)*/
+  __IO uint32_t BLK25_6;           /*!< General-purpose Register Block 25 (bit 223 - 192)*/
+  __IO uint32_t BLK25_7;           /*!< General-purpose Register Block 25 (bit 255 - 224)*/
+  __IO uint32_t BLK26_0;           /*!< General-purpose Register Block 26 (bit 31 - 0)*/
+  __IO uint32_t BLK26_1;           /*!< General-purpose Register Block 26 (bit 63 - 32)*/
+  __IO uint32_t BLK26_2;           /*!< General-purpose Register Block 26 (bit 95 - 64)*/
+  __IO uint32_t BLK26_3;           /*!< General-purpose Register Block 26 (bit 127 - 96)*/
+  __IO uint32_t BLK26_4;           /*!< General-purpose Register Block 26 (bit 159 - 128)*/
+  __IO uint32_t BLK26_5;           /*!< General-purpose Register Block 26 (bit 191 - 160)*/
+  __IO uint32_t BLK26_6;           /*!< General-purpose Register Block 26 (bit 223 - 192)*/
+  __IO uint32_t BLK26_7;           /*!< General-purpose Register Block 26 (bit 255 - 224)*/
+  __IO uint32_t BLK27_0;           /*!< General-purpose Register Block 27 (bit 31 - 0)*/
+  __IO uint32_t BLK27_1;           /*!< General-purpose Register Block 27 (bit 63 - 32)*/
+  __IO uint32_t BLK27_2;           /*!< General-purpose Register Block 27 (bit 95 - 64)*/
+  __IO uint32_t BLK27_3;           /*!< General-purpose Register Block 27 (bit 127 - 96)*/
+  __IO uint32_t BLK27_4;           /*!< General-purpose Register Block 27 (bit 159 - 128)*/
+  __IO uint32_t BLK27_5;           /*!< General-purpose Register Block 27 (bit 191 - 160)*/
+  __IO uint32_t BLK27_6;           /*!< General-purpose Register Block 27 (bit 223 - 192)*/
+  __IO uint32_t BLK27_7;           /*!< General-purpose Register Block 27 (bit 255 - 224)*/
+  __IO uint32_t BLK28_0;           /*!< General-purpose Register Block 28 (bit 31 - 0)*/
+  __IO uint32_t BLK28_1;           /*!< General-purpose Register Block 28 (bit 63 - 32)*/
+  __IO uint32_t BLK28_2;           /*!< General-purpose Register Block 28 (bit 95 - 64)*/
+  __IO uint32_t BLK28_3;           /*!< General-purpose Register Block 28 (bit 127 - 96)*/
+  __IO uint32_t BLK28_4;           /*!< General-purpose Register Block 28 (bit 159 - 128)*/
+  __IO uint32_t BLK28_5;           /*!< General-purpose Register Block 28 (bit 191 - 160)*/
+  __IO uint32_t BLK28_6;           /*!< General-purpose Register Block 28 (bit 223 - 192)*/
+  __IO uint32_t BLK28_7;           /*!< General-purpose Register Block 28 (bit 255 - 224)*/
+  __IO uint32_t BLK29_0;           /*!< General-purpose Register Block 29 (bit 31 - 0)*/
+  __IO uint32_t BLK29_1;           /*!< General-purpose Register Block 29 (bit 63 - 32)*/
+  __IO uint32_t BLK29_2;           /*!< General-purpose Register Block 29 (bit 95 - 64)*/
+  __IO uint32_t BLK29_3;           /*!< General-purpose Register Block 29 (bit 127 - 96)*/
+  __IO uint32_t BLK29_4;           /*!< General-purpose Register Block 29 (bit 159 - 128)*/
+  __IO uint32_t BLK29_5;           /*!< General-purpose Register Block 29 (bit 191 - 160)*/
+  __IO uint32_t BLK29_6;           /*!< General-purpose Register Block 29 (bit 223 - 192)*/
+  __IO uint32_t BLK29_7;           /*!< General-purpose Register Block 29 (bit 255 - 224)*/
+  __IO uint32_t BLK30_0;           /*!< General-purpose Register Block 30 (bit 31 - 0)*/
+  __IO uint32_t BLK30_1;           /*!< General-purpose Register Block 30 (bit 63 - 32)*/
+  __IO uint32_t BLK30_2;           /*!< General-purpose Register Block 30 (bit 95 - 64)*/
+  __IO uint32_t BLK30_3;           /*!< General-purpose Register Block 30 (bit 127 - 96)*/
+  __IO uint32_t BLK30_4;           /*!< General-purpose Register Block 30 (bit 159 - 128)*/
+  __IO uint32_t BLK30_5;           /*!< General-purpose Register Block 30 (bit 191 - 160)*/
+  __IO uint32_t BLK30_6;           /*!< General-purpose Register Block 30 (bit 223 - 192)*/
+  __IO uint32_t BLK30_7;           /*!< General-purpose Register Block 30 (bit 255 - 224)*/
+  __IO uint32_t BLK31_0;           /*!< General-purpose Register Block 31 (bit 31 - 0)*/
+  __IO uint32_t BLK31_1;           /*!< General-purpose Register Block 31 (bit 63 - 32)*/
+  __IO uint32_t BLK31_2;           /*!< General-purpose Register Block 31 (bit 95 - 64)*/
+  __IO uint32_t BLK31_3;           /*!< General-purpose Register Block 31 (bit 127 - 96)*/
+  __IO uint32_t BLK31_4;           /*!< General-purpose Register Block 31 (bit 159 - 128)*/
+  __IO uint32_t BLK31_5;           /*!< General-purpose Register Block 31 (bit 191 - 160)*/
+  __IO uint32_t BLK31_6;           /*!< General-purpose Register Block 31 (bit 223 - 192)*/
+  __IO uint32_t BLK31_7;           /*!< General-purpose Register Block 31 (bit 255 - 224)*/
+       uint32_t RESERVED1[260];
+  __IO uint32_t BLK0_0;            /*!< General-purpose Register Block 0 (bit 31 - 0)*/
+  __IO uint32_t BLK0_1;            /*!< General-purpose Register Block 0 (bit 63 - 32)*/
+  __IO uint32_t BLK0_2;            /*!< General-purpose Register Block 0 (bit 95 - 64)*/
+  __IO uint32_t BLK0_3;            /*!< General-purpose Register Block 0 (bit 127 - 96)*/
+  __IO uint32_t BLK0_4;            /*!< General-purpose Register Block 0 (bit 159 - 128)*/
+  __IO uint32_t BLK0_5;            /*!< General-purpose Register Block 0 (bit 191 - 160)*/
+  __IO uint32_t BLK0_6;            /*!< General-purpose Register Block 0 (bit 223 - 192)*/
+  __IO uint32_t BLK0_7;            /*!< General-purpose Register Block 0 (bit 255 - 224)*/
+} TSB_MLA_TypeDef;
+
+/**
+  * @brief Port A
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port A Data Register                         */
+  __IO uint32_t CR;                /*!< Port A Output Control Register               */
+  __IO uint32_t FR1;               /*!< Port A Function Register 1                   */
+  __IO uint32_t FR2;               /*!< Port A Function Register 2                   */
+  __IO uint32_t FR3;               /*!< Port A Function Register 3                   */
+  __IO uint32_t FR4;               /*!< Port A Function Register 4                   */
+  __IO uint32_t FR5;               /*!< Port A Function Register 5                   */
+       uint32_t RESERVED0[3];
+  __IO uint32_t OD;                /*!< Port A Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port A Pull-up Control Register              */
+  __IO uint32_t PDN;               /*!< Port A Pull-down Control Register            */
+       uint32_t RESERVED1;
+  __IO uint32_t IE;                /*!< Port A Input Control Register                */
+} TSB_PA_TypeDef;
+
+/**
+  * @brief Port B
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port B Data Register                         */
+  __IO uint32_t CR;                /*!< Port B Output Control Register               */
+  __IO uint32_t FR1;               /*!< Port B Function Register 1                   */
+  __IO uint32_t FR2;               /*!< Port B Function Register 2                   */
+  __IO uint32_t FR3;               /*!< Port B Function Register 3                   */
+  __IO uint32_t FR4;               /*!< Port B Function Register 4                   */
+  __IO uint32_t FR5;               /*!< Port B Function Register 5                   */
+       uint32_t RESERVED0[3];
+  __IO uint32_t OD;                /*!< Port B Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port B Pull-up Control Register              */
+       uint32_t RESERVED1[2];
+  __IO uint32_t IE;                /*!< Port B Input Control Register                */
+} TSB_PB_TypeDef;
+
+/**
+  * @brief Port C
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port C Data Register                         */
+  __IO uint32_t CR;                /*!< Port C Output Control Register               */
+  __IO uint32_t FR1;               /*!< Port C Function Register 1                   */
+  __IO uint32_t FR2;               /*!< Port C Function Register 2                   */
+       uint32_t RESERVED0[6];
+  __IO uint32_t OD;                /*!< Port C Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port C Pull-up Control Register              */
+       uint32_t RESERVED1[2];
+  __IO uint32_t IE;                /*!< Port C Input Control Register                */
+} TSB_PC_TypeDef;
+
+/**
+  * @brief Port D
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port D Data Register                         */
+  __IO uint32_t CR;                /*!< Port D Output Control Register               */
+  __IO uint32_t FR1;               /*!< Port D Function Register 1                   */
+       uint32_t RESERVED0[7];
+  __IO uint32_t OD;                /*!< Port D Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port D Pull-up Control Register              */
+       uint32_t RESERVED1[2];
+  __IO uint32_t IE;                /*!< Port D Input Control Register                */
+} TSB_PD_TypeDef;
+
+/**
+  * @brief Port E
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port E Data Register                         */
+  __IO uint32_t CR;                /*!< Port E Output Control Register               */
+  __IO uint32_t FR1;               /*!< Port E Function Register 1                   */
+       uint32_t RESERVED0;
+  __IO uint32_t FR3;               /*!< Port E Function Register 3                   */
+  __IO uint32_t FR4;               /*!< Port E Function Register 4                   */
+  __IO uint32_t FR5;               /*!< Port E Function Register 5                   */
+       uint32_t RESERVED1[3];
+  __IO uint32_t OD;                /*!< Port E Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port E Pull-up Control Register              */
+       uint32_t RESERVED2[2];
+  __IO uint32_t IE;                /*!< Port E Input Control Register                */
+} TSB_PE_TypeDef;
+
+/**
+  * @brief Port F
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port F Data Register                         */
+  __IO uint32_t CR;                /*!< Port F Output Control Register               */
+  __IO uint32_t FR1;               /*!< Port F Function Register 1                   */
+       uint32_t RESERVED0;
+  __IO uint32_t FR3;               /*!< Port F Function Register 3                   */
+  __IO uint32_t FR4;               /*!< Port F Function Register 4                   */
+  __IO uint32_t FR5;               /*!< Port F Function Register 5                   */
+       uint32_t RESERVED1[3];
+  __IO uint32_t OD;                /*!< Port F Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port E Pull-up Control Register              */
+       uint32_t RESERVED2[2];
+  __IO uint32_t IE;                /*!< Port F Input Control Register                */
+} TSB_PF_TypeDef;
+
+/**
+  * @brief Port G
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port G Data Register                         */
+  __IO uint32_t CR;                /*!< Port G Output Control Register               */
+  __IO uint32_t FR1;               /*!< Port G Function Register 1                   */
+       uint32_t RESERVED0;
+  __IO uint32_t FR3;               /*!< Port G Function Register 3                   */
+  __IO uint32_t FR4;               /*!< Port G Function Register 4                   */
+  __IO uint32_t FR5;               /*!< Port G Function Register 5                   */
+       uint32_t RESERVED1[3];
+  __IO uint32_t OD;                /*!< Port G Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port G Pull-up Control Register              */
+       uint32_t RESERVED2[2];
+  __IO uint32_t IE;                /*!< Port G Input Control Register                */
+} TSB_PG_TypeDef;
+
+/**
+  * @brief Port H
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port H Data Register                         */
+  __IO uint32_t CR;                /*!< Port H Output Control Register               */
+  __IO uint32_t FR1;               /*!< Port H Function Register 1                   */
+  __IO uint32_t FR2;               /*!< Port H Function Register 2                   */
+  __IO uint32_t FR3;               /*!< Port H Function Register 3                   */
+  __IO uint32_t FR4;               /*!< Port H Function Register 4                   */
+       uint32_t RESERVED0[4];
+  __IO uint32_t OD;                /*!< Port H Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port H Pull-up Control Register              */
+       uint32_t RESERVED1[2];
+  __IO uint32_t IE;                /*!< Port H Input Control Register                */
+} TSB_PH_TypeDef;
+
+/**
+  * @brief Port J
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port J Data Register                         */
+  __IO uint32_t CR;                /*!< Port J Output Control Register               */
+  __IO uint32_t FR1;               /*!< Port J Function Register 1                   */
+  __IO uint32_t FR2;               /*!< Port J Function Register 2                   */
+  __IO uint32_t FR3;               /*!< Port J Function Register 3                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t OD;                /*!< Port J Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port J Pull-up Control Register              */
+       uint32_t RESERVED1[2];
+  __IO uint32_t IE;                /*!< Port J Input Control Register                */
+} TSB_PJ_TypeDef;
+
+/**
+  * @brief Port K
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port K Data Register                         */
+  __IO uint32_t CR;                /*!< Port K Output Control Register               */
+       uint32_t RESERVED0;
+  __IO uint32_t FR2;               /*!< Port K Function Register 2                   */
+  __IO uint32_t FR3;               /*!< Port K Function Register 3                   */
+  __IO uint32_t FR4;               /*!< Port K Function Register 4                   */
+       uint32_t RESERVED1[4];
+  __IO uint32_t OD;                /*!< Port K Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port K Pull-up Control Register              */
+       uint32_t RESERVED2[2];
+  __IO uint32_t IE;                /*!< Port K Input Control Register                */
+} TSB_PK_TypeDef;
+
+/**
+  * @brief Port L
+  */
+typedef struct
+{
+  __IO uint32_t DATA;              /*!< Port L Data Register                         */
+  __IO uint32_t CR;                /*!< Port L Output Control Register               */
+       uint32_t RESERVED0[2];
+  __IO uint32_t FR3;               /*!< Port L Function Register 3                   */
+  __IO uint32_t FR4;               /*!< Port L Function Register 4                   */
+  __IO uint32_t FR5;               /*!< Port L Function Register 5                   */
+  __IO uint32_t FR6;               /*!< Port L Function Register 6                   */
+       uint32_t RESERVED1[2];
+  __IO uint32_t OD;                /*!< Port L Open Drain Control Register           */
+  __IO uint32_t PUP;               /*!< Port L Pull-up Control Register              */
+       uint32_t RESERVED2[2];
+  __IO uint32_t IE;                /*!< Port L Input Control Register                */
+} TSB_PL_TypeDef;
+
+/**
+  * @brief 16-bit Timer/Event Counter (TB)
+  */
+typedef struct
+{
+  __IO uint32_t EN;                /*!< TB Enable Register                           */
+  __IO uint32_t RUN;               /*!< TB RUN Register                              */
+  __IO uint32_t CR;                /*!< TB Control Register                          */
+  __IO uint32_t MOD;               /*!< TB Mode Register                             */
+  __IO uint32_t FFCR;              /*!< TB Flip-Flop Control Register                */
+  __I  uint32_t ST;                /*!< TB Status Register                           */
+  __IO uint32_t IM;                /*!< TB Interrupt Mask Register                   */
+  __I  uint32_t UC;                /*!< TB Up-counter Capture Register               */
+  __IO uint32_t RG0;               /*!< TB RG0 Timer Register                        */
+  __IO uint32_t RG1;               /*!< TB RG1 Timer Register                        */
+  __I  uint32_t CP0;               /*!< TB CP0 Capture Register                      */
+  __I  uint32_t CP1;               /*!< TB CP1 Capture Register                      */
+} TSB_TB_TypeDef;
+
+/**
+  * @brief 16-bit Multi-Purpose Timer (MPT-TMR/IGBT)
+  */
+typedef struct
+{
+  __IO uint32_t EN;                /*!< MPT Enable Register                          */
+  __IO uint32_t RUN;               /*!< MPT RUN Register                             */
+  __IO uint32_t TBCR;              /*!< MPT Control Register                         */
+  __IO uint32_t TBMOD;             /*!< MPT Mode Register                            */
+  __IO uint32_t TBFFCR;            /*!< MPT Flip-Flop Control Register               */
+  __I  uint32_t TBST;              /*!< MPT Status Register                          */
+  __IO uint32_t TBIM;              /*!< MPT Interrupt Mask Register                  */
+  __I  uint32_t TBUC;              /*!< MPT Read Capture Register                    */
+  __IO uint32_t RG0;               /*!< MPT RG0 Timer Register                       */
+  __IO uint32_t RG1;               /*!< MPT RG1 Timer Register                       */
+  __I  uint32_t CP0;               /*!< MPT CP0 Capture Register                     */
+  __I  uint32_t CP1;               /*!< MPT CP1 Capture Register                     */
+  __IO uint32_t IGCR;              /*!< IGBT Control Register                        */
+  __O  uint32_t IGRESTA;           /*!< IGBT Timer Restart Register                  */
+  __I  uint32_t IGST;              /*!< IGBT Timer Status Register                   */
+  __IO uint32_t IGICR;             /*!< IGBT Input Control Register                  */
+  __IO uint32_t IGOCR;             /*!< IGBT Output Control Register                 */
+  __IO uint32_t IGRG2;             /*!< IGBT RG2 Timer Register                      */
+  __IO uint32_t IGRG3;             /*!< IGBT RG3 Timer Register                      */
+  __IO uint32_t IGRG4;             /*!< IGBT RG4 Timer Register                      */
+  __IO uint32_t IGEMGCR;           /*!< IGBT EMG Control Register                    */
+  __I  uint32_t IGEMGST;           /*!< IGBT EMG Status Register                     */
+  __IO uint32_t IGTRG;             /*!< IGBT Trigger Status Register                 */
+} TSB_MT_TypeDef;
+
+/**
+  * @brief Real Time Clock (RTC)
+  */
+typedef struct
+{
+  __IO uint8_t  SECR;              /*!< RTC Sec setting register                     */
+  __IO uint8_t  MINR;              /*!< RTC Min settging register                    */
+  __IO uint8_t  HOURR;             /*!< RTC Hour setting register                    */
+       uint8_t  RESERVED0;
+  __IO uint8_t  DAYR;              /*!< RTC Day setting register                     */
+  __IO uint8_t  DATER;             /*!< RTC Date setting register                    */
+  __IO uint8_t  MONTHR;            /*!< RTC Month settging register PAGE0            */
+  __IO uint8_t  YEARR;             /*!< RTC Year setting register PAGE0              */
+  __IO uint8_t  PAGER;             /*!< RTC Page register                            */
+       uint8_t  RESERVED1[3];
+  __IO uint8_t  RESTR;             /*!< RTC Reset register                           */
+       uint8_t  RESERVED2;
+  __IO uint8_t  PROTECT;           /*!< RTC protect register                         */
+  __IO uint8_t  ADJCTL;            /*!< RTC clock adjust control register            */
+  __IO uint16_t ADJDAT;            /*!< RTC clock adjust data register               */
+} TSB_RTC_TypeDef;
+
+/**
+  * @brief Serial Channel (SC)
+  */
+typedef struct
+{
+  __IO uint32_t EN;                /*!< SC Enable Register                           */
+  __IO uint32_t BUF;               /*!< SC Buffer Register                           */
+  __IO uint32_t CR;                /*!< SC Control Register                          */
+  __IO uint32_t MOD0;              /*!< SC Mode Control Register 0                   */
+  __IO uint32_t BRCR;              /*!< SC Baud Rate Generator Control Register      */
+  __IO uint32_t BRADD;             /*!< SC Baud Rate Generator Control Register 2    */
+  __IO uint32_t MOD1;              /*!< SC Mode Control Register 1                   */
+  __IO uint32_t MOD2;              /*!< SC Mode Control Register 2                   */
+  __IO uint32_t RFC;               /*!< SC RX FIFO Configuration Register            */
+  __IO uint32_t TFC;               /*!< SC TX FIFO Configuration Register            */
+  __I  uint32_t RST;               /*!< SC RX FIFO Status Register                   */
+  __I  uint32_t TST;               /*!< SC TX FIFO Status Register                   */
+  __IO uint32_t FCNF;              /*!< SC FIFO Configuration Register               */
+} TSB_SC_TypeDef;
+
+/**
+  * @brief Watchdog Timer (WD)
+  */
+typedef struct
+{
+  __IO uint32_t MOD;               /*!< WD Mode Register                             */
+  __O  uint32_t CR;                /*!< WD Control Register                          */
+  __I  uint32_t FLG;               /*!< Flag Register                                */
+} TSB_WD_TypeDef;
+
+/**
+  * @brief Clock Generator (CG)
+  */
+typedef struct
+{
+  __IO uint32_t SYSCR;             /*!< System Control Register                      */
+  __IO uint32_t OSCCR;             /*!< Oscillation Control Register                 */
+  __IO uint32_t STBYCR;            /*!< Standby Control Register                     */
+  __IO uint32_t PLLSEL;            /*!< PLL Selection Register                       */
+       uint32_t RESERVED0[4];
+  __IO uint32_t FSYSMSKA;          /*!< fclk Supply Stop Register A                  */
+  __IO uint32_t FSYSMSKB;          /*!< fclk Supply Stop Register B                  */
+       uint32_t RESERVED1[5];
+  __IO uint32_t PROTECT;           /*!< Protect Register                             */
+  __IO uint32_t IMCGA;             /*!< CG Interrupt Mode Control Register A         */
+  __IO uint32_t IMCGB;             /*!< CG Interrupt Mode Control Register B         */
+       uint32_t RESERVED2[6];
+  __O  uint32_t ICRCG;             /*!< CG Interrupt Request Clear Register          */
+  __IO uint32_t RSTFLG;            /*!< Reset Flag Register                          */
+  __I  uint32_t NMIFLG;            /*!< NMI Flag Register                            */
+} TSB_CG_TypeDef;
+
+/**
+  * @brief Low voltage detecter
+  */
+typedef struct
+{
+       uint32_t RESERVED0;
+  __IO uint32_t CR1;               /*!< LVD detection control register 1             */
+} TSB_LVD_TypeDef;
+
+/**
+  * @brief Flash Control (FC)
+  */
+typedef struct
+{
+       uint32_t RESERVED0[4];
+  __IO uint32_t SECBIT;            /*!< Security Bit Register                        */
+       uint32_t RESERVED1[3];
+  __I  uint32_t PSR0;              /*!< Protect Status Register 0                    */
+       uint32_t RESERVED2[3];
+  __I  uint32_t PSR1;              /*!< Protect Status Register 1                    */
+       uint32_t RESERVED3[51];
+  __I  uint32_t SR;                /*!< Status Register                              */
+  __I  uint32_t SWPSR;             /*!< Swap Status Register                         */
+       uint32_t RESERVED4[14];
+  __IO uint32_t AREASEL;           /*!< Area Selection Register                      */
+       uint32_t RESERVED5;
+  __IO uint32_t CR;                /*!< Control Register                             */
+  __IO uint32_t STSCLR;            /*!< Status Clear Register                        */
+  __IO uint32_t WCLKCR;            /*!< WCLK Configuration Register                  */
+  __IO uint32_t PROGCR;            /*!< Program Counter Configuration Register       */
+  __IO uint32_t ERASECR;           /*!< Erase Counter Configuration Register         */
+} TSB_FC_TypeDef;
+
+
+/* Memory map */
+#define FLASH_BASE            (0x00000000UL)
+#define RAM_BASE              (0x20000000UL)
+#define PERI_BASE             (0x40000000UL)
+
+
+#define TSB_SSP0_BASE              (PERI_BASE  + 0x0040000UL)
+#define TSB_SSP1_BASE              (PERI_BASE  + 0x0041000UL)
+#define TSB_SSP2_BASE              (PERI_BASE  + 0x0042000UL)
+#define TSB_UART0_BASE             (PERI_BASE  + 0x0048000UL)
+#define TSB_UART1_BASE             (PERI_BASE  + 0x0049000UL)
+#define TSB_DMAA_BASE              (PERI_BASE  + 0x004C000UL)
+#define TSB_DMAB_BASE              (PERI_BASE  + 0x004D000UL)
+#define TSB_DMAC_BASE              (PERI_BASE  + 0x004E000UL)
+#define TSB_AD_BASE                (PERI_BASE  + 0x0050000UL)
+#define TSB_EXB_BASE               (PERI_BASE  + 0x005C000UL)
+#define TSB_SNFC_BASE              (PERI_BASE  + 0x005C400UL)
+#define TSB_DMAIF_BASE             (PERI_BASE  + 0x005F000UL)
+#define TSB_ADILV_BASE             (PERI_BASE  + 0x0066000UL)
+#define TSB_I2C0_BASE              (PERI_BASE  + 0x00A0000UL)
+#define TSB_I2C1_BASE              (PERI_BASE  + 0x00A1000UL)
+#define TSB_I2C2_BASE              (PERI_BASE  + 0x00A2000UL)
+#define TSB_AES_BASE               (PERI_BASE  + 0x00B8200UL)
+#define TSB_SHA_BASE               (PERI_BASE  + 0x00B8300UL)
+#define TSB_ESG_BASE               (PERI_BASE  + 0x00B8400UL)
+#define TSB_SRST_BASE              (PERI_BASE  + 0x00B8500UL)
+#define TSB_MLA_BASE               (PERI_BASE  + 0x00B9000UL)
+#define TSB_PA_BASE                (PERI_BASE  + 0x00C0000UL)
+#define TSB_PB_BASE                (PERI_BASE  + 0x00C0100UL)
+#define TSB_PC_BASE                (PERI_BASE  + 0x00C0200UL)
+#define TSB_PD_BASE                (PERI_BASE  + 0x00C0300UL)
+#define TSB_PE_BASE                (PERI_BASE  + 0x00C0400UL)
+#define TSB_PF_BASE                (PERI_BASE  + 0x00C0500UL)
+#define TSB_PG_BASE                (PERI_BASE  + 0x00C0600UL)
+#define TSB_PH_BASE                (PERI_BASE  + 0x00C0700UL)
+#define TSB_PJ_BASE                (PERI_BASE  + 0x00C0800UL)
+#define TSB_PK_BASE                (PERI_BASE  + 0x00C0900UL)
+#define TSB_PL_BASE                (PERI_BASE  + 0x00C0A00UL)
+#define TSB_TB0_BASE               (PERI_BASE  + 0x00C4000UL)
+#define TSB_TB1_BASE               (PERI_BASE  + 0x00C4100UL)
+#define TSB_TB2_BASE               (PERI_BASE  + 0x00C4200UL)
+#define TSB_TB3_BASE               (PERI_BASE  + 0x00C4300UL)
+#define TSB_TB4_BASE               (PERI_BASE  + 0x00C4400UL)
+#define TSB_TB5_BASE               (PERI_BASE  + 0x00C4500UL)
+#define TSB_TB6_BASE               (PERI_BASE  + 0x00C4600UL)
+#define TSB_TB7_BASE               (PERI_BASE  + 0x00C4700UL)
+#define TSB_MT0_BASE               (PERI_BASE  + 0x00C7000UL)
+#define TSB_MT1_BASE               (PERI_BASE  + 0x00C7100UL)
+#define TSB_MT2_BASE               (PERI_BASE  + 0x00C7200UL)
+#define TSB_MT3_BASE               (PERI_BASE  + 0x00C7300UL)
+#define TSB_RTC_BASE               (PERI_BASE  + 0x00CC000UL)
+#define TSB_SC0_BASE               (PERI_BASE  + 0x00E1000UL)
+#define TSB_SC1_BASE               (PERI_BASE  + 0x00E1100UL)
+#define TSB_SC2_BASE               (PERI_BASE  + 0x00E1200UL)
+#define TSB_SC3_BASE               (PERI_BASE  + 0x00E1300UL)
+#define TSB_WD_BASE                (PERI_BASE  + 0x00F2000UL)
+#define TSB_CG_BASE                (PERI_BASE  + 0x00F3000UL)
+#define TSB_LVD_BASE               (PERI_BASE  + 0x00F4000UL)
+#define TSB_FC_BASE                (PERI_BASE  + 0x1DFF0000UL)
+
+
+/* Peripheral declaration */
+#define TSB_SSP0                   ((    TSB_SSP_TypeDef *)  TSB_SSP0_BASE)
+#define TSB_SSP1                   ((    TSB_SSP_TypeDef *)  TSB_SSP1_BASE)
+#define TSB_SSP2                   ((    TSB_SSP_TypeDef *)  TSB_SSP2_BASE)
+#define TSB_UART0                  ((   TSB_UART_TypeDef *) TSB_UART0_BASE)
+#define TSB_UART1                  ((   TSB_UART_TypeDef *) TSB_UART1_BASE)
+#define TSB_DMAA                   ((    TSB_DMA_TypeDef *)  TSB_DMAA_BASE)
+#define TSB_DMAB                   ((    TSB_DMA_TypeDef *)  TSB_DMAB_BASE)
+#define TSB_DMAC                   ((    TSB_DMA_TypeDef *)  TSB_DMAC_BASE)
+#define TSB_AD                     ((     TSB_AD_TypeDef *)    TSB_AD_BASE)
+#define TSB_EXB                    ((    TSB_EXB_TypeDef *)   TSB_EXB_BASE)
+#define TSB_SNFC                   ((   TSB_SNFC_TypeDef *)  TSB_SNFC_BASE)
+#define TSB_DMAIF                  ((  TSB_DMAIF_TypeDef *) TSB_DMAIF_BASE)
+#define TSB_ADILV                  ((  TSB_ADILV_TypeDef *) TSB_ADILV_BASE)
+#define TSB_I2C0                   ((    TSB_I2C_TypeDef *)  TSB_I2C0_BASE)
+#define TSB_I2C1                   ((    TSB_I2C_TypeDef *)  TSB_I2C1_BASE)
+#define TSB_I2C2                   ((    TSB_I2C_TypeDef *)  TSB_I2C2_BASE)
+#define TSB_AES                    ((    TSB_AES_TypeDef *)   TSB_AES_BASE)
+#define TSB_SHA                    ((    TSB_SHA_TypeDef *)   TSB_SHA_BASE)
+#define TSB_ESG                    ((    TSB_ESG_TypeDef *)   TSB_ESG_BASE)
+#define TSB_SRST                   ((   TSB_SRST_TypeDef *)  TSB_SRST_BASE)
+#define TSB_MLA                    ((    TSB_MLA_TypeDef *)   TSB_MLA_BASE)
+#define TSB_PA                     ((     TSB_PA_TypeDef *)    TSB_PA_BASE)
+#define TSB_PB                     ((     TSB_PB_TypeDef *)    TSB_PB_BASE)
+#define TSB_PC                     ((     TSB_PC_TypeDef *)    TSB_PC_BASE)
+#define TSB_PD                     ((     TSB_PD_TypeDef *)    TSB_PD_BASE)
+#define TSB_PE                     ((     TSB_PE_TypeDef *)    TSB_PE_BASE)
+#define TSB_PF                     ((     TSB_PF_TypeDef *)    TSB_PF_BASE)
+#define TSB_PG                     ((     TSB_PG_TypeDef *)    TSB_PG_BASE)
+#define TSB_PH                     ((     TSB_PH_TypeDef *)    TSB_PH_BASE)
+#define TSB_PJ                     ((     TSB_PJ_TypeDef *)    TSB_PJ_BASE)
+#define TSB_PK                     ((     TSB_PK_TypeDef *)    TSB_PK_BASE)
+#define TSB_PL                     ((     TSB_PL_TypeDef *)    TSB_PL_BASE)
+#define TSB_TB0                    ((     TSB_TB_TypeDef *)   TSB_TB0_BASE)
+#define TSB_TB1                    ((     TSB_TB_TypeDef *)   TSB_TB1_BASE)
+#define TSB_TB2                    ((     TSB_TB_TypeDef *)   TSB_TB2_BASE)
+#define TSB_TB3                    ((     TSB_TB_TypeDef *)   TSB_TB3_BASE)
+#define TSB_TB4                    ((     TSB_TB_TypeDef *)   TSB_TB4_BASE)
+#define TSB_TB5                    ((     TSB_TB_TypeDef *)   TSB_TB5_BASE)
+#define TSB_TB6                    ((     TSB_TB_TypeDef *)   TSB_TB6_BASE)
+#define TSB_TB7                    ((     TSB_TB_TypeDef *)   TSB_TB7_BASE)
+#define TSB_MT0                    ((     TSB_MT_TypeDef *)   TSB_MT0_BASE)
+#define TSB_MT1                    ((     TSB_MT_TypeDef *)   TSB_MT1_BASE)
+#define TSB_MT2                    ((     TSB_MT_TypeDef *)   TSB_MT2_BASE)
+#define TSB_MT3                    ((     TSB_MT_TypeDef *)   TSB_MT3_BASE)
+#define TSB_RTC                    ((    TSB_RTC_TypeDef *)   TSB_RTC_BASE)
+#define TSB_SC0                    ((     TSB_SC_TypeDef *)   TSB_SC0_BASE)
+#define TSB_SC1                    ((     TSB_SC_TypeDef *)   TSB_SC1_BASE)
+#define TSB_SC2                    ((     TSB_SC_TypeDef *)   TSB_SC2_BASE)
+#define TSB_SC3                    ((     TSB_SC_TypeDef *)   TSB_SC3_BASE)
+#define TSB_WD                     ((     TSB_WD_TypeDef *)    TSB_WD_BASE)
+#define TSB_CG                     ((     TSB_CG_TypeDef *)    TSB_CG_BASE)
+#define TSB_LVD                    ((    TSB_LVD_TypeDef *)   TSB_LVD_BASE)
+#define TSB_FC                     ((     TSB_FC_TypeDef *)    TSB_FC_BASE)
+
+
+/* Bit-Band for Device Specific Peripheral Registers */
+#define BITBAND_OFFSET (0x02000000UL)
+#define BITBAND_PERI_BASE (PERI_BASE + BITBAND_OFFSET)
+#define BITBAND_PERI(addr, bitnum) (BITBAND_PERI_BASE + (((uint32_t)(addr) - PERI_BASE) << 5) + ((uint32_t)(bitnum) << 2))
+
+
+
+/* Synchronous Serial Port */
+#define TSB_SSP0_CR0_SPO                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->CR0,6)))
+#define TSB_SSP0_CR0_SPH                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->CR0,7)))
+#define TSB_SSP0_CR1_LBM                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->CR1,0)))
+#define TSB_SSP0_CR1_SSE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->CR1,1)))
+#define TSB_SSP0_CR1_MS                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->CR1,2)))
+#define TSB_SSP0_CR1_SOD                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->CR1,3)))
+#define TSB_SSP0_SR_TFE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->SR,0)))
+#define TSB_SSP0_SR_TNF                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->SR,1)))
+#define TSB_SSP0_SR_RNE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->SR,2)))
+#define TSB_SSP0_SR_RFF                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->SR,3)))
+#define TSB_SSP0_SR_BSY                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->SR,4)))
+#define TSB_SSP0_IMSC_RORIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->IMSC,0)))
+#define TSB_SSP0_IMSC_RTIM                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->IMSC,1)))
+#define TSB_SSP0_IMSC_RXIM                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->IMSC,2)))
+#define TSB_SSP0_IMSC_TXIM                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->IMSC,3)))
+#define TSB_SSP0_RIS_RORRIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->RIS,0)))
+#define TSB_SSP0_RIS_RTRIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->RIS,1)))
+#define TSB_SSP0_RIS_RXRIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->RIS,2)))
+#define TSB_SSP0_RIS_TXRIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->RIS,3)))
+#define TSB_SSP0_MIS_RORMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->MIS,0)))
+#define TSB_SSP0_MIS_RTMIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->MIS,1)))
+#define TSB_SSP0_MIS_RXMIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->MIS,2)))
+#define TSB_SSP0_MIS_TXMIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP0->MIS,3)))
+#define TSB_SSP0_ICR_RORIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_SSP0->ICR,0)))
+#define TSB_SSP0_ICR_RTIC                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_SSP0->ICR,1)))
+#define TSB_SSP0_DMACR_RXDMAE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->DMACR,0)))
+#define TSB_SSP0_DMACR_TXDMAE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP0->DMACR,1)))
+
+#define TSB_SSP1_CR0_SPO                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->CR0,6)))
+#define TSB_SSP1_CR0_SPH                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->CR0,7)))
+#define TSB_SSP1_CR1_LBM                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->CR1,0)))
+#define TSB_SSP1_CR1_SSE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->CR1,1)))
+#define TSB_SSP1_CR1_MS                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->CR1,2)))
+#define TSB_SSP1_CR1_SOD                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->CR1,3)))
+#define TSB_SSP1_SR_TFE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->SR,0)))
+#define TSB_SSP1_SR_TNF                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->SR,1)))
+#define TSB_SSP1_SR_RNE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->SR,2)))
+#define TSB_SSP1_SR_RFF                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->SR,3)))
+#define TSB_SSP1_SR_BSY                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->SR,4)))
+#define TSB_SSP1_IMSC_RORIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->IMSC,0)))
+#define TSB_SSP1_IMSC_RTIM                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->IMSC,1)))
+#define TSB_SSP1_IMSC_RXIM                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->IMSC,2)))
+#define TSB_SSP1_IMSC_TXIM                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->IMSC,3)))
+#define TSB_SSP1_RIS_RORRIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->RIS,0)))
+#define TSB_SSP1_RIS_RTRIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->RIS,1)))
+#define TSB_SSP1_RIS_RXRIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->RIS,2)))
+#define TSB_SSP1_RIS_TXRIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->RIS,3)))
+#define TSB_SSP1_MIS_RORMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->MIS,0)))
+#define TSB_SSP1_MIS_RTMIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->MIS,1)))
+#define TSB_SSP1_MIS_RXMIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->MIS,2)))
+#define TSB_SSP1_MIS_TXMIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP1->MIS,3)))
+#define TSB_SSP1_ICR_RORIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_SSP1->ICR,0)))
+#define TSB_SSP1_ICR_RTIC                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_SSP1->ICR,1)))
+#define TSB_SSP1_DMACR_RXDMAE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->DMACR,0)))
+#define TSB_SSP1_DMACR_TXDMAE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP1->DMACR,1)))
+
+#define TSB_SSP2_CR0_SPO                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->CR0,6)))
+#define TSB_SSP2_CR0_SPH                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->CR0,7)))
+#define TSB_SSP2_CR1_LBM                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->CR1,0)))
+#define TSB_SSP2_CR1_SSE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->CR1,1)))
+#define TSB_SSP2_CR1_MS                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->CR1,2)))
+#define TSB_SSP2_CR1_SOD                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->CR1,3)))
+#define TSB_SSP2_SR_TFE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->SR,0)))
+#define TSB_SSP2_SR_TNF                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->SR,1)))
+#define TSB_SSP2_SR_RNE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->SR,2)))
+#define TSB_SSP2_SR_RFF                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->SR,3)))
+#define TSB_SSP2_SR_BSY                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->SR,4)))
+#define TSB_SSP2_IMSC_RORIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->IMSC,0)))
+#define TSB_SSP2_IMSC_RTIM                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->IMSC,1)))
+#define TSB_SSP2_IMSC_RXIM                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->IMSC,2)))
+#define TSB_SSP2_IMSC_TXIM                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->IMSC,3)))
+#define TSB_SSP2_RIS_RORRIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->RIS,0)))
+#define TSB_SSP2_RIS_RTRIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->RIS,1)))
+#define TSB_SSP2_RIS_RXRIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->RIS,2)))
+#define TSB_SSP2_RIS_TXRIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->RIS,3)))
+#define TSB_SSP2_MIS_RORMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->MIS,0)))
+#define TSB_SSP2_MIS_RTMIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->MIS,1)))
+#define TSB_SSP2_MIS_RXMIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->MIS,2)))
+#define TSB_SSP2_MIS_TXMIS                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SSP2->MIS,3)))
+#define TSB_SSP2_ICR_RORIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_SSP2->ICR,0)))
+#define TSB_SSP2_ICR_RTIC                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_SSP2->ICR,1)))
+#define TSB_SSP2_DMACR_RXDMAE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->DMACR,0)))
+#define TSB_SSP2_DMACR_TXDMAE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SSP2->DMACR,1)))
+
+
+/* UART */
+#define TSB_UART0_DR_FE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->DR,8)))
+#define TSB_UART0_DR_PE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->DR,9)))
+#define TSB_UART0_DR_BE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->DR,10)))
+#define TSB_UART0_DR_OE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->DR,11)))
+#define TSB_UART0_RSR_FE                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RSR,0)))
+#define TSB_UART0_RSR_PE                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RSR,1)))
+#define TSB_UART0_RSR_BE                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RSR,2)))
+#define TSB_UART0_RSR_OE                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RSR,3)))
+#define TSB_UART0_ECR_FE                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ECR,0)))
+#define TSB_UART0_ECR_PE                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ECR,1)))
+#define TSB_UART0_ECR_BE                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ECR,2)))
+#define TSB_UART0_ECR_OE                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ECR,3)))
+#define TSB_UART0_FR_CTS                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->FR,0)))
+#define TSB_UART0_FR_DSR                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->FR,1)))
+#define TSB_UART0_FR_DCD                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->FR,2)))
+#define TSB_UART0_FR_BUSY                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->FR,3)))
+#define TSB_UART0_FR_RXFE                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->FR,4)))
+#define TSB_UART0_FR_TXFF                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->FR,5)))
+#define TSB_UART0_FR_RXFF                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->FR,6)))
+#define TSB_UART0_FR_TXFE                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->FR,7)))
+#define TSB_UART0_FR_RI                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->FR,8)))
+#define TSB_UART0_LCR_H_BRK                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->LCR_H,0)))
+#define TSB_UART0_LCR_H_PEN                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->LCR_H,1)))
+#define TSB_UART0_LCR_H_EPS                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->LCR_H,2)))
+#define TSB_UART0_LCR_H_STP2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->LCR_H,3)))
+#define TSB_UART0_LCR_H_FEN                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->LCR_H,4)))
+#define TSB_UART0_LCR_H_SPS                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->LCR_H,7)))
+#define TSB_UART0_CR_UARTEN                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR,0)))
+#define TSB_UART0_CR_SIREN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR,1)))
+#define TSB_UART0_CR_SIRLP                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR,2)))
+#define TSB_UART0_CR_TXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR,8)))
+#define TSB_UART0_CR_RXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR,9)))
+#define TSB_UART0_CR_DTR                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR,10)))
+#define TSB_UART0_CR_RTS                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR,11)))
+#define TSB_UART0_CR_RTSEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR,14)))
+#define TSB_UART0_CR_CTSEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->CR,15)))
+#define TSB_UART0_IMSC_RIMIM                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,0)))
+#define TSB_UART0_IMSC_CTSMIM                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,1)))
+#define TSB_UART0_IMSC_DCDMIM                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,2)))
+#define TSB_UART0_IMSC_DSRMIM                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,3)))
+#define TSB_UART0_IMSC_RXIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,4)))
+#define TSB_UART0_IMSC_TXIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,5)))
+#define TSB_UART0_IMSC_RTIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,6)))
+#define TSB_UART0_IMSC_FEIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,7)))
+#define TSB_UART0_IMSC_PEIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,8)))
+#define TSB_UART0_IMSC_BEIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,9)))
+#define TSB_UART0_IMSC_OEIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->IMSC,10)))
+#define TSB_UART0_RIS_RIRMIS                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,0)))
+#define TSB_UART0_RIS_CTSRMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,1)))
+#define TSB_UART0_RIS_DCDRMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,2)))
+#define TSB_UART0_RIS_DSRRMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,3)))
+#define TSB_UART0_RIS_RXRIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,4)))
+#define TSB_UART0_RIS_TXRIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,5)))
+#define TSB_UART0_RIS_RTRIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,6)))
+#define TSB_UART0_RIS_FERIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,7)))
+#define TSB_UART0_RIS_PERIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,8)))
+#define TSB_UART0_RIS_BERIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,9)))
+#define TSB_UART0_RIS_OERIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->RIS,10)))
+#define TSB_UART0_MIS_RIMMIS                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,0)))
+#define TSB_UART0_MIS_CTSMMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,1)))
+#define TSB_UART0_MIS_DCDMMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,2)))
+#define TSB_UART0_MIS_DSRMMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,3)))
+#define TSB_UART0_MIS_RXMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,4)))
+#define TSB_UART0_MIS_TXMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,5)))
+#define TSB_UART0_MIS_RTMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,6)))
+#define TSB_UART0_MIS_FEMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,7)))
+#define TSB_UART0_MIS_PEMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,8)))
+#define TSB_UART0_MIS_BEMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,9)))
+#define TSB_UART0_MIS_OEMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART0->MIS,10)))
+#define TSB_UART0_ICR_RIMIC                       (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,0)))
+#define TSB_UART0_ICR_CTSMIC                      (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,1)))
+#define TSB_UART0_ICR_DCDMIC                      (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,2)))
+#define TSB_UART0_ICR_DSRMIC                      (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,3)))
+#define TSB_UART0_ICR_RXIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,4)))
+#define TSB_UART0_ICR_TXIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,5)))
+#define TSB_UART0_ICR_RTIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,6)))
+#define TSB_UART0_ICR_FEIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,7)))
+#define TSB_UART0_ICR_PEIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,8)))
+#define TSB_UART0_ICR_BEIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,9)))
+#define TSB_UART0_ICR_OEIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART0->ICR,10)))
+#define TSB_UART0_DMACR_RXDMAE                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->DMACR,0)))
+#define TSB_UART0_DMACR_TXDMAE                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->DMACR,1)))
+#define TSB_UART0_DMACR_DMAONERR                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART0->DMACR,2)))
+
+#define TSB_UART1_DR_FE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->DR,8)))
+#define TSB_UART1_DR_PE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->DR,9)))
+#define TSB_UART1_DR_BE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->DR,10)))
+#define TSB_UART1_DR_OE                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->DR,11)))
+#define TSB_UART1_RSR_FE                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RSR,0)))
+#define TSB_UART1_RSR_PE                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RSR,1)))
+#define TSB_UART1_RSR_BE                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RSR,2)))
+#define TSB_UART1_RSR_OE                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RSR,3)))
+#define TSB_UART1_ECR_FE                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ECR,0)))
+#define TSB_UART1_ECR_PE                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ECR,1)))
+#define TSB_UART1_ECR_BE                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ECR,2)))
+#define TSB_UART1_ECR_OE                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ECR,3)))
+#define TSB_UART1_FR_CTS                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->FR,0)))
+#define TSB_UART1_FR_DSR                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->FR,1)))
+#define TSB_UART1_FR_DCD                          (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->FR,2)))
+#define TSB_UART1_FR_BUSY                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->FR,3)))
+#define TSB_UART1_FR_RXFE                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->FR,4)))
+#define TSB_UART1_FR_TXFF                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->FR,5)))
+#define TSB_UART1_FR_RXFF                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->FR,6)))
+#define TSB_UART1_FR_TXFE                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->FR,7)))
+#define TSB_UART1_FR_RI                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->FR,8)))
+#define TSB_UART1_LCR_H_BRK                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->LCR_H,0)))
+#define TSB_UART1_LCR_H_PEN                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->LCR_H,1)))
+#define TSB_UART1_LCR_H_EPS                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->LCR_H,2)))
+#define TSB_UART1_LCR_H_STP2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->LCR_H,3)))
+#define TSB_UART1_LCR_H_FEN                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->LCR_H,4)))
+#define TSB_UART1_LCR_H_SPS                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->LCR_H,7)))
+#define TSB_UART1_CR_UARTEN                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR,0)))
+#define TSB_UART1_CR_SIREN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR,1)))
+#define TSB_UART1_CR_SIRLP                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR,2)))
+#define TSB_UART1_CR_TXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR,8)))
+#define TSB_UART1_CR_RXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR,9)))
+#define TSB_UART1_CR_DTR                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR,10)))
+#define TSB_UART1_CR_RTS                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR,11)))
+#define TSB_UART1_CR_RTSEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR,14)))
+#define TSB_UART1_CR_CTSEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->CR,15)))
+#define TSB_UART1_IMSC_RIMIM                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,0)))
+#define TSB_UART1_IMSC_CTSMIM                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,1)))
+#define TSB_UART1_IMSC_DCDMIM                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,2)))
+#define TSB_UART1_IMSC_DSRMIM                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,3)))
+#define TSB_UART1_IMSC_RXIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,4)))
+#define TSB_UART1_IMSC_TXIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,5)))
+#define TSB_UART1_IMSC_RTIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,6)))
+#define TSB_UART1_IMSC_FEIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,7)))
+#define TSB_UART1_IMSC_PEIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,8)))
+#define TSB_UART1_IMSC_BEIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,9)))
+#define TSB_UART1_IMSC_OEIM                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->IMSC,10)))
+#define TSB_UART1_RIS_RIRMIS                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,0)))
+#define TSB_UART1_RIS_CTSRMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,1)))
+#define TSB_UART1_RIS_DCDRMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,2)))
+#define TSB_UART1_RIS_DSRRMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,3)))
+#define TSB_UART1_RIS_RXRIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,4)))
+#define TSB_UART1_RIS_TXRIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,5)))
+#define TSB_UART1_RIS_RTRIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,6)))
+#define TSB_UART1_RIS_FERIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,7)))
+#define TSB_UART1_RIS_PERIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,8)))
+#define TSB_UART1_RIS_BERIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,9)))
+#define TSB_UART1_RIS_OERIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->RIS,10)))
+#define TSB_UART1_MIS_RIMMIS                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,0)))
+#define TSB_UART1_MIS_CTSMMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,1)))
+#define TSB_UART1_MIS_DCDMMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,2)))
+#define TSB_UART1_MIS_DSRMMIS                     (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,3)))
+#define TSB_UART1_MIS_RXMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,4)))
+#define TSB_UART1_MIS_TXMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,5)))
+#define TSB_UART1_MIS_RTMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,6)))
+#define TSB_UART1_MIS_FEMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,7)))
+#define TSB_UART1_MIS_PEMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,8)))
+#define TSB_UART1_MIS_BEMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,9)))
+#define TSB_UART1_MIS_OEMIS                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_UART1->MIS,10)))
+#define TSB_UART1_ICR_RIMIC                       (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,0)))
+#define TSB_UART1_ICR_CTSMIC                      (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,1)))
+#define TSB_UART1_ICR_DCDMIC                      (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,2)))
+#define TSB_UART1_ICR_DSRMIC                      (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,3)))
+#define TSB_UART1_ICR_RXIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,4)))
+#define TSB_UART1_ICR_TXIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,5)))
+#define TSB_UART1_ICR_RTIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,6)))
+#define TSB_UART1_ICR_FEIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,7)))
+#define TSB_UART1_ICR_PEIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,8)))
+#define TSB_UART1_ICR_BEIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,9)))
+#define TSB_UART1_ICR_OEIC                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_UART1->ICR,10)))
+#define TSB_UART1_DMACR_RXDMAE                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->DMACR,0)))
+#define TSB_UART1_DMACR_TXDMAE                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->DMACR,1)))
+#define TSB_UART1_DMACR_DMAONERR                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_UART1->DMACR,2)))
+
+
+/* DMA Controller */
+#define TSB_DMAA_STATUS_MASTER_ENABLE             (*((__I  uint32_t *)BITBAND_PERI(&TSB_DMAA->STATUS,0)))
+#define TSB_DMAA_CFG_MASTER_ENABLE                (*((__O  uint32_t *)BITBAND_PERI(&TSB_DMAA->CFG,0)))
+#define TSB_DMAA_ERRCLR_ERR_CLR                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAA->ERRCLR,0)))
+
+#define TSB_DMAB_STATUS_MASTER_ENABLE             (*((__I  uint32_t *)BITBAND_PERI(&TSB_DMAB->STATUS,0)))
+#define TSB_DMAB_CFG_MASTER_ENABLE                (*((__O  uint32_t *)BITBAND_PERI(&TSB_DMAB->CFG,0)))
+#define TSB_DMAB_ERRCLR_ERR_CLR                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAB->ERRCLR,0)))
+
+#define TSB_DMAC_STATUS_MASTER_ENABLE             (*((__I  uint32_t *)BITBAND_PERI(&TSB_DMAC->STATUS,0)))
+#define TSB_DMAC_CFG_MASTER_ENABLE                (*((__O  uint32_t *)BITBAND_PERI(&TSB_DMAC->CFG,0)))
+#define TSB_DMAC_ERRCLR_ERR_CLR                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_DMAC->ERRCLR,0)))
+
+
+/* 12bit A/D Converter */
+#define TSB_AD_MOD0_ADS                           (*((__O  uint32_t *)BITBAND_PERI(&TSB_AD->MOD0,0)))
+#define TSB_AD_MOD0_HPADS                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_AD->MOD0,1)))
+#define TSB_AD_MOD1_ADHWE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,0)))
+#define TSB_AD_MOD1_ADHWS                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,1)))
+#define TSB_AD_MOD1_HPADHWE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,2)))
+#define TSB_AD_MOD1_HPADHWS                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,3)))
+#define TSB_AD_MOD1_RCUT                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,5)))
+#define TSB_AD_MOD1_I2AD                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,6)))
+#define TSB_AD_MOD1_DACON                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD1,7)))
+#define TSB_AD_MOD3_SCAN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD3,0)))
+#define TSB_AD_MOD3_REPEAT                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->MOD3,1)))
+#define TSB_AD_CMPCR0_ADBIG0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->CMPCR0,4)))
+#define TSB_AD_CMPCR0_CMPCOND0                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->CMPCR0,5)))
+#define TSB_AD_CMPCR0_CMP0EN                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->CMPCR0,7)))
+#define TSB_AD_CMPCR1_ADBIG1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->CMPCR1,4)))
+#define TSB_AD_CMPCR1_CMPCOND1                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->CMPCR1,5)))
+#define TSB_AD_CMPCR1_CMP1EN                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_AD->CMPCR1,7)))
+
+
+/* External Bus Interface(EXB) */
+#define TSB_EXB_MOD_EXBSEL                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->MOD,0)))
+#define TSB_EXB_CS0_CSW0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS0,0)))
+#define TSB_EXB_CS1_CSW0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS1,0)))
+#define TSB_EXB_CS2_CSW0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS2,0)))
+#define TSB_EXB_CS3_CSW0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_EXB->CS3,0)))
+
+
+/* SNFC (SLC NAND Flash Controller)  */
+#define TSB_SNFC_ENC_EN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->ENC,0)))
+#define TSB_SNFC_ECCMOD_SELBCH                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->ECCMOD,0)))
+#define TSB_SNFC_ECCMOD_GOUTMODE                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->ECCMOD,1)))
+#define TSB_SNFC_IE_SEQEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->IE,0)))
+#define TSB_SNFC_IE_SEQFLG                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->IE,1)))
+#define TSB_SNFC_IE_SEQCLR                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->IE,2)))
+#define TSB_SNFC_IE_PRTAEFLG                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->IE,6)))
+#define TSB_SNFC_IE_PRTAECLR                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->IE,7)))
+#define TSB_SNFC_IE_PRTCEFLG                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->IE,17)))
+#define TSB_SNFC_IE_PRTCECLR                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->IE,18)))
+#define TSB_SNFC_IE_FAILEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->IE,19)))
+#define TSB_SNFC_IE_FAILFLG                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->IE,20)))
+#define TSB_SNFC_IE_FAILCLR                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->IE,21)))
+#define TSB_SNFC_CS1_PA3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS1,12)))
+#define TSB_SNFC_CS1_PA                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS1,13)))
+#define TSB_SNFC_CS1_CA                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS1,14)))
+#define TSB_SNFC_CS1_CLE1                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS1,15)))
+#define TSB_SNFC_CS1_DMYA                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS1,26)))
+#define TSB_SNFC_CS1_BSY                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS1,27)))
+#define TSB_SNFC_CS1_ALE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS1,30)))
+#define TSB_SNFC_CS1_CLE2                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS1,31)))
+#define TSB_SNFC_CS2_PA3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS2,12)))
+#define TSB_SNFC_CS2_PA                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS2,13)))
+#define TSB_SNFC_CS2_CA                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS2,14)))
+#define TSB_SNFC_CS2_CLE1                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS2,15)))
+#define TSB_SNFC_CS2_DMYA                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS2,26)))
+#define TSB_SNFC_CS2_BSY                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS2,27)))
+#define TSB_SNFC_CS2_ALE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS2,30)))
+#define TSB_SNFC_CS2_CLE2                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS2,31)))
+#define TSB_SNFC_CS3_PA3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS3,12)))
+#define TSB_SNFC_CS3_PA                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS3,13)))
+#define TSB_SNFC_CS3_CA                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS3,14)))
+#define TSB_SNFC_CS3_CLE1                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS3,15)))
+#define TSB_SNFC_CS3_DMYA                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS3,26)))
+#define TSB_SNFC_CS3_BSY                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS3,27)))
+#define TSB_SNFC_CS3_ALE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS3,30)))
+#define TSB_SNFC_CS3_CLE2                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS3,31)))
+#define TSB_SNFC_CS4_PA3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS4,12)))
+#define TSB_SNFC_CS4_PA                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS4,13)))
+#define TSB_SNFC_CS4_CA                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS4,14)))
+#define TSB_SNFC_CS4_CLE1                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS4,15)))
+#define TSB_SNFC_CS4_DMYA                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS4,26)))
+#define TSB_SNFC_CS4_BSY                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS4,27)))
+#define TSB_SNFC_CS4_ALE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS4,30)))
+#define TSB_SNFC_CS4_CLE2                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CS4,31)))
+#define TSB_SNFC_CSE_CMDSQ1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CSE,0)))
+#define TSB_SNFC_CSE_CMDSQ2                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CSE,1)))
+#define TSB_SNFC_CSE_CMDSQ3                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CSE,2)))
+#define TSB_SNFC_CSE_CMDSQ4                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CSE,3)))
+#define TSB_SNFC_CSE_RAMSEL                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CSE,6)))
+#define TSB_SNFC_CSE_DECMODE                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->CSE,7)))
+#define TSB_SNFC_EOC_GOUTEN                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SNFC->EOC,8)))
+#define TSB_SNFC_EBS_BSYST0                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EBS,0)))
+#define TSB_SNFC_EBS_BSYST1                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EBS,1)))
+#define TSB_SNFC_EBS_BSYST2                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EBS,2)))
+#define TSB_SNFC_EES_ERR1                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EES,0)))
+#define TSB_SNFC_EES_ERR2                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EES,1)))
+#define TSB_SNFC_EES_ERR3                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EES,2)))
+#define TSB_SNFC_EES_ERR4                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EES,3)))
+#define TSB_SNFC_EES_ERR5                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EES,4)))
+#define TSB_SNFC_EES_ERR6                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EES,5)))
+#define TSB_SNFC_EES_ERR7                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EES,6)))
+#define TSB_SNFC_EES_ERR8                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EES,7)))
+#define TSB_SNFC_EDS1_ERRST0                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS1,4)))
+#define TSB_SNFC_EDS1_ERRST1                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS1,5)))
+#define TSB_SNFC_EDS1_ERRST2                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS1,6)))
+#define TSB_SNFC_EDS1_ERRST3                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS1,7)))
+#define TSB_SNFC_EDS2_ERRST0                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS2,4)))
+#define TSB_SNFC_EDS2_ERRST1                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS2,5)))
+#define TSB_SNFC_EDS2_ERRST2                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS2,6)))
+#define TSB_SNFC_EDS2_ERRST3                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS2,7)))
+#define TSB_SNFC_EDS3_ERRST0                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS3,4)))
+#define TSB_SNFC_EDS3_ERRST1                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS3,5)))
+#define TSB_SNFC_EDS3_ERRST2                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS3,6)))
+#define TSB_SNFC_EDS3_ERRST3                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS3,7)))
+#define TSB_SNFC_EDS4_ERRST0                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS4,4)))
+#define TSB_SNFC_EDS4_ERRST1                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS4,5)))
+#define TSB_SNFC_EDS4_ERRST2                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS4,6)))
+#define TSB_SNFC_EDS4_ERRST3                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS4,7)))
+#define TSB_SNFC_EDS5_ERRST0                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS5,4)))
+#define TSB_SNFC_EDS5_ERRST1                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS5,5)))
+#define TSB_SNFC_EDS5_ERRST2                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS5,6)))
+#define TSB_SNFC_EDS5_ERRST3                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS5,7)))
+#define TSB_SNFC_EDS6_ERRST0                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS6,4)))
+#define TSB_SNFC_EDS6_ERRST1                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS6,5)))
+#define TSB_SNFC_EDS6_ERRST2                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS6,6)))
+#define TSB_SNFC_EDS6_ERRST3                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS6,7)))
+#define TSB_SNFC_EDS7_ERRST0                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS7,4)))
+#define TSB_SNFC_EDS7_ERRST1                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS7,5)))
+#define TSB_SNFC_EDS7_ERRST2                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS7,6)))
+#define TSB_SNFC_EDS7_ERRST3                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS7,7)))
+#define TSB_SNFC_EDS8_ERRST0                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS8,4)))
+#define TSB_SNFC_EDS8_ERRST1                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS8,5)))
+#define TSB_SNFC_EDS8_ERRST2                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS8,6)))
+#define TSB_SNFC_EDS8_ERRST3                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_SNFC->EDS8,7)))
+
+
+
+/* ADC infterface Register */
+#define TSB_ADILV_TRGSEL_TRGSELEN                 (*((__IO uint32_t *)BITBAND_PERI(&TSB_ADILV->TRGSEL,0)))
+
+
+/* I2C Bus Interface (I2C) */
+#define TSB_I2C0_CR1_NOACK                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,3)))
+#define TSB_I2C0_CR1_ACK                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->CR1,4)))
+#define TSB_I2C0_AR_ALS                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->AR,0)))
+#define TSB_I2C0_CR2_I2CM                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,3)))
+#define TSB_I2C0_CR2_PIN                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,4)))
+#define TSB_I2C0_CR2_BB                           (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,5)))
+#define TSB_I2C0_CR2_TRX                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,6)))
+#define TSB_I2C0_CR2_MST                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C0->CR2,7)))
+#define TSB_I2C0_SR_LRB                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,0)))
+#define TSB_I2C0_SR_ADO                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,1)))
+#define TSB_I2C0_SR_AAS                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,2)))
+#define TSB_I2C0_SR_AL                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,3)))
+#define TSB_I2C0_SR_PIN                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,4)))
+#define TSB_I2C0_SR_BB                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,5)))
+#define TSB_I2C0_SR_TRX                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,6)))
+#define TSB_I2C0_SR_MST                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C0->SR,7)))
+#define TSB_I2C0_IE_IE                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IE,0)))
+#define TSB_I2C0_IR_ISIC                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C0->IR,0)))
+
+#define TSB_I2C1_CR1_NOACK                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,3)))
+#define TSB_I2C1_CR1_ACK                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->CR1,4)))
+#define TSB_I2C1_AR_ALS                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->AR,0)))
+#define TSB_I2C1_CR2_I2CM                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,3)))
+#define TSB_I2C1_CR2_PIN                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,4)))
+#define TSB_I2C1_CR2_BB                           (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,5)))
+#define TSB_I2C1_CR2_TRX                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,6)))
+#define TSB_I2C1_CR2_MST                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C1->CR2,7)))
+#define TSB_I2C1_SR_LRB                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,0)))
+#define TSB_I2C1_SR_ADO                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,1)))
+#define TSB_I2C1_SR_AAS                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,2)))
+#define TSB_I2C1_SR_AL                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,3)))
+#define TSB_I2C1_SR_PIN                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,4)))
+#define TSB_I2C1_SR_BB                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,5)))
+#define TSB_I2C1_SR_TRX                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,6)))
+#define TSB_I2C1_SR_MST                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C1->SR,7)))
+#define TSB_I2C1_IE_IE                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IE,0)))
+#define TSB_I2C1_IR_ISIC                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C1->IR,0)))
+
+#define TSB_I2C2_CR1_NOACK                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,3)))
+#define TSB_I2C2_CR1_ACK                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->CR1,4)))
+#define TSB_I2C2_AR_ALS                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->AR,0)))
+#define TSB_I2C2_CR2_I2CM                         (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,3)))
+#define TSB_I2C2_CR2_PIN                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,4)))
+#define TSB_I2C2_CR2_BB                           (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,5)))
+#define TSB_I2C2_CR2_TRX                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,6)))
+#define TSB_I2C2_CR2_MST                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_I2C2->CR2,7)))
+#define TSB_I2C2_SR_LRB                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,0)))
+#define TSB_I2C2_SR_ADO                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,1)))
+#define TSB_I2C2_SR_AAS                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,2)))
+#define TSB_I2C2_SR_AL                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,3)))
+#define TSB_I2C2_SR_PIN                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,4)))
+#define TSB_I2C2_SR_BB                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,5)))
+#define TSB_I2C2_SR_TRX                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,6)))
+#define TSB_I2C2_SR_MST                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_I2C2->SR,7)))
+#define TSB_I2C2_IE_IE                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IE,0)))
+#define TSB_I2C2_IR_ISIC                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_I2C2->IR,0)))
+
+
+/* Advanced Encryption Standard (AES) */
+#define TSB_AES_CLR_FIFOCLR                       (*((__O  uint32_t *)BITBAND_PERI(&TSB_AES->CLR,0)))
+#define TSB_AES_MOD_OP                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_AES->MOD,0)))
+#define TSB_AES_MOD_DMAEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_AES->MOD,1)))
+#define TSB_AES_STATUS_BUSY                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_AES->STATUS,0)))
+#define TSB_AES_STATUS_WFIFOST                    (*((__I  uint32_t *)BITBAND_PERI(&TSB_AES->STATUS,1)))
+#define TSB_AES_STATUS_RFIFOST                    (*((__I  uint32_t *)BITBAND_PERI(&TSB_AES->STATUS,2)))
+
+
+/* Secure Hash Algorithm Processor (SHA) */
+#define TSB_SHA_START_START                       (*((__O  uint32_t *)BITBAND_PERI(&TSB_SHA->START,0)))
+#define TSB_SHA_CR_INTEN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SHA->CR,3)))
+#define TSB_SHA_DMAEN_DMAEN                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SHA->DMAEN,0)))
+#define TSB_SHA_STATUS_BUSY                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_SHA->STATUS,0)))
+
+
+/* Entropy Seed Generator (ESG) */
+#define TSB_ESG_CR_START                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_ESG->CR,0)))
+#define TSB_ESG_ST_BUSY                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_ESG->ST,0)))
+#define TSB_ESG_INT_INT                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_ESG->INT,0)))
+
+
+/* Soft Reset */
+#define TSB_SRST_IPRST_IPRST0                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SRST->IPRST,0)))
+#define TSB_SRST_IPRST_IPRST1                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SRST->IPRST,1)))
+#define TSB_SRST_IPRST_IPRST2                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SRST->IPRST,2)))
+#define TSB_SRST_IPRST_IPRST3                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SRST->IPRST,3)))
+#define TSB_SRST_IPRST_IPRST4                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_SRST->IPRST,4)))
+
+
+/* Multiple Length Arithmetic Coprocessor (MLA) */
+#define TSB_MLA_ST_CABO                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_MLA->ST,0)))
+#define TSB_MLA_ST_BUSY                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_MLA->ST,1)))
+
+
+/* Port A */
+#define TSB_PA_DATA_PA0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,0)))
+#define TSB_PA_DATA_PA1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,1)))
+#define TSB_PA_DATA_PA2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,2)))
+#define TSB_PA_DATA_PA3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,3)))
+#define TSB_PA_DATA_PA4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,4)))
+#define TSB_PA_DATA_PA5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,5)))
+#define TSB_PA_DATA_PA6                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,6)))
+#define TSB_PA_DATA_PA7                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->DATA,7)))
+#define TSB_PA_CR_PA0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,0)))
+#define TSB_PA_CR_PA1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,1)))
+#define TSB_PA_CR_PA2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,2)))
+#define TSB_PA_CR_PA3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,3)))
+#define TSB_PA_CR_PA4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,4)))
+#define TSB_PA_CR_PA5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,5)))
+#define TSB_PA_CR_PA6C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,6)))
+#define TSB_PA_CR_PA7C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->CR,7)))
+#define TSB_PA_FR1_PA0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,0)))
+#define TSB_PA_FR1_PA1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,1)))
+#define TSB_PA_FR1_PA2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,2)))
+#define TSB_PA_FR1_PA3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,3)))
+#define TSB_PA_FR1_PA4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,4)))
+#define TSB_PA_FR1_PA5F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,5)))
+#define TSB_PA_FR1_PA6F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,6)))
+#define TSB_PA_FR1_PA7F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR1,7)))
+#define TSB_PA_FR2_PA0F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,0)))
+#define TSB_PA_FR2_PA1F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,1)))
+#define TSB_PA_FR2_PA2F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,2)))
+#define TSB_PA_FR2_PA3F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,3)))
+#define TSB_PA_FR2_PA4F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,4)))
+#define TSB_PA_FR2_PA5F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,5)))
+#define TSB_PA_FR2_PA6F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,6)))
+#define TSB_PA_FR2_PA7F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR2,7)))
+#define TSB_PA_FR3_PA5F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,5)))
+#define TSB_PA_FR3_PA6F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,6)))
+#define TSB_PA_FR3_PA7F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR3,7)))
+#define TSB_PA_FR4_PA7F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR4,7)))
+#define TSB_PA_FR5_PA7F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->FR5,7)))
+#define TSB_PA_OD_PA0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,0)))
+#define TSB_PA_OD_PA1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,1)))
+#define TSB_PA_OD_PA2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,2)))
+#define TSB_PA_OD_PA3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,3)))
+#define TSB_PA_OD_PA4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,4)))
+#define TSB_PA_OD_PA5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,5)))
+#define TSB_PA_OD_PA6OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,6)))
+#define TSB_PA_OD_PA7OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->OD,7)))
+#define TSB_PA_PUP_PA0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,0)))
+#define TSB_PA_PUP_PA1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,1)))
+#define TSB_PA_PUP_PA3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,3)))
+#define TSB_PA_PUP_PA4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,4)))
+#define TSB_PA_PUP_PA5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,5)))
+#define TSB_PA_PUP_PA6UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,6)))
+#define TSB_PA_PUP_PA7UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PUP,7)))
+#define TSB_PA_PDN_PA2DN                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->PDN,2)))
+#define TSB_PA_IE_PA0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,0)))
+#define TSB_PA_IE_PA1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,1)))
+#define TSB_PA_IE_PA2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,2)))
+#define TSB_PA_IE_PA3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,3)))
+#define TSB_PA_IE_PA4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,4)))
+#define TSB_PA_IE_PA5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,5)))
+#define TSB_PA_IE_PA6IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,6)))
+#define TSB_PA_IE_PA7IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PA->IE,7)))
+
+
+/* Port B */
+#define TSB_PB_DATA_PB0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,0)))
+#define TSB_PB_DATA_PB1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,1)))
+#define TSB_PB_DATA_PB2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,2)))
+#define TSB_PB_DATA_PB3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,3)))
+#define TSB_PB_DATA_PB4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,4)))
+#define TSB_PB_DATA_PB5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,5)))
+#define TSB_PB_DATA_PB6                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,6)))
+#define TSB_PB_DATA_PB7                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->DATA,7)))
+#define TSB_PB_CR_PB0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,0)))
+#define TSB_PB_CR_PB1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,1)))
+#define TSB_PB_CR_PB2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,2)))
+#define TSB_PB_CR_PB3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,3)))
+#define TSB_PB_CR_PB4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,4)))
+#define TSB_PB_CR_PB5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,5)))
+#define TSB_PB_CR_PB6C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,6)))
+#define TSB_PB_CR_PB7C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->CR,7)))
+#define TSB_PB_FR1_PB0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,0)))
+#define TSB_PB_FR1_PB1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,1)))
+#define TSB_PB_FR1_PB2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,2)))
+#define TSB_PB_FR1_PB3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,3)))
+#define TSB_PB_FR1_PB4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,4)))
+#define TSB_PB_FR1_PB5F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,5)))
+#define TSB_PB_FR1_PB6F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR1,6)))
+#define TSB_PB_FR2_PB6F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR2,6)))
+#define TSB_PB_FR3_PB0F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,0)))
+#define TSB_PB_FR3_PB1F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,1)))
+#define TSB_PB_FR3_PB2F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,2)))
+#define TSB_PB_FR3_PB3F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,3)))
+#define TSB_PB_FR3_PB4F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,4)))
+#define TSB_PB_FR3_PB5F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR3,5)))
+#define TSB_PB_FR4_PB2F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,2)))
+#define TSB_PB_FR4_PB3F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,3)))
+#define TSB_PB_FR4_PB6F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR4,6)))
+#define TSB_PB_FR5_PB2F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,2)))
+#define TSB_PB_FR5_PB3F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,3)))
+#define TSB_PB_FR5_PB4F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,4)))
+#define TSB_PB_FR5_PB5F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,5)))
+#define TSB_PB_FR5_PB6F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,6)))
+#define TSB_PB_FR5_PB7F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->FR5,7)))
+#define TSB_PB_OD_PB0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,0)))
+#define TSB_PB_OD_PB1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,1)))
+#define TSB_PB_OD_PB2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,2)))
+#define TSB_PB_OD_PB3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,3)))
+#define TSB_PB_OD_PB4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,4)))
+#define TSB_PB_OD_PB5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,5)))
+#define TSB_PB_OD_PB6OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,6)))
+#define TSB_PB_OD_PB7OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->OD,7)))
+#define TSB_PB_PUP_PB0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,0)))
+#define TSB_PB_PUP_PB1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,1)))
+#define TSB_PB_PUP_PB2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,2)))
+#define TSB_PB_PUP_PB3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,3)))
+#define TSB_PB_PUP_PB4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,4)))
+#define TSB_PB_PUP_PB5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,5)))
+#define TSB_PB_PUP_PB6UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,6)))
+#define TSB_PB_PUP_PB7UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->PUP,7)))
+#define TSB_PB_IE_PB0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,0)))
+#define TSB_PB_IE_PB1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,1)))
+#define TSB_PB_IE_PB2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,2)))
+#define TSB_PB_IE_PB3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,3)))
+#define TSB_PB_IE_PB4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,4)))
+#define TSB_PB_IE_PB5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,5)))
+#define TSB_PB_IE_PB7IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PB->IE,7)))
+
+
+/* Port C */
+#define TSB_PC_DATA_PC0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,0)))
+#define TSB_PC_DATA_PC1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,1)))
+#define TSB_PC_DATA_PC2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,2)))
+#define TSB_PC_DATA_PC3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,3)))
+#define TSB_PC_DATA_PC4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,4)))
+#define TSB_PC_DATA_PC5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->DATA,5)))
+#define TSB_PC_CR_PC0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,0)))
+#define TSB_PC_CR_PC1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,1)))
+#define TSB_PC_CR_PC2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,2)))
+#define TSB_PC_CR_PC3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,3)))
+#define TSB_PC_CR_PC4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,4)))
+#define TSB_PC_CR_PC5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->CR,5)))
+#define TSB_PC_FR1_PC2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,2)))
+#define TSB_PC_FR1_PC3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,3)))
+#define TSB_PC_FR1_PC4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,4)))
+#define TSB_PC_FR1_PC5F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR1,5)))
+#define TSB_PC_FR2_PC5F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->FR2,5)))
+#define TSB_PC_OD_PC0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,0)))
+#define TSB_PC_OD_PC1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,1)))
+#define TSB_PC_OD_PC2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,2)))
+#define TSB_PC_OD_PC3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,3)))
+#define TSB_PC_OD_PC4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,4)))
+#define TSB_PC_OD_PC5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->OD,5)))
+#define TSB_PC_PUP_PC0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,0)))
+#define TSB_PC_PUP_PC1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,1)))
+#define TSB_PC_PUP_PC2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,2)))
+#define TSB_PC_PUP_PC3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,3)))
+#define TSB_PC_PUP_PC4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,4)))
+#define TSB_PC_PUP_PC5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->PUP,5)))
+#define TSB_PC_IE_PC0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,0)))
+#define TSB_PC_IE_PC1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,1)))
+#define TSB_PC_IE_PC2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,2)))
+#define TSB_PC_IE_PC3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,3)))
+#define TSB_PC_IE_PC4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,4)))
+#define TSB_PC_IE_PC5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PC->IE,5)))
+
+
+/* Port D */
+#define TSB_PD_DATA_PD0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,0)))
+#define TSB_PD_DATA_PD1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,1)))
+#define TSB_PD_DATA_PD2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,2)))
+#define TSB_PD_DATA_PD3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,3)))
+#define TSB_PD_DATA_PD4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->DATA,4)))
+#define TSB_PD_CR_PD0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,0)))
+#define TSB_PD_CR_PD1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,1)))
+#define TSB_PD_CR_PD2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,2)))
+#define TSB_PD_CR_PD3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,3)))
+#define TSB_PD_CR_PD4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->CR,4)))
+#define TSB_PD_FR1_PD0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,0)))
+#define TSB_PD_FR1_PD1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,1)))
+#define TSB_PD_FR1_PD2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,2)))
+#define TSB_PD_FR1_PD3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,3)))
+#define TSB_PD_FR1_PD4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->FR1,4)))
+#define TSB_PD_OD_PD0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,0)))
+#define TSB_PD_OD_PD1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,1)))
+#define TSB_PD_OD_PD2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,2)))
+#define TSB_PD_OD_PD3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,3)))
+#define TSB_PD_OD_PD4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->OD,4)))
+#define TSB_PD_PUP_PD0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,0)))
+#define TSB_PD_PUP_PD1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,1)))
+#define TSB_PD_PUP_PD2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,2)))
+#define TSB_PD_PUP_PD3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,3)))
+#define TSB_PD_PUP_PD4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->PUP,4)))
+#define TSB_PD_IE_PD0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,0)))
+#define TSB_PD_IE_PD1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,1)))
+#define TSB_PD_IE_PD2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,2)))
+#define TSB_PD_IE_PD3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,3)))
+#define TSB_PD_IE_PD4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PD->IE,4)))
+
+
+/* Port E */
+#define TSB_PE_DATA_PE0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,0)))
+#define TSB_PE_DATA_PE1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,1)))
+#define TSB_PE_DATA_PE2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,2)))
+#define TSB_PE_DATA_PE3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,3)))
+#define TSB_PE_DATA_PE4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,4)))
+#define TSB_PE_DATA_PE5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,5)))
+#define TSB_PE_DATA_PE6                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,6)))
+#define TSB_PE_DATA_PE7                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->DATA,7)))
+#define TSB_PE_CR_PE0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,0)))
+#define TSB_PE_CR_PE1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,1)))
+#define TSB_PE_CR_PE2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,2)))
+#define TSB_PE_CR_PE3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,3)))
+#define TSB_PE_CR_PE4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,4)))
+#define TSB_PE_CR_PE5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,5)))
+#define TSB_PE_CR_PE6C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,6)))
+#define TSB_PE_CR_PE7C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->CR,7)))
+#define TSB_PE_FR1_PE1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,1)))
+#define TSB_PE_FR1_PE2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,2)))
+#define TSB_PE_FR1_PE3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,3)))
+#define TSB_PE_FR1_PE4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,4)))
+#define TSB_PE_FR1_PE5F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,5)))
+#define TSB_PE_FR1_PE6F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR1,6)))
+#define TSB_PE_FR3_PE0F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,0)))
+#define TSB_PE_FR3_PE1F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,1)))
+#define TSB_PE_FR3_PE2F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,2)))
+#define TSB_PE_FR3_PE3F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,3)))
+#define TSB_PE_FR3_PE4F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,4)))
+#define TSB_PE_FR3_PE5F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,5)))
+#define TSB_PE_FR3_PE6F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,6)))
+#define TSB_PE_FR3_PE7F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR3,7)))
+#define TSB_PE_FR4_PE3F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,3)))
+#define TSB_PE_FR4_PE4F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR4,4)))
+#define TSB_PE_FR5_PE0F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,0)))
+#define TSB_PE_FR5_PE1F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,1)))
+#define TSB_PE_FR5_PE2F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,2)))
+#define TSB_PE_FR5_PE3F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,3)))
+#define TSB_PE_FR5_PE4F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,4)))
+#define TSB_PE_FR5_PE7F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->FR5,7)))
+#define TSB_PE_OD_PE0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,0)))
+#define TSB_PE_OD_PE1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,1)))
+#define TSB_PE_OD_PE2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,2)))
+#define TSB_PE_OD_PE3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,3)))
+#define TSB_PE_OD_PE4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,4)))
+#define TSB_PE_OD_PE5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,5)))
+#define TSB_PE_OD_PE6OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,6)))
+#define TSB_PE_OD_PE7OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->OD,7)))
+#define TSB_PE_PUP_PE0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,0)))
+#define TSB_PE_PUP_PE1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,1)))
+#define TSB_PE_PUP_PE2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,2)))
+#define TSB_PE_PUP_PE3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,3)))
+#define TSB_PE_PUP_PE4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,4)))
+#define TSB_PE_PUP_PE5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,5)))
+#define TSB_PE_PUP_PE6UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,6)))
+#define TSB_PE_PUP_PE7UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->PUP,7)))
+#define TSB_PE_IE_PE0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,0)))
+#define TSB_PE_IE_PE1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,1)))
+#define TSB_PE_IE_PE2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,2)))
+#define TSB_PE_IE_PE3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,3)))
+#define TSB_PE_IE_PE4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,4)))
+#define TSB_PE_IE_PE5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,5)))
+#define TSB_PE_IE_PE6IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,6)))
+#define TSB_PE_IE_PE7IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PE->IE,7)))
+
+
+/* Port F */
+#define TSB_PF_DATA_PF0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,0)))
+#define TSB_PF_DATA_PF1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,1)))
+#define TSB_PF_DATA_PF2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,2)))
+#define TSB_PF_DATA_PF3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,3)))
+#define TSB_PF_DATA_PF4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,4)))
+#define TSB_PF_DATA_PF5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,5)))
+#define TSB_PF_DATA_PF6                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,6)))
+#define TSB_PF_DATA_PF7                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->DATA,7)))
+#define TSB_PF_CR_PF0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,0)))
+#define TSB_PF_CR_PF1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,1)))
+#define TSB_PF_CR_PF2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,2)))
+#define TSB_PF_CR_PF3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,3)))
+#define TSB_PF_CR_PF4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,4)))
+#define TSB_PF_CR_PF5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,5)))
+#define TSB_PF_CR_PF6C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,6)))
+#define TSB_PF_CR_PF7C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->CR,7)))
+#define TSB_PF_FR1_PF0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,0)))
+#define TSB_PF_FR1_PF1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,1)))
+#define TSB_PF_FR1_PF2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,2)))
+#define TSB_PF_FR1_PF3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,3)))
+#define TSB_PF_FR1_PF4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,4)))
+#define TSB_PF_FR1_PF5F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,5)))
+#define TSB_PF_FR1_PF6F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,6)))
+#define TSB_PF_FR1_PF7F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR1,7)))
+#define TSB_PF_FR3_PF0F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,0)))
+#define TSB_PF_FR3_PF1F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,1)))
+#define TSB_PF_FR3_PF2F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,2)))
+#define TSB_PF_FR3_PF3F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,3)))
+#define TSB_PF_FR3_PF4F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,4)))
+#define TSB_PF_FR3_PF5F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,5)))
+#define TSB_PF_FR3_PF6F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,6)))
+#define TSB_PF_FR3_PF7F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR3,7)))
+#define TSB_PF_FR4_PF1F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,1)))
+#define TSB_PF_FR4_PF2F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,2)))
+#define TSB_PF_FR4_PF6F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,6)))
+#define TSB_PF_FR4_PF7F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR4,7)))
+#define TSB_PF_FR5_PF3F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,3)))
+#define TSB_PF_FR5_PF4F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,4)))
+#define TSB_PF_FR5_PF5F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,5)))
+#define TSB_PF_FR5_PF6F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->FR5,6)))
+#define TSB_PF_OD_PF0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,0)))
+#define TSB_PF_OD_PF1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,1)))
+#define TSB_PF_OD_PF2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,2)))
+#define TSB_PF_OD_PF3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,3)))
+#define TSB_PF_OD_PF4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,4)))
+#define TSB_PF_OD_PF5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,5)))
+#define TSB_PF_OD_PF6OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,6)))
+#define TSB_PF_OD_PF7OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->OD,7)))
+#define TSB_PF_PUP_PF0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,0)))
+#define TSB_PF_PUP_PF1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,1)))
+#define TSB_PF_PUP_PF2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,2)))
+#define TSB_PF_PUP_PF3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,3)))
+#define TSB_PF_PUP_PF4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,4)))
+#define TSB_PF_PUP_PF5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,5)))
+#define TSB_PF_PUP_PF6UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,6)))
+#define TSB_PF_PUP_PF7UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->PUP,7)))
+#define TSB_PF_IE_PF0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,0)))
+#define TSB_PF_IE_PF1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,1)))
+#define TSB_PF_IE_PF2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,2)))
+#define TSB_PF_IE_PF3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,3)))
+#define TSB_PF_IE_PF4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,4)))
+#define TSB_PF_IE_PF5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,5)))
+#define TSB_PF_IE_PF6IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,6)))
+#define TSB_PF_IE_PF7IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PF->IE,7)))
+
+
+/* Port G */
+#define TSB_PG_DATA_PG0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,0)))
+#define TSB_PG_DATA_PG1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,1)))
+#define TSB_PG_DATA_PG2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,2)))
+#define TSB_PG_DATA_PG3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,3)))
+#define TSB_PG_DATA_PG4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,4)))
+#define TSB_PG_DATA_PG5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,5)))
+#define TSB_PG_DATA_PG6                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,6)))
+#define TSB_PG_DATA_PG7                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->DATA,7)))
+#define TSB_PG_CR_PG0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,0)))
+#define TSB_PG_CR_PG1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,1)))
+#define TSB_PG_CR_PG2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,2)))
+#define TSB_PG_CR_PG3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,3)))
+#define TSB_PG_CR_PG4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,4)))
+#define TSB_PG_CR_PG5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,5)))
+#define TSB_PG_CR_PG6C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,6)))
+#define TSB_PG_CR_PG7C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->CR,7)))
+#define TSB_PG_FR1_PG0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,0)))
+#define TSB_PG_FR1_PG1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,1)))
+#define TSB_PG_FR1_PG2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,2)))
+#define TSB_PG_FR1_PG3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,3)))
+#define TSB_PG_FR1_PG4F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,4)))
+#define TSB_PG_FR1_PG5F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,5)))
+#define TSB_PG_FR1_PG6F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,6)))
+#define TSB_PG_FR1_PG7F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR1,7)))
+#define TSB_PG_FR3_PG0F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,0)))
+#define TSB_PG_FR3_PG1F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,1)))
+#define TSB_PG_FR3_PG2F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,2)))
+#define TSB_PG_FR3_PG3F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR3,3)))
+#define TSB_PG_FR4_PG2F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,2)))
+#define TSB_PG_FR4_PG3F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR4,3)))
+#define TSB_PG_FR5_PG0F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,0)))
+#define TSB_PG_FR5_PG1F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,1)))
+#define TSB_PG_FR5_PG2F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,2)))
+#define TSB_PG_FR5_PG3F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,3)))
+#define TSB_PG_FR5_PG4F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,4)))
+#define TSB_PG_FR5_PG5F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,5)))
+#define TSB_PG_FR5_PG6F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,6)))
+#define TSB_PG_FR5_PG7F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->FR5,7)))
+#define TSB_PG_OD_PG0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,0)))
+#define TSB_PG_OD_PG1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,1)))
+#define TSB_PG_OD_PG2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,2)))
+#define TSB_PG_OD_PG3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,3)))
+#define TSB_PG_OD_PG4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,4)))
+#define TSB_PG_OD_PG5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,5)))
+#define TSB_PG_OD_PG6OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,6)))
+#define TSB_PG_OD_PG7OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->OD,7)))
+#define TSB_PG_PUP_PG0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,0)))
+#define TSB_PG_PUP_PG1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,1)))
+#define TSB_PG_PUP_PG2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,2)))
+#define TSB_PG_PUP_PG3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,3)))
+#define TSB_PG_PUP_PG4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,4)))
+#define TSB_PG_PUP_PG5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,5)))
+#define TSB_PG_PUP_PG6UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,6)))
+#define TSB_PG_PUP_PG7UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->PUP,7)))
+#define TSB_PG_IE_PG0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,0)))
+#define TSB_PG_IE_PG1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,1)))
+#define TSB_PG_IE_PG2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,2)))
+#define TSB_PG_IE_PG3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,3)))
+#define TSB_PG_IE_PG4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,4)))
+#define TSB_PG_IE_PG5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,5)))
+#define TSB_PG_IE_PG6IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,6)))
+#define TSB_PG_IE_PG7IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PG->IE,7)))
+
+
+/* Port H */
+#define TSB_PH_DATA_PH0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,0)))
+#define TSB_PH_DATA_PH1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,1)))
+#define TSB_PH_DATA_PH2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,2)))
+#define TSB_PH_DATA_PH3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->DATA,3)))
+#define TSB_PH_CR_PH0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,0)))
+#define TSB_PH_CR_PH1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,1)))
+#define TSB_PH_CR_PH2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,2)))
+#define TSB_PH_CR_PH3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->CR,3)))
+#define TSB_PH_FR1_PH0F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,0)))
+#define TSB_PH_FR1_PH1F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,1)))
+#define TSB_PH_FR1_PH2F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,2)))
+#define TSB_PH_FR1_PH3F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR1,3)))
+#define TSB_PH_FR2_PH0F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR2,0)))
+#define TSB_PH_FR2_PH1F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR2,1)))
+#define TSB_PH_FR3_PH0F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,0)))
+#define TSB_PH_FR3_PH1F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,1)))
+#define TSB_PH_FR3_PH2F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,2)))
+#define TSB_PH_FR3_PH3F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR3,3)))
+#define TSB_PH_FR4_PH0F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,0)))
+#define TSB_PH_FR4_PH1F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,1)))
+#define TSB_PH_FR4_PH2F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,2)))
+#define TSB_PH_FR4_PH3F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->FR4,3)))
+#define TSB_PH_OD_PH0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,0)))
+#define TSB_PH_OD_PH1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,1)))
+#define TSB_PH_OD_PH2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,2)))
+#define TSB_PH_OD_PH3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->OD,3)))
+#define TSB_PH_PUP_PH0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,0)))
+#define TSB_PH_PUP_PH1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,1)))
+#define TSB_PH_PUP_PH2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,2)))
+#define TSB_PH_PUP_PH3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->PUP,3)))
+#define TSB_PH_IE_PH0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,0)))
+#define TSB_PH_IE_PH1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,1)))
+#define TSB_PH_IE_PH2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,2)))
+#define TSB_PH_IE_PH3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PH->IE,3)))
+
+
+/* Port J */
+#define TSB_PJ_DATA_PJ0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,0)))
+#define TSB_PJ_DATA_PJ1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,1)))
+#define TSB_PJ_DATA_PJ2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,2)))
+#define TSB_PJ_DATA_PJ3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,3)))
+#define TSB_PJ_DATA_PJ4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,4)))
+#define TSB_PJ_DATA_PJ5                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,5)))
+#define TSB_PJ_DATA_PJ6                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,6)))
+#define TSB_PJ_DATA_PJ7                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->DATA,7)))
+#define TSB_PJ_CR_PJ0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,0)))
+#define TSB_PJ_CR_PJ1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,1)))
+#define TSB_PJ_CR_PJ2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,2)))
+#define TSB_PJ_CR_PJ3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,3)))
+#define TSB_PJ_CR_PJ4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,4)))
+#define TSB_PJ_CR_PJ5C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,5)))
+#define TSB_PJ_CR_PJ6C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,6)))
+#define TSB_PJ_CR_PJ7C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->CR,7)))
+#define TSB_PJ_FR1_PJ7F1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR1,7)))
+#define TSB_PJ_FR2_PJ7F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR2,7)))
+#define TSB_PJ_FR3_PJ7F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->FR3,7)))
+#define TSB_PJ_OD_PJ0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,0)))
+#define TSB_PJ_OD_PJ1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,1)))
+#define TSB_PJ_OD_PJ2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,2)))
+#define TSB_PJ_OD_PJ3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,3)))
+#define TSB_PJ_OD_PJ4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,4)))
+#define TSB_PJ_OD_PJ5OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,5)))
+#define TSB_PJ_OD_PJ6OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,6)))
+#define TSB_PJ_OD_PJ7OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->OD,7)))
+#define TSB_PJ_PUP_PJ0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,0)))
+#define TSB_PJ_PUP_PJ1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,1)))
+#define TSB_PJ_PUP_PJ2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,2)))
+#define TSB_PJ_PUP_PJ3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,3)))
+#define TSB_PJ_PUP_PJ4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,4)))
+#define TSB_PJ_PUP_PJ5UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,5)))
+#define TSB_PJ_PUP_PJ6UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,6)))
+#define TSB_PJ_PUP_PJ7UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->PUP,7)))
+#define TSB_PJ_IE_PJ0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,0)))
+#define TSB_PJ_IE_PJ1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,1)))
+#define TSB_PJ_IE_PJ2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,2)))
+#define TSB_PJ_IE_PJ3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,3)))
+#define TSB_PJ_IE_PJ4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,4)))
+#define TSB_PJ_IE_PJ5IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,5)))
+#define TSB_PJ_IE_PJ6IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,6)))
+#define TSB_PJ_IE_PJ7IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PJ->IE,7)))
+
+
+/* Port K */
+#define TSB_PK_DATA_PK0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,0)))
+#define TSB_PK_DATA_PK1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,1)))
+#define TSB_PK_DATA_PK2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,2)))
+#define TSB_PK_DATA_PK3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,3)))
+#define TSB_PK_DATA_PK4                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->DATA,4)))
+#define TSB_PK_CR_PK0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,0)))
+#define TSB_PK_CR_PK1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,1)))
+#define TSB_PK_CR_PK2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,2)))
+#define TSB_PK_CR_PK3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,3)))
+#define TSB_PK_CR_PK4C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->CR,4)))
+#define TSB_PK_FR2_PK1F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,1)))
+#define TSB_PK_FR2_PK2F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,2)))
+#define TSB_PK_FR2_PK3F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,3)))
+#define TSB_PK_FR2_PK4F2                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR2,4)))
+#define TSB_PK_FR3_PK2F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,2)))
+#define TSB_PK_FR3_PK3F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR3,3)))
+#define TSB_PK_FR4_PK1F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->FR4,1)))
+#define TSB_PK_OD_PK0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,0)))
+#define TSB_PK_OD_PK1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,1)))
+#define TSB_PK_OD_PK2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,2)))
+#define TSB_PK_OD_PK3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,3)))
+#define TSB_PK_OD_PK4OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->OD,4)))
+#define TSB_PK_PUP_PK0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,0)))
+#define TSB_PK_PUP_PK1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,1)))
+#define TSB_PK_PUP_PK2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,2)))
+#define TSB_PK_PUP_PK3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,3)))
+#define TSB_PK_PUP_PK4UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->PUP,4)))
+#define TSB_PK_IE_PK0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,0)))
+#define TSB_PK_IE_PK1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,1)))
+#define TSB_PK_IE_PK2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,2)))
+#define TSB_PK_IE_PK3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,3)))
+#define TSB_PK_IE_PK4IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PK->IE,4)))
+
+
+/* Port L */
+#define TSB_PL_DATA_PL0                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,0)))
+#define TSB_PL_DATA_PL1                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,1)))
+#define TSB_PL_DATA_PL2                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,2)))
+#define TSB_PL_DATA_PL3                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->DATA,3)))
+#define TSB_PL_CR_PL0C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,0)))
+#define TSB_PL_CR_PL1C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,1)))
+#define TSB_PL_CR_PL2C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,2)))
+#define TSB_PL_CR_PL3C                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->CR,3)))
+#define TSB_PL_FR3_PL0F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,0)))
+#define TSB_PL_FR3_PL1F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,1)))
+#define TSB_PL_FR3_PL2F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,2)))
+#define TSB_PL_FR3_PL3F3                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR3,3)))
+#define TSB_PL_FR4_PL0F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,0)))
+#define TSB_PL_FR4_PL2F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,2)))
+#define TSB_PL_FR4_PL3F4                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR4,3)))
+#define TSB_PL_FR5_PL1F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,1)))
+#define TSB_PL_FR5_PL2F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,2)))
+#define TSB_PL_FR5_PL3F5                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR5,3)))
+#define TSB_PL_FR6_PL3F6                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->FR6,3)))
+#define TSB_PL_OD_PL0OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,0)))
+#define TSB_PL_OD_PL1OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,1)))
+#define TSB_PL_OD_PL2OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,2)))
+#define TSB_PL_OD_PL3OD                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->OD,3)))
+#define TSB_PL_PUP_PL0UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,0)))
+#define TSB_PL_PUP_PL1UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,1)))
+#define TSB_PL_PUP_PL2UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,2)))
+#define TSB_PL_PUP_PL3UP                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->PUP,3)))
+#define TSB_PL_IE_PL0IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,0)))
+#define TSB_PL_IE_PL1IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,1)))
+#define TSB_PL_IE_PL2IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,2)))
+#define TSB_PL_IE_PL3IE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_PL->IE,3)))
+
+
+/* 16-bit Timer/Event Counter (TB) */
+#define TSB_TB0_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->EN,6)))
+#define TSB_TB0_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->EN,7)))
+#define TSB_TB0_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->RUN,0)))
+#define TSB_TB0_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->RUN,2)))
+#define TSB_TB0_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,0)))
+#define TSB_TB0_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,1)))
+#define TSB_TB0_CR_I2TB                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,3)))
+#define TSB_TB0_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,5)))
+#define TSB_TB0_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->CR,7)))
+#define TSB_TB0_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->MOD,3)))
+#define TSB_TB0_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB0->MOD,6)))
+#define TSB_TB0_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,2)))
+#define TSB_TB0_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,3)))
+#define TSB_TB0_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,4)))
+#define TSB_TB0_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->FFCR,5)))
+#define TSB_TB0_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,0)))
+#define TSB_TB0_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,1)))
+#define TSB_TB0_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB0->IM,2)))
+
+#define TSB_TB1_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->EN,6)))
+#define TSB_TB1_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->EN,7)))
+#define TSB_TB1_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->RUN,0)))
+#define TSB_TB1_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->RUN,2)))
+#define TSB_TB1_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,0)))
+#define TSB_TB1_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,1)))
+#define TSB_TB1_CR_I2TB                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,3)))
+#define TSB_TB1_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,5)))
+#define TSB_TB1_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->CR,7)))
+#define TSB_TB1_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->MOD,3)))
+#define TSB_TB1_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB1->MOD,6)))
+#define TSB_TB1_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,2)))
+#define TSB_TB1_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,3)))
+#define TSB_TB1_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,4)))
+#define TSB_TB1_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->FFCR,5)))
+#define TSB_TB1_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,0)))
+#define TSB_TB1_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,1)))
+#define TSB_TB1_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB1->IM,2)))
+
+#define TSB_TB2_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->EN,6)))
+#define TSB_TB2_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->EN,7)))
+#define TSB_TB2_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->RUN,0)))
+#define TSB_TB2_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->RUN,2)))
+#define TSB_TB2_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,0)))
+#define TSB_TB2_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,1)))
+#define TSB_TB2_CR_I2TB                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,3)))
+#define TSB_TB2_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,5)))
+#define TSB_TB2_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->CR,7)))
+#define TSB_TB2_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->MOD,3)))
+#define TSB_TB2_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB2->MOD,6)))
+#define TSB_TB2_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,2)))
+#define TSB_TB2_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,3)))
+#define TSB_TB2_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,4)))
+#define TSB_TB2_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->FFCR,5)))
+#define TSB_TB2_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,0)))
+#define TSB_TB2_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,1)))
+#define TSB_TB2_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB2->IM,2)))
+
+#define TSB_TB3_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->EN,6)))
+#define TSB_TB3_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->EN,7)))
+#define TSB_TB3_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->RUN,0)))
+#define TSB_TB3_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->RUN,2)))
+#define TSB_TB3_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,0)))
+#define TSB_TB3_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,1)))
+#define TSB_TB3_CR_I2TB                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,3)))
+#define TSB_TB3_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,5)))
+#define TSB_TB3_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->CR,7)))
+#define TSB_TB3_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->MOD,3)))
+#define TSB_TB3_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB3->MOD,6)))
+#define TSB_TB3_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,2)))
+#define TSB_TB3_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,3)))
+#define TSB_TB3_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,4)))
+#define TSB_TB3_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->FFCR,5)))
+#define TSB_TB3_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,0)))
+#define TSB_TB3_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,1)))
+#define TSB_TB3_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB3->IM,2)))
+
+#define TSB_TB4_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->EN,6)))
+#define TSB_TB4_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->EN,7)))
+#define TSB_TB4_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->RUN,0)))
+#define TSB_TB4_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->RUN,2)))
+#define TSB_TB4_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,0)))
+#define TSB_TB4_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,1)))
+#define TSB_TB4_CR_I2TB                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,3)))
+#define TSB_TB4_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,5)))
+#define TSB_TB4_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->CR,7)))
+#define TSB_TB4_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->MOD,3)))
+#define TSB_TB4_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB4->MOD,6)))
+#define TSB_TB4_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,2)))
+#define TSB_TB4_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,3)))
+#define TSB_TB4_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,4)))
+#define TSB_TB4_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->FFCR,5)))
+#define TSB_TB4_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,0)))
+#define TSB_TB4_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,1)))
+#define TSB_TB4_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB4->IM,2)))
+
+#define TSB_TB5_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->EN,6)))
+#define TSB_TB5_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->EN,7)))
+#define TSB_TB5_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->RUN,0)))
+#define TSB_TB5_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->RUN,2)))
+#define TSB_TB5_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,0)))
+#define TSB_TB5_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,1)))
+#define TSB_TB5_CR_I2TB                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,3)))
+#define TSB_TB5_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,5)))
+#define TSB_TB5_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->CR,7)))
+#define TSB_TB5_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->MOD,3)))
+#define TSB_TB5_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB5->MOD,6)))
+#define TSB_TB5_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,2)))
+#define TSB_TB5_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,3)))
+#define TSB_TB5_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,4)))
+#define TSB_TB5_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->FFCR,5)))
+#define TSB_TB5_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,0)))
+#define TSB_TB5_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,1)))
+#define TSB_TB5_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB5->IM,2)))
+
+#define TSB_TB6_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->EN,6)))
+#define TSB_TB6_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->EN,7)))
+#define TSB_TB6_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->RUN,0)))
+#define TSB_TB6_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->RUN,2)))
+#define TSB_TB6_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,0)))
+#define TSB_TB6_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,1)))
+#define TSB_TB6_CR_I2TB                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,3)))
+#define TSB_TB6_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,5)))
+#define TSB_TB6_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->CR,7)))
+#define TSB_TB6_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->MOD,3)))
+#define TSB_TB6_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB6->MOD,6)))
+#define TSB_TB6_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,2)))
+#define TSB_TB6_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,3)))
+#define TSB_TB6_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,4)))
+#define TSB_TB6_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->FFCR,5)))
+#define TSB_TB6_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,0)))
+#define TSB_TB6_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,1)))
+#define TSB_TB6_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB6->IM,2)))
+
+#define TSB_TB7_EN_TBHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->EN,6)))
+#define TSB_TB7_EN_TBEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->EN,7)))
+#define TSB_TB7_RUN_TBRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->RUN,0)))
+#define TSB_TB7_RUN_TBPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->RUN,2)))
+#define TSB_TB7_CR_CSSEL                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,0)))
+#define TSB_TB7_CR_TRGSEL                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,1)))
+#define TSB_TB7_CR_I2TB                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,3)))
+#define TSB_TB7_CR_TBSYNC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,5)))
+#define TSB_TB7_CR_TBWBF                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->CR,7)))
+#define TSB_TB7_MOD_TBCLE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->MOD,3)))
+#define TSB_TB7_MOD_TBCP                          (*((__O  uint32_t *)BITBAND_PERI(&TSB_TB7->MOD,6)))
+#define TSB_TB7_FFCR_TBE0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,2)))
+#define TSB_TB7_FFCR_TBE1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,3)))
+#define TSB_TB7_FFCR_TBC0T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,4)))
+#define TSB_TB7_FFCR_TBC1T1                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->FFCR,5)))
+#define TSB_TB7_IM_TBIM0                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,0)))
+#define TSB_TB7_IM_TBIM1                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,1)))
+#define TSB_TB7_IM_TBIMOF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_TB7->IM,2)))
+
+
+/* 16-bit Multi-Purpose Timer (MPT-TMR/IGBT) */
+#define TSB_MT0_EN_MTMODE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->EN,0)))
+#define TSB_MT0_EN_MTHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->EN,6)))
+#define TSB_MT0_EN_MTEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->EN,7)))
+#define TSB_MT0_RUN_MTRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->RUN,0)))
+#define TSB_MT0_RUN_MTPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->RUN,2)))
+#define TSB_MT0_TBCR_MTTBCSSEL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBCR,0)))
+#define TSB_MT0_TBCR_MTTBTRGSEL                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBCR,1)))
+#define TSB_MT0_TBCR_MTI2TB                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBCR,3)))
+#define TSB_MT0_TBCR_MTTBWBF                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBCR,7)))
+#define TSB_MT0_TBMOD_MTTBCLE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBMOD,2)))
+#define TSB_MT0_TBMOD_MTTBCP                      (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT0->TBMOD,5)))
+#define TSB_MT0_TBMOD_MTTBRSWR                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBMOD,6)))
+#define TSB_MT0_TBFFCR_MTTBE0T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBFFCR,2)))
+#define TSB_MT0_TBFFCR_MTTBE1T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBFFCR,3)))
+#define TSB_MT0_TBFFCR_MTTBC0T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBFFCR,4)))
+#define TSB_MT0_TBFFCR_MTTBC1T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBFFCR,5)))
+#define TSB_MT0_TBST_MTTBINTTB0                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT0->TBST,0)))
+#define TSB_MT0_TBST_MTTBINTTB1                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT0->TBST,1)))
+#define TSB_MT0_TBST_MTTBINTTBOF                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT0->TBST,2)))
+#define TSB_MT0_TBIM_MTTBIM0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBIM,0)))
+#define TSB_MT0_TBIM_MTTBIM1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBIM,1)))
+#define TSB_MT0_TBIM_MTTBIMOF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->TBIM,2)))
+#define TSB_MT0_IGCR_IGSNGL                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGCR,6)))
+#define TSB_MT0_IGCR_IGCLSYNC                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGCR,7)))
+#define TSB_MT0_IGCR_IGIDIS                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGCR,10)))
+#define TSB_MT0_IGRESTA_IGRESTA                   (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT0->IGRESTA,0)))
+#define TSB_MT0_IGST_IGST                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT0->IGST,0)))
+#define TSB_MT0_IGICR_IGTRGSEL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGICR,6)))
+#define TSB_MT0_IGICR_IGTRGM                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGICR,7)))
+#define TSB_MT0_IGOCR_IGOEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGOCR,0)))
+#define TSB_MT0_IGOCR_IGOEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGOCR,1)))
+#define TSB_MT0_IGOCR_IGPOL0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGOCR,4)))
+#define TSB_MT0_IGOCR_IGPOL1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGOCR,5)))
+#define TSB_MT0_IGEMGCR_IGEMGEN                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGEMGCR,0)))
+#define TSB_MT0_IGEMGCR_IGEMGOC                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT0->IGEMGCR,1)))
+#define TSB_MT0_IGEMGCR_IGEMGRS                   (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT0->IGEMGCR,2)))
+#define TSB_MT0_IGEMGST_IGEMGST                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT0->IGEMGST,0)))
+#define TSB_MT0_IGEMGST_IGEMGIN                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT0->IGEMGST,1)))
+
+#define TSB_MT1_EN_MTMODE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->EN,0)))
+#define TSB_MT1_EN_MTHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->EN,6)))
+#define TSB_MT1_EN_MTEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->EN,7)))
+#define TSB_MT1_RUN_MTRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->RUN,0)))
+#define TSB_MT1_RUN_MTPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->RUN,2)))
+#define TSB_MT1_TBCR_MTTBCSSEL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBCR,0)))
+#define TSB_MT1_TBCR_MTTBTRGSEL                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBCR,1)))
+#define TSB_MT1_TBCR_MTI2TB                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBCR,3)))
+#define TSB_MT1_TBCR_MTTBWBF                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBCR,7)))
+#define TSB_MT1_TBMOD_MTTBCLE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBMOD,2)))
+#define TSB_MT1_TBMOD_MTTBCP                      (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT1->TBMOD,5)))
+#define TSB_MT1_TBMOD_MTTBRSWR                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBMOD,6)))
+#define TSB_MT1_TBFFCR_MTTBE0T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBFFCR,2)))
+#define TSB_MT1_TBFFCR_MTTBE1T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBFFCR,3)))
+#define TSB_MT1_TBFFCR_MTTBC0T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBFFCR,4)))
+#define TSB_MT1_TBFFCR_MTTBC1T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBFFCR,5)))
+#define TSB_MT1_TBST_MTTBINTTB0                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT1->TBST,0)))
+#define TSB_MT1_TBST_MTTBINTTB1                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT1->TBST,1)))
+#define TSB_MT1_TBST_MTTBINTTBOF                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT1->TBST,2)))
+#define TSB_MT1_TBIM_MTTBIM0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBIM,0)))
+#define TSB_MT1_TBIM_MTTBIM1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBIM,1)))
+#define TSB_MT1_TBIM_MTTBIMOF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->TBIM,2)))
+#define TSB_MT1_IGCR_IGSNGL                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGCR,6)))
+#define TSB_MT1_IGCR_IGCLSYNC                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGCR,7)))
+#define TSB_MT1_IGCR_IGIDIS                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGCR,10)))
+#define TSB_MT1_IGRESTA_IGRESTA                   (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT1->IGRESTA,0)))
+#define TSB_MT1_IGST_IGST                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT1->IGST,0)))
+#define TSB_MT1_IGICR_IGTRGSEL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGICR,6)))
+#define TSB_MT1_IGICR_IGTRGM                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGICR,7)))
+#define TSB_MT1_IGOCR_IGOEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGOCR,0)))
+#define TSB_MT1_IGOCR_IGOEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGOCR,1)))
+#define TSB_MT1_IGOCR_IGPOL0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGOCR,4)))
+#define TSB_MT1_IGOCR_IGPOL1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGOCR,5)))
+#define TSB_MT1_IGEMGCR_IGEMGEN                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGEMGCR,0)))
+#define TSB_MT1_IGEMGCR_IGEMGOC                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT1->IGEMGCR,1)))
+#define TSB_MT1_IGEMGCR_IGEMGRS                   (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT1->IGEMGCR,2)))
+#define TSB_MT1_IGEMGST_IGEMGST                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT1->IGEMGST,0)))
+#define TSB_MT1_IGEMGST_IGEMGIN                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT1->IGEMGST,1)))
+
+#define TSB_MT2_EN_MTMODE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->EN,0)))
+#define TSB_MT2_EN_MTHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->EN,6)))
+#define TSB_MT2_EN_MTEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->EN,7)))
+#define TSB_MT2_RUN_MTRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->RUN,0)))
+#define TSB_MT2_RUN_MTPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->RUN,2)))
+#define TSB_MT2_TBCR_MTTBCSSEL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBCR,0)))
+#define TSB_MT2_TBCR_MTTBTRGSEL                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBCR,1)))
+#define TSB_MT2_TBCR_MTI2TB                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBCR,3)))
+#define TSB_MT2_TBCR_MTTBWBF                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBCR,7)))
+#define TSB_MT2_TBMOD_MTTBCLE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBMOD,2)))
+#define TSB_MT2_TBMOD_MTTBCP                      (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT2->TBMOD,5)))
+#define TSB_MT2_TBMOD_MTTBRSWR                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBMOD,6)))
+#define TSB_MT2_TBFFCR_MTTBE0T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBFFCR,2)))
+#define TSB_MT2_TBFFCR_MTTBE1T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBFFCR,3)))
+#define TSB_MT2_TBFFCR_MTTBC0T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBFFCR,4)))
+#define TSB_MT2_TBFFCR_MTTBC1T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBFFCR,5)))
+#define TSB_MT2_TBST_MTTBINTTB0                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT2->TBST,0)))
+#define TSB_MT2_TBST_MTTBINTTB1                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT2->TBST,1)))
+#define TSB_MT2_TBST_MTTBINTTBOF                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT2->TBST,2)))
+#define TSB_MT2_TBIM_MTTBIM0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBIM,0)))
+#define TSB_MT2_TBIM_MTTBIM1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBIM,1)))
+#define TSB_MT2_TBIM_MTTBIMOF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->TBIM,2)))
+#define TSB_MT2_IGCR_IGSNGL                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGCR,6)))
+#define TSB_MT2_IGCR_IGCLSYNC                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGCR,7)))
+#define TSB_MT2_IGCR_IGIDIS                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGCR,10)))
+#define TSB_MT2_IGRESTA_IGRESTA                   (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT2->IGRESTA,0)))
+#define TSB_MT2_IGST_IGST                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT2->IGST,0)))
+#define TSB_MT2_IGICR_IGTRGSEL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGICR,6)))
+#define TSB_MT2_IGICR_IGTRGM                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGICR,7)))
+#define TSB_MT2_IGOCR_IGOEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGOCR,0)))
+#define TSB_MT2_IGOCR_IGOEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGOCR,1)))
+#define TSB_MT2_IGOCR_IGPOL0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGOCR,4)))
+#define TSB_MT2_IGOCR_IGPOL1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGOCR,5)))
+#define TSB_MT2_IGEMGCR_IGEMGEN                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGEMGCR,0)))
+#define TSB_MT2_IGEMGCR_IGEMGOC                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT2->IGEMGCR,1)))
+#define TSB_MT2_IGEMGCR_IGEMGRS                   (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT2->IGEMGCR,2)))
+#define TSB_MT2_IGEMGST_IGEMGST                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT2->IGEMGST,0)))
+#define TSB_MT2_IGEMGST_IGEMGIN                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT2->IGEMGST,1)))
+
+#define TSB_MT3_EN_MTMODE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->EN,0)))
+#define TSB_MT3_EN_MTHALT                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->EN,6)))
+#define TSB_MT3_EN_MTEN                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->EN,7)))
+#define TSB_MT3_RUN_MTRUN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->RUN,0)))
+#define TSB_MT3_RUN_MTPRUN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->RUN,2)))
+#define TSB_MT3_TBCR_MTTBCSSEL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBCR,0)))
+#define TSB_MT3_TBCR_MTTBTRGSEL                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBCR,1)))
+#define TSB_MT3_TBCR_MTI2TB                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBCR,3)))
+#define TSB_MT3_TBCR_MTTBWBF                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBCR,7)))
+#define TSB_MT3_TBMOD_MTTBCLE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBMOD,2)))
+#define TSB_MT3_TBMOD_MTTBCP                      (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT3->TBMOD,5)))
+#define TSB_MT3_TBMOD_MTTBRSWR                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBMOD,6)))
+#define TSB_MT3_TBFFCR_MTTBE0T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBFFCR,2)))
+#define TSB_MT3_TBFFCR_MTTBE1T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBFFCR,3)))
+#define TSB_MT3_TBFFCR_MTTBC0T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBFFCR,4)))
+#define TSB_MT3_TBFFCR_MTTBC1T1                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBFFCR,5)))
+#define TSB_MT3_TBST_MTTBINTTB0                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT3->TBST,0)))
+#define TSB_MT3_TBST_MTTBINTTB1                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT3->TBST,1)))
+#define TSB_MT3_TBST_MTTBINTTBOF                  (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT3->TBST,2)))
+#define TSB_MT3_TBIM_MTTBIM0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBIM,0)))
+#define TSB_MT3_TBIM_MTTBIM1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBIM,1)))
+#define TSB_MT3_TBIM_MTTBIMOF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->TBIM,2)))
+#define TSB_MT3_IGCR_IGSNGL                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGCR,6)))
+#define TSB_MT3_IGCR_IGCLSYNC                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGCR,7)))
+#define TSB_MT3_IGCR_IGIDIS                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGCR,10)))
+#define TSB_MT3_IGRESTA_IGRESTA                   (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT3->IGRESTA,0)))
+#define TSB_MT3_IGST_IGST                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT3->IGST,0)))
+#define TSB_MT3_IGICR_IGTRGSEL                    (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGICR,6)))
+#define TSB_MT3_IGICR_IGTRGM                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGICR,7)))
+#define TSB_MT3_IGOCR_IGOEN0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGOCR,0)))
+#define TSB_MT3_IGOCR_IGOEN1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGOCR,1)))
+#define TSB_MT3_IGOCR_IGPOL0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGOCR,4)))
+#define TSB_MT3_IGOCR_IGPOL1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGOCR,5)))
+#define TSB_MT3_IGEMGCR_IGEMGEN                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGEMGCR,0)))
+#define TSB_MT3_IGEMGCR_IGEMGOC                   (*((__IO uint32_t *)BITBAND_PERI(&TSB_MT3->IGEMGCR,1)))
+#define TSB_MT3_IGEMGCR_IGEMGRS                   (*((__O  uint32_t *)BITBAND_PERI(&TSB_MT3->IGEMGCR,2)))
+#define TSB_MT3_IGEMGST_IGEMGST                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT3->IGEMGST,0)))
+#define TSB_MT3_IGEMGST_IGEMGIN                   (*((__I  uint32_t *)BITBAND_PERI(&TSB_MT3->IGEMGST,1)))
+
+
+/* Real Time Clock (RTC) */
+#define TSB_RTC_ADJCTL_AJEN                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_RTC->ADJCTL,0)))
+
+
+/* Serial Channel (SC) */
+#define TSB_SC0_EN_SIOE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->EN,0)))
+#define TSB_SC0_EN_BRCKSEL                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->EN,1)))
+#define TSB_SC0_MOD0_WU                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,4)))
+#define TSB_SC0_MOD0_RXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,5)))
+#define TSB_SC0_MOD0_CTSE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,6)))
+#define TSB_SC0_MOD0_TB8                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD0,7)))
+#define TSB_SC0_BRCR_BRADDE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->BRCR,6)))
+#define TSB_SC0_MOD1_TXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD1,4)))
+#define TSB_SC0_MOD1_I2SC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD1,7)))
+#define TSB_SC0_MOD2_WBUF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,2)))
+#define TSB_SC0_MOD2_DRCHG                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,3)))
+#define TSB_SC0_MOD2_SBLEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,4)))
+#define TSB_SC0_MOD2_TXRUN                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,5)))
+#define TSB_SC0_MOD2_RBFLL                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,6)))
+#define TSB_SC0_MOD2_TBEMP                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC0->MOD2,7)))
+#define TSB_SC0_TST_TUR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC0->TST,7)))
+#define TSB_SC0_FCNF_CNFG                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,0)))
+#define TSB_SC0_FCNF_RXTXCNT                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,1)))
+#define TSB_SC0_FCNF_RFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,2)))
+#define TSB_SC0_FCNF_TFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,3)))
+#define TSB_SC0_FCNF_RFST                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC0->FCNF,4)))
+
+#define TSB_SC1_EN_SIOE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->EN,0)))
+#define TSB_SC1_EN_BRCKSEL                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->EN,1)))
+#define TSB_SC1_MOD0_WU                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,4)))
+#define TSB_SC1_MOD0_RXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,5)))
+#define TSB_SC1_MOD0_CTSE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,6)))
+#define TSB_SC1_MOD0_TB8                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD0,7)))
+#define TSB_SC1_BRCR_BRADDE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->BRCR,6)))
+#define TSB_SC1_MOD1_TXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD1,4)))
+#define TSB_SC1_MOD1_I2SC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD1,7)))
+#define TSB_SC1_MOD2_WBUF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,2)))
+#define TSB_SC1_MOD2_DRCHG                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,3)))
+#define TSB_SC1_MOD2_SBLEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,4)))
+#define TSB_SC1_MOD2_TXRUN                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,5)))
+#define TSB_SC1_MOD2_RBFLL                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,6)))
+#define TSB_SC1_MOD2_TBEMP                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC1->MOD2,7)))
+#define TSB_SC1_TST_TUR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC1->TST,7)))
+#define TSB_SC1_FCNF_CNFG                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,0)))
+#define TSB_SC1_FCNF_RXTXCNT                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,1)))
+#define TSB_SC1_FCNF_RFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,2)))
+#define TSB_SC1_FCNF_TFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,3)))
+#define TSB_SC1_FCNF_RFST                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC1->FCNF,4)))
+
+#define TSB_SC2_EN_SIOE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->EN,0)))
+#define TSB_SC2_EN_BRCKSEL                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->EN,1)))
+#define TSB_SC2_MOD0_WU                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->MOD0,4)))
+#define TSB_SC2_MOD0_RXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->MOD0,5)))
+#define TSB_SC2_MOD0_CTSE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->MOD0,6)))
+#define TSB_SC2_MOD0_TB8                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->MOD0,7)))
+#define TSB_SC2_BRCR_BRADDE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->BRCR,6)))
+#define TSB_SC2_MOD1_TXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->MOD1,4)))
+#define TSB_SC2_MOD1_I2SC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->MOD1,7)))
+#define TSB_SC2_MOD2_WBUF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->MOD2,2)))
+#define TSB_SC2_MOD2_DRCHG                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->MOD2,3)))
+#define TSB_SC2_MOD2_SBLEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->MOD2,4)))
+#define TSB_SC2_MOD2_TXRUN                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC2->MOD2,5)))
+#define TSB_SC2_MOD2_RBFLL                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC2->MOD2,6)))
+#define TSB_SC2_MOD2_TBEMP                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC2->MOD2,7)))
+#define TSB_SC2_TST_TUR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC2->TST,7)))
+#define TSB_SC2_FCNF_CNFG                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->FCNF,0)))
+#define TSB_SC2_FCNF_RXTXCNT                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->FCNF,1)))
+#define TSB_SC2_FCNF_RFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->FCNF,2)))
+#define TSB_SC2_FCNF_TFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->FCNF,3)))
+#define TSB_SC2_FCNF_RFST                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC2->FCNF,4)))
+
+#define TSB_SC3_EN_SIOE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->EN,0)))
+#define TSB_SC3_EN_BRCKSEL                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->EN,1)))
+#define TSB_SC3_MOD0_WU                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->MOD0,4)))
+#define TSB_SC3_MOD0_RXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->MOD0,5)))
+#define TSB_SC3_MOD0_CTSE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->MOD0,6)))
+#define TSB_SC3_MOD0_TB8                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->MOD0,7)))
+#define TSB_SC3_BRCR_BRADDE                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->BRCR,6)))
+#define TSB_SC3_MOD1_TXE                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->MOD1,4)))
+#define TSB_SC3_MOD1_I2SC                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->MOD1,7)))
+#define TSB_SC3_MOD2_WBUF                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->MOD2,2)))
+#define TSB_SC3_MOD2_DRCHG                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->MOD2,3)))
+#define TSB_SC3_MOD2_SBLEN                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->MOD2,4)))
+#define TSB_SC3_MOD2_TXRUN                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC3->MOD2,5)))
+#define TSB_SC3_MOD2_RBFLL                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC3->MOD2,6)))
+#define TSB_SC3_MOD2_TBEMP                        (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC3->MOD2,7)))
+#define TSB_SC3_TST_TUR                           (*((__I  uint32_t *)BITBAND_PERI(&TSB_SC3->TST,7)))
+#define TSB_SC3_FCNF_CNFG                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->FCNF,0)))
+#define TSB_SC3_FCNF_RXTXCNT                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->FCNF,1)))
+#define TSB_SC3_FCNF_RFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->FCNF,2)))
+#define TSB_SC3_FCNF_TFIE                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->FCNF,3)))
+#define TSB_SC3_FCNF_RFST                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_SC3->FCNF,4)))
+
+
+/* Watchdog Timer (WD) */
+#define TSB_WD_MOD_RESCR                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,1)))
+#define TSB_WD_MOD_I2WDT                          (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,2)))
+#define TSB_WD_MOD_WDTE                           (*((__IO uint32_t *)BITBAND_PERI(&TSB_WD->MOD,7)))
+#define TSB_WD_FLG_FLG                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_WD->FLG,0)))
+
+
+/* Clock Generator (CG) */
+#define TSB_CG_SYSCR_FPSEL                        (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SYSCR,12)))
+#define TSB_CG_SYSCR_FCSTOP                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->SYSCR,20)))
+#define TSB_CG_OSCCR_XEN1                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,0)))
+#define TSB_CG_OSCCR_XEN2                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,1)))
+#define TSB_CG_OSCCR_XTEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,3)))
+#define TSB_CG_OSCCR_DRVOSCL                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,7)))
+#define TSB_CG_OSCCR_OSCSEL                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,8)))
+#define TSB_CG_OSCCR_OSCF                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,9)))
+#define TSB_CG_OSCCR_HOSCON                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,10)))
+#define TSB_CG_OSCCR_DRVOSCH                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,12)))
+#define TSB_CG_OSCCR_WUEON                        (*((__O  uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,14)))
+#define TSB_CG_OSCCR_WUEF                         (*((__I  uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,15)))
+#define TSB_CG_OSCCR_WUPSEL1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,16)))
+#define TSB_CG_OSCCR_WUPSEL2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->OSCCR,17)))
+#define TSB_CG_STBYCR_PTKEEP                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->STBYCR,17)))
+#define TSB_CG_PLLSEL_PLLON                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLLSEL,16)))
+#define TSB_CG_PLLSEL_PLLSEL                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->PLLSEL,17)))
+#define TSB_CG_PLLSEL_PLLST                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_CG->PLLSEL,18)))
+#define TSB_CG_FSYSMSKA_PORTA                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,0)))
+#define TSB_CG_FSYSMSKA_PORTB                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,1)))
+#define TSB_CG_FSYSMSKA_PORTC                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,2)))
+#define TSB_CG_FSYSMSKA_PORTD                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,3)))
+#define TSB_CG_FSYSMSKA_PORTE                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,4)))
+#define TSB_CG_FSYSMSKA_PORTF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,5)))
+#define TSB_CG_FSYSMSKA_PORTG                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,6)))
+#define TSB_CG_FSYSMSKA_PORTH                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,7)))
+#define TSB_CG_FSYSMSKA_PORTJ                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,8)))
+#define TSB_CG_FSYSMSKA_PORTK                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,9)))
+#define TSB_CG_FSYSMSKA_PORTL                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,10)))
+#define TSB_CG_FSYSMSKA_TMRB0                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,13)))
+#define TSB_CG_FSYSMSKA_TMRB1                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,14)))
+#define TSB_CG_FSYSMSKA_TMRB2                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,15)))
+#define TSB_CG_FSYSMSKA_TMRB3                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,16)))
+#define TSB_CG_FSYSMSKA_TMRB4                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,17)))
+#define TSB_CG_FSYSMSKA_TMRB5                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,18)))
+#define TSB_CG_FSYSMSKA_TMRB6                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,19)))
+#define TSB_CG_FSYSMSKA_TMRB7                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,20)))
+#define TSB_CG_FSYSMSKA_MPT0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,27)))
+#define TSB_CG_FSYSMSKA_MPT1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,28)))
+#define TSB_CG_FSYSMSKA_MPT2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,29)))
+#define TSB_CG_FSYSMSKA_MPT3                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,30)))
+#define TSB_CG_FSYSMSKA_TRACECLK                  (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKA,31)))
+#define TSB_CG_FSYSMSKB_SIO0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,0)))
+#define TSB_CG_FSYSMSKB_SIO1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,1)))
+#define TSB_CG_FSYSMSKB_SIO2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,2)))
+#define TSB_CG_FSYSMSKB_SIO3                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,3)))
+#define TSB_CG_FSYSMSKB_UART0                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,10)))
+#define TSB_CG_FSYSMSKB_UART1                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,11)))
+#define TSB_CG_FSYSMSKB_I2C0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,12)))
+#define TSB_CG_FSYSMSKB_I2C1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,13)))
+#define TSB_CG_FSYSMSKB_I2C2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,14)))
+#define TSB_CG_FSYSMSKB_SSP0                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,17)))
+#define TSB_CG_FSYSMSKB_SSP1                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,18)))
+#define TSB_CG_FSYSMSKB_SSP2                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,19)))
+#define TSB_CG_FSYSMSKB_EBIF                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,20)))
+#define TSB_CG_FSYSMSKB_DMAA                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,21)))
+#define TSB_CG_FSYSMSKB_DMAB                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,22)))
+#define TSB_CG_FSYSMSKB_DMAC                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,23)))
+#define TSB_CG_FSYSMSKB_DMAIF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,24)))
+#define TSB_CG_FSYSMSKB_ADC                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,25)))
+#define TSB_CG_FSYSMSKB_WDT                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,26)))
+#define TSB_CG_FSYSMSKB_AES                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,28)))
+#define TSB_CG_FSYSMSKB_SHA                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,29)))
+#define TSB_CG_FSYSMSKB_ESG                       (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,30)))
+#define TSB_CG_FSYSMSKB_MLA                       (*((__I  uint32_t *)BITBAND_PERI(&TSB_CG->FSYSMSKB,31)))
+#define TSB_CG_IMCGA_INT00EN                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->IMCGA,0)))
+#define TSB_CG_IMCGA_INT01EN                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->IMCGA,8)))
+#define TSB_CG_IMCGA_INT02EN                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->IMCGA,16)))
+#define TSB_CG_IMCGA_INT03EN                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->IMCGA,24)))
+#define TSB_CG_IMCGB_INT04EN                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->IMCGB,0)))
+#define TSB_CG_IMCGB_INT05EN                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->IMCGB,8)))
+#define TSB_CG_IMCGB_INT06EN                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->IMCGB,16)))
+#define TSB_CG_IMCGB_INT07EN                      (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->IMCGB,24)))
+#define TSB_CG_RSTFLG_PINRSTF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->RSTFLG,0)))
+#define TSB_CG_RSTFLG_OSCFLF                      (*((__I  uint32_t *)BITBAND_PERI(&TSB_CG->RSTFLG,1)))
+#define TSB_CG_RSTFLG_WDTRSTF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->RSTFLG,2)))
+#define TSB_CG_RSTFLG_BUPRSTF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->RSTFLG,3)))
+#define TSB_CG_RSTFLG_SYSRSTF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->RSTFLG,4)))
+#define TSB_CG_RSTFLG_LVDRSTF                     (*((__IO uint32_t *)BITBAND_PERI(&TSB_CG->RSTFLG,6)))
+
+
+/* Low voltage detecter */
+#define TSB_LVD_CR1_EN                            (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,0)))
+#define TSB_LVD_CR1_INTEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,5)))
+#define TSB_LVD_CR1_RSTEN                         (*((__IO uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,6)))
+#define TSB_LVD_CR1_ST                            (*((__I  uint32_t *)BITBAND_PERI(&TSB_LVD->CR1,7)))
+
+/** @} */ /* End of group Device_Peripheral_registers */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __TMPM46B_H__ */
+
+/** @} */ /* End of group TMPM46B */
+/** @} */ /* End of group TOSHIBA_TX04_MICROCONTROLLER */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/TOOLCHAIN_ARM_STD/startup_TMPM46B.S	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,418 @@
+;/**
+; *******************************************************************************
+; * @file    startup_TMPM46B.s
+; * @brief   CMSIS Cortex-M4 Core Device Startup File for the
+; *          TOSHIBA 'TMPM46B' Device Series
+; * @version V2.0.2.4
+; * @date    2015/03/31
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; * 
+; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+; * 
+; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+; *******************************************************************************
+; */
+
+__initial_sp    EQU     0x20080000
+
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors   DCD __initial_sp              ; Top of Stack
+            DCD Reset_Handler             ; Reset Handler
+            DCD NMI_Handler               ; NMI Handler
+            DCD HardFault_Handler         ; Hard Fault Handler
+            DCD MemManage_Handler         ; MPU Fault Handler
+            DCD BusFault_Handler          ; Bus Fault Handler
+            DCD UsageFault_Handler        ; Usage Fault Handler
+            DCD 0                         ; Reserved
+            DCD 0                         ; Reserved
+            DCD 0                         ; Reserved
+            DCD 0                         ; Reserved
+            DCD SVC_Handler               ; SVCall Handler
+            DCD DebugMon_Handler          ; Debug Monitor Handler
+            DCD 0                         ; Reserved
+            DCD PendSV_Handler            ; PendSV Handler
+            DCD SysTick_Handler           ; SysTick Handler
+
+            ; External Interrupts
+            DCD INT0_IRQHandler           ; 0: Interrupt pin 0
+            DCD INT1_IRQHandler           ; 1: Interrupt pin 1
+            DCD INT2_IRQHandler           ; 2: Interrupt pin 2
+            DCD INT3_IRQHandler           ; 3: Interrupt pin 3
+            DCD INT4_IRQHandler           ; 4: Interrupt pin 4
+            DCD INT5_IRQHandler           ; 5: Interrupt pin 5
+            DCD INT6_IRQHandler           ; 6: Interrupt pin 6
+            DCD INT7_IRQHandler           ; 7: Interrupt pin 7
+            DCD INT8_IRQHandler           ; 8: Interrupt pin 8
+            DCD INT9_IRQHandler           ; 9: Interrupt pin 9
+            DCD INTA_IRQHandler           ; 10: Interrupt pin A
+            DCD INTB_IRQHandler           ; 11: Interrupt pin B
+            DCD INTC_IRQHandler           ; 12: Interrupt pin C
+            DCD INTD_IRQHandler           ; 13: Interrupt pin D
+            DCD INTE_IRQHandler           ; 14: Interrupt pin E
+            DCD INTF_IRQHandler           ; 15: Interrupt pin F
+            DCD INTRX0_IRQHandler         ; 16: Serial0 reception interrupt
+            DCD INTTX0_IRQHandler         ; 17: Serial0 transmission interrupt
+            DCD INTRX1_IRQHandler         ; 18: Serial1 reception interrupt
+            DCD INTTX1_IRQHandler         ; 19: Serial1 transmission interrupt
+            DCD INTRX2_IRQHandler         ; 20: Serial2 reception interrupt
+            DCD INTTX2_IRQHandler         ; 21: Serial2 transmission interrupt
+            DCD INTRX3_IRQHandler         ; 22: Serial3 reception interrupt
+            DCD INTTX3_IRQHandler         ; 23: Serial3 transmission interrupt
+            DCD INTUART0_IRQHandler       ; 24: Full UART0 transmission and reception interrupt
+            DCD INTUART1_IRQHandler       ; 25: Full UART1 transmission and reception interrupt
+            DCD INTI2C0_IRQHandler        ; 26: I2C0 transmission and reception interrupt
+            DCD INTI2C1_IRQHandler        ; 27: I2C1 transmission and reception interrupt
+            DCD INTI2C2_IRQHandler        ; 28: I2C2 transmission and reception interrupt
+            DCD INTSSP0_IRQHandler        ; 29: SSP(SPI) Serial interface 0 interrupt 
+            DCD INTSSP1_IRQHandler        ; 30: SSP(SPI) Serial interface 1 interrupt 
+            DCD INTSSP2_IRQHandler        ; 31: SSP(SPI) Serial interface 2 interrupt 
+            DCD INTADHP_IRQHandler        ; 32: High Priority AD conversion interrupt
+            DCD INTADM0_IRQHandler        ; 33: AD conversion monitor interrupt 0
+            DCD INTADM1_IRQHandler        ; 34: AD conversion monitor interrupt 1
+            DCD INTAD_IRQHandler          ; 35: AD conversion interrupt 
+            DCD INTAES_IRQHandler         ; 36: AES completion interrupt
+            DCD INTSHA_IRQHandler         ; 37: SHA completion interrupt
+            DCD INTMLA_IRQHandler         ; 38: MLA completion interrupt
+            DCD INTESG_IRQHandler         ; 39: ESG completion interrupt
+            DCD INTSNFCSEQ_IRQHandler     ; 40: SNFC command sequence end interrupt
+            DCD INTSNFCPRTAE_IRQHandler   ; 41: SNFC page lead RAM transfer end interrupt
+            DCD INTSNFCPRTCE_IRQHandler   ; 42: SNFC decode data RAM transmission end interrupt
+            DCD INTSNFCFAIL_IRQHandler    ; 43: SNFC decode fail interrupt
+            DCD 0                         ; 44: Reserved1
+            DCD 0                         ; 45: Reserved2
+            DCD 0                         ; 46: Reserved3
+            DCD INTMTEMG0_IRQHandler      ; 47: MPT0 EMG interrupt
+            DCD INTMTPTB00_IRQHandler     ; 48: MPT0 compare match0/overflow,IGBT cycle interrupt
+            DCD INTMTPTB01_IRQHandler     ; 49: MPT0 compare match1/overflow,IGBT cycle interrupt
+            DCD INTMTCAP00_IRQHandler     ; 50: MPT0 input capture0 interrupt
+            DCD INTMTCAP01_IRQHandler     ; 51: MPT0 input capture1 interrupt
+            DCD INTMTEMG1_IRQHandler      ; 52: MPT1 EMG interrupt
+            DCD INTMTPTB10_IRQHandler     ; 53: MPT1 compare match0/overflow,IGBT cycle interrupt
+            DCD INTMTPTB11_IRQHandler     ; 54: MPT1 compare match1/overflow,IGBT cycle interrupt
+            DCD INTMTCAP10_IRQHandler     ; 55: MPT1 input capture0 interrupt
+            DCD INTMTCAP11_IRQHandler     ; 56: MPT1 input capture1 interrupt
+            DCD INTMTEMG2_IRQHandler      ; 57: MPT2 EMG interrupt
+            DCD INTMTPTB20_IRQHandler     ; 58: MPT2 compare match0/overflow,IGBT cycle interrupt
+            DCD INTMTTTB21_IRQHandler     ; 59: MPT2 compare match1/overflow,IGBT cycle interrupt
+            DCD INTMTCAP20_IRQHandler     ; 60: MPT2 input capture0 interrupt
+            DCD INTMTCAP21_IRQHandler     ; 61: MPT2 input capture1 interrupt
+            DCD INTMTEMG3_IRQHandler      ; 62: MPT3 EMG interrupt
+            DCD INTMTPTB30_IRQHandler     ; 63: MPT3 compare match0/overflow,IGBT cycle interrupt
+            DCD INTMTTTB31_IRQHandler     ; 64: MPT3 compare match1/overflow,IGBT cycle interrupt
+            DCD INTMTCAP30_IRQHandler     ; 65: MPT3 input capture0 interrupt
+            DCD INTMTCAP31_IRQHandler     ; 66: MPT3 input capture1 interrupt
+            DCD INTTB0_IRQHandler         ; 67: TMRB0 compare match detection interrupt
+            DCD INTCAP00_IRQHandler       ; 68: TMRB0 input capture 0 interrupt
+            DCD INTCAP01_IRQHandler       ; 69: TMRB0 input capture 1 interrupt
+            DCD INTTB1_IRQHandler         ; 70: TMRB1 compare match detection interrupt
+            DCD INTCAP10_IRQHandler       ; 71: TMRB1 input capture 0 interrupt
+            DCD INTCAP11_IRQHandler       ; 72: TMRB1 input capture 1 interrupt
+            DCD INTTB2_IRQHandler         ; 73: TMRB2 compare match detection interrupt
+            DCD INTCAP20_IRQHandler       ; 74: TMRB2 input capture 0 interrupt
+            DCD INTCAP21_IRQHandler       ; 75: TMRB2 input capture 1 interrupt
+            DCD INTTB3_IRQHandler         ; 76: TMRB3 compare match detection interrupt
+            DCD INTCAP30_IRQHandler       ; 77: TMRB3 input capture 0 interrupt
+            DCD INTCAP31_IRQHandler       ; 78: TMRB3 input capture 1 interrupt
+            DCD INTTB4_IRQHandler         ; 79: TMRB4 compare match detection interrupt
+            DCD INTCAP40_IRQHandler       ; 80: TMRB4 input capture 0 interrupt
+            DCD INTCAP41_IRQHandler       ; 81: TMRB4 input capture 1 interrupt
+            DCD INTTB5_IRQHandler         ; 82: TMRB5 compare match detection interrupt
+            DCD INTCAP50_IRQHandler       ; 83: TMRB5 input capture 0 interrupt
+            DCD INTCAP51_IRQHandler       ; 84: TMRB5 input capture 1 interrupt
+            DCD INTTB6_IRQHandler         ; 85: TMRB6 compare match detection interrupt
+            DCD INTCAP60_IRQHandler       ; 86: TMRB6 input capture 0 interrupt
+            DCD INTCAP61_IRQHandler       ; 87: TMRB6 input capture 1 interrupt
+            DCD INTTB7_IRQHandler         ; 88: TMRB7 compare match detection interrupt
+            DCD INTCAP70_IRQHandler       ; 89: TMRB7 input capture 0 interrupt
+            DCD INTCAP71_IRQHandler       ; 90: TMRB7 input capture 1 interrupt
+            DCD INTRTC_IRQHandler         ; 91: Real time clock interrupt
+            DCD INTDMAA_IRQHandler        ; 92: DMAC unitA transmission completion interrupt(ch4-31)
+            DCD INTDMAB_IRQHandler        ; 93: DMAC unitB transmission completion interrupt(ch24-31)
+            DCD INTDMAC_IRQHandler        ; 94: DMAC unitC transmission completion interrupt(ch12-31)
+            DCD INTDMACTC8_IRQHandler     ; 95: DMAC unitC transmission completion interrupt(ch8)
+            DCD INTDMACTC9_IRQHandler     ; 96: DMAC unitC transmission completion interrupt(ch9)
+            DCD INTDMACTC10_IRQHandler    ; 97: DMAC unitC transmission completion interrupt(ch10)
+            DCD INTDMACTC11_IRQHandler    ; 98: DMAC unitC transmission completion interrupt(ch11)
+            DCD INTDMAAERR_IRQHandler     ; 99: DMAC transmission error interrupt(unitA)
+            DCD INTDMABERR_IRQHandler     ; 100: DMAC transmission error interrupt(unitB)
+            DCD INTDMACERR_IRQHandler     ; 101: DMAC transmission error interrupt(unitC)
+            DCD INTFLRDY_IRQHandler       ; 102: Flash Ready interrupt
+
+
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler           [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler             [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler       [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler       [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler        [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler      [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler             [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler        [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler          [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler         [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT INT0_IRQHandler           [WEAK]
+                EXPORT INT1_IRQHandler           [WEAK]
+                EXPORT INT2_IRQHandler           [WEAK]
+                EXPORT INT3_IRQHandler           [WEAK]
+                EXPORT INT4_IRQHandler           [WEAK]
+                EXPORT INT5_IRQHandler           [WEAK]
+                EXPORT INT6_IRQHandler           [WEAK]
+                EXPORT INT7_IRQHandler           [WEAK]
+                EXPORT INT8_IRQHandler           [WEAK]
+                EXPORT INT9_IRQHandler           [WEAK]
+                EXPORT INTA_IRQHandler           [WEAK]
+                EXPORT INTB_IRQHandler           [WEAK]
+                EXPORT INTC_IRQHandler           [WEAK]
+                EXPORT INTD_IRQHandler           [WEAK]
+                EXPORT INTE_IRQHandler           [WEAK]
+                EXPORT INTF_IRQHandler           [WEAK]
+                EXPORT INTRX0_IRQHandler         [WEAK]
+                EXPORT INTTX0_IRQHandler         [WEAK]
+                EXPORT INTRX1_IRQHandler         [WEAK]
+                EXPORT INTTX1_IRQHandler         [WEAK]
+                EXPORT INTRX2_IRQHandler         [WEAK]
+                EXPORT INTTX2_IRQHandler         [WEAK]
+                EXPORT INTRX3_IRQHandler         [WEAK]
+                EXPORT INTTX3_IRQHandler         [WEAK]
+                EXPORT INTUART0_IRQHandler       [WEAK]
+                EXPORT INTUART1_IRQHandler       [WEAK]
+                EXPORT INTI2C0_IRQHandler        [WEAK]
+                EXPORT INTI2C1_IRQHandler        [WEAK]
+                EXPORT INTI2C2_IRQHandler        [WEAK]
+                EXPORT INTSSP0_IRQHandler        [WEAK]
+                EXPORT INTSSP1_IRQHandler        [WEAK]
+                EXPORT INTSSP2_IRQHandler        [WEAK]
+                EXPORT INTADHP_IRQHandler        [WEAK]
+                EXPORT INTADM0_IRQHandler        [WEAK]
+                EXPORT INTADM1_IRQHandler        [WEAK]
+                EXPORT INTAD_IRQHandler          [WEAK]
+                EXPORT INTAES_IRQHandler         [WEAK]
+                EXPORT INTSHA_IRQHandler         [WEAK]
+                EXPORT INTMLA_IRQHandler         [WEAK]
+                EXPORT INTESG_IRQHandler         [WEAK]
+                EXPORT INTSNFCSEQ_IRQHandler     [WEAK]
+                EXPORT INTSNFCPRTAE_IRQHandler   [WEAK]
+                EXPORT INTSNFCPRTCE_IRQHandler   [WEAK]
+                EXPORT INTSNFCFAIL_IRQHandler    [WEAK]
+                EXPORT INTMTEMG0_IRQHandler      [WEAK]
+                EXPORT INTMTPTB00_IRQHandler     [WEAK]
+                EXPORT INTMTPTB01_IRQHandler     [WEAK]
+                EXPORT INTMTCAP00_IRQHandler     [WEAK]
+                EXPORT INTMTCAP01_IRQHandler     [WEAK]
+                EXPORT INTMTEMG1_IRQHandler      [WEAK]
+                EXPORT INTMTPTB10_IRQHandler     [WEAK]
+                EXPORT INTMTPTB11_IRQHandler     [WEAK]
+                EXPORT INTMTCAP10_IRQHandler     [WEAK]
+                EXPORT INTMTCAP11_IRQHandler     [WEAK]
+                EXPORT INTMTEMG2_IRQHandler      [WEAK]
+                EXPORT INTMTPTB20_IRQHandler     [WEAK]
+                EXPORT INTMTTTB21_IRQHandler     [WEAK]
+                EXPORT INTMTCAP20_IRQHandler     [WEAK]
+                EXPORT INTMTCAP21_IRQHandler     [WEAK]
+                EXPORT INTMTEMG3_IRQHandler      [WEAK]
+                EXPORT INTMTPTB30_IRQHandler     [WEAK]
+                EXPORT INTMTTTB31_IRQHandler     [WEAK]
+                EXPORT INTMTCAP30_IRQHandler     [WEAK]
+                EXPORT INTMTCAP31_IRQHandler     [WEAK]
+                EXPORT INTTB0_IRQHandler         [WEAK]
+                EXPORT INTCAP00_IRQHandler       [WEAK]
+                EXPORT INTCAP01_IRQHandler       [WEAK]
+                EXPORT INTTB1_IRQHandler         [WEAK]
+                EXPORT INTCAP10_IRQHandler       [WEAK]
+                EXPORT INTCAP11_IRQHandler       [WEAK]
+                EXPORT INTTB2_IRQHandler         [WEAK]
+                EXPORT INTCAP20_IRQHandler       [WEAK]
+                EXPORT INTCAP21_IRQHandler       [WEAK]
+                EXPORT INTTB3_IRQHandler         [WEAK]
+                EXPORT INTCAP30_IRQHandler       [WEAK]
+                EXPORT INTCAP31_IRQHandler       [WEAK]
+                EXPORT INTTB4_IRQHandler         [WEAK]
+                EXPORT INTCAP40_IRQHandler       [WEAK]
+                EXPORT INTCAP41_IRQHandler       [WEAK]
+                EXPORT INTTB5_IRQHandler         [WEAK]
+                EXPORT INTCAP50_IRQHandler       [WEAK]
+                EXPORT INTCAP51_IRQHandler       [WEAK]
+                EXPORT INTTB6_IRQHandler         [WEAK]
+                EXPORT INTCAP60_IRQHandler       [WEAK]
+                EXPORT INTCAP61_IRQHandler       [WEAK]
+                EXPORT INTTB7_IRQHandler         [WEAK]
+                EXPORT INTCAP70_IRQHandler       [WEAK]
+                EXPORT INTCAP71_IRQHandler       [WEAK]
+                EXPORT INTRTC_IRQHandler         [WEAK]
+                EXPORT INTDMAA_IRQHandler        [WEAK]
+                EXPORT INTDMAB_IRQHandler        [WEAK]
+                EXPORT INTDMAC_IRQHandler        [WEAK]
+                EXPORT INTDMACTC8_IRQHandler     [WEAK]
+                EXPORT INTDMACTC9_IRQHandler     [WEAK]
+                EXPORT INTDMACTC10_IRQHandler    [WEAK]
+                EXPORT INTDMACTC11_IRQHandler    [WEAK]
+                EXPORT INTDMAAERR_IRQHandler     [WEAK]
+                EXPORT INTDMABERR_IRQHandler     [WEAK]
+                EXPORT INTDMACERR_IRQHandler     [WEAK]
+                EXPORT INTFLRDY_IRQHandler       [WEAK]
+
+INT0_IRQHandler
+INT1_IRQHandler
+INT2_IRQHandler
+INT3_IRQHandler
+INT4_IRQHandler
+INT5_IRQHandler
+INT6_IRQHandler
+INT7_IRQHandler
+INT8_IRQHandler
+INT9_IRQHandler
+INTA_IRQHandler
+INTB_IRQHandler
+INTC_IRQHandler
+INTD_IRQHandler
+INTE_IRQHandler
+INTF_IRQHandler
+INTRX0_IRQHandler
+INTTX0_IRQHandler
+INTRX1_IRQHandler
+INTTX1_IRQHandler
+INTRX2_IRQHandler
+INTTX2_IRQHandler
+INTRX3_IRQHandler
+INTTX3_IRQHandler
+INTUART0_IRQHandler
+INTUART1_IRQHandler
+INTI2C0_IRQHandler
+INTI2C1_IRQHandler
+INTI2C2_IRQHandler
+INTSSP0_IRQHandler
+INTSSP1_IRQHandler
+INTSSP2_IRQHandler
+INTADHP_IRQHandler
+INTADM0_IRQHandler
+INTADM1_IRQHandler
+INTAD_IRQHandler
+INTAES_IRQHandler
+INTSHA_IRQHandler
+INTMLA_IRQHandler
+INTESG_IRQHandler
+INTSNFCSEQ_IRQHandler
+INTSNFCPRTAE_IRQHandler
+INTSNFCPRTCE_IRQHandler
+INTSNFCFAIL_IRQHandler
+INTMTEMG0_IRQHandler
+INTMTPTB00_IRQHandler
+INTMTPTB01_IRQHandler
+INTMTCAP00_IRQHandler
+INTMTCAP01_IRQHandler
+INTMTEMG1_IRQHandler
+INTMTPTB10_IRQHandler
+INTMTPTB11_IRQHandler
+INTMTCAP10_IRQHandler
+INTMTCAP11_IRQHandler
+INTMTEMG2_IRQHandler
+INTMTPTB20_IRQHandler
+INTMTTTB21_IRQHandler
+INTMTCAP20_IRQHandler
+INTMTCAP21_IRQHandler
+INTMTEMG3_IRQHandler
+INTMTPTB30_IRQHandler
+INTMTTTB31_IRQHandler
+INTMTCAP30_IRQHandler
+INTMTCAP31_IRQHandler
+INTTB0_IRQHandler
+INTCAP00_IRQHandler
+INTCAP01_IRQHandler
+INTTB1_IRQHandler
+INTCAP10_IRQHandler
+INTCAP11_IRQHandler
+INTTB2_IRQHandler
+INTCAP20_IRQHandler
+INTCAP21_IRQHandler
+INTTB3_IRQHandler
+INTCAP30_IRQHandler
+INTCAP31_IRQHandler
+INTTB4_IRQHandler
+INTCAP40_IRQHandler
+INTCAP41_IRQHandler
+INTTB5_IRQHandler
+INTCAP50_IRQHandler
+INTCAP51_IRQHandler
+INTTB6_IRQHandler
+INTCAP60_IRQHandler
+INTCAP61_IRQHandler
+INTTB7_IRQHandler
+INTCAP70_IRQHandler
+INTCAP71_IRQHandler
+INTRTC_IRQHandler
+INTDMAA_IRQHandler
+INTDMAB_IRQHandler
+INTDMAC_IRQHandler
+INTDMACTC8_IRQHandler
+INTDMACTC9_IRQHandler
+INTDMACTC10_IRQHandler
+INTDMACTC11_IRQHandler
+INTDMAAERR_IRQHandler
+INTDMABERR_IRQHandler
+INTDMACERR_IRQHandler
+INTFLRDY_IRQHandler
+
+                B       .
+
+                ENDP
+                
+                ALIGN
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/TOOLCHAIN_ARM_STD/tmpm46bf10fg.sct	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,41 @@
+#! armcc -E -I. --cpu Cortex-M4
+;;  TMPM46BF10 scatter file
+
+;;  Vector table starts at 0
+;;    Initial SP == |Image$$ARM_LIB_STACK$$ZI$$Limit| (for two region model)
+;;               or |Image$$ARM_LIB_STACKHEAP$$ZI$$Limit| (for one region model)
+;;    Initial PC == &__main (with LSB set to indicate Thumb)
+;;    These two values are provided by the library
+;;    Other vectors must be provided by the user
+;;  Code starts after the last possible vector
+;;  Data starts at 0x20000000
+;;    Heap is positioned by ARM_LIB_HEAB (this is the heap managed by the ARM libraries)
+;;    Stack is positioned by ARM_LIB_STACK (library will use this to set SP - see above)
+
+;; Compatible with ISSM model
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x100000
+#endif
+
+; TMPM46B: 1024 KB FLASH (0x100000) + 512 KB SRAM (0x80000)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE ; load region size_region
+{
+  ER_IROM1 MBED_APP_START MBED_APP_SIZE
+  {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+
+  RW_IRAM1 0x200001E0 (0x80000 - 0x1E0)
+  {
+     tmpm46b_fc.o(+RO)
+    .ANY (+RW, +ZI)
+  }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/TOOLCHAIN_GCC_ARM/startup_TMPM46b.S	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,453 @@
+/**
+ *******************************************************************************
+ * @file    startup_TMPM46b.s
+ * @brief   CMSIS Cortex-M4F Core Device Startup File for the
+ *          TOSHIBA 'TMPM46B' Device Series
+ * @version V5.00
+ * @date    2016/03/02
+ *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *******************************************************************************
+ */
+
+.syntax unified
+.arch    armv7-m
+
+.section .stack
+.align 3
+
+/*
+// <h> Stack Configuration
+//   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+#ifdef __STACK_SIZE
+.equ    Stack_Size, __STACK_SIZE
+#else
+.equ    Stack_Size, 0x400
+#endif
+.globl    __StackTop
+.globl    __StackLimit
+__StackLimit:
+.space    Stack_Size
+.size __StackLimit, . - __StackLimit
+__StackTop:
+.size __StackTop, . - __StackTop
+
+/*
+// <h> Heap Configuration
+//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+// </h>
+*/
+
+.section .heap
+.align 3
+#ifdef __HEAP_SIZE
+.equ    Heap_Size, __HEAP_SIZE
+#else
+.equ    Heap_Size, 0
+#endif
+.globl    __HeapBase
+.globl    __HeapLimit
+__HeapBase:
+.if    Heap_Size
+.space    Heap_Size
+.endif
+.size __HeapBase, . - __HeapBase
+__HeapLimit:
+.size __HeapLimit, . - __HeapLimit
+
+    .section .vectors
+    .align 2
+    .globl    __Vectors
+__Vectors:
+    .long   __StackTop                  /* Top of Stack          */
+    .long   Reset_Handler               /* Reset Handler         */
+    .long   NMI_Handler                 /* NMI Handler           */
+    .long   HardFault_Handler           /* Hard Fault Handler    */
+    .long   MemManage_Handler           /* MPU Fault Handler     */
+    .long   BusFault_Handler            /* Bus Fault Handler     */
+    .long   UsageFault_Handler          /* Usage Fault Handler   */
+    .long   0                           /* Reserved              */
+    .long   0                           /* Reserved              */
+    .long   0                           /* Reserved              */
+    .long   0                           /* Reserved              */
+    .long   SVC_Handler                 /* SVCall Handler        */
+    .long   DebugMon_Handler            /* Debug Monitor Handler */
+    .long   0                           /* Reserved              */
+    .long   PendSV_Handler              /* PendSV Handler        */
+    .long   SysTick_Handler             /* SysTick Handler       */
+
+    /* External interrupts */
+    .long     INT0_IRQHandler           // 0:  Interrupt pin 0
+    .long     INT1_IRQHandler           // 1:  Interrupt pin 1
+    .long     INT2_IRQHandler           // 2:  Interrupt pin 2
+    .long     INT3_IRQHandler           // 3:  Interrupt pin 3
+    .long     INT4_IRQHandler           // 4:  Interrupt pin 4
+    .long     INT5_IRQHandler           // 5:  Interrupt pin 5
+    .long     INT6_IRQHandler           // 6:  Interrupt pin 6
+    .long     INT7_IRQHandler           // 7:  Interrupt pin 7
+    .long     INT8_IRQHandler           // 8:  Interrupt pin 8
+    .long     INT9_IRQHandler           // 9:  Interrupt pin 9
+    .long     INTA_IRQHandler           // 10: Interrupt pin A
+    .long     INTB_IRQHandler           // 11: Interrupt pin B
+    .long     INTC_IRQHandler           // 12: Interrupt pin C
+    .long     INTD_IRQHandler           // 13: Interrupt pin D
+    .long     INTE_IRQHandler           // 14: Interrupt pin E
+    .long     INTF_IRQHandler           // 15: Interrupt pin F
+    .long     INTRX0_IRQHandler         // 16: Serial0 reception interrupt
+    .long     INTTX0_IRQHandler         // 17: Serial0 transmission interrupt
+    .long     INTRX1_IRQHandler         // 18: Serial1 reception interrupt
+    .long     INTTX1_IRQHandler         // 19: Serial1 transmission interrupt
+    .long     INTRX2_IRQHandler         // 20: Serial2 reception interrupt
+    .long     INTTX2_IRQHandler         // 21:  Serial2 transmission interrupt
+    .long     INTRX3_IRQHandler         // 22:  Serial3 reception interrupt
+    .long     INTTX3_IRQHandler         // 23:  Serial3 transmission interrupt
+    .long     INTUART0_IRQHandler       // 24:  Full UART0 transmission and reception interrupt
+    .long     INTUART1_IRQHandler       // 25:  Full UART1 transmission and reception interrupt
+    .long     INTI2C0_IRQHandler        // 26:  I2C0 transmission and reception interrupt
+    .long     INTI2C1_IRQHandler        // 27:  I2C1 transmission and reception interrupt
+    .long     INTI2C2_IRQHandler        // 28:  I2C2 transmission and reception interrupt
+    .long     INTSSP0_IRQHandler        // 29:  SSP(SPI) Serial interface 0 interrupt
+    .long     INTSSP1_IRQHandler        // 30:  SSP(SPI) Serial interface 1 interrupt
+    .long     INTSSP2_IRQHandler        // 31:  SSP(SPI) Serial interface 2 interrupt
+    .long     INTADHP_IRQHandler        // 32:  High Priority AD conversion interrupt
+    .long     INTADM0_IRQHandler        // 33:  AD conversion monitor interrupt 0
+    .long     INTADM1_IRQHandler        // 34:  AD conversion monitor interrupt 1
+    .long     INTAD_IRQHandler          // 35:  AD conversion interrupt
+    .long     INTAES_IRQHandler         // 36:  AES completion interrupt
+    .long     INTSHA_IRQHandler         // 37:  SHA completion interrupt
+    .long     INTMLA_IRQHandler         // 38:  MLA completion interrupt
+    .long     INTESG_IRQHandler         // 39:  ESG completion interrupt
+    .long     INTSNFCSEQ_IRQHandler     // 40:  SNFC command sequence end interrupt
+    .long     INTSNFCPRTAE_IRQHandler   // 41:  SNFC page lead RAM transfer end interrupt
+    .long     INTSNFCPRTCE_IRQHandler   // 42:  SNFC decode data RAM transmission end interrupt
+    .long     INTSNFCFAIL_IRQHandler    // 43:  SNFC decode fail interrupt
+    .long     0                         // 44:  Reserved1
+    .long     0                         // 45:  Reserved2
+    .long     0                         // 46:  Reserved3
+    .long     INTMTEMG0_IRQHandler      // 47:  MPT0 EMG interrupt
+    .long     INTMTPTB00_IRQHandler     // 48:  MPT0 compare match0/overflow,IGBT cycle interrupt
+    .long     INTMTPTB01_IRQHandler     // 49:  MPT0 compare match1/overflow,IGBT cycle interrupt
+    .long     INTMTCAP00_IRQHandler     // 50:  MPT0 input capture0 interrupt
+    .long     INTMTCAP01_IRQHandler     // 51:  MPT0 input capture1 interrupt
+    .long     INTMTEMG1_IRQHandler      // 52:  MPT1 EMG interrupt
+    .long     INTMTPTB10_IRQHandler     // 53:  MPT1 compare match0/overflow,IGBT cycle interrupt
+    .long     INTMTPTB11_IRQHandler     // 54:  MPT1 compare match1/overflow,IGBT cycle interrupt
+    .long     INTMTCAP10_IRQHandler     // 55:  MPT1 input capture0 interrupt
+    .long     INTMTCAP11_IRQHandler     // 56:  MPT1 input capture1 interrupt
+    .long     INTMTEMG2_IRQHandler      // 57:  MPT2 EMG interrupt
+    .long     INTMTPTB20_IRQHandler     // 58:  MPT2 compare match0/overflow,IGBT cycle interrupt
+    .long     INTMTTTB21_IRQHandler     // 59:  MPT2 compare match1/overflow,IGBT cycle interrupt
+    .long     INTMTCAP20_IRQHandler     // 60:  MPT2 input capture0 interrupt
+    .long     INTMTCAP21_IRQHandler     // 61:  MPT2 input capture1 interrupt
+    .long     INTMTEMG3_IRQHandler      // 62:  MPT3 EMG interrupt
+    .long     INTMTPTB30_IRQHandler     // 63:  MPT3 compare match0/overflow,IGBT cycle interrupt
+    .long     INTMTTTB31_IRQHandler     // 64:  MPT3 compare match1/overflow,IGBT cycle interrupt
+    .long     INTMTCAP30_IRQHandler     // 65:  MPT3 input capture0 interrupt
+    .long     INTMTCAP31_IRQHandler     // 66:  MPT3 input capture1 interrupt
+    .long     INTTB0_IRQHandler         // 67:  TMRB0 compare match detection interrupt
+    .long     INTCAP00_IRQHandler       // 68:  TMRB0 input capture 0 interrupt
+    .long     INTCAP01_IRQHandler       // 69:  TMRB0 input capture 1 interrupt
+    .long     INTTB1_IRQHandler         // 70:  TMRB1 compare match detection interrupt
+    .long     INTCAP10_IRQHandler       // 71:  TMRB1 input capture 0 interrupt
+    .long     INTCAP11_IRQHandler       // 72:  TMRB1 input capture 1 interrupt
+    .long     INTTB2_IRQHandler         // 73:  TMRB2 compare match detection interrupt
+    .long     INTCAP20_IRQHandler       // 74:  TMRB2 input capture 0 interrupt
+    .long     INTCAP21_IRQHandler       // 75:  TMRB2 input capture 1 interrupt
+    .long     INTTB3_IRQHandler         // 76:  TMRB3 compare match detection interrupt
+    .long     INTCAP30_IRQHandler       // 77:  TMRB3 input capture 0 interrupt
+    .long     INTCAP31_IRQHandler       // 78:  TMRB3 input capture 1 interrupt
+    .long     INTTB4_IRQHandler         // 79:  TMRB4 compare match detection interrupt
+    .long     INTCAP40_IRQHandler       // 80:  TMRB4 input capture 0 interrupt
+    .long     INTCAP41_IRQHandler       // 81:  TMRB4 input capture 1 interrupt
+    .long     INTTB5_IRQHandler         // 82:  TMRB5 compare match detection interrupt
+    .long     INTCAP50_IRQHandler       // 83:  TMRB5 input capture 0 interrupt
+    .long     INTCAP51_IRQHandler       // 84:  TMRB5 input capture 1 interrupt
+    .long     INTTB6_IRQHandler         // 85:  TMRB6 compare match detection interrupt
+    .long     INTCAP60_IRQHandler       // 86:  TMRB6 input capture 0 interrupt
+    .long     INTCAP61_IRQHandler       // 87:  TMRB6 input capture 1 interrupt
+    .long     INTTB7_IRQHandler         // 88:  TMRB7 compare match detection interrupt
+    .long     INTCAP70_IRQHandler       // 89:  TMRB7 input capture 0 interrupt
+    .long     INTCAP71_IRQHandler       // 90:  TMRB7 input capture 1 interrupt
+    .long     INTRTC_IRQHandler         // 91:  Real time clock interrupt
+    .long     INTDMAA_IRQHandler        // 92:  DMAC unitA transmission completion interrupt(ch4-31)
+    .long     INTDMAB_IRQHandler        // 93:  DMAC unitB transmission completion interrupt(ch24-31)
+    .long     INTDMAC_IRQHandler        // 94:  DMAC unitC transmission completion interrupt(ch12-31)
+    .long     INTDMACTC8_IRQHandler     // 95:  DMAC unitC transmission completion interrupt(ch8)
+    .long     INTDMACTC9_IRQHandler     // 96:  DMAC unitC transmission completion interrupt(ch9)
+    .long     INTDMACTC10_IRQHandler    // 97:  DMAC unitC transmission completion interrupt(ch10)
+    .long     INTDMACTC11_IRQHandler    // 98:  DMAC unitC transmission completion interrupt(ch11)
+    .long     INTDMAAERR_IRQHandler     // 99:  DMAC transmission error interrupt(unitA)
+    .long     INTDMABERR_IRQHandler     // 100: DMAC transmission error interrupt(unitB)
+    .long     INTDMACERR_IRQHandler     // 101: DMAC transmission error interrupt(unitC)
+    .long     INTFLRDY_IRQHandler       // 102: Flash Ready interrupt
+
+    .size    __Vectors, . - __Vectors
+
+    .text
+    .thumb
+    .thumb_func
+    .align    2
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+/*  Firstly it copies data from read only memory to RAM. There are two schemes
+ *  to copy. One can copy more than one sections. Another can only copy
+ *  one section.  The former scheme needs more instructions and read-only
+ *  data to implement than the latter.
+ *  Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes.  */
+
+#ifdef __STARTUP_COPY_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of triplets, each of which specify:
+ *    offset 0: LMA of start of a section to copy from
+ *    offset 4: VMA of start of a section to copy to
+ *    offset 8: size of the section to copy. Must be multiply of 4
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r4, =__copy_table_start__
+    ldr    r5, =__copy_table_end__
+
+.L_loop0:
+    cmp    r4, r5
+    bge    .L_loop0_done
+    ldr    r1, [r4]
+    ldr    r2, [r4, #4]
+    ldr    r3, [r4, #8]
+
+.L_loop0_0:
+    subs    r3, #4
+    ittt    ge
+    ldrge    r0, [r1, r3]
+    strge    r0, [r2, r3]
+    bge    .L_loop0_0
+
+    adds    r4, #12
+    b    .L_loop0
+
+.L_loop0_done:
+#else
+/*  Single section scheme.
+ *
+ *  The ranges of copy from/to are specified by following symbols
+ *    __etext: LMA of start of the section to copy from. Usually end of text
+ *    __data_start__: VMA of start of the section to copy to
+ *    __data_end__: VMA of end of the section to copy to
+ *
+ *  All addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+.L_loop1:
+    cmp    r2, r3
+    ittt    lt
+    ldrlt    r0, [r1], #4
+    strlt    r0, [r2], #4
+    blt    .L_loop1
+#endif /*__STARTUP_COPY_MULTIPLE */
+
+/*  This part of work usually is done in C library startup code. Otherwise,
+ *  define this macro to enable it in this startup.
+ *
+ *  There are two schemes too. One can clear multiple BSS sections. Another
+ *  can only clear one section. The former is more size expensive than the
+ *  latter.
+ *
+ *  Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
+ *  Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
+ */
+#ifdef __STARTUP_CLEAR_BSS_MULTIPLE
+/*  Multiple sections scheme.
+ *
+ *  Between symbol address __copy_table_start__ and __copy_table_end__,
+ *  there are array of tuples specifying:
+ *    offset 0: Start of a BSS section
+ *    offset 4: Size of this BSS section. Must be multiply of 4
+ */
+    ldr    r3, =__zero_table_start__
+    ldr    r4, =__zero_table_end__
+
+.L_loop2:
+    cmp    r3, r4
+    bge    .L_loop2_done
+    ldr    r1, [r3]
+    ldr    r2, [r3, #4]
+    movs    r0, 0
+
+.L_loop2_0:
+    subs    r2, #4
+    itt    ge
+    strge    r0, [r1, r2]
+    bge    .L_loop2_0
+
+    adds    r3, #8
+    b    .L_loop2
+.L_loop2_done:
+#elif defined (__STARTUP_CLEAR_BSS)
+/*  Single BSS section scheme.
+ *
+ *  The BSS section is specified by following symbols
+ *    __bss_start__: start of the BSS section.
+ *    __bss_end__: end of the BSS section.
+ *
+ *  Both addresses must be aligned to 4 bytes boundary.
+ */
+    ldr    r1, =__bss_start__
+    ldr    r2, =__bss_end__
+
+    movs    r0, 0
+.L_loop3:
+    cmp    r1, r2
+    itt    lt
+    strlt    r0, [r1], #4
+    blt    .L_loop3
+#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
+
+#ifndef __NO_SYSTEM_INIT
+    bl    SystemInit
+#endif
+
+#ifndef __START
+#define __START _start
+#endif
+    bl    __START
+
+    .pool
+    .size    Reset_Handler, . - Reset_Handler
+
+    .align    1
+    .thumb_func
+    .weak    Default_Handler
+    .type    Default_Handler, %function
+Default_Handler:
+    b    .
+    .size    Default_Handler, . - Default_Handler
+
+/*    Macro to define default handlers. Default handler
+ *    will be weak symbol and just dead loops. They can be
+ *    overwritten by other handlers */
+    .macro    def_irq_handler    handler_name
+    .weak    \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+    def_irq_handler     NMI_Handler
+    def_irq_handler     HardFault_Handler
+    def_irq_handler     MemManage_Handler
+    def_irq_handler     BusFault_Handler
+    def_irq_handler     UsageFault_Handler
+    def_irq_handler     SVC_Handler
+    def_irq_handler     DebugMon_Handler
+    def_irq_handler     PendSV_Handler
+    def_irq_handler     SysTick_Handler
+
+    def_irq_handler    INT0_IRQHandler
+    def_irq_handler    INT1_IRQHandler
+    def_irq_handler    INT2_IRQHandler
+    def_irq_handler    INT3_IRQHandler
+    def_irq_handler    INT4_IRQHandler
+    def_irq_handler    INT5_IRQHandler
+    def_irq_handler    INT6_IRQHandler
+    def_irq_handler    INT7_IRQHandler
+    def_irq_handler    INT8_IRQHandler
+    def_irq_handler    INT9_IRQHandler
+    def_irq_handler    INTA_IRQHandler
+    def_irq_handler    INTB_IRQHandler
+    def_irq_handler    INTC_IRQHandler
+    def_irq_handler    INTD_IRQHandler
+    def_irq_handler    INTE_IRQHandler
+    def_irq_handler    INTF_IRQHandler
+    def_irq_handler    INTRX0_IRQHandler
+    def_irq_handler    INTTX0_IRQHandler
+    def_irq_handler    INTRX1_IRQHandler
+    def_irq_handler    INTTX1_IRQHandler
+    def_irq_handler    INTRX2_IRQHandler
+    def_irq_handler    INTTX2_IRQHandler
+    def_irq_handler    INTRX3_IRQHandler
+    def_irq_handler    INTTX3_IRQHandler
+    def_irq_handler    INTUART0_IRQHandler
+    def_irq_handler    INTUART1_IRQHandler
+    def_irq_handler    INTI2C0_IRQHandler
+    def_irq_handler    INTI2C1_IRQHandler
+    def_irq_handler    INTI2C2_IRQHandler
+    def_irq_handler    INTSSP0_IRQHandler
+    def_irq_handler    INTSSP1_IRQHandler
+    def_irq_handler    INTSSP2_IRQHandler
+    def_irq_handler    INTADHP_IRQHandler
+    def_irq_handler    INTADM0_IRQHandler
+    def_irq_handler    INTADM1_IRQHandler
+    def_irq_handler    INTAD_IRQHandler
+    def_irq_handler    INTAES_IRQHandler
+    def_irq_handler    INTSHA_IRQHandler
+    def_irq_handler    INTMLA_IRQHandler
+    def_irq_handler    INTESG_IRQHandler
+    def_irq_handler    INTSNFCSEQ_IRQHandler
+    def_irq_handler    INTSNFCPRTAE_IRQHandler
+    def_irq_handler    INTSNFCPRTCE_IRQHandler
+    def_irq_handler    INTSNFCFAIL_IRQHandler
+    def_irq_handler    INTMTEMG0_IRQHandler
+    def_irq_handler    INTMTPTB00_IRQHandler
+    def_irq_handler    INTMTPTB01_IRQHandler
+    def_irq_handler    INTMTCAP00_IRQHandler
+    def_irq_handler    INTMTCAP01_IRQHandler
+    def_irq_handler    INTMTEMG1_IRQHandler
+    def_irq_handler    INTMTPTB10_IRQHandler
+    def_irq_handler    INTMTPTB11_IRQHandler
+    def_irq_handler    INTMTCAP10_IRQHandler
+    def_irq_handler    INTMTCAP11_IRQHandler
+    def_irq_handler    INTMTEMG2_IRQHandler
+    def_irq_handler    INTMTPTB20_IRQHandler
+    def_irq_handler    INTMTTTB21_IRQHandler
+    def_irq_handler    INTMTCAP20_IRQHandler
+    def_irq_handler    INTMTCAP21_IRQHandler
+    def_irq_handler    INTMTEMG3_IRQHandler
+    def_irq_handler    INTMTPTB30_IRQHandler
+    def_irq_handler    INTMTTTB31_IRQHandler
+    def_irq_handler    INTMTCAP30_IRQHandler
+    def_irq_handler    INTMTCAP31_IRQHandler
+    def_irq_handler    INTTB0_IRQHandler
+    def_irq_handler    INTCAP00_IRQHandler
+    def_irq_handler    INTCAP01_IRQHandler
+    def_irq_handler    INTTB1_IRQHandler
+    def_irq_handler    INTCAP10_IRQHandler
+    def_irq_handler    INTCAP11_IRQHandler
+    def_irq_handler    INTTB2_IRQHandler
+    def_irq_handler    INTCAP20_IRQHandler
+    def_irq_handler    INTCAP21_IRQHandler
+    def_irq_handler    INTTB3_IRQHandler
+    def_irq_handler    INTCAP30_IRQHandler
+    def_irq_handler    INTCAP31_IRQHandler
+    def_irq_handler    INTTB4_IRQHandler
+    def_irq_handler    INTCAP40_IRQHandler
+    def_irq_handler    INTCAP41_IRQHandler
+    def_irq_handler    INTTB5_IRQHandler
+    def_irq_handler    INTCAP50_IRQHandler
+    def_irq_handler    INTCAP51_IRQHandler
+    def_irq_handler    INTTB6_IRQHandler
+    def_irq_handler    INTCAP60_IRQHandler
+    def_irq_handler    INTCAP61_IRQHandler
+    def_irq_handler    INTTB7_IRQHandler
+    def_irq_handler    INTCAP70_IRQHandler
+    def_irq_handler    INTCAP71_IRQHandler
+    def_irq_handler    INTRTC_IRQHandler
+    def_irq_handler    INTDMAA_IRQHandler
+    def_irq_handler    INTDMAB_IRQHandler
+    def_irq_handler    INTDMAC_IRQHandler
+    def_irq_handler    INTDMACTC8_IRQHandler
+    def_irq_handler    INTDMACTC9_IRQHandler
+    def_irq_handler    INTDMACTC10_IRQHandler
+    def_irq_handler    INTDMACTC11_IRQHandler
+    def_irq_handler    INTDMAAERR_IRQHandler
+    def_irq_handler    INTDMABERR_IRQHandler
+    def_irq_handler    INTDMACERR_IRQHandler
+    def_irq_handler    INTFLRDY_IRQHandler
+
+    .end

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/TOOLCHAIN_GCC_ARM/tmpm46bf10fg.ld	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,207 @@
+/* Linker script for Toshiba TMPM46B */
+
+/* Linker script to configure memory regions. */
+
+#if !defined(MBED_APP_START)
+  #define MBED_APP_START 0x00000000
+#endif
+
+#if !defined(MBED_APP_SIZE)
+  #define MBED_APP_SIZE 0x100000
+#endif
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+  RAM (rwx) : ORIGIN = 0x200001E0, LENGTH = (512K - 0x1E0)
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a libnosys.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapBase
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ *   __Vectors_End
+ *   __Vectors_Size
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.vectors))
+		__Vectors_End = .;
+		__Vectors_Size = __Vectors_End - __Vectors;
+		__end__ = .;
+
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	/* To copy multiple ROM to RAM sections,
+	 * uncomment .copy.table section and,
+	 * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.copy.table :
+	{
+		. = ALIGN(4);
+		__copy_table_start__ = .;
+		LONG (__etext)
+		LONG (__data_start__)
+		LONG (__data_end__ - __data_start__)
+		LONG (__etext2)
+		LONG (__data2_start__)
+		LONG (__data2_end__ - __data2_start__)
+		__copy_table_end__ = .;
+	} > FLASH
+	*/
+
+	/* To clear multiple BSS sections,
+	 * uncomment .zero.table section and,
+	 * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+	/*
+	.zero.table :
+	{
+		. = ALIGN(4);
+		__zero_table_start__ = .;
+		LONG (__bss_start__)
+		LONG (__bss_end__ - __bss_start__)
+		LONG (__bss2_start__)
+		LONG (__bss2_end__ - __bss2_start__)
+		__zero_table_end__ = .;
+	} > FLASH
+	*/
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+        *(.ram_func*)
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		KEEP(*(.jcr*))
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (COPY):
+	{
+		__HeapBase = .;
+		__end__ = .;
+		end = __end__;
+		KEEP(*(.heap*))
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (COPY):
+	{
+		KEEP(*(.stack*))
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/TOOLCHAIN_IAR/startup_TMPM46B.S	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,714 @@
+;/**
+; *******************************************************************************
+; * @file    startup_TMPM46B.s
+; * @brief   CMSIS Cortex-M4 Core Device Startup File for the
+; *          TOSHIBA 'TMPM46B' Device Series
+; * @version V2.0.2.4
+; * @date    2015/03/31
+; * 
+; * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+; * 
+; * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+; *******************************************************************************
+; */
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; Cortex-M version
+;
+
+                MODULE  ?cstartup
+
+                ;; Forward declaration of sections.
+                SECTION CSTACK:DATA:NOROOT(3)
+
+                SECTION .intvec:CODE:NOROOT(2)
+
+                EXTERN  __iar_program_start
+                EXTERN  SystemInit
+                PUBLIC  __vector_table
+
+                DATA
+__vector_table  DCD     sfe(CSTACK)
+                DCD     Reset_Handler
+
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     MemManage_Handler         ; MPU Fault Handler
+                DCD     BusFault_Handler          ; Bus Fault Handler
+                DCD     UsageFault_Handler        ; Usage Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     DebugMon_Handler          ; Debug Monitor Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD     INT0_IRQHandler           ; 0:	Interrupt pin 0
+                DCD     INT1_IRQHandler           ; 1:	Interrupt pin 1
+                DCD     INT2_IRQHandler           ; 2:	Interrupt pin 2
+                DCD     INT3_IRQHandler           ; 3:	Interrupt pin 3
+                DCD     INT4_IRQHandler           ; 4:	Interrupt pin 4
+                DCD     INT5_IRQHandler           ; 5:	Interrupt pin 5
+                DCD     INT6_IRQHandler           ; 6:	Interrupt pin 6
+                DCD     INT7_IRQHandler           ; 7:	Interrupt pin 7
+                DCD     INT8_IRQHandler           ; 8:	Interrupt pin 8
+                DCD     INT9_IRQHandler           ; 9:	Interrupt pin 9
+                DCD     INTA_IRQHandler           ; 10:	Interrupt pin A
+                DCD     INTB_IRQHandler           ; 11:	Interrupt pin B
+                DCD     INTC_IRQHandler           ; 12:	Interrupt pin C
+                DCD     INTD_IRQHandler           ; 13:	Interrupt pin D
+                DCD     INTE_IRQHandler           ; 14:	Interrupt pin E
+                DCD     INTF_IRQHandler           ; 15:	Interrupt pin F
+                DCD     INTRX0_IRQHandler         ; 16:	Serial0 reception interrupt
+                DCD     INTTX0_IRQHandler         ; 17:	Serial0 transmission interrupt
+                DCD     INTRX1_IRQHandler         ; 18:	Serial1 reception interrupt
+                DCD     INTTX1_IRQHandler         ; 19:	Serial1 transmission interrupt
+                DCD     INTRX2_IRQHandler         ; 20:	Serial2 reception interrupt
+                DCD     INTTX2_IRQHandler         ; 21:	Serial2 transmission interrupt
+                DCD     INTRX3_IRQHandler         ; 22:	Serial3 reception interrupt
+                DCD     INTTX3_IRQHandler         ; 23:	Serial3 transmission interrupt
+                DCD     INTUART0_IRQHandler       ; 24:	Full UART0 transmission and reception interrupt
+                DCD     INTUART1_IRQHandler       ; 25:	Full UART1 transmission and reception interrupt
+                DCD     INTI2C0_IRQHandler        ; 26:	I2C0 transmission and reception interrupt
+                DCD     INTI2C1_IRQHandler        ; 27:	I2C1 transmission and reception interrupt
+                DCD     INTI2C2_IRQHandler        ; 28:	I2C2 transmission and reception interrupt
+                DCD     INTSSP0_IRQHandler        ; 29:	SSP(SPI) Serial interface 0 interrupt 
+                DCD     INTSSP1_IRQHandler        ; 30:	SSP(SPI) Serial interface 1 interrupt 
+                DCD     INTSSP2_IRQHandler        ; 31:	SSP(SPI) Serial interface 2 interrupt 
+                DCD     INTADHP_IRQHandler        ; 32:	High Priority AD conversion interrupt
+                DCD     INTADM0_IRQHandler        ; 33:	AD conversion monitor interrupt 0
+                DCD     INTADM1_IRQHandler        ; 34:	AD conversion monitor interrupt 1
+                DCD     INTAD_IRQHandler          ; 35:	AD conversion interrupt 
+                DCD     INTAES_IRQHandler         ; 36:	AES completion interrupt
+                DCD     INTSHA_IRQHandler         ; 37:	SHA completion interrupt
+                DCD     INTMLA_IRQHandler         ; 38:	MLA completion interrupt
+                DCD     INTESG_IRQHandler         ; 39:	ESG completion interrupt
+                DCD     INTSNFCSEQ_IRQHandler     ; 40:	SNFC command sequence end interrupt
+                DCD     INTSNFCPRTAE_IRQHandler   ; 41:	SNFC page lead RAM transfer end interrupt
+                DCD     INTSNFCPRTCE_IRQHandler   ; 42:	SNFC decode data RAM transmission end interrupt
+                DCD     INTSNFCFAIL_IRQHandler    ; 43:	SNFC decode fail interrupt
+                DCD     0                         ; 44:	Reserved
+                DCD     0                         ; 45:	Reserved
+                DCD     0                         ; 46:	Reserved
+                DCD     INTMTEMG0_IRQHandler      ; 47:	MPT0 EMG interrupt
+                DCD     INTMTPTB00_IRQHandler     ; 48:	MPT0 compare match0/overflow,IGBT cycle interrupt
+                DCD     INTMTPTB01_IRQHandler     ; 49:	MPT0 compare match1/overflow,IGBT cycle interrupt
+                DCD     INTMTCAP00_IRQHandler     ; 50:	MPT0 input capture0 interrupt
+                DCD     INTMTCAP01_IRQHandler     ; 51:	MPT0 input capture1 interrupt
+                DCD     INTMTEMG1_IRQHandler      ; 52:	MPT1 EMG interrupt
+                DCD     INTMTPTB10_IRQHandler     ; 53:	MPT1 compare match0/overflow,IGBT cycle interrupt
+                DCD     INTMTPTB11_IRQHandler     ; 54:	MPT1 compare match1/overflow,IGBT cycle interrupt
+                DCD     INTMTCAP10_IRQHandler     ; 55:	MPT1 input capture0 interrupt
+                DCD     INTMTCAP11_IRQHandler     ; 56:	MPT1 input capture1 interrupt
+                DCD     INTMTEMG2_IRQHandler      ; 57:	MPT2 EMG interrupt
+                DCD     INTMTPTB20_IRQHandler     ; 58:	MPT2 compare match0/overflow,IGBT cycle interrupt
+                DCD     INTMTTTB21_IRQHandler     ; 59:	MPT2 compare match1/overflow,IGBT cycle interrupt
+                DCD     INTMTCAP20_IRQHandler     ; 60:	MPT2 input capture0 interrupt
+                DCD     INTMTCAP21_IRQHandler     ; 61:	MPT2 input capture1 interrupt
+                DCD     INTMTEMG3_IRQHandler      ; 62:	MPT3 EMG interrupt
+                DCD     INTMTPTB30_IRQHandler     ; 63:	MPT3 compare match0/overflow,IGBT cycle interrupt
+                DCD     INTMTTTB31_IRQHandler     ; 64:	MPT3 compare match1/overflow,IGBT cycle interrupt
+                DCD     INTMTCAP30_IRQHandler     ; 65:	MPT3 input capture0 interrupt
+                DCD     INTMTCAP31_IRQHandler     ; 66:	MPT3 input capture1 interrupt
+                DCD     INTTB0_IRQHandler         ; 67:	TMRB0 compare match detection interrupt
+                DCD     INTCAP00_IRQHandler       ; 68:	TMRB0 input capture 0 interrupt
+                DCD     INTCAP01_IRQHandler       ; 69:	TMRB0 input capture 1 interrupt
+                DCD     INTTB1_IRQHandler         ; 70:	TMRB1 compare match detection interrupt
+                DCD     INTCAP10_IRQHandler       ; 71:	TMRB1 input capture 0 interrupt
+                DCD     INTCAP11_IRQHandler       ; 72:	TMRB1 input capture 1 interrupt
+                DCD     INTTB2_IRQHandler         ; 73:	TMRB2 compare match detection interrupt
+                DCD     INTCAP20_IRQHandler       ; 74:	TMRB2 input capture 0 interrupt
+                DCD     INTCAP21_IRQHandler       ; 75:	TMRB2 input capture 1 interrupt
+                DCD     INTTB3_IRQHandler         ; 76:	TMRB3 compare match detection interrupt
+                DCD     INTCAP30_IRQHandler       ; 77:	TMRB3 input capture 0 interrupt
+                DCD     INTCAP31_IRQHandler       ; 78:	TMRB3 input capture 1 interrupt
+                DCD     INTTB4_IRQHandler         ; 79:	TMRB4 compare match detection interrupt
+                DCD     INTCAP40_IRQHandler       ; 80:	TMRB4 input capture 0 interrupt
+                DCD     INTCAP41_IRQHandler       ; 81:	TMRB4 input capture 1 interrupt
+                DCD     INTTB5_IRQHandler         ; 82:	TMRB5 compare match detection interrupt
+                DCD     INTCAP50_IRQHandler       ; 83:	TMRB5 input capture 0 interrupt
+                DCD     INTCAP51_IRQHandler       ; 84:	TMRB5 input capture 1 interrupt
+                DCD     INTTB6_IRQHandler         ; 85:	TMRB6 compare match detection interrupt
+                DCD     INTCAP60_IRQHandler       ; 86:	TMRB6 input capture 0 interrupt
+                DCD     INTCAP61_IRQHandler       ; 87:	TMRB6 input capture 1 interrupt
+                DCD     INTTB7_IRQHandler         ; 88:	TMRB7 compare match detection interrupt
+                DCD     INTCAP70_IRQHandler       ; 89:	TMRB7 input capture 0 interrupt
+                DCD     INTCAP71_IRQHandler       ; 90:	TMRB7 input capture 1 interrupt
+                DCD     INTRTC_IRQHandler         ; 91:	Real time clock interrupt
+                DCD     INTDMAA_IRQHandler        ; 92:	DMAC unitA transmission completion interrupt(ch4-31)
+                DCD     INTDMAB_IRQHandler        ; 93:	DMAC unitB transmission completion interrupt(ch24-31)
+                DCD     INTDMAC_IRQHandler        ; 94:	DMAC unitC transmission completion interrupt(ch12-31)
+                DCD     INTDMACTC8_IRQHandler     ; 95:	DMAC unitC transmission completion interrupt(ch8)
+                DCD     INTDMACTC9_IRQHandler     ; 96:	DMAC unitC transmission completion interrupt(ch9)
+                DCD     INTDMACTC10_IRQHandler    ; 97:	DMAC unitC transmission completion interrupt(ch10)
+                DCD     INTDMACTC11_IRQHandler    ; 98:	DMAC unitC transmission completion interrupt(ch11)
+                DCD     INTDMAAERR_IRQHandler     ; 99:	DMAC transmission error interrupt(unitA)
+                DCD     INTDMABERR_IRQHandler     ; 100:	DMAC transmission error interrupt(unitB)
+                DCD     INTDMACERR_IRQHandler     ; 101:	DMAC transmission error interrupt(unitC)
+                DCD     INTFLRDY_IRQHandler       ; 102:	Flash Ready interrupt
+                THUMB
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+                PUBWEAK Reset_Handler
+                SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__iar_program_start
+                BX      R0
+
+                PUBWEAK NMI_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+                B       NMI_Handler
+
+                PUBWEAK HardFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+                B       HardFault_Handler
+
+                PUBWEAK MemManage_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+MemManage_Handler
+                B       MemManage_Handler
+
+                PUBWEAK BusFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+BusFault_Handler
+                B       BusFault_Handler
+
+                PUBWEAK UsageFault_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+UsageFault_Handler
+                B       UsageFault_Handler
+
+                PUBWEAK SVC_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+                B       SVC_Handler
+
+                PUBWEAK DebugMon_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+DebugMon_Handler
+                B       DebugMon_Handler
+
+                PUBWEAK PendSV_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+                B       PendSV_Handler
+
+                PUBWEAK SysTick_Handler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+                B       SysTick_Handler
+
+                PUBWEAK INT0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT0_IRQHandler
+                B       INT0_IRQHandler
+
+                PUBWEAK INT1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT1_IRQHandler
+                B       INT1_IRQHandler
+
+                PUBWEAK INT2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT2_IRQHandler
+                B       INT2_IRQHandler
+
+                PUBWEAK INT3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT3_IRQHandler
+                B       INT3_IRQHandler
+
+                PUBWEAK INT4_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT4_IRQHandler
+                B       INT4_IRQHandler
+
+                PUBWEAK INT5_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT5_IRQHandler
+                B       INT5_IRQHandler
+
+                PUBWEAK INT6_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT6_IRQHandler
+                B       INT6_IRQHandler
+
+                PUBWEAK INT7_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT7_IRQHandler
+                B       INT7_IRQHandler
+
+                PUBWEAK INT8_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT8_IRQHandler
+                B       INT8_IRQHandler
+
+                PUBWEAK INT9_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INT9_IRQHandler
+                B       INT9_IRQHandler
+
+                PUBWEAK INTA_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTA_IRQHandler
+                B       INTA_IRQHandler
+
+                PUBWEAK INTB_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTB_IRQHandler
+                B       INTB_IRQHandler
+
+                PUBWEAK INTC_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTC_IRQHandler
+                B       INTC_IRQHandler
+
+                PUBWEAK INTD_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTD_IRQHandler
+                B       INTD_IRQHandler
+
+                PUBWEAK INTE_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTE_IRQHandler
+                B       INTE_IRQHandler
+
+                PUBWEAK INTF_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTF_IRQHandler
+                B       INTF_IRQHandler
+
+                PUBWEAK INTRX0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTRX0_IRQHandler
+                B       INTRX0_IRQHandler
+
+                PUBWEAK INTTX0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTX0_IRQHandler
+                B       INTTX0_IRQHandler
+
+                PUBWEAK INTRX1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTRX1_IRQHandler
+                B       INTRX1_IRQHandler
+
+                PUBWEAK INTTX1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTX1_IRQHandler
+                B       INTTX1_IRQHandler
+
+                PUBWEAK INTRX2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTRX2_IRQHandler
+                B       INTRX2_IRQHandler
+
+                PUBWEAK INTTX2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTX2_IRQHandler
+                B       INTTX2_IRQHandler
+
+                PUBWEAK INTRX3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTRX3_IRQHandler
+                B       INTRX3_IRQHandler
+
+                PUBWEAK INTTX3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTX3_IRQHandler
+                B       INTTX3_IRQHandler
+
+                PUBWEAK INTUART0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTUART0_IRQHandler
+                B       INTUART0_IRQHandler
+
+                PUBWEAK INTUART1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTUART1_IRQHandler
+                B       INTUART1_IRQHandler
+
+                PUBWEAK INTI2C0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTI2C0_IRQHandler
+                B       INTI2C0_IRQHandler
+
+                PUBWEAK INTI2C1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTI2C1_IRQHandler
+                B       INTI2C1_IRQHandler
+
+                PUBWEAK INTI2C2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTI2C2_IRQHandler
+                B       INTI2C2_IRQHandler
+
+                PUBWEAK INTSSP0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSSP0_IRQHandler
+                B       INTSSP0_IRQHandler
+
+                PUBWEAK INTSSP1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSSP1_IRQHandler
+                B       INTSSP1_IRQHandler
+
+                PUBWEAK INTSSP2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSSP2_IRQHandler
+                B       INTSSP2_IRQHandler
+
+                PUBWEAK INTADHP_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTADHP_IRQHandler
+                B       INTADHP_IRQHandler
+
+                PUBWEAK INTADM0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTADM0_IRQHandler
+                B       INTADM0_IRQHandler
+
+                PUBWEAK INTADM1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTADM1_IRQHandler
+                B       INTADM1_IRQHandler
+
+                PUBWEAK INTAD_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTAD_IRQHandler
+                B       INTAD_IRQHandler
+
+                PUBWEAK INTAES_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTAES_IRQHandler
+                B       INTAES_IRQHandler
+
+                PUBWEAK INTSHA_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSHA_IRQHandler
+                B       INTSHA_IRQHandler
+
+                PUBWEAK INTMLA_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMLA_IRQHandler
+                B       INTMLA_IRQHandler
+
+                PUBWEAK INTESG_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTESG_IRQHandler
+                B       INTESG_IRQHandler
+
+                PUBWEAK INTSNFCSEQ_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSNFCSEQ_IRQHandler
+                B       INTSNFCSEQ_IRQHandler
+
+                PUBWEAK INTSNFCPRTAE_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSNFCPRTAE_IRQHandler
+                B       INTSNFCPRTAE_IRQHandler
+
+                PUBWEAK INTSNFCPRTCE_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSNFCPRTCE_IRQHandler
+                B       INTSNFCPRTCE_IRQHandler
+
+                PUBWEAK INTSNFCFAIL_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTSNFCFAIL_IRQHandler
+                B       INTSNFCFAIL_IRQHandler
+
+                PUBWEAK INTMTEMG0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTEMG0_IRQHandler
+                B       INTMTEMG0_IRQHandler
+
+                PUBWEAK INTMTPTB00_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTPTB00_IRQHandler
+                B       INTMTPTB00_IRQHandler
+
+                PUBWEAK INTMTPTB01_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTPTB01_IRQHandler
+                B       INTMTPTB01_IRQHandler
+
+                PUBWEAK INTMTCAP00_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTCAP00_IRQHandler
+                B       INTMTCAP00_IRQHandler
+
+                PUBWEAK INTMTCAP01_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTCAP01_IRQHandler
+                B       INTMTCAP01_IRQHandler
+
+                PUBWEAK INTMTEMG1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTEMG1_IRQHandler
+                B       INTMTEMG1_IRQHandler
+
+                PUBWEAK INTMTPTB10_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTPTB10_IRQHandler
+                B       INTMTPTB10_IRQHandler
+
+                PUBWEAK INTMTPTB11_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTPTB11_IRQHandler
+                B       INTMTPTB11_IRQHandler
+
+                PUBWEAK INTMTCAP10_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTCAP10_IRQHandler
+                B       INTMTCAP10_IRQHandler
+
+                PUBWEAK INTMTCAP11_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTCAP11_IRQHandler
+                B       INTMTCAP11_IRQHandler
+
+                PUBWEAK INTMTEMG2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTEMG2_IRQHandler
+                B       INTMTEMG2_IRQHandler
+
+                PUBWEAK INTMTPTB20_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTPTB20_IRQHandler
+                B       INTMTPTB20_IRQHandler
+
+                PUBWEAK INTMTTTB21_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTTTB21_IRQHandler
+                B       INTMTTTB21_IRQHandler
+
+                PUBWEAK INTMTCAP20_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTCAP20_IRQHandler
+                B       INTMTCAP20_IRQHandler
+
+                PUBWEAK INTMTCAP21_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTCAP21_IRQHandler
+                B       INTMTCAP21_IRQHandler
+
+                PUBWEAK INTMTEMG3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTEMG3_IRQHandler
+                B       INTMTEMG3_IRQHandler
+
+                PUBWEAK INTMTPTB30_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTPTB30_IRQHandler
+                B       INTMTPTB30_IRQHandler
+
+                PUBWEAK INTMTTTB31_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTTTB31_IRQHandler
+                B       INTMTTTB31_IRQHandler
+
+                PUBWEAK INTMTCAP30_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTCAP30_IRQHandler
+                B       INTMTCAP30_IRQHandler
+
+                PUBWEAK INTMTCAP31_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTMTCAP31_IRQHandler
+                B       INTMTCAP31_IRQHandler
+
+                PUBWEAK INTTB0_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB0_IRQHandler
+                B       INTTB0_IRQHandler
+
+                PUBWEAK INTCAP00_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP00_IRQHandler
+                B       INTCAP00_IRQHandler
+
+                PUBWEAK INTCAP01_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP01_IRQHandler
+                B       INTCAP01_IRQHandler
+
+                PUBWEAK INTTB1_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB1_IRQHandler
+                B       INTTB1_IRQHandler
+
+                PUBWEAK INTCAP10_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP10_IRQHandler
+                B       INTCAP10_IRQHandler
+
+                PUBWEAK INTCAP11_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP11_IRQHandler
+                B       INTCAP11_IRQHandler
+
+                PUBWEAK INTTB2_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB2_IRQHandler
+                B       INTTB2_IRQHandler
+
+                PUBWEAK INTCAP20_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP20_IRQHandler
+                B       INTCAP20_IRQHandler
+
+                PUBWEAK INTCAP21_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP21_IRQHandler
+                B       INTCAP21_IRQHandler
+
+                PUBWEAK INTTB3_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB3_IRQHandler
+                B       INTTB3_IRQHandler
+
+                PUBWEAK INTCAP30_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP30_IRQHandler
+                B       INTCAP30_IRQHandler
+
+                PUBWEAK INTCAP31_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP31_IRQHandler
+                B       INTCAP31_IRQHandler
+
+                PUBWEAK INTTB4_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB4_IRQHandler
+                B       INTTB4_IRQHandler
+
+                PUBWEAK INTCAP40_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP40_IRQHandler
+                B       INTCAP40_IRQHandler
+
+                PUBWEAK INTCAP41_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP41_IRQHandler
+                B       INTCAP41_IRQHandler
+
+                PUBWEAK INTTB5_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB5_IRQHandler
+                B       INTTB5_IRQHandler
+
+                PUBWEAK INTCAP50_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP50_IRQHandler
+                B       INTCAP50_IRQHandler
+
+                PUBWEAK INTCAP51_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP51_IRQHandler
+                B       INTCAP51_IRQHandler
+
+                PUBWEAK INTTB6_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB6_IRQHandler
+                B       INTTB6_IRQHandler
+
+                PUBWEAK INTCAP60_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP60_IRQHandler
+                B       INTCAP60_IRQHandler
+
+                PUBWEAK INTCAP61_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP61_IRQHandler
+                B       INTCAP61_IRQHandler
+
+                PUBWEAK INTTB7_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTTB7_IRQHandler
+                B       INTTB7_IRQHandler
+
+                PUBWEAK INTCAP70_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP70_IRQHandler
+                B       INTCAP70_IRQHandler
+
+                PUBWEAK INTCAP71_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTCAP71_IRQHandler
+                B       INTCAP71_IRQHandler
+
+                PUBWEAK INTRTC_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTRTC_IRQHandler
+                B       INTRTC_IRQHandler
+
+                PUBWEAK INTDMAA_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMAA_IRQHandler
+                B       INTDMAA_IRQHandler
+
+                PUBWEAK INTDMAB_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMAB_IRQHandler
+                B       INTDMAB_IRQHandler
+
+                PUBWEAK INTDMAC_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMAC_IRQHandler
+                B       INTDMAC_IRQHandler
+
+                PUBWEAK INTDMACTC8_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMACTC8_IRQHandler
+                B       INTDMACTC8_IRQHandler
+
+                PUBWEAK INTDMACTC9_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMACTC9_IRQHandler
+                B       INTDMACTC9_IRQHandler
+
+                PUBWEAK INTDMACTC10_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMACTC10_IRQHandler
+                B       INTDMACTC10_IRQHandler
+
+                PUBWEAK INTDMACTC11_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMACTC11_IRQHandler
+                B       INTDMACTC11_IRQHandler
+
+                PUBWEAK INTDMAAERR_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMAAERR_IRQHandler
+                B       INTDMAAERR_IRQHandler
+
+                PUBWEAK INTDMABERR_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMABERR_IRQHandler
+                B       INTDMABERR_IRQHandler
+
+                PUBWEAK INTDMACERR_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTDMACERR_IRQHandler
+                B       INTDMACERR_IRQHandler
+
+                PUBWEAK INTFLRDY_IRQHandler
+                SECTION .text:CODE:REORDER:NOROOT(1)
+INTFLRDY_IRQHandler
+                B       INTFLRDY_IRQHandler
+
+                END

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/TOOLCHAIN_IAR/tmpm46bf10fg.icf	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,40 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+if (!isdefinedsymbol(MBED_APP_START)) { define symbol MBED_APP_START = 0x00000000; }
+if (!isdefinedsymbol(MBED_APP_SIZE)) { define symbol MBED_APP_SIZE = 0x100000; }
+define symbol __ICFEDIT_intvec_start__ = MBED_APP_START;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = MBED_APP_START;
+define symbol __ICFEDIT_region_ROM_end__     = MBED_APP_START + MBED_APP_SIZE - 1;
+define symbol __ICFEDIT_region_RAM_start__   = 0x200001E0;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2006FFFF;
+define symbol __ICFEDIT_region_BRAM_start__  = 0x20070000;
+define symbol __ICFEDIT_region_BRAM_end__    = 0x200807FF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__   = 0x10000;
+define symbol __ICFEDIT_size_heap__     = 0x20000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+define block FLASH_CODE_ROM  {section FLASH_ROM_init object flash_api.o, section .text_init object tmpm46b_fc.o}; 
+define block FLASH_CODE_RAM  {section FLASH_ROM object flash_api.o, section .text object tmpm46b_fc.o};
+
+initialize by copy { readwrite };
+initialize manually { section FLASH_ROM object flash_api.o, section .text object tmpm46b_fc.o};
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place at address mem: 0x400 { block FLASH_CODE_ROM };
+place at address mem: 0x20070000 { block FLASH_CODE_RAM };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+place in ROM_region   { readonly };

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/cmsis.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,12 @@
+/* mbed Microcontroller Library - CMSIS for TMPM46B
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in TMPM46B specifics
+ */
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "TMPM46B.h"
+#include "cmsis_nvic.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/cmsis_nvic.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library - cmsis_nvic for TMPM46B
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+
+#if defined(__ICCARM__)
+    #pragma section=".intvec"
+    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)__section_begin(".intvec"))
+#elif defined(__CC_ARM)
+    extern uint32_t Load$$LR$$LR_IROM1$$Base[];
+    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)Load$$LR$$LR_IROM1$$Base)
+#elif defined(__GNUC__)
+    extern uint32_t vectors[];
+    #define NVIC_FLASH_VECTOR_ADDRESS   ((uint32_t)vectors)
+#else
+    #error "Flash vector address not set for this toolchain"
+#endif
+
+
+#define NVIC_NUM_VECTORS             (119)
+#define NVIC_RAM_VECTOR_ADDRESS      0x20000000    // Location of vectors in RAM
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/system_TMPM46B.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,387 @@
+/**
+ *******************************************************************************
+ * @file    system_TMPM46B.c
+ * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Source File for the
+ *          TOSHIBA 'TMPM46B' Device Series
+ * @version V2.0.2.4
+ * @date    2018/3/15
+ *
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ *
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ *******************************************************************************
+ */
+
+#include "TMPM46B.h"
+
+/*-------- <<< Start of configuration section >>> ----------------------------*/
+
+/* Watchdog Timer (WD) Configuration */
+#define WD_SETUP                (1U)
+#define WDMOD_Val               (0x00000000UL)
+#define WDCR_Val                (0x000000B1UL)
+
+/* Clock Generator (CG) Configuration */
+#define CLOCK_SETUP             (1U)
+#define SYSCR_Val               (0x00010000UL)
+#define OSCCR_Val               (0x00020501UL) /* OSCCR<OSCSEL> = 1, OSCCR<XEN2> = 0, OSCCR<XEN1> = 1, <HOSCON> = 1 */
+
+#define STBYCR_Val              (0x00000003UL)
+
+#define CG_8M_MUL_4_FPLL        (0x00006A0FUL<<1U)
+#define CG_8M_MUL_5_FPLL        (0x00006A13UL<<1U)
+#define CG_8M_MUL_6_FPLL        (0x00006917UL<<1U)
+#define CG_8M_MUL_10_FPLL       (0x00006A26UL<<1U)
+#define CG_8M_MUL_12_FPLL       (0x0000692EUL<<1U)
+
+#define CG_10M_MUL_4_FPLL       (0x00006A0FUL<<1U)
+#define CG_10M_MUL_5_FPLL       (0x00006A13UL<<1U)
+#define CG_10M_MUL_6_FPLL       (0x00006917UL<<1U)
+#define CG_10M_MUL_8_FPLL       (0x00006A1EUL<<1U)
+#define CG_10M_MUL_10_FPLL      (0x00006A26UL<<1U)
+#define CG_10M_MUL_12_FPLL      (0x0000692EUL<<1U)
+
+#define CG_12M_MUL_4_FPLL       (0x00006A0FUL<<1U)
+#define CG_12M_MUL_5_FPLL       (0x00006A13UL<<1U)
+#define CG_12M_MUL_8_FPLL       (0x00006A1EUL<<1U)
+#define CG_12M_MUL_10_FPLL      (0x00006A26UL<<1U)
+
+#define CG_16M_MUL_4_FPLL       (0x00006A0FUL<<1U)
+
+#define CG_PLLSEL_PLLON_SET                  ((uint32_t)0x00010000)
+#define CG_PLLSEL_PLLON_CLEAR                ((uint32_t)0xFFFEFFFF)
+#define CG_PLLSEL_PLLSEL_SET                 ((uint32_t)0x00020000)
+#define CG_PLLSEL_PLLST_MASK                 ((uint32_t)0x00040000)
+
+#define CG_OSCCR_XEN1_SET                    ((uint32_t)0x00000001)
+#define CG_OSCCR_XEN2_CLEAR                  ((uint32_t)0xFFFFFFFD)
+#define CG_OSCCR_HOSCON_SET                  ((uint32_t)0x00000400)
+#define CG_OSCCR_OSCSEL_SET                  ((uint32_t)0x00000100)
+#define CG_WUP_START_SET                     ((uint32_t)0x00004000)
+#define CG_WUEF_VALUE_MASK                   ((uint32_t)0x00008000)
+#define CG_OSCCR_WUPSEL2_SET                 ((uint32_t)0x00020000)
+#define CG_OSCCR_WUPSEL1_CLEAR               ((uint32_t)0xFFFEFFFF)
+#define CG_OSCCR_OSCF_MASK                   ((uint32_t)0x00000200)
+
+#define WD_MOD_WDTE_SET                      ((uint32_t)0x00000080)
+
+//#define PLLSEL_Ready            CG_16M_MUL_5_FPLL     /* -M46BSTK */
+#define PLLSEL_Ready              CG_12M_MUL_5_FPLL     /* +M46BSTK */
+
+#define PLLSEL_Val              (PLLSEL_Ready|0x00030000UL)
+#define PLLSEL_MASK             (0x0000FFFEUL)
+
+/*-------- <<< End of configuration section >>> ------------------------------*/
+
+/*-------- DEFINES -----------------------------------------------------------*/
+/* Define clocks */
+#define OSC_8M                  ( 8000000UL)
+#define OSC_10M                 (10000000UL)
+#define OSC_12M                 (12000000UL)
+#define OSC_16M                 (16000000UL)
+//#define EXTALH                  OSC_16M     /* External high-speed oscillator freq */     /* -M46BSTK */
+#define EXTALH                  OSC_12M     /* External high-speed oscillator freq */       /* +M46BSTK */
+#define XTALH                   OSC_10M     /* Internal high-speed oscillator freq */
+
+/* Configure Warm-up time */
+#define HZ_1M                  (1000000UL)
+#define WU_TIME_EXT            (5000UL)          /* warm-up time for EXT is 5ms   */
+#define WU_TIME_PLL            (100UL)           /* warm-up time for PLL is 100us */
+#define OSCCR_WUPT_MASK        (0x000FFFFFUL)
+#define OSCCR_WUPT_EXT         ((uint32_t)(((uint64_t)WU_TIME_EXT * EXTALH / HZ_1M / 16UL) << 20U)) /* OSCCR<WUPT11:0> = warm-up time(us) * EXTALH / 16 */
+#define OSCCR_WUPT_PLL         ((WU_TIME_PLL * EXTALH / HZ_1M /16UL) << 20U)
+
+#if (CLOCK_SETUP)               /* Clock(external) Setup */
+/* Determine core clock frequency according to settings */
+/* System clock is high-speed clock*/
+#if (OSCCR_Val & (1U<<8U))
+  #define CORE_TALH (EXTALH)
+#else
+  #define CORE_TALH (XTALH)
+#endif
+
+#if ((PLLSEL_Val & (1U<<16U)) && (PLLSEL_Val & (1U<<17U)))   /* If PLL selected and enabled */
+  #if (CORE_TALH == OSC_8M)                             /* If input is 8MHz */
+    #if ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_4_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 4U )            /* output clock is 32MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_5_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 5U )           /* output clock is 40MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_6_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 6U )           /* output clock is 48MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_8_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 8U )           /* output clock is 64MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_10_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 10U )           /* output clock is 80MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_8M_MUL_12_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 12U )           /* output clock is 96MHz */
+    #else                                               /* fc -> reserved */
+      #define __CORE_CLK   (0U)
+    #endif                                              /* End input is 8MHz */
+  #elif (CORE_TALH == OSC_10M)                       /* If input is 10MHz */
+    #if ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_4_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 4U )            /* output clock is 40MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_5_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 5U )           /* output clock is 50MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_6_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 6U )           /* output clock is 60MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_8_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 8U )           /* output clock is 80MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_10_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 10U )           /* output clock is 100MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == (CG_10M_MUL_12_FPLL))
+      #define __CORE_CLK   (CORE_TALH * 12U )           /* output clock is 120MHz */
+    #else                                               /* fc -> reserved */
+      #define __CORE_CLK   (0U)
+    #endif                                              /* End input is 10MHz */
+  #elif (CORE_TALH == OSC_12M)                       /* If input is 12MHz */
+    #if ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_4_FPLL)
+      #define __CORE_CLK   (CORE_TALH * 4U )            /* output clock is 48MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_5_FPLL)
+      #define __CORE_CLK   (CORE_TALH * 5U )            /* output clock is 60MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_6_FPLL)
+      #define __CORE_CLK   (CORE_TALH * 6U )            /* output clock is 72MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_8_FPLL)
+      #define __CORE_CLK   (CORE_TALH * 8U )            /* output clock is 96MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == CG_12M_MUL_10_FPLL)
+      #define __CORE_CLK   (CORE_TALH * 10U )            /* output clock is 120MHz */
+    #else                                               /* fc -> reserved */
+      #define __CORE_CLK   (0U)
+    #endif                                              /* End input is 12MHz */
+  #elif (CORE_TALH == OSC_16M)                       /* If input is 16MHz */
+    #if ((PLLSEL_Val & PLLSEL_MASK) == CG_16M_MUL_4_FPLL)
+      #define __CORE_CLK   (CORE_TALH * 4U )            /* output clock is 64MHz */
+    #elif ((PLLSEL_Val & PLLSEL_MASK) == CG_16M_MUL_5_FPLL)
+      #define __CORE_CLK   (CORE_TALH * 5U )            /* output clock is 80MHz */
+    #else                                               /* fc -> reserved        */
+      #define __CORE_CLK   (0U)
+    #endif                                              /* End input is 16MHz    */
+  #else                                                 /* input clock not known */
+    #define __CORE_CLK   (0U)
+    #error "Core Oscillator Frequency invalid!"
+  #endif                                                /* End switch input clock */
+#else
+  #define __CORE_CLK   (CORE_TALH)
+#endif
+
+#if   ((SYSCR_Val & 7U) == 0U)                          /* Gear -> fc             */
+  #define __CORE_SYS   (__CORE_CLK)
+#elif ((SYSCR_Val & 7U) == 4U)                          /* Gear -> fc/2           */
+  #define __CORE_SYS   (__CORE_CLK / 2U)
+#elif ((SYSCR_Val & 7U) == 5U)                          /* Gear -> fc/4           */
+  #define __CORE_SYS   (__CORE_CLK / 4U)
+#elif ((SYSCR_Val & 7U) == 6U)                          /* Gear -> fc/8           */
+  #define __CORE_SYS   (__CORE_CLK / 8U)
+#elif ((SYSCR_Val & 7U) == 7U)                          /* Gear -> fc/16          */
+  #define __CORE_SYS   (__CORE_CLK / 16U)
+#else                                                   /* Gear -> reserved       */
+  #define __CORE_SYS   (0U)
+#endif
+
+#else
+  #define __CORE_SYS   (XTALH)
+
+#endif                                                  /* clock Setup */
+
+/* Clock Variable definitions */
+uint32_t SystemCoreClock = __CORE_SYS;  /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Update SystemCoreClock according register values.
+ */
+void SystemCoreClockUpdate(void)
+{                               /* Get Core Clock Frequency */
+    uint32_t CoreClock = 0U;
+    uint32_t CoreClockInput = 0U;
+    uint32_t regval = 0U;
+    uint32_t oscsel = 0U;
+    uint32_t pllsel = 0U;
+    uint32_t pllon = 0U;
+    /* Determine clock frequency according to clock register values */
+    /* System clock is high-speed clock */
+    regval = TSB_CG->OSCCR;
+    oscsel = regval & CG_OSCCR_OSCSEL_SET;
+    if (oscsel) {  /* If system clock is External high-speed oscillator freq */
+        CoreClock = EXTALH;
+    } else {                    /* If system clock is Internal high-speed oscillator freq */
+        CoreClock = XTALH;
+    }
+    regval = TSB_CG->PLLSEL;
+    pllsel = regval & CG_PLLSEL_PLLSEL_SET;
+    pllon = regval & CG_PLLSEL_PLLON_SET;
+    if (pllsel && pllon) {                        /* If PLL enabled  */
+        if (CoreClock == OSC_8M) {                                          /* If input is 8MHz */
+            if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_4_FPLL) {
+                CoreClockInput = CoreClock * 4U;                             /* output clock is 32MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_5_FPLL) {
+                CoreClockInput = CoreClock * 5U;                            /* output clock is 40MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_6_FPLL) {
+                CoreClockInput = CoreClock * 6U;                            /* output clock is 48MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_10_FPLL) {
+                CoreClockInput = CoreClock * 10U;                            /* output clock is 80MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_8M_MUL_12_FPLL) {
+                CoreClockInput = CoreClock * 12U;                            /* output clock is 96MHz */
+            } else {
+                CoreClockInput = 0U;                                         /* fc -> reserved            */
+            }
+        } else if (CoreClock == OSC_10M) {                                  /* If input is 10MHz */
+            if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_4_FPLL) {
+                CoreClockInput = CoreClock * 4U;                             /* output clock is 40MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_5_FPLL) {
+                CoreClockInput = CoreClock * 5U;                            /* output clock is 50MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_6_FPLL) {
+                CoreClockInput = CoreClock * 6U;                            /* output clock is 60MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_8_FPLL) {
+                CoreClockInput = CoreClock * 8U;                            /* output clock is 80MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_10_FPLL) {
+                CoreClockInput = CoreClock * 10U;                            /* output clock is 100MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_10M_MUL_12_FPLL) {
+                CoreClockInput = CoreClock * 12U;                            /* output clock is 120MHz */
+            }else {
+                CoreClockInput = 0U;                                         /* fc -> reserved */
+            }
+        } else if (CoreClock == OSC_12M) {                                  /* If input is 12MHz */
+            if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_4_FPLL) {
+                CoreClockInput = CoreClock * 4U;                             /* output clock is 48MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_5_FPLL) {
+                CoreClockInput = CoreClock * 5U;                             /* output clock is 60MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_8_FPLL) {
+                CoreClockInput = CoreClock * 8U;                             /* output clock is 96MHz */
+            } else if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_12M_MUL_10_FPLL) {
+                CoreClockInput = CoreClock * 10U;                             /* output clock is 120MHz */
+            } else {
+                CoreClockInput = 0U;                                         /* fc -> reserved */
+            }
+        } else if (CoreClock == OSC_16M) {                                  /* If input is 16MHz */
+            if ((TSB_CG->PLLSEL & PLLSEL_MASK) == CG_16M_MUL_4_FPLL) {
+                CoreClockInput = CoreClock * 4U;                             /* output clock is 64MHz */
+            } else {
+                CoreClockInput = 0U;                                         /* fc -> reserved        */
+            }
+        } else {
+            CoreClockInput = 0U;
+        }
+    } else {
+        CoreClockInput = CoreClock;
+    }
+    switch (TSB_CG->SYSCR & 7U) {
+    case 0U:
+        SystemCoreClock = CoreClockInput;                                    /* Gear -> fc      */
+        break;
+    case 1U:
+    case 2U:
+    case 3U:                                                                 /* Gear -> reserved */
+        SystemCoreClock = 0U;
+        break;
+    case 4U:                                                                 /* Gear -> fc/2     */
+        SystemCoreClock = CoreClockInput / 2U;
+        break;
+    case 5U:                                                                 /* Gear -> fc/4     */
+        SystemCoreClock = CoreClockInput / 4U;
+        break;
+    case 6U:                                                                 /* Gear -> fc/8     */
+        SystemCoreClock = CoreClockInput / 8U;
+        break;
+    case 7U:                                                                 /* Gear -> fc/16     */
+        if (CoreClockInput >= OSC_16M){
+        SystemCoreClock = CoreClockInput / 16U;
+        } else{
+             SystemCoreClock = 0U;
+        }
+        break;
+    default:
+        SystemCoreClock = 0U;
+        break;
+    }
+}
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System.
+ */
+void SystemInit(void)
+{
+    uint32_t regval = 0U;
+    volatile uint32_t pllst = 0U;
+    volatile uint32_t wuef = 0U;
+    volatile uint32_t oscf = 0U;
+    uint32_t wdte = 0U;
+
+#if defined ( __CC_ARM  )/*Enable FPU for Keil*/
+  #if (__FPU_USED == 1)                        /* __FPU_USED is defined in core_cm4.h */
+    /* enable FPU if available and used */
+    SCB->CPACR |= ((3UL << 10*2) |             /* set CP10 Full Access                */
+                   (3UL << 11*2)  );           /* set CP11 Full Access                */
+  #endif
+#endif 
+
+#if (WD_SETUP)                  /* Watchdog Setup */
+    while (TSB_WD->FLG != 0U) {
+    }                /* When writing to WDMOD or WDCR, confirm "0" of WDFLG<FLG>. */
+    TSB_WD->MOD = WDMOD_Val;
+    regval = TSB_WD->MOD;
+    wdte = regval & WD_MOD_WDTE_SET;
+    if (!wdte) {     /* If watchdog is to be disabled */
+        TSB_WD->CR = WDCR_Val;
+    } else {
+        /*Do nothing*/
+    }
+#endif
+
+#if (CLOCK_SETUP)               /* Clock(external) Setup */
+    TSB_CG->SYSCR = SYSCR_Val;
+    TSB_CG->OSCCR &= OSCCR_WUPT_MASK;
+    TSB_CG->OSCCR |= OSCCR_WUPT_EXT;
+    TSB_CG->OSCCR |= CG_OSCCR_HOSCON_SET;
+    TSB_CG->OSCCR |= CG_OSCCR_XEN1_SET;
+    TSB_CG->OSCCR |= CG_OSCCR_WUPSEL2_SET;
+    TSB_CG->OSCCR &= CG_OSCCR_WUPSEL1_CLEAR;
+    TSB_CG->OSCCR |= CG_WUP_START_SET;
+    wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
+    while (wuef) {
+        wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
+    }                           /* Warm-up */
+    TSB_CG->OSCCR |= CG_OSCCR_OSCSEL_SET;
+    oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK;
+    while (oscf != CG_OSCCR_OSCF_MASK) {
+        oscf = TSB_CG->OSCCR & CG_OSCCR_OSCF_MASK;
+    }                         /* Confirm CGOSCCR<OSCF>="1" */
+    /* TSB_CG->OSCCR &= CG_OSCCR_XEN2_CLEAR ; */  /* IHOSC should be not stopped for using WDT. */
+
+    TSB_CG->OSCCR &= OSCCR_WUPT_MASK;
+    TSB_CG->OSCCR |= OSCCR_WUPT_PLL;
+    TSB_CG->PLLSEL &= CG_PLLSEL_PLLON_CLEAR;
+    TSB_CG->PLLSEL = PLLSEL_Ready;
+    TSB_CG->OSCCR |= CG_WUP_START_SET;
+    wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
+    while (wuef) {
+        wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
+    }                           /* Warm-up */
+
+    TSB_CG->OSCCR &= OSCCR_WUPT_MASK;
+    TSB_CG->OSCCR |= OSCCR_WUPT_PLL;
+    TSB_CG->PLLSEL |= CG_PLLSEL_PLLON_SET;    /* PLL enabled */
+    TSB_CG->STBYCR = STBYCR_Val;
+    TSB_CG->OSCCR |= CG_WUP_START_SET;
+    wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
+    while (wuef) {
+        wuef = TSB_CG->OSCCR & CG_WUEF_VALUE_MASK;
+    }                           /* Warm-up */
+    TSB_CG->PLLSEL |= CG_PLLSEL_PLLSEL_SET;
+    pllst = TSB_CG->PLLSEL & CG_PLLSEL_PLLST_MASK;
+    while (pllst != CG_PLLSEL_PLLST_MASK) {
+        pllst = TSB_CG->PLLSEL & CG_PLLSEL_PLLST_MASK;
+    }                        /*Confirm CGPLLSEL<PLLST> = "1" */
+
+#endif
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/device/system_TMPM46B.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,50 @@
+/**
+ *****************************************************************************
+ * @file     system_TMPM46B.h
+ * @brief    CMSIS Cortex-M4 Device Peripheral Access Layer Header File for the
+ *           TOSHIBA 'TMPM46B' Device Series 
+ * @version  V2.0.2.1
+ * @date     2014/12/03
+ * 
+ * DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LICENSE AGREEMENT.
+ * 
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *****************************************************************************
+ */
+
+#ifndef __SYSTEM_TMPM46B_H
+#define __SYSTEM_TMPM46B_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock 
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/flash_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,163 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "flash_api.h"
+#include "mbed_critical.h"
+#include "tmpm46b_fc.h"
+
+#define PROGRAM_WIRTE_MAX             16U      /* Page program could be written 16 bytes/4 words once */
+#define SECTOR_SIZE                   0x8000   /* (512 * 8) sectors  */
+
+#if defined ( __ICCARM__ )    /* IAR Compiler */
+#define FLASH_API_ROM           ((uint32_t *)__section_begin("FLASH_CODE_ROM"))
+#define SIZE_FLASH_API          ((uint32_t)__section_size("FLASH_CODE_ROM"))
+#define FLASH_API_RAM           ((uint32_t *)__section_begin("FLASH_CODE_RAM"))
+#pragma section = "FLASH_CODE_RAM"
+#pragma section = "FLASH_CODE_ROM"
+#endif
+
+#if defined ( __ICCARM__ )    /* IAR Compiler */
+static void Copy_Routine(uint32_t * dest, uint32_t * source, uint32_t size)
+{
+    uint32_t *dest_addr, *source_addr, tmpsize;
+    uint32_t i, tmps, tmpd, mask;
+
+    dest_addr = dest;
+    source_addr = source;
+
+    tmpsize = size >> 2U;
+    for (i = 0U; i < tmpsize; i++) {    /* 32bits copy */
+        *dest_addr = *source_addr;
+        dest_addr++;
+        source_addr++;
+    }
+    if (size & 0x00000003U) {   /* if the last data size is not 0(maybe 1,2 or 3), copy the last data */
+        mask = 0xFFFFFF00U;
+        i = size & 0x00000003U;
+        tmps = *source_addr;
+        tmpd = *dest_addr;
+        while (i - 1U) {
+            mask = mask << 8U;
+            i--;
+        }
+        tmps = tmps & (~mask);
+        tmpd = tmpd & (mask);
+        *dest_addr = tmps + tmpd;       /* 32bits copy, but only change the bytes need to be changed */
+    } else {
+        /* Do nothing */
+    }
+}
+#endif
+
+int32_t flash_init(flash_t *obj)
+{
+    TSB_FC->WCLKCR  = 0x00000004U;
+    TSB_FC->PROGCR  = 0x00000001U;
+    TSB_FC->ERASECR = 0x00000007U;
+    TSB_FC->AREASEL = 0x00000000U;
+#if defined ( __ICCARM__ )    /* IAR Compiler */
+    Copy_Routine(FLASH_API_RAM, FLASH_API_ROM, SIZE_FLASH_API);
+#endif
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    return 0;
+}
+
+#if defined ( __ICCARM__ )    /* IAR Compiler */
+#pragma location = "FLASH_ROM"
+#endif
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    int status = FAIL;
+    /* We need to prevent flash accesses during erase operation */
+    core_util_critical_section_enter();
+
+    if (FC_SUCCESS == FC_EraseBlock(address)) {
+        status = SUCCESS;
+    } else {
+        /* Do nothing */
+    }
+    core_util_critical_section_exit();
+    return status;
+}
+
+#if defined ( __ICCARM__ )    /* IAR Compiler */
+#pragma location = "FLASH_ROM"
+#endif
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+    int status = SUCCESS;
+
+    /* We need to prevent flash accesses during program operation */
+    core_util_critical_section_enter();
+    while (size > PROGRAM_WIRTE_MAX) {
+        if (FC_SUCCESS == FC_WritePage((uint32_t)address, (uint32_t *)data)) {      /* write one page every time */
+            /* Do nothing */
+        } else {
+            status = FAIL;
+            break;
+        }
+        size = size - PROGRAM_WIRTE_MAX;
+        address = address + PROGRAM_WIRTE_MAX;
+        data = data + PROGRAM_WIRTE_MAX;
+    }
+    if (FC_SUCCESS == FC_WritePage((uint32_t)address, (uint32_t *)data)) {  /* write the last data, no more than one page */
+        /* Do nothing */
+    } else {
+        status = FAIL;
+    }
+
+    core_util_critical_section_exit();
+    return status;
+}
+
+#if defined ( __ICCARM__ )    /* IAR Compiler */
+#pragma location = "FLASH_ROM"
+#endif
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    if (address >= FLASH_CHIP_SIZE)
+        return MBED_FLASH_INVALID_SIZE;
+
+    return SECTOR_SIZE;
+}
+
+#if defined ( __ICCARM__ )    /* IAR Compiler */
+#pragma location = "FLASH_ROM"
+#endif
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return FLASH_PAGE_SIZE;
+}
+
+#if defined ( __ICCARM__ )    /* IAR Compiler */
+#pragma location = "FLASH_ROM"
+#endif
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    return FLASH_START_ADDR;
+}
+
+#if defined ( __ICCARM__ )    /* IAR Compiler */
+#pragma location = "FLASH_ROM"
+#endif
+uint32_t flash_get_size(const flash_t *obj)
+{
+    return FLASH_CHIP_SIZE;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/gpio_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#define GPIO_DATA PIN_DATA(0, 3)
+extern const PinMap PinMap_GPIO_IRQ[];
+
+uint32_t gpio_set(PinName pin)
+{
+    // Check that pin is valid
+    MBED_ASSERT(pin != (PinName)NC);
+
+    // Set pin function as GPIO pin
+    pin_function(pin, GPIO_DATA);
+
+    // Return pin mask
+    return (1 << (pin & 0x07));
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+    // Store above pin mask, pin name into GPIO object
+    obj->pin      = pin;
+    obj->mask     = gpio_set(pin);
+    obj->port     = (GPIO_Port) (pin >> 3);
+    CG_SetFcPeriphA((1 << obj->port), ENABLE);
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    // Set pin mode
+    pin_mode(obj->pin, mode);
+}
+
+// Set gpio object pin direction
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    // Set direction
+    switch (direction) {
+        case PIN_INPUT:
+            // Set pin input
+            GPIO_SetInput(obj->port, obj->mask);
+            break;
+        case PIN_OUTPUT:
+            // Set pin output
+            GPIO_SetOutput(obj->port, obj->mask);
+            break;
+        case PIN_INOUT:
+            // Set pin both input and output
+            GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE);
+            GPIO_SetInputEnableReg(obj->port, obj->mask, ENABLE);
+            break;
+        default:
+            error("Invalid direction\n");
+            break;
+    }
+}
+
+void gpio_write(gpio_t *obj, int value)
+{
+    // Write gpio object pin data
+    if ((value == 0) || (value == 1)) {
+        GPIO_WriteDataBit(obj->port, obj->mask, value);
+    } else {
+        error("Invalid value\n");
+    }
+}
+
+int gpio_read(gpio_t *obj)
+{
+    // Read gpio object pin data
+    return GPIO_ReadDataBit(obj->port, obj->mask);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/gpio_irq_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,233 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_irq_api.h"
+#include "mbed_error.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "mbed_critical.h"
+
+#define CHANNEL_NUM          7
+
+const PinMap PinMap_GPIO_IRQ[] = {
+    {PC4, GPIO_IRQ_0, PIN_DATA(0, 0)},
+    {PL0, GPIO_IRQ_1, PIN_DATA(0, 0)},
+    {PD4, GPIO_IRQ_2, PIN_DATA(0, 0)},
+    {PK1, GPIO_IRQ_3, PIN_DATA(0, 0)},
+    {PK0, GPIO_IRQ_4, PIN_DATA(0, 0)},
+    {PC0, GPIO_IRQ_5, PIN_DATA(0, 0)},
+    {PC1, GPIO_IRQ_6, PIN_DATA(0, 0)},
+    {NC,  NC,         0}
+};
+
+static uint32_t channel_ids[CHANNEL_NUM] = {0};
+static gpio_irq_handler hal_irq_handler[CHANNEL_NUM] = {NULL};
+
+static void INT_IRQHandler(PinName pin, GPIO_IRQName irq_id, uint32_t index)
+{
+    uint32_t val;
+    GPIO_Port port;
+    uint32_t mask;
+
+    port = (GPIO_Port)(pin >> 3);
+    mask = 0x01 << (pin & 0x07);
+
+    // Clear interrupt request
+    CG_ClearINTReq((CG_INTSrc)(CG_INT_SRC_1 + index));
+    // Get pin value
+    val = GPIO_ReadDataBit(port, mask);
+    switch (val) {
+        // Falling edge detection
+        case 0:
+            hal_irq_handler[index](channel_ids[index], IRQ_FALL);
+            break;
+        // Rising edge detection
+        case 1:
+            hal_irq_handler[index](channel_ids[index], IRQ_RISE);
+            break;
+        default:
+            break;
+    }
+}
+
+void INT1_IRQHandler(void)
+{
+    INT_IRQHandler(PC4, GPIO_IRQ_0, 0);
+}
+
+void INT2_IRQHandler(void)
+{
+    INT_IRQHandler(PL0, GPIO_IRQ_1, 1);
+}
+
+void INT7_IRQHandler(void)
+{
+    INT_IRQHandler(PD4, GPIO_IRQ_2, 2);
+}
+
+void INT8_IRQHandler(void)
+{
+    INT_IRQHandler(PK1, GPIO_IRQ_3, 3);
+}
+
+void INTD_IRQHandler(void)
+{
+    INT_IRQHandler(PK0, GPIO_IRQ_4, 4);
+}
+
+void INTE_IRQHandler(void)
+{
+    INT_IRQHandler(PC0, GPIO_IRQ_5, 5);
+}
+
+void INTF_IRQHandler(void)
+{
+    INT_IRQHandler(PC1, GPIO_IRQ_6, 6);
+}
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    // Get gpio interrupt ID
+    obj->irq_id = pinmap_peripheral(pin, PinMap_GPIO_IRQ);
+    core_util_critical_section_enter();
+    // Get pin mask
+    obj->mask = (uint32_t)(1 << (pin & 0x07));
+    // Get GPIO port
+    obj->port = (GPIO_Port)(pin >> 3);
+    // Set pin level as LOW
+    GPIO_WriteDataBit(obj->port, obj->mask, 0);
+    // Enable gpio interrupt function
+    pinmap_pinout(pin, PinMap_GPIO_IRQ);
+
+    // Get GPIO irq source
+    switch (obj->irq_id) {
+        case GPIO_IRQ_0:
+            obj->irq_src = CG_INT_SRC_1;
+            break;
+        case GPIO_IRQ_1:
+            obj->irq_src = CG_INT_SRC_2;
+            break;
+        case GPIO_IRQ_2:
+            obj->irq_src = CG_INT_SRC_7;
+            break;
+        case GPIO_IRQ_3:
+            obj->irq_src = CG_INT_SRC_8;
+            break;
+        case GPIO_IRQ_4:
+            obj->irq_src = CG_INT_SRC_D;
+            break;
+        case GPIO_IRQ_5:
+            obj->irq_src = CG_INT_SRC_E;
+            break;
+        case GPIO_IRQ_6:
+            obj->irq_src = CG_INT_SRC_F;
+            break;
+        default:
+            break;
+    }
+    // Save irq handler
+    hal_irq_handler[obj->irq_src] = handler;
+    // Save irq id
+    channel_ids[obj->irq_src] = id;
+    // Initialize interrupt event as both edges detection
+    obj->event = CG_INT_ACTIVE_STATE_INVALID;
+    // Clear gpio pending interrupt
+    NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
+    // Set interrupt event and enable INTx clear
+    CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE);
+    core_util_critical_section_exit();;
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    // Clear gpio_irq
+    NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
+    // Reset interrupt handler
+    hal_irq_handler[obj->irq_src] = NULL;
+    // Reset interrupt id
+    channel_ids[obj->irq_src] = 0;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    //Disable GPIO interrupt on obj
+    gpio_irq_disable(obj);
+    if (enable) {
+        // Get gpio interrupt event
+        if (event == IRQ_RISE) {
+            if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) ||
+                    (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) {
+                obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
+            } else {
+                obj->event = CG_INT_ACTIVE_STATE_RISING;
+            }
+        } else if (event == IRQ_FALL) {
+            if ((obj->event == CG_INT_ACTIVE_STATE_RISING) ||
+                    (obj->event == CG_INT_ACTIVE_STATE_BOTH_EDGES)) {
+                obj->event = CG_INT_ACTIVE_STATE_BOTH_EDGES;
+            } else {
+                obj->event = CG_INT_ACTIVE_STATE_FALLING;
+            }
+        } else {
+            error("Not supported event\n");
+        }
+    } else {
+        // Get gpio interrupt event
+        if (event == IRQ_RISE) {
+            if ((obj->event == CG_INT_ACTIVE_STATE_RISING) ||
+                    (obj->event == CG_INT_ACTIVE_STATE_INVALID)) {
+                obj->event = CG_INT_ACTIVE_STATE_INVALID;
+            } else {
+                obj->event = CG_INT_ACTIVE_STATE_FALLING;
+            }
+        } else if (event == IRQ_FALL) {
+            if ((obj->event == CG_INT_ACTIVE_STATE_FALLING) ||
+                    (obj->event == CG_INT_ACTIVE_STATE_INVALID)) {
+                obj->event = CG_INT_ACTIVE_STATE_INVALID;
+            } else {
+                obj->event = CG_INT_ACTIVE_STATE_RISING;
+            }
+        } else {
+            error("Not supported event\n");
+        }
+    }
+
+    if (obj->event != CG_INT_ACTIVE_STATE_INVALID ) {
+        // Set interrupt event and enable INTx clear
+        CG_SetSTBYReleaseINTSrc(obj->irq_src, (CG_INTActiveState)obj->event, ENABLE);
+        GPIO_SetOutputEnableReg(obj->port, obj->mask, DISABLE);
+    } else {
+        GPIO_SetOutputEnableReg(obj->port, obj->mask, ENABLE);
+    }
+
+    // Clear interrupt request
+    CG_ClearINTReq(obj->irq_src);
+    // Enable GPIO interrupt on obj
+    gpio_irq_enable(obj);
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    // Clear and Enable gpio_irq object
+    NVIC_ClearPendingIRQ((IRQn_Type)obj->irq_id);
+    NVIC_EnableIRQ((IRQn_Type)obj->irq_id);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    // Disable gpio_irq object
+    NVIC_DisableIRQ((IRQn_Type)obj->irq_id);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/gpio_object.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName pin;
+    uint32_t mask;
+    GPIO_Port port;
+} gpio_t;
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+    return (obj->pin != (PinName)NC);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/i2c_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,348 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "i2c_api.h"
+#include "mbed_error.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "tmpm46b_i2c.h"
+#include <string.h>
+#include <stdlib.h>
+
+static const PinMap PinMap_I2C_SDA[] = {
+    {PK2, I2C_0, PIN_DATA(3, 2)},
+    {PF7, I2C_1, PIN_DATA(4, 2)},
+    {PH0, I2C_2, PIN_DATA(4, 2)},
+    {NC,  NC,    0}
+};
+
+static const PinMap PinMap_I2C_SCL[] = {
+    {PK3, I2C_0, PIN_DATA(3, 2)},
+    {PF6, I2C_1, PIN_DATA(4, 2)},
+    {PH1, I2C_2, PIN_DATA(4, 2)},
+    {NC,  NC,    0}
+};
+
+#define SBI_I2C_SEND              0x00
+#define SBI_I2C_RECEIVE           0x01
+#define MAX_NUM_I2C               3
+#define DELAY_MS_MULTIPLIER       5500
+
+struct i2c_xfer {
+    int32_t count;
+    int32_t len;
+    void *done;
+    char *buf;
+};
+
+// Clock setting structure definition
+typedef struct {
+    uint32_t sck;
+    uint32_t prsck;
+} I2C_clock_setting_t;
+
+static void DelayMS(uint32_t delay)
+{
+    volatile uint32_t VarI;
+    for (VarI = 0; VarI < delay * DELAY_MS_MULTIPLIER; VarI++);
+}
+
+static const uint32_t I2C_SCK_DIVIDER_TBL[8] = {
+    20, 24, 32, 48, 80, 144, 272, 528
+};  // SCK Divider value table
+
+static I2C_clock_setting_t clk;
+static I2C_InitTypeDef myi2c;
+static int32_t start_flag = 1;
+static struct i2c_xfer xfer[MAX_NUM_I2C];
+static TSB_I2C_TypeDef *i2c_lut[MAX_NUM_I2C] = {TSB_I2C0, TSB_I2C1, TSB_I2C2};
+static char *gI2C_TxData = NULL;
+static char *gI2C_LTxData = NULL;
+static uint8_t send_byte = 0;
+static uint8_t byte_func = 0;
+
+// Initialize the I2C peripheral. It sets the default parameters for I2C
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    MBED_ASSERT(obj != NULL);
+    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
+    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
+    I2CName i2c_name = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
+    MBED_ASSERT((int)i2c_name != NC);
+
+    switch(i2c_name) {
+        case I2C_0:
+            CG_SetFcPeriphB(CG_FC_PERIPH_I2C0, ENABLE);
+            CG_SetFcPeriphA(CG_FC_PERIPH_PORTK, ENABLE);
+            obj->i2c = TSB_I2C0;
+            obj->index = 0;
+            obj->IRQn = INTI2C0_IRQn;
+            break;
+        case I2C_1:
+            CG_SetFcPeriphB(CG_FC_PERIPH_I2C1, ENABLE);
+            CG_SetFcPeriphA(CG_FC_PERIPH_PORTF, ENABLE);
+            obj->i2c = TSB_I2C1;
+            obj->index = 1;
+            obj->IRQn = INTI2C1_IRQn;
+            break;
+        case I2C_2:
+            CG_SetFcPeriphB(CG_FC_PERIPH_I2C2, ENABLE);
+            CG_SetFcPeriphA(CG_FC_PERIPH_PORTH, ENABLE);
+            obj->i2c = TSB_I2C2;
+            obj->index = 2;
+            obj->IRQn = INTI2C2_IRQn;
+            break;
+        default:
+            error("I2C is not available");
+            break;
+    }
+
+    pinmap_pinout(sda, PinMap_I2C_SDA);
+    pin_mode(sda, OpenDrain);
+    pin_mode(sda, PullUp);
+
+    pinmap_pinout(scl, PinMap_I2C_SCL);
+    pin_mode(scl, OpenDrain);
+    pin_mode(scl, PullUp);
+
+    i2c_reset(obj);
+    i2c_frequency(obj, 100000);
+}
+
+// Configure the I2C frequency
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    uint32_t sck = 0;
+    uint32_t tmp_sck = 0;
+    uint32_t prsck = 1;
+    uint32_t tmp_prsck = 1;
+    uint32_t fscl = 0;
+    uint32_t tmp_fscl = 0;
+    uint64_t fx;
+
+    if (hz <= 400000) { // Maximum 400khz clock frequency supported by  M46B
+        for (prsck = 1; prsck <= 32; prsck++) {
+            fx = ((uint64_t)SystemCoreClock / prsck);
+            if ((fx < 20000000U) && (fx > 6666666U)) {
+                for (sck = 0; sck <= 7; sck++) {
+                    fscl = (fx / (uint64_t)I2C_SCK_DIVIDER_TBL[sck]);
+                    if ((fscl <= (uint64_t)hz) && (fscl > tmp_fscl)) {
+                        tmp_fscl = fscl;
+                        tmp_sck = sck;
+                        tmp_prsck = (prsck < 32)? prsck: 1;
+                    }
+                }
+            }
+        }
+        clk.sck = (uint32_t)tmp_sck;
+        clk.prsck = (tmp_prsck < 32)? (uint32_t)tmp_prsck - 1 : 1;
+    } else {
+        clk.sck = I2C_SCK_CLK_DIV_24;
+        clk.prsck = I2C_PRESCALER_DIV_4;
+    }
+    myi2c.I2CSelfAddr = 0xE0; // Self Address
+    myi2c.I2CDataLen = I2C_DATA_LEN_8;
+    myi2c.I2CACKState = ENABLE;
+    myi2c.I2CClkDiv = clk.sck;
+    myi2c.PrescalerClkDiv = clk.prsck;
+
+    I2C_SWReset(obj->i2c);
+    I2C_Init(obj->i2c, &myi2c);
+    NVIC_EnableIRQ(obj->IRQn);
+    I2C_SetINTReq(obj->i2c, ENABLE);
+}
+
+int i2c_start(i2c_t *obj)
+{
+    start_flag = 1;
+    return 0;
+}
+
+int i2c_stop(i2c_t *obj)
+{
+    I2C_GenerateStop(obj->i2c);
+    return 0;
+}
+
+void i2c_reset(i2c_t *obj)
+{
+    I2C_SWReset(obj->i2c);
+}
+
+static void wait_i2c_bus_free(i2c_t *obj)
+{
+    I2C_State status;
+
+    do {
+        status = I2C_GetState(obj->i2c);
+    } while (status.Bit.BusState);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    TSB_I2C_TypeDef *sbi = obj->i2c;
+    uint32_t i2c_num = 0;
+    obj->address = address;
+
+    i2c_num = obj->index;
+
+    // receive data
+    xfer[i2c_num].count = 0;
+    xfer[i2c_num].len = length;
+    xfer[i2c_num].buf = data;
+
+    I2C_SetSendData(sbi, address | SBI_I2C_RECEIVE);
+    I2C_GenerateStart(sbi);
+
+    wait_i2c_bus_free(obj);
+    return (xfer[i2c_num].count - 1);
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    int8_t i = 0;
+    TSB_I2C_TypeDef *sbi = obj->i2c;
+    uint32_t i2c_num = 0;
+    obj->address = address;
+
+    i2c_num = obj->index;
+    gI2C_TxData = (char *)calloc(length, sizeof(int8_t));
+
+    for (i = 0; i < length; i++) {
+        gI2C_TxData[i] = data[i];
+    }
+    // receive data
+    xfer[i2c_num].count = 0;
+    xfer[i2c_num].len = length;
+    xfer[i2c_num].buf = gI2C_TxData;
+
+    I2C_SetSendData(sbi, address | SBI_I2C_SEND);
+    I2C_GenerateStart(sbi);  // Start condition
+
+    wait_i2c_bus_free(obj);
+    free(gI2C_TxData);
+    DelayMS(8);
+    if (((xfer[i2c_num].count - 1) == 0) && (byte_func == 1)) {
+        send_byte = 1;
+        i2c_byte_write(obj, 0x00);
+        xfer[i2c_num].count = 1;
+        byte_func = 0;
+    }
+    return (xfer[i2c_num].count - 1);
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+    char i2c_ret = 0;
+    i2c_read(obj, obj->address, &i2c_ret, 1, last);
+    return i2c_ret;
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+    uint32_t wb = 1;
+    static size_t counter = 1;
+
+    byte_func = 1;
+    if (start_flag == 0 && send_byte == 0) {
+        gI2C_LTxData = (char *)realloc(gI2C_LTxData, counter++);
+        gI2C_LTxData[counter - 2] = data;
+    }
+
+    if (send_byte == 1) {
+        wb = i2c_write(obj, obj->address, gI2C_LTxData, (counter - 1), 0);
+        start_flag = 1;
+        send_byte = 0;
+        byte_func = 0;
+        counter = 1;
+        return wb;
+    } else {
+        if (start_flag == 1) {
+            obj->address = data;
+            start_flag = 0;
+        } else {
+            // Store the number of written bytes
+            wb = i2c_write(obj, obj->address, (char*)&data, 1, 0);
+        }
+        if (wb == 1)
+            return 1;
+        else
+            return 0;
+    }
+}
+
+static void i2c_irq_handler(int i2c_num)
+{
+    uint32_t tmp = 0U;
+    TSB_I2C_TypeDef *sbi = i2c_lut[i2c_num];
+    I2C_State sbi_sr;
+
+    sbi_sr = I2C_GetState(sbi);
+
+    // we don't support slave mode
+    if (!sbi_sr.Bit.MasterSlave)
+        return;
+
+    if (sbi_sr.Bit.TRx) { // Tx mode
+        if (sbi_sr.Bit.LastRxBit) { // LRB=1: the receiver requires no further data.
+            I2C_GenerateStop(sbi);
+        } else { // LRB=0: the receiver requires further data.
+            if (xfer[i2c_num].count < xfer[i2c_num].len) {
+                I2C_SetSendData(sbi, xfer[i2c_num].buf[xfer[i2c_num].count]); // Send next data
+            } else if (xfer[i2c_num].count == xfer[i2c_num].len) { // I2C data send finished.
+                I2C_GenerateStop(sbi);
+            } else {
+                // Do nothing
+            }
+            xfer[i2c_num].count++;
+        }
+    } else { // Rx Mode
+        if (xfer[i2c_num].count > xfer[i2c_num].len) {
+            I2C_GenerateStop(sbi);
+            I2C_SetACK(sbi, ENABLE);
+        } else {
+            if (xfer[i2c_num].count == xfer[i2c_num].len) { // Rx last data
+                I2C_SetBitNum(sbi, I2C_DATA_LEN_1);
+            } else if (xfer[i2c_num].count == (xfer[i2c_num].len - 1)) { // Rx the data second to last
+                // Not generate ACK for next data Rx end.
+                I2C_SetACK(sbi, DISABLE);
+            } else {
+                // Do nothing
+            }
+            tmp = I2C_GetReceiveData(sbi);
+            if (xfer[i2c_num].count > 0) {
+                xfer[i2c_num].buf[xfer[i2c_num].count - 1U] = tmp;
+            } else {
+                // first read is dummy read
+            }
+            xfer[i2c_num].count++;
+        }
+    }
+}
+
+void INTI2C0_IRQHandler(void)
+{
+    i2c_irq_handler(0);
+}
+
+void INTI2C1_IRQHandler(void)
+{
+    i2c_irq_handler(1);
+}
+
+void INTI2C2_IRQHandler(void)
+{
+    i2c_irq_handler(2);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/objects.h	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include <stdbool.h>
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "tmpm46b_gpio.h"
+#include "tmpm46b_uart.h"
+#include "tmpm46b_fuart.h"
+#include "tmpm46b_cg.h"
+#include "tmpm46b_i2c.h"
+#include "tmpm46b_adc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    uint32_t mask;
+    GPIO_Port port;
+    uint32_t irq_id;
+    CG_INTActiveState event;
+    CG_INTSrc irq_src;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+};
+
+struct pwmout_s {
+    PinName pin;
+    TSB_TB_TypeDef * channel;
+    uint16_t trailing_timing;
+    uint16_t leading_timing;
+    uint16_t divisor;
+    float period;
+};
+
+struct serial_s {
+    PinName pin;
+    uint32_t index;
+    TSB_SC_TypeDef * UARTx;
+    TSB_FUART_TypeDef *FUART;
+    UART_InitTypeDef uart_config;
+    FUART_InitTypeDef fuart_config;
+    TSB_UART_TypeDef *FUART_Reg;
+};
+
+struct analogin_s {
+    PinName pin;
+    ADCName adc;
+    TSB_AD_TypeDef* obj;
+    ADC_AINx channel;
+};
+
+struct i2c_s {
+    uint32_t index;
+    int address;
+    IRQn_Type IRQn;
+    TSB_I2C_TypeDef *i2c;
+    I2C_InitTypeDef myi2c;
+};
+
+struct spi_s {
+    TSB_SSP_TypeDef *spi;
+    SPIName module;
+    uint8_t bits;
+};
+
+struct trng_s {
+    bool trng_init;
+};
+
+struct flash_s {
+    uint8_t dummy;
+};
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/pinmap.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,106 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "tmpm46b_gpio.h"
+
+#define PIN_FUNC_MAX        6
+
+void pin_function(PinName pin, int function)
+{
+    uint32_t port = 0;
+    uint8_t bit = 0;
+    uint8_t i = 0;
+    uint8_t func = 0;
+    uint8_t dir = 0;
+
+    // Assert that pin is valid
+    MBED_ASSERT(pin != NC);
+
+    // Calculate pin function and pin direction
+    func = PIN_FUNC(function);
+    dir  = PIN_DIR(function);
+    // Calculate port and pin position
+    port = PIN_PORT(pin);
+    bit  = PIN_POS(pin);
+    // Set function if function is in range
+    if (func <= PIN_FUNC_MAX) {
+        // Disable other functions
+        for (i = 0; i < PIN_FUNC_MAX; i++) {
+            if (i != (func - 1)) {
+                GPIO_DisableFuncReg((GPIO_Port)port, i, (1 << bit));
+            }
+        }
+        // Set pin function
+        if (func) {
+            GPIO_EnableFuncReg((GPIO_Port)port, (uint8_t)(func - 1), (1 << bit));
+        }
+    }
+
+    // Set direction if direction is in range
+    switch (dir) {
+        case PIN_INPUT:
+            GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
+            GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), DISABLE);
+            break;
+        case PIN_OUTPUT:
+            GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
+            GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), DISABLE);
+            break;
+        case PIN_INOUT:
+            GPIO_SetOutputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
+            GPIO_SetInputEnableReg((GPIO_Port)port, (1 << bit), ENABLE);
+            break;
+        default:
+            break;
+    }
+}
+
+void pin_mode(PinName pin, PinMode mode)
+{
+    uint32_t port = 0;
+    uint8_t bit = 0;
+
+    // Assert that pin is valid
+    MBED_ASSERT(pin != NC);
+
+    // Check if function is in range
+    if (mode > OpenDrain) {
+        return;
+    }
+    // Calculate port and pin position
+    port = PIN_PORT(pin);
+    bit = PIN_POS(pin);
+    // Set pin mode
+    switch (mode) {
+        case PullNone:
+            GPIO_SetPullUp((GPIO_Port)port, (1 << bit), DISABLE);
+            GPIO_SetPullDown((GPIO_Port)port, (1 << bit), DISABLE);
+            GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), DISABLE);
+            break;
+        case PullUp:
+            GPIO_SetPullUp((GPIO_Port)port, (1 << bit), ENABLE);
+            break;
+        case PullDown:
+            GPIO_SetPullDown((GPIO_Port)port, (1 << bit), ENABLE);
+            break;
+        case OpenDrain:
+            GPIO_SetOpenDrain((GPIO_Port)port, (1 << bit), ENABLE);
+            break;
+        default:
+            break;
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/port_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "port_api.h"
+#include "pinmap.h"
+
+#define PORT_PIN_NUM        8
+
+PinName port_pin(PortName port, int pin_n)
+{
+    PinName pin = NC;
+    pin = (PinName)((port << 3) | pin_n);
+    return pin;
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+    uint8_t i = 0;
+
+    // Assert that port is valid
+    MBED_ASSERT(port <= PortL);
+
+    // Store port and port mask for future use
+    obj->port = port;
+    obj->mask = mask;
+
+    CG_SetFcPeriphA((1 << obj->port), ENABLE);
+
+    // Set port function and port direction
+    for (i = 0; i < PORT_PIN_NUM; i++) {
+        // If the pin is used
+        if (obj->mask & (1 << i)) {
+            pin_function(port_pin(obj->port, i), dir);
+        }
+    }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+    uint8_t i = 0;
+
+    // Assert that port is valid
+    MBED_ASSERT(obj->port <= PortL);
+
+    // Set mode for masked pins
+    for (i = 0; i < PORT_PIN_NUM; i++) {
+        // If the pin is used
+        if (obj->mask & (1 << i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+    // Assert that port is valid
+    MBED_ASSERT(obj->port <= PortL);
+
+    // Set direction for masked pins
+    switch (dir) {
+        case PIN_INPUT:
+            GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE);
+            GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
+            break;
+        case PIN_OUTPUT:
+            GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, DISABLE);
+            GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
+            break;
+        case PIN_INOUT:
+            GPIO_SetOutputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
+            GPIO_SetInputEnableReg((GPIO_Port)obj->port, obj->mask, ENABLE);
+            break;
+        default:
+            break;
+    }
+}
+
+void port_write(port_t *obj, int value)
+{
+    uint8_t port_data = 0;
+    uint8_t data = 0;
+
+    // Assert that port is valid
+    MBED_ASSERT(obj->port <= PortL);
+
+    // Get current data of port
+    port_data = GPIO_ReadData((GPIO_Port)obj->port);
+    // Calculate data to write to masked pins
+    data = (port_data & ~obj->mask) | (value & obj->mask);
+    // Write data to masked pins of the port
+    GPIO_WriteData((GPIO_Port)obj->port, data);
+}
+
+int port_read(port_t *obj)
+{
+    uint8_t port_data = 0;
+    uint8_t data = 0;
+
+    // Assert that port is valid
+    MBED_ASSERT(obj->port <= PortL);
+
+    // Get current data of port
+    port_data = GPIO_ReadData((GPIO_Port)obj->port);
+    // Calculate data of masked pins
+    data = port_data & obj->mask;
+    return data;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/pwmout_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,213 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pwmout_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "tmpm46b_tmrb.h"
+
+#define MAX_COUNTER_16B         0xFFFF
+
+static TMRB_InitTypeDef m_tmrb;
+static TMRB_FFOutputTypeDef FFStruct;
+
+static const PinMap PinMap_PWM[] = {
+    {PE4, PWM_0, PIN_DATA(5, 1)},
+    {PB6, PWM_1, PIN_DATA(4, 1)},
+    {PH1, PWM_2, PIN_DATA(2, 1)},
+    {PH0, PWM_3, PIN_DATA(2, 1)},
+    {PK1, PWM_4, PIN_DATA(4, 1)},
+    {PA7, PWM_5, PIN_DATA(5, 1)},
+    {NC,  NC,    0}
+};
+
+static const uint32_t prescale_tbl[] = {
+    2, 8, 32, 64, 128, 256, 512
+};
+
+#define CLOCK_FREQUENCY                         (48000000)  // Input source clock
+
+void pwmout_init(pwmout_t *obj, PinName pin)
+{
+    // Determine the pwm channel
+    PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
+    //Assert input is valid
+    MBED_ASSERT(pwm != (PWMName)NC);
+    switch (pwm) {
+        case PWM_0:
+            obj->channel = TSB_TB2;
+            break;
+        case PWM_1:
+            obj->channel = TSB_TB3;
+            break;
+        case PWM_2:
+            obj->channel = TSB_TB4;
+            break;
+        case PWM_3:
+            obj->channel = TSB_TB5;
+            break;
+        case PWM_4:
+            obj->channel = TSB_TB6;
+            break;
+        case PWM_5:
+            obj->channel = TSB_TB7;
+            break;
+        default:
+            obj->channel = NULL;
+            break;
+    }
+    CG_SetFcPeriphA((0x01U << (15U + pwm)), ENABLE);
+    TMRB_SetIdleMode(TSB_TB0, DISABLE);
+    // Set pin function as PWM
+    pinmap_pinout(pin, PinMap_PWM);
+    // Default to 20ms, 0% duty cycle
+    pwmout_period_ms(obj, 20);
+}
+
+void pwmout_free(pwmout_t *obj)
+{
+    // Stops and clear count operation
+    TMRB_SetRunState(obj->channel, TMRB_STOP);
+    pwmout_write(obj,0);
+    obj->channel = NULL;
+    obj->trailing_timing = 0;
+    obj->leading_timing = 0;
+    obj->divisor = 0;
+    TMRB_SetIdleMode(TSB_TB0, ENABLE);
+}
+
+void pwmout_write(pwmout_t *obj, float value)
+{
+    // Stop timer for setting clock again
+    TMRB_SetRunState(obj->channel, TMRB_STOP);
+    // values outside this range will be saturated to 0.0f or 1.0f
+    // Disable flip-flop reverse trigger when leading_timing and trailing_timing are duplicated
+    if (value <= 0.0f) {
+        value = 0;
+        FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
+        FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
+    } else if (value >= 1.0f) {
+        value = 1;
+        FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_SET;
+        FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
+    } else {
+        FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
+        FFStruct.FlipflopReverseTrg = (TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING);
+    }
+    TMRB_SetFlipFlop(obj->channel, &FFStruct);
+
+    if (obj->period > 0.7) {
+        value = 1; //TMPM46B duty cycle should be < 700ms, above 700ms fixed 50% duty cycle
+    }
+    // Store the new leading_timing value
+    obj->leading_timing = obj->trailing_timing - (uint16_t)(obj->trailing_timing * value);
+
+    // Setting TBxRG0 register
+    TMRB_ChangeLeadingTiming(obj->channel, obj->leading_timing);
+    TMRB_SetRunState(obj->channel, TMRB_RUN);
+}
+
+float pwmout_read(pwmout_t *obj)
+{
+    float duty_cycle = (float)(obj->trailing_timing - obj->leading_timing) / obj->trailing_timing;
+    return duty_cycle;
+}
+
+void pwmout_period(pwmout_t *obj, float seconds)
+{
+    pwmout_period_us(obj, (int)(seconds * 1000000.0f));
+}
+
+void pwmout_period_ms(pwmout_t *obj, int ms)
+{
+    pwmout_period_us(obj, (ms * 1000));
+}
+
+// Set the PWM period, keeping the duty cycle the same.
+void pwmout_period_us(pwmout_t *obj, int us)
+{
+    float seconds = 0;
+    uint32_t cycles = 0;
+    int ClkDiv = 0;
+    int i = 0;
+    float duty_cycle = 0;
+    uint32_t clk_freq = 0;
+
+    seconds = (float)((us) / 1000000.0f);
+    obj->period = seconds;
+
+    if (obj->period > 0.7) {
+        clk_freq = (CLOCK_FREQUENCY / 2);
+    } else {
+        clk_freq = CLOCK_FREQUENCY;
+    }
+    // Select highest timer resolution
+    for (i = 0; i < 7; ++i) {
+        cycles = (int)((clk_freq / prescale_tbl[i]) * seconds);
+        if (cycles <= MAX_COUNTER_16B) {
+            ClkDiv = i + 1; // range 1:6
+            break;
+        } else {
+            cycles = MAX_COUNTER_16B;
+            ClkDiv = 7;
+        }
+    }
+    // Stops and clear count operation
+    TMRB_SetRunState(obj->channel, TMRB_STOP);
+    // Restore the duty-cycle
+    duty_cycle = (float)((obj->trailing_timing - obj->leading_timing) / obj->trailing_timing);
+    obj->trailing_timing = cycles;
+    obj->leading_timing = ((cycles)- (uint16_t)(cycles * duty_cycle));
+
+    // Change the source clock division and period
+    m_tmrb.Mode = TMRB_INTERVAL_TIMER;
+    m_tmrb.ClkDiv = ClkDiv;
+    m_tmrb.UpCntCtrl = TMRB_AUTO_CLEAR;
+    m_tmrb.TrailingTiming = obj->trailing_timing;
+    m_tmrb.LeadingTiming = obj->leading_timing;
+    FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_SET;
+    FFStruct.FlipflopReverseTrg = (TMRB_FLIPFLOP_MATCH_TRAILING | TMRB_FLIPFLOP_MATCH_LEADING);
+    // Enable channel
+    TMRB_Enable(obj->channel);
+    // Disable double buffering
+    TMRB_SetDoubleBuf(obj->channel, DISABLE, TMRB_WRITE_REG_SEPARATE);
+    // Init timer function
+    TMRB_Init(obj->channel, &m_tmrb);
+    // Enable double buffering
+    TMRB_SetDoubleBuf(obj->channel, ENABLE, TMRB_WRITE_REG_SEPARATE);
+    TMRB_SetFlipFlop(obj->channel, &FFStruct);
+    // Start timer function
+    TMRB_SetRunState(obj->channel, TMRB_RUN);
+}
+
+void pwmout_pulsewidth(pwmout_t *obj, float seconds)
+{
+    pwmout_pulsewidth_us(obj, (seconds * 1000000.0f));
+}
+
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
+{
+    pwmout_pulsewidth_us(obj, (ms * 1000));
+}
+
+void pwmout_pulsewidth_us(pwmout_t *obj, int us)
+{
+    float seconds = 0;
+    float value = 0;
+
+    seconds = (float)(us / 1000000.0f);
+    value = (((seconds / obj->period) * 100.0f) / 100.0f);
+    pwmout_write(obj, value);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/serial_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,573 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <string.h>
+#include "serial_api.h"
+#include "PeripheralNames.h"
+#include "pinmap.h"
+#include "tmpm46b_uart.h"
+#include "tmpm46b_fuart.h"
+
+#define UART_NUM                      6
+#define FUART_INT_BITS                0x07FF
+
+static const PinMap PinMap_UART_TX[] = {
+    {PE2, SERIAL_0, PIN_DATA(1, 1)},
+    {PE5, SERIAL_1, PIN_DATA(1, 1)},
+    {PL2, SERIAL_2, PIN_DATA(5, 1)},
+    {PB0, SERIAL_3, PIN_DATA(3, 1)},
+    {PF1, SERIAL_4, PIN_DATA(3, 1)},
+    {PA6, SERIAL_5, PIN_DATA(2, 1)},
+    {NC,  NC,    0}
+};
+
+static const PinMap PinMap_UART_RX[] = {
+    {PE1, SERIAL_0, PIN_DATA(1, 0)},
+    {PE6, SERIAL_1, PIN_DATA(1, 0)},
+    {PL1, SERIAL_2, PIN_DATA(5, 0)},
+    {PB1, SERIAL_3, PIN_DATA(3, 0)},
+    {PF2, SERIAL_4, PIN_DATA(3, 0)},
+    {PA5, SERIAL_5, PIN_DATA(2, 0)},
+    {NC, NC,    0}
+};
+
+static const PinMap PinMap_UART_CTS[] = {
+    {PE3, SERIAL_0, PIN_DATA(4, 0)},
+    {PE4, SERIAL_1, PIN_DATA(4, 0)},
+    {PL3, SERIAL_2, PIN_DATA(6, 0)},
+    {PA7, SERIAL_3, PIN_DATA(4, 0)},
+    {PF0, SERIAL_4, PIN_DATA(3, 0)},
+    {PA7, SERIAL_5, PIN_DATA(2, 0)},
+    {NC,  NC,    0}
+};
+
+static const PinMap PinMap_UART_RTS[] = {
+    {PF3, SERIAL_4, PIN_DATA(3, 1)},
+    {PA4, SERIAL_5, PIN_DATA(2, 1)},
+    {NC,  NC,    0}
+};
+
+
+static uint32_t serial_irq_ids[UART_NUM] = {0};
+static uart_irq_handler irq_handler;
+void serial_init_UART_configure(int uartname, serial_t *obj, PinName tx, PinName rx);
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    int is_stdio_uart = 0;
+
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+    UARTName uart_name = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT((int)uart_name != NC);
+
+    obj->index = uart_name;
+    // Initialize UART instance
+    switch (uart_name) {
+        case SERIAL_0:
+            obj->UARTx = UART0;
+            serial_init_UART_configure(SERIAL_0, obj, tx, rx);
+            break;
+        case SERIAL_1:
+            obj->UARTx = UART1;
+            serial_init_UART_configure(SERIAL_1, obj, tx, rx);
+            break;
+        case SERIAL_2:
+            obj->UARTx = UART2;
+            serial_init_UART_configure(SERIAL_2, obj, tx, rx);
+            break;
+        case SERIAL_3:
+            obj->UARTx = UART3;
+            serial_init_UART_configure(SERIAL_3, obj, tx, rx);
+            break;
+        case SERIAL_4:
+            obj->FUART = FUART0;
+            serial_init_UART_configure(SERIAL_4, obj, tx, rx);
+            break;
+        case SERIAL_5:
+            obj->FUART = FUART1;
+            serial_init_UART_configure(SERIAL_5, obj, tx, rx);
+            break;
+        default:
+            break;
+    }
+
+    is_stdio_uart = (uart_name == STDIO_UART) ? (1) : (0);
+
+    if (is_stdio_uart) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_init_UART_configure(int uartname, serial_t *obj, PinName tx, PinName rx)
+{
+    if (uartname <= SERIAL_3)    {
+        obj->uart_config.BaudRate = 9600U;
+        obj->uart_config.DataBits = UART_DATA_BITS_8;
+        obj->uart_config.StopBits = UART_STOP_BITS_1;
+        obj->uart_config.Parity   = UART_NO_PARITY;
+        obj->uart_config.FlowCtrl = UART_NONE_FLOW_CTRL;
+
+        if (tx != NC && rx != NC) {
+            obj->uart_config.Mode = UART_ENABLE_RX | UART_ENABLE_TX;
+        } else if (tx != NC) {
+            obj->uart_config.Mode = UART_ENABLE_TX;
+        } else if (rx != NC) {
+            obj->uart_config.Mode = UART_ENABLE_RX;
+        }
+
+        // Pinout the chosen uart
+        pinmap_pinout(tx, PinMap_UART_TX);
+        pinmap_pinout(rx, PinMap_UART_RX);
+
+        UART_Enable(obj->UARTx);
+        UART_SetIdleMode(obj->UARTx, ENABLE);
+        UART_Init(obj->UARTx, &obj->uart_config);
+    } else {
+        obj->fuart_config.BaudRate = 9600U;
+        obj->fuart_config.DataBits = FUART_DATA_BITS_8;
+        obj->fuart_config.StopBits = FUART_STOP_BITS_1;
+        obj->fuart_config.Parity = FUART_NO_PARITY;
+        obj->fuart_config.FlowCtrl = FUART_NONE_FLOW_CTRL;
+
+        if (tx != NC && rx != NC) {
+            obj->fuart_config.Mode = FUART_ENABLE_TX | FUART_ENABLE_RX;
+        } else if (tx != NC) {
+            obj->fuart_config.Mode = FUART_ENABLE_TX;
+        } else if (rx != NC) {
+            obj->fuart_config.Mode = FUART_ENABLE_RX;
+        }
+
+        // pin-out the chosen UART
+        pinmap_pinout(tx, PinMap_UART_TX);
+        pinmap_pinout(rx, PinMap_UART_RX);
+
+        FUART_Init(obj->FUART, &obj->fuart_config);
+        FUART_Enable(obj->FUART);
+    }
+}
+
+void serial_free(serial_t *obj)
+{
+    switch (obj->index) {
+        case SERIAL_0:
+        case SERIAL_1:
+        case SERIAL_2:
+        case SERIAL_3:
+            // Disable UART
+            UART_Disable(obj->UARTx);
+            UART_SWReset(obj->UARTx);
+            // set information of object to invalid
+            obj->uart_config.BaudRate = 0;
+            obj->uart_config.DataBits = 0;
+            obj->uart_config.StopBits = 0;
+            obj->uart_config.Parity = 0;
+            obj->uart_config.Mode = 0;
+            obj->uart_config.FlowCtrl = 0;
+            break;
+        case SERIAL_4:
+        case SERIAL_5:
+            // Disable UART
+            FUART_Disable(obj->FUART);
+            // set information of object to invalid
+            obj->fuart_config.BaudRate = 0;
+            obj->fuart_config.DataBits = 0;
+            obj->fuart_config.StopBits = 0;
+            obj->fuart_config.Parity = 0;
+            obj->fuart_config.Mode = 0;
+            obj->fuart_config.FlowCtrl = 0;
+            break;
+    }
+}
+
+// serial_baud
+void serial_baud(serial_t *obj, int baudrate)
+{
+    switch (obj->index) {
+        case SERIAL_0:
+        case SERIAL_1:
+        case SERIAL_2:
+        case SERIAL_3:
+            obj->uart_config.BaudRate = baudrate;
+            UART_Init(obj->UARTx,&obj->uart_config);
+            break;
+        case SERIAL_4:
+        case SERIAL_5:
+            FUART_Disable(obj->FUART);
+            obj->fuart_config.BaudRate = baudrate;
+            FUART_Init(obj->FUART,&obj->fuart_config);
+            FUART_Enable(obj->FUART);
+            break;
+    }
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+    // 0: 1 stop bits, 1: 2 stop bits
+    MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
+    MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
+                (parity == ParityForced1) || (parity == ParityForced0));
+    // 0: 7 data bits ... 2: 9 data bits
+    switch (obj->index) {
+        case SERIAL_0:
+        case SERIAL_1:
+        case SERIAL_2:
+        case SERIAL_3:
+            MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits
+            obj->uart_config.DataBits = data_bits;
+            obj->uart_config.StopBits = stop_bits;
+            obj->uart_config.Parity = parity;
+            UART_Init(obj->UARTx,&obj->uart_config);
+            break;
+        case SERIAL_4:
+        case SERIAL_5:
+            FUART_Disable(obj->FUART);
+            MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 2: 8 data bits
+            obj->fuart_config.DataBits = data_bits;
+            obj->fuart_config.StopBits = stop_bits;
+            obj->fuart_config.Parity = parity;
+            FUART_Init(obj->FUART,&obj->fuart_config);
+            FUART_Enable(obj->FUART);
+            break;
+    }
+}
+
+void INTTX0_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_0], TxIrq);
+}
+
+void INTRX0_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_0], RxIrq);
+}
+
+void INTTX1_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_1], TxIrq);
+}
+
+void INTRX1_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_1], RxIrq);
+}
+
+void INTTX2_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_2], TxIrq);
+}
+
+void INTRX2_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_2], RxIrq);
+}
+
+void INTTX3_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_3], TxIrq);
+}
+
+void INTRX3_IRQHandler(void)
+{
+    irq_handler(serial_irq_ids[SERIAL_3], RxIrq);
+}
+
+void INTUART0_IRQHandler(void)
+{
+    FUART_INTStatus fuart_int;
+    fuart_int = FUART_GetMaskedINTStatus(FUART0);
+    if (fuart_int.Bit.TxFIFO == 1) {
+        irq_handler(serial_irq_ids[SERIAL_4], TxIrq);
+    }
+    if (fuart_int.Bit.RxFIFO == 1) {
+        irq_handler(serial_irq_ids[SERIAL_4], RxIrq);
+    }
+}
+
+void INTUART1_IRQHandler(void)
+{
+    FUART_INTStatus fuart_int;
+    fuart_int = FUART_GetMaskedINTStatus(FUART1);
+    if (fuart_int.Bit.TxFIFO == 1) {
+        irq_handler(serial_irq_ids[SERIAL_5], TxIrq);
+    }
+    if (fuart_int.Bit.RxFIFO == 1) {
+        irq_handler(serial_irq_ids[SERIAL_5], RxIrq);
+    }
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t int_mask = 0;
+
+    switch (obj->index) {
+        case SERIAL_0:
+            if (irq == RxIrq) {
+                irq_n = INTRX0_IRQn;
+            } else {
+                irq_n = INTTX0_IRQn;
+            }
+            break;
+        case SERIAL_1:
+            if (irq == RxIrq) {
+                irq_n = INTRX1_IRQn;
+            } else {
+                irq_n = INTTX1_IRQn;
+            }
+            break;
+        case SERIAL_2:
+            if (irq == RxIrq) {
+                irq_n = INTRX2_IRQn;
+            } else {
+                irq_n = INTTX2_IRQn;
+            }
+            break;
+        case SERIAL_3:
+            if (irq == RxIrq) {
+                irq_n = INTRX3_IRQn;
+            } else {
+                irq_n = INTTX3_IRQn;
+            }
+            break;
+        case SERIAL_4:
+            irq_n = INTUART0_IRQn;
+            break;
+        case SERIAL_5:
+            irq_n = INTUART1_IRQn;
+            break;
+    }
+
+    if ((obj->index == SERIAL_4) || (obj->index == SERIAL_5)) {
+        // Get interrupt mask
+        int_mask = obj->FUART->IMSC & FUART_INT_BITS;
+
+        // Set interrupt mask
+        if (irq == RxIrq) {
+            int_mask |= FUART_RX_FIFO_INT_MASK;
+        } else {
+            int_mask |= FUART_TX_FIFO_INT_MASK;
+        }
+        FUART_SetINTMask(obj->FUART, int_mask);
+    }
+
+    if (enable) {
+        NVIC_EnableIRQ(irq_n);
+    } else {
+        NVIC_DisableIRQ(irq_n);
+    }
+}
+
+int serial_getc(serial_t *obj)
+{
+    int data = 0;
+
+    // Wait until Rx buffer is full
+    while (!serial_readable(obj)) {
+        // Do nothing
+    }
+    switch (obj->index) {
+        case SERIAL_0:
+        case SERIAL_1:
+        case SERIAL_2:
+        case SERIAL_3:
+            data = (int) UART_GetRxData(obj->UARTx);
+            break;
+        case SERIAL_4:
+        case SERIAL_5:
+            data = (int) FUART_GetRxData(obj->FUART);
+            break;
+        default:
+            break;
+    }
+    return data;
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    // Wait until Tx buffer is empty
+    while (!serial_writable(obj)) {
+        // Do nothing
+    }
+
+    switch (obj->index) {
+        case SERIAL_0:
+        case SERIAL_1:
+        case SERIAL_2:
+        case SERIAL_3:
+            UART_SetTxData(obj->UARTx,(uint32_t)c);
+            break;
+        case SERIAL_4:
+        case SERIAL_5:
+            FUART_SetTxData(obj->FUART,(uint32_t)c);
+            break;
+    }
+}
+
+int serial_readable(serial_t *obj)
+{
+    int ret = 0;
+
+    switch (obj->index) {
+        case SERIAL_0:
+        case SERIAL_1:
+        case SERIAL_2:
+        case SERIAL_3:
+            if(UART_GetBufState(obj->UARTx, UART_RX) == DONE) {
+                ret = 1;
+            }
+            break;
+        case SERIAL_4:
+        case SERIAL_5:
+            if (FUART_GetStorageStatus(obj->FUART, FUART_RX) == FUART_STORAGE_FULL) {
+                ret = 1;
+            }
+            break;
+    }
+    return ret;
+}
+
+int serial_writable(serial_t *obj)
+{
+    int ret = 0;
+
+    switch (obj->index) {
+        case SERIAL_0:
+        case SERIAL_1:
+        case SERIAL_2:
+        case SERIAL_3:
+            if(UART_GetBufState(obj->UARTx, UART_TX) == DONE) {
+                ret = 1;
+            }
+            break;
+        case SERIAL_4:
+        case SERIAL_5:
+            if (FUART_GetStorageStatus(obj->FUART, FUART_TX) == FUART_STORAGE_EMPTY) {
+                ret = 1;
+            }
+            break;
+    }
+    return ret;
+}
+
+void serial_clear(serial_t *obj)
+{
+    switch (obj->index) {
+        case SERIAL_0:
+        case SERIAL_1:
+        case SERIAL_2:
+        case SERIAL_3:
+            UART_GetRxData(obj->UARTx);
+            break;
+        case SERIAL_4:
+        case SERIAL_5:
+            FUART_GetRxData(obj->FUART);
+            break;
+    }
+}
+
+void serial_pinout_tx(PinName tx)
+{
+    // pin out the chosen UART
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+// Set flow control, Just support CTS
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
+{
+    UARTName uart_cts = (UARTName)pinmap_peripheral(txflow, PinMap_UART_CTS);
+    UARTName uart_rts = (UARTName)pinmap_peripheral(rxflow, PinMap_UART_RTS);
+    UARTName uart_name = (UARTName)pinmap_merge(uart_cts, uart_rts);
+
+    switch (obj->index) {
+        case SERIAL_0:
+        case SERIAL_1:
+        case SERIAL_2:
+        case SERIAL_3:
+            if (FlowControlCTS == type) {
+                MBED_ASSERT(uart_cts != (UARTName) NC);
+
+                // Enable the pin for CTS function
+                pinmap_pinout(txflow, PinMap_UART_CTS);
+
+                // Support CTS hardware control flow only
+                obj->UARTx->MOD0 |= 1 << 6;
+            } else {
+                // Disable hardware flow control
+                obj->UARTx->MOD0 &= !(1 << 6);
+            }
+            break;
+        case SERIAL_4:
+        case SERIAL_5:
+            FUART_Disable(obj->FUART);
+            if (type == FlowControlCTS) {
+                MBED_ASSERT(uart_cts != (UARTName) NC);
+
+                // Enable CTS hardware flow control
+                obj->FUART->CR |= FUART_CTS_FLOW_CTRL;
+
+                // Enable the pin for CTS and RTS function
+                pinmap_pinout(txflow, PinMap_UART_CTS);
+            } else if (type == FlowControlRTS) {
+                MBED_ASSERT(uart_rts != (UARTName) NC);
+
+                // Enable RTS hardware flow control
+                obj->FUART->CR |= FUART_RTS_FLOW_CTRL;
+
+                // Enable the pin for RTS function
+                pinmap_pinout(rxflow, PinMap_UART_RTS);
+            } else if (type == FlowControlRTSCTS) {
+                MBED_ASSERT(uart_name != (UARTName) NC);
+
+                // Enable CTS and RTS hardware flow control
+                obj->FUART->CR |= FUART_CTS_FLOW_CTRL | FUART_RTS_FLOW_CTRL;
+
+                // Enable the pin for CTS and RTS function
+                pinmap_pinout(txflow, PinMap_UART_CTS);
+                pinmap_pinout(rxflow, PinMap_UART_RTS);
+            } else {
+                // Disable CTS and RTS hardware flow control
+                obj->FUART->CR &= (uint32_t) 0xFFFF0FFF;
+            }
+            FUART_Enable(obj->FUART);
+            break;
+    }
+}
+
+// Pause transmission
+void serial_break_set(serial_t *obj)
+{
+    if (obj->index == SERIAL_4 || obj->index == SERIAL_5) {
+        FUART_SetSendBreak(obj->FUART, ENABLE);
+    }
+}
+
+// Switch to normal transmission
+void serial_break_clear(serial_t *obj)
+{
+    if (obj->index == SERIAL_4 || obj->index == SERIAL_5) {
+        FUART_SetSendBreak(obj->FUART, DISABLE);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/sleep.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+
+// Number of warm-up cycle = warm-up time to set / input frequency cycle (s)
+// Number of 3*10^-6 (s) / (1/12 (MHz)) = 60000 = 0xea60
+#define CG_WUODR_INT     ((uint16_t)0xea60)
+
+static void external_losc_enable(void);
+
+void hal_sleep(void)
+{
+    // Set low power consumption mode IDLE
+    CG_SetSTBYMode(CG_STBY_MODE_IDLE);
+    // Enter idle mode
+    __WFI();
+}
+
+void hal_deepsleep(void)
+{
+    // Set low power consumption mode STOP1
+    CG_SetSTBYMode(CG_STBY_MODE_STOP1);
+    // Setup warm up time
+    CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_EXT_HIGH, CG_WUODR_INT);
+    // Enter stop1 mode
+    __WFI();
+    // Switch over from IHOSC to EHOSC
+    external_losc_enable();
+}
+
+static void external_losc_enable(void)
+{
+    // Enable high-speed oscillator
+    CG_SetFosc(CG_FOSC_OSC_EXT, ENABLE);
+    // Select internal(fIHOSC) as warm-up clock
+    CG_SetWarmUpTime(CG_WARM_UP_SRC_OSC_INT_HIGH, CG_WUODR_INT);
+    // Start warm-up
+    CG_StartWarmUp();
+    // Wait until EHOSC become stable
+    while (CG_GetWarmUpState() != DONE) {
+        // Do nothing
+    }
+
+    // Set fosc source
+    CG_SetFoscSrc(CG_FOSC_OSC_EXT);
+    // Wait for <OSCSEL> to become "1"
+    while (CG_GetFoscSrc() != CG_FOSC_OSC_EXT) {
+        // Do nothing
+    }
+
+    // Stop IHOSC
+    CG_SetFosc(CG_FOSC_OSC_INT, DISABLE);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/spi_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,283 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "spi_api.h"
+#include "mbed_error.h"
+#include "pinmap.h"
+#include "tmpm46b_ssp.h"
+
+static const PinMap PinMap_SPI_SCLK[] = {
+    {PK4, SPI_0, PIN_DATA(2, 1)},
+    {PF3, SPI_1, PIN_DATA(5, 1)},
+    {PD3, SPI_2, PIN_DATA(1, 1)},
+    {NC,  NC,    0}
+};
+
+static const PinMap PinMap_SPI_MOSI[] = {
+    {PK3, SPI_0, PIN_DATA(2, 1)},
+    {PF4, SPI_1, PIN_DATA(5, 1)},
+    {PD2, SPI_2, PIN_DATA(1, 1)},
+    {NC,  NC,    0}
+};
+
+static const PinMap PinMap_SPI_MISO[] = {
+    {PK2, SPI_0, PIN_DATA(2, 0)},
+    {PF5, SPI_1, PIN_DATA(5, 0)},
+    {PD1, SPI_2, PIN_DATA(1, 0)},
+    {NC,  NC,    0}
+};
+
+static const PinMap PinMap_SPI_SSEL[] = {
+    {PK1, SPI_0, PIN_DATA(2, 1)},
+    {PF6, SPI_1, PIN_DATA(5, 1)},
+    {PD0, SPI_2, PIN_DATA(1, 1)},
+    {NC,  NC,    0}
+};
+
+#define TMPM46B_SPI_2_FMAX    20000000
+#define TMPM46B_SPI_FMAX      10000000
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    SSP_InitTypeDef config;
+
+    // Check pin parameters
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+    obj->module = (SPIName)pinmap_merge(spi_data, spi_sclk);
+    obj->module = (SPIName)pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT((int)obj->module!= NC);
+
+    // Identify SPI module to use
+    switch ((int)obj->module) {
+        case SPI_0:
+            obj->spi = TSB_SSP0;
+            break;
+        case SPI_1:
+            obj->spi = TSB_SSP1;
+            break;
+        case SPI_2:
+            obj->spi = TSB_SSP2;
+            break;
+        default:
+            obj->spi= NULL;
+            obj->module = (SPIName)NC;
+            error("Cannot found SPI module corresponding with input pins.");
+            break;
+    }
+
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+
+    // Declare Config
+    config.FrameFormat = SSP_FORMAT_SPI;
+
+    // bit_rate = Fsys / (clk_prescale * (clk_rate + 1))
+    config.PreScale = 48;
+    config.ClkRate = 0;
+
+    config.ClkPolarity = SSP_POLARITY_LOW;
+    config.ClkPhase = SSP_PHASE_FIRST_EDGE;
+    config.DataSize = 0x08;
+
+    obj->bits = config.DataSize;
+    config.Mode = SSP_MASTER;
+    SSP_Init(obj->spi, &config);
+
+    // Disable all interrupt
+
+    SSP_SetINTConfig(obj->spi, SSP_INTCFG_NONE);
+    SSP_Enable(obj->spi);
+}
+
+void spi_free(spi_t *obj)
+{
+    SSP_Disable(obj->spi);
+    obj->spi = NULL;
+    obj->module = (SPIName)NC;
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    TSB_SSP_TypeDef* spi;
+    MBED_ASSERT(slave == SSP_MASTER);   // Master mode only
+
+    spi = obj->spi;
+
+    SSP_Disable(spi);
+
+    obj->bits = bits;
+
+    SSP_SetDataSize(spi, bits);
+    SSP_SetClkPolarity(spi, (SSP_ClkPolarity)(mode & 0x1));
+    SSP_SetClkPhase(spi, (SSP_ClkPhase)((mode >> 1) & 0x1));
+
+    SSP_Enable(spi);
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+    TSB_SSP_TypeDef* spi;
+
+    // Search Freq data
+    int fr_gear = 1;
+    int cur_hz = 1;
+    int32_t best_diff = TMPM46B_SPI_FMAX;
+    int best_cpsdvsr = 254;
+    int best_scr = 255;
+    int cur_cpsdvsr = 48;
+    int cur_scr = 0;
+    int32_t diff;
+
+    /* Assert Min frequency
+       Hz = Fsys / (CPSDVSR * (SCR + 1))
+       Domain value of CPSDVSR is an even number between 2 to 254
+       Domain value of SCR is a number between 0 to 255
+       Hz Min if CPSDVSR and SCR max (CPSDVSR = 254, SCR = 255)
+    */
+    MBED_ASSERT((SystemCoreClock / 65024) <= (uint32_t)hz);
+
+    if (obj->module == SPI_2) {
+        MBED_ASSERT(hz <= TMPM46B_SPI_2_FMAX);
+    } else {
+        MBED_ASSERT(hz <= TMPM46B_SPI_FMAX); // Default value of SPI_0, SPI_1, SPI_2
+    }
+
+    spi = obj->spi;
+    fr_gear = SystemCoreClock / hz;
+    if (fr_gear < 48) {
+        cur_cpsdvsr = fr_gear;
+    }
+    while (best_diff != 0 && cur_cpsdvsr <= 254) {
+        cur_scr = fr_gear / cur_cpsdvsr - 1;
+
+        if (cur_scr < 0) {
+            break;
+        }
+
+        for (; cur_scr < 256; ++cur_scr) {
+            cur_hz = SystemCoreClock / (cur_cpsdvsr * (1 + cur_scr));
+
+            diff = cur_hz - hz;
+
+            if (diff < 0) {
+                diff = -diff;
+            }
+
+            if (diff < best_diff) {
+                best_cpsdvsr = cur_cpsdvsr;
+                best_scr = cur_scr;
+                best_diff = diff;
+            } else if (diff >= best_diff) {
+                break;
+            }
+        }
+
+        cur_cpsdvsr += 2;
+    }
+
+    SSP_Disable(spi);
+    // Set bit rate of SPI
+    SSP_SetClkPreScale(spi, (uint8_t)best_cpsdvsr, (uint8_t)best_scr);
+    SSP_Enable(spi);
+}
+
+static void spi_clear_FIFOs(TSB_SSP_TypeDef *spi)
+{
+    SSP_FIFOState tx_buf_state, rx_buf_state;
+
+    do {
+        while (SSP_GetWorkState(spi) == BUSY);
+
+        // Get data from receive FIFO
+        SSP_GetRxData(spi);
+
+        // Check receive FIFO
+        rx_buf_state = SSP_GetFIFOState(spi, SSP_RX);
+
+        // Check transmit FIFO
+        tx_buf_state = SSP_GetFIFOState(spi, SSP_TX);
+    } while (rx_buf_state != SSP_FIFO_EMPTY || tx_buf_state != SSP_FIFO_EMPTY);
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+    TSB_SSP_TypeDef* spi;
+
+    spi = obj->spi;
+    // Clear all data in transmit FIFO and receive FIFO
+    spi_clear_FIFOs(spi);
+    // Transmit data
+    SSP_SetTxData(spi, value);
+    // Wait for transmitting
+    while (SSP_GetWorkState(spi) == BUSY);
+    // Read received data
+    value = SSP_GetRxData(spi);
+
+    return value;
+}
+
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
+                           char *rx_buffer, int rx_length, char write_fill)
+{
+    int total = (tx_length > rx_length) ? tx_length : rx_length;
+
+    for (int i = 0; i < total; i++) {
+        char out = (i < tx_length) ? tx_buffer[i] : write_fill;
+        char in = spi_master_write(obj, out);
+        if (i < rx_length) {
+            rx_buffer[i] = in;
+        }
+    }
+
+    return total;
+}
+
+int spi_busy(spi_t *obj)
+{
+    WorkState state;
+    state = SSP_GetWorkState(obj->spi);
+    return (state == BUSY);
+}
+
+uint8_t spi_get_module(spi_t *obj)
+{
+    return (uint8_t)(obj->module);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/trng_api.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_error.h"
+#include "tmpm46b_esg.h"
+#include "trng_api.h"
+
+static Result ESG_Config(void)
+{
+    Result ret = ERROR;
+    uint16_t Fintming = 560U;
+
+    // Confirm the ESG core stops
+    if (ESG_GetCalculationStatus() == ESG_CALCULATION_COMPLETE) {
+        // Confirm no interrupt generation
+        if (ESG_GetIntStatus() == DISABLE) {
+            // Set the latch timing & output timing
+            if ((ESG_SetLatchTiming(ESG_LATCH_TIMING_1) == SUCCESS) &&
+                (ESG_SetFintiming(Fintming) == SUCCESS)) {
+                ret = SUCCESS;
+            }
+        }
+    }
+    return ret;
+}
+
+void trng_init(trng_t *obj)
+{
+    // Enable clock supply
+    CG_SetFcPeriphB(CG_FC_PERIPH_ESG, ENABLE);
+    // Initialise ESG core & Start up the ESG core
+    if ((ESG_Config() == SUCCESS) && (ESG_Startup() == SUCCESS)) {
+        obj->trng_init = true;
+    } else {
+        error("TRNG is not Initialised");
+        obj->trng_init = false;
+    }
+}
+
+void trng_free(trng_t *obj)
+{
+    ESG_IPReset();
+    // Disable clock supply
+    CG_SetFcPeriphB(CG_FC_PERIPH_ESG, DISABLE);
+    obj->trng_init = false;
+}
+
+int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
+{
+    volatile uint8_t random[64] = {0};
+    uint8_t i;
+    Result ret = ERROR;
+
+    *output_length = 0;
+
+    if (!obj->trng_init) {
+        error("TRNG is not Initialised");
+        return FAIL; // fail i.e. -1 
+    }
+
+    while (ESG_GetIntStatus() == DISABLE) {
+        // Wait for ESG core for generating an interrupt
+    }
+    // Interrupt clearing
+    ret = ESG_ClrInt();
+    if (ret == ERROR) {
+        return FAIL; // fail i.e. -1 
+    }
+    // Get the calculation result
+    ESG_GetResult((uint32_t*)random); //512-bit entropy
+
+    for (i = 0; (i < 64) && (i < length); i++) {
+        *output++ = random[i];
+        // clear the buffer
+        random[i] = 0;
+    }
+    *output_length = i;
+    //clear and restart the ESG core
+    ESG_IPReset();
+    ret |= ESG_Startup();
+    if (ret == ERROR) {
+        return FAIL; // fail i.e. -1
+    }
+
+    return ret;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_TOSHIBA/TARGET_TMPM46B/us_ticker.c	Thu Apr 19 17:12:19 2018 +0100
@@ -0,0 +1,133 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2017 All rights reserved
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "us_ticker_api.h"
+#include "tmpm46b_tmrb.h"
+
+#define TMR16A_100US          0xFFFF
+#define TMRB_CLK_DIV          0x3
+
+static uint8_t us_ticker_inited = 0;                // Is ticker initialized yet?
+static volatile uint32_t us_ticker = 0;             // timer counter
+
+const ticker_info_t* us_ticker_get_info()
+{
+    static const ticker_info_t info = {
+        1875000, // 1875000,
+        16       // 16 bit counter
+    };
+    return &info;
+}
+
+// initialize us_ticker
+void us_ticker_init(void)
+{
+    TMRB_InitTypeDef m_tmrb0;
+    TMRB_FFOutputTypeDef FFStruct;
+
+    if (us_ticker_inited) {
+        return;
+    }
+    us_ticker_inited = 1;
+
+    // Enable channel 0
+    TMRB_Enable(TSB_TB0);
+    // Stops and clear count operation
+    TMRB_SetRunState(TSB_TB0, TMRB_STOP);
+    // Disable to TBxFF0 reverse trigger
+    FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
+    FFStruct.FlipflopReverseTrg =TMRB_DISABLE_FLIPFLOP;
+    TMRB_SetFlipFlop(TSB_TB0, &FFStruct);
+
+    // TSB_TB0 using free-run
+    m_tmrb0.Mode = TMRB_INTERVAL_TIMER;
+    m_tmrb0.ClkDiv = TMRB_CLK_DIV;
+    m_tmrb0.UpCntCtrl = TMRB_AUTO_CLEAR;
+    m_tmrb0.TrailingTiming = TMR16A_100US;
+    m_tmrb0.LeadingTiming = TMR16A_100US;
+    TMRB_Init(TSB_TB0, &m_tmrb0);
+
+    // Enable TMRB when system is in idle mode
+    TMRB_SetIdleMode(TSB_TB0, ENABLE);
+    // Starts TSB_TB0
+    TMRB_SetRunState(TSB_TB0, TMRB_RUN);
+}
+
+uint32_t us_ticker_read(void)
+{
+    uint32_t ret_val = 0;
+
+    if (!us_ticker_inited) {
+        us_ticker_init();
+    }
+
+    ret_val = (uint32_t)TMRB_GetUpCntValue(TSB_TB0);
+
+    return ret_val;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    TMRB_InitTypeDef m_tmrb1;
+    TMRB_FFOutputTypeDef FFStruct;
+
+    const uint32_t now_ticks = us_ticker_read();
+    uint32_t delta_ticks =
+        timestamp >= now_ticks ? timestamp - now_ticks : (uint32_t)((uint64_t) timestamp + 0xFFFF - now_ticks);
+
+    if (delta_ticks == 0) {
+        /* The requested delay is less than the minimum resolution of this counter. */
+        delta_ticks = 1;
+    }
+
+    // Ticker interrupt handle
+    TMRB_Enable(TSB_TB1);
+    TMRB_SetRunState(TSB_TB1, TMRB_STOP);
+    NVIC_SetVector(INTTB1_IRQn, (uint32_t)us_ticker_irq_handler);
+    NVIC_EnableIRQ(INTTB1_IRQn);
+
+    // Split delta for preventing the Multiply overflowing
+    FFStruct.FlipflopCtrl = TMRB_FLIPFLOP_CLEAR;
+    FFStruct.FlipflopReverseTrg = TMRB_DISABLE_FLIPFLOP;
+    TMRB_SetFlipFlop(TSB_TB1, &FFStruct);
+
+    // TSB_TB0 using free-run
+    m_tmrb1.Mode = TMRB_INTERVAL_TIMER;
+    m_tmrb1.ClkDiv = TMRB_CLK_DIV;
+    m_tmrb1.UpCntCtrl = TMRB_AUTO_CLEAR;
+    m_tmrb1.TrailingTiming = delta_ticks;
+    m_tmrb1.LeadingTiming = delta_ticks;
+    TMRB_Init(TSB_TB1, &m_tmrb1);
+    TMRB_SetINTMask(TSB_TB1,TMRB_MASK_OVERFLOW_INT | TMRB_MASK_MATCH_LEADING_INT);
+    // Enable TMRB when system is in idle mode
+    TMRB_SetIdleMode(TSB_TB1, ENABLE);
+    TMRB_SetRunState(TSB_TB1, TMRB_RUN);
+}
+
+void us_ticker_fire_interrupt(void)
+{
+    NVIC_SetPendingIRQ(INTTB1_IRQn);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+    // Also disable interrupts by NVIC
+    NVIC_DisableIRQ(INTTB1_IRQn);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+    // No flag to clear
+}

--- a/targets/TARGET_TOSHIBA/mbed_rtx.h	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/TARGET_TOSHIBA/mbed_rtx.h	Thu Apr 19 17:12:19 2018 +0100
@@ -25,4 +25,12 @@
 
 #endif
 
+#if defined(TARGET_TMPM46B)
+
+#ifndef INITIAL_SP
+#define INITIAL_SP                        (0x20080000UL)
+#endif
+
+#endif
+
 #endif  // MBED_MBED_RTX_H

--- a/targets/targets.json	Tue Mar 20 17:01:51 2018 +0000
+++ b/targets/targets.json	Thu Apr 19 17:12:19 2018 +0100
@@ -742,7 +742,7 @@
         "macros": ["CPU_LPC54114J256BD64_cm4", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
         "detect_code": ["1054"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name" : "LPC54114J256BD64"
     },
@@ -753,7 +753,7 @@
         "is_disk_virtual": true,
         "macros": ["CPU_LPC54628J512ET180", "FSL_RTOS_MBED"],
         "inherits": ["Target"],
-        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
+        "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES", "FLASH"],
         "features": ["LWIP"],
         "device_name" : "LPC54628J512ET180"
     },
@@ -1531,7 +1531,7 @@
         "device_name": "STM32L433RC",
         "bootloader_supported": true
     },
-	"MTB_ADV_WISE_1510": {
+    "MTB_ADV_WISE_1510": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO"],
         "core": "Cortex-M4F",
@@ -1609,7 +1609,7 @@
             }
         },
         "detect_code": ["0827"],
-        "macros_add": ["USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT"],
+        "macros_add": ["USBHOST_OTHER", "MBEDTLS_CONFIG_HW_SUPPORT", "TWO_RAM_REGIONS"],
         "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "STM32L486RG"
@@ -1626,10 +1626,11 @@
             }
         },
         "detect_code": ["0460"],
-        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "WISE_1570"],
+        "macros_add": ["MBEDTLS_CONFIG_HW_SUPPORT", "WISE_1570", "TWO_RAM_REGIONS"],
         "device_has_add": ["ANALOGOUT", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
         "release_versions": ["5"],
-        "device_name": "STM32L486RG"
+        "device_name": "STM32L486RG",
+        "OUTPUT_EXT": "hex"
     },
     "ARCH_MAX": {
         "inherits": ["FAMILY_STM32"],
@@ -2027,6 +2028,17 @@
         "device_name": "STM32L151CC",
         "bootloader_supported": true
     },
+    "MTB_RAK811": {
+        "inherits": ["FAMILY_STM32"],
+        "core": "Cortex-M3",
+        "default_toolchain": "ARM",
+        "extra_labels_add": ["STM32L1", "STM32L151xBA", "STM32L151CBA"],
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "device_has_add": ["ANALOGOUT"],
+        "release_versions": ["5"],
+        "device_name": "STM32L151CBxxA",
+        "bootloader_supported": true
+    },
     "MOTE_L152RC": {
         "inherits": ["FAMILY_STM32"],
         "core": "Cortex-M3",
@@ -2663,8 +2675,9 @@
         "core": "Cortex-M3",
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "extra_labels": ["ARM_SSG", "CM3DS_MPS2"],
+        "OUTPUT_EXT": "elf",
         "macros": ["CMSDK_CM3DS"],
-        "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC"],
+        "device_has": ["ANALOGIN", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SPI", "RTC", "LOWPOWERTIMER"],
         "release_versions": ["2", "5"],
         "copy_method": "mps2",
         "reset_method": "reboot.txt"
@@ -2697,8 +2710,8 @@
     },
     "VK_RZ_A1H": {
         "inherits": ["RZ_A1XX"],
-        "extra_labels": ["RZA1H", "VKRZA1H"],
-        "release_versions": []
+        "extra_labels_add": ["RZA1H", "VKRZA1H"],
+        "release_versions": ["2", "5"]
     },
     "GR_LYCHEE": {
         "inherits": ["RZ_A1XX"],
@@ -2762,13 +2775,13 @@
         "extra_labels": ["Maxim", "MAX32630"],
         "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
         "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
-		"features": ["BLE"],
+        "features": ["BLE"],
         "release_versions": ["2", "5"]
     },
     "EFM32": {
         "inherits": ["Target"],
         "extra_labels": ["Silicon_Labs", "EFM32"],
-        "macros": ["MBEDTLS_CONFIG_HW_SUPPORT"],
+        "macros": ["MBEDTLS_CONFIG_HW_SUPPORT", "MBED_TICKLESS"],
         "public": false
     },
     "EFM32GG990F1024": {
@@ -2785,7 +2798,7 @@
     "EFM32GG_STK3700": {
         "inherits": ["EFM32GG990F1024"],
         "progen": {"target": "efm32gg-stk"},
-        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH"],
+        "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "FLASH", "ITM"],
         "forced_reset_timeout": 2,
         "config": {
             "hf_clock_src": {
@@ -3493,7 +3506,7 @@
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF52"],
         "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "FLASH"],
         "release_versions": ["2", "5"],
         "device_name": "nRF52832_xxAA"
     },
@@ -3509,7 +3522,7 @@
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF52"],
         "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
-        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "FLASH"],
+        "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
         "release_versions": ["2", "5"],
         "device_name": "nRF52832_xxAA"
     },
@@ -3581,7 +3594,7 @@
         "inherits": ["Target"],
         "core": "Cortex-M4F",
         "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"],
-        "device_has": ["STCLK_OFF_DURING_SLEEP"],
+        "device_has": ["STCLK_OFF_DURING_SLEEP", "ITM"],
         "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5", "SDK13", "NRF52_COMMON"],
         "OUTPUT_EXT": "hex",
         "is_disk_virtual": true,
@@ -3759,7 +3772,7 @@
             }
         },
         "inherits": ["Target"],
-        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\""],
+        "macros": ["CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"","MBED_FAULT_HANDLER_DISABLED"],
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
         "release_versions": ["5"],
         "device_name": "NANO130KE3BN"
@@ -3797,7 +3810,7 @@
         "inherits": ["Target"],
         "detect_code": ["4600"],
         "extra_labels": ["Realtek", "AMEBA", "RTL8195A"],
-        "macros": ["__RTL8195A__","CONFIG_PLATFORM_8195A","CONFIG_MBED_ENABLED","PLATFORM_CMSIS_RTOS"],
+        "macros": ["__RTL8195A__","CONFIG_PLATFORM_8195A","CONFIG_MBED_ENABLED","PLATFORM_CMSIS_RTOS","MBED_FAULT_HANDLER_DISABLED"],
         "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
         "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "TRNG", "EMAC", "FLASH"],
         "features": ["LWIP"],
@@ -3839,6 +3852,27 @@
         "release_versions": ["2"],
         "device_name": "nRF51822_xxAC"
     },
+    "DISCO_L496AG": {
+        "inherits": ["FAMILY_STM32"],
+        "supported_form_factors": ["ARDUINO"],
+        "core": "Cortex-M4F",
+        "extra_labels_add": ["STM32L4", "STM32L496AG", "STM32L496xG"],
+        "config": {
+            "clock_source": {
+                "help": "Mask value : USE_PLL_HSE_EXTC (need HW patch) | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI | USE_PLL_MSI",
+                "value": "USE_PLL_MSI",
+                "macro_name": "CLOCK_SOURCE"
+            },
+            "lowpowertimer_lptim": {
+                "help": "This target supports LPTIM. Set value 1 to use LPTIM for LOWPOWERTIMER, or 0 to use RTC wakeup timer",
+                "value": 1
+            }
+        },
+        "detect_code": ["0822"],
+        "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
+        "release_versions": ["2", "5"],
+        "device_name": "STM32L496AG"
+    },
     "NUCLEO_L496ZG": {
         "inherits": ["FAMILY_STM32"],
         "supported_form_factors": ["ARDUINO", "MORPHO"],
@@ -3940,5 +3974,18 @@
         "device_has_add": ["LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "FLASH"],
         "release_versions": ["2"],
         "device_name": "STM32F411RE"
+    },
+    "TMPM46B": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4",
+        "is_disk_virtual": true,
+        "extra_labels": ["TOSHIBA"],
+        "macros": ["__TMPM46B__"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "device_has": ["ANALOGIN", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SERIAL_FC", "SPI", "I2C", "STDIO_MESSAGES", "TRNG", "FLASH", "SLEEP"],
+        "device_name": "TMPM46BF10FG",
+        "detect_code": ["7013"],
+        "release_versions": ["5"],
+        "bootloader_supported": true
     }
 }