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TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5
Child:
96:487b796308b0
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_rcc.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 18-June-2014
bogdanm 84:0b3ab51c8877 7 * @brief Header file of RCC HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
bogdanm 84:0b3ab51c8877 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_RCC_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_RCC_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
bogdanm 84:0b3ab51c8877 53 /** @addtogroup RCC
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 /* Exported types ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 58
bogdanm 84:0b3ab51c8877 59 /**
bogdanm 84:0b3ab51c8877 60 * @brief RCC PLL configuration structure definition
bogdanm 84:0b3ab51c8877 61 */
bogdanm 84:0b3ab51c8877 62 typedef struct
bogdanm 84:0b3ab51c8877 63 {
bogdanm 84:0b3ab51c8877 64 uint32_t PLLState; /*!< The new state of the PLL.
bogdanm 84:0b3ab51c8877 65 This parameter can be a value of @ref RCC_PLL_Config */
bogdanm 84:0b3ab51c8877 66
bogdanm 84:0b3ab51c8877 67 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
bogdanm 84:0b3ab51c8877 68 This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm 84:0b3ab51c8877 69
bogdanm 84:0b3ab51c8877 70 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
bogdanm 92:4fc01daae5a5 71 This parameter must of @ref RCC_PLLMultiplication_Factor */
bogdanm 84:0b3ab51c8877 72
bogdanm 84:0b3ab51c8877 73 uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
bogdanm 84:0b3ab51c8877 74 This parameter must be a value of @ref RCC_PLLDivider_Factor */
bogdanm 84:0b3ab51c8877 75
bogdanm 84:0b3ab51c8877 76 }RCC_PLLInitTypeDef;
bogdanm 84:0b3ab51c8877 77
bogdanm 84:0b3ab51c8877 78 /**
bogdanm 84:0b3ab51c8877 79 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm 84:0b3ab51c8877 80 */
bogdanm 84:0b3ab51c8877 81 typedef struct
bogdanm 84:0b3ab51c8877 82 {
bogdanm 84:0b3ab51c8877 83 uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm 84:0b3ab51c8877 84 This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm 84:0b3ab51c8877 85
bogdanm 84:0b3ab51c8877 86 uint32_t HSEState; /*!< The new state of the HSE.
bogdanm 84:0b3ab51c8877 87 This parameter can be a value of @ref RCC_HSE_Config */
bogdanm 84:0b3ab51c8877 88
bogdanm 84:0b3ab51c8877 89 uint32_t LSEState; /*!< The new state of the LSE.
bogdanm 84:0b3ab51c8877 90 This parameter can be a value of @ref RCC_LSE_Config */
bogdanm 84:0b3ab51c8877 91
bogdanm 84:0b3ab51c8877 92 uint32_t HSIState; /*!< The new state of the HSI.
bogdanm 84:0b3ab51c8877 93 This parameter can be a value of @ref RCC_HSI_Config */
bogdanm 84:0b3ab51c8877 94
bogdanm 84:0b3ab51c8877 95 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm 84:0b3ab51c8877 96 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm 84:0b3ab51c8877 97
bogdanm 84:0b3ab51c8877 98 uint32_t LSIState; /*!< The new state of the LSI.
bogdanm 84:0b3ab51c8877 99 This parameter can be a value of @ref RCC_LSI_Config */
bogdanm 84:0b3ab51c8877 100
bogdanm 84:0b3ab51c8877 101 uint32_t HSI48State; /*!< The new state of the HSI48.
bogdanm 84:0b3ab51c8877 102 This parameter can be a value of @ref RCC_HSI48_Config */
bogdanm 84:0b3ab51c8877 103
bogdanm 84:0b3ab51c8877 104 uint32_t MSIState; /*!< The new state of the MSI.
bogdanm 84:0b3ab51c8877 105 This parameter can be a value of @ref RCC_MSI_Config */
bogdanm 84:0b3ab51c8877 106
bogdanm 84:0b3ab51c8877 107 uint32_t MSICalibrationValue; /*!< The calibration trimming value.
bogdanm 84:0b3ab51c8877 108 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
bogdanm 84:0b3ab51c8877 109
bogdanm 84:0b3ab51c8877 110 uint32_t MSIClockRange; /*!< The MSI frequency range.
bogdanm 84:0b3ab51c8877 111 This parameter can be a value of @ref RCC_MSI_Clock_Range */
bogdanm 84:0b3ab51c8877 112
bogdanm 84:0b3ab51c8877 113 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
bogdanm 84:0b3ab51c8877 114
bogdanm 84:0b3ab51c8877 115 }RCC_OscInitTypeDef;
bogdanm 84:0b3ab51c8877 116
bogdanm 84:0b3ab51c8877 117 /**
bogdanm 84:0b3ab51c8877 118 * @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm 84:0b3ab51c8877 119 */
bogdanm 84:0b3ab51c8877 120 typedef struct
bogdanm 84:0b3ab51c8877 121 {
bogdanm 84:0b3ab51c8877 122 uint32_t ClockType; /*!< The clock to be configured.
bogdanm 84:0b3ab51c8877 123 This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm 84:0b3ab51c8877 124
bogdanm 84:0b3ab51c8877 125 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm 84:0b3ab51c8877 126 This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm 84:0b3ab51c8877 127
bogdanm 84:0b3ab51c8877 128 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm 84:0b3ab51c8877 129 This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm 84:0b3ab51c8877 130
bogdanm 84:0b3ab51c8877 131 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 84:0b3ab51c8877 132 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 84:0b3ab51c8877 133
bogdanm 84:0b3ab51c8877 134 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm 84:0b3ab51c8877 135 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm 84:0b3ab51c8877 136
bogdanm 84:0b3ab51c8877 137 }RCC_ClkInitTypeDef;
bogdanm 84:0b3ab51c8877 138
bogdanm 84:0b3ab51c8877 139 /* Exported constants --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 140 /** @defgroup RCC_Exported_Constants
bogdanm 84:0b3ab51c8877 141 * @{
bogdanm 84:0b3ab51c8877 142 */
bogdanm 84:0b3ab51c8877 143
bogdanm 84:0b3ab51c8877 144 /** @defgroup RCC_BitAddress_AliasRegion
bogdanm 84:0b3ab51c8877 145 * @brief RCC registers bit address in the alias region
bogdanm 84:0b3ab51c8877 146 * @{
bogdanm 84:0b3ab51c8877 147 */
bogdanm 84:0b3ab51c8877 148 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm 84:0b3ab51c8877 149 /* --- CR Register ---*/
bogdanm 84:0b3ab51c8877 150 /* Alias word address of HSION bit */
bogdanm 84:0b3ab51c8877 151 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm 84:0b3ab51c8877 152 /* --- CFGR Register ---*/
bogdanm 84:0b3ab51c8877 153 /* Alias word address of I2SSRC bit */
bogdanm 84:0b3ab51c8877 154 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
bogdanm 84:0b3ab51c8877 155 /* --- CSR Register ---*/
bogdanm 84:0b3ab51c8877 156 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
bogdanm 84:0b3ab51c8877 157
bogdanm 84:0b3ab51c8877 158 /* CR register byte 3 (Bits[23:16]) base address */
bogdanm 84:0b3ab51c8877 159 #define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
bogdanm 84:0b3ab51c8877 160
bogdanm 84:0b3ab51c8877 161 /* CIER register byte 0 (Bits[0:8]) base address */
bogdanm 84:0b3ab51c8877 162 #define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
bogdanm 84:0b3ab51c8877 163
bogdanm 84:0b3ab51c8877 164 #define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
bogdanm 84:0b3ab51c8877 165 #define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 84:0b3ab51c8877 166
bogdanm 84:0b3ab51c8877 167 /**
bogdanm 84:0b3ab51c8877 168 * @}
bogdanm 84:0b3ab51c8877 169 */
bogdanm 84:0b3ab51c8877 170
bogdanm 84:0b3ab51c8877 171 /** @defgroup RCC_Oscillator_Type
bogdanm 84:0b3ab51c8877 172 * @{
bogdanm 84:0b3ab51c8877 173 */
bogdanm 84:0b3ab51c8877 174 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 175 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 176 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 177 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 178 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 179 #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 180 #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 181
bogdanm 92:4fc01daae5a5 182 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 0x3F)
bogdanm 92:4fc01daae5a5 183
bogdanm 84:0b3ab51c8877 184 /**
bogdanm 84:0b3ab51c8877 185 * @}
bogdanm 84:0b3ab51c8877 186 */
bogdanm 84:0b3ab51c8877 187
bogdanm 84:0b3ab51c8877 188 /** @defgroup RCC_HSE_Config
bogdanm 84:0b3ab51c8877 189 * @{
bogdanm 84:0b3ab51c8877 190 */
bogdanm 84:0b3ab51c8877 191 #define RCC_HSE_OFF ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 192 #define RCC_HSE_ON RCC_CR_HSEON
bogdanm 84:0b3ab51c8877 193 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
bogdanm 84:0b3ab51c8877 194
bogdanm 84:0b3ab51c8877 195 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
bogdanm 84:0b3ab51c8877 196 ((HSE) == RCC_HSE_BYPASS))
bogdanm 84:0b3ab51c8877 197 /**
bogdanm 84:0b3ab51c8877 198 * @}
bogdanm 84:0b3ab51c8877 199 */
bogdanm 84:0b3ab51c8877 200
bogdanm 84:0b3ab51c8877 201 /** @defgroup RCC_LSE_Config
bogdanm 84:0b3ab51c8877 202 * @{
bogdanm 84:0b3ab51c8877 203 */
bogdanm 84:0b3ab51c8877 204 #define RCC_LSE_OFF ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 205 #define RCC_LSE_ON RCC_CSR_LSEON
bogdanm 84:0b3ab51c8877 206 #define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON))
bogdanm 84:0b3ab51c8877 207
bogdanm 84:0b3ab51c8877 208 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
bogdanm 84:0b3ab51c8877 209 ((LSE) == RCC_LSE_BYPASS))
bogdanm 84:0b3ab51c8877 210 /**
bogdanm 84:0b3ab51c8877 211 * @}
bogdanm 84:0b3ab51c8877 212 */
bogdanm 84:0b3ab51c8877 213
bogdanm 84:0b3ab51c8877 214 /** @defgroup RCC_HSI_Config
bogdanm 84:0b3ab51c8877 215 * @{
bogdanm 84:0b3ab51c8877 216 */
bogdanm 84:0b3ab51c8877 217 #define RCC_HSI_OFF ((uint8_t)0x00)
bogdanm 84:0b3ab51c8877 218 #define RCC_HSI_ON ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 219 #define RCC_HSI_DIV4 ((uint8_t)0x09)
bogdanm 84:0b3ab51c8877 220 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \
bogdanm 84:0b3ab51c8877 221 ((HSI) == RCC_HSI_DIV4))
bogdanm 84:0b3ab51c8877 222
bogdanm 84:0b3ab51c8877 223 /**
bogdanm 84:0b3ab51c8877 224 * @}
bogdanm 84:0b3ab51c8877 225 */
bogdanm 84:0b3ab51c8877 226
bogdanm 92:4fc01daae5a5 227 /** @defgroup RCC_MSI_Clock_Range
bogdanm 84:0b3ab51c8877 228 * @{
bogdanm 84:0b3ab51c8877 229 */
bogdanm 84:0b3ab51c8877 230
bogdanm 84:0b3ab51c8877 231 #define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */
bogdanm 84:0b3ab51c8877 232 #define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
bogdanm 84:0b3ab51c8877 233 #define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
bogdanm 84:0b3ab51c8877 234 #define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
bogdanm 84:0b3ab51c8877 235 #define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */
bogdanm 84:0b3ab51c8877 236 #define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */
bogdanm 84:0b3ab51c8877 237 #define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */
bogdanm 84:0b3ab51c8877 238
bogdanm 84:0b3ab51c8877 239 #define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRANGE_0) || \
bogdanm 84:0b3ab51c8877 240 ((RANGE) == RCC_MSIRANGE_1) || \
bogdanm 84:0b3ab51c8877 241 ((RANGE) == RCC_MSIRANGE_2) || \
bogdanm 84:0b3ab51c8877 242 ((RANGE) == RCC_MSIRANGE_3) || \
bogdanm 84:0b3ab51c8877 243 ((RANGE) == RCC_MSIRANGE_4) || \
bogdanm 84:0b3ab51c8877 244 ((RANGE) == RCC_MSIRANGE_5) || \
bogdanm 84:0b3ab51c8877 245 ((RANGE) == RCC_MSIRANGE_6))
bogdanm 84:0b3ab51c8877 246
bogdanm 84:0b3ab51c8877 247 /**
bogdanm 84:0b3ab51c8877 248 * @}
bogdanm 84:0b3ab51c8877 249 */
bogdanm 84:0b3ab51c8877 250
bogdanm 92:4fc01daae5a5 251 /** @defgroup RCC_LSI_Config
bogdanm 84:0b3ab51c8877 252 * @{
bogdanm 84:0b3ab51c8877 253 */
bogdanm 84:0b3ab51c8877 254 #define RCC_LSI_OFF ((uint8_t)0x00)
bogdanm 84:0b3ab51c8877 255 #define RCC_LSI_ON ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 256
bogdanm 84:0b3ab51c8877 257 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
bogdanm 84:0b3ab51c8877 258 /**
bogdanm 84:0b3ab51c8877 259 * @}
bogdanm 84:0b3ab51c8877 260 */
bogdanm 84:0b3ab51c8877 261
bogdanm 84:0b3ab51c8877 262
bogdanm 92:4fc01daae5a5 263 /** @defgroup RCC_MSI_Config
bogdanm 84:0b3ab51c8877 264 * @{
bogdanm 84:0b3ab51c8877 265 */
bogdanm 84:0b3ab51c8877 266 #define RCC_MSI_OFF ((uint8_t)0x00)
bogdanm 84:0b3ab51c8877 267 #define RCC_MSI_ON ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 268
bogdanm 84:0b3ab51c8877 269 #define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_OFF) || ((MSI) == RCC_MSI_ON))
bogdanm 84:0b3ab51c8877 270 /**
bogdanm 84:0b3ab51c8877 271 * @}
bogdanm 84:0b3ab51c8877 272 */
bogdanm 84:0b3ab51c8877 273
bogdanm 92:4fc01daae5a5 274 /** @defgroup RCC_HSI48_Config
bogdanm 84:0b3ab51c8877 275 * @{
bogdanm 84:0b3ab51c8877 276 */
bogdanm 84:0b3ab51c8877 277 #define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm 84:0b3ab51c8877 278 #define RCC_HSI48_ON ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 279
bogdanm 84:0b3ab51c8877 280 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
bogdanm 84:0b3ab51c8877 281 /**
bogdanm 84:0b3ab51c8877 282 * @}
bogdanm 84:0b3ab51c8877 283 */
bogdanm 84:0b3ab51c8877 284
bogdanm 92:4fc01daae5a5 285 /** @defgroup RCC_PLL_Config
bogdanm 84:0b3ab51c8877 286 * @{
bogdanm 84:0b3ab51c8877 287 */
bogdanm 84:0b3ab51c8877 288 #define RCC_PLL_NONE ((uint8_t)0x00)
bogdanm 84:0b3ab51c8877 289 #define RCC_PLL_OFF ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 290 #define RCC_PLL_ON ((uint8_t)0x02)
bogdanm 84:0b3ab51c8877 291
bogdanm 84:0b3ab51c8877 292 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
bogdanm 84:0b3ab51c8877 293 /**
bogdanm 84:0b3ab51c8877 294 * @}
bogdanm 84:0b3ab51c8877 295 */
bogdanm 84:0b3ab51c8877 296
bogdanm 92:4fc01daae5a5 297 /** @defgroup RCC_PLL_Clock_Source
bogdanm 84:0b3ab51c8877 298 * @{
bogdanm 84:0b3ab51c8877 299 */
bogdanm 84:0b3ab51c8877 300 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
bogdanm 84:0b3ab51c8877 301 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
bogdanm 84:0b3ab51c8877 302
bogdanm 84:0b3ab51c8877 303 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
bogdanm 84:0b3ab51c8877 304 ((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm 84:0b3ab51c8877 305
bogdanm 84:0b3ab51c8877 306 /**
bogdanm 84:0b3ab51c8877 307 * @}
bogdanm 84:0b3ab51c8877 308 */
bogdanm 84:0b3ab51c8877 309
bogdanm 92:4fc01daae5a5 310 /** @defgroup RCC_PLLMultiplication_Factor
bogdanm 84:0b3ab51c8877 311 * @{
bogdanm 84:0b3ab51c8877 312 */
bogdanm 84:0b3ab51c8877 313
bogdanm 84:0b3ab51c8877 314 #define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
bogdanm 84:0b3ab51c8877 315 #define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
bogdanm 84:0b3ab51c8877 316 #define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
bogdanm 84:0b3ab51c8877 317 #define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
bogdanm 84:0b3ab51c8877 318 #define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
bogdanm 84:0b3ab51c8877 319 #define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
bogdanm 84:0b3ab51c8877 320 #define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
bogdanm 84:0b3ab51c8877 321 #define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
bogdanm 84:0b3ab51c8877 322 #define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
bogdanm 84:0b3ab51c8877 323 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMUL_3) || ((MUL) == RCC_PLLMUL_4) || \
bogdanm 84:0b3ab51c8877 324 ((MUL) == RCC_PLLMUL_6) || ((MUL) == RCC_PLLMUL_8) || \
bogdanm 84:0b3ab51c8877 325 ((MUL) == RCC_PLLMUL_12) || ((MUL) == RCC_PLLMUL_16) || \
bogdanm 84:0b3ab51c8877 326 ((MUL) == RCC_PLLMUL_24) || ((MUL) == RCC_PLLMUL_32) || \
bogdanm 84:0b3ab51c8877 327 ((MUL) == RCC_PLLMUL_48))
bogdanm 84:0b3ab51c8877 328 /**
bogdanm 84:0b3ab51c8877 329 * @}
bogdanm 84:0b3ab51c8877 330 */
bogdanm 84:0b3ab51c8877 331
bogdanm 92:4fc01daae5a5 332 /** @defgroup RCC_PLLDivider_Factor
bogdanm 84:0b3ab51c8877 333 * @{
bogdanm 84:0b3ab51c8877 334 */
bogdanm 84:0b3ab51c8877 335
bogdanm 84:0b3ab51c8877 336 #define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
bogdanm 84:0b3ab51c8877 337 #define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
bogdanm 84:0b3ab51c8877 338 #define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
bogdanm 84:0b3ab51c8877 339 #define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDIV_2) || ((DIV) == RCC_PLLDIV_3) || \
bogdanm 84:0b3ab51c8877 340 ((DIV) == RCC_PLLDIV_4))
bogdanm 84:0b3ab51c8877 341 /**
bogdanm 84:0b3ab51c8877 342 * @}
bogdanm 84:0b3ab51c8877 343 */
bogdanm 84:0b3ab51c8877 344
bogdanm 84:0b3ab51c8877 345 /** @defgroup RCC_System_Clock_Type
bogdanm 84:0b3ab51c8877 346 * @{
bogdanm 84:0b3ab51c8877 347 */
bogdanm 84:0b3ab51c8877 348 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 349 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm 84:0b3ab51c8877 350 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm 84:0b3ab51c8877 351 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 352
bogdanm 84:0b3ab51c8877 353 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
bogdanm 84:0b3ab51c8877 354 /**
bogdanm 84:0b3ab51c8877 355 * @}
bogdanm 84:0b3ab51c8877 356 */
bogdanm 84:0b3ab51c8877 357
bogdanm 92:4fc01daae5a5 358 /** @defgroup RCC_System_Clock_Source
bogdanm 84:0b3ab51c8877 359 * @{
bogdanm 84:0b3ab51c8877 360 */
bogdanm 84:0b3ab51c8877 361 #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
bogdanm 84:0b3ab51c8877 362 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm 84:0b3ab51c8877 363 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm 84:0b3ab51c8877 364 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm 84:0b3ab51c8877 365
bogdanm 84:0b3ab51c8877 366 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
bogdanm 84:0b3ab51c8877 367 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
bogdanm 84:0b3ab51c8877 368 ((SOURCE) == RCC_SYSCLKSOURCE_MSI) || \
bogdanm 84:0b3ab51c8877 369 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm 84:0b3ab51c8877 370 /**
bogdanm 84:0b3ab51c8877 371 * @}
bogdanm 84:0b3ab51c8877 372 */
bogdanm 84:0b3ab51c8877 373
bogdanm 84:0b3ab51c8877 374 /** @defgroup RCC_AHB_Clock_Source
bogdanm 84:0b3ab51c8877 375 * @{
bogdanm 84:0b3ab51c8877 376 */
bogdanm 84:0b3ab51c8877 377 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm 84:0b3ab51c8877 378 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm 84:0b3ab51c8877 379 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm 84:0b3ab51c8877 380 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm 84:0b3ab51c8877 381 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm 84:0b3ab51c8877 382 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm 84:0b3ab51c8877 383 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm 84:0b3ab51c8877 384 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm 84:0b3ab51c8877 385 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm 84:0b3ab51c8877 386
bogdanm 84:0b3ab51c8877 387 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
bogdanm 84:0b3ab51c8877 388 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
bogdanm 84:0b3ab51c8877 389 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
bogdanm 84:0b3ab51c8877 390 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
bogdanm 84:0b3ab51c8877 391 ((HCLK) == RCC_SYSCLK_DIV512))
bogdanm 84:0b3ab51c8877 392 /**
bogdanm 84:0b3ab51c8877 393 * @}
bogdanm 84:0b3ab51c8877 394 */
bogdanm 84:0b3ab51c8877 395
bogdanm 84:0b3ab51c8877 396 /** @defgroup RCC_APB1_APB2_Clock_Source
bogdanm 84:0b3ab51c8877 397 * @{
bogdanm 84:0b3ab51c8877 398 */
bogdanm 84:0b3ab51c8877 399 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm 84:0b3ab51c8877 400 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm 84:0b3ab51c8877 401 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm 84:0b3ab51c8877 402 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm 84:0b3ab51c8877 403 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm 84:0b3ab51c8877 404
bogdanm 84:0b3ab51c8877 405 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
bogdanm 84:0b3ab51c8877 406 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
bogdanm 84:0b3ab51c8877 407 ((PCLK) == RCC_HCLK_DIV16))
bogdanm 84:0b3ab51c8877 408 /**
bogdanm 84:0b3ab51c8877 409 * @}
bogdanm 84:0b3ab51c8877 410 */
bogdanm 84:0b3ab51c8877 411
bogdanm 84:0b3ab51c8877 412 /** @defgroup RCC_RTC_Clock_Source
bogdanm 84:0b3ab51c8877 413 * @{
bogdanm 84:0b3ab51c8877 414 */
bogdanm 84:0b3ab51c8877 415 #define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
bogdanm 84:0b3ab51c8877 416 #define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
bogdanm 84:0b3ab51c8877 417 #define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
bogdanm 84:0b3ab51c8877 418 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
bogdanm 84:0b3ab51c8877 419 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
bogdanm 84:0b3ab51c8877 420 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
bogdanm 84:0b3ab51c8877 421 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \
bogdanm 84:0b3ab51c8877 422 ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \
bogdanm 84:0b3ab51c8877 423 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
bogdanm 84:0b3ab51c8877 424 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
bogdanm 84:0b3ab51c8877 425 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
bogdanm 84:0b3ab51c8877 426 ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16))
bogdanm 84:0b3ab51c8877 427 /**
bogdanm 84:0b3ab51c8877 428 * @}
bogdanm 84:0b3ab51c8877 429 */
bogdanm 84:0b3ab51c8877 430
bogdanm 84:0b3ab51c8877 431 /** @defgroup RCC_MCO_Clock_Source
bogdanm 84:0b3ab51c8877 432 * @{
bogdanm 84:0b3ab51c8877 433 */
bogdanm 84:0b3ab51c8877 434 #define RCC_MCO1SOURCE_NOCLOCK ((uint8_t)0x00)
bogdanm 84:0b3ab51c8877 435 #define RCC_MCO1SOURCE_SYSCLK ((uint8_t)0x01)
bogdanm 84:0b3ab51c8877 436 #define RCC_MCO1SOURCE_HSI ((uint8_t)0x02)
bogdanm 84:0b3ab51c8877 437 #define RCC_MCO1SOURCE_MSI ((uint8_t)0x03)
bogdanm 84:0b3ab51c8877 438 #define RCC_MCO1SOURCE_HSE ((uint8_t)0x04)
bogdanm 84:0b3ab51c8877 439 #define RCC_MCO1SOURCE_PLLCLK ((uint8_t)0x05)
bogdanm 84:0b3ab51c8877 440 #define RCC_MCO1SOURCE_LSI ((uint8_t)0x06)
bogdanm 84:0b3ab51c8877 441 #define RCC_MCO1SOURCE_LSE ((uint8_t)0x07)
bogdanm 84:0b3ab51c8877 442 #define RCC_MCO1SOURCE_HSI48 ((uint8_t)0x08)
bogdanm 84:0b3ab51c8877 443
bogdanm 84:0b3ab51c8877 444 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \
bogdanm 84:0b3ab51c8877 445 ((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_MSI) || \
bogdanm 84:0b3ab51c8877 446 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \
bogdanm 84:0b3ab51c8877 447 ((SOURCE) == RCC_MCO1SOURCE_LSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
bogdanm 84:0b3ab51c8877 448 ((SOURCE) == RCC_MCO1SOURCE_HSI48))
bogdanm 84:0b3ab51c8877 449 /**
bogdanm 84:0b3ab51c8877 450 * @}
bogdanm 84:0b3ab51c8877 451 */
bogdanm 84:0b3ab51c8877 452
bogdanm 84:0b3ab51c8877 453 /** @defgroup RCC_MCOPrescaler
bogdanm 84:0b3ab51c8877 454 * @{
bogdanm 84:0b3ab51c8877 455 */
bogdanm 84:0b3ab51c8877 456
bogdanm 84:0b3ab51c8877 457 #define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
bogdanm 84:0b3ab51c8877 458 #define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
bogdanm 84:0b3ab51c8877 459 #define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
bogdanm 84:0b3ab51c8877 460 #define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
bogdanm 84:0b3ab51c8877 461 #define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
bogdanm 84:0b3ab51c8877 462
bogdanm 84:0b3ab51c8877 463 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || \
bogdanm 84:0b3ab51c8877 464 ((DIV) == RCC_MCODIV_2) || \
bogdanm 84:0b3ab51c8877 465 ((DIV) == RCC_MCODIV_4) || \
bogdanm 84:0b3ab51c8877 466 ((DIV) == RCC_MCODIV_8) || \
bogdanm 84:0b3ab51c8877 467 ((DIV) == RCC_MCODIV_16))
bogdanm 84:0b3ab51c8877 468 /**
bogdanm 84:0b3ab51c8877 469 * @}
bogdanm 84:0b3ab51c8877 470 */
bogdanm 84:0b3ab51c8877 471
bogdanm 84:0b3ab51c8877 472 /** @defgroup RCC_MCO_Index
bogdanm 84:0b3ab51c8877 473 * @{
bogdanm 84:0b3ab51c8877 474 */
bogdanm 84:0b3ab51c8877 475 #define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 476 #define RCC_MCO2 ((uint32_t)0x00000001)
bogdanm 84:0b3ab51c8877 477
bogdanm 84:0b3ab51c8877 478 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
bogdanm 84:0b3ab51c8877 479 /**
bogdanm 84:0b3ab51c8877 480 * @}
bogdanm 84:0b3ab51c8877 481 */
bogdanm 84:0b3ab51c8877 482
bogdanm 92:4fc01daae5a5 483 /** @defgroup RCC_Interrupt
bogdanm 84:0b3ab51c8877 484 * @{
bogdanm 84:0b3ab51c8877 485 */
bogdanm 84:0b3ab51c8877 486 #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
bogdanm 84:0b3ab51c8877 487 #define RCC_IT_LSERDY RCC_CIFR_LSERDYF
bogdanm 84:0b3ab51c8877 488 #define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
bogdanm 84:0b3ab51c8877 489 #define RCC_IT_HSERDY RCC_CIFR_HSERDYF
bogdanm 84:0b3ab51c8877 490 #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
bogdanm 84:0b3ab51c8877 491 #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
bogdanm 84:0b3ab51c8877 492 #define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
bogdanm 84:0b3ab51c8877 493 #define RCC_IT_LSECSS RCC_CIFR_LSECSSF
bogdanm 84:0b3ab51c8877 494 #define RCC_IT_CSS RCC_CIFR_CSSF
bogdanm 84:0b3ab51c8877 495
bogdanm 84:0b3ab51c8877 496 #define IS_RCC_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
bogdanm 84:0b3ab51c8877 497 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
bogdanm 84:0b3ab51c8877 498 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \
bogdanm 84:0b3ab51c8877 499 ((IT) == RCC_IT_HSI48RDY) || ((IT) == RCC_IT_LSECSS))
bogdanm 84:0b3ab51c8877 500
bogdanm 84:0b3ab51c8877 501 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
bogdanm 84:0b3ab51c8877 502 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
bogdanm 84:0b3ab51c8877 503 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \
bogdanm 84:0b3ab51c8877 504 ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY) || \
bogdanm 84:0b3ab51c8877 505 ((IT) == RCC_IT_LSECSS))
bogdanm 84:0b3ab51c8877 506
bogdanm 84:0b3ab51c8877 507 #define IS_RCC_CLEAR_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
bogdanm 84:0b3ab51c8877 508 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
bogdanm 84:0b3ab51c8877 509 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \
bogdanm 84:0b3ab51c8877 510 ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY) || \
bogdanm 84:0b3ab51c8877 511 ((IT) == RCC_IT_LSECSS))
bogdanm 84:0b3ab51c8877 512
bogdanm 84:0b3ab51c8877 513 /**
bogdanm 84:0b3ab51c8877 514 * @}
bogdanm 84:0b3ab51c8877 515 */
bogdanm 84:0b3ab51c8877 516
bogdanm 84:0b3ab51c8877 517 /** @defgroup RCC_Flag
bogdanm 84:0b3ab51c8877 518 * Elements values convention: 0XXYYYYYb
bogdanm 84:0b3ab51c8877 519 * - YYYYY : Flag position in the register
bogdanm 84:0b3ab51c8877 520 * - 0XX : Register index
bogdanm 84:0b3ab51c8877 521 * - 01: CR register
bogdanm 84:0b3ab51c8877 522 * - 10: CSR register
bogdanm 84:0b3ab51c8877 523 * - 11: CRRCR register
bogdanm 84:0b3ab51c8877 524 * @{
bogdanm 84:0b3ab51c8877 525 */
bogdanm 84:0b3ab51c8877 526 /* Flags in the CR register */
bogdanm 84:0b3ab51c8877 527 #define RCC_FLAG_HSIRDY ((uint8_t)0x22)
bogdanm 84:0b3ab51c8877 528 #define RCC_FLAG_HSIDIV ((uint8_t)0x24)
bogdanm 84:0b3ab51c8877 529 #define RCC_FLAG_MSIRDY ((uint8_t)0x29)
bogdanm 84:0b3ab51c8877 530 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
bogdanm 84:0b3ab51c8877 531 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
bogdanm 84:0b3ab51c8877 532
bogdanm 84:0b3ab51c8877 533 /* Flags in the CSR register */
bogdanm 84:0b3ab51c8877 534 #define RCC_FLAG_LSERDY ((uint8_t)0x49)
bogdanm 84:0b3ab51c8877 535 #define RCC_FLAG_LSECSS ((uint8_t)0x4E)
bogdanm 84:0b3ab51c8877 536 #define RCC_FLAG_LSIRDY ((uint8_t)0x41)
bogdanm 84:0b3ab51c8877 537 #define RCC_FLAG_FIREWALLRST ((uint8_t)0x58)
bogdanm 84:0b3ab51c8877 538 #define RCC_FLAG_OBLRST ((uint8_t)0x59)
bogdanm 84:0b3ab51c8877 539 #define RCC_FLAG_PINRST ((uint8_t)0x5A)
bogdanm 84:0b3ab51c8877 540 #define RCC_FLAG_PORRST ((uint8_t)0x5B)
bogdanm 84:0b3ab51c8877 541 #define RCC_FLAG_SFTRST ((uint8_t)0x5C)
bogdanm 84:0b3ab51c8877 542 #define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
bogdanm 84:0b3ab51c8877 543 #define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
bogdanm 84:0b3ab51c8877 544 #define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
bogdanm 84:0b3ab51c8877 545
bogdanm 84:0b3ab51c8877 546 /* Flags in the CRRCR register */
bogdanm 84:0b3ab51c8877 547 #define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
bogdanm 84:0b3ab51c8877 548
bogdanm 84:0b3ab51c8877 549
bogdanm 84:0b3ab51c8877 550
bogdanm 84:0b3ab51c8877 551 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
bogdanm 92:4fc01daae5a5 552 #define IS_RCC_MSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0xFF)
bogdanm 84:0b3ab51c8877 553 /**
bogdanm 84:0b3ab51c8877 554 * @}
bogdanm 84:0b3ab51c8877 555 */
bogdanm 84:0b3ab51c8877 556
bogdanm 84:0b3ab51c8877 557 /**
bogdanm 84:0b3ab51c8877 558 * @}
bogdanm 84:0b3ab51c8877 559 */
bogdanm 84:0b3ab51c8877 560 /* Exported macro ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 561 /** @defgroup RCC_Exported macro
bogdanm 84:0b3ab51c8877 562 * @{
bogdanm 84:0b3ab51c8877 563 */
bogdanm 84:0b3ab51c8877 564
bogdanm 84:0b3ab51c8877 565 /** @brief Enable or disable the AHB peripheral clock.
bogdanm 84:0b3ab51c8877 566 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 84:0b3ab51c8877 567 * is disabled and the application software has to enable this clock before
bogdanm 84:0b3ab51c8877 568 * using it.
bogdanm 84:0b3ab51c8877 569 */
bogdanm 84:0b3ab51c8877 570 #define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
bogdanm 84:0b3ab51c8877 571 #define __MIF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_MIFEN))
bogdanm 84:0b3ab51c8877 572 #define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
bogdanm 84:0b3ab51c8877 573
bogdanm 84:0b3ab51c8877 574
bogdanm 84:0b3ab51c8877 575 #define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_DMA1EN))
bogdanm 84:0b3ab51c8877 576 #define __MIF_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_MIFEN))
bogdanm 84:0b3ab51c8877 577 #define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRCEN))
bogdanm 84:0b3ab51c8877 578
bogdanm 84:0b3ab51c8877 579
bogdanm 84:0b3ab51c8877 580 /** @brief Enable or disable the IOPORT peripheral clock.
bogdanm 84:0b3ab51c8877 581 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 84:0b3ab51c8877 582 * is disabled and the application software has to enable this clock before
bogdanm 84:0b3ab51c8877 583 * using it.
bogdanm 84:0b3ab51c8877 584 */
bogdanm 84:0b3ab51c8877 585 #define __GPIOA_CLK_ENABLE() (RCC->IOPENR |= (RCC_IOPENR_GPIOAEN))
bogdanm 84:0b3ab51c8877 586 #define __GPIOB_CLK_ENABLE() (RCC->IOPENR |= (RCC_IOPENR_GPIOBEN))
bogdanm 84:0b3ab51c8877 587 #define __GPIOC_CLK_ENABLE() (RCC->IOPENR |= (RCC_IOPENR_GPIOCEN))
bogdanm 84:0b3ab51c8877 588 #define __GPIOD_CLK_ENABLE() (RCC->IOPENR |= (RCC_IOPENR_GPIODEN))
bogdanm 84:0b3ab51c8877 589 #define __GPIOH_CLK_ENABLE() (RCC->IOPENR |= (RCC_IOPENR_GPIOHEN))
bogdanm 84:0b3ab51c8877 590
bogdanm 84:0b3ab51c8877 591 #define __GPIOA_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN))
bogdanm 84:0b3ab51c8877 592 #define __GPIOB_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN))
bogdanm 84:0b3ab51c8877 593 #define __GPIOC_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN))
bogdanm 84:0b3ab51c8877 594 #define __GPIOD_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN))
bogdanm 84:0b3ab51c8877 595 #define __GPIOH_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN))
bogdanm 84:0b3ab51c8877 596
bogdanm 84:0b3ab51c8877 597
bogdanm 84:0b3ab51c8877 598 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm 84:0b3ab51c8877 599 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 84:0b3ab51c8877 600 * is disabled and the application software has to enable this clock before
bogdanm 84:0b3ab51c8877 601 * using it.
bogdanm 84:0b3ab51c8877 602 */
bogdanm 84:0b3ab51c8877 603 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
bogdanm 84:0b3ab51c8877 604 #define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
bogdanm 84:0b3ab51c8877 605
bogdanm 84:0b3ab51c8877 606 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN))
bogdanm 84:0b3ab51c8877 607 #define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN))
bogdanm 84:0b3ab51c8877 608
bogdanm 84:0b3ab51c8877 609 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm 84:0b3ab51c8877 610 * @note After reset, the peripheral clock (used for registers read/write access)
bogdanm 84:0b3ab51c8877 611 * is disabled and the application software has to enable this clock before
bogdanm 84:0b3ab51c8877 612 * using it.
bogdanm 84:0b3ab51c8877 613 */
bogdanm 84:0b3ab51c8877 614 #define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
bogdanm 84:0b3ab51c8877 615 #define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN))
bogdanm 84:0b3ab51c8877 616
bogdanm 84:0b3ab51c8877 617 #define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SYSCFGEN))
bogdanm 84:0b3ab51c8877 618 #define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_DBGMCUEN))
bogdanm 84:0b3ab51c8877 619
bogdanm 84:0b3ab51c8877 620 /** @brief Force or release AHB peripheral reset.
bogdanm 84:0b3ab51c8877 621 */
bogdanm 84:0b3ab51c8877 622 #define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
bogdanm 84:0b3ab51c8877 623 #define __DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))
bogdanm 84:0b3ab51c8877 624 #define __MIF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_MIFRST))
bogdanm 84:0b3ab51c8877 625 #define __CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST))
bogdanm 84:0b3ab51c8877 626
bogdanm 84:0b3ab51c8877 627 #define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
bogdanm 84:0b3ab51c8877 628 #define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST))
bogdanm 84:0b3ab51c8877 629 #define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST))
bogdanm 84:0b3ab51c8877 630 #define __MIF_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST))
bogdanm 84:0b3ab51c8877 631
bogdanm 84:0b3ab51c8877 632
bogdanm 84:0b3ab51c8877 633 /** @brief Force or release IOPORT peripheral reset.
bogdanm 84:0b3ab51c8877 634 */
bogdanm 84:0b3ab51c8877 635 #define __IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
bogdanm 84:0b3ab51c8877 636 #define __GPIOA_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOARST))
bogdanm 84:0b3ab51c8877 637 #define __GPIOB_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOBRST))
bogdanm 84:0b3ab51c8877 638 #define __GPIOC_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOCRST))
bogdanm 84:0b3ab51c8877 639 #define __GPIOD_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIODRST))
bogdanm 84:0b3ab51c8877 640 #define __GPIOH_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOHRST))
bogdanm 84:0b3ab51c8877 641
bogdanm 84:0b3ab51c8877 642 #define __IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
bogdanm 84:0b3ab51c8877 643 #define __GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST))
bogdanm 84:0b3ab51c8877 644 #define __GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST))
bogdanm 84:0b3ab51c8877 645 #define __GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST))
bogdanm 84:0b3ab51c8877 646 #define __GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST))
bogdanm 84:0b3ab51c8877 647 #define __GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST))
bogdanm 84:0b3ab51c8877 648
bogdanm 84:0b3ab51c8877 649 /** @brief Force or release APB1 peripheral reset.
bogdanm 84:0b3ab51c8877 650 */
bogdanm 84:0b3ab51c8877 651 #define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm 84:0b3ab51c8877 652 #define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
bogdanm 84:0b3ab51c8877 653 #define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
bogdanm 84:0b3ab51c8877 654
bogdanm 84:0b3ab51c8877 655 #define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm 84:0b3ab51c8877 656 #define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST))
bogdanm 84:0b3ab51c8877 657 #define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST))
bogdanm 84:0b3ab51c8877 658
bogdanm 84:0b3ab51c8877 659 /** @brief Force or release APB2 peripheral reset.
bogdanm 84:0b3ab51c8877 660 */
bogdanm 84:0b3ab51c8877 661 #define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm 84:0b3ab51c8877 662 #define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST))
bogdanm 84:0b3ab51c8877 663 #define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
bogdanm 84:0b3ab51c8877 664
bogdanm 84:0b3ab51c8877 665 #define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm 84:0b3ab51c8877 666 #define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST))
bogdanm 84:0b3ab51c8877 667 #define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST))
bogdanm 84:0b3ab51c8877 668
bogdanm 84:0b3ab51c8877 669 /** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
bogdanm 84:0b3ab51c8877 670 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 84:0b3ab51c8877 671 * power consumption.
bogdanm 84:0b3ab51c8877 672 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 84:0b3ab51c8877 673 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 84:0b3ab51c8877 674 */
bogdanm 84:0b3ab51c8877 675 #define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_CRCSMEN))
bogdanm 84:0b3ab51c8877 676 #define __MIF_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_MIFSMEN))
bogdanm 84:0b3ab51c8877 677 #define __SRAM_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_SRAMSMEN))
bogdanm 84:0b3ab51c8877 678 #define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_DMA1SMEN))
bogdanm 84:0b3ab51c8877 679
bogdanm 84:0b3ab51c8877 680 #define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_CRCSMEN))
bogdanm 84:0b3ab51c8877 681 #define __MIF_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_MIFSMEN))
bogdanm 84:0b3ab51c8877 682 #define __SRAM_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_SRAMSMEN))
bogdanm 84:0b3ab51c8877 683 #define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_DMA1SMEN))
bogdanm 84:0b3ab51c8877 684
bogdanm 84:0b3ab51c8877 685 /** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
bogdanm 84:0b3ab51c8877 686 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 84:0b3ab51c8877 687 * power consumption.
bogdanm 84:0b3ab51c8877 688 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 84:0b3ab51c8877 689 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 84:0b3ab51c8877 690 */
bogdanm 84:0b3ab51c8877 691
bogdanm 84:0b3ab51c8877 692 #define __GPIOA_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOASMEN))
bogdanm 84:0b3ab51c8877 693 #define __GPIOB_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOBSMEN))
bogdanm 84:0b3ab51c8877 694 #define __GPIOC_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOCSMEN))
bogdanm 84:0b3ab51c8877 695 #define __GPIOD_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIODSMEN))
bogdanm 84:0b3ab51c8877 696 #define __GPIOH_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOHSMEN))
bogdanm 84:0b3ab51c8877 697
bogdanm 84:0b3ab51c8877 698 #define __GPIOA_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN))
bogdanm 84:0b3ab51c8877 699 #define __GPIOB_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN))
bogdanm 84:0b3ab51c8877 700 #define __GPIOC_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN))
bogdanm 84:0b3ab51c8877 701 #define __GPIOD_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN))
bogdanm 84:0b3ab51c8877 702 #define __GPIOH_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN))
bogdanm 84:0b3ab51c8877 703
bogdanm 84:0b3ab51c8877 704 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm 84:0b3ab51c8877 705 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 84:0b3ab51c8877 706 * power consumption.
bogdanm 84:0b3ab51c8877 707 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 84:0b3ab51c8877 708 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 84:0b3ab51c8877 709 */
bogdanm 84:0b3ab51c8877 710 #define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_WWDGSMEN))
bogdanm 84:0b3ab51c8877 711 #define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_PWRSMEN))
bogdanm 84:0b3ab51c8877 712
bogdanm 84:0b3ab51c8877 713 #define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN))
bogdanm 84:0b3ab51c8877 714 #define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN))
bogdanm 84:0b3ab51c8877 715
bogdanm 84:0b3ab51c8877 716 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm 84:0b3ab51c8877 717 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm 84:0b3ab51c8877 718 * power consumption.
bogdanm 84:0b3ab51c8877 719 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm 84:0b3ab51c8877 720 * @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm 84:0b3ab51c8877 721 */
bogdanm 84:0b3ab51c8877 722 #define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SYSCFGSMEN))
bogdanm 84:0b3ab51c8877 723 #define __DBGMCU_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_DBGMCUSMEN))
bogdanm 84:0b3ab51c8877 724
bogdanm 84:0b3ab51c8877 725 #define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SYSCFGSMEN))
bogdanm 84:0b3ab51c8877 726 #define __DBGMCU_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_DBGMCUSMEN))
bogdanm 84:0b3ab51c8877 727
bogdanm 84:0b3ab51c8877 728 /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
bogdanm 84:0b3ab51c8877 729 * @note After enabling the HSI, the application software should wait on
bogdanm 84:0b3ab51c8877 730 * HSIRDY flag to be set indicating that HSI clock is stable and can
bogdanm 84:0b3ab51c8877 731 * be used to clock the PLL and/or system clock.
bogdanm 84:0b3ab51c8877 732 * @note HSI can not be stopped if it is used directly or through the PLL
bogdanm 84:0b3ab51c8877 733 * as system clock. In this case, you have to select another source
bogdanm 84:0b3ab51c8877 734 * of the system clock then stop the HSI.
bogdanm 84:0b3ab51c8877 735 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 736 * @param __STATE__: specifies the new state of the HSI.
bogdanm 84:0b3ab51c8877 737 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 738 * @arg RCC_HSI_OFF: turn OFF the HSI oscillator
bogdanm 84:0b3ab51c8877 739 * @arg RCC_HSI_ON: turn ON the HSI oscillator
bogdanm 84:0b3ab51c8877 740 * @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
bogdanm 84:0b3ab51c8877 741 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm 84:0b3ab51c8877 742 * clock cycles.
bogdanm 84:0b3ab51c8877 743 */
bogdanm 84:0b3ab51c8877 744 #define __HAL_RCC_HSI_CONFIG(__STATE__) \
bogdanm 84:0b3ab51c8877 745 MODIFY_REG(RCC->CR, RCC_CR_HSION|RCC_CR_HSIDIVEN, (uint32_t)(__STATE__))
bogdanm 84:0b3ab51c8877 746
bogdanm 84:0b3ab51c8877 747 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm 84:0b3ab51c8877 748 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 749 * It is used (enabled by hardware) as system clock source after startup
bogdanm 84:0b3ab51c8877 750 * from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm 84:0b3ab51c8877 751 * of the HSE used directly or indirectly as system clock (if the Clock
bogdanm 84:0b3ab51c8877 752 * Security System CSS is enabled).
bogdanm 84:0b3ab51c8877 753 * @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm 84:0b3ab51c8877 754 * you have to select another source of the system clock then stop the HSI.
bogdanm 84:0b3ab51c8877 755 * @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm 84:0b3ab51c8877 756 * flag to be set indicating that HSI clock is stable and can be used as
bogdanm 84:0b3ab51c8877 757 * system clock source.
bogdanm 84:0b3ab51c8877 758 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm 84:0b3ab51c8877 759 * clock cycles.
bogdanm 84:0b3ab51c8877 760 */
bogdanm 84:0b3ab51c8877 761 #define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
bogdanm 84:0b3ab51c8877 762 #define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
bogdanm 84:0b3ab51c8877 763
bogdanm 84:0b3ab51c8877 764 /**
bogdanm 84:0b3ab51c8877 765 * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
bogdanm 84:0b3ab51c8877 766 * @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 767 * It is used (enabled by hardware) as system clock source after
bogdanm 84:0b3ab51c8877 768 * startup from Reset, wakeup from STOP and STANDBY mode, or in case
bogdanm 84:0b3ab51c8877 769 * of failure of the HSE used directly or indirectly as system clock
bogdanm 84:0b3ab51c8877 770 * (if the Clock Security System CSS is enabled).
bogdanm 84:0b3ab51c8877 771 * @note MSI can not be stopped if it is used as system clock source.
bogdanm 84:0b3ab51c8877 772 * In this case, you have to select another source of the system
bogdanm 84:0b3ab51c8877 773 * clock then stop the MSI.
bogdanm 84:0b3ab51c8877 774 * @note After enabling the MSI, the application software should wait on
bogdanm 84:0b3ab51c8877 775 * MSIRDY flag to be set indicating that MSI clock is stable and can
bogdanm 84:0b3ab51c8877 776 * be used as system clock source.
bogdanm 84:0b3ab51c8877 777 * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
bogdanm 84:0b3ab51c8877 778 * clock cycles.
bogdanm 84:0b3ab51c8877 779 */
bogdanm 84:0b3ab51c8877 780 #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
bogdanm 84:0b3ab51c8877 781 #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
bogdanm 84:0b3ab51c8877 782
bogdanm 84:0b3ab51c8877 783 /**
bogdanm 84:0b3ab51c8877 784 * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
bogdanm 84:0b3ab51c8877 785 * @note After enabling the HSI48, the application software should wait on
bogdanm 84:0b3ab51c8877 786 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can
bogdanm 84:0b3ab51c8877 787 * be used to clock the USB.
bogdanm 84:0b3ab51c8877 788 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 789 */
bogdanm 84:0b3ab51c8877 790 #define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
bogdanm 84:0b3ab51c8877 791 RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; \
bogdanm 84:0b3ab51c8877 792 SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT); \
bogdanm 84:0b3ab51c8877 793 } while (0)
bogdanm 84:0b3ab51c8877 794 #define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
bogdanm 84:0b3ab51c8877 795 SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); \
bogdanm 84:0b3ab51c8877 796 } while (0)
bogdanm 84:0b3ab51c8877 797
bogdanm 84:0b3ab51c8877 798 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm 84:0b3ab51c8877 799 * @note The calibration is used to compensate for the variations in voltage
bogdanm 84:0b3ab51c8877 800 * and temperature that influence the frequency of the internal HSI RC.
bogdanm 84:0b3ab51c8877 801 * @param __HSICalibrationValue__: specifies the calibration trimming value.
bogdanm 84:0b3ab51c8877 802 * This parameter must be a number between 0 and 0x1F.
bogdanm 84:0b3ab51c8877 803 */
bogdanm 84:0b3ab51c8877 804 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
bogdanm 84:0b3ab51c8877 805 RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
bogdanm 84:0b3ab51c8877 806
bogdanm 84:0b3ab51c8877 807 /** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
bogdanm 84:0b3ab51c8877 808 * @note The calibration is used to compensate for the variations in voltage
bogdanm 84:0b3ab51c8877 809 * and temperature that influence the frequency of the internal MSI RC.
bogdanm 84:0b3ab51c8877 810 * Refer to the Application Note AN3300 for more details on how to
bogdanm 84:0b3ab51c8877 811 * calibrate the MSI.
bogdanm 84:0b3ab51c8877 812 * @param __MSICalibrationValue__: specifies the calibration trimming value.
bogdanm 84:0b3ab51c8877 813 * This parameter must be a number between 0 and 0xFF.
bogdanm 84:0b3ab51c8877 814 */
bogdanm 84:0b3ab51c8877 815 #define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
bogdanm 84:0b3ab51c8877 816 RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
bogdanm 84:0b3ab51c8877 817
bogdanm 84:0b3ab51c8877 818 /**
bogdanm 84:0b3ab51c8877 819 * @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
bogdanm 84:0b3ab51c8877 820 * @note After restart from Reset or wakeup from STANDBY, the MSI clock is
bogdanm 84:0b3ab51c8877 821 * around 2.097 MHz. The MSI clock does not change after wake-up from
bogdanm 84:0b3ab51c8877 822 * STOP mode.
bogdanm 84:0b3ab51c8877 823 * @note The MSI clock range can be modified on the fly.
bogdanm 84:0b3ab51c8877 824 * @param RCC_MSIRange: specifies the MSI Clock range.
bogdanm 84:0b3ab51c8877 825 * This parameter must be one of the following values:
bogdanm 84:0b3ab51c8877 826 * @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
bogdanm 84:0b3ab51c8877 827 * @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
bogdanm 84:0b3ab51c8877 828 * @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
bogdanm 84:0b3ab51c8877 829 * @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
bogdanm 84:0b3ab51c8877 830 * @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
bogdanm 84:0b3ab51c8877 831 * @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
bogdanm 84:0b3ab51c8877 832 * @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
bogdanm 84:0b3ab51c8877 833 */
bogdanm 84:0b3ab51c8877 834 #define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
bogdanm 84:0b3ab51c8877 835 RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
bogdanm 84:0b3ab51c8877 836
bogdanm 84:0b3ab51c8877 837 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm 84:0b3ab51c8877 838 * @note After enabling the LSI, the application software should wait on
bogdanm 84:0b3ab51c8877 839 * LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm 84:0b3ab51c8877 840 * be used to clock the IWDG and/or the RTC.
bogdanm 84:0b3ab51c8877 841 * @note LSI can not be disabled if the IWDG is running.
bogdanm 84:0b3ab51c8877 842 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm 84:0b3ab51c8877 843 * clock cycles.
bogdanm 84:0b3ab51c8877 844 */
bogdanm 84:0b3ab51c8877 845 #define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm 84:0b3ab51c8877 846 #define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
bogdanm 84:0b3ab51c8877 847
bogdanm 84:0b3ab51c8877 848 /**
bogdanm 84:0b3ab51c8877 849 * @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm 84:0b3ab51c8877 850 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm 84:0b3ab51c8877 851 * software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm 84:0b3ab51c8877 852 * is stable and can be used to clock the PLL and/or system clock.
bogdanm 84:0b3ab51c8877 853 * @note HSE state can not be changed if it is used directly or through the
bogdanm 84:0b3ab51c8877 854 * PLL as system clock. In this case, you have to select another source
bogdanm 84:0b3ab51c8877 855 * of the system clock then change the HSE state (ex. disable it).
bogdanm 84:0b3ab51c8877 856 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 857 * @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm 84:0b3ab51c8877 858 * was previously enabled you have to enable it again after calling this
bogdanm 84:0b3ab51c8877 859 * function.
bogdanm 84:0b3ab51c8877 860 * @param __STATE__: specifies the new state of the HSE.
bogdanm 84:0b3ab51c8877 861 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 862 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm 84:0b3ab51c8877 863 * 6 HSE oscillator clock cycles.
bogdanm 84:0b3ab51c8877 864 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm 84:0b3ab51c8877 865 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm 84:0b3ab51c8877 866 */
bogdanm 84:0b3ab51c8877 867 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
bogdanm 84:0b3ab51c8877 868 MODIFY_REG(RCC->CR, RCC_CR_HSEON|RCC_CR_HSEBYP, (uint32_t)(__STATE__))
bogdanm 84:0b3ab51c8877 869
bogdanm 84:0b3ab51c8877 870 /**
bogdanm 84:0b3ab51c8877 871 * @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm 84:0b3ab51c8877 872 * @note As the LSE is in the Backup domain and write access is denied to
bogdanm 84:0b3ab51c8877 873 * this domain after reset, you have to enable write access using
bogdanm 84:0b3ab51c8877 874 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm 84:0b3ab51c8877 875 * (to be done once after reset).
bogdanm 84:0b3ab51c8877 876 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm 84:0b3ab51c8877 877 * software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm 84:0b3ab51c8877 878 * is stable and can be used to clock the RTC.
bogdanm 84:0b3ab51c8877 879 * @param __STATE__: specifies the new state of the LSE.
bogdanm 84:0b3ab51c8877 880 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 881 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm 84:0b3ab51c8877 882 * 6 LSE oscillator clock cycles.
bogdanm 84:0b3ab51c8877 883 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm 84:0b3ab51c8877 884 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm 84:0b3ab51c8877 885 */
bogdanm 84:0b3ab51c8877 886 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
bogdanm 84:0b3ab51c8877 887 MODIFY_REG(RCC->CSR, RCC_CSR_LSEON|RCC_CSR_LSEBYP, (uint32_t)(__STATE__))
bogdanm 84:0b3ab51c8877 888
bogdanm 84:0b3ab51c8877 889 /** @brief Macros to enable or disable the the RTC clock.
bogdanm 84:0b3ab51c8877 890 * @note These macros must be used only after the RTC clock source was selected.
bogdanm 84:0b3ab51c8877 891 */
bogdanm 84:0b3ab51c8877 892 #define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
bogdanm 84:0b3ab51c8877 893 #define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
bogdanm 84:0b3ab51c8877 894
bogdanm 84:0b3ab51c8877 895 /**
bogdanm 84:0b3ab51c8877 896 * @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
bogdanm 84:0b3ab51c8877 897 * @note As the RTC clock configuration bits are in the RTC domain and write
bogdanm 84:0b3ab51c8877 898 * access is denied to this domain after reset, you have to enable write
bogdanm 84:0b3ab51c8877 899 * access using PWR_RTCAccessCmd(ENABLE) function before to configure
bogdanm 84:0b3ab51c8877 900 * the RTC clock source (to be done once after reset).
bogdanm 84:0b3ab51c8877 901 * @note Once the RTC clock is configured it can't be changed unless the RTC
bogdanm 84:0b3ab51c8877 902 * is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
bogdanm 84:0b3ab51c8877 903 * @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
bogdanm 84:0b3ab51c8877 904 *
bogdanm 84:0b3ab51c8877 905 * @param RCC_RTCCLKSource: specifies the RTC clock source.
bogdanm 84:0b3ab51c8877 906 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 907 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
bogdanm 84:0b3ab51c8877 908 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
bogdanm 84:0b3ab51c8877 909 * @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
bogdanm 84:0b3ab51c8877 910 * @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
bogdanm 84:0b3ab51c8877 911 * @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
bogdanm 84:0b3ab51c8877 912 * @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
bogdanm 84:0b3ab51c8877 913 *
bogdanm 84:0b3ab51c8877 914 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm 84:0b3ab51c8877 915 * work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm 84:0b3ab51c8877 916 * However, when the HSE clock is used as RTC clock source, the RTC
bogdanm 84:0b3ab51c8877 917 * cannot be used in STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 918 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm 84:0b3ab51c8877 919 * RTC clock source).
bogdanm 84:0b3ab51c8877 920 */
bogdanm 84:0b3ab51c8877 921 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
bogdanm 84:0b3ab51c8877 922 MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTCCLKSource__) & 0xFFFCFFFF)) : CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
bogdanm 84:0b3ab51c8877 923
bogdanm 84:0b3ab51c8877 924 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
bogdanm 84:0b3ab51c8877 925 MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)(__RTCCLKSource__)); \
bogdanm 84:0b3ab51c8877 926 } while (0)
bogdanm 84:0b3ab51c8877 927
bogdanm 92:4fc01daae5a5 928 #define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
bogdanm 84:0b3ab51c8877 929
bogdanm 84:0b3ab51c8877 930 /** @brief Macros to force or release the Backup domain reset.
bogdanm 84:0b3ab51c8877 931 * @note This function resets the RTC peripheral (including the backup registers)
bogdanm 84:0b3ab51c8877 932 * and the RTC clock source selection in RCC_CSR register.
bogdanm 84:0b3ab51c8877 933 * @note The BKPSRAM is not affected by this reset.
bogdanm 84:0b3ab51c8877 934 */
bogdanm 84:0b3ab51c8877 935 #define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
bogdanm 84:0b3ab51c8877 936 #define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
bogdanm 84:0b3ab51c8877 937
bogdanm 84:0b3ab51c8877 938 /** @brief Macros to enable or disable the main PLL.
bogdanm 84:0b3ab51c8877 939 * @note After enabling the main PLL, the application software should wait on
bogdanm 84:0b3ab51c8877 940 * PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm 84:0b3ab51c8877 941 * be used as system clock source.
bogdanm 84:0b3ab51c8877 942 * @note The main PLL can not be disabled if it is used as system clock source
bogdanm 84:0b3ab51c8877 943 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm 84:0b3ab51c8877 944 */
bogdanm 84:0b3ab51c8877 945 #define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm 84:0b3ab51c8877 946 #define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
bogdanm 84:0b3ab51c8877 947
bogdanm 84:0b3ab51c8877 948 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm 84:0b3ab51c8877 949 * @note This function must be used only when the main PLL is disabled.
bogdanm 84:0b3ab51c8877 950 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm 84:0b3ab51c8877 951 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 952 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm 84:0b3ab51c8877 953 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm 84:0b3ab51c8877 954 * @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
bogdanm 84:0b3ab51c8877 955 * This parameter must be one of the following values:
bogdanm 84:0b3ab51c8877 956 * @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
bogdanm 84:0b3ab51c8877 957 * @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
bogdanm 84:0b3ab51c8877 958 * @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
bogdanm 84:0b3ab51c8877 959 * @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
bogdanm 84:0b3ab51c8877 960 * @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
bogdanm 84:0b3ab51c8877 961 * @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
bogdanm 84:0b3ab51c8877 962 * @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
bogdanm 84:0b3ab51c8877 963 * @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
bogdanm 84:0b3ab51c8877 964 * @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
bogdanm 84:0b3ab51c8877 965 * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
bogdanm 84:0b3ab51c8877 966 * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
bogdanm 84:0b3ab51c8877 967 * in Range 3.
bogdanm 84:0b3ab51c8877 968 * @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
bogdanm 84:0b3ab51c8877 969 * This parameter must be one of the following values:
bogdanm 84:0b3ab51c8877 970 * @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
bogdanm 84:0b3ab51c8877 971 * @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
bogdanm 84:0b3ab51c8877 972 * @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
bogdanm 84:0b3ab51c8877 973 */
bogdanm 84:0b3ab51c8877 974
bogdanm 84:0b3ab51c8877 975 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__ ,__PLLDIV__ ) \
bogdanm 84:0b3ab51c8877 976 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)| (__PLLDIV__)| (__RCC_PLLSource__)))
bogdanm 84:0b3ab51c8877 977
bogdanm 84:0b3ab51c8877 978 /** @brief Macro to get the clock source used as system clock.
bogdanm 84:0b3ab51c8877 979 * @retval The clock source used as system clock. The returned value can be one
bogdanm 84:0b3ab51c8877 980 * of the following:
bogdanm 84:0b3ab51c8877 981 * - RCC_CFGR_SWS_HSI: HSI used as system clock.
bogdanm 84:0b3ab51c8877 982 * - RCC_CFGR_SWS_HSE: HSE used as system clock.
bogdanm 84:0b3ab51c8877 983 * - RCC_CFGR_SWS_PLL: PLL used as system clock.
bogdanm 84:0b3ab51c8877 984 */
bogdanm 84:0b3ab51c8877 985 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
bogdanm 84:0b3ab51c8877 986
bogdanm 84:0b3ab51c8877 987 /** @brief Macro to get the oscillator used as PLL clock source.
bogdanm 84:0b3ab51c8877 988 * @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm 84:0b3ab51c8877 989 * of the following:
bogdanm 84:0b3ab51c8877 990 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm 84:0b3ab51c8877 991 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm 84:0b3ab51c8877 992 */
bogdanm 84:0b3ab51c8877 993 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
bogdanm 84:0b3ab51c8877 994
bogdanm 84:0b3ab51c8877 995 /** @defgroup RCC_Flags_Interrupts_Management
bogdanm 84:0b3ab51c8877 996 * @brief macros to manage the specified RCC Flags and interrupts.
bogdanm 84:0b3ab51c8877 997 * @{
bogdanm 84:0b3ab51c8877 998 */
bogdanm 84:0b3ab51c8877 999
bogdanm 84:0b3ab51c8877 1000 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
bogdanm 84:0b3ab51c8877 1001 * the selected interrupts).
bogdanm 84:0b3ab51c8877 1002 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
bogdanm 84:0b3ab51c8877 1003 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
bogdanm 84:0b3ab51c8877 1004 * automatically generated. The NMI will be executed indefinitely, and
bogdanm 84:0b3ab51c8877 1005 * since NMI has higher priority than any other IRQ (and main program)
bogdanm 84:0b3ab51c8877 1006 * the application will be stacked in the NMI ISR unless the CSS interrupt
bogdanm 84:0b3ab51c8877 1007 * pending bit is cleared.
bogdanm 84:0b3ab51c8877 1008 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm 84:0b3ab51c8877 1009 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 1010 * @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm 84:0b3ab51c8877 1011 * @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm 84:0b3ab51c8877 1012 * @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm 84:0b3ab51c8877 1013 * @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm 84:0b3ab51c8877 1014 * @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm 84:0b3ab51c8877 1015 * @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm 84:0b3ab51c8877 1016 * @arg RCC_IT_LSECSS: LSE CSS interrupt
bogdanm 84:0b3ab51c8877 1017 */
bogdanm 84:0b3ab51c8877 1018 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIER_BYTE0_ADDRESS |= (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 1019
bogdanm 84:0b3ab51c8877 1020 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
bogdanm 84:0b3ab51c8877 1021 * the selected interrupts).
bogdanm 84:0b3ab51c8877 1022 * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
bogdanm 84:0b3ab51c8877 1023 * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
bogdanm 84:0b3ab51c8877 1024 * automatically generated. The NMI will be executed indefinitely, and
bogdanm 84:0b3ab51c8877 1025 * since NMI has higher priority than any other IRQ (and main program)
bogdanm 84:0b3ab51c8877 1026 * the application will be stacked in the NMI ISR unless the CSS interrupt
bogdanm 84:0b3ab51c8877 1027 * pending bit is cleared.
bogdanm 84:0b3ab51c8877 1028 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm 84:0b3ab51c8877 1029 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 1030 * @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm 84:0b3ab51c8877 1031 * @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm 84:0b3ab51c8877 1032 * @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm 84:0b3ab51c8877 1033 * @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm 84:0b3ab51c8877 1034 * @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm 84:0b3ab51c8877 1035 * @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm 84:0b3ab51c8877 1036 * @arg RCC_IT_LSECSS: LSE CSS interrupt
bogdanm 84:0b3ab51c8877 1037 */
bogdanm 84:0b3ab51c8877 1038 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIER_BYTE0_ADDRESS &= ~(__INTERRUPT__))
bogdanm 84:0b3ab51c8877 1039
bogdanm 84:0b3ab51c8877 1040 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm 84:0b3ab51c8877 1041 * bits to clear the selected interrupt pending bits.
bogdanm 84:0b3ab51c8877 1042 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 84:0b3ab51c8877 1043 * This parameter can be any combination of the following values:
bogdanm 84:0b3ab51c8877 1044 * @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm 84:0b3ab51c8877 1045 * @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm 84:0b3ab51c8877 1046 * @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm 84:0b3ab51c8877 1047 * @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm 84:0b3ab51c8877 1048 * @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm 84:0b3ab51c8877 1049 * @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm 84:0b3ab51c8877 1050 * @arg RCC_IT_LSECSS: LSE CSS interrupt
bogdanm 84:0b3ab51c8877 1051 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 84:0b3ab51c8877 1052 */
bogdanm 92:4fc01daae5a5 1053 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 1054
bogdanm 84:0b3ab51c8877 1055 /** @brief Check the RCC's interrupt has occurred or not.
bogdanm 84:0b3ab51c8877 1056 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm 84:0b3ab51c8877 1057 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1058 * @arg RCC_IT_LSIRDY: LSI ready interrupt
bogdanm 84:0b3ab51c8877 1059 * @arg RCC_IT_LSERDY: LSE ready interrupt
bogdanm 84:0b3ab51c8877 1060 * @arg RCC_IT_HSIRDY: HSI ready interrupt
bogdanm 84:0b3ab51c8877 1061 * @arg RCC_IT_HSERDY: HSE ready interrupt
bogdanm 84:0b3ab51c8877 1062 * @arg RCC_IT_PLLRDY: PLL ready interrupt
bogdanm 84:0b3ab51c8877 1063 * @arg RCC_IT_MSIRDY: MSI ready interrupt
bogdanm 84:0b3ab51c8877 1064 * @arg RCC_IT_LSECSS: LSE CSS interrupt
bogdanm 84:0b3ab51c8877 1065 * @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm 84:0b3ab51c8877 1066 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 1067 */
bogdanm 84:0b3ab51c8877 1068 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 1069
bogdanm 84:0b3ab51c8877 1070 /** @brief Set RMVF bit to clear the reset flags.
bogdanm 84:0b3ab51c8877 1071 * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm 84:0b3ab51c8877 1072 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
bogdanm 84:0b3ab51c8877 1073 */
bogdanm 84:0b3ab51c8877 1074 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
bogdanm 84:0b3ab51c8877 1075
bogdanm 84:0b3ab51c8877 1076 /** @brief Check RCC flag is set or not.
bogdanm 84:0b3ab51c8877 1077 * @param __FLAG__: specifies the flag to check.
bogdanm 84:0b3ab51c8877 1078 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 1079 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
bogdanm 84:0b3ab51c8877 1080 * @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
bogdanm 84:0b3ab51c8877 1081 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
bogdanm 84:0b3ab51c8877 1082 * @arg RCC_FLAG_PLLRDY: PLL clock ready
bogdanm 84:0b3ab51c8877 1083 * @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
bogdanm 84:0b3ab51c8877 1084 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
bogdanm 84:0b3ab51c8877 1085 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
bogdanm 84:0b3ab51c8877 1086 * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
bogdanm 84:0b3ab51c8877 1087 * @arg RCC_FLAG_PINRST: Pin reset
bogdanm 84:0b3ab51c8877 1088 * @arg RCC_FLAG_PORRST: POR/PDR reset
bogdanm 84:0b3ab51c8877 1089 * @arg RCC_FLAG_SFTRST: Software reset
bogdanm 84:0b3ab51c8877 1090 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
bogdanm 84:0b3ab51c8877 1091 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
bogdanm 84:0b3ab51c8877 1092 * @arg RCC_FLAG_LPWRRST: Low Power reset
bogdanm 84:0b3ab51c8877 1093 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 1094 */
bogdanm 84:0b3ab51c8877 1095 #define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm 84:0b3ab51c8877 1096 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
bogdanm 84:0b3ab51c8877 1097 RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
bogdanm 84:0b3ab51c8877 1098
bogdanm 84:0b3ab51c8877 1099 /**
bogdanm 84:0b3ab51c8877 1100 * @}
bogdanm 84:0b3ab51c8877 1101 */
bogdanm 84:0b3ab51c8877 1102
bogdanm 84:0b3ab51c8877 1103 #define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
bogdanm 84:0b3ab51c8877 1104 /**
bogdanm 84:0b3ab51c8877 1105 * @}
bogdanm 84:0b3ab51c8877 1106 */
bogdanm 84:0b3ab51c8877 1107
bogdanm 84:0b3ab51c8877 1108 /* Include RCC HAL Extension module */
bogdanm 85:024bf7f99721 1109 #include "stm32l0xx_hal_rcc_ex.h"
bogdanm 84:0b3ab51c8877 1110
bogdanm 84:0b3ab51c8877 1111 /* Exported functions --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 1112 /* Initialization and de-initialization methods ******************************/
bogdanm 84:0b3ab51c8877 1113 void HAL_RCC_DeInit(void);
bogdanm 84:0b3ab51c8877 1114 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 84:0b3ab51c8877 1115 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm 84:0b3ab51c8877 1116
bogdanm 84:0b3ab51c8877 1117 /* Peripheral Control methods ************************************************/
bogdanm 84:0b3ab51c8877 1118 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm 84:0b3ab51c8877 1119 void HAL_RCC_EnableCSS(void);
bogdanm 84:0b3ab51c8877 1120 uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm 84:0b3ab51c8877 1121 uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm 84:0b3ab51c8877 1122 uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm 84:0b3ab51c8877 1123 uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm 84:0b3ab51c8877 1124 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm 84:0b3ab51c8877 1125 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
bogdanm 84:0b3ab51c8877 1126
bogdanm 84:0b3ab51c8877 1127 /* CSS NMI IRQ handler */
bogdanm 84:0b3ab51c8877 1128 void HAL_RCC_NMI_IRQHandler(void);
bogdanm 84:0b3ab51c8877 1129
bogdanm 84:0b3ab51c8877 1130 /* User Callbacks in non blocking mode (IT mode) */
bogdanm 84:0b3ab51c8877 1131 void HAL_RCC_CCSCallback(void);
bogdanm 84:0b3ab51c8877 1132
bogdanm 84:0b3ab51c8877 1133 /**
bogdanm 84:0b3ab51c8877 1134 * @}
bogdanm 84:0b3ab51c8877 1135 */
bogdanm 84:0b3ab51c8877 1136
bogdanm 84:0b3ab51c8877 1137 /**
bogdanm 84:0b3ab51c8877 1138 * @}
bogdanm 84:0b3ab51c8877 1139 */
bogdanm 84:0b3ab51c8877 1140
bogdanm 84:0b3ab51c8877 1141 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 1142 }
bogdanm 84:0b3ab51c8877 1143 #endif
bogdanm 84:0b3ab51c8877 1144
bogdanm 84:0b3ab51c8877 1145 #endif /* __STM32L0xx_HAL_RCC_H */
bogdanm 84:0b3ab51c8877 1146
bogdanm 84:0b3ab51c8877 1147 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/