Revision 1:c125f4e65df7, committed 2021-11-03

Comitter:

rajathr

Date:

Wed Nov 03 05:31:26 2021 +0000

Parent:

0:716b93ab9a58

Commit message:

Commit as on 3rd Nov at 1.31 AM

Changed in this revision

--- a/gpio.c	Fri Oct 29 20:56:20 2021 +0000
+++ b/gpio.c	Wed Nov 03 05:31:26 2021 +0000
@@ -13,6 +13,16 @@
 #define PORTF_ODR_REGISTER (PORTF_BASE_ADDRESS + 0x14)
 #define PORTF_AFR1_REGISTER (PORTF_BASE_ADDRESS + 0x20)
 
+/* Below are defined Address of Port B and corresponding registers*/
+#define PORTB_BASE_ADDRESS              ((uint32_t)0x40020400)
+#define PORTB_MODER_REGISTER            (PORTB_BASE_ADDRESS + 0x00)
+#define PORTB_OTYPER_REGISTER           (PORTB_BASE_ADDRESS + 0x04)
+#define PORTB_OSPEEDR_REGISTER          (PORTB_BASE_ADDRESS + 0x08)
+#define PORTB_PUPDR_REGISTER            (PORTB_BASE_ADDRESS + 0x0C)
+#define PORTB_IDR_REGISTER              (PORTB_BASE_ADDRESS + 0x10)
+#define PORTB_ODR_REGISTER              (PORTB_BASE_ADDRESS + 0x14)
+#define PORTB_AFR1_REGISTER             (PORTB_BASE_ADDRESS + 0x20)
+
 
 
 void InitPortFPin7asAnalog(void)
@@ -52,5 +62,57 @@
 }
 
 
+void InitPortBPin0asOutput(void)
+{
+    uint32_t *reg; /*Define Pointer*/
+    RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); /* Enable the clock */
+    
+    reg = (uint32_t *)PORTB_MODER_REGISTER;
+    *reg = *reg & (~((uint32_t)0x03)); /*Clear last two bits of Moder Register*/
+    *reg = *reg | ((uint32_t)0x01); /* Set the last two pins corresponding to Pin0 as Output Mode - 01 */
+    
+    reg = (uint32_t *)PORTB_OTYPER_REGISTER;
+    *reg = *reg & (~((uint32_t)0x01)); /* Clear the last bit of OTYPER REGISTER*/
+    *reg = *reg | ((uint32_t)0x00);/*Statement is to set the OTYPER REGISTER TO 0 - Push Pull Type*/
+    
+    reg = (uint32_t *)PORTB_PUPDR_REGISTER;
+    *reg = *reg & (~((uint32_t)0x03)); /* Clear the last two bits of PUPDR REGISTER*/
+    *reg = *reg | ((uint32_t)0x00);/*Statement is to set the PUPDR REGISTER TO 00 - No Pull Up No Pull Down Type*/
+    
+    reg=(uint32_t *)PORTB_OSPEEDR_REGISTER;
+    *reg=*reg&(~((uint32_t)0x11)); /* Clear the last two bits of OSPEEDR REGISTER*/
+    *reg=*reg|((uint32_t)0x11); /* Set the last two bits of OSPEEDR REGISTER to High Speed*/
+    
+    reg = (uint32_t *)PORTB_ODR_REGISTER;
+    *reg = *reg | ((uint32_t)0x01); /* Setting the ODR REGISTER TO HIGH TO START WITH - Last bit is 1*/
+}
+
 
 
+void toggleGPIOB0(void)
+{
+    uint32_t value;
+    uint32_t *reg; /* Defining the variables*/
+    
+    reg = (uint32_t *)PORTB_ODR_REGISTER; /*Initializing the current value of ODR REGISTER*/
+    value = *reg & ((uint32_t)0x1); /* Reading the value of last bit of current ODR REGISTER - Stored in reg*/
+    
+    if (value > 0)
+    {
+        /* The bit is high initially*/
+        /*Need to set it to low now*/
+        *reg = *reg & (~((uint32_t)0x1));
+    }
+    
+    else
+    {
+        /* The bit is low initially*/
+        /* Need to set it to high now*/
+        *reg = *reg | ((uint32_t)0x01);
+    }
+}
+
+
+
+
+

--- a/gpio.h	Fri Oct 29 20:56:20 2021 +0000
+++ b/gpio.h	Wed Nov 03 05:31:26 2021 +0000
@@ -14,6 +14,12 @@
 /*Defining function that initializes Port F Pin 7,8,9 as Analog Output*/
 void InitPortFPin7Pin8Pin9asAnalog(void);
 
+/*Defining function that initializes Port B Pin 0 as Output*/
+void InitPortBPin0asOutput(void);
+
+/*Defining function that Toggles Port B Pin 0*/
+void toggleGPIOB0(void);
+
 
 #ifdef __cplusplus
 }

--- a/hardware_adc.c	Fri Oct 29 20:56:20 2021 +0000
+++ b/hardware_adc.c	Wed Nov 03 05:31:26 2021 +0000
@@ -60,17 +60,20 @@
      //Initialize GPIO F 7 as Analog
      InitPortFPin7asAnalog();
      
-     initDMAForAdc3_1Channel();              //FUNCTION IS DEFINED
+     initDMAForAdc3_1Channel();              //FUNCTION IS DEFINED // CHECK FOR THIS FUNCTION IN MAIN
      enableDMAForAdc3_1channels();           //FUNCTION IS DEFINED
      
      //Writing Pre Scale Value divided by 4 - 01 in bits 17&16 of CCR Register
      reg = (uint32_t *)ADC_CCR_REGISTER;
      *reg = 0x10000; 
      
-     //Clear Status Register                    //QUESTION - IS THIS ACTION MANDATORY ??
-     reg = (uint32_t *)ADC_3_SR_REGISTER;
-     *reg = 0;
-        
+     //STATUS REGISTER IS CLEARED IN START CONVERSION FUNCTION
+     
+//     //Clear Status Register                    //QUESTION - IS THIS ACTION MANDATORY ??
+//     reg = (uint32_t *)ADC_3_SR_REGISTER;
+//     *reg = 0;
+//        
+
      //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED - EOCIE
      reg = (uint32_t *)ADC_3_CR1_REGISTER;
      *reg = 0; //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED - EOCIE
@@ -79,13 +82,12 @@
      //Configure ADC External trigger disabled, right data alignment, DMA Enabled ,
      //EOC is set at the end of each regular conversion, continuous conversion enabled 
      reg = (uint32_t *)ADC_3_CR2_REGISTER;
-     *reg = 0;
      *reg = ((uint32_t)0x02) + ((uint32_t)0x100) + ((uint32_t)0x400);
      //*reg = ADC_E0CS + ADC_CONT + ADC_DDS + ADC_DMA;   //DO YOU HAVE TO WRITE TO THIS REGISTER OR READ THE VALUE ???
         
      //There will be 1 Channel (Channel 5) in the sequence of conversions - SQR1
      reg = (uint32_t *)ADC_3_SQR1_REGISTER;
-     *reg = (uint32_t)0x100000;
+     *reg = 0; //1 conversion is 0000
      
      //Configure Channels 5 to max sampling times (480 cycles)
      reg = (uint32_t *)ADC_3_SMPR2_REGISTER;
@@ -95,7 +97,7 @@
      reg = (uint32_t *)ADC_3_SQR3_REGISTER;
      * reg = 0x05; //WRITING 7 TO SQR1 (BITS 0 TO 4) IN SQR3 REGISTER
      
-     enableADC3();
+     enableADC3(); //ADDITIONAL LINE - IT ALREADY IS PRESENT IN START ADC CONVERSION
      
      //Start a software conversion
      //Need to do this separately
@@ -118,27 +120,30 @@
      initDMAForAdc3_3Channels();             //FUNCTION IS DEFINED
      enableDMAForAdc3_3channels();           //FUNCTION IS DEFINED
      
+     //I HAVE NOT CLEARED STATUS REGISTER - NO NEED - STATUS REGISTER IS CLEARED WHILE CALLING FUNCTION - START CONVERSION
+     
      //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED , SCAN MODE ENABLED 
      //TO BE ABLE TO SCAN A GROUP OF CHANNELS
      reg = (uint32_t *)ADC_3_CR1_REGISTER;
-     *reg = ADC_SCAN;
+     //*reg = 0; //IS THIS STATEMENT MANDATORY TO SET 25TH and 24th BIT AS 00
+     *reg = (uint32_t)0x100 ;  //THIS STATEMENT ALSO SETS 25TH and 24th BIT AS 00 but it does set the SCAN MODE ON
      
-     //Configure ADC External trigger dissabled, right data alignment, DMA ,
+     //Configure ADC External trigger dissabled (29th and 28th Bit is set to 0), right data alignment (11th bit is 0), DMA ,
      //EOC is set at the end of each regular conversion, continuous conversion enabled 
      reg = (uint32_t *)ADC_3_CR2_REGISTER;
-     *reg = ADC_E0CS + ADC_CONT + ADC_DDS + ADC_DMA;
+     *reg = (uint32_t)0x100 + (uint32_t)0x02 + (uint32_t)0x400; //Is the 10th bit supposed to be set to 0 - EC0 SET AT THE END OF EACH CONVERSION
      
      //There will be 3 channels in the sequence of conversions
      reg = (uint32_t *)ADC_3_SQR1_REGISTER;
-     *reg = ADC_3_CONVERSIONS;
+     *reg = (uint32_t)0x200000; //0010 3 will be 2 actually
      
      //Configure Channels 5,6,7 to max sampling times (480 cycles)
      reg = (uint32_t *)ADC_3_SMPR2_REGISTER;
-     *reg = ADC_SMP_5_MX + ADC_SMP_6_MX + ADC_SMP_7_MX;
+     *reg = (uint32_t)0x38000 + (uint32_t)0x1C0000 + (uint32_t)0xE00000; //In the order of 5th Channel set to 480 Cycles , 6th Channel set to 480 Cycles , 7th Channel set to 480 Cycles
      
      //Configure the sequence of conversion for the ADC (5,6,7)
      reg = (uint32_t *)ADC_3_SQR3_REGISTER;
-     * reg = (ADC_CHANNEL_5_MORT2<<ADC_SQ1) + (ADC_CHANNEL_6_MORT2<<ADC_SQ2) + (ADC_CHANNEL_7_MORT2<<ADC_SQ3);
+     * reg = (uint32_t)0x05 + (uint32_t)0xC0 + (uint32_t)0x1C00; //In the order of SQ1 written to 5, SQ2 written to 6 . SQ3 writtent to 7
      
      enableADC3();
      
@@ -155,4 +160,16 @@
      reg = (uint32_t *)ADC_3_CR2_REGISTER;
      *reg= *reg | ((uint32_t)0x01);
 }    
-     
\ No newline at end of file
+
+
+//FUNCTION TO START ADC CONVERSION
+void startADCConversion(void)
+{
+     uint32_t * reg;
+     
+     reg = (uint32_t *)ADC_3_SR_REGISTER;
+     *reg = 0;
+     
+     reg = (uint32_t *)ADC_3_CR2_REGISTER;
+     *reg = *reg | 0x01;
+}     
\ No newline at end of file

--- a/hardware_adc.h	Fri Oct 29 20:56:20 2021 +0000
+++ b/hardware_adc.h	Wed Nov 03 05:31:26 2021 +0000
@@ -17,6 +17,9 @@
 //Definig Function that enables ADC3
 void enableADC3(void);
 
+//DEFINING FUNCTION TO START ADC CONVERSION
+void startADCConversion(void);
+
 #ifdef __cplusplus
 }
 #endif

--- a/hardware_dma_controller.c	Fri Oct 29 20:56:20 2021 +0000
+++ b/hardware_dma_controller.c	Wed Nov 03 05:31:26 2021 +0000
@@ -26,14 +26,20 @@
 #define DMA_SxCR_DIR_PERTOMEM           0
 #define DMA_SxCR_STREAM_ENABLE          1
 
-uint16_t adcDmaDataStorageBuffer[3]; //Variable Definition to store read values
-uint16_t adcDmaDataStorageBuffer[1]; //Variable Definition to store read value
+
+#define ADC_REGISTER_BASE_ADDRESS   ((uint32_t)0x40012000)
+#define ADC_3_BASE_ADDRESS          (ADC_REGISTER_BASE_ADDRESS + 0x200)
+#define ADC_3_DR_REGISTER           (ADC_3_BASE_ADDRESS + 0x4C)
+
+
+uint16_t adcDmaDataStorageBuffer_3_Channel[3]; //Variable Definition to store read values
+uint16_t adcDmaDataStorageBuffer_1_Channel[1]; //Variable Definition to store read value
 
 
 //FUNCTION GIVEN BY PROFESSOR TO SETUP DMA TO READ VALUES FROM 3 PINS
 void initDMAForAdc3_1Channel(void)
 {
-    uint32_t reg;
+    uint32_t * reg;
     RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); /* Enable the clock */
     
     // Configure Stream 0 to use Channel 2 - ADC3
@@ -50,7 +56,7 @@
     
     //We will transfer to the adcDmaDataStorageBuffer we created
     reg = (uint32_t *)DMA2_S0M0AR_REGISTER;
-    *reg = (uint32_t)&adcDmaDataStorageBuffer[0]; //QUESTION - WHY IS THIS ZERO??? DIDNT UNDERSTAND THIS STATEMENT
+    *reg = (uint32_t)&adcDmaDataStorageBuffer_1_Channel[0]; //QUESTION - WHY IS THIS ZERO??? DIDNT UNDERSTAND THIS STATEMENT
     
 }
 
@@ -59,7 +65,7 @@
 //FUNCTION GIVEN BY PROFESSOR TO SETUP DMA TO READ VALUES FROM 3 PINS
 void initDMAForAdc3_3Channels(void)
 {
-    uint32_t reg;
+    uint32_t * reg;
     RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); /* Enable the clock */
     
     // Configure Stream 0 to use Channel 2 (ADC3)
@@ -72,11 +78,11 @@
     
     //We will transfer from the ADC3 Data Register
     reg = (uint32_t *)DMA2_S0PAR_REGISTER;
-    *reg = ADC_3_DR_REGISTER; //THIS FUNCTION IS NOT DETECTED
+    *reg = ADC_3_DR_REGISTER; //THIS FUNCTION IS DETECTED
     
     //We will transfer to the adcDmaDataStorageBuffer we just created
     reg = (uint32_t *)DMA2_S0M0AR_REGISTER;
-    *reg = (uint32_t)& adcDmaDataStorageBuffer[0];
+    *reg = (uint32_t)& adcDmaDataStorageBuffer_3_Channel[0];
     
 }
 
@@ -97,12 +103,17 @@
 
 
 
-uint16_t returnADC3StoredValue(uint8_t index)
+uint16_t returnADC3StoredValue3Channel(uint8_t index)
 {
-    return adcDmaDataStorageBuffer[index];
+    return adcDmaDataStorageBuffer_3_Channel[index];
 }
     
     
+uint16_t returnADC3StoredValue1Channel(uint8_t index)
+{
+    return adcDmaDataStorageBuffer_1_Channel[index];
+}
+    
      
      
 

--- a/hardware_dma_controller.h	Fri Oct 29 20:56:20 2021 +0000
+++ b/hardware_dma_controller.h	Wed Nov 03 05:31:26 2021 +0000
@@ -14,8 +14,12 @@
 /*Defining function that initializes DMA FOR ADC 3 - 1 CHANNELS*/
 void initDMAForAdc3_1Channel(void);
 
-/*Defining function that returns ADC value to DMA Storage Value*/
-uint16_t returnADC3StoredValue(uint8_t index);
+/*Defining function that returns ADC value to DMA Storage Value FOR 3 CHANNEL*/
+uint16_t returnADC3StoredValue3Channel(uint8_t index);
+
+/*Defining function that returns ADC value to DMA Storage Value FOR 1 CHANNELS*/
+uint16_t returnADC3StoredValue1Channel(uint8_t index);
+
 
 /*Defining function that enables DMA for ADC3 - 3 CHANNELS*/
 void enableDMAForAdc3_3channels (void);

--- a/interrupt.c	Fri Oct 29 20:56:20 2021 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,142 +0,0 @@
-#include "hardware_timer.h"
-#include "gpio.h"
-#include "stm32f4xx_rcc_mort.h"
-#include "interrupt.h"
-
-/*Below are defined all Timers and flags required */ //COPYING ALL VALUES AND DEFINITIONS FROM HARDWARE_TIMER3.C
-#define TIM3_BASE_ADDRESS                                   ((uint32_t)0x40000400)
-#define TIM3_STATUS_REGISTER                                (TIM3_BASE_ADDRESS + 0x10)
-#define TIM3_PSC_REGISTER                                   (TIM3_BASE_ADDRESS + 0x28)
-#define TIM3_AUTORELOAD_REGISTER                            (TIM3_BASE_ADDRESS + 0x2C)
-#define TIM3_COUNTER_REGISTER                               (TIM3_BASE_ADDRESS + 0x24)
-#define TIM3_CAPTURE_COMPARE_MODE_2_REGISTER                (TIM3_BASE_ADDRESS + 0x1C)
-#define TIM_CCMR13_OC1M_0                                   (0b00010000)
-#define TIM_CCMR13_OC1M_1                                   (0b00100000)
-#define TIM_CCMR13_OC1M_2                                   (0b01000000)
-#define TIM_CCMR13_OCPE                                     (0b00001000)
-#define TIM_CCMR13_OUTPUT                                   (0x00)
-#define TIM3_COMPARE3_REGISTER                              (TIM3_BASE_ADDRESS + 0x3C)
-#define TIM3_CAPTURE_COMPARE_ENABLE_REGISTER                (TIM3_BASE_ADDRESS + 0x20)
-#define TIM3_CR1_REGISTER1                                  (TIM3_BASE_ADDRESS + 0x00)
-#define TIM3_CAPTURE_COMPARE_MODE_1_REGISTER                (TIM3_BASE_ADDRESS + 0x18)
-#define TIM3_CAPTURE_COMPARE_REGISTER_1                     (TIM3_BASE_ADDRESS + 0x34)
-#define TIM3_CCMR2_CC3S_OUTPUT                              (0b11111100)
-#define TIM3_CCMR2_OC3FE                                    (0b11111011)
-#define TIM3_CCMR2_OC3PE                                    (0b00001000)
-#define TIM3_CCMR2_OC3M1                                    (0b11101111)
-#define TIM3_CCMR2_OC3M2 (0b01100000)
-
-# define TIM3_INTERRUPT_ENABLE_REGISTER (TIM3_BASE_ADDRESS + 0x0C)
-
-/* MACRO definitions----------------------------------------------------------*/
-#define SYSTEM_CONTROL_BASE_ADDRESS                         (0xE000E000)
-#define NVIC_BASE_ADDRESS                                   (SYSTEM_CONTROL_BASE_ADDRESS + 0x100)
-#define NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31             (NVIC_BASE_ADDRESS)
-#define NVIC_INTERRUPT_SET_ENABLE_REGISTER_32_63            (NVIC_BASE_ADDRESS+0x4)
-#define NVIC_INTERRUPT_SET_ENABLE_REGISTER_64_95            (NVIC_BASE_ADDRESS+0x8)
-#define TIM3_INTERRUPT_BIT                                  (0x20000000)
-
-#define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31           (NVIC_BASE_ADDRESS + 0x80)
-#define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_32_63          (NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 + 0x4)
-#define NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_64_95          (NVIC_INTERRUPT_CLEAR_ENABLE_REGISTER_0_31 + 0x8)
-#define NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31            (NVIC_BASE_ADDRESS + 0x100)
-#define NVIC_INTERRUPT_SET_PENDING_REGISTER_32_63           (NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 + 0x4)
-#define NVIC_INTERRUPT_SET_PENDING_REGISTER_64_95           (NVIC_INTERRUPT_SET_PENDING_REGISTER_0_31 + 0x8)
-#define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31          (NVIC_BASE_ADDRESS + 0x180)
-#define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_32_63         (NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 + 0x4)
-#define NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_64_95         (NVIC_INTERRUPT_CLEAR_PENDING_REGISTER_0_31 + 0x8)
-#define EXTI9_5_INTERRUPT_BIT                               (0x800000)
-
-//For external interrupts:
-#define SYSCFG_BASE_ADDRESS                                 ((uint32_t)(0x40013800))
-#define SYSCFG_EXTERNAL_INTERRUPT_REGISTER_2                (SYSCFG_BASE_ADDRESS + 0x0C)
-#define SYSCFG_EXTERNAL_INTERRUPT_6_BITS                    ((uint32_t)0xF00) //flags for External interrupt register 2
-#define SYSCFG_EXTERNAL_INTERRUPT_6_PORTC                   ((uint32_t)0x200) 
-
-//External interrupt controller :
-#define EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS          ((uint32_t)(0x40013C00))
-#define EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER         (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS)
-#define EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER_EXTI6   ((uint32_t)0x40) //flags for external interrupt controller mask register
-#define EXTERNAL_INTERRUPT_CONTROLLER_RTSR                  (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x08)
-#define EXTERNAL_INTERRUPT_CONTROLLER_RTSR_EXTI6            ((uint32_t)0x40)
-#define EXTERNAL_INTERRUPT_CONTROLLER_FTSR                  (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x0C)
-#define EXTERNAL_INTERRUPT_CONTROLLER_FTSR_EXTI6            ((uint32_t)0x40)
-#define EXTERNAL_INTERRUPT_CONTROLLER_PENDING_REGISTER      (EXTERNAL_INTERRUPT_CONTROLLER_BASE_ADDRESS+0x14)
-#define EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6         ((uint32_t)0x40)
-
-
-void enableNVIC_Timer3(void)
-{
-    uint32_t * reg;
-    reg = (uint32_t *)NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31;
-    *reg = TIM3_INTERRUPT_BIT; 
-}
-
-void TIM3_IRQHandler(void)
-{
-    uint16_t * reg_pointer_16_sr;
-    uint16_t * reg_pointer_16_dier;
-    reg_pointer_16_sr = (uint16_t *)TIM3_STATUS_REGISTER;
-    reg_pointer_16_dier = (uint16_t *)TIM3_INTERRUPT_ENABLE_REGISTER;
- //check which interrupts fired and if they were supposed to fire, then clear the flags so they don’t keep firing,
-// then perform actions according to these interrupts
-//check if Output Compare 3 triggered the interrupt:
-    if (( (*reg_pointer_16_sr & 0x8) >0) && ( (*reg_pointer_16_dier & 0x8) >0))
-    {
- //clear interrupt
-    *reg_pointer_16_sr = ~((uint16_t)0x8);
- //perform action
-    clearGPIOB0(); 
-     }
-//check if Overflow triggered the interrupt: I.e. Timer Counter 3 >= Autorreload value
-    if (( (*reg_pointer_16_sr & 0x01) >0) && ( (*reg_pointer_16_dier & 0x1) >0))
-    {
- //clear interrupt
-    *reg_pointer_16_sr = ~((uint16_t)0x01);
- //perform action
-    setGPIOB0();
-    } 
-}
-
-void enableEXTI6OnPortC(void)
-{
-    uint32_t * reg;
- /*Init GPIO 6 C as input*/
-    initGpioC6AsInput();
- /*As a test, Init GPIO B0 as output for debugging*/
-    InitPortBPin0asOutput();
- /* Enable SYSCFG clock */
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- /*map EXTI6 to port C bit 6*/
-    reg = (uint32_t *)SYSCFG_EXTERNAL_INTERRUPT_REGISTER_2;
- //clear EXTI6
-    *reg = *reg & ~SYSCFG_EXTERNAL_INTERRUPT_6_BITS;
- //set EXTI6 to Port C
-    *reg = *reg | SYSCFG_EXTERNAL_INTERRUPT_6_PORTC; 
- /*un-mask EXTI6*/
-    reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER;
-    *reg = *reg | EXTERNAL_INTERRUPT_CONTROLLER_MASK_REGISTER_EXTI6;
- /*trigger on rising edge*/
-    reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_RTSR;
-    *reg = *reg | EXTERNAL_INTERRUPT_CONTROLLER_RTSR_EXTI6;
- /* set the NVIC to respond to EXTI9_5*/
-    reg = (uint32_t *)NVIC_INTERRUPT_SET_ENABLE_REGISTER_0_31;
-    *reg = EXTI9_5_INTERRUPT_BIT; 
-}
-
-void EXTI9_5_IRQHandler(void)
-{
-    uint32_t * reg;
-    reg = (uint32_t *)EXTERNAL_INTERRUPT_CONTROLLER_PENDING_REGISTER;
- //check which interrupt fired:
-    if ((*reg & EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6)>0)
- {
- //clear the interrupt:
-    *reg = EXTERNAL_INTERRUPT_CONTROLLER_PENDING_EXTI6;
- //toggle the LED
-    toggleGPIOB0();
- }
-}
-
-
-

--- a/interrupt.h	Fri Oct 29 20:56:20 2021 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,21 +0,0 @@
-#ifndef __INTERRUPT_H_
-#define __INTERRUPT_H_
-
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "main.h"
-
-//Defining function that enables Interrupt corresponding to TIMER 3 IN  NVIC
-void enableNVIC_Timer3(void);
-
-//Defining function that enables Interrupt configuration and handling
-void enableEXTI6OnPortC(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__INTERRUPT_H */
\ No newline at end of file

--- a/led1.c	Fri Oct 29 20:56:20 2021 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,12 +0,0 @@
-#include "led1.h"
-#include "gpio.h"
-
-void init_LED1(void)
-{
-    InitPortBPin0asOutput();   
-}
-
-void toggle_LED1(void)
-{
-    toggleGPIOB0();
-}

--- a/led1.h	Fri Oct 29 20:56:20 2021 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,20 +0,0 @@
-#ifndef __LED1_H_  //Mort: These labels need to be unique! otherwise it doesn't work!
-#define __LED1_H_
-
-#include "main_Lec9.h"
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*Defining Function that initializes the LED*/
-void init_LED1(void);
-
-/*Defining function that toggles the LED Switch*/
-void toggle_LED1(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__LED1_H */
\ No newline at end of file

--- a/main.cpp	Fri Oct 29 20:56:20 2021 +0000
+++ b/main.cpp	Wed Nov 03 05:31:26 2021 +0000
@@ -1,50 +1,47 @@
 #include "gpio.h"
-#include "led1.h"
-#include "main_Lec9.h" //Mort: including main_Lec9.h
 #include "mbed.h"
-#include "hardware_timer.h"
+#include "hardware_adc.h"
+#include "hardware_dma_controller.h"
 
 Serial pc(USBTX, USBRX);
 
 
 int main(void)
 {
-    //uint32_t i,j;
-    uint16_t countervalue;
-    uint16_t checkvalue;
-
-    //This is for first LED function
-    //init_LED1(); //Calling the initialization function - To initialize PortB as its corresponding functionality //Mort: Do not need to say void here
-    
+    uint32_t i,j,k;
+    j = 0;
     
-    //This is for Output Compare:
-    InitGPIOBPin0asOutputCompare();
-    TMR3CH3OutputCompare(); 
+    //For Design Problem 1 - Exercise 10 - START
+    initADC3_5_withDMA();
+    InitPortBPin0asOutput(); //initialize GPIOB as Output
+    startADCConversion(); 
+    //For Design Problem 1 - Exercise 10 - END
     
-    //This is for Input Capture:
-    InitGPIOCPin6asInputCapture();
-    TMR3CH1GPIOCPin6asInputCapture();
-      
-    while(true)
+    //For Design Problem 2 - Exercise 10 - START
+    initADC3_567_withDMA();
+    InitPortBPin0asOutput(); //initialize GPIOB as Output
+    startADCConversion(); 
+    //For Design Problem 2 - Exercise 10 - END
+    
+    while(1)
     {
-        // Create FOR Loop to have some delay between toggling
-//        for(i=1; i<100; i++) //Mort: Your code was fine, just your delay was too large.
-//        {
-//            //pc.printf("hi hi hi \n");
-//            j=j+1;
-//        }
-        //toggle_LED1(); //Function Call to toggle LED
-        
-        countervalue = readCounterValueIfFlagIsSet();
-        if (countervalue > 0 & checkvalue != countervalue)
+        for (i=0; i<10000000; i++)
         {
-            pc.printf("\nCounter Value is = %d", countervalue);
-            checkvalue = countervalue;
+            for(k=0; k<10000000; k++)
+            {
+                j=j+1; //Tiny Delay
+            }
         }
-    }    
+        
+        //Code for DMA - DESIGN PROBLEM 1 - Exercise 10 - START
+        pc.printf("ADC Value is %u\n", returnADC3StoredValue1Channel(0));
+        toggleGPIOB0();
+        //Code for DMA - DESIGN PROBLEM 1 - Exercise 10 - END
+        
+        
+        //Code for DMA - DESIGN PROBLEM 2 - Exercise 10 - START
+        pc.printf("ADC Value 1 is %u, ADC Value 2 is % u and ADC Value 3 is %u\n", returnADC3StoredValue3Channel(0), returnADC3StoredValue3Channel(1), returnADC3StoredValue3Channel(2));
+        toggleGPIOB0();
+        //Code for DMA - DESIGN PROBLEM 2 - Exercise 10 - END
+    }
 }
-
-void debugPrint(uint32_t what)
-{
-    pc.printf("The value is %u\n",what);    
-}

--- a/main.h	Fri Oct 29 20:56:20 2021 +0000
+++ b/main.h	Wed Nov 03 05:31:26 2021 +0000
@@ -1,6 +1,6 @@
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_LEC9_H_
-#define __MAIN__LEC9_H_
+#ifndef __MAIN__H_
+#define __MAIN___H_
 
 #ifdef __cplusplus
  extern "C" {
@@ -12,7 +12,7 @@
 
 
 /*Function definitions---------------------------------------------------------*/
-void debugPrint(uint32_t what);
+
 
 
 #ifdef __cplusplus