Rajath Ravi / Mbed 2 deprecated ADC_DMA_POST_LEC12

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Dependencies:   mbed

gpio.c@1:c125f4e65df7, 2021-11-03 (annotated)

Committer:
rajathr
Date:
Wed Nov 03 05:31:26 2021 +0000
Revision:
1:c125f4e65df7
Parent:
0:716b93ab9a58 
Commit as on 3rd Nov at 1.31 AM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rajathr 0:716b93ab9a58 1 #include "gpio.h"
rajathr 0:716b93ab9a58 2 #include "main.h"
rajathr 0:716b93ab9a58 3 #include "stm32f4xx_rcc_mort.h"
rajathr 0:716b93ab9a58 4
rajathr 0:716b93ab9a58 5
rajathr 0:716b93ab9a58 6 /* Below are defined Address of Port F and corresponding registers*/
rajathr 0:716b93ab9a58 7 #define PORTF_BASE_ADDRESS ((uint32_t)0x40021400)
rajathr 0:716b93ab9a58 8 #define PORTF_MODER_REGISTER (PORTF_BASE_ADDRESS + 0x00)
rajathr 0:716b93ab9a58 9 #define PORTF_OTYPER_REGISTER (PORTF_BASE_ADDRESS + 0x04)
rajathr 0:716b93ab9a58 10 #define PORTF_OSPEEDR_REGISTER (PORTF_BASE_ADDRESS + 0x08)
rajathr 0:716b93ab9a58 11 #define PORTF_PUPDR_REGISTER (PORTF_BASE_ADDRESS + 0x0C)
rajathr 0:716b93ab9a58 12 #define PORTF_IDR_REGISTER (PORTF_BASE_ADDRESS + 0x10)
rajathr 0:716b93ab9a58 13 #define PORTF_ODR_REGISTER (PORTF_BASE_ADDRESS + 0x14)
rajathr 0:716b93ab9a58 14 #define PORTF_AFR1_REGISTER (PORTF_BASE_ADDRESS + 0x20)
rajathr 0:716b93ab9a58 15
rajathr 1:c125f4e65df7 16 /* Below are defined Address of Port B and corresponding registers*/
rajathr 1:c125f4e65df7 17 #define PORTB_BASE_ADDRESS ((uint32_t)0x40020400)
rajathr 1:c125f4e65df7 18 #define PORTB_MODER_REGISTER (PORTB_BASE_ADDRESS + 0x00)
rajathr 1:c125f4e65df7 19 #define PORTB_OTYPER_REGISTER (PORTB_BASE_ADDRESS + 0x04)
rajathr 1:c125f4e65df7 20 #define PORTB_OSPEEDR_REGISTER (PORTB_BASE_ADDRESS + 0x08)
rajathr 1:c125f4e65df7 21 #define PORTB_PUPDR_REGISTER (PORTB_BASE_ADDRESS + 0x0C)
rajathr 1:c125f4e65df7 22 #define PORTB_IDR_REGISTER (PORTB_BASE_ADDRESS + 0x10)
rajathr 1:c125f4e65df7 23 #define PORTB_ODR_REGISTER (PORTB_BASE_ADDRESS + 0x14)
rajathr 1:c125f4e65df7 24 #define PORTB_AFR1_REGISTER (PORTB_BASE_ADDRESS + 0x20)
rajathr 1:c125f4e65df7 25
rajathr 0:716b93ab9a58 26
rajathr 0:716b93ab9a58 27
rajathr 0:716b93ab9a58 28 void InitPortFPin7asAnalog(void)
rajathr 0:716b93ab9a58 29 {
rajathr 0:716b93ab9a58 30 uint32_t *reg; /*Define Pointer*/
rajathr 0:716b93ab9a58 31 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOF, ENABLE); /* Enable the clock */
rajathr 0:716b93ab9a58 32
rajathr 0:716b93ab9a58 33 reg = (uint32_t *)PORTF_MODER_REGISTER;
rajathr 0:716b93ab9a58 34 *reg = *reg & (~((uint32_t)(0x03<<14))); /*Clear bits 14 & 15 of Moder Register*/
rajathr 0:716b93ab9a58 35 *reg = *reg | (uint32_t)(0x03<<14); /* Set the bits 14 & 15 as 11 - Analog Output Mode */
rajathr 0:716b93ab9a58 36
rajathr 0:716b93ab9a58 37 reg = (uint32_t *)PORTF_OTYPER_REGISTER;
rajathr 0:716b93ab9a58 38 *reg = *reg & (~((uint32_t)(0x01<<7))); /* Statement is to set the OTYPER REGISTER of Pin 7 TO 0 - Push Pull Type */
rajathr 0:716b93ab9a58 39
rajathr 0:716b93ab9a58 40
rajathr 0:716b93ab9a58 41 reg = (uint32_t *)PORTF_PUPDR_REGISTER;
rajathr 0:716b93ab9a58 42 *reg = *reg & (~((uint32_t)(0x03<<14))); /* Statement is to set the PUPDR REGISTER TO 00 - No Pull Up No Pull Down Type*/
rajathr 0:716b93ab9a58 43
rajathr 0:716b93ab9a58 44 }
rajathr 0:716b93ab9a58 45
rajathr 0:716b93ab9a58 46 void InitPortFPin7Pin8Pin9asAnalog(void)
rajathr 0:716b93ab9a58 47 {
rajathr 0:716b93ab9a58 48 uint32_t *reg; /*Define Pointer*/
rajathr 0:716b93ab9a58 49 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOF, ENABLE); /* Enable the clock */
rajathr 0:716b93ab9a58 50
rajathr 0:716b93ab9a58 51 reg = (uint32_t *)PORTF_MODER_REGISTER;
rajathr 0:716b93ab9a58 52 *reg = *reg & (~((uint32_t)(0x03<<14))+ (uint32_t)(0x03<<16) + (uint32_t)(0x03<<18)); /*Clear bits 14, 15, 16, 17, 18, 19 of Moder Register*/
rajathr 0:716b93ab9a58 53 *reg = *reg | ((uint32_t)(0x03<<14) + (uint32_t)(0x03<<16) + (uint32_t)(0x03<<18)); /* Set the bits 14, 15, 16, 17, 18, 19 as 11 - Analog Output Mode */
rajathr 0:716b93ab9a58 54
rajathr 0:716b93ab9a58 55 reg = (uint32_t *)PORTF_OTYPER_REGISTER;
rajathr 0:716b93ab9a58 56 *reg = *reg & (~((uint32_t)(0x01<<7)+ (uint32_t)(0x01<<8) + (uint32_t)(0x01<<9))); /* Statement is to set the OTYPER REGISTER of Pin 7, 8, 9 TO 0 - Push Pull Type */
rajathr 0:716b93ab9a58 57
rajathr 0:716b93ab9a58 58
rajathr 0:716b93ab9a58 59 reg = (uint32_t *)PORTF_PUPDR_REGISTER;
rajathr 0:716b93ab9a58 60 *reg = *reg & (~((uint32_t)(0x03<<14)+ (uint32_t)(0x03<<16) + (uint32_t)(0x03<<18) )); /* Statement is to set the PUPDR REGISTER OF PIN 7,8,9 TO 00 - No Pull Up No Pull Down Type*/
rajathr 0:716b93ab9a58 61
rajathr 0:716b93ab9a58 62 }
rajathr 0:716b93ab9a58 63
rajathr 0:716b93ab9a58 64
rajathr 1:c125f4e65df7 65 void InitPortBPin0asOutput(void)
rajathr 1:c125f4e65df7 66 {
rajathr 1:c125f4e65df7 67 uint32_t *reg; /*Define Pointer*/
rajathr 1:c125f4e65df7 68 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); /* Enable the clock */
rajathr 1:c125f4e65df7 69
rajathr 1:c125f4e65df7 70 reg = (uint32_t *)PORTB_MODER_REGISTER;
rajathr 1:c125f4e65df7 71 *reg = *reg & (~((uint32_t)0x03)); /*Clear last two bits of Moder Register*/
rajathr 1:c125f4e65df7 72 *reg = *reg | ((uint32_t)0x01); /* Set the last two pins corresponding to Pin0 as Output Mode - 01 */
rajathr 1:c125f4e65df7 73
rajathr 1:c125f4e65df7 74 reg = (uint32_t *)PORTB_OTYPER_REGISTER;
rajathr 1:c125f4e65df7 75 *reg = *reg & (~((uint32_t)0x01)); /* Clear the last bit of OTYPER REGISTER*/
rajathr 1:c125f4e65df7 76 *reg = *reg | ((uint32_t)0x00);/*Statement is to set the OTYPER REGISTER TO 0 - Push Pull Type*/
rajathr 1:c125f4e65df7 77
rajathr 1:c125f4e65df7 78 reg = (uint32_t *)PORTB_PUPDR_REGISTER;
rajathr 1:c125f4e65df7 79 *reg = *reg & (~((uint32_t)0x03)); /* Clear the last two bits of PUPDR REGISTER*/
rajathr 1:c125f4e65df7 80 *reg = *reg | ((uint32_t)0x00);/*Statement is to set the PUPDR REGISTER TO 00 - No Pull Up No Pull Down Type*/
rajathr 1:c125f4e65df7 81
rajathr 1:c125f4e65df7 82 reg=(uint32_t *)PORTB_OSPEEDR_REGISTER;
rajathr 1:c125f4e65df7 83 *reg=*reg&(~((uint32_t)0x11)); /* Clear the last two bits of OSPEEDR REGISTER*/
rajathr 1:c125f4e65df7 84 *reg=*reg|((uint32_t)0x11); /* Set the last two bits of OSPEEDR REGISTER to High Speed*/
rajathr 1:c125f4e65df7 85
rajathr 1:c125f4e65df7 86 reg = (uint32_t *)PORTB_ODR_REGISTER;
rajathr 1:c125f4e65df7 87 *reg = *reg | ((uint32_t)0x01); /* Setting the ODR REGISTER TO HIGH TO START WITH - Last bit is 1*/
rajathr 1:c125f4e65df7 88 }
rajathr 1:c125f4e65df7 89
rajathr 0:716b93ab9a58 90
rajathr 0:716b93ab9a58 91
rajathr 1:c125f4e65df7 92 void toggleGPIOB0(void)
rajathr 1:c125f4e65df7 93 {
rajathr 1:c125f4e65df7 94 uint32_t value;
rajathr 1:c125f4e65df7 95 uint32_t *reg; /* Defining the variables*/
rajathr 1:c125f4e65df7 96
rajathr 1:c125f4e65df7 97 reg = (uint32_t *)PORTB_ODR_REGISTER; /*Initializing the current value of ODR REGISTER*/
rajathr 1:c125f4e65df7 98 value = *reg & ((uint32_t)0x1); /* Reading the value of last bit of current ODR REGISTER - Stored in reg*/
rajathr 1:c125f4e65df7 99
rajathr 1:c125f4e65df7 100 if (value > 0)
rajathr 1:c125f4e65df7 101 {
rajathr 1:c125f4e65df7 102 /* The bit is high initially*/
rajathr 1:c125f4e65df7 103 /*Need to set it to low now*/
rajathr 1:c125f4e65df7 104 *reg = *reg & (~((uint32_t)0x1));
rajathr 1:c125f4e65df7 105 }
rajathr 1:c125f4e65df7 106
rajathr 1:c125f4e65df7 107 else
rajathr 1:c125f4e65df7 108 {
rajathr 1:c125f4e65df7 109 /* The bit is low initially*/
rajathr 1:c125f4e65df7 110 /* Need to set it to high now*/
rajathr 1:c125f4e65df7 111 *reg = *reg | ((uint32_t)0x01);
rajathr 1:c125f4e65df7 112 }
rajathr 1:c125f4e65df7 113 }
rajathr 1:c125f4e65df7 114
rajathr 1:c125f4e65df7 115
rajathr 1:c125f4e65df7 116
rajathr 1:c125f4e65df7 117
rajathr 1:c125f4e65df7 118