Rajath Ravi / Mbed 2 deprecated ADC_DMA_POST_LEC12

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Dependencies:   mbed

hardware_adc.c@1:c125f4e65df7, 2021-11-03 (annotated)

Committer:
rajathr
Date:
Wed Nov 03 05:31:26 2021 +0000
Revision:
1:c125f4e65df7
Parent:
0:716b93ab9a58 
Commit as on 3rd Nov at 1.31 AM

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rajathr 0:716b93ab9a58 1 #include "gpio.h"
rajathr 0:716b93ab9a58 2 #include "hardware_adc.h"
rajathr 0:716b93ab9a58 3 #include "stm32f4xx_rcc_mort.h"
rajathr 0:716b93ab9a58 4 #include "hardware_dma_controller.h"
rajathr 0:716b93ab9a58 5
rajathr 0:716b93ab9a58 6 //DEFINITION OF BASE ADDRESS FOR ADC1-ADC2-ADC3
rajathr 0:716b93ab9a58 7 #define ADC_REGISTER_BASE_ADDRESS ((uint32_t)0x40012000)
rajathr 0:716b93ab9a58 8
rajathr 0:716b93ab9a58 9 //DEFINITION OF BASE ADDRESS AND REGISTER ADDRESSES FOR ADC1
rajathr 0:716b93ab9a58 10 #define ADC_1_BASE_ADDRESS (ADC_REGISTER_BASE_ADDRESS + 0x000)
rajathr 0:716b93ab9a58 11 #define ADC_1_SR_REGISTER (ADC_1_BASE_ADDRESS + 0x00)
rajathr 0:716b93ab9a58 12 #define ADC_1_CR1_REGISTER (ADC_1_BASE_ADDRESS + 0x04)
rajathr 0:716b93ab9a58 13 #define ADC_1_CR2_REGISTER (ADC_1_BASE_ADDRESS + 0x08)
rajathr 0:716b93ab9a58 14 #define ADC_1_SMPR1_REGISTER (ADC_1_BASE_ADDRESS + 0x0C)
rajathr 0:716b93ab9a58 15 #define ADC_1_SMPR2_REGISTER (ADC_1_BASE_ADDRESS + 0x10)
rajathr 0:716b93ab9a58 16 #define ADC_1_SQR1_REGISTER (ADC_1_BASE_ADDRESS + 0x2C)
rajathr 0:716b93ab9a58 17 #define ADC_1_SQR2_REGISTER (ADC_1_BASE_ADDRESS + 0x30)
rajathr 0:716b93ab9a58 18 #define ADC_1_SQR3_REGISTER (ADC_1_BASE_ADDRESS + 0x34)
rajathr 0:716b93ab9a58 19 #define ADC_1_DR_REGISTER (ADC_1_BASE_ADDRESS + 0x4C)
rajathr 0:716b93ab9a58 20
rajathr 0:716b93ab9a58 21 //DEFINITION OF BASE ADDRESS AND REGISTER ADDRESSES FOR ADC2
rajathr 0:716b93ab9a58 22 #define ADC_2_BASE_ADDRESS (ADC_REGISTER_BASE_ADDRESS + 0x100)
rajathr 0:716b93ab9a58 23 #define ADC_2_SR_REGISTER (ADC_2_BASE_ADDRESS + 0x00)
rajathr 0:716b93ab9a58 24 #define ADC_2_CR1_REGISTER (ADC_2_BASE_ADDRESS + 0x04)
rajathr 0:716b93ab9a58 25 #define ADC_2_CR2_REGISTER (ADC_2_BASE_ADDRESS + 0x08)
rajathr 0:716b93ab9a58 26 #define ADC_2_SMPR1_REGISTER (ADC_2_BASE_ADDRESS + 0x0C)
rajathr 0:716b93ab9a58 27 #define ADC_2_SMPR2_REGISTER (ADC_2_BASE_ADDRESS + 0x10)
rajathr 0:716b93ab9a58 28 #define ADC_2_SQR1_REGISTER (ADC_2_BASE_ADDRESS + 0x2C)
rajathr 0:716b93ab9a58 29 #define ADC_2_SQR2_REGISTER (ADC_2_BASE_ADDRESS + 0x30)
rajathr 0:716b93ab9a58 30 #define ADC_2_SQR3_REGISTER (ADC_2_BASE_ADDRESS + 0x34)
rajathr 0:716b93ab9a58 31 #define ADC_2_DR_REGISTER (ADC_2_BASE_ADDRESS + 0x4C)
rajathr 0:716b93ab9a58 32
rajathr 0:716b93ab9a58 33 //DEFINITION OF BASE ADDRESS AND REGISTER ADDRESSES FOR ADC3
rajathr 0:716b93ab9a58 34 #define ADC_3_BASE_ADDRESS (ADC_REGISTER_BASE_ADDRESS + 0x200)
rajathr 0:716b93ab9a58 35 #define ADC_3_SR_REGISTER (ADC_3_BASE_ADDRESS + 0x00)
rajathr 0:716b93ab9a58 36 #define ADC_3_CR1_REGISTER (ADC_3_BASE_ADDRESS + 0x04)
rajathr 0:716b93ab9a58 37 #define ADC_3_CR2_REGISTER (ADC_3_BASE_ADDRESS + 0x08)
rajathr 0:716b93ab9a58 38 #define ADC_3_SMPR1_REGISTER (ADC_3_BASE_ADDRESS + 0x0C)
rajathr 0:716b93ab9a58 39 #define ADC_3_SMPR2_REGISTER (ADC_3_BASE_ADDRESS + 0x10)
rajathr 0:716b93ab9a58 40 #define ADC_3_SQR1_REGISTER (ADC_3_BASE_ADDRESS + 0x2C)
rajathr 0:716b93ab9a58 41 #define ADC_3_SQR2_REGISTER (ADC_3_BASE_ADDRESS + 0x30)
rajathr 0:716b93ab9a58 42 #define ADC_3_SQR3_REGISTER (ADC_3_BASE_ADDRESS + 0x34)
rajathr 0:716b93ab9a58 43 #define ADC_3_DR_REGISTER (ADC_3_BASE_ADDRESS + 0x4C)
rajathr 0:716b93ab9a58 44
rajathr 0:716b93ab9a58 45 //DEFINITION OF BASE ADDRESS AND REGISTER ADDRESSES FOR COMMON REGISTERS
rajathr 0:716b93ab9a58 46 #define ADC_COMMON_REGISTERS (ADC_REGISTER_BASE_ADDRESS + 0x300)
rajathr 0:716b93ab9a58 47 #define ADC_CSR_REGISTER (ADC_COMMON_REGISTERS + 0x00)
rajathr 0:716b93ab9a58 48 #define ADC_CCR_REGISTER (ADC_COMMON_REGISTERS + 0x04)
rajathr 0:716b93ab9a58 49
rajathr 0:716b93ab9a58 50
rajathr 0:716b93ab9a58 51
rajathr 0:716b93ab9a58 52 //FUNCTION DEFINED FOR - ADC 3 CONTINUOUS CONVERSION USING CHANNEL 5
rajathr 0:716b93ab9a58 53 void initADC3_5_withDMA(void)
rajathr 0:716b93ab9a58 54 {
rajathr 0:716b93ab9a58 55 uint32_t * reg;
rajathr 0:716b93ab9a58 56
rajathr 0:716b93ab9a58 57 //Turn on ADC3 BUS CLOCKS
rajathr 0:716b93ab9a58 58 RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE); /* Enable the clock */
rajathr 0:716b93ab9a58 59
rajathr 0:716b93ab9a58 60 //Initialize GPIO F 7 as Analog
rajathr 0:716b93ab9a58 61 InitPortFPin7asAnalog();
rajathr 0:716b93ab9a58 62
rajathr 1:c125f4e65df7 63 initDMAForAdc3_1Channel(); //FUNCTION IS DEFINED // CHECK FOR THIS FUNCTION IN MAIN
rajathr 0:716b93ab9a58 64 enableDMAForAdc3_1channels(); //FUNCTION IS DEFINED
rajathr 0:716b93ab9a58 65
rajathr 0:716b93ab9a58 66 //Writing Pre Scale Value divided by 4 - 01 in bits 17&16 of CCR Register
rajathr 0:716b93ab9a58 67 reg = (uint32_t *)ADC_CCR_REGISTER;
rajathr 0:716b93ab9a58 68 *reg = 0x10000;
rajathr 0:716b93ab9a58 69
rajathr 1:c125f4e65df7 70 //STATUS REGISTER IS CLEARED IN START CONVERSION FUNCTION
rajathr 1:c125f4e65df7 71
rajathr 1:c125f4e65df7 72 // //Clear Status Register //QUESTION - IS THIS ACTION MANDATORY ??
rajathr 1:c125f4e65df7 73 // reg = (uint32_t *)ADC_3_SR_REGISTER;
rajathr 1:c125f4e65df7 74 // *reg = 0;
rajathr 1:c125f4e65df7 75 //
rajathr 1:c125f4e65df7 76
rajathr 0:716b93ab9a58 77 //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED - EOCIE
rajathr 0:716b93ab9a58 78 reg = (uint32_t *)ADC_3_CR1_REGISTER;
rajathr 0:716b93ab9a58 79 *reg = 0; //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED - EOCIE
rajathr 0:716b93ab9a58 80 //*reg = *reg & (~((uint32_t)0x3000000)) & (~((uint32_t)0x20)); //DO YOU HAVE TO WRITE TO THIS REGISTER OR READ THE VALUE ???
rajathr 0:716b93ab9a58 81
rajathr 0:716b93ab9a58 82 //Configure ADC External trigger disabled, right data alignment, DMA Enabled ,
rajathr 0:716b93ab9a58 83 //EOC is set at the end of each regular conversion, continuous conversion enabled
rajathr 0:716b93ab9a58 84 reg = (uint32_t *)ADC_3_CR2_REGISTER;
rajathr 0:716b93ab9a58 85 *reg = ((uint32_t)0x02) + ((uint32_t)0x100) + ((uint32_t)0x400);
rajathr 0:716b93ab9a58 86 //*reg = ADC_E0CS + ADC_CONT + ADC_DDS + ADC_DMA; //DO YOU HAVE TO WRITE TO THIS REGISTER OR READ THE VALUE ???
rajathr 0:716b93ab9a58 87
rajathr 0:716b93ab9a58 88 //There will be 1 Channel (Channel 5) in the sequence of conversions - SQR1
rajathr 0:716b93ab9a58 89 reg = (uint32_t *)ADC_3_SQR1_REGISTER;
rajathr 1:c125f4e65df7 90 *reg = 0; //1 conversion is 0000
rajathr 0:716b93ab9a58 91
rajathr 0:716b93ab9a58 92 //Configure Channels 5 to max sampling times (480 cycles)
rajathr 0:716b93ab9a58 93 reg = (uint32_t *)ADC_3_SMPR2_REGISTER;
rajathr 0:716b93ab9a58 94 *reg = 0x38000; //Writing 111 to bits 15,16&17
rajathr 0:716b93ab9a58 95
rajathr 0:716b93ab9a58 96 //Configure the sequence of conversion for the ADC (7)
rajathr 0:716b93ab9a58 97 reg = (uint32_t *)ADC_3_SQR3_REGISTER;
rajathr 0:716b93ab9a58 98 * reg = 0x05; //WRITING 7 TO SQR1 (BITS 0 TO 4) IN SQR3 REGISTER
rajathr 0:716b93ab9a58 99
rajathr 1:c125f4e65df7 100 enableADC3(); //ADDITIONAL LINE - IT ALREADY IS PRESENT IN START ADC CONVERSION
rajathr 0:716b93ab9a58 101
rajathr 0:716b93ab9a58 102 //Start a software conversion
rajathr 0:716b93ab9a58 103 //Need to do this separately
rajathr 0:716b93ab9a58 104
rajathr 0:716b93ab9a58 105 }
rajathr 0:716b93ab9a58 106
rajathr 0:716b93ab9a58 107
rajathr 0:716b93ab9a58 108
rajathr 0:716b93ab9a58 109 //FUNCTION DEFINED BY PROFESSOR - ADC 3 SCAN CONTINUOUS CONVERSION USING 3 CHANNELS
rajathr 0:716b93ab9a58 110 void initADC3_567_withDMA(void)
rajathr 0:716b93ab9a58 111 {
rajathr 0:716b93ab9a58 112 uint32_t * reg;
rajathr 0:716b93ab9a58 113
rajathr 0:716b93ab9a58 114 //Turn on ADC3 BUS CLOCKS
rajathr 0:716b93ab9a58 115 RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC3, ENABLE); /* Enable the clock */
rajathr 0:716b93ab9a58 116
rajathr 0:716b93ab9a58 117 //Initialize GPIO F 7 8 9 as Analog
rajathr 0:716b93ab9a58 118 InitPortFPin7Pin8Pin9asAnalog();
rajathr 0:716b93ab9a58 119
rajathr 0:716b93ab9a58 120 initDMAForAdc3_3Channels(); //FUNCTION IS DEFINED
rajathr 0:716b93ab9a58 121 enableDMAForAdc3_3channels(); //FUNCTION IS DEFINED
rajathr 0:716b93ab9a58 122
rajathr 1:c125f4e65df7 123 //I HAVE NOT CLEARED STATUS REGISTER - NO NEED - STATUS REGISTER IS CLEARED WHILE CALLING FUNCTION - START CONVERSION
rajathr 1:c125f4e65df7 124
rajathr 0:716b93ab9a58 125 //Configure ADC 12BIT Resolution, END OF CONVERSION INTERRUPT DISABLED , SCAN MODE ENABLED
rajathr 0:716b93ab9a58 126 //TO BE ABLE TO SCAN A GROUP OF CHANNELS
rajathr 0:716b93ab9a58 127 reg = (uint32_t *)ADC_3_CR1_REGISTER;
rajathr 1:c125f4e65df7 128 //*reg = 0; //IS THIS STATEMENT MANDATORY TO SET 25TH and 24th BIT AS 00
rajathr 1:c125f4e65df7 129 *reg = (uint32_t)0x100 ; //THIS STATEMENT ALSO SETS 25TH and 24th BIT AS 00 but it does set the SCAN MODE ON
rajathr 0:716b93ab9a58 130
rajathr 1:c125f4e65df7 131 //Configure ADC External trigger dissabled (29th and 28th Bit is set to 0), right data alignment (11th bit is 0), DMA ,
rajathr 0:716b93ab9a58 132 //EOC is set at the end of each regular conversion, continuous conversion enabled
rajathr 0:716b93ab9a58 133 reg = (uint32_t *)ADC_3_CR2_REGISTER;
rajathr 1:c125f4e65df7 134 *reg = (uint32_t)0x100 + (uint32_t)0x02 + (uint32_t)0x400; //Is the 10th bit supposed to be set to 0 - EC0 SET AT THE END OF EACH CONVERSION
rajathr 0:716b93ab9a58 135
rajathr 0:716b93ab9a58 136 //There will be 3 channels in the sequence of conversions
rajathr 0:716b93ab9a58 137 reg = (uint32_t *)ADC_3_SQR1_REGISTER;
rajathr 1:c125f4e65df7 138 *reg = (uint32_t)0x200000; //0010 3 will be 2 actually
rajathr 0:716b93ab9a58 139
rajathr 0:716b93ab9a58 140 //Configure Channels 5,6,7 to max sampling times (480 cycles)
rajathr 0:716b93ab9a58 141 reg = (uint32_t *)ADC_3_SMPR2_REGISTER;
rajathr 1:c125f4e65df7 142 *reg = (uint32_t)0x38000 + (uint32_t)0x1C0000 + (uint32_t)0xE00000; //In the order of 5th Channel set to 480 Cycles , 6th Channel set to 480 Cycles , 7th Channel set to 480 Cycles
rajathr 0:716b93ab9a58 143
rajathr 0:716b93ab9a58 144 //Configure the sequence of conversion for the ADC (5,6,7)
rajathr 0:716b93ab9a58 145 reg = (uint32_t *)ADC_3_SQR3_REGISTER;
rajathr 1:c125f4e65df7 146 * reg = (uint32_t)0x05 + (uint32_t)0xC0 + (uint32_t)0x1C00; //In the order of SQ1 written to 5, SQ2 written to 6 . SQ3 writtent to 7
rajathr 0:716b93ab9a58 147
rajathr 0:716b93ab9a58 148 enableADC3();
rajathr 0:716b93ab9a58 149
rajathr 0:716b93ab9a58 150 //Start a software conversion
rajathr 0:716b93ab9a58 151 //Need to do this separately
rajathr 0:716b93ab9a58 152
rajathr 0:716b93ab9a58 153 }
rajathr 0:716b93ab9a58 154
rajathr 0:716b93ab9a58 155
rajathr 0:716b93ab9a58 156 //FUNCTON TO TURN ON ADC3
rajathr 0:716b93ab9a58 157 void enableADC3(void)
rajathr 0:716b93ab9a58 158 {
rajathr 0:716b93ab9a58 159 uint32_t * reg;
rajathr 0:716b93ab9a58 160 reg = (uint32_t *)ADC_3_CR2_REGISTER;
rajathr 0:716b93ab9a58 161 *reg= *reg | ((uint32_t)0x01);
rajathr 0:716b93ab9a58 162 }
rajathr 1:c125f4e65df7 163
rajathr 1:c125f4e65df7 164
rajathr 1:c125f4e65df7 165 //FUNCTION TO START ADC CONVERSION
rajathr 1:c125f4e65df7 166 void startADCConversion(void)
rajathr 1:c125f4e65df7 167 {
rajathr 1:c125f4e65df7 168 uint32_t * reg;
rajathr 1:c125f4e65df7 169
rajathr 1:c125f4e65df7 170 reg = (uint32_t *)ADC_3_SR_REGISTER;
rajathr 1:c125f4e65df7 171 *reg = 0;
rajathr 1:c125f4e65df7 172
rajathr 1:c125f4e65df7 173 reg = (uint32_t *)ADC_3_CR2_REGISTER;
rajathr 1:c125f4e65df7 174 *reg = *reg | 0x01;
rajathr 1:c125f4e65df7 175 }