in de mix
Fork of RF24 by
RF24.cpp@2:3bdf0d9bb71f, 2015-11-05 (annotated)
- Committer:
- akashvibhute
- Date:
- Thu Nov 05 05:40:23 2015 +0000
- Revision:
- 2:3bdf0d9bb71f
- Parent:
- 1:00706a42491e
- Child:
- 3:e94be00fd19e
Updated with TMRh20's RF24 library on Nov/04/2015 from https://github.com/TMRh20; Porting completed on Nov/05/2015
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
akashvibhute | 0:bb74812ac6bb | 1 | /* |
akashvibhute | 0:bb74812ac6bb | 2 | Copyright (C) 2011 J. Coliz <maniacbug@ymail.com> |
akashvibhute | 0:bb74812ac6bb | 3 | |
akashvibhute | 0:bb74812ac6bb | 4 | This program is free software; you can redistribute it and/or |
akashvibhute | 0:bb74812ac6bb | 5 | modify it under the terms of the GNU General Public License |
akashvibhute | 0:bb74812ac6bb | 6 | version 2 as published by the Free Software Foundation. |
akashvibhute | 0:bb74812ac6bb | 7 | */ |
akashvibhute | 0:bb74812ac6bb | 8 | |
akashvibhute | 2:3bdf0d9bb71f | 9 | #include "nRF24L01.h" |
akashvibhute | 2:3bdf0d9bb71f | 10 | #include "RF24_config.h" |
akashvibhute | 0:bb74812ac6bb | 11 | #include "RF24.h" |
akashvibhute | 0:bb74812ac6bb | 12 | |
akashvibhute | 0:bb74812ac6bb | 13 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 14 | |
akashvibhute | 2:3bdf0d9bb71f | 15 | void RF24::csn(bool mode) |
akashvibhute | 0:bb74812ac6bb | 16 | { |
akashvibhute | 0:bb74812ac6bb | 17 | csn_pin = mode; |
akashvibhute | 2:3bdf0d9bb71f | 18 | wait_us(5); |
akashvibhute | 2:3bdf0d9bb71f | 19 | |
akashvibhute | 2:3bdf0d9bb71f | 20 | |
akashvibhute | 2:3bdf0d9bb71f | 21 | |
akashvibhute | 2:3bdf0d9bb71f | 22 | |
akashvibhute | 2:3bdf0d9bb71f | 23 | |
akashvibhute | 2:3bdf0d9bb71f | 24 | |
akashvibhute | 2:3bdf0d9bb71f | 25 | |
akashvibhute | 2:3bdf0d9bb71f | 26 | |
akashvibhute | 2:3bdf0d9bb71f | 27 | |
akashvibhute | 2:3bdf0d9bb71f | 28 | |
akashvibhute | 2:3bdf0d9bb71f | 29 | |
akashvibhute | 2:3bdf0d9bb71f | 30 | |
akashvibhute | 2:3bdf0d9bb71f | 31 | |
akashvibhute | 2:3bdf0d9bb71f | 32 | |
akashvibhute | 2:3bdf0d9bb71f | 33 | |
akashvibhute | 2:3bdf0d9bb71f | 34 | |
akashvibhute | 2:3bdf0d9bb71f | 35 | |
akashvibhute | 2:3bdf0d9bb71f | 36 | |
akashvibhute | 2:3bdf0d9bb71f | 37 | |
akashvibhute | 2:3bdf0d9bb71f | 38 | |
akashvibhute | 2:3bdf0d9bb71f | 39 | |
akashvibhute | 2:3bdf0d9bb71f | 40 | |
akashvibhute | 2:3bdf0d9bb71f | 41 | |
akashvibhute | 2:3bdf0d9bb71f | 42 | |
akashvibhute | 2:3bdf0d9bb71f | 43 | |
akashvibhute | 2:3bdf0d9bb71f | 44 | |
akashvibhute | 2:3bdf0d9bb71f | 45 | |
akashvibhute | 2:3bdf0d9bb71f | 46 | |
akashvibhute | 2:3bdf0d9bb71f | 47 | |
akashvibhute | 2:3bdf0d9bb71f | 48 | |
akashvibhute | 2:3bdf0d9bb71f | 49 | |
akashvibhute | 2:3bdf0d9bb71f | 50 | |
akashvibhute | 2:3bdf0d9bb71f | 51 | |
akashvibhute | 2:3bdf0d9bb71f | 52 | |
akashvibhute | 2:3bdf0d9bb71f | 53 | |
akashvibhute | 2:3bdf0d9bb71f | 54 | |
akashvibhute | 2:3bdf0d9bb71f | 55 | |
akashvibhute | 2:3bdf0d9bb71f | 56 | |
akashvibhute | 2:3bdf0d9bb71f | 57 | |
akashvibhute | 2:3bdf0d9bb71f | 58 | |
akashvibhute | 0:bb74812ac6bb | 59 | |
akashvibhute | 0:bb74812ac6bb | 60 | } |
akashvibhute | 0:bb74812ac6bb | 61 | |
akashvibhute | 0:bb74812ac6bb | 62 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 63 | |
akashvibhute | 2:3bdf0d9bb71f | 64 | void RF24::ce(bool level) |
akashvibhute | 0:bb74812ac6bb | 65 | { |
akashvibhute | 0:bb74812ac6bb | 66 | ce_pin = level; |
akashvibhute | 2:3bdf0d9bb71f | 67 | |
akashvibhute | 0:bb74812ac6bb | 68 | } |
akashvibhute | 0:bb74812ac6bb | 69 | |
akashvibhute | 0:bb74812ac6bb | 70 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 71 | |
akashvibhute | 2:3bdf0d9bb71f | 72 | inline void RF24::beginTransaction() { |
akashvibhute | 2:3bdf0d9bb71f | 73 | csn_pin=LOW; |
akashvibhute | 2:3bdf0d9bb71f | 74 | |
akashvibhute | 2:3bdf0d9bb71f | 75 | |
akashvibhute | 2:3bdf0d9bb71f | 76 | |
akashvibhute | 2:3bdf0d9bb71f | 77 | } |
akashvibhute | 2:3bdf0d9bb71f | 78 | |
akashvibhute | 2:3bdf0d9bb71f | 79 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 80 | |
akashvibhute | 2:3bdf0d9bb71f | 81 | inline void RF24::endTransaction() { |
akashvibhute | 2:3bdf0d9bb71f | 82 | csn_pin=HIGH; |
akashvibhute | 2:3bdf0d9bb71f | 83 | |
akashvibhute | 2:3bdf0d9bb71f | 84 | |
akashvibhute | 2:3bdf0d9bb71f | 85 | |
akashvibhute | 2:3bdf0d9bb71f | 86 | } |
akashvibhute | 2:3bdf0d9bb71f | 87 | |
akashvibhute | 2:3bdf0d9bb71f | 88 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 89 | |
akashvibhute | 0:bb74812ac6bb | 90 | uint8_t RF24::read_register(uint8_t reg, uint8_t* buf, uint8_t len) |
akashvibhute | 0:bb74812ac6bb | 91 | { |
akashvibhute | 0:bb74812ac6bb | 92 | uint8_t status; |
akashvibhute | 0:bb74812ac6bb | 93 | |
akashvibhute | 2:3bdf0d9bb71f | 94 | beginTransaction(); |
akashvibhute | 0:bb74812ac6bb | 95 | status = spi.write( R_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 0:bb74812ac6bb | 96 | while ( len-- ) |
akashvibhute | 0:bb74812ac6bb | 97 | *buf++ = spi.write(0xff); |
akashvibhute | 2:3bdf0d9bb71f | 98 | endTransaction(); |
akashvibhute | 0:bb74812ac6bb | 99 | |
akashvibhute | 2:3bdf0d9bb71f | 100 | |
akashvibhute | 2:3bdf0d9bb71f | 101 | |
akashvibhute | 2:3bdf0d9bb71f | 102 | |
akashvibhute | 2:3bdf0d9bb71f | 103 | |
akashvibhute | 2:3bdf0d9bb71f | 104 | |
akashvibhute | 2:3bdf0d9bb71f | 105 | |
akashvibhute | 2:3bdf0d9bb71f | 106 | |
akashvibhute | 2:3bdf0d9bb71f | 107 | |
akashvibhute | 2:3bdf0d9bb71f | 108 | |
akashvibhute | 2:3bdf0d9bb71f | 109 | |
akashvibhute | 2:3bdf0d9bb71f | 110 | |
akashvibhute | 2:3bdf0d9bb71f | 111 | |
akashvibhute | 2:3bdf0d9bb71f | 112 | |
akashvibhute | 2:3bdf0d9bb71f | 113 | |
akashvibhute | 2:3bdf0d9bb71f | 114 | |
akashvibhute | 2:3bdf0d9bb71f | 115 | |
akashvibhute | 2:3bdf0d9bb71f | 116 | |
akashvibhute | 2:3bdf0d9bb71f | 117 | |
akashvibhute | 2:3bdf0d9bb71f | 118 | |
akashvibhute | 2:3bdf0d9bb71f | 119 | |
akashvibhute | 2:3bdf0d9bb71f | 120 | |
akashvibhute | 2:3bdf0d9bb71f | 121 | |
akashvibhute | 0:bb74812ac6bb | 122 | return status; |
akashvibhute | 0:bb74812ac6bb | 123 | } |
akashvibhute | 0:bb74812ac6bb | 124 | |
akashvibhute | 0:bb74812ac6bb | 125 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 126 | |
akashvibhute | 0:bb74812ac6bb | 127 | uint8_t RF24::read_register(uint8_t reg) |
akashvibhute | 0:bb74812ac6bb | 128 | { |
akashvibhute | 2:3bdf0d9bb71f | 129 | uint8_t result; |
akashvibhute | 2:3bdf0d9bb71f | 130 | |
akashvibhute | 2:3bdf0d9bb71f | 131 | beginTransaction(); |
akashvibhute | 0:bb74812ac6bb | 132 | spi.write( R_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 2:3bdf0d9bb71f | 133 | result = spi.write(0xff); |
akashvibhute | 2:3bdf0d9bb71f | 134 | endTransaction(); |
akashvibhute | 0:bb74812ac6bb | 135 | |
akashvibhute | 2:3bdf0d9bb71f | 136 | |
akashvibhute | 2:3bdf0d9bb71f | 137 | |
akashvibhute | 2:3bdf0d9bb71f | 138 | |
akashvibhute | 2:3bdf0d9bb71f | 139 | |
akashvibhute | 2:3bdf0d9bb71f | 140 | |
akashvibhute | 2:3bdf0d9bb71f | 141 | |
akashvibhute | 2:3bdf0d9bb71f | 142 | |
akashvibhute | 2:3bdf0d9bb71f | 143 | |
akashvibhute | 2:3bdf0d9bb71f | 144 | |
akashvibhute | 2:3bdf0d9bb71f | 145 | |
akashvibhute | 2:3bdf0d9bb71f | 146 | |
akashvibhute | 2:3bdf0d9bb71f | 147 | |
akashvibhute | 2:3bdf0d9bb71f | 148 | |
akashvibhute | 2:3bdf0d9bb71f | 149 | |
akashvibhute | 2:3bdf0d9bb71f | 150 | |
akashvibhute | 2:3bdf0d9bb71f | 151 | |
akashvibhute | 0:bb74812ac6bb | 152 | return result; |
akashvibhute | 0:bb74812ac6bb | 153 | } |
akashvibhute | 0:bb74812ac6bb | 154 | |
akashvibhute | 0:bb74812ac6bb | 155 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 156 | |
akashvibhute | 0:bb74812ac6bb | 157 | uint8_t RF24::write_register(uint8_t reg, const uint8_t* buf, uint8_t len) |
akashvibhute | 0:bb74812ac6bb | 158 | { |
akashvibhute | 0:bb74812ac6bb | 159 | uint8_t status; |
akashvibhute | 0:bb74812ac6bb | 160 | |
akashvibhute | 2:3bdf0d9bb71f | 161 | beginTransaction(); |
akashvibhute | 0:bb74812ac6bb | 162 | status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 0:bb74812ac6bb | 163 | while ( len-- ) |
akashvibhute | 0:bb74812ac6bb | 164 | spi.write(*buf++); |
akashvibhute | 2:3bdf0d9bb71f | 165 | endTransaction(); |
akashvibhute | 0:bb74812ac6bb | 166 | |
akashvibhute | 2:3bdf0d9bb71f | 167 | |
akashvibhute | 2:3bdf0d9bb71f | 168 | |
akashvibhute | 2:3bdf0d9bb71f | 169 | |
akashvibhute | 2:3bdf0d9bb71f | 170 | |
akashvibhute | 2:3bdf0d9bb71f | 171 | |
akashvibhute | 2:3bdf0d9bb71f | 172 | |
akashvibhute | 2:3bdf0d9bb71f | 173 | |
akashvibhute | 2:3bdf0d9bb71f | 174 | |
akashvibhute | 2:3bdf0d9bb71f | 175 | |
akashvibhute | 2:3bdf0d9bb71f | 176 | |
akashvibhute | 2:3bdf0d9bb71f | 177 | |
akashvibhute | 2:3bdf0d9bb71f | 178 | |
akashvibhute | 2:3bdf0d9bb71f | 179 | |
akashvibhute | 2:3bdf0d9bb71f | 180 | |
akashvibhute | 2:3bdf0d9bb71f | 181 | |
akashvibhute | 2:3bdf0d9bb71f | 182 | |
akashvibhute | 2:3bdf0d9bb71f | 183 | |
akashvibhute | 2:3bdf0d9bb71f | 184 | |
akashvibhute | 0:bb74812ac6bb | 185 | return status; |
akashvibhute | 0:bb74812ac6bb | 186 | } |
akashvibhute | 0:bb74812ac6bb | 187 | |
akashvibhute | 0:bb74812ac6bb | 188 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 189 | |
akashvibhute | 0:bb74812ac6bb | 190 | uint8_t RF24::write_register(uint8_t reg, uint8_t value) |
akashvibhute | 0:bb74812ac6bb | 191 | { |
akashvibhute | 0:bb74812ac6bb | 192 | uint8_t status; |
akashvibhute | 0:bb74812ac6bb | 193 | |
akashvibhute | 2:3bdf0d9bb71f | 194 | IF_SERIAL_DEBUG(printf(PSTR("write_register(%02x,%02x)\r\n"),reg,value)); |
akashvibhute | 0:bb74812ac6bb | 195 | |
akashvibhute | 2:3bdf0d9bb71f | 196 | |
akashvibhute | 2:3bdf0d9bb71f | 197 | beginTransaction(); |
akashvibhute | 0:bb74812ac6bb | 198 | status = spi.write( W_REGISTER | ( REGISTER_MASK & reg ) ); |
akashvibhute | 0:bb74812ac6bb | 199 | spi.write(value); |
akashvibhute | 2:3bdf0d9bb71f | 200 | endTransaction(); |
akashvibhute | 2:3bdf0d9bb71f | 201 | |
akashvibhute | 2:3bdf0d9bb71f | 202 | |
akashvibhute | 2:3bdf0d9bb71f | 203 | |
akashvibhute | 2:3bdf0d9bb71f | 204 | |
akashvibhute | 2:3bdf0d9bb71f | 205 | |
akashvibhute | 2:3bdf0d9bb71f | 206 | |
akashvibhute | 2:3bdf0d9bb71f | 207 | |
akashvibhute | 2:3bdf0d9bb71f | 208 | |
akashvibhute | 2:3bdf0d9bb71f | 209 | |
akashvibhute | 2:3bdf0d9bb71f | 210 | |
akashvibhute | 2:3bdf0d9bb71f | 211 | |
akashvibhute | 2:3bdf0d9bb71f | 212 | |
akashvibhute | 2:3bdf0d9bb71f | 213 | |
akashvibhute | 2:3bdf0d9bb71f | 214 | |
akashvibhute | 2:3bdf0d9bb71f | 215 | return status; |
akashvibhute | 2:3bdf0d9bb71f | 216 | } |
akashvibhute | 2:3bdf0d9bb71f | 217 | |
akashvibhute | 2:3bdf0d9bb71f | 218 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 219 | uint8_t RF24::write_payload(const void* buf, uint8_t len, const uint8_t writeType) |
akashvibhute | 2:3bdf0d9bb71f | 220 | { |
akashvibhute | 2:3bdf0d9bb71f | 221 | uint8_t status; |
akashvibhute | 2:3bdf0d9bb71f | 222 | const uint8_t* current = reinterpret_cast<const uint8_t*>(buf); |
akashvibhute | 2:3bdf0d9bb71f | 223 | |
akashvibhute | 2:3bdf0d9bb71f | 224 | uint8_t data_len = rf24_min(data_len, payload_size); |
akashvibhute | 2:3bdf0d9bb71f | 225 | uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len; |
akashvibhute | 2:3bdf0d9bb71f | 226 | |
akashvibhute | 2:3bdf0d9bb71f | 227 | //printf("[Writing %u bytes %u blanks]",data_len,blank_len); |
akashvibhute | 2:3bdf0d9bb71f | 228 | IF_SERIAL_DEBUG( printf("[Writing %u bytes %u blanks]\n",data_len,blank_len); ); |
akashvibhute | 2:3bdf0d9bb71f | 229 | |
akashvibhute | 0:bb74812ac6bb | 230 | |
akashvibhute | 2:3bdf0d9bb71f | 231 | beginTransaction(); |
akashvibhute | 2:3bdf0d9bb71f | 232 | status = spi.write( W_TX_PAYLOAD ); |
akashvibhute | 2:3bdf0d9bb71f | 233 | while ( data_len-- ) |
akashvibhute | 2:3bdf0d9bb71f | 234 | spi.write(*current++); |
akashvibhute | 2:3bdf0d9bb71f | 235 | while ( blank_len-- ) |
akashvibhute | 2:3bdf0d9bb71f | 236 | spi.write(0); |
akashvibhute | 2:3bdf0d9bb71f | 237 | |
akashvibhute | 2:3bdf0d9bb71f | 238 | endTransaction(); |
akashvibhute | 2:3bdf0d9bb71f | 239 | |
akashvibhute | 2:3bdf0d9bb71f | 240 | |
akashvibhute | 2:3bdf0d9bb71f | 241 | |
akashvibhute | 2:3bdf0d9bb71f | 242 | |
akashvibhute | 2:3bdf0d9bb71f | 243 | |
akashvibhute | 2:3bdf0d9bb71f | 244 | |
akashvibhute | 2:3bdf0d9bb71f | 245 | |
akashvibhute | 2:3bdf0d9bb71f | 246 | |
akashvibhute | 2:3bdf0d9bb71f | 247 | |
akashvibhute | 2:3bdf0d9bb71f | 248 | |
akashvibhute | 2:3bdf0d9bb71f | 249 | |
akashvibhute | 2:3bdf0d9bb71f | 250 | |
akashvibhute | 2:3bdf0d9bb71f | 251 | |
akashvibhute | 2:3bdf0d9bb71f | 252 | |
akashvibhute | 2:3bdf0d9bb71f | 253 | |
akashvibhute | 2:3bdf0d9bb71f | 254 | |
akashvibhute | 2:3bdf0d9bb71f | 255 | |
akashvibhute | 2:3bdf0d9bb71f | 256 | |
akashvibhute | 2:3bdf0d9bb71f | 257 | |
akashvibhute | 2:3bdf0d9bb71f | 258 | |
akashvibhute | 2:3bdf0d9bb71f | 259 | |
akashvibhute | 2:3bdf0d9bb71f | 260 | |
akashvibhute | 2:3bdf0d9bb71f | 261 | |
akashvibhute | 0:bb74812ac6bb | 262 | return status; |
akashvibhute | 0:bb74812ac6bb | 263 | } |
akashvibhute | 0:bb74812ac6bb | 264 | |
akashvibhute | 0:bb74812ac6bb | 265 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 266 | |
akashvibhute | 2:3bdf0d9bb71f | 267 | uint8_t RF24::read_payload(void* buf, uint8_t data_len) |
akashvibhute | 0:bb74812ac6bb | 268 | { |
akashvibhute | 0:bb74812ac6bb | 269 | uint8_t status; |
akashvibhute | 0:bb74812ac6bb | 270 | uint8_t* current = reinterpret_cast<uint8_t*>(buf); |
akashvibhute | 0:bb74812ac6bb | 271 | |
akashvibhute | 2:3bdf0d9bb71f | 272 | if(data_len > payload_size) data_len = payload_size; |
akashvibhute | 0:bb74812ac6bb | 273 | uint8_t blank_len = dynamic_payloads_enabled ? 0 : payload_size - data_len; |
akashvibhute | 0:bb74812ac6bb | 274 | |
akashvibhute | 0:bb74812ac6bb | 275 | //printf("[Reading %u bytes %u blanks]",data_len,blank_len); |
akashvibhute | 2:3bdf0d9bb71f | 276 | |
akashvibhute | 2:3bdf0d9bb71f | 277 | IF_SERIAL_DEBUG( printf("[Reading %u bytes %u blanks]\n",data_len,blank_len); ); |
akashvibhute | 2:3bdf0d9bb71f | 278 | |
akashvibhute | 2:3bdf0d9bb71f | 279 | beginTransaction(); |
akashvibhute | 0:bb74812ac6bb | 280 | status = spi.write( R_RX_PAYLOAD ); |
akashvibhute | 0:bb74812ac6bb | 281 | while ( data_len-- ) |
akashvibhute | 0:bb74812ac6bb | 282 | *current++ = spi.write(0xff); |
akashvibhute | 0:bb74812ac6bb | 283 | while ( blank_len-- ) |
akashvibhute | 0:bb74812ac6bb | 284 | spi.write(0xff); |
akashvibhute | 2:3bdf0d9bb71f | 285 | endTransaction(); |
akashvibhute | 0:bb74812ac6bb | 286 | |
akashvibhute | 2:3bdf0d9bb71f | 287 | |
akashvibhute | 2:3bdf0d9bb71f | 288 | |
akashvibhute | 2:3bdf0d9bb71f | 289 | |
akashvibhute | 2:3bdf0d9bb71f | 290 | |
akashvibhute | 2:3bdf0d9bb71f | 291 | |
akashvibhute | 2:3bdf0d9bb71f | 292 | |
akashvibhute | 2:3bdf0d9bb71f | 293 | |
akashvibhute | 2:3bdf0d9bb71f | 294 | |
akashvibhute | 2:3bdf0d9bb71f | 295 | |
akashvibhute | 2:3bdf0d9bb71f | 296 | |
akashvibhute | 2:3bdf0d9bb71f | 297 | |
akashvibhute | 2:3bdf0d9bb71f | 298 | |
akashvibhute | 2:3bdf0d9bb71f | 299 | |
akashvibhute | 2:3bdf0d9bb71f | 300 | |
akashvibhute | 2:3bdf0d9bb71f | 301 | |
akashvibhute | 2:3bdf0d9bb71f | 302 | |
akashvibhute | 2:3bdf0d9bb71f | 303 | |
akashvibhute | 2:3bdf0d9bb71f | 304 | |
akashvibhute | 2:3bdf0d9bb71f | 305 | |
akashvibhute | 2:3bdf0d9bb71f | 306 | |
akashvibhute | 2:3bdf0d9bb71f | 307 | |
akashvibhute | 2:3bdf0d9bb71f | 308 | |
akashvibhute | 2:3bdf0d9bb71f | 309 | |
akashvibhute | 2:3bdf0d9bb71f | 310 | |
akashvibhute | 2:3bdf0d9bb71f | 311 | |
akashvibhute | 2:3bdf0d9bb71f | 312 | |
akashvibhute | 2:3bdf0d9bb71f | 313 | |
akashvibhute | 2:3bdf0d9bb71f | 314 | |
akashvibhute | 0:bb74812ac6bb | 315 | return status; |
akashvibhute | 0:bb74812ac6bb | 316 | } |
akashvibhute | 0:bb74812ac6bb | 317 | |
akashvibhute | 0:bb74812ac6bb | 318 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 319 | |
akashvibhute | 0:bb74812ac6bb | 320 | uint8_t RF24::flush_rx(void) |
akashvibhute | 0:bb74812ac6bb | 321 | { |
akashvibhute | 2:3bdf0d9bb71f | 322 | return spiTrans( FLUSH_RX ); |
akashvibhute | 0:bb74812ac6bb | 323 | } |
akashvibhute | 0:bb74812ac6bb | 324 | |
akashvibhute | 0:bb74812ac6bb | 325 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 326 | |
akashvibhute | 0:bb74812ac6bb | 327 | uint8_t RF24::flush_tx(void) |
akashvibhute | 0:bb74812ac6bb | 328 | { |
akashvibhute | 2:3bdf0d9bb71f | 329 | return spiTrans( FLUSH_TX ); |
akashvibhute | 2:3bdf0d9bb71f | 330 | } |
akashvibhute | 2:3bdf0d9bb71f | 331 | |
akashvibhute | 2:3bdf0d9bb71f | 332 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 333 | |
akashvibhute | 2:3bdf0d9bb71f | 334 | uint8_t RF24::spiTrans(uint8_t cmd){ |
akashvibhute | 2:3bdf0d9bb71f | 335 | |
akashvibhute | 0:bb74812ac6bb | 336 | uint8_t status; |
akashvibhute | 0:bb74812ac6bb | 337 | |
akashvibhute | 2:3bdf0d9bb71f | 338 | beginTransaction(); |
akashvibhute | 2:3bdf0d9bb71f | 339 | status = spi.write( cmd ); |
akashvibhute | 2:3bdf0d9bb71f | 340 | endTransaction(); |
akashvibhute | 0:bb74812ac6bb | 341 | |
akashvibhute | 2:3bdf0d9bb71f | 342 | |
akashvibhute | 2:3bdf0d9bb71f | 343 | |
akashvibhute | 2:3bdf0d9bb71f | 344 | |
akashvibhute | 2:3bdf0d9bb71f | 345 | |
akashvibhute | 2:3bdf0d9bb71f | 346 | |
akashvibhute | 2:3bdf0d9bb71f | 347 | |
akashvibhute | 2:3bdf0d9bb71f | 348 | |
akashvibhute | 0:bb74812ac6bb | 349 | return status; |
akashvibhute | 0:bb74812ac6bb | 350 | } |
akashvibhute | 0:bb74812ac6bb | 351 | |
akashvibhute | 0:bb74812ac6bb | 352 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 353 | |
akashvibhute | 0:bb74812ac6bb | 354 | uint8_t RF24::get_status(void) |
akashvibhute | 0:bb74812ac6bb | 355 | { |
akashvibhute | 2:3bdf0d9bb71f | 356 | return spiTrans(NOP); |
akashvibhute | 0:bb74812ac6bb | 357 | } |
akashvibhute | 0:bb74812ac6bb | 358 | |
akashvibhute | 0:bb74812ac6bb | 359 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 360 | #if !defined (MINIMAL) |
akashvibhute | 0:bb74812ac6bb | 361 | void RF24::print_status(uint8_t status) |
akashvibhute | 0:bb74812ac6bb | 362 | { |
akashvibhute | 2:3bdf0d9bb71f | 363 | printf(("STATUS\t\t = 0x%02x RX_DR=%x TX_DS=%x MAX_RT=%x RX_P_NO=%x TX_FULL=%x\r\n"), |
akashvibhute | 0:bb74812ac6bb | 364 | status, |
akashvibhute | 0:bb74812ac6bb | 365 | (status & _BV(RX_DR))?1:0, |
akashvibhute | 0:bb74812ac6bb | 366 | (status & _BV(TX_DS))?1:0, |
akashvibhute | 0:bb74812ac6bb | 367 | (status & _BV(MAX_RT))?1:0, |
akashvibhute | 0:bb74812ac6bb | 368 | ((status >> RX_P_NO) & 7), |
akashvibhute | 0:bb74812ac6bb | 369 | (status & _BV(TX_FULL))?1:0 |
akashvibhute | 0:bb74812ac6bb | 370 | ); |
akashvibhute | 0:bb74812ac6bb | 371 | } |
akashvibhute | 0:bb74812ac6bb | 372 | |
akashvibhute | 0:bb74812ac6bb | 373 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 374 | |
akashvibhute | 0:bb74812ac6bb | 375 | void RF24::print_observe_tx(uint8_t value) |
akashvibhute | 0:bb74812ac6bb | 376 | { |
akashvibhute | 0:bb74812ac6bb | 377 | printf(("OBSERVE_TX=%02x: POLS_CNT=%x ARC_CNT=%x\r\n"), |
akashvibhute | 0:bb74812ac6bb | 378 | value, |
akashvibhute | 2:3bdf0d9bb71f | 379 | ((value >> PLOS_CNT) & 15), |
akashvibhute | 2:3bdf0d9bb71f | 380 | ((value >> ARC_CNT) & 15) |
akashvibhute | 0:bb74812ac6bb | 381 | ); |
akashvibhute | 0:bb74812ac6bb | 382 | } |
akashvibhute | 0:bb74812ac6bb | 383 | |
akashvibhute | 0:bb74812ac6bb | 384 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 385 | |
akashvibhute | 0:bb74812ac6bb | 386 | void RF24::print_byte_register(const char* name, uint8_t reg, uint8_t qty) |
akashvibhute | 0:bb74812ac6bb | 387 | { |
akashvibhute | 2:3bdf0d9bb71f | 388 | printf("%s =",name); |
akashvibhute | 0:bb74812ac6bb | 389 | while (qty--) |
akashvibhute | 2:3bdf0d9bb71f | 390 | printf_P(PSTR(" 0x%02x"),read_register(reg++)); |
akashvibhute | 2:3bdf0d9bb71f | 391 | printf_P(PSTR("\r\n")); |
akashvibhute | 2:3bdf0d9bb71f | 392 | |
akashvibhute | 2:3bdf0d9bb71f | 393 | |
akashvibhute | 2:3bdf0d9bb71f | 394 | |
akashvibhute | 2:3bdf0d9bb71f | 395 | |
akashvibhute | 2:3bdf0d9bb71f | 396 | |
akashvibhute | 2:3bdf0d9bb71f | 397 | |
akashvibhute | 0:bb74812ac6bb | 398 | } |
akashvibhute | 0:bb74812ac6bb | 399 | |
akashvibhute | 0:bb74812ac6bb | 400 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 401 | |
akashvibhute | 0:bb74812ac6bb | 402 | void RF24::print_address_register(const char* name, uint8_t reg, uint8_t qty) |
akashvibhute | 0:bb74812ac6bb | 403 | { |
akashvibhute | 2:3bdf0d9bb71f | 404 | printf_P(PSTR(PRIPSTR"\t ="),name); |
akashvibhute | 2:3bdf0d9bb71f | 405 | |
akashvibhute | 0:bb74812ac6bb | 406 | while (qty--) |
akashvibhute | 0:bb74812ac6bb | 407 | { |
akashvibhute | 2:3bdf0d9bb71f | 408 | uint8_t buffer[addr_width]; |
akashvibhute | 0:bb74812ac6bb | 409 | read_register(reg++,buffer,sizeof buffer); |
akashvibhute | 0:bb74812ac6bb | 410 | |
akashvibhute | 2:3bdf0d9bb71f | 411 | printf_P(PSTR(" 0x")); |
akashvibhute | 0:bb74812ac6bb | 412 | uint8_t* bufptr = buffer + sizeof buffer; |
akashvibhute | 0:bb74812ac6bb | 413 | while( --bufptr >= buffer ) |
akashvibhute | 2:3bdf0d9bb71f | 414 | printf_P(PSTR("%02x"),*bufptr); |
akashvibhute | 0:bb74812ac6bb | 415 | } |
akashvibhute | 0:bb74812ac6bb | 416 | |
akashvibhute | 2:3bdf0d9bb71f | 417 | printf_P(PSTR("\r\n")); |
akashvibhute | 2:3bdf0d9bb71f | 418 | |
akashvibhute | 2:3bdf0d9bb71f | 419 | |
akashvibhute | 2:3bdf0d9bb71f | 420 | |
akashvibhute | 2:3bdf0d9bb71f | 421 | |
akashvibhute | 2:3bdf0d9bb71f | 422 | } |
akashvibhute | 2:3bdf0d9bb71f | 423 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 424 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 425 | |
akashvibhute | 2:3bdf0d9bb71f | 426 | RF24::RF24(PinName mosi, PinName miso, PinName sck, PinName _cepin, PinName _csnpin): |
akashvibhute | 2:3bdf0d9bb71f | 427 | ce_pin(_cepin), csn_pin(_csnpin), p_variant(false), |
akashvibhute | 2:3bdf0d9bb71f | 428 | payload_size(32), dynamic_payloads_enabled(false), addr_width(5), spi(mosi, miso, sck) |
akashvibhute | 2:3bdf0d9bb71f | 429 | { |
akashvibhute | 2:3bdf0d9bb71f | 430 | pipe0_reading_address[0]=0; |
akashvibhute | 2:3bdf0d9bb71f | 431 | spi.frequency(10000000/5); // 2Mbit, 1/5th the maximum transfer rate for the spi bus |
akashvibhute | 2:3bdf0d9bb71f | 432 | spi.format(8,0); // 8-bit, ClockPhase = 0, ClockPolarity = 0 |
akashvibhute | 2:3bdf0d9bb71f | 433 | |
akashvibhute | 2:3bdf0d9bb71f | 434 | DigitalOut ce_pin(_cepin); /**< "Chip Enable" pin, activates the RX or TX role */ |
akashvibhute | 2:3bdf0d9bb71f | 435 | DigitalOut csn_pin(_csnpin); /**< SPI Chip select */ |
akashvibhute | 2:3bdf0d9bb71f | 436 | |
akashvibhute | 2:3bdf0d9bb71f | 437 | wait_ms(100); |
akashvibhute | 2:3bdf0d9bb71f | 438 | |
akashvibhute | 0:bb74812ac6bb | 439 | } |
akashvibhute | 0:bb74812ac6bb | 440 | |
akashvibhute | 2:3bdf0d9bb71f | 441 | |
akashvibhute | 2:3bdf0d9bb71f | 442 | |
akashvibhute | 0:bb74812ac6bb | 443 | |
akashvibhute | 2:3bdf0d9bb71f | 444 | |
akashvibhute | 2:3bdf0d9bb71f | 445 | |
akashvibhute | 2:3bdf0d9bb71f | 446 | |
akashvibhute | 0:bb74812ac6bb | 447 | |
akashvibhute | 0:bb74812ac6bb | 448 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 449 | |
akashvibhute | 0:bb74812ac6bb | 450 | void RF24::setChannel(uint8_t channel) |
akashvibhute | 0:bb74812ac6bb | 451 | { |
akashvibhute | 0:bb74812ac6bb | 452 | const uint8_t max_channel = 127; |
akashvibhute | 2:3bdf0d9bb71f | 453 | write_register(RF_CH,rf24_min(channel,max_channel)); |
akashvibhute | 0:bb74812ac6bb | 454 | } |
akashvibhute | 0:bb74812ac6bb | 455 | |
akashvibhute | 2:3bdf0d9bb71f | 456 | uint8_t RF24::getChannel() |
akashvibhute | 2:3bdf0d9bb71f | 457 | { |
akashvibhute | 2:3bdf0d9bb71f | 458 | return read_register(RF_CH); |
akashvibhute | 2:3bdf0d9bb71f | 459 | } |
akashvibhute | 0:bb74812ac6bb | 460 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 461 | |
akashvibhute | 0:bb74812ac6bb | 462 | void RF24::setPayloadSize(uint8_t size) |
akashvibhute | 0:bb74812ac6bb | 463 | { |
akashvibhute | 2:3bdf0d9bb71f | 464 | payload_size = rf24_min(size,32); |
akashvibhute | 0:bb74812ac6bb | 465 | } |
akashvibhute | 0:bb74812ac6bb | 466 | |
akashvibhute | 0:bb74812ac6bb | 467 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 468 | |
akashvibhute | 0:bb74812ac6bb | 469 | uint8_t RF24::getPayloadSize(void) |
akashvibhute | 0:bb74812ac6bb | 470 | { |
akashvibhute | 0:bb74812ac6bb | 471 | return payload_size; |
akashvibhute | 0:bb74812ac6bb | 472 | } |
akashvibhute | 0:bb74812ac6bb | 473 | |
akashvibhute | 0:bb74812ac6bb | 474 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 475 | |
akashvibhute | 2:3bdf0d9bb71f | 476 | #if !defined (MINIMAL) |
akashvibhute | 2:3bdf0d9bb71f | 477 | |
akashvibhute | 2:3bdf0d9bb71f | 478 | static const char rf24_datarate_e_str_0[] PROGMEM = "1MBPS"; |
akashvibhute | 2:3bdf0d9bb71f | 479 | static const char rf24_datarate_e_str_1[] PROGMEM = "2MBPS"; |
akashvibhute | 2:3bdf0d9bb71f | 480 | static const char rf24_datarate_e_str_2[] PROGMEM = "250KBPS"; |
akashvibhute | 2:3bdf0d9bb71f | 481 | static const char * const rf24_datarate_e_str_P[] PROGMEM = { |
akashvibhute | 0:bb74812ac6bb | 482 | rf24_datarate_e_str_0, |
akashvibhute | 0:bb74812ac6bb | 483 | rf24_datarate_e_str_1, |
akashvibhute | 0:bb74812ac6bb | 484 | rf24_datarate_e_str_2, |
akashvibhute | 0:bb74812ac6bb | 485 | }; |
akashvibhute | 2:3bdf0d9bb71f | 486 | static const char rf24_model_e_str_0[] PROGMEM = "nRF24L01"; |
akashvibhute | 2:3bdf0d9bb71f | 487 | static const char rf24_model_e_str_1[] PROGMEM = "nRF24L01+"; |
akashvibhute | 2:3bdf0d9bb71f | 488 | static const char * const rf24_model_e_str_P[] PROGMEM = { |
akashvibhute | 0:bb74812ac6bb | 489 | rf24_model_e_str_0, |
akashvibhute | 0:bb74812ac6bb | 490 | rf24_model_e_str_1, |
akashvibhute | 0:bb74812ac6bb | 491 | }; |
akashvibhute | 2:3bdf0d9bb71f | 492 | static const char rf24_crclength_e_str_0[] PROGMEM = "Disabled"; |
akashvibhute | 2:3bdf0d9bb71f | 493 | static const char rf24_crclength_e_str_1[] PROGMEM = "8 bits"; |
akashvibhute | 2:3bdf0d9bb71f | 494 | static const char rf24_crclength_e_str_2[] PROGMEM = "16 bits" ; |
akashvibhute | 2:3bdf0d9bb71f | 495 | static const char * const rf24_crclength_e_str_P[] PROGMEM = { |
akashvibhute | 0:bb74812ac6bb | 496 | rf24_crclength_e_str_0, |
akashvibhute | 0:bb74812ac6bb | 497 | rf24_crclength_e_str_1, |
akashvibhute | 0:bb74812ac6bb | 498 | rf24_crclength_e_str_2, |
akashvibhute | 0:bb74812ac6bb | 499 | }; |
akashvibhute | 2:3bdf0d9bb71f | 500 | static const char rf24_pa_dbm_e_str_0[] PROGMEM = "PA_MIN"; |
akashvibhute | 2:3bdf0d9bb71f | 501 | static const char rf24_pa_dbm_e_str_1[] PROGMEM = "PA_LOW"; |
akashvibhute | 2:3bdf0d9bb71f | 502 | static const char rf24_pa_dbm_e_str_2[] PROGMEM = "PA_HIGH"; |
akashvibhute | 2:3bdf0d9bb71f | 503 | static const char rf24_pa_dbm_e_str_3[] PROGMEM = "PA_MAX"; |
akashvibhute | 2:3bdf0d9bb71f | 504 | static const char * const rf24_pa_dbm_e_str_P[] PROGMEM = { |
akashvibhute | 0:bb74812ac6bb | 505 | rf24_pa_dbm_e_str_0, |
akashvibhute | 0:bb74812ac6bb | 506 | rf24_pa_dbm_e_str_1, |
akashvibhute | 0:bb74812ac6bb | 507 | rf24_pa_dbm_e_str_2, |
akashvibhute | 0:bb74812ac6bb | 508 | rf24_pa_dbm_e_str_3, |
akashvibhute | 0:bb74812ac6bb | 509 | }; |
akashvibhute | 0:bb74812ac6bb | 510 | |
akashvibhute | 2:3bdf0d9bb71f | 511 | |
akashvibhute | 2:3bdf0d9bb71f | 512 | |
akashvibhute | 2:3bdf0d9bb71f | 513 | |
akashvibhute | 2:3bdf0d9bb71f | 514 | |
akashvibhute | 2:3bdf0d9bb71f | 515 | |
akashvibhute | 2:3bdf0d9bb71f | 516 | |
akashvibhute | 2:3bdf0d9bb71f | 517 | |
akashvibhute | 2:3bdf0d9bb71f | 518 | |
akashvibhute | 2:3bdf0d9bb71f | 519 | |
akashvibhute | 2:3bdf0d9bb71f | 520 | |
akashvibhute | 2:3bdf0d9bb71f | 521 | |
akashvibhute | 2:3bdf0d9bb71f | 522 | |
akashvibhute | 2:3bdf0d9bb71f | 523 | |
akashvibhute | 0:bb74812ac6bb | 524 | void RF24::printDetails(void) |
akashvibhute | 0:bb74812ac6bb | 525 | { |
akashvibhute | 2:3bdf0d9bb71f | 526 | |
akashvibhute | 2:3bdf0d9bb71f | 527 | |
akashvibhute | 2:3bdf0d9bb71f | 528 | |
akashvibhute | 2:3bdf0d9bb71f | 529 | |
akashvibhute | 2:3bdf0d9bb71f | 530 | |
akashvibhute | 2:3bdf0d9bb71f | 531 | |
akashvibhute | 2:3bdf0d9bb71f | 532 | |
akashvibhute | 2:3bdf0d9bb71f | 533 | |
akashvibhute | 2:3bdf0d9bb71f | 534 | |
akashvibhute | 2:3bdf0d9bb71f | 535 | |
akashvibhute | 2:3bdf0d9bb71f | 536 | |
akashvibhute | 2:3bdf0d9bb71f | 537 | |
akashvibhute | 2:3bdf0d9bb71f | 538 | |
akashvibhute | 2:3bdf0d9bb71f | 539 | |
akashvibhute | 2:3bdf0d9bb71f | 540 | |
akashvibhute | 2:3bdf0d9bb71f | 541 | |
akashvibhute | 2:3bdf0d9bb71f | 542 | |
akashvibhute | 2:3bdf0d9bb71f | 543 | |
akashvibhute | 2:3bdf0d9bb71f | 544 | |
akashvibhute | 2:3bdf0d9bb71f | 545 | |
akashvibhute | 2:3bdf0d9bb71f | 546 | |
akashvibhute | 2:3bdf0d9bb71f | 547 | |
akashvibhute | 2:3bdf0d9bb71f | 548 | |
akashvibhute | 2:3bdf0d9bb71f | 549 | |
akashvibhute | 2:3bdf0d9bb71f | 550 | |
akashvibhute | 2:3bdf0d9bb71f | 551 | |
akashvibhute | 2:3bdf0d9bb71f | 552 | |
akashvibhute | 2:3bdf0d9bb71f | 553 | |
akashvibhute | 2:3bdf0d9bb71f | 554 | |
akashvibhute | 2:3bdf0d9bb71f | 555 | |
akashvibhute | 2:3bdf0d9bb71f | 556 | |
akashvibhute | 2:3bdf0d9bb71f | 557 | |
akashvibhute | 2:3bdf0d9bb71f | 558 | |
akashvibhute | 0:bb74812ac6bb | 559 | print_status(get_status()); |
akashvibhute | 0:bb74812ac6bb | 560 | |
akashvibhute | 2:3bdf0d9bb71f | 561 | print_address_register(PSTR("RX_ADDR_P0-1"),RX_ADDR_P0,2); |
akashvibhute | 2:3bdf0d9bb71f | 562 | print_byte_register(PSTR("RX_ADDR_P2-5"),RX_ADDR_P2,4); |
akashvibhute | 2:3bdf0d9bb71f | 563 | print_address_register(PSTR("TX_ADDR\t"),TX_ADDR); |
akashvibhute | 0:bb74812ac6bb | 564 | |
akashvibhute | 2:3bdf0d9bb71f | 565 | print_byte_register(PSTR("RX_PW_P0-6"),RX_PW_P0,6); |
akashvibhute | 2:3bdf0d9bb71f | 566 | print_byte_register(PSTR("EN_AA\t"),EN_AA); |
akashvibhute | 2:3bdf0d9bb71f | 567 | print_byte_register(PSTR("EN_RXADDR"),EN_RXADDR); |
akashvibhute | 2:3bdf0d9bb71f | 568 | print_byte_register(PSTR("RF_CH\t"),RF_CH); |
akashvibhute | 2:3bdf0d9bb71f | 569 | print_byte_register(PSTR("RF_SETUP"),RF_SETUP); |
akashvibhute | 2:3bdf0d9bb71f | 570 | print_byte_register(PSTR("CONFIG\t"),CONFIG); |
akashvibhute | 2:3bdf0d9bb71f | 571 | print_byte_register(PSTR("DYNPD/FEATURE"),DYNPD,2); |
akashvibhute | 0:bb74812ac6bb | 572 | |
akashvibhute | 2:3bdf0d9bb71f | 573 | printf_P(PSTR("Data Rate\t = "PRIPSTR"\r\n"),pgm_read_word(&rf24_datarate_e_str_P[getDataRate()])); |
akashvibhute | 2:3bdf0d9bb71f | 574 | printf_P(PSTR("Model\t\t = "PRIPSTR"\r\n"),pgm_read_word(&rf24_model_e_str_P[isPVariant()])); |
akashvibhute | 2:3bdf0d9bb71f | 575 | printf_P(PSTR("CRC Length\t = "PRIPSTR"\r\n"),pgm_read_word(&rf24_crclength_e_str_P[getCRCLength()])); |
akashvibhute | 2:3bdf0d9bb71f | 576 | printf_P(PSTR("PA Power\t = "PRIPSTR"\r\n"), pgm_read_word(&rf24_pa_dbm_e_str_P[getPALevel()])); |
akashvibhute | 2:3bdf0d9bb71f | 577 | |
akashvibhute | 0:bb74812ac6bb | 578 | } |
akashvibhute | 0:bb74812ac6bb | 579 | |
akashvibhute | 2:3bdf0d9bb71f | 580 | #endif |
akashvibhute | 0:bb74812ac6bb | 581 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 582 | |
akashvibhute | 2:3bdf0d9bb71f | 583 | bool RF24::begin(void) |
akashvibhute | 0:bb74812ac6bb | 584 | { |
akashvibhute | 2:3bdf0d9bb71f | 585 | |
akashvibhute | 2:3bdf0d9bb71f | 586 | uint8_t setup=0; |
akashvibhute | 2:3bdf0d9bb71f | 587 | |
akashvibhute | 2:3bdf0d9bb71f | 588 | mainTimer.start(); |
akashvibhute | 2:3bdf0d9bb71f | 589 | |
akashvibhute | 2:3bdf0d9bb71f | 590 | ce_pin=LOW; |
akashvibhute | 2:3bdf0d9bb71f | 591 | csn_pin=HIGH; |
akashvibhute | 0:bb74812ac6bb | 592 | |
akashvibhute | 2:3bdf0d9bb71f | 593 | |
akashvibhute | 2:3bdf0d9bb71f | 594 | |
akashvibhute | 2:3bdf0d9bb71f | 595 | |
akashvibhute | 2:3bdf0d9bb71f | 596 | |
akashvibhute | 2:3bdf0d9bb71f | 597 | |
akashvibhute | 2:3bdf0d9bb71f | 598 | |
akashvibhute | 2:3bdf0d9bb71f | 599 | |
akashvibhute | 2:3bdf0d9bb71f | 600 | |
akashvibhute | 2:3bdf0d9bb71f | 601 | |
akashvibhute | 2:3bdf0d9bb71f | 602 | |
akashvibhute | 2:3bdf0d9bb71f | 603 | |
akashvibhute | 2:3bdf0d9bb71f | 604 | |
akashvibhute | 2:3bdf0d9bb71f | 605 | |
akashvibhute | 2:3bdf0d9bb71f | 606 | |
akashvibhute | 2:3bdf0d9bb71f | 607 | |
akashvibhute | 2:3bdf0d9bb71f | 608 | |
akashvibhute | 2:3bdf0d9bb71f | 609 | |
akashvibhute | 2:3bdf0d9bb71f | 610 | |
akashvibhute | 2:3bdf0d9bb71f | 611 | |
akashvibhute | 2:3bdf0d9bb71f | 612 | |
akashvibhute | 2:3bdf0d9bb71f | 613 | |
akashvibhute | 2:3bdf0d9bb71f | 614 | |
akashvibhute | 2:3bdf0d9bb71f | 615 | |
akashvibhute | 2:3bdf0d9bb71f | 616 | |
akashvibhute | 2:3bdf0d9bb71f | 617 | |
akashvibhute | 2:3bdf0d9bb71f | 618 | |
akashvibhute | 2:3bdf0d9bb71f | 619 | |
akashvibhute | 2:3bdf0d9bb71f | 620 | |
akashvibhute | 2:3bdf0d9bb71f | 621 | |
akashvibhute | 2:3bdf0d9bb71f | 622 | |
akashvibhute | 2:3bdf0d9bb71f | 623 | |
akashvibhute | 2:3bdf0d9bb71f | 624 | |
akashvibhute | 2:3bdf0d9bb71f | 625 | |
akashvibhute | 2:3bdf0d9bb71f | 626 | |
akashvibhute | 2:3bdf0d9bb71f | 627 | |
akashvibhute | 2:3bdf0d9bb71f | 628 | |
akashvibhute | 2:3bdf0d9bb71f | 629 | |
akashvibhute | 0:bb74812ac6bb | 630 | // Must allow the radio time to settle else configuration bits will not necessarily stick. |
akashvibhute | 0:bb74812ac6bb | 631 | // This is actually only required following power up but some settling time also appears to |
akashvibhute | 0:bb74812ac6bb | 632 | // be required after resets too. For full coverage, we'll always assume the worst. |
akashvibhute | 0:bb74812ac6bb | 633 | // Enabling 16b CRC is by far the most obvious case if the wrong timing is used - or skipped. |
akashvibhute | 0:bb74812ac6bb | 634 | // Technically we require 4.5ms + 14us as a worst case. We'll just call it 5ms for good measure. |
akashvibhute | 2:3bdf0d9bb71f | 635 | // WARNING: Delay is based on P-variant whereby non-P *may* require different timing. |
akashvibhute | 0:bb74812ac6bb | 636 | wait_ms( 5 ) ; |
akashvibhute | 0:bb74812ac6bb | 637 | |
akashvibhute | 2:3bdf0d9bb71f | 638 | // Reset CONFIG and enable 16-bit CRC. |
akashvibhute | 2:3bdf0d9bb71f | 639 | write_register( CONFIG, 12 ) ; |
akashvibhute | 2:3bdf0d9bb71f | 640 | |
akashvibhute | 0:bb74812ac6bb | 641 | // Set 1500uS (minimum for 32B payload in ESB@250KBPS) timeouts, to make testing a little easier |
akashvibhute | 0:bb74812ac6bb | 642 | // WARNING: If this is ever lowered, either 250KBS mode with AA is broken or maximum packet |
akashvibhute | 0:bb74812ac6bb | 643 | // sizes must never be used. See documentation for a more complete explanation. |
akashvibhute | 2:3bdf0d9bb71f | 644 | setRetries(5,15); |
akashvibhute | 0:bb74812ac6bb | 645 | |
akashvibhute | 2:3bdf0d9bb71f | 646 | // Reset value is MAX |
akashvibhute | 0:bb74812ac6bb | 647 | setPALevel( RF24_PA_MAX ) ; |
akashvibhute | 0:bb74812ac6bb | 648 | |
akashvibhute | 2:3bdf0d9bb71f | 649 | // check for connected module and if this is a p nRF24l01 variant |
akashvibhute | 2:3bdf0d9bb71f | 650 | // |
akashvibhute | 0:bb74812ac6bb | 651 | if( setDataRate( RF24_250KBPS ) ) |
akashvibhute | 0:bb74812ac6bb | 652 | { |
akashvibhute | 0:bb74812ac6bb | 653 | p_variant = true ; |
akashvibhute | 0:bb74812ac6bb | 654 | } |
akashvibhute | 2:3bdf0d9bb71f | 655 | /*setup = read_register(RF_SETUP); |
akashvibhute | 2:3bdf0d9bb71f | 656 | if( setup == 0b00001110 ) // register default for nRF24L01P |
akashvibhute | 2:3bdf0d9bb71f | 657 | { |
akashvibhute | 2:3bdf0d9bb71f | 658 | p_variant = true ; |
akashvibhute | 2:3bdf0d9bb71f | 659 | }*/ |
akashvibhute | 0:bb74812ac6bb | 660 | |
akashvibhute | 0:bb74812ac6bb | 661 | // Then set the data rate to the slowest (and most reliable) speed supported by all |
akashvibhute | 0:bb74812ac6bb | 662 | // hardware. |
akashvibhute | 0:bb74812ac6bb | 663 | setDataRate( RF24_1MBPS ) ; |
akashvibhute | 0:bb74812ac6bb | 664 | |
akashvibhute | 0:bb74812ac6bb | 665 | // Initialize CRC and request 2-byte (16bit) CRC |
akashvibhute | 0:bb74812ac6bb | 666 | setCRCLength( RF24_CRC_16 ) ; |
akashvibhute | 2:3bdf0d9bb71f | 667 | |
akashvibhute | 2:3bdf0d9bb71f | 668 | // Disable dynamic payloads, to match dynamic_payloads_enabled setting - Reset value is 0 |
akashvibhute | 2:3bdf0d9bb71f | 669 | toggle_features(); |
akashvibhute | 2:3bdf0d9bb71f | 670 | write_register(FEATURE,0 ); |
akashvibhute | 0:bb74812ac6bb | 671 | write_register(DYNPD,0); |
akashvibhute | 0:bb74812ac6bb | 672 | |
akashvibhute | 0:bb74812ac6bb | 673 | // Reset current status |
akashvibhute | 0:bb74812ac6bb | 674 | // Notice reset and flush is the last thing we do |
akashvibhute | 2:3bdf0d9bb71f | 675 | write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 0:bb74812ac6bb | 676 | |
akashvibhute | 0:bb74812ac6bb | 677 | // Set up default configuration. Callers can always change it later. |
akashvibhute | 0:bb74812ac6bb | 678 | // This channel should be universally safe and not bleed over into adjacent |
akashvibhute | 0:bb74812ac6bb | 679 | // spectrum. |
akashvibhute | 1:00706a42491e | 680 | setChannel(76); |
akashvibhute | 0:bb74812ac6bb | 681 | |
akashvibhute | 0:bb74812ac6bb | 682 | // Flush buffers |
akashvibhute | 0:bb74812ac6bb | 683 | flush_rx(); |
akashvibhute | 0:bb74812ac6bb | 684 | flush_tx(); |
akashvibhute | 2:3bdf0d9bb71f | 685 | |
akashvibhute | 2:3bdf0d9bb71f | 686 | powerUp(); //Power up by default when begin() is called |
akashvibhute | 2:3bdf0d9bb71f | 687 | |
akashvibhute | 2:3bdf0d9bb71f | 688 | // Enable PTX, do not write CE high so radio will remain in standby I mode ( 130us max to transition to RX or TX instead of 1500us from powerUp ) |
akashvibhute | 2:3bdf0d9bb71f | 689 | // PTX should use only 22uA of power |
akashvibhute | 2:3bdf0d9bb71f | 690 | write_register(CONFIG, ( read_register(CONFIG) ) & ~_BV(PRIM_RX) ); |
akashvibhute | 2:3bdf0d9bb71f | 691 | |
akashvibhute | 2:3bdf0d9bb71f | 692 | // if setup is 0 or ff then there was no response from module |
akashvibhute | 2:3bdf0d9bb71f | 693 | return ( setup != 0 && setup != 0xff ); |
akashvibhute | 0:bb74812ac6bb | 694 | } |
akashvibhute | 0:bb74812ac6bb | 695 | |
akashvibhute | 0:bb74812ac6bb | 696 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 697 | |
akashvibhute | 0:bb74812ac6bb | 698 | void RF24::startListening(void) |
akashvibhute | 0:bb74812ac6bb | 699 | { |
akashvibhute | 2:3bdf0d9bb71f | 700 | |
akashvibhute | 2:3bdf0d9bb71f | 701 | |
akashvibhute | 0:bb74812ac6bb | 702 | |
akashvibhute | 2:3bdf0d9bb71f | 703 | write_register(CONFIG, read_register(CONFIG) | _BV(PRIM_RX)); |
akashvibhute | 2:3bdf0d9bb71f | 704 | write_register(NRF_STATUS, _BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 2:3bdf0d9bb71f | 705 | ce(true); |
akashvibhute | 0:bb74812ac6bb | 706 | // Restore the pipe0 adddress, if exists |
akashvibhute | 2:3bdf0d9bb71f | 707 | if (pipe0_reading_address[0] > 0){ |
akashvibhute | 2:3bdf0d9bb71f | 708 | write_register(RX_ADDR_P0, pipe0_reading_address, addr_width); |
akashvibhute | 2:3bdf0d9bb71f | 709 | }else{ |
akashvibhute | 2:3bdf0d9bb71f | 710 | closeReadingPipe(0); |
akashvibhute | 2:3bdf0d9bb71f | 711 | } |
akashvibhute | 0:bb74812ac6bb | 712 | |
akashvibhute | 0:bb74812ac6bb | 713 | // Flush buffers |
akashvibhute | 2:3bdf0d9bb71f | 714 | //flush_rx(); |
akashvibhute | 2:3bdf0d9bb71f | 715 | if(read_register(FEATURE) & _BV(EN_ACK_PAY)){ |
akashvibhute | 2:3bdf0d9bb71f | 716 | flush_tx(); |
akashvibhute | 2:3bdf0d9bb71f | 717 | } |
akashvibhute | 0:bb74812ac6bb | 718 | |
akashvibhute | 0:bb74812ac6bb | 719 | // Go! |
akashvibhute | 2:3bdf0d9bb71f | 720 | //delayMicroseconds(100); |
akashvibhute | 0:bb74812ac6bb | 721 | } |
akashvibhute | 0:bb74812ac6bb | 722 | |
akashvibhute | 0:bb74812ac6bb | 723 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 724 | static const uint8_t child_pipe_enable[] PROGMEM = |
akashvibhute | 2:3bdf0d9bb71f | 725 | { |
akashvibhute | 2:3bdf0d9bb71f | 726 | ERX_P0, ERX_P1, ERX_P2, ERX_P3, ERX_P4, ERX_P5 |
akashvibhute | 2:3bdf0d9bb71f | 727 | }; |
akashvibhute | 0:bb74812ac6bb | 728 | |
akashvibhute | 0:bb74812ac6bb | 729 | void RF24::stopListening(void) |
akashvibhute | 2:3bdf0d9bb71f | 730 | { |
akashvibhute | 2:3bdf0d9bb71f | 731 | ce_pin=LOW; |
akashvibhute | 2:3bdf0d9bb71f | 732 | |
akashvibhute | 2:3bdf0d9bb71f | 733 | wait_us(txRxDelay); |
akashvibhute | 2:3bdf0d9bb71f | 734 | |
akashvibhute | 2:3bdf0d9bb71f | 735 | if(read_register(FEATURE) & _BV(EN_ACK_PAY)){ |
akashvibhute | 2:3bdf0d9bb71f | 736 | wait_us(txRxDelay); //200 |
akashvibhute | 2:3bdf0d9bb71f | 737 | flush_tx(); |
akashvibhute | 2:3bdf0d9bb71f | 738 | } |
akashvibhute | 2:3bdf0d9bb71f | 739 | //flush_rx(); |
akashvibhute | 2:3bdf0d9bb71f | 740 | write_register(CONFIG, ( read_register(CONFIG) ) & ~_BV(PRIM_RX) ); |
akashvibhute | 2:3bdf0d9bb71f | 741 | |
akashvibhute | 2:3bdf0d9bb71f | 742 | |
akashvibhute | 2:3bdf0d9bb71f | 743 | |
akashvibhute | 2:3bdf0d9bb71f | 744 | |
akashvibhute | 2:3bdf0d9bb71f | 745 | |
akashvibhute | 2:3bdf0d9bb71f | 746 | |
akashvibhute | 2:3bdf0d9bb71f | 747 | |
akashvibhute | 2:3bdf0d9bb71f | 748 | |
akashvibhute | 2:3bdf0d9bb71f | 749 | write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[0]))); // Enable RX on pipe0 |
akashvibhute | 2:3bdf0d9bb71f | 750 | |
akashvibhute | 2:3bdf0d9bb71f | 751 | //delayMicroseconds(100); |
akashvibhute | 2:3bdf0d9bb71f | 752 | |
akashvibhute | 0:bb74812ac6bb | 753 | } |
akashvibhute | 0:bb74812ac6bb | 754 | |
akashvibhute | 0:bb74812ac6bb | 755 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 756 | |
akashvibhute | 0:bb74812ac6bb | 757 | void RF24::powerDown(void) |
akashvibhute | 0:bb74812ac6bb | 758 | { |
akashvibhute | 2:3bdf0d9bb71f | 759 | ce(false); // Guarantee CE is low on powerDown |
akashvibhute | 0:bb74812ac6bb | 760 | write_register(CONFIG,read_register(CONFIG) & ~_BV(PWR_UP)); |
akashvibhute | 0:bb74812ac6bb | 761 | } |
akashvibhute | 0:bb74812ac6bb | 762 | |
akashvibhute | 0:bb74812ac6bb | 763 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 764 | |
akashvibhute | 2:3bdf0d9bb71f | 765 | //Power up now. Radio will not power down unless instructed by MCU for config changes etc. |
akashvibhute | 0:bb74812ac6bb | 766 | void RF24::powerUp(void) |
akashvibhute | 0:bb74812ac6bb | 767 | { |
akashvibhute | 2:3bdf0d9bb71f | 768 | uint8_t cfg = read_register(CONFIG); |
akashvibhute | 2:3bdf0d9bb71f | 769 | |
akashvibhute | 2:3bdf0d9bb71f | 770 | // if not powered up then power up and wait for the radio to initialize |
akashvibhute | 2:3bdf0d9bb71f | 771 | if (!(cfg & _BV(PWR_UP))){ |
akashvibhute | 2:3bdf0d9bb71f | 772 | write_register(CONFIG,read_register(CONFIG) | _BV(PWR_UP)); |
akashvibhute | 2:3bdf0d9bb71f | 773 | |
akashvibhute | 2:3bdf0d9bb71f | 774 | // For nRF24L01+ to go from power down mode to TX or RX mode it must first pass through stand-by mode. |
akashvibhute | 2:3bdf0d9bb71f | 775 | // There must be a delay of Tpd2stby (see Table 16.) after the nRF24L01+ leaves power down mode before |
akashvibhute | 2:3bdf0d9bb71f | 776 | // the CEis set high. - Tpd2stby can be up to 5ms per the 1.0 datasheet |
akashvibhute | 2:3bdf0d9bb71f | 777 | wait_ms(5); |
akashvibhute | 2:3bdf0d9bb71f | 778 | } |
akashvibhute | 0:bb74812ac6bb | 779 | } |
akashvibhute | 0:bb74812ac6bb | 780 | |
akashvibhute | 0:bb74812ac6bb | 781 | /******************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 782 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 783 | void RF24::errNotify(){ |
akashvibhute | 2:3bdf0d9bb71f | 784 | #if defined (SERIAL_DEBUG) |
akashvibhute | 2:3bdf0d9bb71f | 785 | printf_P(PSTR("RF24 HARDWARE FAIL: Radio not responding, verify pin connections, wiring, etc.\r\n")); |
akashvibhute | 2:3bdf0d9bb71f | 786 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 787 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 788 | failureDetected = 1; |
akashvibhute | 2:3bdf0d9bb71f | 789 | #else |
akashvibhute | 2:3bdf0d9bb71f | 790 | wait_ms(5000); |
akashvibhute | 2:3bdf0d9bb71f | 791 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 792 | } |
akashvibhute | 2:3bdf0d9bb71f | 793 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 794 | /******************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 795 | |
akashvibhute | 2:3bdf0d9bb71f | 796 | //Similar to the previous write, clears the interrupt flags |
akashvibhute | 2:3bdf0d9bb71f | 797 | bool RF24::write( const void* buf, uint8_t len, const bool multicast ) |
akashvibhute | 2:3bdf0d9bb71f | 798 | { |
akashvibhute | 2:3bdf0d9bb71f | 799 | //Start Writing |
akashvibhute | 2:3bdf0d9bb71f | 800 | startFastWrite(buf,len,multicast); |
akashvibhute | 0:bb74812ac6bb | 801 | |
akashvibhute | 2:3bdf0d9bb71f | 802 | //Wait until complete or failed |
akashvibhute | 2:3bdf0d9bb71f | 803 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 804 | uint32_t timer = mainTimer.read_ms(); |
akashvibhute | 2:3bdf0d9bb71f | 805 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 806 | |
akashvibhute | 2:3bdf0d9bb71f | 807 | while( ! ( get_status() & ( _BV(TX_DS) | _BV(MAX_RT) ))) { |
akashvibhute | 2:3bdf0d9bb71f | 808 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 809 | if(mainTimer.read_ms() - timer > 85){ |
akashvibhute | 2:3bdf0d9bb71f | 810 | errNotify(); |
akashvibhute | 2:3bdf0d9bb71f | 811 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 812 | return 0; |
akashvibhute | 2:3bdf0d9bb71f | 813 | #else |
akashvibhute | 2:3bdf0d9bb71f | 814 | wait_ms(100); |
akashvibhute | 2:3bdf0d9bb71f | 815 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 816 | } |
akashvibhute | 2:3bdf0d9bb71f | 817 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 818 | } |
akashvibhute | 2:3bdf0d9bb71f | 819 | |
akashvibhute | 2:3bdf0d9bb71f | 820 | ce_pin=LOW; |
akashvibhute | 0:bb74812ac6bb | 821 | |
akashvibhute | 2:3bdf0d9bb71f | 822 | uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 0:bb74812ac6bb | 823 | |
akashvibhute | 2:3bdf0d9bb71f | 824 | //Max retries exceeded |
akashvibhute | 2:3bdf0d9bb71f | 825 | if( status & _BV(MAX_RT)){ |
akashvibhute | 2:3bdf0d9bb71f | 826 | flush_tx(); //Only going to be 1 packet int the FIFO at a time using this method, so just flush |
akashvibhute | 2:3bdf0d9bb71f | 827 | return 0; |
akashvibhute | 2:3bdf0d9bb71f | 828 | } |
akashvibhute | 2:3bdf0d9bb71f | 829 | //TX OK 1 or 0 |
akashvibhute | 2:3bdf0d9bb71f | 830 | return 1; |
akashvibhute | 2:3bdf0d9bb71f | 831 | } |
akashvibhute | 0:bb74812ac6bb | 832 | |
akashvibhute | 2:3bdf0d9bb71f | 833 | bool RF24::write( const void* buf, uint8_t len ){ |
akashvibhute | 2:3bdf0d9bb71f | 834 | return write(buf,len,0); |
akashvibhute | 0:bb74812ac6bb | 835 | } |
akashvibhute | 0:bb74812ac6bb | 836 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 837 | |
akashvibhute | 2:3bdf0d9bb71f | 838 | //For general use, the interrupt flags are not important to clear |
akashvibhute | 2:3bdf0d9bb71f | 839 | bool RF24::writeBlocking( const void* buf, uint8_t len, uint32_t timeout ) |
akashvibhute | 2:3bdf0d9bb71f | 840 | { |
akashvibhute | 2:3bdf0d9bb71f | 841 | //Block until the FIFO is NOT full. |
akashvibhute | 2:3bdf0d9bb71f | 842 | //Keep track of the MAX retries and set auto-retry if seeing failures |
akashvibhute | 2:3bdf0d9bb71f | 843 | //This way the FIFO will fill up and allow blocking until packets go through |
akashvibhute | 2:3bdf0d9bb71f | 844 | //The radio will auto-clear everything in the FIFO as long as CE remains high |
akashvibhute | 2:3bdf0d9bb71f | 845 | |
akashvibhute | 2:3bdf0d9bb71f | 846 | uint32_t timer = mainTimer.read_ms(); //Get the time that the payload transmission started |
akashvibhute | 2:3bdf0d9bb71f | 847 | |
akashvibhute | 2:3bdf0d9bb71f | 848 | while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or timeout |
akashvibhute | 2:3bdf0d9bb71f | 849 | |
akashvibhute | 2:3bdf0d9bb71f | 850 | if( get_status() & _BV(MAX_RT)){ //If MAX Retries have been reached |
akashvibhute | 2:3bdf0d9bb71f | 851 | reUseTX(); //Set re-transmit and clear the MAX_RT interrupt flag |
akashvibhute | 2:3bdf0d9bb71f | 852 | if(mainTimer.read_ms() - timer > timeout){ return 0; } //If this payload has exceeded the user-defined timeout, exit and return 0 |
akashvibhute | 2:3bdf0d9bb71f | 853 | } |
akashvibhute | 2:3bdf0d9bb71f | 854 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 855 | if(mainTimer.read_ms() - timer > (timeout+85) ){ |
akashvibhute | 2:3bdf0d9bb71f | 856 | errNotify(); |
akashvibhute | 2:3bdf0d9bb71f | 857 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 858 | return 0; |
akashvibhute | 2:3bdf0d9bb71f | 859 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 860 | } |
akashvibhute | 2:3bdf0d9bb71f | 861 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 862 | |
akashvibhute | 2:3bdf0d9bb71f | 863 | } |
akashvibhute | 2:3bdf0d9bb71f | 864 | |
akashvibhute | 2:3bdf0d9bb71f | 865 | //Start Writing |
akashvibhute | 2:3bdf0d9bb71f | 866 | startFastWrite(buf,len,0); //Write the payload if a buffer is clear |
akashvibhute | 2:3bdf0d9bb71f | 867 | |
akashvibhute | 2:3bdf0d9bb71f | 868 | return 1; //Return 1 to indicate successful transmission |
akashvibhute | 2:3bdf0d9bb71f | 869 | } |
akashvibhute | 2:3bdf0d9bb71f | 870 | |
akashvibhute | 2:3bdf0d9bb71f | 871 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 872 | |
akashvibhute | 2:3bdf0d9bb71f | 873 | void RF24::reUseTX(){ |
akashvibhute | 2:3bdf0d9bb71f | 874 | write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag |
akashvibhute | 2:3bdf0d9bb71f | 875 | spiTrans( REUSE_TX_PL ); |
akashvibhute | 2:3bdf0d9bb71f | 876 | ce_pin=LOW; //Re-Transfer packet |
akashvibhute | 2:3bdf0d9bb71f | 877 | ce_pin=HIGH; |
akashvibhute | 2:3bdf0d9bb71f | 878 | } |
akashvibhute | 2:3bdf0d9bb71f | 879 | |
akashvibhute | 2:3bdf0d9bb71f | 880 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 881 | |
akashvibhute | 2:3bdf0d9bb71f | 882 | bool RF24::writeFast( const void* buf, uint8_t len, const bool multicast ) |
akashvibhute | 0:bb74812ac6bb | 883 | { |
akashvibhute | 2:3bdf0d9bb71f | 884 | //Block until the FIFO is NOT full. |
akashvibhute | 2:3bdf0d9bb71f | 885 | //Keep track of the MAX retries and set auto-retry if seeing failures |
akashvibhute | 2:3bdf0d9bb71f | 886 | //Return 0 so the user can control the retrys and set a timer or failure counter if required |
akashvibhute | 2:3bdf0d9bb71f | 887 | //The radio will auto-clear everything in the FIFO as long as CE remains high |
akashvibhute | 2:3bdf0d9bb71f | 888 | |
akashvibhute | 2:3bdf0d9bb71f | 889 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 890 | uint32_t timer = mainTimer.read_ms(); |
akashvibhute | 2:3bdf0d9bb71f | 891 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 892 | |
akashvibhute | 2:3bdf0d9bb71f | 893 | while( ( get_status() & ( _BV(TX_FULL) ))) { //Blocking only if FIFO is full. This will loop and block until TX is successful or fail |
akashvibhute | 2:3bdf0d9bb71f | 894 | |
akashvibhute | 2:3bdf0d9bb71f | 895 | if( get_status() & _BV(MAX_RT)){ |
akashvibhute | 2:3bdf0d9bb71f | 896 | //reUseTX(); //Set re-transmit |
akashvibhute | 2:3bdf0d9bb71f | 897 | write_register(NRF_STATUS,_BV(MAX_RT) ); //Clear max retry flag |
akashvibhute | 2:3bdf0d9bb71f | 898 | return 0; //Return 0. The previous payload has been retransmitted |
akashvibhute | 2:3bdf0d9bb71f | 899 | //From the user perspective, if you get a 0, just keep trying to send the same payload |
akashvibhute | 2:3bdf0d9bb71f | 900 | } |
akashvibhute | 2:3bdf0d9bb71f | 901 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 902 | if(mainTimer.read_ms() - timer > 85 ){ |
akashvibhute | 2:3bdf0d9bb71f | 903 | errNotify(); |
akashvibhute | 2:3bdf0d9bb71f | 904 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 905 | return 0; |
akashvibhute | 2:3bdf0d9bb71f | 906 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 907 | } |
akashvibhute | 2:3bdf0d9bb71f | 908 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 909 | } |
akashvibhute | 2:3bdf0d9bb71f | 910 | //Start Writing |
akashvibhute | 2:3bdf0d9bb71f | 911 | startFastWrite(buf,len,multicast); |
akashvibhute | 2:3bdf0d9bb71f | 912 | |
akashvibhute | 2:3bdf0d9bb71f | 913 | return 1; |
akashvibhute | 2:3bdf0d9bb71f | 914 | } |
akashvibhute | 2:3bdf0d9bb71f | 915 | |
akashvibhute | 2:3bdf0d9bb71f | 916 | bool RF24::writeFast( const void* buf, uint8_t len ){ |
akashvibhute | 2:3bdf0d9bb71f | 917 | return writeFast(buf,len,0); |
akashvibhute | 2:3bdf0d9bb71f | 918 | } |
akashvibhute | 2:3bdf0d9bb71f | 919 | |
akashvibhute | 2:3bdf0d9bb71f | 920 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 921 | |
akashvibhute | 2:3bdf0d9bb71f | 922 | //Per the documentation, we want to set PTX Mode when not listening. Then all we do is write data and set CE high |
akashvibhute | 2:3bdf0d9bb71f | 923 | //In this mode, if we can keep the FIFO buffers loaded, packets will transmit immediately (no 130us delay) |
akashvibhute | 2:3bdf0d9bb71f | 924 | //Otherwise we enter Standby-II mode, which is still faster than standby mode |
akashvibhute | 2:3bdf0d9bb71f | 925 | //Also, we remove the need to keep writing the config register over and over and delaying for 150 us each time if sending a stream of data |
akashvibhute | 2:3bdf0d9bb71f | 926 | |
akashvibhute | 2:3bdf0d9bb71f | 927 | void RF24::startFastWrite( const void* buf, uint8_t len, const bool multicast, bool startTx){ //TMRh20 |
akashvibhute | 2:3bdf0d9bb71f | 928 | |
akashvibhute | 2:3bdf0d9bb71f | 929 | //write_payload( buf,len); |
akashvibhute | 2:3bdf0d9bb71f | 930 | write_payload( buf, len,multicast ? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ; |
akashvibhute | 2:3bdf0d9bb71f | 931 | if(startTx){ |
akashvibhute | 2:3bdf0d9bb71f | 932 | ce_pin=HIGH; |
akashvibhute | 2:3bdf0d9bb71f | 933 | } |
akashvibhute | 2:3bdf0d9bb71f | 934 | |
akashvibhute | 2:3bdf0d9bb71f | 935 | } |
akashvibhute | 2:3bdf0d9bb71f | 936 | |
akashvibhute | 2:3bdf0d9bb71f | 937 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 938 | |
akashvibhute | 2:3bdf0d9bb71f | 939 | //Added the original startWrite back in so users can still use interrupts, ack payloads, etc |
akashvibhute | 2:3bdf0d9bb71f | 940 | //Allows the library to pass all tests |
akashvibhute | 2:3bdf0d9bb71f | 941 | void RF24::startWrite( const void* buf, uint8_t len, const bool multicast ){ |
akashvibhute | 0:bb74812ac6bb | 942 | |
akashvibhute | 0:bb74812ac6bb | 943 | // Send the payload |
akashvibhute | 2:3bdf0d9bb71f | 944 | |
akashvibhute | 2:3bdf0d9bb71f | 945 | //write_payload( buf, len ); |
akashvibhute | 2:3bdf0d9bb71f | 946 | write_payload( buf, len,multicast? W_TX_PAYLOAD_NO_ACK : W_TX_PAYLOAD ) ; |
akashvibhute | 2:3bdf0d9bb71f | 947 | ce_pin=HIGH; |
akashvibhute | 2:3bdf0d9bb71f | 948 | |
akashvibhute | 2:3bdf0d9bb71f | 949 | wait_us(10); |
akashvibhute | 2:3bdf0d9bb71f | 950 | |
akashvibhute | 2:3bdf0d9bb71f | 951 | ce_pin=LOW; |
akashvibhute | 2:3bdf0d9bb71f | 952 | |
akashvibhute | 2:3bdf0d9bb71f | 953 | |
akashvibhute | 2:3bdf0d9bb71f | 954 | } |
akashvibhute | 2:3bdf0d9bb71f | 955 | |
akashvibhute | 2:3bdf0d9bb71f | 956 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 957 | |
akashvibhute | 2:3bdf0d9bb71f | 958 | bool RF24::rxFifoFull(){ |
akashvibhute | 2:3bdf0d9bb71f | 959 | return read_register(FIFO_STATUS) & _BV(RX_FULL); |
akashvibhute | 2:3bdf0d9bb71f | 960 | } |
akashvibhute | 2:3bdf0d9bb71f | 961 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 962 | |
akashvibhute | 2:3bdf0d9bb71f | 963 | bool RF24::txStandBy(){ |
akashvibhute | 2:3bdf0d9bb71f | 964 | |
akashvibhute | 2:3bdf0d9bb71f | 965 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 966 | uint32_t timeout = mainTimer.read_ms(); |
akashvibhute | 2:3bdf0d9bb71f | 967 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 968 | while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){ |
akashvibhute | 2:3bdf0d9bb71f | 969 | if( get_status() & _BV(MAX_RT)){ |
akashvibhute | 2:3bdf0d9bb71f | 970 | write_register(NRF_STATUS,_BV(MAX_RT) ); |
akashvibhute | 2:3bdf0d9bb71f | 971 | ce_pin=LOW; |
akashvibhute | 2:3bdf0d9bb71f | 972 | flush_tx(); //Non blocking, flush the data |
akashvibhute | 2:3bdf0d9bb71f | 973 | return 0; |
akashvibhute | 2:3bdf0d9bb71f | 974 | } |
akashvibhute | 2:3bdf0d9bb71f | 975 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 976 | if( mainTimer.read_ms() - timeout > 85){ |
akashvibhute | 2:3bdf0d9bb71f | 977 | errNotify(); |
akashvibhute | 2:3bdf0d9bb71f | 978 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 979 | return 0; |
akashvibhute | 2:3bdf0d9bb71f | 980 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 981 | } |
akashvibhute | 2:3bdf0d9bb71f | 982 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 983 | } |
akashvibhute | 0:bb74812ac6bb | 984 | |
akashvibhute | 2:3bdf0d9bb71f | 985 | ce_pin=LOW; //Set STANDBY-I mode |
akashvibhute | 2:3bdf0d9bb71f | 986 | return 1; |
akashvibhute | 2:3bdf0d9bb71f | 987 | } |
akashvibhute | 2:3bdf0d9bb71f | 988 | |
akashvibhute | 2:3bdf0d9bb71f | 989 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 990 | |
akashvibhute | 2:3bdf0d9bb71f | 991 | bool RF24::txStandBy(uint32_t timeout, bool startTx){ |
akashvibhute | 2:3bdf0d9bb71f | 992 | |
akashvibhute | 2:3bdf0d9bb71f | 993 | if(startTx){ |
akashvibhute | 2:3bdf0d9bb71f | 994 | stopListening(); |
akashvibhute | 2:3bdf0d9bb71f | 995 | ce_pin=HIGH; |
akashvibhute | 2:3bdf0d9bb71f | 996 | } |
akashvibhute | 2:3bdf0d9bb71f | 997 | uint32_t start = mainTimer.read_ms(); |
akashvibhute | 2:3bdf0d9bb71f | 998 | |
akashvibhute | 2:3bdf0d9bb71f | 999 | while( ! (read_register(FIFO_STATUS) & _BV(TX_EMPTY)) ){ |
akashvibhute | 2:3bdf0d9bb71f | 1000 | if( get_status() & _BV(MAX_RT)){ |
akashvibhute | 2:3bdf0d9bb71f | 1001 | write_register(NRF_STATUS,_BV(MAX_RT) ); |
akashvibhute | 2:3bdf0d9bb71f | 1002 | ce_pin=LOW; //Set re-transmit |
akashvibhute | 2:3bdf0d9bb71f | 1003 | ce_pin=HIGH; |
akashvibhute | 2:3bdf0d9bb71f | 1004 | if(mainTimer.read_ms() - start >= timeout){ |
akashvibhute | 2:3bdf0d9bb71f | 1005 | ce_pin=LOW;; flush_tx(); return 0; |
akashvibhute | 2:3bdf0d9bb71f | 1006 | } |
akashvibhute | 2:3bdf0d9bb71f | 1007 | } |
akashvibhute | 2:3bdf0d9bb71f | 1008 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 1009 | if( mainTimer.read_ms() - start > (timeout+85)){ |
akashvibhute | 2:3bdf0d9bb71f | 1010 | errNotify(); |
akashvibhute | 2:3bdf0d9bb71f | 1011 | #if defined (FAILURE_HANDLING) |
akashvibhute | 2:3bdf0d9bb71f | 1012 | return 0; |
akashvibhute | 2:3bdf0d9bb71f | 1013 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 1014 | } |
akashvibhute | 2:3bdf0d9bb71f | 1015 | #endif |
akashvibhute | 2:3bdf0d9bb71f | 1016 | } |
akashvibhute | 2:3bdf0d9bb71f | 1017 | |
akashvibhute | 2:3bdf0d9bb71f | 1018 | |
akashvibhute | 2:3bdf0d9bb71f | 1019 | ce_pin=LOW; //Set STANDBY-I mode |
akashvibhute | 2:3bdf0d9bb71f | 1020 | return 1; |
akashvibhute | 2:3bdf0d9bb71f | 1021 | |
akashvibhute | 2:3bdf0d9bb71f | 1022 | } |
akashvibhute | 2:3bdf0d9bb71f | 1023 | |
akashvibhute | 2:3bdf0d9bb71f | 1024 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 1025 | |
akashvibhute | 2:3bdf0d9bb71f | 1026 | void RF24::maskIRQ(bool tx, bool fail, bool rx){ |
akashvibhute | 2:3bdf0d9bb71f | 1027 | |
akashvibhute | 2:3bdf0d9bb71f | 1028 | write_register(CONFIG, ( read_register(CONFIG) ) | fail << MASK_MAX_RT | tx << MASK_TX_DS | rx << MASK_RX_DR ); |
akashvibhute | 0:bb74812ac6bb | 1029 | } |
akashvibhute | 0:bb74812ac6bb | 1030 | |
akashvibhute | 0:bb74812ac6bb | 1031 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1032 | |
akashvibhute | 0:bb74812ac6bb | 1033 | uint8_t RF24::getDynamicPayloadSize(void) |
akashvibhute | 0:bb74812ac6bb | 1034 | { |
akashvibhute | 0:bb74812ac6bb | 1035 | uint8_t result = 0; |
akashvibhute | 0:bb74812ac6bb | 1036 | |
akashvibhute | 2:3bdf0d9bb71f | 1037 | |
akashvibhute | 2:3bdf0d9bb71f | 1038 | |
akashvibhute | 2:3bdf0d9bb71f | 1039 | |
akashvibhute | 2:3bdf0d9bb71f | 1040 | |
akashvibhute | 2:3bdf0d9bb71f | 1041 | |
akashvibhute | 2:3bdf0d9bb71f | 1042 | |
akashvibhute | 2:3bdf0d9bb71f | 1043 | |
akashvibhute | 2:3bdf0d9bb71f | 1044 | |
akashvibhute | 2:3bdf0d9bb71f | 1045 | beginTransaction(); |
akashvibhute | 0:bb74812ac6bb | 1046 | spi.write( R_RX_PL_WID ); |
akashvibhute | 0:bb74812ac6bb | 1047 | result = spi.write(0xff); |
akashvibhute | 2:3bdf0d9bb71f | 1048 | endTransaction(); |
akashvibhute | 0:bb74812ac6bb | 1049 | |
akashvibhute | 2:3bdf0d9bb71f | 1050 | |
akashvibhute | 2:3bdf0d9bb71f | 1051 | if(result > 32) { flush_rx(); wait_ms(2); return 0; } |
akashvibhute | 0:bb74812ac6bb | 1052 | return result; |
akashvibhute | 0:bb74812ac6bb | 1053 | } |
akashvibhute | 0:bb74812ac6bb | 1054 | |
akashvibhute | 0:bb74812ac6bb | 1055 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1056 | |
akashvibhute | 0:bb74812ac6bb | 1057 | bool RF24::available(void) |
akashvibhute | 0:bb74812ac6bb | 1058 | { |
akashvibhute | 0:bb74812ac6bb | 1059 | return available(NULL); |
akashvibhute | 0:bb74812ac6bb | 1060 | } |
akashvibhute | 0:bb74812ac6bb | 1061 | |
akashvibhute | 0:bb74812ac6bb | 1062 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1063 | |
akashvibhute | 0:bb74812ac6bb | 1064 | bool RF24::available(uint8_t* pipe_num) |
akashvibhute | 0:bb74812ac6bb | 1065 | { |
akashvibhute | 2:3bdf0d9bb71f | 1066 | if (!( read_register(FIFO_STATUS) & _BV(RX_EMPTY) )) { |
akashvibhute | 0:bb74812ac6bb | 1067 | |
akashvibhute | 2:3bdf0d9bb71f | 1068 | // If the caller wants the pipe number, include that |
akashvibhute | 2:3bdf0d9bb71f | 1069 | if ( pipe_num ) { |
akashvibhute | 2:3bdf0d9bb71f | 1070 | uint8_t status = get_status(); |
akashvibhute | 2:3bdf0d9bb71f | 1071 | *pipe_num = ( status >> RX_P_NO ) & 7; |
akashvibhute | 2:3bdf0d9bb71f | 1072 | } |
akashvibhute | 2:3bdf0d9bb71f | 1073 | return 1; |
akashvibhute | 0:bb74812ac6bb | 1074 | } |
akashvibhute | 2:3bdf0d9bb71f | 1075 | |
akashvibhute | 2:3bdf0d9bb71f | 1076 | |
akashvibhute | 2:3bdf0d9bb71f | 1077 | return 0; |
akashvibhute | 2:3bdf0d9bb71f | 1078 | |
akashvibhute | 2:3bdf0d9bb71f | 1079 | |
akashvibhute | 0:bb74812ac6bb | 1080 | } |
akashvibhute | 0:bb74812ac6bb | 1081 | |
akashvibhute | 0:bb74812ac6bb | 1082 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1083 | |
akashvibhute | 2:3bdf0d9bb71f | 1084 | void RF24::read( void* buf, uint8_t len ){ |
akashvibhute | 2:3bdf0d9bb71f | 1085 | |
akashvibhute | 0:bb74812ac6bb | 1086 | // Fetch the payload |
akashvibhute | 0:bb74812ac6bb | 1087 | read_payload( buf, len ); |
akashvibhute | 0:bb74812ac6bb | 1088 | |
akashvibhute | 2:3bdf0d9bb71f | 1089 | //Clear the two possible interrupt flags with one command |
akashvibhute | 2:3bdf0d9bb71f | 1090 | write_register(NRF_STATUS,_BV(RX_DR) | _BV(MAX_RT) | _BV(TX_DS) ); |
akashvibhute | 2:3bdf0d9bb71f | 1091 | |
akashvibhute | 0:bb74812ac6bb | 1092 | } |
akashvibhute | 0:bb74812ac6bb | 1093 | |
akashvibhute | 0:bb74812ac6bb | 1094 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1095 | |
akashvibhute | 0:bb74812ac6bb | 1096 | void RF24::whatHappened(bool& tx_ok,bool& tx_fail,bool& rx_ready) |
akashvibhute | 0:bb74812ac6bb | 1097 | { |
akashvibhute | 0:bb74812ac6bb | 1098 | // Read the status & reset the status in one easy call |
akashvibhute | 0:bb74812ac6bb | 1099 | // Or is that such a good idea? |
akashvibhute | 2:3bdf0d9bb71f | 1100 | uint8_t status = write_register(NRF_STATUS,_BV(RX_DR) | _BV(TX_DS) | _BV(MAX_RT) ); |
akashvibhute | 0:bb74812ac6bb | 1101 | |
akashvibhute | 0:bb74812ac6bb | 1102 | // Report to the user what happened |
akashvibhute | 0:bb74812ac6bb | 1103 | tx_ok = status & _BV(TX_DS); |
akashvibhute | 0:bb74812ac6bb | 1104 | tx_fail = status & _BV(MAX_RT); |
akashvibhute | 0:bb74812ac6bb | 1105 | rx_ready = status & _BV(RX_DR); |
akashvibhute | 0:bb74812ac6bb | 1106 | } |
akashvibhute | 0:bb74812ac6bb | 1107 | |
akashvibhute | 0:bb74812ac6bb | 1108 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1109 | |
akashvibhute | 0:bb74812ac6bb | 1110 | void RF24::openWritingPipe(uint64_t value) |
akashvibhute | 0:bb74812ac6bb | 1111 | { |
akashvibhute | 0:bb74812ac6bb | 1112 | // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+) |
akashvibhute | 0:bb74812ac6bb | 1113 | // expects it LSB first too, so we're good. |
akashvibhute | 0:bb74812ac6bb | 1114 | |
akashvibhute | 2:3bdf0d9bb71f | 1115 | write_register(RX_ADDR_P0, reinterpret_cast<uint8_t*>(&value), addr_width); |
akashvibhute | 2:3bdf0d9bb71f | 1116 | write_register(TX_ADDR, reinterpret_cast<uint8_t*>(&value), addr_width); |
akashvibhute | 2:3bdf0d9bb71f | 1117 | |
akashvibhute | 0:bb74812ac6bb | 1118 | |
akashvibhute | 2:3bdf0d9bb71f | 1119 | //const uint8_t max_payload_size = 32; |
akashvibhute | 2:3bdf0d9bb71f | 1120 | //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size)); |
akashvibhute | 2:3bdf0d9bb71f | 1121 | write_register(RX_PW_P0,payload_size); |
akashvibhute | 0:bb74812ac6bb | 1122 | } |
akashvibhute | 0:bb74812ac6bb | 1123 | |
akashvibhute | 0:bb74812ac6bb | 1124 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 1125 | void RF24::openWritingPipe(const uint8_t *address) |
akashvibhute | 2:3bdf0d9bb71f | 1126 | { |
akashvibhute | 2:3bdf0d9bb71f | 1127 | // Note that AVR 8-bit uC's store this LSB first, and the NRF24L01(+) |
akashvibhute | 2:3bdf0d9bb71f | 1128 | // expects it LSB first too, so we're good. |
akashvibhute | 0:bb74812ac6bb | 1129 | |
akashvibhute | 2:3bdf0d9bb71f | 1130 | write_register(RX_ADDR_P0,address, addr_width); |
akashvibhute | 2:3bdf0d9bb71f | 1131 | write_register(TX_ADDR, address, addr_width); |
akashvibhute | 2:3bdf0d9bb71f | 1132 | |
akashvibhute | 2:3bdf0d9bb71f | 1133 | //const uint8_t max_payload_size = 32; |
akashvibhute | 2:3bdf0d9bb71f | 1134 | //write_register(RX_PW_P0,rf24_min(payload_size,max_payload_size)); |
akashvibhute | 2:3bdf0d9bb71f | 1135 | write_register(RX_PW_P0,payload_size); |
akashvibhute | 2:3bdf0d9bb71f | 1136 | } |
akashvibhute | 2:3bdf0d9bb71f | 1137 | |
akashvibhute | 2:3bdf0d9bb71f | 1138 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 1139 | static const uint8_t child_pipe[] PROGMEM = |
akashvibhute | 0:bb74812ac6bb | 1140 | { |
akashvibhute | 0:bb74812ac6bb | 1141 | RX_ADDR_P0, RX_ADDR_P1, RX_ADDR_P2, RX_ADDR_P3, RX_ADDR_P4, RX_ADDR_P5 |
akashvibhute | 0:bb74812ac6bb | 1142 | }; |
akashvibhute | 2:3bdf0d9bb71f | 1143 | static const uint8_t child_payload_size[] PROGMEM = |
akashvibhute | 0:bb74812ac6bb | 1144 | { |
akashvibhute | 0:bb74812ac6bb | 1145 | RX_PW_P0, RX_PW_P1, RX_PW_P2, RX_PW_P3, RX_PW_P4, RX_PW_P5 |
akashvibhute | 0:bb74812ac6bb | 1146 | }; |
akashvibhute | 2:3bdf0d9bb71f | 1147 | |
akashvibhute | 0:bb74812ac6bb | 1148 | |
akashvibhute | 0:bb74812ac6bb | 1149 | void RF24::openReadingPipe(uint8_t child, uint64_t address) |
akashvibhute | 0:bb74812ac6bb | 1150 | { |
akashvibhute | 0:bb74812ac6bb | 1151 | // If this is pipe 0, cache the address. This is needed because |
akashvibhute | 0:bb74812ac6bb | 1152 | // openWritingPipe() will overwrite the pipe 0 address, so |
akashvibhute | 0:bb74812ac6bb | 1153 | // startListening() will have to restore it. |
akashvibhute | 2:3bdf0d9bb71f | 1154 | if (child == 0){ |
akashvibhute | 2:3bdf0d9bb71f | 1155 | memcpy(pipe0_reading_address,&address,addr_width); |
akashvibhute | 2:3bdf0d9bb71f | 1156 | } |
akashvibhute | 0:bb74812ac6bb | 1157 | |
akashvibhute | 0:bb74812ac6bb | 1158 | if (child <= 6) |
akashvibhute | 0:bb74812ac6bb | 1159 | { |
akashvibhute | 0:bb74812ac6bb | 1160 | // For pipes 2-5, only write the LSB |
akashvibhute | 0:bb74812ac6bb | 1161 | if ( child < 2 ) |
akashvibhute | 2:3bdf0d9bb71f | 1162 | write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), addr_width); |
akashvibhute | 0:bb74812ac6bb | 1163 | else |
akashvibhute | 2:3bdf0d9bb71f | 1164 | write_register(pgm_read_byte(&child_pipe[child]), reinterpret_cast<const uint8_t*>(&address), 1); |
akashvibhute | 0:bb74812ac6bb | 1165 | |
akashvibhute | 2:3bdf0d9bb71f | 1166 | write_register(pgm_read_byte(&child_payload_size[child]),payload_size); |
akashvibhute | 0:bb74812ac6bb | 1167 | |
akashvibhute | 0:bb74812ac6bb | 1168 | // Note it would be more efficient to set all of the bits for all open |
akashvibhute | 0:bb74812ac6bb | 1169 | // pipes at once. However, I thought it would make the calling code |
akashvibhute | 0:bb74812ac6bb | 1170 | // more simple to do it this way. |
akashvibhute | 2:3bdf0d9bb71f | 1171 | write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))); |
akashvibhute | 2:3bdf0d9bb71f | 1172 | } |
akashvibhute | 2:3bdf0d9bb71f | 1173 | } |
akashvibhute | 2:3bdf0d9bb71f | 1174 | |
akashvibhute | 2:3bdf0d9bb71f | 1175 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 1176 | void RF24::setAddressWidth(uint8_t a_width){ |
akashvibhute | 2:3bdf0d9bb71f | 1177 | |
akashvibhute | 2:3bdf0d9bb71f | 1178 | if(a_width -= 2){ |
akashvibhute | 2:3bdf0d9bb71f | 1179 | write_register(SETUP_AW,a_width%4); |
akashvibhute | 2:3bdf0d9bb71f | 1180 | addr_width = (a_width%4) + 2; |
akashvibhute | 2:3bdf0d9bb71f | 1181 | } |
akashvibhute | 2:3bdf0d9bb71f | 1182 | |
akashvibhute | 2:3bdf0d9bb71f | 1183 | } |
akashvibhute | 2:3bdf0d9bb71f | 1184 | |
akashvibhute | 2:3bdf0d9bb71f | 1185 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 1186 | |
akashvibhute | 2:3bdf0d9bb71f | 1187 | void RF24::openReadingPipe(uint8_t child, const uint8_t *address) |
akashvibhute | 2:3bdf0d9bb71f | 1188 | { |
akashvibhute | 2:3bdf0d9bb71f | 1189 | // If this is pipe 0, cache the address. This is needed because |
akashvibhute | 2:3bdf0d9bb71f | 1190 | // openWritingPipe() will overwrite the pipe 0 address, so |
akashvibhute | 2:3bdf0d9bb71f | 1191 | // startListening() will have to restore it. |
akashvibhute | 2:3bdf0d9bb71f | 1192 | if (child == 0){ |
akashvibhute | 2:3bdf0d9bb71f | 1193 | memcpy(pipe0_reading_address,address,addr_width); |
akashvibhute | 0:bb74812ac6bb | 1194 | } |
akashvibhute | 2:3bdf0d9bb71f | 1195 | if (child <= 6) |
akashvibhute | 2:3bdf0d9bb71f | 1196 | { |
akashvibhute | 2:3bdf0d9bb71f | 1197 | // For pipes 2-5, only write the LSB |
akashvibhute | 2:3bdf0d9bb71f | 1198 | if ( child < 2 ){ |
akashvibhute | 2:3bdf0d9bb71f | 1199 | write_register(pgm_read_byte(&child_pipe[child]), address, addr_width); |
akashvibhute | 2:3bdf0d9bb71f | 1200 | }else{ |
akashvibhute | 2:3bdf0d9bb71f | 1201 | write_register(pgm_read_byte(&child_pipe[child]), address, 1); |
akashvibhute | 2:3bdf0d9bb71f | 1202 | } |
akashvibhute | 2:3bdf0d9bb71f | 1203 | write_register(pgm_read_byte(&child_payload_size[child]),payload_size); |
akashvibhute | 2:3bdf0d9bb71f | 1204 | |
akashvibhute | 2:3bdf0d9bb71f | 1205 | // Note it would be more efficient to set all of the bits for all open |
akashvibhute | 2:3bdf0d9bb71f | 1206 | // pipes at once. However, I thought it would make the calling code |
akashvibhute | 2:3bdf0d9bb71f | 1207 | // more simple to do it this way. |
akashvibhute | 2:3bdf0d9bb71f | 1208 | write_register(EN_RXADDR,read_register(EN_RXADDR) | _BV(pgm_read_byte(&child_pipe_enable[child]))); |
akashvibhute | 2:3bdf0d9bb71f | 1209 | |
akashvibhute | 2:3bdf0d9bb71f | 1210 | } |
akashvibhute | 2:3bdf0d9bb71f | 1211 | } |
akashvibhute | 2:3bdf0d9bb71f | 1212 | |
akashvibhute | 2:3bdf0d9bb71f | 1213 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 1214 | |
akashvibhute | 2:3bdf0d9bb71f | 1215 | void RF24::closeReadingPipe( uint8_t pipe ) |
akashvibhute | 2:3bdf0d9bb71f | 1216 | { |
akashvibhute | 2:3bdf0d9bb71f | 1217 | write_register(EN_RXADDR,read_register(EN_RXADDR) & ~_BV(pgm_read_byte(&child_pipe_enable[pipe]))); |
akashvibhute | 0:bb74812ac6bb | 1218 | } |
akashvibhute | 0:bb74812ac6bb | 1219 | |
akashvibhute | 0:bb74812ac6bb | 1220 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1221 | |
akashvibhute | 0:bb74812ac6bb | 1222 | void RF24::toggle_features(void) |
akashvibhute | 0:bb74812ac6bb | 1223 | { |
akashvibhute | 2:3bdf0d9bb71f | 1224 | beginTransaction(); |
akashvibhute | 2:3bdf0d9bb71f | 1225 | spi.write( ACTIVATE ); |
akashvibhute | 2:3bdf0d9bb71f | 1226 | spi.write( 0x73 ); |
akashvibhute | 2:3bdf0d9bb71f | 1227 | endTransaction(); |
akashvibhute | 2:3bdf0d9bb71f | 1228 | |
akashvibhute | 2:3bdf0d9bb71f | 1229 | |
akashvibhute | 2:3bdf0d9bb71f | 1230 | |
akashvibhute | 2:3bdf0d9bb71f | 1231 | |
akashvibhute | 2:3bdf0d9bb71f | 1232 | |
akashvibhute | 2:3bdf0d9bb71f | 1233 | |
akashvibhute | 2:3bdf0d9bb71f | 1234 | |
akashvibhute | 2:3bdf0d9bb71f | 1235 | |
akashvibhute | 2:3bdf0d9bb71f | 1236 | |
akashvibhute | 0:bb74812ac6bb | 1237 | } |
akashvibhute | 0:bb74812ac6bb | 1238 | |
akashvibhute | 0:bb74812ac6bb | 1239 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1240 | |
akashvibhute | 0:bb74812ac6bb | 1241 | void RF24::enableDynamicPayloads(void) |
akashvibhute | 0:bb74812ac6bb | 1242 | { |
akashvibhute | 0:bb74812ac6bb | 1243 | // Enable dynamic payload throughout the system |
akashvibhute | 0:bb74812ac6bb | 1244 | |
akashvibhute | 2:3bdf0d9bb71f | 1245 | //toggle_features(); |
akashvibhute | 0:bb74812ac6bb | 1246 | write_register(FEATURE,read_register(FEATURE) | _BV(EN_DPL) ); |
akashvibhute | 2:3bdf0d9bb71f | 1247 | |
akashvibhute | 0:bb74812ac6bb | 1248 | |
akashvibhute | 2:3bdf0d9bb71f | 1249 | IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); |
akashvibhute | 0:bb74812ac6bb | 1250 | |
akashvibhute | 0:bb74812ac6bb | 1251 | // Enable dynamic payload on all pipes |
akashvibhute | 0:bb74812ac6bb | 1252 | // |
akashvibhute | 0:bb74812ac6bb | 1253 | // Not sure the use case of only having dynamic payload on certain |
akashvibhute | 0:bb74812ac6bb | 1254 | // pipes, so the library does not support it. |
akashvibhute | 0:bb74812ac6bb | 1255 | write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P5) | _BV(DPL_P4) | _BV(DPL_P3) | _BV(DPL_P2) | _BV(DPL_P1) | _BV(DPL_P0)); |
akashvibhute | 0:bb74812ac6bb | 1256 | |
akashvibhute | 0:bb74812ac6bb | 1257 | dynamic_payloads_enabled = true; |
akashvibhute | 0:bb74812ac6bb | 1258 | } |
akashvibhute | 0:bb74812ac6bb | 1259 | |
akashvibhute | 0:bb74812ac6bb | 1260 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1261 | |
akashvibhute | 0:bb74812ac6bb | 1262 | void RF24::enableAckPayload(void) |
akashvibhute | 0:bb74812ac6bb | 1263 | { |
akashvibhute | 0:bb74812ac6bb | 1264 | // |
akashvibhute | 0:bb74812ac6bb | 1265 | // enable ack payload and dynamic payload features |
akashvibhute | 0:bb74812ac6bb | 1266 | // |
akashvibhute | 0:bb74812ac6bb | 1267 | |
akashvibhute | 2:3bdf0d9bb71f | 1268 | //toggle_features(); |
akashvibhute | 2:3bdf0d9bb71f | 1269 | write_register(FEATURE,read_register(FEATURE) | _BV(EN_ACK_PAY) | _BV(EN_DPL) ); |
akashvibhute | 0:bb74812ac6bb | 1270 | |
akashvibhute | 2:3bdf0d9bb71f | 1271 | IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); |
akashvibhute | 0:bb74812ac6bb | 1272 | |
akashvibhute | 0:bb74812ac6bb | 1273 | // |
akashvibhute | 0:bb74812ac6bb | 1274 | // Enable dynamic payload on pipes 0 & 1 |
akashvibhute | 0:bb74812ac6bb | 1275 | // |
akashvibhute | 0:bb74812ac6bb | 1276 | |
akashvibhute | 0:bb74812ac6bb | 1277 | write_register(DYNPD,read_register(DYNPD) | _BV(DPL_P1) | _BV(DPL_P0)); |
akashvibhute | 2:3bdf0d9bb71f | 1278 | dynamic_payloads_enabled = true; |
akashvibhute | 2:3bdf0d9bb71f | 1279 | } |
akashvibhute | 2:3bdf0d9bb71f | 1280 | |
akashvibhute | 2:3bdf0d9bb71f | 1281 | /****************************************************************************/ |
akashvibhute | 2:3bdf0d9bb71f | 1282 | |
akashvibhute | 2:3bdf0d9bb71f | 1283 | void RF24::enableDynamicAck(void){ |
akashvibhute | 2:3bdf0d9bb71f | 1284 | // |
akashvibhute | 2:3bdf0d9bb71f | 1285 | // enable dynamic ack features |
akashvibhute | 2:3bdf0d9bb71f | 1286 | // |
akashvibhute | 2:3bdf0d9bb71f | 1287 | //toggle_features(); |
akashvibhute | 2:3bdf0d9bb71f | 1288 | write_register(FEATURE,read_register(FEATURE) | _BV(EN_DYN_ACK) ); |
akashvibhute | 2:3bdf0d9bb71f | 1289 | |
akashvibhute | 2:3bdf0d9bb71f | 1290 | IF_SERIAL_DEBUG(printf("FEATURE=%i\r\n",read_register(FEATURE))); |
akashvibhute | 2:3bdf0d9bb71f | 1291 | |
akashvibhute | 2:3bdf0d9bb71f | 1292 | |
akashvibhute | 0:bb74812ac6bb | 1293 | } |
akashvibhute | 0:bb74812ac6bb | 1294 | |
akashvibhute | 0:bb74812ac6bb | 1295 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1296 | |
akashvibhute | 0:bb74812ac6bb | 1297 | void RF24::writeAckPayload(uint8_t pipe, const void* buf, uint8_t len) |
akashvibhute | 0:bb74812ac6bb | 1298 | { |
akashvibhute | 0:bb74812ac6bb | 1299 | const uint8_t* current = reinterpret_cast<const uint8_t*>(buf); |
akashvibhute | 0:bb74812ac6bb | 1300 | |
akashvibhute | 2:3bdf0d9bb71f | 1301 | uint8_t data_len = rf24_min(len,32); |
akashvibhute | 2:3bdf0d9bb71f | 1302 | |
akashvibhute | 2:3bdf0d9bb71f | 1303 | beginTransaction(); |
akashvibhute | 2:3bdf0d9bb71f | 1304 | spi.write(W_ACK_PAYLOAD | ( pipe & 7 ) ); |
akashvibhute | 2:3bdf0d9bb71f | 1305 | |
akashvibhute | 0:bb74812ac6bb | 1306 | while ( data_len-- ) |
akashvibhute | 0:bb74812ac6bb | 1307 | spi.write(*current++); |
akashvibhute | 2:3bdf0d9bb71f | 1308 | endTransaction(); |
akashvibhute | 0:bb74812ac6bb | 1309 | |
akashvibhute | 0:bb74812ac6bb | 1310 | } |
akashvibhute | 0:bb74812ac6bb | 1311 | |
akashvibhute | 0:bb74812ac6bb | 1312 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1313 | |
akashvibhute | 0:bb74812ac6bb | 1314 | bool RF24::isAckPayloadAvailable(void) |
akashvibhute | 0:bb74812ac6bb | 1315 | { |
akashvibhute | 2:3bdf0d9bb71f | 1316 | return ! (read_register(FIFO_STATUS) & _BV(RX_EMPTY)); |
akashvibhute | 0:bb74812ac6bb | 1317 | } |
akashvibhute | 0:bb74812ac6bb | 1318 | |
akashvibhute | 0:bb74812ac6bb | 1319 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1320 | |
akashvibhute | 0:bb74812ac6bb | 1321 | bool RF24::isPVariant(void) |
akashvibhute | 0:bb74812ac6bb | 1322 | { |
akashvibhute | 0:bb74812ac6bb | 1323 | return p_variant ; |
akashvibhute | 0:bb74812ac6bb | 1324 | } |
akashvibhute | 0:bb74812ac6bb | 1325 | |
akashvibhute | 0:bb74812ac6bb | 1326 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1327 | |
akashvibhute | 0:bb74812ac6bb | 1328 | void RF24::setAutoAck(bool enable) |
akashvibhute | 0:bb74812ac6bb | 1329 | { |
akashvibhute | 0:bb74812ac6bb | 1330 | if ( enable ) |
akashvibhute | 0:bb74812ac6bb | 1331 | write_register(EN_AA, 63); |
akashvibhute | 0:bb74812ac6bb | 1332 | else |
akashvibhute | 0:bb74812ac6bb | 1333 | write_register(EN_AA, 0); |
akashvibhute | 0:bb74812ac6bb | 1334 | } |
akashvibhute | 0:bb74812ac6bb | 1335 | |
akashvibhute | 0:bb74812ac6bb | 1336 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1337 | |
akashvibhute | 0:bb74812ac6bb | 1338 | void RF24::setAutoAck( uint8_t pipe, bool enable ) |
akashvibhute | 0:bb74812ac6bb | 1339 | { |
akashvibhute | 0:bb74812ac6bb | 1340 | if ( pipe <= 6 ) |
akashvibhute | 0:bb74812ac6bb | 1341 | { |
akashvibhute | 0:bb74812ac6bb | 1342 | uint8_t en_aa = read_register( EN_AA ) ; |
akashvibhute | 0:bb74812ac6bb | 1343 | if( enable ) |
akashvibhute | 0:bb74812ac6bb | 1344 | { |
akashvibhute | 0:bb74812ac6bb | 1345 | en_aa |= _BV(pipe) ; |
akashvibhute | 0:bb74812ac6bb | 1346 | } |
akashvibhute | 0:bb74812ac6bb | 1347 | else |
akashvibhute | 0:bb74812ac6bb | 1348 | { |
akashvibhute | 0:bb74812ac6bb | 1349 | en_aa &= ~_BV(pipe) ; |
akashvibhute | 0:bb74812ac6bb | 1350 | } |
akashvibhute | 0:bb74812ac6bb | 1351 | write_register( EN_AA, en_aa ) ; |
akashvibhute | 0:bb74812ac6bb | 1352 | } |
akashvibhute | 0:bb74812ac6bb | 1353 | } |
akashvibhute | 0:bb74812ac6bb | 1354 | |
akashvibhute | 0:bb74812ac6bb | 1355 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1356 | |
akashvibhute | 0:bb74812ac6bb | 1357 | bool RF24::testCarrier(void) |
akashvibhute | 0:bb74812ac6bb | 1358 | { |
akashvibhute | 0:bb74812ac6bb | 1359 | return ( read_register(CD) & 1 ); |
akashvibhute | 0:bb74812ac6bb | 1360 | } |
akashvibhute | 0:bb74812ac6bb | 1361 | |
akashvibhute | 0:bb74812ac6bb | 1362 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1363 | |
akashvibhute | 0:bb74812ac6bb | 1364 | bool RF24::testRPD(void) |
akashvibhute | 0:bb74812ac6bb | 1365 | { |
akashvibhute | 0:bb74812ac6bb | 1366 | return ( read_register(RPD) & 1 ) ; |
akashvibhute | 0:bb74812ac6bb | 1367 | } |
akashvibhute | 0:bb74812ac6bb | 1368 | |
akashvibhute | 0:bb74812ac6bb | 1369 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1370 | |
akashvibhute | 2:3bdf0d9bb71f | 1371 | void RF24::setPALevel(uint8_t level) |
akashvibhute | 0:bb74812ac6bb | 1372 | { |
akashvibhute | 2:3bdf0d9bb71f | 1373 | |
akashvibhute | 2:3bdf0d9bb71f | 1374 | uint8_t setup = read_register(RF_SETUP) & 248; |
akashvibhute | 0:bb74812ac6bb | 1375 | |
akashvibhute | 2:3bdf0d9bb71f | 1376 | if(level > 3){ // If invalid level, go to max PA |
akashvibhute | 2:3bdf0d9bb71f | 1377 | level = (RF24_PA_MAX << 1) + 1; // +1 to support the SI24R1 chip extra bit |
akashvibhute | 2:3bdf0d9bb71f | 1378 | }else{ |
akashvibhute | 2:3bdf0d9bb71f | 1379 | level = (level << 1) + 1; // Else set level as requested |
akashvibhute | 0:bb74812ac6bb | 1380 | } |
akashvibhute | 0:bb74812ac6bb | 1381 | |
akashvibhute | 2:3bdf0d9bb71f | 1382 | |
akashvibhute | 2:3bdf0d9bb71f | 1383 | write_register( RF_SETUP, setup |= level ) ; // Write it to the chip |
akashvibhute | 0:bb74812ac6bb | 1384 | } |
akashvibhute | 0:bb74812ac6bb | 1385 | |
akashvibhute | 0:bb74812ac6bb | 1386 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1387 | |
akashvibhute | 2:3bdf0d9bb71f | 1388 | uint8_t RF24::getPALevel(void) |
akashvibhute | 0:bb74812ac6bb | 1389 | { |
akashvibhute | 0:bb74812ac6bb | 1390 | |
akashvibhute | 2:3bdf0d9bb71f | 1391 | return (read_register(RF_SETUP) & (_BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH))) >> 1 ; |
akashvibhute | 0:bb74812ac6bb | 1392 | } |
akashvibhute | 0:bb74812ac6bb | 1393 | |
akashvibhute | 0:bb74812ac6bb | 1394 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1395 | |
akashvibhute | 0:bb74812ac6bb | 1396 | bool RF24::setDataRate(rf24_datarate_e speed) |
akashvibhute | 0:bb74812ac6bb | 1397 | { |
akashvibhute | 0:bb74812ac6bb | 1398 | bool result = false; |
akashvibhute | 0:bb74812ac6bb | 1399 | uint8_t setup = read_register(RF_SETUP) ; |
akashvibhute | 0:bb74812ac6bb | 1400 | |
akashvibhute | 0:bb74812ac6bb | 1401 | // HIGH and LOW '00' is 1Mbs - our default |
akashvibhute | 0:bb74812ac6bb | 1402 | setup &= ~(_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)) ; |
akashvibhute | 2:3bdf0d9bb71f | 1403 | |
akashvibhute | 2:3bdf0d9bb71f | 1404 | |
akashvibhute | 2:3bdf0d9bb71f | 1405 | txRxDelay=85; |
akashvibhute | 2:3bdf0d9bb71f | 1406 | |
akashvibhute | 0:bb74812ac6bb | 1407 | if( speed == RF24_250KBPS ) |
akashvibhute | 0:bb74812ac6bb | 1408 | { |
akashvibhute | 0:bb74812ac6bb | 1409 | // Must set the RF_DR_LOW to 1; RF_DR_HIGH (used to be RF_DR) is already 0 |
akashvibhute | 0:bb74812ac6bb | 1410 | // Making it '10'. |
akashvibhute | 0:bb74812ac6bb | 1411 | setup |= _BV( RF_DR_LOW ) ; |
akashvibhute | 2:3bdf0d9bb71f | 1412 | txRxDelay=155; |
akashvibhute | 0:bb74812ac6bb | 1413 | } |
akashvibhute | 0:bb74812ac6bb | 1414 | else |
akashvibhute | 0:bb74812ac6bb | 1415 | { |
akashvibhute | 0:bb74812ac6bb | 1416 | // Set 2Mbs, RF_DR (RF_DR_HIGH) is set 1 |
akashvibhute | 0:bb74812ac6bb | 1417 | // Making it '01' |
akashvibhute | 0:bb74812ac6bb | 1418 | if ( speed == RF24_2MBPS ) |
akashvibhute | 0:bb74812ac6bb | 1419 | { |
akashvibhute | 0:bb74812ac6bb | 1420 | setup |= _BV(RF_DR_HIGH); |
akashvibhute | 2:3bdf0d9bb71f | 1421 | txRxDelay=65; |
akashvibhute | 0:bb74812ac6bb | 1422 | } |
akashvibhute | 0:bb74812ac6bb | 1423 | } |
akashvibhute | 0:bb74812ac6bb | 1424 | write_register(RF_SETUP,setup); |
akashvibhute | 0:bb74812ac6bb | 1425 | |
akashvibhute | 0:bb74812ac6bb | 1426 | // Verify our result |
akashvibhute | 0:bb74812ac6bb | 1427 | if ( read_register(RF_SETUP) == setup ) |
akashvibhute | 0:bb74812ac6bb | 1428 | { |
akashvibhute | 0:bb74812ac6bb | 1429 | result = true; |
akashvibhute | 0:bb74812ac6bb | 1430 | } |
akashvibhute | 0:bb74812ac6bb | 1431 | return result; |
akashvibhute | 0:bb74812ac6bb | 1432 | } |
akashvibhute | 0:bb74812ac6bb | 1433 | |
akashvibhute | 0:bb74812ac6bb | 1434 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1435 | |
akashvibhute | 0:bb74812ac6bb | 1436 | rf24_datarate_e RF24::getDataRate( void ) |
akashvibhute | 0:bb74812ac6bb | 1437 | { |
akashvibhute | 0:bb74812ac6bb | 1438 | rf24_datarate_e result ; |
akashvibhute | 0:bb74812ac6bb | 1439 | uint8_t dr = read_register(RF_SETUP) & (_BV(RF_DR_LOW) | _BV(RF_DR_HIGH)); |
akashvibhute | 2:3bdf0d9bb71f | 1440 | |
akashvibhute | 0:bb74812ac6bb | 1441 | // switch uses RAM (evil!) |
akashvibhute | 0:bb74812ac6bb | 1442 | // Order matters in our case below |
akashvibhute | 0:bb74812ac6bb | 1443 | if ( dr == _BV(RF_DR_LOW) ) |
akashvibhute | 0:bb74812ac6bb | 1444 | { |
akashvibhute | 0:bb74812ac6bb | 1445 | // '10' = 250KBPS |
akashvibhute | 0:bb74812ac6bb | 1446 | result = RF24_250KBPS ; |
akashvibhute | 0:bb74812ac6bb | 1447 | } |
akashvibhute | 0:bb74812ac6bb | 1448 | else if ( dr == _BV(RF_DR_HIGH) ) |
akashvibhute | 0:bb74812ac6bb | 1449 | { |
akashvibhute | 0:bb74812ac6bb | 1450 | // '01' = 2MBPS |
akashvibhute | 0:bb74812ac6bb | 1451 | result = RF24_2MBPS ; |
akashvibhute | 0:bb74812ac6bb | 1452 | } |
akashvibhute | 0:bb74812ac6bb | 1453 | else |
akashvibhute | 0:bb74812ac6bb | 1454 | { |
akashvibhute | 0:bb74812ac6bb | 1455 | // '00' = 1MBPS |
akashvibhute | 0:bb74812ac6bb | 1456 | result = RF24_1MBPS ; |
akashvibhute | 0:bb74812ac6bb | 1457 | } |
akashvibhute | 0:bb74812ac6bb | 1458 | return result ; |
akashvibhute | 0:bb74812ac6bb | 1459 | } |
akashvibhute | 0:bb74812ac6bb | 1460 | |
akashvibhute | 0:bb74812ac6bb | 1461 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1462 | |
akashvibhute | 0:bb74812ac6bb | 1463 | void RF24::setCRCLength(rf24_crclength_e length) |
akashvibhute | 0:bb74812ac6bb | 1464 | { |
akashvibhute | 0:bb74812ac6bb | 1465 | uint8_t config = read_register(CONFIG) & ~( _BV(CRCO) | _BV(EN_CRC)) ; |
akashvibhute | 2:3bdf0d9bb71f | 1466 | |
akashvibhute | 2:3bdf0d9bb71f | 1467 | // switch uses RAM (evil!) |
akashvibhute | 0:bb74812ac6bb | 1468 | if ( length == RF24_CRC_DISABLED ) |
akashvibhute | 0:bb74812ac6bb | 1469 | { |
akashvibhute | 2:3bdf0d9bb71f | 1470 | // Do nothing, we turned it off above. |
akashvibhute | 0:bb74812ac6bb | 1471 | } |
akashvibhute | 0:bb74812ac6bb | 1472 | else if ( length == RF24_CRC_8 ) |
akashvibhute | 0:bb74812ac6bb | 1473 | { |
akashvibhute | 0:bb74812ac6bb | 1474 | config |= _BV(EN_CRC); |
akashvibhute | 0:bb74812ac6bb | 1475 | } |
akashvibhute | 0:bb74812ac6bb | 1476 | else |
akashvibhute | 0:bb74812ac6bb | 1477 | { |
akashvibhute | 0:bb74812ac6bb | 1478 | config |= _BV(EN_CRC); |
akashvibhute | 0:bb74812ac6bb | 1479 | config |= _BV( CRCO ); |
akashvibhute | 0:bb74812ac6bb | 1480 | } |
akashvibhute | 0:bb74812ac6bb | 1481 | write_register( CONFIG, config ) ; |
akashvibhute | 0:bb74812ac6bb | 1482 | } |
akashvibhute | 0:bb74812ac6bb | 1483 | |
akashvibhute | 0:bb74812ac6bb | 1484 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1485 | |
akashvibhute | 0:bb74812ac6bb | 1486 | rf24_crclength_e RF24::getCRCLength(void) |
akashvibhute | 0:bb74812ac6bb | 1487 | { |
akashvibhute | 0:bb74812ac6bb | 1488 | rf24_crclength_e result = RF24_CRC_DISABLED; |
akashvibhute | 2:3bdf0d9bb71f | 1489 | |
akashvibhute | 0:bb74812ac6bb | 1490 | uint8_t config = read_register(CONFIG) & ( _BV(CRCO) | _BV(EN_CRC)) ; |
akashvibhute | 2:3bdf0d9bb71f | 1491 | uint8_t AA = read_register(EN_AA); |
akashvibhute | 2:3bdf0d9bb71f | 1492 | |
akashvibhute | 2:3bdf0d9bb71f | 1493 | if ( config & _BV(EN_CRC ) || AA) |
akashvibhute | 0:bb74812ac6bb | 1494 | { |
akashvibhute | 0:bb74812ac6bb | 1495 | if ( config & _BV(CRCO) ) |
akashvibhute | 0:bb74812ac6bb | 1496 | result = RF24_CRC_16; |
akashvibhute | 0:bb74812ac6bb | 1497 | else |
akashvibhute | 0:bb74812ac6bb | 1498 | result = RF24_CRC_8; |
akashvibhute | 0:bb74812ac6bb | 1499 | } |
akashvibhute | 0:bb74812ac6bb | 1500 | |
akashvibhute | 0:bb74812ac6bb | 1501 | return result; |
akashvibhute | 0:bb74812ac6bb | 1502 | } |
akashvibhute | 0:bb74812ac6bb | 1503 | |
akashvibhute | 0:bb74812ac6bb | 1504 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1505 | |
akashvibhute | 0:bb74812ac6bb | 1506 | void RF24::disableCRC( void ) |
akashvibhute | 0:bb74812ac6bb | 1507 | { |
akashvibhute | 0:bb74812ac6bb | 1508 | uint8_t disable = read_register(CONFIG) & ~_BV(EN_CRC) ; |
akashvibhute | 0:bb74812ac6bb | 1509 | write_register( CONFIG, disable ) ; |
akashvibhute | 0:bb74812ac6bb | 1510 | } |
akashvibhute | 0:bb74812ac6bb | 1511 | |
akashvibhute | 0:bb74812ac6bb | 1512 | /****************************************************************************/ |
akashvibhute | 0:bb74812ac6bb | 1513 | void RF24::setRetries(uint8_t delay, uint8_t count) |
akashvibhute | 0:bb74812ac6bb | 1514 | { |
akashvibhute | 0:bb74812ac6bb | 1515 | write_register(SETUP_RETR,(delay&0xf)<<ARD | (count&0xf)<<ARC); |
akashvibhute | 0:bb74812ac6bb | 1516 | } |