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Dependencies: FiniteStateMachine HipControl Knee LinearBlend1 LocalFileSystem_Read dataComm hapticFeedback initExoVars mbed Blend_Generator Brad_poly_gait Gait_Generator MM_gait Encoders IMUdriver
Fork of Motion Control by
Knee/StepperDriver/StepperDriver.h@0:d38d627c922f, 2014-11-14 (annotated)
- Committer:
- perr1940
- Date:
- Fri Nov 14 22:39:10 2014 +0000
- Revision:
- 0:d38d627c922f
- Child:
- 3:9719ad064a2c
this is without encoders going to test the knee steppers alone. They work alone but not with the encoders. Strange huh?
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| perr1940 | 0:d38d627c922f | 1 | /* L6482 Driver code communicated via SPI |
| perr1940 | 0:d38d627c922f | 2 | * file name: StepperDriver.h |
| perr1940 | 0:d38d627c922f | 3 | * 07/15/2014 edited by Grace |
| perr1940 | 0:d38d627c922f | 4 | */ |
| perr1940 | 0:d38d627c922f | 5 | |
| perr1940 | 0:d38d627c922f | 6 | #ifndef STEPPERDRIVER_H |
| perr1940 | 0:d38d627c922f | 7 | #define STEPPERDRIVER_H |
| perr1940 | 0:d38d627c922f | 8 | |
| perr1940 | 0:d38d627c922f | 9 | #include "mbed.h" |
| perr1940 | 0:d38d627c922f | 10 | |
| perr1940 | 0:d38d627c922f | 11 | class StepperDriver |
| perr1940 | 0:d38d627c922f | 12 | { |
| perr1940 | 0:d38d627c922f | 13 | public: |
| perr1940 | 0:d38d627c922f | 14 | // Constructor |
| perr1940 | 0:d38d627c922f | 15 | StepperDriver(PinName CSPin, PinName mosi, PinName miso, PinName sck); |
| perr1940 | 0:d38d627c922f | 16 | |
| perr1940 | 0:d38d627c922f | 17 | // Provide access to the parameter |
| perr1940 | 0:d38d627c922f | 18 | void setParam (char param, unsigned long value); |
| perr1940 | 0:d38d627c922f | 19 | unsigned long getParam(char param); |
| perr1940 | 0:d38d627c922f | 20 | void setAcc(float stepsPerSecPerSec); |
| perr1940 | 0:d38d627c922f | 21 | void setDec(float stepsPerSecPerSec); |
| perr1940 | 0:d38d627c922f | 22 | void setMaxSpeed(float stepsPerSecond); |
| perr1940 | 0:d38d627c922f | 23 | void setDecTVAL(char tvalInput); |
| perr1940 | 0:d38d627c922f | 24 | void setAccTVAL(char tvalInput); |
| perr1940 | 0:d38d627c922f | 25 | void setRunTVAL(char tvalInput); |
| perr1940 | 0:d38d627c922f | 26 | void setHoldTVAL(char tvalInput); |
| perr1940 | 0:d38d627c922f | 27 | int getStatus(); |
| perr1940 | 0:d38d627c922f | 28 | void resetDev(); |
| perr1940 | 0:d38d627c922f | 29 | void hardHiZ(); |
| perr1940 | 0:d38d627c922f | 30 | void softHiZ(); |
| perr1940 | 0:d38d627c922f | 31 | |
| perr1940 | 0:d38d627c922f | 32 | // Operational commands |
| perr1940 | 0:d38d627c922f | 33 | void run (char dir, float stepsPerSec); |
| perr1940 | 0:d38d627c922f | 34 | void move(char dir, unsigned long numSteps); |
| perr1940 | 0:d38d627c922f | 35 | |
| perr1940 | 0:d38d627c922f | 36 | private: |
| perr1940 | 0:d38d627c922f | 37 | |
| perr1940 | 0:d38d627c922f | 38 | char SPIWrite (char data); |
| perr1940 | 0:d38d627c922f | 39 | unsigned long writeParam (unsigned long value, char bitLength); |
| perr1940 | 0:d38d627c922f | 40 | unsigned long paramHandler (char param, unsigned long value); |
| perr1940 | 0:d38d627c922f | 41 | |
| perr1940 | 0:d38d627c922f | 42 | // converting the units to L6482 units |
| perr1940 | 0:d38d627c922f | 43 | |
| perr1940 | 0:d38d627c922f | 44 | unsigned long accCalc (float stepsPerSecPerSec); |
| perr1940 | 0:d38d627c922f | 45 | unsigned long decCalc (float stepsPerSecPerSec); |
| perr1940 | 0:d38d627c922f | 46 | unsigned long spdCalc (float stepsPerSec); |
| perr1940 | 0:d38d627c922f | 47 | unsigned long maxSpdCalc(float stepsPerSec); |
| perr1940 | 0:d38d627c922f | 48 | unsigned long minSpdCalc(float stepsPerSec); |
| perr1940 | 0:d38d627c922f | 49 | void setFullSpeed(float stepsPerSecond); |
| perr1940 | 0:d38d627c922f | 50 | unsigned long FSCalc(float stepsPerSec); |
| perr1940 | 0:d38d627c922f | 51 | DigitalOut _CSPin; |
| perr1940 | 0:d38d627c922f | 52 | SPI SPIPin; |
| perr1940 | 0:d38d627c922f | 53 | //Serial pcS; |
| perr1940 | 0:d38d627c922f | 54 | }; |
| perr1940 | 0:d38d627c922f | 55 | |
| perr1940 | 0:d38d627c922f | 56 | #define FWD 0x01 |
| perr1940 | 0:d38d627c922f | 57 | #define REV 0x00 |
| perr1940 | 0:d38d627c922f | 58 | |
| perr1940 | 0:d38d627c922f | 59 | #define BUSY_PIN 0x00 // !BUSY/SYNC pin set to !BUSY mode |
| perr1940 | 0:d38d627c922f | 60 | #define SYNC_PIN 0x80 // pin set to SYNC mode |
| perr1940 | 0:d38d627c922f | 61 | |
| perr1940 | 0:d38d627c922f | 62 | // configStepMode() options: select the microsteps per full step |
| perr1940 | 0:d38d627c922f | 63 | |
| perr1940 | 0:d38d627c922f | 64 | #define STEP_FS 0x00 |
| perr1940 | 0:d38d627c922f | 65 | #define STEP_FS_2 0x01 |
| perr1940 | 0:d38d627c922f | 66 | #define STEP_FS_4 0x02 |
| perr1940 | 0:d38d627c922f | 67 | #define STEP_FS_8 0x03 |
| perr1940 | 0:d38d627c922f | 68 | #define STEP_FS_16 0x04 |
| perr1940 | 0:d38d627c922f | 69 | |
| perr1940 | 0:d38d627c922f | 70 | //cSPIN commands |
| perr1940 | 0:d38d627c922f | 71 | #define NOP 0x00 |
| perr1940 | 0:d38d627c922f | 72 | #define SET_PARAM 0x00 |
| perr1940 | 0:d38d627c922f | 73 | #define GET_PARAM 0x20 |
| perr1940 | 0:d38d627c922f | 74 | #define RUN 0x50 |
| perr1940 | 0:d38d627c922f | 75 | #define STEP_CLOCK 0x58 |
| perr1940 | 0:d38d627c922f | 76 | #define MOVE 0x40 |
| perr1940 | 0:d38d627c922f | 77 | #define GOTO 0x60 |
| perr1940 | 0:d38d627c922f | 78 | #define GOTO_DIR 0x68 |
| perr1940 | 0:d38d627c922f | 79 | #define GO_UNTIL 0x82 |
| perr1940 | 0:d38d627c922f | 80 | #define RELEASE_SW 0x92 |
| perr1940 | 0:d38d627c922f | 81 | #define GO_HOME 0x70 |
| perr1940 | 0:d38d627c922f | 82 | #define GO_MARK 0x78 |
| perr1940 | 0:d38d627c922f | 83 | #define RESET_POS 0xD8 |
| perr1940 | 0:d38d627c922f | 84 | #define RESET_DEVICE 0xC0 |
| perr1940 | 0:d38d627c922f | 85 | #define SOFT_STOP 0xB0 |
| perr1940 | 0:d38d627c922f | 86 | #define HARD_STOP 0xB8 |
| perr1940 | 0:d38d627c922f | 87 | #define SOFT_HIZ 0xA0 |
| perr1940 | 0:d38d627c922f | 88 | #define HARD_HIZ 0xA8 |
| perr1940 | 0:d38d627c922f | 89 | #define GET_STATUS 0xD0 |
| perr1940 | 0:d38d627c922f | 90 | |
| perr1940 | 0:d38d627c922f | 91 | // Register address redefines. |
| perr1940 | 0:d38d627c922f | 92 | // See the Param_Handler() function for more info about these. |
| perr1940 | 0:d38d627c922f | 93 | #define ABS_POS 0x01 |
| perr1940 | 0:d38d627c922f | 94 | #define EL_POS 0x02 |
| perr1940 | 0:d38d627c922f | 95 | #define MARK 0x03 |
| perr1940 | 0:d38d627c922f | 96 | #define SPEED 0x04 |
| perr1940 | 0:d38d627c922f | 97 | #define ACC 0x05 |
| perr1940 | 0:d38d627c922f | 98 | #define DEC 0x06 |
| perr1940 | 0:d38d627c922f | 99 | #define MAX_SPEED 0x07 |
| perr1940 | 0:d38d627c922f | 100 | #define MIN_SPEED 0x08 |
| perr1940 | 0:d38d627c922f | 101 | #define FS_SPD 0x15 |
| perr1940 | 0:d38d627c922f | 102 | #define TVAL_HOLD 0x09 |
| perr1940 | 0:d38d627c922f | 103 | #define TVAL_RUN 0x0A |
| perr1940 | 0:d38d627c922f | 104 | #define TVAL_ACC 0x0B |
| perr1940 | 0:d38d627c922f | 105 | #define TVAL_DEC 0x0C |
| perr1940 | 0:d38d627c922f | 106 | #define RESERVED 0x0D |
| perr1940 | 0:d38d627c922f | 107 | #define T_FAST 0x0E |
| perr1940 | 0:d38d627c922f | 108 | #define TON_MIN 0x0F |
| perr1940 | 0:d38d627c922f | 109 | #define TOFF_MIN 0x10 |
| perr1940 | 0:d38d627c922f | 110 | #define GATECFG1 0x18 |
| perr1940 | 0:d38d627c922f | 111 | #define GATECFG2 0x19 |
| perr1940 | 0:d38d627c922f | 112 | #define ADC_OUT 0x12 |
| perr1940 | 0:d38d627c922f | 113 | #define OCD_TH 0x13 |
| perr1940 | 0:d38d627c922f | 114 | #define STEP_MODE 0x16 |
| perr1940 | 0:d38d627c922f | 115 | #define ALARM_EN 0x17 |
| perr1940 | 0:d38d627c922f | 116 | #define GATECFG1 0x18 |
| perr1940 | 0:d38d627c922f | 117 | #define GATECFG2 0x19 |
| perr1940 | 0:d38d627c922f | 118 | #define CONFIG 0x1A |
| perr1940 | 0:d38d627c922f | 119 | #define STATUS 0x1B |
| perr1940 | 0:d38d627c922f | 120 | |
| perr1940 | 0:d38d627c922f | 121 | // STEP_MODE option values. |
| perr1940 | 0:d38d627c922f | 122 | |
| perr1940 | 0:d38d627c922f | 123 | #define STEP_SEL_1 0x08 |
| perr1940 | 0:d38d627c922f | 124 | #define STEP_SEL_1_2 0x09 |
| perr1940 | 0:d38d627c922f | 125 | #define STEP_SEL_1_4 0x0A |
| perr1940 | 0:d38d627c922f | 126 | #define STEP_SEL_1_8 0x0B |
| perr1940 | 0:d38d627c922f | 127 | #define STEP_SEL_1_16 0x0C |
| perr1940 | 0:d38d627c922f | 128 | |
| perr1940 | 0:d38d627c922f | 129 | |
| perr1940 | 0:d38d627c922f | 130 | // When SYNC_EN is high, the BUSYN pin will instead |
| perr1940 | 0:d38d627c922f | 131 | // output a clock related to the full-step frequency as defined by the |
| perr1940 | 0:d38d627c922f | 132 | // SYNC_SEL bits below. |
| perr1940 | 0:d38d627c922f | 133 | #define BUSYPIN 0x00 |
| perr1940 | 0:d38d627c922f | 134 | #define SYNC_EN 0x80 |
| perr1940 | 0:d38d627c922f | 135 | |
| perr1940 | 0:d38d627c922f | 136 | // The clock output is defined by the full-step frequency |
| perr1940 | 0:d38d627c922f | 137 | // see the datasheet(page 51). |
| perr1940 | 0:d38d627c922f | 138 | #define SYNC_SEL_1_2 0x00 |
| perr1940 | 0:d38d627c922f | 139 | #define SYNC_SEL_1 0x10 |
| perr1940 | 0:d38d627c922f | 140 | #define SYNC_SEL_2 0x20 |
| perr1940 | 0:d38d627c922f | 141 | #define SYNC_SEL_4 0x30 |
| perr1940 | 0:d38d627c922f | 142 | #define SYNC_SEL_8 0x40 |
| perr1940 | 0:d38d627c922f | 143 | |
| perr1940 | 0:d38d627c922f | 144 | #define CONFIG_OSC_SEL 0x000F // Mask for this bit field. |
| perr1940 | 0:d38d627c922f | 145 | #define CONFIG_INT_16MHZ 0x0000 // Internal 16MHz, no output |
| perr1940 | 0:d38d627c922f | 146 | #define CONFIG_INT_16MHZ_OSCOUT_2MHZ 0x0008 // Default; internal 16MHz, 2MHz output |
| perr1940 | 0:d38d627c922f | 147 | #define CONFIG_INT_16MHZ_OSCOUT_4MHZ 0x0009 // Internal 16MHz, 4MHz output |
| perr1940 | 0:d38d627c922f | 148 | #define CONFIG_INT_16MHZ_OSCOUT_8MHZ 0x000A // Internal 16MHz, 8MHz output |
| perr1940 | 0:d38d627c922f | 149 | #define CONFIG_INT_16MHZ_OSCOUT_16MHZ 0x000B // Internal 16MHz, 16MHz output |
| perr1940 | 0:d38d627c922f | 150 | #define CONFIG_EXT_8MHZ_XTAL_DRIVE 0x0004 // External 8MHz crystal |
| perr1940 | 0:d38d627c922f | 151 | #define CONFIG_EXT_16MHZ_XTAL_DRIVE 0x0005 // External 16MHz crystal |
| perr1940 | 0:d38d627c922f | 152 | #define CONFIG_EXT_24MHZ_XTAL_DRIVE 0x0006 // External 24MHz crystal |
| perr1940 | 0:d38d627c922f | 153 | #define CONFIG_EXT_32MHZ_XTAL_DRIVE 0x0007 // External 32MHz crystal |
| perr1940 | 0:d38d627c922f | 154 | #define CONFIG_EXT_8MHZ_OSCOUT_INVERT 0x000C // External 8MHz crystal, output inverted |
| perr1940 | 0:d38d627c922f | 155 | #define CONFIG_EXT_16MHZ_OSCOUT_INVERT 0x000D // External 16MHz crystal, output inverted |
| perr1940 | 0:d38d627c922f | 156 | #define CONFIG_EXT_24MHZ_OSCOUT_INVERT 0x000E // External 24MHz crystal, output inverted |
| perr1940 | 0:d38d627c922f | 157 | #define CONFIG_EXT_32MHZ_OSCOUT_INVERT 0x000F // External 32MHz crystal, output inverted |
| perr1940 | 0:d38d627c922f | 158 | |
| perr1940 | 0:d38d627c922f | 159 | #define CONFIG_SW_HARD_STOP 0x0000 // Default; hard stop motor on switch. |
| perr1940 | 0:d38d627c922f | 160 | #define CONFIG_SW_USER 0x0010 // Tie to the GoUntil and ReleaseSW |
| perr1940 | 0:d38d627c922f | 161 | |
| perr1940 | 0:d38d627c922f | 162 | #define CONFIG_OC_SD_DISABLE 0x0000 // Bridges do NOT shutdown on OC detect |
| perr1940 | 0:d38d627c922f | 163 | #define CONFIG_OC_SD_ENABLE 0x0080 // Bridges shutdown on OC detect |
| perr1940 | 0:d38d627c922f | 164 | |
| perr1940 | 0:d38d627c922f | 165 | #define CONFIG_UVLOVAL_LOW 0x0000 |
| perr1940 | 0:d38d627c922f | 166 | #define CONFIG_UVLOVAL_HIGH 0x0100 |
| perr1940 | 0:d38d627c922f | 167 | |
| perr1940 | 0:d38d627c922f | 168 | #define CONFIG_VCCVAL_LOW 0x0000 |
| perr1940 | 0:d38d627c922f | 169 | #define CONFIG_VCCVAL_HIGH 0x0200 |
| perr1940 | 0:d38d627c922f | 170 | |
| perr1940 | 0:d38d627c922f | 171 | #define CONFIG_EN_TQREG_DISABLE 0x0000 |
| perr1940 | 0:d38d627c922f | 172 | #define CONFIG_EN_TQREG_ENABLE 0x0010 |
| perr1940 | 0:d38d627c922f | 173 | |
| perr1940 | 0:d38d627c922f | 174 | #define CONFIG_TSW_250KHZ 0x0000 |
| perr1940 | 0:d38d627c922f | 175 | #define CONFIG_PRED_EN_DISABLE 0x0000 |
| perr1940 | 0:d38d627c922f | 176 | #define CONFIG_PRED_EN_ENABLE 0x8000 |
| perr1940 | 0:d38d627c922f | 177 | |
| perr1940 | 0:d38d627c922f | 178 | #endif |
| perr1940 | 0:d38d627c922f | 179 | |
| perr1940 | 0:d38d627c922f | 180 |
