mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

Dependents: IR_LED_Send

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h@113:b3775bf36a83, 2016-04-19 (annotated)

Committer:: mbed_official
Date:: Tue Apr 19 11:15:15 2016 +0100
Revision:: 113:b3775bf36a83
Parent:: 0:9b334a45a8ff

Synchronized with git revision 896981126b34b6d9441e3eea77881c67a1ae3dbd

Full URL: https://github.com/mbedmicro/mbed/commit/896981126b34b6d9441e3eea77881c67a1ae3dbd/

Exporter tool addition for e2 studio

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_rcc_ex.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
mbed_official	113:b3775bf36a83	5	* @version V1.5.0
mbed_official	113:b3775bf36a83	6	* @date 8-January-2016
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL Extension module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
mbed_official	113:b3775bf36a83	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L0xx_HAL_RCC_EX_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L0xx_HAL_RCC_EX_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l0xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
mbed_official	113:b3775bf36a83	53	/** @defgroup RCCEx RCCEx
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
mbed_official	113:b3775bf36a83	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
mbed_official	113:b3775bf36a83	59	* @{
mbed_official	113:b3775bf36a83	60	*/
mbed_official	113:b3775bf36a83	61
bogdanm	0:9b334a45a8ff	62	/**
bogdanm	0:9b334a45a8ff	63	* @brief RCC extended clocks structure definition
bogdanm	0:9b334a45a8ff	64	*/
mbed_official	113:b3775bf36a83	65	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	66	typedef struct
bogdanm	0:9b334a45a8ff	67	{
bogdanm	0:9b334a45a8ff	68	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	69	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	70	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	71	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	72
bogdanm	0:9b334a45a8ff	73	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	0:9b334a45a8ff	74	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	0:9b334a45a8ff	75
bogdanm	0:9b334a45a8ff	76	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
mbed_official	113:b3775bf36a83	77	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
bogdanm	0:9b334a45a8ff	78
bogdanm	0:9b334a45a8ff	79	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	80	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	81	#if defined (STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	82	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm	0:9b334a45a8ff	83	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm	0:9b334a45a8ff	84	#endif
bogdanm	0:9b334a45a8ff	85
bogdanm	0:9b334a45a8ff	86	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	87	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	88	#if defined (STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	89	uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
bogdanm	0:9b334a45a8ff	90	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	91	#endif
bogdanm	0:9b334a45a8ff	92
bogdanm	0:9b334a45a8ff	93	uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
bogdanm	0:9b334a45a8ff	94	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	0:9b334a45a8ff	95
bogdanm	0:9b334a45a8ff	96	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
bogdanm	0:9b334a45a8ff	97	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
bogdanm	0:9b334a45a8ff	98
bogdanm	0:9b334a45a8ff	99	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	100
bogdanm	0:9b334a45a8ff	101
mbed_official	113:b3775bf36a83	102	#else /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	typedef struct
bogdanm	0:9b334a45a8ff	105	{
bogdanm	0:9b334a45a8ff	106	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	107	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	113:b3775bf36a83	108	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx)
bogdanm	0:9b334a45a8ff	109	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	110	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	111	#endif
bogdanm	0:9b334a45a8ff	112	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	0:9b334a45a8ff	113	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	0:9b334a45a8ff	114
bogdanm	0:9b334a45a8ff	115	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
bogdanm	0:9b334a45a8ff	116	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
bogdanm	0:9b334a45a8ff	117
bogdanm	0:9b334a45a8ff	118	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	119	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	120
bogdanm	0:9b334a45a8ff	121	#if defined (STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	122	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm	0:9b334a45a8ff	123	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm	0:9b334a45a8ff	124	#endif
bogdanm	0:9b334a45a8ff	125
bogdanm	0:9b334a45a8ff	126	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	127	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	128
bogdanm	0:9b334a45a8ff	129	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
bogdanm	0:9b334a45a8ff	130	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	133
mbed_official	113:b3775bf36a83	134	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	135
mbed_official	113:b3775bf36a83	136	/**
mbed_official	113:b3775bf36a83	137	* @}
mbed_official	113:b3775bf36a83	138	*/
bogdanm	0:9b334a45a8ff	139
mbed_official	113:b3775bf36a83	140	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
mbed_official	113:b3775bf36a83	141	* @{
mbed_official	113:b3775bf36a83	142	*/
mbed_official	113:b3775bf36a83	143	/**
mbed_official	113:b3775bf36a83	144	* @}
mbed_official	113:b3775bf36a83	145	*/
mbed_official	113:b3775bf36a83	146
mbed_official	113:b3775bf36a83	147	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	148
mbed_official	113:b3775bf36a83	149	/** @addtogroup RCCEx_Exported_Constants
bogdanm	0:9b334a45a8ff	150	* @{
bogdanm	0:9b334a45a8ff	151	*/
bogdanm	0:9b334a45a8ff	152	/**
bogdanm	0:9b334a45a8ff	153	* @brief RCC CRS Status definition
bogdanm	0:9b334a45a8ff	154	*/
bogdanm	0:9b334a45a8ff	155
bogdanm	0:9b334a45a8ff	156	#define RCC_CRS_NONE ((uint32_t) 0x00000000)
bogdanm	0:9b334a45a8ff	157	#define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001)
bogdanm	0:9b334a45a8ff	158	#define RCC_CRS_SYNCOK ((uint32_t) 0x00000002)
bogdanm	0:9b334a45a8ff	159	#define RCC_CRS_SYNCWARM ((uint32_t) 0x00000004)
bogdanm	0:9b334a45a8ff	160	#define RCC_CRS_SYNCERR ((uint32_t) 0x00000008)
bogdanm	0:9b334a45a8ff	161	#define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010)
bogdanm	0:9b334a45a8ff	162	#define RCC_CRS_TRIMOV ((uint32_t) 0x00000020)
bogdanm	0:9b334a45a8ff	163
bogdanm	0:9b334a45a8ff	164	/**
bogdanm	0:9b334a45a8ff	165	* @}
bogdanm	0:9b334a45a8ff	166	*/
mbed_official	113:b3775bf36a83	167
mbed_official	113:b3775bf36a83	168	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
mbed_official	113:b3775bf36a83	169	* @{
mbed_official	113:b3775bf36a83	170	*/
bogdanm	0:9b334a45a8ff	171	/**
bogdanm	0:9b334a45a8ff	172	* @brief RCC_CRS Init structure definition
bogdanm	0:9b334a45a8ff	173	*/
bogdanm	0:9b334a45a8ff	174	typedef struct
bogdanm	0:9b334a45a8ff	175	{
bogdanm	0:9b334a45a8ff	176	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
bogdanm	0:9b334a45a8ff	177	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
bogdanm	0:9b334a45a8ff	178
bogdanm	0:9b334a45a8ff	179	uint32_t Source; /*!< Specifies the SYNC signal source.
bogdanm	0:9b334a45a8ff	180	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
bogdanm	0:9b334a45a8ff	181
bogdanm	0:9b334a45a8ff	182	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
bogdanm	0:9b334a45a8ff	183	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
bogdanm	0:9b334a45a8ff	184
bogdanm	0:9b334a45a8ff	185	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
bogdanm	0:9b334a45a8ff	186	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
bogdanm	0:9b334a45a8ff	187	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
bogdanm	0:9b334a45a8ff	188
bogdanm	0:9b334a45a8ff	189	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
bogdanm	0:9b334a45a8ff	190	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
bogdanm	0:9b334a45a8ff	191
bogdanm	0:9b334a45a8ff	192	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
bogdanm	0:9b334a45a8ff	193	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
bogdanm	0:9b334a45a8ff	194
bogdanm	0:9b334a45a8ff	195	}RCC_CRSInitTypeDef;
bogdanm	0:9b334a45a8ff	196
bogdanm	0:9b334a45a8ff	197	/**
bogdanm	0:9b334a45a8ff	198	* @brief RCC_CRS Synchronization structure definition
bogdanm	0:9b334a45a8ff	199	*/
bogdanm	0:9b334a45a8ff	200	typedef struct
bogdanm	0:9b334a45a8ff	201	{
bogdanm	0:9b334a45a8ff	202	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
bogdanm	0:9b334a45a8ff	203	This parameter must be a number between 0 and 0xFFFF*/
bogdanm	0:9b334a45a8ff	204
bogdanm	0:9b334a45a8ff	205	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
bogdanm	0:9b334a45a8ff	206	This parameter must be a number between 0 and 0x3F */
bogdanm	0:9b334a45a8ff	207
bogdanm	0:9b334a45a8ff	208	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
bogdanm	0:9b334a45a8ff	209	value latched in the time of the last SYNC event.
bogdanm	0:9b334a45a8ff	210	This parameter must be a number between 0 and 0xFFFF */
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
bogdanm	0:9b334a45a8ff	213	frequency error counter latched in the time of the last SYNC event.
bogdanm	0:9b334a45a8ff	214	It shows whether the actual frequency is below or above the target.
bogdanm	0:9b334a45a8ff	215	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
bogdanm	0:9b334a45a8ff	216
bogdanm	0:9b334a45a8ff	217	}RCC_CRSSynchroInfoTypeDef;
mbed_official	113:b3775bf36a83	218
mbed_official	113:b3775bf36a83	219	/**
mbed_official	113:b3775bf36a83	220	* @}
mbed_official	113:b3775bf36a83	221	*/
mbed_official	113:b3775bf36a83	222
mbed_official	113:b3775bf36a83	223	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	224
bogdanm	0:9b334a45a8ff	225	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	226	/** @addtogroup RCCEx_Exported_Constants
bogdanm	0:9b334a45a8ff	227	* @{
bogdanm	0:9b334a45a8ff	228	*/
bogdanm	0:9b334a45a8ff	229
mbed_official	113:b3775bf36a83	230	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
bogdanm	0:9b334a45a8ff	231	* @{
bogdanm	0:9b334a45a8ff	232	*/
mbed_official	113:b3775bf36a83	233	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	236	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	237	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	238	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	239	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	240	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	241	#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	242	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	243	#if defined (STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	244	#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	245	#endif
bogdanm	0:9b334a45a8ff	246	#if defined (STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	247	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	248	#endif
bogdanm	0:9b334a45a8ff	249
bogdanm	0:9b334a45a8ff	250
mbed_official	113:b3775bf36a83	251	#else /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	252
mbed_official	113:b3775bf36a83	253	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
bogdanm	0:9b334a45a8ff	254	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	255	#endif
bogdanm	0:9b334a45a8ff	256	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	257	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	258	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
mbed_official	113:b3775bf36a83	259	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
bogdanm	0:9b334a45a8ff	260	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	261	#endif
bogdanm	0:9b334a45a8ff	262	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	263	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	264	#if defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	265	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	266	#endif
bogdanm	0:9b334a45a8ff	267
mbed_official	113:b3775bf36a83	268	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	269	/**
bogdanm	0:9b334a45a8ff	270	* @}
bogdanm	0:9b334a45a8ff	271	*/
bogdanm	0:9b334a45a8ff	272
mbed_official	113:b3775bf36a83	273	/** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source
bogdanm	0:9b334a45a8ff	274	* @{
bogdanm	0:9b334a45a8ff	275	*/
bogdanm	0:9b334a45a8ff	276	#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	277	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
bogdanm	0:9b334a45a8ff	278	#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
bogdanm	0:9b334a45a8ff	279	#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 \| RCC_CCIPR_USART1SEL_1)
mbed_official	113:b3775bf36a83	280
bogdanm	0:9b334a45a8ff	281	/**
bogdanm	0:9b334a45a8ff	282	* @}
bogdanm	0:9b334a45a8ff	283	*/
bogdanm	0:9b334a45a8ff	284
mbed_official	113:b3775bf36a83	285	/** @defgroup RCCEx_USART2_Clock_Source RCC USART2 Clock Source
bogdanm	0:9b334a45a8ff	286	* @{
bogdanm	0:9b334a45a8ff	287	*/
bogdanm	0:9b334a45a8ff	288	#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	289	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
bogdanm	0:9b334a45a8ff	290	#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
bogdanm	0:9b334a45a8ff	291	#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 \| RCC_CCIPR_USART2SEL_1)
mbed_official	113:b3775bf36a83	292
bogdanm	0:9b334a45a8ff	293	/**
bogdanm	0:9b334a45a8ff	294	* @}
bogdanm	0:9b334a45a8ff	295	*/
bogdanm	0:9b334a45a8ff	296
mbed_official	113:b3775bf36a83	297	/** @defgroup RCCEx_LPUART1_Clock_Source RCC LPUART Clock Source
bogdanm	0:9b334a45a8ff	298	* @{
bogdanm	0:9b334a45a8ff	299	*/
bogdanm	0:9b334a45a8ff	300	#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	301	#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
bogdanm	0:9b334a45a8ff	302	#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
bogdanm	0:9b334a45a8ff	303	#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 \| RCC_CCIPR_LPUART1SEL_1)
mbed_official	113:b3775bf36a83	304
bogdanm	0:9b334a45a8ff	305	/**
bogdanm	0:9b334a45a8ff	306	* @}
bogdanm	0:9b334a45a8ff	307	*/
bogdanm	0:9b334a45a8ff	308
mbed_official	113:b3775bf36a83	309	/** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source
bogdanm	0:9b334a45a8ff	310	* @{
bogdanm	0:9b334a45a8ff	311	*/
bogdanm	0:9b334a45a8ff	312	#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	313	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
bogdanm	0:9b334a45a8ff	314	#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
mbed_official	113:b3775bf36a83	315
bogdanm	0:9b334a45a8ff	316	/**
bogdanm	0:9b334a45a8ff	317	* @}
bogdanm	0:9b334a45a8ff	318	*/
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	#if defined(STM32L071xx) \|\| defined(STM32L072xx) \|\| defined(STM32L073xx)\|\| defined(STM32L081xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	321
mbed_official	113:b3775bf36a83	322	/** @defgroup RCCEx_I2C3_Clock_Source RCC I2C3 Clock Source
bogdanm	0:9b334a45a8ff	323	* @{
bogdanm	0:9b334a45a8ff	324	*/
bogdanm	0:9b334a45a8ff	325	#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	326	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
bogdanm	0:9b334a45a8ff	327	#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	/**
bogdanm	0:9b334a45a8ff	330	* @}
bogdanm	0:9b334a45a8ff	331	*/
mbed_official	113:b3775bf36a83	332	#endif /* defined(STM32L071xx) \|\| defined(STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L081xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) */
bogdanm	0:9b334a45a8ff	333
mbed_official	113:b3775bf36a83	334
mbed_official	113:b3775bf36a83	335
mbed_official	113:b3775bf36a83	336	/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM Prescaler Selection
bogdanm	0:9b334a45a8ff	337	* @{
bogdanm	0:9b334a45a8ff	338	*/
bogdanm	0:9b334a45a8ff	339	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	340	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	341	/**
bogdanm	0:9b334a45a8ff	342	* @}
bogdanm	0:9b334a45a8ff	343	*/
bogdanm	0:9b334a45a8ff	344
mbed_official	113:b3775bf36a83	345	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	346	/** @defgroup RCCEx_USB_Clock_Source RCC USB Clock Source
bogdanm	0:9b334a45a8ff	347	* @{
bogdanm	0:9b334a45a8ff	348	*/
bogdanm	0:9b334a45a8ff	349	#define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
mbed_official	113:b3775bf36a83	350	#define RCC_USBCLKSOURCE_PLL ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352	/**
bogdanm	0:9b334a45a8ff	353	* @}
bogdanm	0:9b334a45a8ff	354	*/
bogdanm	0:9b334a45a8ff	355
mbed_official	113:b3775bf36a83	356	/** @defgroup RCCEx_RNG_Clock_Source RCC RNG Clock Source
bogdanm	0:9b334a45a8ff	357	* @{
bogdanm	0:9b334a45a8ff	358	*/
bogdanm	0:9b334a45a8ff	359	#define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
bogdanm	0:9b334a45a8ff	360	#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	361
bogdanm	0:9b334a45a8ff	362	/**
bogdanm	0:9b334a45a8ff	363	* @}
bogdanm	0:9b334a45a8ff	364	*/
bogdanm	0:9b334a45a8ff	365
mbed_official	113:b3775bf36a83	366	/** @defgroup RCCEx_HSI48M_Clock_Source RCC HSI48M Clock Source
bogdanm	0:9b334a45a8ff	367	* @{
bogdanm	0:9b334a45a8ff	368	*/
bogdanm	0:9b334a45a8ff	369	#define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	#define RCC_HSI48M_PLL ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	372	#define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
bogdanm	0:9b334a45a8ff	373
bogdanm	0:9b334a45a8ff	374
bogdanm	0:9b334a45a8ff	375	/**
bogdanm	0:9b334a45a8ff	376	* @}
bogdanm	0:9b334a45a8ff	377	*/
mbed_official	113:b3775bf36a83	378	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	379
mbed_official	113:b3775bf36a83	380	/** @defgroup RCC_HSI_Config RCC HSI Configuration
bogdanm	0:9b334a45a8ff	381	* @{
bogdanm	0:9b334a45a8ff	382	*/
bogdanm	0:9b334a45a8ff	383	#define RCC_HSI_OFF ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	384	#define RCC_HSI_ON RCC_CR_HSION
bogdanm	0:9b334a45a8ff	385	#define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN \| RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	386	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	387	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	388	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	389	#define RCC_HSI_OUTEN RCC_CR_HSIOUTEN
bogdanm	0:9b334a45a8ff	390	#endif
bogdanm	0:9b334a45a8ff	391
bogdanm	0:9b334a45a8ff	392	/**
bogdanm	0:9b334a45a8ff	393	* @}
bogdanm	0:9b334a45a8ff	394	*/
bogdanm	0:9b334a45a8ff	395
mbed_official	113:b3775bf36a83	396	/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
bogdanm	0:9b334a45a8ff	397	* @{
bogdanm	0:9b334a45a8ff	398	*/
bogdanm	0:9b334a45a8ff	399	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	400	#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
bogdanm	0:9b334a45a8ff	401	#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
bogdanm	0:9b334a45a8ff	402	#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
bogdanm	0:9b334a45a8ff	403
bogdanm	0:9b334a45a8ff	404	/**
bogdanm	0:9b334a45a8ff	405	* @}
bogdanm	0:9b334a45a8ff	406	*/
bogdanm	0:9b334a45a8ff	407
mbed_official	113:b3775bf36a83	408	/** @defgroup RCCEx_StopWakeUp_Clock RCC StopWakeUp Clock
bogdanm	0:9b334a45a8ff	409	* @{
bogdanm	0:9b334a45a8ff	410	*/
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00)
bogdanm	0:9b334a45a8ff	413	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	/**
bogdanm	0:9b334a45a8ff	416	* @}
bogdanm	0:9b334a45a8ff	417	*/
bogdanm	0:9b334a45a8ff	418
mbed_official	113:b3775bf36a83	419	/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
bogdanm	0:9b334a45a8ff	420	* @{
bogdanm	0:9b334a45a8ff	421	*/
bogdanm	0:9b334a45a8ff	422
bogdanm	0:9b334a45a8ff	423	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	424	#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
bogdanm	0:9b334a45a8ff	425	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
bogdanm	0:9b334a45a8ff	426	#define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
mbed_official	113:b3775bf36a83	427
bogdanm	0:9b334a45a8ff	428	/**
bogdanm	0:9b334a45a8ff	429	* @}
bogdanm	0:9b334a45a8ff	430	*/
bogdanm	0:9b334a45a8ff	431
mbed_official	113:b3775bf36a83	432	/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
mbed_official	113:b3775bf36a83	433	* @{
mbed_official	113:b3775bf36a83	434	*/
mbed_official	113:b3775bf36a83	435	#define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /!< External interrupt line 19 connected to the LSE CSS EXTI Line /
mbed_official	113:b3775bf36a83	436	/**
mbed_official	113:b3775bf36a83	437	* @}
mbed_official	113:b3775bf36a83	438	*/
mbed_official	113:b3775bf36a83	439
mbed_official	113:b3775bf36a83	440	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	441	/** @defgroup RCCEx_CRS_SynchroSource RCC CRS Synchro Source
bogdanm	0:9b334a45a8ff	442	* @{
bogdanm	0:9b334a45a8ff	443	*/
bogdanm	0:9b334a45a8ff	444	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal source GPIO /
bogdanm	0:9b334a45a8ff	445	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
bogdanm	0:9b334a45a8ff	446	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	/**
bogdanm	0:9b334a45a8ff	449	* @}
bogdanm	0:9b334a45a8ff	450	*/
bogdanm	0:9b334a45a8ff	451
mbed_official	113:b3775bf36a83	452	/** @defgroup RCCEx_CRS_SynchroDivider RCC CRS Synchro Divider
bogdanm	0:9b334a45a8ff	453	* @{
bogdanm	0:9b334a45a8ff	454	*/
bogdanm	0:9b334a45a8ff	455	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
bogdanm	0:9b334a45a8ff	456	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
bogdanm	0:9b334a45a8ff	457	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
bogdanm	0:9b334a45a8ff	458	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
bogdanm	0:9b334a45a8ff	459	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
bogdanm	0:9b334a45a8ff	460	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
bogdanm	0:9b334a45a8ff	461	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
bogdanm	0:9b334a45a8ff	462	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
bogdanm	0:9b334a45a8ff	463
bogdanm	0:9b334a45a8ff	464	/**
bogdanm	0:9b334a45a8ff	465	* @}
bogdanm	0:9b334a45a8ff	466	*/
bogdanm	0:9b334a45a8ff	467
mbed_official	113:b3775bf36a83	468	/** @defgroup RCCEx_CRS_SynchroPolarity RCC CRS Synchro Polarity
bogdanm	0:9b334a45a8ff	469	* @{
bogdanm	0:9b334a45a8ff	470	*/
bogdanm	0:9b334a45a8ff	471	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
bogdanm	0:9b334a45a8ff	472	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
bogdanm	0:9b334a45a8ff	473
bogdanm	0:9b334a45a8ff	474	/**
bogdanm	0:9b334a45a8ff	475	* @}
bogdanm	0:9b334a45a8ff	476	*/
bogdanm	0:9b334a45a8ff	477
mbed_official	113:b3775bf36a83	478	/** @defgroup RCCEx_CRS_ReloadValueDefault RCC CRS Reload Default Value
bogdanm	0:9b334a45a8ff	479	* @{
bogdanm	0:9b334a45a8ff	480	*/
bogdanm	0:9b334a45a8ff	481	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
bogdanm	0:9b334a45a8ff	482	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	/**
bogdanm	0:9b334a45a8ff	485	* @}
bogdanm	0:9b334a45a8ff	486	*/
bogdanm	0:9b334a45a8ff	487
mbed_official	113:b3775bf36a83	488	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCC CRS Error Limit Default
bogdanm	0:9b334a45a8ff	489	* @{
bogdanm	0:9b334a45a8ff	490	*/
bogdanm	0:9b334a45a8ff	491	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	/**
bogdanm	0:9b334a45a8ff	494	* @}
bogdanm	0:9b334a45a8ff	495	*/
bogdanm	0:9b334a45a8ff	496
mbed_official	113:b3775bf36a83	497	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCC CRS HSI48 Calibration Default
bogdanm	0:9b334a45a8ff	498	* @{
bogdanm	0:9b334a45a8ff	499	*/
bogdanm	0:9b334a45a8ff	500	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
bogdanm	0:9b334a45a8ff	501	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
bogdanm	0:9b334a45a8ff	502	corresponds to a higher output frequency */
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504	/**
bogdanm	0:9b334a45a8ff	505	* @}
bogdanm	0:9b334a45a8ff	506	*/
bogdanm	0:9b334a45a8ff	507
mbed_official	113:b3775bf36a83	508	/** @defgroup RCCEx_CRS_FreqErrorDirection RCC CRS Frequency Error Direction
bogdanm	0:9b334a45a8ff	509	* @{
bogdanm	0:9b334a45a8ff	510	*/
bogdanm	0:9b334a45a8ff	511	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
bogdanm	0:9b334a45a8ff	512	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
bogdanm	0:9b334a45a8ff	513
bogdanm	0:9b334a45a8ff	514	/**
bogdanm	0:9b334a45a8ff	515	* @}
bogdanm	0:9b334a45a8ff	516	*/
bogdanm	0:9b334a45a8ff	517
mbed_official	113:b3775bf36a83	518	/** @defgroup RCCEx_CRS_Interrupt_Sources RCC CRS Interrupt Sources
bogdanm	0:9b334a45a8ff	519	* @{
bogdanm	0:9b334a45a8ff	520	*/
bogdanm	0:9b334a45a8ff	521	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
bogdanm	0:9b334a45a8ff	522	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
bogdanm	0:9b334a45a8ff	523	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
bogdanm	0:9b334a45a8ff	524	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
bogdanm	0:9b334a45a8ff	525	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	0:9b334a45a8ff	526	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	0:9b334a45a8ff	527	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	/**
bogdanm	0:9b334a45a8ff	530	* @}
bogdanm	0:9b334a45a8ff	531	*/
bogdanm	0:9b334a45a8ff	532
mbed_official	113:b3775bf36a83	533	/** @defgroup RCCEx_CRS_Flags RCC CRS Flags
bogdanm	0:9b334a45a8ff	534	* @{
bogdanm	0:9b334a45a8ff	535	*/
bogdanm	0:9b334a45a8ff	536	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
bogdanm	0:9b334a45a8ff	537	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
bogdanm	0:9b334a45a8ff	538	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
bogdanm	0:9b334a45a8ff	539	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
bogdanm	0:9b334a45a8ff	540	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	0:9b334a45a8ff	541	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	0:9b334a45a8ff	542	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	/**
bogdanm	0:9b334a45a8ff	545	* @}
bogdanm	0:9b334a45a8ff	546	*/
bogdanm	0:9b334a45a8ff	547
mbed_official	113:b3775bf36a83	548	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	549	/**
bogdanm	0:9b334a45a8ff	550	* @}
bogdanm	0:9b334a45a8ff	551	*/
bogdanm	0:9b334a45a8ff	552
bogdanm	0:9b334a45a8ff	553	/* Exported macro ------------------------------------------------------------*/
mbed_official	113:b3775bf36a83	554	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
bogdanm	0:9b334a45a8ff	555	* @{
bogdanm	0:9b334a45a8ff	556	*/
mbed_official	113:b3775bf36a83	557	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
mbed_official	113:b3775bf36a83	558	* @brief Enable or disable the AHB peripheral clock.
bogdanm	0:9b334a45a8ff	559	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	560	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	561	* using it.
mbed_official	113:b3775bf36a83	562	* @{
bogdanm	0:9b334a45a8ff	563	*/
bogdanm	0:9b334a45a8ff	564
mbed_official	113:b3775bf36a83	565	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) \|\| defined(STM32L041xx) \|\| defined(STM32L021xx)
mbed_official	113:b3775bf36a83	566	#define __HAL_RCC_AES_CLK_ENABLE() SET_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
mbed_official	113:b3775bf36a83	567	#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
mbed_official	113:b3775bf36a83	568	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx \|\| STM32L041xx \|\| STM32L021xx */
mbed_official	113:b3775bf36a83	569
mbed_official	113:b3775bf36a83	570	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	571	#define __HAL_RCC_TSC_CLK_ENABLE() SET_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
mbed_official	113:b3775bf36a83	572	#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
mbed_official	113:b3775bf36a83	573
mbed_official	113:b3775bf36a83	574	#define __HAL_RCC_RNG_CLK_ENABLE() SET_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
mbed_official	113:b3775bf36a83	575	#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
mbed_official	113:b3775bf36a83	576	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	113:b3775bf36a83	577
mbed_official	113:b3775bf36a83	578
mbed_official	113:b3775bf36a83	579	/**
mbed_official	113:b3775bf36a83	580	* @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
mbed_official	113:b3775bf36a83	581	* @retval None
mbed_official	113:b3775bf36a83	582	*/
mbed_official	113:b3775bf36a83	583	#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
mbed_official	113:b3775bf36a83	584
mbed_official	113:b3775bf36a83	585	/**
mbed_official	113:b3775bf36a83	586	* @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
mbed_official	113:b3775bf36a83	587	* @retval None
mbed_official	113:b3775bf36a83	588	*/
mbed_official	113:b3775bf36a83	589	#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
bogdanm	0:9b334a45a8ff	590
mbed_official	113:b3775bf36a83	591	/**
mbed_official	113:b3775bf36a83	592	* @brief Enable event on RCC LSE CSS EXTI Line 19.
mbed_official	113:b3775bf36a83	593	* @retval None.
mbed_official	113:b3775bf36a83	594	*/
mbed_official	113:b3775bf36a83	595	#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
mbed_official	113:b3775bf36a83	596
mbed_official	113:b3775bf36a83	597	/**
mbed_official	113:b3775bf36a83	598	* @brief Disable event on RCC LSE CSS EXTI Line 19.
mbed_official	113:b3775bf36a83	599	* @retval None.
mbed_official	113:b3775bf36a83	600	*/
mbed_official	113:b3775bf36a83	601	#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
mbed_official	113:b3775bf36a83	602
bogdanm	0:9b334a45a8ff	603
mbed_official	113:b3775bf36a83	604	/**
mbed_official	113:b3775bf36a83	605	* @brief RCC LSE CSS EXTI line configuration: set falling edge trigger.
mbed_official	113:b3775bf36a83	606	* @retval None.
mbed_official	113:b3775bf36a83	607	*/
mbed_official	113:b3775bf36a83	608	#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
mbed_official	113:b3775bf36a83	609
mbed_official	113:b3775bf36a83	610
mbed_official	113:b3775bf36a83	611	/**
mbed_official	113:b3775bf36a83	612	* @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
mbed_official	113:b3775bf36a83	613	* @retval None.
mbed_official	113:b3775bf36a83	614	*/
mbed_official	113:b3775bf36a83	615	#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
bogdanm	0:9b334a45a8ff	616
bogdanm	0:9b334a45a8ff	617
mbed_official	113:b3775bf36a83	618	/**
mbed_official	113:b3775bf36a83	619	* @brief RCC LSE CSS EXTI line configuration: set rising edge trigger.
mbed_official	113:b3775bf36a83	620	* @retval None.
mbed_official	113:b3775bf36a83	621	*/
mbed_official	113:b3775bf36a83	622	#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
mbed_official	113:b3775bf36a83	623
mbed_official	113:b3775bf36a83	624	/**
mbed_official	113:b3775bf36a83	625	* @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
mbed_official	113:b3775bf36a83	626	* @retval None.
mbed_official	113:b3775bf36a83	627	*/
mbed_official	113:b3775bf36a83	628	#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
mbed_official	113:b3775bf36a83	629
mbed_official	113:b3775bf36a83	630	/**
mbed_official	113:b3775bf36a83	631	* @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
mbed_official	113:b3775bf36a83	632	* @retval None.
mbed_official	113:b3775bf36a83	633	*/
mbed_official	113:b3775bf36a83	634	#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
mbed_official	113:b3775bf36a83	635	do { \
mbed_official	113:b3775bf36a83	636	__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
mbed_official	113:b3775bf36a83	637	__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
mbed_official	113:b3775bf36a83	638	} while(0)
mbed_official	113:b3775bf36a83	639
mbed_official	113:b3775bf36a83	640	/**
mbed_official	113:b3775bf36a83	641	* @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
mbed_official	113:b3775bf36a83	642	* @retval None.
mbed_official	113:b3775bf36a83	643	*/
mbed_official	113:b3775bf36a83	644	#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
mbed_official	113:b3775bf36a83	645	do { \
mbed_official	113:b3775bf36a83	646	__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
mbed_official	113:b3775bf36a83	647	__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
mbed_official	113:b3775bf36a83	648	} while(0)
mbed_official	113:b3775bf36a83	649
mbed_official	113:b3775bf36a83	650	/**
mbed_official	113:b3775bf36a83	651	* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
mbed_official	113:b3775bf36a83	652	* @retval EXTI RCC LSE CSS Line Status.
mbed_official	113:b3775bf36a83	653	*/
mbed_official	113:b3775bf36a83	654	#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
mbed_official	113:b3775bf36a83	655
mbed_official	113:b3775bf36a83	656	/**
mbed_official	113:b3775bf36a83	657	* @brief Clear the RCC LSE CSS EXTI flag.
mbed_official	113:b3775bf36a83	658	* @retval None.
mbed_official	113:b3775bf36a83	659	*/
mbed_official	113:b3775bf36a83	660	#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
mbed_official	113:b3775bf36a83	661
mbed_official	113:b3775bf36a83	662	/**
mbed_official	113:b3775bf36a83	663	* @brief Generate a Software interrupt on selected EXTI line.
mbed_official	113:b3775bf36a83	664	* @retval None.
mbed_official	113:b3775bf36a83	665	*/
mbed_official	113:b3775bf36a83	666	#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
mbed_official	113:b3775bf36a83	667
mbed_official	113:b3775bf36a83	668
mbed_official	113:b3775bf36a83	669
mbed_official	113:b3775bf36a83	670	/**
mbed_official	113:b3775bf36a83	671	* @}
mbed_official	113:b3775bf36a83	672	*/
mbed_official	113:b3775bf36a83	673
mbed_official	113:b3775bf36a83	674	/** @defgroup RCCEx_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
mbed_official	113:b3775bf36a83	675	* @brief Enable or disable the IOPORT peripheral clock.
mbed_official	113:b3775bf36a83	676	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	113:b3775bf36a83	677	* is disabled and the application software has to enable this clock before
mbed_official	113:b3775bf36a83	678	* using it.
mbed_official	113:b3775bf36a83	679	* @{
mbed_official	113:b3775bf36a83	680	*/
bogdanm	0:9b334a45a8ff	681	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	682	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	683	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	684	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	685	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	686	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
bogdanm	0:9b334a45a8ff	687	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	688	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
bogdanm	0:9b334a45a8ff	689	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	690	} while(0)
bogdanm	0:9b334a45a8ff	691
mbed_official	113:b3775bf36a83	692	#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN))
bogdanm	0:9b334a45a8ff	693
bogdanm	0:9b334a45a8ff	694	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	695	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	696	/* STM32L073xx \|\| STM32L083xx */
mbed_official	113:b3775bf36a83	697	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
mbed_official	113:b3775bf36a83	698	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
mbed_official	113:b3775bf36a83	699	__IO uint32_t tmpreg; \
mbed_official	113:b3775bf36a83	700	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
mbed_official	113:b3775bf36a83	701	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	113:b3775bf36a83	702	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
mbed_official	113:b3775bf36a83	703	UNUSED(tmpreg); \
mbed_official	113:b3775bf36a83	704	} while(0)
mbed_official	113:b3775bf36a83	705	#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN))
mbed_official	113:b3775bf36a83	706	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
mbed_official	113:b3775bf36a83	707	/**
mbed_official	113:b3775bf36a83	708	* @}
mbed_official	113:b3775bf36a83	709	*/
bogdanm	0:9b334a45a8ff	710
mbed_official	113:b3775bf36a83	711	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
mbed_official	113:b3775bf36a83	712	* @brief Enable or disable the APB1 peripheral clock.
bogdanm	0:9b334a45a8ff	713	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	714	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	715	* using it.
mbed_official	113:b3775bf36a83	716	* @{
bogdanm	0:9b334a45a8ff	717	*/
bogdanm	0:9b334a45a8ff	718
mbed_official	113:b3775bf36a83	719	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	720	#define __HAL_RCC_USB_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
mbed_official	113:b3775bf36a83	721	#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
bogdanm	0:9b334a45a8ff	722
mbed_official	113:b3775bf36a83	723	#define __HAL_RCC_CRS_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN))
mbed_official	113:b3775bf36a83	724	#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN))
mbed_official	113:b3775bf36a83	725	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727
bogdanm	0:9b334a45a8ff	728	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
mbed_official	113:b3775bf36a83	729	#define __HAL_RCC_LCD_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
mbed_official	113:b3775bf36a83	730	#define __HAL_RCC_LCD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
bogdanm	0:9b334a45a8ff	731	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	732
bogdanm	0:9b334a45a8ff	733	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	0:9b334a45a8ff	734	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	0:9b334a45a8ff	735	defined(STM32L051xx) \|\| defined(STM32L061xx)
mbed_official	113:b3775bf36a83	736	#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
mbed_official	113:b3775bf36a83	737	#define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
mbed_official	113:b3775bf36a83	738	#define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
mbed_official	113:b3775bf36a83	739	#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
mbed_official	113:b3775bf36a83	740	#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
mbed_official	113:b3775bf36a83	741	#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
mbed_official	113:b3775bf36a83	742	#define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
mbed_official	113:b3775bf36a83	743	#define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
mbed_official	113:b3775bf36a83	744	#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	745
mbed_official	113:b3775bf36a83	746	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
mbed_official	113:b3775bf36a83	747	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
mbed_official	113:b3775bf36a83	748	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
mbed_official	113:b3775bf36a83	749	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
mbed_official	113:b3775bf36a83	750	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
mbed_official	113:b3775bf36a83	751	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
mbed_official	113:b3775bf36a83	752	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
mbed_official	113:b3775bf36a83	753	#define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
mbed_official	113:b3775bf36a83	754	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	755	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	0:9b334a45a8ff	756	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	0:9b334a45a8ff	757	/* STM32L053xx \|\| STM32L063xx \|\| */
bogdanm	0:9b334a45a8ff	758
mbed_official	113:b3775bf36a83	759	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
mbed_official	113:b3775bf36a83	760	#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
mbed_official	113:b3775bf36a83	761	#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
mbed_official	113:b3775bf36a83	762	#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
mbed_official	113:b3775bf36a83	763	#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
mbed_official	113:b3775bf36a83	764	#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	765
mbed_official	113:b3775bf36a83	766	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
mbed_official	113:b3775bf36a83	767	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
mbed_official	113:b3775bf36a83	768	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
mbed_official	113:b3775bf36a83	769	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
mbed_official	113:b3775bf36a83	770	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
mbed_official	113:b3775bf36a83	771	#endif /* STM32L011xx \|\| STM32L021xx \|\| STM32L031xx \|\| STM32L041xx */
bogdanm	0:9b334a45a8ff	772
bogdanm	0:9b334a45a8ff	773
bogdanm	0:9b334a45a8ff	774	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	775	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	776	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	777	#define __HAL_RCC_TIM2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
mbed_official	113:b3775bf36a83	778	#define __HAL_RCC_TIM3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
mbed_official	113:b3775bf36a83	779	#define __HAL_RCC_TIM6_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
mbed_official	113:b3775bf36a83	780	#define __HAL_RCC_TIM7_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
mbed_official	113:b3775bf36a83	781	#define __HAL_RCC_SPI2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
mbed_official	113:b3775bf36a83	782	#define __HAL_RCC_USART2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
mbed_official	113:b3775bf36a83	783	#define __HAL_RCC_USART4_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
mbed_official	113:b3775bf36a83	784	#define __HAL_RCC_USART5_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
mbed_official	113:b3775bf36a83	785	#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
mbed_official	113:b3775bf36a83	786	#define __HAL_RCC_I2C1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
mbed_official	113:b3775bf36a83	787	#define __HAL_RCC_I2C2_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
mbed_official	113:b3775bf36a83	788	#define __HAL_RCC_I2C3_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
mbed_official	113:b3775bf36a83	789	#define __HAL_RCC_DAC_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
mbed_official	113:b3775bf36a83	790	#define __HAL_RCC_LPTIM1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	791
mbed_official	113:b3775bf36a83	792	#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
mbed_official	113:b3775bf36a83	793	#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
mbed_official	113:b3775bf36a83	794	#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
mbed_official	113:b3775bf36a83	795	#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
mbed_official	113:b3775bf36a83	796	#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
mbed_official	113:b3775bf36a83	797	#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
mbed_official	113:b3775bf36a83	798	#define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
mbed_official	113:b3775bf36a83	799	#define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
mbed_official	113:b3775bf36a83	800	#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
mbed_official	113:b3775bf36a83	801	#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
mbed_official	113:b3775bf36a83	802	#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
mbed_official	113:b3775bf36a83	803	#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
mbed_official	113:b3775bf36a83	804	#define __HAL_RCC_DAC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
mbed_official	113:b3775bf36a83	805	#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	806	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	807	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	808	/* STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	809
bogdanm	0:9b334a45a8ff	810	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	811	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	812	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx) \|\| \
mbed_official	113:b3775bf36a83	813	defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L011xx) \|\| defined(STM32L021xx)
mbed_official	113:b3775bf36a83	814	/**
mbed_official	113:b3775bf36a83	815	* @}
mbed_official	113:b3775bf36a83	816	*/
mbed_official	113:b3775bf36a83	817
mbed_official	113:b3775bf36a83	818	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
mbed_official	113:b3775bf36a83	819	* @brief Enable or disable the APB2 peripheral clock.
bogdanm	0:9b334a45a8ff	820	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	821	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	822	* using it.
mbed_official	113:b3775bf36a83	823	* @{
bogdanm	0:9b334a45a8ff	824	*/
mbed_official	113:b3775bf36a83	825	#define __HAL_RCC_TIM21_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
mbed_official	113:b3775bf36a83	826	#if !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official	113:b3775bf36a83	827	#define __HAL_RCC_TIM22_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
mbed_official	113:b3775bf36a83	828	#endif
mbed_official	113:b3775bf36a83	829	#define __HAL_RCC_ADC1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
mbed_official	113:b3775bf36a83	830	#define __HAL_RCC_SPI1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
mbed_official	113:b3775bf36a83	831	#define __HAL_RCC_USART1_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
bogdanm	0:9b334a45a8ff	832
mbed_official	113:b3775bf36a83	833	#define __HAL_RCC_TIM21_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
mbed_official	113:b3775bf36a83	834	#if !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official	113:b3775bf36a83	835	#define __HAL_RCC_TIM22_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
mbed_official	113:b3775bf36a83	836	#endif
mbed_official	113:b3775bf36a83	837	#define __HAL_RCC_ADC1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
mbed_official	113:b3775bf36a83	838	#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
mbed_official	113:b3775bf36a83	839	#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
mbed_official	113:b3775bf36a83	840	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
mbed_official	113:b3775bf36a83	841	#define __HAL_RCC_FIREWALL_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
mbed_official	113:b3775bf36a83	842	#define __HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
mbed_official	113:b3775bf36a83	843	#endif /* !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */
bogdanm	0:9b334a45a8ff	844	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	845	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	113:b3775bf36a83	846	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	113:b3775bf36a83	847	/* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
mbed_official	113:b3775bf36a83	848
mbed_official	113:b3775bf36a83	849	/**
mbed_official	113:b3775bf36a83	850	* @}
mbed_official	113:b3775bf36a83	851	*/
bogdanm	0:9b334a45a8ff	852
mbed_official	113:b3775bf36a83	853	/** @defgroup RCCEx_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
mbed_official	113:b3775bf36a83	854	* @brief Force or release AHB peripheral reset.
mbed_official	113:b3775bf36a83	855	* @{
mbed_official	113:b3775bf36a83	856	*/
mbed_official	113:b3775bf36a83	857	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) \|\| defined(STM32L041xx) \|\| defined(STM32L021xx)
mbed_official	113:b3775bf36a83	858	#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
mbed_official	113:b3775bf36a83	859	#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
mbed_official	113:b3775bf36a83	860	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx \|\| STM32L041xx \|\| STM32L021xx*/
bogdanm	0:9b334a45a8ff	861
mbed_official	113:b3775bf36a83	862	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	863	#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
mbed_official	113:b3775bf36a83	864	#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
mbed_official	113:b3775bf36a83	865	#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
mbed_official	113:b3775bf36a83	866	#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
mbed_official	113:b3775bf36a83	867	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	113:b3775bf36a83	868
mbed_official	113:b3775bf36a83	869	/**
mbed_official	113:b3775bf36a83	870	* @}
mbed_official	113:b3775bf36a83	871	*/
mbed_official	113:b3775bf36a83	872
mbed_official	113:b3775bf36a83	873	/** @defgroup RCCEx_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
mbed_official	113:b3775bf36a83	874	* @brief Force or release IOPORT peripheral reset.
mbed_official	113:b3775bf36a83	875	* @{
bogdanm	0:9b334a45a8ff	876	*/
bogdanm	0:9b334a45a8ff	877	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	878	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	879	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	880	#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST))
bogdanm	0:9b334a45a8ff	881
mbed_official	113:b3775bf36a83	882	#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST))
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	885	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	886	/* STM32L073xx \|\| STM32L083xx */
mbed_official	113:b3775bf36a83	887	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
mbed_official	113:b3775bf36a83	888	#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST))
mbed_official	113:b3775bf36a83	889	#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST))
mbed_official	113:b3775bf36a83	890	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
mbed_official	113:b3775bf36a83	891	/**
mbed_official	113:b3775bf36a83	892	* @}
mbed_official	113:b3775bf36a83	893	*/
mbed_official	113:b3775bf36a83	894
mbed_official	113:b3775bf36a83	895	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
mbed_official	113:b3775bf36a83	896	* @brief Force or release APB1 peripheral reset.
mbed_official	113:b3775bf36a83	897	* @{
mbed_official	113:b3775bf36a83	898	*/
bogdanm	0:9b334a45a8ff	899
bogdanm	0:9b334a45a8ff	900	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	0:9b334a45a8ff	901	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	0:9b334a45a8ff	902	defined(STM32L051xx) \|\| defined(STM32L061xx)
mbed_official	113:b3775bf36a83	903	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
mbed_official	113:b3775bf36a83	904	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
mbed_official	113:b3775bf36a83	905	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
mbed_official	113:b3775bf36a83	906	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
mbed_official	113:b3775bf36a83	907	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
mbed_official	113:b3775bf36a83	908	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
mbed_official	113:b3775bf36a83	909	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
mbed_official	113:b3775bf36a83	910	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
mbed_official	113:b3775bf36a83	911	#define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	912
mbed_official	113:b3775bf36a83	913	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
mbed_official	113:b3775bf36a83	914	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
mbed_official	113:b3775bf36a83	915	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
mbed_official	113:b3775bf36a83	916	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
mbed_official	113:b3775bf36a83	917	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
mbed_official	113:b3775bf36a83	918	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
mbed_official	113:b3775bf36a83	919	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
mbed_official	113:b3775bf36a83	920	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
mbed_official	113:b3775bf36a83	921	#define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	922	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	0:9b334a45a8ff	923	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	0:9b334a45a8ff	924	/* STM32L053xx \|\| STM32L063xx */
mbed_official	113:b3775bf36a83	925	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
mbed_official	113:b3775bf36a83	926	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
mbed_official	113:b3775bf36a83	927	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
mbed_official	113:b3775bf36a83	928	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
mbed_official	113:b3775bf36a83	929	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
mbed_official	113:b3775bf36a83	930	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
bogdanm	0:9b334a45a8ff	931
mbed_official	113:b3775bf36a83	932	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
mbed_official	113:b3775bf36a83	933	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
mbed_official	113:b3775bf36a83	934	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
mbed_official	113:b3775bf36a83	935	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
mbed_official	113:b3775bf36a83	936	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
mbed_official	113:b3775bf36a83	937	#endif /* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
bogdanm	0:9b334a45a8ff	938
bogdanm	0:9b334a45a8ff	939	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	940	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	941	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	942	#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
mbed_official	113:b3775bf36a83	943	#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
mbed_official	113:b3775bf36a83	944	#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
mbed_official	113:b3775bf36a83	945	#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
mbed_official	113:b3775bf36a83	946	#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
mbed_official	113:b3775bf36a83	947	#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
mbed_official	113:b3775bf36a83	948	#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
mbed_official	113:b3775bf36a83	949	#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
mbed_official	113:b3775bf36a83	950	#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
mbed_official	113:b3775bf36a83	951	#define __HAL_RCC_USART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
mbed_official	113:b3775bf36a83	952	#define __HAL_RCC_USART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
mbed_official	113:b3775bf36a83	953	#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
mbed_official	113:b3775bf36a83	954	#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
mbed_official	113:b3775bf36a83	955	#define __HAL_RCC_DAC_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	956
mbed_official	113:b3775bf36a83	957	#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
mbed_official	113:b3775bf36a83	958	#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
mbed_official	113:b3775bf36a83	959	#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
mbed_official	113:b3775bf36a83	960	#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
mbed_official	113:b3775bf36a83	961	#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
mbed_official	113:b3775bf36a83	962	#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
mbed_official	113:b3775bf36a83	963	#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
mbed_official	113:b3775bf36a83	964	#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
mbed_official	113:b3775bf36a83	965	#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
mbed_official	113:b3775bf36a83	966	#define __HAL_RCC_USART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
mbed_official	113:b3775bf36a83	967	#define __HAL_RCC_USART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
mbed_official	113:b3775bf36a83	968	#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
mbed_official	113:b3775bf36a83	969	#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
mbed_official	113:b3775bf36a83	970	#define __HAL_RCC_DAC_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	971	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	972	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	973	/* STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	0:9b334a45a8ff	974
mbed_official	113:b3775bf36a83	975	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	976	#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
mbed_official	113:b3775bf36a83	977	#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
mbed_official	113:b3775bf36a83	978	#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_CRSRST))
mbed_official	113:b3775bf36a83	979	#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR,(RCC_APB1RSTR_CRSRST))
mbed_official	113:b3775bf36a83	980	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	981
bogdanm	0:9b334a45a8ff	982	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
mbed_official	113:b3775bf36a83	983	#define __HAL_RCC_LCD_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
mbed_official	113:b3775bf36a83	984	#define __HAL_RCC_LCD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
bogdanm	0:9b334a45a8ff	985	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	988	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	113:b3775bf36a83	989	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	990
mbed_official	113:b3775bf36a83	991	/**
mbed_official	113:b3775bf36a83	992	* @}
mbed_official	113:b3775bf36a83	993	*/
mbed_official	113:b3775bf36a83	994
mbed_official	113:b3775bf36a83	995	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
mbed_official	113:b3775bf36a83	996	* @brief Force or release APB2 peripheral reset.
mbed_official	113:b3775bf36a83	997	* @{
bogdanm	0:9b334a45a8ff	998	*/
mbed_official	113:b3775bf36a83	999	#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
mbed_official	113:b3775bf36a83	1000	#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
mbed_official	113:b3775bf36a83	1001	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
mbed_official	113:b3775bf36a83	1002	#define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
mbed_official	113:b3775bf36a83	1003	#if !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official	113:b3775bf36a83	1004	#define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
mbed_official	113:b3775bf36a83	1005	#endif
bogdanm	0:9b334a45a8ff	1006
mbed_official	113:b3775bf36a83	1007	#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
mbed_official	113:b3775bf36a83	1008	#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
mbed_official	113:b3775bf36a83	1009	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
mbed_official	113:b3775bf36a83	1010	#define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
mbed_official	113:b3775bf36a83	1011	#if !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official	113:b3775bf36a83	1012	#define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
mbed_official	113:b3775bf36a83	1013	#endif
bogdanm	0:9b334a45a8ff	1014	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1015	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1016	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	113:b3775bf36a83	1017	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
mbed_official	113:b3775bf36a83	1018	#define __HAL_RCC_ADC1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
mbed_official	113:b3775bf36a83	1019	#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
mbed_official	113:b3775bf36a83	1020	#define __HAL_RCC_TIM21_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
mbed_official	113:b3775bf36a83	1021	#if !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official	113:b3775bf36a83	1022	#define __HAL_RCC_TIM22_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
mbed_official	113:b3775bf36a83	1023	#endif
mbed_official	113:b3775bf36a83	1024	#define __HAL_RCC_ADC1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
mbed_official	113:b3775bf36a83	1025	#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
mbed_official	113:b3775bf36a83	1026	#define __HAL_RCC_TIM21_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
mbed_official	113:b3775bf36a83	1027	#if !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official	113:b3775bf36a83	1028	#define __HAL_RCC_TIM22_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
mbed_official	113:b3775bf36a83	1029	#endif
mbed_official	113:b3775bf36a83	1030	#endif /* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx*/
bogdanm	0:9b334a45a8ff	1031
mbed_official	113:b3775bf36a83	1032
mbed_official	113:b3775bf36a83	1033	/**
mbed_official	113:b3775bf36a83	1034	* @}
mbed_official	113:b3775bf36a83	1035	*/
mbed_official	113:b3775bf36a83	1036
mbed_official	113:b3775bf36a83	1037	/** @defgroup RCCEx_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
mbed_official	113:b3775bf36a83	1038	* @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1039	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1040	* power consumption.
bogdanm	0:9b334a45a8ff	1041	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1042	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	1043	* @{
bogdanm	0:9b334a45a8ff	1044	*/
bogdanm	0:9b334a45a8ff	1045
mbed_official	113:b3775bf36a83	1046	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	1047	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
mbed_official	113:b3775bf36a83	1048	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
mbed_official	113:b3775bf36a83	1049	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
mbed_official	113:b3775bf36a83	1050	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
mbed_official	113:b3775bf36a83	1051	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	1052
mbed_official	113:b3775bf36a83	1053	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) \|\| defined(STM32L041xx)
mbed_official	113:b3775bf36a83	1054	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
mbed_official	113:b3775bf36a83	1055	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
mbed_official	113:b3775bf36a83	1056	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx \|\| STM32L041xx */
bogdanm	0:9b334a45a8ff	1057
mbed_official	113:b3775bf36a83	1058	/**
mbed_official	113:b3775bf36a83	1059	* @}
mbed_official	113:b3775bf36a83	1060	*/
mbed_official	113:b3775bf36a83	1061
mbed_official	113:b3775bf36a83	1062	/** @defgroup RCCEx_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
mbed_official	113:b3775bf36a83	1063	* @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1064	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1065	* power consumption.
bogdanm	0:9b334a45a8ff	1066	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1067	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	1068	* @{
bogdanm	0:9b334a45a8ff	1069	*/
mbed_official	113:b3775bf36a83	1070	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	113:b3775bf36a83	1071	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	113:b3775bf36a83	1072	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	1073	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN))
mbed_official	113:b3775bf36a83	1074	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN))
bogdanm	0:9b334a45a8ff	1075
bogdanm	0:9b334a45a8ff	1076	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1077	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1078	/* STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	113:b3775bf36a83	1079	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
mbed_official	113:b3775bf36a83	1080	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN))
mbed_official	113:b3775bf36a83	1081	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN))
mbed_official	113:b3775bf36a83	1082	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
mbed_official	113:b3775bf36a83	1083	/**
mbed_official	113:b3775bf36a83	1084	* @}
mbed_official	113:b3775bf36a83	1085	*/
bogdanm	0:9b334a45a8ff	1086
mbed_official	113:b3775bf36a83	1087
mbed_official	113:b3775bf36a83	1088	/** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
mbed_official	113:b3775bf36a83	1089	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1090	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1091	* power consumption.
bogdanm	0:9b334a45a8ff	1092	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1093	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	1094	* @{
bogdanm	0:9b334a45a8ff	1095	*/
bogdanm	0:9b334a45a8ff	1096
bogdanm	0:9b334a45a8ff	1097	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	0:9b334a45a8ff	1098	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	0:9b334a45a8ff	1099	defined(STM32L051xx) \|\| defined(STM32L061xx)
mbed_official	113:b3775bf36a83	1100	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
mbed_official	113:b3775bf36a83	1101	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
mbed_official	113:b3775bf36a83	1102	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
mbed_official	113:b3775bf36a83	1103	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
mbed_official	113:b3775bf36a83	1104	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
mbed_official	113:b3775bf36a83	1105	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
mbed_official	113:b3775bf36a83	1106	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
mbed_official	113:b3775bf36a83	1107	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
mbed_official	113:b3775bf36a83	1108	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	0:9b334a45a8ff	1109
mbed_official	113:b3775bf36a83	1110	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
mbed_official	113:b3775bf36a83	1111	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
mbed_official	113:b3775bf36a83	1112	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
mbed_official	113:b3775bf36a83	1113	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
mbed_official	113:b3775bf36a83	1114	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
mbed_official	113:b3775bf36a83	1115	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
mbed_official	113:b3775bf36a83	1116	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
mbed_official	113:b3775bf36a83	1117	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
mbed_official	113:b3775bf36a83	1118	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	0:9b334a45a8ff	1119	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	0:9b334a45a8ff	1120	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	0:9b334a45a8ff	1121	/* STM32L053xx \|\| STM32L063xx */
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	1124	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	1125	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	1126	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
mbed_official	113:b3775bf36a83	1127	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
mbed_official	113:b3775bf36a83	1128	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
mbed_official	113:b3775bf36a83	1129	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
mbed_official	113:b3775bf36a83	1130	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
mbed_official	113:b3775bf36a83	1131	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
mbed_official	113:b3775bf36a83	1132	#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
mbed_official	113:b3775bf36a83	1133	#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
mbed_official	113:b3775bf36a83	1134	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
mbed_official	113:b3775bf36a83	1135	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
mbed_official	113:b3775bf36a83	1136	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
mbed_official	113:b3775bf36a83	1137	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
mbed_official	113:b3775bf36a83	1138	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
mbed_official	113:b3775bf36a83	1139	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	0:9b334a45a8ff	1140
mbed_official	113:b3775bf36a83	1141	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
mbed_official	113:b3775bf36a83	1142	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
mbed_official	113:b3775bf36a83	1143	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
mbed_official	113:b3775bf36a83	1144	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
mbed_official	113:b3775bf36a83	1145	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
mbed_official	113:b3775bf36a83	1146	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
mbed_official	113:b3775bf36a83	1147	#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
mbed_official	113:b3775bf36a83	1148	#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
mbed_official	113:b3775bf36a83	1149	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
mbed_official	113:b3775bf36a83	1150	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
mbed_official	113:b3775bf36a83	1151	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
mbed_official	113:b3775bf36a83	1152	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
mbed_official	113:b3775bf36a83	1153	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
mbed_official	113:b3775bf36a83	1154	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	0:9b334a45a8ff	1155	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1156	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1157	/* STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	113:b3775bf36a83	1158
mbed_official	113:b3775bf36a83	1159	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
mbed_official	113:b3775bf36a83	1160	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
mbed_official	113:b3775bf36a83	1161	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
mbed_official	113:b3775bf36a83	1162	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
mbed_official	113:b3775bf36a83	1163	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
mbed_official	113:b3775bf36a83	1164	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
mbed_official	113:b3775bf36a83	1165
mbed_official	113:b3775bf36a83	1166	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
mbed_official	113:b3775bf36a83	1167	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
mbed_official	113:b3775bf36a83	1168	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
mbed_official	113:b3775bf36a83	1169	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
mbed_official	113:b3775bf36a83	1170	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
mbed_official	113:b3775bf36a83	1171	#endif /* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
mbed_official	113:b3775bf36a83	1172
mbed_official	113:b3775bf36a83	1173	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	113:b3775bf36a83	1174	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
mbed_official	113:b3775bf36a83	1175	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
mbed_official	113:b3775bf36a83	1176	#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
mbed_official	113:b3775bf36a83	1177	#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
mbed_official	113:b3775bf36a83	1178	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	1179
bogdanm	0:9b334a45a8ff	1180	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
mbed_official	113:b3775bf36a83	1181	#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
mbed_official	113:b3775bf36a83	1182	#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
bogdanm	0:9b334a45a8ff	1183	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	1184
bogdanm	0:9b334a45a8ff	1185	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	1186	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	113:b3775bf36a83	1187	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx) \|\| \
mbed_official	113:b3775bf36a83	1188	defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L011xx) \|\| defined(STM32L021xx)
mbed_official	113:b3775bf36a83	1189
mbed_official	113:b3775bf36a83	1190	/**
mbed_official	113:b3775bf36a83	1191	* @}
mbed_official	113:b3775bf36a83	1192	*/
mbed_official	113:b3775bf36a83	1193
mbed_official	113:b3775bf36a83	1194	/** @defgroup RCCEx_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
mbed_official	113:b3775bf36a83	1195	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1196	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1197	* power consumption.
bogdanm	0:9b334a45a8ff	1198	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1199	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	113:b3775bf36a83	1200	* @{
bogdanm	0:9b334a45a8ff	1201	*/
mbed_official	113:b3775bf36a83	1202	#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
mbed_official	113:b3775bf36a83	1203	#if !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official	113:b3775bf36a83	1204	#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
mbed_official	113:b3775bf36a83	1205	#endif
mbed_official	113:b3775bf36a83	1206	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
mbed_official	113:b3775bf36a83	1207	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
mbed_official	113:b3775bf36a83	1208	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
bogdanm	0:9b334a45a8ff	1209
mbed_official	113:b3775bf36a83	1210	#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
mbed_official	113:b3775bf36a83	1211	#if !defined (STM32L011xx) && !defined (STM32L021xx)
mbed_official	113:b3775bf36a83	1212	#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
mbed_official	113:b3775bf36a83	1213	#endif
mbed_official	113:b3775bf36a83	1214	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
mbed_official	113:b3775bf36a83	1215	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
mbed_official	113:b3775bf36a83	1216	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
bogdanm	0:9b334a45a8ff	1217	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1218	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1219	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	113:b3775bf36a83	1220	/* STM32L031xx \|\| STM32L041xx \|\| STM32L011xx \|\| STM32L021xx */
bogdanm	0:9b334a45a8ff	1221
mbed_official	113:b3775bf36a83	1222	/** @brief Macro to configures LCD clock (LCDCLK).
mbed_official	113:b3775bf36a83	1223	* @note LCD and RTC use the same configuration
mbed_official	113:b3775bf36a83	1224	* @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
mbed_official	113:b3775bf36a83	1225	* LCD clock source.
mbed_official	113:b3775bf36a83	1226	*
mbed_official	113:b3775bf36a83	1227	* @param __LCD_CLKSOURCE__ specifies the LCD clock source.
mbed_official	113:b3775bf36a83	1228	* This parameter can be one of the following values:
mbed_official	113:b3775bf36a83	1229	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
mbed_official	113:b3775bf36a83	1230	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
mbed_official	113:b3775bf36a83	1231	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
mbed_official	113:b3775bf36a83	1232	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
mbed_official	113:b3775bf36a83	1233	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
mbed_official	113:b3775bf36a83	1234	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
mbed_official	113:b3775bf36a83	1235	*/
mbed_official	113:b3775bf36a83	1236	#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
mbed_official	113:b3775bf36a83	1237
mbed_official	113:b3775bf36a83	1238	/** @brief macros to get the LCD clock source.
mbed_official	113:b3775bf36a83	1239	*/
mbed_official	113:b3775bf36a83	1240	#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE()
mbed_official	113:b3775bf36a83	1241
mbed_official	113:b3775bf36a83	1242	/** @brief macros to get the LCD clock pre-scaler.
mbed_official	113:b3775bf36a83	1243	*/
mbed_official	113:b3775bf36a83	1244	#define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER()
mbed_official	113:b3775bf36a83	1245	/**
mbed_official	113:b3775bf36a83	1246	* @}
mbed_official	113:b3775bf36a83	1247	*/
mbed_official	113:b3775bf36a83	1248
mbed_official	113:b3775bf36a83	1249	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
bogdanm	0:9b334a45a8ff	1250	*
mbed_official	113:b3775bf36a83	1251	* @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
bogdanm	0:9b334a45a8ff	1252	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1253	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1254	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1255	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
mbed_official	113:b3775bf36a83	1256	* @retval None
bogdanm	0:9b334a45a8ff	1257	*/
mbed_official	113:b3775bf36a83	1258	#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
mbed_official	113:b3775bf36a83	1259	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	1260
mbed_official	113:b3775bf36a83	1261	/** @brief Macro to get the I2C1 clock source.
bogdanm	0:9b334a45a8ff	1262	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1263	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1264	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1265	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1266	*/
bogdanm	0:9b334a45a8ff	1267	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
bogdanm	0:9b334a45a8ff	1268
bogdanm	0:9b334a45a8ff	1269	#if defined (STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	1270	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	1271	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	1272	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
bogdanm	0:9b334a45a8ff	1273	*
mbed_official	113:b3775bf36a83	1274	* @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
bogdanm	0:9b334a45a8ff	1275	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1276	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
bogdanm	0:9b334a45a8ff	1277	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official	113:b3775bf36a83	1278	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official	113:b3775bf36a83	1279	* @retval None
bogdanm	0:9b334a45a8ff	1280	*/
mbed_official	113:b3775bf36a83	1281	#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
mbed_official	113:b3775bf36a83	1282	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	1283
mbed_official	113:b3775bf36a83	1284	/** @brief Macro to get the I2C3 clock source.
bogdanm	0:9b334a45a8ff	1285	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1286	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
bogdanm	0:9b334a45a8ff	1287	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm	0:9b334a45a8ff	1288	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm	0:9b334a45a8ff	1289	*/
bogdanm	0:9b334a45a8ff	1290	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
bogdanm	0:9b334a45a8ff	1291
bogdanm	0:9b334a45a8ff	1292	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1293	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1294	/* STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	0:9b334a45a8ff	1295
mbed_official	113:b3775bf36a83	1296	/** @brief Macro to configure the USART1 clock (USART1CLK).
bogdanm	0:9b334a45a8ff	1297	*
mbed_official	113:b3775bf36a83	1298	* @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
bogdanm	0:9b334a45a8ff	1299	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1300	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
bogdanm	0:9b334a45a8ff	1301	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	0:9b334a45a8ff	1302	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	0:9b334a45a8ff	1303	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
mbed_official	113:b3775bf36a83	1304	* @retval None
bogdanm	0:9b334a45a8ff	1305	*/
mbed_official	113:b3775bf36a83	1306	#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
mbed_official	113:b3775bf36a83	1307	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	1308
mbed_official	113:b3775bf36a83	1309	/** @brief Macro to get the USART1 clock source.
bogdanm	0:9b334a45a8ff	1310	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1311	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
bogdanm	0:9b334a45a8ff	1312	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	0:9b334a45a8ff	1313	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	0:9b334a45a8ff	1314	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	0:9b334a45a8ff	1315	*/
bogdanm	0:9b334a45a8ff	1316	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
bogdanm	0:9b334a45a8ff	1317
mbed_official	113:b3775bf36a83	1318	/** @brief Macro to configure the USART2 clock (USART2CLK).
bogdanm	0:9b334a45a8ff	1319	*
mbed_official	113:b3775bf36a83	1320	* @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
bogdanm	0:9b334a45a8ff	1321	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1322	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	0:9b334a45a8ff	1323	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	0:9b334a45a8ff	1324	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	0:9b334a45a8ff	1325	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
mbed_official	113:b3775bf36a83	1326	* @retval None
bogdanm	0:9b334a45a8ff	1327	*/
mbed_official	113:b3775bf36a83	1328	#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
mbed_official	113:b3775bf36a83	1329	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	1330
mbed_official	113:b3775bf36a83	1331	/** @brief Macro to get the USART2 clock source.
bogdanm	0:9b334a45a8ff	1332	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1333	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	0:9b334a45a8ff	1334	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	0:9b334a45a8ff	1335	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	0:9b334a45a8ff	1336	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	0:9b334a45a8ff	1337	*/
bogdanm	0:9b334a45a8ff	1338	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
bogdanm	0:9b334a45a8ff	1339
mbed_official	113:b3775bf36a83	1340	/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
bogdanm	0:9b334a45a8ff	1341	*
mbed_official	113:b3775bf36a83	1342	* @param __LPUART1_CLKSOURCE__: specifies the LPUART1 clock source.
bogdanm	0:9b334a45a8ff	1343	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1344	* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1345	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1346	* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1347	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
mbed_official	113:b3775bf36a83	1348	* @retval None
bogdanm	0:9b334a45a8ff	1349	*/
mbed_official	113:b3775bf36a83	1350	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
mbed_official	113:b3775bf36a83	1351	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	1352
mbed_official	113:b3775bf36a83	1353	/** @brief Macro to get the LPUART1 clock source.
bogdanm	0:9b334a45a8ff	1354	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1355	* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1356	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1357	* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1358	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1359	*/
bogdanm	0:9b334a45a8ff	1360	#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
bogdanm	0:9b334a45a8ff	1361
mbed_official	113:b3775bf36a83	1362	/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
bogdanm	0:9b334a45a8ff	1363	*
mbed_official	113:b3775bf36a83	1364	* @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
bogdanm	0:9b334a45a8ff	1365	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1366	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	1367	* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	1368	* @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	1369	* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock
mbed_official	113:b3775bf36a83	1370	* @retval None
bogdanm	0:9b334a45a8ff	1371	*/
mbed_official	113:b3775bf36a83	1372	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
mbed_official	113:b3775bf36a83	1373	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
bogdanm	0:9b334a45a8ff	1374
mbed_official	113:b3775bf36a83	1375	/** @brief Macro to get the LPTIM1 clock source.
bogdanm	0:9b334a45a8ff	1376	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1377	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1378	* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1379	* @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1380	* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1381	*/
bogdanm	0:9b334a45a8ff	1382	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
bogdanm	0:9b334a45a8ff	1383
mbed_official	113:b3775bf36a83	1384	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1385	/** @brief Macro to configure the USB clock (USBCLK).
bogdanm	0:9b334a45a8ff	1386	* @param __USBCLKSource__: specifies the USB clock source.
bogdanm	0:9b334a45a8ff	1387	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1388	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
mbed_official	113:b3775bf36a83	1389	* @arg RCC_USBCLKSOURCE_PLL: PLL Clock selected as USB clock
bogdanm	0:9b334a45a8ff	1390	*/
bogdanm	0:9b334a45a8ff	1391	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm	0:9b334a45a8ff	1392	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__))
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	/** @brief Macro to get the USB clock source.
bogdanm	0:9b334a45a8ff	1395	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1396	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
mbed_official	113:b3775bf36a83	1397	* @arg RCC_USBCLKSOURCE_PLL: PLL Clock selected as USB clock
bogdanm	0:9b334a45a8ff	1398	*/
bogdanm	0:9b334a45a8ff	1399	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401	/** @brief Macro to configure the RNG clock (RNGCLK).
bogdanm	0:9b334a45a8ff	1402	* @param __RNGCLKSource__: specifies the USB clock source.
bogdanm	0:9b334a45a8ff	1403	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1404	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
bogdanm	0:9b334a45a8ff	1405	* @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
bogdanm	0:9b334a45a8ff	1406	*/
bogdanm	0:9b334a45a8ff	1407	#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
bogdanm	0:9b334a45a8ff	1408	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNGCLKSource__))
bogdanm	0:9b334a45a8ff	1409
bogdanm	0:9b334a45a8ff	1410	/** @brief Macro to get the RNG clock source.
bogdanm	0:9b334a45a8ff	1411	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1412	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
bogdanm	0:9b334a45a8ff	1413	* @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
bogdanm	0:9b334a45a8ff	1414	*/
bogdanm	0:9b334a45a8ff	1415	#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
bogdanm	0:9b334a45a8ff	1416
bogdanm	0:9b334a45a8ff	1417	/** @brief macro to select the HSI48M clock source
bogdanm	0:9b334a45a8ff	1418	* @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
bogdanm	0:9b334a45a8ff	1419	* __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
bogdanm	0:9b334a45a8ff	1420	*
bogdanm	0:9b334a45a8ff	1421	* @param __HSI48MCLKSource__: specifies the HSI48M clock source dedicated for
bogdanm	0:9b334a45a8ff	1422	* USB an RNG peripherals.
bogdanm	0:9b334a45a8ff	1423	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1424	* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
bogdanm	0:9b334a45a8ff	1425	* @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
bogdanm	0:9b334a45a8ff	1426	*/
bogdanm	0:9b334a45a8ff	1427	#define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \
bogdanm	0:9b334a45a8ff	1428	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__))
bogdanm	0:9b334a45a8ff	1429
bogdanm	0:9b334a45a8ff	1430	/** @brief macro to get the HSI48M clock source.
bogdanm	0:9b334a45a8ff	1431	* @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
bogdanm	0:9b334a45a8ff	1432	* __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
bogdanm	0:9b334a45a8ff	1433	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1434	* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
bogdanm	0:9b334a45a8ff	1435	* @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
bogdanm	0:9b334a45a8ff	1436	*/
bogdanm	0:9b334a45a8ff	1437	#define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
mbed_official	113:b3775bf36a83	1438	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	1439
bogdanm	0:9b334a45a8ff	1440	/**
bogdanm	0:9b334a45a8ff	1441	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
bogdanm	0:9b334a45a8ff	1442	* in STOP mode to be quickly available as kernel clock for USART and I2C.
bogdanm	0:9b334a45a8ff	1443	* @note The Enable of this function has not effect on the HSION bit.
bogdanm	0:9b334a45a8ff	1444	* @retval None
bogdanm	0:9b334a45a8ff	1445	*/
bogdanm	0:9b334a45a8ff	1446	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
bogdanm	0:9b334a45a8ff	1447	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
bogdanm	0:9b334a45a8ff	1448
bogdanm	0:9b334a45a8ff	1449	/**
bogdanm	0:9b334a45a8ff	1450	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
mbed_official	113:b3775bf36a83	1451	* @param __RCC_LSEDrive__: specifies the new state of the LSE drive capability.
bogdanm	0:9b334a45a8ff	1452	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1453	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
bogdanm	0:9b334a45a8ff	1454	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
bogdanm	0:9b334a45a8ff	1455	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
bogdanm	0:9b334a45a8ff	1456	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
bogdanm	0:9b334a45a8ff	1457	* @retval None
bogdanm	0:9b334a45a8ff	1458	*/
bogdanm	0:9b334a45a8ff	1459	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDrive__) (MODIFY_REG(RCC->CSR,\
bogdanm	0:9b334a45a8ff	1460	RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDrive__) ))
bogdanm	0:9b334a45a8ff	1461
bogdanm	0:9b334a45a8ff	1462	/**
bogdanm	0:9b334a45a8ff	1463	* @brief Macro to configures the wake up from stop clock.
mbed_official	113:b3775bf36a83	1464	* @param __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
bogdanm	0:9b334a45a8ff	1465	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1466	* @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
bogdanm	0:9b334a45a8ff	1467	* @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
bogdanm	0:9b334a45a8ff	1468	* @retval None
bogdanm	0:9b334a45a8ff	1469	*/
bogdanm	0:9b334a45a8ff	1470	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
bogdanm	0:9b334a45a8ff	1471	RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
bogdanm	0:9b334a45a8ff	1472
mbed_official	113:b3775bf36a83	1473	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1474	/**
bogdanm	0:9b334a45a8ff	1475	* @brief Enables the specified CRS interrupts.
bogdanm	0:9b334a45a8ff	1476	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
bogdanm	0:9b334a45a8ff	1477	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1478	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	1479	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	1480	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	1481	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	1482	* @retval None
bogdanm	0:9b334a45a8ff	1483	*/
mbed_official	113:b3775bf36a83	1484	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1485
bogdanm	0:9b334a45a8ff	1486	/**
bogdanm	0:9b334a45a8ff	1487	* @brief Disables the specified CRS interrupts.
bogdanm	0:9b334a45a8ff	1488	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
bogdanm	0:9b334a45a8ff	1489	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1490	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	1491	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	1492	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	1493	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	1494	* @retval None
bogdanm	0:9b334a45a8ff	1495	*/
mbed_official	113:b3775bf36a83	1496	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR,(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	/** @brief Check the CRS interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	1499	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
bogdanm	0:9b334a45a8ff	1500	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1501	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	1502	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	1503	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	1504	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	1505	* @retval The new state of __INTERRUPT__ (SET or RESET).
bogdanm	0:9b334a45a8ff	1506	*/
bogdanm	0:9b334a45a8ff	1507	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
bogdanm	0:9b334a45a8ff	1508
bogdanm	0:9b334a45a8ff	1509	/** @brief Clear the CRS interrupt pending bits
bogdanm	0:9b334a45a8ff	1510	* bits to clear the selected interrupt pending bits.
bogdanm	0:9b334a45a8ff	1511	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	1512	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1513	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	1514	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	1515	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	1516	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	1517	* @arg RCC_CRS_IT_TRIMOVF
bogdanm	0:9b334a45a8ff	1518	* @arg RCC_CRS_IT_SYNCERR
bogdanm	0:9b334a45a8ff	1519	* @arg RCC_CRS_IT_SYNCMISS
bogdanm	0:9b334a45a8ff	1520	*/
bogdanm	0:9b334a45a8ff	1521	/* CRS IT Error Mask */
bogdanm	0:9b334a45a8ff	1522	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
bogdanm	0:9b334a45a8ff	1523
bogdanm	0:9b334a45a8ff	1524	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	0:9b334a45a8ff	1525	(CRS->ICR = (__INTERRUPT__)))
bogdanm	0:9b334a45a8ff	1526
bogdanm	0:9b334a45a8ff	1527	/**
bogdanm	0:9b334a45a8ff	1528	* @brief Checks whether the specified CRS flag is set or not.
mbed_official	113:b3775bf36a83	1529	* @param __FLAG__: specifies the flag to check.
bogdanm	0:9b334a45a8ff	1530	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1531	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	0:9b334a45a8ff	1532	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	0:9b334a45a8ff	1533	* @arg RCC_CRS_FLAG_ERR
bogdanm	0:9b334a45a8ff	1534	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	0:9b334a45a8ff	1535	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	0:9b334a45a8ff	1536	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	0:9b334a45a8ff	1537	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	0:9b334a45a8ff	1538	* @retval The new state of _FLAG_ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1539	*/
bogdanm	0:9b334a45a8ff	1540	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1541
bogdanm	0:9b334a45a8ff	1542	/**
bogdanm	0:9b334a45a8ff	1543	* @brief Clears the CRS specified FLAG.
bogdanm	0:9b334a45a8ff	1544	* @param _FLAG_: specifies the flag to clear.
bogdanm	0:9b334a45a8ff	1545	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1546	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	0:9b334a45a8ff	1547	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	0:9b334a45a8ff	1548	* @arg RCC_CRS_FLAG_ERR
bogdanm	0:9b334a45a8ff	1549	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	0:9b334a45a8ff	1550	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	0:9b334a45a8ff	1551	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	0:9b334a45a8ff	1552	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	0:9b334a45a8ff	1553	* @retval None
bogdanm	0:9b334a45a8ff	1554	*/
bogdanm	0:9b334a45a8ff	1555
bogdanm	0:9b334a45a8ff	1556	/* CRS Flag Error Mask */
bogdanm	0:9b334a45a8ff	1557	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
bogdanm	0:9b334a45a8ff	1558
bogdanm	0:9b334a45a8ff	1559	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	0:9b334a45a8ff	1560	(CRS->ICR = (__FLAG__)))
bogdanm	0:9b334a45a8ff	1561
bogdanm	0:9b334a45a8ff	1562
bogdanm	0:9b334a45a8ff	1563	/**
bogdanm	0:9b334a45a8ff	1564	* @brief Enables the oscillator clock for frequency error counter.
bogdanm	0:9b334a45a8ff	1565	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	0:9b334a45a8ff	1566	* @retval None
bogdanm	0:9b334a45a8ff	1567	*/
mbed_official	113:b3775bf36a83	1568	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
bogdanm	0:9b334a45a8ff	1569
bogdanm	0:9b334a45a8ff	1570	/**
bogdanm	0:9b334a45a8ff	1571	* @brief Disables the oscillator clock for frequency error counter.
bogdanm	0:9b334a45a8ff	1572	* @retval None
bogdanm	0:9b334a45a8ff	1573	*/
mbed_official	113:b3775bf36a83	1574	#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR,CRS_CR_CEN)
bogdanm	0:9b334a45a8ff	1575
bogdanm	0:9b334a45a8ff	1576	/**
bogdanm	0:9b334a45a8ff	1577	* @brief Enables the automatic hardware adjustment of TRIM bits.
bogdanm	0:9b334a45a8ff	1578	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	0:9b334a45a8ff	1579	* @retval None
bogdanm	0:9b334a45a8ff	1580	*/
mbed_official	113:b3775bf36a83	1581	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
bogdanm	0:9b334a45a8ff	1582
bogdanm	0:9b334a45a8ff	1583	/**
bogdanm	0:9b334a45a8ff	1584	* @brief Enables or disables the automatic hardware adjustment of TRIM bits.
bogdanm	0:9b334a45a8ff	1585	* @retval None
bogdanm	0:9b334a45a8ff	1586	*/
mbed_official	113:b3775bf36a83	1587	#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR,CRS_CR_AUTOTRIMEN)
bogdanm	0:9b334a45a8ff	1588
bogdanm	0:9b334a45a8ff	1589	/**
bogdanm	0:9b334a45a8ff	1590	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
bogdanm	0:9b334a45a8ff	1591	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
bogdanm	0:9b334a45a8ff	1592	* of the synchronization source after prescaling. It is then decreased by one in order to
bogdanm	0:9b334a45a8ff	1593	* reach the expected synchronization on the zero value. The formula is the following:
bogdanm	0:9b334a45a8ff	1594	* RELOAD = (fTARGET / fSYNC) -1
mbed_official	113:b3775bf36a83	1595	* @param __FTARGET__ Target frequency (value in Hz)
mbed_official	113:b3775bf36a83	1596	* @param __FSYNC__ Synchronization signal frequency (value in Hz)
bogdanm	0:9b334a45a8ff	1597	* @retval None
bogdanm	0:9b334a45a8ff	1598	*/
mbed_official	113:b3775bf36a83	1599	#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
bogdanm	0:9b334a45a8ff	1600
mbed_official	113:b3775bf36a83	1601	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	1602
bogdanm	0:9b334a45a8ff	1603	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	1604	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	1605	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1606	/** @brief Enable or disable the HSI OUT .
bogdanm	0:9b334a45a8ff	1607	* @note After reset, the HSI output is not available
bogdanm	0:9b334a45a8ff	1608	*/
bogdanm	0:9b334a45a8ff	1609
bogdanm	0:9b334a45a8ff	1610	#define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
bogdanm	0:9b334a45a8ff	1611	#define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
bogdanm	0:9b334a45a8ff	1612
bogdanm	0:9b334a45a8ff	1613	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1614	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1615	/* STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	1616
bogdanm	0:9b334a45a8ff	1617	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\|\
bogdanm	0:9b334a45a8ff	1618	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx)
bogdanm	0:9b334a45a8ff	1619
bogdanm	0:9b334a45a8ff	1620	/**
bogdanm	0:9b334a45a8ff	1621	* @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
bogdanm	0:9b334a45a8ff	1622	* @note After enabling the HSI48, the application software should wait on
bogdanm	0:9b334a45a8ff	1623	* HSI48RDY flag to be set indicating that HSI48 clock is stable and can
bogdanm	0:9b334a45a8ff	1624	* be used to clock the USB.
bogdanm	0:9b334a45a8ff	1625	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1626	*/
bogdanm	0:9b334a45a8ff	1627	#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
bogdanm	0:9b334a45a8ff	1628	RCC->APB2ENR \|= RCC_APB2ENR_SYSCFGEN; \
bogdanm	0:9b334a45a8ff	1629	SYSCFG->CFGR3 \|= (SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT); \
bogdanm	0:9b334a45a8ff	1630	} while (0)
bogdanm	0:9b334a45a8ff	1631	#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
bogdanm	0:9b334a45a8ff	1632	SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT)); \
bogdanm	0:9b334a45a8ff	1633	} while (0)
bogdanm	0:9b334a45a8ff	1634	/** @brief Enable or disable the HSI48M DIV6 OUT .
bogdanm	0:9b334a45a8ff	1635	* @note After reset, the HSI48Mhz (divided by 6) output is not available
bogdanm	0:9b334a45a8ff	1636	*/
bogdanm	0:9b334a45a8ff	1637
bogdanm	0:9b334a45a8ff	1638	#define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
bogdanm	0:9b334a45a8ff	1639	#define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
bogdanm	0:9b334a45a8ff	1640
bogdanm	0:9b334a45a8ff	1641	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1642	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1643	/* STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	1644
bogdanm	0:9b334a45a8ff	1645	/**
bogdanm	0:9b334a45a8ff	1646	* @}
bogdanm	0:9b334a45a8ff	1647	*/
bogdanm	0:9b334a45a8ff	1648
bogdanm	0:9b334a45a8ff	1649	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
bogdanm	0:9b334a45a8ff	1650	* @{
bogdanm	0:9b334a45a8ff	1651	*/
bogdanm	0:9b334a45a8ff	1652
bogdanm	0:9b334a45a8ff	1653	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	1654
bogdanm	0:9b334a45a8ff	1655	* @{
bogdanm	0:9b334a45a8ff	1656	*/
bogdanm	0:9b334a45a8ff	1657	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	0:9b334a45a8ff	1658	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	113:b3775bf36a83	1659	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
bogdanm	0:9b334a45a8ff	1660	void HAL_RCCEx_EnableLSECSS(void);
bogdanm	0:9b334a45a8ff	1661	void HAL_RCCEx_DisableLSECSS(void);
mbed_official	113:b3775bf36a83	1662	void HAL_RCCEx_EnableLSECSS_IT(void);
mbed_official	113:b3775bf36a83	1663	void HAL_RCCEx_LSECSS_IRQHandler(void);
mbed_official	113:b3775bf36a83	1664	void HAL_RCCEx_LSECSS_Callback(void);
mbed_official	113:b3775bf36a83	1665
mbed_official	113:b3775bf36a83	1666	#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1667	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
bogdanm	0:9b334a45a8ff	1668	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
bogdanm	0:9b334a45a8ff	1669	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
bogdanm	0:9b334a45a8ff	1670	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
bogdanm	0:9b334a45a8ff	1671	void HAL_RCCEx_EnableHSI48_VREFINT(void);
bogdanm	0:9b334a45a8ff	1672	void HAL_RCCEx_DisableHSI48_VREFINT(void);
mbed_official	113:b3775bf36a83	1673	#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	1674
bogdanm	0:9b334a45a8ff	1675	/**
bogdanm	0:9b334a45a8ff	1676	* @}
bogdanm	0:9b334a45a8ff	1677	*/
bogdanm	0:9b334a45a8ff	1678	/**
bogdanm	0:9b334a45a8ff	1679	* @}
bogdanm	0:9b334a45a8ff	1680	*/
bogdanm	0:9b334a45a8ff	1681
mbed_official	113:b3775bf36a83	1682
mbed_official	113:b3775bf36a83	1683	/* Private macros ------------------------------------------------------------*/
mbed_official	113:b3775bf36a83	1684	/** @addtogroup RCCEx_Private_Macros
mbed_official	113:b3775bf36a83	1685	* @{
mbed_official	113:b3775bf36a83	1686	*/
mbed_official	113:b3775bf36a83	1687
mbed_official	113:b3775bf36a83	1688	#if defined (STM32L052xx) \|\| defined(STM32L062xx)
mbed_official	113:b3775bf36a83	1689	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	113:b3775bf36a83	1690	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	113:b3775bf36a83	1691	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1))
mbed_official	113:b3775bf36a83	1692	#elif defined (STM32L053xx) \|\| defined(STM32L063xx)
mbed_official	113:b3775bf36a83	1693	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	113:b3775bf36a83	1694	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	113:b3775bf36a83	1695	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_LCD))
mbed_official	113:b3775bf36a83	1696	#elif defined (STM32L072xx) \|\| defined(STM32L082xx)
mbed_official	113:b3775bf36a83	1697	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	113:b3775bf36a83	1698	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	113:b3775bf36a83	1699	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 ))
mbed_official	113:b3775bf36a83	1700	#elif defined (STM32L073xx) \|\| defined(STM32L083xx)
mbed_official	113:b3775bf36a83	1701	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	113:b3775bf36a83	1702	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	113:b3775bf36a83	1703	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 \| \
mbed_official	113:b3775bf36a83	1704	RCC_PERIPHCLK_LCD))
mbed_official	113:b3775bf36a83	1705	#endif
mbed_official	113:b3775bf36a83	1706
mbed_official	113:b3775bf36a83	1707	#if defined(STM32L011xx) \|\| defined(STM32L021xx) \|\| defined(STM32L031xx) \|\| defined(STM32L041xx)
mbed_official	113:b3775bf36a83	1708	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	113:b3775bf36a83	1709	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_RTC \| \
mbed_official	113:b3775bf36a83	1710	RCC_PERIPHCLK_LPTIM1))
mbed_official	113:b3775bf36a83	1711	#elif defined(STM32L051xx) \|\| defined(STM32L061xx)
mbed_official	113:b3775bf36a83	1712	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	113:b3775bf36a83	1713	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	113:b3775bf36a83	1714	RCC_PERIPHCLK_LPTIM1))
mbed_official	113:b3775bf36a83	1715	#elif defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	1716	#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	113:b3775bf36a83	1717	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	113:b3775bf36a83	1718	RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3))
mbed_official	113:b3775bf36a83	1719	#endif
mbed_official	113:b3775bf36a83	1720
mbed_official	113:b3775bf36a83	1721	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
mbed_official	113:b3775bf36a83	1722	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	113:b3775bf36a83	1723	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	113:b3775bf36a83	1724	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
mbed_official	113:b3775bf36a83	1725
mbed_official	113:b3775bf36a83	1726
mbed_official	113:b3775bf36a83	1727	#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
mbed_official	113:b3775bf36a83	1728	((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
mbed_official	113:b3775bf36a83	1729	((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) \|\| \
mbed_official	113:b3775bf36a83	1730	((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
mbed_official	113:b3775bf36a83	1731
mbed_official	113:b3775bf36a83	1732	#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) \|\| \
mbed_official	113:b3775bf36a83	1733	((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	113:b3775bf36a83	1734	((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
mbed_official	113:b3775bf36a83	1735	((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
mbed_official	113:b3775bf36a83	1736
mbed_official	113:b3775bf36a83	1737	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
mbed_official	113:b3775bf36a83	1738	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
mbed_official	113:b3775bf36a83	1739	((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
mbed_official	113:b3775bf36a83	1740
mbed_official	113:b3775bf36a83	1741	#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
mbed_official	113:b3775bf36a83	1742	((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
mbed_official	113:b3775bf36a83	1743	((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
mbed_official	113:b3775bf36a83	1744
mbed_official	113:b3775bf36a83	1745	#define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) \|\| \
mbed_official	113:b3775bf36a83	1746	((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
mbed_official	113:b3775bf36a83	1747
mbed_official	113:b3775bf36a83	1748	#define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) \|\| \
mbed_official	113:b3775bf36a83	1749	((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
mbed_official	113:b3775bf36a83	1750
mbed_official	113:b3775bf36a83	1751	#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) \|\| ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
mbed_official	113:b3775bf36a83	1752
mbed_official	113:b3775bf36a83	1753	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	113:b3775bf36a83	1754	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	113:b3775bf36a83	1755	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	113:b3775bf36a83	1756
mbed_official	113:b3775bf36a83	1757	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
mbed_official	113:b3775bf36a83	1758	((__HSI__) == RCC_HSI_DIV4) \|\| ((__HSI__) == RCC_HSI_OUTEN ))
mbed_official	113:b3775bf36a83	1759	#else
mbed_official	113:b3775bf36a83	1760	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
mbed_official	113:b3775bf36a83	1761	((__HSI__) == RCC_HSI_DIV4))
mbed_official	113:b3775bf36a83	1762	#endif
mbed_official	113:b3775bf36a83	1763
mbed_official	113:b3775bf36a83	1764	#define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
mbed_official	113:b3775bf36a83	1765	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
mbed_official	113:b3775bf36a83	1766	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
mbed_official	113:b3775bf36a83	1767	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
mbed_official	113:b3775bf36a83	1768
mbed_official	113:b3775bf36a83	1769	#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) \|\| \
mbed_official	113:b3775bf36a83	1770	((__SOURCE__) == RCC_StopWakeUpClock_HSI))
mbed_official	113:b3775bf36a83	1771
mbed_official	113:b3775bf36a83	1772	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
mbed_official	113:b3775bf36a83	1773	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
mbed_official	113:b3775bf36a83	1774
mbed_official	113:b3775bf36a83	1775	#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
mbed_official	113:b3775bf36a83	1776	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) \|\|\
mbed_official	113:b3775bf36a83	1777	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
mbed_official	113:b3775bf36a83	1778
mbed_official	113:b3775bf36a83	1779	#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV2) \|\|\
mbed_official	113:b3775bf36a83	1780	((__DIV__) == RCC_CRS_SYNC_DIV4) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV8) \|\| \
mbed_official	113:b3775bf36a83	1781	((__DIV__) == RCC_CRS_SYNC_DIV16) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV32) \|\| \
mbed_official	113:b3775bf36a83	1782	((__DIV__) == RCC_CRS_SYNC_DIV64) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV128))
mbed_official	113:b3775bf36a83	1783
mbed_official	113:b3775bf36a83	1784	#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
mbed_official	113:b3775bf36a83	1785	((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
mbed_official	113:b3775bf36a83	1786
mbed_official	113:b3775bf36a83	1787	#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
mbed_official	113:b3775bf36a83	1788
mbed_official	113:b3775bf36a83	1789	#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
mbed_official	113:b3775bf36a83	1790
mbed_official	113:b3775bf36a83	1791	#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
mbed_official	113:b3775bf36a83	1792
mbed_official	113:b3775bf36a83	1793	#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) \|\| \
mbed_official	113:b3775bf36a83	1794	((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
mbed_official	113:b3775bf36a83	1795
mbed_official	113:b3775bf36a83	1796	/**
mbed_official	113:b3775bf36a83	1797	* @}
mbed_official	113:b3775bf36a83	1798	*/
mbed_official	113:b3775bf36a83	1799
mbed_official	113:b3775bf36a83	1800
mbed_official	113:b3775bf36a83	1801	/**
mbed_official	113:b3775bf36a83	1802	* @}
mbed_official	113:b3775bf36a83	1803	*/
mbed_official	113:b3775bf36a83	1804
bogdanm	0:9b334a45a8ff	1805	/**
bogdanm	0:9b334a45a8ff	1806	* @}
bogdanm	0:9b334a45a8ff	1807	*/
bogdanm	0:9b334a45a8ff	1808
bogdanm	0:9b334a45a8ff	1809	/**
bogdanm	0:9b334a45a8ff	1810	* @}
bogdanm	0:9b334a45a8ff	1811	*/
bogdanm	0:9b334a45a8ff	1812
bogdanm	0:9b334a45a8ff	1813	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1814	}
bogdanm	0:9b334a45a8ff	1815	#endif
bogdanm	0:9b334a45a8ff	1816
bogdanm	0:9b334a45a8ff	1817	#endif /* __STM32L0xx_HAL_RCC_EX_H */
bogdanm	0:9b334a45a8ff	1818
bogdanm	0:9b334a45a8ff	1819	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	1820

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h@113:b3775bf36a83, 2016-04-19 (annotated)

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