mbed-dev - fix LPC812 PWM

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fix LPC812 PWM

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 113:b3775bf36a83

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32l0xx_hal_rcc_ex.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.2.0
bogdanm	0:9b334a45a8ff	6	* @date 06-February-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL Extension module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32L0xx_HAL_RCC_EX_H
bogdanm	0:9b334a45a8ff	40	#define __STM32L0xx_HAL_RCC_EX_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32l0xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @defgroup RCCEx
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	58	/**
bogdanm	0:9b334a45a8ff	59	* @brief RCC extended clocks structure definition
bogdanm	0:9b334a45a8ff	60	*/
bogdanm	0:9b334a45a8ff	61	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	62	typedef struct
bogdanm	0:9b334a45a8ff	63	{
bogdanm	0:9b334a45a8ff	64	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	65	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	66	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	67	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	68
bogdanm	0:9b334a45a8ff	69	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	0:9b334a45a8ff	70	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	0:9b334a45a8ff	71
bogdanm	0:9b334a45a8ff	72	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
bogdanm	0:9b334a45a8ff	73	This parameter can be a value of @ref RCCEx_LPUART_Clock_Source */
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	76	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	77	#if defined (STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	78	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm	0:9b334a45a8ff	79	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm	0:9b334a45a8ff	80	#endif
bogdanm	0:9b334a45a8ff	81
bogdanm	0:9b334a45a8ff	82	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	83	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	84	#if defined (STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	85	uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
bogdanm	0:9b334a45a8ff	86	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	87	#endif
bogdanm	0:9b334a45a8ff	88
bogdanm	0:9b334a45a8ff	89	uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
bogdanm	0:9b334a45a8ff	90	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	0:9b334a45a8ff	91
bogdanm	0:9b334a45a8ff	92	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
bogdanm	0:9b334a45a8ff	93	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
bogdanm	0:9b334a45a8ff	94
bogdanm	0:9b334a45a8ff	95	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	96
bogdanm	0:9b334a45a8ff	97
bogdanm	0:9b334a45a8ff	98	#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	99
bogdanm	0:9b334a45a8ff	100	typedef struct
bogdanm	0:9b334a45a8ff	101	{
bogdanm	0:9b334a45a8ff	102	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	103	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	104	#if !defined (STM32L031xx) && !defined (STM32L041xx)
bogdanm	0:9b334a45a8ff	105	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	106	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	107	#endif
bogdanm	0:9b334a45a8ff	108	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	0:9b334a45a8ff	109	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	0:9b334a45a8ff	110
bogdanm	0:9b334a45a8ff	111	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
bogdanm	0:9b334a45a8ff	112	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
bogdanm	0:9b334a45a8ff	113
bogdanm	0:9b334a45a8ff	114	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	115	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	#if defined (STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	118	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm	0:9b334a45a8ff	119	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm	0:9b334a45a8ff	120	#endif
bogdanm	0:9b334a45a8ff	121
bogdanm	0:9b334a45a8ff	122	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	123	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	124
bogdanm	0:9b334a45a8ff	125	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
bogdanm	0:9b334a45a8ff	126	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
bogdanm	0:9b334a45a8ff	127
bogdanm	0:9b334a45a8ff	128	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130	#endif /* STM32L0x1xx */
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132
bogdanm	0:9b334a45a8ff	133	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	134	/** @defgroup RCCEx_Exported_Constants
bogdanm	0:9b334a45a8ff	135	* @{
bogdanm	0:9b334a45a8ff	136	*/
bogdanm	0:9b334a45a8ff	137	/**
bogdanm	0:9b334a45a8ff	138	* @brief RCC CRS Status definition
bogdanm	0:9b334a45a8ff	139	*/
bogdanm	0:9b334a45a8ff	140
bogdanm	0:9b334a45a8ff	141	#define RCC_CRS_NONE ((uint32_t) 0x00000000)
bogdanm	0:9b334a45a8ff	142	#define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001)
bogdanm	0:9b334a45a8ff	143	#define RCC_CRS_SYNCOK ((uint32_t) 0x00000002)
bogdanm	0:9b334a45a8ff	144	#define RCC_CRS_SYNCWARM ((uint32_t) 0x00000004)
bogdanm	0:9b334a45a8ff	145	#define RCC_CRS_SYNCERR ((uint32_t) 0x00000008)
bogdanm	0:9b334a45a8ff	146	#define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010)
bogdanm	0:9b334a45a8ff	147	#define RCC_CRS_TRIMOV ((uint32_t) 0x00000020)
bogdanm	0:9b334a45a8ff	148
bogdanm	0:9b334a45a8ff	149	/**
bogdanm	0:9b334a45a8ff	150	* @}
bogdanm	0:9b334a45a8ff	151	*/
bogdanm	0:9b334a45a8ff	152	/**
bogdanm	0:9b334a45a8ff	153	* @brief RCC_CRS Init structure definition
bogdanm	0:9b334a45a8ff	154	*/
bogdanm	0:9b334a45a8ff	155	typedef struct
bogdanm	0:9b334a45a8ff	156	{
bogdanm	0:9b334a45a8ff	157	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
bogdanm	0:9b334a45a8ff	158	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
bogdanm	0:9b334a45a8ff	159
bogdanm	0:9b334a45a8ff	160	uint32_t Source; /*!< Specifies the SYNC signal source.
bogdanm	0:9b334a45a8ff	161	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
bogdanm	0:9b334a45a8ff	162
bogdanm	0:9b334a45a8ff	163	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
bogdanm	0:9b334a45a8ff	164	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
bogdanm	0:9b334a45a8ff	165
bogdanm	0:9b334a45a8ff	166	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
bogdanm	0:9b334a45a8ff	167	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
bogdanm	0:9b334a45a8ff	168	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
bogdanm	0:9b334a45a8ff	169
bogdanm	0:9b334a45a8ff	170	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
bogdanm	0:9b334a45a8ff	171	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
bogdanm	0:9b334a45a8ff	172
bogdanm	0:9b334a45a8ff	173	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
bogdanm	0:9b334a45a8ff	174	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
bogdanm	0:9b334a45a8ff	175
bogdanm	0:9b334a45a8ff	176	}RCC_CRSInitTypeDef;
bogdanm	0:9b334a45a8ff	177
bogdanm	0:9b334a45a8ff	178	/**
bogdanm	0:9b334a45a8ff	179	* @brief RCC_CRS Synchronization structure definition
bogdanm	0:9b334a45a8ff	180	*/
bogdanm	0:9b334a45a8ff	181	typedef struct
bogdanm	0:9b334a45a8ff	182	{
bogdanm	0:9b334a45a8ff	183	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
bogdanm	0:9b334a45a8ff	184	This parameter must be a number between 0 and 0xFFFF*/
bogdanm	0:9b334a45a8ff	185
bogdanm	0:9b334a45a8ff	186	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
bogdanm	0:9b334a45a8ff	187	This parameter must be a number between 0 and 0x3F */
bogdanm	0:9b334a45a8ff	188
bogdanm	0:9b334a45a8ff	189	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
bogdanm	0:9b334a45a8ff	190	value latched in the time of the last SYNC event.
bogdanm	0:9b334a45a8ff	191	This parameter must be a number between 0 and 0xFFFF */
bogdanm	0:9b334a45a8ff	192
bogdanm	0:9b334a45a8ff	193	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
bogdanm	0:9b334a45a8ff	194	frequency error counter latched in the time of the last SYNC event.
bogdanm	0:9b334a45a8ff	195	It shows whether the actual frequency is below or above the target.
bogdanm	0:9b334a45a8ff	196	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
bogdanm	0:9b334a45a8ff	197
bogdanm	0:9b334a45a8ff	198	}RCC_CRSSynchroInfoTypeDef;
bogdanm	0:9b334a45a8ff	199	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	200
bogdanm	0:9b334a45a8ff	201	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	202	/** @addtogroup RCCEx_Exported_Constants
bogdanm	0:9b334a45a8ff	203	* @{
bogdanm	0:9b334a45a8ff	204	*/
bogdanm	0:9b334a45a8ff	205
bogdanm	0:9b334a45a8ff	206	/** @defgroup RCCEx_Periph_Clock_Selection
bogdanm	0:9b334a45a8ff	207	* @{
bogdanm	0:9b334a45a8ff	208	*/
bogdanm	0:9b334a45a8ff	209	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	210
bogdanm	0:9b334a45a8ff	211	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	212	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	213	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	214	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	215	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	216	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	217	#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
bogdanm	0:9b334a45a8ff	218	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	219	#if defined (STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	220	#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800)
bogdanm	0:9b334a45a8ff	221	#endif
bogdanm	0:9b334a45a8ff	222	#if defined (STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	223	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	224	#endif
bogdanm	0:9b334a45a8ff	225
bogdanm	0:9b334a45a8ff	226	#if defined (STM32L052xx) \|\| defined(STM32L062xx)
bogdanm	0:9b334a45a8ff	227	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
bogdanm	0:9b334a45a8ff	228	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
bogdanm	0:9b334a45a8ff	229	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1))
bogdanm	0:9b334a45a8ff	230	#elif defined (STM32L053xx) \|\| defined(STM32L063xx)
bogdanm	0:9b334a45a8ff	231	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
bogdanm	0:9b334a45a8ff	232	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
bogdanm	0:9b334a45a8ff	233	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_LCD))
bogdanm	0:9b334a45a8ff	234	#elif defined (STM32L072xx) \|\| defined(STM32L082xx)
bogdanm	0:9b334a45a8ff	235	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
bogdanm	0:9b334a45a8ff	236	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
bogdanm	0:9b334a45a8ff	237	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 ))
bogdanm	0:9b334a45a8ff	238	#elif defined (STM32L073xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	239	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
bogdanm	0:9b334a45a8ff	240	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
bogdanm	0:9b334a45a8ff	241	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 \| \
bogdanm	0:9b334a45a8ff	242	RCC_PERIPHCLK_LCD))
bogdanm	0:9b334a45a8ff	243	#endif
bogdanm	0:9b334a45a8ff	244
bogdanm	0:9b334a45a8ff	245	#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	246
bogdanm	0:9b334a45a8ff	247	#if !defined(STM32L031xx) && !defined(STM32L041xx)
bogdanm	0:9b334a45a8ff	248	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	249	#endif
bogdanm	0:9b334a45a8ff	250	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	251	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	252	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	253	#if !defined(STM32L031xx) && !defined(STM32L041xx)
bogdanm	0:9b334a45a8ff	254	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	255	#endif
bogdanm	0:9b334a45a8ff	256	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	257	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
bogdanm	0:9b334a45a8ff	258	#if defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	259	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
bogdanm	0:9b334a45a8ff	260	#endif
bogdanm	0:9b334a45a8ff	261
bogdanm	0:9b334a45a8ff	262	#if defined(STM32L031xx) \|\| defined(STM32L041xx)
bogdanm	0:9b334a45a8ff	263	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
bogdanm	0:9b334a45a8ff	264	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_RTC ))
bogdanm	0:9b334a45a8ff	265	#elif defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	0:9b334a45a8ff	266	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
bogdanm	0:9b334a45a8ff	267	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
bogdanm	0:9b334a45a8ff	268	RCC_PERIPHCLK_LPTIM1))
bogdanm	0:9b334a45a8ff	269	#elif defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	270	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
bogdanm	0:9b334a45a8ff	271	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
bogdanm	0:9b334a45a8ff	272	RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3))
bogdanm	0:9b334a45a8ff	273	#endif
bogdanm	0:9b334a45a8ff	274
bogdanm	0:9b334a45a8ff	275	#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	276	/**
bogdanm	0:9b334a45a8ff	277	* @}
bogdanm	0:9b334a45a8ff	278	*/
bogdanm	0:9b334a45a8ff	279
bogdanm	0:9b334a45a8ff	280	/** @defgroup RCCEx_USART1_Clock_Source
bogdanm	0:9b334a45a8ff	281	* @{
bogdanm	0:9b334a45a8ff	282	*/
bogdanm	0:9b334a45a8ff	283	#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	284	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
bogdanm	0:9b334a45a8ff	285	#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
bogdanm	0:9b334a45a8ff	286	#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 \| RCC_CCIPR_USART1SEL_1)
bogdanm	0:9b334a45a8ff	287	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
bogdanm	0:9b334a45a8ff	288	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	289	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	290	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	291	/**
bogdanm	0:9b334a45a8ff	292	* @}
bogdanm	0:9b334a45a8ff	293	*/
bogdanm	0:9b334a45a8ff	294
bogdanm	0:9b334a45a8ff	295	/** @defgroup RCCEx_USART2_Clock_Source
bogdanm	0:9b334a45a8ff	296	* @{
bogdanm	0:9b334a45a8ff	297	*/
bogdanm	0:9b334a45a8ff	298	#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	299	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
bogdanm	0:9b334a45a8ff	300	#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
bogdanm	0:9b334a45a8ff	301	#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 \| RCC_CCIPR_USART2SEL_1)
bogdanm	0:9b334a45a8ff	302	#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	303	((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	304	((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	305	((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	306	/**
bogdanm	0:9b334a45a8ff	307	* @}
bogdanm	0:9b334a45a8ff	308	*/
bogdanm	0:9b334a45a8ff	309
bogdanm	0:9b334a45a8ff	310	/** @defgroup RCCEx_LPUART_Clock_Source
bogdanm	0:9b334a45a8ff	311	* @{
bogdanm	0:9b334a45a8ff	312	*/
bogdanm	0:9b334a45a8ff	313	#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	314	#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
bogdanm	0:9b334a45a8ff	315	#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
bogdanm	0:9b334a45a8ff	316	#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 \| RCC_CCIPR_LPUART1SEL_1)
bogdanm	0:9b334a45a8ff	317	#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	318	((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	319	((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	320	((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	321	/**
bogdanm	0:9b334a45a8ff	322	* @}
bogdanm	0:9b334a45a8ff	323	*/
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	/** @defgroup RCCEx_I2C1_Clock_Source
bogdanm	0:9b334a45a8ff	326	* @{
bogdanm	0:9b334a45a8ff	327	*/
bogdanm	0:9b334a45a8ff	328	#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	329	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
bogdanm	0:9b334a45a8ff	330	#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
bogdanm	0:9b334a45a8ff	331	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	332	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
bogdanm	0:9b334a45a8ff	333	((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	334	/**
bogdanm	0:9b334a45a8ff	335	* @}
bogdanm	0:9b334a45a8ff	336	*/
bogdanm	0:9b334a45a8ff	337
bogdanm	0:9b334a45a8ff	338	#if defined(STM32L071xx) \|\| defined(STM32L072xx) \|\| defined(STM32L073xx)\|\| defined(STM32L081xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	339
bogdanm	0:9b334a45a8ff	340	/** @defgroup RCCEx_I2C3_Clock_Source
bogdanm	0:9b334a45a8ff	341	* @{
bogdanm	0:9b334a45a8ff	342	*/
bogdanm	0:9b334a45a8ff	343	#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	344	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
bogdanm	0:9b334a45a8ff	345	#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
bogdanm	0:9b334a45a8ff	346	#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	347	((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
bogdanm	0:9b334a45a8ff	348	((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	349	#endif /* defined(STM32L071xx) \|\| defined(STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L081xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) */
bogdanm	0:9b334a45a8ff	350
bogdanm	0:9b334a45a8ff	351	/**
bogdanm	0:9b334a45a8ff	352	* @}
bogdanm	0:9b334a45a8ff	353	*/
bogdanm	0:9b334a45a8ff	354
bogdanm	0:9b334a45a8ff	355	/** @defgroup RCCEx_TIM_PRescaler_Selection
bogdanm	0:9b334a45a8ff	356	* @{
bogdanm	0:9b334a45a8ff	357	*/
bogdanm	0:9b334a45a8ff	358	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	359	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	360	/**
bogdanm	0:9b334a45a8ff	361	* @}
bogdanm	0:9b334a45a8ff	362	*/
bogdanm	0:9b334a45a8ff	363
bogdanm	0:9b334a45a8ff	364	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	365	/** @defgroup RCCEx_USB_Clock_Source
bogdanm	0:9b334a45a8ff	366	* @{
bogdanm	0:9b334a45a8ff	367	*/
bogdanm	0:9b334a45a8ff	368	#define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
bogdanm	0:9b334a45a8ff	369	#define RCC_USBCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	#define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) \|\| \
bogdanm	0:9b334a45a8ff	372	((__SOURCE__) == RCC_USBCLKSOURCE_PLLCLK))
bogdanm	0:9b334a45a8ff	373	/**
bogdanm	0:9b334a45a8ff	374	* @}
bogdanm	0:9b334a45a8ff	375	*/
bogdanm	0:9b334a45a8ff	376
bogdanm	0:9b334a45a8ff	377	/** @defgroup RCCEx_RNG_Clock_Source
bogdanm	0:9b334a45a8ff	378	* @{
bogdanm	0:9b334a45a8ff	379	*/
bogdanm	0:9b334a45a8ff	380	#define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
bogdanm	0:9b334a45a8ff	381	#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	382
bogdanm	0:9b334a45a8ff	383	#define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) \|\| \
bogdanm	0:9b334a45a8ff	384	((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
bogdanm	0:9b334a45a8ff	385	/**
bogdanm	0:9b334a45a8ff	386	* @}
bogdanm	0:9b334a45a8ff	387	*/
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	/** @defgroup RCCEx_HSI48M_Clock_Source
bogdanm	0:9b334a45a8ff	390	* @{
bogdanm	0:9b334a45a8ff	391	*/
bogdanm	0:9b334a45a8ff	392	#define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF
bogdanm	0:9b334a45a8ff	393
bogdanm	0:9b334a45a8ff	394	#define RCC_HSI48M_PLL ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	395	#define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
bogdanm	0:9b334a45a8ff	396
bogdanm	0:9b334a45a8ff	397	#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) \|\| ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
bogdanm	0:9b334a45a8ff	398
bogdanm	0:9b334a45a8ff	399	/**
bogdanm	0:9b334a45a8ff	400	* @}
bogdanm	0:9b334a45a8ff	401	*/
bogdanm	0:9b334a45a8ff	402	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	403
bogdanm	0:9b334a45a8ff	404	/** @defgroup RCC_HSI_Config
bogdanm	0:9b334a45a8ff	405	* @{
bogdanm	0:9b334a45a8ff	406	*/
bogdanm	0:9b334a45a8ff	407	#define RCC_HSI_OFF ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	408	#define RCC_HSI_ON RCC_CR_HSION
bogdanm	0:9b334a45a8ff	409	#define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN \| RCC_CR_HSION)
bogdanm	0:9b334a45a8ff	410	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	411	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	412	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	413	#define RCC_HSI_OUTEN RCC_CR_HSIOUTEN
bogdanm	0:9b334a45a8ff	414
bogdanm	0:9b334a45a8ff	415	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
bogdanm	0:9b334a45a8ff	416	((__HSI__) == RCC_HSI_DIV4) \|\| ((__HSI__) == RCC_HSI_OUTEN ))
bogdanm	0:9b334a45a8ff	417	#else
bogdanm	0:9b334a45a8ff	418	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
bogdanm	0:9b334a45a8ff	419	((__HSI__) == RCC_HSI_DIV4))
bogdanm	0:9b334a45a8ff	420	#endif
bogdanm	0:9b334a45a8ff	421
bogdanm	0:9b334a45a8ff	422	/**
bogdanm	0:9b334a45a8ff	423	* @}
bogdanm	0:9b334a45a8ff	424	*/
bogdanm	0:9b334a45a8ff	425
bogdanm	0:9b334a45a8ff	426	/** @defgroup RCCEx_LPTIM1_Clock_Source
bogdanm	0:9b334a45a8ff	427	* @{
bogdanm	0:9b334a45a8ff	428	*/
bogdanm	0:9b334a45a8ff	429	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	430	#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
bogdanm	0:9b334a45a8ff	431	#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
bogdanm	0:9b334a45a8ff	432	#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
bogdanm	0:9b334a45a8ff	433
bogdanm	0:9b334a45a8ff	434	#define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
bogdanm	0:9b334a45a8ff	435	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	436	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	437	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
bogdanm	0:9b334a45a8ff	438	/**
bogdanm	0:9b334a45a8ff	439	* @}
bogdanm	0:9b334a45a8ff	440	*/
bogdanm	0:9b334a45a8ff	441
bogdanm	0:9b334a45a8ff	442	/** @defgroup RCCEx_StopWakeUp_Clock
bogdanm	0:9b334a45a8ff	443	* @{
bogdanm	0:9b334a45a8ff	444	*/
bogdanm	0:9b334a45a8ff	445
bogdanm	0:9b334a45a8ff	446	#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00)
bogdanm	0:9b334a45a8ff	447	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
bogdanm	0:9b334a45a8ff	448
bogdanm	0:9b334a45a8ff	449	#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) \|\| \
bogdanm	0:9b334a45a8ff	450	((__SOURCE__) == RCC_StopWakeUpClock_HSI))
bogdanm	0:9b334a45a8ff	451	/**
bogdanm	0:9b334a45a8ff	452	* @}
bogdanm	0:9b334a45a8ff	453	*/
bogdanm	0:9b334a45a8ff	454
bogdanm	0:9b334a45a8ff	455	/** @defgroup RCCEx_LSEDrive_Configuration
bogdanm	0:9b334a45a8ff	456	* @{
bogdanm	0:9b334a45a8ff	457	*/
bogdanm	0:9b334a45a8ff	458
bogdanm	0:9b334a45a8ff	459	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	460	#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
bogdanm	0:9b334a45a8ff	461	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
bogdanm	0:9b334a45a8ff	462	#define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
bogdanm	0:9b334a45a8ff	463	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
bogdanm	0:9b334a45a8ff	464	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
bogdanm	0:9b334a45a8ff	465	/**
bogdanm	0:9b334a45a8ff	466	* @}
bogdanm	0:9b334a45a8ff	467	*/
bogdanm	0:9b334a45a8ff	468
bogdanm	0:9b334a45a8ff	469	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	470	/** @defgroup RCCEx_CRS_SynchroSource
bogdanm	0:9b334a45a8ff	471	* @{
bogdanm	0:9b334a45a8ff	472	*/
bogdanm	0:9b334a45a8ff	473	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal source GPIO /
bogdanm	0:9b334a45a8ff	474	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
bogdanm	0:9b334a45a8ff	475	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
bogdanm	0:9b334a45a8ff	476
bogdanm	0:9b334a45a8ff	477	#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
bogdanm	0:9b334a45a8ff	478	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) \|\|\
bogdanm	0:9b334a45a8ff	479	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
bogdanm	0:9b334a45a8ff	480	/**
bogdanm	0:9b334a45a8ff	481	* @}
bogdanm	0:9b334a45a8ff	482	*/
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	/** @defgroup RCCEx_CRS_SynchroDivider
bogdanm	0:9b334a45a8ff	485	* @{
bogdanm	0:9b334a45a8ff	486	*/
bogdanm	0:9b334a45a8ff	487	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
bogdanm	0:9b334a45a8ff	488	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
bogdanm	0:9b334a45a8ff	489	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
bogdanm	0:9b334a45a8ff	490	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
bogdanm	0:9b334a45a8ff	491	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
bogdanm	0:9b334a45a8ff	492	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
bogdanm	0:9b334a45a8ff	493	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
bogdanm	0:9b334a45a8ff	494	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
bogdanm	0:9b334a45a8ff	495
bogdanm	0:9b334a45a8ff	496	#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV2) \|\|\
bogdanm	0:9b334a45a8ff	497	((__DIV__) == RCC_CRS_SYNC_DIV4) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	498	((__DIV__) == RCC_CRS_SYNC_DIV16) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV32) \|\| \
bogdanm	0:9b334a45a8ff	499	((__DIV__) == RCC_CRS_SYNC_DIV64) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV128))
bogdanm	0:9b334a45a8ff	500	/**
bogdanm	0:9b334a45a8ff	501	* @}
bogdanm	0:9b334a45a8ff	502	*/
bogdanm	0:9b334a45a8ff	503
bogdanm	0:9b334a45a8ff	504	/** @defgroup RCCEx_CRS_SynchroPolarity
bogdanm	0:9b334a45a8ff	505	* @{
bogdanm	0:9b334a45a8ff	506	*/
bogdanm	0:9b334a45a8ff	507	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
bogdanm	0:9b334a45a8ff	508	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
bogdanm	0:9b334a45a8ff	509
bogdanm	0:9b334a45a8ff	510	#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	511	((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
bogdanm	0:9b334a45a8ff	512	/**
bogdanm	0:9b334a45a8ff	513	* @}
bogdanm	0:9b334a45a8ff	514	*/
bogdanm	0:9b334a45a8ff	515
bogdanm	0:9b334a45a8ff	516	/** @defgroup RCCEx_CRS_ReloadValueDefault
bogdanm	0:9b334a45a8ff	517	* @{
bogdanm	0:9b334a45a8ff	518	*/
bogdanm	0:9b334a45a8ff	519	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
bogdanm	0:9b334a45a8ff	520	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
bogdanm	0:9b334a45a8ff	521
bogdanm	0:9b334a45a8ff	522	#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
bogdanm	0:9b334a45a8ff	523	/**
bogdanm	0:9b334a45a8ff	524	* @}
bogdanm	0:9b334a45a8ff	525	*/
bogdanm	0:9b334a45a8ff	526
bogdanm	0:9b334a45a8ff	527	/** @defgroup RCCEx_CRS_ErrorLimitDefault
bogdanm	0:9b334a45a8ff	528	* @{
bogdanm	0:9b334a45a8ff	529	*/
bogdanm	0:9b334a45a8ff	530	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
bogdanm	0:9b334a45a8ff	531
bogdanm	0:9b334a45a8ff	532	#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
bogdanm	0:9b334a45a8ff	533	/**
bogdanm	0:9b334a45a8ff	534	* @}
bogdanm	0:9b334a45a8ff	535	*/
bogdanm	0:9b334a45a8ff	536
bogdanm	0:9b334a45a8ff	537	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault
bogdanm	0:9b334a45a8ff	538	* @{
bogdanm	0:9b334a45a8ff	539	*/
bogdanm	0:9b334a45a8ff	540	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
bogdanm	0:9b334a45a8ff	541	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
bogdanm	0:9b334a45a8ff	542	corresponds to a higher output frequency */
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
bogdanm	0:9b334a45a8ff	545	/**
bogdanm	0:9b334a45a8ff	546	* @}
bogdanm	0:9b334a45a8ff	547	*/
bogdanm	0:9b334a45a8ff	548
bogdanm	0:9b334a45a8ff	549	/** @defgroup RCCEx_CRS_FreqErrorDirection
bogdanm	0:9b334a45a8ff	550	* @{
bogdanm	0:9b334a45a8ff	551	*/
bogdanm	0:9b334a45a8ff	552	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
bogdanm	0:9b334a45a8ff	553	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
bogdanm	0:9b334a45a8ff	554
bogdanm	0:9b334a45a8ff	555	#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) \|\| \
bogdanm	0:9b334a45a8ff	556	((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
bogdanm	0:9b334a45a8ff	557	/**
bogdanm	0:9b334a45a8ff	558	* @}
bogdanm	0:9b334a45a8ff	559	*/
bogdanm	0:9b334a45a8ff	560
bogdanm	0:9b334a45a8ff	561	/** @defgroup RCCEx_CRS_Interrupt_Sources
bogdanm	0:9b334a45a8ff	562	* @{
bogdanm	0:9b334a45a8ff	563	*/
bogdanm	0:9b334a45a8ff	564	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
bogdanm	0:9b334a45a8ff	565	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
bogdanm	0:9b334a45a8ff	566	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
bogdanm	0:9b334a45a8ff	567	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
bogdanm	0:9b334a45a8ff	568	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	0:9b334a45a8ff	569	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	0:9b334a45a8ff	570	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	/**
bogdanm	0:9b334a45a8ff	573	* @}
bogdanm	0:9b334a45a8ff	574	*/
bogdanm	0:9b334a45a8ff	575
bogdanm	0:9b334a45a8ff	576	/** @defgroup RCCEx_CRS_Flags
bogdanm	0:9b334a45a8ff	577	* @{
bogdanm	0:9b334a45a8ff	578	*/
bogdanm	0:9b334a45a8ff	579	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
bogdanm	0:9b334a45a8ff	580	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
bogdanm	0:9b334a45a8ff	581	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
bogdanm	0:9b334a45a8ff	582	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
bogdanm	0:9b334a45a8ff	583	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	0:9b334a45a8ff	584	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	0:9b334a45a8ff	585	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	0:9b334a45a8ff	586
bogdanm	0:9b334a45a8ff	587	/**
bogdanm	0:9b334a45a8ff	588	* @}
bogdanm	0:9b334a45a8ff	589	*/
bogdanm	0:9b334a45a8ff	590
bogdanm	0:9b334a45a8ff	591	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	592	/**
bogdanm	0:9b334a45a8ff	593	* @}
bogdanm	0:9b334a45a8ff	594	*/
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	/* Exported macro ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	597	/** @defgroup RCCEx_Exported_Macros RCC Ex Exported Macros
bogdanm	0:9b334a45a8ff	598	* @{
bogdanm	0:9b334a45a8ff	599	*/
bogdanm	0:9b334a45a8ff	600
bogdanm	0:9b334a45a8ff	601	/** @brief Enable or disable the AHB peripheral clock.
bogdanm	0:9b334a45a8ff	602	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	603	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	604	* using it.
bogdanm	0:9b334a45a8ff	605	*/
bogdanm	0:9b334a45a8ff	606
bogdanm	0:9b334a45a8ff	607	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	608	#define __HAL_RCC_AES_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRYPEN))
bogdanm	0:9b334a45a8ff	609	#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN))
bogdanm	0:9b334a45a8ff	610	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	611
bogdanm	0:9b334a45a8ff	612	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	613	#define __HAL_RCC_TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
bogdanm	0:9b334a45a8ff	614	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN))
bogdanm	0:9b334a45a8ff	615
bogdanm	0:9b334a45a8ff	616	#define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_RNGEN))
bogdanm	0:9b334a45a8ff	617	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN))
bogdanm	0:9b334a45a8ff	618	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	619
bogdanm	0:9b334a45a8ff	620
bogdanm	0:9b334a45a8ff	621	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	622	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	623	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	624	/** @brief Enable or disable the IOPORT peripheral clock.
bogdanm	0:9b334a45a8ff	625	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	626	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	627	* using it.
bogdanm	0:9b334a45a8ff	628	*/
bogdanm	0:9b334a45a8ff	629	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	630	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	631	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
bogdanm	0:9b334a45a8ff	632	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	633	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
bogdanm	0:9b334a45a8ff	634	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	635	} while(0)
bogdanm	0:9b334a45a8ff	636
bogdanm	0:9b334a45a8ff	637	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOEEN))
bogdanm	0:9b334a45a8ff	638
bogdanm	0:9b334a45a8ff	639	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	640	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	641	/* STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	642
bogdanm	0:9b334a45a8ff	643	/** @brief Enable or disable the APB1 peripheral clock.
bogdanm	0:9b334a45a8ff	644	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	645	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	646	* using it.
bogdanm	0:9b334a45a8ff	647	*/
bogdanm	0:9b334a45a8ff	648
bogdanm	0:9b334a45a8ff	649	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	650	#define __HAL_RCC_USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
bogdanm	0:9b334a45a8ff	651	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN))
bogdanm	0:9b334a45a8ff	652
bogdanm	0:9b334a45a8ff	653	#define __HAL_RCC_CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
bogdanm	0:9b334a45a8ff	654	#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
bogdanm	0:9b334a45a8ff	655	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	656
bogdanm	0:9b334a45a8ff	657
bogdanm	0:9b334a45a8ff	658	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	659	#define __HAL_RCC_LCD_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LCDEN))
bogdanm	0:9b334a45a8ff	660	#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN))
bogdanm	0:9b334a45a8ff	661	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	662
bogdanm	0:9b334a45a8ff	663	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	0:9b334a45a8ff	664	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	0:9b334a45a8ff	665	defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	0:9b334a45a8ff	666	#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
bogdanm	0:9b334a45a8ff	667	#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
bogdanm	0:9b334a45a8ff	668	#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
bogdanm	0:9b334a45a8ff	669	#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
bogdanm	0:9b334a45a8ff	670	#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPUART1EN))
bogdanm	0:9b334a45a8ff	671	#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
bogdanm	0:9b334a45a8ff	672	#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
bogdanm	0:9b334a45a8ff	673	#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
bogdanm	0:9b334a45a8ff	674	#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	675
bogdanm	0:9b334a45a8ff	676	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
bogdanm	0:9b334a45a8ff	677	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
bogdanm	0:9b334a45a8ff	678	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
bogdanm	0:9b334a45a8ff	679	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
bogdanm	0:9b334a45a8ff	680	#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
bogdanm	0:9b334a45a8ff	681	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
bogdanm	0:9b334a45a8ff	682	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
bogdanm	0:9b334a45a8ff	683	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
bogdanm	0:9b334a45a8ff	684	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	685	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	0:9b334a45a8ff	686	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	0:9b334a45a8ff	687	/* STM32L053xx \|\| STM32L063xx \|\| */
bogdanm	0:9b334a45a8ff	688
bogdanm	0:9b334a45a8ff	689	#if defined(STM32L031xx) \|\| defined(STM32L041xx)
bogdanm	0:9b334a45a8ff	690	#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
bogdanm	0:9b334a45a8ff	691	#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
bogdanm	0:9b334a45a8ff	692	#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPUART1EN))
bogdanm	0:9b334a45a8ff	693	#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
bogdanm	0:9b334a45a8ff	694	#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	695
bogdanm	0:9b334a45a8ff	696	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
bogdanm	0:9b334a45a8ff	697	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
bogdanm	0:9b334a45a8ff	698	#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
bogdanm	0:9b334a45a8ff	699	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
bogdanm	0:9b334a45a8ff	700	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	701	#endif /* STM32L031xx \|\| STM32L041xx \|\| */
bogdanm	0:9b334a45a8ff	702
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	705	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	706	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	707	#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
bogdanm	0:9b334a45a8ff	708	#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
bogdanm	0:9b334a45a8ff	709	#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
bogdanm	0:9b334a45a8ff	710	#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
bogdanm	0:9b334a45a8ff	711	#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
bogdanm	0:9b334a45a8ff	712	#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
bogdanm	0:9b334a45a8ff	713	#define __HAL_RCC_USART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART4EN))
bogdanm	0:9b334a45a8ff	714	#define __HAL_RCC_USART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART5EN))
bogdanm	0:9b334a45a8ff	715	#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPUART1EN))
bogdanm	0:9b334a45a8ff	716	#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
bogdanm	0:9b334a45a8ff	717	#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
bogdanm	0:9b334a45a8ff	718	#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
bogdanm	0:9b334a45a8ff	719	#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
bogdanm	0:9b334a45a8ff	720	#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	721
bogdanm	0:9b334a45a8ff	722	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
bogdanm	0:9b334a45a8ff	723	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM3EN))
bogdanm	0:9b334a45a8ff	724	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
bogdanm	0:9b334a45a8ff	725	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM7EN))
bogdanm	0:9b334a45a8ff	726	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
bogdanm	0:9b334a45a8ff	727	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
bogdanm	0:9b334a45a8ff	728	#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART4EN))
bogdanm	0:9b334a45a8ff	729	#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART5EN))
bogdanm	0:9b334a45a8ff	730	#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
bogdanm	0:9b334a45a8ff	731	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
bogdanm	0:9b334a45a8ff	732	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
bogdanm	0:9b334a45a8ff	733	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C3EN))
bogdanm	0:9b334a45a8ff	734	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
bogdanm	0:9b334a45a8ff	735	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
bogdanm	0:9b334a45a8ff	736	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	737	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	738	/* STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	739
bogdanm	0:9b334a45a8ff	740	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	741	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	742	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx) \|\| \
bogdanm	0:9b334a45a8ff	743	defined(STM32L031xx) \|\| defined(STM32L041xx)
bogdanm	0:9b334a45a8ff	744
bogdanm	0:9b334a45a8ff	745	/** @brief Enable or disable the APB2 peripheral clock.
bogdanm	0:9b334a45a8ff	746	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	747	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	748	* using it.
bogdanm	0:9b334a45a8ff	749	*/
bogdanm	0:9b334a45a8ff	750	#define __HAL_RCC_TIM21_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM21EN))
bogdanm	0:9b334a45a8ff	751	#define __HAL_RCC_TIM22_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM22EN))
bogdanm	0:9b334a45a8ff	752	#define __HAL_RCC_FIREWALL_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_MIFIEN))
bogdanm	0:9b334a45a8ff	753	#define __HAL_RCC_ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
bogdanm	0:9b334a45a8ff	754	#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
bogdanm	0:9b334a45a8ff	755	#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
bogdanm	0:9b334a45a8ff	756
bogdanm	0:9b334a45a8ff	757	#define __HAL_RCC_TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN))
bogdanm	0:9b334a45a8ff	758	#define __HAL_RCC_TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN))
bogdanm	0:9b334a45a8ff	759	#define __HAL_RCC_FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN))
bogdanm	0:9b334a45a8ff	760	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN))
bogdanm	0:9b334a45a8ff	761	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN))
bogdanm	0:9b334a45a8ff	762	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN))
bogdanm	0:9b334a45a8ff	763	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	764	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	765	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	766
bogdanm	0:9b334a45a8ff	767	/** @brief Force or release AHB peripheral reset.
bogdanm	0:9b334a45a8ff	768	*/
bogdanm	0:9b334a45a8ff	769	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	770	#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRYPRST))
bogdanm	0:9b334a45a8ff	771	#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST))
bogdanm	0:9b334a45a8ff	772	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	773
bogdanm	0:9b334a45a8ff	774	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	775	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
bogdanm	0:9b334a45a8ff	776	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST))
bogdanm	0:9b334a45a8ff	777	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_RNGRST))
bogdanm	0:9b334a45a8ff	778	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST))
bogdanm	0:9b334a45a8ff	779	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	780
bogdanm	0:9b334a45a8ff	781	/** @brief Force or release IOPORT peripheral reset.
bogdanm	0:9b334a45a8ff	782	*/
bogdanm	0:9b334a45a8ff	783	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	784	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	785	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	786	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOERST))
bogdanm	0:9b334a45a8ff	787
bogdanm	0:9b334a45a8ff	788	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOERST))
bogdanm	0:9b334a45a8ff	789
bogdanm	0:9b334a45a8ff	790	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	791	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	792	/* STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	793
bogdanm	0:9b334a45a8ff	794	/** @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	795	*/
bogdanm	0:9b334a45a8ff	796
bogdanm	0:9b334a45a8ff	797	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	0:9b334a45a8ff	798	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	0:9b334a45a8ff	799	defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	0:9b334a45a8ff	800	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	801	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	802	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
bogdanm	0:9b334a45a8ff	803	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	804	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	0:9b334a45a8ff	805	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	806	#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPUART1RST))
bogdanm	0:9b334a45a8ff	807	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	0:9b334a45a8ff	808	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	809
bogdanm	0:9b334a45a8ff	810	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	811	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	812	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
bogdanm	0:9b334a45a8ff	813	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	814	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
bogdanm	0:9b334a45a8ff	815	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	816	#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
bogdanm	0:9b334a45a8ff	817	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
bogdanm	0:9b334a45a8ff	818	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	819	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	0:9b334a45a8ff	820	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	0:9b334a45a8ff	821	/* STM32L053xx \|\| STM32L063xx */
bogdanm	0:9b334a45a8ff	822	#if defined(STM32L031xx) \|\| defined(STM32L041xx)
bogdanm	0:9b334a45a8ff	823	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	824	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
bogdanm	0:9b334a45a8ff	825	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	826	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	827	#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPUART1RST))
bogdanm	0:9b334a45a8ff	828
bogdanm	0:9b334a45a8ff	829	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	830	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
bogdanm	0:9b334a45a8ff	831	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	832	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	833	#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
bogdanm	0:9b334a45a8ff	834	#endif /* STM32L031xx \|\| STM32L041xx \|\| */
bogdanm	0:9b334a45a8ff	835
bogdanm	0:9b334a45a8ff	836	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	837	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	838	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	839	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	840	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	0:9b334a45a8ff	841	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	842	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	843	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
bogdanm	0:9b334a45a8ff	844	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	845	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	0:9b334a45a8ff	846	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
bogdanm	0:9b334a45a8ff	847	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	848	#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
bogdanm	0:9b334a45a8ff	849	#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
bogdanm	0:9b334a45a8ff	850	#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPUART1RST))
bogdanm	0:9b334a45a8ff	851	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	0:9b334a45a8ff	852	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	855	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM3RST))
bogdanm	0:9b334a45a8ff	856	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	857	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	858	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
bogdanm	0:9b334a45a8ff	859	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
bogdanm	0:9b334a45a8ff	860	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
bogdanm	0:9b334a45a8ff	861	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C3RST))
bogdanm	0:9b334a45a8ff	862	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	863	#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART4RST))
bogdanm	0:9b334a45a8ff	864	#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART5RST))
bogdanm	0:9b334a45a8ff	865	#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
bogdanm	0:9b334a45a8ff	866	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
bogdanm	0:9b334a45a8ff	867	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	868	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	869	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	870	/* STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	0:9b334a45a8ff	871
bogdanm	0:9b334a45a8ff	872	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	873	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
bogdanm	0:9b334a45a8ff	874	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST))
bogdanm	0:9b334a45a8ff	875	#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
bogdanm	0:9b334a45a8ff	876	#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
bogdanm	0:9b334a45a8ff	877	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	878
bogdanm	0:9b334a45a8ff	879	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	880	#define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LCDRST))
bogdanm	0:9b334a45a8ff	881	#define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST))
bogdanm	0:9b334a45a8ff	882	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	883
bogdanm	0:9b334a45a8ff	884	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	885	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	886	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	887	/** @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	888	*/
bogdanm	0:9b334a45a8ff	889	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	0:9b334a45a8ff	890	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
bogdanm	0:9b334a45a8ff	891	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	0:9b334a45a8ff	892	#define __HAL_RCC_TIM21_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM21RST))
bogdanm	0:9b334a45a8ff	893	#define __HAL_RCC_TIM22_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM22RST))
bogdanm	0:9b334a45a8ff	894
bogdanm	0:9b334a45a8ff	895	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST))
bogdanm	0:9b334a45a8ff	896	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST))
bogdanm	0:9b334a45a8ff	897	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST))
bogdanm	0:9b334a45a8ff	898	#define __HAL_RCC_TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST))
bogdanm	0:9b334a45a8ff	899	#define __HAL_RCC_TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST))
bogdanm	0:9b334a45a8ff	900	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	901	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	902	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	0:9b334a45a8ff	903
bogdanm	0:9b334a45a8ff	904	/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	905	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	906	* power consumption.
bogdanm	0:9b334a45a8ff	907	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	908	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	909	*/
bogdanm	0:9b334a45a8ff	910
bogdanm	0:9b334a45a8ff	911	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	912	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_TSCSMEN))
bogdanm	0:9b334a45a8ff	913	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_RNGSMEN))
bogdanm	0:9b334a45a8ff	914	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN))
bogdanm	0:9b334a45a8ff	915	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN))
bogdanm	0:9b334a45a8ff	916	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	917
bogdanm	0:9b334a45a8ff	918	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	919	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBSMENR_CRYPSMEN))
bogdanm	0:9b334a45a8ff	920	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN))
bogdanm	0:9b334a45a8ff	921	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	924	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	925	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	926	/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	927	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	928	* power consumption.
bogdanm	0:9b334a45a8ff	929	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	930	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	931	*/
bogdanm	0:9b334a45a8ff	932
bogdanm	0:9b334a45a8ff	933	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOESMEN))
bogdanm	0:9b334a45a8ff	934	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOESMEN))
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	937	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	938	/* STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	0:9b334a45a8ff	939
bogdanm	0:9b334a45a8ff	940	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	941	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	942	* power consumption.
bogdanm	0:9b334a45a8ff	943	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	944	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	945	*/
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	0:9b334a45a8ff	948	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	0:9b334a45a8ff	949	defined(STM32L051xx) \|\| defined(STM32L061xx)
bogdanm	0:9b334a45a8ff	950	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM2SMEN))
bogdanm	0:9b334a45a8ff	951	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM6SMEN))
bogdanm	0:9b334a45a8ff	952	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_SPI2SMEN))
bogdanm	0:9b334a45a8ff	953	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART2SMEN))
bogdanm	0:9b334a45a8ff	954	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPUART1SMEN))
bogdanm	0:9b334a45a8ff	955	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C1SMEN))
bogdanm	0:9b334a45a8ff	956	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C2SMEN))
bogdanm	0:9b334a45a8ff	957	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_DACSMEN))
bogdanm	0:9b334a45a8ff	958	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	0:9b334a45a8ff	959
bogdanm	0:9b334a45a8ff	960	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
bogdanm	0:9b334a45a8ff	961	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
bogdanm	0:9b334a45a8ff	962	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
bogdanm	0:9b334a45a8ff	963	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
bogdanm	0:9b334a45a8ff	964	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
bogdanm	0:9b334a45a8ff	965	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
bogdanm	0:9b334a45a8ff	966	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
bogdanm	0:9b334a45a8ff	967	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
bogdanm	0:9b334a45a8ff	968	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	0:9b334a45a8ff	969	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	0:9b334a45a8ff	970	/* STM32L052xx \|\| STM32L062xx \|\| */
bogdanm	0:9b334a45a8ff	971	/* STM32L053xx \|\| STM32L063xx */
bogdanm	0:9b334a45a8ff	972
bogdanm	0:9b334a45a8ff	973	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	974	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	975	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	976	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM2SMEN))
bogdanm	0:9b334a45a8ff	977	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM3SMEN))
bogdanm	0:9b334a45a8ff	978	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM6SMEN))
bogdanm	0:9b334a45a8ff	979	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM7SMEN))
bogdanm	0:9b334a45a8ff	980	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_SPI2SMEN))
bogdanm	0:9b334a45a8ff	981	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART2SMEN))
bogdanm	0:9b334a45a8ff	982	#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART4SMEN))
bogdanm	0:9b334a45a8ff	983	#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART5SMEN))
bogdanm	0:9b334a45a8ff	984	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPUART1SMEN))
bogdanm	0:9b334a45a8ff	985	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C1SMEN))
bogdanm	0:9b334a45a8ff	986	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C2SMEN))
bogdanm	0:9b334a45a8ff	987	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C3SMEN))
bogdanm	0:9b334a45a8ff	988	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_DACSMEN))
bogdanm	0:9b334a45a8ff	989	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
bogdanm	0:9b334a45a8ff	992	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM3SMEN))
bogdanm	0:9b334a45a8ff	993	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
bogdanm	0:9b334a45a8ff	994	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM7SMEN))
bogdanm	0:9b334a45a8ff	995	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
bogdanm	0:9b334a45a8ff	996	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
bogdanm	0:9b334a45a8ff	997	#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART4SMEN))
bogdanm	0:9b334a45a8ff	998	#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART5SMEN))
bogdanm	0:9b334a45a8ff	999	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
bogdanm	0:9b334a45a8ff	1000	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
bogdanm	0:9b334a45a8ff	1001	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
bogdanm	0:9b334a45a8ff	1002	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C3SMEN))
bogdanm	0:9b334a45a8ff	1003	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
bogdanm	0:9b334a45a8ff	1004	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	0:9b334a45a8ff	1005	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1006	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1007	/* STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	0:9b334a45a8ff	1008
bogdanm	0:9b334a45a8ff	1009	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1010	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USBSMEN))
bogdanm	0:9b334a45a8ff	1011	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN))
bogdanm	0:9b334a45a8ff	1012	#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_CRSSMEN))
bogdanm	0:9b334a45a8ff	1013	#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN))
bogdanm	0:9b334a45a8ff	1014	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	1015
bogdanm	0:9b334a45a8ff	1016	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
bogdanm	0:9b334a45a8ff	1017	#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LCDSMEN))
bogdanm	0:9b334a45a8ff	1018	#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN))
bogdanm	0:9b334a45a8ff	1019	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	1020
bogdanm	0:9b334a45a8ff	1021	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	1022	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	1023	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1024	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	0:9b334a45a8ff	1025	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	0:9b334a45a8ff	1026	* power consumption.
bogdanm	0:9b334a45a8ff	1027	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	0:9b334a45a8ff	1028	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	0:9b334a45a8ff	1029	*/
bogdanm	0:9b334a45a8ff	1030	#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_TIM21SMEN))
bogdanm	0:9b334a45a8ff	1031	#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_TIM22SMEN))
bogdanm	0:9b334a45a8ff	1032	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_ADC1SMEN))
bogdanm	0:9b334a45a8ff	1033	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_SPI1SMEN))
bogdanm	0:9b334a45a8ff	1034	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_USART1SMEN))
bogdanm	0:9b334a45a8ff	1035
bogdanm	0:9b334a45a8ff	1036	#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN))
bogdanm	0:9b334a45a8ff	1037	#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN))
bogdanm	0:9b334a45a8ff	1038	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN))
bogdanm	0:9b334a45a8ff	1039	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN))
bogdanm	0:9b334a45a8ff	1040	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN))
bogdanm	0:9b334a45a8ff	1041	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1042	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1043	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	0:9b334a45a8ff	1044
bogdanm	0:9b334a45a8ff	1045	/** @brief macro to configure the I2C1 clock (I2C1CLK).
bogdanm	0:9b334a45a8ff	1046	*
bogdanm	0:9b334a45a8ff	1047	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
bogdanm	0:9b334a45a8ff	1048	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1049	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1050	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1051	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1052	*/
bogdanm	0:9b334a45a8ff	1053	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
bogdanm	0:9b334a45a8ff	1054	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1CLKSource__))
bogdanm	0:9b334a45a8ff	1055
bogdanm	0:9b334a45a8ff	1056	/** @brief macro to get the I2C1 clock source.
bogdanm	0:9b334a45a8ff	1057	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1058	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1059	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1060	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	0:9b334a45a8ff	1061	*/
bogdanm	0:9b334a45a8ff	1062	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
bogdanm	0:9b334a45a8ff	1063
bogdanm	0:9b334a45a8ff	1064	#if defined (STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	1065	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	1066	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1067	/** @brief macro to configure the I2C3 clock (I2C3CLK).
bogdanm	0:9b334a45a8ff	1068	*
bogdanm	0:9b334a45a8ff	1069	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
bogdanm	0:9b334a45a8ff	1070	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1071	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
bogdanm	0:9b334a45a8ff	1072	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm	0:9b334a45a8ff	1073	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm	0:9b334a45a8ff	1074	*/
bogdanm	0:9b334a45a8ff	1075	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
bogdanm	0:9b334a45a8ff	1076	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3CLKSource__))
bogdanm	0:9b334a45a8ff	1077
bogdanm	0:9b334a45a8ff	1078	/** @brief macro to get the I2C3 clock source.
bogdanm	0:9b334a45a8ff	1079	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1080	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
bogdanm	0:9b334a45a8ff	1081	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm	0:9b334a45a8ff	1082	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm	0:9b334a45a8ff	1083	*/
bogdanm	0:9b334a45a8ff	1084	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
bogdanm	0:9b334a45a8ff	1085
bogdanm	0:9b334a45a8ff	1086	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1087	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1088	/* STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	0:9b334a45a8ff	1089
bogdanm	0:9b334a45a8ff	1090	/** @brief macro to configure the USART1 clock (USART1CLK).
bogdanm	0:9b334a45a8ff	1091	*
bogdanm	0:9b334a45a8ff	1092	* @param __USART1CLKSource__: specifies the USART1 clock source.
bogdanm	0:9b334a45a8ff	1093	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1094	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
bogdanm	0:9b334a45a8ff	1095	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	0:9b334a45a8ff	1096	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	0:9b334a45a8ff	1097	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	0:9b334a45a8ff	1098	*/
bogdanm	0:9b334a45a8ff	1099	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
bogdanm	0:9b334a45a8ff	1100	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1CLKSource__))
bogdanm	0:9b334a45a8ff	1101
bogdanm	0:9b334a45a8ff	1102	/** @brief macro to get the USART1 clock source.
bogdanm	0:9b334a45a8ff	1103	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1104	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
bogdanm	0:9b334a45a8ff	1105	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	0:9b334a45a8ff	1106	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	0:9b334a45a8ff	1107	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	0:9b334a45a8ff	1108	*/
bogdanm	0:9b334a45a8ff	1109	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
bogdanm	0:9b334a45a8ff	1110
bogdanm	0:9b334a45a8ff	1111	/** @brief macro to configure the USART2 clock (USART2CLK).
bogdanm	0:9b334a45a8ff	1112	*
bogdanm	0:9b334a45a8ff	1113	* @param __USART2CLKSource__: specifies the USART2 clock source.
bogdanm	0:9b334a45a8ff	1114	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1115	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	0:9b334a45a8ff	1116	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	0:9b334a45a8ff	1117	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	0:9b334a45a8ff	1118	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	0:9b334a45a8ff	1119	*/
bogdanm	0:9b334a45a8ff	1120	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
bogdanm	0:9b334a45a8ff	1121	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2CLKSource__))
bogdanm	0:9b334a45a8ff	1122
bogdanm	0:9b334a45a8ff	1123	/** @brief macro to get the USART2 clock source.
bogdanm	0:9b334a45a8ff	1124	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1125	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	0:9b334a45a8ff	1126	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	0:9b334a45a8ff	1127	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	0:9b334a45a8ff	1128	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	0:9b334a45a8ff	1129	*/
bogdanm	0:9b334a45a8ff	1130	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
bogdanm	0:9b334a45a8ff	1131
bogdanm	0:9b334a45a8ff	1132	/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
bogdanm	0:9b334a45a8ff	1133	*
bogdanm	0:9b334a45a8ff	1134	* @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
bogdanm	0:9b334a45a8ff	1135	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1136	* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1137	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1138	* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1139	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1140	*/
bogdanm	0:9b334a45a8ff	1141	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
bogdanm	0:9b334a45a8ff	1142	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
bogdanm	0:9b334a45a8ff	1143
bogdanm	0:9b334a45a8ff	1144	/** @brief macro to get the LPUART1 clock source.
bogdanm	0:9b334a45a8ff	1145	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1146	* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1147	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1148	* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1149	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1150	*/
bogdanm	0:9b334a45a8ff	1151	#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
bogdanm	0:9b334a45a8ff	1152
bogdanm	0:9b334a45a8ff	1153	/** @brief macro to configure the LPTIM1 clock (LPTIM1CLK).
bogdanm	0:9b334a45a8ff	1154	*
bogdanm	0:9b334a45a8ff	1155	* @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source.
bogdanm	0:9b334a45a8ff	1156	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1157	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	1158	* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	1159	* @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	1160	* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock
bogdanm	0:9b334a45a8ff	1161	*/
bogdanm	0:9b334a45a8ff	1162	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
bogdanm	0:9b334a45a8ff	1163	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
bogdanm	0:9b334a45a8ff	1164
bogdanm	0:9b334a45a8ff	1165	/** @brief macro to get the LPTIM1 clock source.
bogdanm	0:9b334a45a8ff	1166	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1167	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1168	* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1169	* @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1170	* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock
bogdanm	0:9b334a45a8ff	1171	*/
bogdanm	0:9b334a45a8ff	1172	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1175	/** @brief Macro to configure the USB clock (USBCLK).
bogdanm	0:9b334a45a8ff	1176	* @param __USBCLKSource__: specifies the USB clock source.
bogdanm	0:9b334a45a8ff	1177	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1178	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm	0:9b334a45a8ff	1179	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	0:9b334a45a8ff	1180	*/
bogdanm	0:9b334a45a8ff	1181	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm	0:9b334a45a8ff	1182	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__))
bogdanm	0:9b334a45a8ff	1183
bogdanm	0:9b334a45a8ff	1184	/** @brief Macro to get the USB clock source.
bogdanm	0:9b334a45a8ff	1185	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1186	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm	0:9b334a45a8ff	1187	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	0:9b334a45a8ff	1188	*/
bogdanm	0:9b334a45a8ff	1189	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
bogdanm	0:9b334a45a8ff	1190
bogdanm	0:9b334a45a8ff	1191	/** @brief Macro to configure the RNG clock (RNGCLK).
bogdanm	0:9b334a45a8ff	1192	* @param __RNGCLKSource__: specifies the USB clock source.
bogdanm	0:9b334a45a8ff	1193	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1194	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
bogdanm	0:9b334a45a8ff	1195	* @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
bogdanm	0:9b334a45a8ff	1196	*/
bogdanm	0:9b334a45a8ff	1197	#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
bogdanm	0:9b334a45a8ff	1198	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNGCLKSource__))
bogdanm	0:9b334a45a8ff	1199
bogdanm	0:9b334a45a8ff	1200	/** @brief Macro to get the RNG clock source.
bogdanm	0:9b334a45a8ff	1201	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1202	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
bogdanm	0:9b334a45a8ff	1203	* @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
bogdanm	0:9b334a45a8ff	1204	*/
bogdanm	0:9b334a45a8ff	1205	#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	/** @brief macro to select the HSI48M clock source
bogdanm	0:9b334a45a8ff	1208	* @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
bogdanm	0:9b334a45a8ff	1209	* __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
bogdanm	0:9b334a45a8ff	1210	*
bogdanm	0:9b334a45a8ff	1211	* @param __HSI48MCLKSource__: specifies the HSI48M clock source dedicated for
bogdanm	0:9b334a45a8ff	1212	* USB an RNG peripherals.
bogdanm	0:9b334a45a8ff	1213	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1214	* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
bogdanm	0:9b334a45a8ff	1215	* @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
bogdanm	0:9b334a45a8ff	1216	*/
bogdanm	0:9b334a45a8ff	1217	#define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \
bogdanm	0:9b334a45a8ff	1218	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__))
bogdanm	0:9b334a45a8ff	1219
bogdanm	0:9b334a45a8ff	1220	/** @brief macro to get the HSI48M clock source.
bogdanm	0:9b334a45a8ff	1221	* @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
bogdanm	0:9b334a45a8ff	1222	* __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
bogdanm	0:9b334a45a8ff	1223	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1224	* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
bogdanm	0:9b334a45a8ff	1225	* @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
bogdanm	0:9b334a45a8ff	1226	*/
bogdanm	0:9b334a45a8ff	1227	#define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
bogdanm	0:9b334a45a8ff	1228	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	0:9b334a45a8ff	1229
bogdanm	0:9b334a45a8ff	1230	/**
bogdanm	0:9b334a45a8ff	1231	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
bogdanm	0:9b334a45a8ff	1232	* in STOP mode to be quickly available as kernel clock for USART and I2C.
bogdanm	0:9b334a45a8ff	1233	* @note The Enable of this function has not effect on the HSION bit.
bogdanm	0:9b334a45a8ff	1234	* This parameter can be: ENABLE or DISABLE.
bogdanm	0:9b334a45a8ff	1235	* @retval None
bogdanm	0:9b334a45a8ff	1236	*/
bogdanm	0:9b334a45a8ff	1237	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
bogdanm	0:9b334a45a8ff	1238	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
bogdanm	0:9b334a45a8ff	1239
bogdanm	0:9b334a45a8ff	1240	/**
bogdanm	0:9b334a45a8ff	1241	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
bogdanm	0:9b334a45a8ff	1242	* @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
bogdanm	0:9b334a45a8ff	1243	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1244	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
bogdanm	0:9b334a45a8ff	1245	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
bogdanm	0:9b334a45a8ff	1246	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
bogdanm	0:9b334a45a8ff	1247	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
bogdanm	0:9b334a45a8ff	1248	* @retval None
bogdanm	0:9b334a45a8ff	1249	*/
bogdanm	0:9b334a45a8ff	1250	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDrive__) (MODIFY_REG(RCC->CSR,\
bogdanm	0:9b334a45a8ff	1251	RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDrive__) ))
bogdanm	0:9b334a45a8ff	1252
bogdanm	0:9b334a45a8ff	1253	/**
bogdanm	0:9b334a45a8ff	1254	* @brief Macro to configures the wake up from stop clock.
bogdanm	0:9b334a45a8ff	1255	* @param RCC_STOPWUCLK: specifies the clock source used after wake up from stop
bogdanm	0:9b334a45a8ff	1256	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1257	* @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
bogdanm	0:9b334a45a8ff	1258	* @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
bogdanm	0:9b334a45a8ff	1259	* @retval None
bogdanm	0:9b334a45a8ff	1260	*/
bogdanm	0:9b334a45a8ff	1261	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
bogdanm	0:9b334a45a8ff	1262	RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
bogdanm	0:9b334a45a8ff	1263
bogdanm	0:9b334a45a8ff	1264	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1265	/**
bogdanm	0:9b334a45a8ff	1266	* @brief Enables the specified CRS interrupts.
bogdanm	0:9b334a45a8ff	1267	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
bogdanm	0:9b334a45a8ff	1268	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1269	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	1270	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	1271	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	1272	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	1273	* @retval None
bogdanm	0:9b334a45a8ff	1274	*/
bogdanm	0:9b334a45a8ff	1275	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1276
bogdanm	0:9b334a45a8ff	1277	/**
bogdanm	0:9b334a45a8ff	1278	* @brief Disables the specified CRS interrupts.
bogdanm	0:9b334a45a8ff	1279	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
bogdanm	0:9b334a45a8ff	1280	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1281	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	1282	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	1283	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	1284	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	1285	* @retval None
bogdanm	0:9b334a45a8ff	1286	*/
bogdanm	0:9b334a45a8ff	1287	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	/** @brief Check the CRS interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	1290	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
bogdanm	0:9b334a45a8ff	1291	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1292	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	1293	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	1294	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	1295	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	1296	* @retval The new state of __INTERRUPT__ (SET or RESET).
bogdanm	0:9b334a45a8ff	1297	*/
bogdanm	0:9b334a45a8ff	1298	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
bogdanm	0:9b334a45a8ff	1299
bogdanm	0:9b334a45a8ff	1300	/** @brief Clear the CRS interrupt pending bits
bogdanm	0:9b334a45a8ff	1301	* bits to clear the selected interrupt pending bits.
bogdanm	0:9b334a45a8ff	1302	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	1303	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	1304	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	1305	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	1306	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	1307	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	1308	* @arg RCC_CRS_IT_TRIMOVF
bogdanm	0:9b334a45a8ff	1309	* @arg RCC_CRS_IT_SYNCERR
bogdanm	0:9b334a45a8ff	1310	* @arg RCC_CRS_IT_SYNCMISS
bogdanm	0:9b334a45a8ff	1311	*/
bogdanm	0:9b334a45a8ff	1312	/* CRS IT Error Mask */
bogdanm	0:9b334a45a8ff	1313	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
bogdanm	0:9b334a45a8ff	1314
bogdanm	0:9b334a45a8ff	1315	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	0:9b334a45a8ff	1316	(CRS->ICR = (__INTERRUPT__)))
bogdanm	0:9b334a45a8ff	1317
bogdanm	0:9b334a45a8ff	1318	/**
bogdanm	0:9b334a45a8ff	1319	* @brief Checks whether the specified CRS flag is set or not.
bogdanm	0:9b334a45a8ff	1320	* @param _FLAG_: specifies the flag to check.
bogdanm	0:9b334a45a8ff	1321	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1322	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	0:9b334a45a8ff	1323	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	0:9b334a45a8ff	1324	* @arg RCC_CRS_FLAG_ERR
bogdanm	0:9b334a45a8ff	1325	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	0:9b334a45a8ff	1326	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	0:9b334a45a8ff	1327	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	0:9b334a45a8ff	1328	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	0:9b334a45a8ff	1329	* @retval The new state of _FLAG_ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	1330	*/
bogdanm	0:9b334a45a8ff	1331	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
bogdanm	0:9b334a45a8ff	1332
bogdanm	0:9b334a45a8ff	1333	/**
bogdanm	0:9b334a45a8ff	1334	* @brief Clears the CRS specified FLAG.
bogdanm	0:9b334a45a8ff	1335	* @param _FLAG_: specifies the flag to clear.
bogdanm	0:9b334a45a8ff	1336	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1337	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	0:9b334a45a8ff	1338	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	0:9b334a45a8ff	1339	* @arg RCC_CRS_FLAG_ERR
bogdanm	0:9b334a45a8ff	1340	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	0:9b334a45a8ff	1341	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	0:9b334a45a8ff	1342	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	0:9b334a45a8ff	1343	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	0:9b334a45a8ff	1344	* @retval None
bogdanm	0:9b334a45a8ff	1345	*/
bogdanm	0:9b334a45a8ff	1346
bogdanm	0:9b334a45a8ff	1347	/* CRS Flag Error Mask */
bogdanm	0:9b334a45a8ff	1348	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
bogdanm	0:9b334a45a8ff	1349
bogdanm	0:9b334a45a8ff	1350	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	0:9b334a45a8ff	1351	(CRS->ICR = (__FLAG__)))
bogdanm	0:9b334a45a8ff	1352
bogdanm	0:9b334a45a8ff	1353
bogdanm	0:9b334a45a8ff	1354	/**
bogdanm	0:9b334a45a8ff	1355	* @brief Enables the oscillator clock for frequency error counter.
bogdanm	0:9b334a45a8ff	1356	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	0:9b334a45a8ff	1357	* @param None
bogdanm	0:9b334a45a8ff	1358	* @retval None
bogdanm	0:9b334a45a8ff	1359	*/
bogdanm	0:9b334a45a8ff	1360	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
bogdanm	0:9b334a45a8ff	1361
bogdanm	0:9b334a45a8ff	1362	/**
bogdanm	0:9b334a45a8ff	1363	* @brief Disables the oscillator clock for frequency error counter.
bogdanm	0:9b334a45a8ff	1364	* @param None
bogdanm	0:9b334a45a8ff	1365	* @retval None
bogdanm	0:9b334a45a8ff	1366	*/
bogdanm	0:9b334a45a8ff	1367	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
bogdanm	0:9b334a45a8ff	1368
bogdanm	0:9b334a45a8ff	1369	/**
bogdanm	0:9b334a45a8ff	1370	* @brief Enables the automatic hardware adjustment of TRIM bits.
bogdanm	0:9b334a45a8ff	1371	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	0:9b334a45a8ff	1372	* @param None
bogdanm	0:9b334a45a8ff	1373	* @retval None
bogdanm	0:9b334a45a8ff	1374	*/
bogdanm	0:9b334a45a8ff	1375	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
bogdanm	0:9b334a45a8ff	1376
bogdanm	0:9b334a45a8ff	1377	/**
bogdanm	0:9b334a45a8ff	1378	* @brief Enables or disables the automatic hardware adjustment of TRIM bits.
bogdanm	0:9b334a45a8ff	1379	* @param None
bogdanm	0:9b334a45a8ff	1380	* @retval None
bogdanm	0:9b334a45a8ff	1381	*/
bogdanm	0:9b334a45a8ff	1382	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
bogdanm	0:9b334a45a8ff	1383
bogdanm	0:9b334a45a8ff	1384	/**
bogdanm	0:9b334a45a8ff	1385	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
bogdanm	0:9b334a45a8ff	1386	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
bogdanm	0:9b334a45a8ff	1387	* of the synchronization source after prescaling. It is then decreased by one in order to
bogdanm	0:9b334a45a8ff	1388	* reach the expected synchronization on the zero value. The formula is the following:
bogdanm	0:9b334a45a8ff	1389	* RELOAD = (fTARGET / fSYNC) -1
bogdanm	0:9b334a45a8ff	1390	* @param _FTARGET_ Target frequency (value in Hz)
bogdanm	0:9b334a45a8ff	1391	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
bogdanm	0:9b334a45a8ff	1392	* @retval None
bogdanm	0:9b334a45a8ff	1393	*/
bogdanm	0:9b334a45a8ff	1394	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
bogdanm	0:9b334a45a8ff	1395
bogdanm	0:9b334a45a8ff	1396	#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	1397
bogdanm	0:9b334a45a8ff	1398	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
bogdanm	0:9b334a45a8ff	1399	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
bogdanm	0:9b334a45a8ff	1400	defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1401	/** @brief Enable or disable the HSI OUT .
bogdanm	0:9b334a45a8ff	1402	* @note After reset, the HSI output is not available
bogdanm	0:9b334a45a8ff	1403	*/
bogdanm	0:9b334a45a8ff	1404
bogdanm	0:9b334a45a8ff	1405	#define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
bogdanm	0:9b334a45a8ff	1406	#define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
bogdanm	0:9b334a45a8ff	1407
bogdanm	0:9b334a45a8ff	1408	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1409	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1410	/* STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	1411
bogdanm	0:9b334a45a8ff	1412	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\|\
bogdanm	0:9b334a45a8ff	1413	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx)
bogdanm	0:9b334a45a8ff	1414
bogdanm	0:9b334a45a8ff	1415	/**
bogdanm	0:9b334a45a8ff	1416	* @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
bogdanm	0:9b334a45a8ff	1417	* @note After enabling the HSI48, the application software should wait on
bogdanm	0:9b334a45a8ff	1418	* HSI48RDY flag to be set indicating that HSI48 clock is stable and can
bogdanm	0:9b334a45a8ff	1419	* be used to clock the USB.
bogdanm	0:9b334a45a8ff	1420	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1421	*/
bogdanm	0:9b334a45a8ff	1422	#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
bogdanm	0:9b334a45a8ff	1423	RCC->APB2ENR \|= RCC_APB2ENR_SYSCFGEN; \
bogdanm	0:9b334a45a8ff	1424	SYSCFG->CFGR3 \|= (SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT); \
bogdanm	0:9b334a45a8ff	1425	} while (0)
bogdanm	0:9b334a45a8ff	1426	#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
bogdanm	0:9b334a45a8ff	1427	SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT)); \
bogdanm	0:9b334a45a8ff	1428	} while (0)
bogdanm	0:9b334a45a8ff	1429	/** @brief Enable or disable the HSI48M DIV6 OUT .
bogdanm	0:9b334a45a8ff	1430	* @note After reset, the HSI48Mhz (divided by 6) output is not available
bogdanm	0:9b334a45a8ff	1431	*/
bogdanm	0:9b334a45a8ff	1432
bogdanm	0:9b334a45a8ff	1433	#define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
bogdanm	0:9b334a45a8ff	1434	#define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
bogdanm	0:9b334a45a8ff	1435
bogdanm	0:9b334a45a8ff	1436	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
bogdanm	0:9b334a45a8ff	1437	/* STM32L072xx \|\| STM32L082xx \|\| */
bogdanm	0:9b334a45a8ff	1438	/* STM32L073xx \|\| STM32L083xx */
bogdanm	0:9b334a45a8ff	1439
bogdanm	0:9b334a45a8ff	1440	/**
bogdanm	0:9b334a45a8ff	1441	* @}
bogdanm	0:9b334a45a8ff	1442	*/
bogdanm	0:9b334a45a8ff	1443
bogdanm	0:9b334a45a8ff	1444	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
bogdanm	0:9b334a45a8ff	1445	* @{
bogdanm	0:9b334a45a8ff	1446	*/
bogdanm	0:9b334a45a8ff	1447
bogdanm	0:9b334a45a8ff	1448	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
bogdanm	0:9b334a45a8ff	1449
bogdanm	0:9b334a45a8ff	1450	* @{
bogdanm	0:9b334a45a8ff	1451	*/
bogdanm	0:9b334a45a8ff	1452	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	0:9b334a45a8ff	1453	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	0:9b334a45a8ff	1454	void HAL_RCCEx_EnableLSECSS(void);
bogdanm	0:9b334a45a8ff	1455	void HAL_RCCEx_DisableLSECSS(void);
bogdanm	0:9b334a45a8ff	1456	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	0:9b334a45a8ff	1457	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
bogdanm	0:9b334a45a8ff	1458	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
bogdanm	0:9b334a45a8ff	1459	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
bogdanm	0:9b334a45a8ff	1460	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
bogdanm	0:9b334a45a8ff	1461	void HAL_RCCEx_EnableHSI48_VREFINT(void);
bogdanm	0:9b334a45a8ff	1462	void HAL_RCCEx_DisableHSI48_VREFINT(void);
bogdanm	0:9b334a45a8ff	1463	#endif /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	0:9b334a45a8ff	1464
bogdanm	0:9b334a45a8ff	1465	/**
bogdanm	0:9b334a45a8ff	1466	* @}
bogdanm	0:9b334a45a8ff	1467	*/
bogdanm	0:9b334a45a8ff	1468	/**
bogdanm	0:9b334a45a8ff	1469	* @}
bogdanm	0:9b334a45a8ff	1470	*/
bogdanm	0:9b334a45a8ff	1471
bogdanm	0:9b334a45a8ff	1472	/**
bogdanm	0:9b334a45a8ff	1473	* @}
bogdanm	0:9b334a45a8ff	1474	*/
bogdanm	0:9b334a45a8ff	1475
bogdanm	0:9b334a45a8ff	1476	/**
bogdanm	0:9b334a45a8ff	1477	* @}
bogdanm	0:9b334a45a8ff	1478	*/
bogdanm	0:9b334a45a8ff	1479
bogdanm	0:9b334a45a8ff	1480	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	1481	}
bogdanm	0:9b334a45a8ff	1482	#endif
bogdanm	0:9b334a45a8ff	1483
bogdanm	0:9b334a45a8ff	1484	#endif /* __STM32L0xx_HAL_RCC_EX_H */
bogdanm	0:9b334a45a8ff	1485
bogdanm	0:9b334a45a8ff	1486	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
bogdanm	0:9b334a45a8ff	1487

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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
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Followers:	1

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)

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