mbed-dev - fix LPC812 PWM

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fix LPC812 PWM
Diff: targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h

Revision:: 113:b3775bf36a83
Parent:: 0:9b334a45a8ff
--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h	Sun Apr 17 17:45:10 2016 +0100
+++ b/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h	Tue Apr 19 11:15:15 2016 +0100
@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32l0xx_hal_rcc_ex.h
   * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    06-February-2015
+  * @version V1.5.0
+  * @date    8-January-2016
   * @brief   Header file of RCC HAL Extension module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -50,15 +50,19 @@
   * @{
   */
 
-/** @defgroup RCCEx
+/** @defgroup RCCEx RCCEx
   * @{
   */ 
 
 /* Exported types ------------------------------------------------------------*/ 
+ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
 /** 
   * @brief  RCC extended clocks structure definition  
   */
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) 
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) 
 typedef struct
 {
   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
@@ -70,7 +74,7 @@
                                         This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
                                    
   uint32_t Lpuart1ClockSelection;  /*!< LPUART1 clock source      
-                                        This parameter can be a value of @ref RCCEx_LPUART_Clock_Source */
+                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
                                    
   uint32_t I2c1ClockSelection;     /*!< I2C1 clock source      
                                         This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
@@ -95,13 +99,13 @@
 }RCC_PeriphCLKInitTypeDef;
 
 
-#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+#else /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
 
 typedef struct
 {
   uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
                                         This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-#if !defined (STM32L031xx) && !defined (STM32L041xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) &&  !defined (STM32L031xx) && !defined (STM32L041xx)
   uint32_t Usart1ClockSelection;   /*!< USART1 clock source      
                                         This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
 #endif
@@ -127,11 +131,22 @@
   
 }RCC_PeriphCLKInitTypeDef;
 
-#endif /* STM32L0x1xx */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
 
+/**
+  * @}
+  */
 
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx) 
-/** @defgroup RCCEx_Exported_Constants
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx)  && !defined(STM32L081xx)
+
+/** @addtogroup RCCEx_Exported_Constants
   * @{
   */
 /** 
@@ -149,6 +164,10 @@
 /**
   * @}
   */
+
+ /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
 /** 
   * @brief RCC_CRS Init structure definition  
   */
@@ -196,17 +215,22 @@
                                     This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
 
 }RCC_CRSSynchroInfoTypeDef;
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+
+/**
+  * @}
+  */
+
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
  
 /* Exported constants --------------------------------------------------------*/
 /** @addtogroup RCCEx_Exported_Constants
   * @{
   */
 
-/** @defgroup RCCEx_Periph_Clock_Selection
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
   * @{
   */
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
 
 #define RCC_PERIPHCLK_USART1           ((uint32_t)0x00000001)
 #define RCC_PERIPHCLK_USART2           ((uint32_t)0x00000002)
@@ -223,34 +247,16 @@
 #define RCC_PERIPHCLK_I2C3             ((uint32_t)0x00000100)
 #endif
 
-#if defined (STM32L052xx) || defined(STM32L062xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
-                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1))
-#elif defined (STM32L053xx) || defined(STM32L063xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
-                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD))
-#elif defined (STM32L072xx) || defined(STM32L082xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
-                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_I2C3 ))
-#elif defined (STM32L073xx) || defined(STM32L083xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC  |  \
-                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_I2C3 | \
-                                                 RCC_PERIPHCLK_LCD))
-#endif
 
-#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+#else /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
 
-#if !defined(STM32L031xx) && !defined(STM32L041xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
 #define RCC_PERIPHCLK_USART1           ((uint32_t)0x00000001)
 #endif
 #define RCC_PERIPHCLK_USART2           ((uint32_t)0x00000002)
 #define RCC_PERIPHCLK_LPUART1          ((uint32_t)0x00000004)
 #define RCC_PERIPHCLK_I2C1             ((uint32_t)0x00000008)
-#if !defined(STM32L031xx) && !defined(STM32L041xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
 #define RCC_PERIPHCLK_I2C2             ((uint32_t)0x00000010)
 #endif
 #define RCC_PERIPHCLK_RTC              ((uint32_t)0x00000020)
@@ -259,100 +265,75 @@
 #define RCC_PERIPHCLK_I2C3             ((uint32_t)0x00000100)
 #endif
 
-#if defined(STM32L031xx) || defined(STM32L041xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                  RCC_PERIPHCLK_I2C1   |  RCC_PERIPHCLK_RTC ))
-#elif defined(STM32L051xx) || defined(STM32L061xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
-                                                 RCC_PERIPHCLK_LPTIM1))
-#elif defined(STM32L071xx) || defined(STM32L081xx)
-#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
-                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
-                                                 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))                               
-#endif
-
-#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
 /**
   * @}
   */
 
-/** @defgroup RCCEx_USART1_Clock_Source
+/** @defgroup RCCEx_USART1_Clock_Source RCC USART1 Clock Source
   * @{
   */
 #define RCC_USART1CLKSOURCE_PCLK2        ((uint32_t)0x00000000) 
 #define RCC_USART1CLKSOURCE_SYSCLK       RCC_CCIPR_USART1SEL_0
 #define RCC_USART1CLKSOURCE_HSI          RCC_CCIPR_USART1SEL_1
 #define RCC_USART1CLKSOURCE_LSE          (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
-#define IS_RCC_USART1CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
-                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
-                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
-                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+
 /**
   * @}
   */
 
-/** @defgroup RCCEx_USART2_Clock_Source
+/** @defgroup RCCEx_USART2_Clock_Source RCC USART2 Clock Source
   * @{
   */
 #define RCC_USART2CLKSOURCE_PCLK1        ((uint32_t)0x00000000) 
 #define RCC_USART2CLKSOURCE_SYSCLK       RCC_CCIPR_USART2SEL_0
 #define RCC_USART2CLKSOURCE_HSI          RCC_CCIPR_USART2SEL_1
 #define RCC_USART2CLKSOURCE_LSE          (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
-#define IS_RCC_USART2CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
-                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
-                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
-                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+
 /**
   * @}
   */
 
-/** @defgroup RCCEx_LPUART_Clock_Source
+/** @defgroup RCCEx_LPUART1_Clock_Source RCC LPUART Clock Source
   * @{
   */
 #define RCC_LPUART1CLKSOURCE_PCLK1        ((uint32_t)0x00000000) 
 #define RCC_LPUART1CLKSOURCE_SYSCLK       RCC_CCIPR_LPUART1SEL_0
 #define RCC_LPUART1CLKSOURCE_HSI          RCC_CCIPR_LPUART1SEL_1
 #define RCC_LPUART1CLKSOURCE_LSE          (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
-#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
-                                             ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
-                                             ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
-                                             ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
+
 /**
   * @}
   */
 
-/** @defgroup RCCEx_I2C1_Clock_Source
+/** @defgroup RCCEx_I2C1_Clock_Source RCC I2C1 Clock Source
   * @{
   */
 #define RCC_I2C1CLKSOURCE_PCLK1          ((uint32_t)0x00000000) 
 #define RCC_I2C1CLKSOURCE_SYSCLK         RCC_CCIPR_I2C1SEL_0
 #define RCC_I2C1CLKSOURCE_HSI            RCC_CCIPR_I2C1SEL_1
-#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
-                                          ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
-                                          ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
+
 /**
   * @}
   */
 
 #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx)|| defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)  
 
-/** @defgroup RCCEx_I2C3_Clock_Source
+/** @defgroup RCCEx_I2C3_Clock_Source RCC I2C3 Clock Source
   * @{
   */
 #define RCC_I2C3CLKSOURCE_PCLK1          ((uint32_t)0x00000000) 
 #define RCC_I2C3CLKSOURCE_SYSCLK         RCC_CCIPR_I2C3SEL_0
 #define RCC_I2C3CLKSOURCE_HSI            RCC_CCIPR_I2C3SEL_1
-#define IS_RCC_I2C3CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
-                                           ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
-                                           ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
-#endif /* defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx)|| defined(STM32L082xx) || defined(STM32L083xx) */ 
 
 /**
   * @}
   */
+#endif /* defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx)|| defined(STM32L082xx) || defined(STM32L083xx) */
 
-/** @defgroup RCCEx_TIM_PRescaler_Selection
+
+
+/** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM Prescaler Selection
   * @{
   */
 #define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00)
@@ -361,32 +342,28 @@
   * @}
   */
 
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
-/** @defgroup RCCEx_USB_Clock_Source
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
+/** @defgroup RCCEx_USB_Clock_Source RCC USB Clock Source
   * @{
   */
 #define RCC_USBCLKSOURCE_HSI48           RCC_CCIPR_HSI48SEL
-#define RCC_USBCLKSOURCE_PLLCLK          ((uint32_t)0x00000000)
+#define RCC_USBCLKSOURCE_PLL          ((uint32_t)0x00000000)
 
-#define IS_RCC_USBCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
-                                          ((__SOURCE__) == RCC_USBCLKSOURCE_PLLCLK))
 /**
   * @}
   */
   
-/** @defgroup RCCEx_RNG_Clock_Source
+/** @defgroup RCCEx_RNG_Clock_Source RCC RNG Clock Source
   * @{
   */
 #define RCC_RNGCLKSOURCE_HSI48           RCC_CCIPR_HSI48SEL
 #define RCC_RNGCLKSOURCE_PLLCLK          ((uint32_t)0x00000000)
 
-#define IS_RCC_RNGCLKSOURCE(_SOURCE_)  (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \
-                                      ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
 /**
   * @}
   */  
 
-/** @defgroup RCCEx_HSI48M_Clock_Source 
+/** @defgroup RCCEx_HSI48M_Clock_Source RCC HSI48M Clock Source
   * @{
   */
 #define RCC_FLAG_HSI48               SYSCFG_CFGR3_REF_HSI48_RDYF
@@ -394,14 +371,13 @@
 #define RCC_HSI48M_PLL                 ((uint32_t)0x00000000)
 #define RCC_HSI48M_HSI48                 RCC_CCIPR_HSI48SEL
 
-#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
 
 /**
   * @}
   */
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ 
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ 
 
-/** @defgroup RCC_HSI_Config
+/** @defgroup RCC_HSI_Config RCC HSI Configuration
   * @{
   */
 #define RCC_HSI_OFF                      ((uint8_t)0x00)
@@ -411,19 +387,13 @@
     defined(STM32L072xx) || defined(STM32L082xx) || \
     defined(STM32L071xx) || defined(STM32L081xx)
 #define RCC_HSI_OUTEN                    RCC_CR_HSIOUTEN
-
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
-                             ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN ))      
-#else
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
-                             ((__HSI__) == RCC_HSI_DIV4))
 #endif
 
 /**
   * @}
   */ 
 
-/** @defgroup RCCEx_LPTIM1_Clock_Source
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
   * @{
   */
 #define RCC_LPTIM1CLKSOURCE_PCLK        ((uint32_t)0x00000000)
@@ -431,28 +401,22 @@
 #define RCC_LPTIM1CLKSOURCE_HSI         RCC_CCIPR_LPTIM1SEL_1
 #define RCC_LPTIM1CLKSOURCE_LSE         RCC_CCIPR_LPTIM1SEL
 
-#define IS_RCC_LPTIMCLK(__LPTIMCLK_)     (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) || \
-                                          ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI)  || \
-                                          ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI)  || \
-                                          ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
 /**
   * @}
   */
 
-/** @defgroup RCCEx_StopWakeUp_Clock
+/** @defgroup RCCEx_StopWakeUp_Clock RCC StopWakeUp Clock
   * @{
   */
 
 #define RCC_STOP_WAKEUPCLOCK_MSI                ((uint32_t)0x00)
 #define RCC_STOP_WAKEUPCLOCK_HSI                RCC_CFGR_STOPWUCK
 
-#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) || \
-                                             ((__SOURCE__) == RCC_StopWakeUpClock_HSI))
 /**
   * @}
   */ 
 
-/** @defgroup RCCEx_LSEDrive_Configuration
+/** @defgroup RCCEx_LSEDrive_Configuration RCC LSE Drive Configuration
   * @{
   */
 
@@ -460,28 +424,32 @@
 #define RCC_LSEDRIVE_MEDIUMLOW           RCC_CSR_LSEDRV_0
 #define RCC_LSEDRIVE_MEDIUMHIGH          RCC_CSR_LSEDRV_1
 #define RCC_LSEDRIVE_HIGH                RCC_CSR_LSEDRV
-#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
-                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
+
 /**
   * @}
   */  
 
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
-/** @defgroup RCCEx_CRS_SynchroSource
+/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
+  * @{
+  */
+#define RCC_EXTI_LINE_LSECSS             (EXTI_IMR_IM19)         /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
+/**
+  * @}
+  */
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
+/** @defgroup RCCEx_CRS_SynchroSource RCC CRS Synchro Source
   * @{
   */
 #define RCC_CRS_SYNC_SOURCE_GPIO       ((uint32_t)0x00)        /*!< Synchro Signal source GPIO */
 #define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */
 #define RCC_CRS_SYNC_SOURCE_USB        CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/
   
-#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
-                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) ||\
-                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
 /**
   * @}
   */
 
-/** @defgroup RCCEx_CRS_SynchroDivider
+/** @defgroup RCCEx_CRS_SynchroDivider RCC CRS Synchro Divider
   * @{
   */
 #define RCC_CRS_SYNC_DIV1        ((uint32_t)0x00)                          /*!< Synchro Signal not divided (default) */
@@ -493,72 +461,61 @@
 #define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
 #define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */
   
-#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2)   ||\
-                                      ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8)   || \
-                                      ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
-                                      ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
 /**
   * @}
   */
 
-/** @defgroup RCCEx_CRS_SynchroPolarity
+/** @defgroup RCCEx_CRS_SynchroPolarity RCC CRS Synchro Polarity
   * @{
   */
 #define RCC_CRS_SYNC_POLARITY_RISING        ((uint32_t)0x00)      /*!< Synchro Active on rising edge (default) */
 #define RCC_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */
   
-#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
-                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
 /**
   * @}
   */
   
-/** @defgroup RCCEx_CRS_ReloadValueDefault
+/** @defgroup RCCEx_CRS_ReloadValueDefault RCC CRS Reload Default Value
   * @{
   */
 #define RCC_CRS_RELOADVALUE_DEFAULT         ((uint32_t)0xBB7F)      /*!< The reset value of the RELOAD field corresponds 
                                                               to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
     
-#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
 /**
   * @}
   */
   
-/** @defgroup RCCEx_CRS_ErrorLimitDefault
+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCC CRS Error Limit Default
   * @{
   */
 #define RCC_CRS_ERRORLIMIT_DEFAULT          ((uint32_t)0x22)      /*!< Default Frequency error limit */
     
-#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
 /**
   * @}
   */
 
-/** @defgroup RCCEx_CRS_HSI48CalibrationDefault
+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCC CRS HSI48 Calibration Default
   * @{
   */
 #define RCC_CRS_HSI48CALIBRATION_DEFAULT    ((uint32_t)0x20)      /*!< The default value is 32, which corresponds to the middle of the trimming interval. 
                                                                 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
                                                                 corresponds to a higher output frequency */
     
-#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
 /**
   * @}
   */
 
-/** @defgroup RCCEx_CRS_FreqErrorDirection
+/** @defgroup RCCEx_CRS_FreqErrorDirection RCC CRS Frequency Error Direction
   * @{
   */
 #define RCC_CRS_FREQERRORDIR_UP             ((uint32_t)0x00)          /*!< Upcounting direction, the actual frequency is above the target */
 #define RCC_CRS_FREQERRORDIR_DOWN           ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
     
-#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
-                                          ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
 /**
   * @}
   */
 
-/** @defgroup RCCEx_CRS_Interrupt_Sources
+/** @defgroup RCCEx_CRS_Interrupt_Sources RCC CRS Interrupt Sources
   * @{
   */
 #define RCC_CRS_IT_SYNCOK             CRS_ISR_SYNCOKF    /*!< SYNC event OK */
@@ -573,7 +530,7 @@
   * @}
   */
   
-/** @defgroup RCCEx_CRS_Flags
+/** @defgroup RCCEx_CRS_Flags RCC CRS Flags
   * @{
   */
 #define RCC_CRS_FLAG_SYNCOK             CRS_ISR_SYNCOKF     /* SYNC event OK flag     */
@@ -588,44 +545,142 @@
   * @}
   */
 
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */  
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */  
 /**
   * @}
   */ 
 
 /* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCC Ex Exported Macros
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
   * @{
   */
-
-/** @brief  Enable or disable the AHB peripheral clock.
+/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before
   *         using it.
+  * @{
   */
 
-#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
-#define __HAL_RCC_AES_CLK_ENABLE()          (RCC->AHBENR |= (RCC_AHBENR_CRYPEN))
-#define __HAL_RCC_AES_CLK_DISABLE()         (RCC->AHBENR  &= ~ (RCC_AHBENR_CRYPEN))
-#endif /* STM32L062xx || STM32L063xx || STM32L072xx  || STM32L073xx || STM32L082xx  || STM32L083xx */
+#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx)
+#define __HAL_RCC_AES_CLK_ENABLE()          SET_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
+#define __HAL_RCC_AES_CLK_DISABLE()         CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_CRYPEN))
+#endif /* STM32L062xx || STM32L063xx || STM32L072xx  || STM32L073xx || STM32L082xx  || STM32L083xx || STM32L041xx || STM32L021xx */
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
+#define __HAL_RCC_TSC_CLK_ENABLE()             SET_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
+#define __HAL_RCC_TSC_CLK_DISABLE()            CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_TSCEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE()            SET_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
+#define __HAL_RCC_RNG_CLK_DISABLE()           CLEAR_BIT(RCC->AHBENR, (RCC_AHBENR_RNGEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+
+
+/**
+  * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.
+  * @retval None
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)
 
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
-#define __HAL_RCC_TSC_CLK_ENABLE()             (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
-#define __HAL_RCC_TSC_CLK_DISABLE()            (RCC->AHBENR  &= ~ (RCC_AHBENR_TSCEN))
+/**
+  * @brief Enable event on RCC LSE CSS EXTI Line 19.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable event on RCC LSE CSS EXTI Line 19.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)
+
 
-#define __HAL_RCC_RNG_CLK_ENABLE()            (RCC->AHBENR |= (RCC_AHBENR_RNGEN))
-#define __HAL_RCC_RNG_CLK_DISABLE()           (RCC->AHBENR  &= ~ (RCC_AHBENR_RNGEN))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+/**
+  * @brief  RCC LSE CSS EXTI line configuration: set falling edge trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
+
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)
 
 
+/**
+  * @brief  RCC LSE CSS EXTI line configuration: set rising edge trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)
+
+/**
+  * @brief  RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                      \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)  
+  
+/**
+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                       \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)  
+
+/**
+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
+  * @retval EXTI RCC LSE CSS Line Status.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (EXTI->PR & (RCC_EXTI_LINE_LSECSS))
+
+/**
+  * @brief Clear the RCC LSE CSS EXTI flag.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     (EXTI->PR = (RCC_EXTI_LINE_LSECSS))
+
+/**
+  * @brief Generate a Software interrupt on selected EXTI line.
+  * @retval None.
+  */
+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
+  * @brief  Enable or disable the IOPORT peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
 #if defined(STM32L073xx) || defined(STM32L083xx) || \
     defined(STM32L072xx) || defined(STM32L082xx) || \
     defined(STM32L071xx) || defined(STM32L081xx)
-/** @brief  Enable or disable the IOPORT peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  */
 #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
                                         __IO uint32_t tmpreg; \
                                         SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
@@ -634,105 +689,120 @@
                                         UNUSED(tmpreg); \
                                       } while(0)
 
-#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->IOPENR &= ~(RCC_IOPENR_GPIOEEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIOEEN))
 
 #endif /* STM32L071xx  ||  STM32L081xx  || */
        /* STM32L072xx  ||  STM32L082xx  || */
        /* STM32L073xx  ||  STM32L083xx     */
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg; \
+                                        SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()        CLEAR_BIT(RCC->IOPENR,(RCC_IOPENR_GPIODEN))
+#endif  /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */
+/**
+  * @}
+  */
 
-/** @brief  Enable or disable the APB1 peripheral clock.
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable							  
+  * @brief  Enable or disable the APB1 peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before 
   *         using it.   
+  * @{
   */
 
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
-#define __HAL_RCC_USB_CLK_ENABLE()         (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
-#define __HAL_RCC_USB_CLK_DISABLE()        (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN))
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
+#define __HAL_RCC_USB_CLK_ENABLE()        SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
+#define __HAL_RCC_USB_CLK_DISABLE()       CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USBEN))
 
-#define __HAL_RCC_CRS_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
-#define __HAL_RCC_CRS_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+#define __HAL_RCC_CRS_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_CRSEN))
+#define __HAL_RCC_CRS_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR,(RCC_APB1ENR_CRSEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
        
 
 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
-#define __HAL_RCC_LCD_CLK_ENABLE()            (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN))
-#define __HAL_RCC_LCD_CLK_DISABLE()           (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN))
+#define __HAL_RCC_LCD_CLK_ENABLE()          SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
+#define __HAL_RCC_LCD_CLK_DISABLE()         CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LCDEN))
 #endif /* STM32L053xx || STM32L063xx || STM32L073xx  || STM32L083xx */
 
 #if defined(STM32L053xx) || defined(STM32L063xx) || \
     defined(STM32L052xx) || defined(STM32L062xx) || \
     defined(STM32L051xx) || defined(STM32L061xx)
-#define __HAL_RCC_TIM2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM6_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_SPI2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_DAC_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_TIM2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM6_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_SPI2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_DAC_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
 
-#define __HAL_RCC_TIM2_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE()  (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_DISABLE()  (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()   (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_TIM2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE()     CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
 #endif /* STM32L051xx  || STM32L061xx  ||  */
        /* STM32L052xx  || STM32L062xx  ||  */
        /* STM32L053xx  || STM32L063xx  ||  */
 
-#if defined(STM32L031xx) || defined(STM32L041xx)
-#define __HAL_RCC_TIM2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_USART2_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
+#define __HAL_RCC_TIM2_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_USART2_CLK_ENABLE()   SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
 
-#define __HAL_RCC_TIM2_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE()  (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_LPUART1_CLK_DISABLE()  (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()   (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
-#endif /* STM32L031xx  || STM32L041xx  ||  */
+#define __HAL_RCC_TIM2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
+#endif /* STM32L011xx  || STM32L021xx  || STM32L031xx  || STM32L041xx   */
 
 
 #if defined(STM32L073xx) || defined(STM32L083xx) || \
     defined(STM32L072xx) || defined(STM32L082xx) || \
     defined(STM32L071xx) || defined(STM32L081xx)
-#define __HAL_RCC_TIM2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM6_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_SPI2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_USART4_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
-#define __HAL_RCC_USART5_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
-#define __HAL_RCC_LPUART1_CLK_ENABLE()  (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_DAC_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()   (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_TIM2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM6_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_SPI2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_USART4_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
+#define __HAL_RCC_USART5_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
+#define __HAL_RCC_LPUART1_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_ENABLE()    SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_DAC_CLK_ENABLE()     SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()  SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
 
-#define __HAL_RCC_TIM2_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_SPI2_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE()  (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_USART4_CLK_DISABLE()  (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART4EN))
-#define __HAL_RCC_USART5_CLK_DISABLE()  (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART5EN))
-#define __HAL_RCC_LPUART1_CLK_DISABLE()  (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()    (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()   (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_TIM2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_SPI2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_USART4_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART4EN))
+#define __HAL_RCC_USART5_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_USART5EN))
+#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPUART1EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()    CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_DAC_CLK_DISABLE()     CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_DACEN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()  CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_LPTIM1EN))
 #endif /* STM32L071xx  ||  STM32L081xx  || */
        /* STM32L072xx  ||  STM32L082xx  || */
        /* STM32L073xx  ||  STM32L083xx     */
@@ -740,232 +810,312 @@
 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
     defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
     defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) || \
-    defined(STM32L031xx) || defined(STM32L041xx)
-    
-/** @brief  Enable or disable the APB2 peripheral clock.
+    defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx) 
+ /**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable	   
+  * @brief  Enable or disable the APB2 peripheral clock.
   * @note   After reset, the peripheral clock (used for registers read/write access)
   *         is disabled and the application software has to enable this clock before 
   *         using it.   
+  * @{
   */
-#define __HAL_RCC_TIM21_CLK_ENABLE()    (RCC->APB2ENR |= (RCC_APB2ENR_TIM21EN))
-#define __HAL_RCC_TIM22_CLK_ENABLE()    (RCC->APB2ENR |= (RCC_APB2ENR_TIM22EN))
-#define __HAL_RCC_FIREWALL_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_MIFIEN))
-#define __HAL_RCC_ADC1_CLK_ENABLE()     (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SPI1_CLK_ENABLE()     (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_USART1_CLK_ENABLE()   (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_TIM21_CLK_ENABLE()    SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM21EN))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_CLK_ENABLE()    SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_TIM22EN))
+#endif
+#define __HAL_RCC_ADC1_CLK_ENABLE()     SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_ENABLE()     SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_USART1_CLK_ENABLE()   SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_USART1EN))
 
-#define __HAL_RCC_TIM21_CLK_DISABLE()    (RCC->APB2ENR &= ~  (RCC_APB2ENR_TIM21EN))
-#define __HAL_RCC_TIM22_CLK_DISABLE()    (RCC->APB2ENR &= ~  (RCC_APB2ENR_TIM22EN))
-#define __HAL_RCC_FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~  (RCC_APB2ENR_MIFIEN))
-#define __HAL_RCC_ADC1_CLK_DISABLE()     (RCC->APB2ENR &= ~  (RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE()     (RCC->APB2ENR &= ~  (RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_USART1_CLK_DISABLE()   (RCC->APB2ENR &= ~  (RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_TIM21_CLK_DISABLE()    CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_TIM21EN))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_CLK_DISABLE()    CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_TIM22EN))
+#endif
+#define __HAL_RCC_ADC1_CLK_DISABLE()     CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE()     CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_USART1_CLK_DISABLE()   CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_USART1EN))
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
+#define __HAL_RCC_FIREWALL_CLK_ENABLE()  SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_MIFIEN))
+#define __HAL_RCC_FIREWALL_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR,  (RCC_APB2ENR_MIFIEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !STM32L031xx && !STM32L041xx */
 #endif /* STM32L051xx  || STM32L061xx  || STM32L071xx  ||  STM32L081xx  || */
        /* STM32L052xx  || STM32L062xx  || STM32L072xx  ||  STM32L082xx  || */
-       /* STM32L053xx  || STM32L063xx  || STM32L073xx  ||  STM32L083xx     */
-
-/** @brief  Force or release AHB peripheral reset.
-  */  
-#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
-#define __HAL_RCC_AES_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_CRYPRST))
-#define __HAL_RCC_AES_RELEASE_RESET()   (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST))
-#endif /* STM32L062xx || STM32L063xx || STM32L072xx  || STM32L073xx || STM32L082xx  || STM32L083xx */
+       /* STM32L053xx  || STM32L063xx  || STM32L073xx  ||  STM32L083xx  || */
+	   /* STM32L031xx  || STM32L041xx  || STM32L011xx  || STM32L021xx      */
+       
+/**
+  * @}
+  */
 
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
-#define __HAL_RCC_TSC_FORCE_RESET()        (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
-#define __HAL_RCC_TSC_RELEASE_RESET()      (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST))
-#define __HAL_RCC_RNG_FORCE_RESET()        (RCC->AHBRSTR |= (RCC_AHBRSTR_RNGRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()      (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+/** @defgroup RCCEx_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
+  * @brief  Force or release AHB peripheral reset.
+  * @{
+  */
+#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx) || defined(STM32L021xx)
+#define __HAL_RCC_AES_FORCE_RESET()     SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
+#define __HAL_RCC_AES_RELEASE_RESET()   CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRYPRST))
+#endif /* STM32L062xx || STM32L063xx || STM32L072xx  || STM32L073xx || STM32L082xx  || STM32L083xx || STM32L041xx || STM32L021xx*/
 
-/** @brief  Force or release IOPORT peripheral reset.
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
+#define __HAL_RCC_TSC_FORCE_RESET()        SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
+#define __HAL_RCC_TSC_RELEASE_RESET()      CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_TSCRST))
+#define __HAL_RCC_RNG_FORCE_RESET()        SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()      CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_RNGRST))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
+  * @brief  Force or release IOPORT peripheral reset.
+  * @{
   */
 #if defined(STM32L073xx) || defined(STM32L083xx) || \
     defined(STM32L072xx) || defined(STM32L082xx) || \
     defined(STM32L071xx) || defined(STM32L081xx)
-#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOERST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOERST))
 
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOERST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIOERST))
 
 #endif /* STM32L071xx  ||  STM32L081xx  || */
        /* STM32L072xx  ||  STM32L082xx  || */
        /* STM32L073xx  ||  STM32L083xx     */
-       
-/** @brief  Force or release APB1 peripheral reset.
-  */  
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
+#define __HAL_RCC_GPIOD_FORCE_RESET()   SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIODRST))
+#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR,(RCC_IOPRSTR_GPIODRST))
+#endif  /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */ 
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset     
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */ 
 
 #if defined(STM32L053xx) || defined(STM32L063xx) || \
     defined(STM32L052xx) || defined(STM32L062xx) || \
     defined(STM32L051xx) || defined(STM32L061xx)  
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM6_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_USART2_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_FORCE_RESET()  SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_FORCE_RESET()      SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
 
-#define __HAL_RCC_TIM2_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()   (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_USART2_RELEASE_RESET()   (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_RELEASE_RESET()  (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()      (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_USART2_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_RELEASE_RESET()  CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
 #endif /* STM32L051xx  || STM32L061xx  || */
        /* STM32L052xx  || STM32L062xx  || */
        /* STM32L053xx  || STM32L063xx     */
-#if defined(STM32L031xx) || defined(STM32L041xx)
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
+#define __HAL_RCC_TIM2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_USART2_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_FORCE_RESET()  SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
 
-#define __HAL_RCC_TIM2_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()   (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_USART2_RELEASE_RESET()   (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_LPUART1_RELEASE_RESET()  (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
-#endif /* STM32L031xx  || STM32L041xx  || */
+#define __HAL_RCC_TIM2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_USART2_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_LPUART1_RELEASE_RESET()  CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
+#endif /* STM32L031xx  || STM32L041xx  || STM32L011xx  || STM32L021xx  */
 
 #if defined(STM32L073xx) || defined(STM32L083xx) || \
     defined(STM32L072xx) || defined(STM32L082xx) || \
     defined(STM32L071xx) || defined(STM32L081xx) 
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
-#define __HAL_RCC_USART5_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
-#define __HAL_RCC_LPUART1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM6_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_USART2_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART4_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
+#define __HAL_RCC_USART5_FORCE_RESET()   SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
+#define __HAL_RCC_LPUART1_FORCE_RESET()  SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_FORCE_RESET()     SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_FORCE_RESET()      SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
 
-#define __HAL_RCC_TIM2_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()   (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_USART2_RELEASE_RESET()   (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_USART4_RELEASE_RESET()   (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART4RST))
-#define __HAL_RCC_USART5_RELEASE_RESET()   (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART5RST))
-#define __HAL_RCC_LPUART1_RELEASE_RESET()  (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
-#define __HAL_RCC_SPI2_RELEASE_RESET()     (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()      (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_USART2_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_USART4_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART4RST))
+#define __HAL_RCC_USART5_RELEASE_RESET()   CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USART5RST))
+#define __HAL_RCC_LPUART1_RELEASE_RESET()  CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LPUART1RST))
+#define __HAL_RCC_SPI2_RELEASE_RESET()     CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_DACRST))
 #endif /* STM32L071xx  ||  STM32L081xx  || */
        /* STM32L072xx  ||  STM32L082xx  || */
        /* STM32L073xx  ||  STM32L083xx  || */
 
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
-#define __HAL_RCC_USB_FORCE_RESET()        (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_USB_RELEASE_RESET()      (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST))
-#define __HAL_RCC_CRS_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
-#define __HAL_RCC_CRS_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
+#define __HAL_RCC_USB_FORCE_RESET()        SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_USB_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_USBRST))
+#define __HAL_RCC_CRS_FORCE_RESET()        SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_CRSRST))
+#define __HAL_RCC_CRS_RELEASE_RESET()      CLEAR_BIT(RCC->APB1RSTR,(RCC_APB1RSTR_CRSRST))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
 
 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
-#define __HAL_RCC_LCD_FORCE_RESET()           (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
-#define __HAL_RCC_LCD_RELEASE_RESET()         (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST))
+#define __HAL_RCC_LCD_FORCE_RESET()           SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
+#define __HAL_RCC_LCD_RELEASE_RESET()         CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_LCDRST))
 #endif /* STM32L053xx || STM32L063xx || STM32L073xx  || STM32L083xx */
 
 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
     defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
-    defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) 
-    /** @brief  Force or release APB2 peripheral reset.
+    defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset       
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
   */ 
-#define __HAL_RCC_USART1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_ADC1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_TIM21_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM21RST))
-#define __HAL_RCC_TIM22_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM22RST))
+#define __HAL_RCC_USART1_FORCE_RESET()     SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_ADC1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM21_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
+#endif
 
-#define __HAL_RCC_USART1_RELEASE_RESET()     (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_ADC1_RELEASE_RESET()       (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST))
-#define __HAL_RCC_SPI1_RELEASE_RESET()       (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_TIM21_RELEASE_RESET()      (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST))
-#define __HAL_RCC_TIM22_RELEASE_RESET()      (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST))
+#define __HAL_RCC_USART1_RELEASE_RESET()     CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_ADC1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM21_RELEASE_RESET()      CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_RELEASE_RESET()      CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
+#endif
 #endif /* STM32L051xx  || STM32L061xx  || STM32L071xx  ||  STM32L081xx  || */
        /* STM32L052xx  || STM32L062xx  || STM32L072xx  ||  STM32L082xx  || */
        /* STM32L053xx  || STM32L063xx  || STM32L073xx  ||  STM32L083xx  || */
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
+#define __HAL_RCC_ADC1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_FORCE_RESET()       SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM21_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_FORCE_RESET()      SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
+#endif
+#define __HAL_RCC_ADC1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_ADC1RST))
+#define __HAL_RCC_SPI1_RELEASE_RESET()       CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_TIM21_RELEASE_RESET()      CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM21RST))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_RELEASE_RESET()      CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_TIM22RST))
+#endif
+#endif /* STM32L031xx  || STM32L041xx  || STM32L011xx  || STM32L021xx*/
 
-/** @brief  Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
   *         power consumption.
   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
   */
 
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
-#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE()           (RCC->AHBSMENR |= (RCC_AHBSMENR_TSCSMEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()           (RCC->AHBSMENR |= (RCC_AHBSMENR_RNGSMEN))
-#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE()          (RCC->AHBSMENR  &= ~ (RCC_AHBSMENR_TSCSMEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()          (RCC->AHBSMENR  &= ~ (RCC_AHBSMENR_RNGSMEN))
-#endif /* !(STM32L031xx ) &&  !(STM32L041xx ) &&  !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
+#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE()           SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()           SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
+#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE()          CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_TSCSMEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()          CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_RNGSMEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) &&  !(STM32L041xx ) &&  !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
        
-#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()          (RCC->AHBLPENR |= (RCC_AHBSMENR_CRYPSMEN))
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()         (RCC->AHBLPENR  &= ~ (RCC_AHBSMENR_CRYPSMEN))
-#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
+#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) || defined(STM32L041xx)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()          SET_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()         CLEAR_BIT(RCC->AHBLPENR, (RCC_AHBSMENR_CRYPSMEN))
+#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx || STM32L041xx */
 
-#if defined(STM32L073xx) || defined(STM32L083xx) || \
-    defined(STM32L072xx) || defined(STM32L082xx) || \
-    defined(STM32L071xx) || defined(STM32L081xx) 
-/** @brief  Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
   *         power consumption.
   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
   */
-
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()         (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOESMEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()        (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOESMEN))
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+    defined(STM32L072xx) || defined(STM32L082xx) || \
+    defined(STM32L071xx) || defined(STM32L081xx) 
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()         SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOESMEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()        CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIOESMEN))
 
 #endif /* STM32L071xx  ||  STM32L081xx  || */
        /* STM32L072xx  ||  STM32L082xx  || */
        /* STM32L073xx  ||  STM32L083xx  || */
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx)
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIODSMEN))
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->IOPSMENR,(RCC_IOPSMENR_GPIODSMEN))
+#endif  /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) */ 
+/**
+  * @}
+  */
 
-/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+
+/** @defgroup RCCEx_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
   *         power consumption.
   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
   */
 
 #if defined(STM32L053xx) || defined(STM32L063xx) || \
     defined(STM32L052xx) || defined(STM32L062xx) || \
     defined(STM32L051xx) || defined(STM32L061xx) 
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()  (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()   (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
 
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()  (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()   (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
 #endif /* STM32L051xx  || STM32L061xx  || */
        /* STM32L052xx  || STM32L062xx  || */
        /* STM32L053xx  || STM32L063xx     */
@@ -973,87 +1123,142 @@
 #if defined(STM32L073xx) || defined(STM32L083xx) || \
     defined(STM32L072xx) || defined(STM32L082xx) || \
     defined(STM32L071xx) || defined(STM32L081xx)
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM3SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM7SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE()  (RCC->APB1SMENR |= (RCC_APB1SMENR_USART4SMEN))
-#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE()  (RCC->APB1SMENR |= (RCC_APB1SMENR_USART5SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()  (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C3SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()   (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
+#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
 
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM3SMEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM7SMEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
-#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE()  (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART4SMEN))
-#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE()  (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART5SMEN))
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()  (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()    (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C3SMEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()   (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM3SMEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM6SMEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM7SMEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_SPI2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART4SMEN))
+#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART5SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C2SMEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C3SMEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_DACSMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
 #endif /*  STM32L071xx  ||  STM32L081xx  || */
        /*  STM32L072xx  ||  STM32L082xx  || */
        /*  STM32L073xx  ||  STM32L083xx  || */
-       
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
-#define __HAL_RCC_USB_CLK_SLEEP_ENABLE()   (RCC->APB1SMENR |= (RCC_APB1SMENR_USBSMEN))
-#define __HAL_RCC_USB_CLK_SLEEP_DISABLE()  (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN))
-#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()   (RCC->APB1SMENR |= (RCC_APB1SMENR_CRSSMEN))
-#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()  (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN))
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx )  && !(STM32L071xx ) && !(STM32L081xx ) */
+
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx) 
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()     SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_TIM2SMEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USART2SMEN))
+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPUART1SMEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_I2C1SMEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LPTIM1SMEN))
+#endif /*  STM32L031xx  ||  STM32L041xx || STM32L011xx  || STM32L021xx */
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) 
+#define __HAL_RCC_USB_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
+#define __HAL_RCC_USB_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_USBSMEN))
+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_CRSSMEN))
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx )  && !(STM32L071xx ) && !(STM32L081xx ) */
 
 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
-#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()      (RCC->APB1SMENR |= (RCC_APB1SMENR_LCDSMEN))
-#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()     (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN))
+#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()      SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
+#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()     CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_LCDSMEN))
 #endif /* STM32L053xx || STM32L063xx || STM32L073xx  || STM32L083xx */
 
 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
     defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
-    defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
-/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+    defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) || \
+	defined(STM32L031xx) || defined(STM32L041xx) || defined(STM32L011xx) || defined(STM32L021xx) 
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
   *         power consumption.
   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
   * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
   */
-#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE()    (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM21SMEN))
-#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE()    (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM22SMEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()     (RCC->APB2SMENR |= (RCC_APB2SMENR_ADC1SMEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()     (RCC->APB2SMENR |= (RCC_APB2SMENR_SPI1SMEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()   (RCC->APB2SMENR |= (RCC_APB2SMENR_USART1SMEN))
+#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM21SMEN))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE()   SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_TIM22SMEN))
+#endif
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_ADC1SMEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SPI1SMEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_USART1SMEN))
 
-#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE()    (RCC->APB2SMENR &= ~  (RCC_APB2SMENR_TIM21SMEN))
-#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE()    (RCC->APB2SMENR &= ~  (RCC_APB2SMENR_TIM22SMEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()     (RCC->APB2SMENR &= ~  (RCC_APB2SMENR_ADC1SMEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()     (RCC->APB2SMENR &= ~  (RCC_APB2SMENR_SPI1SMEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()   (RCC->APB2SMENR &= ~  (RCC_APB2SMENR_USART1SMEN))
+#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_TIM21SMEN))
+#if !defined (STM32L011xx) && !defined (STM32L021xx)
+#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_TIM22SMEN))
+#endif
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_ADC1SMEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_SPI1SMEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->APB2SMENR,  (RCC_APB2SMENR_USART1SMEN))
 #endif /* STM32L051xx  || STM32L061xx  || STM32L071xx  ||  STM32L081xx  || */
        /* STM32L052xx  || STM32L062xx  || STM32L072xx  ||  STM32L082xx  || */
        /* STM32L053xx  || STM32L063xx  || STM32L073xx  ||  STM32L083xx  || */
+	     /* STM32L031xx  || STM32L041xx  || STM32L011xx  ||  STM32L021xx   */
 
-/** @brief macro to configure the I2C1 clock (I2C1CLK).
+/** @brief Macro to configures LCD clock (LCDCLK).
+  *  @note   LCD and RTC use the same configuration
+  *  @note   LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
+  *   LCD clock source.
+  *    
+  *  @param  __LCD_CLKSOURCE__ specifies the LCD clock source.
+  *          This parameter can be one of the following values:
+  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock
+  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock
+  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock
+  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock
+  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock
+  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock
+  */
+#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
+
+/** @brief macros to get the LCD clock source.
+  */
+#define __HAL_RCC_GET_LCD_SOURCE()              __HAL_RCC_GET_RTC_SOURCE()
+
+/** @brief macros to get the LCD clock pre-scaler.
+  */
+#define  __HAL_RCC_GET_LCD_HSE_PRESCALER()      __HAL_RCC_GET_RTC_HSE_PRESCALER()
+/**
+  * @}
+  */
+          
+/** @brief  Macro to configure the I2C1 clock (I2C1CLK).
   *
-  * @param  __I2C1CLKSource__: specifies the I2C1 clock source.
+  * @param  __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
   *          This parameter can be one of the following values:
   *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock  
   *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
   *            @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock 
+  * @retval None
   */
-#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1CLKSource__))
+#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
 
-/** @brief  macro to get the I2C1 clock source.
+/** @brief  Macro to get the I2C1 clock source.
   * @retval The clock source can be one of the following values:
   *            @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock  
   *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
@@ -1064,18 +1269,19 @@
 #if defined (STM32L073xx) || defined(STM32L083xx) || \
     defined(STM32L072xx) || defined(STM32L082xx) || \
     defined(STM32L071xx) || defined(STM32L081xx)
-/** @brief macro to configure the I2C3 clock (I2C3CLK).
+/** @brief  Macro to configure the I2C3 clock (I2C3CLK).
   *
-  * @param  __I2C3CLKSource__: specifies the I2C3 clock source.
+  * @param  __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
   *          This parameter can be one of the following values:
   *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock  
   *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
-  *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock 
+  *            @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
+  * @retval None
   */
-#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3CLKSource__))
+#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
 
-/** @brief  macro to get the I2C3 clock source.
+/** @brief  Macro to get the I2C3 clock source.
   * @retval The clock source can be one of the following values:
   *            @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock  
   *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
@@ -1087,19 +1293,20 @@
        /*  STM32L072xx  ||  STM32L082xx  || */
        /*  STM32L073xx  ||  STM32L083xx  || */
 
-/** @brief macro to configure the USART1 clock (USART1CLK).
+/** @brief  Macro to configure the USART1 clock (USART1CLK).
   *
-  * @param  __USART1CLKSource__: specifies the USART1 clock source.
+  * @param  __USART1_CLKSOURCE__: specifies the USART1 clock source.
   *          This parameter can be one of the following values:
   *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
   *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
   *            @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
   *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
+  * @retval None
   */
-#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1CLKSource__))
+#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
 
-/** @brief  macro to get the USART1 clock source.
+/** @brief  Macro to get the USART1 clock source.
   * @retval The clock source can be one of the following values:
   *            @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
   *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
@@ -1108,19 +1315,20 @@
   */
 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
 
-/** @brief macro to configure the USART2 clock (USART2CLK).
+/** @brief  Macro to configure the USART2 clock (USART2CLK).
   *
-  * @param  __USART2CLKSource__: specifies the USART2 clock source.
+  * @param  __USART2_CLKSOURCE__: specifies the USART2 clock source.
   *          This parameter can be one of the following values:
   *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
   *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
   *            @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
   *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
+  * @retval None
   */
-#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2CLKSource__))
+#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
 
-/** @brief  macro to get the USART2 clock source.
+/** @brief  Macro to get the USART2 clock source.
   * @retval The clock source can be one of the following values:
   *            @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
   *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
@@ -1129,19 +1337,20 @@
   */
 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
 
-/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
+/** @brief  Macro to configure the LPUART1 clock (LPUART1CLK).
   *
-  * @param  __LPUART1CLKSource__: specifies the LPUART1 clock source.
+  * @param  __LPUART1_CLKSOURCE__: specifies the LPUART1 clock source.
   *          This parameter can be one of the following values:
   *            @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
   *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
   *            @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
   *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
+  * @retval None
   */
-#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
 
-/** @brief  macro to get the LPUART1 clock source.
+/** @brief  Macro to get the LPUART1 clock source.
   * @retval The clock source can be one of the following values:
   *            @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
   *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
@@ -1150,19 +1359,20 @@
   */
 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
 
-/** @brief macro to configure the LPTIM1 clock (LPTIM1CLK).
+/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
   *
-  * @param  __LPTIM1CLKSource__: specifies the LPTIM1 clock source.
+  * @param  __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
   *          This parameter can be one of the following values:
   *            @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
   *            @arg RCC_LPTIM1CLKSOURCE_LSI : HSI  selected as LPTIM1 clock
   *            @arg RCC_LPTIM1CLKSOURCE_HSI : LSI  selected as LPTIM1 clock
   *            @arg RCC_LPTIM1CLKSOURCE_LSE : LSE  selected as LPTIM1 clock
+  * @retval None
   */
-#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
-                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
+                  MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
 
-/** @brief  macro to get the LPTIM1 clock source.
+/** @brief  Macro to get the LPTIM1 clock source.
   * @retval The clock source can be one of the following values:
   *            @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
   *            @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
@@ -1171,12 +1381,12 @@
   */
 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
 
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
 /** @brief  Macro to configure the USB clock (USBCLK).
   * @param  __USBCLKSource__: specifies the USB clock source.
   *         This parameter can be one of the following values:
   *            @arg RCC_USBCLKSOURCE_HSI48:  HSI48 selected as USB clock
-  *            @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_PLL: PLL Clock selected as USB clock
   */
 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
                   MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__))
@@ -1184,7 +1394,7 @@
 /** @brief  Macro to get the USB clock source.
   * @retval The clock source can be one of the following values:
   *            @arg RCC_USBCLKSOURCE_HSI48:  HSI48 selected as USB clock
-  *            @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
+  *            @arg RCC_USBCLKSOURCE_PLL: PLL Clock selected as USB clock
   */
 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
 
@@ -1225,13 +1435,12 @@
   *            @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator. 
   */
 #define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))       
-#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx )  && !(STM32L071xx )  && !(STM32L081xx ) */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx )  && !(STM32L071xx )  && !(STM32L081xx ) */
 
 /**
   * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
   *           in STOP mode to be quickly available as kernel clock for USART and I2C.
   * @note     The Enable of this function has not effect on the HSION bit.
-  *   This parameter can be: ENABLE or DISABLE.
   * @retval None
   */
 #define __HAL_RCC_HSISTOP_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSIKERON)
@@ -1239,7 +1448,7 @@
 
 /**
   * @brief  Macro to configures the External Low Speed oscillator (LSE) drive capability.
-  * @param  RCC_LSEDrive: specifies the new state of the LSE drive capability.
+  * @param  __RCC_LSEDrive__: specifies the new state of the LSE drive capability.
   *          This parameter can be one of the following values:
   *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
   *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
@@ -1252,7 +1461,7 @@
 
 /**
   * @brief  Macro to configures the wake up from stop clock.
-  * @param  RCC_STOPWUCLK: specifies the clock source used after wake up from stop 
+  * @param  __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop
   *   This parameter can be one of the following values:
   *     @arg RCC_STOP_WAKEUPCLOCK_MSI:    MSI selected as system clock source
   *     @arg RCC_STOP_WAKEUPCLOCK_HSI:    HSI selected as system clock source
@@ -1261,7 +1470,7 @@
 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
         RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
  
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
 /**
   * @brief  Enables the specified CRS interrupts.
   * @param  __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
@@ -1272,7 +1481,7 @@
   *              @arg RCC_CRS_IT_ESYNC
   * @retval None
   */
-#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   (CRS->CR |= (__INTERRUPT__))
+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
 
 /**
   * @brief  Disables the specified CRS interrupts.
@@ -1284,7 +1493,7 @@
   *              @arg RCC_CRS_IT_ESYNC
   * @retval None
   */
-#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  (CRS->CR &= ~(__INTERRUPT__))
+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR,(__INTERRUPT__))
 
 /** @brief  Check the CRS interrupt has occurred or not.
   * @param  __INTERRUPT__: specifies the CRS interrupt source to check.
@@ -1317,7 +1526,7 @@
 
 /**
   * @brief  Checks whether the specified CRS flag is set or not.
-  * @param  _FLAG_: specifies the flag to check.
+  * @param  __FLAG__: specifies the flag to check.
   *          This parameter can be one of the following values:
   *              @arg RCC_CRS_FLAG_SYNCOK
   *              @arg RCC_CRS_FLAG_SYNCWARN
@@ -1354,32 +1563,28 @@
 /**
   * @brief  Enables the oscillator clock for frequency error counter.
   * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.
-  * @param  None
   * @retval None
   */
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN)
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
 
 /**
   * @brief  Disables the oscillator clock for frequency error counter.
-  * @param  None
   * @retval None
   */
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER()  (CRS->CR &= ~CRS_CR_CEN)
+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE()  CLEAR_BIT(CRS->CR,CRS_CR_CEN)
 
 /**
   * @brief  Enables the automatic hardware adjustment of TRIM bits.
   * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
-  * @param  None
   * @retval None
   */
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB()  (CRS->CR |= CRS_CR_AUTOTRIMEN)
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
 
 /**
   * @brief  Enables or disables the automatic hardware adjustment of TRIM bits.
-  * @param  None
   * @retval None
   */
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB()  (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()  CLEAR_BIT(CRS->CR,CRS_CR_AUTOTRIMEN)
 
 /**
   * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies
@@ -1387,13 +1592,13 @@
   *             of the synchronization source after prescaling. It is then decreased by one in order to 
   *             reach the expected synchronization on the zero value. The formula is the following:
   *             RELOAD = (fTARGET / fSYNC) -1
-  * @param  _FTARGET_ Target frequency (value in Hz)
-  * @param  _FSYNC_ Synchronization signal frequency (value in Hz)
+  * @param  __FTARGET__ Target frequency (value in Hz)
+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)
   * @retval None
   */
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1)
+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1)
 
-#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
 
 #if defined(STM32L073xx) || defined(STM32L083xx) || \
     defined(STM32L072xx) || defined(STM32L082xx) || \
@@ -1451,16 +1656,21 @@
   */
 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
 void                  HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+uint32_t              HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
 void                  HAL_RCCEx_EnableLSECSS(void);
 void                  HAL_RCCEx_DisableLSECSS(void);
-#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
+void                  HAL_RCCEx_EnableLSECSS_IT(void);
+void                  HAL_RCCEx_LSECSS_IRQHandler(void);
+void                  HAL_RCCEx_LSECSS_Callback(void);
+
+#if !defined(STM32L011xx) && !defined(STM32L021xx) && !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
 void                  HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
 void                  HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
 void                  HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
 uint32_t              HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
 void HAL_RCCEx_EnableHSI48_VREFINT(void);
 void HAL_RCCEx_DisableHSI48_VREFINT(void);
-#endif /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
+#endif /* !(STM32L011xx) && !(STM32L021xx) && !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
 
 /**
   * @}
@@ -1469,6 +1679,129 @@
   * @}
   */ 
 
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Macros
+  * @{
+  */
+
+#if defined (STM32L052xx) || defined(STM32L062xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
+                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1))
+#elif defined (STM32L053xx) || defined(STM32L063xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
+                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD))
+#elif defined (STM32L072xx) || defined(STM32L082xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
+                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_I2C3 ))
+#elif defined (STM32L073xx) || defined(STM32L083xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC  |  \
+                                                 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1  | RCC_PERIPHCLK_I2C3 | \
+                                                 RCC_PERIPHCLK_LCD))
+#endif
+
+#if defined(STM32L011xx) || defined(STM32L021xx) || defined(STM32L031xx) || defined(STM32L041xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+                                                  RCC_PERIPHCLK_I2C1   |  RCC_PERIPHCLK_RTC    | \
+                                                  RCC_PERIPHCLK_LPTIM1))
+#elif defined(STM32L051xx) || defined(STM32L061xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
+                                                 RCC_PERIPHCLK_LPTIM1))
+#elif defined(STM32L071xx) || defined(STM32L081xx)
+#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
+                                                 RCC_PERIPHCLK_I2C1   | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC       |  \
+                                                 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))                               
+#endif
+
+#define IS_RCC_USART1CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
+                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
+                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
+                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
+                                             
+                                             
+#define IS_RCC_USART2CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
+                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
+                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
+                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
+    
+#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
+                                             ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
+                                             ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
+                                             ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
+
+#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
+                                          ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
+                                          ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
+                                          
+#define IS_RCC_I2C3CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
+                                           ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
+                                           ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
+                                           
+#define IS_RCC_USBCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
+                                          ((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
+
+#define IS_RCC_RNGCLKSOURCE(_SOURCE_)  (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \
+                                      ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
+                                      
+#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
+                                          
+#if defined(STM32L073xx) || defined(STM32L083xx) || \
+    defined(STM32L072xx) || defined(STM32L082xx) || \
+    defined(STM32L071xx) || defined(STM32L081xx)
+
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
+                             ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN ))      
+#else
+#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
+                             ((__HSI__) == RCC_HSI_DIV4))
+#endif
+
+#define IS_RCC_LPTIMCLK(__LPTIMCLK_)     (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) || \
+                                          ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI)  || \
+                                          ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI)  || \
+                                          ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
+                                          
+#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) || \
+                                             ((__SOURCE__) == RCC_StopWakeUpClock_HSI))
+
+#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW)        || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
+                                     ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
+                                     
+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) ||\
+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
+
+#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2)   ||\
+                                      ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8)   || \
+                                      ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
+                                      ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
+                                      
+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
+                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
+                                                
+#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
+
+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
+
+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
+
+#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
+                                          ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
+                                          
+/**
+  * @}
+  */
+                                          
+                                            
+/**
+  * @}
+  */
+
 /**
   * @}
   */
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Type:	Library
Created:	16 May 2016
Imports:	1
Forks:	0
Commits:	130
Dependents:	1
Dependencies:	0
Followers:	1
Diff: targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h

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