Diff: spi_dma/spi_dma_stm32f4.c

Revision:

2:0e871408d51b

Child:

18:1b1a0e68008a

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/spi_dma/spi_dma_stm32f4.c	Sat Feb 13 18:50:11 2016 +0900
@@ -0,0 +1,139 @@
+#if defined(TARGET_STM32F4)
+/*
+
+This file is licensed under Apache 2.0 license.
+(C) 2016 dinau
+
+*/
+#include "spi_dma.h"
+
+#define DMAx_CLK_ENABLE()     __DMA2_CLK_ENABLE()    
+#define SPIx_TX_DMA_STREAM    DMA2_Stream3
+#define SPIx_RX_DMA_STREAM    DMA2_Stream2
+#define SPIx_TX_DMA_CHANNEL   DMA_CHANNEL_3
+#define SPIx_RX_DMA_CHANNEL   DMA_CHANNEL_3
+
+#define readReg( reg, mask)  (  (reg) & (mask)  )    
+
+#if 0
+    static SPI_HandleTypeDef Spi2Handle;
+#endif
+
+void spi_dma_get_info( SPI_TypeDef *spi )
+{
+    SPI_HandleTypeDef *hspi;
+    if( spi == SPI1 ){
+        hspi = &Spi1Handle;
+    } 
+    #if 0
+    else {
+        hspi = &Spi2Handle;
+    }
+    #endif
+    hspi->Instance = spi;
+    hspi->Init.Mode              = readReg(spi->CR1, SPI_MODE_MASTER); 
+    hspi->Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
+    hspi->Init.Direction         = readReg(spi->CR1, SPI_CR1_BIDIMODE); 
+    hspi->Init.CLKPhase          = readReg(spi->CR1, SPI_CR1_CPHA);
+    hspi->Init.CLKPolarity       = readReg(spi->CR1, SPI_CR1_CPOL);
+    hspi->Init.CRCCalculation    = readReg(spi->CR1, SPI_CR1_CRCEN);
+    hspi->Init.CRCPolynomial     = spi->CRCPR & 0xFFFF;
+    hspi->Init.DataSize          = readReg(spi->CR1, SPI_CR1_DFF);
+    hspi->Init.FirstBit          = SPI_FIRSTBIT_MSB;
+    hspi->Init.NSS               = readReg(spi->CR1, SPI_CR1_SSM);
+    hspi->Init.TIMode            = SPI_TIMODE_DISABLED;
+    hspi->State                     = HAL_SPI_STATE_READY;
+}
+
+void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode ){
+    /* Peripheral DMA init*/
+    if( spi == SPI1 ){ 
+        /* TX: */
+        hdma_spi1_tx.Instance       = SPIx_TX_DMA_STREAM;
+        hdma_spi1_tx.Init.Channel   = SPIx_TX_DMA_CHANNEL; 
+        hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+        hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+        if (mode == DMA_SPI_READ){
+            hdma_spi1_tx.Init.MemInc = DMA_MINC_DISABLE;
+        }
+        else{
+            hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
+        }
+        hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+        hdma_spi1_tx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
+        hdma_spi1_tx.Init.Mode                = DMA_NORMAL;
+        hdma_spi1_tx.Init.Priority            = DMA_PRIORITY_HIGH;
+		/**/
+		hdma_spi1_tx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
+		hdma_spi1_tx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+		hdma_spi1_tx.Init.MemBurst            = DMA_MBURST_SINGLE;
+		hdma_spi1_tx.Init.PeriphBurst         = DMA_PBURST_SINGLE;
+		/**/
+        HAL_DMA_Init(&hdma_spi1_tx);
+        __HAL_LINKDMA( &Spi1Handle,hdmatx,hdma_spi1_tx);
+
+        /* RX: */
+        hdma_spi1_rx.Instance       = SPIx_RX_DMA_STREAM;
+		hdma_spi1_rx.Init.Channel   = SPIx_RX_DMA_CHANNEL;
+        hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+        hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+        if (mode == DMA_SPI_READ){
+            hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
+        }
+        else{
+            hdma_spi1_rx.Init.MemInc = DMA_MINC_DISABLE;
+        }
+        hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+        hdma_spi1_rx.Init.MemDataAlignment    = DMA_MDATAALIGN_BYTE;
+        hdma_spi1_rx.Init.Mode                = DMA_NORMAL;
+        hdma_spi1_rx.Init.Priority            = DMA_PRIORITY_LOW;
+		/**/
+		hdma_spi1_rx.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;         
+		hdma_spi1_rx.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
+		hdma_spi1_rx.Init.MemBurst            = DMA_MBURST_SINGLE;
+		hdma_spi1_rx.Init.PeriphBurst         = DMA_PBURST_SINGLE; 
+		/**/
+        HAL_DMA_Init(&hdma_spi1_rx);
+
+        __HAL_LINKDMA( &Spi1Handle,hdmarx,hdma_spi1_rx);
+    } 
+    #if 0
+    else if( spi == SPI2 ) {
+
+    }
+    #endif
+}
+
+void spi_dma_irq_setup( SPI_TypeDef *spi) 
+{
+    if( spi == SPI1 ) {
+        /* DMA controller clock enable */
+        DMAx_CLK_ENABLE();
+
+        /* DMA interrupt init */
+        HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 0, 1);
+        HAL_NVIC_EnableIRQ(  DMA2_Stream3_IRQn);
+        HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);
+        HAL_NVIC_EnableIRQ(  DMA2_Stream2_IRQn);
+    }
+#if 0
+    else if ( spi == SPI2 ){ 
+
+    }
+#endif
+}
+
+
+void DMA2_Stream2_IRQHandler(void)
+{
+  HAL_DMA_IRQHandler(&hdma_spi1_rx);
+}
+
+void DMA2_Stream3_IRQHandler(void)
+{
+  HAL_DMA_IRQHandler(&hdma_spi1_tx);
+}
+
+
+#endif /* TARGET_STM32F4 */
+