mi mi / SDFileSystemDMA Featured

first 2016/02 SDFileSystemDMA inherited from Official SDFileSystem.

Dependents:   SDFileSystemDMA-test DmdFullRGB_0_1

Fork of SDFileSystemDMA by mi mi

SDFileSystemDMA is enhanced SDFileSystem library for STM32 micros by using DMA functionality.
Max read transfer rate reaches over 2MByte/sec at 24MHz SPI clock if enough read buffer size is set.
Even though minimum read buffer size (512Byte) is set, read transfer rate will reach over 1MByte/sec at 24MHz SPI Clock.
( but depends on the ability of each SD card)

Test program is here.
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA-test/

/media/uploads/mimi3/sdfilesystemdma-speed-test3-read-buffer-512byte.png

/media/uploads/mimi3/sdfilesystemdma-speed-test-buffer-vs-spi-clock-nucleo-f411re-96mhz.png

Supported SPI port is shown below table.

(v): Verified. It works well.
(w): Probably it will work well. (not tested)
(c): Only compiled. (not tested)
(f): Over flash.
(r): Only read mode. (when _FS_READONLY==1)
(u) Under construction
(z): Dose not work.

Caution

If your board has SRAM less than or equal to 8KB, the buffer size must be set to 512 Bytes.

Supported Boards:
Cortex-M0

BoardSRAMSPI1SPI2SPI3
NUCLEO-F030R88KB(v)
DISCO-F051R88KB(w)
NUCLEO-F031K64KB(f)
NUCLEO-F042K66KB(r)
NUCLEO-F070RB16KB(w)
NUCLEO-F072RB16KB(w)
NUCLEO-F091RC32KB(c)

Cortex-L0

BoardSRAMSPI1SPI2SPI3
DISCO-L053C88KB(c)
NUCLEO-L053R88KB(c)
NUCLEO-L073RZ20KB(c)

Cortex-M3

BoardSRAMSPI1SPI2SPI3
DISCO-F100RB8KB(v)(v)-
BLUEPILL-F103CB20KB(w)(w)-
NUCLEO-F103RB20KB(v)(v)-
NUCLEO-L152RE80KB(v)(w)-
MOTE-L152RC32KB(w)(w)-

Cortex-M4
F3

BoardSRAMSPI1SPI2SPI3
DISCO-F303VC40KB-(v)(v)
NUCLEO-F303RE64KB(w)(w)(w)
NUCLEO-F302R816KB--(c)
NUCLEO-F303K812KB(c)--
DISCO-F334C812KB(c)--
NUCLEO-F334R812KB(c)--

F4

BoardSPI1SPI2SPI3
ELMO-F411RE(w)-(w)
MTS-MDOT-F411RE(u)-(u)
MTS-DRAGONFLY-F411RE(w)-(w)
NUCLEO-F411RE(v)-(v)
NUCLEO-F401RE(w)-(w)
MTS-MDOT-F405RG(u)-(u)
NUCLEO-F410RB(c)-(c)
NUCLEO-F446RE(c)-(c)
NUCLEO-F429ZI(c)-(c)
B96B-F446VE(c)-(c)
NUCLEO-F446ZE(c)-(c)
DISCO-F429ZI(u)-(u)
DISCO-F469NI(c)-(c)

Information

This library is set to use "short file name" in SDFileSystemDMA/FATFileSystem/ChaN/ffconf.h . ( _USE_LFN=0)
You can change this option to _USE_LFN=1 .

spi_dma/spi_dma_stm32f4.c@2:0e871408d51b, 2016-02-13 (annotated)

Committer:
mimi3
Date:
Sat Feb 13 18:50:11 2016 +0900
Revision:
2:0e871408d51b
Child:
18:1b1a0e68008a
split files for each model

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mimi3 2:0e871408d51b 1 #if defined(TARGET_STM32F4)
mimi3 2:0e871408d51b 2 /*
mimi3 2:0e871408d51b 3
mimi3 2:0e871408d51b 4 This file is licensed under Apache 2.0 license.
mimi3 2:0e871408d51b 5 (C) 2016 dinau
mimi3 2:0e871408d51b 6
mimi3 2:0e871408d51b 7 */
mimi3 2:0e871408d51b 8 #include "spi_dma.h"
mimi3 2:0e871408d51b 9
mimi3 2:0e871408d51b 10 #define DMAx_CLK_ENABLE() __DMA2_CLK_ENABLE()
mimi3 2:0e871408d51b 11 #define SPIx_TX_DMA_STREAM DMA2_Stream3
mimi3 2:0e871408d51b 12 #define SPIx_RX_DMA_STREAM DMA2_Stream2
mimi3 2:0e871408d51b 13 #define SPIx_TX_DMA_CHANNEL DMA_CHANNEL_3
mimi3 2:0e871408d51b 14 #define SPIx_RX_DMA_CHANNEL DMA_CHANNEL_3
mimi3 2:0e871408d51b 15
mimi3 2:0e871408d51b 16 #define readReg( reg, mask) ( (reg) & (mask) )
mimi3 2:0e871408d51b 17
mimi3 2:0e871408d51b 18 #if 0
mimi3 2:0e871408d51b 19 static SPI_HandleTypeDef Spi2Handle;
mimi3 2:0e871408d51b 20 #endif
mimi3 2:0e871408d51b 21
mimi3 2:0e871408d51b 22 void spi_dma_get_info( SPI_TypeDef *spi )
mimi3 2:0e871408d51b 23 {
mimi3 2:0e871408d51b 24 SPI_HandleTypeDef *hspi;
mimi3 2:0e871408d51b 25 if( spi == SPI1 ){
mimi3 2:0e871408d51b 26 hspi = &Spi1Handle;
mimi3 2:0e871408d51b 27 }
mimi3 2:0e871408d51b 28 #if 0
mimi3 2:0e871408d51b 29 else {
mimi3 2:0e871408d51b 30 hspi = &Spi2Handle;
mimi3 2:0e871408d51b 31 }
mimi3 2:0e871408d51b 32 #endif
mimi3 2:0e871408d51b 33 hspi->Instance = spi;
mimi3 2:0e871408d51b 34 hspi->Init.Mode = readReg(spi->CR1, SPI_MODE_MASTER);
mimi3 2:0e871408d51b 35 hspi->Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR);
mimi3 2:0e871408d51b 36 hspi->Init.Direction = readReg(spi->CR1, SPI_CR1_BIDIMODE);
mimi3 2:0e871408d51b 37 hspi->Init.CLKPhase = readReg(spi->CR1, SPI_CR1_CPHA);
mimi3 2:0e871408d51b 38 hspi->Init.CLKPolarity = readReg(spi->CR1, SPI_CR1_CPOL);
mimi3 2:0e871408d51b 39 hspi->Init.CRCCalculation = readReg(spi->CR1, SPI_CR1_CRCEN);
mimi3 2:0e871408d51b 40 hspi->Init.CRCPolynomial = spi->CRCPR & 0xFFFF;
mimi3 2:0e871408d51b 41 hspi->Init.DataSize = readReg(spi->CR1, SPI_CR1_DFF);
mimi3 2:0e871408d51b 42 hspi->Init.FirstBit = SPI_FIRSTBIT_MSB;
mimi3 2:0e871408d51b 43 hspi->Init.NSS = readReg(spi->CR1, SPI_CR1_SSM);
mimi3 2:0e871408d51b 44 hspi->Init.TIMode = SPI_TIMODE_DISABLED;
mimi3 2:0e871408d51b 45 hspi->State = HAL_SPI_STATE_READY;
mimi3 2:0e871408d51b 46 }
mimi3 2:0e871408d51b 47
mimi3 2:0e871408d51b 48 void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode ){
mimi3 2:0e871408d51b 49 /* Peripheral DMA init*/
mimi3 2:0e871408d51b 50 if( spi == SPI1 ){
mimi3 2:0e871408d51b 51 /* TX: */
mimi3 2:0e871408d51b 52 hdma_spi1_tx.Instance = SPIx_TX_DMA_STREAM;
mimi3 2:0e871408d51b 53 hdma_spi1_tx.Init.Channel = SPIx_TX_DMA_CHANNEL;
mimi3 2:0e871408d51b 54 hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
mimi3 2:0e871408d51b 55 hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3 2:0e871408d51b 56 if (mode == DMA_SPI_READ){
mimi3 2:0e871408d51b 57 hdma_spi1_tx.Init.MemInc = DMA_MINC_DISABLE;
mimi3 2:0e871408d51b 58 }
mimi3 2:0e871408d51b 59 else{
mimi3 2:0e871408d51b 60 hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
mimi3 2:0e871408d51b 61 }
mimi3 2:0e871408d51b 62 hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3 2:0e871408d51b 63 hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3 2:0e871408d51b 64 hdma_spi1_tx.Init.Mode = DMA_NORMAL;
mimi3 2:0e871408d51b 65 hdma_spi1_tx.Init.Priority = DMA_PRIORITY_HIGH;
mimi3 2:0e871408d51b 66 /**/
mimi3 2:0e871408d51b 67 hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
mimi3 2:0e871408d51b 68 hdma_spi1_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
mimi3 2:0e871408d51b 69 hdma_spi1_tx.Init.MemBurst = DMA_MBURST_SINGLE;
mimi3 2:0e871408d51b 70 hdma_spi1_tx.Init.PeriphBurst = DMA_PBURST_SINGLE;
mimi3 2:0e871408d51b 71 /**/
mimi3 2:0e871408d51b 72 HAL_DMA_Init(&hdma_spi1_tx);
mimi3 2:0e871408d51b 73 __HAL_LINKDMA( &Spi1Handle,hdmatx,hdma_spi1_tx);
mimi3 2:0e871408d51b 74
mimi3 2:0e871408d51b 75 /* RX: */
mimi3 2:0e871408d51b 76 hdma_spi1_rx.Instance = SPIx_RX_DMA_STREAM;
mimi3 2:0e871408d51b 77 hdma_spi1_rx.Init.Channel = SPIx_RX_DMA_CHANNEL;
mimi3 2:0e871408d51b 78 hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
mimi3 2:0e871408d51b 79 hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
mimi3 2:0e871408d51b 80 if (mode == DMA_SPI_READ){
mimi3 2:0e871408d51b 81 hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
mimi3 2:0e871408d51b 82 }
mimi3 2:0e871408d51b 83 else{
mimi3 2:0e871408d51b 84 hdma_spi1_rx.Init.MemInc = DMA_MINC_DISABLE;
mimi3 2:0e871408d51b 85 }
mimi3 2:0e871408d51b 86 hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
mimi3 2:0e871408d51b 87 hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
mimi3 2:0e871408d51b 88 hdma_spi1_rx.Init.Mode = DMA_NORMAL;
mimi3 2:0e871408d51b 89 hdma_spi1_rx.Init.Priority = DMA_PRIORITY_LOW;
mimi3 2:0e871408d51b 90 /**/
mimi3 2:0e871408d51b 91 hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
mimi3 2:0e871408d51b 92 hdma_spi1_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
mimi3 2:0e871408d51b 93 hdma_spi1_rx.Init.MemBurst = DMA_MBURST_SINGLE;
mimi3 2:0e871408d51b 94 hdma_spi1_rx.Init.PeriphBurst = DMA_PBURST_SINGLE;
mimi3 2:0e871408d51b 95 /**/
mimi3 2:0e871408d51b 96 HAL_DMA_Init(&hdma_spi1_rx);
mimi3 2:0e871408d51b 97
mimi3 2:0e871408d51b 98 __HAL_LINKDMA( &Spi1Handle,hdmarx,hdma_spi1_rx);
mimi3 2:0e871408d51b 99 }
mimi3 2:0e871408d51b 100 #if 0
mimi3 2:0e871408d51b 101 else if( spi == SPI2 ) {
mimi3 2:0e871408d51b 102
mimi3 2:0e871408d51b 103 }
mimi3 2:0e871408d51b 104 #endif
mimi3 2:0e871408d51b 105 }
mimi3 2:0e871408d51b 106
mimi3 2:0e871408d51b 107 void spi_dma_irq_setup( SPI_TypeDef *spi)
mimi3 2:0e871408d51b 108 {
mimi3 2:0e871408d51b 109 if( spi == SPI1 ) {
mimi3 2:0e871408d51b 110 /* DMA controller clock enable */
mimi3 2:0e871408d51b 111 DMAx_CLK_ENABLE();
mimi3 2:0e871408d51b 112
mimi3 2:0e871408d51b 113 /* DMA interrupt init */
mimi3 2:0e871408d51b 114 HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 0, 1);
mimi3 2:0e871408d51b 115 HAL_NVIC_EnableIRQ( DMA2_Stream3_IRQn);
mimi3 2:0e871408d51b 116 HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0);
mimi3 2:0e871408d51b 117 HAL_NVIC_EnableIRQ( DMA2_Stream2_IRQn);
mimi3 2:0e871408d51b 118 }
mimi3 2:0e871408d51b 119 #if 0
mimi3 2:0e871408d51b 120 else if ( spi == SPI2 ){
mimi3 2:0e871408d51b 121
mimi3 2:0e871408d51b 122 }
mimi3 2:0e871408d51b 123 #endif
mimi3 2:0e871408d51b 124 }
mimi3 2:0e871408d51b 125
mimi3 2:0e871408d51b 126
mimi3 2:0e871408d51b 127 void DMA2_Stream2_IRQHandler(void)
mimi3 2:0e871408d51b 128 {
mimi3 2:0e871408d51b 129 HAL_DMA_IRQHandler(&hdma_spi1_rx);
mimi3 2:0e871408d51b 130 }
mimi3 2:0e871408d51b 131
mimi3 2:0e871408d51b 132 void DMA2_Stream3_IRQHandler(void)
mimi3 2:0e871408d51b 133 {
mimi3 2:0e871408d51b 134 HAL_DMA_IRQHandler(&hdma_spi1_tx);
mimi3 2:0e871408d51b 135 }
mimi3 2:0e871408d51b 136
mimi3 2:0e871408d51b 137
mimi3 2:0e871408d51b 138 #endif /* TARGET_STM32F4 */
mimi3 2:0e871408d51b 139