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targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.c@369:2e96f1b71984, 2014-10-27 (annotated)

Committer:
mbed_official
Date:
Mon Oct 27 09:45:07 2014 +0000
Revision:
369:2e96f1b71984
Parent:
226:b062af740e40 
Synchronized with git revision 2d1f64de28cfb25c0e602532e3ce5ad1d9accbed



Full URL: https://github.com/mbedmicro/mbed/commit/2d1f64de28cfb25c0e602532e3ce5ad1d9accbed/



CMSIS: NUCLEO_F401RE - Update STM32Cube driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_eth.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 369:2e96f1b71984 5 * @version V1.1.0
mbed_official 369:2e96f1b71984 6 * @date 19-June-2014
mbed_official 87:085cde657901 7 * @brief ETH HAL module driver.
mbed_official 87:085cde657901 8 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 9 * functionalities of the Ethernet (ETH) peripheral:
mbed_official 87:085cde657901 10 * + Initialization and de-initialization functions
mbed_official 87:085cde657901 11 * + IO operation functions
mbed_official 87:085cde657901 12 * + Peripheral Control functions
mbed_official 87:085cde657901 13 * + Peripheral State and Errors functions
mbed_official 87:085cde657901 14 *
mbed_official 87:085cde657901 15 @verbatim
mbed_official 87:085cde657901 16 ==============================================================================
mbed_official 87:085cde657901 17 ##### How to use this driver #####
mbed_official 87:085cde657901 18 ==============================================================================
mbed_official 87:085cde657901 19 [..]
mbed_official 87:085cde657901 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
mbed_official 87:085cde657901 21 ETH_HandleTypeDef heth;
mbed_official 87:085cde657901 22
mbed_official 87:085cde657901 23 (#)Fill parameters of Init structure in heth handle
mbed_official 87:085cde657901 24
mbed_official 87:085cde657901 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
mbed_official 87:085cde657901 26
mbed_official 87:085cde657901 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
mbed_official 87:085cde657901 28 (##) Enable the Ethernet interface clock using
mbed_official 87:085cde657901 29 (+++) __ETHMAC_CLK_ENABLE();
mbed_official 87:085cde657901 30 (+++) __ETHMACTX_CLK_ENABLE();
mbed_official 87:085cde657901 31 (+++) __ETHMACRX_CLK_ENABLE();
mbed_official 87:085cde657901 32
mbed_official 87:085cde657901 33 (##) Initialize the related GPIO clocks
mbed_official 87:085cde657901 34 (##) Configure Ethernet pin-out
mbed_official 87:085cde657901 35 (##) Configure Ethernet NVIC interrupt (IT mode)
mbed_official 87:085cde657901 36
mbed_official 87:085cde657901 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
mbed_official 87:085cde657901 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
mbed_official 87:085cde657901 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
mbed_official 87:085cde657901 40
mbed_official 87:085cde657901 41 (#)Enable MAC and DMA transmission and reception:
mbed_official 87:085cde657901 42 (##) HAL_ETH_Start();
mbed_official 87:085cde657901 43
mbed_official 87:085cde657901 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
mbed_official 87:085cde657901 45 the frame to MAC TX FIFO:
mbed_official 87:085cde657901 46 (##) HAL_ETH_TransmitFrame();
mbed_official 87:085cde657901 47
mbed_official 87:085cde657901 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
mbed_official 87:085cde657901 49 frame parameters
mbed_official 87:085cde657901 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
mbed_official 87:085cde657901 51
mbed_official 87:085cde657901 52 (#) Get a received frame when an ETH RX interrupt occurs:
mbed_official 87:085cde657901 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
mbed_official 87:085cde657901 54
mbed_official 87:085cde657901 55 (#) Communicate with external PHY device:
mbed_official 87:085cde657901 56 (##) Read a specific register from the PHY
mbed_official 87:085cde657901 57 HAL_ETH_ReadPHYRegister();
mbed_official 87:085cde657901 58 (##) Write data to a specific RHY register:
mbed_official 87:085cde657901 59 HAL_ETH_WritePHYRegister();
mbed_official 87:085cde657901 60
mbed_official 87:085cde657901 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
mbed_official 87:085cde657901 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
mbed_official 87:085cde657901 63
mbed_official 87:085cde657901 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
mbed_official 87:085cde657901 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
mbed_official 87:085cde657901 66
mbed_official 87:085cde657901 67 @endverbatim
mbed_official 87:085cde657901 68 ******************************************************************************
mbed_official 87:085cde657901 69 * @attention
mbed_official 87:085cde657901 70 *
mbed_official 87:085cde657901 71 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 72 *
mbed_official 87:085cde657901 73 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 74 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 75 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 76 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 78 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 79 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 81 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 82 * without specific prior written permission.
mbed_official 87:085cde657901 83 *
mbed_official 87:085cde657901 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 94 *
mbed_official 87:085cde657901 95 ******************************************************************************
mbed_official 87:085cde657901 96 */
mbed_official 87:085cde657901 97
mbed_official 87:085cde657901 98 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 99 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 100
mbed_official 87:085cde657901 101 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 102 * @{
mbed_official 87:085cde657901 103 */
mbed_official 87:085cde657901 104
mbed_official 87:085cde657901 105 /** @defgroup ETH
mbed_official 87:085cde657901 106 * @brief ETH HAL module driver
mbed_official 87:085cde657901 107 * @{
mbed_official 87:085cde657901 108 */
mbed_official 87:085cde657901 109
mbed_official 87:085cde657901 110 #ifdef HAL_ETH_MODULE_ENABLED
mbed_official 87:085cde657901 111
mbed_official 87:085cde657901 112 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 87:085cde657901 113
mbed_official 87:085cde657901 114 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 115 /* Private define ------------------------------------------------------------*/
mbed_official 369:2e96f1b71984 116 #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
mbed_official 369:2e96f1b71984 117 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
mbed_official 369:2e96f1b71984 118
mbed_official 87:085cde657901 119 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 120 /* Private variables ---------------------------------------------------------*/
mbed_official 87:085cde657901 121 /* Private function prototypes -----------------------------------------------*/
mbed_official 87:085cde657901 122 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
mbed_official 87:085cde657901 123 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
mbed_official 87:085cde657901 124 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 125 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 126 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 127 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 128 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 129 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 130 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 131 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 132 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 133
mbed_official 87:085cde657901 134 /* Private functions ---------------------------------------------------------*/
mbed_official 87:085cde657901 135
mbed_official 87:085cde657901 136 /** @defgroup ETH_Private_Functions
mbed_official 87:085cde657901 137 * @{
mbed_official 87:085cde657901 138 */
mbed_official 87:085cde657901 139
mbed_official 87:085cde657901 140 /** @defgroup ETH_Group1 Initialization and de-initialization functions
mbed_official 87:085cde657901 141 * @brief Initialization and Configuration functions
mbed_official 87:085cde657901 142 *
mbed_official 87:085cde657901 143 @verbatim
mbed_official 87:085cde657901 144 ===============================================================================
mbed_official 87:085cde657901 145 ##### Initialization and de-initialization functions #####
mbed_official 87:085cde657901 146 ===============================================================================
mbed_official 87:085cde657901 147 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 148 (+) Initialize and configure the Ethernet peripheral
mbed_official 87:085cde657901 149 (+) De-initialize the Ethernet peripheral
mbed_official 87:085cde657901 150
mbed_official 87:085cde657901 151 @endverbatim
mbed_official 87:085cde657901 152 * @{
mbed_official 87:085cde657901 153 */
mbed_official 87:085cde657901 154
mbed_official 87:085cde657901 155 /**
mbed_official 87:085cde657901 156 * @brief Initializes the Ethernet MAC and DMA according to default
mbed_official 87:085cde657901 157 * parameters.
mbed_official 226:b062af740e40 158 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 159 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 160 * @retval HAL status
mbed_official 87:085cde657901 161 */
mbed_official 87:085cde657901 162 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 163 {
mbed_official 87:085cde657901 164 uint32_t tmpreg = 0, phyreg = 0;
mbed_official 87:085cde657901 165 uint32_t hclk = 60000000;
mbed_official 369:2e96f1b71984 166 uint32_t tickstart = 0;
mbed_official 87:085cde657901 167 uint32_t err = ETH_SUCCESS;
mbed_official 87:085cde657901 168
mbed_official 87:085cde657901 169 /* Check the ETH peripheral state */
mbed_official 87:085cde657901 170 if(heth == NULL)
mbed_official 87:085cde657901 171 {
mbed_official 87:085cde657901 172 return HAL_ERROR;
mbed_official 87:085cde657901 173 }
mbed_official 87:085cde657901 174
mbed_official 87:085cde657901 175 /* Check parameters */
mbed_official 87:085cde657901 176 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
mbed_official 87:085cde657901 177 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
mbed_official 87:085cde657901 178 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
mbed_official 87:085cde657901 179 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
mbed_official 87:085cde657901 180
mbed_official 87:085cde657901 181 if(heth->State == HAL_ETH_STATE_RESET)
mbed_official 87:085cde657901 182 {
mbed_official 87:085cde657901 183 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 87:085cde657901 184 HAL_ETH_MspInit(heth);
mbed_official 87:085cde657901 185 }
mbed_official 87:085cde657901 186
mbed_official 87:085cde657901 187 /* Enable SYSCFG Clock */
mbed_official 87:085cde657901 188 __SYSCFG_CLK_ENABLE();
mbed_official 87:085cde657901 189
mbed_official 87:085cde657901 190 /* Select MII or RMII Mode*/
mbed_official 87:085cde657901 191 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
mbed_official 87:085cde657901 192 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
mbed_official 87:085cde657901 193
mbed_official 87:085cde657901 194 /* Ethernet Software reset */
mbed_official 87:085cde657901 195 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
mbed_official 87:085cde657901 196 /* After reset all the registers holds their respective reset values */
mbed_official 87:085cde657901 197 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
mbed_official 87:085cde657901 198
mbed_official 87:085cde657901 199 /* Wait for software reset */
mbed_official 87:085cde657901 200 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
mbed_official 87:085cde657901 201 {
mbed_official 87:085cde657901 202 }
mbed_official 87:085cde657901 203
mbed_official 87:085cde657901 204 /*-------------------------------- MAC Initialization ----------------------*/
mbed_official 87:085cde657901 205 /* Get the ETHERNET MACMIIAR value */
mbed_official 87:085cde657901 206 tmpreg = (heth->Instance)->MACMIIAR;
mbed_official 87:085cde657901 207 /* Clear CSR Clock Range CR[2:0] bits */
mbed_official 87:085cde657901 208 tmpreg &= MACMIIAR_CR_MASK;
mbed_official 87:085cde657901 209
mbed_official 87:085cde657901 210 /* Get hclk frequency value */
mbed_official 87:085cde657901 211 hclk = HAL_RCC_GetHCLKFreq();
mbed_official 87:085cde657901 212
mbed_official 87:085cde657901 213 /* Set CR bits depending on hclk value */
mbed_official 87:085cde657901 214 if((hclk >= 20000000)&&(hclk < 35000000))
mbed_official 87:085cde657901 215 {
mbed_official 87:085cde657901 216 /* CSR Clock Range between 20-35 MHz */
mbed_official 87:085cde657901 217 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
mbed_official 87:085cde657901 218 }
mbed_official 87:085cde657901 219 else if((hclk >= 35000000)&&(hclk < 60000000))
mbed_official 87:085cde657901 220 {
mbed_official 87:085cde657901 221 /* CSR Clock Range between 35-60 MHz */
mbed_official 87:085cde657901 222 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
mbed_official 87:085cde657901 223 }
mbed_official 87:085cde657901 224 else if((hclk >= 60000000)&&(hclk < 100000000))
mbed_official 87:085cde657901 225 {
mbed_official 87:085cde657901 226 /* CSR Clock Range between 60-100 MHz */
mbed_official 87:085cde657901 227 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
mbed_official 87:085cde657901 228 }
mbed_official 87:085cde657901 229 else if((hclk >= 100000000)&&(hclk < 150000000))
mbed_official 87:085cde657901 230 {
mbed_official 87:085cde657901 231 /* CSR Clock Range between 100-150 MHz */
mbed_official 87:085cde657901 232 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
mbed_official 87:085cde657901 233 }
mbed_official 87:085cde657901 234 else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
mbed_official 87:085cde657901 235 {
mbed_official 87:085cde657901 236 /* CSR Clock Range between 150-168 MHz */
mbed_official 87:085cde657901 237 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
mbed_official 87:085cde657901 238 }
mbed_official 87:085cde657901 239
mbed_official 87:085cde657901 240 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
mbed_official 87:085cde657901 241 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 242
mbed_official 87:085cde657901 243 /*-------------------- PHY initialization and configuration ----------------*/
mbed_official 87:085cde657901 244 /* Put the PHY in reset mode */
mbed_official 87:085cde657901 245 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
mbed_official 87:085cde657901 246 {
mbed_official 87:085cde657901 247 /* In case of write timeout */
mbed_official 87:085cde657901 248 err = ETH_ERROR;
mbed_official 87:085cde657901 249
mbed_official 87:085cde657901 250 /* Config MAC and DMA */
mbed_official 87:085cde657901 251 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 252
mbed_official 87:085cde657901 253 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 254 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 255
mbed_official 87:085cde657901 256 /* Return HAL_ERROR */
mbed_official 87:085cde657901 257 return HAL_ERROR;
mbed_official 87:085cde657901 258 }
mbed_official 87:085cde657901 259
mbed_official 87:085cde657901 260 /* Delay to assure PHY reset */
mbed_official 87:085cde657901 261 HAL_Delay(PHY_RESET_DELAY);
mbed_official 87:085cde657901 262
mbed_official 87:085cde657901 263 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
mbed_official 87:085cde657901 264 {
mbed_official 369:2e96f1b71984 265 /* Get tick */
mbed_official 369:2e96f1b71984 266 tickstart = HAL_GetTick();
mbed_official 369:2e96f1b71984 267
mbed_official 87:085cde657901 268 /* We wait for linked status */
mbed_official 87:085cde657901 269 do
mbed_official 87:085cde657901 270 {
mbed_official 87:085cde657901 271 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 369:2e96f1b71984 272
mbed_official 369:2e96f1b71984 273 /* Check for the Timeout */
mbed_official 369:2e96f1b71984 274 if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
mbed_official 369:2e96f1b71984 275 {
mbed_official 369:2e96f1b71984 276 /* In case of write timeout */
mbed_official 369:2e96f1b71984 277 err = ETH_ERROR;
mbed_official 87:085cde657901 278
mbed_official 369:2e96f1b71984 279 /* Config MAC and DMA */
mbed_official 369:2e96f1b71984 280 ETH_MACDMAConfig(heth, err);
mbed_official 369:2e96f1b71984 281
mbed_official 369:2e96f1b71984 282 heth->State= HAL_ETH_STATE_READY;
mbed_official 369:2e96f1b71984 283
mbed_official 369:2e96f1b71984 284 /* Process Unlocked */
mbed_official 369:2e96f1b71984 285 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 286
mbed_official 369:2e96f1b71984 287 return HAL_TIMEOUT;
mbed_official 369:2e96f1b71984 288 }
mbed_official 369:2e96f1b71984 289 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
mbed_official 369:2e96f1b71984 290
mbed_official 87:085cde657901 291
mbed_official 87:085cde657901 292 /* Enable Auto-Negotiation */
mbed_official 87:085cde657901 293 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
mbed_official 87:085cde657901 294 {
mbed_official 87:085cde657901 295 /* In case of write timeout */
mbed_official 87:085cde657901 296 err = ETH_ERROR;
mbed_official 87:085cde657901 297
mbed_official 87:085cde657901 298 /* Config MAC and DMA */
mbed_official 87:085cde657901 299 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 300
mbed_official 87:085cde657901 301 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 302 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 303
mbed_official 87:085cde657901 304 /* Return HAL_ERROR */
mbed_official 87:085cde657901 305 return HAL_ERROR;
mbed_official 87:085cde657901 306 }
mbed_official 87:085cde657901 307
mbed_official 369:2e96f1b71984 308 /* Get tick */
mbed_official 369:2e96f1b71984 309 tickstart = HAL_GetTick();
mbed_official 369:2e96f1b71984 310
mbed_official 87:085cde657901 311 /* Wait until the auto-negotiation will be completed */
mbed_official 87:085cde657901 312 do
mbed_official 87:085cde657901 313 {
mbed_official 87:085cde657901 314 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 369:2e96f1b71984 315
mbed_official 369:2e96f1b71984 316 /* Check for the Timeout */
mbed_official 369:2e96f1b71984 317 if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
mbed_official 369:2e96f1b71984 318 {
mbed_official 369:2e96f1b71984 319 /* In case of write timeout */
mbed_official 369:2e96f1b71984 320 err = ETH_ERROR;
mbed_official 369:2e96f1b71984 321
mbed_official 369:2e96f1b71984 322 /* Config MAC and DMA */
mbed_official 369:2e96f1b71984 323 ETH_MACDMAConfig(heth, err);
mbed_official 369:2e96f1b71984 324
mbed_official 369:2e96f1b71984 325 heth->State= HAL_ETH_STATE_READY;
mbed_official 369:2e96f1b71984 326
mbed_official 369:2e96f1b71984 327 /* Process Unlocked */
mbed_official 369:2e96f1b71984 328 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 329
mbed_official 369:2e96f1b71984 330 return HAL_TIMEOUT;
mbed_official 369:2e96f1b71984 331 }
mbed_official 369:2e96f1b71984 332
mbed_official 369:2e96f1b71984 333 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
mbed_official 369:2e96f1b71984 334
mbed_official 369:2e96f1b71984 335 /* Read the result of the auto-negotiation */
mbed_official 369:2e96f1b71984 336 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
mbed_official 87:085cde657901 337 {
mbed_official 369:2e96f1b71984 338 /* In case of write timeout */
mbed_official 87:085cde657901 339 err = ETH_ERROR;
mbed_official 87:085cde657901 340
mbed_official 87:085cde657901 341 /* Config MAC and DMA */
mbed_official 87:085cde657901 342 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 343
mbed_official 87:085cde657901 344 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 345 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 346
mbed_official 87:085cde657901 347 /* Return HAL_ERROR */
mbed_official 369:2e96f1b71984 348 return HAL_ERROR;
mbed_official 87:085cde657901 349 }
mbed_official 87:085cde657901 350
mbed_official 87:085cde657901 351 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
mbed_official 87:085cde657901 352 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
mbed_official 87:085cde657901 353 {
mbed_official 87:085cde657901 354 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
mbed_official 87:085cde657901 355 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 87:085cde657901 356 }
mbed_official 87:085cde657901 357 else
mbed_official 87:085cde657901 358 {
mbed_official 87:085cde657901 359 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
mbed_official 87:085cde657901 360 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
mbed_official 87:085cde657901 361 }
mbed_official 87:085cde657901 362 /* Configure the MAC with the speed fixed by the auto-negotiation process */
mbed_official 87:085cde657901 363 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
mbed_official 87:085cde657901 364 {
mbed_official 87:085cde657901 365 /* Set Ethernet speed to 10M following the auto-negotiation */
mbed_official 87:085cde657901 366 (heth->Init).Speed = ETH_SPEED_10M;
mbed_official 87:085cde657901 367 }
mbed_official 87:085cde657901 368 else
mbed_official 87:085cde657901 369 {
mbed_official 87:085cde657901 370 /* Set Ethernet speed to 100M following the auto-negotiation */
mbed_official 87:085cde657901 371 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 87:085cde657901 372 }
mbed_official 87:085cde657901 373 }
mbed_official 87:085cde657901 374 else /* AutoNegotiation Disable */
mbed_official 87:085cde657901 375 {
mbed_official 87:085cde657901 376 /* Check parameters */
mbed_official 87:085cde657901 377 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 87:085cde657901 378 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 87:085cde657901 379
mbed_official 87:085cde657901 380 /* Set MAC Speed and Duplex Mode */
mbed_official 87:085cde657901 381 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
mbed_official 87:085cde657901 382 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
mbed_official 87:085cde657901 383 {
mbed_official 87:085cde657901 384 /* In case of write timeout */
mbed_official 87:085cde657901 385 err = ETH_ERROR;
mbed_official 87:085cde657901 386
mbed_official 87:085cde657901 387 /* Config MAC and DMA */
mbed_official 87:085cde657901 388 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 389
mbed_official 87:085cde657901 390 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 391 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 392
mbed_official 87:085cde657901 393 /* Return HAL_ERROR */
mbed_official 87:085cde657901 394 return HAL_ERROR;
mbed_official 87:085cde657901 395 }
mbed_official 87:085cde657901 396
mbed_official 87:085cde657901 397 /* Delay to assure PHY configuration */
mbed_official 87:085cde657901 398 HAL_Delay(PHY_CONFIG_DELAY);
mbed_official 87:085cde657901 399 }
mbed_official 87:085cde657901 400
mbed_official 87:085cde657901 401 /* Config MAC and DMA */
mbed_official 87:085cde657901 402 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 403
mbed_official 87:085cde657901 404 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 405 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 406
mbed_official 87:085cde657901 407 /* Return function status */
mbed_official 87:085cde657901 408 return HAL_OK;
mbed_official 87:085cde657901 409 }
mbed_official 87:085cde657901 410
mbed_official 87:085cde657901 411 /**
mbed_official 87:085cde657901 412 * @brief De-Initializes the ETH peripheral.
mbed_official 226:b062af740e40 413 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 414 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 415 * @retval HAL status
mbed_official 87:085cde657901 416 */
mbed_official 87:085cde657901 417 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 418 {
mbed_official 87:085cde657901 419 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 420 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 421
mbed_official 87:085cde657901 422 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 87:085cde657901 423 HAL_ETH_MspDeInit(heth);
mbed_official 87:085cde657901 424
mbed_official 87:085cde657901 425 /* Set ETH HAL state to Disabled */
mbed_official 87:085cde657901 426 heth->State= HAL_ETH_STATE_RESET;
mbed_official 106:ced8cbb51063 427
mbed_official 106:ced8cbb51063 428 /* Release Lock */
mbed_official 106:ced8cbb51063 429 __HAL_UNLOCK(heth);
mbed_official 106:ced8cbb51063 430
mbed_official 87:085cde657901 431 /* Return function status */
mbed_official 87:085cde657901 432 return HAL_OK;
mbed_official 87:085cde657901 433 }
mbed_official 87:085cde657901 434
mbed_official 87:085cde657901 435 /**
mbed_official 87:085cde657901 436 * @brief Initializes the DMA Tx descriptors in chain mode.
mbed_official 226:b062af740e40 437 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 438 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 439 * @param DMATxDescTab: Pointer to the first Tx desc list
mbed_official 87:085cde657901 440 * @param TxBuff: Pointer to the first TxBuffer list
mbed_official 87:085cde657901 441 * @param TxBuffCount: Number of the used Tx desc in the list
mbed_official 87:085cde657901 442 * @retval HAL status
mbed_official 87:085cde657901 443 */
mbed_official 87:085cde657901 444 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
mbed_official 87:085cde657901 445 {
mbed_official 87:085cde657901 446 uint32_t i = 0;
mbed_official 87:085cde657901 447 ETH_DMADescTypeDef *dmatxdesc;
mbed_official 87:085cde657901 448
mbed_official 87:085cde657901 449 /* Process Locked */
mbed_official 87:085cde657901 450 __HAL_LOCK(heth);
mbed_official 87:085cde657901 451
mbed_official 87:085cde657901 452 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 453 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 454
mbed_official 87:085cde657901 455 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
mbed_official 87:085cde657901 456 heth->TxDesc = DMATxDescTab;
mbed_official 87:085cde657901 457
mbed_official 87:085cde657901 458 /* Fill each DMATxDesc descriptor with the right values */
mbed_official 87:085cde657901 459 for(i=0; i < TxBuffCount; i++)
mbed_official 87:085cde657901 460 {
mbed_official 87:085cde657901 461 /* Get the pointer on the ith member of the Tx Desc list */
mbed_official 87:085cde657901 462 dmatxdesc = DMATxDescTab + i;
mbed_official 87:085cde657901 463
mbed_official 87:085cde657901 464 /* Set Second Address Chained bit */
mbed_official 87:085cde657901 465 dmatxdesc->Status = ETH_DMATXDESC_TCH;
mbed_official 87:085cde657901 466
mbed_official 87:085cde657901 467 /* Set Buffer1 address pointer */
mbed_official 87:085cde657901 468 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
mbed_official 87:085cde657901 469
mbed_official 87:085cde657901 470 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 87:085cde657901 471 {
mbed_official 87:085cde657901 472 /* Set the DMA Tx descriptors checksum insertion */
mbed_official 87:085cde657901 473 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
mbed_official 87:085cde657901 474 }
mbed_official 87:085cde657901 475
mbed_official 87:085cde657901 476 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 87:085cde657901 477 if(i < (TxBuffCount-1))
mbed_official 87:085cde657901 478 {
mbed_official 87:085cde657901 479 /* Set next descriptor address register with next descriptor base address */
mbed_official 87:085cde657901 480 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
mbed_official 87:085cde657901 481 }
mbed_official 87:085cde657901 482 else
mbed_official 87:085cde657901 483 {
mbed_official 87:085cde657901 484 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 87:085cde657901 485 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
mbed_official 87:085cde657901 486 }
mbed_official 87:085cde657901 487 }
mbed_official 87:085cde657901 488
mbed_official 87:085cde657901 489 /* Set Transmit Descriptor List Address Register */
mbed_official 87:085cde657901 490 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
mbed_official 87:085cde657901 491
mbed_official 87:085cde657901 492 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 493 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 494
mbed_official 87:085cde657901 495 /* Process Unlocked */
mbed_official 87:085cde657901 496 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 497
mbed_official 87:085cde657901 498 /* Return function status */
mbed_official 87:085cde657901 499 return HAL_OK;
mbed_official 87:085cde657901 500 }
mbed_official 87:085cde657901 501
mbed_official 87:085cde657901 502 /**
mbed_official 87:085cde657901 503 * @brief Initializes the DMA Rx descriptors in chain mode.
mbed_official 226:b062af740e40 504 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 505 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 506 * @param DMARxDescTab: Pointer to the first Rx desc list
mbed_official 87:085cde657901 507 * @param RxBuff: Pointer to the first RxBuffer list
mbed_official 87:085cde657901 508 * @param RxBuffCount: Number of the used Rx desc in the list
mbed_official 87:085cde657901 509 * @retval HAL status
mbed_official 87:085cde657901 510 */
mbed_official 87:085cde657901 511 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
mbed_official 87:085cde657901 512 {
mbed_official 87:085cde657901 513 uint32_t i = 0;
mbed_official 87:085cde657901 514 ETH_DMADescTypeDef *DMARxDesc;
mbed_official 87:085cde657901 515
mbed_official 87:085cde657901 516 /* Process Locked */
mbed_official 87:085cde657901 517 __HAL_LOCK(heth);
mbed_official 87:085cde657901 518
mbed_official 87:085cde657901 519 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 520 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 521
mbed_official 87:085cde657901 522 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
mbed_official 87:085cde657901 523 heth->RxDesc = DMARxDescTab;
mbed_official 87:085cde657901 524
mbed_official 87:085cde657901 525 /* Fill each DMARxDesc descriptor with the right values */
mbed_official 87:085cde657901 526 for(i=0; i < RxBuffCount; i++)
mbed_official 87:085cde657901 527 {
mbed_official 87:085cde657901 528 /* Get the pointer on the ith member of the Rx Desc list */
mbed_official 87:085cde657901 529 DMARxDesc = DMARxDescTab+i;
mbed_official 87:085cde657901 530
mbed_official 87:085cde657901 531 /* Set Own bit of the Rx descriptor Status */
mbed_official 87:085cde657901 532 DMARxDesc->Status = ETH_DMARXDESC_OWN;
mbed_official 87:085cde657901 533
mbed_official 87:085cde657901 534 /* Set Buffer1 size and Second Address Chained bit */
mbed_official 87:085cde657901 535 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
mbed_official 87:085cde657901 536
mbed_official 87:085cde657901 537 /* Set Buffer1 address pointer */
mbed_official 87:085cde657901 538 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
mbed_official 87:085cde657901 539
mbed_official 87:085cde657901 540 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 87:085cde657901 541 {
mbed_official 87:085cde657901 542 /* Enable Ethernet DMA Rx Descriptor interrupt */
mbed_official 87:085cde657901 543 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
mbed_official 87:085cde657901 544 }
mbed_official 87:085cde657901 545
mbed_official 87:085cde657901 546 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 87:085cde657901 547 if(i < (RxBuffCount-1))
mbed_official 87:085cde657901 548 {
mbed_official 87:085cde657901 549 /* Set next descriptor address register with next descriptor base address */
mbed_official 87:085cde657901 550 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
mbed_official 87:085cde657901 551 }
mbed_official 87:085cde657901 552 else
mbed_official 87:085cde657901 553 {
mbed_official 87:085cde657901 554 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 87:085cde657901 555 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
mbed_official 87:085cde657901 556 }
mbed_official 87:085cde657901 557 }
mbed_official 87:085cde657901 558
mbed_official 87:085cde657901 559 /* Set Receive Descriptor List Address Register */
mbed_official 87:085cde657901 560 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
mbed_official 87:085cde657901 561
mbed_official 87:085cde657901 562 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 563 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 564
mbed_official 87:085cde657901 565 /* Process Unlocked */
mbed_official 87:085cde657901 566 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 567
mbed_official 87:085cde657901 568 /* Return function status */
mbed_official 87:085cde657901 569 return HAL_OK;
mbed_official 87:085cde657901 570 }
mbed_official 87:085cde657901 571
mbed_official 87:085cde657901 572 /**
mbed_official 87:085cde657901 573 * @brief Initializes the ETH MSP.
mbed_official 226:b062af740e40 574 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 575 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 576 * @retval None
mbed_official 87:085cde657901 577 */
mbed_official 87:085cde657901 578 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 579 {
mbed_official 87:085cde657901 580 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 581 the HAL_ETH_MspInit could be implemented in the user file
mbed_official 87:085cde657901 582 */
mbed_official 87:085cde657901 583 }
mbed_official 87:085cde657901 584
mbed_official 87:085cde657901 585 /**
mbed_official 87:085cde657901 586 * @brief DeInitializes ETH MSP.
mbed_official 226:b062af740e40 587 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 588 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 589 * @retval None
mbed_official 87:085cde657901 590 */
mbed_official 87:085cde657901 591 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 592 {
mbed_official 87:085cde657901 593 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 594 the HAL_ETH_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 595 */
mbed_official 87:085cde657901 596 }
mbed_official 87:085cde657901 597
mbed_official 87:085cde657901 598 /**
mbed_official 87:085cde657901 599 * @}
mbed_official 87:085cde657901 600 */
mbed_official 87:085cde657901 601
mbed_official 87:085cde657901 602 /** @defgroup ETH_Group2 IO operation functions
mbed_official 87:085cde657901 603 * @brief Data transfers functions
mbed_official 87:085cde657901 604 *
mbed_official 87:085cde657901 605 @verbatim
mbed_official 87:085cde657901 606 ==============================================================================
mbed_official 87:085cde657901 607 ##### IO operation functions #####
mbed_official 87:085cde657901 608 ==============================================================================
mbed_official 87:085cde657901 609 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 610 (+) Transmit a frame
mbed_official 87:085cde657901 611 HAL_ETH_TransmitFrame();
mbed_official 87:085cde657901 612 (+) Receive a frame
mbed_official 87:085cde657901 613 HAL_ETH_GetReceivedFrame();
mbed_official 87:085cde657901 614 HAL_ETH_GetReceivedFrame_IT();
mbed_official 87:085cde657901 615 (+) Read from an External PHY register
mbed_official 87:085cde657901 616 HAL_ETH_ReadPHYRegister();
mbed_official 226:b062af740e40 617 (+) Write to an External PHY register
mbed_official 87:085cde657901 618 HAL_ETH_WritePHYRegister();
mbed_official 87:085cde657901 619
mbed_official 87:085cde657901 620 @endverbatim
mbed_official 87:085cde657901 621
mbed_official 87:085cde657901 622 * @{
mbed_official 87:085cde657901 623 */
mbed_official 87:085cde657901 624
mbed_official 87:085cde657901 625 /**
mbed_official 87:085cde657901 626 * @brief Sends an Ethernet frame.
mbed_official 226:b062af740e40 627 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 628 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 629 * @param FrameLength: Amount of data to be sent
mbed_official 87:085cde657901 630 * @retval HAL status
mbed_official 87:085cde657901 631 */
mbed_official 87:085cde657901 632 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
mbed_official 87:085cde657901 633 {
mbed_official 87:085cde657901 634 uint32_t bufcount = 0, size = 0, i = 0;
mbed_official 87:085cde657901 635
mbed_official 87:085cde657901 636 /* Process Locked */
mbed_official 87:085cde657901 637 __HAL_LOCK(heth);
mbed_official 87:085cde657901 638
mbed_official 87:085cde657901 639 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 640 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 641
mbed_official 87:085cde657901 642 if (FrameLength == 0)
mbed_official 87:085cde657901 643 {
mbed_official 87:085cde657901 644 /* Set ETH HAL state to READY */
mbed_official 87:085cde657901 645 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 646
mbed_official 87:085cde657901 647 /* Process Unlocked */
mbed_official 87:085cde657901 648 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 649
mbed_official 87:085cde657901 650 return HAL_ERROR;
mbed_official 87:085cde657901 651 }
mbed_official 87:085cde657901 652
mbed_official 87:085cde657901 653 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
mbed_official 87:085cde657901 654 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
mbed_official 87:085cde657901 655 {
mbed_official 87:085cde657901 656 /* OWN bit set */
mbed_official 87:085cde657901 657 heth->State = HAL_ETH_STATE_BUSY_TX;
mbed_official 87:085cde657901 658
mbed_official 87:085cde657901 659 /* Process Unlocked */
mbed_official 87:085cde657901 660 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 661
mbed_official 87:085cde657901 662 return HAL_ERROR;
mbed_official 87:085cde657901 663 }
mbed_official 87:085cde657901 664
mbed_official 87:085cde657901 665 /* Get the number of needed Tx buffers for the current frame */
mbed_official 87:085cde657901 666 if (FrameLength > ETH_TX_BUF_SIZE)
mbed_official 87:085cde657901 667 {
mbed_official 87:085cde657901 668 bufcount = FrameLength/ETH_TX_BUF_SIZE;
mbed_official 87:085cde657901 669 if (FrameLength % ETH_TX_BUF_SIZE)
mbed_official 87:085cde657901 670 {
mbed_official 87:085cde657901 671 bufcount++;
mbed_official 87:085cde657901 672 }
mbed_official 87:085cde657901 673 }
mbed_official 87:085cde657901 674 else
mbed_official 87:085cde657901 675 {
mbed_official 87:085cde657901 676 bufcount = 1;
mbed_official 87:085cde657901 677 }
mbed_official 87:085cde657901 678 if (bufcount == 1)
mbed_official 87:085cde657901 679 {
mbed_official 87:085cde657901 680 /* Set LAST and FIRST segment */
mbed_official 87:085cde657901 681 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
mbed_official 87:085cde657901 682 /* Set frame size */
mbed_official 87:085cde657901 683 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
mbed_official 87:085cde657901 684 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 87:085cde657901 685 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 87:085cde657901 686 /* Point to next descriptor */
mbed_official 87:085cde657901 687 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 688 }
mbed_official 87:085cde657901 689 else
mbed_official 87:085cde657901 690 {
mbed_official 87:085cde657901 691 for (i=0; i< bufcount; i++)
mbed_official 87:085cde657901 692 {
mbed_official 87:085cde657901 693 /* Clear FIRST and LAST segment bits */
mbed_official 87:085cde657901 694 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
mbed_official 87:085cde657901 695
mbed_official 87:085cde657901 696 if (i == 0)
mbed_official 87:085cde657901 697 {
mbed_official 87:085cde657901 698 /* Setting the first segment bit */
mbed_official 87:085cde657901 699 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
mbed_official 87:085cde657901 700 }
mbed_official 87:085cde657901 701
mbed_official 87:085cde657901 702 /* Program size */
mbed_official 87:085cde657901 703 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
mbed_official 87:085cde657901 704
mbed_official 87:085cde657901 705 if (i == (bufcount-1))
mbed_official 87:085cde657901 706 {
mbed_official 87:085cde657901 707 /* Setting the last segment bit */
mbed_official 87:085cde657901 708 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
mbed_official 87:085cde657901 709 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
mbed_official 87:085cde657901 710 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
mbed_official 87:085cde657901 711 }
mbed_official 87:085cde657901 712
mbed_official 87:085cde657901 713 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 87:085cde657901 714 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 87:085cde657901 715 /* point to next descriptor */
mbed_official 87:085cde657901 716 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 717 }
mbed_official 87:085cde657901 718 }
mbed_official 87:085cde657901 719
mbed_official 87:085cde657901 720 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
mbed_official 87:085cde657901 721 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
mbed_official 87:085cde657901 722 {
mbed_official 87:085cde657901 723 /* Clear TBUS ETHERNET DMA flag */
mbed_official 87:085cde657901 724 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
mbed_official 87:085cde657901 725 /* Resume DMA transmission*/
mbed_official 87:085cde657901 726 (heth->Instance)->DMATPDR = 0;
mbed_official 87:085cde657901 727 }
mbed_official 87:085cde657901 728
mbed_official 87:085cde657901 729 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 730 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 731
mbed_official 87:085cde657901 732 /* Process Unlocked */
mbed_official 87:085cde657901 733 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 734
mbed_official 87:085cde657901 735 /* Return function status */
mbed_official 87:085cde657901 736 return HAL_OK;
mbed_official 87:085cde657901 737 }
mbed_official 87:085cde657901 738
mbed_official 87:085cde657901 739 /**
mbed_official 87:085cde657901 740 * @brief Checks for received frames.
mbed_official 226:b062af740e40 741 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 742 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 743 * @retval HAL status
mbed_official 87:085cde657901 744 */
mbed_official 87:085cde657901 745 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 746 {
mbed_official 87:085cde657901 747 uint32_t framelength = 0;
mbed_official 87:085cde657901 748
mbed_official 87:085cde657901 749 /* Process Locked */
mbed_official 87:085cde657901 750 __HAL_LOCK(heth);
mbed_official 87:085cde657901 751
mbed_official 87:085cde657901 752 /* Check the ETH state to BUSY */
mbed_official 87:085cde657901 753 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 754
mbed_official 87:085cde657901 755 /* Check if segment is not owned by DMA */
mbed_official 87:085cde657901 756 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
mbed_official 87:085cde657901 757 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
mbed_official 87:085cde657901 758 {
mbed_official 87:085cde657901 759 /* Check if last segment */
mbed_official 87:085cde657901 760 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
mbed_official 87:085cde657901 761 {
mbed_official 87:085cde657901 762 /* increment segment count */
mbed_official 87:085cde657901 763 (heth->RxFrameInfos).SegCount++;
mbed_official 87:085cde657901 764
mbed_official 87:085cde657901 765 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 87:085cde657901 766 if ((heth->RxFrameInfos).SegCount == 1)
mbed_official 87:085cde657901 767 {
mbed_official 87:085cde657901 768 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
mbed_official 87:085cde657901 769 }
mbed_official 87:085cde657901 770
mbed_official 87:085cde657901 771 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 772
mbed_official 87:085cde657901 773 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 87:085cde657901 774 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 87:085cde657901 775 heth->RxFrameInfos.length = framelength;
mbed_official 87:085cde657901 776
mbed_official 87:085cde657901 777 /* Get the address of the buffer start address */
mbed_official 87:085cde657901 778 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 87:085cde657901 779 /* point to next descriptor */
mbed_official 87:085cde657901 780 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
mbed_official 87:085cde657901 781
mbed_official 87:085cde657901 782 /* Set HAL State to Ready */
mbed_official 87:085cde657901 783 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 784
mbed_official 87:085cde657901 785 /* Process Unlocked */
mbed_official 87:085cde657901 786 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 787
mbed_official 87:085cde657901 788 /* Return function status */
mbed_official 87:085cde657901 789 return HAL_OK;
mbed_official 87:085cde657901 790 }
mbed_official 87:085cde657901 791 /* Check if first segment */
mbed_official 87:085cde657901 792 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
mbed_official 87:085cde657901 793 {
mbed_official 87:085cde657901 794 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 795 (heth->RxFrameInfos).LSRxDesc = NULL;
mbed_official 87:085cde657901 796 (heth->RxFrameInfos).SegCount = 1;
mbed_official 87:085cde657901 797 /* Point to next descriptor */
mbed_official 87:085cde657901 798 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 799 }
mbed_official 87:085cde657901 800 /* Check if intermediate segment */
mbed_official 87:085cde657901 801 else
mbed_official 87:085cde657901 802 {
mbed_official 87:085cde657901 803 (heth->RxFrameInfos).SegCount++;
mbed_official 87:085cde657901 804 /* Point to next descriptor */
mbed_official 87:085cde657901 805 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 806 }
mbed_official 87:085cde657901 807 }
mbed_official 87:085cde657901 808
mbed_official 87:085cde657901 809 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 810 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 811
mbed_official 87:085cde657901 812 /* Process Unlocked */
mbed_official 87:085cde657901 813 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 814
mbed_official 369:2e96f1b71984 815 /* Return function status */
mbed_official 87:085cde657901 816 return HAL_ERROR;
mbed_official 87:085cde657901 817 }
mbed_official 87:085cde657901 818
mbed_official 87:085cde657901 819 /**
mbed_official 87:085cde657901 820 * @brief Gets the Received frame in interrupt mode.
mbed_official 226:b062af740e40 821 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 822 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 823 * @retval HAL status
mbed_official 87:085cde657901 824 */
mbed_official 87:085cde657901 825 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 826 {
mbed_official 87:085cde657901 827 uint32_t descriptorscancounter = 0;
mbed_official 87:085cde657901 828
mbed_official 87:085cde657901 829 /* Process Locked */
mbed_official 87:085cde657901 830 __HAL_LOCK(heth);
mbed_official 87:085cde657901 831
mbed_official 87:085cde657901 832 /* Set ETH HAL State to BUSY */
mbed_official 87:085cde657901 833 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 834
mbed_official 87:085cde657901 835 /* Scan descriptors owned by CPU */
mbed_official 87:085cde657901 836 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
mbed_official 87:085cde657901 837 {
mbed_official 87:085cde657901 838 /* Just for security */
mbed_official 87:085cde657901 839 descriptorscancounter++;
mbed_official 87:085cde657901 840
mbed_official 87:085cde657901 841 /* Check if first segment in frame */
mbed_official 87:085cde657901 842 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
mbed_official 87:085cde657901 843 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
mbed_official 87:085cde657901 844 {
mbed_official 87:085cde657901 845 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 846 heth->RxFrameInfos.SegCount = 1;
mbed_official 87:085cde657901 847 /* Point to next descriptor */
mbed_official 87:085cde657901 848 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 849 }
mbed_official 87:085cde657901 850 /* Check if intermediate segment */
mbed_official 87:085cde657901 851 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
mbed_official 87:085cde657901 852 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
mbed_official 87:085cde657901 853 {
mbed_official 87:085cde657901 854 /* Increment segment count */
mbed_official 87:085cde657901 855 (heth->RxFrameInfos.SegCount)++;
mbed_official 87:085cde657901 856 /* Point to next descriptor */
mbed_official 87:085cde657901 857 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 858 }
mbed_official 87:085cde657901 859 /* Should be last segment */
mbed_official 87:085cde657901 860 else
mbed_official 87:085cde657901 861 {
mbed_official 87:085cde657901 862 /* Last segment */
mbed_official 87:085cde657901 863 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 864
mbed_official 87:085cde657901 865 /* Increment segment count */
mbed_official 87:085cde657901 866 (heth->RxFrameInfos.SegCount)++;
mbed_official 87:085cde657901 867
mbed_official 87:085cde657901 868 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 87:085cde657901 869 if ((heth->RxFrameInfos.SegCount) == 1)
mbed_official 87:085cde657901 870 {
mbed_official 87:085cde657901 871 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 872 }
mbed_official 87:085cde657901 873
mbed_official 87:085cde657901 874 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 87:085cde657901 875 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 87:085cde657901 876
mbed_official 87:085cde657901 877 /* Get the address of the buffer start address */
mbed_official 87:085cde657901 878 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 87:085cde657901 879
mbed_official 87:085cde657901 880 /* Point to next descriptor */
mbed_official 87:085cde657901 881 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 882
mbed_official 87:085cde657901 883 /* Set HAL State to Ready */
mbed_official 87:085cde657901 884 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 885
mbed_official 87:085cde657901 886 /* Process Unlocked */
mbed_official 87:085cde657901 887 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 888
mbed_official 87:085cde657901 889 /* Return function status */
mbed_official 87:085cde657901 890 return HAL_OK;
mbed_official 87:085cde657901 891 }
mbed_official 87:085cde657901 892 }
mbed_official 87:085cde657901 893
mbed_official 87:085cde657901 894 /* Set HAL State to Ready */
mbed_official 87:085cde657901 895 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 896
mbed_official 87:085cde657901 897 /* Process Unlocked */
mbed_official 87:085cde657901 898 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 899
mbed_official 87:085cde657901 900 /* Return function status */
mbed_official 369:2e96f1b71984 901 return HAL_ERROR;
mbed_official 87:085cde657901 902 }
mbed_official 87:085cde657901 903
mbed_official 87:085cde657901 904 /**
mbed_official 87:085cde657901 905 * @brief This function handles ETH interrupt request.
mbed_official 226:b062af740e40 906 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 907 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 908 * @retval HAL status
mbed_official 87:085cde657901 909 */
mbed_official 87:085cde657901 910 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 911 {
mbed_official 87:085cde657901 912 /* Frame received */
mbed_official 87:085cde657901 913 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
mbed_official 87:085cde657901 914 {
mbed_official 87:085cde657901 915 /* Receive complete callback */
mbed_official 87:085cde657901 916 HAL_ETH_RxCpltCallback(heth);
mbed_official 87:085cde657901 917
mbed_official 87:085cde657901 918 /* Clear the Eth DMA Rx IT pending bits */
mbed_official 106:ced8cbb51063 919 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
mbed_official 87:085cde657901 920
mbed_official 87:085cde657901 921 /* Set HAL State to Ready */
mbed_official 87:085cde657901 922 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 923
mbed_official 87:085cde657901 924 /* Process Unlocked */
mbed_official 87:085cde657901 925 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 926
mbed_official 87:085cde657901 927 }
mbed_official 87:085cde657901 928 /* Frame transmitted */
mbed_official 87:085cde657901 929 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
mbed_official 87:085cde657901 930 {
mbed_official 87:085cde657901 931 /* Transfer complete callback */
mbed_official 87:085cde657901 932 HAL_ETH_TxCpltCallback(heth);
mbed_official 87:085cde657901 933
mbed_official 87:085cde657901 934 /* Clear the Eth DMA Tx IT pending bits */
mbed_official 106:ced8cbb51063 935 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
mbed_official 87:085cde657901 936
mbed_official 87:085cde657901 937 /* Set HAL State to Ready */
mbed_official 87:085cde657901 938 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 939
mbed_official 87:085cde657901 940 /* Process Unlocked */
mbed_official 87:085cde657901 941 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 942 }
mbed_official 87:085cde657901 943
mbed_official 87:085cde657901 944 /* Clear the interrupt flags */
mbed_official 106:ced8cbb51063 945 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
mbed_official 87:085cde657901 946
mbed_official 87:085cde657901 947 /* ETH DMA Error */
mbed_official 87:085cde657901 948 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
mbed_official 87:085cde657901 949 {
mbed_official 87:085cde657901 950 /* Ethernet Error callback */
mbed_official 87:085cde657901 951 HAL_ETH_ErrorCallback(heth);
mbed_official 87:085cde657901 952
mbed_official 87:085cde657901 953 /* Clear the interrupt flags */
mbed_official 106:ced8cbb51063 954 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
mbed_official 87:085cde657901 955
mbed_official 87:085cde657901 956 /* Set HAL State to Ready */
mbed_official 87:085cde657901 957 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 958
mbed_official 87:085cde657901 959 /* Process Unlocked */
mbed_official 87:085cde657901 960 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 961 }
mbed_official 87:085cde657901 962 }
mbed_official 87:085cde657901 963
mbed_official 87:085cde657901 964 /**
mbed_official 87:085cde657901 965 * @brief Tx Transfer completed callbacks.
mbed_official 226:b062af740e40 966 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 967 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 968 * @retval None
mbed_official 87:085cde657901 969 */
mbed_official 87:085cde657901 970 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 971 {
mbed_official 87:085cde657901 972 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 973 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 87:085cde657901 974 */
mbed_official 87:085cde657901 975 }
mbed_official 87:085cde657901 976
mbed_official 87:085cde657901 977 /**
mbed_official 87:085cde657901 978 * @brief Rx Transfer completed callbacks.
mbed_official 226:b062af740e40 979 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 980 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 981 * @retval None
mbed_official 87:085cde657901 982 */
mbed_official 87:085cde657901 983 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 984 {
mbed_official 87:085cde657901 985 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 986 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 87:085cde657901 987 */
mbed_official 87:085cde657901 988 }
mbed_official 87:085cde657901 989
mbed_official 87:085cde657901 990 /**
mbed_official 87:085cde657901 991 * @brief Ethernet transfer error callbacks
mbed_official 226:b062af740e40 992 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 993 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 994 * @retval None
mbed_official 87:085cde657901 995 */
mbed_official 87:085cde657901 996 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 997 {
mbed_official 87:085cde657901 998 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 999 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 87:085cde657901 1000 */
mbed_official 87:085cde657901 1001 }
mbed_official 87:085cde657901 1002
mbed_official 87:085cde657901 1003 /**
mbed_official 87:085cde657901 1004 * @brief Reads a PHY register
mbed_official 226:b062af740e40 1005 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1006 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1007 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 87:085cde657901 1008 * This parameter can be one of the following values:
mbed_official 226:b062af740e40 1009 * PHY_BCR: Transceiver Basic Control Register,
mbed_official 226:b062af740e40 1010 * PHY_BSR: Transceiver Basic Status Register.
mbed_official 226:b062af740e40 1011 * More PHY register could be read depending on the used PHY
mbed_official 87:085cde657901 1012 * @param RegValue: PHY register value
mbed_official 226:b062af740e40 1013 * @retval HAL status
mbed_official 87:085cde657901 1014 */
mbed_official 87:085cde657901 1015 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
mbed_official 87:085cde657901 1016 {
mbed_official 87:085cde657901 1017 uint32_t tmpreg = 0;
mbed_official 369:2e96f1b71984 1018 uint32_t tickstart = 0;
mbed_official 87:085cde657901 1019
mbed_official 87:085cde657901 1020 /* Check parameters */
mbed_official 87:085cde657901 1021 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 87:085cde657901 1022
mbed_official 87:085cde657901 1023 /* Check the ETH peripheral state */
mbed_official 87:085cde657901 1024 if(heth->State == HAL_ETH_STATE_BUSY_RD)
mbed_official 87:085cde657901 1025 {
mbed_official 87:085cde657901 1026 return HAL_BUSY;
mbed_official 87:085cde657901 1027 }
mbed_official 87:085cde657901 1028 /* Set ETH HAL State to BUSY_RD */
mbed_official 87:085cde657901 1029 heth->State = HAL_ETH_STATE_BUSY_RD;
mbed_official 87:085cde657901 1030
mbed_official 87:085cde657901 1031 /* Get the ETHERNET MACMIIAR value */
mbed_official 87:085cde657901 1032 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1033
mbed_official 87:085cde657901 1034 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 87:085cde657901 1035 tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official 87:085cde657901 1036
mbed_official 87:085cde657901 1037 /* Prepare the MII address register value */
mbed_official 87:085cde657901 1038 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 87:085cde657901 1039 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 87:085cde657901 1040 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
mbed_official 87:085cde657901 1041 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 87:085cde657901 1042
mbed_official 87:085cde657901 1043 /* Write the result value into the MII Address register */
mbed_official 87:085cde657901 1044 heth->Instance->MACMIIAR = tmpreg;
mbed_official 87:085cde657901 1045
mbed_official 369:2e96f1b71984 1046 /* Get tick */
mbed_official 369:2e96f1b71984 1047 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 1048
mbed_official 369:2e96f1b71984 1049 /* Check for the Busy flag */
mbed_official 369:2e96f1b71984 1050 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
mbed_official 87:085cde657901 1051 {
mbed_official 369:2e96f1b71984 1052 /* Check for the Timeout */
mbed_official 369:2e96f1b71984 1053 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
mbed_official 369:2e96f1b71984 1054 {
mbed_official 369:2e96f1b71984 1055 heth->State= HAL_ETH_STATE_READY;
mbed_official 369:2e96f1b71984 1056
mbed_official 369:2e96f1b71984 1057 /* Process Unlocked */
mbed_official 369:2e96f1b71984 1058 __HAL_UNLOCK(heth);
mbed_official 369:2e96f1b71984 1059
mbed_official 369:2e96f1b71984 1060 return HAL_TIMEOUT;
mbed_official 369:2e96f1b71984 1061 }
mbed_official 369:2e96f1b71984 1062
mbed_official 369:2e96f1b71984 1063 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1064 }
mbed_official 87:085cde657901 1065
mbed_official 87:085cde657901 1066 /* Get MACMIIDR value */
mbed_official 87:085cde657901 1067 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
mbed_official 87:085cde657901 1068
mbed_official 87:085cde657901 1069 /* Set ETH HAL State to READY */
mbed_official 87:085cde657901 1070 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1071
mbed_official 87:085cde657901 1072 /* Return function status */
mbed_official 87:085cde657901 1073 return HAL_OK;
mbed_official 87:085cde657901 1074 }
mbed_official 87:085cde657901 1075
mbed_official 87:085cde657901 1076 /**
mbed_official 87:085cde657901 1077 * @brief Writes to a PHY register.
mbed_official 226:b062af740e40 1078 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1079 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1080 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 87:085cde657901 1081 * This parameter can be one of the following values:
mbed_official 226:b062af740e40 1082 * PHY_BCR: Transceiver Control Register.
mbed_official 226:b062af740e40 1083 * More PHY register could be written depending on the used PHY
mbed_official 87:085cde657901 1084 * @param RegValue: the value to write
mbed_official 87:085cde657901 1085 * @retval HAL status
mbed_official 87:085cde657901 1086 */
mbed_official 87:085cde657901 1087 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
mbed_official 87:085cde657901 1088 {
mbed_official 87:085cde657901 1089 uint32_t tmpreg = 0;
mbed_official 369:2e96f1b71984 1090 uint32_t tickstart = 0;
mbed_official 87:085cde657901 1091
mbed_official 87:085cde657901 1092 /* Check parameters */
mbed_official 87:085cde657901 1093 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 87:085cde657901 1094
mbed_official 87:085cde657901 1095 /* Check the ETH peripheral state */
mbed_official 87:085cde657901 1096 if(heth->State == HAL_ETH_STATE_BUSY_WR)
mbed_official 87:085cde657901 1097 {
mbed_official 87:085cde657901 1098 return HAL_BUSY;
mbed_official 87:085cde657901 1099 }
mbed_official 87:085cde657901 1100 /* Set ETH HAL State to BUSY_WR */
mbed_official 87:085cde657901 1101 heth->State = HAL_ETH_STATE_BUSY_WR;
mbed_official 87:085cde657901 1102
mbed_official 87:085cde657901 1103 /* Get the ETHERNET MACMIIAR value */
mbed_official 87:085cde657901 1104 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1105
mbed_official 87:085cde657901 1106 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 87:085cde657901 1107 tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official 87:085cde657901 1108
mbed_official 87:085cde657901 1109 /* Prepare the MII register address value */
mbed_official 87:085cde657901 1110 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 87:085cde657901 1111 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 87:085cde657901 1112 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
mbed_official 87:085cde657901 1113 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 87:085cde657901 1114
mbed_official 87:085cde657901 1115 /* Give the value to the MII data register */
mbed_official 87:085cde657901 1116 heth->Instance->MACMIIDR = (uint16_t)RegValue;
mbed_official 87:085cde657901 1117
mbed_official 87:085cde657901 1118 /* Write the result value into the MII Address register */
mbed_official 87:085cde657901 1119 heth->Instance->MACMIIAR = tmpreg;
mbed_official 87:085cde657901 1120
mbed_official 369:2e96f1b71984 1121 /* Get tick */
mbed_official 369:2e96f1b71984 1122 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 1123
mbed_official 369:2e96f1b71984 1124 /* Check for the Busy flag */
mbed_official 369:2e96f1b71984 1125 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
mbed_official 87:085cde657901 1126 {
mbed_official 369:2e96f1b71984 1127 /* Check for the Timeout */
mbed_official 369:2e96f1b71984 1128 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
mbed_official 369:2e96f1b71984 1129 {
mbed_official 369:2e96f1b71984 1130 heth->State= HAL_ETH_STATE_READY;
mbed_official 369:2e96f1b71984 1131
mbed_official 369:2e96f1b71984 1132 /* Process Unlocked */
mbed_official 369:2e96f1b71984 1133 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1134
mbed_official 369:2e96f1b71984 1135 return HAL_TIMEOUT;
mbed_official 369:2e96f1b71984 1136 }
mbed_official 369:2e96f1b71984 1137
mbed_official 369:2e96f1b71984 1138 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1139 }
mbed_official 87:085cde657901 1140
mbed_official 87:085cde657901 1141 /* Set ETH HAL State to READY */
mbed_official 87:085cde657901 1142 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1143
mbed_official 87:085cde657901 1144 /* Return function status */
mbed_official 87:085cde657901 1145 return HAL_OK;
mbed_official 87:085cde657901 1146 }
mbed_official 87:085cde657901 1147
mbed_official 87:085cde657901 1148 /**
mbed_official 87:085cde657901 1149 * @}
mbed_official 87:085cde657901 1150 */
mbed_official 87:085cde657901 1151
mbed_official 87:085cde657901 1152 /** @defgroup ETH_Group3 Peripheral Control functions
mbed_official 87:085cde657901 1153 * @brief Peripheral Control functions
mbed_official 87:085cde657901 1154 *
mbed_official 87:085cde657901 1155 @verbatim
mbed_official 87:085cde657901 1156 ===============================================================================
mbed_official 87:085cde657901 1157 ##### Peripheral Control functions #####
mbed_official 87:085cde657901 1158 ===============================================================================
mbed_official 87:085cde657901 1159 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 1160 (+) Enable MAC and DMA transmission and reception.
mbed_official 87:085cde657901 1161 HAL_ETH_Start();
mbed_official 87:085cde657901 1162 (+) Disable MAC and DMA transmission and reception.
mbed_official 87:085cde657901 1163 HAL_ETH_Stop();
mbed_official 87:085cde657901 1164 (+) Set the MAC configuration in runtime mode
mbed_official 87:085cde657901 1165 HAL_ETH_ConfigMAC();
mbed_official 87:085cde657901 1166 (+) Set the DMA configuration in runtime mode
mbed_official 87:085cde657901 1167 HAL_ETH_ConfigDMA();
mbed_official 87:085cde657901 1168
mbed_official 87:085cde657901 1169 @endverbatim
mbed_official 87:085cde657901 1170 * @{
mbed_official 87:085cde657901 1171 */
mbed_official 87:085cde657901 1172
mbed_official 87:085cde657901 1173 /**
mbed_official 87:085cde657901 1174 * @brief Enables Ethernet MAC and DMA reception/transmission
mbed_official 226:b062af740e40 1175 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1176 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1177 * @retval HAL status
mbed_official 87:085cde657901 1178 */
mbed_official 87:085cde657901 1179 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1180 {
mbed_official 87:085cde657901 1181 /* Process Locked */
mbed_official 87:085cde657901 1182 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1183
mbed_official 87:085cde657901 1184 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1185 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1186
mbed_official 87:085cde657901 1187 /* Enable transmit state machine of the MAC for transmission on the MII */
mbed_official 87:085cde657901 1188 ETH_MACTransmissionEnable(heth);
mbed_official 87:085cde657901 1189
mbed_official 87:085cde657901 1190 /* Enable receive state machine of the MAC for reception from the MII */
mbed_official 87:085cde657901 1191 ETH_MACReceptionEnable(heth);
mbed_official 87:085cde657901 1192
mbed_official 87:085cde657901 1193 /* Flush Transmit FIFO */
mbed_official 87:085cde657901 1194 ETH_FlushTransmitFIFO(heth);
mbed_official 87:085cde657901 1195
mbed_official 87:085cde657901 1196 /* Start DMA transmission */
mbed_official 87:085cde657901 1197 ETH_DMATransmissionEnable(heth);
mbed_official 87:085cde657901 1198
mbed_official 87:085cde657901 1199 /* Start DMA reception */
mbed_official 87:085cde657901 1200 ETH_DMAReceptionEnable(heth);
mbed_official 87:085cde657901 1201
mbed_official 87:085cde657901 1202 /* Set the ETH state to READY*/
mbed_official 87:085cde657901 1203 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1204
mbed_official 87:085cde657901 1205 /* Process Unlocked */
mbed_official 87:085cde657901 1206 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1207
mbed_official 87:085cde657901 1208 /* Return function status */
mbed_official 87:085cde657901 1209 return HAL_OK;
mbed_official 87:085cde657901 1210 }
mbed_official 87:085cde657901 1211
mbed_official 87:085cde657901 1212 /**
mbed_official 87:085cde657901 1213 * @brief Stop Ethernet MAC and DMA reception/transmission
mbed_official 226:b062af740e40 1214 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1215 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1216 * @retval HAL status
mbed_official 87:085cde657901 1217 */
mbed_official 87:085cde657901 1218 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1219 {
mbed_official 87:085cde657901 1220 /* Process Locked */
mbed_official 87:085cde657901 1221 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1222
mbed_official 87:085cde657901 1223 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1224 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1225
mbed_official 87:085cde657901 1226 /* Stop DMA transmission */
mbed_official 87:085cde657901 1227 ETH_DMATransmissionDisable(heth);
mbed_official 87:085cde657901 1228
mbed_official 87:085cde657901 1229 /* Stop DMA reception */
mbed_official 87:085cde657901 1230 ETH_DMAReceptionDisable(heth);
mbed_official 87:085cde657901 1231
mbed_official 87:085cde657901 1232 /* Disable receive state machine of the MAC for reception from the MII */
mbed_official 87:085cde657901 1233 ETH_MACReceptionDisable(heth);
mbed_official 87:085cde657901 1234
mbed_official 87:085cde657901 1235 /* Flush Transmit FIFO */
mbed_official 87:085cde657901 1236 ETH_FlushTransmitFIFO(heth);
mbed_official 87:085cde657901 1237
mbed_official 87:085cde657901 1238 /* Disable transmit state machine of the MAC for transmission on the MII */
mbed_official 87:085cde657901 1239 ETH_MACTransmissionDisable(heth);
mbed_official 87:085cde657901 1240
mbed_official 87:085cde657901 1241 /* Set the ETH state*/
mbed_official 87:085cde657901 1242 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1243
mbed_official 87:085cde657901 1244 /* Process Unlocked */
mbed_official 87:085cde657901 1245 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1246
mbed_official 87:085cde657901 1247 /* Return function status */
mbed_official 87:085cde657901 1248 return HAL_OK;
mbed_official 87:085cde657901 1249 }
mbed_official 87:085cde657901 1250
mbed_official 87:085cde657901 1251 /**
mbed_official 87:085cde657901 1252 * @brief Set ETH MAC Configuration.
mbed_official 226:b062af740e40 1253 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1254 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1255 * @param macconf: MAC Configuration structure
mbed_official 87:085cde657901 1256 * @retval HAL status
mbed_official 87:085cde657901 1257 */
mbed_official 87:085cde657901 1258 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
mbed_official 87:085cde657901 1259 {
mbed_official 87:085cde657901 1260 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1261
mbed_official 87:085cde657901 1262 /* Process Locked */
mbed_official 87:085cde657901 1263 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1264
mbed_official 87:085cde657901 1265 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1266 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1267
mbed_official 87:085cde657901 1268 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 87:085cde657901 1269 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 87:085cde657901 1270
mbed_official 87:085cde657901 1271 if (macconf != NULL)
mbed_official 87:085cde657901 1272 {
mbed_official 87:085cde657901 1273 /* Check the parameters */
mbed_official 87:085cde657901 1274 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
mbed_official 87:085cde657901 1275 assert_param(IS_ETH_JABBER(macconf->Jabber));
mbed_official 87:085cde657901 1276 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
mbed_official 87:085cde657901 1277 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
mbed_official 87:085cde657901 1278 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
mbed_official 87:085cde657901 1279 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
mbed_official 87:085cde657901 1280 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
mbed_official 87:085cde657901 1281 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
mbed_official 87:085cde657901 1282 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
mbed_official 87:085cde657901 1283 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
mbed_official 87:085cde657901 1284 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
mbed_official 87:085cde657901 1285 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
mbed_official 87:085cde657901 1286 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
mbed_official 87:085cde657901 1287 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
mbed_official 87:085cde657901 1288 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
mbed_official 87:085cde657901 1289 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
mbed_official 87:085cde657901 1290 assert_param(IS_ETH_PROMISCIOUS_MODE(macconf->PromiscuousMode));
mbed_official 87:085cde657901 1291 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
mbed_official 87:085cde657901 1292 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
mbed_official 87:085cde657901 1293 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
mbed_official 87:085cde657901 1294 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
mbed_official 87:085cde657901 1295 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
mbed_official 87:085cde657901 1296 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
mbed_official 87:085cde657901 1297 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
mbed_official 87:085cde657901 1298 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
mbed_official 87:085cde657901 1299 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
mbed_official 87:085cde657901 1300 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
mbed_official 87:085cde657901 1301
mbed_official 87:085cde657901 1302 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 87:085cde657901 1303 /* Get the ETHERNET MACCR value */
mbed_official 87:085cde657901 1304 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1305 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 87:085cde657901 1306 tmpreg &= MACCR_CLEAR_MASK;
mbed_official 87:085cde657901 1307
mbed_official 87:085cde657901 1308 tmpreg |= (uint32_t)(macconf->Watchdog |
mbed_official 87:085cde657901 1309 macconf->Jabber |
mbed_official 87:085cde657901 1310 macconf->InterFrameGap |
mbed_official 87:085cde657901 1311 macconf->CarrierSense |
mbed_official 87:085cde657901 1312 (heth->Init).Speed |
mbed_official 87:085cde657901 1313 macconf->ReceiveOwn |
mbed_official 87:085cde657901 1314 macconf->LoopbackMode |
mbed_official 87:085cde657901 1315 (heth->Init).DuplexMode |
mbed_official 87:085cde657901 1316 macconf->ChecksumOffload |
mbed_official 87:085cde657901 1317 macconf->RetryTransmission |
mbed_official 87:085cde657901 1318 macconf->AutomaticPadCRCStrip |
mbed_official 87:085cde657901 1319 macconf->BackOffLimit |
mbed_official 87:085cde657901 1320 macconf->DeferralCheck);
mbed_official 87:085cde657901 1321
mbed_official 87:085cde657901 1322 /* Write to ETHERNET MACCR */
mbed_official 87:085cde657901 1323 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1324
mbed_official 87:085cde657901 1325 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1326 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1327 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1328 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1329 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1330
mbed_official 87:085cde657901 1331 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 87:085cde657901 1332 /* Write to ETHERNET MACFFR */
mbed_official 87:085cde657901 1333 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
mbed_official 87:085cde657901 1334 macconf->SourceAddrFilter |
mbed_official 87:085cde657901 1335 macconf->PassControlFrames |
mbed_official 87:085cde657901 1336 macconf->BroadcastFramesReception |
mbed_official 87:085cde657901 1337 macconf->DestinationAddrFilter |
mbed_official 87:085cde657901 1338 macconf->PromiscuousMode |
mbed_official 87:085cde657901 1339 macconf->MulticastFramesFilter |
mbed_official 87:085cde657901 1340 macconf->UnicastFramesFilter);
mbed_official 87:085cde657901 1341
mbed_official 87:085cde657901 1342 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1343 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1344 tmpreg = (heth->Instance)->MACFFR;
mbed_official 87:085cde657901 1345 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1346 (heth->Instance)->MACFFR = tmpreg;
mbed_official 87:085cde657901 1347
mbed_official 87:085cde657901 1348 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
mbed_official 87:085cde657901 1349 /* Write to ETHERNET MACHTHR */
mbed_official 87:085cde657901 1350 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
mbed_official 87:085cde657901 1351
mbed_official 87:085cde657901 1352 /* Write to ETHERNET MACHTLR */
mbed_official 87:085cde657901 1353 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
mbed_official 87:085cde657901 1354 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
mbed_official 87:085cde657901 1355
mbed_official 87:085cde657901 1356 /* Get the ETHERNET MACFCR value */
mbed_official 87:085cde657901 1357 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1358 /* Clear xx bits */
mbed_official 87:085cde657901 1359 tmpreg &= MACFCR_CLEAR_MASK;
mbed_official 87:085cde657901 1360
mbed_official 87:085cde657901 1361 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
mbed_official 87:085cde657901 1362 macconf->ZeroQuantaPause |
mbed_official 87:085cde657901 1363 macconf->PauseLowThreshold |
mbed_official 87:085cde657901 1364 macconf->UnicastPauseFrameDetect |
mbed_official 87:085cde657901 1365 macconf->ReceiveFlowControl |
mbed_official 87:085cde657901 1366 macconf->TransmitFlowControl);
mbed_official 87:085cde657901 1367
mbed_official 87:085cde657901 1368 /* Write to ETHERNET MACFCR */
mbed_official 87:085cde657901 1369 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1370
mbed_official 87:085cde657901 1371 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1372 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1373 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1374 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1375 (heth->Instance)->MACFCR = tmpreg;
mbed_official 87:085cde657901 1376
mbed_official 87:085cde657901 1377 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
mbed_official 87:085cde657901 1378 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
mbed_official 87:085cde657901 1379 macconf->VLANTagIdentifier);
mbed_official 87:085cde657901 1380
mbed_official 87:085cde657901 1381 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1382 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1383 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 87:085cde657901 1384 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1385 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 87:085cde657901 1386 }
mbed_official 87:085cde657901 1387 else /* macconf == NULL : here we just configure Speed and Duplex mode */
mbed_official 87:085cde657901 1388 {
mbed_official 87:085cde657901 1389 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 87:085cde657901 1390 /* Get the ETHERNET MACCR value */
mbed_official 87:085cde657901 1391 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1392
mbed_official 87:085cde657901 1393 /* Clear FES and DM bits */
mbed_official 87:085cde657901 1394 tmpreg &= ~((uint32_t)0x00004800);
mbed_official 87:085cde657901 1395
mbed_official 87:085cde657901 1396 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
mbed_official 87:085cde657901 1397
mbed_official 87:085cde657901 1398 /* Write to ETHERNET MACCR */
mbed_official 87:085cde657901 1399 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1400
mbed_official 87:085cde657901 1401 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1402 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1403 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1404 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1405 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1406 }
mbed_official 87:085cde657901 1407
mbed_official 87:085cde657901 1408 /* Set the ETH state to Ready */
mbed_official 87:085cde657901 1409 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1410
mbed_official 87:085cde657901 1411 /* Process Unlocked */
mbed_official 87:085cde657901 1412 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1413
mbed_official 87:085cde657901 1414 /* Return function status */
mbed_official 87:085cde657901 1415 return HAL_OK;
mbed_official 87:085cde657901 1416 }
mbed_official 87:085cde657901 1417
mbed_official 87:085cde657901 1418 /**
mbed_official 87:085cde657901 1419 * @brief Sets ETH DMA Configuration.
mbed_official 226:b062af740e40 1420 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1421 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1422 * @param dmaconf: DMA Configuration structure
mbed_official 87:085cde657901 1423 * @retval HAL status
mbed_official 87:085cde657901 1424 */
mbed_official 87:085cde657901 1425 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
mbed_official 87:085cde657901 1426 {
mbed_official 87:085cde657901 1427 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1428
mbed_official 87:085cde657901 1429 /* Process Locked */
mbed_official 87:085cde657901 1430 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1431
mbed_official 87:085cde657901 1432 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1433 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1434
mbed_official 87:085cde657901 1435 /* Check parameters */
mbed_official 87:085cde657901 1436 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
mbed_official 87:085cde657901 1437 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
mbed_official 87:085cde657901 1438 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
mbed_official 87:085cde657901 1439 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
mbed_official 87:085cde657901 1440 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
mbed_official 87:085cde657901 1441 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
mbed_official 87:085cde657901 1442 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
mbed_official 87:085cde657901 1443 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
mbed_official 87:085cde657901 1444 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
mbed_official 87:085cde657901 1445 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
mbed_official 87:085cde657901 1446 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
mbed_official 87:085cde657901 1447 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
mbed_official 87:085cde657901 1448 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
mbed_official 87:085cde657901 1449 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
mbed_official 87:085cde657901 1450 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
mbed_official 87:085cde657901 1451 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
mbed_official 87:085cde657901 1452
mbed_official 87:085cde657901 1453 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
mbed_official 87:085cde657901 1454 /* Get the ETHERNET DMAOMR value */
mbed_official 87:085cde657901 1455 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1456 /* Clear xx bits */
mbed_official 87:085cde657901 1457 tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official 87:085cde657901 1458
mbed_official 87:085cde657901 1459 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
mbed_official 87:085cde657901 1460 dmaconf->ReceiveStoreForward |
mbed_official 87:085cde657901 1461 dmaconf->FlushReceivedFrame |
mbed_official 87:085cde657901 1462 dmaconf->TransmitStoreForward |
mbed_official 87:085cde657901 1463 dmaconf->TransmitThresholdControl |
mbed_official 87:085cde657901 1464 dmaconf->ForwardErrorFrames |
mbed_official 87:085cde657901 1465 dmaconf->ForwardUndersizedGoodFrames |
mbed_official 87:085cde657901 1466 dmaconf->ReceiveThresholdControl |
mbed_official 87:085cde657901 1467 dmaconf->SecondFrameOperate);
mbed_official 87:085cde657901 1468
mbed_official 87:085cde657901 1469 /* Write to ETHERNET DMAOMR */
mbed_official 87:085cde657901 1470 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1471
mbed_official 87:085cde657901 1472 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1473 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1474 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1475 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1476 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 87:085cde657901 1477
mbed_official 87:085cde657901 1478 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
mbed_official 87:085cde657901 1479 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
mbed_official 87:085cde657901 1480 dmaconf->FixedBurst |
mbed_official 87:085cde657901 1481 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 87:085cde657901 1482 dmaconf->TxDMABurstLength |
mbed_official 87:085cde657901 1483 dmaconf->EnhancedDescriptorFormat |
mbed_official 87:085cde657901 1484 (dmaconf->DescriptorSkipLength << 2) |
mbed_official 87:085cde657901 1485 dmaconf->DMAArbitration |
mbed_official 87:085cde657901 1486 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 87:085cde657901 1487
mbed_official 87:085cde657901 1488 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1489 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1490 tmpreg = (heth->Instance)->DMABMR;
mbed_official 87:085cde657901 1491 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1492 (heth->Instance)->DMABMR = tmpreg;
mbed_official 87:085cde657901 1493
mbed_official 87:085cde657901 1494 /* Set the ETH state to Ready */
mbed_official 87:085cde657901 1495 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1496
mbed_official 87:085cde657901 1497 /* Process Unlocked */
mbed_official 87:085cde657901 1498 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1499
mbed_official 87:085cde657901 1500 /* Return function status */
mbed_official 87:085cde657901 1501 return HAL_OK;
mbed_official 87:085cde657901 1502 }
mbed_official 87:085cde657901 1503
mbed_official 87:085cde657901 1504 /**
mbed_official 87:085cde657901 1505 * @}
mbed_official 87:085cde657901 1506 */
mbed_official 87:085cde657901 1507
mbed_official 87:085cde657901 1508 /** @defgroup ETH_Group4 Peripheral State functions
mbed_official 87:085cde657901 1509 * @brief Peripheral State functions
mbed_official 87:085cde657901 1510 *
mbed_official 87:085cde657901 1511 @verbatim
mbed_official 87:085cde657901 1512 ===============================================================================
mbed_official 87:085cde657901 1513 ##### Peripheral State functions #####
mbed_official 87:085cde657901 1514 ===============================================================================
mbed_official 87:085cde657901 1515 [..]
mbed_official 87:085cde657901 1516 This subsection permits to get in run-time the status of the peripheral
mbed_official 87:085cde657901 1517 and the data flow.
mbed_official 87:085cde657901 1518 (+) Get the ETH handle state:
mbed_official 87:085cde657901 1519 HAL_ETH_GetState();
mbed_official 87:085cde657901 1520
mbed_official 87:085cde657901 1521
mbed_official 87:085cde657901 1522 @endverbatim
mbed_official 87:085cde657901 1523 * @{
mbed_official 87:085cde657901 1524 */
mbed_official 87:085cde657901 1525
mbed_official 87:085cde657901 1526 /**
mbed_official 87:085cde657901 1527 * @brief Return the ETH HAL state
mbed_official 226:b062af740e40 1528 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1529 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1530 * @retval HAL state
mbed_official 87:085cde657901 1531 */
mbed_official 87:085cde657901 1532 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1533 {
mbed_official 87:085cde657901 1534 /* Return ETH state */
mbed_official 87:085cde657901 1535 return heth->State;
mbed_official 87:085cde657901 1536 }
mbed_official 87:085cde657901 1537
mbed_official 87:085cde657901 1538 /**
mbed_official 87:085cde657901 1539 * @}
mbed_official 87:085cde657901 1540 */
mbed_official 87:085cde657901 1541
mbed_official 87:085cde657901 1542 /**
mbed_official 87:085cde657901 1543 * @brief Configures Ethernet MAC and DMA with default parameters.
mbed_official 226:b062af740e40 1544 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1545 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1546 * @param err: Ethernet Init error
mbed_official 87:085cde657901 1547 * @retval HAL status
mbed_official 87:085cde657901 1548 */
mbed_official 87:085cde657901 1549 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
mbed_official 87:085cde657901 1550 {
mbed_official 87:085cde657901 1551 ETH_MACInitTypeDef macinit;
mbed_official 87:085cde657901 1552 ETH_DMAInitTypeDef dmainit;
mbed_official 87:085cde657901 1553 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1554
mbed_official 87:085cde657901 1555 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
mbed_official 87:085cde657901 1556 {
mbed_official 87:085cde657901 1557 /* Set Ethernet duplex mode to Full-duplex */
mbed_official 87:085cde657901 1558 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 87:085cde657901 1559
mbed_official 87:085cde657901 1560 /* Set Ethernet speed to 100M */
mbed_official 87:085cde657901 1561 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 87:085cde657901 1562 }
mbed_official 87:085cde657901 1563
mbed_official 87:085cde657901 1564 /* Ethernet MAC default initialization **************************************/
mbed_official 87:085cde657901 1565 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
mbed_official 87:085cde657901 1566 macinit.Jabber = ETH_JABBER_ENABLE;
mbed_official 87:085cde657901 1567 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
mbed_official 87:085cde657901 1568 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
mbed_official 87:085cde657901 1569 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
mbed_official 87:085cde657901 1570 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
mbed_official 87:085cde657901 1571 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 87:085cde657901 1572 {
mbed_official 87:085cde657901 1573 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
mbed_official 87:085cde657901 1574 }
mbed_official 87:085cde657901 1575 else
mbed_official 87:085cde657901 1576 {
mbed_official 87:085cde657901 1577 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
mbed_official 87:085cde657901 1578 }
mbed_official 87:085cde657901 1579 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
mbed_official 87:085cde657901 1580 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
mbed_official 87:085cde657901 1581 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
mbed_official 87:085cde657901 1582 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
mbed_official 87:085cde657901 1583 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
mbed_official 87:085cde657901 1584 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
mbed_official 87:085cde657901 1585 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
mbed_official 87:085cde657901 1586 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
mbed_official 87:085cde657901 1587 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
mbed_official 87:085cde657901 1588 macinit.PromiscuousMode = ETH_PROMISCIOUSMODE_DISABLE;
mbed_official 87:085cde657901 1589 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
mbed_official 87:085cde657901 1590 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
mbed_official 87:085cde657901 1591 macinit.HashTableHigh = 0x0;
mbed_official 87:085cde657901 1592 macinit.HashTableLow = 0x0;
mbed_official 87:085cde657901 1593 macinit.PauseTime = 0x0;
mbed_official 87:085cde657901 1594 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
mbed_official 87:085cde657901 1595 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
mbed_official 87:085cde657901 1596 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
mbed_official 87:085cde657901 1597 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
mbed_official 87:085cde657901 1598 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
mbed_official 87:085cde657901 1599 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
mbed_official 87:085cde657901 1600 macinit.VLANTagIdentifier = 0x0;
mbed_official 87:085cde657901 1601
mbed_official 87:085cde657901 1602 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 87:085cde657901 1603 /* Get the ETHERNET MACCR value */
mbed_official 87:085cde657901 1604 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1605 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 87:085cde657901 1606 tmpreg &= MACCR_CLEAR_MASK;
mbed_official 87:085cde657901 1607 /* Set the WD bit according to ETH Watchdog value */
mbed_official 87:085cde657901 1608 /* Set the JD: bit according to ETH Jabber value */
mbed_official 87:085cde657901 1609 /* Set the IFG bit according to ETH InterFrameGap value */
mbed_official 87:085cde657901 1610 /* Set the DCRS bit according to ETH CarrierSense value */
mbed_official 87:085cde657901 1611 /* Set the FES bit according to ETH Speed value */
mbed_official 87:085cde657901 1612 /* Set the DO bit according to ETH ReceiveOwn value */
mbed_official 87:085cde657901 1613 /* Set the LM bit according to ETH LoopbackMode value */
mbed_official 87:085cde657901 1614 /* Set the DM bit according to ETH Mode value */
mbed_official 87:085cde657901 1615 /* Set the IPCO bit according to ETH ChecksumOffload value */
mbed_official 87:085cde657901 1616 /* Set the DR bit according to ETH RetryTransmission value */
mbed_official 87:085cde657901 1617 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
mbed_official 87:085cde657901 1618 /* Set the BL bit according to ETH BackOffLimit value */
mbed_official 87:085cde657901 1619 /* Set the DC bit according to ETH DeferralCheck value */
mbed_official 87:085cde657901 1620 tmpreg |= (uint32_t)(macinit.Watchdog |
mbed_official 87:085cde657901 1621 macinit.Jabber |
mbed_official 87:085cde657901 1622 macinit.InterFrameGap |
mbed_official 87:085cde657901 1623 macinit.CarrierSense |
mbed_official 87:085cde657901 1624 (heth->Init).Speed |
mbed_official 87:085cde657901 1625 macinit.ReceiveOwn |
mbed_official 87:085cde657901 1626 macinit.LoopbackMode |
mbed_official 87:085cde657901 1627 (heth->Init).DuplexMode |
mbed_official 87:085cde657901 1628 macinit.ChecksumOffload |
mbed_official 87:085cde657901 1629 macinit.RetryTransmission |
mbed_official 87:085cde657901 1630 macinit.AutomaticPadCRCStrip |
mbed_official 87:085cde657901 1631 macinit.BackOffLimit |
mbed_official 87:085cde657901 1632 macinit.DeferralCheck);
mbed_official 87:085cde657901 1633
mbed_official 87:085cde657901 1634 /* Write to ETHERNET MACCR */
mbed_official 87:085cde657901 1635 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1636
mbed_official 87:085cde657901 1637 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1638 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1639 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1640 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1641 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1642
mbed_official 87:085cde657901 1643 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 87:085cde657901 1644 /* Set the RA bit according to ETH ReceiveAll value */
mbed_official 87:085cde657901 1645 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
mbed_official 87:085cde657901 1646 /* Set the PCF bit according to ETH PassControlFrames value */
mbed_official 87:085cde657901 1647 /* Set the DBF bit according to ETH BroadcastFramesReception value */
mbed_official 87:085cde657901 1648 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
mbed_official 87:085cde657901 1649 /* Set the PR bit according to ETH PromiscuousMode value */
mbed_official 87:085cde657901 1650 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
mbed_official 87:085cde657901 1651 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
mbed_official 87:085cde657901 1652 /* Write to ETHERNET MACFFR */
mbed_official 87:085cde657901 1653 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
mbed_official 87:085cde657901 1654 macinit.SourceAddrFilter |
mbed_official 87:085cde657901 1655 macinit.PassControlFrames |
mbed_official 87:085cde657901 1656 macinit.BroadcastFramesReception |
mbed_official 87:085cde657901 1657 macinit.DestinationAddrFilter |
mbed_official 87:085cde657901 1658 macinit.PromiscuousMode |
mbed_official 87:085cde657901 1659 macinit.MulticastFramesFilter |
mbed_official 87:085cde657901 1660 macinit.UnicastFramesFilter);
mbed_official 87:085cde657901 1661
mbed_official 87:085cde657901 1662 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1663 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1664 tmpreg = (heth->Instance)->MACFFR;
mbed_official 87:085cde657901 1665 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1666 (heth->Instance)->MACFFR = tmpreg;
mbed_official 87:085cde657901 1667
mbed_official 87:085cde657901 1668 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
mbed_official 87:085cde657901 1669 /* Write to ETHERNET MACHTHR */
mbed_official 87:085cde657901 1670 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
mbed_official 87:085cde657901 1671
mbed_official 87:085cde657901 1672 /* Write to ETHERNET MACHTLR */
mbed_official 87:085cde657901 1673 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
mbed_official 87:085cde657901 1674 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
mbed_official 87:085cde657901 1675
mbed_official 87:085cde657901 1676 /* Get the ETHERNET MACFCR value */
mbed_official 87:085cde657901 1677 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1678 /* Clear xx bits */
mbed_official 87:085cde657901 1679 tmpreg &= MACFCR_CLEAR_MASK;
mbed_official 87:085cde657901 1680
mbed_official 87:085cde657901 1681 /* Set the PT bit according to ETH PauseTime value */
mbed_official 87:085cde657901 1682 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
mbed_official 87:085cde657901 1683 /* Set the PLT bit according to ETH PauseLowThreshold value */
mbed_official 87:085cde657901 1684 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
mbed_official 87:085cde657901 1685 /* Set the RFE bit according to ETH ReceiveFlowControl value */
mbed_official 87:085cde657901 1686 /* Set the TFE bit according to ETH TransmitFlowControl value */
mbed_official 87:085cde657901 1687 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
mbed_official 87:085cde657901 1688 macinit.ZeroQuantaPause |
mbed_official 87:085cde657901 1689 macinit.PauseLowThreshold |
mbed_official 87:085cde657901 1690 macinit.UnicastPauseFrameDetect |
mbed_official 87:085cde657901 1691 macinit.ReceiveFlowControl |
mbed_official 87:085cde657901 1692 macinit.TransmitFlowControl);
mbed_official 87:085cde657901 1693
mbed_official 87:085cde657901 1694 /* Write to ETHERNET MACFCR */
mbed_official 87:085cde657901 1695 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1696
mbed_official 87:085cde657901 1697 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1698 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1699 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1700 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1701 (heth->Instance)->MACFCR = tmpreg;
mbed_official 87:085cde657901 1702
mbed_official 87:085cde657901 1703 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
mbed_official 87:085cde657901 1704 /* Set the ETV bit according to ETH VLANTagComparison value */
mbed_official 87:085cde657901 1705 /* Set the VL bit according to ETH VLANTagIdentifier value */
mbed_official 87:085cde657901 1706 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
mbed_official 87:085cde657901 1707 macinit.VLANTagIdentifier);
mbed_official 87:085cde657901 1708
mbed_official 87:085cde657901 1709 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1710 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1711 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 87:085cde657901 1712 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1713 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 87:085cde657901 1714
mbed_official 87:085cde657901 1715 /* Ethernet DMA default initialization ************************************/
mbed_official 87:085cde657901 1716 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
mbed_official 87:085cde657901 1717 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
mbed_official 87:085cde657901 1718 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
mbed_official 87:085cde657901 1719 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
mbed_official 87:085cde657901 1720 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
mbed_official 87:085cde657901 1721 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
mbed_official 87:085cde657901 1722 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
mbed_official 87:085cde657901 1723 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
mbed_official 87:085cde657901 1724 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
mbed_official 87:085cde657901 1725 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
mbed_official 87:085cde657901 1726 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
mbed_official 87:085cde657901 1727 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
mbed_official 87:085cde657901 1728 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
mbed_official 87:085cde657901 1729 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
mbed_official 87:085cde657901 1730 dmainit.DescriptorSkipLength = 0x0;
mbed_official 87:085cde657901 1731 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
mbed_official 87:085cde657901 1732
mbed_official 87:085cde657901 1733 /* Get the ETHERNET DMAOMR value */
mbed_official 87:085cde657901 1734 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1735 /* Clear xx bits */
mbed_official 87:085cde657901 1736 tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official 87:085cde657901 1737
mbed_official 87:085cde657901 1738 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
mbed_official 87:085cde657901 1739 /* Set the RSF bit according to ETH ReceiveStoreForward value */
mbed_official 87:085cde657901 1740 /* Set the DFF bit according to ETH FlushReceivedFrame value */
mbed_official 87:085cde657901 1741 /* Set the TSF bit according to ETH TransmitStoreForward value */
mbed_official 87:085cde657901 1742 /* Set the TTC bit according to ETH TransmitThresholdControl value */
mbed_official 87:085cde657901 1743 /* Set the FEF bit according to ETH ForwardErrorFrames value */
mbed_official 87:085cde657901 1744 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
mbed_official 87:085cde657901 1745 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
mbed_official 87:085cde657901 1746 /* Set the OSF bit according to ETH SecondFrameOperate value */
mbed_official 87:085cde657901 1747 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
mbed_official 87:085cde657901 1748 dmainit.ReceiveStoreForward |
mbed_official 87:085cde657901 1749 dmainit.FlushReceivedFrame |
mbed_official 87:085cde657901 1750 dmainit.TransmitStoreForward |
mbed_official 87:085cde657901 1751 dmainit.TransmitThresholdControl |
mbed_official 87:085cde657901 1752 dmainit.ForwardErrorFrames |
mbed_official 87:085cde657901 1753 dmainit.ForwardUndersizedGoodFrames |
mbed_official 87:085cde657901 1754 dmainit.ReceiveThresholdControl |
mbed_official 87:085cde657901 1755 dmainit.SecondFrameOperate);
mbed_official 87:085cde657901 1756
mbed_official 87:085cde657901 1757 /* Write to ETHERNET DMAOMR */
mbed_official 87:085cde657901 1758 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1759
mbed_official 87:085cde657901 1760 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1761 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1762 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1763 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1764 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 87:085cde657901 1765
mbed_official 87:085cde657901 1766 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
mbed_official 87:085cde657901 1767 /* Set the AAL bit according to ETH AddressAlignedBeats value */
mbed_official 87:085cde657901 1768 /* Set the FB bit according to ETH FixedBurst value */
mbed_official 87:085cde657901 1769 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
mbed_official 87:085cde657901 1770 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
mbed_official 87:085cde657901 1771 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
mbed_official 87:085cde657901 1772 /* Set the DSL bit according to ETH DesciptorSkipLength value */
mbed_official 87:085cde657901 1773 /* Set the PR and DA bits according to ETH DMAArbitration value */
mbed_official 87:085cde657901 1774 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
mbed_official 87:085cde657901 1775 dmainit.FixedBurst |
mbed_official 87:085cde657901 1776 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 87:085cde657901 1777 dmainit.TxDMABurstLength |
mbed_official 87:085cde657901 1778 dmainit.EnhancedDescriptorFormat |
mbed_official 87:085cde657901 1779 (dmainit.DescriptorSkipLength << 2) |
mbed_official 87:085cde657901 1780 dmainit.DMAArbitration |
mbed_official 87:085cde657901 1781 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 87:085cde657901 1782
mbed_official 87:085cde657901 1783 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1784 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1785 tmpreg = (heth->Instance)->DMABMR;
mbed_official 87:085cde657901 1786 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1787 (heth->Instance)->DMABMR = tmpreg;
mbed_official 87:085cde657901 1788
mbed_official 87:085cde657901 1789 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 87:085cde657901 1790 {
mbed_official 87:085cde657901 1791 /* Enable the Ethernet Rx Interrupt */
mbed_official 87:085cde657901 1792 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
mbed_official 87:085cde657901 1793 }
mbed_official 87:085cde657901 1794
mbed_official 87:085cde657901 1795 /* Initialize MAC address in ethernet MAC */
mbed_official 87:085cde657901 1796 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
mbed_official 87:085cde657901 1797 }
mbed_official 87:085cde657901 1798
mbed_official 87:085cde657901 1799 /**
mbed_official 87:085cde657901 1800 * @brief Configures the selected MAC address.
mbed_official 226:b062af740e40 1801 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1802 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1803 * @param MacAddr: The MAC address to configure
mbed_official 87:085cde657901 1804 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1805 * @arg ETH_MAC_Address0: MAC Address0
mbed_official 87:085cde657901 1806 * @arg ETH_MAC_Address1: MAC Address1
mbed_official 87:085cde657901 1807 * @arg ETH_MAC_Address2: MAC Address2
mbed_official 87:085cde657901 1808 * @arg ETH_MAC_Address3: MAC Address3
mbed_official 87:085cde657901 1809 * @param Addr: Pointer to MAC address buffer data (6 bytes)
mbed_official 87:085cde657901 1810 * @retval HAL status
mbed_official 87:085cde657901 1811 */
mbed_official 87:085cde657901 1812 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
mbed_official 87:085cde657901 1813 {
mbed_official 87:085cde657901 1814 uint32_t tmpreg;
mbed_official 87:085cde657901 1815
mbed_official 87:085cde657901 1816 /* Check the parameters */
mbed_official 87:085cde657901 1817 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
mbed_official 87:085cde657901 1818
mbed_official 87:085cde657901 1819 /* Calculate the selected MAC address high register */
mbed_official 87:085cde657901 1820 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
mbed_official 87:085cde657901 1821 /* Load the selected MAC address high register */
mbed_official 87:085cde657901 1822 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
mbed_official 87:085cde657901 1823 /* Calculate the selected MAC address low register */
mbed_official 87:085cde657901 1824 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
mbed_official 87:085cde657901 1825
mbed_official 87:085cde657901 1826 /* Load the selected MAC address low register */
mbed_official 87:085cde657901 1827 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
mbed_official 87:085cde657901 1828 }
mbed_official 87:085cde657901 1829
mbed_official 87:085cde657901 1830 /**
mbed_official 87:085cde657901 1831 * @brief Enables the MAC transmission.
mbed_official 226:b062af740e40 1832 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1833 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1834 * @retval None
mbed_official 87:085cde657901 1835 */
mbed_official 87:085cde657901 1836 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1837 {
mbed_official 87:085cde657901 1838 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1839
mbed_official 87:085cde657901 1840 /* Enable the MAC transmission */
mbed_official 87:085cde657901 1841 (heth->Instance)->MACCR |= ETH_MACCR_TE;
mbed_official 87:085cde657901 1842
mbed_official 87:085cde657901 1843 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1844 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1845 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1846 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1847 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1848 }
mbed_official 87:085cde657901 1849
mbed_official 87:085cde657901 1850 /**
mbed_official 87:085cde657901 1851 * @brief Disables the MAC transmission.
mbed_official 226:b062af740e40 1852 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1853 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1854 * @retval None
mbed_official 87:085cde657901 1855 */
mbed_official 87:085cde657901 1856 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1857 {
mbed_official 87:085cde657901 1858 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1859
mbed_official 87:085cde657901 1860 /* Disable the MAC transmission */
mbed_official 87:085cde657901 1861 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
mbed_official 87:085cde657901 1862
mbed_official 87:085cde657901 1863 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1864 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1865 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1866 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1867 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1868 }
mbed_official 87:085cde657901 1869
mbed_official 87:085cde657901 1870 /**
mbed_official 87:085cde657901 1871 * @brief Enables the MAC reception.
mbed_official 226:b062af740e40 1872 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1873 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1874 * @retval None
mbed_official 87:085cde657901 1875 */
mbed_official 87:085cde657901 1876 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1877 {
mbed_official 87:085cde657901 1878 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1879
mbed_official 87:085cde657901 1880 /* Enable the MAC reception */
mbed_official 87:085cde657901 1881 (heth->Instance)->MACCR |= ETH_MACCR_RE;
mbed_official 87:085cde657901 1882
mbed_official 87:085cde657901 1883 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1884 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1885 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1886 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1887 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1888 }
mbed_official 87:085cde657901 1889
mbed_official 87:085cde657901 1890 /**
mbed_official 87:085cde657901 1891 * @brief Disables the MAC reception.
mbed_official 226:b062af740e40 1892 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1893 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1894 * @retval None
mbed_official 87:085cde657901 1895 */
mbed_official 87:085cde657901 1896 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1897 {
mbed_official 87:085cde657901 1898 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1899
mbed_official 87:085cde657901 1900 /* Disable the MAC reception */
mbed_official 87:085cde657901 1901 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
mbed_official 87:085cde657901 1902
mbed_official 87:085cde657901 1903 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1904 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1905 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1906 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1907 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1908 }
mbed_official 87:085cde657901 1909
mbed_official 87:085cde657901 1910 /**
mbed_official 87:085cde657901 1911 * @brief Enables the DMA transmission.
mbed_official 226:b062af740e40 1912 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1913 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1914 * @retval None
mbed_official 87:085cde657901 1915 */
mbed_official 87:085cde657901 1916 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1917 {
mbed_official 87:085cde657901 1918 /* Enable the DMA transmission */
mbed_official 87:085cde657901 1919 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
mbed_official 87:085cde657901 1920 }
mbed_official 87:085cde657901 1921
mbed_official 87:085cde657901 1922 /**
mbed_official 87:085cde657901 1923 * @brief Disables the DMA transmission.
mbed_official 226:b062af740e40 1924 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1925 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1926 * @retval None
mbed_official 87:085cde657901 1927 */
mbed_official 87:085cde657901 1928 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1929 {
mbed_official 87:085cde657901 1930 /* Disable the DMA transmission */
mbed_official 87:085cde657901 1931 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
mbed_official 87:085cde657901 1932 }
mbed_official 87:085cde657901 1933
mbed_official 87:085cde657901 1934 /**
mbed_official 87:085cde657901 1935 * @brief Enables the DMA reception.
mbed_official 226:b062af740e40 1936 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1937 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1938 * @retval None
mbed_official 87:085cde657901 1939 */
mbed_official 87:085cde657901 1940 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1941 {
mbed_official 87:085cde657901 1942 /* Enable the DMA reception */
mbed_official 87:085cde657901 1943 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
mbed_official 87:085cde657901 1944 }
mbed_official 87:085cde657901 1945
mbed_official 87:085cde657901 1946 /**
mbed_official 87:085cde657901 1947 * @brief Disables the DMA reception.
mbed_official 226:b062af740e40 1948 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1949 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1950 * @retval None
mbed_official 87:085cde657901 1951 */
mbed_official 87:085cde657901 1952 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1953 {
mbed_official 87:085cde657901 1954 /* Disable the DMA reception */
mbed_official 87:085cde657901 1955 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
mbed_official 87:085cde657901 1956 }
mbed_official 87:085cde657901 1957
mbed_official 87:085cde657901 1958 /**
mbed_official 87:085cde657901 1959 * @brief Clears the ETHERNET transmit FIFO.
mbed_official 226:b062af740e40 1960 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1961 * the configuration information for ETHERNET module
mbed_official 87:085cde657901 1962 * @retval None
mbed_official 87:085cde657901 1963 */
mbed_official 87:085cde657901 1964 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1965 {
mbed_official 87:085cde657901 1966 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1967
mbed_official 87:085cde657901 1968 /* Set the Flush Transmit FIFO bit */
mbed_official 87:085cde657901 1969 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
mbed_official 87:085cde657901 1970
mbed_official 87:085cde657901 1971 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1972 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1973 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1974 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1975 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 87:085cde657901 1976 }
mbed_official 87:085cde657901 1977
mbed_official 87:085cde657901 1978 /**
mbed_official 87:085cde657901 1979 * @}
mbed_official 87:085cde657901 1980 */
mbed_official 87:085cde657901 1981
mbed_official 87:085cde657901 1982 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 1983 #endif /* HAL_ETH_MODULE_ENABLED */
mbed_official 87:085cde657901 1984 /**
mbed_official 87:085cde657901 1985 * @}
mbed_official 87:085cde657901 1986 */
mbed_official 87:085cde657901 1987
mbed_official 87:085cde657901 1988 /**
mbed_official 87:085cde657901 1989 * @}
mbed_official 87:085cde657901 1990 */
mbed_official 87:085cde657901 1991
mbed_official 87:085cde657901 1992 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/