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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_eth.c@106:ced8cbb51063, 2014-02-26 (annotated)

Committer:
mbed_official
Date:
Wed Feb 26 09:45:12 2014 +0000
Revision:
106:ced8cbb51063
Parent:
87:085cde657901
Child:
226:b062af740e40
Synchronized with git revision 4222735eff5868389433f0e9271976b39c8115cd



Full URL: https://github.com/mbedmicro/mbed/commit/4222735eff5868389433f0e9271976b39c8115cd/



[NUCLEO_xxx] Update STM32CubeF4 driver V1.0.0 + update license

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_eth.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 106:ced8cbb51063 5 * @version V1.0.0
mbed_official 106:ced8cbb51063 6 * @date 18-February-2014
mbed_official 87:085cde657901 7 * @brief ETH HAL module driver.
mbed_official 87:085cde657901 8 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 9 * functionalities of the Ethernet (ETH) peripheral:
mbed_official 87:085cde657901 10 * + Initialization and de-initialization functions
mbed_official 87:085cde657901 11 * + IO operation functions
mbed_official 87:085cde657901 12 * + Peripheral Control functions
mbed_official 87:085cde657901 13 * + Peripheral State and Errors functions
mbed_official 87:085cde657901 14 *
mbed_official 87:085cde657901 15 @verbatim
mbed_official 87:085cde657901 16 ==============================================================================
mbed_official 87:085cde657901 17 ##### How to use this driver #####
mbed_official 87:085cde657901 18 ==============================================================================
mbed_official 87:085cde657901 19 [..]
mbed_official 87:085cde657901 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
mbed_official 87:085cde657901 21 ETH_HandleTypeDef heth;
mbed_official 87:085cde657901 22
mbed_official 87:085cde657901 23 (#)Fill parameters of Init structure in heth handle
mbed_official 87:085cde657901 24
mbed_official 87:085cde657901 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
mbed_official 87:085cde657901 26
mbed_official 87:085cde657901 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
mbed_official 87:085cde657901 28 (##) Enable the Ethernet interface clock using
mbed_official 87:085cde657901 29 (+++) __ETHMAC_CLK_ENABLE();
mbed_official 87:085cde657901 30 (+++) __ETHMACTX_CLK_ENABLE();
mbed_official 87:085cde657901 31 (+++) __ETHMACRX_CLK_ENABLE();
mbed_official 87:085cde657901 32
mbed_official 87:085cde657901 33 (##) Initialize the related GPIO clocks
mbed_official 87:085cde657901 34 (##) Configure Ethernet pin-out
mbed_official 87:085cde657901 35 (##) Configure Ethernet NVIC interrupt (IT mode)
mbed_official 87:085cde657901 36
mbed_official 87:085cde657901 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
mbed_official 87:085cde657901 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
mbed_official 87:085cde657901 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
mbed_official 87:085cde657901 40
mbed_official 87:085cde657901 41 (#)Enable MAC and DMA transmission and reception:
mbed_official 87:085cde657901 42 (##) HAL_ETH_Start();
mbed_official 87:085cde657901 43
mbed_official 87:085cde657901 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
mbed_official 87:085cde657901 45 the frame to MAC TX FIFO:
mbed_official 87:085cde657901 46 (##) HAL_ETH_TransmitFrame();
mbed_official 87:085cde657901 47
mbed_official 87:085cde657901 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
mbed_official 87:085cde657901 49 frame parameters
mbed_official 87:085cde657901 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
mbed_official 87:085cde657901 51
mbed_official 87:085cde657901 52 (#) Get a received frame when an ETH RX interrupt occurs:
mbed_official 87:085cde657901 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
mbed_official 87:085cde657901 54
mbed_official 87:085cde657901 55 (#) Communicate with external PHY device:
mbed_official 87:085cde657901 56 (##) Read a specific register from the PHY
mbed_official 87:085cde657901 57 HAL_ETH_ReadPHYRegister();
mbed_official 87:085cde657901 58 (##) Write data to a specific RHY register:
mbed_official 87:085cde657901 59 HAL_ETH_WritePHYRegister();
mbed_official 87:085cde657901 60
mbed_official 87:085cde657901 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
mbed_official 87:085cde657901 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
mbed_official 87:085cde657901 63
mbed_official 87:085cde657901 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
mbed_official 87:085cde657901 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
mbed_official 87:085cde657901 66
mbed_official 87:085cde657901 67 @endverbatim
mbed_official 87:085cde657901 68 ******************************************************************************
mbed_official 87:085cde657901 69 * @attention
mbed_official 87:085cde657901 70 *
mbed_official 87:085cde657901 71 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 72 *
mbed_official 87:085cde657901 73 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 74 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 75 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 76 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 77 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 78 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 79 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 80 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 81 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 82 * without specific prior written permission.
mbed_official 87:085cde657901 83 *
mbed_official 87:085cde657901 84 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 87 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 88 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 89 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 92 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 93 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 94 *
mbed_official 87:085cde657901 95 ******************************************************************************
mbed_official 87:085cde657901 96 */
mbed_official 87:085cde657901 97
mbed_official 87:085cde657901 98 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 99 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 100
mbed_official 87:085cde657901 101 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 102 * @{
mbed_official 87:085cde657901 103 */
mbed_official 87:085cde657901 104
mbed_official 87:085cde657901 105 /** @defgroup ETH
mbed_official 87:085cde657901 106 * @brief ETH HAL module driver
mbed_official 87:085cde657901 107 * @{
mbed_official 87:085cde657901 108 */
mbed_official 87:085cde657901 109
mbed_official 87:085cde657901 110 #ifdef HAL_ETH_MODULE_ENABLED
mbed_official 87:085cde657901 111
mbed_official 87:085cde657901 112 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 87:085cde657901 113
mbed_official 87:085cde657901 114 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 115 /* Private define ------------------------------------------------------------*/
mbed_official 87:085cde657901 116 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 117 /* Private variables ---------------------------------------------------------*/
mbed_official 87:085cde657901 118 /* Private function prototypes -----------------------------------------------*/
mbed_official 87:085cde657901 119 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
mbed_official 87:085cde657901 120 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
mbed_official 87:085cde657901 121 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 122 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 123 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 124 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 125 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 126 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 127 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 128 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 129 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 130
mbed_official 87:085cde657901 131 /* Private functions ---------------------------------------------------------*/
mbed_official 87:085cde657901 132
mbed_official 87:085cde657901 133 /** @defgroup ETH_Private_Functions
mbed_official 87:085cde657901 134 * @{
mbed_official 87:085cde657901 135 */
mbed_official 87:085cde657901 136
mbed_official 87:085cde657901 137 /** @defgroup ETH_Group1 Initialization and de-initialization functions
mbed_official 87:085cde657901 138 * @brief Initialization and Configuration functions
mbed_official 87:085cde657901 139 *
mbed_official 87:085cde657901 140 @verbatim
mbed_official 87:085cde657901 141 ===============================================================================
mbed_official 87:085cde657901 142 ##### Initialization and de-initialization functions #####
mbed_official 87:085cde657901 143 ===============================================================================
mbed_official 87:085cde657901 144 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 145 (+) Initialize and configure the Ethernet peripheral
mbed_official 87:085cde657901 146 (+) De-initialize the Ethernet peripheral
mbed_official 87:085cde657901 147
mbed_official 87:085cde657901 148 @endverbatim
mbed_official 87:085cde657901 149 * @{
mbed_official 87:085cde657901 150 */
mbed_official 87:085cde657901 151
mbed_official 87:085cde657901 152 /**
mbed_official 87:085cde657901 153 * @brief Initializes the Ethernet MAC and DMA according to default
mbed_official 87:085cde657901 154 * parameters.
mbed_official 87:085cde657901 155 * @param heth: ETH handle
mbed_official 87:085cde657901 156 * @retval HAL status
mbed_official 87:085cde657901 157 */
mbed_official 87:085cde657901 158 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 159 {
mbed_official 87:085cde657901 160 uint32_t tmpreg = 0, phyreg = 0;
mbed_official 87:085cde657901 161 uint32_t hclk = 60000000;
mbed_official 87:085cde657901 162 uint32_t timeout = 0;
mbed_official 87:085cde657901 163 uint32_t err = ETH_SUCCESS;
mbed_official 87:085cde657901 164
mbed_official 87:085cde657901 165 /* Check the ETH peripheral state */
mbed_official 87:085cde657901 166 if(heth == NULL)
mbed_official 87:085cde657901 167 {
mbed_official 87:085cde657901 168 return HAL_ERROR;
mbed_official 87:085cde657901 169 }
mbed_official 87:085cde657901 170
mbed_official 87:085cde657901 171 /* Check parameters */
mbed_official 87:085cde657901 172 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
mbed_official 87:085cde657901 173 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
mbed_official 87:085cde657901 174 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
mbed_official 87:085cde657901 175 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
mbed_official 87:085cde657901 176
mbed_official 87:085cde657901 177 if(heth->State == HAL_ETH_STATE_RESET)
mbed_official 87:085cde657901 178 {
mbed_official 87:085cde657901 179 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 87:085cde657901 180 HAL_ETH_MspInit(heth);
mbed_official 87:085cde657901 181 }
mbed_official 87:085cde657901 182
mbed_official 87:085cde657901 183 /* Enable SYSCFG Clock */
mbed_official 87:085cde657901 184 __SYSCFG_CLK_ENABLE();
mbed_official 87:085cde657901 185
mbed_official 87:085cde657901 186 /* Select MII or RMII Mode*/
mbed_official 87:085cde657901 187 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
mbed_official 87:085cde657901 188 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
mbed_official 87:085cde657901 189
mbed_official 87:085cde657901 190 /* Ethernet Software reset */
mbed_official 87:085cde657901 191 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
mbed_official 87:085cde657901 192 /* After reset all the registers holds their respective reset values */
mbed_official 87:085cde657901 193 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
mbed_official 87:085cde657901 194
mbed_official 87:085cde657901 195 /* Wait for software reset */
mbed_official 87:085cde657901 196 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
mbed_official 87:085cde657901 197 {
mbed_official 87:085cde657901 198 }
mbed_official 87:085cde657901 199
mbed_official 87:085cde657901 200 /*-------------------------------- MAC Initialization ----------------------*/
mbed_official 87:085cde657901 201 /* Get the ETHERNET MACMIIAR value */
mbed_official 87:085cde657901 202 tmpreg = (heth->Instance)->MACMIIAR;
mbed_official 87:085cde657901 203 /* Clear CSR Clock Range CR[2:0] bits */
mbed_official 87:085cde657901 204 tmpreg &= MACMIIAR_CR_MASK;
mbed_official 87:085cde657901 205
mbed_official 87:085cde657901 206 /* Get hclk frequency value */
mbed_official 87:085cde657901 207 hclk = HAL_RCC_GetHCLKFreq();
mbed_official 87:085cde657901 208
mbed_official 87:085cde657901 209 /* Set CR bits depending on hclk value */
mbed_official 87:085cde657901 210 if((hclk >= 20000000)&&(hclk < 35000000))
mbed_official 87:085cde657901 211 {
mbed_official 87:085cde657901 212 /* CSR Clock Range between 20-35 MHz */
mbed_official 87:085cde657901 213 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
mbed_official 87:085cde657901 214 }
mbed_official 87:085cde657901 215 else if((hclk >= 35000000)&&(hclk < 60000000))
mbed_official 87:085cde657901 216 {
mbed_official 87:085cde657901 217 /* CSR Clock Range between 35-60 MHz */
mbed_official 87:085cde657901 218 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
mbed_official 87:085cde657901 219 }
mbed_official 87:085cde657901 220 else if((hclk >= 60000000)&&(hclk < 100000000))
mbed_official 87:085cde657901 221 {
mbed_official 87:085cde657901 222 /* CSR Clock Range between 60-100 MHz */
mbed_official 87:085cde657901 223 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
mbed_official 87:085cde657901 224 }
mbed_official 87:085cde657901 225 else if((hclk >= 100000000)&&(hclk < 150000000))
mbed_official 87:085cde657901 226 {
mbed_official 87:085cde657901 227 /* CSR Clock Range between 100-150 MHz */
mbed_official 87:085cde657901 228 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
mbed_official 87:085cde657901 229 }
mbed_official 87:085cde657901 230 else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
mbed_official 87:085cde657901 231 {
mbed_official 87:085cde657901 232 /* CSR Clock Range between 150-168 MHz */
mbed_official 87:085cde657901 233 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
mbed_official 87:085cde657901 234 }
mbed_official 87:085cde657901 235
mbed_official 87:085cde657901 236 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
mbed_official 87:085cde657901 237 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 238
mbed_official 87:085cde657901 239 /*-------------------- PHY initialization and configuration ----------------*/
mbed_official 87:085cde657901 240 /* Put the PHY in reset mode */
mbed_official 87:085cde657901 241 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
mbed_official 87:085cde657901 242 {
mbed_official 87:085cde657901 243 /* In case of write timeout */
mbed_official 87:085cde657901 244 err = ETH_ERROR;
mbed_official 87:085cde657901 245
mbed_official 87:085cde657901 246 /* Config MAC and DMA */
mbed_official 87:085cde657901 247 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 248
mbed_official 87:085cde657901 249 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 250 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 251
mbed_official 87:085cde657901 252 /* Return HAL_ERROR */
mbed_official 87:085cde657901 253 return HAL_ERROR;
mbed_official 87:085cde657901 254 }
mbed_official 87:085cde657901 255
mbed_official 87:085cde657901 256 /* Delay to assure PHY reset */
mbed_official 87:085cde657901 257 HAL_Delay(PHY_RESET_DELAY);
mbed_official 87:085cde657901 258
mbed_official 87:085cde657901 259 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
mbed_official 87:085cde657901 260 {
mbed_official 87:085cde657901 261 /* We wait for linked status */
mbed_official 87:085cde657901 262 do
mbed_official 87:085cde657901 263 {
mbed_official 87:085cde657901 264 timeout++;
mbed_official 87:085cde657901 265 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 87:085cde657901 266 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS) && (timeout < PHY_READ_TO));
mbed_official 87:085cde657901 267
mbed_official 87:085cde657901 268 if(timeout == PHY_READ_TO)
mbed_official 87:085cde657901 269 {
mbed_official 87:085cde657901 270 /* In case of write timeout */
mbed_official 87:085cde657901 271 err = ETH_ERROR;
mbed_official 87:085cde657901 272
mbed_official 87:085cde657901 273 /* Config MAC and DMA */
mbed_official 87:085cde657901 274 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 275
mbed_official 87:085cde657901 276 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 277 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 278
mbed_official 87:085cde657901 279 /* Return HAL_ERROR */
mbed_official 87:085cde657901 280 return HAL_ERROR;
mbed_official 87:085cde657901 281 }
mbed_official 87:085cde657901 282
mbed_official 87:085cde657901 283 /* Reset Timeout counter */
mbed_official 87:085cde657901 284 timeout = 0;
mbed_official 87:085cde657901 285
mbed_official 87:085cde657901 286 /* Enable Auto-Negotiation */
mbed_official 87:085cde657901 287 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
mbed_official 87:085cde657901 288 {
mbed_official 87:085cde657901 289 /* In case of write timeout */
mbed_official 87:085cde657901 290 err = ETH_ERROR;
mbed_official 87:085cde657901 291
mbed_official 87:085cde657901 292 /* Config MAC and DMA */
mbed_official 87:085cde657901 293 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 294
mbed_official 87:085cde657901 295 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 296 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 297
mbed_official 87:085cde657901 298 /* Return HAL_ERROR */
mbed_official 87:085cde657901 299 return HAL_ERROR;
mbed_official 87:085cde657901 300 }
mbed_official 87:085cde657901 301
mbed_official 87:085cde657901 302 /* Wait until the auto-negotiation will be completed */
mbed_official 87:085cde657901 303 do
mbed_official 87:085cde657901 304 {
mbed_official 87:085cde657901 305 timeout++;
mbed_official 87:085cde657901 306 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 87:085cde657901 307 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE) && (timeout < PHY_READ_TO));
mbed_official 87:085cde657901 308
mbed_official 87:085cde657901 309 if(timeout == PHY_READ_TO)
mbed_official 87:085cde657901 310 {
mbed_official 87:085cde657901 311 /* In case of timeout */
mbed_official 87:085cde657901 312 err = ETH_ERROR;
mbed_official 87:085cde657901 313
mbed_official 87:085cde657901 314 /* Config MAC and DMA */
mbed_official 87:085cde657901 315 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 316
mbed_official 87:085cde657901 317 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 318 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 319
mbed_official 87:085cde657901 320 /* Return HAL_ERROR */
mbed_official 87:085cde657901 321 return HAL_ERROR;
mbed_official 87:085cde657901 322 }
mbed_official 87:085cde657901 323
mbed_official 87:085cde657901 324 /* Reset Timeout counter */
mbed_official 87:085cde657901 325 timeout = 0;
mbed_official 87:085cde657901 326
mbed_official 87:085cde657901 327 /* Read the result of the auto-negotiation */
mbed_official 87:085cde657901 328 HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg);
mbed_official 87:085cde657901 329
mbed_official 87:085cde657901 330 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
mbed_official 87:085cde657901 331 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
mbed_official 87:085cde657901 332 {
mbed_official 87:085cde657901 333 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
mbed_official 87:085cde657901 334 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 87:085cde657901 335 }
mbed_official 87:085cde657901 336 else
mbed_official 87:085cde657901 337 {
mbed_official 87:085cde657901 338 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
mbed_official 87:085cde657901 339 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
mbed_official 87:085cde657901 340 }
mbed_official 87:085cde657901 341 /* Configure the MAC with the speed fixed by the auto-negotiation process */
mbed_official 87:085cde657901 342 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
mbed_official 87:085cde657901 343 {
mbed_official 87:085cde657901 344 /* Set Ethernet speed to 10M following the auto-negotiation */
mbed_official 87:085cde657901 345 (heth->Init).Speed = ETH_SPEED_10M;
mbed_official 87:085cde657901 346 }
mbed_official 87:085cde657901 347 else
mbed_official 87:085cde657901 348 {
mbed_official 87:085cde657901 349 /* Set Ethernet speed to 100M following the auto-negotiation */
mbed_official 87:085cde657901 350 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 87:085cde657901 351 }
mbed_official 87:085cde657901 352 }
mbed_official 87:085cde657901 353 else /* AutoNegotiation Disable */
mbed_official 87:085cde657901 354 {
mbed_official 87:085cde657901 355 /* Check parameters */
mbed_official 87:085cde657901 356 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 87:085cde657901 357 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 87:085cde657901 358
mbed_official 87:085cde657901 359 /* Set MAC Speed and Duplex Mode */
mbed_official 87:085cde657901 360 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
mbed_official 87:085cde657901 361 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
mbed_official 87:085cde657901 362 {
mbed_official 87:085cde657901 363 /* In case of write timeout */
mbed_official 87:085cde657901 364 err = ETH_ERROR;
mbed_official 87:085cde657901 365
mbed_official 87:085cde657901 366 /* Config MAC and DMA */
mbed_official 87:085cde657901 367 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 368
mbed_official 87:085cde657901 369 /* Set the ETH peripheral state to READY */
mbed_official 87:085cde657901 370 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 371
mbed_official 87:085cde657901 372 /* Return HAL_ERROR */
mbed_official 87:085cde657901 373 return HAL_ERROR;
mbed_official 87:085cde657901 374 }
mbed_official 87:085cde657901 375
mbed_official 87:085cde657901 376 /* Delay to assure PHY configuration */
mbed_official 87:085cde657901 377 HAL_Delay(PHY_CONFIG_DELAY);
mbed_official 87:085cde657901 378 }
mbed_official 87:085cde657901 379
mbed_official 87:085cde657901 380 /* Config MAC and DMA */
mbed_official 87:085cde657901 381 ETH_MACDMAConfig(heth, err);
mbed_official 87:085cde657901 382
mbed_official 87:085cde657901 383 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 384 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 385
mbed_official 87:085cde657901 386 /* Return function status */
mbed_official 87:085cde657901 387 return HAL_OK;
mbed_official 87:085cde657901 388 }
mbed_official 87:085cde657901 389
mbed_official 87:085cde657901 390 /**
mbed_official 87:085cde657901 391 * @brief De-Initializes the ETH peripheral.
mbed_official 87:085cde657901 392 * @param heth: ETH handle
mbed_official 87:085cde657901 393 * @retval HAL status
mbed_official 87:085cde657901 394 */
mbed_official 87:085cde657901 395 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 396 {
mbed_official 87:085cde657901 397 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 398 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 399
mbed_official 87:085cde657901 400 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 87:085cde657901 401 HAL_ETH_MspDeInit(heth);
mbed_official 87:085cde657901 402
mbed_official 87:085cde657901 403 /* Set ETH HAL state to Disabled */
mbed_official 87:085cde657901 404 heth->State= HAL_ETH_STATE_RESET;
mbed_official 106:ced8cbb51063 405
mbed_official 106:ced8cbb51063 406 /* Release Lock */
mbed_official 106:ced8cbb51063 407 __HAL_UNLOCK(heth);
mbed_official 106:ced8cbb51063 408
mbed_official 87:085cde657901 409 /* Return function status */
mbed_official 87:085cde657901 410 return HAL_OK;
mbed_official 87:085cde657901 411 }
mbed_official 87:085cde657901 412
mbed_official 87:085cde657901 413 /**
mbed_official 87:085cde657901 414 * @brief Initializes the DMA Tx descriptors in chain mode.
mbed_official 87:085cde657901 415 * @param heth: ETH handle
mbed_official 87:085cde657901 416 * @param DMATxDescTab: Pointer to the first Tx desc list
mbed_official 87:085cde657901 417 * @param TxBuff: Pointer to the first TxBuffer list
mbed_official 87:085cde657901 418 * @param TxBuffCount: Number of the used Tx desc in the list
mbed_official 87:085cde657901 419 * @retval HAL status
mbed_official 87:085cde657901 420 */
mbed_official 87:085cde657901 421 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
mbed_official 87:085cde657901 422 {
mbed_official 87:085cde657901 423 uint32_t i = 0;
mbed_official 87:085cde657901 424 ETH_DMADescTypeDef *dmatxdesc;
mbed_official 87:085cde657901 425
mbed_official 87:085cde657901 426 /* Process Locked */
mbed_official 87:085cde657901 427 __HAL_LOCK(heth);
mbed_official 87:085cde657901 428
mbed_official 87:085cde657901 429 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 430 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 431
mbed_official 87:085cde657901 432 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
mbed_official 87:085cde657901 433 heth->TxDesc = DMATxDescTab;
mbed_official 87:085cde657901 434
mbed_official 87:085cde657901 435 /* Fill each DMATxDesc descriptor with the right values */
mbed_official 87:085cde657901 436 for(i=0; i < TxBuffCount; i++)
mbed_official 87:085cde657901 437 {
mbed_official 87:085cde657901 438 /* Get the pointer on the ith member of the Tx Desc list */
mbed_official 87:085cde657901 439 dmatxdesc = DMATxDescTab + i;
mbed_official 87:085cde657901 440
mbed_official 87:085cde657901 441 /* Set Second Address Chained bit */
mbed_official 87:085cde657901 442 dmatxdesc->Status = ETH_DMATXDESC_TCH;
mbed_official 87:085cde657901 443
mbed_official 87:085cde657901 444 /* Set Buffer1 address pointer */
mbed_official 87:085cde657901 445 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
mbed_official 87:085cde657901 446
mbed_official 87:085cde657901 447 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 87:085cde657901 448 {
mbed_official 87:085cde657901 449 /* Set the DMA Tx descriptors checksum insertion */
mbed_official 87:085cde657901 450 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
mbed_official 87:085cde657901 451 }
mbed_official 87:085cde657901 452
mbed_official 87:085cde657901 453 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 87:085cde657901 454 if(i < (TxBuffCount-1))
mbed_official 87:085cde657901 455 {
mbed_official 87:085cde657901 456 /* Set next descriptor address register with next descriptor base address */
mbed_official 87:085cde657901 457 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
mbed_official 87:085cde657901 458 }
mbed_official 87:085cde657901 459 else
mbed_official 87:085cde657901 460 {
mbed_official 87:085cde657901 461 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 87:085cde657901 462 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
mbed_official 87:085cde657901 463 }
mbed_official 87:085cde657901 464 }
mbed_official 87:085cde657901 465
mbed_official 87:085cde657901 466 /* Set Transmit Descriptor List Address Register */
mbed_official 87:085cde657901 467 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
mbed_official 87:085cde657901 468
mbed_official 87:085cde657901 469 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 470 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 471
mbed_official 87:085cde657901 472 /* Process Unlocked */
mbed_official 87:085cde657901 473 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 474
mbed_official 87:085cde657901 475 /* Return function status */
mbed_official 87:085cde657901 476 return HAL_OK;
mbed_official 87:085cde657901 477 }
mbed_official 87:085cde657901 478
mbed_official 87:085cde657901 479 /**
mbed_official 87:085cde657901 480 * @brief Initializes the DMA Rx descriptors in chain mode.
mbed_official 87:085cde657901 481 * @param heth: ETH handle
mbed_official 87:085cde657901 482 * @param DMARxDescTab: Pointer to the first Rx desc list
mbed_official 87:085cde657901 483 * @param RxBuff: Pointer to the first RxBuffer list
mbed_official 87:085cde657901 484 * @param RxBuffCount: Number of the used Rx desc in the list
mbed_official 87:085cde657901 485 * @retval HAL status
mbed_official 87:085cde657901 486 */
mbed_official 87:085cde657901 487 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
mbed_official 87:085cde657901 488 {
mbed_official 87:085cde657901 489 uint32_t i = 0;
mbed_official 87:085cde657901 490 ETH_DMADescTypeDef *DMARxDesc;
mbed_official 87:085cde657901 491
mbed_official 87:085cde657901 492 /* Process Locked */
mbed_official 87:085cde657901 493 __HAL_LOCK(heth);
mbed_official 87:085cde657901 494
mbed_official 87:085cde657901 495 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 496 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 497
mbed_official 87:085cde657901 498 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
mbed_official 87:085cde657901 499 heth->RxDesc = DMARxDescTab;
mbed_official 87:085cde657901 500
mbed_official 87:085cde657901 501 /* Fill each DMARxDesc descriptor with the right values */
mbed_official 87:085cde657901 502 for(i=0; i < RxBuffCount; i++)
mbed_official 87:085cde657901 503 {
mbed_official 87:085cde657901 504 /* Get the pointer on the ith member of the Rx Desc list */
mbed_official 87:085cde657901 505 DMARxDesc = DMARxDescTab+i;
mbed_official 87:085cde657901 506
mbed_official 87:085cde657901 507 /* Set Own bit of the Rx descriptor Status */
mbed_official 87:085cde657901 508 DMARxDesc->Status = ETH_DMARXDESC_OWN;
mbed_official 87:085cde657901 509
mbed_official 87:085cde657901 510 /* Set Buffer1 size and Second Address Chained bit */
mbed_official 87:085cde657901 511 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
mbed_official 87:085cde657901 512
mbed_official 87:085cde657901 513 /* Set Buffer1 address pointer */
mbed_official 87:085cde657901 514 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
mbed_official 87:085cde657901 515
mbed_official 87:085cde657901 516 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 87:085cde657901 517 {
mbed_official 87:085cde657901 518 /* Enable Ethernet DMA Rx Descriptor interrupt */
mbed_official 87:085cde657901 519 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
mbed_official 87:085cde657901 520 }
mbed_official 87:085cde657901 521
mbed_official 87:085cde657901 522 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 87:085cde657901 523 if(i < (RxBuffCount-1))
mbed_official 87:085cde657901 524 {
mbed_official 87:085cde657901 525 /* Set next descriptor address register with next descriptor base address */
mbed_official 87:085cde657901 526 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
mbed_official 87:085cde657901 527 }
mbed_official 87:085cde657901 528 else
mbed_official 87:085cde657901 529 {
mbed_official 87:085cde657901 530 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 87:085cde657901 531 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
mbed_official 87:085cde657901 532 }
mbed_official 87:085cde657901 533 }
mbed_official 87:085cde657901 534
mbed_official 87:085cde657901 535 /* Set Receive Descriptor List Address Register */
mbed_official 87:085cde657901 536 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
mbed_official 87:085cde657901 537
mbed_official 87:085cde657901 538 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 539 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 540
mbed_official 87:085cde657901 541 /* Process Unlocked */
mbed_official 87:085cde657901 542 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 543
mbed_official 87:085cde657901 544 /* Return function status */
mbed_official 87:085cde657901 545 return HAL_OK;
mbed_official 87:085cde657901 546 }
mbed_official 87:085cde657901 547
mbed_official 87:085cde657901 548 /**
mbed_official 87:085cde657901 549 * @brief Initializes the ETH MSP.
mbed_official 87:085cde657901 550 * @param heth: ETH handle
mbed_official 87:085cde657901 551 * @retval None
mbed_official 87:085cde657901 552 */
mbed_official 87:085cde657901 553 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 554 {
mbed_official 87:085cde657901 555 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 556 the HAL_ETH_MspInit could be implemented in the user file
mbed_official 87:085cde657901 557 */
mbed_official 87:085cde657901 558 }
mbed_official 87:085cde657901 559
mbed_official 87:085cde657901 560 /**
mbed_official 87:085cde657901 561 * @brief DeInitializes ETH MSP.
mbed_official 87:085cde657901 562 * @param heth: ETH handle
mbed_official 87:085cde657901 563 * @retval None
mbed_official 87:085cde657901 564 */
mbed_official 87:085cde657901 565 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 566 {
mbed_official 87:085cde657901 567 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 568 the HAL_ETH_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 569 */
mbed_official 87:085cde657901 570 }
mbed_official 87:085cde657901 571
mbed_official 87:085cde657901 572 /**
mbed_official 87:085cde657901 573 * @}
mbed_official 87:085cde657901 574 */
mbed_official 87:085cde657901 575
mbed_official 87:085cde657901 576 /** @defgroup ETH_Group2 IO operation functions
mbed_official 87:085cde657901 577 * @brief Data transfers functions
mbed_official 87:085cde657901 578 *
mbed_official 87:085cde657901 579 @verbatim
mbed_official 87:085cde657901 580 ==============================================================================
mbed_official 87:085cde657901 581 ##### IO operation functions #####
mbed_official 87:085cde657901 582 ==============================================================================
mbed_official 87:085cde657901 583 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 584 (+) Transmit a frame
mbed_official 87:085cde657901 585 HAL_ETH_TransmitFrame();
mbed_official 87:085cde657901 586 (+) Receive a frame
mbed_official 87:085cde657901 587 HAL_ETH_GetReceivedFrame();
mbed_official 87:085cde657901 588 HAL_ETH_GetReceivedFrame_IT();
mbed_official 87:085cde657901 589 (+) Read from an External PHY register
mbed_official 87:085cde657901 590 HAL_ETH_ReadPHYRegister();
mbed_official 87:085cde657901 591 (+) Writo to an External PHY register
mbed_official 87:085cde657901 592 HAL_ETH_WritePHYRegister();
mbed_official 87:085cde657901 593
mbed_official 87:085cde657901 594 @endverbatim
mbed_official 87:085cde657901 595
mbed_official 87:085cde657901 596 * @{
mbed_official 87:085cde657901 597 */
mbed_official 87:085cde657901 598
mbed_official 87:085cde657901 599 /**
mbed_official 87:085cde657901 600 * @brief Sends an Ethernet frame.
mbed_official 87:085cde657901 601 * @param heth: ETH handle
mbed_official 87:085cde657901 602 * @param FrameLength: Amount of data to be sent
mbed_official 87:085cde657901 603 * @retval HAL status
mbed_official 87:085cde657901 604 */
mbed_official 87:085cde657901 605 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
mbed_official 87:085cde657901 606 {
mbed_official 87:085cde657901 607 uint32_t bufcount = 0, size = 0, i = 0;
mbed_official 87:085cde657901 608
mbed_official 87:085cde657901 609 /* Process Locked */
mbed_official 87:085cde657901 610 __HAL_LOCK(heth);
mbed_official 87:085cde657901 611
mbed_official 87:085cde657901 612 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 613 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 614
mbed_official 87:085cde657901 615 if (FrameLength == 0)
mbed_official 87:085cde657901 616 {
mbed_official 87:085cde657901 617 /* Set ETH HAL state to READY */
mbed_official 87:085cde657901 618 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 619
mbed_official 87:085cde657901 620 /* Process Unlocked */
mbed_official 87:085cde657901 621 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 622
mbed_official 87:085cde657901 623 return HAL_ERROR;
mbed_official 87:085cde657901 624 }
mbed_official 87:085cde657901 625
mbed_official 87:085cde657901 626 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
mbed_official 87:085cde657901 627 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
mbed_official 87:085cde657901 628 {
mbed_official 87:085cde657901 629 /* OWN bit set */
mbed_official 87:085cde657901 630 heth->State = HAL_ETH_STATE_BUSY_TX;
mbed_official 87:085cde657901 631
mbed_official 87:085cde657901 632 /* Process Unlocked */
mbed_official 87:085cde657901 633 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 634
mbed_official 87:085cde657901 635 return HAL_ERROR;
mbed_official 87:085cde657901 636 }
mbed_official 87:085cde657901 637
mbed_official 87:085cde657901 638 /* Get the number of needed Tx buffers for the current frame */
mbed_official 87:085cde657901 639 if (FrameLength > ETH_TX_BUF_SIZE)
mbed_official 87:085cde657901 640 {
mbed_official 87:085cde657901 641 bufcount = FrameLength/ETH_TX_BUF_SIZE;
mbed_official 87:085cde657901 642 if (FrameLength % ETH_TX_BUF_SIZE)
mbed_official 87:085cde657901 643 {
mbed_official 87:085cde657901 644 bufcount++;
mbed_official 87:085cde657901 645 }
mbed_official 87:085cde657901 646 }
mbed_official 87:085cde657901 647 else
mbed_official 87:085cde657901 648 {
mbed_official 87:085cde657901 649 bufcount = 1;
mbed_official 87:085cde657901 650 }
mbed_official 87:085cde657901 651 if (bufcount == 1)
mbed_official 87:085cde657901 652 {
mbed_official 87:085cde657901 653 /* Set LAST and FIRST segment */
mbed_official 87:085cde657901 654 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
mbed_official 87:085cde657901 655 /* Set frame size */
mbed_official 87:085cde657901 656 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
mbed_official 87:085cde657901 657 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 87:085cde657901 658 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 87:085cde657901 659 /* Point to next descriptor */
mbed_official 87:085cde657901 660 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 661 }
mbed_official 87:085cde657901 662 else
mbed_official 87:085cde657901 663 {
mbed_official 87:085cde657901 664 for (i=0; i< bufcount; i++)
mbed_official 87:085cde657901 665 {
mbed_official 87:085cde657901 666 /* Clear FIRST and LAST segment bits */
mbed_official 87:085cde657901 667 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
mbed_official 87:085cde657901 668
mbed_official 87:085cde657901 669 if (i == 0)
mbed_official 87:085cde657901 670 {
mbed_official 87:085cde657901 671 /* Setting the first segment bit */
mbed_official 87:085cde657901 672 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
mbed_official 87:085cde657901 673 }
mbed_official 87:085cde657901 674
mbed_official 87:085cde657901 675 /* Program size */
mbed_official 87:085cde657901 676 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
mbed_official 87:085cde657901 677
mbed_official 87:085cde657901 678 if (i == (bufcount-1))
mbed_official 87:085cde657901 679 {
mbed_official 87:085cde657901 680 /* Setting the last segment bit */
mbed_official 87:085cde657901 681 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
mbed_official 87:085cde657901 682 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
mbed_official 87:085cde657901 683 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
mbed_official 87:085cde657901 684 }
mbed_official 87:085cde657901 685
mbed_official 87:085cde657901 686 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 87:085cde657901 687 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 87:085cde657901 688 /* point to next descriptor */
mbed_official 87:085cde657901 689 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 690 }
mbed_official 87:085cde657901 691 }
mbed_official 87:085cde657901 692
mbed_official 87:085cde657901 693 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
mbed_official 87:085cde657901 694 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
mbed_official 87:085cde657901 695 {
mbed_official 87:085cde657901 696 /* Clear TBUS ETHERNET DMA flag */
mbed_official 87:085cde657901 697 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
mbed_official 87:085cde657901 698 /* Resume DMA transmission*/
mbed_official 87:085cde657901 699 (heth->Instance)->DMATPDR = 0;
mbed_official 87:085cde657901 700 }
mbed_official 87:085cde657901 701
mbed_official 87:085cde657901 702 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 703 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 704
mbed_official 87:085cde657901 705 /* Process Unlocked */
mbed_official 87:085cde657901 706 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 707
mbed_official 87:085cde657901 708 /* Return function status */
mbed_official 87:085cde657901 709 return HAL_OK;
mbed_official 87:085cde657901 710 }
mbed_official 87:085cde657901 711
mbed_official 87:085cde657901 712 /**
mbed_official 87:085cde657901 713 * @brief Checks for received frames.
mbed_official 87:085cde657901 714 * @param heth: ETH handle
mbed_official 87:085cde657901 715 * @retval HAL status
mbed_official 87:085cde657901 716 */
mbed_official 87:085cde657901 717 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 718 {
mbed_official 87:085cde657901 719 uint32_t framelength = 0;
mbed_official 87:085cde657901 720
mbed_official 87:085cde657901 721 /* Process Locked */
mbed_official 87:085cde657901 722 __HAL_LOCK(heth);
mbed_official 87:085cde657901 723
mbed_official 87:085cde657901 724 /* Check the ETH state to BUSY */
mbed_official 87:085cde657901 725 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 726
mbed_official 87:085cde657901 727 /* Check if segment is not owned by DMA */
mbed_official 87:085cde657901 728 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
mbed_official 87:085cde657901 729 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
mbed_official 87:085cde657901 730 {
mbed_official 87:085cde657901 731 /* Check if last segment */
mbed_official 87:085cde657901 732 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
mbed_official 87:085cde657901 733 {
mbed_official 87:085cde657901 734 /* increment segment count */
mbed_official 87:085cde657901 735 (heth->RxFrameInfos).SegCount++;
mbed_official 87:085cde657901 736
mbed_official 87:085cde657901 737 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 87:085cde657901 738 if ((heth->RxFrameInfos).SegCount == 1)
mbed_official 87:085cde657901 739 {
mbed_official 87:085cde657901 740 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
mbed_official 87:085cde657901 741 }
mbed_official 87:085cde657901 742
mbed_official 87:085cde657901 743 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 744
mbed_official 87:085cde657901 745 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 87:085cde657901 746 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 87:085cde657901 747 heth->RxFrameInfos.length = framelength;
mbed_official 87:085cde657901 748
mbed_official 87:085cde657901 749 /* Get the address of the buffer start address */
mbed_official 87:085cde657901 750 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 87:085cde657901 751 /* point to next descriptor */
mbed_official 87:085cde657901 752 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
mbed_official 87:085cde657901 753
mbed_official 87:085cde657901 754 /* Set HAL State to Ready */
mbed_official 87:085cde657901 755 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 756
mbed_official 87:085cde657901 757 /* Process Unlocked */
mbed_official 87:085cde657901 758 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 759
mbed_official 87:085cde657901 760 /* Return function status */
mbed_official 87:085cde657901 761 return HAL_OK;
mbed_official 87:085cde657901 762 }
mbed_official 87:085cde657901 763 /* Check if first segment */
mbed_official 87:085cde657901 764 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
mbed_official 87:085cde657901 765 {
mbed_official 87:085cde657901 766 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 767 (heth->RxFrameInfos).LSRxDesc = NULL;
mbed_official 87:085cde657901 768 (heth->RxFrameInfos).SegCount = 1;
mbed_official 87:085cde657901 769 /* Point to next descriptor */
mbed_official 87:085cde657901 770 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 771 }
mbed_official 87:085cde657901 772 /* Check if intermediate segment */
mbed_official 87:085cde657901 773 else
mbed_official 87:085cde657901 774 {
mbed_official 87:085cde657901 775 (heth->RxFrameInfos).SegCount++;
mbed_official 87:085cde657901 776 /* Point to next descriptor */
mbed_official 87:085cde657901 777 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 778 }
mbed_official 87:085cde657901 779 }
mbed_official 87:085cde657901 780
mbed_official 87:085cde657901 781 /* Set ETH HAL State to Ready */
mbed_official 87:085cde657901 782 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 783
mbed_official 87:085cde657901 784 /* Process Unlocked */
mbed_official 87:085cde657901 785 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 786
mbed_official 87:085cde657901 787 return HAL_ERROR;
mbed_official 87:085cde657901 788 }
mbed_official 87:085cde657901 789
mbed_official 87:085cde657901 790 /**
mbed_official 87:085cde657901 791 * @brief Gets the Received frame in interrupt mode.
mbed_official 87:085cde657901 792 * @param heth: ETH handle
mbed_official 87:085cde657901 793 * @retval HAL status
mbed_official 87:085cde657901 794 */
mbed_official 87:085cde657901 795 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 796 {
mbed_official 87:085cde657901 797 uint32_t descriptorscancounter = 0;
mbed_official 87:085cde657901 798
mbed_official 87:085cde657901 799 /* Process Locked */
mbed_official 87:085cde657901 800 __HAL_LOCK(heth);
mbed_official 87:085cde657901 801
mbed_official 87:085cde657901 802 /* Set ETH HAL State to BUSY */
mbed_official 87:085cde657901 803 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 804
mbed_official 87:085cde657901 805 /* Scan descriptors owned by CPU */
mbed_official 87:085cde657901 806 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
mbed_official 87:085cde657901 807 {
mbed_official 87:085cde657901 808 /* Just for security */
mbed_official 87:085cde657901 809 descriptorscancounter++;
mbed_official 87:085cde657901 810
mbed_official 87:085cde657901 811 /* Check if first segment in frame */
mbed_official 87:085cde657901 812 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
mbed_official 87:085cde657901 813 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
mbed_official 87:085cde657901 814 {
mbed_official 87:085cde657901 815 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 816 heth->RxFrameInfos.SegCount = 1;
mbed_official 87:085cde657901 817 /* Point to next descriptor */
mbed_official 87:085cde657901 818 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 819 }
mbed_official 87:085cde657901 820 /* Check if intermediate segment */
mbed_official 87:085cde657901 821 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
mbed_official 87:085cde657901 822 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
mbed_official 87:085cde657901 823 {
mbed_official 87:085cde657901 824 /* Increment segment count */
mbed_official 87:085cde657901 825 (heth->RxFrameInfos.SegCount)++;
mbed_official 87:085cde657901 826 /* Point to next descriptor */
mbed_official 87:085cde657901 827 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 828 }
mbed_official 87:085cde657901 829 /* Should be last segment */
mbed_official 87:085cde657901 830 else
mbed_official 87:085cde657901 831 {
mbed_official 87:085cde657901 832 /* Last segment */
mbed_official 87:085cde657901 833 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 834
mbed_official 87:085cde657901 835 /* Increment segment count */
mbed_official 87:085cde657901 836 (heth->RxFrameInfos.SegCount)++;
mbed_official 87:085cde657901 837
mbed_official 87:085cde657901 838 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 87:085cde657901 839 if ((heth->RxFrameInfos.SegCount) == 1)
mbed_official 87:085cde657901 840 {
mbed_official 87:085cde657901 841 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 87:085cde657901 842 }
mbed_official 87:085cde657901 843
mbed_official 87:085cde657901 844 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 87:085cde657901 845 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 87:085cde657901 846
mbed_official 87:085cde657901 847 /* Get the address of the buffer start address */
mbed_official 87:085cde657901 848 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 87:085cde657901 849
mbed_official 87:085cde657901 850 /* Point to next descriptor */
mbed_official 87:085cde657901 851 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 87:085cde657901 852
mbed_official 87:085cde657901 853 /* Set HAL State to Ready */
mbed_official 87:085cde657901 854 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 855
mbed_official 87:085cde657901 856 /* Process Unlocked */
mbed_official 87:085cde657901 857 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 858
mbed_official 87:085cde657901 859 /* Return function status */
mbed_official 87:085cde657901 860 return HAL_OK;
mbed_official 87:085cde657901 861 }
mbed_official 87:085cde657901 862 }
mbed_official 87:085cde657901 863
mbed_official 87:085cde657901 864 /* Set HAL State to Ready */
mbed_official 87:085cde657901 865 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 866
mbed_official 87:085cde657901 867 /* Process Unlocked */
mbed_official 87:085cde657901 868 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 869
mbed_official 87:085cde657901 870 /* Return function status */
mbed_official 87:085cde657901 871 return HAL_OK;
mbed_official 87:085cde657901 872 }
mbed_official 87:085cde657901 873
mbed_official 87:085cde657901 874 /**
mbed_official 87:085cde657901 875 * @brief This function handles ETH interrupt request.
mbed_official 87:085cde657901 876 * @param heth: ETH handle
mbed_official 87:085cde657901 877 * @retval HAL status
mbed_official 87:085cde657901 878 */
mbed_official 87:085cde657901 879 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 880 {
mbed_official 87:085cde657901 881 /* Frame received */
mbed_official 87:085cde657901 882 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
mbed_official 87:085cde657901 883 {
mbed_official 87:085cde657901 884 /* Receive complete callback */
mbed_official 87:085cde657901 885 HAL_ETH_RxCpltCallback(heth);
mbed_official 87:085cde657901 886
mbed_official 87:085cde657901 887 /* Clear the Eth DMA Rx IT pending bits */
mbed_official 106:ced8cbb51063 888 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
mbed_official 87:085cde657901 889
mbed_official 87:085cde657901 890 /* Set HAL State to Ready */
mbed_official 87:085cde657901 891 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 892
mbed_official 87:085cde657901 893 /* Process Unlocked */
mbed_official 87:085cde657901 894 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 895
mbed_official 87:085cde657901 896 }
mbed_official 87:085cde657901 897 /* Frame transmitted */
mbed_official 87:085cde657901 898 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
mbed_official 87:085cde657901 899 {
mbed_official 87:085cde657901 900 /* Transfer complete callback */
mbed_official 87:085cde657901 901 HAL_ETH_TxCpltCallback(heth);
mbed_official 87:085cde657901 902
mbed_official 87:085cde657901 903 /* Clear the Eth DMA Tx IT pending bits */
mbed_official 106:ced8cbb51063 904 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
mbed_official 87:085cde657901 905
mbed_official 87:085cde657901 906 /* Set HAL State to Ready */
mbed_official 87:085cde657901 907 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 908
mbed_official 87:085cde657901 909 /* Process Unlocked */
mbed_official 87:085cde657901 910 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 911 }
mbed_official 87:085cde657901 912
mbed_official 87:085cde657901 913 /* Clear the interrupt flags */
mbed_official 106:ced8cbb51063 914 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
mbed_official 87:085cde657901 915
mbed_official 87:085cde657901 916 /* ETH DMA Error */
mbed_official 87:085cde657901 917 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
mbed_official 87:085cde657901 918 {
mbed_official 87:085cde657901 919 /* Ethernet Error callback */
mbed_official 87:085cde657901 920 HAL_ETH_ErrorCallback(heth);
mbed_official 87:085cde657901 921
mbed_official 87:085cde657901 922 /* Clear the interrupt flags */
mbed_official 106:ced8cbb51063 923 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
mbed_official 87:085cde657901 924
mbed_official 87:085cde657901 925 /* Set HAL State to Ready */
mbed_official 87:085cde657901 926 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 927
mbed_official 87:085cde657901 928 /* Process Unlocked */
mbed_official 87:085cde657901 929 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 930 }
mbed_official 87:085cde657901 931 }
mbed_official 87:085cde657901 932
mbed_official 87:085cde657901 933 /**
mbed_official 87:085cde657901 934 * @brief Tx Transfer completed callbacks.
mbed_official 87:085cde657901 935 * @param heth: ETH handle
mbed_official 87:085cde657901 936 * @retval None
mbed_official 87:085cde657901 937 */
mbed_official 87:085cde657901 938 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 939 {
mbed_official 87:085cde657901 940 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 941 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 87:085cde657901 942 */
mbed_official 87:085cde657901 943 }
mbed_official 87:085cde657901 944
mbed_official 87:085cde657901 945 /**
mbed_official 87:085cde657901 946 * @brief Rx Transfer completed callbacks.
mbed_official 87:085cde657901 947 * @param heth: ETH handle
mbed_official 87:085cde657901 948 * @retval None
mbed_official 87:085cde657901 949 */
mbed_official 87:085cde657901 950 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 951 {
mbed_official 87:085cde657901 952 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 953 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 87:085cde657901 954 */
mbed_official 87:085cde657901 955 }
mbed_official 87:085cde657901 956
mbed_official 87:085cde657901 957 /**
mbed_official 87:085cde657901 958 * @brief Ethernet transfer error callbacks
mbed_official 87:085cde657901 959 * @param heth: ETH handle
mbed_official 87:085cde657901 960 * @retval None
mbed_official 87:085cde657901 961 */
mbed_official 87:085cde657901 962 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 963 {
mbed_official 87:085cde657901 964 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 965 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 87:085cde657901 966 */
mbed_official 87:085cde657901 967 }
mbed_official 87:085cde657901 968
mbed_official 87:085cde657901 969 /**
mbed_official 87:085cde657901 970 * @brief Reads a PHY register
mbed_official 87:085cde657901 971 * @param heth: ETH handle
mbed_official 87:085cde657901 972 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 87:085cde657901 973 * This parameter can be one of the following values:
mbed_official 87:085cde657901 974 * @arg PHY_BCR: Transceiver Basic Control Register
mbed_official 87:085cde657901 975 * @arg PHY_BSR: Transceiver Basic Status Register
mbed_official 87:085cde657901 976 * @arg More PHY register could be read depending on the used PHY
mbed_official 87:085cde657901 977 * @param RegValue: PHY register value
mbed_official 87:085cde657901 978 * @retval HAL_TIMEOUT: in case of timeout
mbed_official 87:085cde657901 979 * MACMIIDR register value: Data read from the selected PHY register (correct read )
mbed_official 87:085cde657901 980 */
mbed_official 87:085cde657901 981 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
mbed_official 87:085cde657901 982 {
mbed_official 87:085cde657901 983 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 984 uint32_t timeout = 0;
mbed_official 87:085cde657901 985
mbed_official 87:085cde657901 986 /* Check parameters */
mbed_official 87:085cde657901 987 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 87:085cde657901 988
mbed_official 87:085cde657901 989 /* Check the ETH peripheral state */
mbed_official 87:085cde657901 990 if(heth->State == HAL_ETH_STATE_BUSY_RD)
mbed_official 87:085cde657901 991 {
mbed_official 87:085cde657901 992 return HAL_BUSY;
mbed_official 87:085cde657901 993 }
mbed_official 87:085cde657901 994 /* Set ETH HAL State to BUSY_RD */
mbed_official 87:085cde657901 995 heth->State = HAL_ETH_STATE_BUSY_RD;
mbed_official 87:085cde657901 996
mbed_official 87:085cde657901 997 /* Get the ETHERNET MACMIIAR value */
mbed_official 87:085cde657901 998 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 999
mbed_official 87:085cde657901 1000 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 87:085cde657901 1001 tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official 87:085cde657901 1002
mbed_official 87:085cde657901 1003 /* Prepare the MII address register value */
mbed_official 87:085cde657901 1004 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 87:085cde657901 1005 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 87:085cde657901 1006 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
mbed_official 87:085cde657901 1007 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 87:085cde657901 1008
mbed_official 87:085cde657901 1009 /* Write the result value into the MII Address register */
mbed_official 87:085cde657901 1010 heth->Instance->MACMIIAR = tmpreg;
mbed_official 87:085cde657901 1011
mbed_official 87:085cde657901 1012 /* Check for the Busy flag */
mbed_official 87:085cde657901 1013 do
mbed_official 87:085cde657901 1014 {
mbed_official 87:085cde657901 1015 timeout++;
mbed_official 87:085cde657901 1016 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1017 } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_READ_TO));
mbed_official 87:085cde657901 1018
mbed_official 87:085cde657901 1019 /* Return ERROR in case of timeout */
mbed_official 87:085cde657901 1020 if(timeout == PHY_READ_TO)
mbed_official 87:085cde657901 1021 {
mbed_official 87:085cde657901 1022 /* Set ETH HAL State to READY */
mbed_official 87:085cde657901 1023 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1024 /* Return HAL_TIMEOUT */
mbed_official 87:085cde657901 1025 return HAL_TIMEOUT;
mbed_official 87:085cde657901 1026 }
mbed_official 87:085cde657901 1027
mbed_official 87:085cde657901 1028 /* Get MACMIIDR value */
mbed_official 87:085cde657901 1029 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
mbed_official 87:085cde657901 1030
mbed_official 87:085cde657901 1031 /* Set ETH HAL State to READY */
mbed_official 87:085cde657901 1032 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1033
mbed_official 87:085cde657901 1034 /* Return function status */
mbed_official 87:085cde657901 1035 return HAL_OK;
mbed_official 87:085cde657901 1036 }
mbed_official 87:085cde657901 1037
mbed_official 87:085cde657901 1038 /**
mbed_official 87:085cde657901 1039 * @brief Writes to a PHY register.
mbed_official 87:085cde657901 1040 * @param heth: ETH handle
mbed_official 87:085cde657901 1041 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 87:085cde657901 1042 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1043 * @arg PHY_BCR: Transceiver Control Register
mbed_official 87:085cde657901 1044 * @arg More PHY register could be written depending on the used PHY
mbed_official 87:085cde657901 1045 * @param RegValue: the value to write
mbed_official 87:085cde657901 1046 * @retval HAL status
mbed_official 87:085cde657901 1047 */
mbed_official 87:085cde657901 1048 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
mbed_official 87:085cde657901 1049 {
mbed_official 87:085cde657901 1050 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1051 uint32_t timeout = 0;
mbed_official 87:085cde657901 1052
mbed_official 87:085cde657901 1053 /* Check parameters */
mbed_official 87:085cde657901 1054 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 87:085cde657901 1055
mbed_official 87:085cde657901 1056 /* Check the ETH peripheral state */
mbed_official 87:085cde657901 1057 if(heth->State == HAL_ETH_STATE_BUSY_WR)
mbed_official 87:085cde657901 1058 {
mbed_official 87:085cde657901 1059 return HAL_BUSY;
mbed_official 87:085cde657901 1060 }
mbed_official 87:085cde657901 1061 /* Set ETH HAL State to BUSY_WR */
mbed_official 87:085cde657901 1062 heth->State = HAL_ETH_STATE_BUSY_WR;
mbed_official 87:085cde657901 1063
mbed_official 87:085cde657901 1064 /* Get the ETHERNET MACMIIAR value */
mbed_official 87:085cde657901 1065 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1066
mbed_official 87:085cde657901 1067 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 87:085cde657901 1068 tmpreg &= ~MACMIIAR_CR_MASK;
mbed_official 87:085cde657901 1069
mbed_official 87:085cde657901 1070 /* Prepare the MII register address value */
mbed_official 87:085cde657901 1071 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 87:085cde657901 1072 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 87:085cde657901 1073 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
mbed_official 87:085cde657901 1074 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 87:085cde657901 1075
mbed_official 87:085cde657901 1076 /* Give the value to the MII data register */
mbed_official 87:085cde657901 1077 heth->Instance->MACMIIDR = (uint16_t)RegValue;
mbed_official 87:085cde657901 1078
mbed_official 87:085cde657901 1079 /* Write the result value into the MII Address register */
mbed_official 87:085cde657901 1080 heth->Instance->MACMIIAR = tmpreg;
mbed_official 87:085cde657901 1081
mbed_official 87:085cde657901 1082 /* Check for the Busy flag */
mbed_official 87:085cde657901 1083 do
mbed_official 87:085cde657901 1084 {
mbed_official 87:085cde657901 1085 timeout++;
mbed_official 87:085cde657901 1086 tmpreg = heth->Instance->MACMIIAR;
mbed_official 87:085cde657901 1087 } while (((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) && (timeout < PHY_WRITE_TO));
mbed_official 87:085cde657901 1088
mbed_official 87:085cde657901 1089 /* Return TIMETOUT in case of timeout */
mbed_official 87:085cde657901 1090 if(timeout == PHY_WRITE_TO)
mbed_official 87:085cde657901 1091 {
mbed_official 87:085cde657901 1092 /* Set ETH HAL State to READY */
mbed_official 87:085cde657901 1093 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1094
mbed_official 87:085cde657901 1095 return HAL_TIMEOUT;
mbed_official 87:085cde657901 1096 }
mbed_official 87:085cde657901 1097
mbed_official 87:085cde657901 1098 /* Set ETH HAL State to READY */
mbed_official 87:085cde657901 1099 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1100
mbed_official 87:085cde657901 1101 /* Return function status */
mbed_official 87:085cde657901 1102 return HAL_OK;
mbed_official 87:085cde657901 1103 }
mbed_official 87:085cde657901 1104
mbed_official 87:085cde657901 1105 /**
mbed_official 87:085cde657901 1106 * @}
mbed_official 87:085cde657901 1107 */
mbed_official 87:085cde657901 1108
mbed_official 87:085cde657901 1109 /** @defgroup ETH_Group3 Peripheral Control functions
mbed_official 87:085cde657901 1110 * @brief Peripheral Control functions
mbed_official 87:085cde657901 1111 *
mbed_official 87:085cde657901 1112 @verbatim
mbed_official 87:085cde657901 1113 ===============================================================================
mbed_official 87:085cde657901 1114 ##### Peripheral Control functions #####
mbed_official 87:085cde657901 1115 ===============================================================================
mbed_official 87:085cde657901 1116 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 1117 (+) Enable MAC and DMA transmission and reception.
mbed_official 87:085cde657901 1118 HAL_ETH_Start();
mbed_official 87:085cde657901 1119 (+) Disable MAC and DMA transmission and reception.
mbed_official 87:085cde657901 1120 HAL_ETH_Stop();
mbed_official 87:085cde657901 1121 (+) Set the MAC configuration in runtime mode
mbed_official 87:085cde657901 1122 HAL_ETH_ConfigMAC();
mbed_official 87:085cde657901 1123 (+) Set the DMA configuration in runtime mode
mbed_official 87:085cde657901 1124 HAL_ETH_ConfigDMA();
mbed_official 87:085cde657901 1125
mbed_official 87:085cde657901 1126 @endverbatim
mbed_official 87:085cde657901 1127 * @{
mbed_official 87:085cde657901 1128 */
mbed_official 87:085cde657901 1129
mbed_official 87:085cde657901 1130 /**
mbed_official 87:085cde657901 1131 * @brief Enables Ethernet MAC and DMA reception/transmission
mbed_official 87:085cde657901 1132 * @param heth: ETH handle
mbed_official 87:085cde657901 1133 * @retval HAL status
mbed_official 87:085cde657901 1134 */
mbed_official 87:085cde657901 1135 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1136 {
mbed_official 87:085cde657901 1137 /* Process Locked */
mbed_official 87:085cde657901 1138 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1139
mbed_official 87:085cde657901 1140 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1141 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1142
mbed_official 87:085cde657901 1143 /* Enable transmit state machine of the MAC for transmission on the MII */
mbed_official 87:085cde657901 1144 ETH_MACTransmissionEnable(heth);
mbed_official 87:085cde657901 1145
mbed_official 87:085cde657901 1146 /* Enable receive state machine of the MAC for reception from the MII */
mbed_official 87:085cde657901 1147 ETH_MACReceptionEnable(heth);
mbed_official 87:085cde657901 1148
mbed_official 87:085cde657901 1149 /* Flush Transmit FIFO */
mbed_official 87:085cde657901 1150 ETH_FlushTransmitFIFO(heth);
mbed_official 87:085cde657901 1151
mbed_official 87:085cde657901 1152 /* Start DMA transmission */
mbed_official 87:085cde657901 1153 ETH_DMATransmissionEnable(heth);
mbed_official 87:085cde657901 1154
mbed_official 87:085cde657901 1155 /* Start DMA reception */
mbed_official 87:085cde657901 1156 ETH_DMAReceptionEnable(heth);
mbed_official 87:085cde657901 1157
mbed_official 87:085cde657901 1158 /* Set the ETH state to READY*/
mbed_official 87:085cde657901 1159 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1160
mbed_official 87:085cde657901 1161 /* Process Unlocked */
mbed_official 87:085cde657901 1162 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1163
mbed_official 87:085cde657901 1164 /* Return function status */
mbed_official 87:085cde657901 1165 return HAL_OK;
mbed_official 87:085cde657901 1166 }
mbed_official 87:085cde657901 1167
mbed_official 87:085cde657901 1168 /**
mbed_official 87:085cde657901 1169 * @brief Stop Ethernet MAC and DMA reception/transmission
mbed_official 87:085cde657901 1170 * @param heth: ETH handle
mbed_official 87:085cde657901 1171 * @retval HAL status
mbed_official 87:085cde657901 1172 */
mbed_official 87:085cde657901 1173 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1174 {
mbed_official 87:085cde657901 1175 /* Process Locked */
mbed_official 87:085cde657901 1176 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1177
mbed_official 87:085cde657901 1178 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1179 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1180
mbed_official 87:085cde657901 1181 /* Stop DMA transmission */
mbed_official 87:085cde657901 1182 ETH_DMATransmissionDisable(heth);
mbed_official 87:085cde657901 1183
mbed_official 87:085cde657901 1184 /* Stop DMA reception */
mbed_official 87:085cde657901 1185 ETH_DMAReceptionDisable(heth);
mbed_official 87:085cde657901 1186
mbed_official 87:085cde657901 1187 /* Disable receive state machine of the MAC for reception from the MII */
mbed_official 87:085cde657901 1188 ETH_MACReceptionDisable(heth);
mbed_official 87:085cde657901 1189
mbed_official 87:085cde657901 1190 /* Flush Transmit FIFO */
mbed_official 87:085cde657901 1191 ETH_FlushTransmitFIFO(heth);
mbed_official 87:085cde657901 1192
mbed_official 87:085cde657901 1193 /* Disable transmit state machine of the MAC for transmission on the MII */
mbed_official 87:085cde657901 1194 ETH_MACTransmissionDisable(heth);
mbed_official 87:085cde657901 1195
mbed_official 87:085cde657901 1196 /* Set the ETH state*/
mbed_official 87:085cde657901 1197 heth->State = HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1198
mbed_official 87:085cde657901 1199 /* Process Unlocked */
mbed_official 87:085cde657901 1200 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1201
mbed_official 87:085cde657901 1202 /* Return function status */
mbed_official 87:085cde657901 1203 return HAL_OK;
mbed_official 87:085cde657901 1204 }
mbed_official 87:085cde657901 1205
mbed_official 87:085cde657901 1206 /**
mbed_official 87:085cde657901 1207 * @brief Set ETH MAC Configuration.
mbed_official 87:085cde657901 1208 * @param heth: ETH handle
mbed_official 87:085cde657901 1209 * @param macconf: MAC Configuration structure
mbed_official 87:085cde657901 1210 * @retval HAL status
mbed_official 87:085cde657901 1211 */
mbed_official 87:085cde657901 1212 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
mbed_official 87:085cde657901 1213 {
mbed_official 87:085cde657901 1214 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1215
mbed_official 87:085cde657901 1216 /* Process Locked */
mbed_official 87:085cde657901 1217 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1218
mbed_official 87:085cde657901 1219 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1220 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1221
mbed_official 87:085cde657901 1222 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 87:085cde657901 1223 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 87:085cde657901 1224
mbed_official 87:085cde657901 1225 if (macconf != NULL)
mbed_official 87:085cde657901 1226 {
mbed_official 87:085cde657901 1227 /* Check the parameters */
mbed_official 87:085cde657901 1228 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
mbed_official 87:085cde657901 1229 assert_param(IS_ETH_JABBER(macconf->Jabber));
mbed_official 87:085cde657901 1230 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
mbed_official 87:085cde657901 1231 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
mbed_official 87:085cde657901 1232 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
mbed_official 87:085cde657901 1233 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
mbed_official 87:085cde657901 1234 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
mbed_official 87:085cde657901 1235 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
mbed_official 87:085cde657901 1236 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
mbed_official 87:085cde657901 1237 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
mbed_official 87:085cde657901 1238 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
mbed_official 87:085cde657901 1239 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
mbed_official 87:085cde657901 1240 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
mbed_official 87:085cde657901 1241 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
mbed_official 87:085cde657901 1242 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
mbed_official 87:085cde657901 1243 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
mbed_official 87:085cde657901 1244 assert_param(IS_ETH_PROMISCIOUS_MODE(macconf->PromiscuousMode));
mbed_official 87:085cde657901 1245 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
mbed_official 87:085cde657901 1246 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
mbed_official 87:085cde657901 1247 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
mbed_official 87:085cde657901 1248 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
mbed_official 87:085cde657901 1249 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
mbed_official 87:085cde657901 1250 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
mbed_official 87:085cde657901 1251 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
mbed_official 87:085cde657901 1252 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
mbed_official 87:085cde657901 1253 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
mbed_official 87:085cde657901 1254 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
mbed_official 87:085cde657901 1255
mbed_official 87:085cde657901 1256 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 87:085cde657901 1257 /* Get the ETHERNET MACCR value */
mbed_official 87:085cde657901 1258 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1259 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 87:085cde657901 1260 tmpreg &= MACCR_CLEAR_MASK;
mbed_official 87:085cde657901 1261
mbed_official 87:085cde657901 1262 tmpreg |= (uint32_t)(macconf->Watchdog |
mbed_official 87:085cde657901 1263 macconf->Jabber |
mbed_official 87:085cde657901 1264 macconf->InterFrameGap |
mbed_official 87:085cde657901 1265 macconf->CarrierSense |
mbed_official 87:085cde657901 1266 (heth->Init).Speed |
mbed_official 87:085cde657901 1267 macconf->ReceiveOwn |
mbed_official 87:085cde657901 1268 macconf->LoopbackMode |
mbed_official 87:085cde657901 1269 (heth->Init).DuplexMode |
mbed_official 87:085cde657901 1270 macconf->ChecksumOffload |
mbed_official 87:085cde657901 1271 macconf->RetryTransmission |
mbed_official 87:085cde657901 1272 macconf->AutomaticPadCRCStrip |
mbed_official 87:085cde657901 1273 macconf->BackOffLimit |
mbed_official 87:085cde657901 1274 macconf->DeferralCheck);
mbed_official 87:085cde657901 1275
mbed_official 87:085cde657901 1276 /* Write to ETHERNET MACCR */
mbed_official 87:085cde657901 1277 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1278
mbed_official 87:085cde657901 1279 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1280 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1281 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1282 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1283 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1284
mbed_official 87:085cde657901 1285 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 87:085cde657901 1286 /* Write to ETHERNET MACFFR */
mbed_official 87:085cde657901 1287 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
mbed_official 87:085cde657901 1288 macconf->SourceAddrFilter |
mbed_official 87:085cde657901 1289 macconf->PassControlFrames |
mbed_official 87:085cde657901 1290 macconf->BroadcastFramesReception |
mbed_official 87:085cde657901 1291 macconf->DestinationAddrFilter |
mbed_official 87:085cde657901 1292 macconf->PromiscuousMode |
mbed_official 87:085cde657901 1293 macconf->MulticastFramesFilter |
mbed_official 87:085cde657901 1294 macconf->UnicastFramesFilter);
mbed_official 87:085cde657901 1295
mbed_official 87:085cde657901 1296 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1297 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1298 tmpreg = (heth->Instance)->MACFFR;
mbed_official 87:085cde657901 1299 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1300 (heth->Instance)->MACFFR = tmpreg;
mbed_official 87:085cde657901 1301
mbed_official 87:085cde657901 1302 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
mbed_official 87:085cde657901 1303 /* Write to ETHERNET MACHTHR */
mbed_official 87:085cde657901 1304 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
mbed_official 87:085cde657901 1305
mbed_official 87:085cde657901 1306 /* Write to ETHERNET MACHTLR */
mbed_official 87:085cde657901 1307 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
mbed_official 87:085cde657901 1308 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
mbed_official 87:085cde657901 1309
mbed_official 87:085cde657901 1310 /* Get the ETHERNET MACFCR value */
mbed_official 87:085cde657901 1311 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1312 /* Clear xx bits */
mbed_official 87:085cde657901 1313 tmpreg &= MACFCR_CLEAR_MASK;
mbed_official 87:085cde657901 1314
mbed_official 87:085cde657901 1315 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
mbed_official 87:085cde657901 1316 macconf->ZeroQuantaPause |
mbed_official 87:085cde657901 1317 macconf->PauseLowThreshold |
mbed_official 87:085cde657901 1318 macconf->UnicastPauseFrameDetect |
mbed_official 87:085cde657901 1319 macconf->ReceiveFlowControl |
mbed_official 87:085cde657901 1320 macconf->TransmitFlowControl);
mbed_official 87:085cde657901 1321
mbed_official 87:085cde657901 1322 /* Write to ETHERNET MACFCR */
mbed_official 87:085cde657901 1323 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1324
mbed_official 87:085cde657901 1325 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1326 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1327 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1328 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1329 (heth->Instance)->MACFCR = tmpreg;
mbed_official 87:085cde657901 1330
mbed_official 87:085cde657901 1331 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
mbed_official 87:085cde657901 1332 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
mbed_official 87:085cde657901 1333 macconf->VLANTagIdentifier);
mbed_official 87:085cde657901 1334
mbed_official 87:085cde657901 1335 /* Wait until the write operation will be taken into account :
mbed_official 87:085cde657901 1336 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1337 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 87:085cde657901 1338 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1339 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 87:085cde657901 1340 }
mbed_official 87:085cde657901 1341 else /* macconf == NULL : here we just configure Speed and Duplex mode */
mbed_official 87:085cde657901 1342 {
mbed_official 87:085cde657901 1343 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 87:085cde657901 1344 /* Get the ETHERNET MACCR value */
mbed_official 87:085cde657901 1345 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1346
mbed_official 87:085cde657901 1347 /* Clear FES and DM bits */
mbed_official 87:085cde657901 1348 tmpreg &= ~((uint32_t)0x00004800);
mbed_official 87:085cde657901 1349
mbed_official 87:085cde657901 1350 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
mbed_official 87:085cde657901 1351
mbed_official 87:085cde657901 1352 /* Write to ETHERNET MACCR */
mbed_official 87:085cde657901 1353 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1354
mbed_official 87:085cde657901 1355 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1356 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1357 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1358 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1359 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1360 }
mbed_official 87:085cde657901 1361
mbed_official 87:085cde657901 1362 /* Set the ETH state to Ready */
mbed_official 87:085cde657901 1363 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1364
mbed_official 87:085cde657901 1365 /* Process Unlocked */
mbed_official 87:085cde657901 1366 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1367
mbed_official 87:085cde657901 1368 /* Return function status */
mbed_official 87:085cde657901 1369 return HAL_OK;
mbed_official 87:085cde657901 1370 }
mbed_official 87:085cde657901 1371
mbed_official 87:085cde657901 1372 /**
mbed_official 87:085cde657901 1373 * @brief Sets ETH DMA Configuration.
mbed_official 87:085cde657901 1374 * @param heth: ETH handle
mbed_official 87:085cde657901 1375 * @param dmaconf: DMA Configuration structure
mbed_official 87:085cde657901 1376 * @retval HAL status
mbed_official 87:085cde657901 1377 */
mbed_official 87:085cde657901 1378 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
mbed_official 87:085cde657901 1379 {
mbed_official 87:085cde657901 1380 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1381
mbed_official 87:085cde657901 1382 /* Process Locked */
mbed_official 87:085cde657901 1383 __HAL_LOCK(heth);
mbed_official 87:085cde657901 1384
mbed_official 87:085cde657901 1385 /* Set the ETH peripheral state to BUSY */
mbed_official 87:085cde657901 1386 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 87:085cde657901 1387
mbed_official 87:085cde657901 1388 /* Check parameters */
mbed_official 87:085cde657901 1389 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
mbed_official 87:085cde657901 1390 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
mbed_official 87:085cde657901 1391 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
mbed_official 87:085cde657901 1392 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
mbed_official 87:085cde657901 1393 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
mbed_official 87:085cde657901 1394 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
mbed_official 87:085cde657901 1395 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
mbed_official 87:085cde657901 1396 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
mbed_official 87:085cde657901 1397 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
mbed_official 87:085cde657901 1398 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
mbed_official 87:085cde657901 1399 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
mbed_official 87:085cde657901 1400 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
mbed_official 87:085cde657901 1401 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
mbed_official 87:085cde657901 1402 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
mbed_official 87:085cde657901 1403 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
mbed_official 87:085cde657901 1404 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
mbed_official 87:085cde657901 1405
mbed_official 87:085cde657901 1406 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
mbed_official 87:085cde657901 1407 /* Get the ETHERNET DMAOMR value */
mbed_official 87:085cde657901 1408 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1409 /* Clear xx bits */
mbed_official 87:085cde657901 1410 tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official 87:085cde657901 1411
mbed_official 87:085cde657901 1412 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
mbed_official 87:085cde657901 1413 dmaconf->ReceiveStoreForward |
mbed_official 87:085cde657901 1414 dmaconf->FlushReceivedFrame |
mbed_official 87:085cde657901 1415 dmaconf->TransmitStoreForward |
mbed_official 87:085cde657901 1416 dmaconf->TransmitThresholdControl |
mbed_official 87:085cde657901 1417 dmaconf->ForwardErrorFrames |
mbed_official 87:085cde657901 1418 dmaconf->ForwardUndersizedGoodFrames |
mbed_official 87:085cde657901 1419 dmaconf->ReceiveThresholdControl |
mbed_official 87:085cde657901 1420 dmaconf->SecondFrameOperate);
mbed_official 87:085cde657901 1421
mbed_official 87:085cde657901 1422 /* Write to ETHERNET DMAOMR */
mbed_official 87:085cde657901 1423 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1424
mbed_official 87:085cde657901 1425 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1426 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1427 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1428 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1429 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 87:085cde657901 1430
mbed_official 87:085cde657901 1431 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
mbed_official 87:085cde657901 1432 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
mbed_official 87:085cde657901 1433 dmaconf->FixedBurst |
mbed_official 87:085cde657901 1434 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 87:085cde657901 1435 dmaconf->TxDMABurstLength |
mbed_official 87:085cde657901 1436 dmaconf->EnhancedDescriptorFormat |
mbed_official 87:085cde657901 1437 (dmaconf->DescriptorSkipLength << 2) |
mbed_official 87:085cde657901 1438 dmaconf->DMAArbitration |
mbed_official 87:085cde657901 1439 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 87:085cde657901 1440
mbed_official 87:085cde657901 1441 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1442 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1443 tmpreg = (heth->Instance)->DMABMR;
mbed_official 87:085cde657901 1444 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1445 (heth->Instance)->DMABMR = tmpreg;
mbed_official 87:085cde657901 1446
mbed_official 87:085cde657901 1447 /* Set the ETH state to Ready */
mbed_official 87:085cde657901 1448 heth->State= HAL_ETH_STATE_READY;
mbed_official 87:085cde657901 1449
mbed_official 87:085cde657901 1450 /* Process Unlocked */
mbed_official 87:085cde657901 1451 __HAL_UNLOCK(heth);
mbed_official 87:085cde657901 1452
mbed_official 87:085cde657901 1453 /* Return function status */
mbed_official 87:085cde657901 1454 return HAL_OK;
mbed_official 87:085cde657901 1455 }
mbed_official 87:085cde657901 1456
mbed_official 87:085cde657901 1457 /**
mbed_official 87:085cde657901 1458 * @}
mbed_official 87:085cde657901 1459 */
mbed_official 87:085cde657901 1460
mbed_official 87:085cde657901 1461 /** @defgroup ETH_Group4 Peripheral State functions
mbed_official 87:085cde657901 1462 * @brief Peripheral State functions
mbed_official 87:085cde657901 1463 *
mbed_official 87:085cde657901 1464 @verbatim
mbed_official 87:085cde657901 1465 ===============================================================================
mbed_official 87:085cde657901 1466 ##### Peripheral State functions #####
mbed_official 87:085cde657901 1467 ===============================================================================
mbed_official 87:085cde657901 1468 [..]
mbed_official 87:085cde657901 1469 This subsection permits to get in run-time the status of the peripheral
mbed_official 87:085cde657901 1470 and the data flow.
mbed_official 87:085cde657901 1471 (+) Get the ETH handle state:
mbed_official 87:085cde657901 1472 HAL_ETH_GetState();
mbed_official 87:085cde657901 1473
mbed_official 87:085cde657901 1474
mbed_official 87:085cde657901 1475 @endverbatim
mbed_official 87:085cde657901 1476 * @{
mbed_official 87:085cde657901 1477 */
mbed_official 87:085cde657901 1478
mbed_official 87:085cde657901 1479 /**
mbed_official 87:085cde657901 1480 * @brief Return the ETH HAL state
mbed_official 87:085cde657901 1481 * @param heth: ETH handle
mbed_official 87:085cde657901 1482 * @retval HAL state
mbed_official 87:085cde657901 1483 */
mbed_official 87:085cde657901 1484 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1485 {
mbed_official 87:085cde657901 1486 /* Return ETH state */
mbed_official 87:085cde657901 1487 return heth->State;
mbed_official 87:085cde657901 1488 }
mbed_official 87:085cde657901 1489
mbed_official 87:085cde657901 1490 /**
mbed_official 87:085cde657901 1491 * @}
mbed_official 87:085cde657901 1492 */
mbed_official 87:085cde657901 1493
mbed_official 87:085cde657901 1494 /**
mbed_official 87:085cde657901 1495 * @brief Configures Ethernet MAC and DMA with default parameters.
mbed_official 87:085cde657901 1496 * @param heth: ETH handle
mbed_official 87:085cde657901 1497 * @param err: Ethernet Init error
mbed_official 87:085cde657901 1498 * @retval HAL status
mbed_official 87:085cde657901 1499 */
mbed_official 87:085cde657901 1500 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
mbed_official 87:085cde657901 1501 {
mbed_official 87:085cde657901 1502 ETH_MACInitTypeDef macinit;
mbed_official 87:085cde657901 1503 ETH_DMAInitTypeDef dmainit;
mbed_official 87:085cde657901 1504 uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1505
mbed_official 87:085cde657901 1506 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
mbed_official 87:085cde657901 1507 {
mbed_official 87:085cde657901 1508 /* Set Ethernet duplex mode to Full-duplex */
mbed_official 87:085cde657901 1509 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 87:085cde657901 1510
mbed_official 87:085cde657901 1511 /* Set Ethernet speed to 100M */
mbed_official 87:085cde657901 1512 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 87:085cde657901 1513 }
mbed_official 87:085cde657901 1514
mbed_official 87:085cde657901 1515 /* Ethernet MAC default initialization **************************************/
mbed_official 87:085cde657901 1516 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
mbed_official 87:085cde657901 1517 macinit.Jabber = ETH_JABBER_ENABLE;
mbed_official 87:085cde657901 1518 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
mbed_official 87:085cde657901 1519 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
mbed_official 87:085cde657901 1520 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
mbed_official 87:085cde657901 1521 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
mbed_official 87:085cde657901 1522 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 87:085cde657901 1523 {
mbed_official 87:085cde657901 1524 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
mbed_official 87:085cde657901 1525 }
mbed_official 87:085cde657901 1526 else
mbed_official 87:085cde657901 1527 {
mbed_official 87:085cde657901 1528 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
mbed_official 87:085cde657901 1529 }
mbed_official 87:085cde657901 1530 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
mbed_official 87:085cde657901 1531 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
mbed_official 87:085cde657901 1532 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
mbed_official 87:085cde657901 1533 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
mbed_official 87:085cde657901 1534 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
mbed_official 87:085cde657901 1535 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
mbed_official 87:085cde657901 1536 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
mbed_official 87:085cde657901 1537 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
mbed_official 87:085cde657901 1538 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
mbed_official 87:085cde657901 1539 macinit.PromiscuousMode = ETH_PROMISCIOUSMODE_DISABLE;
mbed_official 87:085cde657901 1540 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
mbed_official 87:085cde657901 1541 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
mbed_official 87:085cde657901 1542 macinit.HashTableHigh = 0x0;
mbed_official 87:085cde657901 1543 macinit.HashTableLow = 0x0;
mbed_official 87:085cde657901 1544 macinit.PauseTime = 0x0;
mbed_official 87:085cde657901 1545 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
mbed_official 87:085cde657901 1546 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
mbed_official 87:085cde657901 1547 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
mbed_official 87:085cde657901 1548 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
mbed_official 87:085cde657901 1549 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
mbed_official 87:085cde657901 1550 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
mbed_official 87:085cde657901 1551 macinit.VLANTagIdentifier = 0x0;
mbed_official 87:085cde657901 1552
mbed_official 87:085cde657901 1553 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 87:085cde657901 1554 /* Get the ETHERNET MACCR value */
mbed_official 87:085cde657901 1555 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1556 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 87:085cde657901 1557 tmpreg &= MACCR_CLEAR_MASK;
mbed_official 87:085cde657901 1558 /* Set the WD bit according to ETH Watchdog value */
mbed_official 87:085cde657901 1559 /* Set the JD: bit according to ETH Jabber value */
mbed_official 87:085cde657901 1560 /* Set the IFG bit according to ETH InterFrameGap value */
mbed_official 87:085cde657901 1561 /* Set the DCRS bit according to ETH CarrierSense value */
mbed_official 87:085cde657901 1562 /* Set the FES bit according to ETH Speed value */
mbed_official 87:085cde657901 1563 /* Set the DO bit according to ETH ReceiveOwn value */
mbed_official 87:085cde657901 1564 /* Set the LM bit according to ETH LoopbackMode value */
mbed_official 87:085cde657901 1565 /* Set the DM bit according to ETH Mode value */
mbed_official 87:085cde657901 1566 /* Set the IPCO bit according to ETH ChecksumOffload value */
mbed_official 87:085cde657901 1567 /* Set the DR bit according to ETH RetryTransmission value */
mbed_official 87:085cde657901 1568 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
mbed_official 87:085cde657901 1569 /* Set the BL bit according to ETH BackOffLimit value */
mbed_official 87:085cde657901 1570 /* Set the DC bit according to ETH DeferralCheck value */
mbed_official 87:085cde657901 1571 tmpreg |= (uint32_t)(macinit.Watchdog |
mbed_official 87:085cde657901 1572 macinit.Jabber |
mbed_official 87:085cde657901 1573 macinit.InterFrameGap |
mbed_official 87:085cde657901 1574 macinit.CarrierSense |
mbed_official 87:085cde657901 1575 (heth->Init).Speed |
mbed_official 87:085cde657901 1576 macinit.ReceiveOwn |
mbed_official 87:085cde657901 1577 macinit.LoopbackMode |
mbed_official 87:085cde657901 1578 (heth->Init).DuplexMode |
mbed_official 87:085cde657901 1579 macinit.ChecksumOffload |
mbed_official 87:085cde657901 1580 macinit.RetryTransmission |
mbed_official 87:085cde657901 1581 macinit.AutomaticPadCRCStrip |
mbed_official 87:085cde657901 1582 macinit.BackOffLimit |
mbed_official 87:085cde657901 1583 macinit.DeferralCheck);
mbed_official 87:085cde657901 1584
mbed_official 87:085cde657901 1585 /* Write to ETHERNET MACCR */
mbed_official 87:085cde657901 1586 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1587
mbed_official 87:085cde657901 1588 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1589 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1590 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1591 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1592 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1593
mbed_official 87:085cde657901 1594 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 87:085cde657901 1595 /* Set the RA bit according to ETH ReceiveAll value */
mbed_official 87:085cde657901 1596 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
mbed_official 87:085cde657901 1597 /* Set the PCF bit according to ETH PassControlFrames value */
mbed_official 87:085cde657901 1598 /* Set the DBF bit according to ETH BroadcastFramesReception value */
mbed_official 87:085cde657901 1599 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
mbed_official 87:085cde657901 1600 /* Set the PR bit according to ETH PromiscuousMode value */
mbed_official 87:085cde657901 1601 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
mbed_official 87:085cde657901 1602 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
mbed_official 87:085cde657901 1603 /* Write to ETHERNET MACFFR */
mbed_official 87:085cde657901 1604 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
mbed_official 87:085cde657901 1605 macinit.SourceAddrFilter |
mbed_official 87:085cde657901 1606 macinit.PassControlFrames |
mbed_official 87:085cde657901 1607 macinit.BroadcastFramesReception |
mbed_official 87:085cde657901 1608 macinit.DestinationAddrFilter |
mbed_official 87:085cde657901 1609 macinit.PromiscuousMode |
mbed_official 87:085cde657901 1610 macinit.MulticastFramesFilter |
mbed_official 87:085cde657901 1611 macinit.UnicastFramesFilter);
mbed_official 87:085cde657901 1612
mbed_official 87:085cde657901 1613 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1614 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1615 tmpreg = (heth->Instance)->MACFFR;
mbed_official 87:085cde657901 1616 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1617 (heth->Instance)->MACFFR = tmpreg;
mbed_official 87:085cde657901 1618
mbed_official 87:085cde657901 1619 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
mbed_official 87:085cde657901 1620 /* Write to ETHERNET MACHTHR */
mbed_official 87:085cde657901 1621 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
mbed_official 87:085cde657901 1622
mbed_official 87:085cde657901 1623 /* Write to ETHERNET MACHTLR */
mbed_official 87:085cde657901 1624 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
mbed_official 87:085cde657901 1625 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
mbed_official 87:085cde657901 1626
mbed_official 87:085cde657901 1627 /* Get the ETHERNET MACFCR value */
mbed_official 87:085cde657901 1628 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1629 /* Clear xx bits */
mbed_official 87:085cde657901 1630 tmpreg &= MACFCR_CLEAR_MASK;
mbed_official 87:085cde657901 1631
mbed_official 87:085cde657901 1632 /* Set the PT bit according to ETH PauseTime value */
mbed_official 87:085cde657901 1633 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
mbed_official 87:085cde657901 1634 /* Set the PLT bit according to ETH PauseLowThreshold value */
mbed_official 87:085cde657901 1635 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
mbed_official 87:085cde657901 1636 /* Set the RFE bit according to ETH ReceiveFlowControl value */
mbed_official 87:085cde657901 1637 /* Set the TFE bit according to ETH TransmitFlowControl value */
mbed_official 87:085cde657901 1638 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
mbed_official 87:085cde657901 1639 macinit.ZeroQuantaPause |
mbed_official 87:085cde657901 1640 macinit.PauseLowThreshold |
mbed_official 87:085cde657901 1641 macinit.UnicastPauseFrameDetect |
mbed_official 87:085cde657901 1642 macinit.ReceiveFlowControl |
mbed_official 87:085cde657901 1643 macinit.TransmitFlowControl);
mbed_official 87:085cde657901 1644
mbed_official 87:085cde657901 1645 /* Write to ETHERNET MACFCR */
mbed_official 87:085cde657901 1646 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1647
mbed_official 87:085cde657901 1648 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1649 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1650 tmpreg = (heth->Instance)->MACFCR;
mbed_official 87:085cde657901 1651 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1652 (heth->Instance)->MACFCR = tmpreg;
mbed_official 87:085cde657901 1653
mbed_official 87:085cde657901 1654 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
mbed_official 87:085cde657901 1655 /* Set the ETV bit according to ETH VLANTagComparison value */
mbed_official 87:085cde657901 1656 /* Set the VL bit according to ETH VLANTagIdentifier value */
mbed_official 87:085cde657901 1657 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
mbed_official 87:085cde657901 1658 macinit.VLANTagIdentifier);
mbed_official 87:085cde657901 1659
mbed_official 87:085cde657901 1660 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1661 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1662 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 87:085cde657901 1663 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1664 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 87:085cde657901 1665
mbed_official 87:085cde657901 1666 /* Ethernet DMA default initialization ************************************/
mbed_official 87:085cde657901 1667 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
mbed_official 87:085cde657901 1668 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
mbed_official 87:085cde657901 1669 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
mbed_official 87:085cde657901 1670 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
mbed_official 87:085cde657901 1671 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
mbed_official 87:085cde657901 1672 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
mbed_official 87:085cde657901 1673 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
mbed_official 87:085cde657901 1674 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
mbed_official 87:085cde657901 1675 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
mbed_official 87:085cde657901 1676 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
mbed_official 87:085cde657901 1677 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
mbed_official 87:085cde657901 1678 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
mbed_official 87:085cde657901 1679 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
mbed_official 87:085cde657901 1680 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
mbed_official 87:085cde657901 1681 dmainit.DescriptorSkipLength = 0x0;
mbed_official 87:085cde657901 1682 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
mbed_official 87:085cde657901 1683
mbed_official 87:085cde657901 1684 /* Get the ETHERNET DMAOMR value */
mbed_official 87:085cde657901 1685 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1686 /* Clear xx bits */
mbed_official 87:085cde657901 1687 tmpreg &= DMAOMR_CLEAR_MASK;
mbed_official 87:085cde657901 1688
mbed_official 87:085cde657901 1689 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
mbed_official 87:085cde657901 1690 /* Set the RSF bit according to ETH ReceiveStoreForward value */
mbed_official 87:085cde657901 1691 /* Set the DFF bit according to ETH FlushReceivedFrame value */
mbed_official 87:085cde657901 1692 /* Set the TSF bit according to ETH TransmitStoreForward value */
mbed_official 87:085cde657901 1693 /* Set the TTC bit according to ETH TransmitThresholdControl value */
mbed_official 87:085cde657901 1694 /* Set the FEF bit according to ETH ForwardErrorFrames value */
mbed_official 87:085cde657901 1695 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
mbed_official 87:085cde657901 1696 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
mbed_official 87:085cde657901 1697 /* Set the OSF bit according to ETH SecondFrameOperate value */
mbed_official 87:085cde657901 1698 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
mbed_official 87:085cde657901 1699 dmainit.ReceiveStoreForward |
mbed_official 87:085cde657901 1700 dmainit.FlushReceivedFrame |
mbed_official 87:085cde657901 1701 dmainit.TransmitStoreForward |
mbed_official 87:085cde657901 1702 dmainit.TransmitThresholdControl |
mbed_official 87:085cde657901 1703 dmainit.ForwardErrorFrames |
mbed_official 87:085cde657901 1704 dmainit.ForwardUndersizedGoodFrames |
mbed_official 87:085cde657901 1705 dmainit.ReceiveThresholdControl |
mbed_official 87:085cde657901 1706 dmainit.SecondFrameOperate);
mbed_official 87:085cde657901 1707
mbed_official 87:085cde657901 1708 /* Write to ETHERNET DMAOMR */
mbed_official 87:085cde657901 1709 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 87:085cde657901 1710
mbed_official 87:085cde657901 1711 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1712 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1713 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1714 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1715 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 87:085cde657901 1716
mbed_official 87:085cde657901 1717 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
mbed_official 87:085cde657901 1718 /* Set the AAL bit according to ETH AddressAlignedBeats value */
mbed_official 87:085cde657901 1719 /* Set the FB bit according to ETH FixedBurst value */
mbed_official 87:085cde657901 1720 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
mbed_official 87:085cde657901 1721 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
mbed_official 87:085cde657901 1722 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
mbed_official 87:085cde657901 1723 /* Set the DSL bit according to ETH DesciptorSkipLength value */
mbed_official 87:085cde657901 1724 /* Set the PR and DA bits according to ETH DMAArbitration value */
mbed_official 87:085cde657901 1725 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
mbed_official 87:085cde657901 1726 dmainit.FixedBurst |
mbed_official 87:085cde657901 1727 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 87:085cde657901 1728 dmainit.TxDMABurstLength |
mbed_official 87:085cde657901 1729 dmainit.EnhancedDescriptorFormat |
mbed_official 87:085cde657901 1730 (dmainit.DescriptorSkipLength << 2) |
mbed_official 87:085cde657901 1731 dmainit.DMAArbitration |
mbed_official 87:085cde657901 1732 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 87:085cde657901 1733
mbed_official 87:085cde657901 1734 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1735 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1736 tmpreg = (heth->Instance)->DMABMR;
mbed_official 87:085cde657901 1737 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1738 (heth->Instance)->DMABMR = tmpreg;
mbed_official 87:085cde657901 1739
mbed_official 87:085cde657901 1740 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 87:085cde657901 1741 {
mbed_official 87:085cde657901 1742 /* Enable the Ethernet Rx Interrupt */
mbed_official 87:085cde657901 1743 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
mbed_official 87:085cde657901 1744 }
mbed_official 87:085cde657901 1745
mbed_official 87:085cde657901 1746 /* Initialize MAC address in ethernet MAC */
mbed_official 87:085cde657901 1747 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
mbed_official 87:085cde657901 1748 }
mbed_official 87:085cde657901 1749
mbed_official 87:085cde657901 1750 /**
mbed_official 87:085cde657901 1751 * @brief Configures the selected MAC address.
mbed_official 87:085cde657901 1752 * @param heth: ETH handle
mbed_official 87:085cde657901 1753 * @param MacAddr: The MAC address to configure
mbed_official 87:085cde657901 1754 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1755 * @arg ETH_MAC_Address0: MAC Address0
mbed_official 87:085cde657901 1756 * @arg ETH_MAC_Address1: MAC Address1
mbed_official 87:085cde657901 1757 * @arg ETH_MAC_Address2: MAC Address2
mbed_official 87:085cde657901 1758 * @arg ETH_MAC_Address3: MAC Address3
mbed_official 87:085cde657901 1759 * @param Addr: Pointer to MAC address buffer data (6 bytes)
mbed_official 87:085cde657901 1760 * @retval HAL status
mbed_official 87:085cde657901 1761 */
mbed_official 87:085cde657901 1762 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
mbed_official 87:085cde657901 1763 {
mbed_official 87:085cde657901 1764 uint32_t tmpreg;
mbed_official 87:085cde657901 1765
mbed_official 87:085cde657901 1766 /* Check the parameters */
mbed_official 87:085cde657901 1767 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
mbed_official 87:085cde657901 1768
mbed_official 87:085cde657901 1769 /* Calculate the selected MAC address high register */
mbed_official 87:085cde657901 1770 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
mbed_official 87:085cde657901 1771 /* Load the selected MAC address high register */
mbed_official 87:085cde657901 1772 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
mbed_official 87:085cde657901 1773 /* Calculate the selected MAC address low register */
mbed_official 87:085cde657901 1774 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
mbed_official 87:085cde657901 1775
mbed_official 87:085cde657901 1776 /* Load the selected MAC address low register */
mbed_official 87:085cde657901 1777 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
mbed_official 87:085cde657901 1778 }
mbed_official 87:085cde657901 1779
mbed_official 87:085cde657901 1780 /**
mbed_official 87:085cde657901 1781 * @brief Enables the MAC transmission.
mbed_official 87:085cde657901 1782 * @param heth: ETH handle
mbed_official 87:085cde657901 1783 * @retval None
mbed_official 87:085cde657901 1784 */
mbed_official 87:085cde657901 1785 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1786 {
mbed_official 87:085cde657901 1787 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1788
mbed_official 87:085cde657901 1789 /* Enable the MAC transmission */
mbed_official 87:085cde657901 1790 (heth->Instance)->MACCR |= ETH_MACCR_TE;
mbed_official 87:085cde657901 1791
mbed_official 87:085cde657901 1792 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1793 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1794 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1795 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1796 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1797 }
mbed_official 87:085cde657901 1798
mbed_official 87:085cde657901 1799 /**
mbed_official 87:085cde657901 1800 * @brief Disables the MAC transmission.
mbed_official 87:085cde657901 1801 * @param heth: ETH handle
mbed_official 87:085cde657901 1802 * @retval None
mbed_official 87:085cde657901 1803 */
mbed_official 87:085cde657901 1804 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1805 {
mbed_official 87:085cde657901 1806 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1807
mbed_official 87:085cde657901 1808 /* Disable the MAC transmission */
mbed_official 87:085cde657901 1809 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
mbed_official 87:085cde657901 1810
mbed_official 87:085cde657901 1811 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1812 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1813 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1814 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1815 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1816 }
mbed_official 87:085cde657901 1817
mbed_official 87:085cde657901 1818 /**
mbed_official 87:085cde657901 1819 * @brief Enables the MAC reception.
mbed_official 87:085cde657901 1820 * @param heth: ETH handle
mbed_official 87:085cde657901 1821 * @retval None
mbed_official 87:085cde657901 1822 */
mbed_official 87:085cde657901 1823 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1824 {
mbed_official 87:085cde657901 1825 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1826
mbed_official 87:085cde657901 1827 /* Enable the MAC reception */
mbed_official 87:085cde657901 1828 (heth->Instance)->MACCR |= ETH_MACCR_RE;
mbed_official 87:085cde657901 1829
mbed_official 87:085cde657901 1830 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1831 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1832 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1833 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1834 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1835 }
mbed_official 87:085cde657901 1836
mbed_official 87:085cde657901 1837 /**
mbed_official 87:085cde657901 1838 * @brief Disables the MAC reception.
mbed_official 87:085cde657901 1839 * @param heth: ETH handle
mbed_official 87:085cde657901 1840 * @retval None
mbed_official 87:085cde657901 1841 */
mbed_official 87:085cde657901 1842 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1843 {
mbed_official 87:085cde657901 1844 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1845
mbed_official 87:085cde657901 1846 /* Disable the MAC reception */
mbed_official 87:085cde657901 1847 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
mbed_official 87:085cde657901 1848
mbed_official 87:085cde657901 1849 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1850 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1851 tmpreg = (heth->Instance)->MACCR;
mbed_official 87:085cde657901 1852 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1853 (heth->Instance)->MACCR = tmpreg;
mbed_official 87:085cde657901 1854 }
mbed_official 87:085cde657901 1855
mbed_official 87:085cde657901 1856 /**
mbed_official 87:085cde657901 1857 * @brief Enables the DMA transmission.
mbed_official 87:085cde657901 1858 * @param heth: ETH handle
mbed_official 87:085cde657901 1859 * @retval None
mbed_official 87:085cde657901 1860 */
mbed_official 87:085cde657901 1861 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1862 {
mbed_official 87:085cde657901 1863 /* Enable the DMA transmission */
mbed_official 87:085cde657901 1864 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
mbed_official 87:085cde657901 1865 }
mbed_official 87:085cde657901 1866
mbed_official 87:085cde657901 1867 /**
mbed_official 87:085cde657901 1868 * @brief Disables the DMA transmission.
mbed_official 87:085cde657901 1869 * @param heth: ETH handle
mbed_official 87:085cde657901 1870 * @retval None
mbed_official 87:085cde657901 1871 */
mbed_official 87:085cde657901 1872 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1873 {
mbed_official 87:085cde657901 1874 /* Disable the DMA transmission */
mbed_official 87:085cde657901 1875 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
mbed_official 87:085cde657901 1876 }
mbed_official 87:085cde657901 1877
mbed_official 87:085cde657901 1878 /**
mbed_official 87:085cde657901 1879 * @brief Enables the DMA reception.
mbed_official 87:085cde657901 1880 * @param heth: ETH handle
mbed_official 87:085cde657901 1881 * @retval None
mbed_official 87:085cde657901 1882 */
mbed_official 87:085cde657901 1883 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1884 {
mbed_official 87:085cde657901 1885 /* Enable the DMA reception */
mbed_official 87:085cde657901 1886 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
mbed_official 87:085cde657901 1887 }
mbed_official 87:085cde657901 1888
mbed_official 87:085cde657901 1889 /**
mbed_official 87:085cde657901 1890 * @brief Disables the DMA reception.
mbed_official 87:085cde657901 1891 * @param heth: ETH handle
mbed_official 87:085cde657901 1892 * @retval None
mbed_official 87:085cde657901 1893 */
mbed_official 87:085cde657901 1894 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1895 {
mbed_official 87:085cde657901 1896 /* Disable the DMA reception */
mbed_official 87:085cde657901 1897 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
mbed_official 87:085cde657901 1898 }
mbed_official 87:085cde657901 1899
mbed_official 87:085cde657901 1900 /**
mbed_official 87:085cde657901 1901 * @brief Clears the ETHERNET transmit FIFO.
mbed_official 87:085cde657901 1902 * @param heth: ETH handle
mbed_official 87:085cde657901 1903 * @retval None
mbed_official 87:085cde657901 1904 */
mbed_official 87:085cde657901 1905 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
mbed_official 87:085cde657901 1906 {
mbed_official 87:085cde657901 1907 __IO uint32_t tmpreg = 0;
mbed_official 87:085cde657901 1908
mbed_official 87:085cde657901 1909 /* Set the Flush Transmit FIFO bit */
mbed_official 87:085cde657901 1910 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
mbed_official 87:085cde657901 1911
mbed_official 87:085cde657901 1912 /* Wait until the write operation will be taken into account:
mbed_official 87:085cde657901 1913 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 87:085cde657901 1914 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 87:085cde657901 1915 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 87:085cde657901 1916 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 87:085cde657901 1917 }
mbed_official 87:085cde657901 1918
mbed_official 87:085cde657901 1919 /**
mbed_official 87:085cde657901 1920 * @}
mbed_official 87:085cde657901 1921 */
mbed_official 87:085cde657901 1922
mbed_official 87:085cde657901 1923 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 1924 #endif /* HAL_ETH_MODULE_ENABLED */
mbed_official 87:085cde657901 1925 /**
mbed_official 87:085cde657901 1926 * @}
mbed_official 87:085cde657901 1927 */
mbed_official 87:085cde657901 1928
mbed_official 87:085cde657901 1929 /**
mbed_official 87:085cde657901 1930 * @}
mbed_official 87:085cde657901 1931 */
mbed_official 87:085cde657901 1932
mbed_official 87:085cde657901 1933 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/