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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/inc/iodefines/dvdec_iodefine.h@579:53297373a894, 2015-07-01 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Jul 01 09:45:11 2015 +0100
- Revision:
- 579:53297373a894
- Parent:
- 390:35c2c1cf29cd
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081
Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/
Initial version of drivers for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 390:35c2c1cf29cd | 1 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 2 | * DISCLAIMER |
| mbed_official | 390:35c2c1cf29cd | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
| mbed_official | 390:35c2c1cf29cd | 4 | * intended for use with Renesas products. No other uses are authorized. This |
| mbed_official | 390:35c2c1cf29cd | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
| mbed_official | 390:35c2c1cf29cd | 6 | * all applicable laws, including copyright laws. |
| mbed_official | 390:35c2c1cf29cd | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
| mbed_official | 390:35c2c1cf29cd | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
| mbed_official | 390:35c2c1cf29cd | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
| mbed_official | 390:35c2c1cf29cd | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
| mbed_official | 390:35c2c1cf29cd | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
| mbed_official | 390:35c2c1cf29cd | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
| mbed_official | 390:35c2c1cf29cd | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
| mbed_official | 390:35c2c1cf29cd | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
| mbed_official | 390:35c2c1cf29cd | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
| mbed_official | 390:35c2c1cf29cd | 16 | * Renesas reserves the right, without notice, to make changes to this software |
| mbed_official | 390:35c2c1cf29cd | 17 | * and to discontinue the availability of this software. By using this software, |
| mbed_official | 390:35c2c1cf29cd | 18 | * you agree to the additional terms and conditions found by accessing the |
| mbed_official | 390:35c2c1cf29cd | 19 | * following link: |
| mbed_official | 390:35c2c1cf29cd | 20 | * http://www.renesas.com/disclaimer* |
| mbed_official | 390:35c2c1cf29cd | 21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. |
| mbed_official | 390:35c2c1cf29cd | 22 | *******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 23 | /******************************************************************************* |
| mbed_official | 390:35c2c1cf29cd | 24 | * File Name : dvdec_iodefine.h |
| mbed_official | 390:35c2c1cf29cd | 25 | * $Rev: $ |
| mbed_official | 390:35c2c1cf29cd | 26 | * $Date:: $ |
| mbed_official | 390:35c2c1cf29cd | 27 | * Description : Definition of I/O Register (V1.00a) |
| mbed_official | 390:35c2c1cf29cd | 28 | ******************************************************************************/ |
| mbed_official | 390:35c2c1cf29cd | 29 | #ifndef DVDEC_IODEFINE_H |
| mbed_official | 390:35c2c1cf29cd | 30 | #define DVDEC_IODEFINE_H |
| mbed_official | 390:35c2c1cf29cd | 31 | /* ->SEC M1.10.1 : Not magic number */ |
| mbed_official | 390:35c2c1cf29cd | 32 | |
| mbed_official | 390:35c2c1cf29cd | 33 | struct st_dvdec |
| mbed_official | 390:35c2c1cf29cd | 34 | { /* DVDEC */ |
| mbed_official | 390:35c2c1cf29cd | 35 | volatile uint16_t ADCCR1; /* ADCCR1 */ |
| mbed_official | 390:35c2c1cf29cd | 36 | volatile uint8_t dummy1[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 37 | #define DVDEC_TGCRn_COUNT 3 |
| mbed_official | 390:35c2c1cf29cd | 38 | volatile uint16_t TGCR1; /* TGCR1 */ |
| mbed_official | 390:35c2c1cf29cd | 39 | volatile uint16_t TGCR2; /* TGCR2 */ |
| mbed_official | 390:35c2c1cf29cd | 40 | volatile uint16_t TGCR3; /* TGCR3 */ |
| mbed_official | 390:35c2c1cf29cd | 41 | volatile uint8_t dummy2[6]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 42 | #define DVDEC_SYNSCRn_COUNT 5 |
| mbed_official | 390:35c2c1cf29cd | 43 | volatile uint16_t SYNSCR1; /* SYNSCR1 */ |
| mbed_official | 390:35c2c1cf29cd | 44 | volatile uint16_t SYNSCR2; /* SYNSCR2 */ |
| mbed_official | 390:35c2c1cf29cd | 45 | volatile uint16_t SYNSCR3; /* SYNSCR3 */ |
| mbed_official | 390:35c2c1cf29cd | 46 | volatile uint16_t SYNSCR4; /* SYNSCR4 */ |
| mbed_official | 390:35c2c1cf29cd | 47 | volatile uint16_t SYNSCR5; /* SYNSCR5 */ |
| mbed_official | 390:35c2c1cf29cd | 48 | #define DVDEC_HAFCCRn_COUNT 3 |
| mbed_official | 390:35c2c1cf29cd | 49 | volatile uint16_t HAFCCR1; /* HAFCCR1 */ |
| mbed_official | 390:35c2c1cf29cd | 50 | volatile uint16_t HAFCCR2; /* HAFCCR2 */ |
| mbed_official | 390:35c2c1cf29cd | 51 | volatile uint16_t HAFCCR3; /* HAFCCR3 */ |
| mbed_official | 390:35c2c1cf29cd | 52 | volatile uint16_t VCDWCR1; /* VCDWCR1 */ |
| mbed_official | 390:35c2c1cf29cd | 53 | volatile uint8_t dummy3[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 54 | #define DVDEC_DCPCRn_COUNT 8 |
| mbed_official | 390:35c2c1cf29cd | 55 | volatile uint16_t DCPCR1; /* DCPCR1 */ |
| mbed_official | 390:35c2c1cf29cd | 56 | volatile uint16_t DCPCR2; /* DCPCR2 */ |
| mbed_official | 390:35c2c1cf29cd | 57 | volatile uint16_t DCPCR3; /* DCPCR3 */ |
| mbed_official | 390:35c2c1cf29cd | 58 | volatile uint16_t DCPCR4; /* DCPCR4 */ |
| mbed_official | 390:35c2c1cf29cd | 59 | volatile uint16_t DCPCR5; /* DCPCR5 */ |
| mbed_official | 390:35c2c1cf29cd | 60 | volatile uint16_t DCPCR6; /* DCPCR6 */ |
| mbed_official | 390:35c2c1cf29cd | 61 | volatile uint16_t DCPCR7; /* DCPCR7 */ |
| mbed_official | 390:35c2c1cf29cd | 62 | volatile uint16_t DCPCR8; /* DCPCR8 */ |
| mbed_official | 390:35c2c1cf29cd | 63 | volatile uint16_t NSDCR; /* NSDCR */ |
| mbed_official | 390:35c2c1cf29cd | 64 | volatile uint16_t BTLCR; /* BTLCR */ |
| mbed_official | 390:35c2c1cf29cd | 65 | volatile uint16_t BTGPCR; /* BTGPCR */ |
| mbed_official | 390:35c2c1cf29cd | 66 | #define DVDEC_ACCCRn_COUNT 3 |
| mbed_official | 390:35c2c1cf29cd | 67 | volatile uint16_t ACCCR1; /* ACCCR1 */ |
| mbed_official | 390:35c2c1cf29cd | 68 | volatile uint16_t ACCCR2; /* ACCCR2 */ |
| mbed_official | 390:35c2c1cf29cd | 69 | volatile uint16_t ACCCR3; /* ACCCR3 */ |
| mbed_official | 390:35c2c1cf29cd | 70 | volatile uint16_t TINTCR; /* TINTCR */ |
| mbed_official | 390:35c2c1cf29cd | 71 | volatile uint16_t YCDCR; /* YCDCR */ |
| mbed_official | 390:35c2c1cf29cd | 72 | #define DVDEC_AGCCRn_COUNT 2 |
| mbed_official | 390:35c2c1cf29cd | 73 | volatile uint16_t AGCCR1; /* AGCCR1 */ |
| mbed_official | 390:35c2c1cf29cd | 74 | volatile uint16_t AGCCR2; /* AGCCR2 */ |
| mbed_official | 390:35c2c1cf29cd | 75 | volatile uint16_t PKLIMITCR; /* PKLIMITCR */ |
| mbed_official | 390:35c2c1cf29cd | 76 | #define DVDEC_RGORCRn_COUNT 7 |
| mbed_official | 390:35c2c1cf29cd | 77 | volatile uint16_t RGORCR1; /* RGORCR1 */ |
| mbed_official | 390:35c2c1cf29cd | 78 | volatile uint16_t RGORCR2; /* RGORCR2 */ |
| mbed_official | 390:35c2c1cf29cd | 79 | volatile uint16_t RGORCR3; /* RGORCR3 */ |
| mbed_official | 390:35c2c1cf29cd | 80 | volatile uint16_t RGORCR4; /* RGORCR4 */ |
| mbed_official | 390:35c2c1cf29cd | 81 | volatile uint16_t RGORCR5; /* RGORCR5 */ |
| mbed_official | 390:35c2c1cf29cd | 82 | volatile uint16_t RGORCR6; /* RGORCR6 */ |
| mbed_official | 390:35c2c1cf29cd | 83 | volatile uint16_t RGORCR7; /* RGORCR7 */ |
| mbed_official | 390:35c2c1cf29cd | 84 | volatile uint8_t dummy4[24]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 85 | volatile uint16_t AFCPFCR; /* AFCPFCR */ |
| mbed_official | 390:35c2c1cf29cd | 86 | volatile uint16_t RUPDCR; /* RUPDCR */ |
| mbed_official | 390:35c2c1cf29cd | 87 | volatile uint16_t VSYNCSR; /* VSYNCSR */ |
| mbed_official | 390:35c2c1cf29cd | 88 | volatile uint16_t HSYNCSR; /* HSYNCSR */ |
| mbed_official | 390:35c2c1cf29cd | 89 | #define DVDEC_DCPSRn_COUNT 2 |
| mbed_official | 390:35c2c1cf29cd | 90 | volatile uint16_t DCPSR1; /* DCPSR1 */ |
| mbed_official | 390:35c2c1cf29cd | 91 | volatile uint16_t DCPSR2; /* DCPSR2 */ |
| mbed_official | 390:35c2c1cf29cd | 92 | volatile uint8_t dummy5[4]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 93 | volatile uint16_t NSDSR; /* NSDSR */ |
| mbed_official | 390:35c2c1cf29cd | 94 | #define DVDEC_CROMASRn_COUNT 2 |
| mbed_official | 390:35c2c1cf29cd | 95 | volatile uint16_t CROMASR1; /* CROMASR1 */ |
| mbed_official | 390:35c2c1cf29cd | 96 | volatile uint16_t CROMASR2; /* CROMASR2 */ |
| mbed_official | 390:35c2c1cf29cd | 97 | volatile uint16_t SYNCSSR; /* SYNCSSR */ |
| mbed_official | 390:35c2c1cf29cd | 98 | #define DVDEC_AGCCSRn_COUNT 2 |
| mbed_official | 390:35c2c1cf29cd | 99 | volatile uint16_t AGCCSR1; /* AGCCSR1 */ |
| mbed_official | 390:35c2c1cf29cd | 100 | volatile uint16_t AGCCSR2; /* AGCCSR2 */ |
| mbed_official | 390:35c2c1cf29cd | 101 | volatile uint8_t dummy6[108]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 102 | #define DVDEC_YCSCRn_COUNT 7 |
| mbed_official | 390:35c2c1cf29cd | 103 | volatile uint16_t YCSCR3; /* YCSCR3 */ |
| mbed_official | 390:35c2c1cf29cd | 104 | volatile uint16_t YCSCR4; /* YCSCR4 */ |
| mbed_official | 390:35c2c1cf29cd | 105 | volatile uint16_t YCSCR5; /* YCSCR5 */ |
| mbed_official | 390:35c2c1cf29cd | 106 | volatile uint16_t YCSCR6; /* YCSCR6 */ |
| mbed_official | 390:35c2c1cf29cd | 107 | volatile uint16_t YCSCR7; /* YCSCR7 */ |
| mbed_official | 390:35c2c1cf29cd | 108 | volatile uint16_t YCSCR8; /* YCSCR8 */ |
| mbed_official | 390:35c2c1cf29cd | 109 | volatile uint16_t YCSCR9; /* YCSCR9 */ |
| mbed_official | 390:35c2c1cf29cd | 110 | volatile uint8_t dummy7[2]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 111 | volatile uint16_t YCSCR11; /* YCSCR11 */ |
| mbed_official | 390:35c2c1cf29cd | 112 | volatile uint16_t YCSCR12; /* YCSCR12 */ |
| mbed_official | 390:35c2c1cf29cd | 113 | volatile uint8_t dummy8[104]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 114 | volatile uint16_t DCPCR9; /* DCPCR9 */ |
| mbed_official | 390:35c2c1cf29cd | 115 | volatile uint8_t dummy9[16]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 116 | #define DVDEC_YCTWA_Fn_COUNT 9 |
| mbed_official | 390:35c2c1cf29cd | 117 | volatile uint16_t YCTWA_F0; /* YCTWA_F0 */ |
| mbed_official | 390:35c2c1cf29cd | 118 | volatile uint16_t YCTWA_F1; /* YCTWA_F1 */ |
| mbed_official | 390:35c2c1cf29cd | 119 | volatile uint16_t YCTWA_F2; /* YCTWA_F2 */ |
| mbed_official | 390:35c2c1cf29cd | 120 | volatile uint16_t YCTWA_F3; /* YCTWA_F3 */ |
| mbed_official | 390:35c2c1cf29cd | 121 | volatile uint16_t YCTWA_F4; /* YCTWA_F4 */ |
| mbed_official | 390:35c2c1cf29cd | 122 | volatile uint16_t YCTWA_F5; /* YCTWA_F5 */ |
| mbed_official | 390:35c2c1cf29cd | 123 | volatile uint16_t YCTWA_F6; /* YCTWA_F6 */ |
| mbed_official | 390:35c2c1cf29cd | 124 | volatile uint16_t YCTWA_F7; /* YCTWA_F7 */ |
| mbed_official | 390:35c2c1cf29cd | 125 | volatile uint16_t YCTWA_F8; /* YCTWA_F8 */ |
| mbed_official | 390:35c2c1cf29cd | 126 | #define DVDEC_YCTWB_Fn_COUNT 9 |
| mbed_official | 390:35c2c1cf29cd | 127 | volatile uint16_t YCTWB_F0; /* YCTWB_F0 */ |
| mbed_official | 390:35c2c1cf29cd | 128 | volatile uint16_t YCTWB_F1; /* YCTWB_F1 */ |
| mbed_official | 390:35c2c1cf29cd | 129 | volatile uint16_t YCTWB_F2; /* YCTWB_F2 */ |
| mbed_official | 390:35c2c1cf29cd | 130 | volatile uint16_t YCTWB_F3; /* YCTWB_F3 */ |
| mbed_official | 390:35c2c1cf29cd | 131 | volatile uint16_t YCTWB_F4; /* YCTWB_F4 */ |
| mbed_official | 390:35c2c1cf29cd | 132 | volatile uint16_t YCTWB_F5; /* YCTWB_F5 */ |
| mbed_official | 390:35c2c1cf29cd | 133 | volatile uint16_t YCTWB_F6; /* YCTWB_F6 */ |
| mbed_official | 390:35c2c1cf29cd | 134 | volatile uint16_t YCTWB_F7; /* YCTWB_F7 */ |
| mbed_official | 390:35c2c1cf29cd | 135 | volatile uint16_t YCTWB_F8; /* YCTWB_F8 */ |
| mbed_official | 390:35c2c1cf29cd | 136 | #define DVDEC_YCTNA_Fn_COUNT 9 |
| mbed_official | 390:35c2c1cf29cd | 137 | volatile uint16_t YCTNA_F0; /* YCTNA_F0 */ |
| mbed_official | 390:35c2c1cf29cd | 138 | volatile uint16_t YCTNA_F1; /* YCTNA_F1 */ |
| mbed_official | 390:35c2c1cf29cd | 139 | volatile uint16_t YCTNA_F2; /* YCTNA_F2 */ |
| mbed_official | 390:35c2c1cf29cd | 140 | volatile uint16_t YCTNA_F3; /* YCTNA_F3 */ |
| mbed_official | 390:35c2c1cf29cd | 141 | volatile uint16_t YCTNA_F4; /* YCTNA_F4 */ |
| mbed_official | 390:35c2c1cf29cd | 142 | volatile uint16_t YCTNA_F5; /* YCTNA_F5 */ |
| mbed_official | 390:35c2c1cf29cd | 143 | volatile uint16_t YCTNA_F6; /* YCTNA_F6 */ |
| mbed_official | 390:35c2c1cf29cd | 144 | volatile uint16_t YCTNA_F7; /* YCTNA_F7 */ |
| mbed_official | 390:35c2c1cf29cd | 145 | volatile uint16_t YCTNA_F8; /* YCTNA_F8 */ |
| mbed_official | 390:35c2c1cf29cd | 146 | #define DVDEC_YCTNB_Fn_COUNT 9 |
| mbed_official | 390:35c2c1cf29cd | 147 | volatile uint16_t YCTNB_F0; /* YCTNB_F0 */ |
| mbed_official | 390:35c2c1cf29cd | 148 | volatile uint16_t YCTNB_F1; /* YCTNB_F1 */ |
| mbed_official | 390:35c2c1cf29cd | 149 | volatile uint16_t YCTNB_F2; /* YCTNB_F2 */ |
| mbed_official | 390:35c2c1cf29cd | 150 | volatile uint16_t YCTNB_F3; /* YCTNB_F3 */ |
| mbed_official | 390:35c2c1cf29cd | 151 | volatile uint16_t YCTNB_F4; /* YCTNB_F4 */ |
| mbed_official | 390:35c2c1cf29cd | 152 | volatile uint16_t YCTNB_F5; /* YCTNB_F5 */ |
| mbed_official | 390:35c2c1cf29cd | 153 | volatile uint16_t YCTNB_F6; /* YCTNB_F6 */ |
| mbed_official | 390:35c2c1cf29cd | 154 | volatile uint16_t YCTNB_F7; /* YCTNB_F7 */ |
| mbed_official | 390:35c2c1cf29cd | 155 | volatile uint16_t YCTNB_F8; /* YCTNB_F8 */ |
| mbed_official | 390:35c2c1cf29cd | 156 | volatile uint8_t dummy10[38]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 157 | volatile uint16_t YGAINCR; /* YGAINCR */ |
| mbed_official | 390:35c2c1cf29cd | 158 | volatile uint16_t CBGAINCR; /* CBGAINCR */ |
| mbed_official | 390:35c2c1cf29cd | 159 | volatile uint16_t CRGAINCR; /* CRGAINCR */ |
| mbed_official | 390:35c2c1cf29cd | 160 | volatile uint8_t dummy11[122]; /* */ |
| mbed_official | 390:35c2c1cf29cd | 161 | volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */ |
| mbed_official | 390:35c2c1cf29cd | 162 | volatile uint16_t PGACR; /* PGACR */ |
| mbed_official | 390:35c2c1cf29cd | 163 | volatile uint16_t ADCCR2; /* ADCCR2 */ |
| mbed_official | 390:35c2c1cf29cd | 164 | }; |
| mbed_official | 390:35c2c1cf29cd | 165 | |
| mbed_official | 390:35c2c1cf29cd | 166 | |
| mbed_official | 390:35c2c1cf29cd | 167 | #define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */ |
| mbed_official | 390:35c2c1cf29cd | 168 | #define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */ |
| mbed_official | 390:35c2c1cf29cd | 169 | |
| mbed_official | 390:35c2c1cf29cd | 170 | |
| mbed_official | 390:35c2c1cf29cd | 171 | /* Start of channnel array defines of DVDEC */ |
| mbed_official | 390:35c2c1cf29cd | 172 | |
| mbed_official | 390:35c2c1cf29cd | 173 | /* Channnel array defines of DVDEC */ |
| mbed_official | 390:35c2c1cf29cd | 174 | /*(Sample) value = DVDEC[ channel ]->ADCCR1; */ |
| mbed_official | 390:35c2c1cf29cd | 175 | #define DVDEC_COUNT 2 |
| mbed_official | 390:35c2c1cf29cd | 176 | #define DVDEC_ADDRESS_LIST \ |
| mbed_official | 390:35c2c1cf29cd | 177 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
| mbed_official | 390:35c2c1cf29cd | 178 | &DVDEC0, &DVDEC1 \ |
| mbed_official | 390:35c2c1cf29cd | 179 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
| mbed_official | 390:35c2c1cf29cd | 180 | |
| mbed_official | 390:35c2c1cf29cd | 181 | /* End of channnel array defines of DVDEC */ |
| mbed_official | 390:35c2c1cf29cd | 182 | |
| mbed_official | 390:35c2c1cf29cd | 183 | |
| mbed_official | 390:35c2c1cf29cd | 184 | #define ADCCR1_1 DVDEC1.ADCCR1 |
| mbed_official | 390:35c2c1cf29cd | 185 | #define TGCR1_1 DVDEC1.TGCR1 |
| mbed_official | 390:35c2c1cf29cd | 186 | #define TGCR2_1 DVDEC1.TGCR2 |
| mbed_official | 390:35c2c1cf29cd | 187 | #define TGCR3_1 DVDEC1.TGCR3 |
| mbed_official | 390:35c2c1cf29cd | 188 | #define SYNSCR1_1 DVDEC1.SYNSCR1 |
| mbed_official | 390:35c2c1cf29cd | 189 | #define SYNSCR2_1 DVDEC1.SYNSCR2 |
| mbed_official | 390:35c2c1cf29cd | 190 | #define SYNSCR3_1 DVDEC1.SYNSCR3 |
| mbed_official | 390:35c2c1cf29cd | 191 | #define SYNSCR4_1 DVDEC1.SYNSCR4 |
| mbed_official | 390:35c2c1cf29cd | 192 | #define SYNSCR5_1 DVDEC1.SYNSCR5 |
| mbed_official | 390:35c2c1cf29cd | 193 | #define HAFCCR1_1 DVDEC1.HAFCCR1 |
| mbed_official | 390:35c2c1cf29cd | 194 | #define HAFCCR2_1 DVDEC1.HAFCCR2 |
| mbed_official | 390:35c2c1cf29cd | 195 | #define HAFCCR3_1 DVDEC1.HAFCCR3 |
| mbed_official | 390:35c2c1cf29cd | 196 | #define VCDWCR1_1 DVDEC1.VCDWCR1 |
| mbed_official | 390:35c2c1cf29cd | 197 | #define DCPCR1_1 DVDEC1.DCPCR1 |
| mbed_official | 390:35c2c1cf29cd | 198 | #define DCPCR2_1 DVDEC1.DCPCR2 |
| mbed_official | 390:35c2c1cf29cd | 199 | #define DCPCR3_1 DVDEC1.DCPCR3 |
| mbed_official | 390:35c2c1cf29cd | 200 | #define DCPCR4_1 DVDEC1.DCPCR4 |
| mbed_official | 390:35c2c1cf29cd | 201 | #define DCPCR5_1 DVDEC1.DCPCR5 |
| mbed_official | 390:35c2c1cf29cd | 202 | #define DCPCR6_1 DVDEC1.DCPCR6 |
| mbed_official | 390:35c2c1cf29cd | 203 | #define DCPCR7_1 DVDEC1.DCPCR7 |
| mbed_official | 390:35c2c1cf29cd | 204 | #define DCPCR8_1 DVDEC1.DCPCR8 |
| mbed_official | 390:35c2c1cf29cd | 205 | #define NSDCR_1 DVDEC1.NSDCR |
| mbed_official | 390:35c2c1cf29cd | 206 | #define BTLCR_1 DVDEC1.BTLCR |
| mbed_official | 390:35c2c1cf29cd | 207 | #define BTGPCR_1 DVDEC1.BTGPCR |
| mbed_official | 390:35c2c1cf29cd | 208 | #define ACCCR1_1 DVDEC1.ACCCR1 |
| mbed_official | 390:35c2c1cf29cd | 209 | #define ACCCR2_1 DVDEC1.ACCCR2 |
| mbed_official | 390:35c2c1cf29cd | 210 | #define ACCCR3_1 DVDEC1.ACCCR3 |
| mbed_official | 390:35c2c1cf29cd | 211 | #define TINTCR_1 DVDEC1.TINTCR |
| mbed_official | 390:35c2c1cf29cd | 212 | #define YCDCR_1 DVDEC1.YCDCR |
| mbed_official | 390:35c2c1cf29cd | 213 | #define AGCCR1_1 DVDEC1.AGCCR1 |
| mbed_official | 390:35c2c1cf29cd | 214 | #define AGCCR2_1 DVDEC1.AGCCR2 |
| mbed_official | 390:35c2c1cf29cd | 215 | #define PKLIMITCR_1 DVDEC1.PKLIMITCR |
| mbed_official | 390:35c2c1cf29cd | 216 | #define RGORCR1_1 DVDEC1.RGORCR1 |
| mbed_official | 390:35c2c1cf29cd | 217 | #define RGORCR2_1 DVDEC1.RGORCR2 |
| mbed_official | 390:35c2c1cf29cd | 218 | #define RGORCR3_1 DVDEC1.RGORCR3 |
| mbed_official | 390:35c2c1cf29cd | 219 | #define RGORCR4_1 DVDEC1.RGORCR4 |
| mbed_official | 390:35c2c1cf29cd | 220 | #define RGORCR5_1 DVDEC1.RGORCR5 |
| mbed_official | 390:35c2c1cf29cd | 221 | #define RGORCR6_1 DVDEC1.RGORCR6 |
| mbed_official | 390:35c2c1cf29cd | 222 | #define RGORCR7_1 DVDEC1.RGORCR7 |
| mbed_official | 390:35c2c1cf29cd | 223 | #define AFCPFCR_1 DVDEC1.AFCPFCR |
| mbed_official | 390:35c2c1cf29cd | 224 | #define RUPDCR_1 DVDEC1.RUPDCR |
| mbed_official | 390:35c2c1cf29cd | 225 | #define VSYNCSR_1 DVDEC1.VSYNCSR |
| mbed_official | 390:35c2c1cf29cd | 226 | #define HSYNCSR_1 DVDEC1.HSYNCSR |
| mbed_official | 390:35c2c1cf29cd | 227 | #define DCPSR1_1 DVDEC1.DCPSR1 |
| mbed_official | 390:35c2c1cf29cd | 228 | #define DCPSR2_1 DVDEC1.DCPSR2 |
| mbed_official | 390:35c2c1cf29cd | 229 | #define NSDSR_1 DVDEC1.NSDSR |
| mbed_official | 390:35c2c1cf29cd | 230 | #define CROMASR1_1 DVDEC1.CROMASR1 |
| mbed_official | 390:35c2c1cf29cd | 231 | #define CROMASR2_1 DVDEC1.CROMASR2 |
| mbed_official | 390:35c2c1cf29cd | 232 | #define SYNCSSR_1 DVDEC1.SYNCSSR |
| mbed_official | 390:35c2c1cf29cd | 233 | #define AGCCSR1_1 DVDEC1.AGCCSR1 |
| mbed_official | 390:35c2c1cf29cd | 234 | #define AGCCSR2_1 DVDEC1.AGCCSR2 |
| mbed_official | 390:35c2c1cf29cd | 235 | #define YCSCR3_1 DVDEC1.YCSCR3 |
| mbed_official | 390:35c2c1cf29cd | 236 | #define YCSCR4_1 DVDEC1.YCSCR4 |
| mbed_official | 390:35c2c1cf29cd | 237 | #define YCSCR5_1 DVDEC1.YCSCR5 |
| mbed_official | 390:35c2c1cf29cd | 238 | #define YCSCR6_1 DVDEC1.YCSCR6 |
| mbed_official | 390:35c2c1cf29cd | 239 | #define YCSCR7_1 DVDEC1.YCSCR7 |
| mbed_official | 390:35c2c1cf29cd | 240 | #define YCSCR8_1 DVDEC1.YCSCR8 |
| mbed_official | 390:35c2c1cf29cd | 241 | #define YCSCR9_1 DVDEC1.YCSCR9 |
| mbed_official | 390:35c2c1cf29cd | 242 | #define YCSCR11_1 DVDEC1.YCSCR11 |
| mbed_official | 390:35c2c1cf29cd | 243 | #define YCSCR12_1 DVDEC1.YCSCR12 |
| mbed_official | 390:35c2c1cf29cd | 244 | #define DCPCR9_1 DVDEC1.DCPCR9 |
| mbed_official | 390:35c2c1cf29cd | 245 | #define YCTWA_F0_1 DVDEC1.YCTWA_F0 |
| mbed_official | 390:35c2c1cf29cd | 246 | #define YCTWA_F1_1 DVDEC1.YCTWA_F1 |
| mbed_official | 390:35c2c1cf29cd | 247 | #define YCTWA_F2_1 DVDEC1.YCTWA_F2 |
| mbed_official | 390:35c2c1cf29cd | 248 | #define YCTWA_F3_1 DVDEC1.YCTWA_F3 |
| mbed_official | 390:35c2c1cf29cd | 249 | #define YCTWA_F4_1 DVDEC1.YCTWA_F4 |
| mbed_official | 390:35c2c1cf29cd | 250 | #define YCTWA_F5_1 DVDEC1.YCTWA_F5 |
| mbed_official | 390:35c2c1cf29cd | 251 | #define YCTWA_F6_1 DVDEC1.YCTWA_F6 |
| mbed_official | 390:35c2c1cf29cd | 252 | #define YCTWA_F7_1 DVDEC1.YCTWA_F7 |
| mbed_official | 390:35c2c1cf29cd | 253 | #define YCTWA_F8_1 DVDEC1.YCTWA_F8 |
| mbed_official | 390:35c2c1cf29cd | 254 | #define YCTWB_F0_1 DVDEC1.YCTWB_F0 |
| mbed_official | 390:35c2c1cf29cd | 255 | #define YCTWB_F1_1 DVDEC1.YCTWB_F1 |
| mbed_official | 390:35c2c1cf29cd | 256 | #define YCTWB_F2_1 DVDEC1.YCTWB_F2 |
| mbed_official | 390:35c2c1cf29cd | 257 | #define YCTWB_F3_1 DVDEC1.YCTWB_F3 |
| mbed_official | 390:35c2c1cf29cd | 258 | #define YCTWB_F4_1 DVDEC1.YCTWB_F4 |
| mbed_official | 390:35c2c1cf29cd | 259 | #define YCTWB_F5_1 DVDEC1.YCTWB_F5 |
| mbed_official | 390:35c2c1cf29cd | 260 | #define YCTWB_F6_1 DVDEC1.YCTWB_F6 |
| mbed_official | 390:35c2c1cf29cd | 261 | #define YCTWB_F7_1 DVDEC1.YCTWB_F7 |
| mbed_official | 390:35c2c1cf29cd | 262 | #define YCTWB_F8_1 DVDEC1.YCTWB_F8 |
| mbed_official | 390:35c2c1cf29cd | 263 | #define YCTNA_F0_1 DVDEC1.YCTNA_F0 |
| mbed_official | 390:35c2c1cf29cd | 264 | #define YCTNA_F1_1 DVDEC1.YCTNA_F1 |
| mbed_official | 390:35c2c1cf29cd | 265 | #define YCTNA_F2_1 DVDEC1.YCTNA_F2 |
| mbed_official | 390:35c2c1cf29cd | 266 | #define YCTNA_F3_1 DVDEC1.YCTNA_F3 |
| mbed_official | 390:35c2c1cf29cd | 267 | #define YCTNA_F4_1 DVDEC1.YCTNA_F4 |
| mbed_official | 390:35c2c1cf29cd | 268 | #define YCTNA_F5_1 DVDEC1.YCTNA_F5 |
| mbed_official | 390:35c2c1cf29cd | 269 | #define YCTNA_F6_1 DVDEC1.YCTNA_F6 |
| mbed_official | 390:35c2c1cf29cd | 270 | #define YCTNA_F7_1 DVDEC1.YCTNA_F7 |
| mbed_official | 390:35c2c1cf29cd | 271 | #define YCTNA_F8_1 DVDEC1.YCTNA_F8 |
| mbed_official | 390:35c2c1cf29cd | 272 | #define YCTNB_F0_1 DVDEC1.YCTNB_F0 |
| mbed_official | 390:35c2c1cf29cd | 273 | #define YCTNB_F1_1 DVDEC1.YCTNB_F1 |
| mbed_official | 390:35c2c1cf29cd | 274 | #define YCTNB_F2_1 DVDEC1.YCTNB_F2 |
| mbed_official | 390:35c2c1cf29cd | 275 | #define YCTNB_F3_1 DVDEC1.YCTNB_F3 |
| mbed_official | 390:35c2c1cf29cd | 276 | #define YCTNB_F4_1 DVDEC1.YCTNB_F4 |
| mbed_official | 390:35c2c1cf29cd | 277 | #define YCTNB_F5_1 DVDEC1.YCTNB_F5 |
| mbed_official | 390:35c2c1cf29cd | 278 | #define YCTNB_F6_1 DVDEC1.YCTNB_F6 |
| mbed_official | 390:35c2c1cf29cd | 279 | #define YCTNB_F7_1 DVDEC1.YCTNB_F7 |
| mbed_official | 390:35c2c1cf29cd | 280 | #define YCTNB_F8_1 DVDEC1.YCTNB_F8 |
| mbed_official | 390:35c2c1cf29cd | 281 | #define YGAINCR_1 DVDEC1.YGAINCR |
| mbed_official | 390:35c2c1cf29cd | 282 | #define CBGAINCR_1 DVDEC1.CBGAINCR |
| mbed_official | 390:35c2c1cf29cd | 283 | #define CRGAINCR_1 DVDEC1.CRGAINCR |
| mbed_official | 390:35c2c1cf29cd | 284 | #define PGA_UPDATE_1 DVDEC1.PGA_UPDATE |
| mbed_official | 390:35c2c1cf29cd | 285 | #define PGACR_1 DVDEC1.PGACR |
| mbed_official | 390:35c2c1cf29cd | 286 | #define ADCCR2_1 DVDEC1.ADCCR2 |
| mbed_official | 390:35c2c1cf29cd | 287 | #define ADCCR1_0 DVDEC0.ADCCR1 |
| mbed_official | 390:35c2c1cf29cd | 288 | #define TGCR1_0 DVDEC0.TGCR1 |
| mbed_official | 390:35c2c1cf29cd | 289 | #define TGCR2_0 DVDEC0.TGCR2 |
| mbed_official | 390:35c2c1cf29cd | 290 | #define TGCR3_0 DVDEC0.TGCR3 |
| mbed_official | 390:35c2c1cf29cd | 291 | #define SYNSCR1_0 DVDEC0.SYNSCR1 |
| mbed_official | 390:35c2c1cf29cd | 292 | #define SYNSCR2_0 DVDEC0.SYNSCR2 |
| mbed_official | 390:35c2c1cf29cd | 293 | #define SYNSCR3_0 DVDEC0.SYNSCR3 |
| mbed_official | 390:35c2c1cf29cd | 294 | #define SYNSCR4_0 DVDEC0.SYNSCR4 |
| mbed_official | 390:35c2c1cf29cd | 295 | #define SYNSCR5_0 DVDEC0.SYNSCR5 |
| mbed_official | 390:35c2c1cf29cd | 296 | #define HAFCCR1_0 DVDEC0.HAFCCR1 |
| mbed_official | 390:35c2c1cf29cd | 297 | #define HAFCCR2_0 DVDEC0.HAFCCR2 |
| mbed_official | 390:35c2c1cf29cd | 298 | #define HAFCCR3_0 DVDEC0.HAFCCR3 |
| mbed_official | 390:35c2c1cf29cd | 299 | #define VCDWCR1_0 DVDEC0.VCDWCR1 |
| mbed_official | 390:35c2c1cf29cd | 300 | #define DCPCR1_0 DVDEC0.DCPCR1 |
| mbed_official | 390:35c2c1cf29cd | 301 | #define DCPCR2_0 DVDEC0.DCPCR2 |
| mbed_official | 390:35c2c1cf29cd | 302 | #define DCPCR3_0 DVDEC0.DCPCR3 |
| mbed_official | 390:35c2c1cf29cd | 303 | #define DCPCR4_0 DVDEC0.DCPCR4 |
| mbed_official | 390:35c2c1cf29cd | 304 | #define DCPCR5_0 DVDEC0.DCPCR5 |
| mbed_official | 390:35c2c1cf29cd | 305 | #define DCPCR6_0 DVDEC0.DCPCR6 |
| mbed_official | 390:35c2c1cf29cd | 306 | #define DCPCR7_0 DVDEC0.DCPCR7 |
| mbed_official | 390:35c2c1cf29cd | 307 | #define DCPCR8_0 DVDEC0.DCPCR8 |
| mbed_official | 390:35c2c1cf29cd | 308 | #define NSDCR_0 DVDEC0.NSDCR |
| mbed_official | 390:35c2c1cf29cd | 309 | #define BTLCR_0 DVDEC0.BTLCR |
| mbed_official | 390:35c2c1cf29cd | 310 | #define BTGPCR_0 DVDEC0.BTGPCR |
| mbed_official | 390:35c2c1cf29cd | 311 | #define ACCCR1_0 DVDEC0.ACCCR1 |
| mbed_official | 390:35c2c1cf29cd | 312 | #define ACCCR2_0 DVDEC0.ACCCR2 |
| mbed_official | 390:35c2c1cf29cd | 313 | #define ACCCR3_0 DVDEC0.ACCCR3 |
| mbed_official | 390:35c2c1cf29cd | 314 | #define TINTCR_0 DVDEC0.TINTCR |
| mbed_official | 390:35c2c1cf29cd | 315 | #define YCDCR_0 DVDEC0.YCDCR |
| mbed_official | 390:35c2c1cf29cd | 316 | #define AGCCR1_0 DVDEC0.AGCCR1 |
| mbed_official | 390:35c2c1cf29cd | 317 | #define AGCCR2_0 DVDEC0.AGCCR2 |
| mbed_official | 390:35c2c1cf29cd | 318 | #define PKLIMITCR_0 DVDEC0.PKLIMITCR |
| mbed_official | 390:35c2c1cf29cd | 319 | #define RGORCR1_0 DVDEC0.RGORCR1 |
| mbed_official | 390:35c2c1cf29cd | 320 | #define RGORCR2_0 DVDEC0.RGORCR2 |
| mbed_official | 390:35c2c1cf29cd | 321 | #define RGORCR3_0 DVDEC0.RGORCR3 |
| mbed_official | 390:35c2c1cf29cd | 322 | #define RGORCR4_0 DVDEC0.RGORCR4 |
| mbed_official | 390:35c2c1cf29cd | 323 | #define RGORCR5_0 DVDEC0.RGORCR5 |
| mbed_official | 390:35c2c1cf29cd | 324 | #define RGORCR6_0 DVDEC0.RGORCR6 |
| mbed_official | 390:35c2c1cf29cd | 325 | #define RGORCR7_0 DVDEC0.RGORCR7 |
| mbed_official | 390:35c2c1cf29cd | 326 | #define AFCPFCR_0 DVDEC0.AFCPFCR |
| mbed_official | 390:35c2c1cf29cd | 327 | #define RUPDCR_0 DVDEC0.RUPDCR |
| mbed_official | 390:35c2c1cf29cd | 328 | #define VSYNCSR_0 DVDEC0.VSYNCSR |
| mbed_official | 390:35c2c1cf29cd | 329 | #define HSYNCSR_0 DVDEC0.HSYNCSR |
| mbed_official | 390:35c2c1cf29cd | 330 | #define DCPSR1_0 DVDEC0.DCPSR1 |
| mbed_official | 390:35c2c1cf29cd | 331 | #define DCPSR2_0 DVDEC0.DCPSR2 |
| mbed_official | 390:35c2c1cf29cd | 332 | #define NSDSR_0 DVDEC0.NSDSR |
| mbed_official | 390:35c2c1cf29cd | 333 | #define CROMASR1_0 DVDEC0.CROMASR1 |
| mbed_official | 390:35c2c1cf29cd | 334 | #define CROMASR2_0 DVDEC0.CROMASR2 |
| mbed_official | 390:35c2c1cf29cd | 335 | #define SYNCSSR_0 DVDEC0.SYNCSSR |
| mbed_official | 390:35c2c1cf29cd | 336 | #define AGCCSR1_0 DVDEC0.AGCCSR1 |
| mbed_official | 390:35c2c1cf29cd | 337 | #define AGCCSR2_0 DVDEC0.AGCCSR2 |
| mbed_official | 390:35c2c1cf29cd | 338 | #define YCSCR3_0 DVDEC0.YCSCR3 |
| mbed_official | 390:35c2c1cf29cd | 339 | #define YCSCR4_0 DVDEC0.YCSCR4 |
| mbed_official | 390:35c2c1cf29cd | 340 | #define YCSCR5_0 DVDEC0.YCSCR5 |
| mbed_official | 390:35c2c1cf29cd | 341 | #define YCSCR6_0 DVDEC0.YCSCR6 |
| mbed_official | 390:35c2c1cf29cd | 342 | #define YCSCR7_0 DVDEC0.YCSCR7 |
| mbed_official | 390:35c2c1cf29cd | 343 | #define YCSCR8_0 DVDEC0.YCSCR8 |
| mbed_official | 390:35c2c1cf29cd | 344 | #define YCSCR9_0 DVDEC0.YCSCR9 |
| mbed_official | 390:35c2c1cf29cd | 345 | #define YCSCR11_0 DVDEC0.YCSCR11 |
| mbed_official | 390:35c2c1cf29cd | 346 | #define YCSCR12_0 DVDEC0.YCSCR12 |
| mbed_official | 390:35c2c1cf29cd | 347 | #define DCPCR9_0 DVDEC0.DCPCR9 |
| mbed_official | 390:35c2c1cf29cd | 348 | #define YCTWA_F0_0 DVDEC0.YCTWA_F0 |
| mbed_official | 390:35c2c1cf29cd | 349 | #define YCTWA_F1_0 DVDEC0.YCTWA_F1 |
| mbed_official | 390:35c2c1cf29cd | 350 | #define YCTWA_F2_0 DVDEC0.YCTWA_F2 |
| mbed_official | 390:35c2c1cf29cd | 351 | #define YCTWA_F3_0 DVDEC0.YCTWA_F3 |
| mbed_official | 390:35c2c1cf29cd | 352 | #define YCTWA_F4_0 DVDEC0.YCTWA_F4 |
| mbed_official | 390:35c2c1cf29cd | 353 | #define YCTWA_F5_0 DVDEC0.YCTWA_F5 |
| mbed_official | 390:35c2c1cf29cd | 354 | #define YCTWA_F6_0 DVDEC0.YCTWA_F6 |
| mbed_official | 390:35c2c1cf29cd | 355 | #define YCTWA_F7_0 DVDEC0.YCTWA_F7 |
| mbed_official | 390:35c2c1cf29cd | 356 | #define YCTWA_F8_0 DVDEC0.YCTWA_F8 |
| mbed_official | 390:35c2c1cf29cd | 357 | #define YCTWB_F0_0 DVDEC0.YCTWB_F0 |
| mbed_official | 390:35c2c1cf29cd | 358 | #define YCTWB_F1_0 DVDEC0.YCTWB_F1 |
| mbed_official | 390:35c2c1cf29cd | 359 | #define YCTWB_F2_0 DVDEC0.YCTWB_F2 |
| mbed_official | 390:35c2c1cf29cd | 360 | #define YCTWB_F3_0 DVDEC0.YCTWB_F3 |
| mbed_official | 390:35c2c1cf29cd | 361 | #define YCTWB_F4_0 DVDEC0.YCTWB_F4 |
| mbed_official | 390:35c2c1cf29cd | 362 | #define YCTWB_F5_0 DVDEC0.YCTWB_F5 |
| mbed_official | 390:35c2c1cf29cd | 363 | #define YCTWB_F6_0 DVDEC0.YCTWB_F6 |
| mbed_official | 390:35c2c1cf29cd | 364 | #define YCTWB_F7_0 DVDEC0.YCTWB_F7 |
| mbed_official | 390:35c2c1cf29cd | 365 | #define YCTWB_F8_0 DVDEC0.YCTWB_F8 |
| mbed_official | 390:35c2c1cf29cd | 366 | #define YCTNA_F0_0 DVDEC0.YCTNA_F0 |
| mbed_official | 390:35c2c1cf29cd | 367 | #define YCTNA_F1_0 DVDEC0.YCTNA_F1 |
| mbed_official | 390:35c2c1cf29cd | 368 | #define YCTNA_F2_0 DVDEC0.YCTNA_F2 |
| mbed_official | 390:35c2c1cf29cd | 369 | #define YCTNA_F3_0 DVDEC0.YCTNA_F3 |
| mbed_official | 390:35c2c1cf29cd | 370 | #define YCTNA_F4_0 DVDEC0.YCTNA_F4 |
| mbed_official | 390:35c2c1cf29cd | 371 | #define YCTNA_F5_0 DVDEC0.YCTNA_F5 |
| mbed_official | 390:35c2c1cf29cd | 372 | #define YCTNA_F6_0 DVDEC0.YCTNA_F6 |
| mbed_official | 390:35c2c1cf29cd | 373 | #define YCTNA_F7_0 DVDEC0.YCTNA_F7 |
| mbed_official | 390:35c2c1cf29cd | 374 | #define YCTNA_F8_0 DVDEC0.YCTNA_F8 |
| mbed_official | 390:35c2c1cf29cd | 375 | #define YCTNB_F0_0 DVDEC0.YCTNB_F0 |
| mbed_official | 390:35c2c1cf29cd | 376 | #define YCTNB_F1_0 DVDEC0.YCTNB_F1 |
| mbed_official | 390:35c2c1cf29cd | 377 | #define YCTNB_F2_0 DVDEC0.YCTNB_F2 |
| mbed_official | 390:35c2c1cf29cd | 378 | #define YCTNB_F3_0 DVDEC0.YCTNB_F3 |
| mbed_official | 390:35c2c1cf29cd | 379 | #define YCTNB_F4_0 DVDEC0.YCTNB_F4 |
| mbed_official | 390:35c2c1cf29cd | 380 | #define YCTNB_F5_0 DVDEC0.YCTNB_F5 |
| mbed_official | 390:35c2c1cf29cd | 381 | #define YCTNB_F6_0 DVDEC0.YCTNB_F6 |
| mbed_official | 390:35c2c1cf29cd | 382 | #define YCTNB_F7_0 DVDEC0.YCTNB_F7 |
| mbed_official | 390:35c2c1cf29cd | 383 | #define YCTNB_F8_0 DVDEC0.YCTNB_F8 |
| mbed_official | 390:35c2c1cf29cd | 384 | #define YGAINCR_0 DVDEC0.YGAINCR |
| mbed_official | 390:35c2c1cf29cd | 385 | #define CBGAINCR_0 DVDEC0.CBGAINCR |
| mbed_official | 390:35c2c1cf29cd | 386 | #define CRGAINCR_0 DVDEC0.CRGAINCR |
| mbed_official | 390:35c2c1cf29cd | 387 | #define PGA_UPDATE_0 DVDEC0.PGA_UPDATE |
| mbed_official | 390:35c2c1cf29cd | 388 | #define PGACR_0 DVDEC0.PGACR |
| mbed_official | 390:35c2c1cf29cd | 389 | #define ADCCR2_0 DVDEC0.ADCCR2 |
| mbed_official | 390:35c2c1cf29cd | 390 | /* <-SEC M1.10.1 */ |
| mbed_official | 390:35c2c1cf29cd | 391 | #endif |
