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targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/TOOLCHAIN_GCC_ARM/startup_MKL26Z4.S
- Committer:
- mbed_official
- Date:
- 2015-07-08
- Revision:
- 585:a1ed5b41f74f
File content as of revision 585:a1ed5b41f74f:
/* ---------------------------------------------------------------------------------------*/ /* @file: startup_MKL26Z4.s */ /* @purpose: CMSIS Cortex-M0P Core Device Startup File */ /* MKL26Z4 */ /* @version: 1.7 */ /* @date: 2015-2-18 */ /* @build: b150218 */ /* ---------------------------------------------------------------------------------------*/ /* */ /* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */ /* All rights reserved. */ /* */ /* Redistribution and use in source and binary forms, with or without modification, */ /* are permitted provided that the following conditions are met: */ /* */ /* o Redistributions of source code must retain the above copyright notice, this list */ /* of conditions and the following disclaimer. */ /* */ /* o Redistributions in binary form must reproduce the above copyright notice, this */ /* list of conditions and the following disclaimer in the documentation and/or */ /* other materials provided with the distribution. */ /* */ /* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ /* contributors may be used to endorse or promote products derived from this */ /* software without specific prior written permission. */ /* */ /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ /* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ /* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ /* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ /* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ /* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ /* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ /* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /*****************************************************************************/ /* Version: GCC for ARM Embedded Processors */ /*****************************************************************************/ .syntax unified .arch armv6-m .section .isr_vector, "a" .align 2 .globl __isr_vector __isr_vector: .long __StackTop /* Top of Stack */ .long Reset_Handler /* Reset Handler */ .long NMI_Handler /* NMI Handler*/ .long HardFault_Handler /* Hard Fault Handler*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long SVC_Handler /* SVCall Handler*/ .long 0 /* Reserved*/ .long 0 /* Reserved*/ .long PendSV_Handler /* PendSV Handler*/ .long SysTick_Handler /* SysTick Handler*/ /* External Interrupts*/ .long DMA0_IRQHandler /* DMA channel 0 transfer complete and error interrupt*/ .long DMA1_IRQHandler /* DMA channel 1 transfer complete and error interrupt*/ .long DMA2_IRQHandler /* DMA channel 2 transfer complete and error interrupt*/ .long DMA3_IRQHandler /* DMA channel 3 transfer complete and error interrupt*/ .long Reserved20_IRQHandler /* Reserved interrupt*/ .long FTFA_IRQHandler /* FTFA command complete and read collision*/ .long LVD_LVW_IRQHandler /* Low-voltage detect, low-voltage warning*/ .long LLWU_IRQHandler /* Low Leakage Wakeup*/ .long I2C0_IRQHandler /* I2C0 interrupt*/ .long I2C1_IRQHandler /* I2C1 interrupt*/ .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/ .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/ .long UART0_IRQHandler /* UART0 status and error*/ .long UART1_IRQHandler /* UART1 status and error*/ .long UART2_IRQHandler /* UART2 status and error*/ .long ADC0_IRQHandler /* ADC0 interrupt*/ .long CMP0_IRQHandler /* CMP0 interrupt*/ .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/ .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/ .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/ .long RTC_IRQHandler /* RTC alarm interrupt*/ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/ .long PIT_IRQHandler /* PIT single interrupt vector for all channels*/ .long I2S0_IRQHandler /* I2S0 Single interrupt vector for all sources*/ .long USB0_IRQHandler /* USB0 OTG*/ .long DAC0_IRQHandler /* DAC0 interrupt*/ .long TSI0_IRQHandler /* TSI0 interrupt*/ .long MCG_IRQHandler /* MCG interrupt*/ .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/ .long Reserved45_IRQHandler /* Reserved interrupt*/ .long PORTA_IRQHandler /* PORTA pin detect*/ .long PORTC_PORTD_IRQHandler /* Single interrupt vector for PORTC and PORTD pin detect*/ .size __isr_vector, . - __isr_vector /* Flash Configuration */ .section .FlashConfig, "a" .long 0xFFFFFFFF .long 0xFFFFFFFF .long 0xFFFFFFFF .long 0xFFFFFFFE .text .thumb /* Reset Handler */ .thumb_func .align 2 .globl Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: cpsid i /* Mask interrupts */ #ifndef __NO_SYSTEM_INIT bl SystemInit #endif bl init_data_bss cpsie i /* Unmask interrupts */ #ifndef __START #define __START _start #endif #ifndef __ATOLLIC__ bl __START #else bl __libc_init_array bl main #endif .pool .size Reset_Handler, . - Reset_Handler .align 1 .thumb_func .weak DefaultISR .type DefaultISR, %function DefaultISR: ldr r0, =DefaultISR bx r0 .size DefaultISR, . - DefaultISR /* Macro to define default handlers. Default handler * will be weak symbol and just dead loops. They can be * overwritten by other handlers */ .macro def_irq_handler handler_name .weak \handler_name .set \handler_name, DefaultISR .endm /* Exception Handlers */ def_irq_handler NMI_Handler def_irq_handler HardFault_Handler def_irq_handler SVC_Handler def_irq_handler PendSV_Handler def_irq_handler SysTick_Handler def_irq_handler DMA0_IRQHandler def_irq_handler DMA1_IRQHandler def_irq_handler DMA2_IRQHandler def_irq_handler DMA3_IRQHandler def_irq_handler Reserved20_IRQHandler def_irq_handler FTFA_IRQHandler def_irq_handler LVD_LVW_IRQHandler def_irq_handler LLWU_IRQHandler def_irq_handler I2C0_IRQHandler def_irq_handler I2C1_IRQHandler def_irq_handler SPI0_IRQHandler def_irq_handler SPI1_IRQHandler def_irq_handler UART0_IRQHandler def_irq_handler UART1_IRQHandler def_irq_handler UART2_IRQHandler def_irq_handler ADC0_IRQHandler def_irq_handler CMP0_IRQHandler def_irq_handler TPM0_IRQHandler def_irq_handler TPM1_IRQHandler def_irq_handler TPM2_IRQHandler def_irq_handler RTC_IRQHandler def_irq_handler RTC_Seconds_IRQHandler def_irq_handler PIT_IRQHandler def_irq_handler I2S0_IRQHandler def_irq_handler USB0_IRQHandler def_irq_handler DAC0_IRQHandler def_irq_handler TSI0_IRQHandler def_irq_handler MCG_IRQHandler def_irq_handler LPTMR0_IRQHandler def_irq_handler Reserved45_IRQHandler def_irq_handler PORTA_IRQHandler def_irq_handler PORTC_PORTD_IRQHandler .end