mbed library sources
Dependents: Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more
Superseded
This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.
Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.
If you are looking for a stable and tested release, please import one of the official mbed library releases:
Import librarymbed
The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h
- Committer:
- mbed_official
- Date:
- 2015-07-01
- Revision:
- 579:53297373a894
- Parent:
- 363:12a245e5c745
File content as of revision 579:53297373a894:
/* ** ################################################################### ** Processors: MKL43Z256VLH4 ** MKL43Z128VLH4 ** MKL43Z64VLH4 ** MKL43Z256VMP4 ** MKL43Z128VMP4 ** MKL43Z64VMP4 ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM ** ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014 ** Version: rev. 1.5, 2014-09-05 ** Build: b140905 ** ** Abstract: ** CMSIS Peripheral Access Layer for MKL43Z4 ** ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. ** All rights reserved. ** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** o Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** o Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.freescale.com ** mail: support@freescale.com ** ** Revisions: ** - rev. 1.0 (2014-03-27) ** Initial version. ** - rev. 1.1 (2014-05-26) ** I2S registers TCR2/RCR2 and others were changed. ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR. ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS. ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS. ** Clock configuration for high range external oscillator has been added. ** RFSYS module access has been added. ** - rev. 1.2 (2014-07-10) ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE. ** UART0 - UART0 module renamed to UART2. ** I2S - removed MDR register. ** - rev. 1.3 (2014-08-21) ** UART2 - Removed ED register. ** UART2 - Removed MODEM register. ** UART2 - Removed IR register. ** UART2 - Removed PFIFO register. ** UART2 - Removed CFIFO register. ** UART2 - Removed SFIFO register. ** UART2 - Removed TWFIFO register. ** UART2 - Removed TCFIFO register. ** UART2 - Removed RWFIFO register. ** UART2 - Removed RCFIFO register. ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register. ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register. ** SIM - Removed bitfield DIEID in SDID register. ** - rev. 1.4 (2014-09-01) ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register. ** USB - USB0_CTL1 was renamed to USB0_CTL register. ** - rev. 1.5 (2014-09-05) ** USB - USBEN bitfield of the USB0_CTL renamed to USBENSOFEN. ** ** ################################################################### */ /*! * @file MKL43Z4.h * @version 1.5 * @date 2014-09-05 * @brief CMSIS Peripheral Access Layer for MKL43Z4 * * CMSIS Peripheral Access Layer for MKL43Z4 */ /* ---------------------------------------------------------------------------- -- MCU activation ---------------------------------------------------------------------------- */ /* Prevention from multiple including the same memory map */ #if !defined(MKL43Z4_H_) /* Check if memory map has not been already included */ #define MKL43Z4_H_ #define MCU_MKL43Z4 /* Check if another memory map has not been also included */ #if (defined(MCU_ACTIVE)) #error MKL43Z4 memory map: There is already included another memory map. Only one memory map can be included. #endif /* (defined(MCU_ACTIVE)) */ #define MCU_ACTIVE #include <stdint.h> /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0100u /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0005u /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Auxiliary constants */ NotAvail_IRQn = -128, /**< Not available device specific interrupt */ /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ /* Device specific interrupts */ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ Reserved20_IRQn = 4, /**< Reserved interrupt */ FTFA_IRQn = 5, /**< Command complete and read collision */ PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ LLWU_IRQn = 7, /**< Low leakage wakeup */ I2C0_IRQn = 8, /**< I2C0 interrupt */ I2C1_IRQn = 9, /**< I2C1 interrupt */ SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */ SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */ LPUART0_IRQn = 12, /**< LPUART0 status and error */ LPUART1_IRQn = 13, /**< LPUART1 status and error */ UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */ ADC0_IRQn = 15, /**< ADC0 interrupt */ CMP0_IRQn = 16, /**< CMP0 interrupt */ TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */ TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */ TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */ RTC_IRQn = 20, /**< RTC alarm */ RTC_Seconds_IRQn = 21, /**< RTC seconds */ PIT_IRQn = 22, /**< PIT interrupt */ I2S0_IRQn = 23, /**< I2S0 interrupt */ USB0_IRQn = 24, /**< USB0 interrupt */ DAC0_IRQn = 25, /**< DAC0 interrupt */ Reserved42_IRQn = 26, /**< Reserved interrupt */ Reserved43_IRQn = 27, /**< Reserved interrupt */ LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */ LCD_IRQn = 29, /**< LCD interrupt */ PORTA_IRQn = 30, /**< PORTA Pin detect */ PORTCD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Cortex M0 Core Configuration ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration * @{ */ #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #include "core_cm0plus.h" /* Core Peripheral Access Layer */ #include "system_MKL43Z4.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #pragma push #pragma anon_unions #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ uint8_t RESERVED_0[4]; __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ } ADC_Type, *ADC_MemMapPtr; /* ---------------------------------------------------------------------------- -- ADC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros * @{ */ /* ADC - Register accessors */ #define ADC_SC1_REG(base,index) ((base)->SC1[index]) #define ADC_CFG1_REG(base) ((base)->CFG1) #define ADC_CFG2_REG(base) ((base)->CFG2) #define ADC_R_REG(base,index) ((base)->R[index]) #define ADC_CV1_REG(base) ((base)->CV1) #define ADC_CV2_REG(base) ((base)->CV2) #define ADC_SC2_REG(base) ((base)->SC2) #define ADC_SC3_REG(base) ((base)->SC3) #define ADC_OFS_REG(base) ((base)->OFS) #define ADC_PG_REG(base) ((base)->PG) #define ADC_MG_REG(base) ((base)->MG) #define ADC_CLPD_REG(base) ((base)->CLPD) #define ADC_CLPS_REG(base) ((base)->CLPS) #define ADC_CLP4_REG(base) ((base)->CLP4) #define ADC_CLP3_REG(base) ((base)->CLP3) #define ADC_CLP2_REG(base) ((base)->CLP2) #define ADC_CLP1_REG(base) ((base)->CLP1) #define ADC_CLP0_REG(base) ((base)->CLP0) #define ADC_CLMD_REG(base) ((base)->CLMD) #define ADC_CLMS_REG(base) ((base)->CLMS) #define ADC_CLM4_REG(base) ((base)->CLM4) #define ADC_CLM3_REG(base) ((base)->CLM3) #define ADC_CLM2_REG(base) ((base)->CLM2) #define ADC_CLM1_REG(base) ((base)->CLM1) #define ADC_CLM0_REG(base) ((base)->CLM0) /*! * @} */ /* end of group ADC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /* SC1 Bit Fields */ #define ADC_SC1_ADCH_MASK 0x1Fu #define ADC_SC1_ADCH_SHIFT 0 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK) #define ADC_SC1_DIFF_MASK 0x20u #define ADC_SC1_DIFF_SHIFT 5 #define ADC_SC1_AIEN_MASK 0x40u #define ADC_SC1_AIEN_SHIFT 6 #define ADC_SC1_COCO_MASK 0x80u #define ADC_SC1_COCO_SHIFT 7 /* CFG1 Bit Fields */ #define ADC_CFG1_ADICLK_MASK 0x3u #define ADC_CFG1_ADICLK_SHIFT 0 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK) #define ADC_CFG1_MODE_MASK 0xCu #define ADC_CFG1_MODE_SHIFT 2 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK) #define ADC_CFG1_ADLSMP_MASK 0x10u #define ADC_CFG1_ADLSMP_SHIFT 4 #define ADC_CFG1_ADIV_MASK 0x60u #define ADC_CFG1_ADIV_SHIFT 5 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK) #define ADC_CFG1_ADLPC_MASK 0x80u #define ADC_CFG1_ADLPC_SHIFT 7 /* CFG2 Bit Fields */ #define ADC_CFG2_ADLSTS_MASK 0x3u #define ADC_CFG2_ADLSTS_SHIFT 0 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK) #define ADC_CFG2_ADHSC_MASK 0x4u #define ADC_CFG2_ADHSC_SHIFT 2 #define ADC_CFG2_ADACKEN_MASK 0x8u #define ADC_CFG2_ADACKEN_SHIFT 3 #define ADC_CFG2_MUXSEL_MASK 0x10u #define ADC_CFG2_MUXSEL_SHIFT 4 /* R Bit Fields */ #define ADC_R_D_MASK 0xFFFFu #define ADC_R_D_SHIFT 0 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK) /* CV1 Bit Fields */ #define ADC_CV1_CV_MASK 0xFFFFu #define ADC_CV1_CV_SHIFT 0 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK) /* CV2 Bit Fields */ #define ADC_CV2_CV_MASK 0xFFFFu #define ADC_CV2_CV_SHIFT 0 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK) /* SC2 Bit Fields */ #define ADC_SC2_REFSEL_MASK 0x3u #define ADC_SC2_REFSEL_SHIFT 0 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK) #define ADC_SC2_DMAEN_MASK 0x4u #define ADC_SC2_DMAEN_SHIFT 2 #define ADC_SC2_ACREN_MASK 0x8u #define ADC_SC2_ACREN_SHIFT 3 #define ADC_SC2_ACFGT_MASK 0x10u #define ADC_SC2_ACFGT_SHIFT 4 #define ADC_SC2_ACFE_MASK 0x20u #define ADC_SC2_ACFE_SHIFT 5 #define ADC_SC2_ADTRG_MASK 0x40u #define ADC_SC2_ADTRG_SHIFT 6 #define ADC_SC2_ADACT_MASK 0x80u #define ADC_SC2_ADACT_SHIFT 7 /* SC3 Bit Fields */ #define ADC_SC3_AVGS_MASK 0x3u #define ADC_SC3_AVGS_SHIFT 0 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK) #define ADC_SC3_AVGE_MASK 0x4u #define ADC_SC3_AVGE_SHIFT 2 #define ADC_SC3_ADCO_MASK 0x8u #define ADC_SC3_ADCO_SHIFT 3 #define ADC_SC3_CALF_MASK 0x40u #define ADC_SC3_CALF_SHIFT 6 #define ADC_SC3_CAL_MASK 0x80u #define ADC_SC3_CAL_SHIFT 7 /* OFS Bit Fields */ #define ADC_OFS_OFS_MASK 0xFFFFu #define ADC_OFS_OFS_SHIFT 0 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK) /* PG Bit Fields */ #define ADC_PG_PG_MASK 0xFFFFu #define ADC_PG_PG_SHIFT 0 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK) /* MG Bit Fields */ #define ADC_MG_MG_MASK 0xFFFFu #define ADC_MG_MG_SHIFT 0 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK) /* CLPD Bit Fields */ #define ADC_CLPD_CLPD_MASK 0x3Fu #define ADC_CLPD_CLPD_SHIFT 0 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK) /* CLPS Bit Fields */ #define ADC_CLPS_CLPS_MASK 0x3Fu #define ADC_CLPS_CLPS_SHIFT 0 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK) /* CLP4 Bit Fields */ #define ADC_CLP4_CLP4_MASK 0x3FFu #define ADC_CLP4_CLP4_SHIFT 0 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK) /* CLP3 Bit Fields */ #define ADC_CLP3_CLP3_MASK 0x1FFu #define ADC_CLP3_CLP3_SHIFT 0 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK) /* CLP2 Bit Fields */ #define ADC_CLP2_CLP2_MASK 0xFFu #define ADC_CLP2_CLP2_SHIFT 0 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK) /* CLP1 Bit Fields */ #define ADC_CLP1_CLP1_MASK 0x7Fu #define ADC_CLP1_CLP1_SHIFT 0 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK) /* CLP0 Bit Fields */ #define ADC_CLP0_CLP0_MASK 0x3Fu #define ADC_CLP0_CLP0_SHIFT 0 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK) /* CLMD Bit Fields */ #define ADC_CLMD_CLMD_MASK 0x3Fu #define ADC_CLMD_CLMD_SHIFT 0 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK) /* CLMS Bit Fields */ #define ADC_CLMS_CLMS_MASK 0x3Fu #define ADC_CLMS_CLMS_SHIFT 0 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK) /* CLM4 Bit Fields */ #define ADC_CLM4_CLM4_MASK 0x3FFu #define ADC_CLM4_CLM4_SHIFT 0 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK) /* CLM3 Bit Fields */ #define ADC_CLM3_CLM3_MASK 0x1FFu #define ADC_CLM3_CLM3_SHIFT 0 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK) /* CLM2 Bit Fields */ #define ADC_CLM2_CLM2_MASK 0xFFu #define ADC_CLM2_CLM2_SHIFT 0 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK) /* CLM1 Bit Fields */ #define ADC_CLM1_CLM1_MASK 0x7Fu #define ADC_CLM1_CLM1_SHIFT 0 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK) /* CLM0 Bit Fields */ #define ADC_CLM0_CLM0_MASK 0x3Fu #define ADC_CLM0_CLM0_SHIFT 0 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK) /*! * @} */ /* end of group ADC_Register_Masks */ /* ADC - Peripheral instance base addresses */ /** Peripheral ADC0 base address */ #define ADC0_BASE (0x4003B000u) /** Peripheral ADC0 base pointer */ #define ADC0 ((ADC_Type *)ADC0_BASE) #define ADC0_BASE_PTR (ADC0) /** Array initializer of ADC peripheral base addresses */ #define ADC_BASE_ADDRS { ADC0_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { ADC0 } /** Interrupt vectors for the ADC peripheral type */ #define ADC_IRQS { ADC0_IRQn } /* ---------------------------------------------------------------------------- -- ADC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros * @{ */ /* ADC - Register instance definitions */ /* ADC0 */ #define ADC0_SC1A ADC_SC1_REG(ADC0,0) #define ADC0_SC1B ADC_SC1_REG(ADC0,1) #define ADC0_CFG1 ADC_CFG1_REG(ADC0) #define ADC0_CFG2 ADC_CFG2_REG(ADC0) #define ADC0_RA ADC_R_REG(ADC0,0) #define ADC0_RB ADC_R_REG(ADC0,1) #define ADC0_CV1 ADC_CV1_REG(ADC0) #define ADC0_CV2 ADC_CV2_REG(ADC0) #define ADC0_SC2 ADC_SC2_REG(ADC0) #define ADC0_SC3 ADC_SC3_REG(ADC0) #define ADC0_OFS ADC_OFS_REG(ADC0) #define ADC0_PG ADC_PG_REG(ADC0) #define ADC0_MG ADC_MG_REG(ADC0) #define ADC0_CLPD ADC_CLPD_REG(ADC0) #define ADC0_CLPS ADC_CLPS_REG(ADC0) #define ADC0_CLP4 ADC_CLP4_REG(ADC0) #define ADC0_CLP3 ADC_CLP3_REG(ADC0) #define ADC0_CLP2 ADC_CLP2_REG(ADC0) #define ADC0_CLP1 ADC_CLP1_REG(ADC0) #define ADC0_CLP0 ADC_CLP0_REG(ADC0) #define ADC0_CLMD ADC_CLMD_REG(ADC0) #define ADC0_CLMS ADC_CLMS_REG(ADC0) #define ADC0_CLM4 ADC_CLM4_REG(ADC0) #define ADC0_CLM3 ADC_CLM3_REG(ADC0) #define ADC0_CLM2 ADC_CLM2_REG(ADC0) #define ADC0_CLM1 ADC_CLM1_REG(ADC0) #define ADC0_CLM0 ADC_CLM0_REG(ADC0) /* ADC - Register array accessors */ #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index) #define ADC0_R(index) ADC_R_REG(ADC0,index) /*! * @} */ /* end of group ADC_Register_Accessor_Macros */ /*! * @} */ /* end of group ADC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- CMP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer * @{ */ /** CMP - Register Layout Typedef */ typedef struct { __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ } CMP_Type, *CMP_MemMapPtr; /* ---------------------------------------------------------------------------- -- CMP - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros * @{ */ /* CMP - Register accessors */ #define CMP_CR0_REG(base) ((base)->CR0) #define CMP_CR1_REG(base) ((base)->CR1) #define CMP_FPR_REG(base) ((base)->FPR) #define CMP_SCR_REG(base) ((base)->SCR) #define CMP_DACCR_REG(base) ((base)->DACCR) #define CMP_MUXCR_REG(base) ((base)->MUXCR) /*! * @} */ /* end of group CMP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CMP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Register_Masks CMP Register Masks * @{ */ /* CR0 Bit Fields */ #define CMP_CR0_HYSTCTR_MASK 0x3u #define CMP_CR0_HYSTCTR_SHIFT 0 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK) #define CMP_CR0_FILTER_CNT_MASK 0x70u #define CMP_CR0_FILTER_CNT_SHIFT 4 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK) /* CR1 Bit Fields */ #define CMP_CR1_EN_MASK 0x1u #define CMP_CR1_EN_SHIFT 0 #define CMP_CR1_OPE_MASK 0x2u #define CMP_CR1_OPE_SHIFT 1 #define CMP_CR1_COS_MASK 0x4u #define CMP_CR1_COS_SHIFT 2 #define CMP_CR1_INV_MASK 0x8u #define CMP_CR1_INV_SHIFT 3 #define CMP_CR1_PMODE_MASK 0x10u #define CMP_CR1_PMODE_SHIFT 4 #define CMP_CR1_TRIGM_MASK 0x20u #define CMP_CR1_TRIGM_SHIFT 5 #define CMP_CR1_WE_MASK 0x40u #define CMP_CR1_WE_SHIFT 6 #define CMP_CR1_SE_MASK 0x80u #define CMP_CR1_SE_SHIFT 7 /* FPR Bit Fields */ #define CMP_FPR_FILT_PER_MASK 0xFFu #define CMP_FPR_FILT_PER_SHIFT 0 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK) /* SCR Bit Fields */ #define CMP_SCR_COUT_MASK 0x1u #define CMP_SCR_COUT_SHIFT 0 #define CMP_SCR_CFF_MASK 0x2u #define CMP_SCR_CFF_SHIFT 1 #define CMP_SCR_CFR_MASK 0x4u #define CMP_SCR_CFR_SHIFT 2 #define CMP_SCR_IEF_MASK 0x8u #define CMP_SCR_IEF_SHIFT 3 #define CMP_SCR_IER_MASK 0x10u #define CMP_SCR_IER_SHIFT 4 #define CMP_SCR_DMAEN_MASK 0x40u #define CMP_SCR_DMAEN_SHIFT 6 /* DACCR Bit Fields */ #define CMP_DACCR_VOSEL_MASK 0x3Fu #define CMP_DACCR_VOSEL_SHIFT 0 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK) #define CMP_DACCR_VRSEL_MASK 0x40u #define CMP_DACCR_VRSEL_SHIFT 6 #define CMP_DACCR_DACEN_MASK 0x80u #define CMP_DACCR_DACEN_SHIFT 7 /* MUXCR Bit Fields */ #define CMP_MUXCR_MSEL_MASK 0x7u #define CMP_MUXCR_MSEL_SHIFT 0 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK) #define CMP_MUXCR_PSEL_MASK 0x38u #define CMP_MUXCR_PSEL_SHIFT 3 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK) #define CMP_MUXCR_PSTM_MASK 0x80u #define CMP_MUXCR_PSTM_SHIFT 7 /*! * @} */ /* end of group CMP_Register_Masks */ /* CMP - Peripheral instance base addresses */ /** Peripheral CMP0 base address */ #define CMP0_BASE (0x40073000u) /** Peripheral CMP0 base pointer */ #define CMP0 ((CMP_Type *)CMP0_BASE) #define CMP0_BASE_PTR (CMP0) /** Array initializer of CMP peripheral base addresses */ #define CMP_BASE_ADDRS { CMP0_BASE } /** Array initializer of CMP peripheral base pointers */ #define CMP_BASE_PTRS { CMP0 } /** Interrupt vectors for the CMP peripheral type */ #define CMP_IRQS { CMP0_IRQn } /* ---------------------------------------------------------------------------- -- CMP - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros * @{ */ /* CMP - Register instance definitions */ /* CMP0 */ #define CMP0_CR0 CMP_CR0_REG(CMP0) #define CMP0_CR1 CMP_CR1_REG(CMP0) #define CMP0_FPR CMP_FPR_REG(CMP0) #define CMP0_SCR CMP_SCR_REG(CMP0) #define CMP0_DACCR CMP_DACCR_REG(CMP0) #define CMP0_MUXCR CMP_MUXCR_REG(CMP0) /*! * @} */ /* end of group CMP_Register_Accessor_Macros */ /*! * @} */ /* end of group CMP_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DAC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer * @{ */ /** DAC - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x2 */ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ } DAT[2]; uint8_t RESERVED_0[28]; __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ } DAC_Type, *DAC_MemMapPtr; /* ---------------------------------------------------------------------------- -- DAC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros * @{ */ /* DAC - Register accessors */ #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL) #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) #define DAC_SR_REG(base) ((base)->SR) #define DAC_C0_REG(base) ((base)->C0) #define DAC_C1_REG(base) ((base)->C1) #define DAC_C2_REG(base) ((base)->C2) /*! * @} */ /* end of group DAC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DAC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DAC_Register_Masks DAC Register Masks * @{ */ /* DATL Bit Fields */ #define DAC_DATL_DATA0_MASK 0xFFu #define DAC_DATL_DATA0_SHIFT 0 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK) /* DATH Bit Fields */ #define DAC_DATH_DATA1_MASK 0xFu #define DAC_DATH_DATA1_SHIFT 0 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK) /* SR Bit Fields */ #define DAC_SR_DACBFRPBF_MASK 0x1u #define DAC_SR_DACBFRPBF_SHIFT 0 #define DAC_SR_DACBFRPTF_MASK 0x2u #define DAC_SR_DACBFRPTF_SHIFT 1 /* C0 Bit Fields */ #define DAC_C0_DACBBIEN_MASK 0x1u #define DAC_C0_DACBBIEN_SHIFT 0 #define DAC_C0_DACBTIEN_MASK 0x2u #define DAC_C0_DACBTIEN_SHIFT 1 #define DAC_C0_LPEN_MASK 0x8u #define DAC_C0_LPEN_SHIFT 3 #define DAC_C0_DACSWTRG_MASK 0x10u #define DAC_C0_DACSWTRG_SHIFT 4 #define DAC_C0_DACTRGSEL_MASK 0x20u #define DAC_C0_DACTRGSEL_SHIFT 5 #define DAC_C0_DACRFS_MASK 0x40u #define DAC_C0_DACRFS_SHIFT 6 #define DAC_C0_DACEN_MASK 0x80u #define DAC_C0_DACEN_SHIFT 7 /* C1 Bit Fields */ #define DAC_C1_DACBFEN_MASK 0x1u #define DAC_C1_DACBFEN_SHIFT 0 #define DAC_C1_DACBFMD_MASK 0x6u #define DAC_C1_DACBFMD_SHIFT 1 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK) #define DAC_C1_DMAEN_MASK 0x80u #define DAC_C1_DMAEN_SHIFT 7 /* C2 Bit Fields */ #define DAC_C2_DACBFUP_MASK 0x1u #define DAC_C2_DACBFUP_SHIFT 0 #define DAC_C2_DACBFRP_MASK 0x10u #define DAC_C2_DACBFRP_SHIFT 4 /*! * @} */ /* end of group DAC_Register_Masks */ /* DAC - Peripheral instance base addresses */ /** Peripheral DAC0 base address */ #define DAC0_BASE (0x4003F000u) /** Peripheral DAC0 base pointer */ #define DAC0 ((DAC_Type *)DAC0_BASE) #define DAC0_BASE_PTR (DAC0) /** Array initializer of DAC peripheral base addresses */ #define DAC_BASE_ADDRS { DAC0_BASE } /** Array initializer of DAC peripheral base pointers */ #define DAC_BASE_PTRS { DAC0 } /** Interrupt vectors for the DAC peripheral type */ #define DAC_IRQS { DAC0_IRQn } /* ---------------------------------------------------------------------------- -- DAC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros * @{ */ /* DAC - Register instance definitions */ /* DAC0 */ #define DAC0_DAT0L DAC_DATL_REG(DAC0,0) #define DAC0_DAT0H DAC_DATH_REG(DAC0,0) #define DAC0_DAT1L DAC_DATL_REG(DAC0,1) #define DAC0_DAT1H DAC_DATH_REG(DAC0,1) #define DAC0_SR DAC_SR_REG(DAC0) #define DAC0_C0 DAC_C0_REG(DAC0) #define DAC0_C1 DAC_C1_REG(DAC0) #define DAC0_C2 DAC_C2_REG(DAC0) /* DAC - Register array accessors */ #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index) #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index) /*! * @} */ /* end of group DAC_Register_Accessor_Macros */ /*! * @} */ /* end of group DAC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer * @{ */ /** DMA - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[256]; struct { /* offset: 0x100, array step: 0x10 */ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */ union { /* offset: 0x108, array step: 0x10 */ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */ struct { /* offset: 0x108, array step: 0x10 */ uint8_t RESERVED_0[3]; __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */ } DMA_DSR_ACCESS8BIT; }; __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */ } DMA[4]; } DMA_Type, *DMA_MemMapPtr; /* ---------------------------------------------------------------------------- -- DMA - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros * @{ */ /* DMA - Register accessors */ #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR) #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR) #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR) #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR) #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR) /*! * @} */ /* end of group DMA_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /* SAR Bit Fields */ #define DMA_SAR_SAR_MASK 0xFFFFFFFFu #define DMA_SAR_SAR_SHIFT 0 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK) /* DAR Bit Fields */ #define DMA_DAR_DAR_MASK 0xFFFFFFFFu #define DMA_DAR_DAR_SHIFT 0 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK) /* DSR_BCR Bit Fields */ #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu #define DMA_DSR_BCR_BCR_SHIFT 0 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK) #define DMA_DSR_BCR_DONE_MASK 0x1000000u #define DMA_DSR_BCR_DONE_SHIFT 24 #define DMA_DSR_BCR_BSY_MASK 0x2000000u #define DMA_DSR_BCR_BSY_SHIFT 25 #define DMA_DSR_BCR_REQ_MASK 0x4000000u #define DMA_DSR_BCR_REQ_SHIFT 26 #define DMA_DSR_BCR_BED_MASK 0x10000000u #define DMA_DSR_BCR_BED_SHIFT 28 #define DMA_DSR_BCR_BES_MASK 0x20000000u #define DMA_DSR_BCR_BES_SHIFT 29 #define DMA_DSR_BCR_CE_MASK 0x40000000u #define DMA_DSR_BCR_CE_SHIFT 30 /* DCR Bit Fields */ #define DMA_DCR_LCH2_MASK 0x3u #define DMA_DCR_LCH2_SHIFT 0 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK) #define DMA_DCR_LCH1_MASK 0xCu #define DMA_DCR_LCH1_SHIFT 2 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK) #define DMA_DCR_LINKCC_MASK 0x30u #define DMA_DCR_LINKCC_SHIFT 4 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK) #define DMA_DCR_D_REQ_MASK 0x80u #define DMA_DCR_D_REQ_SHIFT 7 #define DMA_DCR_DMOD_MASK 0xF00u #define DMA_DCR_DMOD_SHIFT 8 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK) #define DMA_DCR_SMOD_MASK 0xF000u #define DMA_DCR_SMOD_SHIFT 12 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK) #define DMA_DCR_START_MASK 0x10000u #define DMA_DCR_START_SHIFT 16 #define DMA_DCR_DSIZE_MASK 0x60000u #define DMA_DCR_DSIZE_SHIFT 17 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK) #define DMA_DCR_DINC_MASK 0x80000u #define DMA_DCR_DINC_SHIFT 19 #define DMA_DCR_SSIZE_MASK 0x300000u #define DMA_DCR_SSIZE_SHIFT 20 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK) #define DMA_DCR_SINC_MASK 0x400000u #define DMA_DCR_SINC_SHIFT 22 #define DMA_DCR_EADREQ_MASK 0x800000u #define DMA_DCR_EADREQ_SHIFT 23 #define DMA_DCR_AA_MASK 0x10000000u #define DMA_DCR_AA_SHIFT 28 #define DMA_DCR_CS_MASK 0x20000000u #define DMA_DCR_CS_SHIFT 29 #define DMA_DCR_ERQ_MASK 0x40000000u #define DMA_DCR_ERQ_SHIFT 30 #define DMA_DCR_EINT_MASK 0x80000000u #define DMA_DCR_EINT_SHIFT 31 /*! * @} */ /* end of group DMA_Register_Masks */ /* DMA - Peripheral instance base addresses */ /** Peripheral DMA base address */ #define DMA_BASE (0x40008000u) /** Peripheral DMA base pointer */ #define DMA0 ((DMA_Type *)DMA_BASE) #define DMA_BASE_PTR (DMA0) /** Array initializer of DMA peripheral base addresses */ #define DMA_BASE_ADDRS { DMA_BASE } /** Array initializer of DMA peripheral base pointers */ #define DMA_BASE_PTRS { DMA0 } /** Interrupt vectors for the DMA peripheral type */ #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } /* ---------------------------------------------------------------------------- -- DMA - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros * @{ */ /* DMA - Register instance definitions */ /* DMA */ #define DMA_SAR0 DMA_SAR_REG(DMA0,0) #define DMA_DAR0 DMA_DAR_REG(DMA0,0) #define DMA_DSR_BCR0 DMA_DSR_BCR_REG(DMA0,0) #define DMA_DSR0 DMA_DSR_REG(DMA0,0) #define DMA_DCR0 DMA_DCR_REG(DMA0,0) #define DMA_SAR1 DMA_SAR_REG(DMA0,1) #define DMA_DAR1 DMA_DAR_REG(DMA0,1) #define DMA_DSR_BCR1 DMA_DSR_BCR_REG(DMA0,1) #define DMA_DSR1 DMA_DSR_REG(DMA0,1) #define DMA_DCR1 DMA_DCR_REG(DMA0,1) #define DMA_SAR2 DMA_SAR_REG(DMA0,2) #define DMA_DAR2 DMA_DAR_REG(DMA0,2) #define DMA_DSR_BCR2 DMA_DSR_BCR_REG(DMA0,2) #define DMA_DSR2 DMA_DSR_REG(DMA0,2) #define DMA_DCR2 DMA_DCR_REG(DMA0,2) #define DMA_SAR3 DMA_SAR_REG(DMA0,3) #define DMA_DAR3 DMA_DAR_REG(DMA0,3) #define DMA_DSR_BCR3 DMA_DSR_BCR_REG(DMA0,3) #define DMA_DSR3 DMA_DSR_REG(DMA0,3) #define DMA_DCR3 DMA_DCR_REG(DMA0,3) /* DMA - Register array accessors */ #define DMA_SAR(index) DMA_SAR_REG(DMA0,index) #define DMA_DAR(index) DMA_DAR_REG(DMA0,index) #define DMA_DSR_BCR(index) DMA_DSR_BCR_REG(DMA0,index) #define DMA_DSR(index) DMA_DSR_REG(DMA0,index) #define DMA_DCR(index) DMA_DCR_REG(DMA0,index) /*! * @} */ /* end of group DMA_Register_Accessor_Macros */ /*! * @} */ /* end of group DMA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- DMAMUX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer * @{ */ /** DMAMUX - Register Layout Typedef */ typedef struct { __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ } DMAMUX_Type, *DMAMUX_MemMapPtr; /* ---------------------------------------------------------------------------- -- DMAMUX - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros * @{ */ /* DMAMUX - Register accessors */ #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index]) /*! * @} */ /* end of group DMAMUX_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks * @{ */ /* CHCFG Bit Fields */ #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu #define DMAMUX_CHCFG_SOURCE_SHIFT 0 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK) #define DMAMUX_CHCFG_TRIG_MASK 0x40u #define DMAMUX_CHCFG_TRIG_SHIFT 6 #define DMAMUX_CHCFG_ENBL_MASK 0x80u #define DMAMUX_CHCFG_ENBL_SHIFT 7 /*! * @} */ /* end of group DMAMUX_Register_Masks */ /* DMAMUX - Peripheral instance base addresses */ /** Peripheral DMAMUX0 base address */ #define DMAMUX0_BASE (0x40021000u) /** Peripheral DMAMUX0 base pointer */ #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) #define DMAMUX0_BASE_PTR (DMAMUX0) /** Array initializer of DMAMUX peripheral base addresses */ #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE } /** Array initializer of DMAMUX peripheral base pointers */ #define DMAMUX_BASE_PTRS { DMAMUX0 } /* ---------------------------------------------------------------------------- -- DMAMUX - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros * @{ */ /* DMAMUX - Register instance definitions */ /* DMAMUX0 */ #define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0,0) #define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0,1) #define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0,2) #define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0,3) /* DMAMUX - Register array accessors */ #define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0,index) /*! * @} */ /* end of group DMAMUX_Register_Accessor_Macros */ /*! * @} */ /* end of group DMAMUX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FLEXIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer * @{ */ /** FLEXIO - Register Layout Typedef */ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ uint8_t RESERVED_0[4]; __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ uint8_t RESERVED_1[4]; __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ uint8_t RESERVED_2[4]; __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ uint8_t RESERVED_3[76]; __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ uint8_t RESERVED_4[112]; __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_5[240]; __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_6[112]; __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x280, array step: 0x4 */ uint8_t RESERVED_7[112]; __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ uint8_t RESERVED_8[112]; __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x380, array step: 0x4 */ uint8_t RESERVED_9[112]; __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ uint8_t RESERVED_10[112]; __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ uint8_t RESERVED_11[112]; __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ } FLEXIO_Type, *FLEXIO_MemMapPtr; /* ---------------------------------------------------------------------------- -- FLEXIO - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros * @{ */ /* FLEXIO - Register accessors */ #define FLEXIO_VERID_REG(base) ((base)->VERID) #define FLEXIO_PARAM_REG(base) ((base)->PARAM) #define FLEXIO_CTRL_REG(base) ((base)->CTRL) #define FLEXIO_SHIFTSTAT_REG(base) ((base)->SHIFTSTAT) #define FLEXIO_SHIFTERR_REG(base) ((base)->SHIFTERR) #define FLEXIO_TIMSTAT_REG(base) ((base)->TIMSTAT) #define FLEXIO_SHIFTSIEN_REG(base) ((base)->SHIFTSIEN) #define FLEXIO_SHIFTEIEN_REG(base) ((base)->SHIFTEIEN) #define FLEXIO_TIMIEN_REG(base) ((base)->TIMIEN) #define FLEXIO_SHIFTSDEN_REG(base) ((base)->SHIFTSDEN) #define FLEXIO_SHIFTCTL_REG(base,index) ((base)->SHIFTCTL[index]) #define FLEXIO_SHIFTCFG_REG(base,index) ((base)->SHIFTCFG[index]) #define FLEXIO_SHIFTBUF_REG(base,index) ((base)->SHIFTBUF[index]) #define FLEXIO_SHIFTBUFBBS_REG(base,index) ((base)->SHIFTBUFBBS[index]) #define FLEXIO_SHIFTBUFBYS_REG(base,index) ((base)->SHIFTBUFBYS[index]) #define FLEXIO_SHIFTBUFBIS_REG(base,index) ((base)->SHIFTBUFBIS[index]) #define FLEXIO_TIMCTL_REG(base,index) ((base)->TIMCTL[index]) #define FLEXIO_TIMCFG_REG(base,index) ((base)->TIMCFG[index]) #define FLEXIO_TIMCMP_REG(base,index) ((base)->TIMCMP[index]) /*! * @} */ /* end of group FLEXIO_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FLEXIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks * @{ */ /* VERID Bit Fields */ #define FLEXIO_VERID_FEATURE_MASK 0xFFFFu #define FLEXIO_VERID_FEATURE_SHIFT 0 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK) #define FLEXIO_VERID_MINOR_MASK 0xFF0000u #define FLEXIO_VERID_MINOR_SHIFT 16 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK) #define FLEXIO_VERID_MAJOR_MASK 0xFF000000u #define FLEXIO_VERID_MAJOR_SHIFT 24 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK) /* PARAM Bit Fields */ #define FLEXIO_PARAM_SHIFTER_MASK 0xFFu #define FLEXIO_PARAM_SHIFTER_SHIFT 0 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK) #define FLEXIO_PARAM_TIMER_MASK 0xFF00u #define FLEXIO_PARAM_TIMER_SHIFT 8 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK) #define FLEXIO_PARAM_PIN_MASK 0xFF0000u #define FLEXIO_PARAM_PIN_SHIFT 16 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK) #define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u #define FLEXIO_PARAM_TRIGGER_SHIFT 24 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK) /* CTRL Bit Fields */ #define FLEXIO_CTRL_FLEXEN_MASK 0x1u #define FLEXIO_CTRL_FLEXEN_SHIFT 0 #define FLEXIO_CTRL_SWRST_MASK 0x2u #define FLEXIO_CTRL_SWRST_SHIFT 1 #define FLEXIO_CTRL_FASTACC_MASK 0x4u #define FLEXIO_CTRL_FASTACC_SHIFT 2 #define FLEXIO_CTRL_DBGE_MASK 0x40000000u #define FLEXIO_CTRL_DBGE_SHIFT 30 #define FLEXIO_CTRL_DOZEN_MASK 0x80000000u #define FLEXIO_CTRL_DOZEN_SHIFT 31 /* SHIFTSTAT Bit Fields */ #define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu #define FLEXIO_SHIFTSTAT_SSF_SHIFT 0 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK) /* SHIFTERR Bit Fields */ #define FLEXIO_SHIFTERR_SEF_MASK 0xFu #define FLEXIO_SHIFTERR_SEF_SHIFT 0 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK) /* TIMSTAT Bit Fields */ #define FLEXIO_TIMSTAT_TSF_MASK 0xFu #define FLEXIO_TIMSTAT_TSF_SHIFT 0 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK) /* SHIFTSIEN Bit Fields */ #define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu #define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK) /* SHIFTEIEN Bit Fields */ #define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu #define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK) /* TIMIEN Bit Fields */ #define FLEXIO_TIMIEN_TEIE_MASK 0xFu #define FLEXIO_TIMIEN_TEIE_SHIFT 0 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK) /* SHIFTSDEN Bit Fields */ #define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu #define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK) /* SHIFTCTL Bit Fields */ #define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u #define FLEXIO_SHIFTCTL_SMOD_SHIFT 0 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK) #define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u #define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7 #define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u #define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK) #define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u #define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK) #define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23 #define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK) /* SHIFTCFG Bit Fields */ #define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u #define FLEXIO_SHIFTCFG_SSTART_SHIFT 0 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK) #define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u #define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK) #define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u #define FLEXIO_SHIFTCFG_INSRC_SHIFT 8 /* SHIFTBUF Bit Fields */ #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK) /* SHIFTBUFBBS Bit Fields */ #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) /* SHIFTBUFBYS Bit Fields */ #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) /* SHIFTBUFBIS Bit Fields */ #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) /* TIMCTL Bit Fields */ #define FLEXIO_TIMCTL_TIMOD_MASK 0x3u #define FLEXIO_TIMCTL_TIMOD_SHIFT 0 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK) #define FLEXIO_TIMCTL_PINPOL_MASK 0x80u #define FLEXIO_TIMCTL_PINPOL_SHIFT 7 #define FLEXIO_TIMCTL_PINSEL_MASK 0x700u #define FLEXIO_TIMCTL_PINSEL_SHIFT 8 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK) #define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u #define FLEXIO_TIMCTL_PINCFG_SHIFT 16 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK) #define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u #define FLEXIO_TIMCTL_TRGSRC_SHIFT 22 #define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u #define FLEXIO_TIMCTL_TRGPOL_SHIFT 23 #define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u #define FLEXIO_TIMCTL_TRGSEL_SHIFT 24 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK) /* TIMCFG Bit Fields */ #define FLEXIO_TIMCFG_TSTART_MASK 0x2u #define FLEXIO_TIMCFG_TSTART_SHIFT 1 #define FLEXIO_TIMCFG_TSTOP_MASK 0x30u #define FLEXIO_TIMCFG_TSTOP_SHIFT 4 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK) #define FLEXIO_TIMCFG_TIMENA_MASK 0x700u #define FLEXIO_TIMCFG_TIMENA_SHIFT 8 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK) #define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u #define FLEXIO_TIMCFG_TIMDIS_SHIFT 12 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK) #define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u #define FLEXIO_TIMCFG_TIMRST_SHIFT 16 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK) #define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u #define FLEXIO_TIMCFG_TIMDEC_SHIFT 20 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK) #define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u #define FLEXIO_TIMCFG_TIMOUT_SHIFT 24 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK) /* TIMCMP Bit Fields */ #define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu #define FLEXIO_TIMCMP_CMP_SHIFT 0 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK) /*! * @} */ /* end of group FLEXIO_Register_Masks */ /* FLEXIO - Peripheral instance base addresses */ /** Peripheral FLEXIO base address */ #define FLEXIO_BASE (0x4005F000u) /** Peripheral FLEXIO base pointer */ #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE) #define FLEXIO_BASE_PTR (FLEXIO) /** Array initializer of FLEXIO peripheral base addresses */ #define FLEXIO_BASE_ADDRS { FLEXIO_BASE } /** Array initializer of FLEXIO peripheral base pointers */ #define FLEXIO_BASE_PTRS { FLEXIO } /* ---------------------------------------------------------------------------- -- FLEXIO - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros * @{ */ /* FLEXIO - Register instance definitions */ /* FLEXIO */ #define FLEXIO_VERID FLEXIO_VERID_REG(FLEXIO) #define FLEXIO_PARAM FLEXIO_PARAM_REG(FLEXIO) #define FLEXIO_CTRL FLEXIO_CTRL_REG(FLEXIO) #define FLEXIO_SHIFTSTAT FLEXIO_SHIFTSTAT_REG(FLEXIO) #define FLEXIO_SHIFTERR FLEXIO_SHIFTERR_REG(FLEXIO) #define FLEXIO_TIMSTAT FLEXIO_TIMSTAT_REG(FLEXIO) #define FLEXIO_SHIFTSIEN FLEXIO_SHIFTSIEN_REG(FLEXIO) #define FLEXIO_SHIFTEIEN FLEXIO_SHIFTEIEN_REG(FLEXIO) #define FLEXIO_TIMIEN FLEXIO_TIMIEN_REG(FLEXIO) #define FLEXIO_SHIFTSDEN FLEXIO_SHIFTSDEN_REG(FLEXIO) #define FLEXIO_SHIFTCTL0 FLEXIO_SHIFTCTL_REG(FLEXIO,0) #define FLEXIO_SHIFTCTL1 FLEXIO_SHIFTCTL_REG(FLEXIO,1) #define FLEXIO_SHIFTCTL2 FLEXIO_SHIFTCTL_REG(FLEXIO,2) #define FLEXIO_SHIFTCTL3 FLEXIO_SHIFTCTL_REG(FLEXIO,3) #define FLEXIO_SHIFTCFG0 FLEXIO_SHIFTCFG_REG(FLEXIO,0) #define FLEXIO_SHIFTCFG1 FLEXIO_SHIFTCFG_REG(FLEXIO,1) #define FLEXIO_SHIFTCFG2 FLEXIO_SHIFTCFG_REG(FLEXIO,2) #define FLEXIO_SHIFTCFG3 FLEXIO_SHIFTCFG_REG(FLEXIO,3) #define FLEXIO_SHIFTBUF0 FLEXIO_SHIFTBUF_REG(FLEXIO,0) #define FLEXIO_SHIFTBUF1 FLEXIO_SHIFTBUF_REG(FLEXIO,1) #define FLEXIO_SHIFTBUF2 FLEXIO_SHIFTBUF_REG(FLEXIO,2) #define FLEXIO_SHIFTBUF3 FLEXIO_SHIFTBUF_REG(FLEXIO,3) #define FLEXIO_SHIFTBUFBBS0 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,0) #define FLEXIO_SHIFTBUFBBS1 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,1) #define FLEXIO_SHIFTBUFBBS2 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,2) #define FLEXIO_SHIFTBUFBBS3 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,3) #define FLEXIO_SHIFTBUFBYS0 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,0) #define FLEXIO_SHIFTBUFBYS1 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,1) #define FLEXIO_SHIFTBUFBYS2 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,2) #define FLEXIO_SHIFTBUFBYS3 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,3) #define FLEXIO_SHIFTBUFBIS0 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,0) #define FLEXIO_SHIFTBUFBIS1 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,1) #define FLEXIO_SHIFTBUFBIS2 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,2) #define FLEXIO_SHIFTBUFBIS3 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,3) #define FLEXIO_TIMCTL0 FLEXIO_TIMCTL_REG(FLEXIO,0) #define FLEXIO_TIMCTL1 FLEXIO_TIMCTL_REG(FLEXIO,1) #define FLEXIO_TIMCTL2 FLEXIO_TIMCTL_REG(FLEXIO,2) #define FLEXIO_TIMCTL3 FLEXIO_TIMCTL_REG(FLEXIO,3) #define FLEXIO_TIMCFG0 FLEXIO_TIMCFG_REG(FLEXIO,0) #define FLEXIO_TIMCFG1 FLEXIO_TIMCFG_REG(FLEXIO,1) #define FLEXIO_TIMCFG2 FLEXIO_TIMCFG_REG(FLEXIO,2) #define FLEXIO_TIMCFG3 FLEXIO_TIMCFG_REG(FLEXIO,3) #define FLEXIO_TIMCMP0 FLEXIO_TIMCMP_REG(FLEXIO,0) #define FLEXIO_TIMCMP1 FLEXIO_TIMCMP_REG(FLEXIO,1) #define FLEXIO_TIMCMP2 FLEXIO_TIMCMP_REG(FLEXIO,2) #define FLEXIO_TIMCMP3 FLEXIO_TIMCMP_REG(FLEXIO,3) /* FLEXIO - Register array accessors */ #define FLEXIO_SHIFTCTL(index) FLEXIO_SHIFTCTL_REG(FLEXIO,index) #define FLEXIO_SHIFTCFG(index) FLEXIO_SHIFTCFG_REG(FLEXIO,index) #define FLEXIO_SHIFTBUF(index) FLEXIO_SHIFTBUF_REG(FLEXIO,index) #define FLEXIO_SHIFTBUFBBS(index) FLEXIO_SHIFTBUFBBS_REG(FLEXIO,index) #define FLEXIO_SHIFTBUFBYS(index) FLEXIO_SHIFTBUFBYS_REG(FLEXIO,index) #define FLEXIO_SHIFTBUFBIS(index) FLEXIO_SHIFTBUFBIS_REG(FLEXIO,index) #define FLEXIO_TIMCTL(index) FLEXIO_TIMCTL_REG(FLEXIO,index) #define FLEXIO_TIMCFG(index) FLEXIO_TIMCFG_REG(FLEXIO,index) #define FLEXIO_TIMCMP(index) FLEXIO_TIMCMP_REG(FLEXIO,index) /*! * @} */ /* end of group FLEXIO_Register_Accessor_Macros */ /*! * @} */ /* end of group FLEXIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- FTFA Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer * @{ */ /** FTFA - Register Layout Typedef */ typedef struct { __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ } FTFA_Type, *FTFA_MemMapPtr; /* ---------------------------------------------------------------------------- -- FTFA - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros * @{ */ /* FTFA - Register accessors */ #define FTFA_FSTAT_REG(base) ((base)->FSTAT) #define FTFA_FCNFG_REG(base) ((base)->FCNFG) #define FTFA_FSEC_REG(base) ((base)->FSEC) #define FTFA_FOPT_REG(base) ((base)->FOPT) #define FTFA_FCCOB3_REG(base) ((base)->FCCOB3) #define FTFA_FCCOB2_REG(base) ((base)->FCCOB2) #define FTFA_FCCOB1_REG(base) ((base)->FCCOB1) #define FTFA_FCCOB0_REG(base) ((base)->FCCOB0) #define FTFA_FCCOB7_REG(base) ((base)->FCCOB7) #define FTFA_FCCOB6_REG(base) ((base)->FCCOB6) #define FTFA_FCCOB5_REG(base) ((base)->FCCOB5) #define FTFA_FCCOB4_REG(base) ((base)->FCCOB4) #define FTFA_FCCOBB_REG(base) ((base)->FCCOBB) #define FTFA_FCCOBA_REG(base) ((base)->FCCOBA) #define FTFA_FCCOB9_REG(base) ((base)->FCCOB9) #define FTFA_FCCOB8_REG(base) ((base)->FCCOB8) #define FTFA_FPROT3_REG(base) ((base)->FPROT3) #define FTFA_FPROT2_REG(base) ((base)->FPROT2) #define FTFA_FPROT1_REG(base) ((base)->FPROT1) #define FTFA_FPROT0_REG(base) ((base)->FPROT0) /*! * @} */ /* end of group FTFA_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FTFA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FTFA_Register_Masks FTFA Register Masks * @{ */ /* FSTAT Bit Fields */ #define FTFA_FSTAT_MGSTAT0_MASK 0x1u #define FTFA_FSTAT_MGSTAT0_SHIFT 0 #define FTFA_FSTAT_FPVIOL_MASK 0x10u #define FTFA_FSTAT_FPVIOL_SHIFT 4 #define FTFA_FSTAT_ACCERR_MASK 0x20u #define FTFA_FSTAT_ACCERR_SHIFT 5 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u #define FTFA_FSTAT_RDCOLERR_SHIFT 6 #define FTFA_FSTAT_CCIF_MASK 0x80u #define FTFA_FSTAT_CCIF_SHIFT 7 /* FCNFG Bit Fields */ #define FTFA_FCNFG_ERSSUSP_MASK 0x10u #define FTFA_FCNFG_ERSSUSP_SHIFT 4 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u #define FTFA_FCNFG_ERSAREQ_SHIFT 5 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u #define FTFA_FCNFG_RDCOLLIE_SHIFT 6 #define FTFA_FCNFG_CCIE_MASK 0x80u #define FTFA_FCNFG_CCIE_SHIFT 7 /* FSEC Bit Fields */ #define FTFA_FSEC_SEC_MASK 0x3u #define FTFA_FSEC_SEC_SHIFT 0 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK) #define FTFA_FSEC_FSLACC_MASK 0xCu #define FTFA_FSEC_FSLACC_SHIFT 2 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK) #define FTFA_FSEC_MEEN_MASK 0x30u #define FTFA_FSEC_MEEN_SHIFT 4 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK) #define FTFA_FSEC_KEYEN_MASK 0xC0u #define FTFA_FSEC_KEYEN_SHIFT 6 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK) /* FOPT Bit Fields */ #define FTFA_FOPT_OPT_MASK 0xFFu #define FTFA_FOPT_OPT_SHIFT 0 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK) /* FCCOB3 Bit Fields */ #define FTFA_FCCOB3_CCOBn_MASK 0xFFu #define FTFA_FCCOB3_CCOBn_SHIFT 0 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK) /* FCCOB2 Bit Fields */ #define FTFA_FCCOB2_CCOBn_MASK 0xFFu #define FTFA_FCCOB2_CCOBn_SHIFT 0 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK) /* FCCOB1 Bit Fields */ #define FTFA_FCCOB1_CCOBn_MASK 0xFFu #define FTFA_FCCOB1_CCOBn_SHIFT 0 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK) /* FCCOB0 Bit Fields */ #define FTFA_FCCOB0_CCOBn_MASK 0xFFu #define FTFA_FCCOB0_CCOBn_SHIFT 0 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK) /* FCCOB7 Bit Fields */ #define FTFA_FCCOB7_CCOBn_MASK 0xFFu #define FTFA_FCCOB7_CCOBn_SHIFT 0 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK) /* FCCOB6 Bit Fields */ #define FTFA_FCCOB6_CCOBn_MASK 0xFFu #define FTFA_FCCOB6_CCOBn_SHIFT 0 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK) /* FCCOB5 Bit Fields */ #define FTFA_FCCOB5_CCOBn_MASK 0xFFu #define FTFA_FCCOB5_CCOBn_SHIFT 0 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK) /* FCCOB4 Bit Fields */ #define FTFA_FCCOB4_CCOBn_MASK 0xFFu #define FTFA_FCCOB4_CCOBn_SHIFT 0 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK) /* FCCOBB Bit Fields */ #define FTFA_FCCOBB_CCOBn_MASK 0xFFu #define FTFA_FCCOBB_CCOBn_SHIFT 0 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK) /* FCCOBA Bit Fields */ #define FTFA_FCCOBA_CCOBn_MASK 0xFFu #define FTFA_FCCOBA_CCOBn_SHIFT 0 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK) /* FCCOB9 Bit Fields */ #define FTFA_FCCOB9_CCOBn_MASK 0xFFu #define FTFA_FCCOB9_CCOBn_SHIFT 0 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK) /* FCCOB8 Bit Fields */ #define FTFA_FCCOB8_CCOBn_MASK 0xFFu #define FTFA_FCCOB8_CCOBn_SHIFT 0 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK) /* FPROT3 Bit Fields */ #define FTFA_FPROT3_PROT_MASK 0xFFu #define FTFA_FPROT3_PROT_SHIFT 0 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK) /* FPROT2 Bit Fields */ #define FTFA_FPROT2_PROT_MASK 0xFFu #define FTFA_FPROT2_PROT_SHIFT 0 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK) /* FPROT1 Bit Fields */ #define FTFA_FPROT1_PROT_MASK 0xFFu #define FTFA_FPROT1_PROT_SHIFT 0 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK) /* FPROT0 Bit Fields */ #define FTFA_FPROT0_PROT_MASK 0xFFu #define FTFA_FPROT0_PROT_SHIFT 0 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK) /*! * @} */ /* end of group FTFA_Register_Masks */ /* FTFA - Peripheral instance base addresses */ /** Peripheral FTFA base address */ #define FTFA_BASE (0x40020000u) /** Peripheral FTFA base pointer */ #define FTFA ((FTFA_Type *)FTFA_BASE) #define FTFA_BASE_PTR (FTFA) /** Array initializer of FTFA peripheral base addresses */ #define FTFA_BASE_ADDRS { FTFA_BASE } /** Array initializer of FTFA peripheral base pointers */ #define FTFA_BASE_PTRS { FTFA } /** Interrupt vectors for the FTFA peripheral type */ #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } /* ---------------------------------------------------------------------------- -- FTFA - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros * @{ */ /* FTFA - Register instance definitions */ /* FTFA */ #define FTFA_FSTAT FTFA_FSTAT_REG(FTFA) #define FTFA_FCNFG FTFA_FCNFG_REG(FTFA) #define FTFA_FSEC FTFA_FSEC_REG(FTFA) #define FTFA_FOPT FTFA_FOPT_REG(FTFA) #define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA) #define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA) #define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA) #define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA) #define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA) #define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA) #define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA) #define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA) #define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA) #define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA) #define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA) #define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA) #define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA) #define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA) #define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA) #define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA) /*! * @} */ /* end of group FTFA_Register_Accessor_Macros */ /*! * @} */ /* end of group FTFA_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- GPIO Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer * @{ */ /** GPIO - Register Layout Typedef */ typedef struct { __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ } GPIO_Type, *GPIO_MemMapPtr; /* ---------------------------------------------------------------------------- -- GPIO - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros * @{ */ /* GPIO - Register accessors */ #define GPIO_PDOR_REG(base) ((base)->PDOR) #define GPIO_PSOR_REG(base) ((base)->PSOR) #define GPIO_PCOR_REG(base) ((base)->PCOR) #define GPIO_PTOR_REG(base) ((base)->PTOR) #define GPIO_PDIR_REG(base) ((base)->PDIR) #define GPIO_PDDR_REG(base) ((base)->PDDR) /*! * @} */ /* end of group GPIO_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /* PDOR Bit Fields */ #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu #define GPIO_PDOR_PDO_SHIFT 0 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK) /* PSOR Bit Fields */ #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu #define GPIO_PSOR_PTSO_SHIFT 0 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK) /* PCOR Bit Fields */ #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu #define GPIO_PCOR_PTCO_SHIFT 0 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK) /* PTOR Bit Fields */ #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu #define GPIO_PTOR_PTTO_SHIFT 0 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK) /* PDIR Bit Fields */ #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu #define GPIO_PDIR_PDI_SHIFT 0 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK) /* PDDR Bit Fields */ #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu #define GPIO_PDDR_PDD_SHIFT 0 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK) /*! * @} */ /* end of group GPIO_Register_Masks */ /* GPIO - Peripheral instance base addresses */ /** Peripheral GPIOA base address */ #define GPIOA_BASE (0x400FF000u) /** Peripheral GPIOA base pointer */ #define GPIOA ((GPIO_Type *)GPIOA_BASE) #define GPIOA_BASE_PTR (GPIOA) /** Peripheral GPIOB base address */ #define GPIOB_BASE (0x400FF040u) /** Peripheral GPIOB base pointer */ #define GPIOB ((GPIO_Type *)GPIOB_BASE) #define GPIOB_BASE_PTR (GPIOB) /** Peripheral GPIOC base address */ #define GPIOC_BASE (0x400FF080u) /** Peripheral GPIOC base pointer */ #define GPIOC ((GPIO_Type *)GPIOC_BASE) #define GPIOC_BASE_PTR (GPIOC) /** Peripheral GPIOD base address */ #define GPIOD_BASE (0x400FF0C0u) /** Peripheral GPIOD base pointer */ #define GPIOD ((GPIO_Type *)GPIOD_BASE) #define GPIOD_BASE_PTR (GPIOD) /** Peripheral GPIOE base address */ #define GPIOE_BASE (0x400FF100u) /** Peripheral GPIOE base pointer */ #define GPIOE ((GPIO_Type *)GPIOE_BASE) #define GPIOE_BASE_PTR (GPIOE) /** Array initializer of GPIO peripheral base addresses */ #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } /** Array initializer of GPIO peripheral base pointers */ #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } /* ---------------------------------------------------------------------------- -- GPIO - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros * @{ */ /* GPIO - Register instance definitions */ /* GPIOA */ #define GPIOA_PDOR GPIO_PDOR_REG(GPIOA) #define GPIOA_PSOR GPIO_PSOR_REG(GPIOA) #define GPIOA_PCOR GPIO_PCOR_REG(GPIOA) #define GPIOA_PTOR GPIO_PTOR_REG(GPIOA) #define GPIOA_PDIR GPIO_PDIR_REG(GPIOA) #define GPIOA_PDDR GPIO_PDDR_REG(GPIOA) /* GPIOB */ #define GPIOB_PDOR GPIO_PDOR_REG(GPIOB) #define GPIOB_PSOR GPIO_PSOR_REG(GPIOB) #define GPIOB_PCOR GPIO_PCOR_REG(GPIOB) #define GPIOB_PTOR GPIO_PTOR_REG(GPIOB) #define GPIOB_PDIR GPIO_PDIR_REG(GPIOB) #define GPIOB_PDDR GPIO_PDDR_REG(GPIOB) /* GPIOC */ #define GPIOC_PDOR GPIO_PDOR_REG(GPIOC) #define GPIOC_PSOR GPIO_PSOR_REG(GPIOC) #define GPIOC_PCOR GPIO_PCOR_REG(GPIOC) #define GPIOC_PTOR GPIO_PTOR_REG(GPIOC) #define GPIOC_PDIR GPIO_PDIR_REG(GPIOC) #define GPIOC_PDDR GPIO_PDDR_REG(GPIOC) /* GPIOD */ #define GPIOD_PDOR GPIO_PDOR_REG(GPIOD) #define GPIOD_PSOR GPIO_PSOR_REG(GPIOD) #define GPIOD_PCOR GPIO_PCOR_REG(GPIOD) #define GPIOD_PTOR GPIO_PTOR_REG(GPIOD) #define GPIOD_PDIR GPIO_PDIR_REG(GPIOD) #define GPIOD_PDDR GPIO_PDDR_REG(GPIOD) /* GPIOE */ #define GPIOE_PDOR GPIO_PDOR_REG(GPIOE) #define GPIOE_PSOR GPIO_PSOR_REG(GPIOE) #define GPIOE_PCOR GPIO_PCOR_REG(GPIOE) #define GPIOE_PTOR GPIO_PTOR_REG(GPIOE) #define GPIOE_PDIR GPIO_PDIR_REG(GPIOE) #define GPIOE_PDDR GPIO_PDDR_REG(GPIOE) /*! * @} */ /* end of group GPIO_Register_Accessor_Macros */ /*! * @} */ /* end of group GPIO_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I2C Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer * @{ */ /** I2C - Register Layout Typedef */ typedef struct { __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */ } I2C_Type, *I2C_MemMapPtr; /* ---------------------------------------------------------------------------- -- I2C - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros * @{ */ /* I2C - Register accessors */ #define I2C_A1_REG(base) ((base)->A1) #define I2C_F_REG(base) ((base)->F) #define I2C_C1_REG(base) ((base)->C1) #define I2C_S_REG(base) ((base)->S) #define I2C_D_REG(base) ((base)->D) #define I2C_C2_REG(base) ((base)->C2) #define I2C_FLT_REG(base) ((base)->FLT) #define I2C_RA_REG(base) ((base)->RA) #define I2C_SMB_REG(base) ((base)->SMB) #define I2C_A2_REG(base) ((base)->A2) #define I2C_SLTH_REG(base) ((base)->SLTH) #define I2C_SLTL_REG(base) ((base)->SLTL) #define I2C_S2_REG(base) ((base)->S2) /*! * @} */ /* end of group I2C_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Register_Masks I2C Register Masks * @{ */ /* A1 Bit Fields */ #define I2C_A1_AD_MASK 0xFEu #define I2C_A1_AD_SHIFT 1 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK) /* F Bit Fields */ #define I2C_F_ICR_MASK 0x3Fu #define I2C_F_ICR_SHIFT 0 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK) #define I2C_F_MULT_MASK 0xC0u #define I2C_F_MULT_SHIFT 6 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK) /* C1 Bit Fields */ #define I2C_C1_DMAEN_MASK 0x1u #define I2C_C1_DMAEN_SHIFT 0 #define I2C_C1_WUEN_MASK 0x2u #define I2C_C1_WUEN_SHIFT 1 #define I2C_C1_RSTA_MASK 0x4u #define I2C_C1_RSTA_SHIFT 2 #define I2C_C1_TXAK_MASK 0x8u #define I2C_C1_TXAK_SHIFT 3 #define I2C_C1_TX_MASK 0x10u #define I2C_C1_TX_SHIFT 4 #define I2C_C1_MST_MASK 0x20u #define I2C_C1_MST_SHIFT 5 #define I2C_C1_IICIE_MASK 0x40u #define I2C_C1_IICIE_SHIFT 6 #define I2C_C1_IICEN_MASK 0x80u #define I2C_C1_IICEN_SHIFT 7 /* S Bit Fields */ #define I2C_S_RXAK_MASK 0x1u #define I2C_S_RXAK_SHIFT 0 #define I2C_S_IICIF_MASK 0x2u #define I2C_S_IICIF_SHIFT 1 #define I2C_S_SRW_MASK 0x4u #define I2C_S_SRW_SHIFT 2 #define I2C_S_RAM_MASK 0x8u #define I2C_S_RAM_SHIFT 3 #define I2C_S_ARBL_MASK 0x10u #define I2C_S_ARBL_SHIFT 4 #define I2C_S_BUSY_MASK 0x20u #define I2C_S_BUSY_SHIFT 5 #define I2C_S_IAAS_MASK 0x40u #define I2C_S_IAAS_SHIFT 6 #define I2C_S_TCF_MASK 0x80u #define I2C_S_TCF_SHIFT 7 /* D Bit Fields */ #define I2C_D_DATA_MASK 0xFFu #define I2C_D_DATA_SHIFT 0 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK) /* C2 Bit Fields */ #define I2C_C2_AD_MASK 0x7u #define I2C_C2_AD_SHIFT 0 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK) #define I2C_C2_RMEN_MASK 0x8u #define I2C_C2_RMEN_SHIFT 3 #define I2C_C2_SBRC_MASK 0x10u #define I2C_C2_SBRC_SHIFT 4 #define I2C_C2_HDRS_MASK 0x20u #define I2C_C2_HDRS_SHIFT 5 #define I2C_C2_ADEXT_MASK 0x40u #define I2C_C2_ADEXT_SHIFT 6 #define I2C_C2_GCAEN_MASK 0x80u #define I2C_C2_GCAEN_SHIFT 7 /* FLT Bit Fields */ #define I2C_FLT_FLT_MASK 0xFu #define I2C_FLT_FLT_SHIFT 0 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK) #define I2C_FLT_STARTF_MASK 0x10u #define I2C_FLT_STARTF_SHIFT 4 #define I2C_FLT_SSIE_MASK 0x20u #define I2C_FLT_SSIE_SHIFT 5 #define I2C_FLT_STOPF_MASK 0x40u #define I2C_FLT_STOPF_SHIFT 6 #define I2C_FLT_SHEN_MASK 0x80u #define I2C_FLT_SHEN_SHIFT 7 /* RA Bit Fields */ #define I2C_RA_RAD_MASK 0xFEu #define I2C_RA_RAD_SHIFT 1 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK) /* SMB Bit Fields */ #define I2C_SMB_SHTF2IE_MASK 0x1u #define I2C_SMB_SHTF2IE_SHIFT 0 #define I2C_SMB_SHTF2_MASK 0x2u #define I2C_SMB_SHTF2_SHIFT 1 #define I2C_SMB_SHTF1_MASK 0x4u #define I2C_SMB_SHTF1_SHIFT 2 #define I2C_SMB_SLTF_MASK 0x8u #define I2C_SMB_SLTF_SHIFT 3 #define I2C_SMB_TCKSEL_MASK 0x10u #define I2C_SMB_TCKSEL_SHIFT 4 #define I2C_SMB_SIICAEN_MASK 0x20u #define I2C_SMB_SIICAEN_SHIFT 5 #define I2C_SMB_ALERTEN_MASK 0x40u #define I2C_SMB_ALERTEN_SHIFT 6 #define I2C_SMB_FACK_MASK 0x80u #define I2C_SMB_FACK_SHIFT 7 /* A2 Bit Fields */ #define I2C_A2_SAD_MASK 0xFEu #define I2C_A2_SAD_SHIFT 1 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK) /* SLTH Bit Fields */ #define I2C_SLTH_SSLT_MASK 0xFFu #define I2C_SLTH_SSLT_SHIFT 0 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK) /* SLTL Bit Fields */ #define I2C_SLTL_SSLT_MASK 0xFFu #define I2C_SLTL_SSLT_SHIFT 0 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK) /* S2 Bit Fields */ #define I2C_S2_EMPTY_MASK 0x1u #define I2C_S2_EMPTY_SHIFT 0 #define I2C_S2_ERROR_MASK 0x2u #define I2C_S2_ERROR_SHIFT 1 /*! * @} */ /* end of group I2C_Register_Masks */ /* I2C - Peripheral instance base addresses */ /** Peripheral I2C0 base address */ #define I2C0_BASE (0x40066000u) /** Peripheral I2C0 base pointer */ #define I2C0 ((I2C_Type *)I2C0_BASE) #define I2C0_BASE_PTR (I2C0) /** Peripheral I2C1 base address */ #define I2C1_BASE (0x40067000u) /** Peripheral I2C1 base pointer */ #define I2C1 ((I2C_Type *)I2C1_BASE) #define I2C1_BASE_PTR (I2C1) /** Array initializer of I2C peripheral base addresses */ #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } /** Array initializer of I2C peripheral base pointers */ #define I2C_BASE_PTRS { I2C0, I2C1 } /** Interrupt vectors for the I2C peripheral type */ #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } /* ---------------------------------------------------------------------------- -- I2C - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros * @{ */ /* I2C - Register instance definitions */ /* I2C0 */ #define I2C0_A1 I2C_A1_REG(I2C0) #define I2C0_F I2C_F_REG(I2C0) #define I2C0_C1 I2C_C1_REG(I2C0) #define I2C0_S I2C_S_REG(I2C0) #define I2C0_D I2C_D_REG(I2C0) #define I2C0_C2 I2C_C2_REG(I2C0) #define I2C0_FLT I2C_FLT_REG(I2C0) #define I2C0_RA I2C_RA_REG(I2C0) #define I2C0_SMB I2C_SMB_REG(I2C0) #define I2C0_A2 I2C_A2_REG(I2C0) #define I2C0_SLTH I2C_SLTH_REG(I2C0) #define I2C0_SLTL I2C_SLTL_REG(I2C0) #define I2C0_S2 I2C_S2_REG(I2C0) /* I2C1 */ #define I2C1_A1 I2C_A1_REG(I2C1) #define I2C1_F I2C_F_REG(I2C1) #define I2C1_C1 I2C_C1_REG(I2C1) #define I2C1_S I2C_S_REG(I2C1) #define I2C1_D I2C_D_REG(I2C1) #define I2C1_C2 I2C_C2_REG(I2C1) #define I2C1_FLT I2C_FLT_REG(I2C1) #define I2C1_RA I2C_RA_REG(I2C1) #define I2C1_SMB I2C_SMB_REG(I2C1) #define I2C1_A2 I2C_A2_REG(I2C1) #define I2C1_SLTH I2C_SLTH_REG(I2C1) #define I2C1_SLTL I2C_SLTL_REG(I2C1) #define I2C1_S2 I2C_S2_REG(I2C1) /*! * @} */ /* end of group I2C_Register_Accessor_Macros */ /*! * @} */ /* end of group I2C_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- I2S Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer * @{ */ /** I2S - Register Layout Typedef */ typedef struct { __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ uint8_t RESERVED_0[4]; __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ uint8_t RESERVED_1[8]; __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_2[60]; __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ uint8_t RESERVED_3[28]; __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ uint8_t RESERVED_4[4]; __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ uint8_t RESERVED_5[8]; __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_6[60]; __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ uint8_t RESERVED_7[28]; __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ } I2S_Type, *I2S_MemMapPtr; /* ---------------------------------------------------------------------------- -- I2S - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros * @{ */ /* I2S - Register accessors */ #define I2S_TCSR_REG(base) ((base)->TCSR) #define I2S_TCR2_REG(base) ((base)->TCR2) #define I2S_TCR3_REG(base) ((base)->TCR3) #define I2S_TCR4_REG(base) ((base)->TCR4) #define I2S_TCR5_REG(base) ((base)->TCR5) #define I2S_TDR_REG(base,index) ((base)->TDR[index]) #define I2S_TMR_REG(base) ((base)->TMR) #define I2S_RCSR_REG(base) ((base)->RCSR) #define I2S_RCR2_REG(base) ((base)->RCR2) #define I2S_RCR3_REG(base) ((base)->RCR3) #define I2S_RCR4_REG(base) ((base)->RCR4) #define I2S_RCR5_REG(base) ((base)->RCR5) #define I2S_RDR_REG(base,index) ((base)->RDR[index]) #define I2S_RMR_REG(base) ((base)->RMR) #define I2S_MCR_REG(base) ((base)->MCR) /*! * @} */ /* end of group I2S_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /* TCSR Bit Fields */ #define I2S_TCSR_FWDE_MASK 0x2u #define I2S_TCSR_FWDE_SHIFT 1 #define I2S_TCSR_FWIE_MASK 0x200u #define I2S_TCSR_FWIE_SHIFT 9 #define I2S_TCSR_FEIE_MASK 0x400u #define I2S_TCSR_FEIE_SHIFT 10 #define I2S_TCSR_SEIE_MASK 0x800u #define I2S_TCSR_SEIE_SHIFT 11 #define I2S_TCSR_WSIE_MASK 0x1000u #define I2S_TCSR_WSIE_SHIFT 12 #define I2S_TCSR_FWF_MASK 0x20000u #define I2S_TCSR_FWF_SHIFT 17 #define I2S_TCSR_FEF_MASK 0x40000u #define I2S_TCSR_FEF_SHIFT 18 #define I2S_TCSR_SEF_MASK 0x80000u #define I2S_TCSR_SEF_SHIFT 19 #define I2S_TCSR_WSF_MASK 0x100000u #define I2S_TCSR_WSF_SHIFT 20 #define I2S_TCSR_SR_MASK 0x1000000u #define I2S_TCSR_SR_SHIFT 24 #define I2S_TCSR_FR_MASK 0x2000000u #define I2S_TCSR_FR_SHIFT 25 #define I2S_TCSR_BCE_MASK 0x10000000u #define I2S_TCSR_BCE_SHIFT 28 #define I2S_TCSR_DBGE_MASK 0x20000000u #define I2S_TCSR_DBGE_SHIFT 29 #define I2S_TCSR_STOPE_MASK 0x40000000u #define I2S_TCSR_STOPE_SHIFT 30 #define I2S_TCSR_TE_MASK 0x80000000u #define I2S_TCSR_TE_SHIFT 31 /* TCR2 Bit Fields */ #define I2S_TCR2_DIV_MASK 0xFFu #define I2S_TCR2_DIV_SHIFT 0 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK) #define I2S_TCR2_BCD_MASK 0x1000000u #define I2S_TCR2_BCD_SHIFT 24 #define I2S_TCR2_BCP_MASK 0x2000000u #define I2S_TCR2_BCP_SHIFT 25 #define I2S_TCR2_MSEL_MASK 0xC000000u #define I2S_TCR2_MSEL_SHIFT 26 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK) #define I2S_TCR2_BCI_MASK 0x10000000u #define I2S_TCR2_BCI_SHIFT 28 #define I2S_TCR2_BCS_MASK 0x20000000u #define I2S_TCR2_BCS_SHIFT 29 #define I2S_TCR2_SYNC_MASK 0xC0000000u #define I2S_TCR2_SYNC_SHIFT 30 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK) /* TCR3 Bit Fields */ #define I2S_TCR3_WDFL_MASK 0x1u #define I2S_TCR3_WDFL_SHIFT 0 #define I2S_TCR3_TCE_MASK 0x10000u #define I2S_TCR3_TCE_SHIFT 16 /* TCR4 Bit Fields */ #define I2S_TCR4_FSD_MASK 0x1u #define I2S_TCR4_FSD_SHIFT 0 #define I2S_TCR4_FSP_MASK 0x2u #define I2S_TCR4_FSP_SHIFT 1 #define I2S_TCR4_ONDEM_MASK 0x4u #define I2S_TCR4_ONDEM_SHIFT 2 #define I2S_TCR4_FSE_MASK 0x8u #define I2S_TCR4_FSE_SHIFT 3 #define I2S_TCR4_MF_MASK 0x10u #define I2S_TCR4_MF_SHIFT 4 #define I2S_TCR4_SYWD_MASK 0x1F00u #define I2S_TCR4_SYWD_SHIFT 8 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK) #define I2S_TCR4_FRSZ_MASK 0x10000u #define I2S_TCR4_FRSZ_SHIFT 16 #define I2S_TCR4_FPACK_MASK 0x3000000u #define I2S_TCR4_FPACK_SHIFT 24 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK) #define I2S_TCR4_FCONT_MASK 0x10000000u #define I2S_TCR4_FCONT_SHIFT 28 /* TCR5 Bit Fields */ #define I2S_TCR5_FBT_MASK 0x1F00u #define I2S_TCR5_FBT_SHIFT 8 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK) #define I2S_TCR5_W0W_MASK 0x1F0000u #define I2S_TCR5_W0W_SHIFT 16 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK) #define I2S_TCR5_WNW_MASK 0x1F000000u #define I2S_TCR5_WNW_SHIFT 24 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK) /* TDR Bit Fields */ #define I2S_TDR_TDR_MASK 0xFFFFFFFFu #define I2S_TDR_TDR_SHIFT 0 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK) /* TMR Bit Fields */ #define I2S_TMR_TWM_MASK 0x3u #define I2S_TMR_TWM_SHIFT 0 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK) /* RCSR Bit Fields */ #define I2S_RCSR_FWDE_MASK 0x2u #define I2S_RCSR_FWDE_SHIFT 1 #define I2S_RCSR_FWIE_MASK 0x200u #define I2S_RCSR_FWIE_SHIFT 9 #define I2S_RCSR_FEIE_MASK 0x400u #define I2S_RCSR_FEIE_SHIFT 10 #define I2S_RCSR_SEIE_MASK 0x800u #define I2S_RCSR_SEIE_SHIFT 11 #define I2S_RCSR_WSIE_MASK 0x1000u #define I2S_RCSR_WSIE_SHIFT 12 #define I2S_RCSR_FWF_MASK 0x20000u #define I2S_RCSR_FWF_SHIFT 17 #define I2S_RCSR_FEF_MASK 0x40000u #define I2S_RCSR_FEF_SHIFT 18 #define I2S_RCSR_SEF_MASK 0x80000u #define I2S_RCSR_SEF_SHIFT 19 #define I2S_RCSR_WSF_MASK 0x100000u #define I2S_RCSR_WSF_SHIFT 20 #define I2S_RCSR_SR_MASK 0x1000000u #define I2S_RCSR_SR_SHIFT 24 #define I2S_RCSR_FR_MASK 0x2000000u #define I2S_RCSR_FR_SHIFT 25 #define I2S_RCSR_BCE_MASK 0x10000000u #define I2S_RCSR_BCE_SHIFT 28 #define I2S_RCSR_DBGE_MASK 0x20000000u #define I2S_RCSR_DBGE_SHIFT 29 #define I2S_RCSR_STOPE_MASK 0x40000000u #define I2S_RCSR_STOPE_SHIFT 30 #define I2S_RCSR_RE_MASK 0x80000000u #define I2S_RCSR_RE_SHIFT 31 /* RCR2 Bit Fields */ #define I2S_RCR2_DIV_MASK 0xFFu #define I2S_RCR2_DIV_SHIFT 0 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK) #define I2S_RCR2_BCD_MASK 0x1000000u #define I2S_RCR2_BCD_SHIFT 24 #define I2S_RCR2_BCP_MASK 0x2000000u #define I2S_RCR2_BCP_SHIFT 25 #define I2S_RCR2_MSEL_MASK 0xC000000u #define I2S_RCR2_MSEL_SHIFT 26 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK) #define I2S_RCR2_BCI_MASK 0x10000000u #define I2S_RCR2_BCI_SHIFT 28 #define I2S_RCR2_BCS_MASK 0x20000000u #define I2S_RCR2_BCS_SHIFT 29 #define I2S_RCR2_SYNC_MASK 0xC0000000u #define I2S_RCR2_SYNC_SHIFT 30 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK) /* RCR3 Bit Fields */ #define I2S_RCR3_WDFL_MASK 0x1u #define I2S_RCR3_WDFL_SHIFT 0 #define I2S_RCR3_RCE_MASK 0x10000u #define I2S_RCR3_RCE_SHIFT 16 /* RCR4 Bit Fields */ #define I2S_RCR4_FSD_MASK 0x1u #define I2S_RCR4_FSD_SHIFT 0 #define I2S_RCR4_FSP_MASK 0x2u #define I2S_RCR4_FSP_SHIFT 1 #define I2S_RCR4_ONDEM_MASK 0x4u #define I2S_RCR4_ONDEM_SHIFT 2 #define I2S_RCR4_FSE_MASK 0x8u #define I2S_RCR4_FSE_SHIFT 3 #define I2S_RCR4_MF_MASK 0x10u #define I2S_RCR4_MF_SHIFT 4 #define I2S_RCR4_SYWD_MASK 0x1F00u #define I2S_RCR4_SYWD_SHIFT 8 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK) #define I2S_RCR4_FRSZ_MASK 0x10000u #define I2S_RCR4_FRSZ_SHIFT 16 #define I2S_RCR4_FPACK_MASK 0x3000000u #define I2S_RCR4_FPACK_SHIFT 24 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK) #define I2S_RCR4_FCONT_MASK 0x10000000u #define I2S_RCR4_FCONT_SHIFT 28 /* RCR5 Bit Fields */ #define I2S_RCR5_FBT_MASK 0x1F00u #define I2S_RCR5_FBT_SHIFT 8 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK) #define I2S_RCR5_W0W_MASK 0x1F0000u #define I2S_RCR5_W0W_SHIFT 16 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK) #define I2S_RCR5_WNW_MASK 0x1F000000u #define I2S_RCR5_WNW_SHIFT 24 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK) /* RDR Bit Fields */ #define I2S_RDR_RDR_MASK 0xFFFFFFFFu #define I2S_RDR_RDR_SHIFT 0 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK) /* RMR Bit Fields */ #define I2S_RMR_RWM_MASK 0x3u #define I2S_RMR_RWM_SHIFT 0 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK) /* MCR Bit Fields */ #define I2S_MCR_MICS_MASK 0x3000000u #define I2S_MCR_MICS_SHIFT 24 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK) #define I2S_MCR_MOE_MASK 0x40000000u #define I2S_MCR_MOE_SHIFT 30 #define I2S_MCR_DUF_MASK 0x80000000u #define I2S_MCR_DUF_SHIFT 31 /*! * @} */ /* end of group I2S_Register_Masks */ /* I2S - Peripheral instance base addresses */ /** Peripheral I2S0 base address */ #define I2S0_BASE (0x4002F000u) /** Peripheral I2S0 base pointer */ #define I2S0 ((I2S_Type *)I2S0_BASE) #define I2S0_BASE_PTR (I2S0) /** Array initializer of I2S peripheral base addresses */ #define I2S_BASE_ADDRS { I2S0_BASE } /** Array initializer of I2S peripheral base pointers */ #define I2S_BASE_PTRS { I2S0 } /** Interrupt vectors for the I2S peripheral type */ #define I2S_RX_IRQS { I2S0_IRQn } #define I2S_TX_IRQS { I2S0_IRQn } /* ---------------------------------------------------------------------------- -- I2S - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros * @{ */ /* I2S - Register instance definitions */ /* I2S0 */ #define I2S0_TCSR I2S_TCSR_REG(I2S0) #define I2S0_TCR2 I2S_TCR2_REG(I2S0) #define I2S0_TCR3 I2S_TCR3_REG(I2S0) #define I2S0_TCR4 I2S_TCR4_REG(I2S0) #define I2S0_TCR5 I2S_TCR5_REG(I2S0) #define I2S0_TDR0 I2S_TDR_REG(I2S0,0) #define I2S0_TMR I2S_TMR_REG(I2S0) #define I2S0_RCSR I2S_RCSR_REG(I2S0) #define I2S0_RCR2 I2S_RCR2_REG(I2S0) #define I2S0_RCR3 I2S_RCR3_REG(I2S0) #define I2S0_RCR4 I2S_RCR4_REG(I2S0) #define I2S0_RCR5 I2S_RCR5_REG(I2S0) #define I2S0_RDR0 I2S_RDR_REG(I2S0,0) #define I2S0_RMR I2S_RMR_REG(I2S0) #define I2S0_MCR I2S_MCR_REG(I2S0) /* I2S - Register array accessors */ #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index) #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index) /*! * @} */ /* end of group I2S_Register_Accessor_Macros */ /*! * @} */ /* end of group I2S_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LCD Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer * @{ */ /** LCD - Register Layout Typedef */ typedef struct { __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */ __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */ __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */ __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */ __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */ __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */ union { /* offset: 0x20 */ __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */ __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */ }; } LCD_Type, *LCD_MemMapPtr; /* ---------------------------------------------------------------------------- -- LCD - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros * @{ */ /* LCD - Register accessors */ #define LCD_GCR_REG(base) ((base)->GCR) #define LCD_AR_REG(base) ((base)->AR) #define LCD_FDCR_REG(base) ((base)->FDCR) #define LCD_FDSR_REG(base) ((base)->FDSR) #define LCD_PEN_REG(base,index) ((base)->PEN[index]) #define LCD_BPEN_REG(base,index) ((base)->BPEN[index]) #define LCD_WF_REG(base,index2) ((base)->WF[index2]) #define LCD_WF8B_REG(base,index2) ((base)->WF8B[index2]) /*! * @} */ /* end of group LCD_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LCD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LCD_Register_Masks LCD Register Masks * @{ */ /* GCR Bit Fields */ #define LCD_GCR_DUTY_MASK 0x7u #define LCD_GCR_DUTY_SHIFT 0 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK) #define LCD_GCR_LCLK_MASK 0x38u #define LCD_GCR_LCLK_SHIFT 3 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK) #define LCD_GCR_SOURCE_MASK 0x40u #define LCD_GCR_SOURCE_SHIFT 6 #define LCD_GCR_LCDEN_MASK 0x80u #define LCD_GCR_LCDEN_SHIFT 7 #define LCD_GCR_LCDSTP_MASK 0x100u #define LCD_GCR_LCDSTP_SHIFT 8 #define LCD_GCR_LCDDOZE_MASK 0x200u #define LCD_GCR_LCDDOZE_SHIFT 9 #define LCD_GCR_FFR_MASK 0x400u #define LCD_GCR_FFR_SHIFT 10 #define LCD_GCR_ALTSOURCE_MASK 0x800u #define LCD_GCR_ALTSOURCE_SHIFT 11 #define LCD_GCR_ALTDIV_MASK 0x3000u #define LCD_GCR_ALTDIV_SHIFT 12 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK) #define LCD_GCR_FDCIEN_MASK 0x4000u #define LCD_GCR_FDCIEN_SHIFT 14 #define LCD_GCR_PADSAFE_MASK 0x8000u #define LCD_GCR_PADSAFE_SHIFT 15 #define LCD_GCR_VSUPPLY_MASK 0x20000u #define LCD_GCR_VSUPPLY_SHIFT 17 #define LCD_GCR_LADJ_MASK 0x300000u #define LCD_GCR_LADJ_SHIFT 20 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK) #define LCD_GCR_CPSEL_MASK 0x800000u #define LCD_GCR_CPSEL_SHIFT 23 #define LCD_GCR_RVTRIM_MASK 0xF000000u #define LCD_GCR_RVTRIM_SHIFT 24 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK) #define LCD_GCR_RVEN_MASK 0x80000000u #define LCD_GCR_RVEN_SHIFT 31 /* AR Bit Fields */ #define LCD_AR_BRATE_MASK 0x7u #define LCD_AR_BRATE_SHIFT 0 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK) #define LCD_AR_BMODE_MASK 0x8u #define LCD_AR_BMODE_SHIFT 3 #define LCD_AR_BLANK_MASK 0x20u #define LCD_AR_BLANK_SHIFT 5 #define LCD_AR_ALT_MASK 0x40u #define LCD_AR_ALT_SHIFT 6 #define LCD_AR_BLINK_MASK 0x80u #define LCD_AR_BLINK_SHIFT 7 /* FDCR Bit Fields */ #define LCD_FDCR_FDPINID_MASK 0x3Fu #define LCD_FDCR_FDPINID_SHIFT 0 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK) #define LCD_FDCR_FDBPEN_MASK 0x40u #define LCD_FDCR_FDBPEN_SHIFT 6 #define LCD_FDCR_FDEN_MASK 0x80u #define LCD_FDCR_FDEN_SHIFT 7 #define LCD_FDCR_FDSWW_MASK 0xE00u #define LCD_FDCR_FDSWW_SHIFT 9 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK) #define LCD_FDCR_FDPRS_MASK 0x7000u #define LCD_FDCR_FDPRS_SHIFT 12 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK) /* FDSR Bit Fields */ #define LCD_FDSR_FDCNT_MASK 0xFFu #define LCD_FDSR_FDCNT_SHIFT 0 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK) #define LCD_FDSR_FDCF_MASK 0x8000u #define LCD_FDSR_FDCF_SHIFT 15 /* PEN Bit Fields */ #define LCD_PEN_PEN_MASK 0xFFFFFFFFu #define LCD_PEN_PEN_SHIFT 0 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK) /* BPEN Bit Fields */ #define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu #define LCD_BPEN_BPEN_SHIFT 0 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK) /* WF Bit Fields */ #define LCD_WF_WF0_MASK 0xFFu #define LCD_WF_WF0_SHIFT 0 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK) #define LCD_WF_WF60_MASK 0xFFu #define LCD_WF_WF60_SHIFT 0 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK) #define LCD_WF_WF56_MASK 0xFFu #define LCD_WF_WF56_SHIFT 0 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK) #define LCD_WF_WF52_MASK 0xFFu #define LCD_WF_WF52_SHIFT 0 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK) #define LCD_WF_WF4_MASK 0xFFu #define LCD_WF_WF4_SHIFT 0 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK) #define LCD_WF_WF48_MASK 0xFFu #define LCD_WF_WF48_SHIFT 0 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK) #define LCD_WF_WF44_MASK 0xFFu #define LCD_WF_WF44_SHIFT 0 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK) #define LCD_WF_WF40_MASK 0xFFu #define LCD_WF_WF40_SHIFT 0 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK) #define LCD_WF_WF8_MASK 0xFFu #define LCD_WF_WF8_SHIFT 0 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK) #define LCD_WF_WF36_MASK 0xFFu #define LCD_WF_WF36_SHIFT 0 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK) #define LCD_WF_WF32_MASK 0xFFu #define LCD_WF_WF32_SHIFT 0 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK) #define LCD_WF_WF28_MASK 0xFFu #define LCD_WF_WF28_SHIFT 0 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK) #define LCD_WF_WF12_MASK 0xFFu #define LCD_WF_WF12_SHIFT 0 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK) #define LCD_WF_WF24_MASK 0xFFu #define LCD_WF_WF24_SHIFT 0 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK) #define LCD_WF_WF20_MASK 0xFFu #define LCD_WF_WF20_SHIFT 0 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK) #define LCD_WF_WF16_MASK 0xFFu #define LCD_WF_WF16_SHIFT 0 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK) #define LCD_WF_WF5_MASK 0xFF00u #define LCD_WF_WF5_SHIFT 8 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK) #define LCD_WF_WF49_MASK 0xFF00u #define LCD_WF_WF49_SHIFT 8 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK) #define LCD_WF_WF45_MASK 0xFF00u #define LCD_WF_WF45_SHIFT 8 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK) #define LCD_WF_WF61_MASK 0xFF00u #define LCD_WF_WF61_SHIFT 8 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK) #define LCD_WF_WF25_MASK 0xFF00u #define LCD_WF_WF25_SHIFT 8 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK) #define LCD_WF_WF17_MASK 0xFF00u #define LCD_WF_WF17_SHIFT 8 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK) #define LCD_WF_WF41_MASK 0xFF00u #define LCD_WF_WF41_SHIFT 8 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK) #define LCD_WF_WF13_MASK 0xFF00u #define LCD_WF_WF13_SHIFT 8 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK) #define LCD_WF_WF57_MASK 0xFF00u #define LCD_WF_WF57_SHIFT 8 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK) #define LCD_WF_WF53_MASK 0xFF00u #define LCD_WF_WF53_SHIFT 8 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK) #define LCD_WF_WF37_MASK 0xFF00u #define LCD_WF_WF37_SHIFT 8 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK) #define LCD_WF_WF9_MASK 0xFF00u #define LCD_WF_WF9_SHIFT 8 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK) #define LCD_WF_WF1_MASK 0xFF00u #define LCD_WF_WF1_SHIFT 8 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK) #define LCD_WF_WF29_MASK 0xFF00u #define LCD_WF_WF29_SHIFT 8 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK) #define LCD_WF_WF33_MASK 0xFF00u #define LCD_WF_WF33_SHIFT 8 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK) #define LCD_WF_WF21_MASK 0xFF00u #define LCD_WF_WF21_SHIFT 8 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK) #define LCD_WF_WF26_MASK 0xFF0000u #define LCD_WF_WF26_SHIFT 16 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK) #define LCD_WF_WF46_MASK 0xFF0000u #define LCD_WF_WF46_SHIFT 16 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK) #define LCD_WF_WF6_MASK 0xFF0000u #define LCD_WF_WF6_SHIFT 16 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK) #define LCD_WF_WF42_MASK 0xFF0000u #define LCD_WF_WF42_SHIFT 16 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK) #define LCD_WF_WF18_MASK 0xFF0000u #define LCD_WF_WF18_SHIFT 16 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK) #define LCD_WF_WF38_MASK 0xFF0000u #define LCD_WF_WF38_SHIFT 16 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK) #define LCD_WF_WF22_MASK 0xFF0000u #define LCD_WF_WF22_SHIFT 16 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK) #define LCD_WF_WF34_MASK 0xFF0000u #define LCD_WF_WF34_SHIFT 16 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK) #define LCD_WF_WF50_MASK 0xFF0000u #define LCD_WF_WF50_SHIFT 16 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK) #define LCD_WF_WF14_MASK 0xFF0000u #define LCD_WF_WF14_SHIFT 16 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK) #define LCD_WF_WF54_MASK 0xFF0000u #define LCD_WF_WF54_SHIFT 16 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK) #define LCD_WF_WF2_MASK 0xFF0000u #define LCD_WF_WF2_SHIFT 16 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK) #define LCD_WF_WF58_MASK 0xFF0000u #define LCD_WF_WF58_SHIFT 16 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK) #define LCD_WF_WF30_MASK 0xFF0000u #define LCD_WF_WF30_SHIFT 16 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK) #define LCD_WF_WF62_MASK 0xFF0000u #define LCD_WF_WF62_SHIFT 16 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK) #define LCD_WF_WF10_MASK 0xFF0000u #define LCD_WF_WF10_SHIFT 16 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK) #define LCD_WF_WF63_MASK 0xFF000000u #define LCD_WF_WF63_SHIFT 24 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK) #define LCD_WF_WF59_MASK 0xFF000000u #define LCD_WF_WF59_SHIFT 24 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK) #define LCD_WF_WF55_MASK 0xFF000000u #define LCD_WF_WF55_SHIFT 24 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK) #define LCD_WF_WF3_MASK 0xFF000000u #define LCD_WF_WF3_SHIFT 24 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK) #define LCD_WF_WF51_MASK 0xFF000000u #define LCD_WF_WF51_SHIFT 24 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK) #define LCD_WF_WF47_MASK 0xFF000000u #define LCD_WF_WF47_SHIFT 24 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK) #define LCD_WF_WF43_MASK 0xFF000000u #define LCD_WF_WF43_SHIFT 24 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK) #define LCD_WF_WF7_MASK 0xFF000000u #define LCD_WF_WF7_SHIFT 24 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK) #define LCD_WF_WF39_MASK 0xFF000000u #define LCD_WF_WF39_SHIFT 24 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK) #define LCD_WF_WF35_MASK 0xFF000000u #define LCD_WF_WF35_SHIFT 24 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK) #define LCD_WF_WF31_MASK 0xFF000000u #define LCD_WF_WF31_SHIFT 24 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK) #define LCD_WF_WF11_MASK 0xFF000000u #define LCD_WF_WF11_SHIFT 24 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK) #define LCD_WF_WF27_MASK 0xFF000000u #define LCD_WF_WF27_SHIFT 24 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK) #define LCD_WF_WF23_MASK 0xFF000000u #define LCD_WF_WF23_SHIFT 24 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK) #define LCD_WF_WF19_MASK 0xFF000000u #define LCD_WF_WF19_SHIFT 24 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK) #define LCD_WF_WF15_MASK 0xFF000000u #define LCD_WF_WF15_SHIFT 24 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK) /* WF8B Bit Fields */ #define LCD_WF8B_BPALCD0_MASK 0x1u #define LCD_WF8B_BPALCD0_SHIFT 0 #define LCD_WF8B_BPALCD63_MASK 0x1u #define LCD_WF8B_BPALCD63_SHIFT 0 #define LCD_WF8B_BPALCD62_MASK 0x1u #define LCD_WF8B_BPALCD62_SHIFT 0 #define LCD_WF8B_BPALCD61_MASK 0x1u #define LCD_WF8B_BPALCD61_SHIFT 0 #define LCD_WF8B_BPALCD60_MASK 0x1u #define LCD_WF8B_BPALCD60_SHIFT 0 #define LCD_WF8B_BPALCD59_MASK 0x1u #define LCD_WF8B_BPALCD59_SHIFT 0 #define LCD_WF8B_BPALCD58_MASK 0x1u #define LCD_WF8B_BPALCD58_SHIFT 0 #define LCD_WF8B_BPALCD57_MASK 0x1u #define LCD_WF8B_BPALCD57_SHIFT 0 #define LCD_WF8B_BPALCD1_MASK 0x1u #define LCD_WF8B_BPALCD1_SHIFT 0 #define LCD_WF8B_BPALCD56_MASK 0x1u #define LCD_WF8B_BPALCD56_SHIFT 0 #define LCD_WF8B_BPALCD55_MASK 0x1u #define LCD_WF8B_BPALCD55_SHIFT 0 #define LCD_WF8B_BPALCD54_MASK 0x1u #define LCD_WF8B_BPALCD54_SHIFT 0 #define LCD_WF8B_BPALCD53_MASK 0x1u #define LCD_WF8B_BPALCD53_SHIFT 0 #define LCD_WF8B_BPALCD52_MASK 0x1u #define LCD_WF8B_BPALCD52_SHIFT 0 #define LCD_WF8B_BPALCD51_MASK 0x1u #define LCD_WF8B_BPALCD51_SHIFT 0 #define LCD_WF8B_BPALCD50_MASK 0x1u #define LCD_WF8B_BPALCD50_SHIFT 0 #define LCD_WF8B_BPALCD2_MASK 0x1u #define LCD_WF8B_BPALCD2_SHIFT 0 #define LCD_WF8B_BPALCD49_MASK 0x1u #define LCD_WF8B_BPALCD49_SHIFT 0 #define LCD_WF8B_BPALCD48_MASK 0x1u #define LCD_WF8B_BPALCD48_SHIFT 0 #define LCD_WF8B_BPALCD47_MASK 0x1u #define LCD_WF8B_BPALCD47_SHIFT 0 #define LCD_WF8B_BPALCD46_MASK 0x1u #define LCD_WF8B_BPALCD46_SHIFT 0 #define LCD_WF8B_BPALCD45_MASK 0x1u #define LCD_WF8B_BPALCD45_SHIFT 0 #define LCD_WF8B_BPALCD44_MASK 0x1u #define LCD_WF8B_BPALCD44_SHIFT 0 #define LCD_WF8B_BPALCD43_MASK 0x1u #define LCD_WF8B_BPALCD43_SHIFT 0 #define LCD_WF8B_BPALCD3_MASK 0x1u #define LCD_WF8B_BPALCD3_SHIFT 0 #define LCD_WF8B_BPALCD42_MASK 0x1u #define LCD_WF8B_BPALCD42_SHIFT 0 #define LCD_WF8B_BPALCD41_MASK 0x1u #define LCD_WF8B_BPALCD41_SHIFT 0 #define LCD_WF8B_BPALCD40_MASK 0x1u #define LCD_WF8B_BPALCD40_SHIFT 0 #define LCD_WF8B_BPALCD39_MASK 0x1u #define LCD_WF8B_BPALCD39_SHIFT 0 #define LCD_WF8B_BPALCD38_MASK 0x1u #define LCD_WF8B_BPALCD38_SHIFT 0 #define LCD_WF8B_BPALCD37_MASK 0x1u #define LCD_WF8B_BPALCD37_SHIFT 0 #define LCD_WF8B_BPALCD36_MASK 0x1u #define LCD_WF8B_BPALCD36_SHIFT 0 #define LCD_WF8B_BPALCD4_MASK 0x1u #define LCD_WF8B_BPALCD4_SHIFT 0 #define LCD_WF8B_BPALCD35_MASK 0x1u #define LCD_WF8B_BPALCD35_SHIFT 0 #define LCD_WF8B_BPALCD34_MASK 0x1u #define LCD_WF8B_BPALCD34_SHIFT 0 #define LCD_WF8B_BPALCD33_MASK 0x1u #define LCD_WF8B_BPALCD33_SHIFT 0 #define LCD_WF8B_BPALCD32_MASK 0x1u #define LCD_WF8B_BPALCD32_SHIFT 0 #define LCD_WF8B_BPALCD31_MASK 0x1u #define LCD_WF8B_BPALCD31_SHIFT 0 #define LCD_WF8B_BPALCD30_MASK 0x1u #define LCD_WF8B_BPALCD30_SHIFT 0 #define LCD_WF8B_BPALCD29_MASK 0x1u #define LCD_WF8B_BPALCD29_SHIFT 0 #define LCD_WF8B_BPALCD5_MASK 0x1u #define LCD_WF8B_BPALCD5_SHIFT 0 #define LCD_WF8B_BPALCD28_MASK 0x1u #define LCD_WF8B_BPALCD28_SHIFT 0 #define LCD_WF8B_BPALCD27_MASK 0x1u #define LCD_WF8B_BPALCD27_SHIFT 0 #define LCD_WF8B_BPALCD26_MASK 0x1u #define LCD_WF8B_BPALCD26_SHIFT 0 #define LCD_WF8B_BPALCD25_MASK 0x1u #define LCD_WF8B_BPALCD25_SHIFT 0 #define LCD_WF8B_BPALCD24_MASK 0x1u #define LCD_WF8B_BPALCD24_SHIFT 0 #define LCD_WF8B_BPALCD23_MASK 0x1u #define LCD_WF8B_BPALCD23_SHIFT 0 #define LCD_WF8B_BPALCD22_MASK 0x1u #define LCD_WF8B_BPALCD22_SHIFT 0 #define LCD_WF8B_BPALCD6_MASK 0x1u #define LCD_WF8B_BPALCD6_SHIFT 0 #define LCD_WF8B_BPALCD21_MASK 0x1u #define LCD_WF8B_BPALCD21_SHIFT 0 #define LCD_WF8B_BPALCD20_MASK 0x1u #define LCD_WF8B_BPALCD20_SHIFT 0 #define LCD_WF8B_BPALCD19_MASK 0x1u #define LCD_WF8B_BPALCD19_SHIFT 0 #define LCD_WF8B_BPALCD18_MASK 0x1u #define LCD_WF8B_BPALCD18_SHIFT 0 #define LCD_WF8B_BPALCD17_MASK 0x1u #define LCD_WF8B_BPALCD17_SHIFT 0 #define LCD_WF8B_BPALCD16_MASK 0x1u #define LCD_WF8B_BPALCD16_SHIFT 0 #define LCD_WF8B_BPALCD15_MASK 0x1u #define LCD_WF8B_BPALCD15_SHIFT 0 #define LCD_WF8B_BPALCD7_MASK 0x1u #define LCD_WF8B_BPALCD7_SHIFT 0 #define LCD_WF8B_BPALCD14_MASK 0x1u #define LCD_WF8B_BPALCD14_SHIFT 0 #define LCD_WF8B_BPALCD13_MASK 0x1u #define LCD_WF8B_BPALCD13_SHIFT 0 #define LCD_WF8B_BPALCD12_MASK 0x1u #define LCD_WF8B_BPALCD12_SHIFT 0 #define LCD_WF8B_BPALCD11_MASK 0x1u #define LCD_WF8B_BPALCD11_SHIFT 0 #define LCD_WF8B_BPALCD10_MASK 0x1u #define LCD_WF8B_BPALCD10_SHIFT 0 #define LCD_WF8B_BPALCD9_MASK 0x1u #define LCD_WF8B_BPALCD9_SHIFT 0 #define LCD_WF8B_BPALCD8_MASK 0x1u #define LCD_WF8B_BPALCD8_SHIFT 0 #define LCD_WF8B_BPBLCD1_MASK 0x2u #define LCD_WF8B_BPBLCD1_SHIFT 1 #define LCD_WF8B_BPBLCD32_MASK 0x2u #define LCD_WF8B_BPBLCD32_SHIFT 1 #define LCD_WF8B_BPBLCD30_MASK 0x2u #define LCD_WF8B_BPBLCD30_SHIFT 1 #define LCD_WF8B_BPBLCD60_MASK 0x2u #define LCD_WF8B_BPBLCD60_SHIFT 1 #define LCD_WF8B_BPBLCD24_MASK 0x2u #define LCD_WF8B_BPBLCD24_SHIFT 1 #define LCD_WF8B_BPBLCD28_MASK 0x2u #define LCD_WF8B_BPBLCD28_SHIFT 1 #define LCD_WF8B_BPBLCD23_MASK 0x2u #define LCD_WF8B_BPBLCD23_SHIFT 1 #define LCD_WF8B_BPBLCD48_MASK 0x2u #define LCD_WF8B_BPBLCD48_SHIFT 1 #define LCD_WF8B_BPBLCD10_MASK 0x2u #define LCD_WF8B_BPBLCD10_SHIFT 1 #define LCD_WF8B_BPBLCD15_MASK 0x2u #define LCD_WF8B_BPBLCD15_SHIFT 1 #define LCD_WF8B_BPBLCD36_MASK 0x2u #define LCD_WF8B_BPBLCD36_SHIFT 1 #define LCD_WF8B_BPBLCD44_MASK 0x2u #define LCD_WF8B_BPBLCD44_SHIFT 1 #define LCD_WF8B_BPBLCD62_MASK 0x2u #define LCD_WF8B_BPBLCD62_SHIFT 1 #define LCD_WF8B_BPBLCD53_MASK 0x2u #define LCD_WF8B_BPBLCD53_SHIFT 1 #define LCD_WF8B_BPBLCD22_MASK 0x2u #define LCD_WF8B_BPBLCD22_SHIFT 1 #define LCD_WF8B_BPBLCD47_MASK 0x2u #define LCD_WF8B_BPBLCD47_SHIFT 1 #define LCD_WF8B_BPBLCD33_MASK 0x2u #define LCD_WF8B_BPBLCD33_SHIFT 1 #define LCD_WF8B_BPBLCD2_MASK 0x2u #define LCD_WF8B_BPBLCD2_SHIFT 1 #define LCD_WF8B_BPBLCD49_MASK 0x2u #define LCD_WF8B_BPBLCD49_SHIFT 1 #define LCD_WF8B_BPBLCD0_MASK 0x2u #define LCD_WF8B_BPBLCD0_SHIFT 1 #define LCD_WF8B_BPBLCD55_MASK 0x2u #define LCD_WF8B_BPBLCD55_SHIFT 1 #define LCD_WF8B_BPBLCD56_MASK 0x2u #define LCD_WF8B_BPBLCD56_SHIFT 1 #define LCD_WF8B_BPBLCD21_MASK 0x2u #define LCD_WF8B_BPBLCD21_SHIFT 1 #define LCD_WF8B_BPBLCD6_MASK 0x2u #define LCD_WF8B_BPBLCD6_SHIFT 1 #define LCD_WF8B_BPBLCD29_MASK 0x2u #define LCD_WF8B_BPBLCD29_SHIFT 1 #define LCD_WF8B_BPBLCD25_MASK 0x2u #define LCD_WF8B_BPBLCD25_SHIFT 1 #define LCD_WF8B_BPBLCD8_MASK 0x2u #define LCD_WF8B_BPBLCD8_SHIFT 1 #define LCD_WF8B_BPBLCD54_MASK 0x2u #define LCD_WF8B_BPBLCD54_SHIFT 1 #define LCD_WF8B_BPBLCD38_MASK 0x2u #define LCD_WF8B_BPBLCD38_SHIFT 1 #define LCD_WF8B_BPBLCD43_MASK 0x2u #define LCD_WF8B_BPBLCD43_SHIFT 1 #define LCD_WF8B_BPBLCD20_MASK 0x2u #define LCD_WF8B_BPBLCD20_SHIFT 1 #define LCD_WF8B_BPBLCD9_MASK 0x2u #define LCD_WF8B_BPBLCD9_SHIFT 1 #define LCD_WF8B_BPBLCD7_MASK 0x2u #define LCD_WF8B_BPBLCD7_SHIFT 1 #define LCD_WF8B_BPBLCD50_MASK 0x2u #define LCD_WF8B_BPBLCD50_SHIFT 1 #define LCD_WF8B_BPBLCD40_MASK 0x2u #define LCD_WF8B_BPBLCD40_SHIFT 1 #define LCD_WF8B_BPBLCD63_MASK 0x2u #define LCD_WF8B_BPBLCD63_SHIFT 1 #define LCD_WF8B_BPBLCD26_MASK 0x2u #define LCD_WF8B_BPBLCD26_SHIFT 1 #define LCD_WF8B_BPBLCD12_MASK 0x2u #define LCD_WF8B_BPBLCD12_SHIFT 1 #define LCD_WF8B_BPBLCD19_MASK 0x2u #define LCD_WF8B_BPBLCD19_SHIFT 1 #define LCD_WF8B_BPBLCD34_MASK 0x2u #define LCD_WF8B_BPBLCD34_SHIFT 1 #define LCD_WF8B_BPBLCD39_MASK 0x2u #define LCD_WF8B_BPBLCD39_SHIFT 1 #define LCD_WF8B_BPBLCD59_MASK 0x2u #define LCD_WF8B_BPBLCD59_SHIFT 1 #define LCD_WF8B_BPBLCD61_MASK 0x2u #define LCD_WF8B_BPBLCD61_SHIFT 1 #define LCD_WF8B_BPBLCD37_MASK 0x2u #define LCD_WF8B_BPBLCD37_SHIFT 1 #define LCD_WF8B_BPBLCD31_MASK 0x2u #define LCD_WF8B_BPBLCD31_SHIFT 1 #define LCD_WF8B_BPBLCD58_MASK 0x2u #define LCD_WF8B_BPBLCD58_SHIFT 1 #define LCD_WF8B_BPBLCD18_MASK 0x2u #define LCD_WF8B_BPBLCD18_SHIFT 1 #define LCD_WF8B_BPBLCD45_MASK 0x2u #define LCD_WF8B_BPBLCD45_SHIFT 1 #define LCD_WF8B_BPBLCD27_MASK 0x2u #define LCD_WF8B_BPBLCD27_SHIFT 1 #define LCD_WF8B_BPBLCD14_MASK 0x2u #define LCD_WF8B_BPBLCD14_SHIFT 1 #define LCD_WF8B_BPBLCD51_MASK 0x2u #define LCD_WF8B_BPBLCD51_SHIFT 1 #define LCD_WF8B_BPBLCD52_MASK 0x2u #define LCD_WF8B_BPBLCD52_SHIFT 1 #define LCD_WF8B_BPBLCD4_MASK 0x2u #define LCD_WF8B_BPBLCD4_SHIFT 1 #define LCD_WF8B_BPBLCD35_MASK 0x2u #define LCD_WF8B_BPBLCD35_SHIFT 1 #define LCD_WF8B_BPBLCD17_MASK 0x2u #define LCD_WF8B_BPBLCD17_SHIFT 1 #define LCD_WF8B_BPBLCD41_MASK 0x2u #define LCD_WF8B_BPBLCD41_SHIFT 1 #define LCD_WF8B_BPBLCD11_MASK 0x2u #define LCD_WF8B_BPBLCD11_SHIFT 1 #define LCD_WF8B_BPBLCD46_MASK 0x2u #define LCD_WF8B_BPBLCD46_SHIFT 1 #define LCD_WF8B_BPBLCD57_MASK 0x2u #define LCD_WF8B_BPBLCD57_SHIFT 1 #define LCD_WF8B_BPBLCD42_MASK 0x2u #define LCD_WF8B_BPBLCD42_SHIFT 1 #define LCD_WF8B_BPBLCD5_MASK 0x2u #define LCD_WF8B_BPBLCD5_SHIFT 1 #define LCD_WF8B_BPBLCD3_MASK 0x2u #define LCD_WF8B_BPBLCD3_SHIFT 1 #define LCD_WF8B_BPBLCD16_MASK 0x2u #define LCD_WF8B_BPBLCD16_SHIFT 1 #define LCD_WF8B_BPBLCD13_MASK 0x2u #define LCD_WF8B_BPBLCD13_SHIFT 1 #define LCD_WF8B_BPCLCD10_MASK 0x4u #define LCD_WF8B_BPCLCD10_SHIFT 2 #define LCD_WF8B_BPCLCD55_MASK 0x4u #define LCD_WF8B_BPCLCD55_SHIFT 2 #define LCD_WF8B_BPCLCD2_MASK 0x4u #define LCD_WF8B_BPCLCD2_SHIFT 2 #define LCD_WF8B_BPCLCD23_MASK 0x4u #define LCD_WF8B_BPCLCD23_SHIFT 2 #define LCD_WF8B_BPCLCD48_MASK 0x4u #define LCD_WF8B_BPCLCD48_SHIFT 2 #define LCD_WF8B_BPCLCD24_MASK 0x4u #define LCD_WF8B_BPCLCD24_SHIFT 2 #define LCD_WF8B_BPCLCD60_MASK 0x4u #define LCD_WF8B_BPCLCD60_SHIFT 2 #define LCD_WF8B_BPCLCD47_MASK 0x4u #define LCD_WF8B_BPCLCD47_SHIFT 2 #define LCD_WF8B_BPCLCD22_MASK 0x4u #define LCD_WF8B_BPCLCD22_SHIFT 2 #define LCD_WF8B_BPCLCD8_MASK 0x4u #define LCD_WF8B_BPCLCD8_SHIFT 2 #define LCD_WF8B_BPCLCD21_MASK 0x4u #define LCD_WF8B_BPCLCD21_SHIFT 2 #define LCD_WF8B_BPCLCD49_MASK 0x4u #define LCD_WF8B_BPCLCD49_SHIFT 2 #define LCD_WF8B_BPCLCD25_MASK 0x4u #define LCD_WF8B_BPCLCD25_SHIFT 2 #define LCD_WF8B_BPCLCD1_MASK 0x4u #define LCD_WF8B_BPCLCD1_SHIFT 2 #define LCD_WF8B_BPCLCD20_MASK 0x4u #define LCD_WF8B_BPCLCD20_SHIFT 2 #define LCD_WF8B_BPCLCD50_MASK 0x4u #define LCD_WF8B_BPCLCD50_SHIFT 2 #define LCD_WF8B_BPCLCD19_MASK 0x4u #define LCD_WF8B_BPCLCD19_SHIFT 2 #define LCD_WF8B_BPCLCD26_MASK 0x4u #define LCD_WF8B_BPCLCD26_SHIFT 2 #define LCD_WF8B_BPCLCD59_MASK 0x4u #define LCD_WF8B_BPCLCD59_SHIFT 2 #define LCD_WF8B_BPCLCD61_MASK 0x4u #define LCD_WF8B_BPCLCD61_SHIFT 2 #define LCD_WF8B_BPCLCD46_MASK 0x4u #define LCD_WF8B_BPCLCD46_SHIFT 2 #define LCD_WF8B_BPCLCD18_MASK 0x4u #define LCD_WF8B_BPCLCD18_SHIFT 2 #define LCD_WF8B_BPCLCD5_MASK 0x4u #define LCD_WF8B_BPCLCD5_SHIFT 2 #define LCD_WF8B_BPCLCD63_MASK 0x4u #define LCD_WF8B_BPCLCD63_SHIFT 2 #define LCD_WF8B_BPCLCD27_MASK 0x4u #define LCD_WF8B_BPCLCD27_SHIFT 2 #define LCD_WF8B_BPCLCD17_MASK 0x4u #define LCD_WF8B_BPCLCD17_SHIFT 2 #define LCD_WF8B_BPCLCD51_MASK 0x4u #define LCD_WF8B_BPCLCD51_SHIFT 2 #define LCD_WF8B_BPCLCD9_MASK 0x4u #define LCD_WF8B_BPCLCD9_SHIFT 2 #define LCD_WF8B_BPCLCD54_MASK 0x4u #define LCD_WF8B_BPCLCD54_SHIFT 2 #define LCD_WF8B_BPCLCD15_MASK 0x4u #define LCD_WF8B_BPCLCD15_SHIFT 2 #define LCD_WF8B_BPCLCD16_MASK 0x4u #define LCD_WF8B_BPCLCD16_SHIFT 2 #define LCD_WF8B_BPCLCD14_MASK 0x4u #define LCD_WF8B_BPCLCD14_SHIFT 2 #define LCD_WF8B_BPCLCD32_MASK 0x4u #define LCD_WF8B_BPCLCD32_SHIFT 2 #define LCD_WF8B_BPCLCD28_MASK 0x4u #define LCD_WF8B_BPCLCD28_SHIFT 2 #define LCD_WF8B_BPCLCD53_MASK 0x4u #define LCD_WF8B_BPCLCD53_SHIFT 2 #define LCD_WF8B_BPCLCD33_MASK 0x4u #define LCD_WF8B_BPCLCD33_SHIFT 2 #define LCD_WF8B_BPCLCD0_MASK 0x4u #define LCD_WF8B_BPCLCD0_SHIFT 2 #define LCD_WF8B_BPCLCD43_MASK 0x4u #define LCD_WF8B_BPCLCD43_SHIFT 2 #define LCD_WF8B_BPCLCD7_MASK 0x4u #define LCD_WF8B_BPCLCD7_SHIFT 2 #define LCD_WF8B_BPCLCD4_MASK 0x4u #define LCD_WF8B_BPCLCD4_SHIFT 2 #define LCD_WF8B_BPCLCD34_MASK 0x4u #define LCD_WF8B_BPCLCD34_SHIFT 2 #define LCD_WF8B_BPCLCD29_MASK 0x4u #define LCD_WF8B_BPCLCD29_SHIFT 2 #define LCD_WF8B_BPCLCD45_MASK 0x4u #define LCD_WF8B_BPCLCD45_SHIFT 2 #define LCD_WF8B_BPCLCD57_MASK 0x4u #define LCD_WF8B_BPCLCD57_SHIFT 2 #define LCD_WF8B_BPCLCD42_MASK 0x4u #define LCD_WF8B_BPCLCD42_SHIFT 2 #define LCD_WF8B_BPCLCD35_MASK 0x4u #define LCD_WF8B_BPCLCD35_SHIFT 2 #define LCD_WF8B_BPCLCD13_MASK 0x4u #define LCD_WF8B_BPCLCD13_SHIFT 2 #define LCD_WF8B_BPCLCD36_MASK 0x4u #define LCD_WF8B_BPCLCD36_SHIFT 2 #define LCD_WF8B_BPCLCD30_MASK 0x4u #define LCD_WF8B_BPCLCD30_SHIFT 2 #define LCD_WF8B_BPCLCD52_MASK 0x4u #define LCD_WF8B_BPCLCD52_SHIFT 2 #define LCD_WF8B_BPCLCD58_MASK 0x4u #define LCD_WF8B_BPCLCD58_SHIFT 2 #define LCD_WF8B_BPCLCD41_MASK 0x4u #define LCD_WF8B_BPCLCD41_SHIFT 2 #define LCD_WF8B_BPCLCD37_MASK 0x4u #define LCD_WF8B_BPCLCD37_SHIFT 2 #define LCD_WF8B_BPCLCD3_MASK 0x4u #define LCD_WF8B_BPCLCD3_SHIFT 2 #define LCD_WF8B_BPCLCD12_MASK 0x4u #define LCD_WF8B_BPCLCD12_SHIFT 2 #define LCD_WF8B_BPCLCD11_MASK 0x4u #define LCD_WF8B_BPCLCD11_SHIFT 2 #define LCD_WF8B_BPCLCD38_MASK 0x4u #define LCD_WF8B_BPCLCD38_SHIFT 2 #define LCD_WF8B_BPCLCD44_MASK 0x4u #define LCD_WF8B_BPCLCD44_SHIFT 2 #define LCD_WF8B_BPCLCD31_MASK 0x4u #define LCD_WF8B_BPCLCD31_SHIFT 2 #define LCD_WF8B_BPCLCD40_MASK 0x4u #define LCD_WF8B_BPCLCD40_SHIFT 2 #define LCD_WF8B_BPCLCD62_MASK 0x4u #define LCD_WF8B_BPCLCD62_SHIFT 2 #define LCD_WF8B_BPCLCD56_MASK 0x4u #define LCD_WF8B_BPCLCD56_SHIFT 2 #define LCD_WF8B_BPCLCD39_MASK 0x4u #define LCD_WF8B_BPCLCD39_SHIFT 2 #define LCD_WF8B_BPCLCD6_MASK 0x4u #define LCD_WF8B_BPCLCD6_SHIFT 2 #define LCD_WF8B_BPDLCD47_MASK 0x8u #define LCD_WF8B_BPDLCD47_SHIFT 3 #define LCD_WF8B_BPDLCD23_MASK 0x8u #define LCD_WF8B_BPDLCD23_SHIFT 3 #define LCD_WF8B_BPDLCD48_MASK 0x8u #define LCD_WF8B_BPDLCD48_SHIFT 3 #define LCD_WF8B_BPDLCD24_MASK 0x8u #define LCD_WF8B_BPDLCD24_SHIFT 3 #define LCD_WF8B_BPDLCD15_MASK 0x8u #define LCD_WF8B_BPDLCD15_SHIFT 3 #define LCD_WF8B_BPDLCD22_MASK 0x8u #define LCD_WF8B_BPDLCD22_SHIFT 3 #define LCD_WF8B_BPDLCD60_MASK 0x8u #define LCD_WF8B_BPDLCD60_SHIFT 3 #define LCD_WF8B_BPDLCD10_MASK 0x8u #define LCD_WF8B_BPDLCD10_SHIFT 3 #define LCD_WF8B_BPDLCD21_MASK 0x8u #define LCD_WF8B_BPDLCD21_SHIFT 3 #define LCD_WF8B_BPDLCD49_MASK 0x8u #define LCD_WF8B_BPDLCD49_SHIFT 3 #define LCD_WF8B_BPDLCD1_MASK 0x8u #define LCD_WF8B_BPDLCD1_SHIFT 3 #define LCD_WF8B_BPDLCD25_MASK 0x8u #define LCD_WF8B_BPDLCD25_SHIFT 3 #define LCD_WF8B_BPDLCD20_MASK 0x8u #define LCD_WF8B_BPDLCD20_SHIFT 3 #define LCD_WF8B_BPDLCD2_MASK 0x8u #define LCD_WF8B_BPDLCD2_SHIFT 3 #define LCD_WF8B_BPDLCD55_MASK 0x8u #define LCD_WF8B_BPDLCD55_SHIFT 3 #define LCD_WF8B_BPDLCD59_MASK 0x8u #define LCD_WF8B_BPDLCD59_SHIFT 3 #define LCD_WF8B_BPDLCD5_MASK 0x8u #define LCD_WF8B_BPDLCD5_SHIFT 3 #define LCD_WF8B_BPDLCD19_MASK 0x8u #define LCD_WF8B_BPDLCD19_SHIFT 3 #define LCD_WF8B_BPDLCD6_MASK 0x8u #define LCD_WF8B_BPDLCD6_SHIFT 3 #define LCD_WF8B_BPDLCD26_MASK 0x8u #define LCD_WF8B_BPDLCD26_SHIFT 3 #define LCD_WF8B_BPDLCD0_MASK 0x8u #define LCD_WF8B_BPDLCD0_SHIFT 3 #define LCD_WF8B_BPDLCD50_MASK 0x8u #define LCD_WF8B_BPDLCD50_SHIFT 3 #define LCD_WF8B_BPDLCD46_MASK 0x8u #define LCD_WF8B_BPDLCD46_SHIFT 3 #define LCD_WF8B_BPDLCD18_MASK 0x8u #define LCD_WF8B_BPDLCD18_SHIFT 3 #define LCD_WF8B_BPDLCD61_MASK 0x8u #define LCD_WF8B_BPDLCD61_SHIFT 3 #define LCD_WF8B_BPDLCD9_MASK 0x8u #define LCD_WF8B_BPDLCD9_SHIFT 3 #define LCD_WF8B_BPDLCD17_MASK 0x8u #define LCD_WF8B_BPDLCD17_SHIFT 3 #define LCD_WF8B_BPDLCD27_MASK 0x8u #define LCD_WF8B_BPDLCD27_SHIFT 3 #define LCD_WF8B_BPDLCD53_MASK 0x8u #define LCD_WF8B_BPDLCD53_SHIFT 3 #define LCD_WF8B_BPDLCD51_MASK 0x8u #define LCD_WF8B_BPDLCD51_SHIFT 3 #define LCD_WF8B_BPDLCD54_MASK 0x8u #define LCD_WF8B_BPDLCD54_SHIFT 3 #define LCD_WF8B_BPDLCD13_MASK 0x8u #define LCD_WF8B_BPDLCD13_SHIFT 3 #define LCD_WF8B_BPDLCD16_MASK 0x8u #define LCD_WF8B_BPDLCD16_SHIFT 3 #define LCD_WF8B_BPDLCD32_MASK 0x8u #define LCD_WF8B_BPDLCD32_SHIFT 3 #define LCD_WF8B_BPDLCD14_MASK 0x8u #define LCD_WF8B_BPDLCD14_SHIFT 3 #define LCD_WF8B_BPDLCD28_MASK 0x8u #define LCD_WF8B_BPDLCD28_SHIFT 3 #define LCD_WF8B_BPDLCD43_MASK 0x8u #define LCD_WF8B_BPDLCD43_SHIFT 3 #define LCD_WF8B_BPDLCD4_MASK 0x8u #define LCD_WF8B_BPDLCD4_SHIFT 3 #define LCD_WF8B_BPDLCD45_MASK 0x8u #define LCD_WF8B_BPDLCD45_SHIFT 3 #define LCD_WF8B_BPDLCD8_MASK 0x8u #define LCD_WF8B_BPDLCD8_SHIFT 3 #define LCD_WF8B_BPDLCD62_MASK 0x8u #define LCD_WF8B_BPDLCD62_SHIFT 3 #define LCD_WF8B_BPDLCD33_MASK 0x8u #define LCD_WF8B_BPDLCD33_SHIFT 3 #define LCD_WF8B_BPDLCD34_MASK 0x8u #define LCD_WF8B_BPDLCD34_SHIFT 3 #define LCD_WF8B_BPDLCD29_MASK 0x8u #define LCD_WF8B_BPDLCD29_SHIFT 3 #define LCD_WF8B_BPDLCD58_MASK 0x8u #define LCD_WF8B_BPDLCD58_SHIFT 3 #define LCD_WF8B_BPDLCD57_MASK 0x8u #define LCD_WF8B_BPDLCD57_SHIFT 3 #define LCD_WF8B_BPDLCD42_MASK 0x8u #define LCD_WF8B_BPDLCD42_SHIFT 3 #define LCD_WF8B_BPDLCD35_MASK 0x8u #define LCD_WF8B_BPDLCD35_SHIFT 3 #define LCD_WF8B_BPDLCD52_MASK 0x8u #define LCD_WF8B_BPDLCD52_SHIFT 3 #define LCD_WF8B_BPDLCD7_MASK 0x8u #define LCD_WF8B_BPDLCD7_SHIFT 3 #define LCD_WF8B_BPDLCD36_MASK 0x8u #define LCD_WF8B_BPDLCD36_SHIFT 3 #define LCD_WF8B_BPDLCD30_MASK 0x8u #define LCD_WF8B_BPDLCD30_SHIFT 3 #define LCD_WF8B_BPDLCD41_MASK 0x8u #define LCD_WF8B_BPDLCD41_SHIFT 3 #define LCD_WF8B_BPDLCD37_MASK 0x8u #define LCD_WF8B_BPDLCD37_SHIFT 3 #define LCD_WF8B_BPDLCD44_MASK 0x8u #define LCD_WF8B_BPDLCD44_SHIFT 3 #define LCD_WF8B_BPDLCD63_MASK 0x8u #define LCD_WF8B_BPDLCD63_SHIFT 3 #define LCD_WF8B_BPDLCD38_MASK 0x8u #define LCD_WF8B_BPDLCD38_SHIFT 3 #define LCD_WF8B_BPDLCD56_MASK 0x8u #define LCD_WF8B_BPDLCD56_SHIFT 3 #define LCD_WF8B_BPDLCD40_MASK 0x8u #define LCD_WF8B_BPDLCD40_SHIFT 3 #define LCD_WF8B_BPDLCD31_MASK 0x8u #define LCD_WF8B_BPDLCD31_SHIFT 3 #define LCD_WF8B_BPDLCD12_MASK 0x8u #define LCD_WF8B_BPDLCD12_SHIFT 3 #define LCD_WF8B_BPDLCD39_MASK 0x8u #define LCD_WF8B_BPDLCD39_SHIFT 3 #define LCD_WF8B_BPDLCD3_MASK 0x8u #define LCD_WF8B_BPDLCD3_SHIFT 3 #define LCD_WF8B_BPDLCD11_MASK 0x8u #define LCD_WF8B_BPDLCD11_SHIFT 3 #define LCD_WF8B_BPELCD12_MASK 0x10u #define LCD_WF8B_BPELCD12_SHIFT 4 #define LCD_WF8B_BPELCD39_MASK 0x10u #define LCD_WF8B_BPELCD39_SHIFT 4 #define LCD_WF8B_BPELCD3_MASK 0x10u #define LCD_WF8B_BPELCD3_SHIFT 4 #define LCD_WF8B_BPELCD38_MASK 0x10u #define LCD_WF8B_BPELCD38_SHIFT 4 #define LCD_WF8B_BPELCD40_MASK 0x10u #define LCD_WF8B_BPELCD40_SHIFT 4 #define LCD_WF8B_BPELCD37_MASK 0x10u #define LCD_WF8B_BPELCD37_SHIFT 4 #define LCD_WF8B_BPELCD41_MASK 0x10u #define LCD_WF8B_BPELCD41_SHIFT 4 #define LCD_WF8B_BPELCD36_MASK 0x10u #define LCD_WF8B_BPELCD36_SHIFT 4 #define LCD_WF8B_BPELCD8_MASK 0x10u #define LCD_WF8B_BPELCD8_SHIFT 4 #define LCD_WF8B_BPELCD35_MASK 0x10u #define LCD_WF8B_BPELCD35_SHIFT 4 #define LCD_WF8B_BPELCD42_MASK 0x10u #define LCD_WF8B_BPELCD42_SHIFT 4 #define LCD_WF8B_BPELCD34_MASK 0x10u #define LCD_WF8B_BPELCD34_SHIFT 4 #define LCD_WF8B_BPELCD33_MASK 0x10u #define LCD_WF8B_BPELCD33_SHIFT 4 #define LCD_WF8B_BPELCD11_MASK 0x10u #define LCD_WF8B_BPELCD11_SHIFT 4 #define LCD_WF8B_BPELCD43_MASK 0x10u #define LCD_WF8B_BPELCD43_SHIFT 4 #define LCD_WF8B_BPELCD32_MASK 0x10u #define LCD_WF8B_BPELCD32_SHIFT 4 #define LCD_WF8B_BPELCD31_MASK 0x10u #define LCD_WF8B_BPELCD31_SHIFT 4 #define LCD_WF8B_BPELCD44_MASK 0x10u #define LCD_WF8B_BPELCD44_SHIFT 4 #define LCD_WF8B_BPELCD30_MASK 0x10u #define LCD_WF8B_BPELCD30_SHIFT 4 #define LCD_WF8B_BPELCD29_MASK 0x10u #define LCD_WF8B_BPELCD29_SHIFT 4 #define LCD_WF8B_BPELCD7_MASK 0x10u #define LCD_WF8B_BPELCD7_SHIFT 4 #define LCD_WF8B_BPELCD45_MASK 0x10u #define LCD_WF8B_BPELCD45_SHIFT 4 #define LCD_WF8B_BPELCD28_MASK 0x10u #define LCD_WF8B_BPELCD28_SHIFT 4 #define LCD_WF8B_BPELCD2_MASK 0x10u #define LCD_WF8B_BPELCD2_SHIFT 4 #define LCD_WF8B_BPELCD27_MASK 0x10u #define LCD_WF8B_BPELCD27_SHIFT 4 #define LCD_WF8B_BPELCD46_MASK 0x10u #define LCD_WF8B_BPELCD46_SHIFT 4 #define LCD_WF8B_BPELCD26_MASK 0x10u #define LCD_WF8B_BPELCD26_SHIFT 4 #define LCD_WF8B_BPELCD10_MASK 0x10u #define LCD_WF8B_BPELCD10_SHIFT 4 #define LCD_WF8B_BPELCD13_MASK 0x10u #define LCD_WF8B_BPELCD13_SHIFT 4 #define LCD_WF8B_BPELCD25_MASK 0x10u #define LCD_WF8B_BPELCD25_SHIFT 4 #define LCD_WF8B_BPELCD5_MASK 0x10u #define LCD_WF8B_BPELCD5_SHIFT 4 #define LCD_WF8B_BPELCD24_MASK 0x10u #define LCD_WF8B_BPELCD24_SHIFT 4 #define LCD_WF8B_BPELCD47_MASK 0x10u #define LCD_WF8B_BPELCD47_SHIFT 4 #define LCD_WF8B_BPELCD23_MASK 0x10u #define LCD_WF8B_BPELCD23_SHIFT 4 #define LCD_WF8B_BPELCD22_MASK 0x10u #define LCD_WF8B_BPELCD22_SHIFT 4 #define LCD_WF8B_BPELCD48_MASK 0x10u #define LCD_WF8B_BPELCD48_SHIFT 4 #define LCD_WF8B_BPELCD21_MASK 0x10u #define LCD_WF8B_BPELCD21_SHIFT 4 #define LCD_WF8B_BPELCD49_MASK 0x10u #define LCD_WF8B_BPELCD49_SHIFT 4 #define LCD_WF8B_BPELCD20_MASK 0x10u #define LCD_WF8B_BPELCD20_SHIFT 4 #define LCD_WF8B_BPELCD19_MASK 0x10u #define LCD_WF8B_BPELCD19_SHIFT 4 #define LCD_WF8B_BPELCD9_MASK 0x10u #define LCD_WF8B_BPELCD9_SHIFT 4 #define LCD_WF8B_BPELCD50_MASK 0x10u #define LCD_WF8B_BPELCD50_SHIFT 4 #define LCD_WF8B_BPELCD18_MASK 0x10u #define LCD_WF8B_BPELCD18_SHIFT 4 #define LCD_WF8B_BPELCD6_MASK 0x10u #define LCD_WF8B_BPELCD6_SHIFT 4 #define LCD_WF8B_BPELCD17_MASK 0x10u #define LCD_WF8B_BPELCD17_SHIFT 4 #define LCD_WF8B_BPELCD51_MASK 0x10u #define LCD_WF8B_BPELCD51_SHIFT 4 #define LCD_WF8B_BPELCD16_MASK 0x10u #define LCD_WF8B_BPELCD16_SHIFT 4 #define LCD_WF8B_BPELCD56_MASK 0x10u #define LCD_WF8B_BPELCD56_SHIFT 4 #define LCD_WF8B_BPELCD57_MASK 0x10u #define LCD_WF8B_BPELCD57_SHIFT 4 #define LCD_WF8B_BPELCD52_MASK 0x10u #define LCD_WF8B_BPELCD52_SHIFT 4 #define LCD_WF8B_BPELCD1_MASK 0x10u #define LCD_WF8B_BPELCD1_SHIFT 4 #define LCD_WF8B_BPELCD58_MASK 0x10u #define LCD_WF8B_BPELCD58_SHIFT 4 #define LCD_WF8B_BPELCD59_MASK 0x10u #define LCD_WF8B_BPELCD59_SHIFT 4 #define LCD_WF8B_BPELCD53_MASK 0x10u #define LCD_WF8B_BPELCD53_SHIFT 4 #define LCD_WF8B_BPELCD14_MASK 0x10u #define LCD_WF8B_BPELCD14_SHIFT 4 #define LCD_WF8B_BPELCD0_MASK 0x10u #define LCD_WF8B_BPELCD0_SHIFT 4 #define LCD_WF8B_BPELCD60_MASK 0x10u #define LCD_WF8B_BPELCD60_SHIFT 4 #define LCD_WF8B_BPELCD15_MASK 0x10u #define LCD_WF8B_BPELCD15_SHIFT 4 #define LCD_WF8B_BPELCD61_MASK 0x10u #define LCD_WF8B_BPELCD61_SHIFT 4 #define LCD_WF8B_BPELCD54_MASK 0x10u #define LCD_WF8B_BPELCD54_SHIFT 4 #define LCD_WF8B_BPELCD62_MASK 0x10u #define LCD_WF8B_BPELCD62_SHIFT 4 #define LCD_WF8B_BPELCD63_MASK 0x10u #define LCD_WF8B_BPELCD63_SHIFT 4 #define LCD_WF8B_BPELCD55_MASK 0x10u #define LCD_WF8B_BPELCD55_SHIFT 4 #define LCD_WF8B_BPELCD4_MASK 0x10u #define LCD_WF8B_BPELCD4_SHIFT 4 #define LCD_WF8B_BPFLCD13_MASK 0x20u #define LCD_WF8B_BPFLCD13_SHIFT 5 #define LCD_WF8B_BPFLCD39_MASK 0x20u #define LCD_WF8B_BPFLCD39_SHIFT 5 #define LCD_WF8B_BPFLCD55_MASK 0x20u #define LCD_WF8B_BPFLCD55_SHIFT 5 #define LCD_WF8B_BPFLCD47_MASK 0x20u #define LCD_WF8B_BPFLCD47_SHIFT 5 #define LCD_WF8B_BPFLCD63_MASK 0x20u #define LCD_WF8B_BPFLCD63_SHIFT 5 #define LCD_WF8B_BPFLCD43_MASK 0x20u #define LCD_WF8B_BPFLCD43_SHIFT 5 #define LCD_WF8B_BPFLCD5_MASK 0x20u #define LCD_WF8B_BPFLCD5_SHIFT 5 #define LCD_WF8B_BPFLCD62_MASK 0x20u #define LCD_WF8B_BPFLCD62_SHIFT 5 #define LCD_WF8B_BPFLCD14_MASK 0x20u #define LCD_WF8B_BPFLCD14_SHIFT 5 #define LCD_WF8B_BPFLCD24_MASK 0x20u #define LCD_WF8B_BPFLCD24_SHIFT 5 #define LCD_WF8B_BPFLCD54_MASK 0x20u #define LCD_WF8B_BPFLCD54_SHIFT 5 #define LCD_WF8B_BPFLCD15_MASK 0x20u #define LCD_WF8B_BPFLCD15_SHIFT 5 #define LCD_WF8B_BPFLCD32_MASK 0x20u #define LCD_WF8B_BPFLCD32_SHIFT 5 #define LCD_WF8B_BPFLCD61_MASK 0x20u #define LCD_WF8B_BPFLCD61_SHIFT 5 #define LCD_WF8B_BPFLCD25_MASK 0x20u #define LCD_WF8B_BPFLCD25_SHIFT 5 #define LCD_WF8B_BPFLCD60_MASK 0x20u #define LCD_WF8B_BPFLCD60_SHIFT 5 #define LCD_WF8B_BPFLCD41_MASK 0x20u #define LCD_WF8B_BPFLCD41_SHIFT 5 #define LCD_WF8B_BPFLCD33_MASK 0x20u #define LCD_WF8B_BPFLCD33_SHIFT 5 #define LCD_WF8B_BPFLCD53_MASK 0x20u #define LCD_WF8B_BPFLCD53_SHIFT 5 #define LCD_WF8B_BPFLCD59_MASK 0x20u #define LCD_WF8B_BPFLCD59_SHIFT 5 #define LCD_WF8B_BPFLCD0_MASK 0x20u #define LCD_WF8B_BPFLCD0_SHIFT 5 #define LCD_WF8B_BPFLCD46_MASK 0x20u #define LCD_WF8B_BPFLCD46_SHIFT 5 #define LCD_WF8B_BPFLCD58_MASK 0x20u #define LCD_WF8B_BPFLCD58_SHIFT 5 #define LCD_WF8B_BPFLCD26_MASK 0x20u #define LCD_WF8B_BPFLCD26_SHIFT 5 #define LCD_WF8B_BPFLCD36_MASK 0x20u #define LCD_WF8B_BPFLCD36_SHIFT 5 #define LCD_WF8B_BPFLCD10_MASK 0x20u #define LCD_WF8B_BPFLCD10_SHIFT 5 #define LCD_WF8B_BPFLCD52_MASK 0x20u #define LCD_WF8B_BPFLCD52_SHIFT 5 #define LCD_WF8B_BPFLCD57_MASK 0x20u #define LCD_WF8B_BPFLCD57_SHIFT 5 #define LCD_WF8B_BPFLCD27_MASK 0x20u #define LCD_WF8B_BPFLCD27_SHIFT 5 #define LCD_WF8B_BPFLCD11_MASK 0x20u #define LCD_WF8B_BPFLCD11_SHIFT 5 #define LCD_WF8B_BPFLCD56_MASK 0x20u #define LCD_WF8B_BPFLCD56_SHIFT 5 #define LCD_WF8B_BPFLCD1_MASK 0x20u #define LCD_WF8B_BPFLCD1_SHIFT 5 #define LCD_WF8B_BPFLCD8_MASK 0x20u #define LCD_WF8B_BPFLCD8_SHIFT 5 #define LCD_WF8B_BPFLCD40_MASK 0x20u #define LCD_WF8B_BPFLCD40_SHIFT 5 #define LCD_WF8B_BPFLCD51_MASK 0x20u #define LCD_WF8B_BPFLCD51_SHIFT 5 #define LCD_WF8B_BPFLCD16_MASK 0x20u #define LCD_WF8B_BPFLCD16_SHIFT 5 #define LCD_WF8B_BPFLCD45_MASK 0x20u #define LCD_WF8B_BPFLCD45_SHIFT 5 #define LCD_WF8B_BPFLCD6_MASK 0x20u #define LCD_WF8B_BPFLCD6_SHIFT 5 #define LCD_WF8B_BPFLCD17_MASK 0x20u #define LCD_WF8B_BPFLCD17_SHIFT 5 #define LCD_WF8B_BPFLCD28_MASK 0x20u #define LCD_WF8B_BPFLCD28_SHIFT 5 #define LCD_WF8B_BPFLCD42_MASK 0x20u #define LCD_WF8B_BPFLCD42_SHIFT 5 #define LCD_WF8B_BPFLCD29_MASK 0x20u #define LCD_WF8B_BPFLCD29_SHIFT 5 #define LCD_WF8B_BPFLCD50_MASK 0x20u #define LCD_WF8B_BPFLCD50_SHIFT 5 #define LCD_WF8B_BPFLCD18_MASK 0x20u #define LCD_WF8B_BPFLCD18_SHIFT 5 #define LCD_WF8B_BPFLCD34_MASK 0x20u #define LCD_WF8B_BPFLCD34_SHIFT 5 #define LCD_WF8B_BPFLCD19_MASK 0x20u #define LCD_WF8B_BPFLCD19_SHIFT 5 #define LCD_WF8B_BPFLCD2_MASK 0x20u #define LCD_WF8B_BPFLCD2_SHIFT 5 #define LCD_WF8B_BPFLCD9_MASK 0x20u #define LCD_WF8B_BPFLCD9_SHIFT 5 #define LCD_WF8B_BPFLCD3_MASK 0x20u #define LCD_WF8B_BPFLCD3_SHIFT 5 #define LCD_WF8B_BPFLCD37_MASK 0x20u #define LCD_WF8B_BPFLCD37_SHIFT 5 #define LCD_WF8B_BPFLCD49_MASK 0x20u #define LCD_WF8B_BPFLCD49_SHIFT 5 #define LCD_WF8B_BPFLCD20_MASK 0x20u #define LCD_WF8B_BPFLCD20_SHIFT 5 #define LCD_WF8B_BPFLCD44_MASK 0x20u #define LCD_WF8B_BPFLCD44_SHIFT 5 #define LCD_WF8B_BPFLCD30_MASK 0x20u #define LCD_WF8B_BPFLCD30_SHIFT 5 #define LCD_WF8B_BPFLCD21_MASK 0x20u #define LCD_WF8B_BPFLCD21_SHIFT 5 #define LCD_WF8B_BPFLCD35_MASK 0x20u #define LCD_WF8B_BPFLCD35_SHIFT 5 #define LCD_WF8B_BPFLCD4_MASK 0x20u #define LCD_WF8B_BPFLCD4_SHIFT 5 #define LCD_WF8B_BPFLCD31_MASK 0x20u #define LCD_WF8B_BPFLCD31_SHIFT 5 #define LCD_WF8B_BPFLCD48_MASK 0x20u #define LCD_WF8B_BPFLCD48_SHIFT 5 #define LCD_WF8B_BPFLCD7_MASK 0x20u #define LCD_WF8B_BPFLCD7_SHIFT 5 #define LCD_WF8B_BPFLCD22_MASK 0x20u #define LCD_WF8B_BPFLCD22_SHIFT 5 #define LCD_WF8B_BPFLCD38_MASK 0x20u #define LCD_WF8B_BPFLCD38_SHIFT 5 #define LCD_WF8B_BPFLCD12_MASK 0x20u #define LCD_WF8B_BPFLCD12_SHIFT 5 #define LCD_WF8B_BPFLCD23_MASK 0x20u #define LCD_WF8B_BPFLCD23_SHIFT 5 #define LCD_WF8B_BPGLCD14_MASK 0x40u #define LCD_WF8B_BPGLCD14_SHIFT 6 #define LCD_WF8B_BPGLCD55_MASK 0x40u #define LCD_WF8B_BPGLCD55_SHIFT 6 #define LCD_WF8B_BPGLCD63_MASK 0x40u #define LCD_WF8B_BPGLCD63_SHIFT 6 #define LCD_WF8B_BPGLCD15_MASK 0x40u #define LCD_WF8B_BPGLCD15_SHIFT 6 #define LCD_WF8B_BPGLCD62_MASK 0x40u #define LCD_WF8B_BPGLCD62_SHIFT 6 #define LCD_WF8B_BPGLCD54_MASK 0x40u #define LCD_WF8B_BPGLCD54_SHIFT 6 #define LCD_WF8B_BPGLCD61_MASK 0x40u #define LCD_WF8B_BPGLCD61_SHIFT 6 #define LCD_WF8B_BPGLCD60_MASK 0x40u #define LCD_WF8B_BPGLCD60_SHIFT 6 #define LCD_WF8B_BPGLCD59_MASK 0x40u #define LCD_WF8B_BPGLCD59_SHIFT 6 #define LCD_WF8B_BPGLCD53_MASK 0x40u #define LCD_WF8B_BPGLCD53_SHIFT 6 #define LCD_WF8B_BPGLCD58_MASK 0x40u #define LCD_WF8B_BPGLCD58_SHIFT 6 #define LCD_WF8B_BPGLCD0_MASK 0x40u #define LCD_WF8B_BPGLCD0_SHIFT 6 #define LCD_WF8B_BPGLCD57_MASK 0x40u #define LCD_WF8B_BPGLCD57_SHIFT 6 #define LCD_WF8B_BPGLCD52_MASK 0x40u #define LCD_WF8B_BPGLCD52_SHIFT 6 #define LCD_WF8B_BPGLCD7_MASK 0x40u #define LCD_WF8B_BPGLCD7_SHIFT 6 #define LCD_WF8B_BPGLCD56_MASK 0x40u #define LCD_WF8B_BPGLCD56_SHIFT 6 #define LCD_WF8B_BPGLCD6_MASK 0x40u #define LCD_WF8B_BPGLCD6_SHIFT 6 #define LCD_WF8B_BPGLCD51_MASK 0x40u #define LCD_WF8B_BPGLCD51_SHIFT 6 #define LCD_WF8B_BPGLCD16_MASK 0x40u #define LCD_WF8B_BPGLCD16_SHIFT 6 #define LCD_WF8B_BPGLCD1_MASK 0x40u #define LCD_WF8B_BPGLCD1_SHIFT 6 #define LCD_WF8B_BPGLCD17_MASK 0x40u #define LCD_WF8B_BPGLCD17_SHIFT 6 #define LCD_WF8B_BPGLCD50_MASK 0x40u #define LCD_WF8B_BPGLCD50_SHIFT 6 #define LCD_WF8B_BPGLCD18_MASK 0x40u #define LCD_WF8B_BPGLCD18_SHIFT 6 #define LCD_WF8B_BPGLCD19_MASK 0x40u #define LCD_WF8B_BPGLCD19_SHIFT 6 #define LCD_WF8B_BPGLCD8_MASK 0x40u #define LCD_WF8B_BPGLCD8_SHIFT 6 #define LCD_WF8B_BPGLCD49_MASK 0x40u #define LCD_WF8B_BPGLCD49_SHIFT 6 #define LCD_WF8B_BPGLCD20_MASK 0x40u #define LCD_WF8B_BPGLCD20_SHIFT 6 #define LCD_WF8B_BPGLCD9_MASK 0x40u #define LCD_WF8B_BPGLCD9_SHIFT 6 #define LCD_WF8B_BPGLCD21_MASK 0x40u #define LCD_WF8B_BPGLCD21_SHIFT 6 #define LCD_WF8B_BPGLCD13_MASK 0x40u #define LCD_WF8B_BPGLCD13_SHIFT 6 #define LCD_WF8B_BPGLCD48_MASK 0x40u #define LCD_WF8B_BPGLCD48_SHIFT 6 #define LCD_WF8B_BPGLCD22_MASK 0x40u #define LCD_WF8B_BPGLCD22_SHIFT 6 #define LCD_WF8B_BPGLCD5_MASK 0x40u #define LCD_WF8B_BPGLCD5_SHIFT 6 #define LCD_WF8B_BPGLCD47_MASK 0x40u #define LCD_WF8B_BPGLCD47_SHIFT 6 #define LCD_WF8B_BPGLCD23_MASK 0x40u #define LCD_WF8B_BPGLCD23_SHIFT 6 #define LCD_WF8B_BPGLCD24_MASK 0x40u #define LCD_WF8B_BPGLCD24_SHIFT 6 #define LCD_WF8B_BPGLCD25_MASK 0x40u #define LCD_WF8B_BPGLCD25_SHIFT 6 #define LCD_WF8B_BPGLCD46_MASK 0x40u #define LCD_WF8B_BPGLCD46_SHIFT 6 #define LCD_WF8B_BPGLCD26_MASK 0x40u #define LCD_WF8B_BPGLCD26_SHIFT 6 #define LCD_WF8B_BPGLCD27_MASK 0x40u #define LCD_WF8B_BPGLCD27_SHIFT 6 #define LCD_WF8B_BPGLCD10_MASK 0x40u #define LCD_WF8B_BPGLCD10_SHIFT 6 #define LCD_WF8B_BPGLCD45_MASK 0x40u #define LCD_WF8B_BPGLCD45_SHIFT 6 #define LCD_WF8B_BPGLCD28_MASK 0x40u #define LCD_WF8B_BPGLCD28_SHIFT 6 #define LCD_WF8B_BPGLCD29_MASK 0x40u #define LCD_WF8B_BPGLCD29_SHIFT 6 #define LCD_WF8B_BPGLCD4_MASK 0x40u #define LCD_WF8B_BPGLCD4_SHIFT 6 #define LCD_WF8B_BPGLCD44_MASK 0x40u #define LCD_WF8B_BPGLCD44_SHIFT 6 #define LCD_WF8B_BPGLCD30_MASK 0x40u #define LCD_WF8B_BPGLCD30_SHIFT 6 #define LCD_WF8B_BPGLCD2_MASK 0x40u #define LCD_WF8B_BPGLCD2_SHIFT 6 #define LCD_WF8B_BPGLCD31_MASK 0x40u #define LCD_WF8B_BPGLCD31_SHIFT 6 #define LCD_WF8B_BPGLCD43_MASK 0x40u #define LCD_WF8B_BPGLCD43_SHIFT 6 #define LCD_WF8B_BPGLCD32_MASK 0x40u #define LCD_WF8B_BPGLCD32_SHIFT 6 #define LCD_WF8B_BPGLCD33_MASK 0x40u #define LCD_WF8B_BPGLCD33_SHIFT 6 #define LCD_WF8B_BPGLCD42_MASK 0x40u #define LCD_WF8B_BPGLCD42_SHIFT 6 #define LCD_WF8B_BPGLCD34_MASK 0x40u #define LCD_WF8B_BPGLCD34_SHIFT 6 #define LCD_WF8B_BPGLCD11_MASK 0x40u #define LCD_WF8B_BPGLCD11_SHIFT 6 #define LCD_WF8B_BPGLCD35_MASK 0x40u #define LCD_WF8B_BPGLCD35_SHIFT 6 #define LCD_WF8B_BPGLCD12_MASK 0x40u #define LCD_WF8B_BPGLCD12_SHIFT 6 #define LCD_WF8B_BPGLCD41_MASK 0x40u #define LCD_WF8B_BPGLCD41_SHIFT 6 #define LCD_WF8B_BPGLCD36_MASK 0x40u #define LCD_WF8B_BPGLCD36_SHIFT 6 #define LCD_WF8B_BPGLCD3_MASK 0x40u #define LCD_WF8B_BPGLCD3_SHIFT 6 #define LCD_WF8B_BPGLCD37_MASK 0x40u #define LCD_WF8B_BPGLCD37_SHIFT 6 #define LCD_WF8B_BPGLCD40_MASK 0x40u #define LCD_WF8B_BPGLCD40_SHIFT 6 #define LCD_WF8B_BPGLCD38_MASK 0x40u #define LCD_WF8B_BPGLCD38_SHIFT 6 #define LCD_WF8B_BPGLCD39_MASK 0x40u #define LCD_WF8B_BPGLCD39_SHIFT 6 #define LCD_WF8B_BPHLCD63_MASK 0x80u #define LCD_WF8B_BPHLCD63_SHIFT 7 #define LCD_WF8B_BPHLCD62_MASK 0x80u #define LCD_WF8B_BPHLCD62_SHIFT 7 #define LCD_WF8B_BPHLCD61_MASK 0x80u #define LCD_WF8B_BPHLCD61_SHIFT 7 #define LCD_WF8B_BPHLCD60_MASK 0x80u #define LCD_WF8B_BPHLCD60_SHIFT 7 #define LCD_WF8B_BPHLCD59_MASK 0x80u #define LCD_WF8B_BPHLCD59_SHIFT 7 #define LCD_WF8B_BPHLCD58_MASK 0x80u #define LCD_WF8B_BPHLCD58_SHIFT 7 #define LCD_WF8B_BPHLCD57_MASK 0x80u #define LCD_WF8B_BPHLCD57_SHIFT 7 #define LCD_WF8B_BPHLCD0_MASK 0x80u #define LCD_WF8B_BPHLCD0_SHIFT 7 #define LCD_WF8B_BPHLCD56_MASK 0x80u #define LCD_WF8B_BPHLCD56_SHIFT 7 #define LCD_WF8B_BPHLCD55_MASK 0x80u #define LCD_WF8B_BPHLCD55_SHIFT 7 #define LCD_WF8B_BPHLCD54_MASK 0x80u #define LCD_WF8B_BPHLCD54_SHIFT 7 #define LCD_WF8B_BPHLCD53_MASK 0x80u #define LCD_WF8B_BPHLCD53_SHIFT 7 #define LCD_WF8B_BPHLCD52_MASK 0x80u #define LCD_WF8B_BPHLCD52_SHIFT 7 #define LCD_WF8B_BPHLCD51_MASK 0x80u #define LCD_WF8B_BPHLCD51_SHIFT 7 #define LCD_WF8B_BPHLCD50_MASK 0x80u #define LCD_WF8B_BPHLCD50_SHIFT 7 #define LCD_WF8B_BPHLCD1_MASK 0x80u #define LCD_WF8B_BPHLCD1_SHIFT 7 #define LCD_WF8B_BPHLCD49_MASK 0x80u #define LCD_WF8B_BPHLCD49_SHIFT 7 #define LCD_WF8B_BPHLCD48_MASK 0x80u #define LCD_WF8B_BPHLCD48_SHIFT 7 #define LCD_WF8B_BPHLCD47_MASK 0x80u #define LCD_WF8B_BPHLCD47_SHIFT 7 #define LCD_WF8B_BPHLCD46_MASK 0x80u #define LCD_WF8B_BPHLCD46_SHIFT 7 #define LCD_WF8B_BPHLCD45_MASK 0x80u #define LCD_WF8B_BPHLCD45_SHIFT 7 #define LCD_WF8B_BPHLCD44_MASK 0x80u #define LCD_WF8B_BPHLCD44_SHIFT 7 #define LCD_WF8B_BPHLCD43_MASK 0x80u #define LCD_WF8B_BPHLCD43_SHIFT 7 #define LCD_WF8B_BPHLCD2_MASK 0x80u #define LCD_WF8B_BPHLCD2_SHIFT 7 #define LCD_WF8B_BPHLCD42_MASK 0x80u #define LCD_WF8B_BPHLCD42_SHIFT 7 #define LCD_WF8B_BPHLCD41_MASK 0x80u #define LCD_WF8B_BPHLCD41_SHIFT 7 #define LCD_WF8B_BPHLCD40_MASK 0x80u #define LCD_WF8B_BPHLCD40_SHIFT 7 #define LCD_WF8B_BPHLCD39_MASK 0x80u #define LCD_WF8B_BPHLCD39_SHIFT 7 #define LCD_WF8B_BPHLCD38_MASK 0x80u #define LCD_WF8B_BPHLCD38_SHIFT 7 #define LCD_WF8B_BPHLCD37_MASK 0x80u #define LCD_WF8B_BPHLCD37_SHIFT 7 #define LCD_WF8B_BPHLCD36_MASK 0x80u #define LCD_WF8B_BPHLCD36_SHIFT 7 #define LCD_WF8B_BPHLCD3_MASK 0x80u #define LCD_WF8B_BPHLCD3_SHIFT 7 #define LCD_WF8B_BPHLCD35_MASK 0x80u #define LCD_WF8B_BPHLCD35_SHIFT 7 #define LCD_WF8B_BPHLCD34_MASK 0x80u #define LCD_WF8B_BPHLCD34_SHIFT 7 #define LCD_WF8B_BPHLCD33_MASK 0x80u #define LCD_WF8B_BPHLCD33_SHIFT 7 #define LCD_WF8B_BPHLCD32_MASK 0x80u #define LCD_WF8B_BPHLCD32_SHIFT 7 #define LCD_WF8B_BPHLCD31_MASK 0x80u #define LCD_WF8B_BPHLCD31_SHIFT 7 #define LCD_WF8B_BPHLCD30_MASK 0x80u #define LCD_WF8B_BPHLCD30_SHIFT 7 #define LCD_WF8B_BPHLCD29_MASK 0x80u #define LCD_WF8B_BPHLCD29_SHIFT 7 #define LCD_WF8B_BPHLCD4_MASK 0x80u #define LCD_WF8B_BPHLCD4_SHIFT 7 #define LCD_WF8B_BPHLCD28_MASK 0x80u #define LCD_WF8B_BPHLCD28_SHIFT 7 #define LCD_WF8B_BPHLCD27_MASK 0x80u #define LCD_WF8B_BPHLCD27_SHIFT 7 #define LCD_WF8B_BPHLCD26_MASK 0x80u #define LCD_WF8B_BPHLCD26_SHIFT 7 #define LCD_WF8B_BPHLCD25_MASK 0x80u #define LCD_WF8B_BPHLCD25_SHIFT 7 #define LCD_WF8B_BPHLCD24_MASK 0x80u #define LCD_WF8B_BPHLCD24_SHIFT 7 #define LCD_WF8B_BPHLCD23_MASK 0x80u #define LCD_WF8B_BPHLCD23_SHIFT 7 #define LCD_WF8B_BPHLCD22_MASK 0x80u #define LCD_WF8B_BPHLCD22_SHIFT 7 #define LCD_WF8B_BPHLCD5_MASK 0x80u #define LCD_WF8B_BPHLCD5_SHIFT 7 #define LCD_WF8B_BPHLCD21_MASK 0x80u #define LCD_WF8B_BPHLCD21_SHIFT 7 #define LCD_WF8B_BPHLCD20_MASK 0x80u #define LCD_WF8B_BPHLCD20_SHIFT 7 #define LCD_WF8B_BPHLCD19_MASK 0x80u #define LCD_WF8B_BPHLCD19_SHIFT 7 #define LCD_WF8B_BPHLCD18_MASK 0x80u #define LCD_WF8B_BPHLCD18_SHIFT 7 #define LCD_WF8B_BPHLCD17_MASK 0x80u #define LCD_WF8B_BPHLCD17_SHIFT 7 #define LCD_WF8B_BPHLCD16_MASK 0x80u #define LCD_WF8B_BPHLCD16_SHIFT 7 #define LCD_WF8B_BPHLCD15_MASK 0x80u #define LCD_WF8B_BPHLCD15_SHIFT 7 #define LCD_WF8B_BPHLCD6_MASK 0x80u #define LCD_WF8B_BPHLCD6_SHIFT 7 #define LCD_WF8B_BPHLCD14_MASK 0x80u #define LCD_WF8B_BPHLCD14_SHIFT 7 #define LCD_WF8B_BPHLCD13_MASK 0x80u #define LCD_WF8B_BPHLCD13_SHIFT 7 #define LCD_WF8B_BPHLCD12_MASK 0x80u #define LCD_WF8B_BPHLCD12_SHIFT 7 #define LCD_WF8B_BPHLCD11_MASK 0x80u #define LCD_WF8B_BPHLCD11_SHIFT 7 #define LCD_WF8B_BPHLCD10_MASK 0x80u #define LCD_WF8B_BPHLCD10_SHIFT 7 #define LCD_WF8B_BPHLCD9_MASK 0x80u #define LCD_WF8B_BPHLCD9_SHIFT 7 #define LCD_WF8B_BPHLCD8_MASK 0x80u #define LCD_WF8B_BPHLCD8_SHIFT 7 #define LCD_WF8B_BPHLCD7_MASK 0x80u #define LCD_WF8B_BPHLCD7_SHIFT 7 /*! * @} */ /* end of group LCD_Register_Masks */ /* LCD - Peripheral instance base addresses */ /** Peripheral LCD base address */ #define LCD_BASE (0x40053000u) /** Peripheral LCD base pointer */ #define LCD ((LCD_Type *)LCD_BASE) #define LCD_BASE_PTR (LCD) /** Array initializer of LCD peripheral base addresses */ #define LCD_BASE_ADDRS { LCD_BASE } /** Array initializer of LCD peripheral base pointers */ #define LCD_BASE_PTRS { LCD } /** Interrupt vectors for the LCD peripheral type */ #define LCD_LCD_IRQS { LCD_IRQn } /* ---------------------------------------------------------------------------- -- LCD - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros * @{ */ /* LCD - Register instance definitions */ /* LCD */ #define LCD_GCR LCD_GCR_REG(LCD) #define LCD_AR LCD_AR_REG(LCD) #define LCD_FDCR LCD_FDCR_REG(LCD) #define LCD_FDSR LCD_FDSR_REG(LCD) #define LCD_PENL LCD_PEN_REG(LCD,0) #define LCD_PENH LCD_PEN_REG(LCD,1) #define LCD_BPENL LCD_BPEN_REG(LCD,0) #define LCD_BPENH LCD_BPEN_REG(LCD,1) #define LCD_WF0 LCD_WF8B_REG(LCD,0) #define LCD_WF3TO0 LCD_WF_REG(LCD,0) #define LCD_WF1 LCD_WF8B_REG(LCD,1) #define LCD_WF2 LCD_WF8B_REG(LCD,2) #define LCD_WF3 LCD_WF8B_REG(LCD,3) #define LCD_WF4 LCD_WF8B_REG(LCD,4) #define LCD_WF7TO4 LCD_WF_REG(LCD,1) #define LCD_WF5 LCD_WF8B_REG(LCD,5) #define LCD_WF6 LCD_WF8B_REG(LCD,6) #define LCD_WF7 LCD_WF8B_REG(LCD,7) #define LCD_WF11TO8 LCD_WF_REG(LCD,2) #define LCD_WF8 LCD_WF8B_REG(LCD,8) #define LCD_WF9 LCD_WF8B_REG(LCD,9) #define LCD_WF10 LCD_WF8B_REG(LCD,10) #define LCD_WF11 LCD_WF8B_REG(LCD,11) #define LCD_WF12 LCD_WF8B_REG(LCD,12) #define LCD_WF15TO12 LCD_WF_REG(LCD,3) #define LCD_WF13 LCD_WF8B_REG(LCD,13) #define LCD_WF14 LCD_WF8B_REG(LCD,14) #define LCD_WF15 LCD_WF8B_REG(LCD,15) #define LCD_WF16 LCD_WF8B_REG(LCD,16) #define LCD_WF19TO16 LCD_WF_REG(LCD,4) #define LCD_WF17 LCD_WF8B_REG(LCD,17) #define LCD_WF18 LCD_WF8B_REG(LCD,18) #define LCD_WF19 LCD_WF8B_REG(LCD,19) #define LCD_WF20 LCD_WF8B_REG(LCD,20) #define LCD_WF23TO20 LCD_WF_REG(LCD,5) #define LCD_WF21 LCD_WF8B_REG(LCD,21) #define LCD_WF22 LCD_WF8B_REG(LCD,22) #define LCD_WF23 LCD_WF8B_REG(LCD,23) #define LCD_WF24 LCD_WF8B_REG(LCD,24) #define LCD_WF27TO24 LCD_WF_REG(LCD,6) #define LCD_WF25 LCD_WF8B_REG(LCD,25) #define LCD_WF26 LCD_WF8B_REG(LCD,26) #define LCD_WF27 LCD_WF8B_REG(LCD,27) #define LCD_WF28 LCD_WF8B_REG(LCD,28) #define LCD_WF31TO28 LCD_WF_REG(LCD,7) #define LCD_WF29 LCD_WF8B_REG(LCD,29) #define LCD_WF30 LCD_WF8B_REG(LCD,30) #define LCD_WF31 LCD_WF8B_REG(LCD,31) #define LCD_WF32 LCD_WF8B_REG(LCD,32) #define LCD_WF35TO32 LCD_WF_REG(LCD,8) #define LCD_WF33 LCD_WF8B_REG(LCD,33) #define LCD_WF34 LCD_WF8B_REG(LCD,34) #define LCD_WF35 LCD_WF8B_REG(LCD,35) #define LCD_WF36 LCD_WF8B_REG(LCD,36) #define LCD_WF39TO36 LCD_WF_REG(LCD,9) #define LCD_WF37 LCD_WF8B_REG(LCD,37) #define LCD_WF38 LCD_WF8B_REG(LCD,38) #define LCD_WF39 LCD_WF8B_REG(LCD,39) #define LCD_WF40 LCD_WF8B_REG(LCD,40) #define LCD_WF43TO40 LCD_WF_REG(LCD,10) #define LCD_WF41 LCD_WF8B_REG(LCD,41) #define LCD_WF42 LCD_WF8B_REG(LCD,42) #define LCD_WF43 LCD_WF8B_REG(LCD,43) #define LCD_WF44 LCD_WF8B_REG(LCD,44) #define LCD_WF47TO44 LCD_WF_REG(LCD,11) #define LCD_WF45 LCD_WF8B_REG(LCD,45) #define LCD_WF46 LCD_WF8B_REG(LCD,46) #define LCD_WF47 LCD_WF8B_REG(LCD,47) #define LCD_WF48 LCD_WF8B_REG(LCD,48) #define LCD_WF51TO48 LCD_WF_REG(LCD,12) #define LCD_WF49 LCD_WF8B_REG(LCD,49) #define LCD_WF50 LCD_WF8B_REG(LCD,50) #define LCD_WF51 LCD_WF8B_REG(LCD,51) #define LCD_WF52 LCD_WF8B_REG(LCD,52) #define LCD_WF55TO52 LCD_WF_REG(LCD,13) #define LCD_WF53 LCD_WF8B_REG(LCD,53) #define LCD_WF54 LCD_WF8B_REG(LCD,54) #define LCD_WF55 LCD_WF8B_REG(LCD,55) #define LCD_WF56 LCD_WF8B_REG(LCD,56) #define LCD_WF59TO56 LCD_WF_REG(LCD,14) #define LCD_WF57 LCD_WF8B_REG(LCD,57) #define LCD_WF58 LCD_WF8B_REG(LCD,58) #define LCD_WF59 LCD_WF8B_REG(LCD,59) #define LCD_WF60 LCD_WF8B_REG(LCD,60) #define LCD_WF63TO60 LCD_WF_REG(LCD,15) #define LCD_WF61 LCD_WF8B_REG(LCD,61) #define LCD_WF62 LCD_WF8B_REG(LCD,62) #define LCD_WF63 LCD_WF8B_REG(LCD,63) /* LCD - Register array accessors */ #define LCD_PEN(index) LCD_PEN_REG(LCD,index) #define LCD_BPEN(index) LCD_BPEN_REG(LCD,index) #define LCD_WF(index2) LCD_WF_REG(LCD,index2) #define LCD_WF8B(index2) LCD_WF8B_REG(LCD,index2) /*! * @} */ /* end of group LCD_Register_Accessor_Macros */ /*! * @} */ /* end of group LCD_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LLWU Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer * @{ */ /** LLWU - Register Layout Typedef */ typedef struct { __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ } LLWU_Type, *LLWU_MemMapPtr; /* ---------------------------------------------------------------------------- -- LLWU - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros * @{ */ /* LLWU - Register accessors */ #define LLWU_PE1_REG(base) ((base)->PE1) #define LLWU_PE2_REG(base) ((base)->PE2) #define LLWU_PE3_REG(base) ((base)->PE3) #define LLWU_PE4_REG(base) ((base)->PE4) #define LLWU_ME_REG(base) ((base)->ME) #define LLWU_F1_REG(base) ((base)->F1) #define LLWU_F2_REG(base) ((base)->F2) #define LLWU_F3_REG(base) ((base)->F3) #define LLWU_FILT1_REG(base) ((base)->FILT1) #define LLWU_FILT2_REG(base) ((base)->FILT2) /*! * @} */ /* end of group LLWU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LLWU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LLWU_Register_Masks LLWU Register Masks * @{ */ /* PE1 Bit Fields */ #define LLWU_PE1_WUPE0_MASK 0x3u #define LLWU_PE1_WUPE0_SHIFT 0 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK) #define LLWU_PE1_WUPE1_MASK 0xCu #define LLWU_PE1_WUPE1_SHIFT 2 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK) #define LLWU_PE1_WUPE2_MASK 0x30u #define LLWU_PE1_WUPE2_SHIFT 4 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK) #define LLWU_PE1_WUPE3_MASK 0xC0u #define LLWU_PE1_WUPE3_SHIFT 6 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK) /* PE2 Bit Fields */ #define LLWU_PE2_WUPE4_MASK 0x3u #define LLWU_PE2_WUPE4_SHIFT 0 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK) #define LLWU_PE2_WUPE5_MASK 0xCu #define LLWU_PE2_WUPE5_SHIFT 2 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK) #define LLWU_PE2_WUPE6_MASK 0x30u #define LLWU_PE2_WUPE6_SHIFT 4 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK) #define LLWU_PE2_WUPE7_MASK 0xC0u #define LLWU_PE2_WUPE7_SHIFT 6 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK) /* PE3 Bit Fields */ #define LLWU_PE3_WUPE8_MASK 0x3u #define LLWU_PE3_WUPE8_SHIFT 0 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK) #define LLWU_PE3_WUPE9_MASK 0xCu #define LLWU_PE3_WUPE9_SHIFT 2 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK) #define LLWU_PE3_WUPE10_MASK 0x30u #define LLWU_PE3_WUPE10_SHIFT 4 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK) #define LLWU_PE3_WUPE11_MASK 0xC0u #define LLWU_PE3_WUPE11_SHIFT 6 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK) /* PE4 Bit Fields */ #define LLWU_PE4_WUPE12_MASK 0x3u #define LLWU_PE4_WUPE12_SHIFT 0 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK) #define LLWU_PE4_WUPE13_MASK 0xCu #define LLWU_PE4_WUPE13_SHIFT 2 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK) #define LLWU_PE4_WUPE14_MASK 0x30u #define LLWU_PE4_WUPE14_SHIFT 4 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK) #define LLWU_PE4_WUPE15_MASK 0xC0u #define LLWU_PE4_WUPE15_SHIFT 6 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK) /* ME Bit Fields */ #define LLWU_ME_WUME0_MASK 0x1u #define LLWU_ME_WUME0_SHIFT 0 #define LLWU_ME_WUME1_MASK 0x2u #define LLWU_ME_WUME1_SHIFT 1 #define LLWU_ME_WUME2_MASK 0x4u #define LLWU_ME_WUME2_SHIFT 2 #define LLWU_ME_WUME3_MASK 0x8u #define LLWU_ME_WUME3_SHIFT 3 #define LLWU_ME_WUME4_MASK 0x10u #define LLWU_ME_WUME4_SHIFT 4 #define LLWU_ME_WUME5_MASK 0x20u #define LLWU_ME_WUME5_SHIFT 5 #define LLWU_ME_WUME6_MASK 0x40u #define LLWU_ME_WUME6_SHIFT 6 #define LLWU_ME_WUME7_MASK 0x80u #define LLWU_ME_WUME7_SHIFT 7 /* F1 Bit Fields */ #define LLWU_F1_WUF0_MASK 0x1u #define LLWU_F1_WUF0_SHIFT 0 #define LLWU_F1_WUF1_MASK 0x2u #define LLWU_F1_WUF1_SHIFT 1 #define LLWU_F1_WUF2_MASK 0x4u #define LLWU_F1_WUF2_SHIFT 2 #define LLWU_F1_WUF3_MASK 0x8u #define LLWU_F1_WUF3_SHIFT 3 #define LLWU_F1_WUF4_MASK 0x10u #define LLWU_F1_WUF4_SHIFT 4 #define LLWU_F1_WUF5_MASK 0x20u #define LLWU_F1_WUF5_SHIFT 5 #define LLWU_F1_WUF6_MASK 0x40u #define LLWU_F1_WUF6_SHIFT 6 #define LLWU_F1_WUF7_MASK 0x80u #define LLWU_F1_WUF7_SHIFT 7 /* F2 Bit Fields */ #define LLWU_F2_WUF8_MASK 0x1u #define LLWU_F2_WUF8_SHIFT 0 #define LLWU_F2_WUF9_MASK 0x2u #define LLWU_F2_WUF9_SHIFT 1 #define LLWU_F2_WUF10_MASK 0x4u #define LLWU_F2_WUF10_SHIFT 2 #define LLWU_F2_WUF11_MASK 0x8u #define LLWU_F2_WUF11_SHIFT 3 #define LLWU_F2_WUF12_MASK 0x10u #define LLWU_F2_WUF12_SHIFT 4 #define LLWU_F2_WUF13_MASK 0x20u #define LLWU_F2_WUF13_SHIFT 5 #define LLWU_F2_WUF14_MASK 0x40u #define LLWU_F2_WUF14_SHIFT 6 #define LLWU_F2_WUF15_MASK 0x80u #define LLWU_F2_WUF15_SHIFT 7 /* F3 Bit Fields */ #define LLWU_F3_MWUF0_MASK 0x1u #define LLWU_F3_MWUF0_SHIFT 0 #define LLWU_F3_MWUF1_MASK 0x2u #define LLWU_F3_MWUF1_SHIFT 1 #define LLWU_F3_MWUF2_MASK 0x4u #define LLWU_F3_MWUF2_SHIFT 2 #define LLWU_F3_MWUF3_MASK 0x8u #define LLWU_F3_MWUF3_SHIFT 3 #define LLWU_F3_MWUF4_MASK 0x10u #define LLWU_F3_MWUF4_SHIFT 4 #define LLWU_F3_MWUF5_MASK 0x20u #define LLWU_F3_MWUF5_SHIFT 5 #define LLWU_F3_MWUF6_MASK 0x40u #define LLWU_F3_MWUF6_SHIFT 6 #define LLWU_F3_MWUF7_MASK 0x80u #define LLWU_F3_MWUF7_SHIFT 7 /* FILT1 Bit Fields */ #define LLWU_FILT1_FILTSEL_MASK 0xFu #define LLWU_FILT1_FILTSEL_SHIFT 0 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK) #define LLWU_FILT1_FILTE_MASK 0x60u #define LLWU_FILT1_FILTE_SHIFT 5 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK) #define LLWU_FILT1_FILTF_MASK 0x80u #define LLWU_FILT1_FILTF_SHIFT 7 /* FILT2 Bit Fields */ #define LLWU_FILT2_FILTSEL_MASK 0xFu #define LLWU_FILT2_FILTSEL_SHIFT 0 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK) #define LLWU_FILT2_FILTE_MASK 0x60u #define LLWU_FILT2_FILTE_SHIFT 5 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK) #define LLWU_FILT2_FILTF_MASK 0x80u #define LLWU_FILT2_FILTF_SHIFT 7 /*! * @} */ /* end of group LLWU_Register_Masks */ /* LLWU - Peripheral instance base addresses */ /** Peripheral LLWU base address */ #define LLWU_BASE (0x4007C000u) /** Peripheral LLWU base pointer */ #define LLWU ((LLWU_Type *)LLWU_BASE) #define LLWU_BASE_PTR (LLWU) /** Array initializer of LLWU peripheral base addresses */ #define LLWU_BASE_ADDRS { LLWU_BASE } /** Array initializer of LLWU peripheral base pointers */ #define LLWU_BASE_PTRS { LLWU } /** Interrupt vectors for the LLWU peripheral type */ #define LLWU_IRQS { LLWU_IRQn } /* ---------------------------------------------------------------------------- -- LLWU - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros * @{ */ /* LLWU - Register instance definitions */ /* LLWU */ #define LLWU_PE1 LLWU_PE1_REG(LLWU) #define LLWU_PE2 LLWU_PE2_REG(LLWU) #define LLWU_PE3 LLWU_PE3_REG(LLWU) #define LLWU_PE4 LLWU_PE4_REG(LLWU) #define LLWU_ME LLWU_ME_REG(LLWU) #define LLWU_F1 LLWU_F1_REG(LLWU) #define LLWU_F2 LLWU_F2_REG(LLWU) #define LLWU_F3 LLWU_F3_REG(LLWU) #define LLWU_FILT1 LLWU_FILT1_REG(LLWU) #define LLWU_FILT2 LLWU_FILT2_REG(LLWU) /*! * @} */ /* end of group LLWU_Register_Accessor_Macros */ /*! * @} */ /* end of group LLWU_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPTMR Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer * @{ */ /** LPTMR - Register Layout Typedef */ typedef struct { __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ } LPTMR_Type, *LPTMR_MemMapPtr; /* ---------------------------------------------------------------------------- -- LPTMR - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros * @{ */ /* LPTMR - Register accessors */ #define LPTMR_CSR_REG(base) ((base)->CSR) #define LPTMR_PSR_REG(base) ((base)->PSR) #define LPTMR_CMR_REG(base) ((base)->CMR) #define LPTMR_CNR_REG(base) ((base)->CNR) /*! * @} */ /* end of group LPTMR_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LPTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Register_Masks LPTMR Register Masks * @{ */ /* CSR Bit Fields */ #define LPTMR_CSR_TEN_MASK 0x1u #define LPTMR_CSR_TEN_SHIFT 0 #define LPTMR_CSR_TMS_MASK 0x2u #define LPTMR_CSR_TMS_SHIFT 1 #define LPTMR_CSR_TFC_MASK 0x4u #define LPTMR_CSR_TFC_SHIFT 2 #define LPTMR_CSR_TPP_MASK 0x8u #define LPTMR_CSR_TPP_SHIFT 3 #define LPTMR_CSR_TPS_MASK 0x30u #define LPTMR_CSR_TPS_SHIFT 4 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK) #define LPTMR_CSR_TIE_MASK 0x40u #define LPTMR_CSR_TIE_SHIFT 6 #define LPTMR_CSR_TCF_MASK 0x80u #define LPTMR_CSR_TCF_SHIFT 7 /* PSR Bit Fields */ #define LPTMR_PSR_PCS_MASK 0x3u #define LPTMR_PSR_PCS_SHIFT 0 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK) #define LPTMR_PSR_PBYP_MASK 0x4u #define LPTMR_PSR_PBYP_SHIFT 2 #define LPTMR_PSR_PRESCALE_MASK 0x78u #define LPTMR_PSR_PRESCALE_SHIFT 3 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK) /* CMR Bit Fields */ #define LPTMR_CMR_COMPARE_MASK 0xFFFFu #define LPTMR_CMR_COMPARE_SHIFT 0 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK) /* CNR Bit Fields */ #define LPTMR_CNR_COUNTER_MASK 0xFFFFu #define LPTMR_CNR_COUNTER_SHIFT 0 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK) /*! * @} */ /* end of group LPTMR_Register_Masks */ /* LPTMR - Peripheral instance base addresses */ /** Peripheral LPTMR0 base address */ #define LPTMR0_BASE (0x40040000u) /** Peripheral LPTMR0 base pointer */ #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) #define LPTMR0_BASE_PTR (LPTMR0) /** Array initializer of LPTMR peripheral base addresses */ #define LPTMR_BASE_ADDRS { LPTMR0_BASE } /** Array initializer of LPTMR peripheral base pointers */ #define LPTMR_BASE_PTRS { LPTMR0 } /** Interrupt vectors for the LPTMR peripheral type */ #define LPTMR_IRQS { LPTMR0_IRQn } /* ---------------------------------------------------------------------------- -- LPTMR - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros * @{ */ /* LPTMR - Register instance definitions */ /* LPTMR0 */ #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0) #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0) #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0) #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0) /*! * @} */ /* end of group LPTMR_Register_Accessor_Macros */ /*! * @} */ /* end of group LPTMR_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- LPUART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer * @{ */ /** LPUART - Register Layout Typedef */ typedef struct { __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */ __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */ __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */ __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */ __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */ } LPUART_Type, *LPUART_MemMapPtr; /* ---------------------------------------------------------------------------- -- LPUART - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros * @{ */ /* LPUART - Register accessors */ #define LPUART_BAUD_REG(base) ((base)->BAUD) #define LPUART_STAT_REG(base) ((base)->STAT) #define LPUART_CTRL_REG(base) ((base)->CTRL) #define LPUART_DATA_REG(base) ((base)->DATA) #define LPUART_MATCH_REG(base) ((base)->MATCH) /*! * @} */ /* end of group LPUART_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LPUART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Register_Masks LPUART Register Masks * @{ */ /* BAUD Bit Fields */ #define LPUART_BAUD_SBR_MASK 0x1FFFu #define LPUART_BAUD_SBR_SHIFT 0 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK) #define LPUART_BAUD_SBNS_MASK 0x2000u #define LPUART_BAUD_SBNS_SHIFT 13 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u #define LPUART_BAUD_RXEDGIE_SHIFT 14 #define LPUART_BAUD_LBKDIE_MASK 0x8000u #define LPUART_BAUD_LBKDIE_SHIFT 15 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u #define LPUART_BAUD_RESYNCDIS_SHIFT 16 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u #define LPUART_BAUD_BOTHEDGE_SHIFT 17 #define LPUART_BAUD_MATCFG_MASK 0xC0000u #define LPUART_BAUD_MATCFG_SHIFT 18 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK) #define LPUART_BAUD_RDMAE_MASK 0x200000u #define LPUART_BAUD_RDMAE_SHIFT 21 #define LPUART_BAUD_TDMAE_MASK 0x800000u #define LPUART_BAUD_TDMAE_SHIFT 23 #define LPUART_BAUD_OSR_MASK 0x1F000000u #define LPUART_BAUD_OSR_SHIFT 24 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK) #define LPUART_BAUD_M10_MASK 0x20000000u #define LPUART_BAUD_M10_SHIFT 29 #define LPUART_BAUD_MAEN2_MASK 0x40000000u #define LPUART_BAUD_MAEN2_SHIFT 30 #define LPUART_BAUD_MAEN1_MASK 0x80000000u #define LPUART_BAUD_MAEN1_SHIFT 31 /* STAT Bit Fields */ #define LPUART_STAT_MA2F_MASK 0x4000u #define LPUART_STAT_MA2F_SHIFT 14 #define LPUART_STAT_MA1F_MASK 0x8000u #define LPUART_STAT_MA1F_SHIFT 15 #define LPUART_STAT_PF_MASK 0x10000u #define LPUART_STAT_PF_SHIFT 16 #define LPUART_STAT_FE_MASK 0x20000u #define LPUART_STAT_FE_SHIFT 17 #define LPUART_STAT_NF_MASK 0x40000u #define LPUART_STAT_NF_SHIFT 18 #define LPUART_STAT_OR_MASK 0x80000u #define LPUART_STAT_OR_SHIFT 19 #define LPUART_STAT_IDLE_MASK 0x100000u #define LPUART_STAT_IDLE_SHIFT 20 #define LPUART_STAT_RDRF_MASK 0x200000u #define LPUART_STAT_RDRF_SHIFT 21 #define LPUART_STAT_TC_MASK 0x400000u #define LPUART_STAT_TC_SHIFT 22 #define LPUART_STAT_TDRE_MASK 0x800000u #define LPUART_STAT_TDRE_SHIFT 23 #define LPUART_STAT_RAF_MASK 0x1000000u #define LPUART_STAT_RAF_SHIFT 24 #define LPUART_STAT_LBKDE_MASK 0x2000000u #define LPUART_STAT_LBKDE_SHIFT 25 #define LPUART_STAT_BRK13_MASK 0x4000000u #define LPUART_STAT_BRK13_SHIFT 26 #define LPUART_STAT_RWUID_MASK 0x8000000u #define LPUART_STAT_RWUID_SHIFT 27 #define LPUART_STAT_RXINV_MASK 0x10000000u #define LPUART_STAT_RXINV_SHIFT 28 #define LPUART_STAT_MSBF_MASK 0x20000000u #define LPUART_STAT_MSBF_SHIFT 29 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u #define LPUART_STAT_RXEDGIF_SHIFT 30 #define LPUART_STAT_LBKDIF_MASK 0x80000000u #define LPUART_STAT_LBKDIF_SHIFT 31 /* CTRL Bit Fields */ #define LPUART_CTRL_PT_MASK 0x1u #define LPUART_CTRL_PT_SHIFT 0 #define LPUART_CTRL_PE_MASK 0x2u #define LPUART_CTRL_PE_SHIFT 1 #define LPUART_CTRL_ILT_MASK 0x4u #define LPUART_CTRL_ILT_SHIFT 2 #define LPUART_CTRL_WAKE_MASK 0x8u #define LPUART_CTRL_WAKE_SHIFT 3 #define LPUART_CTRL_M_MASK 0x10u #define LPUART_CTRL_M_SHIFT 4 #define LPUART_CTRL_RSRC_MASK 0x20u #define LPUART_CTRL_RSRC_SHIFT 5 #define LPUART_CTRL_DOZEEN_MASK 0x40u #define LPUART_CTRL_DOZEEN_SHIFT 6 #define LPUART_CTRL_LOOPS_MASK 0x80u #define LPUART_CTRL_LOOPS_SHIFT 7 #define LPUART_CTRL_IDLECFG_MASK 0x700u #define LPUART_CTRL_IDLECFG_SHIFT 8 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK) #define LPUART_CTRL_MA2IE_MASK 0x4000u #define LPUART_CTRL_MA2IE_SHIFT 14 #define LPUART_CTRL_MA1IE_MASK 0x8000u #define LPUART_CTRL_MA1IE_SHIFT 15 #define LPUART_CTRL_SBK_MASK 0x10000u #define LPUART_CTRL_SBK_SHIFT 16 #define LPUART_CTRL_RWU_MASK 0x20000u #define LPUART_CTRL_RWU_SHIFT 17 #define LPUART_CTRL_RE_MASK 0x40000u #define LPUART_CTRL_RE_SHIFT 18 #define LPUART_CTRL_TE_MASK 0x80000u #define LPUART_CTRL_TE_SHIFT 19 #define LPUART_CTRL_ILIE_MASK 0x100000u #define LPUART_CTRL_ILIE_SHIFT 20 #define LPUART_CTRL_RIE_MASK 0x200000u #define LPUART_CTRL_RIE_SHIFT 21 #define LPUART_CTRL_TCIE_MASK 0x400000u #define LPUART_CTRL_TCIE_SHIFT 22 #define LPUART_CTRL_TIE_MASK 0x800000u #define LPUART_CTRL_TIE_SHIFT 23 #define LPUART_CTRL_PEIE_MASK 0x1000000u #define LPUART_CTRL_PEIE_SHIFT 24 #define LPUART_CTRL_FEIE_MASK 0x2000000u #define LPUART_CTRL_FEIE_SHIFT 25 #define LPUART_CTRL_NEIE_MASK 0x4000000u #define LPUART_CTRL_NEIE_SHIFT 26 #define LPUART_CTRL_ORIE_MASK 0x8000000u #define LPUART_CTRL_ORIE_SHIFT 27 #define LPUART_CTRL_TXINV_MASK 0x10000000u #define LPUART_CTRL_TXINV_SHIFT 28 #define LPUART_CTRL_TXDIR_MASK 0x20000000u #define LPUART_CTRL_TXDIR_SHIFT 29 #define LPUART_CTRL_R9T8_MASK 0x40000000u #define LPUART_CTRL_R9T8_SHIFT 30 #define LPUART_CTRL_R8T9_MASK 0x80000000u #define LPUART_CTRL_R8T9_SHIFT 31 /* DATA Bit Fields */ #define LPUART_DATA_R0T0_MASK 0x1u #define LPUART_DATA_R0T0_SHIFT 0 #define LPUART_DATA_R1T1_MASK 0x2u #define LPUART_DATA_R1T1_SHIFT 1 #define LPUART_DATA_R2T2_MASK 0x4u #define LPUART_DATA_R2T2_SHIFT 2 #define LPUART_DATA_R3T3_MASK 0x8u #define LPUART_DATA_R3T3_SHIFT 3 #define LPUART_DATA_R4T4_MASK 0x10u #define LPUART_DATA_R4T4_SHIFT 4 #define LPUART_DATA_R5T5_MASK 0x20u #define LPUART_DATA_R5T5_SHIFT 5 #define LPUART_DATA_R6T6_MASK 0x40u #define LPUART_DATA_R6T6_SHIFT 6 #define LPUART_DATA_R7T7_MASK 0x80u #define LPUART_DATA_R7T7_SHIFT 7 #define LPUART_DATA_R8T8_MASK 0x100u #define LPUART_DATA_R8T8_SHIFT 8 #define LPUART_DATA_R9T9_MASK 0x200u #define LPUART_DATA_R9T9_SHIFT 9 #define LPUART_DATA_IDLINE_MASK 0x800u #define LPUART_DATA_IDLINE_SHIFT 11 #define LPUART_DATA_RXEMPT_MASK 0x1000u #define LPUART_DATA_RXEMPT_SHIFT 12 #define LPUART_DATA_FRETSC_MASK 0x2000u #define LPUART_DATA_FRETSC_SHIFT 13 #define LPUART_DATA_PARITYE_MASK 0x4000u #define LPUART_DATA_PARITYE_SHIFT 14 #define LPUART_DATA_NOISY_MASK 0x8000u #define LPUART_DATA_NOISY_SHIFT 15 /* MATCH Bit Fields */ #define LPUART_MATCH_MA1_MASK 0x3FFu #define LPUART_MATCH_MA1_SHIFT 0 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK) #define LPUART_MATCH_MA2_MASK 0x3FF0000u #define LPUART_MATCH_MA2_SHIFT 16 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK) /*! * @} */ /* end of group LPUART_Register_Masks */ /* LPUART - Peripheral instance base addresses */ /** Peripheral LPUART0 base address */ #define LPUART0_BASE (0x40054000u) /** Peripheral LPUART0 base pointer */ #define LPUART0 ((LPUART_Type *)LPUART0_BASE) #define LPUART0_BASE_PTR (LPUART0) /** Peripheral LPUART1 base address */ #define LPUART1_BASE (0x40055000u) /** Peripheral LPUART1 base pointer */ #define LPUART1 ((LPUART_Type *)LPUART1_BASE) #define LPUART1_BASE_PTR (LPUART1) /** Array initializer of LPUART peripheral base addresses */ #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE } /** Array initializer of LPUART peripheral base pointers */ #define LPUART_BASE_PTRS { LPUART0, LPUART1 } /** Interrupt vectors for the LPUART peripheral type */ #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn } #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn } /* ---------------------------------------------------------------------------- -- LPUART - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros * @{ */ /* LPUART - Register instance definitions */ /* LPUART0 */ #define LPUART0_BAUD LPUART_BAUD_REG(LPUART0) #define LPUART0_STAT LPUART_STAT_REG(LPUART0) #define LPUART0_CTRL LPUART_CTRL_REG(LPUART0) #define LPUART0_DATA LPUART_DATA_REG(LPUART0) #define LPUART0_MATCH LPUART_MATCH_REG(LPUART0) /* LPUART1 */ #define LPUART1_BAUD LPUART_BAUD_REG(LPUART1) #define LPUART1_STAT LPUART_STAT_REG(LPUART1) #define LPUART1_CTRL LPUART_CTRL_REG(LPUART1) #define LPUART1_DATA LPUART_DATA_REG(LPUART1) #define LPUART1_MATCH LPUART_MATCH_REG(LPUART1) /*! * @} */ /* end of group LPUART_Register_Accessor_Macros */ /*! * @} */ /* end of group LPUART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MCG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer * @{ */ /** MCG - Register Layout Typedef */ typedef struct { __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */ __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */ uint8_t RESERVED_0[4]; __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ uint8_t RESERVED_1[1]; __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ uint8_t RESERVED_2[11]; __I uint8_t HCTRIM; /**< MCG High-frequency IRC Coarse Trim Register, offset: 0x14 */ __I uint8_t HTTRIM; /**< MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register, offset: 0x15 */ __I uint8_t HFTRIM; /**< MCG High-frequency IRC Fine Trim Register, offset: 0x16 */ uint8_t RESERVED_3[1]; __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */ __I uint8_t LTRIMRNG; /**< MCG Low-frequency IRC Trim Range Register, offset: 0x19 */ __I uint8_t LFTRIM; /**< MCG Low-frequency IRC8M Trim Register, offset: 0x1A */ __I uint8_t LSTRIM; /**< MCG Low-frequency IRC2M Trim Register, offset: 0x1B */ } MCG_Type, *MCG_MemMapPtr; /* ---------------------------------------------------------------------------- -- MCG - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros * @{ */ /* MCG - Register accessors */ #define MCG_C1_REG(base) ((base)->C1) #define MCG_C2_REG(base) ((base)->C2) #define MCG_S_REG(base) ((base)->S) #define MCG_SC_REG(base) ((base)->SC) #define MCG_HCTRIM_REG(base) ((base)->HCTRIM) #define MCG_HTTRIM_REG(base) ((base)->HTTRIM) #define MCG_HFTRIM_REG(base) ((base)->HFTRIM) #define MCG_MC_REG(base) ((base)->MC) #define MCG_LTRIMRNG_REG(base) ((base)->LTRIMRNG) #define MCG_LFTRIM_REG(base) ((base)->LFTRIM) #define MCG_LSTRIM_REG(base) ((base)->LSTRIM) /*! * @} */ /* end of group MCG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCG_Register_Masks MCG Register Masks * @{ */ /* C1 Bit Fields */ #define MCG_C1_IREFSTEN_MASK 0x1u #define MCG_C1_IREFSTEN_SHIFT 0 #define MCG_C1_IRCLKEN_MASK 0x2u #define MCG_C1_IRCLKEN_SHIFT 1 #define MCG_C1_CLKS_MASK 0xC0u #define MCG_C1_CLKS_SHIFT 6 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK) /* C2 Bit Fields */ #define MCG_C2_IRCS_MASK 0x1u #define MCG_C2_IRCS_SHIFT 0 #define MCG_C2_EREFS0_MASK 0x4u #define MCG_C2_EREFS0_SHIFT 2 #define MCG_C2_HGO0_MASK 0x8u #define MCG_C2_HGO0_SHIFT 3 #define MCG_C2_RANGE0_MASK 0x30u #define MCG_C2_RANGE0_SHIFT 4 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK) /* S Bit Fields */ #define MCG_S_OSCINIT0_MASK 0x2u #define MCG_S_OSCINIT0_SHIFT 1 #define MCG_S_CLKST_MASK 0xCu #define MCG_S_CLKST_SHIFT 2 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK) /* SC Bit Fields */ #define MCG_SC_FCRDIV_MASK 0xEu #define MCG_SC_FCRDIV_SHIFT 1 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK) /* HCTRIM Bit Fields */ #define MCG_HCTRIM_COARSE_TRIM_MASK 0x3Fu #define MCG_HCTRIM_COARSE_TRIM_SHIFT 0 #define MCG_HCTRIM_COARSE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HCTRIM_COARSE_TRIM_SHIFT))&MCG_HCTRIM_COARSE_TRIM_MASK) /* HTTRIM Bit Fields */ #define MCG_HTTRIM_TEMPCO_TRIM_MASK 0x1Fu #define MCG_HTTRIM_TEMPCO_TRIM_SHIFT 0 #define MCG_HTTRIM_TEMPCO_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HTTRIM_TEMPCO_TRIM_SHIFT))&MCG_HTTRIM_TEMPCO_TRIM_MASK) /* HFTRIM Bit Fields */ #define MCG_HFTRIM_FINE_TRIM_MASK 0x7Fu #define MCG_HFTRIM_FINE_TRIM_SHIFT 0 #define MCG_HFTRIM_FINE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HFTRIM_FINE_TRIM_SHIFT))&MCG_HFTRIM_FINE_TRIM_MASK) /* MC Bit Fields */ #define MCG_MC_LIRC_DIV2_MASK 0x7u #define MCG_MC_LIRC_DIV2_SHIFT 0 #define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x))<<MCG_MC_LIRC_DIV2_SHIFT))&MCG_MC_LIRC_DIV2_MASK) #define MCG_MC_HIRCEN_MASK 0x80u #define MCG_MC_HIRCEN_SHIFT 7 /* LTRIMRNG Bit Fields */ #define MCG_LTRIMRNG_STRIMRNG_MASK 0x3u #define MCG_LTRIMRNG_STRIMRNG_SHIFT 0 #define MCG_LTRIMRNG_STRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_STRIMRNG_SHIFT))&MCG_LTRIMRNG_STRIMRNG_MASK) #define MCG_LTRIMRNG_FTRIMRNG_MASK 0xCu #define MCG_LTRIMRNG_FTRIMRNG_SHIFT 2 #define MCG_LTRIMRNG_FTRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_FTRIMRNG_SHIFT))&MCG_LTRIMRNG_FTRIMRNG_MASK) /* LFTRIM Bit Fields */ #define MCG_LFTRIM_LIRC_FTRIM_MASK 0x7Fu #define MCG_LFTRIM_LIRC_FTRIM_SHIFT 0 #define MCG_LFTRIM_LIRC_FTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LFTRIM_LIRC_FTRIM_SHIFT))&MCG_LFTRIM_LIRC_FTRIM_MASK) /* LSTRIM Bit Fields */ #define MCG_LSTRIM_LIRC_STRIM_MASK 0x7Fu #define MCG_LSTRIM_LIRC_STRIM_SHIFT 0 #define MCG_LSTRIM_LIRC_STRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LSTRIM_LIRC_STRIM_SHIFT))&MCG_LSTRIM_LIRC_STRIM_MASK) /*! * @} */ /* end of group MCG_Register_Masks */ /* MCG - Peripheral instance base addresses */ /** Peripheral MCG base address */ #define MCG_BASE (0x40064000u) /** Peripheral MCG base pointer */ #define MCG ((MCG_Type *)MCG_BASE) #define MCG_BASE_PTR (MCG) /** Array initializer of MCG peripheral base addresses */ #define MCG_BASE_ADDRS { MCG_BASE } /** Array initializer of MCG peripheral base pointers */ #define MCG_BASE_PTRS { MCG } /* ---------------------------------------------------------------------------- -- MCG - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros * @{ */ /* MCG - Register instance definitions */ /* MCG */ #define MCG_C1 MCG_C1_REG(MCG) #define MCG_C2 MCG_C2_REG(MCG) #define MCG_S MCG_S_REG(MCG) #define MCG_SC MCG_SC_REG(MCG) #define MCG_HCTRIM MCG_HCTRIM_REG(MCG) #define MCG_HTTRIM MCG_HTTRIM_REG(MCG) #define MCG_HFTRIM MCG_HFTRIM_REG(MCG) #define MCG_MC MCG_MC_REG(MCG) #define MCG_LTRIMRNG MCG_LTRIMRNG_REG(MCG) #define MCG_LFTRIM MCG_LFTRIM_REG(MCG) #define MCG_LSTRIM MCG_LSTRIM_REG(MCG) /*! * @} */ /* end of group MCG_Register_Accessor_Macros */ /*! * @} */ /* end of group MCG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer * @{ */ /** MCM - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[8]; __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ uint8_t RESERVED_1[48]; __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ } MCM_Type, *MCM_MemMapPtr; /* ---------------------------------------------------------------------------- -- MCM - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros * @{ */ /* MCM - Register accessors */ #define MCM_PLASC_REG(base) ((base)->PLASC) #define MCM_PLAMC_REG(base) ((base)->PLAMC) #define MCM_PLACR_REG(base) ((base)->PLACR) #define MCM_CPO_REG(base) ((base)->CPO) /*! * @} */ /* end of group MCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Masks MCM Register Masks * @{ */ /* PLASC Bit Fields */ #define MCM_PLASC_ASC_MASK 0xFFu #define MCM_PLASC_ASC_SHIFT 0 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK) /* PLAMC Bit Fields */ #define MCM_PLAMC_AMC_MASK 0xFFu #define MCM_PLAMC_AMC_SHIFT 0 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK) /* PLACR Bit Fields */ #define MCM_PLACR_ARB_MASK 0x200u #define MCM_PLACR_ARB_SHIFT 9 #define MCM_PLACR_CFCC_MASK 0x400u #define MCM_PLACR_CFCC_SHIFT 10 #define MCM_PLACR_DFCDA_MASK 0x800u #define MCM_PLACR_DFCDA_SHIFT 11 #define MCM_PLACR_DFCIC_MASK 0x1000u #define MCM_PLACR_DFCIC_SHIFT 12 #define MCM_PLACR_DFCC_MASK 0x2000u #define MCM_PLACR_DFCC_SHIFT 13 #define MCM_PLACR_EFDS_MASK 0x4000u #define MCM_PLACR_EFDS_SHIFT 14 #define MCM_PLACR_DFCS_MASK 0x8000u #define MCM_PLACR_DFCS_SHIFT 15 #define MCM_PLACR_ESFC_MASK 0x10000u #define MCM_PLACR_ESFC_SHIFT 16 /* CPO Bit Fields */ #define MCM_CPO_CPOREQ_MASK 0x1u #define MCM_CPO_CPOREQ_SHIFT 0 #define MCM_CPO_CPOACK_MASK 0x2u #define MCM_CPO_CPOACK_SHIFT 1 #define MCM_CPO_CPOWOI_MASK 0x4u #define MCM_CPO_CPOWOI_SHIFT 2 /*! * @} */ /* end of group MCM_Register_Masks */ /* MCM - Peripheral instance base addresses */ /** Peripheral MCM base address */ #define MCM_BASE (0xF0003000u) /** Peripheral MCM base pointer */ #define MCM ((MCM_Type *)MCM_BASE) #define MCM_BASE_PTR (MCM) /** Array initializer of MCM peripheral base addresses */ #define MCM_BASE_ADDRS { MCM_BASE } /** Array initializer of MCM peripheral base pointers */ #define MCM_BASE_PTRS { MCM } /* ---------------------------------------------------------------------------- -- MCM - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros * @{ */ /* MCM - Register instance definitions */ /* MCM */ #define MCM_PLASC MCM_PLASC_REG(MCM) #define MCM_PLAMC MCM_PLAMC_REG(MCM) #define MCM_PLACR MCM_PLACR_REG(MCM) #define MCM_CPO MCM_CPO_REG(MCM) /*! * @} */ /* end of group MCM_Register_Accessor_Macros */ /*! * @} */ /* end of group MCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MTB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer * @{ */ /** MTB - Register Layout Typedef */ typedef struct { __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ uint8_t RESERVED_0[3824]; __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ uint8_t RESERVED_1[156]; __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ uint8_t RESERVED_2[8]; __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ uint8_t RESERVED_3[8]; __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ } MTB_Type, *MTB_MemMapPtr; /* ---------------------------------------------------------------------------- -- MTB - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros * @{ */ /* MTB - Register accessors */ #define MTB_POSITION_REG(base) ((base)->POSITION) #define MTB_MASTER_REG(base) ((base)->MASTER) #define MTB_FLOW_REG(base) ((base)->FLOW) #define MTB_BASE_REG(base) ((base)->BASE) #define MTB_MODECTRL_REG(base) ((base)->MODECTRL) #define MTB_TAGSET_REG(base) ((base)->TAGSET) #define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR) #define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS) #define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT) #define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT) #define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH) #define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG) #define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID) #define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index]) #define MTB_COMPID_REG(base,index) ((base)->COMPID[index]) /*! * @} */ /* end of group MTB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MTB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MTB_Register_Masks MTB Register Masks * @{ */ /* POSITION Bit Fields */ #define MTB_POSITION_WRAP_MASK 0x4u #define MTB_POSITION_WRAP_SHIFT 2 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u #define MTB_POSITION_POINTER_SHIFT 3 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK) /* MASTER Bit Fields */ #define MTB_MASTER_MASK_MASK 0x1Fu #define MTB_MASTER_MASK_SHIFT 0 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK) #define MTB_MASTER_TSTARTEN_MASK 0x20u #define MTB_MASTER_TSTARTEN_SHIFT 5 #define MTB_MASTER_TSTOPEN_MASK 0x40u #define MTB_MASTER_TSTOPEN_SHIFT 6 #define MTB_MASTER_SFRWPRIV_MASK 0x80u #define MTB_MASTER_SFRWPRIV_SHIFT 7 #define MTB_MASTER_RAMPRIV_MASK 0x100u #define MTB_MASTER_RAMPRIV_SHIFT 8 #define MTB_MASTER_HALTREQ_MASK 0x200u #define MTB_MASTER_HALTREQ_SHIFT 9 #define MTB_MASTER_EN_MASK 0x80000000u #define MTB_MASTER_EN_SHIFT 31 /* FLOW Bit Fields */ #define MTB_FLOW_AUTOSTOP_MASK 0x1u #define MTB_FLOW_AUTOSTOP_SHIFT 0 #define MTB_FLOW_AUTOHALT_MASK 0x2u #define MTB_FLOW_AUTOHALT_SHIFT 1 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u #define MTB_FLOW_WATERMARK_SHIFT 3 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK) /* BASE Bit Fields */ #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu #define MTB_BASE_BASEADDR_SHIFT 0 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK) /* MODECTRL Bit Fields */ #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu #define MTB_MODECTRL_MODECTRL_SHIFT 0 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK) /* TAGSET Bit Fields */ #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu #define MTB_TAGSET_TAGSET_SHIFT 0 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK) /* TAGCLEAR Bit Fields */ #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK) /* LOCKACCESS Bit Fields */ #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK) /* LOCKSTAT Bit Fields */ #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK) /* AUTHSTAT Bit Fields */ #define MTB_AUTHSTAT_BIT0_MASK 0x1u #define MTB_AUTHSTAT_BIT0_SHIFT 0 #define MTB_AUTHSTAT_BIT1_MASK 0x2u #define MTB_AUTHSTAT_BIT1_SHIFT 1 #define MTB_AUTHSTAT_BIT2_MASK 0x4u #define MTB_AUTHSTAT_BIT2_SHIFT 2 #define MTB_AUTHSTAT_BIT3_MASK 0x8u #define MTB_AUTHSTAT_BIT3_SHIFT 3 /* DEVICEARCH Bit Fields */ #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK) /* DEVICECFG Bit Fields */ #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu #define MTB_DEVICECFG_DEVICECFG_SHIFT 0 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK) /* DEVICETYPID Bit Fields */ #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK) /* PERIPHID Bit Fields */ #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu #define MTB_PERIPHID_PERIPHID_SHIFT 0 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK) /* COMPID Bit Fields */ #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu #define MTB_COMPID_COMPID_SHIFT 0 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK) /*! * @} */ /* end of group MTB_Register_Masks */ /* MTB - Peripheral instance base addresses */ /** Peripheral MTB base address */ #define MTB_BASE (0xF0000000u) /** Peripheral MTB base pointer */ #define MTB ((MTB_Type *)MTB_BASE) #define MTB_BASE_PTR (MTB) /** Array initializer of MTB peripheral base addresses */ #define MTB_BASE_ADDRS { MTB_BASE } /** Array initializer of MTB peripheral base pointers */ #define MTB_BASE_PTRS { MTB } /* ---------------------------------------------------------------------------- -- MTB - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros * @{ */ /* MTB - Register instance definitions */ /* MTB */ #define MTB_POSITION MTB_POSITION_REG(MTB) #define MTB_MASTER MTB_MASTER_REG(MTB) #define MTB_FLOW MTB_FLOW_REG(MTB) #define MTB_BASEr MTB_BASE_REG(MTB) #define MTB_MODECTRL MTB_MODECTRL_REG(MTB) #define MTB_TAGSET MTB_TAGSET_REG(MTB) #define MTB_TAGCLEAR MTB_TAGCLEAR_REG(MTB) #define MTB_LOCKACCESS MTB_LOCKACCESS_REG(MTB) #define MTB_LOCKSTAT MTB_LOCKSTAT_REG(MTB) #define MTB_AUTHSTAT MTB_AUTHSTAT_REG(MTB) #define MTB_DEVICEARCH MTB_DEVICEARCH_REG(MTB) #define MTB_DEVICECFG MTB_DEVICECFG_REG(MTB) #define MTB_DEVICETYPID MTB_DEVICETYPID_REG(MTB) #define MTB_PERIPHID4 MTB_PERIPHID_REG(MTB,0) #define MTB_PERIPHID5 MTB_PERIPHID_REG(MTB,1) #define MTB_PERIPHID6 MTB_PERIPHID_REG(MTB,2) #define MTB_PERIPHID7 MTB_PERIPHID_REG(MTB,3) #define MTB_PERIPHID0 MTB_PERIPHID_REG(MTB,4) #define MTB_PERIPHID1 MTB_PERIPHID_REG(MTB,5) #define MTB_PERIPHID2 MTB_PERIPHID_REG(MTB,6) #define MTB_PERIPHID3 MTB_PERIPHID_REG(MTB,7) #define MTB_COMPID0 MTB_COMPID_REG(MTB,0) #define MTB_COMPID1 MTB_COMPID_REG(MTB,1) #define MTB_COMPID2 MTB_COMPID_REG(MTB,2) #define MTB_COMPID3 MTB_COMPID_REG(MTB,3) /* MTB - Register array accessors */ #define MTB_PERIPHID(index) MTB_PERIPHID_REG(MTB,index) #define MTB_COMPID(index) MTB_COMPID_REG(MTB,index) /*! * @} */ /* end of group MTB_Register_Accessor_Macros */ /*! * @} */ /* end of group MTB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- MTBDWT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer * @{ */ /** MTBDWT - Register Layout Typedef */ typedef struct { __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ uint8_t RESERVED_0[28]; struct { /* offset: 0x20, array step: 0x10 */ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ uint8_t RESERVED_0[4]; } COMPARATOR[2]; uint8_t RESERVED_1[448]; __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ uint8_t RESERVED_2[3524]; __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ } MTBDWT_Type, *MTBDWT_MemMapPtr; /* ---------------------------------------------------------------------------- -- MTBDWT - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros * @{ */ /* MTBDWT - Register accessors */ #define MTBDWT_CTRL_REG(base) ((base)->CTRL) #define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP) #define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK) #define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT) #define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL) #define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG) #define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID) #define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index]) #define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index]) /*! * @} */ /* end of group MTBDWT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MTBDWT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks * @{ */ /* CTRL Bit Fields */ #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK) #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u #define MTBDWT_CTRL_NUMCMP_SHIFT 28 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK) /* COMP Bit Fields */ #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu #define MTBDWT_COMP_COMP_SHIFT 0 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK) /* MASK Bit Fields */ #define MTBDWT_MASK_MASK_MASK 0x1Fu #define MTBDWT_MASK_MASK_SHIFT 0 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK) /* FCT Bit Fields */ #define MTBDWT_FCT_FUNCTION_MASK 0xFu #define MTBDWT_FCT_FUNCTION_SHIFT 0 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK) #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u #define MTBDWT_FCT_DATAVMATCH_SHIFT 8 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u #define MTBDWT_FCT_DATAVSIZE_SHIFT 10 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK) #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u #define MTBDWT_FCT_DATAVADDR0_SHIFT 12 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK) #define MTBDWT_FCT_MATCHED_MASK 0x1000000u #define MTBDWT_FCT_MATCHED_SHIFT 24 /* TBCTRL Bit Fields */ #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK) /* DEVICECFG Bit Fields */ #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK) /* DEVICETYPID Bit Fields */ #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK) /* PERIPHID Bit Fields */ #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK) /* COMPID Bit Fields */ #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu #define MTBDWT_COMPID_COMPID_SHIFT 0 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK) /*! * @} */ /* end of group MTBDWT_Register_Masks */ /* MTBDWT - Peripheral instance base addresses */ /** Peripheral MTBDWT base address */ #define MTBDWT_BASE (0xF0001000u) /** Peripheral MTBDWT base pointer */ #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) #define MTBDWT_BASE_PTR (MTBDWT) /** Array initializer of MTBDWT peripheral base addresses */ #define MTBDWT_BASE_ADDRS { MTBDWT_BASE } /** Array initializer of MTBDWT peripheral base pointers */ #define MTBDWT_BASE_PTRS { MTBDWT } /* ---------------------------------------------------------------------------- -- MTBDWT - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros * @{ */ /* MTBDWT - Register instance definitions */ /* MTBDWT */ #define MTBDWT_CTRL MTBDWT_CTRL_REG(MTBDWT) #define MTBDWT_COMP0 MTBDWT_COMP_REG(MTBDWT,0) #define MTBDWT_MASK0 MTBDWT_MASK_REG(MTBDWT,0) #define MTBDWT_FCT0 MTBDWT_FCT_REG(MTBDWT,0) #define MTBDWT_COMP1 MTBDWT_COMP_REG(MTBDWT,1) #define MTBDWT_MASK1 MTBDWT_MASK_REG(MTBDWT,1) #define MTBDWT_FCT1 MTBDWT_FCT_REG(MTBDWT,1) #define MTBDWT_TBCTRL MTBDWT_TBCTRL_REG(MTBDWT) #define MTBDWT_DEVICECFG MTBDWT_DEVICECFG_REG(MTBDWT) #define MTBDWT_DEVICETYPID MTBDWT_DEVICETYPID_REG(MTBDWT) #define MTBDWT_PERIPHID4 MTBDWT_PERIPHID_REG(MTBDWT,0) #define MTBDWT_PERIPHID5 MTBDWT_PERIPHID_REG(MTBDWT,1) #define MTBDWT_PERIPHID6 MTBDWT_PERIPHID_REG(MTBDWT,2) #define MTBDWT_PERIPHID7 MTBDWT_PERIPHID_REG(MTBDWT,3) #define MTBDWT_PERIPHID0 MTBDWT_PERIPHID_REG(MTBDWT,4) #define MTBDWT_PERIPHID1 MTBDWT_PERIPHID_REG(MTBDWT,5) #define MTBDWT_PERIPHID2 MTBDWT_PERIPHID_REG(MTBDWT,6) #define MTBDWT_PERIPHID3 MTBDWT_PERIPHID_REG(MTBDWT,7) #define MTBDWT_COMPID0 MTBDWT_COMPID_REG(MTBDWT,0) #define MTBDWT_COMPID1 MTBDWT_COMPID_REG(MTBDWT,1) #define MTBDWT_COMPID2 MTBDWT_COMPID_REG(MTBDWT,2) #define MTBDWT_COMPID3 MTBDWT_COMPID_REG(MTBDWT,3) /* MTBDWT - Register array accessors */ #define MTBDWT_COMP(index) MTBDWT_COMP_REG(MTBDWT,index) #define MTBDWT_MASK(index) MTBDWT_MASK_REG(MTBDWT,index) #define MTBDWT_FCT(index) MTBDWT_FCT_REG(MTBDWT,index) #define MTBDWT_PERIPHID(index) MTBDWT_PERIPHID_REG(MTBDWT,index) #define MTBDWT_COMPID(index) MTBDWT_COMPID_REG(MTBDWT,index) /*! * @} */ /* end of group MTBDWT_Register_Accessor_Macros */ /*! * @} */ /* end of group MTBDWT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- NV Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer * @{ */ /** NV - Register Layout Typedef */ typedef struct { __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ } NV_Type, *NV_MemMapPtr; /* ---------------------------------------------------------------------------- -- NV - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros * @{ */ /* NV - Register accessors */ #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3) #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) #define NV_FPROT3_REG(base) ((base)->FPROT3) #define NV_FPROT2_REG(base) ((base)->FPROT2) #define NV_FPROT1_REG(base) ((base)->FPROT1) #define NV_FPROT0_REG(base) ((base)->FPROT0) #define NV_FSEC_REG(base) ((base)->FSEC) #define NV_FOPT_REG(base) ((base)->FOPT) /*! * @} */ /* end of group NV_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- NV Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NV_Register_Masks NV Register Masks * @{ */ /* BACKKEY3 Bit Fields */ #define NV_BACKKEY3_KEY_MASK 0xFFu #define NV_BACKKEY3_KEY_SHIFT 0 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK) /* BACKKEY2 Bit Fields */ #define NV_BACKKEY2_KEY_MASK 0xFFu #define NV_BACKKEY2_KEY_SHIFT 0 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK) /* BACKKEY1 Bit Fields */ #define NV_BACKKEY1_KEY_MASK 0xFFu #define NV_BACKKEY1_KEY_SHIFT 0 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK) /* BACKKEY0 Bit Fields */ #define NV_BACKKEY0_KEY_MASK 0xFFu #define NV_BACKKEY0_KEY_SHIFT 0 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK) /* BACKKEY7 Bit Fields */ #define NV_BACKKEY7_KEY_MASK 0xFFu #define NV_BACKKEY7_KEY_SHIFT 0 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK) /* BACKKEY6 Bit Fields */ #define NV_BACKKEY6_KEY_MASK 0xFFu #define NV_BACKKEY6_KEY_SHIFT 0 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK) /* BACKKEY5 Bit Fields */ #define NV_BACKKEY5_KEY_MASK 0xFFu #define NV_BACKKEY5_KEY_SHIFT 0 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK) /* BACKKEY4 Bit Fields */ #define NV_BACKKEY4_KEY_MASK 0xFFu #define NV_BACKKEY4_KEY_SHIFT 0 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK) /* FPROT3 Bit Fields */ #define NV_FPROT3_PROT_MASK 0xFFu #define NV_FPROT3_PROT_SHIFT 0 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK) /* FPROT2 Bit Fields */ #define NV_FPROT2_PROT_MASK 0xFFu #define NV_FPROT2_PROT_SHIFT 0 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK) /* FPROT1 Bit Fields */ #define NV_FPROT1_PROT_MASK 0xFFu #define NV_FPROT1_PROT_SHIFT 0 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK) /* FPROT0 Bit Fields */ #define NV_FPROT0_PROT_MASK 0xFFu #define NV_FPROT0_PROT_SHIFT 0 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK) /* FSEC Bit Fields */ #define NV_FSEC_SEC_MASK 0x3u #define NV_FSEC_SEC_SHIFT 0 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK) #define NV_FSEC_FSLACC_MASK 0xCu #define NV_FSEC_FSLACC_SHIFT 2 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK) #define NV_FSEC_MEEN_MASK 0x30u #define NV_FSEC_MEEN_SHIFT 4 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK) #define NV_FSEC_KEYEN_MASK 0xC0u #define NV_FSEC_KEYEN_SHIFT 6 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK) /* FOPT Bit Fields */ #define NV_FOPT_LPBOOT0_MASK 0x1u #define NV_FOPT_LPBOOT0_SHIFT 0 #define NV_FOPT_BOOTPIN_OPT_MASK 0x2u #define NV_FOPT_BOOTPIN_OPT_SHIFT 1 #define NV_FOPT_NMI_DIS_MASK 0x4u #define NV_FOPT_NMI_DIS_SHIFT 2 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u #define NV_FOPT_RESET_PIN_CFG_SHIFT 3 #define NV_FOPT_LPBOOT1_MASK 0x10u #define NV_FOPT_LPBOOT1_SHIFT 4 #define NV_FOPT_FAST_INIT_MASK 0x20u #define NV_FOPT_FAST_INIT_SHIFT 5 #define NV_FOPT_BOOTSRC_SEL_MASK 0xC0u #define NV_FOPT_BOOTSRC_SEL_SHIFT 6 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTSRC_SEL_SHIFT))&NV_FOPT_BOOTSRC_SEL_MASK) /*! * @} */ /* end of group NV_Register_Masks */ /* NV - Peripheral instance base addresses */ /** Peripheral FTFA_FlashConfig base address */ #define FTFA_FlashConfig_BASE (0x400u) /** Peripheral FTFA_FlashConfig base pointer */ #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) #define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig) /** Array initializer of NV peripheral base addresses */ #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } /** Array initializer of NV peripheral base pointers */ #define NV_BASE_PTRS { FTFA_FlashConfig } /* ---------------------------------------------------------------------------- -- NV - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros * @{ */ /* NV - Register instance definitions */ /* FTFA_FlashConfig */ #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig) #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig) #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig) #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig) #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig) #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig) #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig) #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig) #define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig) #define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig) #define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig) #define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig) #define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig) #define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig) /*! * @} */ /* end of group NV_Register_Accessor_Macros */ /*! * @} */ /* end of group NV_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- OSC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer * @{ */ /** OSC - Register Layout Typedef */ typedef struct { __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ } OSC_Type, *OSC_MemMapPtr; /* ---------------------------------------------------------------------------- -- OSC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros * @{ */ /* OSC - Register accessors */ #define OSC_CR_REG(base) ((base)->CR) /*! * @} */ /* end of group OSC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- OSC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OSC_Register_Masks OSC Register Masks * @{ */ /* CR Bit Fields */ #define OSC_CR_SC16P_MASK 0x1u #define OSC_CR_SC16P_SHIFT 0 #define OSC_CR_SC8P_MASK 0x2u #define OSC_CR_SC8P_SHIFT 1 #define OSC_CR_SC4P_MASK 0x4u #define OSC_CR_SC4P_SHIFT 2 #define OSC_CR_SC2P_MASK 0x8u #define OSC_CR_SC2P_SHIFT 3 #define OSC_CR_EREFSTEN_MASK 0x20u #define OSC_CR_EREFSTEN_SHIFT 5 #define OSC_CR_ERCLKEN_MASK 0x80u #define OSC_CR_ERCLKEN_SHIFT 7 /*! * @} */ /* end of group OSC_Register_Masks */ /* OSC - Peripheral instance base addresses */ /** Peripheral OSC0 base address */ #define OSC0_BASE (0x40065000u) /** Peripheral OSC0 base pointer */ #define OSC0 ((OSC_Type *)OSC0_BASE) #define OSC0_BASE_PTR (OSC0) /** Array initializer of OSC peripheral base addresses */ #define OSC_BASE_ADDRS { OSC0_BASE } /** Array initializer of OSC peripheral base pointers */ #define OSC_BASE_PTRS { OSC0 } /* ---------------------------------------------------------------------------- -- OSC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros * @{ */ /* OSC - Register instance definitions */ /* OSC0 */ #define OSC0_CR OSC_CR_REG(OSC0) /*! * @} */ /* end of group OSC_Register_Accessor_Macros */ /*! * @} */ /* end of group OSC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PIT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer * @{ */ /** PIT - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ uint8_t RESERVED_0[220]; __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ uint8_t RESERVED_1[24]; struct { /* offset: 0x100, array step: 0x10 */ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ } CHANNEL[2]; } PIT_Type, *PIT_MemMapPtr; /* ---------------------------------------------------------------------------- -- PIT - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros * @{ */ /* PIT - Register accessors */ #define PIT_MCR_REG(base) ((base)->MCR) #define PIT_LTMR64H_REG(base) ((base)->LTMR64H) #define PIT_LTMR64L_REG(base) ((base)->LTMR64L) #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) /*! * @} */ /* end of group PIT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PIT_Register_Masks PIT Register Masks * @{ */ /* MCR Bit Fields */ #define PIT_MCR_FRZ_MASK 0x1u #define PIT_MCR_FRZ_SHIFT 0 #define PIT_MCR_MDIS_MASK 0x2u #define PIT_MCR_MDIS_SHIFT 1 /* LTMR64H Bit Fields */ #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu #define PIT_LTMR64H_LTH_SHIFT 0 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK) /* LTMR64L Bit Fields */ #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu #define PIT_LTMR64L_LTL_SHIFT 0 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK) /* LDVAL Bit Fields */ #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu #define PIT_LDVAL_TSV_SHIFT 0 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) /* CVAL Bit Fields */ #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu #define PIT_CVAL_TVL_SHIFT 0 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) /* TCTRL Bit Fields */ #define PIT_TCTRL_TEN_MASK 0x1u #define PIT_TCTRL_TEN_SHIFT 0 #define PIT_TCTRL_TIE_MASK 0x2u #define PIT_TCTRL_TIE_SHIFT 1 #define PIT_TCTRL_CHN_MASK 0x4u #define PIT_TCTRL_CHN_SHIFT 2 /* TFLG Bit Fields */ #define PIT_TFLG_TIF_MASK 0x1u #define PIT_TFLG_TIF_SHIFT 0 /*! * @} */ /* end of group PIT_Register_Masks */ /* PIT - Peripheral instance base addresses */ /** Peripheral PIT base address */ #define PIT_BASE (0x40037000u) /** Peripheral PIT base pointer */ #define PIT ((PIT_Type *)PIT_BASE) #define PIT_BASE_PTR (PIT) /** Array initializer of PIT peripheral base addresses */ #define PIT_BASE_ADDRS { PIT_BASE } /** Array initializer of PIT peripheral base pointers */ #define PIT_BASE_PTRS { PIT } /** Interrupt vectors for the PIT peripheral type */ #define PIT_IRQS { PIT_IRQn, PIT_IRQn } /* ---------------------------------------------------------------------------- -- PIT - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros * @{ */ /* PIT - Register instance definitions */ /* PIT */ #define PIT_MCR PIT_MCR_REG(PIT) #define PIT_LTMR64H PIT_LTMR64H_REG(PIT) #define PIT_LTMR64L PIT_LTMR64L_REG(PIT) #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0) #define PIT_CVAL0 PIT_CVAL_REG(PIT,0) #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0) #define PIT_TFLG0 PIT_TFLG_REG(PIT,0) #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1) #define PIT_CVAL1 PIT_CVAL_REG(PIT,1) #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1) #define PIT_TFLG1 PIT_TFLG_REG(PIT,1) /* PIT - Register array accessors */ #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index) #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index) #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index) #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index) /*! * @} */ /* end of group PIT_Register_Accessor_Macros */ /*! * @} */ /* end of group PIT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer * @{ */ /** PMC - Register Layout Typedef */ typedef struct { __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ } PMC_Type, *PMC_MemMapPtr; /* ---------------------------------------------------------------------------- -- PMC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros * @{ */ /* PMC - Register accessors */ #define PMC_LVDSC1_REG(base) ((base)->LVDSC1) #define PMC_LVDSC2_REG(base) ((base)->LVDSC2) #define PMC_REGSC_REG(base) ((base)->REGSC) /*! * @} */ /* end of group PMC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC_Register_Masks PMC Register Masks * @{ */ /* LVDSC1 Bit Fields */ #define PMC_LVDSC1_LVDV_MASK 0x3u #define PMC_LVDSC1_LVDV_SHIFT 0 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) #define PMC_LVDSC1_LVDRE_MASK 0x10u #define PMC_LVDSC1_LVDRE_SHIFT 4 #define PMC_LVDSC1_LVDIE_MASK 0x20u #define PMC_LVDSC1_LVDIE_SHIFT 5 #define PMC_LVDSC1_LVDACK_MASK 0x40u #define PMC_LVDSC1_LVDACK_SHIFT 6 #define PMC_LVDSC1_LVDF_MASK 0x80u #define PMC_LVDSC1_LVDF_SHIFT 7 /* LVDSC2 Bit Fields */ #define PMC_LVDSC2_LVWV_MASK 0x3u #define PMC_LVDSC2_LVWV_SHIFT 0 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) #define PMC_LVDSC2_LVWIE_MASK 0x20u #define PMC_LVDSC2_LVWIE_SHIFT 5 #define PMC_LVDSC2_LVWACK_MASK 0x40u #define PMC_LVDSC2_LVWACK_SHIFT 6 #define PMC_LVDSC2_LVWF_MASK 0x80u #define PMC_LVDSC2_LVWF_SHIFT 7 /* REGSC Bit Fields */ #define PMC_REGSC_BGBE_MASK 0x1u #define PMC_REGSC_BGBE_SHIFT 0 #define PMC_REGSC_REGONS_MASK 0x4u #define PMC_REGSC_REGONS_SHIFT 2 #define PMC_REGSC_ACKISO_MASK 0x8u #define PMC_REGSC_ACKISO_SHIFT 3 #define PMC_REGSC_BGEN_MASK 0x10u #define PMC_REGSC_BGEN_SHIFT 4 /*! * @} */ /* end of group PMC_Register_Masks */ /* PMC - Peripheral instance base addresses */ /** Peripheral PMC base address */ #define PMC_BASE (0x4007D000u) /** Peripheral PMC base pointer */ #define PMC ((PMC_Type *)PMC_BASE) #define PMC_BASE_PTR (PMC) /** Array initializer of PMC peripheral base addresses */ #define PMC_BASE_ADDRS { PMC_BASE } /** Array initializer of PMC peripheral base pointers */ #define PMC_BASE_PTRS { PMC } /** Interrupt vectors for the PMC peripheral type */ #define PMC_IRQS { PMC_IRQn } /* ---------------------------------------------------------------------------- -- PMC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros * @{ */ /* PMC - Register instance definitions */ /* PMC */ #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC) #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC) #define PMC_REGSC PMC_REGSC_REG(PMC) /*! * @} */ /* end of group PMC_Register_Accessor_Macros */ /*! * @} */ /* end of group PMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PORT Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer * @{ */ /** PORT - Register Layout Typedef */ typedef struct { __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ uint8_t RESERVED_0[24]; __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ } PORT_Type, *PORT_MemMapPtr; /* ---------------------------------------------------------------------------- -- PORT - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros * @{ */ /* PORT - Register accessors */ #define PORT_PCR_REG(base,index) ((base)->PCR[index]) #define PORT_GPCLR_REG(base) ((base)->GPCLR) #define PORT_GPCHR_REG(base) ((base)->GPCHR) #define PORT_ISFR_REG(base) ((base)->ISFR) /*! * @} */ /* end of group PORT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PORT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Register_Masks PORT Register Masks * @{ */ /* PCR Bit Fields */ #define PORT_PCR_PS_MASK 0x1u #define PORT_PCR_PS_SHIFT 0 #define PORT_PCR_PE_MASK 0x2u #define PORT_PCR_PE_SHIFT 1 #define PORT_PCR_SRE_MASK 0x4u #define PORT_PCR_SRE_SHIFT 2 #define PORT_PCR_PFE_MASK 0x10u #define PORT_PCR_PFE_SHIFT 4 #define PORT_PCR_DSE_MASK 0x40u #define PORT_PCR_DSE_SHIFT 6 #define PORT_PCR_MUX_MASK 0x700u #define PORT_PCR_MUX_SHIFT 8 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK) #define PORT_PCR_IRQC_MASK 0xF0000u #define PORT_PCR_IRQC_SHIFT 16 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK) #define PORT_PCR_ISF_MASK 0x1000000u #define PORT_PCR_ISF_SHIFT 24 /* GPCLR Bit Fields */ #define PORT_GPCLR_GPWD_MASK 0xFFFFu #define PORT_GPCLR_GPWD_SHIFT 0 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK) #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u #define PORT_GPCLR_GPWE_SHIFT 16 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK) /* GPCHR Bit Fields */ #define PORT_GPCHR_GPWD_MASK 0xFFFFu #define PORT_GPCHR_GPWD_SHIFT 0 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK) #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u #define PORT_GPCHR_GPWE_SHIFT 16 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK) /* ISFR Bit Fields */ #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu #define PORT_ISFR_ISF_SHIFT 0 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK) /*! * @} */ /* end of group PORT_Register_Masks */ /* PORT - Peripheral instance base addresses */ /** Peripheral PORTA base address */ #define PORTA_BASE (0x40049000u) /** Peripheral PORTA base pointer */ #define PORTA ((PORT_Type *)PORTA_BASE) #define PORTA_BASE_PTR (PORTA) /** Peripheral PORTB base address */ #define PORTB_BASE (0x4004A000u) /** Peripheral PORTB base pointer */ #define PORTB ((PORT_Type *)PORTB_BASE) #define PORTB_BASE_PTR (PORTB) /** Peripheral PORTC base address */ #define PORTC_BASE (0x4004B000u) /** Peripheral PORTC base pointer */ #define PORTC ((PORT_Type *)PORTC_BASE) #define PORTC_BASE_PTR (PORTC) /** Peripheral PORTD base address */ #define PORTD_BASE (0x4004C000u) /** Peripheral PORTD base pointer */ #define PORTD ((PORT_Type *)PORTD_BASE) #define PORTD_BASE_PTR (PORTD) /** Peripheral PORTE base address */ #define PORTE_BASE (0x4004D000u) /** Peripheral PORTE base pointer */ #define PORTE ((PORT_Type *)PORTE_BASE) #define PORTE_BASE_PTR (PORTE) /** Array initializer of PORT peripheral base addresses */ #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } /** Array initializer of PORT peripheral base pointers */ #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } /** Interrupt vectors for the PORT peripheral type */ #define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTCD_IRQn, PORTCD_IRQn, NotAvail_IRQn } /* ---------------------------------------------------------------------------- -- PORT - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros * @{ */ /* PORT - Register instance definitions */ /* PORTA */ #define PORTA_PCR0 PORT_PCR_REG(PORTA,0) #define PORTA_PCR1 PORT_PCR_REG(PORTA,1) #define PORTA_PCR2 PORT_PCR_REG(PORTA,2) #define PORTA_PCR3 PORT_PCR_REG(PORTA,3) #define PORTA_PCR4 PORT_PCR_REG(PORTA,4) #define PORTA_PCR5 PORT_PCR_REG(PORTA,5) #define PORTA_PCR6 PORT_PCR_REG(PORTA,6) #define PORTA_PCR7 PORT_PCR_REG(PORTA,7) #define PORTA_PCR8 PORT_PCR_REG(PORTA,8) #define PORTA_PCR9 PORT_PCR_REG(PORTA,9) #define PORTA_PCR10 PORT_PCR_REG(PORTA,10) #define PORTA_PCR11 PORT_PCR_REG(PORTA,11) #define PORTA_PCR12 PORT_PCR_REG(PORTA,12) #define PORTA_PCR13 PORT_PCR_REG(PORTA,13) #define PORTA_PCR14 PORT_PCR_REG(PORTA,14) #define PORTA_PCR15 PORT_PCR_REG(PORTA,15) #define PORTA_PCR16 PORT_PCR_REG(PORTA,16) #define PORTA_PCR17 PORT_PCR_REG(PORTA,17) #define PORTA_PCR18 PORT_PCR_REG(PORTA,18) #define PORTA_PCR19 PORT_PCR_REG(PORTA,19) #define PORTA_PCR20 PORT_PCR_REG(PORTA,20) #define PORTA_PCR21 PORT_PCR_REG(PORTA,21) #define PORTA_PCR22 PORT_PCR_REG(PORTA,22) #define PORTA_PCR23 PORT_PCR_REG(PORTA,23) #define PORTA_PCR24 PORT_PCR_REG(PORTA,24) #define PORTA_PCR25 PORT_PCR_REG(PORTA,25) #define PORTA_PCR26 PORT_PCR_REG(PORTA,26) #define PORTA_PCR27 PORT_PCR_REG(PORTA,27) #define PORTA_PCR28 PORT_PCR_REG(PORTA,28) #define PORTA_PCR29 PORT_PCR_REG(PORTA,29) #define PORTA_PCR30 PORT_PCR_REG(PORTA,30) #define PORTA_PCR31 PORT_PCR_REG(PORTA,31) #define PORTA_GPCLR PORT_GPCLR_REG(PORTA) #define PORTA_GPCHR PORT_GPCHR_REG(PORTA) #define PORTA_ISFR PORT_ISFR_REG(PORTA) /* PORTB */ #define PORTB_PCR0 PORT_PCR_REG(PORTB,0) #define PORTB_PCR1 PORT_PCR_REG(PORTB,1) #define PORTB_PCR2 PORT_PCR_REG(PORTB,2) #define PORTB_PCR3 PORT_PCR_REG(PORTB,3) #define PORTB_PCR4 PORT_PCR_REG(PORTB,4) #define PORTB_PCR5 PORT_PCR_REG(PORTB,5) #define PORTB_PCR6 PORT_PCR_REG(PORTB,6) #define PORTB_PCR7 PORT_PCR_REG(PORTB,7) #define PORTB_PCR8 PORT_PCR_REG(PORTB,8) #define PORTB_PCR9 PORT_PCR_REG(PORTB,9) #define PORTB_PCR10 PORT_PCR_REG(PORTB,10) #define PORTB_PCR11 PORT_PCR_REG(PORTB,11) #define PORTB_PCR12 PORT_PCR_REG(PORTB,12) #define PORTB_PCR13 PORT_PCR_REG(PORTB,13) #define PORTB_PCR14 PORT_PCR_REG(PORTB,14) #define PORTB_PCR15 PORT_PCR_REG(PORTB,15) #define PORTB_PCR16 PORT_PCR_REG(PORTB,16) #define PORTB_PCR17 PORT_PCR_REG(PORTB,17) #define PORTB_PCR18 PORT_PCR_REG(PORTB,18) #define PORTB_PCR19 PORT_PCR_REG(PORTB,19) #define PORTB_PCR20 PORT_PCR_REG(PORTB,20) #define PORTB_PCR21 PORT_PCR_REG(PORTB,21) #define PORTB_PCR22 PORT_PCR_REG(PORTB,22) #define PORTB_PCR23 PORT_PCR_REG(PORTB,23) #define PORTB_PCR24 PORT_PCR_REG(PORTB,24) #define PORTB_PCR25 PORT_PCR_REG(PORTB,25) #define PORTB_PCR26 PORT_PCR_REG(PORTB,26) #define PORTB_PCR27 PORT_PCR_REG(PORTB,27) #define PORTB_PCR28 PORT_PCR_REG(PORTB,28) #define PORTB_PCR29 PORT_PCR_REG(PORTB,29) #define PORTB_PCR30 PORT_PCR_REG(PORTB,30) #define PORTB_PCR31 PORT_PCR_REG(PORTB,31) #define PORTB_GPCLR PORT_GPCLR_REG(PORTB) #define PORTB_GPCHR PORT_GPCHR_REG(PORTB) #define PORTB_ISFR PORT_ISFR_REG(PORTB) /* PORTC */ #define PORTC_PCR0 PORT_PCR_REG(PORTC,0) #define PORTC_PCR1 PORT_PCR_REG(PORTC,1) #define PORTC_PCR2 PORT_PCR_REG(PORTC,2) #define PORTC_PCR3 PORT_PCR_REG(PORTC,3) #define PORTC_PCR4 PORT_PCR_REG(PORTC,4) #define PORTC_PCR5 PORT_PCR_REG(PORTC,5) #define PORTC_PCR6 PORT_PCR_REG(PORTC,6) #define PORTC_PCR7 PORT_PCR_REG(PORTC,7) #define PORTC_PCR8 PORT_PCR_REG(PORTC,8) #define PORTC_PCR9 PORT_PCR_REG(PORTC,9) #define PORTC_PCR10 PORT_PCR_REG(PORTC,10) #define PORTC_PCR11 PORT_PCR_REG(PORTC,11) #define PORTC_PCR12 PORT_PCR_REG(PORTC,12) #define PORTC_PCR13 PORT_PCR_REG(PORTC,13) #define PORTC_PCR14 PORT_PCR_REG(PORTC,14) #define PORTC_PCR15 PORT_PCR_REG(PORTC,15) #define PORTC_PCR16 PORT_PCR_REG(PORTC,16) #define PORTC_PCR17 PORT_PCR_REG(PORTC,17) #define PORTC_PCR18 PORT_PCR_REG(PORTC,18) #define PORTC_PCR19 PORT_PCR_REG(PORTC,19) #define PORTC_PCR20 PORT_PCR_REG(PORTC,20) #define PORTC_PCR21 PORT_PCR_REG(PORTC,21) #define PORTC_PCR22 PORT_PCR_REG(PORTC,22) #define PORTC_PCR23 PORT_PCR_REG(PORTC,23) #define PORTC_PCR24 PORT_PCR_REG(PORTC,24) #define PORTC_PCR25 PORT_PCR_REG(PORTC,25) #define PORTC_PCR26 PORT_PCR_REG(PORTC,26) #define PORTC_PCR27 PORT_PCR_REG(PORTC,27) #define PORTC_PCR28 PORT_PCR_REG(PORTC,28) #define PORTC_PCR29 PORT_PCR_REG(PORTC,29) #define PORTC_PCR30 PORT_PCR_REG(PORTC,30) #define PORTC_PCR31 PORT_PCR_REG(PORTC,31) #define PORTC_GPCLR PORT_GPCLR_REG(PORTC) #define PORTC_GPCHR PORT_GPCHR_REG(PORTC) #define PORTC_ISFR PORT_ISFR_REG(PORTC) /* PORTD */ #define PORTD_PCR0 PORT_PCR_REG(PORTD,0) #define PORTD_PCR1 PORT_PCR_REG(PORTD,1) #define PORTD_PCR2 PORT_PCR_REG(PORTD,2) #define PORTD_PCR3 PORT_PCR_REG(PORTD,3) #define PORTD_PCR4 PORT_PCR_REG(PORTD,4) #define PORTD_PCR5 PORT_PCR_REG(PORTD,5) #define PORTD_PCR6 PORT_PCR_REG(PORTD,6) #define PORTD_PCR7 PORT_PCR_REG(PORTD,7) #define PORTD_PCR8 PORT_PCR_REG(PORTD,8) #define PORTD_PCR9 PORT_PCR_REG(PORTD,9) #define PORTD_PCR10 PORT_PCR_REG(PORTD,10) #define PORTD_PCR11 PORT_PCR_REG(PORTD,11) #define PORTD_PCR12 PORT_PCR_REG(PORTD,12) #define PORTD_PCR13 PORT_PCR_REG(PORTD,13) #define PORTD_PCR14 PORT_PCR_REG(PORTD,14) #define PORTD_PCR15 PORT_PCR_REG(PORTD,15) #define PORTD_PCR16 PORT_PCR_REG(PORTD,16) #define PORTD_PCR17 PORT_PCR_REG(PORTD,17) #define PORTD_PCR18 PORT_PCR_REG(PORTD,18) #define PORTD_PCR19 PORT_PCR_REG(PORTD,19) #define PORTD_PCR20 PORT_PCR_REG(PORTD,20) #define PORTD_PCR21 PORT_PCR_REG(PORTD,21) #define PORTD_PCR22 PORT_PCR_REG(PORTD,22) #define PORTD_PCR23 PORT_PCR_REG(PORTD,23) #define PORTD_PCR24 PORT_PCR_REG(PORTD,24) #define PORTD_PCR25 PORT_PCR_REG(PORTD,25) #define PORTD_PCR26 PORT_PCR_REG(PORTD,26) #define PORTD_PCR27 PORT_PCR_REG(PORTD,27) #define PORTD_PCR28 PORT_PCR_REG(PORTD,28) #define PORTD_PCR29 PORT_PCR_REG(PORTD,29) #define PORTD_PCR30 PORT_PCR_REG(PORTD,30) #define PORTD_PCR31 PORT_PCR_REG(PORTD,31) #define PORTD_GPCLR PORT_GPCLR_REG(PORTD) #define PORTD_GPCHR PORT_GPCHR_REG(PORTD) #define PORTD_ISFR PORT_ISFR_REG(PORTD) /* PORTE */ #define PORTE_PCR0 PORT_PCR_REG(PORTE,0) #define PORTE_PCR1 PORT_PCR_REG(PORTE,1) #define PORTE_PCR2 PORT_PCR_REG(PORTE,2) #define PORTE_PCR3 PORT_PCR_REG(PORTE,3) #define PORTE_PCR4 PORT_PCR_REG(PORTE,4) #define PORTE_PCR5 PORT_PCR_REG(PORTE,5) #define PORTE_PCR6 PORT_PCR_REG(PORTE,6) #define PORTE_PCR7 PORT_PCR_REG(PORTE,7) #define PORTE_PCR8 PORT_PCR_REG(PORTE,8) #define PORTE_PCR9 PORT_PCR_REG(PORTE,9) #define PORTE_PCR10 PORT_PCR_REG(PORTE,10) #define PORTE_PCR11 PORT_PCR_REG(PORTE,11) #define PORTE_PCR12 PORT_PCR_REG(PORTE,12) #define PORTE_PCR13 PORT_PCR_REG(PORTE,13) #define PORTE_PCR14 PORT_PCR_REG(PORTE,14) #define PORTE_PCR15 PORT_PCR_REG(PORTE,15) #define PORTE_PCR16 PORT_PCR_REG(PORTE,16) #define PORTE_PCR17 PORT_PCR_REG(PORTE,17) #define PORTE_PCR18 PORT_PCR_REG(PORTE,18) #define PORTE_PCR19 PORT_PCR_REG(PORTE,19) #define PORTE_PCR20 PORT_PCR_REG(PORTE,20) #define PORTE_PCR21 PORT_PCR_REG(PORTE,21) #define PORTE_PCR22 PORT_PCR_REG(PORTE,22) #define PORTE_PCR23 PORT_PCR_REG(PORTE,23) #define PORTE_PCR24 PORT_PCR_REG(PORTE,24) #define PORTE_PCR25 PORT_PCR_REG(PORTE,25) #define PORTE_PCR26 PORT_PCR_REG(PORTE,26) #define PORTE_PCR27 PORT_PCR_REG(PORTE,27) #define PORTE_PCR28 PORT_PCR_REG(PORTE,28) #define PORTE_PCR29 PORT_PCR_REG(PORTE,29) #define PORTE_PCR30 PORT_PCR_REG(PORTE,30) #define PORTE_PCR31 PORT_PCR_REG(PORTE,31) #define PORTE_GPCLR PORT_GPCLR_REG(PORTE) #define PORTE_GPCHR PORT_GPCHR_REG(PORTE) #define PORTE_ISFR PORT_ISFR_REG(PORTE) /* PORT - Register array accessors */ #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index) #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index) #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index) #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index) #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index) /*! * @} */ /* end of group PORT_Register_Accessor_Macros */ /*! * @} */ /* end of group PORT_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RCM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer * @{ */ /** RCM - Register Layout Typedef */ typedef struct { __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ uint8_t RESERVED_0[2]; __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */ __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */ __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */ } RCM_Type, *RCM_MemMapPtr; /* ---------------------------------------------------------------------------- -- RCM - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros * @{ */ /* RCM - Register accessors */ #define RCM_SRS0_REG(base) ((base)->SRS0) #define RCM_SRS1_REG(base) ((base)->SRS1) #define RCM_RPFC_REG(base) ((base)->RPFC) #define RCM_RPFW_REG(base) ((base)->RPFW) #define RCM_FM_REG(base) ((base)->FM) #define RCM_MR_REG(base) ((base)->MR) #define RCM_SSRS0_REG(base) ((base)->SSRS0) #define RCM_SSRS1_REG(base) ((base)->SSRS1) /*! * @} */ /* end of group RCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RCM_Register_Masks RCM Register Masks * @{ */ /* SRS0 Bit Fields */ #define RCM_SRS0_WAKEUP_MASK 0x1u #define RCM_SRS0_WAKEUP_SHIFT 0 #define RCM_SRS0_LVD_MASK 0x2u #define RCM_SRS0_LVD_SHIFT 1 #define RCM_SRS0_WDOG_MASK 0x20u #define RCM_SRS0_WDOG_SHIFT 5 #define RCM_SRS0_PIN_MASK 0x40u #define RCM_SRS0_PIN_SHIFT 6 #define RCM_SRS0_POR_MASK 0x80u #define RCM_SRS0_POR_SHIFT 7 /* SRS1 Bit Fields */ #define RCM_SRS1_LOCKUP_MASK 0x2u #define RCM_SRS1_LOCKUP_SHIFT 1 #define RCM_SRS1_SW_MASK 0x4u #define RCM_SRS1_SW_SHIFT 2 #define RCM_SRS1_MDM_AP_MASK 0x8u #define RCM_SRS1_MDM_AP_SHIFT 3 #define RCM_SRS1_SACKERR_MASK 0x20u #define RCM_SRS1_SACKERR_SHIFT 5 /* RPFC Bit Fields */ #define RCM_RPFC_RSTFLTSRW_MASK 0x3u #define RCM_RPFC_RSTFLTSRW_SHIFT 0 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK) #define RCM_RPFC_RSTFLTSS_MASK 0x4u #define RCM_RPFC_RSTFLTSS_SHIFT 2 /* RPFW Bit Fields */ #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu #define RCM_RPFW_RSTFLTSEL_SHIFT 0 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK) /* FM Bit Fields */ #define RCM_FM_FORCEROM_MASK 0x6u #define RCM_FM_FORCEROM_SHIFT 1 #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_FM_FORCEROM_SHIFT))&RCM_FM_FORCEROM_MASK) /* MR Bit Fields */ #define RCM_MR_BOOTROM_MASK 0x6u #define RCM_MR_BOOTROM_SHIFT 1 #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_MR_BOOTROM_SHIFT))&RCM_MR_BOOTROM_MASK) /* SSRS0 Bit Fields */ #define RCM_SSRS0_SWAKEUP_MASK 0x1u #define RCM_SSRS0_SWAKEUP_SHIFT 0 #define RCM_SSRS0_SLVD_MASK 0x2u #define RCM_SSRS0_SLVD_SHIFT 1 #define RCM_SSRS0_SWDOG_MASK 0x20u #define RCM_SSRS0_SWDOG_SHIFT 5 #define RCM_SSRS0_SPIN_MASK 0x40u #define RCM_SSRS0_SPIN_SHIFT 6 #define RCM_SSRS0_SPOR_MASK 0x80u #define RCM_SSRS0_SPOR_SHIFT 7 /* SSRS1 Bit Fields */ #define RCM_SSRS1_SLOCKUP_MASK 0x2u #define RCM_SSRS1_SLOCKUP_SHIFT 1 #define RCM_SSRS1_SSW_MASK 0x4u #define RCM_SSRS1_SSW_SHIFT 2 #define RCM_SSRS1_SMDM_AP_MASK 0x8u #define RCM_SSRS1_SMDM_AP_SHIFT 3 #define RCM_SSRS1_SSACKERR_MASK 0x20u #define RCM_SSRS1_SSACKERR_SHIFT 5 /*! * @} */ /* end of group RCM_Register_Masks */ /* RCM - Peripheral instance base addresses */ /** Peripheral RCM base address */ #define RCM_BASE (0x4007F000u) /** Peripheral RCM base pointer */ #define RCM ((RCM_Type *)RCM_BASE) #define RCM_BASE_PTR (RCM) /** Array initializer of RCM peripheral base addresses */ #define RCM_BASE_ADDRS { RCM_BASE } /** Array initializer of RCM peripheral base pointers */ #define RCM_BASE_PTRS { RCM } /* ---------------------------------------------------------------------------- -- RCM - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros * @{ */ /* RCM - Register instance definitions */ /* RCM */ #define RCM_SRS0 RCM_SRS0_REG(RCM) #define RCM_SRS1 RCM_SRS1_REG(RCM) #define RCM_RPFC RCM_RPFC_REG(RCM) #define RCM_RPFW RCM_RPFW_REG(RCM) #define RCM_FM RCM_FM_REG(RCM) #define RCM_MR RCM_MR_REG(RCM) #define RCM_SSRS0 RCM_SSRS0_REG(RCM) #define RCM_SSRS1 RCM_SSRS1_REG(RCM) /*! * @} */ /* end of group RCM_Register_Accessor_Macros */ /*! * @} */ /* end of group RCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RFSYS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer * @{ */ /** RFSYS - Register Layout Typedef */ typedef struct { __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ } RFSYS_Type, *RFSYS_MemMapPtr; /* ---------------------------------------------------------------------------- -- RFSYS - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros * @{ */ /* RFSYS - Register accessors */ #define RFSYS_REG_REG(base,index) ((base)->REG[index]) /*! * @} */ /* end of group RFSYS_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RFSYS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RFSYS_Register_Masks RFSYS Register Masks * @{ */ /* REG Bit Fields */ #define RFSYS_REG_LL_MASK 0xFFu #define RFSYS_REG_LL_SHIFT 0 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK) #define RFSYS_REG_LH_MASK 0xFF00u #define RFSYS_REG_LH_SHIFT 8 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK) #define RFSYS_REG_HL_MASK 0xFF0000u #define RFSYS_REG_HL_SHIFT 16 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK) #define RFSYS_REG_HH_MASK 0xFF000000u #define RFSYS_REG_HH_SHIFT 24 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK) /*! * @} */ /* end of group RFSYS_Register_Masks */ /* RFSYS - Peripheral instance base addresses */ /** Peripheral RFSYS base address */ #define RFSYS_BASE (0x40041000u) /** Peripheral RFSYS base pointer */ #define RFSYS ((RFSYS_Type *)RFSYS_BASE) #define RFSYS_BASE_PTR (RFSYS) /** Array initializer of RFSYS peripheral base addresses */ #define RFSYS_BASE_ADDRS { RFSYS_BASE } /** Array initializer of RFSYS peripheral base pointers */ #define RFSYS_BASE_PTRS { RFSYS } /* ---------------------------------------------------------------------------- -- RFSYS - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros * @{ */ /* RFSYS - Register instance definitions */ /* RFSYS */ #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0) #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1) #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2) #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3) #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4) #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5) #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6) #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7) /* RFSYS - Register array accessors */ #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index) /*! * @} */ /* end of group RFSYS_Register_Accessor_Macros */ /*! * @} */ /* end of group RFSYS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- ROM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer * @{ */ /** ROM - Register Layout Typedef */ typedef struct { __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ uint8_t RESERVED_0[4028]; __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ } ROM_Type, *ROM_MemMapPtr; /* ---------------------------------------------------------------------------- -- ROM - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros * @{ */ /* ROM - Register accessors */ #define ROM_ENTRY_REG(base,index) ((base)->ENTRY[index]) #define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK) #define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS) #define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4) #define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5) #define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6) #define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7) #define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0) #define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1) #define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2) #define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3) #define ROM_COMPID_REG(base,index) ((base)->COMPID[index]) /*! * @} */ /* end of group ROM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ROM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ROM_Register_Masks ROM Register Masks * @{ */ /* ENTRY Bit Fields */ #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu #define ROM_ENTRY_ENTRY_SHIFT 0 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK) /* TABLEMARK Bit Fields */ #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu #define ROM_TABLEMARK_MARK_SHIFT 0 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK) /* SYSACCESS Bit Fields */ #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu #define ROM_SYSACCESS_SYSACCESS_SHIFT 0 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK) /* PERIPHID4 Bit Fields */ #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu #define ROM_PERIPHID4_PERIPHID_SHIFT 0 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK) /* PERIPHID5 Bit Fields */ #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu #define ROM_PERIPHID5_PERIPHID_SHIFT 0 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK) /* PERIPHID6 Bit Fields */ #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu #define ROM_PERIPHID6_PERIPHID_SHIFT 0 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK) /* PERIPHID7 Bit Fields */ #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu #define ROM_PERIPHID7_PERIPHID_SHIFT 0 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK) /* PERIPHID0 Bit Fields */ #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu #define ROM_PERIPHID0_PERIPHID_SHIFT 0 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK) /* PERIPHID1 Bit Fields */ #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu #define ROM_PERIPHID1_PERIPHID_SHIFT 0 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK) /* PERIPHID2 Bit Fields */ #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu #define ROM_PERIPHID2_PERIPHID_SHIFT 0 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK) /* PERIPHID3 Bit Fields */ #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu #define ROM_PERIPHID3_PERIPHID_SHIFT 0 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK) /* COMPID Bit Fields */ #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu #define ROM_COMPID_COMPID_SHIFT 0 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK) /*! * @} */ /* end of group ROM_Register_Masks */ /* ROM - Peripheral instance base addresses */ /** Peripheral ROM base address */ #define ROM_BASE (0xF0002000u) /** Peripheral ROM base pointer */ #define ROM ((ROM_Type *)ROM_BASE) #define ROM_BASE_PTR (ROM) /** Array initializer of ROM peripheral base addresses */ #define ROM_BASE_ADDRS { ROM_BASE } /** Array initializer of ROM peripheral base pointers */ #define ROM_BASE_PTRS { ROM } /* ---------------------------------------------------------------------------- -- ROM - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros * @{ */ /* ROM - Register instance definitions */ /* ROM */ #define ROM_ENTRY0 ROM_ENTRY_REG(ROM,0) #define ROM_ENTRY1 ROM_ENTRY_REG(ROM,1) #define ROM_ENTRY2 ROM_ENTRY_REG(ROM,2) #define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM) #define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM) #define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM) #define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM) #define ROM_PERIPHID6 ROM_PERIPHID6_REG(ROM) #define ROM_PERIPHID7 ROM_PERIPHID7_REG(ROM) #define ROM_PERIPHID0 ROM_PERIPHID0_REG(ROM) #define ROM_PERIPHID1 ROM_PERIPHID1_REG(ROM) #define ROM_PERIPHID2 ROM_PERIPHID2_REG(ROM) #define ROM_PERIPHID3 ROM_PERIPHID3_REG(ROM) #define ROM_COMPID0 ROM_COMPID_REG(ROM,0) #define ROM_COMPID1 ROM_COMPID_REG(ROM,1) #define ROM_COMPID2 ROM_COMPID_REG(ROM,2) #define ROM_COMPID3 ROM_COMPID_REG(ROM,3) /* ROM - Register array accessors */ #define ROM_ENTRY(index) ROM_ENTRY_REG(ROM,index) #define ROM_COMPID(index) ROM_COMPID_REG(ROM,index) /*! * @} */ /* end of group ROM_Register_Accessor_Macros */ /*! * @} */ /* end of group ROM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- RTC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer * @{ */ /** RTC - Register Layout Typedef */ typedef struct { __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ } RTC_Type, *RTC_MemMapPtr; /* ---------------------------------------------------------------------------- -- RTC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros * @{ */ /* RTC - Register accessors */ #define RTC_TSR_REG(base) ((base)->TSR) #define RTC_TPR_REG(base) ((base)->TPR) #define RTC_TAR_REG(base) ((base)->TAR) #define RTC_TCR_REG(base) ((base)->TCR) #define RTC_CR_REG(base) ((base)->CR) #define RTC_SR_REG(base) ((base)->SR) #define RTC_LR_REG(base) ((base)->LR) #define RTC_IER_REG(base) ((base)->IER) /*! * @} */ /* end of group RTC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RTC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Register_Masks RTC Register Masks * @{ */ /* TSR Bit Fields */ #define RTC_TSR_TSR_MASK 0xFFFFFFFFu #define RTC_TSR_TSR_SHIFT 0 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK) /* TPR Bit Fields */ #define RTC_TPR_TPR_MASK 0xFFFFu #define RTC_TPR_TPR_SHIFT 0 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK) /* TAR Bit Fields */ #define RTC_TAR_TAR_MASK 0xFFFFFFFFu #define RTC_TAR_TAR_SHIFT 0 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK) /* TCR Bit Fields */ #define RTC_TCR_TCR_MASK 0xFFu #define RTC_TCR_TCR_SHIFT 0 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK) #define RTC_TCR_CIR_MASK 0xFF00u #define RTC_TCR_CIR_SHIFT 8 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK) #define RTC_TCR_TCV_MASK 0xFF0000u #define RTC_TCR_TCV_SHIFT 16 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK) #define RTC_TCR_CIC_MASK 0xFF000000u #define RTC_TCR_CIC_SHIFT 24 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK) /* CR Bit Fields */ #define RTC_CR_SWR_MASK 0x1u #define RTC_CR_SWR_SHIFT 0 #define RTC_CR_WPE_MASK 0x2u #define RTC_CR_WPE_SHIFT 1 #define RTC_CR_SUP_MASK 0x4u #define RTC_CR_SUP_SHIFT 2 #define RTC_CR_UM_MASK 0x8u #define RTC_CR_UM_SHIFT 3 #define RTC_CR_WPS_MASK 0x10u #define RTC_CR_WPS_SHIFT 4 #define RTC_CR_OSCE_MASK 0x100u #define RTC_CR_OSCE_SHIFT 8 #define RTC_CR_CLKO_MASK 0x200u #define RTC_CR_CLKO_SHIFT 9 #define RTC_CR_SC16P_MASK 0x400u #define RTC_CR_SC16P_SHIFT 10 #define RTC_CR_SC8P_MASK 0x800u #define RTC_CR_SC8P_SHIFT 11 #define RTC_CR_SC4P_MASK 0x1000u #define RTC_CR_SC4P_SHIFT 12 #define RTC_CR_SC2P_MASK 0x2000u #define RTC_CR_SC2P_SHIFT 13 /* SR Bit Fields */ #define RTC_SR_TIF_MASK 0x1u #define RTC_SR_TIF_SHIFT 0 #define RTC_SR_TOF_MASK 0x2u #define RTC_SR_TOF_SHIFT 1 #define RTC_SR_TAF_MASK 0x4u #define RTC_SR_TAF_SHIFT 2 #define RTC_SR_TCE_MASK 0x10u #define RTC_SR_TCE_SHIFT 4 /* LR Bit Fields */ #define RTC_LR_TCL_MASK 0x8u #define RTC_LR_TCL_SHIFT 3 #define RTC_LR_CRL_MASK 0x10u #define RTC_LR_CRL_SHIFT 4 #define RTC_LR_SRL_MASK 0x20u #define RTC_LR_SRL_SHIFT 5 #define RTC_LR_LRL_MASK 0x40u #define RTC_LR_LRL_SHIFT 6 /* IER Bit Fields */ #define RTC_IER_TIIE_MASK 0x1u #define RTC_IER_TIIE_SHIFT 0 #define RTC_IER_TOIE_MASK 0x2u #define RTC_IER_TOIE_SHIFT 1 #define RTC_IER_TAIE_MASK 0x4u #define RTC_IER_TAIE_SHIFT 2 #define RTC_IER_TSIE_MASK 0x10u #define RTC_IER_TSIE_SHIFT 4 #define RTC_IER_WPON_MASK 0x80u #define RTC_IER_WPON_SHIFT 7 /*! * @} */ /* end of group RTC_Register_Masks */ /* RTC - Peripheral instance base addresses */ /** Peripheral RTC base address */ #define RTC_BASE (0x4003D000u) /** Peripheral RTC base pointer */ #define RTC ((RTC_Type *)RTC_BASE) #define RTC_BASE_PTR (RTC) /** Array initializer of RTC peripheral base addresses */ #define RTC_BASE_ADDRS { RTC_BASE } /** Array initializer of RTC peripheral base pointers */ #define RTC_BASE_PTRS { RTC } /** Interrupt vectors for the RTC peripheral type */ #define RTC_IRQS { RTC_IRQn } #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } /* ---------------------------------------------------------------------------- -- RTC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros * @{ */ /* RTC - Register instance definitions */ /* RTC */ #define RTC_TSR RTC_TSR_REG(RTC) #define RTC_TPR RTC_TPR_REG(RTC) #define RTC_TAR RTC_TAR_REG(RTC) #define RTC_TCR RTC_TCR_REG(RTC) #define RTC_CR RTC_CR_REG(RTC) #define RTC_SR RTC_SR_REG(RTC) #define RTC_LR RTC_LR_REG(RTC) #define RTC_IER RTC_IER_REG(RTC) /*! * @} */ /* end of group RTC_Register_Accessor_Macros */ /*! * @} */ /* end of group RTC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SIM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer * @{ */ /** SIM - Register Layout Typedef */ typedef struct { __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ uint8_t RESERVED_0[4092]; __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ uint8_t RESERVED_1[4]; __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ uint8_t RESERVED_2[4]; __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ uint8_t RESERVED_3[8]; __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ uint8_t RESERVED_4[12]; __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ uint8_t RESERVED_5[4]; __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ uint8_t RESERVED_6[4]; __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ uint8_t RESERVED_7[156]; __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */ __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */ } SIM_Type, *SIM_MemMapPtr; /* ---------------------------------------------------------------------------- -- SIM - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros * @{ */ /* SIM - Register accessors */ #define SIM_SOPT1_REG(base) ((base)->SOPT1) #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) #define SIM_SOPT2_REG(base) ((base)->SOPT2) #define SIM_SOPT4_REG(base) ((base)->SOPT4) #define SIM_SOPT5_REG(base) ((base)->SOPT5) #define SIM_SOPT7_REG(base) ((base)->SOPT7) #define SIM_SDID_REG(base) ((base)->SDID) #define SIM_SCGC4_REG(base) ((base)->SCGC4) #define SIM_SCGC5_REG(base) ((base)->SCGC5) #define SIM_SCGC6_REG(base) ((base)->SCGC6) #define SIM_SCGC7_REG(base) ((base)->SCGC7) #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) #define SIM_FCFG1_REG(base) ((base)->FCFG1) #define SIM_FCFG2_REG(base) ((base)->FCFG2) #define SIM_UIDMH_REG(base) ((base)->UIDMH) #define SIM_UIDML_REG(base) ((base)->UIDML) #define SIM_UIDL_REG(base) ((base)->UIDL) #define SIM_COPC_REG(base) ((base)->COPC) #define SIM_SRVCOP_REG(base) ((base)->SRVCOP) /*! * @} */ /* end of group SIM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Register_Masks SIM Register Masks * @{ */ /* SOPT1 Bit Fields */ #define SIM_SOPT1_OSC32KOUT_MASK 0x30000u #define SIM_SOPT1_OSC32KOUT_SHIFT 16 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK) #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u #define SIM_SOPT1_OSC32KSEL_SHIFT 18 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK) #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u #define SIM_SOPT1_USBVSTBY_SHIFT 29 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u #define SIM_SOPT1_USBSSTBY_SHIFT 30 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u #define SIM_SOPT1_USBREGEN_SHIFT 31 /* SOPT1CFG Bit Fields */ #define SIM_SOPT1CFG_URWE_MASK 0x1000000u #define SIM_SOPT1CFG_URWE_SHIFT 24 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u #define SIM_SOPT1CFG_UVSWE_SHIFT 25 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u #define SIM_SOPT1CFG_USSWE_SHIFT 26 /* SOPT2 Bit Fields */ #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u #define SIM_SOPT2_CLKOUTSEL_SHIFT 5 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK) #define SIM_SOPT2_USBSRC_MASK 0x40000u #define SIM_SOPT2_USBSRC_SHIFT 18 #define SIM_SOPT2_FLEXIOSRC_MASK 0xC00000u #define SIM_SOPT2_FLEXIOSRC_SHIFT 22 #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FLEXIOSRC_SHIFT))&SIM_SOPT2_FLEXIOSRC_MASK) #define SIM_SOPT2_TPMSRC_MASK 0x3000000u #define SIM_SOPT2_TPMSRC_SHIFT 24 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK) #define SIM_SOPT2_LPUART0SRC_MASK 0xC000000u #define SIM_SOPT2_LPUART0SRC_SHIFT 26 #define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART0SRC_SHIFT))&SIM_SOPT2_LPUART0SRC_MASK) #define SIM_SOPT2_LPUART1SRC_MASK 0x30000000u #define SIM_SOPT2_LPUART1SRC_SHIFT 28 #define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART1SRC_SHIFT))&SIM_SOPT2_LPUART1SRC_MASK) /* SOPT4 Bit Fields */ #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK) #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26 /* SOPT5 Bit Fields */ #define SIM_SOPT5_LPUART0TXSRC_MASK 0x3u #define SIM_SOPT5_LPUART0TXSRC_SHIFT 0 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0TXSRC_SHIFT))&SIM_SOPT5_LPUART0TXSRC_MASK) #define SIM_SOPT5_LPUART0RXSRC_MASK 0x4u #define SIM_SOPT5_LPUART0RXSRC_SHIFT 2 #define SIM_SOPT5_LPUART1TXSRC_MASK 0x30u #define SIM_SOPT5_LPUART1TXSRC_SHIFT 4 #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART1TXSRC_SHIFT))&SIM_SOPT5_LPUART1TXSRC_MASK) #define SIM_SOPT5_LPUART1RXSRC_MASK 0x40u #define SIM_SOPT5_LPUART1RXSRC_SHIFT 6 #define SIM_SOPT5_LPUART0ODE_MASK 0x10000u #define SIM_SOPT5_LPUART0ODE_SHIFT 16 #define SIM_SOPT5_LPUART1ODE_MASK 0x20000u #define SIM_SOPT5_LPUART1ODE_SHIFT 17 #define SIM_SOPT5_UART2ODE_MASK 0x40000u #define SIM_SOPT5_UART2ODE_SHIFT 18 /* SOPT7 Bit Fields */ #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK) #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7 /* SDID Bit Fields */ #define SIM_SDID_PINID_MASK 0xFu #define SIM_SDID_PINID_SHIFT 0 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK) #define SIM_SDID_REVID_MASK 0xF000u #define SIM_SDID_REVID_SHIFT 12 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK) #define SIM_SDID_SRAMSIZE_MASK 0xF0000u #define SIM_SDID_SRAMSIZE_SHIFT 16 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK) #define SIM_SDID_SERIESID_MASK 0xF00000u #define SIM_SDID_SERIESID_SHIFT 20 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK) #define SIM_SDID_SUBFAMID_MASK 0xF000000u #define SIM_SDID_SUBFAMID_SHIFT 24 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK) #define SIM_SDID_FAMID_MASK 0xF0000000u #define SIM_SDID_FAMID_SHIFT 28 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK) /* SCGC4 Bit Fields */ #define SIM_SCGC4_I2C0_MASK 0x40u #define SIM_SCGC4_I2C0_SHIFT 6 #define SIM_SCGC4_I2C1_MASK 0x80u #define SIM_SCGC4_I2C1_SHIFT 7 #define SIM_SCGC4_UART2_MASK 0x1000u #define SIM_SCGC4_UART2_SHIFT 12 #define SIM_SCGC4_USBFS_MASK 0x40000u #define SIM_SCGC4_USBFS_SHIFT 18 #define SIM_SCGC4_CMP0_MASK 0x80000u #define SIM_SCGC4_CMP0_SHIFT 19 #define SIM_SCGC4_VREF_MASK 0x100000u #define SIM_SCGC4_VREF_SHIFT 20 #define SIM_SCGC4_SPI0_MASK 0x400000u #define SIM_SCGC4_SPI0_SHIFT 22 #define SIM_SCGC4_SPI1_MASK 0x800000u #define SIM_SCGC4_SPI1_SHIFT 23 /* SCGC5 Bit Fields */ #define SIM_SCGC5_LPTMR_MASK 0x1u #define SIM_SCGC5_LPTMR_SHIFT 0 #define SIM_SCGC5_PORTA_MASK 0x200u #define SIM_SCGC5_PORTA_SHIFT 9 #define SIM_SCGC5_PORTB_MASK 0x400u #define SIM_SCGC5_PORTB_SHIFT 10 #define SIM_SCGC5_PORTC_MASK 0x800u #define SIM_SCGC5_PORTC_SHIFT 11 #define SIM_SCGC5_PORTD_MASK 0x1000u #define SIM_SCGC5_PORTD_SHIFT 12 #define SIM_SCGC5_PORTE_MASK 0x2000u #define SIM_SCGC5_PORTE_SHIFT 13 #define SIM_SCGC5_SLCD_MASK 0x80000u #define SIM_SCGC5_SLCD_SHIFT 19 #define SIM_SCGC5_LPUART0_MASK 0x100000u #define SIM_SCGC5_LPUART0_SHIFT 20 #define SIM_SCGC5_LPUART1_MASK 0x200000u #define SIM_SCGC5_LPUART1_SHIFT 21 #define SIM_SCGC5_FLEXIO_MASK 0x80000000u #define SIM_SCGC5_FLEXIO_SHIFT 31 /* SCGC6 Bit Fields */ #define SIM_SCGC6_FTF_MASK 0x1u #define SIM_SCGC6_FTF_SHIFT 0 #define SIM_SCGC6_DMAMUX_MASK 0x2u #define SIM_SCGC6_DMAMUX_SHIFT 1 #define SIM_SCGC6_I2S_MASK 0x8000u #define SIM_SCGC6_I2S_SHIFT 15 #define SIM_SCGC6_PIT_MASK 0x800000u #define SIM_SCGC6_PIT_SHIFT 23 #define SIM_SCGC6_TPM0_MASK 0x1000000u #define SIM_SCGC6_TPM0_SHIFT 24 #define SIM_SCGC6_TPM1_MASK 0x2000000u #define SIM_SCGC6_TPM1_SHIFT 25 #define SIM_SCGC6_TPM2_MASK 0x4000000u #define SIM_SCGC6_TPM2_SHIFT 26 #define SIM_SCGC6_ADC0_MASK 0x8000000u #define SIM_SCGC6_ADC0_SHIFT 27 #define SIM_SCGC6_RTC_MASK 0x20000000u #define SIM_SCGC6_RTC_SHIFT 29 #define SIM_SCGC6_DAC0_MASK 0x80000000u #define SIM_SCGC6_DAC0_SHIFT 31 /* SCGC7 Bit Fields */ #define SIM_SCGC7_DMA_MASK 0x100u #define SIM_SCGC7_DMA_SHIFT 8 /* CLKDIV1 Bit Fields */ #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u #define SIM_CLKDIV1_OUTDIV4_SHIFT 16 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK) #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u #define SIM_CLKDIV1_OUTDIV1_SHIFT 28 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK) /* FCFG1 Bit Fields */ #define SIM_FCFG1_FLASHDIS_MASK 0x1u #define SIM_FCFG1_FLASHDIS_SHIFT 0 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u #define SIM_FCFG1_FLASHDOZE_SHIFT 1 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u #define SIM_FCFG1_PFSIZE_SHIFT 24 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK) /* FCFG2 Bit Fields */ #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u #define SIM_FCFG2_MAXADDR1_SHIFT 16 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK) #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u #define SIM_FCFG2_MAXADDR0_SHIFT 24 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK) /* UIDMH Bit Fields */ #define SIM_UIDMH_UID_MASK 0xFFFFu #define SIM_UIDMH_UID_SHIFT 0 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK) /* UIDML Bit Fields */ #define SIM_UIDML_UID_MASK 0xFFFFFFFFu #define SIM_UIDML_UID_SHIFT 0 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK) /* UIDL Bit Fields */ #define SIM_UIDL_UID_MASK 0xFFFFFFFFu #define SIM_UIDL_UID_SHIFT 0 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK) /* COPC Bit Fields */ #define SIM_COPC_COPW_MASK 0x1u #define SIM_COPC_COPW_SHIFT 0 #define SIM_COPC_COPCLKS_MASK 0x2u #define SIM_COPC_COPCLKS_SHIFT 1 #define SIM_COPC_COPT_MASK 0xCu #define SIM_COPC_COPT_SHIFT 2 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK) #define SIM_COPC_COPSTPEN_MASK 0x10u #define SIM_COPC_COPSTPEN_SHIFT 4 #define SIM_COPC_COPDBGEN_MASK 0x20u #define SIM_COPC_COPDBGEN_SHIFT 5 #define SIM_COPC_COPCLKSEL_MASK 0xC0u #define SIM_COPC_COPCLKSEL_SHIFT 6 #define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPCLKSEL_SHIFT))&SIM_COPC_COPCLKSEL_MASK) /* SRVCOP Bit Fields */ #define SIM_SRVCOP_SRVCOP_MASK 0xFFu #define SIM_SRVCOP_SRVCOP_SHIFT 0 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK) /*! * @} */ /* end of group SIM_Register_Masks */ /* SIM - Peripheral instance base addresses */ /** Peripheral SIM base address */ #define SIM_BASE (0x40047000u) /** Peripheral SIM base pointer */ #define SIM ((SIM_Type *)SIM_BASE) #define SIM_BASE_PTR (SIM) /** Array initializer of SIM peripheral base addresses */ #define SIM_BASE_ADDRS { SIM_BASE } /** Array initializer of SIM peripheral base pointers */ #define SIM_BASE_PTRS { SIM } /* ---------------------------------------------------------------------------- -- SIM - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros * @{ */ /* SIM - Register instance definitions */ /* SIM */ #define SIM_SOPT1 SIM_SOPT1_REG(SIM) #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM) #define SIM_SOPT2 SIM_SOPT2_REG(SIM) #define SIM_SOPT4 SIM_SOPT4_REG(SIM) #define SIM_SOPT5 SIM_SOPT5_REG(SIM) #define SIM_SOPT7 SIM_SOPT7_REG(SIM) #define SIM_SDID SIM_SDID_REG(SIM) #define SIM_SCGC4 SIM_SCGC4_REG(SIM) #define SIM_SCGC5 SIM_SCGC5_REG(SIM) #define SIM_SCGC6 SIM_SCGC6_REG(SIM) #define SIM_SCGC7 SIM_SCGC7_REG(SIM) #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM) #define SIM_FCFG1 SIM_FCFG1_REG(SIM) #define SIM_FCFG2 SIM_FCFG2_REG(SIM) #define SIM_UIDMH SIM_UIDMH_REG(SIM) #define SIM_UIDML SIM_UIDML_REG(SIM) #define SIM_UIDL SIM_UIDL_REG(SIM) #define SIM_COPC SIM_COPC_REG(SIM) #define SIM_SRVCOP SIM_SRVCOP_REG(SIM) /*! * @} */ /* end of group SIM_Register_Accessor_Macros */ /*! * @} */ /* end of group SIM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SMC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer * @{ */ /** SMC - Register Layout Typedef */ typedef struct { __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ } SMC_Type, *SMC_MemMapPtr; /* ---------------------------------------------------------------------------- -- SMC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros * @{ */ /* SMC - Register accessors */ #define SMC_PMPROT_REG(base) ((base)->PMPROT) #define SMC_PMCTRL_REG(base) ((base)->PMCTRL) #define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL) #define SMC_PMSTAT_REG(base) ((base)->PMSTAT) /*! * @} */ /* end of group SMC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Register_Masks SMC Register Masks * @{ */ /* PMPROT Bit Fields */ #define SMC_PMPROT_AVLLS_MASK 0x2u #define SMC_PMPROT_AVLLS_SHIFT 1 #define SMC_PMPROT_ALLS_MASK 0x8u #define SMC_PMPROT_ALLS_SHIFT 3 #define SMC_PMPROT_AVLP_MASK 0x20u #define SMC_PMPROT_AVLP_SHIFT 5 /* PMCTRL Bit Fields */ #define SMC_PMCTRL_STOPM_MASK 0x7u #define SMC_PMCTRL_STOPM_SHIFT 0 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK) #define SMC_PMCTRL_STOPA_MASK 0x8u #define SMC_PMCTRL_STOPA_SHIFT 3 #define SMC_PMCTRL_RUNM_MASK 0x60u #define SMC_PMCTRL_RUNM_SHIFT 5 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK) /* STOPCTRL Bit Fields */ #define SMC_STOPCTRL_VLLSM_MASK 0x7u #define SMC_STOPCTRL_VLLSM_SHIFT 0 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK) #define SMC_STOPCTRL_PORPO_MASK 0x20u #define SMC_STOPCTRL_PORPO_SHIFT 5 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u #define SMC_STOPCTRL_PSTOPO_SHIFT 6 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK) /* PMSTAT Bit Fields */ #define SMC_PMSTAT_PMSTAT_MASK 0xFFu #define SMC_PMSTAT_PMSTAT_SHIFT 0 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK) /*! * @} */ /* end of group SMC_Register_Masks */ /* SMC - Peripheral instance base addresses */ /** Peripheral SMC base address */ #define SMC_BASE (0x4007E000u) /** Peripheral SMC base pointer */ #define SMC ((SMC_Type *)SMC_BASE) #define SMC_BASE_PTR (SMC) /** Array initializer of SMC peripheral base addresses */ #define SMC_BASE_ADDRS { SMC_BASE } /** Array initializer of SMC peripheral base pointers */ #define SMC_BASE_PTRS { SMC } /* ---------------------------------------------------------------------------- -- SMC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros * @{ */ /* SMC - Register instance definitions */ /* SMC */ #define SMC_PMPROT SMC_PMPROT_REG(SMC) #define SMC_PMCTRL SMC_PMCTRL_REG(SMC) #define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC) #define SMC_PMSTAT SMC_PMSTAT_REG(SMC) /*! * @} */ /* end of group SMC_Register_Accessor_Macros */ /*! * @} */ /* end of group SMC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- SPI Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer * @{ */ /** SPI - Register Layout Typedef */ typedef struct { __I uint8_t S; /**< SPI Status Register, offset: 0x0 */ __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */ __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */ __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */ __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */ __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */ __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */ __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */ uint8_t RESERVED_0[2]; __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */ __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */ } SPI_Type, *SPI_MemMapPtr; /* ---------------------------------------------------------------------------- -- SPI - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros * @{ */ /* SPI - Register accessors */ #define SPI_S_REG(base) ((base)->S) #define SPI_BR_REG(base) ((base)->BR) #define SPI_C2_REG(base) ((base)->C2) #define SPI_C1_REG(base) ((base)->C1) #define SPI_ML_REG(base) ((base)->ML) #define SPI_MH_REG(base) ((base)->MH) #define SPI_DL_REG(base) ((base)->DL) #define SPI_DH_REG(base) ((base)->DH) #define SPI_CI_REG(base) ((base)->CI) #define SPI_C3_REG(base) ((base)->C3) /*! * @} */ /* end of group SPI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPI_Register_Masks SPI Register Masks * @{ */ /* S Bit Fields */ #define SPI_S_RFIFOEF_MASK 0x1u #define SPI_S_RFIFOEF_SHIFT 0 #define SPI_S_TXFULLF_MASK 0x2u #define SPI_S_TXFULLF_SHIFT 1 #define SPI_S_TNEAREF_MASK 0x4u #define SPI_S_TNEAREF_SHIFT 2 #define SPI_S_RNFULLF_MASK 0x8u #define SPI_S_RNFULLF_SHIFT 3 #define SPI_S_MODF_MASK 0x10u #define SPI_S_MODF_SHIFT 4 #define SPI_S_SPTEF_MASK 0x20u #define SPI_S_SPTEF_SHIFT 5 #define SPI_S_SPMF_MASK 0x40u #define SPI_S_SPMF_SHIFT 6 #define SPI_S_SPRF_MASK 0x80u #define SPI_S_SPRF_SHIFT 7 /* BR Bit Fields */ #define SPI_BR_SPR_MASK 0xFu #define SPI_BR_SPR_SHIFT 0 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK) #define SPI_BR_SPPR_MASK 0x70u #define SPI_BR_SPPR_SHIFT 4 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK) /* C2 Bit Fields */ #define SPI_C2_SPC0_MASK 0x1u #define SPI_C2_SPC0_SHIFT 0 #define SPI_C2_SPISWAI_MASK 0x2u #define SPI_C2_SPISWAI_SHIFT 1 #define SPI_C2_RXDMAE_MASK 0x4u #define SPI_C2_RXDMAE_SHIFT 2 #define SPI_C2_BIDIROE_MASK 0x8u #define SPI_C2_BIDIROE_SHIFT 3 #define SPI_C2_MODFEN_MASK 0x10u #define SPI_C2_MODFEN_SHIFT 4 #define SPI_C2_TXDMAE_MASK 0x20u #define SPI_C2_TXDMAE_SHIFT 5 #define SPI_C2_SPIMODE_MASK 0x40u #define SPI_C2_SPIMODE_SHIFT 6 #define SPI_C2_SPMIE_MASK 0x80u #define SPI_C2_SPMIE_SHIFT 7 /* C1 Bit Fields */ #define SPI_C1_LSBFE_MASK 0x1u #define SPI_C1_LSBFE_SHIFT 0 #define SPI_C1_SSOE_MASK 0x2u #define SPI_C1_SSOE_SHIFT 1 #define SPI_C1_CPHA_MASK 0x4u #define SPI_C1_CPHA_SHIFT 2 #define SPI_C1_CPOL_MASK 0x8u #define SPI_C1_CPOL_SHIFT 3 #define SPI_C1_MSTR_MASK 0x10u #define SPI_C1_MSTR_SHIFT 4 #define SPI_C1_SPTIE_MASK 0x20u #define SPI_C1_SPTIE_SHIFT 5 #define SPI_C1_SPE_MASK 0x40u #define SPI_C1_SPE_SHIFT 6 #define SPI_C1_SPIE_MASK 0x80u #define SPI_C1_SPIE_SHIFT 7 /* ML Bit Fields */ #define SPI_ML_Bits_MASK 0xFFu #define SPI_ML_Bits_SHIFT 0 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK) /* MH Bit Fields */ #define SPI_MH_Bits_MASK 0xFFu #define SPI_MH_Bits_SHIFT 0 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK) /* DL Bit Fields */ #define SPI_DL_Bits_MASK 0xFFu #define SPI_DL_Bits_SHIFT 0 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK) /* DH Bit Fields */ #define SPI_DH_Bits_MASK 0xFFu #define SPI_DH_Bits_SHIFT 0 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK) /* CI Bit Fields */ #define SPI_CI_SPRFCI_MASK 0x1u #define SPI_CI_SPRFCI_SHIFT 0 #define SPI_CI_SPTEFCI_MASK 0x2u #define SPI_CI_SPTEFCI_SHIFT 1 #define SPI_CI_RNFULLFCI_MASK 0x4u #define SPI_CI_RNFULLFCI_SHIFT 2 #define SPI_CI_TNEAREFCI_MASK 0x8u #define SPI_CI_TNEAREFCI_SHIFT 3 #define SPI_CI_RXFOF_MASK 0x10u #define SPI_CI_RXFOF_SHIFT 4 #define SPI_CI_TXFOF_MASK 0x20u #define SPI_CI_TXFOF_SHIFT 5 #define SPI_CI_RXFERR_MASK 0x40u #define SPI_CI_RXFERR_SHIFT 6 #define SPI_CI_TXFERR_MASK 0x80u #define SPI_CI_TXFERR_SHIFT 7 /* C3 Bit Fields */ #define SPI_C3_FIFOMODE_MASK 0x1u #define SPI_C3_FIFOMODE_SHIFT 0 #define SPI_C3_RNFULLIEN_MASK 0x2u #define SPI_C3_RNFULLIEN_SHIFT 1 #define SPI_C3_TNEARIEN_MASK 0x4u #define SPI_C3_TNEARIEN_SHIFT 2 #define SPI_C3_INTCLR_MASK 0x8u #define SPI_C3_INTCLR_SHIFT 3 #define SPI_C3_RNFULLF_MARK_MASK 0x10u #define SPI_C3_RNFULLF_MARK_SHIFT 4 #define SPI_C3_TNEAREF_MARK_MASK 0x20u #define SPI_C3_TNEAREF_MARK_SHIFT 5 /*! * @} */ /* end of group SPI_Register_Masks */ /* SPI - Peripheral instance base addresses */ /** Peripheral SPI0 base address */ #define SPI0_BASE (0x40076000u) /** Peripheral SPI0 base pointer */ #define SPI0 ((SPI_Type *)SPI0_BASE) #define SPI0_BASE_PTR (SPI0) /** Peripheral SPI1 base address */ #define SPI1_BASE (0x40077000u) /** Peripheral SPI1 base pointer */ #define SPI1 ((SPI_Type *)SPI1_BASE) #define SPI1_BASE_PTR (SPI1) /** Array initializer of SPI peripheral base addresses */ #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } /** Array initializer of SPI peripheral base pointers */ #define SPI_BASE_PTRS { SPI0, SPI1 } /** Interrupt vectors for the SPI peripheral type */ #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } /* ---------------------------------------------------------------------------- -- SPI - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros * @{ */ /* SPI - Register instance definitions */ /* SPI0 */ #define SPI0_S SPI_S_REG(SPI0) #define SPI0_BR SPI_BR_REG(SPI0) #define SPI0_C2 SPI_C2_REG(SPI0) #define SPI0_C1 SPI_C1_REG(SPI0) #define SPI0_ML SPI_ML_REG(SPI0) #define SPI0_MH SPI_MH_REG(SPI0) #define SPI0_DL SPI_DL_REG(SPI0) #define SPI0_DH SPI_DH_REG(SPI0) /* SPI1 */ #define SPI1_S SPI_S_REG(SPI1) #define SPI1_BR SPI_BR_REG(SPI1) #define SPI1_C2 SPI_C2_REG(SPI1) #define SPI1_C1 SPI_C1_REG(SPI1) #define SPI1_ML SPI_ML_REG(SPI1) #define SPI1_MH SPI_MH_REG(SPI1) #define SPI1_DL SPI_DL_REG(SPI1) #define SPI1_DH SPI_DH_REG(SPI1) #define SPI1_CI SPI_CI_REG(SPI1) #define SPI1_C3 SPI_C3_REG(SPI1) /*! * @} */ /* end of group SPI_Register_Accessor_Macros */ /*! * @} */ /* end of group SPI_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- TPM Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer * @{ */ /** TPM - Register Layout Typedef */ typedef struct { __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ __IO uint32_t CNT; /**< Counter, offset: 0x4 */ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ struct { /* offset: 0xC, array step: 0x8 */ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ } CONTROLS[6]; uint8_t RESERVED_0[20]; __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ uint8_t RESERVED_1[28]; __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ uint8_t RESERVED_2[16]; __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ } TPM_Type, *TPM_MemMapPtr; /* ---------------------------------------------------------------------------- -- TPM - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros * @{ */ /* TPM - Register accessors */ #define TPM_SC_REG(base) ((base)->SC) #define TPM_CNT_REG(base) ((base)->CNT) #define TPM_MOD_REG(base) ((base)->MOD) #define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) #define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) #define TPM_STATUS_REG(base) ((base)->STATUS) #define TPM_POL_REG(base) ((base)->POL) #define TPM_CONF_REG(base) ((base)->CONF) /*! * @} */ /* end of group TPM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- TPM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup TPM_Register_Masks TPM Register Masks * @{ */ /* SC Bit Fields */ #define TPM_SC_PS_MASK 0x7u #define TPM_SC_PS_SHIFT 0 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK) #define TPM_SC_CMOD_MASK 0x18u #define TPM_SC_CMOD_SHIFT 3 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK) #define TPM_SC_CPWMS_MASK 0x20u #define TPM_SC_CPWMS_SHIFT 5 #define TPM_SC_TOIE_MASK 0x40u #define TPM_SC_TOIE_SHIFT 6 #define TPM_SC_TOF_MASK 0x80u #define TPM_SC_TOF_SHIFT 7 #define TPM_SC_DMA_MASK 0x100u #define TPM_SC_DMA_SHIFT 8 /* CNT Bit Fields */ #define TPM_CNT_COUNT_MASK 0xFFFFu #define TPM_CNT_COUNT_SHIFT 0 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK) /* MOD Bit Fields */ #define TPM_MOD_MOD_MASK 0xFFFFu #define TPM_MOD_MOD_SHIFT 0 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK) /* CnSC Bit Fields */ #define TPM_CnSC_DMA_MASK 0x1u #define TPM_CnSC_DMA_SHIFT 0 #define TPM_CnSC_ELSA_MASK 0x4u #define TPM_CnSC_ELSA_SHIFT 2 #define TPM_CnSC_ELSB_MASK 0x8u #define TPM_CnSC_ELSB_SHIFT 3 #define TPM_CnSC_MSA_MASK 0x10u #define TPM_CnSC_MSA_SHIFT 4 #define TPM_CnSC_MSB_MASK 0x20u #define TPM_CnSC_MSB_SHIFT 5 #define TPM_CnSC_CHIE_MASK 0x40u #define TPM_CnSC_CHIE_SHIFT 6 #define TPM_CnSC_CHF_MASK 0x80u #define TPM_CnSC_CHF_SHIFT 7 /* CnV Bit Fields */ #define TPM_CnV_VAL_MASK 0xFFFFu #define TPM_CnV_VAL_SHIFT 0 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK) /* STATUS Bit Fields */ #define TPM_STATUS_CH0F_MASK 0x1u #define TPM_STATUS_CH0F_SHIFT 0 #define TPM_STATUS_CH1F_MASK 0x2u #define TPM_STATUS_CH1F_SHIFT 1 #define TPM_STATUS_CH2F_MASK 0x4u #define TPM_STATUS_CH2F_SHIFT 2 #define TPM_STATUS_CH3F_MASK 0x8u #define TPM_STATUS_CH3F_SHIFT 3 #define TPM_STATUS_CH4F_MASK 0x10u #define TPM_STATUS_CH4F_SHIFT 4 #define TPM_STATUS_CH5F_MASK 0x20u #define TPM_STATUS_CH5F_SHIFT 5 #define TPM_STATUS_TOF_MASK 0x100u #define TPM_STATUS_TOF_SHIFT 8 /* POL Bit Fields */ #define TPM_POL_POL0_MASK 0x1u #define TPM_POL_POL0_SHIFT 0 #define TPM_POL_POL1_MASK 0x2u #define TPM_POL_POL1_SHIFT 1 #define TPM_POL_POL2_MASK 0x4u #define TPM_POL_POL2_SHIFT 2 #define TPM_POL_POL3_MASK 0x8u #define TPM_POL_POL3_SHIFT 3 #define TPM_POL_POL4_MASK 0x10u #define TPM_POL_POL4_SHIFT 4 #define TPM_POL_POL5_MASK 0x20u #define TPM_POL_POL5_SHIFT 5 /* CONF Bit Fields */ #define TPM_CONF_DOZEEN_MASK 0x20u #define TPM_CONF_DOZEEN_SHIFT 5 #define TPM_CONF_DBGMODE_MASK 0xC0u #define TPM_CONF_DBGMODE_SHIFT 6 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK) #define TPM_CONF_GTBSYNC_MASK 0x100u #define TPM_CONF_GTBSYNC_SHIFT 8 #define TPM_CONF_GTBEEN_MASK 0x200u #define TPM_CONF_GTBEEN_SHIFT 9 #define TPM_CONF_CSOT_MASK 0x10000u #define TPM_CONF_CSOT_SHIFT 16 #define TPM_CONF_CSOO_MASK 0x20000u #define TPM_CONF_CSOO_SHIFT 17 #define TPM_CONF_CROT_MASK 0x40000u #define TPM_CONF_CROT_SHIFT 18 #define TPM_CONF_CPOT_MASK 0x80000u #define TPM_CONF_CPOT_SHIFT 19 #define TPM_CONF_TRGPOL_MASK 0x400000u #define TPM_CONF_TRGPOL_SHIFT 22 #define TPM_CONF_TRGSRC_MASK 0x800000u #define TPM_CONF_TRGSRC_SHIFT 23 #define TPM_CONF_TRGSEL_MASK 0xF000000u #define TPM_CONF_TRGSEL_SHIFT 24 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK) /*! * @} */ /* end of group TPM_Register_Masks */ /* TPM - Peripheral instance base addresses */ /** Peripheral TPM0 base address */ #define TPM0_BASE (0x40038000u) /** Peripheral TPM0 base pointer */ #define TPM0 ((TPM_Type *)TPM0_BASE) #define TPM0_BASE_PTR (TPM0) /** Peripheral TPM1 base address */ #define TPM1_BASE (0x40039000u) /** Peripheral TPM1 base pointer */ #define TPM1 ((TPM_Type *)TPM1_BASE) #define TPM1_BASE_PTR (TPM1) /** Peripheral TPM2 base address */ #define TPM2_BASE (0x4003A000u) /** Peripheral TPM2 base pointer */ #define TPM2 ((TPM_Type *)TPM2_BASE) #define TPM2_BASE_PTR (TPM2) /** Array initializer of TPM peripheral base addresses */ #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE } /** Array initializer of TPM peripheral base pointers */ #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 } /** Interrupt vectors for the TPM peripheral type */ #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn } /* ---------------------------------------------------------------------------- -- TPM - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros * @{ */ /* TPM - Register instance definitions */ /* TPM0 */ #define TPM0_SC TPM_SC_REG(TPM0) #define TPM0_CNT TPM_CNT_REG(TPM0) #define TPM0_MOD TPM_MOD_REG(TPM0) #define TPM0_C0SC TPM_CnSC_REG(TPM0,0) #define TPM0_C0V TPM_CnV_REG(TPM0,0) #define TPM0_C1SC TPM_CnSC_REG(TPM0,1) #define TPM0_C1V TPM_CnV_REG(TPM0,1) #define TPM0_C2SC TPM_CnSC_REG(TPM0,2) #define TPM0_C2V TPM_CnV_REG(TPM0,2) #define TPM0_C3SC TPM_CnSC_REG(TPM0,3) #define TPM0_C3V TPM_CnV_REG(TPM0,3) #define TPM0_C4SC TPM_CnSC_REG(TPM0,4) #define TPM0_C4V TPM_CnV_REG(TPM0,4) #define TPM0_C5SC TPM_CnSC_REG(TPM0,5) #define TPM0_C5V TPM_CnV_REG(TPM0,5) #define TPM0_STATUS TPM_STATUS_REG(TPM0) #define TPM0_POL TPM_POL_REG(TPM0) #define TPM0_CONF TPM_CONF_REG(TPM0) /* TPM1 */ #define TPM1_SC TPM_SC_REG(TPM1) #define TPM1_CNT TPM_CNT_REG(TPM1) #define TPM1_MOD TPM_MOD_REG(TPM1) #define TPM1_C0SC TPM_CnSC_REG(TPM1,0) #define TPM1_C0V TPM_CnV_REG(TPM1,0) #define TPM1_C1SC TPM_CnSC_REG(TPM1,1) #define TPM1_C1V TPM_CnV_REG(TPM1,1) #define TPM1_STATUS TPM_STATUS_REG(TPM1) #define TPM1_POL TPM_POL_REG(TPM1) #define TPM1_CONF TPM_CONF_REG(TPM1) /* TPM2 */ #define TPM2_SC TPM_SC_REG(TPM2) #define TPM2_CNT TPM_CNT_REG(TPM2) #define TPM2_MOD TPM_MOD_REG(TPM2) #define TPM2_C0SC TPM_CnSC_REG(TPM2,0) #define TPM2_C0V TPM_CnV_REG(TPM2,0) #define TPM2_C1SC TPM_CnSC_REG(TPM2,1) #define TPM2_C1V TPM_CnV_REG(TPM2,1) #define TPM2_STATUS TPM_STATUS_REG(TPM2) #define TPM2_POL TPM_POL_REG(TPM2) #define TPM2_CONF TPM_CONF_REG(TPM2) /* TPM - Register array accessors */ #define TPM0_CnSC(index) TPM_CnSC_REG(TPM0,index) #define TPM1_CnSC(index) TPM_CnSC_REG(TPM1,index) #define TPM2_CnSC(index) TPM_CnSC_REG(TPM2,index) #define TPM0_CnV(index) TPM_CnV_REG(TPM0,index) #define TPM1_CnV(index) TPM_CnV_REG(TPM1,index) #define TPM2_CnV(index) TPM_CnV_REG(TPM2,index) /*! * @} */ /* end of group TPM_Register_Accessor_Macros */ /*! * @} */ /* end of group TPM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- UART Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer * @{ */ /** UART - Register Layout Typedef */ typedef struct { __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ uint8_t RESERVED_0[12]; __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ uint8_t RESERVED_1[26]; __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */ __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */ union { /* offset: 0x3C */ struct { /* offset: 0x3C */ __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */ __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */ } TYPE0; struct { /* offset: 0x3C */ __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */ __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */ } TYPE1; }; __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */ __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */ } UART_Type, *UART_MemMapPtr; /* ---------------------------------------------------------------------------- -- UART - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros * @{ */ /* UART - Register accessors */ #define UART_BDH_REG(base) ((base)->BDH) #define UART_BDL_REG(base) ((base)->BDL) #define UART_C1_REG(base) ((base)->C1) #define UART_C2_REG(base) ((base)->C2) #define UART_S1_REG(base) ((base)->S1) #define UART_S2_REG(base) ((base)->S2) #define UART_C3_REG(base) ((base)->C3) #define UART_D_REG(base) ((base)->D) #define UART_MA1_REG(base) ((base)->MA1) #define UART_MA2_REG(base) ((base)->MA2) #define UART_C4_REG(base) ((base)->C4) #define UART_C5_REG(base) ((base)->C5) #define UART_C7816_REG(base) ((base)->C7816) #define UART_IE7816_REG(base) ((base)->IE7816) #define UART_IS7816_REG(base) ((base)->IS7816) #define UART_WP7816_REG(base) ((base)->WP7816) #define UART_WN7816_REG(base) ((base)->WN7816) #define UART_WF7816_REG(base) ((base)->WF7816) #define UART_ET7816_REG(base) ((base)->ET7816) #define UART_TL7816_REG(base) ((base)->TL7816) #define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0) #define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0) #define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0) #define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0) #define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1) #define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1) #define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1) #define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1) /*! * @} */ /* end of group UART_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- UART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Register_Masks UART Register Masks * @{ */ /* BDH Bit Fields */ #define UART_BDH_SBR_MASK 0x1Fu #define UART_BDH_SBR_SHIFT 0 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK) #define UART_BDH_RXEDGIE_MASK 0x40u #define UART_BDH_RXEDGIE_SHIFT 6 /* BDL Bit Fields */ #define UART_BDL_SBR_MASK 0xFFu #define UART_BDL_SBR_SHIFT 0 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK) /* C1 Bit Fields */ #define UART_C1_PT_MASK 0x1u #define UART_C1_PT_SHIFT 0 #define UART_C1_PE_MASK 0x2u #define UART_C1_PE_SHIFT 1 #define UART_C1_ILT_MASK 0x4u #define UART_C1_ILT_SHIFT 2 #define UART_C1_WAKE_MASK 0x8u #define UART_C1_WAKE_SHIFT 3 #define UART_C1_M_MASK 0x10u #define UART_C1_M_SHIFT 4 #define UART_C1_RSRC_MASK 0x20u #define UART_C1_RSRC_SHIFT 5 #define UART_C1_LOOPS_MASK 0x80u #define UART_C1_LOOPS_SHIFT 7 /* C2 Bit Fields */ #define UART_C2_SBK_MASK 0x1u #define UART_C2_SBK_SHIFT 0 #define UART_C2_RWU_MASK 0x2u #define UART_C2_RWU_SHIFT 1 #define UART_C2_RE_MASK 0x4u #define UART_C2_RE_SHIFT 2 #define UART_C2_TE_MASK 0x8u #define UART_C2_TE_SHIFT 3 #define UART_C2_ILIE_MASK 0x10u #define UART_C2_ILIE_SHIFT 4 #define UART_C2_RIE_MASK 0x20u #define UART_C2_RIE_SHIFT 5 #define UART_C2_TCIE_MASK 0x40u #define UART_C2_TCIE_SHIFT 6 #define UART_C2_TIE_MASK 0x80u #define UART_C2_TIE_SHIFT 7 /* S1 Bit Fields */ #define UART_S1_PF_MASK 0x1u #define UART_S1_PF_SHIFT 0 #define UART_S1_FE_MASK 0x2u #define UART_S1_FE_SHIFT 1 #define UART_S1_NF_MASK 0x4u #define UART_S1_NF_SHIFT 2 #define UART_S1_OR_MASK 0x8u #define UART_S1_OR_SHIFT 3 #define UART_S1_IDLE_MASK 0x10u #define UART_S1_IDLE_SHIFT 4 #define UART_S1_RDRF_MASK 0x20u #define UART_S1_RDRF_SHIFT 5 #define UART_S1_TC_MASK 0x40u #define UART_S1_TC_SHIFT 6 #define UART_S1_TDRE_MASK 0x80u #define UART_S1_TDRE_SHIFT 7 /* S2 Bit Fields */ #define UART_S2_RAF_MASK 0x1u #define UART_S2_RAF_SHIFT 0 #define UART_S2_BRK13_MASK 0x4u #define UART_S2_BRK13_SHIFT 2 #define UART_S2_RWUID_MASK 0x8u #define UART_S2_RWUID_SHIFT 3 #define UART_S2_RXINV_MASK 0x10u #define UART_S2_RXINV_SHIFT 4 #define UART_S2_MSBF_MASK 0x20u #define UART_S2_MSBF_SHIFT 5 #define UART_S2_RXEDGIF_MASK 0x40u #define UART_S2_RXEDGIF_SHIFT 6 /* C3 Bit Fields */ #define UART_C3_PEIE_MASK 0x1u #define UART_C3_PEIE_SHIFT 0 #define UART_C3_FEIE_MASK 0x2u #define UART_C3_FEIE_SHIFT 1 #define UART_C3_NEIE_MASK 0x4u #define UART_C3_NEIE_SHIFT 2 #define UART_C3_ORIE_MASK 0x8u #define UART_C3_ORIE_SHIFT 3 #define UART_C3_TXINV_MASK 0x10u #define UART_C3_TXINV_SHIFT 4 #define UART_C3_TXDIR_MASK 0x20u #define UART_C3_TXDIR_SHIFT 5 #define UART_C3_T8_MASK 0x40u #define UART_C3_T8_SHIFT 6 #define UART_C3_R8_MASK 0x80u #define UART_C3_R8_SHIFT 7 /* D Bit Fields */ #define UART_D_RT_MASK 0xFFu #define UART_D_RT_SHIFT 0 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK) /* MA1 Bit Fields */ #define UART_MA1_MA_MASK 0xFFu #define UART_MA1_MA_SHIFT 0 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK) /* MA2 Bit Fields */ #define UART_MA2_MA_MASK 0xFFu #define UART_MA2_MA_SHIFT 0 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK) /* C4 Bit Fields */ #define UART_C4_BRFA_MASK 0x1Fu #define UART_C4_BRFA_SHIFT 0 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK) #define UART_C4_M10_MASK 0x20u #define UART_C4_M10_SHIFT 5 #define UART_C4_MAEN2_MASK 0x40u #define UART_C4_MAEN2_SHIFT 6 #define UART_C4_MAEN1_MASK 0x80u #define UART_C4_MAEN1_SHIFT 7 /* C5 Bit Fields */ #define UART_C5_RDMAS_MASK 0x20u #define UART_C5_RDMAS_SHIFT 5 #define UART_C5_TDMAS_MASK 0x80u #define UART_C5_TDMAS_SHIFT 7 /* C7816 Bit Fields */ #define UART_C7816_ISO_7816E_MASK 0x1u #define UART_C7816_ISO_7816E_SHIFT 0 #define UART_C7816_TTYPE_MASK 0x2u #define UART_C7816_TTYPE_SHIFT 1 #define UART_C7816_INIT_MASK 0x4u #define UART_C7816_INIT_SHIFT 2 #define UART_C7816_ANACK_MASK 0x8u #define UART_C7816_ANACK_SHIFT 3 #define UART_C7816_ONACK_MASK 0x10u #define UART_C7816_ONACK_SHIFT 4 /* IE7816 Bit Fields */ #define UART_IE7816_RXTE_MASK 0x1u #define UART_IE7816_RXTE_SHIFT 0 #define UART_IE7816_TXTE_MASK 0x2u #define UART_IE7816_TXTE_SHIFT 1 #define UART_IE7816_GTVE_MASK 0x4u #define UART_IE7816_GTVE_SHIFT 2 #define UART_IE7816_ADTE_MASK 0x8u #define UART_IE7816_ADTE_SHIFT 3 #define UART_IE7816_INITDE_MASK 0x10u #define UART_IE7816_INITDE_SHIFT 4 #define UART_IE7816_BWTE_MASK 0x20u #define UART_IE7816_BWTE_SHIFT 5 #define UART_IE7816_CWTE_MASK 0x40u #define UART_IE7816_CWTE_SHIFT 6 #define UART_IE7816_WTE_MASK 0x80u #define UART_IE7816_WTE_SHIFT 7 /* IS7816 Bit Fields */ #define UART_IS7816_RXT_MASK 0x1u #define UART_IS7816_RXT_SHIFT 0 #define UART_IS7816_TXT_MASK 0x2u #define UART_IS7816_TXT_SHIFT 1 #define UART_IS7816_GTV_MASK 0x4u #define UART_IS7816_GTV_SHIFT 2 #define UART_IS7816_ADT_MASK 0x8u #define UART_IS7816_ADT_SHIFT 3 #define UART_IS7816_INITD_MASK 0x10u #define UART_IS7816_INITD_SHIFT 4 #define UART_IS7816_BWT_MASK 0x20u #define UART_IS7816_BWT_SHIFT 5 #define UART_IS7816_CWT_MASK 0x40u #define UART_IS7816_CWT_SHIFT 6 #define UART_IS7816_WT_MASK 0x80u #define UART_IS7816_WT_SHIFT 7 /* WP7816 Bit Fields */ #define UART_WP7816_WTX_MASK 0xFFu #define UART_WP7816_WTX_SHIFT 0 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK) /* WN7816 Bit Fields */ #define UART_WN7816_GTN_MASK 0xFFu #define UART_WN7816_GTN_SHIFT 0 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK) /* WF7816 Bit Fields */ #define UART_WF7816_GTFD_MASK 0xFFu #define UART_WF7816_GTFD_SHIFT 0 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK) /* ET7816 Bit Fields */ #define UART_ET7816_RXTHRESHOLD_MASK 0xFu #define UART_ET7816_RXTHRESHOLD_SHIFT 0 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK) #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u #define UART_ET7816_TXTHRESHOLD_SHIFT 4 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK) /* TL7816 Bit Fields */ #define UART_TL7816_TLEN_MASK 0xFFu #define UART_TL7816_TLEN_SHIFT 0 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK) /* AP7816A_T0 Bit Fields */ #define UART_AP7816A_T0_ADTI_H_MASK 0xFFu #define UART_AP7816A_T0_ADTI_H_SHIFT 0 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK) /* AP7816B_T0 Bit Fields */ #define UART_AP7816B_T0_ADTI_L_MASK 0xFFu #define UART_AP7816B_T0_ADTI_L_SHIFT 0 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK) /* WP7816A_T0 Bit Fields */ #define UART_WP7816A_T0_WI_H_MASK 0xFFu #define UART_WP7816A_T0_WI_H_SHIFT 0 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK) /* WP7816B_T0 Bit Fields */ #define UART_WP7816B_T0_WI_L_MASK 0xFFu #define UART_WP7816B_T0_WI_L_SHIFT 0 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK) /* WP7816A_T1 Bit Fields */ #define UART_WP7816A_T1_BWI_H_MASK 0xFFu #define UART_WP7816A_T1_BWI_H_SHIFT 0 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK) /* WP7816B_T1 Bit Fields */ #define UART_WP7816B_T1_BWI_L_MASK 0xFFu #define UART_WP7816B_T1_BWI_L_SHIFT 0 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK) /* WGP7816_T1 Bit Fields */ #define UART_WGP7816_T1_BGI_MASK 0xFu #define UART_WGP7816_T1_BGI_SHIFT 0 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK) #define UART_WGP7816_T1_CWI1_MASK 0xF0u #define UART_WGP7816_T1_CWI1_SHIFT 4 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK) /* WP7816C_T1 Bit Fields */ #define UART_WP7816C_T1_CWI2_MASK 0x1Fu #define UART_WP7816C_T1_CWI2_SHIFT 0 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK) /*! * @} */ /* end of group UART_Register_Masks */ /* UART - Peripheral instance base addresses */ /** Peripheral UART2 base address */ #define UART2_BASE (0x4006C000u) /** Peripheral UART2 base pointer */ #define UART2 ((UART_Type *)UART2_BASE) #define UART2_BASE_PTR (UART2) /** Array initializer of UART peripheral base addresses */ #define UART_BASE_ADDRS { UART2_BASE } /** Array initializer of UART peripheral base pointers */ #define UART_BASE_PTRS { UART2 } /** Interrupt vectors for the UART peripheral type */ #define UART_RX_TX_IRQS { UART2_FLEXIO_IRQn } #define UART_ERR_IRQS { UART2_FLEXIO_IRQn } /* ---------------------------------------------------------------------------- -- UART - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros * @{ */ /* UART - Register instance definitions */ /* UART2 */ #define UART2_BDH UART_BDH_REG(UART2) #define UART2_BDL UART_BDL_REG(UART2) #define UART2_C1 UART_C1_REG(UART2) #define UART2_C2 UART_C2_REG(UART2) #define UART2_S1 UART_S1_REG(UART2) #define UART2_S2 UART_S2_REG(UART2) #define UART2_C3 UART_C3_REG(UART2) #define UART2_D UART_D_REG(UART2) #define UART2_MA1 UART_MA1_REG(UART2) #define UART2_MA2 UART_MA2_REG(UART2) #define UART2_C4 UART_C4_REG(UART2) #define UART2_C5 UART_C5_REG(UART2) #define UART2_C7816 UART_C7816_REG(UART2) #define UART2_IE7816 UART_IE7816_REG(UART2) #define UART2_IS7816 UART_IS7816_REG(UART2) #define UART2_WP7816 UART_WP7816_REG(UART2) #define UART2_WN7816 UART_WN7816_REG(UART2) #define UART2_WF7816 UART_WF7816_REG(UART2) #define UART2_ET7816 UART_ET7816_REG(UART2) #define UART2_TL7816 UART_TL7816_REG(UART2) #define UART2_AP7816A_T0 UART_AP7816A_T0_REG(UART2) #define UART2_AP7816B_T0 UART_AP7816B_T0_REG(UART2) #define UART2_WP7816A_T0 UART_WP7816A_T0_REG(UART2) #define UART2_WP7816A_T1 UART_WP7816A_T1_REG(UART2) #define UART2_WP7816B_T0 UART_WP7816B_T0_REG(UART2) #define UART2_WP7816B_T1 UART_WP7816B_T1_REG(UART2) #define UART2_WGP7816_T1 UART_WGP7816_T1_REG(UART2) #define UART2_WP7816C_T1 UART_WP7816C_T1_REG(UART2) /*! * @} */ /* end of group UART_Register_Accessor_Macros */ /*! * @} */ /* end of group UART_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- USB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer * @{ */ /** USB - Register Layout Typedef */ typedef struct { __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ uint8_t RESERVED_0[3]; __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ uint8_t RESERVED_1[3]; __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ uint8_t RESERVED_2[3]; __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ uint8_t RESERVED_3[15]; __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ uint8_t RESERVED_4[99]; __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ uint8_t RESERVED_5[3]; __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ uint8_t RESERVED_6[3]; __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ uint8_t RESERVED_7[3]; __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ uint8_t RESERVED_8[3]; __I uint8_t STAT; /**< Status register, offset: 0x90 */ uint8_t RESERVED_9[3]; __IO uint8_t CTL; /**< Control register, offset: 0x94 */ uint8_t RESERVED_10[3]; __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ uint8_t RESERVED_11[3]; __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ uint8_t RESERVED_12[3]; __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ uint8_t RESERVED_13[3]; __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ uint8_t RESERVED_14[11]; __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ uint8_t RESERVED_15[3]; __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ uint8_t RESERVED_16[11]; struct { /* offset: 0xC0, array step: 0x4 */ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_0[3]; } ENDPOINT[16]; __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ uint8_t RESERVED_17[3]; __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ uint8_t RESERVED_18[3]; __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ uint8_t RESERVED_19[3]; __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ uint8_t RESERVED_20[7]; __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ uint8_t RESERVED_21[43]; __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ uint8_t RESERVED_22[3]; __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ uint8_t RESERVED_23[15]; __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */ uint8_t RESERVED_24[7]; __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ } USB_Type, *USB_MemMapPtr; /* ---------------------------------------------------------------------------- -- USB - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros * @{ */ /* USB - Register accessors */ #define USB_PERID_REG(base) ((base)->PERID) #define USB_IDCOMP_REG(base) ((base)->IDCOMP) #define USB_REV_REG(base) ((base)->REV) #define USB_ADDINFO_REG(base) ((base)->ADDINFO) #define USB_OTGCTL_REG(base) ((base)->OTGCTL) #define USB_ISTAT_REG(base) ((base)->ISTAT) #define USB_INTEN_REG(base) ((base)->INTEN) #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) #define USB_ERREN_REG(base) ((base)->ERREN) #define USB_STAT_REG(base) ((base)->STAT) #define USB_CTL_REG(base) ((base)->CTL) #define USB_ADDR_REG(base) ((base)->ADDR) #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) #define USB_FRMNUML_REG(base) ((base)->FRMNUML) #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) #define USB_USBCTRL_REG(base) ((base)->USBCTRL) #define USB_OBSERVE_REG(base) ((base)->OBSERVE) #define USB_CONTROL_REG(base) ((base)->CONTROL) #define USB_USBTRC0_REG(base) ((base)->USBTRC0) #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) #define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN) #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) /*! * @} */ /* end of group USB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Masks USB Register Masks * @{ */ /* PERID Bit Fields */ #define USB_PERID_ID_MASK 0x3Fu #define USB_PERID_ID_SHIFT 0 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK) /* IDCOMP Bit Fields */ #define USB_IDCOMP_NID_MASK 0x3Fu #define USB_IDCOMP_NID_SHIFT 0 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK) /* REV Bit Fields */ #define USB_REV_REV_MASK 0xFFu #define USB_REV_REV_SHIFT 0 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK) /* ADDINFO Bit Fields */ #define USB_ADDINFO_IEHOST_MASK 0x1u #define USB_ADDINFO_IEHOST_SHIFT 0 /* OTGCTL Bit Fields */ #define USB_OTGCTL_DPHIGH_MASK 0x80u #define USB_OTGCTL_DPHIGH_SHIFT 7 /* ISTAT Bit Fields */ #define USB_ISTAT_USBRST_MASK 0x1u #define USB_ISTAT_USBRST_SHIFT 0 #define USB_ISTAT_ERROR_MASK 0x2u #define USB_ISTAT_ERROR_SHIFT 1 #define USB_ISTAT_SOFTOK_MASK 0x4u #define USB_ISTAT_SOFTOK_SHIFT 2 #define USB_ISTAT_TOKDNE_MASK 0x8u #define USB_ISTAT_TOKDNE_SHIFT 3 #define USB_ISTAT_SLEEP_MASK 0x10u #define USB_ISTAT_SLEEP_SHIFT 4 #define USB_ISTAT_RESUME_MASK 0x20u #define USB_ISTAT_RESUME_SHIFT 5 #define USB_ISTAT_STALL_MASK 0x80u #define USB_ISTAT_STALL_SHIFT 7 /* INTEN Bit Fields */ #define USB_INTEN_USBRSTEN_MASK 0x1u #define USB_INTEN_USBRSTEN_SHIFT 0 #define USB_INTEN_ERROREN_MASK 0x2u #define USB_INTEN_ERROREN_SHIFT 1 #define USB_INTEN_SOFTOKEN_MASK 0x4u #define USB_INTEN_SOFTOKEN_SHIFT 2 #define USB_INTEN_TOKDNEEN_MASK 0x8u #define USB_INTEN_TOKDNEEN_SHIFT 3 #define USB_INTEN_SLEEPEN_MASK 0x10u #define USB_INTEN_SLEEPEN_SHIFT 4 #define USB_INTEN_RESUMEEN_MASK 0x20u #define USB_INTEN_RESUMEEN_SHIFT 5 #define USB_INTEN_STALLEN_MASK 0x80u #define USB_INTEN_STALLEN_SHIFT 7 /* ERRSTAT Bit Fields */ #define USB_ERRSTAT_PIDERR_MASK 0x1u #define USB_ERRSTAT_PIDERR_SHIFT 0 #define USB_ERRSTAT_CRC5_MASK 0x2u #define USB_ERRSTAT_CRC5_SHIFT 1 #define USB_ERRSTAT_CRC16_MASK 0x4u #define USB_ERRSTAT_CRC16_SHIFT 2 #define USB_ERRSTAT_DFN8_MASK 0x8u #define USB_ERRSTAT_DFN8_SHIFT 3 #define USB_ERRSTAT_BTOERR_MASK 0x10u #define USB_ERRSTAT_BTOERR_SHIFT 4 #define USB_ERRSTAT_DMAERR_MASK 0x20u #define USB_ERRSTAT_DMAERR_SHIFT 5 #define USB_ERRSTAT_BTSERR_MASK 0x80u #define USB_ERRSTAT_BTSERR_SHIFT 7 /* ERREN Bit Fields */ #define USB_ERREN_PIDERREN_MASK 0x1u #define USB_ERREN_PIDERREN_SHIFT 0 #define USB_ERREN_CRC5EOFEN_MASK 0x2u #define USB_ERREN_CRC5EOFEN_SHIFT 1 #define USB_ERREN_CRC16EN_MASK 0x4u #define USB_ERREN_CRC16EN_SHIFT 2 #define USB_ERREN_DFN8EN_MASK 0x8u #define USB_ERREN_DFN8EN_SHIFT 3 #define USB_ERREN_BTOERREN_MASK 0x10u #define USB_ERREN_BTOERREN_SHIFT 4 #define USB_ERREN_DMAERREN_MASK 0x20u #define USB_ERREN_DMAERREN_SHIFT 5 #define USB_ERREN_BTSERREN_MASK 0x80u #define USB_ERREN_BTSERREN_SHIFT 7 /* STAT Bit Fields */ #define USB_STAT_ODD_MASK 0x4u #define USB_STAT_ODD_SHIFT 2 #define USB_STAT_TX_MASK 0x8u #define USB_STAT_TX_SHIFT 3 #define USB_STAT_ENDP_MASK 0xF0u #define USB_STAT_ENDP_SHIFT 4 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK) /* CTL Bit Fields */ #define USB_CTL_USBENSOFEN_MASK 0x1u #define USB_CTL_USBENSOFEN_SHIFT 0 #define USB_CTL_ODDRST_MASK 0x2u #define USB_CTL_ODDRST_SHIFT 1 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5 #define USB_CTL_SE0_MASK 0x40u #define USB_CTL_SE0_SHIFT 6 #define USB_CTL_JSTATE_MASK 0x80u #define USB_CTL_JSTATE_SHIFT 7 /* ADDR Bit Fields */ #define USB_ADDR_ADDR_MASK 0x7Fu #define USB_ADDR_ADDR_SHIFT 0 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK) /* BDTPAGE1 Bit Fields */ #define USB_BDTPAGE1_BDTBA_MASK 0xFEu #define USB_BDTPAGE1_BDTBA_SHIFT 1 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK) /* FRMNUML Bit Fields */ #define USB_FRMNUML_FRM_MASK 0xFFu #define USB_FRMNUML_FRM_SHIFT 0 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK) /* FRMNUMH Bit Fields */ #define USB_FRMNUMH_FRM_MASK 0x7u #define USB_FRMNUMH_FRM_SHIFT 0 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK) /* BDTPAGE2 Bit Fields */ #define USB_BDTPAGE2_BDTBA_MASK 0xFFu #define USB_BDTPAGE2_BDTBA_SHIFT 0 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK) /* BDTPAGE3 Bit Fields */ #define USB_BDTPAGE3_BDTBA_MASK 0xFFu #define USB_BDTPAGE3_BDTBA_SHIFT 0 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK) /* ENDPT Bit Fields */ #define USB_ENDPT_EPHSHK_MASK 0x1u #define USB_ENDPT_EPHSHK_SHIFT 0 #define USB_ENDPT_EPSTALL_MASK 0x2u #define USB_ENDPT_EPSTALL_SHIFT 1 #define USB_ENDPT_EPTXEN_MASK 0x4u #define USB_ENDPT_EPTXEN_SHIFT 2 #define USB_ENDPT_EPRXEN_MASK 0x8u #define USB_ENDPT_EPRXEN_SHIFT 3 #define USB_ENDPT_EPCTLDIS_MASK 0x10u #define USB_ENDPT_EPCTLDIS_SHIFT 4 /* USBCTRL Bit Fields */ #define USB_USBCTRL_PDE_MASK 0x40u #define USB_USBCTRL_PDE_SHIFT 6 #define USB_USBCTRL_SUSP_MASK 0x80u #define USB_USBCTRL_SUSP_SHIFT 7 /* OBSERVE Bit Fields */ #define USB_OBSERVE_DMPD_MASK 0x10u #define USB_OBSERVE_DMPD_SHIFT 4 #define USB_OBSERVE_DPPD_MASK 0x40u #define USB_OBSERVE_DPPD_SHIFT 6 #define USB_OBSERVE_DPPU_MASK 0x80u #define USB_OBSERVE_DPPU_SHIFT 7 /* CONTROL Bit Fields */ #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4 /* USBTRC0 Bit Fields */ #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0 #define USB_USBTRC0_SYNC_DET_MASK 0x2u #define USB_USBTRC0_SYNC_DET_SHIFT 1 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2 #define USB_USBTRC0_USBRESMEN_MASK 0x20u #define USB_USBTRC0_USBRESMEN_SHIFT 5 #define USB_USBTRC0_USBRESET_MASK 0x80u #define USB_USBTRC0_USBRESET_SHIFT 7 /* USBFRMADJUST Bit Fields */ #define USB_USBFRMADJUST_ADJ_MASK 0xFFu #define USB_USBFRMADJUST_ADJ_SHIFT 0 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK) /* CLK_RECOVER_CTRL Bit Fields */ #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7 /* CLK_RECOVER_IRC_EN Bit Fields */ #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1 /* CLK_RECOVER_INT_EN Bit Fields */ #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4 /* CLK_RECOVER_INT_STATUS Bit Fields */ #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4 /*! * @} */ /* end of group USB_Register_Masks */ /* USB - Peripheral instance base addresses */ /** Peripheral USB0 base address */ #define USB0_BASE (0x40072000u) /** Peripheral USB0 base pointer */ #define USB0 ((USB_Type *)USB0_BASE) #define USB0_BASE_PTR (USB0) /** Array initializer of USB peripheral base addresses */ #define USB_BASE_ADDRS { USB0_BASE } /** Array initializer of USB peripheral base pointers */ #define USB_BASE_PTRS { USB0 } /** Interrupt vectors for the USB peripheral type */ #define USB_IRQS { USB0_IRQn } /* ---------------------------------------------------------------------------- -- USB - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros * @{ */ /* USB - Register instance definitions */ /* USB0 */ #define USB0_PERID USB_PERID_REG(USB0) #define USB0_IDCOMP USB_IDCOMP_REG(USB0) #define USB0_REV USB_REV_REG(USB0) #define USB0_ADDINFO USB_ADDINFO_REG(USB0) #define USB0_OTGCTL USB_OTGCTL_REG(USB0) #define USB0_ISTAT USB_ISTAT_REG(USB0) #define USB0_INTEN USB_INTEN_REG(USB0) #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0) #define USB0_ERREN USB_ERREN_REG(USB0) #define USB0_STAT USB_STAT_REG(USB0) #define USB0_CTL USB_CTL_REG(USB0) #define USB0_ADDR USB_ADDR_REG(USB0) #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0) #define USB0_FRMNUML USB_FRMNUML_REG(USB0) #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0) #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0) #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0) #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0) #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1) #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2) #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3) #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4) #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5) #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6) #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7) #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8) #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9) #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10) #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11) #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12) #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13) #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14) #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15) #define USB0_USBCTRL USB_USBCTRL_REG(USB0) #define USB0_OBSERVE USB_OBSERVE_REG(USB0) #define USB0_CONTROL USB_CONTROL_REG(USB0) #define USB0_USBTRC0 USB_USBTRC0_REG(USB0) #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0) #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0) #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0) #define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0) #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0) /* USB - Register array accessors */ #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index) /*! * @} */ /* end of group USB_Register_Accessor_Macros */ /*! * @} */ /* end of group USB_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- VREF Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer * @{ */ /** VREF - Register Layout Typedef */ typedef struct { __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ } VREF_Type, *VREF_MemMapPtr; /* ---------------------------------------------------------------------------- -- VREF - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros * @{ */ /* VREF - Register accessors */ #define VREF_TRM_REG(base) ((base)->TRM) #define VREF_SC_REG(base) ((base)->SC) /*! * @} */ /* end of group VREF_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- VREF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VREF_Register_Masks VREF Register Masks * @{ */ /* TRM Bit Fields */ #define VREF_TRM_TRIM_MASK 0x3Fu #define VREF_TRM_TRIM_SHIFT 0 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK) #define VREF_TRM_CHOPEN_MASK 0x40u #define VREF_TRM_CHOPEN_SHIFT 6 /* SC Bit Fields */ #define VREF_SC_MODE_LV_MASK 0x3u #define VREF_SC_MODE_LV_SHIFT 0 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK) #define VREF_SC_VREFST_MASK 0x4u #define VREF_SC_VREFST_SHIFT 2 #define VREF_SC_ICOMPEN_MASK 0x20u #define VREF_SC_ICOMPEN_SHIFT 5 #define VREF_SC_REGEN_MASK 0x40u #define VREF_SC_REGEN_SHIFT 6 #define VREF_SC_VREFEN_MASK 0x80u #define VREF_SC_VREFEN_SHIFT 7 /*! * @} */ /* end of group VREF_Register_Masks */ /* VREF - Peripheral instance base addresses */ /** Peripheral VREF base address */ #define VREF_BASE (0x40074000u) /** Peripheral VREF base pointer */ #define VREF ((VREF_Type *)VREF_BASE) #define VREF_BASE_PTR (VREF) /** Array initializer of VREF peripheral base addresses */ #define VREF_BASE_ADDRS { VREF_BASE } /** Array initializer of VREF peripheral base pointers */ #define VREF_BASE_PTRS { VREF } /* ---------------------------------------------------------------------------- -- VREF - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros * @{ */ /* VREF - Register instance definitions */ /* VREF */ #define VREF_TRM VREF_TRM_REG(VREF) #define VREF_SC VREF_SC_REG(VREF) /*! * @} */ /* end of group VREF_Register_Accessor_Macros */ /*! * @} */ /* end of group VREF_Peripheral_Access_Layer */ /* ** End of section using anonymous unions */ #if defined(__ARMCC_VERSION) #pragma pop #elif defined(__CWCC__) #pragma pop #elif defined(__GNUC__) /* leave anonymous unions enabled */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=default #else #error Not supported compiler type #endif /*! * @} */ /* end of group Peripheral_access_layer */ /* ---------------------------------------------------------------------------- -- Backward Compatibility ---------------------------------------------------------------------------- */ /*! * @addtogroup Backward_Compatibility_Symbols Backward Compatibility * @{ */ #define I2C_S1_RXAK_MASK I2C_S_RXAK_MASK #define I2C_S1_RXAK_SHIFT I2C_S_RXAK_SHIFT #define I2C_S1_IICIF_MASK I2C_S_IICIF_MASK #define I2C_S1_IICIF_SHIFT I2C_S_IICIF_SHIFTFT #define I2C_S1_SRW_MASK I2C_S_SRW_MASK #define I2C_S1_SRW_SHIFT I2C_S_SRW_SHIFT #define I2C_S1_RAM_MASK I2C_S_RAM_MASK #define I2C_S1_RAM_SHIFT I2C_S_RAM_SHIFT #define I2C_S1_ARBL_MASK I2C_S_ARBL_MASK #define I2C_S1_ARBL_SHIFT I2C_S_ARBL_SHIFT #define I2C_S1_BUSY_MASK I2C_S_BUSY_MASK #define I2C_S1_BUSY_SHIFT I2C_S_BUSY_SHIFT #define I2C_S1_IAAS_MASK I2C_S_IAAS_MASK #define I2C_S1_IAAS_SHIFT I2C_S_IAAS_SHIFT #define I2C_S1_TCF_MASK I2C_S_TCF_MASK #define I2C_S1_TCF_SHIFT I2C_S_TCF_SHIFT #define I2C_S1_REG(base) I2C_S_REG(base) #define I2C0_S1 I2C0_S #define I2C1_S1 I2C1_S #define ADC_BASES ADC_BASE_PTRS #define CMP_BASES CMP_BASE_PTRS #define DAC_BASES DAC_BASE_PTRS #define DMA_BASES DMA_BASE_PTRS #define DMAMUX_BASES DMAMUX_BASE_PTRS #define FLEXIO_BASES FLEXIO_BASE_PTRS #define FTFA_BASES FTFA_BASE_PTRS #define GPIO_BASES GPIO_BASE_PTRS #define I2C_BASES I2C_BASE_PTRS #define I2S_BASES I2S_BASE_PTRS #define LCD_BASES LCD_BASE_PTRS #define LLWU_BASES LLWU_BASE_PTRS #define LPTMR_BASES LPTMR_BASE_PTRS #define LPUART_BASES LPUART_BASE_PTRS #define MCG_BASES MCG_BASE_PTRS #define MCM_BASES MCM_BASE_PTRS #define MTB_BASES MTB_BASE_PTRS #define MTBDWT_BASES MTBDWT_BASE_PTRS #define NV_BASES NV_BASE_PTRS #define OSC_BASES OSC_BASE_PTRS #define PIT_BASES PIT_BASE_PTRS #define PMC_BASES PMC_BASE_PTRS #define PORT_BASES PORT_BASE_PTRS #define RCM_BASES RCM_BASE_PTRS #define ROM_BASES ROM_BASE_PTRS #define RTC_BASES RTC_BASE_PTRS #define SIM_BASES SIM_BASE_PTRS #define SMC_BASES SMC_BASE_PTRS #define SPI_BASES SPI_BASE_PTRS #define TPM_BASES TPM_BASE_PTRS #define UART_BASES UART_BASE_PTRS #define USB_BASES USB_BASE_PTRS #define VREF_BASES VREF_BASE_PTRS #define PTA_BASE_PTR GPIOA_BASE_PTR #define PTB_BASE_PTR GPIOB_BASE_PTR #define PTC_BASE_PTR GPIOC_BASE_PTR #define PTD_BASE_PTR GPIOD_BASE_PTR #define PTE_BASE_PTR GPIOE_BASE_PTR #define PTA_BASE GPIOA_BASE #define PTB_BASE GPIOB_BASE #define PTC_BASE GPIOC_BASE #define PTD_BASE GPIOD_BASE #define PTE_BASE GPIOE_BASE #define PTA GPIOA #define PTB GPIOB #define PTC GPIOC #define PTD GPIOD #define PTE GPIOE #define UART0_FLEXIO_IRQn UART2_FLEXIO_IRQn #define SIM_SOPT5_UART0ODE_MASK SIM_SOPT5_UART2ODE_MASK #define SIM_SOPT5_UART0ODE_SHIFT SIM_SOPT5_UART2ODE_SHIFT #define SIM_SCGC4_UART0_MASK SIM_SCGC4_UART2_MASK #define SIM_SCGC4_UART0_SHIFT SIM_SCGC4_UART2_SHIFT #define UART0_BASE UART2_BASE #define UART0 UART2 #define UART0_BASE_PTR UART2_BASE_PTR #define UART0_BDH UART2_BDH #define UART0_BDL UART2_BDL #define UART0_C1 UART2_C1 #define UART0_C2 UART2_C2 #define UART0_S1 UART2_S1 #define UART0_S2 UART2_S2 #define UART0_C3 UART2_C3 #define UART0_D UART2_D #define UART0_MA1 UART2_MA1 #define UART0_MA2 UART2_MA2 #define UART0_C4 UART2_C4 #define UART0_C5 UART2_C5 #define UART0_ED UART2_ED #define UART0_MODEM UART2_MODEM #define UART0_IR UART2_IR #define UART0_PFIFO UART2_PFIFO #define UART0_CFIFO UART2_CFIFO #define UART0_SFIFO UART2_SFIFO #define UART0_TWFIFO UART2_TWFIFO #define UART0_TCFIFO UART2_TCFIFO #define UART0_RWFIFO UART2_RWFIFO #define UART0_RCFIFO UART2_RCFIFO #define UART0_C7816 UART2_C7816 #define UART0_IE7816 UART2_IE7816 #define UART0_IS7816 UART2_IS7816 #define UART0_WP7816 UART2_WP7816 #define UART0_WN7816 UART2_WN7816 #define UART0_WF7816 UART2_WF7816 #define UART0_ET7816 UART2_ET7816 #define UART0_TL7816 UART2_TL7816 #define UART0_AP7816A_T0 UART2_AP7816A_T0 #define UART0_AP7816B_T0 UART2_AP7816B_T0 #define UART0_WP7816A_T0 UART2_WP7816A_T0 #define UART0_WP7816A_T1 UART2_WP7816A_T1 #define UART0_WP7816B_T0 UART2_WP7816B_T0 #define UART0_WP7816B_T1 UART2_WP7816B_T1 #define UART0_WGP7816_T1 UART2_WGP7816_T1 #define UART0_WP7816C_T1 UART2_WP7816C_T1 #define I2S0_MDR This_symb_has_been_deprecated #define I2S_MDR_DIVIDE_MASK This_symb_has_been_deprecated #define I2S_MDR_DIVIDE_SHIFT This_symb_has_been_deprecated #define I2S_MDR_DIVIDE(x) This_symb_has_been_deprecated #define I2S_MDR_FRACT_MASK This_symb_has_been_deprecated #define I2S_MDR_FRACT_SHIFT This_symb_has_been_deprecated #define I2S_MDR_FRACT(x) This_symb_has_been_deprecated #define I2S_MDR_REG(base) This_symb_has_been_deprecated #define CTL0 OTGCTL #define USB0_CTL0 USB0_OTGCTL #define USB_CTL0_REG(base) USB_OTGCTL_REG(base) #define USB_CTL0_DPHIGH_MASK USB_OTGCTL_DPHIGH_MASK #define USB_CTL0_DPHIGH_SHIFT USB_OTGCTL_DPHIGH_SHIFT #define CTL1 CTL #define USB0_CTL1 USB0_CTL #define USB_CTL1_REG(base) USB_CTL_REG(base) #define USB_CTL1_USBEN_MASK USB_CTL_USBEN_MASK #define USB_CTL1_USBEN_SHIFT USB_CTL_USBEN_SHIFT #define USB_CTL1_ODDRST_MASK USB_CTL_ODDRST_MASK #define USB_CTL1_ODDRST_SHIFT USB_CTL_ODDRST_SHIFT #define USB_CTL1_TXSUSPENDTOKENBUSY_MASK USB_CTL_TXSUSPENDTOKENBUSY_MASK #define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT USB_CTL_TXSUSPENDTOKENBUSY_SHIFT #define USB_CTL1_SE0_MASK USB_CTL_SE0_MASK #define USB_CTL1_SE0_SHIFT USB_CTL_SE0_SHIFT #define USB_CTL1_JSTATE_MASK USB_CTL_JSTATE_MASK #define USB_CTL1_JSTATE_SHIFT USB_CTL_JSTATE_SHIFT #define USB_CTL_USBEN_MASK USB_CTL_USBENSOFEN_MASK #define USB_CTL_USBEN_SHIFT USB_CTL_USBENSOFEN_SHIFT /*! * @} */ /* end of group Backward_Compatibility_Symbols */ #else /* #if !defined(MKL43Z4_H_) */ /* There is already included the same memory map. Check if it is compatible (has the same major version) */ #if (MCU_MEM_MAP_VERSION != 0x0100u) #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) #warning There are included two not compatible versions of memory maps. Please check possible differences. #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */ #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */ #endif /* #if !defined(MKL43Z4_H_) */ /* MKL43Z4.h, eof. */