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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
363:12a245e5c745 
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 363:12a245e5c745 1 /*
mbed_official 363:12a245e5c745 2 ** ###################################################################
mbed_official 363:12a245e5c745 3 ** Processors: MKL43Z256VLH4
mbed_official 363:12a245e5c745 4 ** MKL43Z128VLH4
mbed_official 363:12a245e5c745 5 ** MKL43Z64VLH4
mbed_official 363:12a245e5c745 6 ** MKL43Z256VMP4
mbed_official 363:12a245e5c745 7 ** MKL43Z128VMP4
mbed_official 363:12a245e5c745 8 ** MKL43Z64VMP4
mbed_official 363:12a245e5c745 9 **
mbed_official 363:12a245e5c745 10 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 363:12a245e5c745 11 ** Freescale C/C++ for Embedded ARM
mbed_official 363:12a245e5c745 12 ** GNU C Compiler
mbed_official 363:12a245e5c745 13 ** GNU C Compiler - CodeSourcery Sourcery G++
mbed_official 363:12a245e5c745 14 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 363:12a245e5c745 15 **
mbed_official 363:12a245e5c745 16 ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
mbed_official 363:12a245e5c745 17 ** Version: rev. 1.5, 2014-09-05
mbed_official 363:12a245e5c745 18 ** Build: b140905
mbed_official 363:12a245e5c745 19 **
mbed_official 363:12a245e5c745 20 ** Abstract:
mbed_official 363:12a245e5c745 21 ** CMSIS Peripheral Access Layer for MKL43Z4
mbed_official 363:12a245e5c745 22 **
mbed_official 363:12a245e5c745 23 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
mbed_official 363:12a245e5c745 24 ** All rights reserved.
mbed_official 363:12a245e5c745 25 **
mbed_official 363:12a245e5c745 26 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 363:12a245e5c745 27 ** are permitted provided that the following conditions are met:
mbed_official 363:12a245e5c745 28 **
mbed_official 363:12a245e5c745 29 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 363:12a245e5c745 30 ** of conditions and the following disclaimer.
mbed_official 363:12a245e5c745 31 **
mbed_official 363:12a245e5c745 32 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 363:12a245e5c745 33 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 363:12a245e5c745 34 ** other materials provided with the distribution.
mbed_official 363:12a245e5c745 35 **
mbed_official 363:12a245e5c745 36 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 363:12a245e5c745 37 ** contributors may be used to endorse or promote products derived from this
mbed_official 363:12a245e5c745 38 ** software without specific prior written permission.
mbed_official 363:12a245e5c745 39 **
mbed_official 363:12a245e5c745 40 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 363:12a245e5c745 41 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 363:12a245e5c745 42 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 363:12a245e5c745 43 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 363:12a245e5c745 44 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 363:12a245e5c745 45 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 363:12a245e5c745 46 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 363:12a245e5c745 47 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 363:12a245e5c745 48 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 363:12a245e5c745 49 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 363:12a245e5c745 50 **
mbed_official 363:12a245e5c745 51 ** http: www.freescale.com
mbed_official 363:12a245e5c745 52 ** mail: support@freescale.com
mbed_official 363:12a245e5c745 53 **
mbed_official 363:12a245e5c745 54 ** Revisions:
mbed_official 363:12a245e5c745 55 ** - rev. 1.0 (2014-03-27)
mbed_official 363:12a245e5c745 56 ** Initial version.
mbed_official 363:12a245e5c745 57 ** - rev. 1.1 (2014-05-26)
mbed_official 363:12a245e5c745 58 ** I2S registers TCR2/RCR2 and others were changed.
mbed_official 363:12a245e5c745 59 ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
mbed_official 363:12a245e5c745 60 ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
mbed_official 363:12a245e5c745 61 ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
mbed_official 363:12a245e5c745 62 ** Clock configuration for high range external oscillator has been added.
mbed_official 363:12a245e5c745 63 ** RFSYS module access has been added.
mbed_official 363:12a245e5c745 64 ** - rev. 1.2 (2014-07-10)
mbed_official 363:12a245e5c745 65 ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
mbed_official 363:12a245e5c745 66 ** UART0 - UART0 module renamed to UART2.
mbed_official 363:12a245e5c745 67 ** I2S - removed MDR register.
mbed_official 363:12a245e5c745 68 ** - rev. 1.3 (2014-08-21)
mbed_official 363:12a245e5c745 69 ** UART2 - Removed ED register.
mbed_official 363:12a245e5c745 70 ** UART2 - Removed MODEM register.
mbed_official 363:12a245e5c745 71 ** UART2 - Removed IR register.
mbed_official 363:12a245e5c745 72 ** UART2 - Removed PFIFO register.
mbed_official 363:12a245e5c745 73 ** UART2 - Removed CFIFO register.
mbed_official 363:12a245e5c745 74 ** UART2 - Removed SFIFO register.
mbed_official 363:12a245e5c745 75 ** UART2 - Removed TWFIFO register.
mbed_official 363:12a245e5c745 76 ** UART2 - Removed TCFIFO register.
mbed_official 363:12a245e5c745 77 ** UART2 - Removed RWFIFO register.
mbed_official 363:12a245e5c745 78 ** UART2 - Removed RCFIFO register.
mbed_official 363:12a245e5c745 79 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
mbed_official 363:12a245e5c745 80 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
mbed_official 363:12a245e5c745 81 ** SIM - Removed bitfield DIEID in SDID register.
mbed_official 363:12a245e5c745 82 ** - rev. 1.4 (2014-09-01)
mbed_official 363:12a245e5c745 83 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
mbed_official 363:12a245e5c745 84 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
mbed_official 363:12a245e5c745 85 ** - rev. 1.5 (2014-09-05)
mbed_official 363:12a245e5c745 86 ** USB - USBEN bitfield of the USB0_CTL renamed to USBENSOFEN.
mbed_official 363:12a245e5c745 87 **
mbed_official 363:12a245e5c745 88 ** ###################################################################
mbed_official 363:12a245e5c745 89 */
mbed_official 363:12a245e5c745 90
mbed_official 363:12a245e5c745 91 /*!
mbed_official 363:12a245e5c745 92 * @file MKL43Z4.h
mbed_official 363:12a245e5c745 93 * @version 1.5
mbed_official 363:12a245e5c745 94 * @date 2014-09-05
mbed_official 363:12a245e5c745 95 * @brief CMSIS Peripheral Access Layer for MKL43Z4
mbed_official 363:12a245e5c745 96 *
mbed_official 363:12a245e5c745 97 * CMSIS Peripheral Access Layer for MKL43Z4
mbed_official 363:12a245e5c745 98 */
mbed_official 363:12a245e5c745 99
mbed_official 363:12a245e5c745 100
mbed_official 363:12a245e5c745 101 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 102 -- MCU activation
mbed_official 363:12a245e5c745 103 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 104
mbed_official 363:12a245e5c745 105 /* Prevention from multiple including the same memory map */
mbed_official 363:12a245e5c745 106 #if !defined(MKL43Z4_H_) /* Check if memory map has not been already included */
mbed_official 363:12a245e5c745 107 #define MKL43Z4_H_
mbed_official 363:12a245e5c745 108 #define MCU_MKL43Z4
mbed_official 363:12a245e5c745 109
mbed_official 363:12a245e5c745 110 /* Check if another memory map has not been also included */
mbed_official 363:12a245e5c745 111 #if (defined(MCU_ACTIVE))
mbed_official 363:12a245e5c745 112 #error MKL43Z4 memory map: There is already included another memory map. Only one memory map can be included.
mbed_official 363:12a245e5c745 113 #endif /* (defined(MCU_ACTIVE)) */
mbed_official 363:12a245e5c745 114 #define MCU_ACTIVE
mbed_official 363:12a245e5c745 115
mbed_official 363:12a245e5c745 116 #include <stdint.h>
mbed_official 363:12a245e5c745 117
mbed_official 363:12a245e5c745 118 /** Memory map major version (memory maps with equal major version number are
mbed_official 363:12a245e5c745 119 * compatible) */
mbed_official 363:12a245e5c745 120 #define MCU_MEM_MAP_VERSION 0x0100u
mbed_official 363:12a245e5c745 121 /** Memory map minor version */
mbed_official 363:12a245e5c745 122 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
mbed_official 363:12a245e5c745 123
mbed_official 363:12a245e5c745 124
mbed_official 363:12a245e5c745 125 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 126 -- Interrupt vector numbers
mbed_official 363:12a245e5c745 127 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 128
mbed_official 363:12a245e5c745 129 /*!
mbed_official 363:12a245e5c745 130 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
mbed_official 363:12a245e5c745 131 * @{
mbed_official 363:12a245e5c745 132 */
mbed_official 363:12a245e5c745 133
mbed_official 363:12a245e5c745 134 /** Interrupt Number Definitions */
mbed_official 363:12a245e5c745 135 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
mbed_official 363:12a245e5c745 136
mbed_official 363:12a245e5c745 137 typedef enum IRQn {
mbed_official 363:12a245e5c745 138 /* Auxiliary constants */
mbed_official 363:12a245e5c745 139 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
mbed_official 363:12a245e5c745 140
mbed_official 363:12a245e5c745 141 /* Core interrupts */
mbed_official 363:12a245e5c745 142 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
mbed_official 363:12a245e5c745 143 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
mbed_official 363:12a245e5c745 144 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
mbed_official 363:12a245e5c745 145 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
mbed_official 363:12a245e5c745 146 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
mbed_official 363:12a245e5c745 147
mbed_official 363:12a245e5c745 148 /* Device specific interrupts */
mbed_official 363:12a245e5c745 149 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
mbed_official 363:12a245e5c745 150 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
mbed_official 363:12a245e5c745 151 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
mbed_official 363:12a245e5c745 152 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
mbed_official 363:12a245e5c745 153 Reserved20_IRQn = 4, /**< Reserved interrupt */
mbed_official 363:12a245e5c745 154 FTFA_IRQn = 5, /**< Command complete and read collision */
mbed_official 363:12a245e5c745 155 PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
mbed_official 363:12a245e5c745 156 LLWU_IRQn = 7, /**< Low leakage wakeup */
mbed_official 363:12a245e5c745 157 I2C0_IRQn = 8, /**< I2C0 interrupt */
mbed_official 363:12a245e5c745 158 I2C1_IRQn = 9, /**< I2C1 interrupt */
mbed_official 363:12a245e5c745 159 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
mbed_official 363:12a245e5c745 160 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
mbed_official 363:12a245e5c745 161 LPUART0_IRQn = 12, /**< LPUART0 status and error */
mbed_official 363:12a245e5c745 162 LPUART1_IRQn = 13, /**< LPUART1 status and error */
mbed_official 363:12a245e5c745 163 UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */
mbed_official 363:12a245e5c745 164 ADC0_IRQn = 15, /**< ADC0 interrupt */
mbed_official 363:12a245e5c745 165 CMP0_IRQn = 16, /**< CMP0 interrupt */
mbed_official 363:12a245e5c745 166 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
mbed_official 363:12a245e5c745 167 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
mbed_official 363:12a245e5c745 168 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
mbed_official 363:12a245e5c745 169 RTC_IRQn = 20, /**< RTC alarm */
mbed_official 363:12a245e5c745 170 RTC_Seconds_IRQn = 21, /**< RTC seconds */
mbed_official 363:12a245e5c745 171 PIT_IRQn = 22, /**< PIT interrupt */
mbed_official 363:12a245e5c745 172 I2S0_IRQn = 23, /**< I2S0 interrupt */
mbed_official 363:12a245e5c745 173 USB0_IRQn = 24, /**< USB0 interrupt */
mbed_official 363:12a245e5c745 174 DAC0_IRQn = 25, /**< DAC0 interrupt */
mbed_official 363:12a245e5c745 175 Reserved42_IRQn = 26, /**< Reserved interrupt */
mbed_official 363:12a245e5c745 176 Reserved43_IRQn = 27, /**< Reserved interrupt */
mbed_official 363:12a245e5c745 177 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
mbed_official 363:12a245e5c745 178 LCD_IRQn = 29, /**< LCD interrupt */
mbed_official 363:12a245e5c745 179 PORTA_IRQn = 30, /**< PORTA Pin detect */
mbed_official 363:12a245e5c745 180 PORTCD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */
mbed_official 363:12a245e5c745 181 } IRQn_Type;
mbed_official 363:12a245e5c745 182
mbed_official 363:12a245e5c745 183 /*!
mbed_official 363:12a245e5c745 184 * @}
mbed_official 363:12a245e5c745 185 */ /* end of group Interrupt_vector_numbers */
mbed_official 363:12a245e5c745 186
mbed_official 363:12a245e5c745 187
mbed_official 363:12a245e5c745 188 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 189 -- Cortex M0 Core Configuration
mbed_official 363:12a245e5c745 190 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 191
mbed_official 363:12a245e5c745 192 /*!
mbed_official 363:12a245e5c745 193 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
mbed_official 363:12a245e5c745 194 * @{
mbed_official 363:12a245e5c745 195 */
mbed_official 363:12a245e5c745 196
mbed_official 363:12a245e5c745 197 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
mbed_official 363:12a245e5c745 198 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
mbed_official 363:12a245e5c745 199 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
mbed_official 363:12a245e5c745 200 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
mbed_official 363:12a245e5c745 201 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
mbed_official 363:12a245e5c745 202
mbed_official 363:12a245e5c745 203 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
mbed_official 363:12a245e5c745 204 #include "system_MKL43Z4.h" /* Device specific configuration file */
mbed_official 363:12a245e5c745 205
mbed_official 363:12a245e5c745 206 /*!
mbed_official 363:12a245e5c745 207 * @}
mbed_official 363:12a245e5c745 208 */ /* end of group Cortex_Core_Configuration */
mbed_official 363:12a245e5c745 209
mbed_official 363:12a245e5c745 210
mbed_official 363:12a245e5c745 211 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 212 -- Device Peripheral Access Layer
mbed_official 363:12a245e5c745 213 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 214
mbed_official 363:12a245e5c745 215 /*!
mbed_official 363:12a245e5c745 216 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
mbed_official 363:12a245e5c745 217 * @{
mbed_official 363:12a245e5c745 218 */
mbed_official 363:12a245e5c745 219
mbed_official 363:12a245e5c745 220
mbed_official 363:12a245e5c745 221 /*
mbed_official 363:12a245e5c745 222 ** Start of section using anonymous unions
mbed_official 363:12a245e5c745 223 */
mbed_official 363:12a245e5c745 224
mbed_official 363:12a245e5c745 225 #if defined(__ARMCC_VERSION)
mbed_official 363:12a245e5c745 226 #pragma push
mbed_official 363:12a245e5c745 227 #pragma anon_unions
mbed_official 363:12a245e5c745 228 #elif defined(__CWCC__)
mbed_official 363:12a245e5c745 229 #pragma push
mbed_official 363:12a245e5c745 230 #pragma cpp_extensions on
mbed_official 363:12a245e5c745 231 #elif defined(__GNUC__)
mbed_official 363:12a245e5c745 232 /* anonymous unions are enabled by default */
mbed_official 363:12a245e5c745 233 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 363:12a245e5c745 234 #pragma language=extended
mbed_official 363:12a245e5c745 235 #else
mbed_official 363:12a245e5c745 236 #error Not supported compiler type
mbed_official 363:12a245e5c745 237 #endif
mbed_official 363:12a245e5c745 238
mbed_official 363:12a245e5c745 239 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 240 -- ADC Peripheral Access Layer
mbed_official 363:12a245e5c745 241 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 242
mbed_official 363:12a245e5c745 243 /*!
mbed_official 363:12a245e5c745 244 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
mbed_official 363:12a245e5c745 245 * @{
mbed_official 363:12a245e5c745 246 */
mbed_official 363:12a245e5c745 247
mbed_official 363:12a245e5c745 248 /** ADC - Register Layout Typedef */
mbed_official 363:12a245e5c745 249 typedef struct {
mbed_official 363:12a245e5c745 250 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
mbed_official 363:12a245e5c745 251 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
mbed_official 363:12a245e5c745 252 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
mbed_official 363:12a245e5c745 253 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
mbed_official 363:12a245e5c745 254 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
mbed_official 363:12a245e5c745 255 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
mbed_official 363:12a245e5c745 256 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
mbed_official 363:12a245e5c745 257 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
mbed_official 363:12a245e5c745 258 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
mbed_official 363:12a245e5c745 259 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
mbed_official 363:12a245e5c745 260 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
mbed_official 363:12a245e5c745 261 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
mbed_official 363:12a245e5c745 262 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
mbed_official 363:12a245e5c745 263 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
mbed_official 363:12a245e5c745 264 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
mbed_official 363:12a245e5c745 265 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
mbed_official 363:12a245e5c745 266 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
mbed_official 363:12a245e5c745 267 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
mbed_official 363:12a245e5c745 268 uint8_t RESERVED_0[4];
mbed_official 363:12a245e5c745 269 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
mbed_official 363:12a245e5c745 270 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
mbed_official 363:12a245e5c745 271 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
mbed_official 363:12a245e5c745 272 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
mbed_official 363:12a245e5c745 273 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
mbed_official 363:12a245e5c745 274 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
mbed_official 363:12a245e5c745 275 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
mbed_official 363:12a245e5c745 276 } ADC_Type, *ADC_MemMapPtr;
mbed_official 363:12a245e5c745 277
mbed_official 363:12a245e5c745 278 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 279 -- ADC - Register accessor macros
mbed_official 363:12a245e5c745 280 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 281
mbed_official 363:12a245e5c745 282 /*!
mbed_official 363:12a245e5c745 283 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
mbed_official 363:12a245e5c745 284 * @{
mbed_official 363:12a245e5c745 285 */
mbed_official 363:12a245e5c745 286
mbed_official 363:12a245e5c745 287
mbed_official 363:12a245e5c745 288 /* ADC - Register accessors */
mbed_official 363:12a245e5c745 289 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
mbed_official 363:12a245e5c745 290 #define ADC_CFG1_REG(base) ((base)->CFG1)
mbed_official 363:12a245e5c745 291 #define ADC_CFG2_REG(base) ((base)->CFG2)
mbed_official 363:12a245e5c745 292 #define ADC_R_REG(base,index) ((base)->R[index])
mbed_official 363:12a245e5c745 293 #define ADC_CV1_REG(base) ((base)->CV1)
mbed_official 363:12a245e5c745 294 #define ADC_CV2_REG(base) ((base)->CV2)
mbed_official 363:12a245e5c745 295 #define ADC_SC2_REG(base) ((base)->SC2)
mbed_official 363:12a245e5c745 296 #define ADC_SC3_REG(base) ((base)->SC3)
mbed_official 363:12a245e5c745 297 #define ADC_OFS_REG(base) ((base)->OFS)
mbed_official 363:12a245e5c745 298 #define ADC_PG_REG(base) ((base)->PG)
mbed_official 363:12a245e5c745 299 #define ADC_MG_REG(base) ((base)->MG)
mbed_official 363:12a245e5c745 300 #define ADC_CLPD_REG(base) ((base)->CLPD)
mbed_official 363:12a245e5c745 301 #define ADC_CLPS_REG(base) ((base)->CLPS)
mbed_official 363:12a245e5c745 302 #define ADC_CLP4_REG(base) ((base)->CLP4)
mbed_official 363:12a245e5c745 303 #define ADC_CLP3_REG(base) ((base)->CLP3)
mbed_official 363:12a245e5c745 304 #define ADC_CLP2_REG(base) ((base)->CLP2)
mbed_official 363:12a245e5c745 305 #define ADC_CLP1_REG(base) ((base)->CLP1)
mbed_official 363:12a245e5c745 306 #define ADC_CLP0_REG(base) ((base)->CLP0)
mbed_official 363:12a245e5c745 307 #define ADC_CLMD_REG(base) ((base)->CLMD)
mbed_official 363:12a245e5c745 308 #define ADC_CLMS_REG(base) ((base)->CLMS)
mbed_official 363:12a245e5c745 309 #define ADC_CLM4_REG(base) ((base)->CLM4)
mbed_official 363:12a245e5c745 310 #define ADC_CLM3_REG(base) ((base)->CLM3)
mbed_official 363:12a245e5c745 311 #define ADC_CLM2_REG(base) ((base)->CLM2)
mbed_official 363:12a245e5c745 312 #define ADC_CLM1_REG(base) ((base)->CLM1)
mbed_official 363:12a245e5c745 313 #define ADC_CLM0_REG(base) ((base)->CLM0)
mbed_official 363:12a245e5c745 314
mbed_official 363:12a245e5c745 315 /*!
mbed_official 363:12a245e5c745 316 * @}
mbed_official 363:12a245e5c745 317 */ /* end of group ADC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 318
mbed_official 363:12a245e5c745 319
mbed_official 363:12a245e5c745 320 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 321 -- ADC Register Masks
mbed_official 363:12a245e5c745 322 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 323
mbed_official 363:12a245e5c745 324 /*!
mbed_official 363:12a245e5c745 325 * @addtogroup ADC_Register_Masks ADC Register Masks
mbed_official 363:12a245e5c745 326 * @{
mbed_official 363:12a245e5c745 327 */
mbed_official 363:12a245e5c745 328
mbed_official 363:12a245e5c745 329 /* SC1 Bit Fields */
mbed_official 363:12a245e5c745 330 #define ADC_SC1_ADCH_MASK 0x1Fu
mbed_official 363:12a245e5c745 331 #define ADC_SC1_ADCH_SHIFT 0
mbed_official 363:12a245e5c745 332 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
mbed_official 363:12a245e5c745 333 #define ADC_SC1_DIFF_MASK 0x20u
mbed_official 363:12a245e5c745 334 #define ADC_SC1_DIFF_SHIFT 5
mbed_official 363:12a245e5c745 335 #define ADC_SC1_AIEN_MASK 0x40u
mbed_official 363:12a245e5c745 336 #define ADC_SC1_AIEN_SHIFT 6
mbed_official 363:12a245e5c745 337 #define ADC_SC1_COCO_MASK 0x80u
mbed_official 363:12a245e5c745 338 #define ADC_SC1_COCO_SHIFT 7
mbed_official 363:12a245e5c745 339 /* CFG1 Bit Fields */
mbed_official 363:12a245e5c745 340 #define ADC_CFG1_ADICLK_MASK 0x3u
mbed_official 363:12a245e5c745 341 #define ADC_CFG1_ADICLK_SHIFT 0
mbed_official 363:12a245e5c745 342 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
mbed_official 363:12a245e5c745 343 #define ADC_CFG1_MODE_MASK 0xCu
mbed_official 363:12a245e5c745 344 #define ADC_CFG1_MODE_SHIFT 2
mbed_official 363:12a245e5c745 345 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
mbed_official 363:12a245e5c745 346 #define ADC_CFG1_ADLSMP_MASK 0x10u
mbed_official 363:12a245e5c745 347 #define ADC_CFG1_ADLSMP_SHIFT 4
mbed_official 363:12a245e5c745 348 #define ADC_CFG1_ADIV_MASK 0x60u
mbed_official 363:12a245e5c745 349 #define ADC_CFG1_ADIV_SHIFT 5
mbed_official 363:12a245e5c745 350 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
mbed_official 363:12a245e5c745 351 #define ADC_CFG1_ADLPC_MASK 0x80u
mbed_official 363:12a245e5c745 352 #define ADC_CFG1_ADLPC_SHIFT 7
mbed_official 363:12a245e5c745 353 /* CFG2 Bit Fields */
mbed_official 363:12a245e5c745 354 #define ADC_CFG2_ADLSTS_MASK 0x3u
mbed_official 363:12a245e5c745 355 #define ADC_CFG2_ADLSTS_SHIFT 0
mbed_official 363:12a245e5c745 356 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
mbed_official 363:12a245e5c745 357 #define ADC_CFG2_ADHSC_MASK 0x4u
mbed_official 363:12a245e5c745 358 #define ADC_CFG2_ADHSC_SHIFT 2
mbed_official 363:12a245e5c745 359 #define ADC_CFG2_ADACKEN_MASK 0x8u
mbed_official 363:12a245e5c745 360 #define ADC_CFG2_ADACKEN_SHIFT 3
mbed_official 363:12a245e5c745 361 #define ADC_CFG2_MUXSEL_MASK 0x10u
mbed_official 363:12a245e5c745 362 #define ADC_CFG2_MUXSEL_SHIFT 4
mbed_official 363:12a245e5c745 363 /* R Bit Fields */
mbed_official 363:12a245e5c745 364 #define ADC_R_D_MASK 0xFFFFu
mbed_official 363:12a245e5c745 365 #define ADC_R_D_SHIFT 0
mbed_official 363:12a245e5c745 366 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
mbed_official 363:12a245e5c745 367 /* CV1 Bit Fields */
mbed_official 363:12a245e5c745 368 #define ADC_CV1_CV_MASK 0xFFFFu
mbed_official 363:12a245e5c745 369 #define ADC_CV1_CV_SHIFT 0
mbed_official 363:12a245e5c745 370 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
mbed_official 363:12a245e5c745 371 /* CV2 Bit Fields */
mbed_official 363:12a245e5c745 372 #define ADC_CV2_CV_MASK 0xFFFFu
mbed_official 363:12a245e5c745 373 #define ADC_CV2_CV_SHIFT 0
mbed_official 363:12a245e5c745 374 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
mbed_official 363:12a245e5c745 375 /* SC2 Bit Fields */
mbed_official 363:12a245e5c745 376 #define ADC_SC2_REFSEL_MASK 0x3u
mbed_official 363:12a245e5c745 377 #define ADC_SC2_REFSEL_SHIFT 0
mbed_official 363:12a245e5c745 378 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
mbed_official 363:12a245e5c745 379 #define ADC_SC2_DMAEN_MASK 0x4u
mbed_official 363:12a245e5c745 380 #define ADC_SC2_DMAEN_SHIFT 2
mbed_official 363:12a245e5c745 381 #define ADC_SC2_ACREN_MASK 0x8u
mbed_official 363:12a245e5c745 382 #define ADC_SC2_ACREN_SHIFT 3
mbed_official 363:12a245e5c745 383 #define ADC_SC2_ACFGT_MASK 0x10u
mbed_official 363:12a245e5c745 384 #define ADC_SC2_ACFGT_SHIFT 4
mbed_official 363:12a245e5c745 385 #define ADC_SC2_ACFE_MASK 0x20u
mbed_official 363:12a245e5c745 386 #define ADC_SC2_ACFE_SHIFT 5
mbed_official 363:12a245e5c745 387 #define ADC_SC2_ADTRG_MASK 0x40u
mbed_official 363:12a245e5c745 388 #define ADC_SC2_ADTRG_SHIFT 6
mbed_official 363:12a245e5c745 389 #define ADC_SC2_ADACT_MASK 0x80u
mbed_official 363:12a245e5c745 390 #define ADC_SC2_ADACT_SHIFT 7
mbed_official 363:12a245e5c745 391 /* SC3 Bit Fields */
mbed_official 363:12a245e5c745 392 #define ADC_SC3_AVGS_MASK 0x3u
mbed_official 363:12a245e5c745 393 #define ADC_SC3_AVGS_SHIFT 0
mbed_official 363:12a245e5c745 394 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
mbed_official 363:12a245e5c745 395 #define ADC_SC3_AVGE_MASK 0x4u
mbed_official 363:12a245e5c745 396 #define ADC_SC3_AVGE_SHIFT 2
mbed_official 363:12a245e5c745 397 #define ADC_SC3_ADCO_MASK 0x8u
mbed_official 363:12a245e5c745 398 #define ADC_SC3_ADCO_SHIFT 3
mbed_official 363:12a245e5c745 399 #define ADC_SC3_CALF_MASK 0x40u
mbed_official 363:12a245e5c745 400 #define ADC_SC3_CALF_SHIFT 6
mbed_official 363:12a245e5c745 401 #define ADC_SC3_CAL_MASK 0x80u
mbed_official 363:12a245e5c745 402 #define ADC_SC3_CAL_SHIFT 7
mbed_official 363:12a245e5c745 403 /* OFS Bit Fields */
mbed_official 363:12a245e5c745 404 #define ADC_OFS_OFS_MASK 0xFFFFu
mbed_official 363:12a245e5c745 405 #define ADC_OFS_OFS_SHIFT 0
mbed_official 363:12a245e5c745 406 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
mbed_official 363:12a245e5c745 407 /* PG Bit Fields */
mbed_official 363:12a245e5c745 408 #define ADC_PG_PG_MASK 0xFFFFu
mbed_official 363:12a245e5c745 409 #define ADC_PG_PG_SHIFT 0
mbed_official 363:12a245e5c745 410 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
mbed_official 363:12a245e5c745 411 /* MG Bit Fields */
mbed_official 363:12a245e5c745 412 #define ADC_MG_MG_MASK 0xFFFFu
mbed_official 363:12a245e5c745 413 #define ADC_MG_MG_SHIFT 0
mbed_official 363:12a245e5c745 414 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
mbed_official 363:12a245e5c745 415 /* CLPD Bit Fields */
mbed_official 363:12a245e5c745 416 #define ADC_CLPD_CLPD_MASK 0x3Fu
mbed_official 363:12a245e5c745 417 #define ADC_CLPD_CLPD_SHIFT 0
mbed_official 363:12a245e5c745 418 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
mbed_official 363:12a245e5c745 419 /* CLPS Bit Fields */
mbed_official 363:12a245e5c745 420 #define ADC_CLPS_CLPS_MASK 0x3Fu
mbed_official 363:12a245e5c745 421 #define ADC_CLPS_CLPS_SHIFT 0
mbed_official 363:12a245e5c745 422 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
mbed_official 363:12a245e5c745 423 /* CLP4 Bit Fields */
mbed_official 363:12a245e5c745 424 #define ADC_CLP4_CLP4_MASK 0x3FFu
mbed_official 363:12a245e5c745 425 #define ADC_CLP4_CLP4_SHIFT 0
mbed_official 363:12a245e5c745 426 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
mbed_official 363:12a245e5c745 427 /* CLP3 Bit Fields */
mbed_official 363:12a245e5c745 428 #define ADC_CLP3_CLP3_MASK 0x1FFu
mbed_official 363:12a245e5c745 429 #define ADC_CLP3_CLP3_SHIFT 0
mbed_official 363:12a245e5c745 430 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
mbed_official 363:12a245e5c745 431 /* CLP2 Bit Fields */
mbed_official 363:12a245e5c745 432 #define ADC_CLP2_CLP2_MASK 0xFFu
mbed_official 363:12a245e5c745 433 #define ADC_CLP2_CLP2_SHIFT 0
mbed_official 363:12a245e5c745 434 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
mbed_official 363:12a245e5c745 435 /* CLP1 Bit Fields */
mbed_official 363:12a245e5c745 436 #define ADC_CLP1_CLP1_MASK 0x7Fu
mbed_official 363:12a245e5c745 437 #define ADC_CLP1_CLP1_SHIFT 0
mbed_official 363:12a245e5c745 438 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
mbed_official 363:12a245e5c745 439 /* CLP0 Bit Fields */
mbed_official 363:12a245e5c745 440 #define ADC_CLP0_CLP0_MASK 0x3Fu
mbed_official 363:12a245e5c745 441 #define ADC_CLP0_CLP0_SHIFT 0
mbed_official 363:12a245e5c745 442 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
mbed_official 363:12a245e5c745 443 /* CLMD Bit Fields */
mbed_official 363:12a245e5c745 444 #define ADC_CLMD_CLMD_MASK 0x3Fu
mbed_official 363:12a245e5c745 445 #define ADC_CLMD_CLMD_SHIFT 0
mbed_official 363:12a245e5c745 446 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
mbed_official 363:12a245e5c745 447 /* CLMS Bit Fields */
mbed_official 363:12a245e5c745 448 #define ADC_CLMS_CLMS_MASK 0x3Fu
mbed_official 363:12a245e5c745 449 #define ADC_CLMS_CLMS_SHIFT 0
mbed_official 363:12a245e5c745 450 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
mbed_official 363:12a245e5c745 451 /* CLM4 Bit Fields */
mbed_official 363:12a245e5c745 452 #define ADC_CLM4_CLM4_MASK 0x3FFu
mbed_official 363:12a245e5c745 453 #define ADC_CLM4_CLM4_SHIFT 0
mbed_official 363:12a245e5c745 454 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
mbed_official 363:12a245e5c745 455 /* CLM3 Bit Fields */
mbed_official 363:12a245e5c745 456 #define ADC_CLM3_CLM3_MASK 0x1FFu
mbed_official 363:12a245e5c745 457 #define ADC_CLM3_CLM3_SHIFT 0
mbed_official 363:12a245e5c745 458 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
mbed_official 363:12a245e5c745 459 /* CLM2 Bit Fields */
mbed_official 363:12a245e5c745 460 #define ADC_CLM2_CLM2_MASK 0xFFu
mbed_official 363:12a245e5c745 461 #define ADC_CLM2_CLM2_SHIFT 0
mbed_official 363:12a245e5c745 462 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
mbed_official 363:12a245e5c745 463 /* CLM1 Bit Fields */
mbed_official 363:12a245e5c745 464 #define ADC_CLM1_CLM1_MASK 0x7Fu
mbed_official 363:12a245e5c745 465 #define ADC_CLM1_CLM1_SHIFT 0
mbed_official 363:12a245e5c745 466 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
mbed_official 363:12a245e5c745 467 /* CLM0 Bit Fields */
mbed_official 363:12a245e5c745 468 #define ADC_CLM0_CLM0_MASK 0x3Fu
mbed_official 363:12a245e5c745 469 #define ADC_CLM0_CLM0_SHIFT 0
mbed_official 363:12a245e5c745 470 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
mbed_official 363:12a245e5c745 471
mbed_official 363:12a245e5c745 472 /*!
mbed_official 363:12a245e5c745 473 * @}
mbed_official 363:12a245e5c745 474 */ /* end of group ADC_Register_Masks */
mbed_official 363:12a245e5c745 475
mbed_official 363:12a245e5c745 476
mbed_official 363:12a245e5c745 477 /* ADC - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 478 /** Peripheral ADC0 base address */
mbed_official 363:12a245e5c745 479 #define ADC0_BASE (0x4003B000u)
mbed_official 363:12a245e5c745 480 /** Peripheral ADC0 base pointer */
mbed_official 363:12a245e5c745 481 #define ADC0 ((ADC_Type *)ADC0_BASE)
mbed_official 363:12a245e5c745 482 #define ADC0_BASE_PTR (ADC0)
mbed_official 363:12a245e5c745 483 /** Array initializer of ADC peripheral base addresses */
mbed_official 363:12a245e5c745 484 #define ADC_BASE_ADDRS { ADC0_BASE }
mbed_official 363:12a245e5c745 485 /** Array initializer of ADC peripheral base pointers */
mbed_official 363:12a245e5c745 486 #define ADC_BASE_PTRS { ADC0 }
mbed_official 363:12a245e5c745 487 /** Interrupt vectors for the ADC peripheral type */
mbed_official 363:12a245e5c745 488 #define ADC_IRQS { ADC0_IRQn }
mbed_official 363:12a245e5c745 489
mbed_official 363:12a245e5c745 490 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 491 -- ADC - Register accessor macros
mbed_official 363:12a245e5c745 492 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 493
mbed_official 363:12a245e5c745 494 /*!
mbed_official 363:12a245e5c745 495 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
mbed_official 363:12a245e5c745 496 * @{
mbed_official 363:12a245e5c745 497 */
mbed_official 363:12a245e5c745 498
mbed_official 363:12a245e5c745 499
mbed_official 363:12a245e5c745 500 /* ADC - Register instance definitions */
mbed_official 363:12a245e5c745 501 /* ADC0 */
mbed_official 363:12a245e5c745 502 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
mbed_official 363:12a245e5c745 503 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
mbed_official 363:12a245e5c745 504 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
mbed_official 363:12a245e5c745 505 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
mbed_official 363:12a245e5c745 506 #define ADC0_RA ADC_R_REG(ADC0,0)
mbed_official 363:12a245e5c745 507 #define ADC0_RB ADC_R_REG(ADC0,1)
mbed_official 363:12a245e5c745 508 #define ADC0_CV1 ADC_CV1_REG(ADC0)
mbed_official 363:12a245e5c745 509 #define ADC0_CV2 ADC_CV2_REG(ADC0)
mbed_official 363:12a245e5c745 510 #define ADC0_SC2 ADC_SC2_REG(ADC0)
mbed_official 363:12a245e5c745 511 #define ADC0_SC3 ADC_SC3_REG(ADC0)
mbed_official 363:12a245e5c745 512 #define ADC0_OFS ADC_OFS_REG(ADC0)
mbed_official 363:12a245e5c745 513 #define ADC0_PG ADC_PG_REG(ADC0)
mbed_official 363:12a245e5c745 514 #define ADC0_MG ADC_MG_REG(ADC0)
mbed_official 363:12a245e5c745 515 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
mbed_official 363:12a245e5c745 516 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
mbed_official 363:12a245e5c745 517 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
mbed_official 363:12a245e5c745 518 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
mbed_official 363:12a245e5c745 519 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
mbed_official 363:12a245e5c745 520 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
mbed_official 363:12a245e5c745 521 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
mbed_official 363:12a245e5c745 522 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
mbed_official 363:12a245e5c745 523 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
mbed_official 363:12a245e5c745 524 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
mbed_official 363:12a245e5c745 525 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
mbed_official 363:12a245e5c745 526 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
mbed_official 363:12a245e5c745 527 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
mbed_official 363:12a245e5c745 528 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
mbed_official 363:12a245e5c745 529
mbed_official 363:12a245e5c745 530 /* ADC - Register array accessors */
mbed_official 363:12a245e5c745 531 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
mbed_official 363:12a245e5c745 532 #define ADC0_R(index) ADC_R_REG(ADC0,index)
mbed_official 363:12a245e5c745 533
mbed_official 363:12a245e5c745 534 /*!
mbed_official 363:12a245e5c745 535 * @}
mbed_official 363:12a245e5c745 536 */ /* end of group ADC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 537
mbed_official 363:12a245e5c745 538
mbed_official 363:12a245e5c745 539 /*!
mbed_official 363:12a245e5c745 540 * @}
mbed_official 363:12a245e5c745 541 */ /* end of group ADC_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 542
mbed_official 363:12a245e5c745 543
mbed_official 363:12a245e5c745 544 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 545 -- CMP Peripheral Access Layer
mbed_official 363:12a245e5c745 546 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 547
mbed_official 363:12a245e5c745 548 /*!
mbed_official 363:12a245e5c745 549 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
mbed_official 363:12a245e5c745 550 * @{
mbed_official 363:12a245e5c745 551 */
mbed_official 363:12a245e5c745 552
mbed_official 363:12a245e5c745 553 /** CMP - Register Layout Typedef */
mbed_official 363:12a245e5c745 554 typedef struct {
mbed_official 363:12a245e5c745 555 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
mbed_official 363:12a245e5c745 556 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
mbed_official 363:12a245e5c745 557 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
mbed_official 363:12a245e5c745 558 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
mbed_official 363:12a245e5c745 559 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
mbed_official 363:12a245e5c745 560 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
mbed_official 363:12a245e5c745 561 } CMP_Type, *CMP_MemMapPtr;
mbed_official 363:12a245e5c745 562
mbed_official 363:12a245e5c745 563 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 564 -- CMP - Register accessor macros
mbed_official 363:12a245e5c745 565 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 566
mbed_official 363:12a245e5c745 567 /*!
mbed_official 363:12a245e5c745 568 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
mbed_official 363:12a245e5c745 569 * @{
mbed_official 363:12a245e5c745 570 */
mbed_official 363:12a245e5c745 571
mbed_official 363:12a245e5c745 572
mbed_official 363:12a245e5c745 573 /* CMP - Register accessors */
mbed_official 363:12a245e5c745 574 #define CMP_CR0_REG(base) ((base)->CR0)
mbed_official 363:12a245e5c745 575 #define CMP_CR1_REG(base) ((base)->CR1)
mbed_official 363:12a245e5c745 576 #define CMP_FPR_REG(base) ((base)->FPR)
mbed_official 363:12a245e5c745 577 #define CMP_SCR_REG(base) ((base)->SCR)
mbed_official 363:12a245e5c745 578 #define CMP_DACCR_REG(base) ((base)->DACCR)
mbed_official 363:12a245e5c745 579 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
mbed_official 363:12a245e5c745 580
mbed_official 363:12a245e5c745 581 /*!
mbed_official 363:12a245e5c745 582 * @}
mbed_official 363:12a245e5c745 583 */ /* end of group CMP_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 584
mbed_official 363:12a245e5c745 585
mbed_official 363:12a245e5c745 586 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 587 -- CMP Register Masks
mbed_official 363:12a245e5c745 588 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 589
mbed_official 363:12a245e5c745 590 /*!
mbed_official 363:12a245e5c745 591 * @addtogroup CMP_Register_Masks CMP Register Masks
mbed_official 363:12a245e5c745 592 * @{
mbed_official 363:12a245e5c745 593 */
mbed_official 363:12a245e5c745 594
mbed_official 363:12a245e5c745 595 /* CR0 Bit Fields */
mbed_official 363:12a245e5c745 596 #define CMP_CR0_HYSTCTR_MASK 0x3u
mbed_official 363:12a245e5c745 597 #define CMP_CR0_HYSTCTR_SHIFT 0
mbed_official 363:12a245e5c745 598 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
mbed_official 363:12a245e5c745 599 #define CMP_CR0_FILTER_CNT_MASK 0x70u
mbed_official 363:12a245e5c745 600 #define CMP_CR0_FILTER_CNT_SHIFT 4
mbed_official 363:12a245e5c745 601 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
mbed_official 363:12a245e5c745 602 /* CR1 Bit Fields */
mbed_official 363:12a245e5c745 603 #define CMP_CR1_EN_MASK 0x1u
mbed_official 363:12a245e5c745 604 #define CMP_CR1_EN_SHIFT 0
mbed_official 363:12a245e5c745 605 #define CMP_CR1_OPE_MASK 0x2u
mbed_official 363:12a245e5c745 606 #define CMP_CR1_OPE_SHIFT 1
mbed_official 363:12a245e5c745 607 #define CMP_CR1_COS_MASK 0x4u
mbed_official 363:12a245e5c745 608 #define CMP_CR1_COS_SHIFT 2
mbed_official 363:12a245e5c745 609 #define CMP_CR1_INV_MASK 0x8u
mbed_official 363:12a245e5c745 610 #define CMP_CR1_INV_SHIFT 3
mbed_official 363:12a245e5c745 611 #define CMP_CR1_PMODE_MASK 0x10u
mbed_official 363:12a245e5c745 612 #define CMP_CR1_PMODE_SHIFT 4
mbed_official 363:12a245e5c745 613 #define CMP_CR1_TRIGM_MASK 0x20u
mbed_official 363:12a245e5c745 614 #define CMP_CR1_TRIGM_SHIFT 5
mbed_official 363:12a245e5c745 615 #define CMP_CR1_WE_MASK 0x40u
mbed_official 363:12a245e5c745 616 #define CMP_CR1_WE_SHIFT 6
mbed_official 363:12a245e5c745 617 #define CMP_CR1_SE_MASK 0x80u
mbed_official 363:12a245e5c745 618 #define CMP_CR1_SE_SHIFT 7
mbed_official 363:12a245e5c745 619 /* FPR Bit Fields */
mbed_official 363:12a245e5c745 620 #define CMP_FPR_FILT_PER_MASK 0xFFu
mbed_official 363:12a245e5c745 621 #define CMP_FPR_FILT_PER_SHIFT 0
mbed_official 363:12a245e5c745 622 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
mbed_official 363:12a245e5c745 623 /* SCR Bit Fields */
mbed_official 363:12a245e5c745 624 #define CMP_SCR_COUT_MASK 0x1u
mbed_official 363:12a245e5c745 625 #define CMP_SCR_COUT_SHIFT 0
mbed_official 363:12a245e5c745 626 #define CMP_SCR_CFF_MASK 0x2u
mbed_official 363:12a245e5c745 627 #define CMP_SCR_CFF_SHIFT 1
mbed_official 363:12a245e5c745 628 #define CMP_SCR_CFR_MASK 0x4u
mbed_official 363:12a245e5c745 629 #define CMP_SCR_CFR_SHIFT 2
mbed_official 363:12a245e5c745 630 #define CMP_SCR_IEF_MASK 0x8u
mbed_official 363:12a245e5c745 631 #define CMP_SCR_IEF_SHIFT 3
mbed_official 363:12a245e5c745 632 #define CMP_SCR_IER_MASK 0x10u
mbed_official 363:12a245e5c745 633 #define CMP_SCR_IER_SHIFT 4
mbed_official 363:12a245e5c745 634 #define CMP_SCR_DMAEN_MASK 0x40u
mbed_official 363:12a245e5c745 635 #define CMP_SCR_DMAEN_SHIFT 6
mbed_official 363:12a245e5c745 636 /* DACCR Bit Fields */
mbed_official 363:12a245e5c745 637 #define CMP_DACCR_VOSEL_MASK 0x3Fu
mbed_official 363:12a245e5c745 638 #define CMP_DACCR_VOSEL_SHIFT 0
mbed_official 363:12a245e5c745 639 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
mbed_official 363:12a245e5c745 640 #define CMP_DACCR_VRSEL_MASK 0x40u
mbed_official 363:12a245e5c745 641 #define CMP_DACCR_VRSEL_SHIFT 6
mbed_official 363:12a245e5c745 642 #define CMP_DACCR_DACEN_MASK 0x80u
mbed_official 363:12a245e5c745 643 #define CMP_DACCR_DACEN_SHIFT 7
mbed_official 363:12a245e5c745 644 /* MUXCR Bit Fields */
mbed_official 363:12a245e5c745 645 #define CMP_MUXCR_MSEL_MASK 0x7u
mbed_official 363:12a245e5c745 646 #define CMP_MUXCR_MSEL_SHIFT 0
mbed_official 363:12a245e5c745 647 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
mbed_official 363:12a245e5c745 648 #define CMP_MUXCR_PSEL_MASK 0x38u
mbed_official 363:12a245e5c745 649 #define CMP_MUXCR_PSEL_SHIFT 3
mbed_official 363:12a245e5c745 650 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
mbed_official 363:12a245e5c745 651 #define CMP_MUXCR_PSTM_MASK 0x80u
mbed_official 363:12a245e5c745 652 #define CMP_MUXCR_PSTM_SHIFT 7
mbed_official 363:12a245e5c745 653
mbed_official 363:12a245e5c745 654 /*!
mbed_official 363:12a245e5c745 655 * @}
mbed_official 363:12a245e5c745 656 */ /* end of group CMP_Register_Masks */
mbed_official 363:12a245e5c745 657
mbed_official 363:12a245e5c745 658
mbed_official 363:12a245e5c745 659 /* CMP - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 660 /** Peripheral CMP0 base address */
mbed_official 363:12a245e5c745 661 #define CMP0_BASE (0x40073000u)
mbed_official 363:12a245e5c745 662 /** Peripheral CMP0 base pointer */
mbed_official 363:12a245e5c745 663 #define CMP0 ((CMP_Type *)CMP0_BASE)
mbed_official 363:12a245e5c745 664 #define CMP0_BASE_PTR (CMP0)
mbed_official 363:12a245e5c745 665 /** Array initializer of CMP peripheral base addresses */
mbed_official 363:12a245e5c745 666 #define CMP_BASE_ADDRS { CMP0_BASE }
mbed_official 363:12a245e5c745 667 /** Array initializer of CMP peripheral base pointers */
mbed_official 363:12a245e5c745 668 #define CMP_BASE_PTRS { CMP0 }
mbed_official 363:12a245e5c745 669 /** Interrupt vectors for the CMP peripheral type */
mbed_official 363:12a245e5c745 670 #define CMP_IRQS { CMP0_IRQn }
mbed_official 363:12a245e5c745 671
mbed_official 363:12a245e5c745 672 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 673 -- CMP - Register accessor macros
mbed_official 363:12a245e5c745 674 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 675
mbed_official 363:12a245e5c745 676 /*!
mbed_official 363:12a245e5c745 677 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
mbed_official 363:12a245e5c745 678 * @{
mbed_official 363:12a245e5c745 679 */
mbed_official 363:12a245e5c745 680
mbed_official 363:12a245e5c745 681
mbed_official 363:12a245e5c745 682 /* CMP - Register instance definitions */
mbed_official 363:12a245e5c745 683 /* CMP0 */
mbed_official 363:12a245e5c745 684 #define CMP0_CR0 CMP_CR0_REG(CMP0)
mbed_official 363:12a245e5c745 685 #define CMP0_CR1 CMP_CR1_REG(CMP0)
mbed_official 363:12a245e5c745 686 #define CMP0_FPR CMP_FPR_REG(CMP0)
mbed_official 363:12a245e5c745 687 #define CMP0_SCR CMP_SCR_REG(CMP0)
mbed_official 363:12a245e5c745 688 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
mbed_official 363:12a245e5c745 689 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
mbed_official 363:12a245e5c745 690
mbed_official 363:12a245e5c745 691 /*!
mbed_official 363:12a245e5c745 692 * @}
mbed_official 363:12a245e5c745 693 */ /* end of group CMP_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 694
mbed_official 363:12a245e5c745 695
mbed_official 363:12a245e5c745 696 /*!
mbed_official 363:12a245e5c745 697 * @}
mbed_official 363:12a245e5c745 698 */ /* end of group CMP_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 699
mbed_official 363:12a245e5c745 700
mbed_official 363:12a245e5c745 701 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 702 -- DAC Peripheral Access Layer
mbed_official 363:12a245e5c745 703 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 704
mbed_official 363:12a245e5c745 705 /*!
mbed_official 363:12a245e5c745 706 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
mbed_official 363:12a245e5c745 707 * @{
mbed_official 363:12a245e5c745 708 */
mbed_official 363:12a245e5c745 709
mbed_official 363:12a245e5c745 710 /** DAC - Register Layout Typedef */
mbed_official 363:12a245e5c745 711 typedef struct {
mbed_official 363:12a245e5c745 712 struct { /* offset: 0x0, array step: 0x2 */
mbed_official 363:12a245e5c745 713 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
mbed_official 363:12a245e5c745 714 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
mbed_official 363:12a245e5c745 715 } DAT[2];
mbed_official 363:12a245e5c745 716 uint8_t RESERVED_0[28];
mbed_official 363:12a245e5c745 717 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
mbed_official 363:12a245e5c745 718 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
mbed_official 363:12a245e5c745 719 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
mbed_official 363:12a245e5c745 720 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
mbed_official 363:12a245e5c745 721 } DAC_Type, *DAC_MemMapPtr;
mbed_official 363:12a245e5c745 722
mbed_official 363:12a245e5c745 723 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 724 -- DAC - Register accessor macros
mbed_official 363:12a245e5c745 725 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 726
mbed_official 363:12a245e5c745 727 /*!
mbed_official 363:12a245e5c745 728 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
mbed_official 363:12a245e5c745 729 * @{
mbed_official 363:12a245e5c745 730 */
mbed_official 363:12a245e5c745 731
mbed_official 363:12a245e5c745 732
mbed_official 363:12a245e5c745 733 /* DAC - Register accessors */
mbed_official 363:12a245e5c745 734 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
mbed_official 363:12a245e5c745 735 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
mbed_official 363:12a245e5c745 736 #define DAC_SR_REG(base) ((base)->SR)
mbed_official 363:12a245e5c745 737 #define DAC_C0_REG(base) ((base)->C0)
mbed_official 363:12a245e5c745 738 #define DAC_C1_REG(base) ((base)->C1)
mbed_official 363:12a245e5c745 739 #define DAC_C2_REG(base) ((base)->C2)
mbed_official 363:12a245e5c745 740
mbed_official 363:12a245e5c745 741 /*!
mbed_official 363:12a245e5c745 742 * @}
mbed_official 363:12a245e5c745 743 */ /* end of group DAC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 744
mbed_official 363:12a245e5c745 745
mbed_official 363:12a245e5c745 746 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 747 -- DAC Register Masks
mbed_official 363:12a245e5c745 748 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 749
mbed_official 363:12a245e5c745 750 /*!
mbed_official 363:12a245e5c745 751 * @addtogroup DAC_Register_Masks DAC Register Masks
mbed_official 363:12a245e5c745 752 * @{
mbed_official 363:12a245e5c745 753 */
mbed_official 363:12a245e5c745 754
mbed_official 363:12a245e5c745 755 /* DATL Bit Fields */
mbed_official 363:12a245e5c745 756 #define DAC_DATL_DATA0_MASK 0xFFu
mbed_official 363:12a245e5c745 757 #define DAC_DATL_DATA0_SHIFT 0
mbed_official 363:12a245e5c745 758 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
mbed_official 363:12a245e5c745 759 /* DATH Bit Fields */
mbed_official 363:12a245e5c745 760 #define DAC_DATH_DATA1_MASK 0xFu
mbed_official 363:12a245e5c745 761 #define DAC_DATH_DATA1_SHIFT 0
mbed_official 363:12a245e5c745 762 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
mbed_official 363:12a245e5c745 763 /* SR Bit Fields */
mbed_official 363:12a245e5c745 764 #define DAC_SR_DACBFRPBF_MASK 0x1u
mbed_official 363:12a245e5c745 765 #define DAC_SR_DACBFRPBF_SHIFT 0
mbed_official 363:12a245e5c745 766 #define DAC_SR_DACBFRPTF_MASK 0x2u
mbed_official 363:12a245e5c745 767 #define DAC_SR_DACBFRPTF_SHIFT 1
mbed_official 363:12a245e5c745 768 /* C0 Bit Fields */
mbed_official 363:12a245e5c745 769 #define DAC_C0_DACBBIEN_MASK 0x1u
mbed_official 363:12a245e5c745 770 #define DAC_C0_DACBBIEN_SHIFT 0
mbed_official 363:12a245e5c745 771 #define DAC_C0_DACBTIEN_MASK 0x2u
mbed_official 363:12a245e5c745 772 #define DAC_C0_DACBTIEN_SHIFT 1
mbed_official 363:12a245e5c745 773 #define DAC_C0_LPEN_MASK 0x8u
mbed_official 363:12a245e5c745 774 #define DAC_C0_LPEN_SHIFT 3
mbed_official 363:12a245e5c745 775 #define DAC_C0_DACSWTRG_MASK 0x10u
mbed_official 363:12a245e5c745 776 #define DAC_C0_DACSWTRG_SHIFT 4
mbed_official 363:12a245e5c745 777 #define DAC_C0_DACTRGSEL_MASK 0x20u
mbed_official 363:12a245e5c745 778 #define DAC_C0_DACTRGSEL_SHIFT 5
mbed_official 363:12a245e5c745 779 #define DAC_C0_DACRFS_MASK 0x40u
mbed_official 363:12a245e5c745 780 #define DAC_C0_DACRFS_SHIFT 6
mbed_official 363:12a245e5c745 781 #define DAC_C0_DACEN_MASK 0x80u
mbed_official 363:12a245e5c745 782 #define DAC_C0_DACEN_SHIFT 7
mbed_official 363:12a245e5c745 783 /* C1 Bit Fields */
mbed_official 363:12a245e5c745 784 #define DAC_C1_DACBFEN_MASK 0x1u
mbed_official 363:12a245e5c745 785 #define DAC_C1_DACBFEN_SHIFT 0
mbed_official 363:12a245e5c745 786 #define DAC_C1_DACBFMD_MASK 0x6u
mbed_official 363:12a245e5c745 787 #define DAC_C1_DACBFMD_SHIFT 1
mbed_official 363:12a245e5c745 788 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
mbed_official 363:12a245e5c745 789 #define DAC_C1_DMAEN_MASK 0x80u
mbed_official 363:12a245e5c745 790 #define DAC_C1_DMAEN_SHIFT 7
mbed_official 363:12a245e5c745 791 /* C2 Bit Fields */
mbed_official 363:12a245e5c745 792 #define DAC_C2_DACBFUP_MASK 0x1u
mbed_official 363:12a245e5c745 793 #define DAC_C2_DACBFUP_SHIFT 0
mbed_official 363:12a245e5c745 794 #define DAC_C2_DACBFRP_MASK 0x10u
mbed_official 363:12a245e5c745 795 #define DAC_C2_DACBFRP_SHIFT 4
mbed_official 363:12a245e5c745 796
mbed_official 363:12a245e5c745 797 /*!
mbed_official 363:12a245e5c745 798 * @}
mbed_official 363:12a245e5c745 799 */ /* end of group DAC_Register_Masks */
mbed_official 363:12a245e5c745 800
mbed_official 363:12a245e5c745 801
mbed_official 363:12a245e5c745 802 /* DAC - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 803 /** Peripheral DAC0 base address */
mbed_official 363:12a245e5c745 804 #define DAC0_BASE (0x4003F000u)
mbed_official 363:12a245e5c745 805 /** Peripheral DAC0 base pointer */
mbed_official 363:12a245e5c745 806 #define DAC0 ((DAC_Type *)DAC0_BASE)
mbed_official 363:12a245e5c745 807 #define DAC0_BASE_PTR (DAC0)
mbed_official 363:12a245e5c745 808 /** Array initializer of DAC peripheral base addresses */
mbed_official 363:12a245e5c745 809 #define DAC_BASE_ADDRS { DAC0_BASE }
mbed_official 363:12a245e5c745 810 /** Array initializer of DAC peripheral base pointers */
mbed_official 363:12a245e5c745 811 #define DAC_BASE_PTRS { DAC0 }
mbed_official 363:12a245e5c745 812 /** Interrupt vectors for the DAC peripheral type */
mbed_official 363:12a245e5c745 813 #define DAC_IRQS { DAC0_IRQn }
mbed_official 363:12a245e5c745 814
mbed_official 363:12a245e5c745 815 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 816 -- DAC - Register accessor macros
mbed_official 363:12a245e5c745 817 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 818
mbed_official 363:12a245e5c745 819 /*!
mbed_official 363:12a245e5c745 820 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
mbed_official 363:12a245e5c745 821 * @{
mbed_official 363:12a245e5c745 822 */
mbed_official 363:12a245e5c745 823
mbed_official 363:12a245e5c745 824
mbed_official 363:12a245e5c745 825 /* DAC - Register instance definitions */
mbed_official 363:12a245e5c745 826 /* DAC0 */
mbed_official 363:12a245e5c745 827 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
mbed_official 363:12a245e5c745 828 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
mbed_official 363:12a245e5c745 829 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
mbed_official 363:12a245e5c745 830 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
mbed_official 363:12a245e5c745 831 #define DAC0_SR DAC_SR_REG(DAC0)
mbed_official 363:12a245e5c745 832 #define DAC0_C0 DAC_C0_REG(DAC0)
mbed_official 363:12a245e5c745 833 #define DAC0_C1 DAC_C1_REG(DAC0)
mbed_official 363:12a245e5c745 834 #define DAC0_C2 DAC_C2_REG(DAC0)
mbed_official 363:12a245e5c745 835
mbed_official 363:12a245e5c745 836 /* DAC - Register array accessors */
mbed_official 363:12a245e5c745 837 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
mbed_official 363:12a245e5c745 838 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
mbed_official 363:12a245e5c745 839
mbed_official 363:12a245e5c745 840 /*!
mbed_official 363:12a245e5c745 841 * @}
mbed_official 363:12a245e5c745 842 */ /* end of group DAC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 843
mbed_official 363:12a245e5c745 844
mbed_official 363:12a245e5c745 845 /*!
mbed_official 363:12a245e5c745 846 * @}
mbed_official 363:12a245e5c745 847 */ /* end of group DAC_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 848
mbed_official 363:12a245e5c745 849
mbed_official 363:12a245e5c745 850 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 851 -- DMA Peripheral Access Layer
mbed_official 363:12a245e5c745 852 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 853
mbed_official 363:12a245e5c745 854 /*!
mbed_official 363:12a245e5c745 855 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
mbed_official 363:12a245e5c745 856 * @{
mbed_official 363:12a245e5c745 857 */
mbed_official 363:12a245e5c745 858
mbed_official 363:12a245e5c745 859 /** DMA - Register Layout Typedef */
mbed_official 363:12a245e5c745 860 typedef struct {
mbed_official 363:12a245e5c745 861 uint8_t RESERVED_0[256];
mbed_official 363:12a245e5c745 862 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 363:12a245e5c745 863 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
mbed_official 363:12a245e5c745 864 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
mbed_official 363:12a245e5c745 865 union { /* offset: 0x108, array step: 0x10 */
mbed_official 363:12a245e5c745 866 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
mbed_official 363:12a245e5c745 867 struct { /* offset: 0x108, array step: 0x10 */
mbed_official 363:12a245e5c745 868 uint8_t RESERVED_0[3];
mbed_official 363:12a245e5c745 869 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
mbed_official 363:12a245e5c745 870 } DMA_DSR_ACCESS8BIT;
mbed_official 363:12a245e5c745 871 };
mbed_official 363:12a245e5c745 872 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
mbed_official 363:12a245e5c745 873 } DMA[4];
mbed_official 363:12a245e5c745 874 } DMA_Type, *DMA_MemMapPtr;
mbed_official 363:12a245e5c745 875
mbed_official 363:12a245e5c745 876 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 877 -- DMA - Register accessor macros
mbed_official 363:12a245e5c745 878 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 879
mbed_official 363:12a245e5c745 880 /*!
mbed_official 363:12a245e5c745 881 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
mbed_official 363:12a245e5c745 882 * @{
mbed_official 363:12a245e5c745 883 */
mbed_official 363:12a245e5c745 884
mbed_official 363:12a245e5c745 885
mbed_official 363:12a245e5c745 886 /* DMA - Register accessors */
mbed_official 363:12a245e5c745 887 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
mbed_official 363:12a245e5c745 888 #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
mbed_official 363:12a245e5c745 889 #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
mbed_official 363:12a245e5c745 890 #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
mbed_official 363:12a245e5c745 891 #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
mbed_official 363:12a245e5c745 892
mbed_official 363:12a245e5c745 893 /*!
mbed_official 363:12a245e5c745 894 * @}
mbed_official 363:12a245e5c745 895 */ /* end of group DMA_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 896
mbed_official 363:12a245e5c745 897
mbed_official 363:12a245e5c745 898 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 899 -- DMA Register Masks
mbed_official 363:12a245e5c745 900 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 901
mbed_official 363:12a245e5c745 902 /*!
mbed_official 363:12a245e5c745 903 * @addtogroup DMA_Register_Masks DMA Register Masks
mbed_official 363:12a245e5c745 904 * @{
mbed_official 363:12a245e5c745 905 */
mbed_official 363:12a245e5c745 906
mbed_official 363:12a245e5c745 907 /* SAR Bit Fields */
mbed_official 363:12a245e5c745 908 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 909 #define DMA_SAR_SAR_SHIFT 0
mbed_official 363:12a245e5c745 910 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
mbed_official 363:12a245e5c745 911 /* DAR Bit Fields */
mbed_official 363:12a245e5c745 912 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 913 #define DMA_DAR_DAR_SHIFT 0
mbed_official 363:12a245e5c745 914 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
mbed_official 363:12a245e5c745 915 /* DSR_BCR Bit Fields */
mbed_official 363:12a245e5c745 916 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
mbed_official 363:12a245e5c745 917 #define DMA_DSR_BCR_BCR_SHIFT 0
mbed_official 363:12a245e5c745 918 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
mbed_official 363:12a245e5c745 919 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
mbed_official 363:12a245e5c745 920 #define DMA_DSR_BCR_DONE_SHIFT 24
mbed_official 363:12a245e5c745 921 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
mbed_official 363:12a245e5c745 922 #define DMA_DSR_BCR_BSY_SHIFT 25
mbed_official 363:12a245e5c745 923 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
mbed_official 363:12a245e5c745 924 #define DMA_DSR_BCR_REQ_SHIFT 26
mbed_official 363:12a245e5c745 925 #define DMA_DSR_BCR_BED_MASK 0x10000000u
mbed_official 363:12a245e5c745 926 #define DMA_DSR_BCR_BED_SHIFT 28
mbed_official 363:12a245e5c745 927 #define DMA_DSR_BCR_BES_MASK 0x20000000u
mbed_official 363:12a245e5c745 928 #define DMA_DSR_BCR_BES_SHIFT 29
mbed_official 363:12a245e5c745 929 #define DMA_DSR_BCR_CE_MASK 0x40000000u
mbed_official 363:12a245e5c745 930 #define DMA_DSR_BCR_CE_SHIFT 30
mbed_official 363:12a245e5c745 931 /* DCR Bit Fields */
mbed_official 363:12a245e5c745 932 #define DMA_DCR_LCH2_MASK 0x3u
mbed_official 363:12a245e5c745 933 #define DMA_DCR_LCH2_SHIFT 0
mbed_official 363:12a245e5c745 934 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
mbed_official 363:12a245e5c745 935 #define DMA_DCR_LCH1_MASK 0xCu
mbed_official 363:12a245e5c745 936 #define DMA_DCR_LCH1_SHIFT 2
mbed_official 363:12a245e5c745 937 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
mbed_official 363:12a245e5c745 938 #define DMA_DCR_LINKCC_MASK 0x30u
mbed_official 363:12a245e5c745 939 #define DMA_DCR_LINKCC_SHIFT 4
mbed_official 363:12a245e5c745 940 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
mbed_official 363:12a245e5c745 941 #define DMA_DCR_D_REQ_MASK 0x80u
mbed_official 363:12a245e5c745 942 #define DMA_DCR_D_REQ_SHIFT 7
mbed_official 363:12a245e5c745 943 #define DMA_DCR_DMOD_MASK 0xF00u
mbed_official 363:12a245e5c745 944 #define DMA_DCR_DMOD_SHIFT 8
mbed_official 363:12a245e5c745 945 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
mbed_official 363:12a245e5c745 946 #define DMA_DCR_SMOD_MASK 0xF000u
mbed_official 363:12a245e5c745 947 #define DMA_DCR_SMOD_SHIFT 12
mbed_official 363:12a245e5c745 948 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
mbed_official 363:12a245e5c745 949 #define DMA_DCR_START_MASK 0x10000u
mbed_official 363:12a245e5c745 950 #define DMA_DCR_START_SHIFT 16
mbed_official 363:12a245e5c745 951 #define DMA_DCR_DSIZE_MASK 0x60000u
mbed_official 363:12a245e5c745 952 #define DMA_DCR_DSIZE_SHIFT 17
mbed_official 363:12a245e5c745 953 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
mbed_official 363:12a245e5c745 954 #define DMA_DCR_DINC_MASK 0x80000u
mbed_official 363:12a245e5c745 955 #define DMA_DCR_DINC_SHIFT 19
mbed_official 363:12a245e5c745 956 #define DMA_DCR_SSIZE_MASK 0x300000u
mbed_official 363:12a245e5c745 957 #define DMA_DCR_SSIZE_SHIFT 20
mbed_official 363:12a245e5c745 958 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
mbed_official 363:12a245e5c745 959 #define DMA_DCR_SINC_MASK 0x400000u
mbed_official 363:12a245e5c745 960 #define DMA_DCR_SINC_SHIFT 22
mbed_official 363:12a245e5c745 961 #define DMA_DCR_EADREQ_MASK 0x800000u
mbed_official 363:12a245e5c745 962 #define DMA_DCR_EADREQ_SHIFT 23
mbed_official 363:12a245e5c745 963 #define DMA_DCR_AA_MASK 0x10000000u
mbed_official 363:12a245e5c745 964 #define DMA_DCR_AA_SHIFT 28
mbed_official 363:12a245e5c745 965 #define DMA_DCR_CS_MASK 0x20000000u
mbed_official 363:12a245e5c745 966 #define DMA_DCR_CS_SHIFT 29
mbed_official 363:12a245e5c745 967 #define DMA_DCR_ERQ_MASK 0x40000000u
mbed_official 363:12a245e5c745 968 #define DMA_DCR_ERQ_SHIFT 30
mbed_official 363:12a245e5c745 969 #define DMA_DCR_EINT_MASK 0x80000000u
mbed_official 363:12a245e5c745 970 #define DMA_DCR_EINT_SHIFT 31
mbed_official 363:12a245e5c745 971
mbed_official 363:12a245e5c745 972 /*!
mbed_official 363:12a245e5c745 973 * @}
mbed_official 363:12a245e5c745 974 */ /* end of group DMA_Register_Masks */
mbed_official 363:12a245e5c745 975
mbed_official 363:12a245e5c745 976
mbed_official 363:12a245e5c745 977 /* DMA - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 978 /** Peripheral DMA base address */
mbed_official 363:12a245e5c745 979 #define DMA_BASE (0x40008000u)
mbed_official 363:12a245e5c745 980 /** Peripheral DMA base pointer */
mbed_official 363:12a245e5c745 981 #define DMA0 ((DMA_Type *)DMA_BASE)
mbed_official 363:12a245e5c745 982 #define DMA_BASE_PTR (DMA0)
mbed_official 363:12a245e5c745 983 /** Array initializer of DMA peripheral base addresses */
mbed_official 363:12a245e5c745 984 #define DMA_BASE_ADDRS { DMA_BASE }
mbed_official 363:12a245e5c745 985 /** Array initializer of DMA peripheral base pointers */
mbed_official 363:12a245e5c745 986 #define DMA_BASE_PTRS { DMA0 }
mbed_official 363:12a245e5c745 987 /** Interrupt vectors for the DMA peripheral type */
mbed_official 363:12a245e5c745 988 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
mbed_official 363:12a245e5c745 989
mbed_official 363:12a245e5c745 990 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 991 -- DMA - Register accessor macros
mbed_official 363:12a245e5c745 992 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 993
mbed_official 363:12a245e5c745 994 /*!
mbed_official 363:12a245e5c745 995 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
mbed_official 363:12a245e5c745 996 * @{
mbed_official 363:12a245e5c745 997 */
mbed_official 363:12a245e5c745 998
mbed_official 363:12a245e5c745 999
mbed_official 363:12a245e5c745 1000 /* DMA - Register instance definitions */
mbed_official 363:12a245e5c745 1001 /* DMA */
mbed_official 363:12a245e5c745 1002 #define DMA_SAR0 DMA_SAR_REG(DMA0,0)
mbed_official 363:12a245e5c745 1003 #define DMA_DAR0 DMA_DAR_REG(DMA0,0)
mbed_official 363:12a245e5c745 1004 #define DMA_DSR_BCR0 DMA_DSR_BCR_REG(DMA0,0)
mbed_official 363:12a245e5c745 1005 #define DMA_DSR0 DMA_DSR_REG(DMA0,0)
mbed_official 363:12a245e5c745 1006 #define DMA_DCR0 DMA_DCR_REG(DMA0,0)
mbed_official 363:12a245e5c745 1007 #define DMA_SAR1 DMA_SAR_REG(DMA0,1)
mbed_official 363:12a245e5c745 1008 #define DMA_DAR1 DMA_DAR_REG(DMA0,1)
mbed_official 363:12a245e5c745 1009 #define DMA_DSR_BCR1 DMA_DSR_BCR_REG(DMA0,1)
mbed_official 363:12a245e5c745 1010 #define DMA_DSR1 DMA_DSR_REG(DMA0,1)
mbed_official 363:12a245e5c745 1011 #define DMA_DCR1 DMA_DCR_REG(DMA0,1)
mbed_official 363:12a245e5c745 1012 #define DMA_SAR2 DMA_SAR_REG(DMA0,2)
mbed_official 363:12a245e5c745 1013 #define DMA_DAR2 DMA_DAR_REG(DMA0,2)
mbed_official 363:12a245e5c745 1014 #define DMA_DSR_BCR2 DMA_DSR_BCR_REG(DMA0,2)
mbed_official 363:12a245e5c745 1015 #define DMA_DSR2 DMA_DSR_REG(DMA0,2)
mbed_official 363:12a245e5c745 1016 #define DMA_DCR2 DMA_DCR_REG(DMA0,2)
mbed_official 363:12a245e5c745 1017 #define DMA_SAR3 DMA_SAR_REG(DMA0,3)
mbed_official 363:12a245e5c745 1018 #define DMA_DAR3 DMA_DAR_REG(DMA0,3)
mbed_official 363:12a245e5c745 1019 #define DMA_DSR_BCR3 DMA_DSR_BCR_REG(DMA0,3)
mbed_official 363:12a245e5c745 1020 #define DMA_DSR3 DMA_DSR_REG(DMA0,3)
mbed_official 363:12a245e5c745 1021 #define DMA_DCR3 DMA_DCR_REG(DMA0,3)
mbed_official 363:12a245e5c745 1022
mbed_official 363:12a245e5c745 1023 /* DMA - Register array accessors */
mbed_official 363:12a245e5c745 1024 #define DMA_SAR(index) DMA_SAR_REG(DMA0,index)
mbed_official 363:12a245e5c745 1025 #define DMA_DAR(index) DMA_DAR_REG(DMA0,index)
mbed_official 363:12a245e5c745 1026 #define DMA_DSR_BCR(index) DMA_DSR_BCR_REG(DMA0,index)
mbed_official 363:12a245e5c745 1027 #define DMA_DSR(index) DMA_DSR_REG(DMA0,index)
mbed_official 363:12a245e5c745 1028 #define DMA_DCR(index) DMA_DCR_REG(DMA0,index)
mbed_official 363:12a245e5c745 1029
mbed_official 363:12a245e5c745 1030 /*!
mbed_official 363:12a245e5c745 1031 * @}
mbed_official 363:12a245e5c745 1032 */ /* end of group DMA_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 1033
mbed_official 363:12a245e5c745 1034
mbed_official 363:12a245e5c745 1035 /*!
mbed_official 363:12a245e5c745 1036 * @}
mbed_official 363:12a245e5c745 1037 */ /* end of group DMA_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 1038
mbed_official 363:12a245e5c745 1039
mbed_official 363:12a245e5c745 1040 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1041 -- DMAMUX Peripheral Access Layer
mbed_official 363:12a245e5c745 1042 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1043
mbed_official 363:12a245e5c745 1044 /*!
mbed_official 363:12a245e5c745 1045 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
mbed_official 363:12a245e5c745 1046 * @{
mbed_official 363:12a245e5c745 1047 */
mbed_official 363:12a245e5c745 1048
mbed_official 363:12a245e5c745 1049 /** DMAMUX - Register Layout Typedef */
mbed_official 363:12a245e5c745 1050 typedef struct {
mbed_official 363:12a245e5c745 1051 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
mbed_official 363:12a245e5c745 1052 } DMAMUX_Type, *DMAMUX_MemMapPtr;
mbed_official 363:12a245e5c745 1053
mbed_official 363:12a245e5c745 1054 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1055 -- DMAMUX - Register accessor macros
mbed_official 363:12a245e5c745 1056 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1057
mbed_official 363:12a245e5c745 1058 /*!
mbed_official 363:12a245e5c745 1059 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
mbed_official 363:12a245e5c745 1060 * @{
mbed_official 363:12a245e5c745 1061 */
mbed_official 363:12a245e5c745 1062
mbed_official 363:12a245e5c745 1063
mbed_official 363:12a245e5c745 1064 /* DMAMUX - Register accessors */
mbed_official 363:12a245e5c745 1065 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
mbed_official 363:12a245e5c745 1066
mbed_official 363:12a245e5c745 1067 /*!
mbed_official 363:12a245e5c745 1068 * @}
mbed_official 363:12a245e5c745 1069 */ /* end of group DMAMUX_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 1070
mbed_official 363:12a245e5c745 1071
mbed_official 363:12a245e5c745 1072 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1073 -- DMAMUX Register Masks
mbed_official 363:12a245e5c745 1074 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1075
mbed_official 363:12a245e5c745 1076 /*!
mbed_official 363:12a245e5c745 1077 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
mbed_official 363:12a245e5c745 1078 * @{
mbed_official 363:12a245e5c745 1079 */
mbed_official 363:12a245e5c745 1080
mbed_official 363:12a245e5c745 1081 /* CHCFG Bit Fields */
mbed_official 363:12a245e5c745 1082 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
mbed_official 363:12a245e5c745 1083 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
mbed_official 363:12a245e5c745 1084 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
mbed_official 363:12a245e5c745 1085 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
mbed_official 363:12a245e5c745 1086 #define DMAMUX_CHCFG_TRIG_SHIFT 6
mbed_official 363:12a245e5c745 1087 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
mbed_official 363:12a245e5c745 1088 #define DMAMUX_CHCFG_ENBL_SHIFT 7
mbed_official 363:12a245e5c745 1089
mbed_official 363:12a245e5c745 1090 /*!
mbed_official 363:12a245e5c745 1091 * @}
mbed_official 363:12a245e5c745 1092 */ /* end of group DMAMUX_Register_Masks */
mbed_official 363:12a245e5c745 1093
mbed_official 363:12a245e5c745 1094
mbed_official 363:12a245e5c745 1095 /* DMAMUX - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 1096 /** Peripheral DMAMUX0 base address */
mbed_official 363:12a245e5c745 1097 #define DMAMUX0_BASE (0x40021000u)
mbed_official 363:12a245e5c745 1098 /** Peripheral DMAMUX0 base pointer */
mbed_official 363:12a245e5c745 1099 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
mbed_official 363:12a245e5c745 1100 #define DMAMUX0_BASE_PTR (DMAMUX0)
mbed_official 363:12a245e5c745 1101 /** Array initializer of DMAMUX peripheral base addresses */
mbed_official 363:12a245e5c745 1102 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
mbed_official 363:12a245e5c745 1103 /** Array initializer of DMAMUX peripheral base pointers */
mbed_official 363:12a245e5c745 1104 #define DMAMUX_BASE_PTRS { DMAMUX0 }
mbed_official 363:12a245e5c745 1105
mbed_official 363:12a245e5c745 1106 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1107 -- DMAMUX - Register accessor macros
mbed_official 363:12a245e5c745 1108 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1109
mbed_official 363:12a245e5c745 1110 /*!
mbed_official 363:12a245e5c745 1111 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
mbed_official 363:12a245e5c745 1112 * @{
mbed_official 363:12a245e5c745 1113 */
mbed_official 363:12a245e5c745 1114
mbed_official 363:12a245e5c745 1115
mbed_official 363:12a245e5c745 1116 /* DMAMUX - Register instance definitions */
mbed_official 363:12a245e5c745 1117 /* DMAMUX0 */
mbed_official 363:12a245e5c745 1118 #define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0,0)
mbed_official 363:12a245e5c745 1119 #define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0,1)
mbed_official 363:12a245e5c745 1120 #define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0,2)
mbed_official 363:12a245e5c745 1121 #define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0,3)
mbed_official 363:12a245e5c745 1122
mbed_official 363:12a245e5c745 1123 /* DMAMUX - Register array accessors */
mbed_official 363:12a245e5c745 1124 #define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0,index)
mbed_official 363:12a245e5c745 1125
mbed_official 363:12a245e5c745 1126 /*!
mbed_official 363:12a245e5c745 1127 * @}
mbed_official 363:12a245e5c745 1128 */ /* end of group DMAMUX_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 1129
mbed_official 363:12a245e5c745 1130
mbed_official 363:12a245e5c745 1131 /*!
mbed_official 363:12a245e5c745 1132 * @}
mbed_official 363:12a245e5c745 1133 */ /* end of group DMAMUX_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 1134
mbed_official 363:12a245e5c745 1135
mbed_official 363:12a245e5c745 1136 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1137 -- FLEXIO Peripheral Access Layer
mbed_official 363:12a245e5c745 1138 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1139
mbed_official 363:12a245e5c745 1140 /*!
mbed_official 363:12a245e5c745 1141 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
mbed_official 363:12a245e5c745 1142 * @{
mbed_official 363:12a245e5c745 1143 */
mbed_official 363:12a245e5c745 1144
mbed_official 363:12a245e5c745 1145 /** FLEXIO - Register Layout Typedef */
mbed_official 363:12a245e5c745 1146 typedef struct {
mbed_official 363:12a245e5c745 1147 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
mbed_official 363:12a245e5c745 1148 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
mbed_official 363:12a245e5c745 1149 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
mbed_official 363:12a245e5c745 1150 uint8_t RESERVED_0[4];
mbed_official 363:12a245e5c745 1151 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
mbed_official 363:12a245e5c745 1152 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
mbed_official 363:12a245e5c745 1153 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
mbed_official 363:12a245e5c745 1154 uint8_t RESERVED_1[4];
mbed_official 363:12a245e5c745 1155 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
mbed_official 363:12a245e5c745 1156 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
mbed_official 363:12a245e5c745 1157 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
mbed_official 363:12a245e5c745 1158 uint8_t RESERVED_2[4];
mbed_official 363:12a245e5c745 1159 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
mbed_official 363:12a245e5c745 1160 uint8_t RESERVED_3[76];
mbed_official 363:12a245e5c745 1161 __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
mbed_official 363:12a245e5c745 1162 uint8_t RESERVED_4[112];
mbed_official 363:12a245e5c745 1163 __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
mbed_official 363:12a245e5c745 1164 uint8_t RESERVED_5[240];
mbed_official 363:12a245e5c745 1165 __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
mbed_official 363:12a245e5c745 1166 uint8_t RESERVED_6[112];
mbed_official 363:12a245e5c745 1167 __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x280, array step: 0x4 */
mbed_official 363:12a245e5c745 1168 uint8_t RESERVED_7[112];
mbed_official 363:12a245e5c745 1169 __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
mbed_official 363:12a245e5c745 1170 uint8_t RESERVED_8[112];
mbed_official 363:12a245e5c745 1171 __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x380, array step: 0x4 */
mbed_official 363:12a245e5c745 1172 uint8_t RESERVED_9[112];
mbed_official 363:12a245e5c745 1173 __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
mbed_official 363:12a245e5c745 1174 uint8_t RESERVED_10[112];
mbed_official 363:12a245e5c745 1175 __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
mbed_official 363:12a245e5c745 1176 uint8_t RESERVED_11[112];
mbed_official 363:12a245e5c745 1177 __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
mbed_official 363:12a245e5c745 1178 } FLEXIO_Type, *FLEXIO_MemMapPtr;
mbed_official 363:12a245e5c745 1179
mbed_official 363:12a245e5c745 1180 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1181 -- FLEXIO - Register accessor macros
mbed_official 363:12a245e5c745 1182 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1183
mbed_official 363:12a245e5c745 1184 /*!
mbed_official 363:12a245e5c745 1185 * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
mbed_official 363:12a245e5c745 1186 * @{
mbed_official 363:12a245e5c745 1187 */
mbed_official 363:12a245e5c745 1188
mbed_official 363:12a245e5c745 1189
mbed_official 363:12a245e5c745 1190 /* FLEXIO - Register accessors */
mbed_official 363:12a245e5c745 1191 #define FLEXIO_VERID_REG(base) ((base)->VERID)
mbed_official 363:12a245e5c745 1192 #define FLEXIO_PARAM_REG(base) ((base)->PARAM)
mbed_official 363:12a245e5c745 1193 #define FLEXIO_CTRL_REG(base) ((base)->CTRL)
mbed_official 363:12a245e5c745 1194 #define FLEXIO_SHIFTSTAT_REG(base) ((base)->SHIFTSTAT)
mbed_official 363:12a245e5c745 1195 #define FLEXIO_SHIFTERR_REG(base) ((base)->SHIFTERR)
mbed_official 363:12a245e5c745 1196 #define FLEXIO_TIMSTAT_REG(base) ((base)->TIMSTAT)
mbed_official 363:12a245e5c745 1197 #define FLEXIO_SHIFTSIEN_REG(base) ((base)->SHIFTSIEN)
mbed_official 363:12a245e5c745 1198 #define FLEXIO_SHIFTEIEN_REG(base) ((base)->SHIFTEIEN)
mbed_official 363:12a245e5c745 1199 #define FLEXIO_TIMIEN_REG(base) ((base)->TIMIEN)
mbed_official 363:12a245e5c745 1200 #define FLEXIO_SHIFTSDEN_REG(base) ((base)->SHIFTSDEN)
mbed_official 363:12a245e5c745 1201 #define FLEXIO_SHIFTCTL_REG(base,index) ((base)->SHIFTCTL[index])
mbed_official 363:12a245e5c745 1202 #define FLEXIO_SHIFTCFG_REG(base,index) ((base)->SHIFTCFG[index])
mbed_official 363:12a245e5c745 1203 #define FLEXIO_SHIFTBUF_REG(base,index) ((base)->SHIFTBUF[index])
mbed_official 363:12a245e5c745 1204 #define FLEXIO_SHIFTBUFBBS_REG(base,index) ((base)->SHIFTBUFBBS[index])
mbed_official 363:12a245e5c745 1205 #define FLEXIO_SHIFTBUFBYS_REG(base,index) ((base)->SHIFTBUFBYS[index])
mbed_official 363:12a245e5c745 1206 #define FLEXIO_SHIFTBUFBIS_REG(base,index) ((base)->SHIFTBUFBIS[index])
mbed_official 363:12a245e5c745 1207 #define FLEXIO_TIMCTL_REG(base,index) ((base)->TIMCTL[index])
mbed_official 363:12a245e5c745 1208 #define FLEXIO_TIMCFG_REG(base,index) ((base)->TIMCFG[index])
mbed_official 363:12a245e5c745 1209 #define FLEXIO_TIMCMP_REG(base,index) ((base)->TIMCMP[index])
mbed_official 363:12a245e5c745 1210
mbed_official 363:12a245e5c745 1211 /*!
mbed_official 363:12a245e5c745 1212 * @}
mbed_official 363:12a245e5c745 1213 */ /* end of group FLEXIO_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 1214
mbed_official 363:12a245e5c745 1215
mbed_official 363:12a245e5c745 1216 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1217 -- FLEXIO Register Masks
mbed_official 363:12a245e5c745 1218 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1219
mbed_official 363:12a245e5c745 1220 /*!
mbed_official 363:12a245e5c745 1221 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
mbed_official 363:12a245e5c745 1222 * @{
mbed_official 363:12a245e5c745 1223 */
mbed_official 363:12a245e5c745 1224
mbed_official 363:12a245e5c745 1225 /* VERID Bit Fields */
mbed_official 363:12a245e5c745 1226 #define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
mbed_official 363:12a245e5c745 1227 #define FLEXIO_VERID_FEATURE_SHIFT 0
mbed_official 363:12a245e5c745 1228 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
mbed_official 363:12a245e5c745 1229 #define FLEXIO_VERID_MINOR_MASK 0xFF0000u
mbed_official 363:12a245e5c745 1230 #define FLEXIO_VERID_MINOR_SHIFT 16
mbed_official 363:12a245e5c745 1231 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
mbed_official 363:12a245e5c745 1232 #define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
mbed_official 363:12a245e5c745 1233 #define FLEXIO_VERID_MAJOR_SHIFT 24
mbed_official 363:12a245e5c745 1234 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
mbed_official 363:12a245e5c745 1235 /* PARAM Bit Fields */
mbed_official 363:12a245e5c745 1236 #define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
mbed_official 363:12a245e5c745 1237 #define FLEXIO_PARAM_SHIFTER_SHIFT 0
mbed_official 363:12a245e5c745 1238 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
mbed_official 363:12a245e5c745 1239 #define FLEXIO_PARAM_TIMER_MASK 0xFF00u
mbed_official 363:12a245e5c745 1240 #define FLEXIO_PARAM_TIMER_SHIFT 8
mbed_official 363:12a245e5c745 1241 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
mbed_official 363:12a245e5c745 1242 #define FLEXIO_PARAM_PIN_MASK 0xFF0000u
mbed_official 363:12a245e5c745 1243 #define FLEXIO_PARAM_PIN_SHIFT 16
mbed_official 363:12a245e5c745 1244 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
mbed_official 363:12a245e5c745 1245 #define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
mbed_official 363:12a245e5c745 1246 #define FLEXIO_PARAM_TRIGGER_SHIFT 24
mbed_official 363:12a245e5c745 1247 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
mbed_official 363:12a245e5c745 1248 /* CTRL Bit Fields */
mbed_official 363:12a245e5c745 1249 #define FLEXIO_CTRL_FLEXEN_MASK 0x1u
mbed_official 363:12a245e5c745 1250 #define FLEXIO_CTRL_FLEXEN_SHIFT 0
mbed_official 363:12a245e5c745 1251 #define FLEXIO_CTRL_SWRST_MASK 0x2u
mbed_official 363:12a245e5c745 1252 #define FLEXIO_CTRL_SWRST_SHIFT 1
mbed_official 363:12a245e5c745 1253 #define FLEXIO_CTRL_FASTACC_MASK 0x4u
mbed_official 363:12a245e5c745 1254 #define FLEXIO_CTRL_FASTACC_SHIFT 2
mbed_official 363:12a245e5c745 1255 #define FLEXIO_CTRL_DBGE_MASK 0x40000000u
mbed_official 363:12a245e5c745 1256 #define FLEXIO_CTRL_DBGE_SHIFT 30
mbed_official 363:12a245e5c745 1257 #define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
mbed_official 363:12a245e5c745 1258 #define FLEXIO_CTRL_DOZEN_SHIFT 31
mbed_official 363:12a245e5c745 1259 /* SHIFTSTAT Bit Fields */
mbed_official 363:12a245e5c745 1260 #define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
mbed_official 363:12a245e5c745 1261 #define FLEXIO_SHIFTSTAT_SSF_SHIFT 0
mbed_official 363:12a245e5c745 1262 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
mbed_official 363:12a245e5c745 1263 /* SHIFTERR Bit Fields */
mbed_official 363:12a245e5c745 1264 #define FLEXIO_SHIFTERR_SEF_MASK 0xFu
mbed_official 363:12a245e5c745 1265 #define FLEXIO_SHIFTERR_SEF_SHIFT 0
mbed_official 363:12a245e5c745 1266 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
mbed_official 363:12a245e5c745 1267 /* TIMSTAT Bit Fields */
mbed_official 363:12a245e5c745 1268 #define FLEXIO_TIMSTAT_TSF_MASK 0xFu
mbed_official 363:12a245e5c745 1269 #define FLEXIO_TIMSTAT_TSF_SHIFT 0
mbed_official 363:12a245e5c745 1270 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
mbed_official 363:12a245e5c745 1271 /* SHIFTSIEN Bit Fields */
mbed_official 363:12a245e5c745 1272 #define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
mbed_official 363:12a245e5c745 1273 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0
mbed_official 363:12a245e5c745 1274 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
mbed_official 363:12a245e5c745 1275 /* SHIFTEIEN Bit Fields */
mbed_official 363:12a245e5c745 1276 #define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
mbed_official 363:12a245e5c745 1277 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0
mbed_official 363:12a245e5c745 1278 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
mbed_official 363:12a245e5c745 1279 /* TIMIEN Bit Fields */
mbed_official 363:12a245e5c745 1280 #define FLEXIO_TIMIEN_TEIE_MASK 0xFu
mbed_official 363:12a245e5c745 1281 #define FLEXIO_TIMIEN_TEIE_SHIFT 0
mbed_official 363:12a245e5c745 1282 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
mbed_official 363:12a245e5c745 1283 /* SHIFTSDEN Bit Fields */
mbed_official 363:12a245e5c745 1284 #define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
mbed_official 363:12a245e5c745 1285 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0
mbed_official 363:12a245e5c745 1286 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
mbed_official 363:12a245e5c745 1287 /* SHIFTCTL Bit Fields */
mbed_official 363:12a245e5c745 1288 #define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
mbed_official 363:12a245e5c745 1289 #define FLEXIO_SHIFTCTL_SMOD_SHIFT 0
mbed_official 363:12a245e5c745 1290 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
mbed_official 363:12a245e5c745 1291 #define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
mbed_official 363:12a245e5c745 1292 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7
mbed_official 363:12a245e5c745 1293 #define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
mbed_official 363:12a245e5c745 1294 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8
mbed_official 363:12a245e5c745 1295 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
mbed_official 363:12a245e5c745 1296 #define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
mbed_official 363:12a245e5c745 1297 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16
mbed_official 363:12a245e5c745 1298 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
mbed_official 363:12a245e5c745 1299 #define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
mbed_official 363:12a245e5c745 1300 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23
mbed_official 363:12a245e5c745 1301 #define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
mbed_official 363:12a245e5c745 1302 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24
mbed_official 363:12a245e5c745 1303 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
mbed_official 363:12a245e5c745 1304 /* SHIFTCFG Bit Fields */
mbed_official 363:12a245e5c745 1305 #define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
mbed_official 363:12a245e5c745 1306 #define FLEXIO_SHIFTCFG_SSTART_SHIFT 0
mbed_official 363:12a245e5c745 1307 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
mbed_official 363:12a245e5c745 1308 #define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
mbed_official 363:12a245e5c745 1309 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4
mbed_official 363:12a245e5c745 1310 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
mbed_official 363:12a245e5c745 1311 #define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
mbed_official 363:12a245e5c745 1312 #define FLEXIO_SHIFTCFG_INSRC_SHIFT 8
mbed_official 363:12a245e5c745 1313 /* SHIFTBUF Bit Fields */
mbed_official 363:12a245e5c745 1314 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 1315 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0
mbed_official 363:12a245e5c745 1316 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
mbed_official 363:12a245e5c745 1317 /* SHIFTBUFBBS Bit Fields */
mbed_official 363:12a245e5c745 1318 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 1319 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0
mbed_official 363:12a245e5c745 1320 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
mbed_official 363:12a245e5c745 1321 /* SHIFTBUFBYS Bit Fields */
mbed_official 363:12a245e5c745 1322 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 1323 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0
mbed_official 363:12a245e5c745 1324 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
mbed_official 363:12a245e5c745 1325 /* SHIFTBUFBIS Bit Fields */
mbed_official 363:12a245e5c745 1326 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 1327 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0
mbed_official 363:12a245e5c745 1328 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
mbed_official 363:12a245e5c745 1329 /* TIMCTL Bit Fields */
mbed_official 363:12a245e5c745 1330 #define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
mbed_official 363:12a245e5c745 1331 #define FLEXIO_TIMCTL_TIMOD_SHIFT 0
mbed_official 363:12a245e5c745 1332 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
mbed_official 363:12a245e5c745 1333 #define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
mbed_official 363:12a245e5c745 1334 #define FLEXIO_TIMCTL_PINPOL_SHIFT 7
mbed_official 363:12a245e5c745 1335 #define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
mbed_official 363:12a245e5c745 1336 #define FLEXIO_TIMCTL_PINSEL_SHIFT 8
mbed_official 363:12a245e5c745 1337 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
mbed_official 363:12a245e5c745 1338 #define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
mbed_official 363:12a245e5c745 1339 #define FLEXIO_TIMCTL_PINCFG_SHIFT 16
mbed_official 363:12a245e5c745 1340 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
mbed_official 363:12a245e5c745 1341 #define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
mbed_official 363:12a245e5c745 1342 #define FLEXIO_TIMCTL_TRGSRC_SHIFT 22
mbed_official 363:12a245e5c745 1343 #define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
mbed_official 363:12a245e5c745 1344 #define FLEXIO_TIMCTL_TRGPOL_SHIFT 23
mbed_official 363:12a245e5c745 1345 #define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
mbed_official 363:12a245e5c745 1346 #define FLEXIO_TIMCTL_TRGSEL_SHIFT 24
mbed_official 363:12a245e5c745 1347 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
mbed_official 363:12a245e5c745 1348 /* TIMCFG Bit Fields */
mbed_official 363:12a245e5c745 1349 #define FLEXIO_TIMCFG_TSTART_MASK 0x2u
mbed_official 363:12a245e5c745 1350 #define FLEXIO_TIMCFG_TSTART_SHIFT 1
mbed_official 363:12a245e5c745 1351 #define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
mbed_official 363:12a245e5c745 1352 #define FLEXIO_TIMCFG_TSTOP_SHIFT 4
mbed_official 363:12a245e5c745 1353 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
mbed_official 363:12a245e5c745 1354 #define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
mbed_official 363:12a245e5c745 1355 #define FLEXIO_TIMCFG_TIMENA_SHIFT 8
mbed_official 363:12a245e5c745 1356 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
mbed_official 363:12a245e5c745 1357 #define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
mbed_official 363:12a245e5c745 1358 #define FLEXIO_TIMCFG_TIMDIS_SHIFT 12
mbed_official 363:12a245e5c745 1359 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
mbed_official 363:12a245e5c745 1360 #define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
mbed_official 363:12a245e5c745 1361 #define FLEXIO_TIMCFG_TIMRST_SHIFT 16
mbed_official 363:12a245e5c745 1362 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
mbed_official 363:12a245e5c745 1363 #define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
mbed_official 363:12a245e5c745 1364 #define FLEXIO_TIMCFG_TIMDEC_SHIFT 20
mbed_official 363:12a245e5c745 1365 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
mbed_official 363:12a245e5c745 1366 #define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
mbed_official 363:12a245e5c745 1367 #define FLEXIO_TIMCFG_TIMOUT_SHIFT 24
mbed_official 363:12a245e5c745 1368 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
mbed_official 363:12a245e5c745 1369 /* TIMCMP Bit Fields */
mbed_official 363:12a245e5c745 1370 #define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
mbed_official 363:12a245e5c745 1371 #define FLEXIO_TIMCMP_CMP_SHIFT 0
mbed_official 363:12a245e5c745 1372 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
mbed_official 363:12a245e5c745 1373
mbed_official 363:12a245e5c745 1374 /*!
mbed_official 363:12a245e5c745 1375 * @}
mbed_official 363:12a245e5c745 1376 */ /* end of group FLEXIO_Register_Masks */
mbed_official 363:12a245e5c745 1377
mbed_official 363:12a245e5c745 1378
mbed_official 363:12a245e5c745 1379 /* FLEXIO - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 1380 /** Peripheral FLEXIO base address */
mbed_official 363:12a245e5c745 1381 #define FLEXIO_BASE (0x4005F000u)
mbed_official 363:12a245e5c745 1382 /** Peripheral FLEXIO base pointer */
mbed_official 363:12a245e5c745 1383 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
mbed_official 363:12a245e5c745 1384 #define FLEXIO_BASE_PTR (FLEXIO)
mbed_official 363:12a245e5c745 1385 /** Array initializer of FLEXIO peripheral base addresses */
mbed_official 363:12a245e5c745 1386 #define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
mbed_official 363:12a245e5c745 1387 /** Array initializer of FLEXIO peripheral base pointers */
mbed_official 363:12a245e5c745 1388 #define FLEXIO_BASE_PTRS { FLEXIO }
mbed_official 363:12a245e5c745 1389
mbed_official 363:12a245e5c745 1390 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1391 -- FLEXIO - Register accessor macros
mbed_official 363:12a245e5c745 1392 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1393
mbed_official 363:12a245e5c745 1394 /*!
mbed_official 363:12a245e5c745 1395 * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
mbed_official 363:12a245e5c745 1396 * @{
mbed_official 363:12a245e5c745 1397 */
mbed_official 363:12a245e5c745 1398
mbed_official 363:12a245e5c745 1399
mbed_official 363:12a245e5c745 1400 /* FLEXIO - Register instance definitions */
mbed_official 363:12a245e5c745 1401 /* FLEXIO */
mbed_official 363:12a245e5c745 1402 #define FLEXIO_VERID FLEXIO_VERID_REG(FLEXIO)
mbed_official 363:12a245e5c745 1403 #define FLEXIO_PARAM FLEXIO_PARAM_REG(FLEXIO)
mbed_official 363:12a245e5c745 1404 #define FLEXIO_CTRL FLEXIO_CTRL_REG(FLEXIO)
mbed_official 363:12a245e5c745 1405 #define FLEXIO_SHIFTSTAT FLEXIO_SHIFTSTAT_REG(FLEXIO)
mbed_official 363:12a245e5c745 1406 #define FLEXIO_SHIFTERR FLEXIO_SHIFTERR_REG(FLEXIO)
mbed_official 363:12a245e5c745 1407 #define FLEXIO_TIMSTAT FLEXIO_TIMSTAT_REG(FLEXIO)
mbed_official 363:12a245e5c745 1408 #define FLEXIO_SHIFTSIEN FLEXIO_SHIFTSIEN_REG(FLEXIO)
mbed_official 363:12a245e5c745 1409 #define FLEXIO_SHIFTEIEN FLEXIO_SHIFTEIEN_REG(FLEXIO)
mbed_official 363:12a245e5c745 1410 #define FLEXIO_TIMIEN FLEXIO_TIMIEN_REG(FLEXIO)
mbed_official 363:12a245e5c745 1411 #define FLEXIO_SHIFTSDEN FLEXIO_SHIFTSDEN_REG(FLEXIO)
mbed_official 363:12a245e5c745 1412 #define FLEXIO_SHIFTCTL0 FLEXIO_SHIFTCTL_REG(FLEXIO,0)
mbed_official 363:12a245e5c745 1413 #define FLEXIO_SHIFTCTL1 FLEXIO_SHIFTCTL_REG(FLEXIO,1)
mbed_official 363:12a245e5c745 1414 #define FLEXIO_SHIFTCTL2 FLEXIO_SHIFTCTL_REG(FLEXIO,2)
mbed_official 363:12a245e5c745 1415 #define FLEXIO_SHIFTCTL3 FLEXIO_SHIFTCTL_REG(FLEXIO,3)
mbed_official 363:12a245e5c745 1416 #define FLEXIO_SHIFTCFG0 FLEXIO_SHIFTCFG_REG(FLEXIO,0)
mbed_official 363:12a245e5c745 1417 #define FLEXIO_SHIFTCFG1 FLEXIO_SHIFTCFG_REG(FLEXIO,1)
mbed_official 363:12a245e5c745 1418 #define FLEXIO_SHIFTCFG2 FLEXIO_SHIFTCFG_REG(FLEXIO,2)
mbed_official 363:12a245e5c745 1419 #define FLEXIO_SHIFTCFG3 FLEXIO_SHIFTCFG_REG(FLEXIO,3)
mbed_official 363:12a245e5c745 1420 #define FLEXIO_SHIFTBUF0 FLEXIO_SHIFTBUF_REG(FLEXIO,0)
mbed_official 363:12a245e5c745 1421 #define FLEXIO_SHIFTBUF1 FLEXIO_SHIFTBUF_REG(FLEXIO,1)
mbed_official 363:12a245e5c745 1422 #define FLEXIO_SHIFTBUF2 FLEXIO_SHIFTBUF_REG(FLEXIO,2)
mbed_official 363:12a245e5c745 1423 #define FLEXIO_SHIFTBUF3 FLEXIO_SHIFTBUF_REG(FLEXIO,3)
mbed_official 363:12a245e5c745 1424 #define FLEXIO_SHIFTBUFBBS0 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,0)
mbed_official 363:12a245e5c745 1425 #define FLEXIO_SHIFTBUFBBS1 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,1)
mbed_official 363:12a245e5c745 1426 #define FLEXIO_SHIFTBUFBBS2 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,2)
mbed_official 363:12a245e5c745 1427 #define FLEXIO_SHIFTBUFBBS3 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,3)
mbed_official 363:12a245e5c745 1428 #define FLEXIO_SHIFTBUFBYS0 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,0)
mbed_official 363:12a245e5c745 1429 #define FLEXIO_SHIFTBUFBYS1 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,1)
mbed_official 363:12a245e5c745 1430 #define FLEXIO_SHIFTBUFBYS2 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,2)
mbed_official 363:12a245e5c745 1431 #define FLEXIO_SHIFTBUFBYS3 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,3)
mbed_official 363:12a245e5c745 1432 #define FLEXIO_SHIFTBUFBIS0 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,0)
mbed_official 363:12a245e5c745 1433 #define FLEXIO_SHIFTBUFBIS1 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,1)
mbed_official 363:12a245e5c745 1434 #define FLEXIO_SHIFTBUFBIS2 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,2)
mbed_official 363:12a245e5c745 1435 #define FLEXIO_SHIFTBUFBIS3 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,3)
mbed_official 363:12a245e5c745 1436 #define FLEXIO_TIMCTL0 FLEXIO_TIMCTL_REG(FLEXIO,0)
mbed_official 363:12a245e5c745 1437 #define FLEXIO_TIMCTL1 FLEXIO_TIMCTL_REG(FLEXIO,1)
mbed_official 363:12a245e5c745 1438 #define FLEXIO_TIMCTL2 FLEXIO_TIMCTL_REG(FLEXIO,2)
mbed_official 363:12a245e5c745 1439 #define FLEXIO_TIMCTL3 FLEXIO_TIMCTL_REG(FLEXIO,3)
mbed_official 363:12a245e5c745 1440 #define FLEXIO_TIMCFG0 FLEXIO_TIMCFG_REG(FLEXIO,0)
mbed_official 363:12a245e5c745 1441 #define FLEXIO_TIMCFG1 FLEXIO_TIMCFG_REG(FLEXIO,1)
mbed_official 363:12a245e5c745 1442 #define FLEXIO_TIMCFG2 FLEXIO_TIMCFG_REG(FLEXIO,2)
mbed_official 363:12a245e5c745 1443 #define FLEXIO_TIMCFG3 FLEXIO_TIMCFG_REG(FLEXIO,3)
mbed_official 363:12a245e5c745 1444 #define FLEXIO_TIMCMP0 FLEXIO_TIMCMP_REG(FLEXIO,0)
mbed_official 363:12a245e5c745 1445 #define FLEXIO_TIMCMP1 FLEXIO_TIMCMP_REG(FLEXIO,1)
mbed_official 363:12a245e5c745 1446 #define FLEXIO_TIMCMP2 FLEXIO_TIMCMP_REG(FLEXIO,2)
mbed_official 363:12a245e5c745 1447 #define FLEXIO_TIMCMP3 FLEXIO_TIMCMP_REG(FLEXIO,3)
mbed_official 363:12a245e5c745 1448
mbed_official 363:12a245e5c745 1449 /* FLEXIO - Register array accessors */
mbed_official 363:12a245e5c745 1450 #define FLEXIO_SHIFTCTL(index) FLEXIO_SHIFTCTL_REG(FLEXIO,index)
mbed_official 363:12a245e5c745 1451 #define FLEXIO_SHIFTCFG(index) FLEXIO_SHIFTCFG_REG(FLEXIO,index)
mbed_official 363:12a245e5c745 1452 #define FLEXIO_SHIFTBUF(index) FLEXIO_SHIFTBUF_REG(FLEXIO,index)
mbed_official 363:12a245e5c745 1453 #define FLEXIO_SHIFTBUFBBS(index) FLEXIO_SHIFTBUFBBS_REG(FLEXIO,index)
mbed_official 363:12a245e5c745 1454 #define FLEXIO_SHIFTBUFBYS(index) FLEXIO_SHIFTBUFBYS_REG(FLEXIO,index)
mbed_official 363:12a245e5c745 1455 #define FLEXIO_SHIFTBUFBIS(index) FLEXIO_SHIFTBUFBIS_REG(FLEXIO,index)
mbed_official 363:12a245e5c745 1456 #define FLEXIO_TIMCTL(index) FLEXIO_TIMCTL_REG(FLEXIO,index)
mbed_official 363:12a245e5c745 1457 #define FLEXIO_TIMCFG(index) FLEXIO_TIMCFG_REG(FLEXIO,index)
mbed_official 363:12a245e5c745 1458 #define FLEXIO_TIMCMP(index) FLEXIO_TIMCMP_REG(FLEXIO,index)
mbed_official 363:12a245e5c745 1459
mbed_official 363:12a245e5c745 1460 /*!
mbed_official 363:12a245e5c745 1461 * @}
mbed_official 363:12a245e5c745 1462 */ /* end of group FLEXIO_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 1463
mbed_official 363:12a245e5c745 1464
mbed_official 363:12a245e5c745 1465 /*!
mbed_official 363:12a245e5c745 1466 * @}
mbed_official 363:12a245e5c745 1467 */ /* end of group FLEXIO_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 1468
mbed_official 363:12a245e5c745 1469
mbed_official 363:12a245e5c745 1470 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1471 -- FTFA Peripheral Access Layer
mbed_official 363:12a245e5c745 1472 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1473
mbed_official 363:12a245e5c745 1474 /*!
mbed_official 363:12a245e5c745 1475 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
mbed_official 363:12a245e5c745 1476 * @{
mbed_official 363:12a245e5c745 1477 */
mbed_official 363:12a245e5c745 1478
mbed_official 363:12a245e5c745 1479 /** FTFA - Register Layout Typedef */
mbed_official 363:12a245e5c745 1480 typedef struct {
mbed_official 363:12a245e5c745 1481 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
mbed_official 363:12a245e5c745 1482 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
mbed_official 363:12a245e5c745 1483 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
mbed_official 363:12a245e5c745 1484 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
mbed_official 363:12a245e5c745 1485 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
mbed_official 363:12a245e5c745 1486 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
mbed_official 363:12a245e5c745 1487 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
mbed_official 363:12a245e5c745 1488 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
mbed_official 363:12a245e5c745 1489 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
mbed_official 363:12a245e5c745 1490 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
mbed_official 363:12a245e5c745 1491 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
mbed_official 363:12a245e5c745 1492 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
mbed_official 363:12a245e5c745 1493 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
mbed_official 363:12a245e5c745 1494 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
mbed_official 363:12a245e5c745 1495 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
mbed_official 363:12a245e5c745 1496 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
mbed_official 363:12a245e5c745 1497 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
mbed_official 363:12a245e5c745 1498 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
mbed_official 363:12a245e5c745 1499 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
mbed_official 363:12a245e5c745 1500 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
mbed_official 363:12a245e5c745 1501 } FTFA_Type, *FTFA_MemMapPtr;
mbed_official 363:12a245e5c745 1502
mbed_official 363:12a245e5c745 1503 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1504 -- FTFA - Register accessor macros
mbed_official 363:12a245e5c745 1505 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1506
mbed_official 363:12a245e5c745 1507 /*!
mbed_official 363:12a245e5c745 1508 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
mbed_official 363:12a245e5c745 1509 * @{
mbed_official 363:12a245e5c745 1510 */
mbed_official 363:12a245e5c745 1511
mbed_official 363:12a245e5c745 1512
mbed_official 363:12a245e5c745 1513 /* FTFA - Register accessors */
mbed_official 363:12a245e5c745 1514 #define FTFA_FSTAT_REG(base) ((base)->FSTAT)
mbed_official 363:12a245e5c745 1515 #define FTFA_FCNFG_REG(base) ((base)->FCNFG)
mbed_official 363:12a245e5c745 1516 #define FTFA_FSEC_REG(base) ((base)->FSEC)
mbed_official 363:12a245e5c745 1517 #define FTFA_FOPT_REG(base) ((base)->FOPT)
mbed_official 363:12a245e5c745 1518 #define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
mbed_official 363:12a245e5c745 1519 #define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
mbed_official 363:12a245e5c745 1520 #define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
mbed_official 363:12a245e5c745 1521 #define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
mbed_official 363:12a245e5c745 1522 #define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
mbed_official 363:12a245e5c745 1523 #define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
mbed_official 363:12a245e5c745 1524 #define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
mbed_official 363:12a245e5c745 1525 #define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
mbed_official 363:12a245e5c745 1526 #define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
mbed_official 363:12a245e5c745 1527 #define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
mbed_official 363:12a245e5c745 1528 #define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
mbed_official 363:12a245e5c745 1529 #define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
mbed_official 363:12a245e5c745 1530 #define FTFA_FPROT3_REG(base) ((base)->FPROT3)
mbed_official 363:12a245e5c745 1531 #define FTFA_FPROT2_REG(base) ((base)->FPROT2)
mbed_official 363:12a245e5c745 1532 #define FTFA_FPROT1_REG(base) ((base)->FPROT1)
mbed_official 363:12a245e5c745 1533 #define FTFA_FPROT0_REG(base) ((base)->FPROT0)
mbed_official 363:12a245e5c745 1534
mbed_official 363:12a245e5c745 1535 /*!
mbed_official 363:12a245e5c745 1536 * @}
mbed_official 363:12a245e5c745 1537 */ /* end of group FTFA_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 1538
mbed_official 363:12a245e5c745 1539
mbed_official 363:12a245e5c745 1540 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1541 -- FTFA Register Masks
mbed_official 363:12a245e5c745 1542 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1543
mbed_official 363:12a245e5c745 1544 /*!
mbed_official 363:12a245e5c745 1545 * @addtogroup FTFA_Register_Masks FTFA Register Masks
mbed_official 363:12a245e5c745 1546 * @{
mbed_official 363:12a245e5c745 1547 */
mbed_official 363:12a245e5c745 1548
mbed_official 363:12a245e5c745 1549 /* FSTAT Bit Fields */
mbed_official 363:12a245e5c745 1550 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
mbed_official 363:12a245e5c745 1551 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
mbed_official 363:12a245e5c745 1552 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
mbed_official 363:12a245e5c745 1553 #define FTFA_FSTAT_FPVIOL_SHIFT 4
mbed_official 363:12a245e5c745 1554 #define FTFA_FSTAT_ACCERR_MASK 0x20u
mbed_official 363:12a245e5c745 1555 #define FTFA_FSTAT_ACCERR_SHIFT 5
mbed_official 363:12a245e5c745 1556 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
mbed_official 363:12a245e5c745 1557 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
mbed_official 363:12a245e5c745 1558 #define FTFA_FSTAT_CCIF_MASK 0x80u
mbed_official 363:12a245e5c745 1559 #define FTFA_FSTAT_CCIF_SHIFT 7
mbed_official 363:12a245e5c745 1560 /* FCNFG Bit Fields */
mbed_official 363:12a245e5c745 1561 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
mbed_official 363:12a245e5c745 1562 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
mbed_official 363:12a245e5c745 1563 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
mbed_official 363:12a245e5c745 1564 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
mbed_official 363:12a245e5c745 1565 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
mbed_official 363:12a245e5c745 1566 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
mbed_official 363:12a245e5c745 1567 #define FTFA_FCNFG_CCIE_MASK 0x80u
mbed_official 363:12a245e5c745 1568 #define FTFA_FCNFG_CCIE_SHIFT 7
mbed_official 363:12a245e5c745 1569 /* FSEC Bit Fields */
mbed_official 363:12a245e5c745 1570 #define FTFA_FSEC_SEC_MASK 0x3u
mbed_official 363:12a245e5c745 1571 #define FTFA_FSEC_SEC_SHIFT 0
mbed_official 363:12a245e5c745 1572 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
mbed_official 363:12a245e5c745 1573 #define FTFA_FSEC_FSLACC_MASK 0xCu
mbed_official 363:12a245e5c745 1574 #define FTFA_FSEC_FSLACC_SHIFT 2
mbed_official 363:12a245e5c745 1575 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
mbed_official 363:12a245e5c745 1576 #define FTFA_FSEC_MEEN_MASK 0x30u
mbed_official 363:12a245e5c745 1577 #define FTFA_FSEC_MEEN_SHIFT 4
mbed_official 363:12a245e5c745 1578 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
mbed_official 363:12a245e5c745 1579 #define FTFA_FSEC_KEYEN_MASK 0xC0u
mbed_official 363:12a245e5c745 1580 #define FTFA_FSEC_KEYEN_SHIFT 6
mbed_official 363:12a245e5c745 1581 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
mbed_official 363:12a245e5c745 1582 /* FOPT Bit Fields */
mbed_official 363:12a245e5c745 1583 #define FTFA_FOPT_OPT_MASK 0xFFu
mbed_official 363:12a245e5c745 1584 #define FTFA_FOPT_OPT_SHIFT 0
mbed_official 363:12a245e5c745 1585 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
mbed_official 363:12a245e5c745 1586 /* FCCOB3 Bit Fields */
mbed_official 363:12a245e5c745 1587 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1588 #define FTFA_FCCOB3_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1589 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
mbed_official 363:12a245e5c745 1590 /* FCCOB2 Bit Fields */
mbed_official 363:12a245e5c745 1591 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1592 #define FTFA_FCCOB2_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1593 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
mbed_official 363:12a245e5c745 1594 /* FCCOB1 Bit Fields */
mbed_official 363:12a245e5c745 1595 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1596 #define FTFA_FCCOB1_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1597 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
mbed_official 363:12a245e5c745 1598 /* FCCOB0 Bit Fields */
mbed_official 363:12a245e5c745 1599 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1600 #define FTFA_FCCOB0_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1601 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
mbed_official 363:12a245e5c745 1602 /* FCCOB7 Bit Fields */
mbed_official 363:12a245e5c745 1603 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1604 #define FTFA_FCCOB7_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1605 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
mbed_official 363:12a245e5c745 1606 /* FCCOB6 Bit Fields */
mbed_official 363:12a245e5c745 1607 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1608 #define FTFA_FCCOB6_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1609 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
mbed_official 363:12a245e5c745 1610 /* FCCOB5 Bit Fields */
mbed_official 363:12a245e5c745 1611 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1612 #define FTFA_FCCOB5_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1613 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
mbed_official 363:12a245e5c745 1614 /* FCCOB4 Bit Fields */
mbed_official 363:12a245e5c745 1615 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1616 #define FTFA_FCCOB4_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1617 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
mbed_official 363:12a245e5c745 1618 /* FCCOBB Bit Fields */
mbed_official 363:12a245e5c745 1619 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1620 #define FTFA_FCCOBB_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1621 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
mbed_official 363:12a245e5c745 1622 /* FCCOBA Bit Fields */
mbed_official 363:12a245e5c745 1623 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1624 #define FTFA_FCCOBA_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1625 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
mbed_official 363:12a245e5c745 1626 /* FCCOB9 Bit Fields */
mbed_official 363:12a245e5c745 1627 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1628 #define FTFA_FCCOB9_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1629 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
mbed_official 363:12a245e5c745 1630 /* FCCOB8 Bit Fields */
mbed_official 363:12a245e5c745 1631 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
mbed_official 363:12a245e5c745 1632 #define FTFA_FCCOB8_CCOBn_SHIFT 0
mbed_official 363:12a245e5c745 1633 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
mbed_official 363:12a245e5c745 1634 /* FPROT3 Bit Fields */
mbed_official 363:12a245e5c745 1635 #define FTFA_FPROT3_PROT_MASK 0xFFu
mbed_official 363:12a245e5c745 1636 #define FTFA_FPROT3_PROT_SHIFT 0
mbed_official 363:12a245e5c745 1637 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
mbed_official 363:12a245e5c745 1638 /* FPROT2 Bit Fields */
mbed_official 363:12a245e5c745 1639 #define FTFA_FPROT2_PROT_MASK 0xFFu
mbed_official 363:12a245e5c745 1640 #define FTFA_FPROT2_PROT_SHIFT 0
mbed_official 363:12a245e5c745 1641 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
mbed_official 363:12a245e5c745 1642 /* FPROT1 Bit Fields */
mbed_official 363:12a245e5c745 1643 #define FTFA_FPROT1_PROT_MASK 0xFFu
mbed_official 363:12a245e5c745 1644 #define FTFA_FPROT1_PROT_SHIFT 0
mbed_official 363:12a245e5c745 1645 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
mbed_official 363:12a245e5c745 1646 /* FPROT0 Bit Fields */
mbed_official 363:12a245e5c745 1647 #define FTFA_FPROT0_PROT_MASK 0xFFu
mbed_official 363:12a245e5c745 1648 #define FTFA_FPROT0_PROT_SHIFT 0
mbed_official 363:12a245e5c745 1649 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
mbed_official 363:12a245e5c745 1650
mbed_official 363:12a245e5c745 1651 /*!
mbed_official 363:12a245e5c745 1652 * @}
mbed_official 363:12a245e5c745 1653 */ /* end of group FTFA_Register_Masks */
mbed_official 363:12a245e5c745 1654
mbed_official 363:12a245e5c745 1655
mbed_official 363:12a245e5c745 1656 /* FTFA - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 1657 /** Peripheral FTFA base address */
mbed_official 363:12a245e5c745 1658 #define FTFA_BASE (0x40020000u)
mbed_official 363:12a245e5c745 1659 /** Peripheral FTFA base pointer */
mbed_official 363:12a245e5c745 1660 #define FTFA ((FTFA_Type *)FTFA_BASE)
mbed_official 363:12a245e5c745 1661 #define FTFA_BASE_PTR (FTFA)
mbed_official 363:12a245e5c745 1662 /** Array initializer of FTFA peripheral base addresses */
mbed_official 363:12a245e5c745 1663 #define FTFA_BASE_ADDRS { FTFA_BASE }
mbed_official 363:12a245e5c745 1664 /** Array initializer of FTFA peripheral base pointers */
mbed_official 363:12a245e5c745 1665 #define FTFA_BASE_PTRS { FTFA }
mbed_official 363:12a245e5c745 1666 /** Interrupt vectors for the FTFA peripheral type */
mbed_official 363:12a245e5c745 1667 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
mbed_official 363:12a245e5c745 1668
mbed_official 363:12a245e5c745 1669 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1670 -- FTFA - Register accessor macros
mbed_official 363:12a245e5c745 1671 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1672
mbed_official 363:12a245e5c745 1673 /*!
mbed_official 363:12a245e5c745 1674 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
mbed_official 363:12a245e5c745 1675 * @{
mbed_official 363:12a245e5c745 1676 */
mbed_official 363:12a245e5c745 1677
mbed_official 363:12a245e5c745 1678
mbed_official 363:12a245e5c745 1679 /* FTFA - Register instance definitions */
mbed_official 363:12a245e5c745 1680 /* FTFA */
mbed_official 363:12a245e5c745 1681 #define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
mbed_official 363:12a245e5c745 1682 #define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
mbed_official 363:12a245e5c745 1683 #define FTFA_FSEC FTFA_FSEC_REG(FTFA)
mbed_official 363:12a245e5c745 1684 #define FTFA_FOPT FTFA_FOPT_REG(FTFA)
mbed_official 363:12a245e5c745 1685 #define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
mbed_official 363:12a245e5c745 1686 #define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
mbed_official 363:12a245e5c745 1687 #define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
mbed_official 363:12a245e5c745 1688 #define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
mbed_official 363:12a245e5c745 1689 #define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
mbed_official 363:12a245e5c745 1690 #define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
mbed_official 363:12a245e5c745 1691 #define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
mbed_official 363:12a245e5c745 1692 #define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
mbed_official 363:12a245e5c745 1693 #define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
mbed_official 363:12a245e5c745 1694 #define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
mbed_official 363:12a245e5c745 1695 #define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
mbed_official 363:12a245e5c745 1696 #define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
mbed_official 363:12a245e5c745 1697 #define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
mbed_official 363:12a245e5c745 1698 #define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
mbed_official 363:12a245e5c745 1699 #define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
mbed_official 363:12a245e5c745 1700 #define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
mbed_official 363:12a245e5c745 1701
mbed_official 363:12a245e5c745 1702 /*!
mbed_official 363:12a245e5c745 1703 * @}
mbed_official 363:12a245e5c745 1704 */ /* end of group FTFA_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 1705
mbed_official 363:12a245e5c745 1706
mbed_official 363:12a245e5c745 1707 /*!
mbed_official 363:12a245e5c745 1708 * @}
mbed_official 363:12a245e5c745 1709 */ /* end of group FTFA_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 1710
mbed_official 363:12a245e5c745 1711
mbed_official 363:12a245e5c745 1712 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1713 -- GPIO Peripheral Access Layer
mbed_official 363:12a245e5c745 1714 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1715
mbed_official 363:12a245e5c745 1716 /*!
mbed_official 363:12a245e5c745 1717 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
mbed_official 363:12a245e5c745 1718 * @{
mbed_official 363:12a245e5c745 1719 */
mbed_official 363:12a245e5c745 1720
mbed_official 363:12a245e5c745 1721 /** GPIO - Register Layout Typedef */
mbed_official 363:12a245e5c745 1722 typedef struct {
mbed_official 363:12a245e5c745 1723 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
mbed_official 363:12a245e5c745 1724 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
mbed_official 363:12a245e5c745 1725 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
mbed_official 363:12a245e5c745 1726 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
mbed_official 363:12a245e5c745 1727 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
mbed_official 363:12a245e5c745 1728 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
mbed_official 363:12a245e5c745 1729 } GPIO_Type, *GPIO_MemMapPtr;
mbed_official 363:12a245e5c745 1730
mbed_official 363:12a245e5c745 1731 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1732 -- GPIO - Register accessor macros
mbed_official 363:12a245e5c745 1733 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1734
mbed_official 363:12a245e5c745 1735 /*!
mbed_official 363:12a245e5c745 1736 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
mbed_official 363:12a245e5c745 1737 * @{
mbed_official 363:12a245e5c745 1738 */
mbed_official 363:12a245e5c745 1739
mbed_official 363:12a245e5c745 1740
mbed_official 363:12a245e5c745 1741 /* GPIO - Register accessors */
mbed_official 363:12a245e5c745 1742 #define GPIO_PDOR_REG(base) ((base)->PDOR)
mbed_official 363:12a245e5c745 1743 #define GPIO_PSOR_REG(base) ((base)->PSOR)
mbed_official 363:12a245e5c745 1744 #define GPIO_PCOR_REG(base) ((base)->PCOR)
mbed_official 363:12a245e5c745 1745 #define GPIO_PTOR_REG(base) ((base)->PTOR)
mbed_official 363:12a245e5c745 1746 #define GPIO_PDIR_REG(base) ((base)->PDIR)
mbed_official 363:12a245e5c745 1747 #define GPIO_PDDR_REG(base) ((base)->PDDR)
mbed_official 363:12a245e5c745 1748
mbed_official 363:12a245e5c745 1749 /*!
mbed_official 363:12a245e5c745 1750 * @}
mbed_official 363:12a245e5c745 1751 */ /* end of group GPIO_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 1752
mbed_official 363:12a245e5c745 1753
mbed_official 363:12a245e5c745 1754 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1755 -- GPIO Register Masks
mbed_official 363:12a245e5c745 1756 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1757
mbed_official 363:12a245e5c745 1758 /*!
mbed_official 363:12a245e5c745 1759 * @addtogroup GPIO_Register_Masks GPIO Register Masks
mbed_official 363:12a245e5c745 1760 * @{
mbed_official 363:12a245e5c745 1761 */
mbed_official 363:12a245e5c745 1762
mbed_official 363:12a245e5c745 1763 /* PDOR Bit Fields */
mbed_official 363:12a245e5c745 1764 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 1765 #define GPIO_PDOR_PDO_SHIFT 0
mbed_official 363:12a245e5c745 1766 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
mbed_official 363:12a245e5c745 1767 /* PSOR Bit Fields */
mbed_official 363:12a245e5c745 1768 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 1769 #define GPIO_PSOR_PTSO_SHIFT 0
mbed_official 363:12a245e5c745 1770 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
mbed_official 363:12a245e5c745 1771 /* PCOR Bit Fields */
mbed_official 363:12a245e5c745 1772 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 1773 #define GPIO_PCOR_PTCO_SHIFT 0
mbed_official 363:12a245e5c745 1774 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
mbed_official 363:12a245e5c745 1775 /* PTOR Bit Fields */
mbed_official 363:12a245e5c745 1776 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 1777 #define GPIO_PTOR_PTTO_SHIFT 0
mbed_official 363:12a245e5c745 1778 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
mbed_official 363:12a245e5c745 1779 /* PDIR Bit Fields */
mbed_official 363:12a245e5c745 1780 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 1781 #define GPIO_PDIR_PDI_SHIFT 0
mbed_official 363:12a245e5c745 1782 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
mbed_official 363:12a245e5c745 1783 /* PDDR Bit Fields */
mbed_official 363:12a245e5c745 1784 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 1785 #define GPIO_PDDR_PDD_SHIFT 0
mbed_official 363:12a245e5c745 1786 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
mbed_official 363:12a245e5c745 1787
mbed_official 363:12a245e5c745 1788 /*!
mbed_official 363:12a245e5c745 1789 * @}
mbed_official 363:12a245e5c745 1790 */ /* end of group GPIO_Register_Masks */
mbed_official 363:12a245e5c745 1791
mbed_official 363:12a245e5c745 1792
mbed_official 363:12a245e5c745 1793 /* GPIO - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 1794 /** Peripheral GPIOA base address */
mbed_official 363:12a245e5c745 1795 #define GPIOA_BASE (0x400FF000u)
mbed_official 363:12a245e5c745 1796 /** Peripheral GPIOA base pointer */
mbed_official 363:12a245e5c745 1797 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
mbed_official 363:12a245e5c745 1798 #define GPIOA_BASE_PTR (GPIOA)
mbed_official 363:12a245e5c745 1799 /** Peripheral GPIOB base address */
mbed_official 363:12a245e5c745 1800 #define GPIOB_BASE (0x400FF040u)
mbed_official 363:12a245e5c745 1801 /** Peripheral GPIOB base pointer */
mbed_official 363:12a245e5c745 1802 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
mbed_official 363:12a245e5c745 1803 #define GPIOB_BASE_PTR (GPIOB)
mbed_official 363:12a245e5c745 1804 /** Peripheral GPIOC base address */
mbed_official 363:12a245e5c745 1805 #define GPIOC_BASE (0x400FF080u)
mbed_official 363:12a245e5c745 1806 /** Peripheral GPIOC base pointer */
mbed_official 363:12a245e5c745 1807 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
mbed_official 363:12a245e5c745 1808 #define GPIOC_BASE_PTR (GPIOC)
mbed_official 363:12a245e5c745 1809 /** Peripheral GPIOD base address */
mbed_official 363:12a245e5c745 1810 #define GPIOD_BASE (0x400FF0C0u)
mbed_official 363:12a245e5c745 1811 /** Peripheral GPIOD base pointer */
mbed_official 363:12a245e5c745 1812 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
mbed_official 363:12a245e5c745 1813 #define GPIOD_BASE_PTR (GPIOD)
mbed_official 363:12a245e5c745 1814 /** Peripheral GPIOE base address */
mbed_official 363:12a245e5c745 1815 #define GPIOE_BASE (0x400FF100u)
mbed_official 363:12a245e5c745 1816 /** Peripheral GPIOE base pointer */
mbed_official 363:12a245e5c745 1817 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
mbed_official 363:12a245e5c745 1818 #define GPIOE_BASE_PTR (GPIOE)
mbed_official 363:12a245e5c745 1819 /** Array initializer of GPIO peripheral base addresses */
mbed_official 363:12a245e5c745 1820 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
mbed_official 363:12a245e5c745 1821 /** Array initializer of GPIO peripheral base pointers */
mbed_official 363:12a245e5c745 1822 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
mbed_official 363:12a245e5c745 1823
mbed_official 363:12a245e5c745 1824 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1825 -- GPIO - Register accessor macros
mbed_official 363:12a245e5c745 1826 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1827
mbed_official 363:12a245e5c745 1828 /*!
mbed_official 363:12a245e5c745 1829 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
mbed_official 363:12a245e5c745 1830 * @{
mbed_official 363:12a245e5c745 1831 */
mbed_official 363:12a245e5c745 1832
mbed_official 363:12a245e5c745 1833
mbed_official 363:12a245e5c745 1834 /* GPIO - Register instance definitions */
mbed_official 363:12a245e5c745 1835 /* GPIOA */
mbed_official 363:12a245e5c745 1836 #define GPIOA_PDOR GPIO_PDOR_REG(GPIOA)
mbed_official 363:12a245e5c745 1837 #define GPIOA_PSOR GPIO_PSOR_REG(GPIOA)
mbed_official 363:12a245e5c745 1838 #define GPIOA_PCOR GPIO_PCOR_REG(GPIOA)
mbed_official 363:12a245e5c745 1839 #define GPIOA_PTOR GPIO_PTOR_REG(GPIOA)
mbed_official 363:12a245e5c745 1840 #define GPIOA_PDIR GPIO_PDIR_REG(GPIOA)
mbed_official 363:12a245e5c745 1841 #define GPIOA_PDDR GPIO_PDDR_REG(GPIOA)
mbed_official 363:12a245e5c745 1842 /* GPIOB */
mbed_official 363:12a245e5c745 1843 #define GPIOB_PDOR GPIO_PDOR_REG(GPIOB)
mbed_official 363:12a245e5c745 1844 #define GPIOB_PSOR GPIO_PSOR_REG(GPIOB)
mbed_official 363:12a245e5c745 1845 #define GPIOB_PCOR GPIO_PCOR_REG(GPIOB)
mbed_official 363:12a245e5c745 1846 #define GPIOB_PTOR GPIO_PTOR_REG(GPIOB)
mbed_official 363:12a245e5c745 1847 #define GPIOB_PDIR GPIO_PDIR_REG(GPIOB)
mbed_official 363:12a245e5c745 1848 #define GPIOB_PDDR GPIO_PDDR_REG(GPIOB)
mbed_official 363:12a245e5c745 1849 /* GPIOC */
mbed_official 363:12a245e5c745 1850 #define GPIOC_PDOR GPIO_PDOR_REG(GPIOC)
mbed_official 363:12a245e5c745 1851 #define GPIOC_PSOR GPIO_PSOR_REG(GPIOC)
mbed_official 363:12a245e5c745 1852 #define GPIOC_PCOR GPIO_PCOR_REG(GPIOC)
mbed_official 363:12a245e5c745 1853 #define GPIOC_PTOR GPIO_PTOR_REG(GPIOC)
mbed_official 363:12a245e5c745 1854 #define GPIOC_PDIR GPIO_PDIR_REG(GPIOC)
mbed_official 363:12a245e5c745 1855 #define GPIOC_PDDR GPIO_PDDR_REG(GPIOC)
mbed_official 363:12a245e5c745 1856 /* GPIOD */
mbed_official 363:12a245e5c745 1857 #define GPIOD_PDOR GPIO_PDOR_REG(GPIOD)
mbed_official 363:12a245e5c745 1858 #define GPIOD_PSOR GPIO_PSOR_REG(GPIOD)
mbed_official 363:12a245e5c745 1859 #define GPIOD_PCOR GPIO_PCOR_REG(GPIOD)
mbed_official 363:12a245e5c745 1860 #define GPIOD_PTOR GPIO_PTOR_REG(GPIOD)
mbed_official 363:12a245e5c745 1861 #define GPIOD_PDIR GPIO_PDIR_REG(GPIOD)
mbed_official 363:12a245e5c745 1862 #define GPIOD_PDDR GPIO_PDDR_REG(GPIOD)
mbed_official 363:12a245e5c745 1863 /* GPIOE */
mbed_official 363:12a245e5c745 1864 #define GPIOE_PDOR GPIO_PDOR_REG(GPIOE)
mbed_official 363:12a245e5c745 1865 #define GPIOE_PSOR GPIO_PSOR_REG(GPIOE)
mbed_official 363:12a245e5c745 1866 #define GPIOE_PCOR GPIO_PCOR_REG(GPIOE)
mbed_official 363:12a245e5c745 1867 #define GPIOE_PTOR GPIO_PTOR_REG(GPIOE)
mbed_official 363:12a245e5c745 1868 #define GPIOE_PDIR GPIO_PDIR_REG(GPIOE)
mbed_official 363:12a245e5c745 1869 #define GPIOE_PDDR GPIO_PDDR_REG(GPIOE)
mbed_official 363:12a245e5c745 1870
mbed_official 363:12a245e5c745 1871 /*!
mbed_official 363:12a245e5c745 1872 * @}
mbed_official 363:12a245e5c745 1873 */ /* end of group GPIO_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 1874
mbed_official 363:12a245e5c745 1875
mbed_official 363:12a245e5c745 1876 /*!
mbed_official 363:12a245e5c745 1877 * @}
mbed_official 363:12a245e5c745 1878 */ /* end of group GPIO_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 1879
mbed_official 363:12a245e5c745 1880
mbed_official 363:12a245e5c745 1881 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1882 -- I2C Peripheral Access Layer
mbed_official 363:12a245e5c745 1883 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1884
mbed_official 363:12a245e5c745 1885 /*!
mbed_official 363:12a245e5c745 1886 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
mbed_official 363:12a245e5c745 1887 * @{
mbed_official 363:12a245e5c745 1888 */
mbed_official 363:12a245e5c745 1889
mbed_official 363:12a245e5c745 1890 /** I2C - Register Layout Typedef */
mbed_official 363:12a245e5c745 1891 typedef struct {
mbed_official 363:12a245e5c745 1892 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
mbed_official 363:12a245e5c745 1893 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
mbed_official 363:12a245e5c745 1894 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
mbed_official 363:12a245e5c745 1895 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
mbed_official 363:12a245e5c745 1896 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
mbed_official 363:12a245e5c745 1897 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
mbed_official 363:12a245e5c745 1898 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
mbed_official 363:12a245e5c745 1899 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
mbed_official 363:12a245e5c745 1900 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
mbed_official 363:12a245e5c745 1901 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
mbed_official 363:12a245e5c745 1902 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
mbed_official 363:12a245e5c745 1903 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
mbed_official 363:12a245e5c745 1904 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
mbed_official 363:12a245e5c745 1905 } I2C_Type, *I2C_MemMapPtr;
mbed_official 363:12a245e5c745 1906
mbed_official 363:12a245e5c745 1907 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1908 -- I2C - Register accessor macros
mbed_official 363:12a245e5c745 1909 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1910
mbed_official 363:12a245e5c745 1911 /*!
mbed_official 363:12a245e5c745 1912 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
mbed_official 363:12a245e5c745 1913 * @{
mbed_official 363:12a245e5c745 1914 */
mbed_official 363:12a245e5c745 1915
mbed_official 363:12a245e5c745 1916
mbed_official 363:12a245e5c745 1917 /* I2C - Register accessors */
mbed_official 363:12a245e5c745 1918 #define I2C_A1_REG(base) ((base)->A1)
mbed_official 363:12a245e5c745 1919 #define I2C_F_REG(base) ((base)->F)
mbed_official 363:12a245e5c745 1920 #define I2C_C1_REG(base) ((base)->C1)
mbed_official 363:12a245e5c745 1921 #define I2C_S_REG(base) ((base)->S)
mbed_official 363:12a245e5c745 1922 #define I2C_D_REG(base) ((base)->D)
mbed_official 363:12a245e5c745 1923 #define I2C_C2_REG(base) ((base)->C2)
mbed_official 363:12a245e5c745 1924 #define I2C_FLT_REG(base) ((base)->FLT)
mbed_official 363:12a245e5c745 1925 #define I2C_RA_REG(base) ((base)->RA)
mbed_official 363:12a245e5c745 1926 #define I2C_SMB_REG(base) ((base)->SMB)
mbed_official 363:12a245e5c745 1927 #define I2C_A2_REG(base) ((base)->A2)
mbed_official 363:12a245e5c745 1928 #define I2C_SLTH_REG(base) ((base)->SLTH)
mbed_official 363:12a245e5c745 1929 #define I2C_SLTL_REG(base) ((base)->SLTL)
mbed_official 363:12a245e5c745 1930 #define I2C_S2_REG(base) ((base)->S2)
mbed_official 363:12a245e5c745 1931
mbed_official 363:12a245e5c745 1932 /*!
mbed_official 363:12a245e5c745 1933 * @}
mbed_official 363:12a245e5c745 1934 */ /* end of group I2C_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 1935
mbed_official 363:12a245e5c745 1936
mbed_official 363:12a245e5c745 1937 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 1938 -- I2C Register Masks
mbed_official 363:12a245e5c745 1939 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 1940
mbed_official 363:12a245e5c745 1941 /*!
mbed_official 363:12a245e5c745 1942 * @addtogroup I2C_Register_Masks I2C Register Masks
mbed_official 363:12a245e5c745 1943 * @{
mbed_official 363:12a245e5c745 1944 */
mbed_official 363:12a245e5c745 1945
mbed_official 363:12a245e5c745 1946 /* A1 Bit Fields */
mbed_official 363:12a245e5c745 1947 #define I2C_A1_AD_MASK 0xFEu
mbed_official 363:12a245e5c745 1948 #define I2C_A1_AD_SHIFT 1
mbed_official 363:12a245e5c745 1949 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
mbed_official 363:12a245e5c745 1950 /* F Bit Fields */
mbed_official 363:12a245e5c745 1951 #define I2C_F_ICR_MASK 0x3Fu
mbed_official 363:12a245e5c745 1952 #define I2C_F_ICR_SHIFT 0
mbed_official 363:12a245e5c745 1953 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
mbed_official 363:12a245e5c745 1954 #define I2C_F_MULT_MASK 0xC0u
mbed_official 363:12a245e5c745 1955 #define I2C_F_MULT_SHIFT 6
mbed_official 363:12a245e5c745 1956 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
mbed_official 363:12a245e5c745 1957 /* C1 Bit Fields */
mbed_official 363:12a245e5c745 1958 #define I2C_C1_DMAEN_MASK 0x1u
mbed_official 363:12a245e5c745 1959 #define I2C_C1_DMAEN_SHIFT 0
mbed_official 363:12a245e5c745 1960 #define I2C_C1_WUEN_MASK 0x2u
mbed_official 363:12a245e5c745 1961 #define I2C_C1_WUEN_SHIFT 1
mbed_official 363:12a245e5c745 1962 #define I2C_C1_RSTA_MASK 0x4u
mbed_official 363:12a245e5c745 1963 #define I2C_C1_RSTA_SHIFT 2
mbed_official 363:12a245e5c745 1964 #define I2C_C1_TXAK_MASK 0x8u
mbed_official 363:12a245e5c745 1965 #define I2C_C1_TXAK_SHIFT 3
mbed_official 363:12a245e5c745 1966 #define I2C_C1_TX_MASK 0x10u
mbed_official 363:12a245e5c745 1967 #define I2C_C1_TX_SHIFT 4
mbed_official 363:12a245e5c745 1968 #define I2C_C1_MST_MASK 0x20u
mbed_official 363:12a245e5c745 1969 #define I2C_C1_MST_SHIFT 5
mbed_official 363:12a245e5c745 1970 #define I2C_C1_IICIE_MASK 0x40u
mbed_official 363:12a245e5c745 1971 #define I2C_C1_IICIE_SHIFT 6
mbed_official 363:12a245e5c745 1972 #define I2C_C1_IICEN_MASK 0x80u
mbed_official 363:12a245e5c745 1973 #define I2C_C1_IICEN_SHIFT 7
mbed_official 363:12a245e5c745 1974 /* S Bit Fields */
mbed_official 363:12a245e5c745 1975 #define I2C_S_RXAK_MASK 0x1u
mbed_official 363:12a245e5c745 1976 #define I2C_S_RXAK_SHIFT 0
mbed_official 363:12a245e5c745 1977 #define I2C_S_IICIF_MASK 0x2u
mbed_official 363:12a245e5c745 1978 #define I2C_S_IICIF_SHIFT 1
mbed_official 363:12a245e5c745 1979 #define I2C_S_SRW_MASK 0x4u
mbed_official 363:12a245e5c745 1980 #define I2C_S_SRW_SHIFT 2
mbed_official 363:12a245e5c745 1981 #define I2C_S_RAM_MASK 0x8u
mbed_official 363:12a245e5c745 1982 #define I2C_S_RAM_SHIFT 3
mbed_official 363:12a245e5c745 1983 #define I2C_S_ARBL_MASK 0x10u
mbed_official 363:12a245e5c745 1984 #define I2C_S_ARBL_SHIFT 4
mbed_official 363:12a245e5c745 1985 #define I2C_S_BUSY_MASK 0x20u
mbed_official 363:12a245e5c745 1986 #define I2C_S_BUSY_SHIFT 5
mbed_official 363:12a245e5c745 1987 #define I2C_S_IAAS_MASK 0x40u
mbed_official 363:12a245e5c745 1988 #define I2C_S_IAAS_SHIFT 6
mbed_official 363:12a245e5c745 1989 #define I2C_S_TCF_MASK 0x80u
mbed_official 363:12a245e5c745 1990 #define I2C_S_TCF_SHIFT 7
mbed_official 363:12a245e5c745 1991 /* D Bit Fields */
mbed_official 363:12a245e5c745 1992 #define I2C_D_DATA_MASK 0xFFu
mbed_official 363:12a245e5c745 1993 #define I2C_D_DATA_SHIFT 0
mbed_official 363:12a245e5c745 1994 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
mbed_official 363:12a245e5c745 1995 /* C2 Bit Fields */
mbed_official 363:12a245e5c745 1996 #define I2C_C2_AD_MASK 0x7u
mbed_official 363:12a245e5c745 1997 #define I2C_C2_AD_SHIFT 0
mbed_official 363:12a245e5c745 1998 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
mbed_official 363:12a245e5c745 1999 #define I2C_C2_RMEN_MASK 0x8u
mbed_official 363:12a245e5c745 2000 #define I2C_C2_RMEN_SHIFT 3
mbed_official 363:12a245e5c745 2001 #define I2C_C2_SBRC_MASK 0x10u
mbed_official 363:12a245e5c745 2002 #define I2C_C2_SBRC_SHIFT 4
mbed_official 363:12a245e5c745 2003 #define I2C_C2_HDRS_MASK 0x20u
mbed_official 363:12a245e5c745 2004 #define I2C_C2_HDRS_SHIFT 5
mbed_official 363:12a245e5c745 2005 #define I2C_C2_ADEXT_MASK 0x40u
mbed_official 363:12a245e5c745 2006 #define I2C_C2_ADEXT_SHIFT 6
mbed_official 363:12a245e5c745 2007 #define I2C_C2_GCAEN_MASK 0x80u
mbed_official 363:12a245e5c745 2008 #define I2C_C2_GCAEN_SHIFT 7
mbed_official 363:12a245e5c745 2009 /* FLT Bit Fields */
mbed_official 363:12a245e5c745 2010 #define I2C_FLT_FLT_MASK 0xFu
mbed_official 363:12a245e5c745 2011 #define I2C_FLT_FLT_SHIFT 0
mbed_official 363:12a245e5c745 2012 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
mbed_official 363:12a245e5c745 2013 #define I2C_FLT_STARTF_MASK 0x10u
mbed_official 363:12a245e5c745 2014 #define I2C_FLT_STARTF_SHIFT 4
mbed_official 363:12a245e5c745 2015 #define I2C_FLT_SSIE_MASK 0x20u
mbed_official 363:12a245e5c745 2016 #define I2C_FLT_SSIE_SHIFT 5
mbed_official 363:12a245e5c745 2017 #define I2C_FLT_STOPF_MASK 0x40u
mbed_official 363:12a245e5c745 2018 #define I2C_FLT_STOPF_SHIFT 6
mbed_official 363:12a245e5c745 2019 #define I2C_FLT_SHEN_MASK 0x80u
mbed_official 363:12a245e5c745 2020 #define I2C_FLT_SHEN_SHIFT 7
mbed_official 363:12a245e5c745 2021 /* RA Bit Fields */
mbed_official 363:12a245e5c745 2022 #define I2C_RA_RAD_MASK 0xFEu
mbed_official 363:12a245e5c745 2023 #define I2C_RA_RAD_SHIFT 1
mbed_official 363:12a245e5c745 2024 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
mbed_official 363:12a245e5c745 2025 /* SMB Bit Fields */
mbed_official 363:12a245e5c745 2026 #define I2C_SMB_SHTF2IE_MASK 0x1u
mbed_official 363:12a245e5c745 2027 #define I2C_SMB_SHTF2IE_SHIFT 0
mbed_official 363:12a245e5c745 2028 #define I2C_SMB_SHTF2_MASK 0x2u
mbed_official 363:12a245e5c745 2029 #define I2C_SMB_SHTF2_SHIFT 1
mbed_official 363:12a245e5c745 2030 #define I2C_SMB_SHTF1_MASK 0x4u
mbed_official 363:12a245e5c745 2031 #define I2C_SMB_SHTF1_SHIFT 2
mbed_official 363:12a245e5c745 2032 #define I2C_SMB_SLTF_MASK 0x8u
mbed_official 363:12a245e5c745 2033 #define I2C_SMB_SLTF_SHIFT 3
mbed_official 363:12a245e5c745 2034 #define I2C_SMB_TCKSEL_MASK 0x10u
mbed_official 363:12a245e5c745 2035 #define I2C_SMB_TCKSEL_SHIFT 4
mbed_official 363:12a245e5c745 2036 #define I2C_SMB_SIICAEN_MASK 0x20u
mbed_official 363:12a245e5c745 2037 #define I2C_SMB_SIICAEN_SHIFT 5
mbed_official 363:12a245e5c745 2038 #define I2C_SMB_ALERTEN_MASK 0x40u
mbed_official 363:12a245e5c745 2039 #define I2C_SMB_ALERTEN_SHIFT 6
mbed_official 363:12a245e5c745 2040 #define I2C_SMB_FACK_MASK 0x80u
mbed_official 363:12a245e5c745 2041 #define I2C_SMB_FACK_SHIFT 7
mbed_official 363:12a245e5c745 2042 /* A2 Bit Fields */
mbed_official 363:12a245e5c745 2043 #define I2C_A2_SAD_MASK 0xFEu
mbed_official 363:12a245e5c745 2044 #define I2C_A2_SAD_SHIFT 1
mbed_official 363:12a245e5c745 2045 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
mbed_official 363:12a245e5c745 2046 /* SLTH Bit Fields */
mbed_official 363:12a245e5c745 2047 #define I2C_SLTH_SSLT_MASK 0xFFu
mbed_official 363:12a245e5c745 2048 #define I2C_SLTH_SSLT_SHIFT 0
mbed_official 363:12a245e5c745 2049 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
mbed_official 363:12a245e5c745 2050 /* SLTL Bit Fields */
mbed_official 363:12a245e5c745 2051 #define I2C_SLTL_SSLT_MASK 0xFFu
mbed_official 363:12a245e5c745 2052 #define I2C_SLTL_SSLT_SHIFT 0
mbed_official 363:12a245e5c745 2053 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
mbed_official 363:12a245e5c745 2054 /* S2 Bit Fields */
mbed_official 363:12a245e5c745 2055 #define I2C_S2_EMPTY_MASK 0x1u
mbed_official 363:12a245e5c745 2056 #define I2C_S2_EMPTY_SHIFT 0
mbed_official 363:12a245e5c745 2057 #define I2C_S2_ERROR_MASK 0x2u
mbed_official 363:12a245e5c745 2058 #define I2C_S2_ERROR_SHIFT 1
mbed_official 363:12a245e5c745 2059
mbed_official 363:12a245e5c745 2060 /*!
mbed_official 363:12a245e5c745 2061 * @}
mbed_official 363:12a245e5c745 2062 */ /* end of group I2C_Register_Masks */
mbed_official 363:12a245e5c745 2063
mbed_official 363:12a245e5c745 2064
mbed_official 363:12a245e5c745 2065 /* I2C - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 2066 /** Peripheral I2C0 base address */
mbed_official 363:12a245e5c745 2067 #define I2C0_BASE (0x40066000u)
mbed_official 363:12a245e5c745 2068 /** Peripheral I2C0 base pointer */
mbed_official 363:12a245e5c745 2069 #define I2C0 ((I2C_Type *)I2C0_BASE)
mbed_official 363:12a245e5c745 2070 #define I2C0_BASE_PTR (I2C0)
mbed_official 363:12a245e5c745 2071 /** Peripheral I2C1 base address */
mbed_official 363:12a245e5c745 2072 #define I2C1_BASE (0x40067000u)
mbed_official 363:12a245e5c745 2073 /** Peripheral I2C1 base pointer */
mbed_official 363:12a245e5c745 2074 #define I2C1 ((I2C_Type *)I2C1_BASE)
mbed_official 363:12a245e5c745 2075 #define I2C1_BASE_PTR (I2C1)
mbed_official 363:12a245e5c745 2076 /** Array initializer of I2C peripheral base addresses */
mbed_official 363:12a245e5c745 2077 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
mbed_official 363:12a245e5c745 2078 /** Array initializer of I2C peripheral base pointers */
mbed_official 363:12a245e5c745 2079 #define I2C_BASE_PTRS { I2C0, I2C1 }
mbed_official 363:12a245e5c745 2080 /** Interrupt vectors for the I2C peripheral type */
mbed_official 363:12a245e5c745 2081 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
mbed_official 363:12a245e5c745 2082
mbed_official 363:12a245e5c745 2083 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 2084 -- I2C - Register accessor macros
mbed_official 363:12a245e5c745 2085 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 2086
mbed_official 363:12a245e5c745 2087 /*!
mbed_official 363:12a245e5c745 2088 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
mbed_official 363:12a245e5c745 2089 * @{
mbed_official 363:12a245e5c745 2090 */
mbed_official 363:12a245e5c745 2091
mbed_official 363:12a245e5c745 2092
mbed_official 363:12a245e5c745 2093 /* I2C - Register instance definitions */
mbed_official 363:12a245e5c745 2094 /* I2C0 */
mbed_official 363:12a245e5c745 2095 #define I2C0_A1 I2C_A1_REG(I2C0)
mbed_official 363:12a245e5c745 2096 #define I2C0_F I2C_F_REG(I2C0)
mbed_official 363:12a245e5c745 2097 #define I2C0_C1 I2C_C1_REG(I2C0)
mbed_official 363:12a245e5c745 2098 #define I2C0_S I2C_S_REG(I2C0)
mbed_official 363:12a245e5c745 2099 #define I2C0_D I2C_D_REG(I2C0)
mbed_official 363:12a245e5c745 2100 #define I2C0_C2 I2C_C2_REG(I2C0)
mbed_official 363:12a245e5c745 2101 #define I2C0_FLT I2C_FLT_REG(I2C0)
mbed_official 363:12a245e5c745 2102 #define I2C0_RA I2C_RA_REG(I2C0)
mbed_official 363:12a245e5c745 2103 #define I2C0_SMB I2C_SMB_REG(I2C0)
mbed_official 363:12a245e5c745 2104 #define I2C0_A2 I2C_A2_REG(I2C0)
mbed_official 363:12a245e5c745 2105 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
mbed_official 363:12a245e5c745 2106 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
mbed_official 363:12a245e5c745 2107 #define I2C0_S2 I2C_S2_REG(I2C0)
mbed_official 363:12a245e5c745 2108 /* I2C1 */
mbed_official 363:12a245e5c745 2109 #define I2C1_A1 I2C_A1_REG(I2C1)
mbed_official 363:12a245e5c745 2110 #define I2C1_F I2C_F_REG(I2C1)
mbed_official 363:12a245e5c745 2111 #define I2C1_C1 I2C_C1_REG(I2C1)
mbed_official 363:12a245e5c745 2112 #define I2C1_S I2C_S_REG(I2C1)
mbed_official 363:12a245e5c745 2113 #define I2C1_D I2C_D_REG(I2C1)
mbed_official 363:12a245e5c745 2114 #define I2C1_C2 I2C_C2_REG(I2C1)
mbed_official 363:12a245e5c745 2115 #define I2C1_FLT I2C_FLT_REG(I2C1)
mbed_official 363:12a245e5c745 2116 #define I2C1_RA I2C_RA_REG(I2C1)
mbed_official 363:12a245e5c745 2117 #define I2C1_SMB I2C_SMB_REG(I2C1)
mbed_official 363:12a245e5c745 2118 #define I2C1_A2 I2C_A2_REG(I2C1)
mbed_official 363:12a245e5c745 2119 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
mbed_official 363:12a245e5c745 2120 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
mbed_official 363:12a245e5c745 2121 #define I2C1_S2 I2C_S2_REG(I2C1)
mbed_official 363:12a245e5c745 2122
mbed_official 363:12a245e5c745 2123 /*!
mbed_official 363:12a245e5c745 2124 * @}
mbed_official 363:12a245e5c745 2125 */ /* end of group I2C_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 2126
mbed_official 363:12a245e5c745 2127
mbed_official 363:12a245e5c745 2128 /*!
mbed_official 363:12a245e5c745 2129 * @}
mbed_official 363:12a245e5c745 2130 */ /* end of group I2C_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 2131
mbed_official 363:12a245e5c745 2132
mbed_official 363:12a245e5c745 2133 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 2134 -- I2S Peripheral Access Layer
mbed_official 363:12a245e5c745 2135 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 2136
mbed_official 363:12a245e5c745 2137 /*!
mbed_official 363:12a245e5c745 2138 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
mbed_official 363:12a245e5c745 2139 * @{
mbed_official 363:12a245e5c745 2140 */
mbed_official 363:12a245e5c745 2141
mbed_official 363:12a245e5c745 2142 /** I2S - Register Layout Typedef */
mbed_official 363:12a245e5c745 2143 typedef struct {
mbed_official 363:12a245e5c745 2144 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
mbed_official 363:12a245e5c745 2145 uint8_t RESERVED_0[4];
mbed_official 363:12a245e5c745 2146 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
mbed_official 363:12a245e5c745 2147 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
mbed_official 363:12a245e5c745 2148 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
mbed_official 363:12a245e5c745 2149 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
mbed_official 363:12a245e5c745 2150 uint8_t RESERVED_1[8];
mbed_official 363:12a245e5c745 2151 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
mbed_official 363:12a245e5c745 2152 uint8_t RESERVED_2[60];
mbed_official 363:12a245e5c745 2153 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
mbed_official 363:12a245e5c745 2154 uint8_t RESERVED_3[28];
mbed_official 363:12a245e5c745 2155 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
mbed_official 363:12a245e5c745 2156 uint8_t RESERVED_4[4];
mbed_official 363:12a245e5c745 2157 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
mbed_official 363:12a245e5c745 2158 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
mbed_official 363:12a245e5c745 2159 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
mbed_official 363:12a245e5c745 2160 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
mbed_official 363:12a245e5c745 2161 uint8_t RESERVED_5[8];
mbed_official 363:12a245e5c745 2162 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
mbed_official 363:12a245e5c745 2163 uint8_t RESERVED_6[60];
mbed_official 363:12a245e5c745 2164 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
mbed_official 363:12a245e5c745 2165 uint8_t RESERVED_7[28];
mbed_official 363:12a245e5c745 2166 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
mbed_official 363:12a245e5c745 2167 } I2S_Type, *I2S_MemMapPtr;
mbed_official 363:12a245e5c745 2168
mbed_official 363:12a245e5c745 2169 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 2170 -- I2S - Register accessor macros
mbed_official 363:12a245e5c745 2171 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 2172
mbed_official 363:12a245e5c745 2173 /*!
mbed_official 363:12a245e5c745 2174 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
mbed_official 363:12a245e5c745 2175 * @{
mbed_official 363:12a245e5c745 2176 */
mbed_official 363:12a245e5c745 2177
mbed_official 363:12a245e5c745 2178
mbed_official 363:12a245e5c745 2179 /* I2S - Register accessors */
mbed_official 363:12a245e5c745 2180 #define I2S_TCSR_REG(base) ((base)->TCSR)
mbed_official 363:12a245e5c745 2181 #define I2S_TCR2_REG(base) ((base)->TCR2)
mbed_official 363:12a245e5c745 2182 #define I2S_TCR3_REG(base) ((base)->TCR3)
mbed_official 363:12a245e5c745 2183 #define I2S_TCR4_REG(base) ((base)->TCR4)
mbed_official 363:12a245e5c745 2184 #define I2S_TCR5_REG(base) ((base)->TCR5)
mbed_official 363:12a245e5c745 2185 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
mbed_official 363:12a245e5c745 2186 #define I2S_TMR_REG(base) ((base)->TMR)
mbed_official 363:12a245e5c745 2187 #define I2S_RCSR_REG(base) ((base)->RCSR)
mbed_official 363:12a245e5c745 2188 #define I2S_RCR2_REG(base) ((base)->RCR2)
mbed_official 363:12a245e5c745 2189 #define I2S_RCR3_REG(base) ((base)->RCR3)
mbed_official 363:12a245e5c745 2190 #define I2S_RCR4_REG(base) ((base)->RCR4)
mbed_official 363:12a245e5c745 2191 #define I2S_RCR5_REG(base) ((base)->RCR5)
mbed_official 363:12a245e5c745 2192 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
mbed_official 363:12a245e5c745 2193 #define I2S_RMR_REG(base) ((base)->RMR)
mbed_official 363:12a245e5c745 2194 #define I2S_MCR_REG(base) ((base)->MCR)
mbed_official 363:12a245e5c745 2195
mbed_official 363:12a245e5c745 2196 /*!
mbed_official 363:12a245e5c745 2197 * @}
mbed_official 363:12a245e5c745 2198 */ /* end of group I2S_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 2199
mbed_official 363:12a245e5c745 2200
mbed_official 363:12a245e5c745 2201 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 2202 -- I2S Register Masks
mbed_official 363:12a245e5c745 2203 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 2204
mbed_official 363:12a245e5c745 2205 /*!
mbed_official 363:12a245e5c745 2206 * @addtogroup I2S_Register_Masks I2S Register Masks
mbed_official 363:12a245e5c745 2207 * @{
mbed_official 363:12a245e5c745 2208 */
mbed_official 363:12a245e5c745 2209
mbed_official 363:12a245e5c745 2210 /* TCSR Bit Fields */
mbed_official 363:12a245e5c745 2211 #define I2S_TCSR_FWDE_MASK 0x2u
mbed_official 363:12a245e5c745 2212 #define I2S_TCSR_FWDE_SHIFT 1
mbed_official 363:12a245e5c745 2213 #define I2S_TCSR_FWIE_MASK 0x200u
mbed_official 363:12a245e5c745 2214 #define I2S_TCSR_FWIE_SHIFT 9
mbed_official 363:12a245e5c745 2215 #define I2S_TCSR_FEIE_MASK 0x400u
mbed_official 363:12a245e5c745 2216 #define I2S_TCSR_FEIE_SHIFT 10
mbed_official 363:12a245e5c745 2217 #define I2S_TCSR_SEIE_MASK 0x800u
mbed_official 363:12a245e5c745 2218 #define I2S_TCSR_SEIE_SHIFT 11
mbed_official 363:12a245e5c745 2219 #define I2S_TCSR_WSIE_MASK 0x1000u
mbed_official 363:12a245e5c745 2220 #define I2S_TCSR_WSIE_SHIFT 12
mbed_official 363:12a245e5c745 2221 #define I2S_TCSR_FWF_MASK 0x20000u
mbed_official 363:12a245e5c745 2222 #define I2S_TCSR_FWF_SHIFT 17
mbed_official 363:12a245e5c745 2223 #define I2S_TCSR_FEF_MASK 0x40000u
mbed_official 363:12a245e5c745 2224 #define I2S_TCSR_FEF_SHIFT 18
mbed_official 363:12a245e5c745 2225 #define I2S_TCSR_SEF_MASK 0x80000u
mbed_official 363:12a245e5c745 2226 #define I2S_TCSR_SEF_SHIFT 19
mbed_official 363:12a245e5c745 2227 #define I2S_TCSR_WSF_MASK 0x100000u
mbed_official 363:12a245e5c745 2228 #define I2S_TCSR_WSF_SHIFT 20
mbed_official 363:12a245e5c745 2229 #define I2S_TCSR_SR_MASK 0x1000000u
mbed_official 363:12a245e5c745 2230 #define I2S_TCSR_SR_SHIFT 24
mbed_official 363:12a245e5c745 2231 #define I2S_TCSR_FR_MASK 0x2000000u
mbed_official 363:12a245e5c745 2232 #define I2S_TCSR_FR_SHIFT 25
mbed_official 363:12a245e5c745 2233 #define I2S_TCSR_BCE_MASK 0x10000000u
mbed_official 363:12a245e5c745 2234 #define I2S_TCSR_BCE_SHIFT 28
mbed_official 363:12a245e5c745 2235 #define I2S_TCSR_DBGE_MASK 0x20000000u
mbed_official 363:12a245e5c745 2236 #define I2S_TCSR_DBGE_SHIFT 29
mbed_official 363:12a245e5c745 2237 #define I2S_TCSR_STOPE_MASK 0x40000000u
mbed_official 363:12a245e5c745 2238 #define I2S_TCSR_STOPE_SHIFT 30
mbed_official 363:12a245e5c745 2239 #define I2S_TCSR_TE_MASK 0x80000000u
mbed_official 363:12a245e5c745 2240 #define I2S_TCSR_TE_SHIFT 31
mbed_official 363:12a245e5c745 2241 /* TCR2 Bit Fields */
mbed_official 363:12a245e5c745 2242 #define I2S_TCR2_DIV_MASK 0xFFu
mbed_official 363:12a245e5c745 2243 #define I2S_TCR2_DIV_SHIFT 0
mbed_official 363:12a245e5c745 2244 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
mbed_official 363:12a245e5c745 2245 #define I2S_TCR2_BCD_MASK 0x1000000u
mbed_official 363:12a245e5c745 2246 #define I2S_TCR2_BCD_SHIFT 24
mbed_official 363:12a245e5c745 2247 #define I2S_TCR2_BCP_MASK 0x2000000u
mbed_official 363:12a245e5c745 2248 #define I2S_TCR2_BCP_SHIFT 25
mbed_official 363:12a245e5c745 2249 #define I2S_TCR2_MSEL_MASK 0xC000000u
mbed_official 363:12a245e5c745 2250 #define I2S_TCR2_MSEL_SHIFT 26
mbed_official 363:12a245e5c745 2251 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
mbed_official 363:12a245e5c745 2252 #define I2S_TCR2_BCI_MASK 0x10000000u
mbed_official 363:12a245e5c745 2253 #define I2S_TCR2_BCI_SHIFT 28
mbed_official 363:12a245e5c745 2254 #define I2S_TCR2_BCS_MASK 0x20000000u
mbed_official 363:12a245e5c745 2255 #define I2S_TCR2_BCS_SHIFT 29
mbed_official 363:12a245e5c745 2256 #define I2S_TCR2_SYNC_MASK 0xC0000000u
mbed_official 363:12a245e5c745 2257 #define I2S_TCR2_SYNC_SHIFT 30
mbed_official 363:12a245e5c745 2258 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
mbed_official 363:12a245e5c745 2259 /* TCR3 Bit Fields */
mbed_official 363:12a245e5c745 2260 #define I2S_TCR3_WDFL_MASK 0x1u
mbed_official 363:12a245e5c745 2261 #define I2S_TCR3_WDFL_SHIFT 0
mbed_official 363:12a245e5c745 2262 #define I2S_TCR3_TCE_MASK 0x10000u
mbed_official 363:12a245e5c745 2263 #define I2S_TCR3_TCE_SHIFT 16
mbed_official 363:12a245e5c745 2264 /* TCR4 Bit Fields */
mbed_official 363:12a245e5c745 2265 #define I2S_TCR4_FSD_MASK 0x1u
mbed_official 363:12a245e5c745 2266 #define I2S_TCR4_FSD_SHIFT 0
mbed_official 363:12a245e5c745 2267 #define I2S_TCR4_FSP_MASK 0x2u
mbed_official 363:12a245e5c745 2268 #define I2S_TCR4_FSP_SHIFT 1
mbed_official 363:12a245e5c745 2269 #define I2S_TCR4_ONDEM_MASK 0x4u
mbed_official 363:12a245e5c745 2270 #define I2S_TCR4_ONDEM_SHIFT 2
mbed_official 363:12a245e5c745 2271 #define I2S_TCR4_FSE_MASK 0x8u
mbed_official 363:12a245e5c745 2272 #define I2S_TCR4_FSE_SHIFT 3
mbed_official 363:12a245e5c745 2273 #define I2S_TCR4_MF_MASK 0x10u
mbed_official 363:12a245e5c745 2274 #define I2S_TCR4_MF_SHIFT 4
mbed_official 363:12a245e5c745 2275 #define I2S_TCR4_SYWD_MASK 0x1F00u
mbed_official 363:12a245e5c745 2276 #define I2S_TCR4_SYWD_SHIFT 8
mbed_official 363:12a245e5c745 2277 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
mbed_official 363:12a245e5c745 2278 #define I2S_TCR4_FRSZ_MASK 0x10000u
mbed_official 363:12a245e5c745 2279 #define I2S_TCR4_FRSZ_SHIFT 16
mbed_official 363:12a245e5c745 2280 #define I2S_TCR4_FPACK_MASK 0x3000000u
mbed_official 363:12a245e5c745 2281 #define I2S_TCR4_FPACK_SHIFT 24
mbed_official 363:12a245e5c745 2282 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
mbed_official 363:12a245e5c745 2283 #define I2S_TCR4_FCONT_MASK 0x10000000u
mbed_official 363:12a245e5c745 2284 #define I2S_TCR4_FCONT_SHIFT 28
mbed_official 363:12a245e5c745 2285 /* TCR5 Bit Fields */
mbed_official 363:12a245e5c745 2286 #define I2S_TCR5_FBT_MASK 0x1F00u
mbed_official 363:12a245e5c745 2287 #define I2S_TCR5_FBT_SHIFT 8
mbed_official 363:12a245e5c745 2288 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
mbed_official 363:12a245e5c745 2289 #define I2S_TCR5_W0W_MASK 0x1F0000u
mbed_official 363:12a245e5c745 2290 #define I2S_TCR5_W0W_SHIFT 16
mbed_official 363:12a245e5c745 2291 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
mbed_official 363:12a245e5c745 2292 #define I2S_TCR5_WNW_MASK 0x1F000000u
mbed_official 363:12a245e5c745 2293 #define I2S_TCR5_WNW_SHIFT 24
mbed_official 363:12a245e5c745 2294 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
mbed_official 363:12a245e5c745 2295 /* TDR Bit Fields */
mbed_official 363:12a245e5c745 2296 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 2297 #define I2S_TDR_TDR_SHIFT 0
mbed_official 363:12a245e5c745 2298 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
mbed_official 363:12a245e5c745 2299 /* TMR Bit Fields */
mbed_official 363:12a245e5c745 2300 #define I2S_TMR_TWM_MASK 0x3u
mbed_official 363:12a245e5c745 2301 #define I2S_TMR_TWM_SHIFT 0
mbed_official 363:12a245e5c745 2302 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
mbed_official 363:12a245e5c745 2303 /* RCSR Bit Fields */
mbed_official 363:12a245e5c745 2304 #define I2S_RCSR_FWDE_MASK 0x2u
mbed_official 363:12a245e5c745 2305 #define I2S_RCSR_FWDE_SHIFT 1
mbed_official 363:12a245e5c745 2306 #define I2S_RCSR_FWIE_MASK 0x200u
mbed_official 363:12a245e5c745 2307 #define I2S_RCSR_FWIE_SHIFT 9
mbed_official 363:12a245e5c745 2308 #define I2S_RCSR_FEIE_MASK 0x400u
mbed_official 363:12a245e5c745 2309 #define I2S_RCSR_FEIE_SHIFT 10
mbed_official 363:12a245e5c745 2310 #define I2S_RCSR_SEIE_MASK 0x800u
mbed_official 363:12a245e5c745 2311 #define I2S_RCSR_SEIE_SHIFT 11
mbed_official 363:12a245e5c745 2312 #define I2S_RCSR_WSIE_MASK 0x1000u
mbed_official 363:12a245e5c745 2313 #define I2S_RCSR_WSIE_SHIFT 12
mbed_official 363:12a245e5c745 2314 #define I2S_RCSR_FWF_MASK 0x20000u
mbed_official 363:12a245e5c745 2315 #define I2S_RCSR_FWF_SHIFT 17
mbed_official 363:12a245e5c745 2316 #define I2S_RCSR_FEF_MASK 0x40000u
mbed_official 363:12a245e5c745 2317 #define I2S_RCSR_FEF_SHIFT 18
mbed_official 363:12a245e5c745 2318 #define I2S_RCSR_SEF_MASK 0x80000u
mbed_official 363:12a245e5c745 2319 #define I2S_RCSR_SEF_SHIFT 19
mbed_official 363:12a245e5c745 2320 #define I2S_RCSR_WSF_MASK 0x100000u
mbed_official 363:12a245e5c745 2321 #define I2S_RCSR_WSF_SHIFT 20
mbed_official 363:12a245e5c745 2322 #define I2S_RCSR_SR_MASK 0x1000000u
mbed_official 363:12a245e5c745 2323 #define I2S_RCSR_SR_SHIFT 24
mbed_official 363:12a245e5c745 2324 #define I2S_RCSR_FR_MASK 0x2000000u
mbed_official 363:12a245e5c745 2325 #define I2S_RCSR_FR_SHIFT 25
mbed_official 363:12a245e5c745 2326 #define I2S_RCSR_BCE_MASK 0x10000000u
mbed_official 363:12a245e5c745 2327 #define I2S_RCSR_BCE_SHIFT 28
mbed_official 363:12a245e5c745 2328 #define I2S_RCSR_DBGE_MASK 0x20000000u
mbed_official 363:12a245e5c745 2329 #define I2S_RCSR_DBGE_SHIFT 29
mbed_official 363:12a245e5c745 2330 #define I2S_RCSR_STOPE_MASK 0x40000000u
mbed_official 363:12a245e5c745 2331 #define I2S_RCSR_STOPE_SHIFT 30
mbed_official 363:12a245e5c745 2332 #define I2S_RCSR_RE_MASK 0x80000000u
mbed_official 363:12a245e5c745 2333 #define I2S_RCSR_RE_SHIFT 31
mbed_official 363:12a245e5c745 2334 /* RCR2 Bit Fields */
mbed_official 363:12a245e5c745 2335 #define I2S_RCR2_DIV_MASK 0xFFu
mbed_official 363:12a245e5c745 2336 #define I2S_RCR2_DIV_SHIFT 0
mbed_official 363:12a245e5c745 2337 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
mbed_official 363:12a245e5c745 2338 #define I2S_RCR2_BCD_MASK 0x1000000u
mbed_official 363:12a245e5c745 2339 #define I2S_RCR2_BCD_SHIFT 24
mbed_official 363:12a245e5c745 2340 #define I2S_RCR2_BCP_MASK 0x2000000u
mbed_official 363:12a245e5c745 2341 #define I2S_RCR2_BCP_SHIFT 25
mbed_official 363:12a245e5c745 2342 #define I2S_RCR2_MSEL_MASK 0xC000000u
mbed_official 363:12a245e5c745 2343 #define I2S_RCR2_MSEL_SHIFT 26
mbed_official 363:12a245e5c745 2344 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
mbed_official 363:12a245e5c745 2345 #define I2S_RCR2_BCI_MASK 0x10000000u
mbed_official 363:12a245e5c745 2346 #define I2S_RCR2_BCI_SHIFT 28
mbed_official 363:12a245e5c745 2347 #define I2S_RCR2_BCS_MASK 0x20000000u
mbed_official 363:12a245e5c745 2348 #define I2S_RCR2_BCS_SHIFT 29
mbed_official 363:12a245e5c745 2349 #define I2S_RCR2_SYNC_MASK 0xC0000000u
mbed_official 363:12a245e5c745 2350 #define I2S_RCR2_SYNC_SHIFT 30
mbed_official 363:12a245e5c745 2351 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
mbed_official 363:12a245e5c745 2352 /* RCR3 Bit Fields */
mbed_official 363:12a245e5c745 2353 #define I2S_RCR3_WDFL_MASK 0x1u
mbed_official 363:12a245e5c745 2354 #define I2S_RCR3_WDFL_SHIFT 0
mbed_official 363:12a245e5c745 2355 #define I2S_RCR3_RCE_MASK 0x10000u
mbed_official 363:12a245e5c745 2356 #define I2S_RCR3_RCE_SHIFT 16
mbed_official 363:12a245e5c745 2357 /* RCR4 Bit Fields */
mbed_official 363:12a245e5c745 2358 #define I2S_RCR4_FSD_MASK 0x1u
mbed_official 363:12a245e5c745 2359 #define I2S_RCR4_FSD_SHIFT 0
mbed_official 363:12a245e5c745 2360 #define I2S_RCR4_FSP_MASK 0x2u
mbed_official 363:12a245e5c745 2361 #define I2S_RCR4_FSP_SHIFT 1
mbed_official 363:12a245e5c745 2362 #define I2S_RCR4_ONDEM_MASK 0x4u
mbed_official 363:12a245e5c745 2363 #define I2S_RCR4_ONDEM_SHIFT 2
mbed_official 363:12a245e5c745 2364 #define I2S_RCR4_FSE_MASK 0x8u
mbed_official 363:12a245e5c745 2365 #define I2S_RCR4_FSE_SHIFT 3
mbed_official 363:12a245e5c745 2366 #define I2S_RCR4_MF_MASK 0x10u
mbed_official 363:12a245e5c745 2367 #define I2S_RCR4_MF_SHIFT 4
mbed_official 363:12a245e5c745 2368 #define I2S_RCR4_SYWD_MASK 0x1F00u
mbed_official 363:12a245e5c745 2369 #define I2S_RCR4_SYWD_SHIFT 8
mbed_official 363:12a245e5c745 2370 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
mbed_official 363:12a245e5c745 2371 #define I2S_RCR4_FRSZ_MASK 0x10000u
mbed_official 363:12a245e5c745 2372 #define I2S_RCR4_FRSZ_SHIFT 16
mbed_official 363:12a245e5c745 2373 #define I2S_RCR4_FPACK_MASK 0x3000000u
mbed_official 363:12a245e5c745 2374 #define I2S_RCR4_FPACK_SHIFT 24
mbed_official 363:12a245e5c745 2375 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
mbed_official 363:12a245e5c745 2376 #define I2S_RCR4_FCONT_MASK 0x10000000u
mbed_official 363:12a245e5c745 2377 #define I2S_RCR4_FCONT_SHIFT 28
mbed_official 363:12a245e5c745 2378 /* RCR5 Bit Fields */
mbed_official 363:12a245e5c745 2379 #define I2S_RCR5_FBT_MASK 0x1F00u
mbed_official 363:12a245e5c745 2380 #define I2S_RCR5_FBT_SHIFT 8
mbed_official 363:12a245e5c745 2381 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
mbed_official 363:12a245e5c745 2382 #define I2S_RCR5_W0W_MASK 0x1F0000u
mbed_official 363:12a245e5c745 2383 #define I2S_RCR5_W0W_SHIFT 16
mbed_official 363:12a245e5c745 2384 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
mbed_official 363:12a245e5c745 2385 #define I2S_RCR5_WNW_MASK 0x1F000000u
mbed_official 363:12a245e5c745 2386 #define I2S_RCR5_WNW_SHIFT 24
mbed_official 363:12a245e5c745 2387 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
mbed_official 363:12a245e5c745 2388 /* RDR Bit Fields */
mbed_official 363:12a245e5c745 2389 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 2390 #define I2S_RDR_RDR_SHIFT 0
mbed_official 363:12a245e5c745 2391 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
mbed_official 363:12a245e5c745 2392 /* RMR Bit Fields */
mbed_official 363:12a245e5c745 2393 #define I2S_RMR_RWM_MASK 0x3u
mbed_official 363:12a245e5c745 2394 #define I2S_RMR_RWM_SHIFT 0
mbed_official 363:12a245e5c745 2395 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
mbed_official 363:12a245e5c745 2396 /* MCR Bit Fields */
mbed_official 363:12a245e5c745 2397 #define I2S_MCR_MICS_MASK 0x3000000u
mbed_official 363:12a245e5c745 2398 #define I2S_MCR_MICS_SHIFT 24
mbed_official 363:12a245e5c745 2399 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
mbed_official 363:12a245e5c745 2400 #define I2S_MCR_MOE_MASK 0x40000000u
mbed_official 363:12a245e5c745 2401 #define I2S_MCR_MOE_SHIFT 30
mbed_official 363:12a245e5c745 2402 #define I2S_MCR_DUF_MASK 0x80000000u
mbed_official 363:12a245e5c745 2403 #define I2S_MCR_DUF_SHIFT 31
mbed_official 363:12a245e5c745 2404
mbed_official 363:12a245e5c745 2405 /*!
mbed_official 363:12a245e5c745 2406 * @}
mbed_official 363:12a245e5c745 2407 */ /* end of group I2S_Register_Masks */
mbed_official 363:12a245e5c745 2408
mbed_official 363:12a245e5c745 2409
mbed_official 363:12a245e5c745 2410 /* I2S - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 2411 /** Peripheral I2S0 base address */
mbed_official 363:12a245e5c745 2412 #define I2S0_BASE (0x4002F000u)
mbed_official 363:12a245e5c745 2413 /** Peripheral I2S0 base pointer */
mbed_official 363:12a245e5c745 2414 #define I2S0 ((I2S_Type *)I2S0_BASE)
mbed_official 363:12a245e5c745 2415 #define I2S0_BASE_PTR (I2S0)
mbed_official 363:12a245e5c745 2416 /** Array initializer of I2S peripheral base addresses */
mbed_official 363:12a245e5c745 2417 #define I2S_BASE_ADDRS { I2S0_BASE }
mbed_official 363:12a245e5c745 2418 /** Array initializer of I2S peripheral base pointers */
mbed_official 363:12a245e5c745 2419 #define I2S_BASE_PTRS { I2S0 }
mbed_official 363:12a245e5c745 2420 /** Interrupt vectors for the I2S peripheral type */
mbed_official 363:12a245e5c745 2421 #define I2S_RX_IRQS { I2S0_IRQn }
mbed_official 363:12a245e5c745 2422 #define I2S_TX_IRQS { I2S0_IRQn }
mbed_official 363:12a245e5c745 2423
mbed_official 363:12a245e5c745 2424 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 2425 -- I2S - Register accessor macros
mbed_official 363:12a245e5c745 2426 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 2427
mbed_official 363:12a245e5c745 2428 /*!
mbed_official 363:12a245e5c745 2429 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
mbed_official 363:12a245e5c745 2430 * @{
mbed_official 363:12a245e5c745 2431 */
mbed_official 363:12a245e5c745 2432
mbed_official 363:12a245e5c745 2433
mbed_official 363:12a245e5c745 2434 /* I2S - Register instance definitions */
mbed_official 363:12a245e5c745 2435 /* I2S0 */
mbed_official 363:12a245e5c745 2436 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
mbed_official 363:12a245e5c745 2437 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
mbed_official 363:12a245e5c745 2438 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
mbed_official 363:12a245e5c745 2439 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
mbed_official 363:12a245e5c745 2440 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
mbed_official 363:12a245e5c745 2441 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
mbed_official 363:12a245e5c745 2442 #define I2S0_TMR I2S_TMR_REG(I2S0)
mbed_official 363:12a245e5c745 2443 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
mbed_official 363:12a245e5c745 2444 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
mbed_official 363:12a245e5c745 2445 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
mbed_official 363:12a245e5c745 2446 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
mbed_official 363:12a245e5c745 2447 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
mbed_official 363:12a245e5c745 2448 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
mbed_official 363:12a245e5c745 2449 #define I2S0_RMR I2S_RMR_REG(I2S0)
mbed_official 363:12a245e5c745 2450 #define I2S0_MCR I2S_MCR_REG(I2S0)
mbed_official 363:12a245e5c745 2451
mbed_official 363:12a245e5c745 2452 /* I2S - Register array accessors */
mbed_official 363:12a245e5c745 2453 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
mbed_official 363:12a245e5c745 2454 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
mbed_official 363:12a245e5c745 2455
mbed_official 363:12a245e5c745 2456 /*!
mbed_official 363:12a245e5c745 2457 * @}
mbed_official 363:12a245e5c745 2458 */ /* end of group I2S_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 2459
mbed_official 363:12a245e5c745 2460
mbed_official 363:12a245e5c745 2461 /*!
mbed_official 363:12a245e5c745 2462 * @}
mbed_official 363:12a245e5c745 2463 */ /* end of group I2S_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 2464
mbed_official 363:12a245e5c745 2465
mbed_official 363:12a245e5c745 2466 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 2467 -- LCD Peripheral Access Layer
mbed_official 363:12a245e5c745 2468 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 2469
mbed_official 363:12a245e5c745 2470 /*!
mbed_official 363:12a245e5c745 2471 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
mbed_official 363:12a245e5c745 2472 * @{
mbed_official 363:12a245e5c745 2473 */
mbed_official 363:12a245e5c745 2474
mbed_official 363:12a245e5c745 2475 /** LCD - Register Layout Typedef */
mbed_official 363:12a245e5c745 2476 typedef struct {
mbed_official 363:12a245e5c745 2477 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
mbed_official 363:12a245e5c745 2478 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
mbed_official 363:12a245e5c745 2479 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
mbed_official 363:12a245e5c745 2480 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
mbed_official 363:12a245e5c745 2481 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
mbed_official 363:12a245e5c745 2482 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
mbed_official 363:12a245e5c745 2483 union { /* offset: 0x20 */
mbed_official 363:12a245e5c745 2484 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
mbed_official 363:12a245e5c745 2485 __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
mbed_official 363:12a245e5c745 2486 };
mbed_official 363:12a245e5c745 2487 } LCD_Type, *LCD_MemMapPtr;
mbed_official 363:12a245e5c745 2488
mbed_official 363:12a245e5c745 2489 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 2490 -- LCD - Register accessor macros
mbed_official 363:12a245e5c745 2491 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 2492
mbed_official 363:12a245e5c745 2493 /*!
mbed_official 363:12a245e5c745 2494 * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
mbed_official 363:12a245e5c745 2495 * @{
mbed_official 363:12a245e5c745 2496 */
mbed_official 363:12a245e5c745 2497
mbed_official 363:12a245e5c745 2498
mbed_official 363:12a245e5c745 2499 /* LCD - Register accessors */
mbed_official 363:12a245e5c745 2500 #define LCD_GCR_REG(base) ((base)->GCR)
mbed_official 363:12a245e5c745 2501 #define LCD_AR_REG(base) ((base)->AR)
mbed_official 363:12a245e5c745 2502 #define LCD_FDCR_REG(base) ((base)->FDCR)
mbed_official 363:12a245e5c745 2503 #define LCD_FDSR_REG(base) ((base)->FDSR)
mbed_official 363:12a245e5c745 2504 #define LCD_PEN_REG(base,index) ((base)->PEN[index])
mbed_official 363:12a245e5c745 2505 #define LCD_BPEN_REG(base,index) ((base)->BPEN[index])
mbed_official 363:12a245e5c745 2506 #define LCD_WF_REG(base,index2) ((base)->WF[index2])
mbed_official 363:12a245e5c745 2507 #define LCD_WF8B_REG(base,index2) ((base)->WF8B[index2])
mbed_official 363:12a245e5c745 2508
mbed_official 363:12a245e5c745 2509 /*!
mbed_official 363:12a245e5c745 2510 * @}
mbed_official 363:12a245e5c745 2511 */ /* end of group LCD_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 2512
mbed_official 363:12a245e5c745 2513
mbed_official 363:12a245e5c745 2514 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 2515 -- LCD Register Masks
mbed_official 363:12a245e5c745 2516 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 2517
mbed_official 363:12a245e5c745 2518 /*!
mbed_official 363:12a245e5c745 2519 * @addtogroup LCD_Register_Masks LCD Register Masks
mbed_official 363:12a245e5c745 2520 * @{
mbed_official 363:12a245e5c745 2521 */
mbed_official 363:12a245e5c745 2522
mbed_official 363:12a245e5c745 2523 /* GCR Bit Fields */
mbed_official 363:12a245e5c745 2524 #define LCD_GCR_DUTY_MASK 0x7u
mbed_official 363:12a245e5c745 2525 #define LCD_GCR_DUTY_SHIFT 0
mbed_official 363:12a245e5c745 2526 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
mbed_official 363:12a245e5c745 2527 #define LCD_GCR_LCLK_MASK 0x38u
mbed_official 363:12a245e5c745 2528 #define LCD_GCR_LCLK_SHIFT 3
mbed_official 363:12a245e5c745 2529 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
mbed_official 363:12a245e5c745 2530 #define LCD_GCR_SOURCE_MASK 0x40u
mbed_official 363:12a245e5c745 2531 #define LCD_GCR_SOURCE_SHIFT 6
mbed_official 363:12a245e5c745 2532 #define LCD_GCR_LCDEN_MASK 0x80u
mbed_official 363:12a245e5c745 2533 #define LCD_GCR_LCDEN_SHIFT 7
mbed_official 363:12a245e5c745 2534 #define LCD_GCR_LCDSTP_MASK 0x100u
mbed_official 363:12a245e5c745 2535 #define LCD_GCR_LCDSTP_SHIFT 8
mbed_official 363:12a245e5c745 2536 #define LCD_GCR_LCDDOZE_MASK 0x200u
mbed_official 363:12a245e5c745 2537 #define LCD_GCR_LCDDOZE_SHIFT 9
mbed_official 363:12a245e5c745 2538 #define LCD_GCR_FFR_MASK 0x400u
mbed_official 363:12a245e5c745 2539 #define LCD_GCR_FFR_SHIFT 10
mbed_official 363:12a245e5c745 2540 #define LCD_GCR_ALTSOURCE_MASK 0x800u
mbed_official 363:12a245e5c745 2541 #define LCD_GCR_ALTSOURCE_SHIFT 11
mbed_official 363:12a245e5c745 2542 #define LCD_GCR_ALTDIV_MASK 0x3000u
mbed_official 363:12a245e5c745 2543 #define LCD_GCR_ALTDIV_SHIFT 12
mbed_official 363:12a245e5c745 2544 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
mbed_official 363:12a245e5c745 2545 #define LCD_GCR_FDCIEN_MASK 0x4000u
mbed_official 363:12a245e5c745 2546 #define LCD_GCR_FDCIEN_SHIFT 14
mbed_official 363:12a245e5c745 2547 #define LCD_GCR_PADSAFE_MASK 0x8000u
mbed_official 363:12a245e5c745 2548 #define LCD_GCR_PADSAFE_SHIFT 15
mbed_official 363:12a245e5c745 2549 #define LCD_GCR_VSUPPLY_MASK 0x20000u
mbed_official 363:12a245e5c745 2550 #define LCD_GCR_VSUPPLY_SHIFT 17
mbed_official 363:12a245e5c745 2551 #define LCD_GCR_LADJ_MASK 0x300000u
mbed_official 363:12a245e5c745 2552 #define LCD_GCR_LADJ_SHIFT 20
mbed_official 363:12a245e5c745 2553 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
mbed_official 363:12a245e5c745 2554 #define LCD_GCR_CPSEL_MASK 0x800000u
mbed_official 363:12a245e5c745 2555 #define LCD_GCR_CPSEL_SHIFT 23
mbed_official 363:12a245e5c745 2556 #define LCD_GCR_RVTRIM_MASK 0xF000000u
mbed_official 363:12a245e5c745 2557 #define LCD_GCR_RVTRIM_SHIFT 24
mbed_official 363:12a245e5c745 2558 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
mbed_official 363:12a245e5c745 2559 #define LCD_GCR_RVEN_MASK 0x80000000u
mbed_official 363:12a245e5c745 2560 #define LCD_GCR_RVEN_SHIFT 31
mbed_official 363:12a245e5c745 2561 /* AR Bit Fields */
mbed_official 363:12a245e5c745 2562 #define LCD_AR_BRATE_MASK 0x7u
mbed_official 363:12a245e5c745 2563 #define LCD_AR_BRATE_SHIFT 0
mbed_official 363:12a245e5c745 2564 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
mbed_official 363:12a245e5c745 2565 #define LCD_AR_BMODE_MASK 0x8u
mbed_official 363:12a245e5c745 2566 #define LCD_AR_BMODE_SHIFT 3
mbed_official 363:12a245e5c745 2567 #define LCD_AR_BLANK_MASK 0x20u
mbed_official 363:12a245e5c745 2568 #define LCD_AR_BLANK_SHIFT 5
mbed_official 363:12a245e5c745 2569 #define LCD_AR_ALT_MASK 0x40u
mbed_official 363:12a245e5c745 2570 #define LCD_AR_ALT_SHIFT 6
mbed_official 363:12a245e5c745 2571 #define LCD_AR_BLINK_MASK 0x80u
mbed_official 363:12a245e5c745 2572 #define LCD_AR_BLINK_SHIFT 7
mbed_official 363:12a245e5c745 2573 /* FDCR Bit Fields */
mbed_official 363:12a245e5c745 2574 #define LCD_FDCR_FDPINID_MASK 0x3Fu
mbed_official 363:12a245e5c745 2575 #define LCD_FDCR_FDPINID_SHIFT 0
mbed_official 363:12a245e5c745 2576 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
mbed_official 363:12a245e5c745 2577 #define LCD_FDCR_FDBPEN_MASK 0x40u
mbed_official 363:12a245e5c745 2578 #define LCD_FDCR_FDBPEN_SHIFT 6
mbed_official 363:12a245e5c745 2579 #define LCD_FDCR_FDEN_MASK 0x80u
mbed_official 363:12a245e5c745 2580 #define LCD_FDCR_FDEN_SHIFT 7
mbed_official 363:12a245e5c745 2581 #define LCD_FDCR_FDSWW_MASK 0xE00u
mbed_official 363:12a245e5c745 2582 #define LCD_FDCR_FDSWW_SHIFT 9
mbed_official 363:12a245e5c745 2583 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
mbed_official 363:12a245e5c745 2584 #define LCD_FDCR_FDPRS_MASK 0x7000u
mbed_official 363:12a245e5c745 2585 #define LCD_FDCR_FDPRS_SHIFT 12
mbed_official 363:12a245e5c745 2586 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
mbed_official 363:12a245e5c745 2587 /* FDSR Bit Fields */
mbed_official 363:12a245e5c745 2588 #define LCD_FDSR_FDCNT_MASK 0xFFu
mbed_official 363:12a245e5c745 2589 #define LCD_FDSR_FDCNT_SHIFT 0
mbed_official 363:12a245e5c745 2590 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
mbed_official 363:12a245e5c745 2591 #define LCD_FDSR_FDCF_MASK 0x8000u
mbed_official 363:12a245e5c745 2592 #define LCD_FDSR_FDCF_SHIFT 15
mbed_official 363:12a245e5c745 2593 /* PEN Bit Fields */
mbed_official 363:12a245e5c745 2594 #define LCD_PEN_PEN_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 2595 #define LCD_PEN_PEN_SHIFT 0
mbed_official 363:12a245e5c745 2596 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
mbed_official 363:12a245e5c745 2597 /* BPEN Bit Fields */
mbed_official 363:12a245e5c745 2598 #define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 2599 #define LCD_BPEN_BPEN_SHIFT 0
mbed_official 363:12a245e5c745 2600 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
mbed_official 363:12a245e5c745 2601 /* WF Bit Fields */
mbed_official 363:12a245e5c745 2602 #define LCD_WF_WF0_MASK 0xFFu
mbed_official 363:12a245e5c745 2603 #define LCD_WF_WF0_SHIFT 0
mbed_official 363:12a245e5c745 2604 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
mbed_official 363:12a245e5c745 2605 #define LCD_WF_WF60_MASK 0xFFu
mbed_official 363:12a245e5c745 2606 #define LCD_WF_WF60_SHIFT 0
mbed_official 363:12a245e5c745 2607 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
mbed_official 363:12a245e5c745 2608 #define LCD_WF_WF56_MASK 0xFFu
mbed_official 363:12a245e5c745 2609 #define LCD_WF_WF56_SHIFT 0
mbed_official 363:12a245e5c745 2610 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
mbed_official 363:12a245e5c745 2611 #define LCD_WF_WF52_MASK 0xFFu
mbed_official 363:12a245e5c745 2612 #define LCD_WF_WF52_SHIFT 0
mbed_official 363:12a245e5c745 2613 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
mbed_official 363:12a245e5c745 2614 #define LCD_WF_WF4_MASK 0xFFu
mbed_official 363:12a245e5c745 2615 #define LCD_WF_WF4_SHIFT 0
mbed_official 363:12a245e5c745 2616 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
mbed_official 363:12a245e5c745 2617 #define LCD_WF_WF48_MASK 0xFFu
mbed_official 363:12a245e5c745 2618 #define LCD_WF_WF48_SHIFT 0
mbed_official 363:12a245e5c745 2619 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
mbed_official 363:12a245e5c745 2620 #define LCD_WF_WF44_MASK 0xFFu
mbed_official 363:12a245e5c745 2621 #define LCD_WF_WF44_SHIFT 0
mbed_official 363:12a245e5c745 2622 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
mbed_official 363:12a245e5c745 2623 #define LCD_WF_WF40_MASK 0xFFu
mbed_official 363:12a245e5c745 2624 #define LCD_WF_WF40_SHIFT 0
mbed_official 363:12a245e5c745 2625 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
mbed_official 363:12a245e5c745 2626 #define LCD_WF_WF8_MASK 0xFFu
mbed_official 363:12a245e5c745 2627 #define LCD_WF_WF8_SHIFT 0
mbed_official 363:12a245e5c745 2628 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
mbed_official 363:12a245e5c745 2629 #define LCD_WF_WF36_MASK 0xFFu
mbed_official 363:12a245e5c745 2630 #define LCD_WF_WF36_SHIFT 0
mbed_official 363:12a245e5c745 2631 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
mbed_official 363:12a245e5c745 2632 #define LCD_WF_WF32_MASK 0xFFu
mbed_official 363:12a245e5c745 2633 #define LCD_WF_WF32_SHIFT 0
mbed_official 363:12a245e5c745 2634 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
mbed_official 363:12a245e5c745 2635 #define LCD_WF_WF28_MASK 0xFFu
mbed_official 363:12a245e5c745 2636 #define LCD_WF_WF28_SHIFT 0
mbed_official 363:12a245e5c745 2637 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
mbed_official 363:12a245e5c745 2638 #define LCD_WF_WF12_MASK 0xFFu
mbed_official 363:12a245e5c745 2639 #define LCD_WF_WF12_SHIFT 0
mbed_official 363:12a245e5c745 2640 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
mbed_official 363:12a245e5c745 2641 #define LCD_WF_WF24_MASK 0xFFu
mbed_official 363:12a245e5c745 2642 #define LCD_WF_WF24_SHIFT 0
mbed_official 363:12a245e5c745 2643 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
mbed_official 363:12a245e5c745 2644 #define LCD_WF_WF20_MASK 0xFFu
mbed_official 363:12a245e5c745 2645 #define LCD_WF_WF20_SHIFT 0
mbed_official 363:12a245e5c745 2646 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
mbed_official 363:12a245e5c745 2647 #define LCD_WF_WF16_MASK 0xFFu
mbed_official 363:12a245e5c745 2648 #define LCD_WF_WF16_SHIFT 0
mbed_official 363:12a245e5c745 2649 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
mbed_official 363:12a245e5c745 2650 #define LCD_WF_WF5_MASK 0xFF00u
mbed_official 363:12a245e5c745 2651 #define LCD_WF_WF5_SHIFT 8
mbed_official 363:12a245e5c745 2652 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
mbed_official 363:12a245e5c745 2653 #define LCD_WF_WF49_MASK 0xFF00u
mbed_official 363:12a245e5c745 2654 #define LCD_WF_WF49_SHIFT 8
mbed_official 363:12a245e5c745 2655 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
mbed_official 363:12a245e5c745 2656 #define LCD_WF_WF45_MASK 0xFF00u
mbed_official 363:12a245e5c745 2657 #define LCD_WF_WF45_SHIFT 8
mbed_official 363:12a245e5c745 2658 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
mbed_official 363:12a245e5c745 2659 #define LCD_WF_WF61_MASK 0xFF00u
mbed_official 363:12a245e5c745 2660 #define LCD_WF_WF61_SHIFT 8
mbed_official 363:12a245e5c745 2661 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
mbed_official 363:12a245e5c745 2662 #define LCD_WF_WF25_MASK 0xFF00u
mbed_official 363:12a245e5c745 2663 #define LCD_WF_WF25_SHIFT 8
mbed_official 363:12a245e5c745 2664 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
mbed_official 363:12a245e5c745 2665 #define LCD_WF_WF17_MASK 0xFF00u
mbed_official 363:12a245e5c745 2666 #define LCD_WF_WF17_SHIFT 8
mbed_official 363:12a245e5c745 2667 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
mbed_official 363:12a245e5c745 2668 #define LCD_WF_WF41_MASK 0xFF00u
mbed_official 363:12a245e5c745 2669 #define LCD_WF_WF41_SHIFT 8
mbed_official 363:12a245e5c745 2670 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
mbed_official 363:12a245e5c745 2671 #define LCD_WF_WF13_MASK 0xFF00u
mbed_official 363:12a245e5c745 2672 #define LCD_WF_WF13_SHIFT 8
mbed_official 363:12a245e5c745 2673 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
mbed_official 363:12a245e5c745 2674 #define LCD_WF_WF57_MASK 0xFF00u
mbed_official 363:12a245e5c745 2675 #define LCD_WF_WF57_SHIFT 8
mbed_official 363:12a245e5c745 2676 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
mbed_official 363:12a245e5c745 2677 #define LCD_WF_WF53_MASK 0xFF00u
mbed_official 363:12a245e5c745 2678 #define LCD_WF_WF53_SHIFT 8
mbed_official 363:12a245e5c745 2679 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
mbed_official 363:12a245e5c745 2680 #define LCD_WF_WF37_MASK 0xFF00u
mbed_official 363:12a245e5c745 2681 #define LCD_WF_WF37_SHIFT 8
mbed_official 363:12a245e5c745 2682 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
mbed_official 363:12a245e5c745 2683 #define LCD_WF_WF9_MASK 0xFF00u
mbed_official 363:12a245e5c745 2684 #define LCD_WF_WF9_SHIFT 8
mbed_official 363:12a245e5c745 2685 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
mbed_official 363:12a245e5c745 2686 #define LCD_WF_WF1_MASK 0xFF00u
mbed_official 363:12a245e5c745 2687 #define LCD_WF_WF1_SHIFT 8
mbed_official 363:12a245e5c745 2688 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
mbed_official 363:12a245e5c745 2689 #define LCD_WF_WF29_MASK 0xFF00u
mbed_official 363:12a245e5c745 2690 #define LCD_WF_WF29_SHIFT 8
mbed_official 363:12a245e5c745 2691 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
mbed_official 363:12a245e5c745 2692 #define LCD_WF_WF33_MASK 0xFF00u
mbed_official 363:12a245e5c745 2693 #define LCD_WF_WF33_SHIFT 8
mbed_official 363:12a245e5c745 2694 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
mbed_official 363:12a245e5c745 2695 #define LCD_WF_WF21_MASK 0xFF00u
mbed_official 363:12a245e5c745 2696 #define LCD_WF_WF21_SHIFT 8
mbed_official 363:12a245e5c745 2697 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
mbed_official 363:12a245e5c745 2698 #define LCD_WF_WF26_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2699 #define LCD_WF_WF26_SHIFT 16
mbed_official 363:12a245e5c745 2700 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
mbed_official 363:12a245e5c745 2701 #define LCD_WF_WF46_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2702 #define LCD_WF_WF46_SHIFT 16
mbed_official 363:12a245e5c745 2703 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
mbed_official 363:12a245e5c745 2704 #define LCD_WF_WF6_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2705 #define LCD_WF_WF6_SHIFT 16
mbed_official 363:12a245e5c745 2706 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
mbed_official 363:12a245e5c745 2707 #define LCD_WF_WF42_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2708 #define LCD_WF_WF42_SHIFT 16
mbed_official 363:12a245e5c745 2709 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
mbed_official 363:12a245e5c745 2710 #define LCD_WF_WF18_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2711 #define LCD_WF_WF18_SHIFT 16
mbed_official 363:12a245e5c745 2712 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
mbed_official 363:12a245e5c745 2713 #define LCD_WF_WF38_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2714 #define LCD_WF_WF38_SHIFT 16
mbed_official 363:12a245e5c745 2715 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
mbed_official 363:12a245e5c745 2716 #define LCD_WF_WF22_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2717 #define LCD_WF_WF22_SHIFT 16
mbed_official 363:12a245e5c745 2718 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
mbed_official 363:12a245e5c745 2719 #define LCD_WF_WF34_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2720 #define LCD_WF_WF34_SHIFT 16
mbed_official 363:12a245e5c745 2721 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
mbed_official 363:12a245e5c745 2722 #define LCD_WF_WF50_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2723 #define LCD_WF_WF50_SHIFT 16
mbed_official 363:12a245e5c745 2724 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
mbed_official 363:12a245e5c745 2725 #define LCD_WF_WF14_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2726 #define LCD_WF_WF14_SHIFT 16
mbed_official 363:12a245e5c745 2727 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
mbed_official 363:12a245e5c745 2728 #define LCD_WF_WF54_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2729 #define LCD_WF_WF54_SHIFT 16
mbed_official 363:12a245e5c745 2730 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
mbed_official 363:12a245e5c745 2731 #define LCD_WF_WF2_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2732 #define LCD_WF_WF2_SHIFT 16
mbed_official 363:12a245e5c745 2733 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
mbed_official 363:12a245e5c745 2734 #define LCD_WF_WF58_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2735 #define LCD_WF_WF58_SHIFT 16
mbed_official 363:12a245e5c745 2736 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
mbed_official 363:12a245e5c745 2737 #define LCD_WF_WF30_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2738 #define LCD_WF_WF30_SHIFT 16
mbed_official 363:12a245e5c745 2739 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
mbed_official 363:12a245e5c745 2740 #define LCD_WF_WF62_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2741 #define LCD_WF_WF62_SHIFT 16
mbed_official 363:12a245e5c745 2742 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
mbed_official 363:12a245e5c745 2743 #define LCD_WF_WF10_MASK 0xFF0000u
mbed_official 363:12a245e5c745 2744 #define LCD_WF_WF10_SHIFT 16
mbed_official 363:12a245e5c745 2745 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
mbed_official 363:12a245e5c745 2746 #define LCD_WF_WF63_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2747 #define LCD_WF_WF63_SHIFT 24
mbed_official 363:12a245e5c745 2748 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
mbed_official 363:12a245e5c745 2749 #define LCD_WF_WF59_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2750 #define LCD_WF_WF59_SHIFT 24
mbed_official 363:12a245e5c745 2751 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
mbed_official 363:12a245e5c745 2752 #define LCD_WF_WF55_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2753 #define LCD_WF_WF55_SHIFT 24
mbed_official 363:12a245e5c745 2754 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
mbed_official 363:12a245e5c745 2755 #define LCD_WF_WF3_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2756 #define LCD_WF_WF3_SHIFT 24
mbed_official 363:12a245e5c745 2757 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
mbed_official 363:12a245e5c745 2758 #define LCD_WF_WF51_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2759 #define LCD_WF_WF51_SHIFT 24
mbed_official 363:12a245e5c745 2760 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
mbed_official 363:12a245e5c745 2761 #define LCD_WF_WF47_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2762 #define LCD_WF_WF47_SHIFT 24
mbed_official 363:12a245e5c745 2763 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
mbed_official 363:12a245e5c745 2764 #define LCD_WF_WF43_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2765 #define LCD_WF_WF43_SHIFT 24
mbed_official 363:12a245e5c745 2766 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
mbed_official 363:12a245e5c745 2767 #define LCD_WF_WF7_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2768 #define LCD_WF_WF7_SHIFT 24
mbed_official 363:12a245e5c745 2769 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
mbed_official 363:12a245e5c745 2770 #define LCD_WF_WF39_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2771 #define LCD_WF_WF39_SHIFT 24
mbed_official 363:12a245e5c745 2772 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
mbed_official 363:12a245e5c745 2773 #define LCD_WF_WF35_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2774 #define LCD_WF_WF35_SHIFT 24
mbed_official 363:12a245e5c745 2775 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
mbed_official 363:12a245e5c745 2776 #define LCD_WF_WF31_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2777 #define LCD_WF_WF31_SHIFT 24
mbed_official 363:12a245e5c745 2778 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
mbed_official 363:12a245e5c745 2779 #define LCD_WF_WF11_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2780 #define LCD_WF_WF11_SHIFT 24
mbed_official 363:12a245e5c745 2781 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
mbed_official 363:12a245e5c745 2782 #define LCD_WF_WF27_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2783 #define LCD_WF_WF27_SHIFT 24
mbed_official 363:12a245e5c745 2784 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
mbed_official 363:12a245e5c745 2785 #define LCD_WF_WF23_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2786 #define LCD_WF_WF23_SHIFT 24
mbed_official 363:12a245e5c745 2787 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
mbed_official 363:12a245e5c745 2788 #define LCD_WF_WF19_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2789 #define LCD_WF_WF19_SHIFT 24
mbed_official 363:12a245e5c745 2790 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
mbed_official 363:12a245e5c745 2791 #define LCD_WF_WF15_MASK 0xFF000000u
mbed_official 363:12a245e5c745 2792 #define LCD_WF_WF15_SHIFT 24
mbed_official 363:12a245e5c745 2793 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
mbed_official 363:12a245e5c745 2794 /* WF8B Bit Fields */
mbed_official 363:12a245e5c745 2795 #define LCD_WF8B_BPALCD0_MASK 0x1u
mbed_official 363:12a245e5c745 2796 #define LCD_WF8B_BPALCD0_SHIFT 0
mbed_official 363:12a245e5c745 2797 #define LCD_WF8B_BPALCD63_MASK 0x1u
mbed_official 363:12a245e5c745 2798 #define LCD_WF8B_BPALCD63_SHIFT 0
mbed_official 363:12a245e5c745 2799 #define LCD_WF8B_BPALCD62_MASK 0x1u
mbed_official 363:12a245e5c745 2800 #define LCD_WF8B_BPALCD62_SHIFT 0
mbed_official 363:12a245e5c745 2801 #define LCD_WF8B_BPALCD61_MASK 0x1u
mbed_official 363:12a245e5c745 2802 #define LCD_WF8B_BPALCD61_SHIFT 0
mbed_official 363:12a245e5c745 2803 #define LCD_WF8B_BPALCD60_MASK 0x1u
mbed_official 363:12a245e5c745 2804 #define LCD_WF8B_BPALCD60_SHIFT 0
mbed_official 363:12a245e5c745 2805 #define LCD_WF8B_BPALCD59_MASK 0x1u
mbed_official 363:12a245e5c745 2806 #define LCD_WF8B_BPALCD59_SHIFT 0
mbed_official 363:12a245e5c745 2807 #define LCD_WF8B_BPALCD58_MASK 0x1u
mbed_official 363:12a245e5c745 2808 #define LCD_WF8B_BPALCD58_SHIFT 0
mbed_official 363:12a245e5c745 2809 #define LCD_WF8B_BPALCD57_MASK 0x1u
mbed_official 363:12a245e5c745 2810 #define LCD_WF8B_BPALCD57_SHIFT 0
mbed_official 363:12a245e5c745 2811 #define LCD_WF8B_BPALCD1_MASK 0x1u
mbed_official 363:12a245e5c745 2812 #define LCD_WF8B_BPALCD1_SHIFT 0
mbed_official 363:12a245e5c745 2813 #define LCD_WF8B_BPALCD56_MASK 0x1u
mbed_official 363:12a245e5c745 2814 #define LCD_WF8B_BPALCD56_SHIFT 0
mbed_official 363:12a245e5c745 2815 #define LCD_WF8B_BPALCD55_MASK 0x1u
mbed_official 363:12a245e5c745 2816 #define LCD_WF8B_BPALCD55_SHIFT 0
mbed_official 363:12a245e5c745 2817 #define LCD_WF8B_BPALCD54_MASK 0x1u
mbed_official 363:12a245e5c745 2818 #define LCD_WF8B_BPALCD54_SHIFT 0
mbed_official 363:12a245e5c745 2819 #define LCD_WF8B_BPALCD53_MASK 0x1u
mbed_official 363:12a245e5c745 2820 #define LCD_WF8B_BPALCD53_SHIFT 0
mbed_official 363:12a245e5c745 2821 #define LCD_WF8B_BPALCD52_MASK 0x1u
mbed_official 363:12a245e5c745 2822 #define LCD_WF8B_BPALCD52_SHIFT 0
mbed_official 363:12a245e5c745 2823 #define LCD_WF8B_BPALCD51_MASK 0x1u
mbed_official 363:12a245e5c745 2824 #define LCD_WF8B_BPALCD51_SHIFT 0
mbed_official 363:12a245e5c745 2825 #define LCD_WF8B_BPALCD50_MASK 0x1u
mbed_official 363:12a245e5c745 2826 #define LCD_WF8B_BPALCD50_SHIFT 0
mbed_official 363:12a245e5c745 2827 #define LCD_WF8B_BPALCD2_MASK 0x1u
mbed_official 363:12a245e5c745 2828 #define LCD_WF8B_BPALCD2_SHIFT 0
mbed_official 363:12a245e5c745 2829 #define LCD_WF8B_BPALCD49_MASK 0x1u
mbed_official 363:12a245e5c745 2830 #define LCD_WF8B_BPALCD49_SHIFT 0
mbed_official 363:12a245e5c745 2831 #define LCD_WF8B_BPALCD48_MASK 0x1u
mbed_official 363:12a245e5c745 2832 #define LCD_WF8B_BPALCD48_SHIFT 0
mbed_official 363:12a245e5c745 2833 #define LCD_WF8B_BPALCD47_MASK 0x1u
mbed_official 363:12a245e5c745 2834 #define LCD_WF8B_BPALCD47_SHIFT 0
mbed_official 363:12a245e5c745 2835 #define LCD_WF8B_BPALCD46_MASK 0x1u
mbed_official 363:12a245e5c745 2836 #define LCD_WF8B_BPALCD46_SHIFT 0
mbed_official 363:12a245e5c745 2837 #define LCD_WF8B_BPALCD45_MASK 0x1u
mbed_official 363:12a245e5c745 2838 #define LCD_WF8B_BPALCD45_SHIFT 0
mbed_official 363:12a245e5c745 2839 #define LCD_WF8B_BPALCD44_MASK 0x1u
mbed_official 363:12a245e5c745 2840 #define LCD_WF8B_BPALCD44_SHIFT 0
mbed_official 363:12a245e5c745 2841 #define LCD_WF8B_BPALCD43_MASK 0x1u
mbed_official 363:12a245e5c745 2842 #define LCD_WF8B_BPALCD43_SHIFT 0
mbed_official 363:12a245e5c745 2843 #define LCD_WF8B_BPALCD3_MASK 0x1u
mbed_official 363:12a245e5c745 2844 #define LCD_WF8B_BPALCD3_SHIFT 0
mbed_official 363:12a245e5c745 2845 #define LCD_WF8B_BPALCD42_MASK 0x1u
mbed_official 363:12a245e5c745 2846 #define LCD_WF8B_BPALCD42_SHIFT 0
mbed_official 363:12a245e5c745 2847 #define LCD_WF8B_BPALCD41_MASK 0x1u
mbed_official 363:12a245e5c745 2848 #define LCD_WF8B_BPALCD41_SHIFT 0
mbed_official 363:12a245e5c745 2849 #define LCD_WF8B_BPALCD40_MASK 0x1u
mbed_official 363:12a245e5c745 2850 #define LCD_WF8B_BPALCD40_SHIFT 0
mbed_official 363:12a245e5c745 2851 #define LCD_WF8B_BPALCD39_MASK 0x1u
mbed_official 363:12a245e5c745 2852 #define LCD_WF8B_BPALCD39_SHIFT 0
mbed_official 363:12a245e5c745 2853 #define LCD_WF8B_BPALCD38_MASK 0x1u
mbed_official 363:12a245e5c745 2854 #define LCD_WF8B_BPALCD38_SHIFT 0
mbed_official 363:12a245e5c745 2855 #define LCD_WF8B_BPALCD37_MASK 0x1u
mbed_official 363:12a245e5c745 2856 #define LCD_WF8B_BPALCD37_SHIFT 0
mbed_official 363:12a245e5c745 2857 #define LCD_WF8B_BPALCD36_MASK 0x1u
mbed_official 363:12a245e5c745 2858 #define LCD_WF8B_BPALCD36_SHIFT 0
mbed_official 363:12a245e5c745 2859 #define LCD_WF8B_BPALCD4_MASK 0x1u
mbed_official 363:12a245e5c745 2860 #define LCD_WF8B_BPALCD4_SHIFT 0
mbed_official 363:12a245e5c745 2861 #define LCD_WF8B_BPALCD35_MASK 0x1u
mbed_official 363:12a245e5c745 2862 #define LCD_WF8B_BPALCD35_SHIFT 0
mbed_official 363:12a245e5c745 2863 #define LCD_WF8B_BPALCD34_MASK 0x1u
mbed_official 363:12a245e5c745 2864 #define LCD_WF8B_BPALCD34_SHIFT 0
mbed_official 363:12a245e5c745 2865 #define LCD_WF8B_BPALCD33_MASK 0x1u
mbed_official 363:12a245e5c745 2866 #define LCD_WF8B_BPALCD33_SHIFT 0
mbed_official 363:12a245e5c745 2867 #define LCD_WF8B_BPALCD32_MASK 0x1u
mbed_official 363:12a245e5c745 2868 #define LCD_WF8B_BPALCD32_SHIFT 0
mbed_official 363:12a245e5c745 2869 #define LCD_WF8B_BPALCD31_MASK 0x1u
mbed_official 363:12a245e5c745 2870 #define LCD_WF8B_BPALCD31_SHIFT 0
mbed_official 363:12a245e5c745 2871 #define LCD_WF8B_BPALCD30_MASK 0x1u
mbed_official 363:12a245e5c745 2872 #define LCD_WF8B_BPALCD30_SHIFT 0
mbed_official 363:12a245e5c745 2873 #define LCD_WF8B_BPALCD29_MASK 0x1u
mbed_official 363:12a245e5c745 2874 #define LCD_WF8B_BPALCD29_SHIFT 0
mbed_official 363:12a245e5c745 2875 #define LCD_WF8B_BPALCD5_MASK 0x1u
mbed_official 363:12a245e5c745 2876 #define LCD_WF8B_BPALCD5_SHIFT 0
mbed_official 363:12a245e5c745 2877 #define LCD_WF8B_BPALCD28_MASK 0x1u
mbed_official 363:12a245e5c745 2878 #define LCD_WF8B_BPALCD28_SHIFT 0
mbed_official 363:12a245e5c745 2879 #define LCD_WF8B_BPALCD27_MASK 0x1u
mbed_official 363:12a245e5c745 2880 #define LCD_WF8B_BPALCD27_SHIFT 0
mbed_official 363:12a245e5c745 2881 #define LCD_WF8B_BPALCD26_MASK 0x1u
mbed_official 363:12a245e5c745 2882 #define LCD_WF8B_BPALCD26_SHIFT 0
mbed_official 363:12a245e5c745 2883 #define LCD_WF8B_BPALCD25_MASK 0x1u
mbed_official 363:12a245e5c745 2884 #define LCD_WF8B_BPALCD25_SHIFT 0
mbed_official 363:12a245e5c745 2885 #define LCD_WF8B_BPALCD24_MASK 0x1u
mbed_official 363:12a245e5c745 2886 #define LCD_WF8B_BPALCD24_SHIFT 0
mbed_official 363:12a245e5c745 2887 #define LCD_WF8B_BPALCD23_MASK 0x1u
mbed_official 363:12a245e5c745 2888 #define LCD_WF8B_BPALCD23_SHIFT 0
mbed_official 363:12a245e5c745 2889 #define LCD_WF8B_BPALCD22_MASK 0x1u
mbed_official 363:12a245e5c745 2890 #define LCD_WF8B_BPALCD22_SHIFT 0
mbed_official 363:12a245e5c745 2891 #define LCD_WF8B_BPALCD6_MASK 0x1u
mbed_official 363:12a245e5c745 2892 #define LCD_WF8B_BPALCD6_SHIFT 0
mbed_official 363:12a245e5c745 2893 #define LCD_WF8B_BPALCD21_MASK 0x1u
mbed_official 363:12a245e5c745 2894 #define LCD_WF8B_BPALCD21_SHIFT 0
mbed_official 363:12a245e5c745 2895 #define LCD_WF8B_BPALCD20_MASK 0x1u
mbed_official 363:12a245e5c745 2896 #define LCD_WF8B_BPALCD20_SHIFT 0
mbed_official 363:12a245e5c745 2897 #define LCD_WF8B_BPALCD19_MASK 0x1u
mbed_official 363:12a245e5c745 2898 #define LCD_WF8B_BPALCD19_SHIFT 0
mbed_official 363:12a245e5c745 2899 #define LCD_WF8B_BPALCD18_MASK 0x1u
mbed_official 363:12a245e5c745 2900 #define LCD_WF8B_BPALCD18_SHIFT 0
mbed_official 363:12a245e5c745 2901 #define LCD_WF8B_BPALCD17_MASK 0x1u
mbed_official 363:12a245e5c745 2902 #define LCD_WF8B_BPALCD17_SHIFT 0
mbed_official 363:12a245e5c745 2903 #define LCD_WF8B_BPALCD16_MASK 0x1u
mbed_official 363:12a245e5c745 2904 #define LCD_WF8B_BPALCD16_SHIFT 0
mbed_official 363:12a245e5c745 2905 #define LCD_WF8B_BPALCD15_MASK 0x1u
mbed_official 363:12a245e5c745 2906 #define LCD_WF8B_BPALCD15_SHIFT 0
mbed_official 363:12a245e5c745 2907 #define LCD_WF8B_BPALCD7_MASK 0x1u
mbed_official 363:12a245e5c745 2908 #define LCD_WF8B_BPALCD7_SHIFT 0
mbed_official 363:12a245e5c745 2909 #define LCD_WF8B_BPALCD14_MASK 0x1u
mbed_official 363:12a245e5c745 2910 #define LCD_WF8B_BPALCD14_SHIFT 0
mbed_official 363:12a245e5c745 2911 #define LCD_WF8B_BPALCD13_MASK 0x1u
mbed_official 363:12a245e5c745 2912 #define LCD_WF8B_BPALCD13_SHIFT 0
mbed_official 363:12a245e5c745 2913 #define LCD_WF8B_BPALCD12_MASK 0x1u
mbed_official 363:12a245e5c745 2914 #define LCD_WF8B_BPALCD12_SHIFT 0
mbed_official 363:12a245e5c745 2915 #define LCD_WF8B_BPALCD11_MASK 0x1u
mbed_official 363:12a245e5c745 2916 #define LCD_WF8B_BPALCD11_SHIFT 0
mbed_official 363:12a245e5c745 2917 #define LCD_WF8B_BPALCD10_MASK 0x1u
mbed_official 363:12a245e5c745 2918 #define LCD_WF8B_BPALCD10_SHIFT 0
mbed_official 363:12a245e5c745 2919 #define LCD_WF8B_BPALCD9_MASK 0x1u
mbed_official 363:12a245e5c745 2920 #define LCD_WF8B_BPALCD9_SHIFT 0
mbed_official 363:12a245e5c745 2921 #define LCD_WF8B_BPALCD8_MASK 0x1u
mbed_official 363:12a245e5c745 2922 #define LCD_WF8B_BPALCD8_SHIFT 0
mbed_official 363:12a245e5c745 2923 #define LCD_WF8B_BPBLCD1_MASK 0x2u
mbed_official 363:12a245e5c745 2924 #define LCD_WF8B_BPBLCD1_SHIFT 1
mbed_official 363:12a245e5c745 2925 #define LCD_WF8B_BPBLCD32_MASK 0x2u
mbed_official 363:12a245e5c745 2926 #define LCD_WF8B_BPBLCD32_SHIFT 1
mbed_official 363:12a245e5c745 2927 #define LCD_WF8B_BPBLCD30_MASK 0x2u
mbed_official 363:12a245e5c745 2928 #define LCD_WF8B_BPBLCD30_SHIFT 1
mbed_official 363:12a245e5c745 2929 #define LCD_WF8B_BPBLCD60_MASK 0x2u
mbed_official 363:12a245e5c745 2930 #define LCD_WF8B_BPBLCD60_SHIFT 1
mbed_official 363:12a245e5c745 2931 #define LCD_WF8B_BPBLCD24_MASK 0x2u
mbed_official 363:12a245e5c745 2932 #define LCD_WF8B_BPBLCD24_SHIFT 1
mbed_official 363:12a245e5c745 2933 #define LCD_WF8B_BPBLCD28_MASK 0x2u
mbed_official 363:12a245e5c745 2934 #define LCD_WF8B_BPBLCD28_SHIFT 1
mbed_official 363:12a245e5c745 2935 #define LCD_WF8B_BPBLCD23_MASK 0x2u
mbed_official 363:12a245e5c745 2936 #define LCD_WF8B_BPBLCD23_SHIFT 1
mbed_official 363:12a245e5c745 2937 #define LCD_WF8B_BPBLCD48_MASK 0x2u
mbed_official 363:12a245e5c745 2938 #define LCD_WF8B_BPBLCD48_SHIFT 1
mbed_official 363:12a245e5c745 2939 #define LCD_WF8B_BPBLCD10_MASK 0x2u
mbed_official 363:12a245e5c745 2940 #define LCD_WF8B_BPBLCD10_SHIFT 1
mbed_official 363:12a245e5c745 2941 #define LCD_WF8B_BPBLCD15_MASK 0x2u
mbed_official 363:12a245e5c745 2942 #define LCD_WF8B_BPBLCD15_SHIFT 1
mbed_official 363:12a245e5c745 2943 #define LCD_WF8B_BPBLCD36_MASK 0x2u
mbed_official 363:12a245e5c745 2944 #define LCD_WF8B_BPBLCD36_SHIFT 1
mbed_official 363:12a245e5c745 2945 #define LCD_WF8B_BPBLCD44_MASK 0x2u
mbed_official 363:12a245e5c745 2946 #define LCD_WF8B_BPBLCD44_SHIFT 1
mbed_official 363:12a245e5c745 2947 #define LCD_WF8B_BPBLCD62_MASK 0x2u
mbed_official 363:12a245e5c745 2948 #define LCD_WF8B_BPBLCD62_SHIFT 1
mbed_official 363:12a245e5c745 2949 #define LCD_WF8B_BPBLCD53_MASK 0x2u
mbed_official 363:12a245e5c745 2950 #define LCD_WF8B_BPBLCD53_SHIFT 1
mbed_official 363:12a245e5c745 2951 #define LCD_WF8B_BPBLCD22_MASK 0x2u
mbed_official 363:12a245e5c745 2952 #define LCD_WF8B_BPBLCD22_SHIFT 1
mbed_official 363:12a245e5c745 2953 #define LCD_WF8B_BPBLCD47_MASK 0x2u
mbed_official 363:12a245e5c745 2954 #define LCD_WF8B_BPBLCD47_SHIFT 1
mbed_official 363:12a245e5c745 2955 #define LCD_WF8B_BPBLCD33_MASK 0x2u
mbed_official 363:12a245e5c745 2956 #define LCD_WF8B_BPBLCD33_SHIFT 1
mbed_official 363:12a245e5c745 2957 #define LCD_WF8B_BPBLCD2_MASK 0x2u
mbed_official 363:12a245e5c745 2958 #define LCD_WF8B_BPBLCD2_SHIFT 1
mbed_official 363:12a245e5c745 2959 #define LCD_WF8B_BPBLCD49_MASK 0x2u
mbed_official 363:12a245e5c745 2960 #define LCD_WF8B_BPBLCD49_SHIFT 1
mbed_official 363:12a245e5c745 2961 #define LCD_WF8B_BPBLCD0_MASK 0x2u
mbed_official 363:12a245e5c745 2962 #define LCD_WF8B_BPBLCD0_SHIFT 1
mbed_official 363:12a245e5c745 2963 #define LCD_WF8B_BPBLCD55_MASK 0x2u
mbed_official 363:12a245e5c745 2964 #define LCD_WF8B_BPBLCD55_SHIFT 1
mbed_official 363:12a245e5c745 2965 #define LCD_WF8B_BPBLCD56_MASK 0x2u
mbed_official 363:12a245e5c745 2966 #define LCD_WF8B_BPBLCD56_SHIFT 1
mbed_official 363:12a245e5c745 2967 #define LCD_WF8B_BPBLCD21_MASK 0x2u
mbed_official 363:12a245e5c745 2968 #define LCD_WF8B_BPBLCD21_SHIFT 1
mbed_official 363:12a245e5c745 2969 #define LCD_WF8B_BPBLCD6_MASK 0x2u
mbed_official 363:12a245e5c745 2970 #define LCD_WF8B_BPBLCD6_SHIFT 1
mbed_official 363:12a245e5c745 2971 #define LCD_WF8B_BPBLCD29_MASK 0x2u
mbed_official 363:12a245e5c745 2972 #define LCD_WF8B_BPBLCD29_SHIFT 1
mbed_official 363:12a245e5c745 2973 #define LCD_WF8B_BPBLCD25_MASK 0x2u
mbed_official 363:12a245e5c745 2974 #define LCD_WF8B_BPBLCD25_SHIFT 1
mbed_official 363:12a245e5c745 2975 #define LCD_WF8B_BPBLCD8_MASK 0x2u
mbed_official 363:12a245e5c745 2976 #define LCD_WF8B_BPBLCD8_SHIFT 1
mbed_official 363:12a245e5c745 2977 #define LCD_WF8B_BPBLCD54_MASK 0x2u
mbed_official 363:12a245e5c745 2978 #define LCD_WF8B_BPBLCD54_SHIFT 1
mbed_official 363:12a245e5c745 2979 #define LCD_WF8B_BPBLCD38_MASK 0x2u
mbed_official 363:12a245e5c745 2980 #define LCD_WF8B_BPBLCD38_SHIFT 1
mbed_official 363:12a245e5c745 2981 #define LCD_WF8B_BPBLCD43_MASK 0x2u
mbed_official 363:12a245e5c745 2982 #define LCD_WF8B_BPBLCD43_SHIFT 1
mbed_official 363:12a245e5c745 2983 #define LCD_WF8B_BPBLCD20_MASK 0x2u
mbed_official 363:12a245e5c745 2984 #define LCD_WF8B_BPBLCD20_SHIFT 1
mbed_official 363:12a245e5c745 2985 #define LCD_WF8B_BPBLCD9_MASK 0x2u
mbed_official 363:12a245e5c745 2986 #define LCD_WF8B_BPBLCD9_SHIFT 1
mbed_official 363:12a245e5c745 2987 #define LCD_WF8B_BPBLCD7_MASK 0x2u
mbed_official 363:12a245e5c745 2988 #define LCD_WF8B_BPBLCD7_SHIFT 1
mbed_official 363:12a245e5c745 2989 #define LCD_WF8B_BPBLCD50_MASK 0x2u
mbed_official 363:12a245e5c745 2990 #define LCD_WF8B_BPBLCD50_SHIFT 1
mbed_official 363:12a245e5c745 2991 #define LCD_WF8B_BPBLCD40_MASK 0x2u
mbed_official 363:12a245e5c745 2992 #define LCD_WF8B_BPBLCD40_SHIFT 1
mbed_official 363:12a245e5c745 2993 #define LCD_WF8B_BPBLCD63_MASK 0x2u
mbed_official 363:12a245e5c745 2994 #define LCD_WF8B_BPBLCD63_SHIFT 1
mbed_official 363:12a245e5c745 2995 #define LCD_WF8B_BPBLCD26_MASK 0x2u
mbed_official 363:12a245e5c745 2996 #define LCD_WF8B_BPBLCD26_SHIFT 1
mbed_official 363:12a245e5c745 2997 #define LCD_WF8B_BPBLCD12_MASK 0x2u
mbed_official 363:12a245e5c745 2998 #define LCD_WF8B_BPBLCD12_SHIFT 1
mbed_official 363:12a245e5c745 2999 #define LCD_WF8B_BPBLCD19_MASK 0x2u
mbed_official 363:12a245e5c745 3000 #define LCD_WF8B_BPBLCD19_SHIFT 1
mbed_official 363:12a245e5c745 3001 #define LCD_WF8B_BPBLCD34_MASK 0x2u
mbed_official 363:12a245e5c745 3002 #define LCD_WF8B_BPBLCD34_SHIFT 1
mbed_official 363:12a245e5c745 3003 #define LCD_WF8B_BPBLCD39_MASK 0x2u
mbed_official 363:12a245e5c745 3004 #define LCD_WF8B_BPBLCD39_SHIFT 1
mbed_official 363:12a245e5c745 3005 #define LCD_WF8B_BPBLCD59_MASK 0x2u
mbed_official 363:12a245e5c745 3006 #define LCD_WF8B_BPBLCD59_SHIFT 1
mbed_official 363:12a245e5c745 3007 #define LCD_WF8B_BPBLCD61_MASK 0x2u
mbed_official 363:12a245e5c745 3008 #define LCD_WF8B_BPBLCD61_SHIFT 1
mbed_official 363:12a245e5c745 3009 #define LCD_WF8B_BPBLCD37_MASK 0x2u
mbed_official 363:12a245e5c745 3010 #define LCD_WF8B_BPBLCD37_SHIFT 1
mbed_official 363:12a245e5c745 3011 #define LCD_WF8B_BPBLCD31_MASK 0x2u
mbed_official 363:12a245e5c745 3012 #define LCD_WF8B_BPBLCD31_SHIFT 1
mbed_official 363:12a245e5c745 3013 #define LCD_WF8B_BPBLCD58_MASK 0x2u
mbed_official 363:12a245e5c745 3014 #define LCD_WF8B_BPBLCD58_SHIFT 1
mbed_official 363:12a245e5c745 3015 #define LCD_WF8B_BPBLCD18_MASK 0x2u
mbed_official 363:12a245e5c745 3016 #define LCD_WF8B_BPBLCD18_SHIFT 1
mbed_official 363:12a245e5c745 3017 #define LCD_WF8B_BPBLCD45_MASK 0x2u
mbed_official 363:12a245e5c745 3018 #define LCD_WF8B_BPBLCD45_SHIFT 1
mbed_official 363:12a245e5c745 3019 #define LCD_WF8B_BPBLCD27_MASK 0x2u
mbed_official 363:12a245e5c745 3020 #define LCD_WF8B_BPBLCD27_SHIFT 1
mbed_official 363:12a245e5c745 3021 #define LCD_WF8B_BPBLCD14_MASK 0x2u
mbed_official 363:12a245e5c745 3022 #define LCD_WF8B_BPBLCD14_SHIFT 1
mbed_official 363:12a245e5c745 3023 #define LCD_WF8B_BPBLCD51_MASK 0x2u
mbed_official 363:12a245e5c745 3024 #define LCD_WF8B_BPBLCD51_SHIFT 1
mbed_official 363:12a245e5c745 3025 #define LCD_WF8B_BPBLCD52_MASK 0x2u
mbed_official 363:12a245e5c745 3026 #define LCD_WF8B_BPBLCD52_SHIFT 1
mbed_official 363:12a245e5c745 3027 #define LCD_WF8B_BPBLCD4_MASK 0x2u
mbed_official 363:12a245e5c745 3028 #define LCD_WF8B_BPBLCD4_SHIFT 1
mbed_official 363:12a245e5c745 3029 #define LCD_WF8B_BPBLCD35_MASK 0x2u
mbed_official 363:12a245e5c745 3030 #define LCD_WF8B_BPBLCD35_SHIFT 1
mbed_official 363:12a245e5c745 3031 #define LCD_WF8B_BPBLCD17_MASK 0x2u
mbed_official 363:12a245e5c745 3032 #define LCD_WF8B_BPBLCD17_SHIFT 1
mbed_official 363:12a245e5c745 3033 #define LCD_WF8B_BPBLCD41_MASK 0x2u
mbed_official 363:12a245e5c745 3034 #define LCD_WF8B_BPBLCD41_SHIFT 1
mbed_official 363:12a245e5c745 3035 #define LCD_WF8B_BPBLCD11_MASK 0x2u
mbed_official 363:12a245e5c745 3036 #define LCD_WF8B_BPBLCD11_SHIFT 1
mbed_official 363:12a245e5c745 3037 #define LCD_WF8B_BPBLCD46_MASK 0x2u
mbed_official 363:12a245e5c745 3038 #define LCD_WF8B_BPBLCD46_SHIFT 1
mbed_official 363:12a245e5c745 3039 #define LCD_WF8B_BPBLCD57_MASK 0x2u
mbed_official 363:12a245e5c745 3040 #define LCD_WF8B_BPBLCD57_SHIFT 1
mbed_official 363:12a245e5c745 3041 #define LCD_WF8B_BPBLCD42_MASK 0x2u
mbed_official 363:12a245e5c745 3042 #define LCD_WF8B_BPBLCD42_SHIFT 1
mbed_official 363:12a245e5c745 3043 #define LCD_WF8B_BPBLCD5_MASK 0x2u
mbed_official 363:12a245e5c745 3044 #define LCD_WF8B_BPBLCD5_SHIFT 1
mbed_official 363:12a245e5c745 3045 #define LCD_WF8B_BPBLCD3_MASK 0x2u
mbed_official 363:12a245e5c745 3046 #define LCD_WF8B_BPBLCD3_SHIFT 1
mbed_official 363:12a245e5c745 3047 #define LCD_WF8B_BPBLCD16_MASK 0x2u
mbed_official 363:12a245e5c745 3048 #define LCD_WF8B_BPBLCD16_SHIFT 1
mbed_official 363:12a245e5c745 3049 #define LCD_WF8B_BPBLCD13_MASK 0x2u
mbed_official 363:12a245e5c745 3050 #define LCD_WF8B_BPBLCD13_SHIFT 1
mbed_official 363:12a245e5c745 3051 #define LCD_WF8B_BPCLCD10_MASK 0x4u
mbed_official 363:12a245e5c745 3052 #define LCD_WF8B_BPCLCD10_SHIFT 2
mbed_official 363:12a245e5c745 3053 #define LCD_WF8B_BPCLCD55_MASK 0x4u
mbed_official 363:12a245e5c745 3054 #define LCD_WF8B_BPCLCD55_SHIFT 2
mbed_official 363:12a245e5c745 3055 #define LCD_WF8B_BPCLCD2_MASK 0x4u
mbed_official 363:12a245e5c745 3056 #define LCD_WF8B_BPCLCD2_SHIFT 2
mbed_official 363:12a245e5c745 3057 #define LCD_WF8B_BPCLCD23_MASK 0x4u
mbed_official 363:12a245e5c745 3058 #define LCD_WF8B_BPCLCD23_SHIFT 2
mbed_official 363:12a245e5c745 3059 #define LCD_WF8B_BPCLCD48_MASK 0x4u
mbed_official 363:12a245e5c745 3060 #define LCD_WF8B_BPCLCD48_SHIFT 2
mbed_official 363:12a245e5c745 3061 #define LCD_WF8B_BPCLCD24_MASK 0x4u
mbed_official 363:12a245e5c745 3062 #define LCD_WF8B_BPCLCD24_SHIFT 2
mbed_official 363:12a245e5c745 3063 #define LCD_WF8B_BPCLCD60_MASK 0x4u
mbed_official 363:12a245e5c745 3064 #define LCD_WF8B_BPCLCD60_SHIFT 2
mbed_official 363:12a245e5c745 3065 #define LCD_WF8B_BPCLCD47_MASK 0x4u
mbed_official 363:12a245e5c745 3066 #define LCD_WF8B_BPCLCD47_SHIFT 2
mbed_official 363:12a245e5c745 3067 #define LCD_WF8B_BPCLCD22_MASK 0x4u
mbed_official 363:12a245e5c745 3068 #define LCD_WF8B_BPCLCD22_SHIFT 2
mbed_official 363:12a245e5c745 3069 #define LCD_WF8B_BPCLCD8_MASK 0x4u
mbed_official 363:12a245e5c745 3070 #define LCD_WF8B_BPCLCD8_SHIFT 2
mbed_official 363:12a245e5c745 3071 #define LCD_WF8B_BPCLCD21_MASK 0x4u
mbed_official 363:12a245e5c745 3072 #define LCD_WF8B_BPCLCD21_SHIFT 2
mbed_official 363:12a245e5c745 3073 #define LCD_WF8B_BPCLCD49_MASK 0x4u
mbed_official 363:12a245e5c745 3074 #define LCD_WF8B_BPCLCD49_SHIFT 2
mbed_official 363:12a245e5c745 3075 #define LCD_WF8B_BPCLCD25_MASK 0x4u
mbed_official 363:12a245e5c745 3076 #define LCD_WF8B_BPCLCD25_SHIFT 2
mbed_official 363:12a245e5c745 3077 #define LCD_WF8B_BPCLCD1_MASK 0x4u
mbed_official 363:12a245e5c745 3078 #define LCD_WF8B_BPCLCD1_SHIFT 2
mbed_official 363:12a245e5c745 3079 #define LCD_WF8B_BPCLCD20_MASK 0x4u
mbed_official 363:12a245e5c745 3080 #define LCD_WF8B_BPCLCD20_SHIFT 2
mbed_official 363:12a245e5c745 3081 #define LCD_WF8B_BPCLCD50_MASK 0x4u
mbed_official 363:12a245e5c745 3082 #define LCD_WF8B_BPCLCD50_SHIFT 2
mbed_official 363:12a245e5c745 3083 #define LCD_WF8B_BPCLCD19_MASK 0x4u
mbed_official 363:12a245e5c745 3084 #define LCD_WF8B_BPCLCD19_SHIFT 2
mbed_official 363:12a245e5c745 3085 #define LCD_WF8B_BPCLCD26_MASK 0x4u
mbed_official 363:12a245e5c745 3086 #define LCD_WF8B_BPCLCD26_SHIFT 2
mbed_official 363:12a245e5c745 3087 #define LCD_WF8B_BPCLCD59_MASK 0x4u
mbed_official 363:12a245e5c745 3088 #define LCD_WF8B_BPCLCD59_SHIFT 2
mbed_official 363:12a245e5c745 3089 #define LCD_WF8B_BPCLCD61_MASK 0x4u
mbed_official 363:12a245e5c745 3090 #define LCD_WF8B_BPCLCD61_SHIFT 2
mbed_official 363:12a245e5c745 3091 #define LCD_WF8B_BPCLCD46_MASK 0x4u
mbed_official 363:12a245e5c745 3092 #define LCD_WF8B_BPCLCD46_SHIFT 2
mbed_official 363:12a245e5c745 3093 #define LCD_WF8B_BPCLCD18_MASK 0x4u
mbed_official 363:12a245e5c745 3094 #define LCD_WF8B_BPCLCD18_SHIFT 2
mbed_official 363:12a245e5c745 3095 #define LCD_WF8B_BPCLCD5_MASK 0x4u
mbed_official 363:12a245e5c745 3096 #define LCD_WF8B_BPCLCD5_SHIFT 2
mbed_official 363:12a245e5c745 3097 #define LCD_WF8B_BPCLCD63_MASK 0x4u
mbed_official 363:12a245e5c745 3098 #define LCD_WF8B_BPCLCD63_SHIFT 2
mbed_official 363:12a245e5c745 3099 #define LCD_WF8B_BPCLCD27_MASK 0x4u
mbed_official 363:12a245e5c745 3100 #define LCD_WF8B_BPCLCD27_SHIFT 2
mbed_official 363:12a245e5c745 3101 #define LCD_WF8B_BPCLCD17_MASK 0x4u
mbed_official 363:12a245e5c745 3102 #define LCD_WF8B_BPCLCD17_SHIFT 2
mbed_official 363:12a245e5c745 3103 #define LCD_WF8B_BPCLCD51_MASK 0x4u
mbed_official 363:12a245e5c745 3104 #define LCD_WF8B_BPCLCD51_SHIFT 2
mbed_official 363:12a245e5c745 3105 #define LCD_WF8B_BPCLCD9_MASK 0x4u
mbed_official 363:12a245e5c745 3106 #define LCD_WF8B_BPCLCD9_SHIFT 2
mbed_official 363:12a245e5c745 3107 #define LCD_WF8B_BPCLCD54_MASK 0x4u
mbed_official 363:12a245e5c745 3108 #define LCD_WF8B_BPCLCD54_SHIFT 2
mbed_official 363:12a245e5c745 3109 #define LCD_WF8B_BPCLCD15_MASK 0x4u
mbed_official 363:12a245e5c745 3110 #define LCD_WF8B_BPCLCD15_SHIFT 2
mbed_official 363:12a245e5c745 3111 #define LCD_WF8B_BPCLCD16_MASK 0x4u
mbed_official 363:12a245e5c745 3112 #define LCD_WF8B_BPCLCD16_SHIFT 2
mbed_official 363:12a245e5c745 3113 #define LCD_WF8B_BPCLCD14_MASK 0x4u
mbed_official 363:12a245e5c745 3114 #define LCD_WF8B_BPCLCD14_SHIFT 2
mbed_official 363:12a245e5c745 3115 #define LCD_WF8B_BPCLCD32_MASK 0x4u
mbed_official 363:12a245e5c745 3116 #define LCD_WF8B_BPCLCD32_SHIFT 2
mbed_official 363:12a245e5c745 3117 #define LCD_WF8B_BPCLCD28_MASK 0x4u
mbed_official 363:12a245e5c745 3118 #define LCD_WF8B_BPCLCD28_SHIFT 2
mbed_official 363:12a245e5c745 3119 #define LCD_WF8B_BPCLCD53_MASK 0x4u
mbed_official 363:12a245e5c745 3120 #define LCD_WF8B_BPCLCD53_SHIFT 2
mbed_official 363:12a245e5c745 3121 #define LCD_WF8B_BPCLCD33_MASK 0x4u
mbed_official 363:12a245e5c745 3122 #define LCD_WF8B_BPCLCD33_SHIFT 2
mbed_official 363:12a245e5c745 3123 #define LCD_WF8B_BPCLCD0_MASK 0x4u
mbed_official 363:12a245e5c745 3124 #define LCD_WF8B_BPCLCD0_SHIFT 2
mbed_official 363:12a245e5c745 3125 #define LCD_WF8B_BPCLCD43_MASK 0x4u
mbed_official 363:12a245e5c745 3126 #define LCD_WF8B_BPCLCD43_SHIFT 2
mbed_official 363:12a245e5c745 3127 #define LCD_WF8B_BPCLCD7_MASK 0x4u
mbed_official 363:12a245e5c745 3128 #define LCD_WF8B_BPCLCD7_SHIFT 2
mbed_official 363:12a245e5c745 3129 #define LCD_WF8B_BPCLCD4_MASK 0x4u
mbed_official 363:12a245e5c745 3130 #define LCD_WF8B_BPCLCD4_SHIFT 2
mbed_official 363:12a245e5c745 3131 #define LCD_WF8B_BPCLCD34_MASK 0x4u
mbed_official 363:12a245e5c745 3132 #define LCD_WF8B_BPCLCD34_SHIFT 2
mbed_official 363:12a245e5c745 3133 #define LCD_WF8B_BPCLCD29_MASK 0x4u
mbed_official 363:12a245e5c745 3134 #define LCD_WF8B_BPCLCD29_SHIFT 2
mbed_official 363:12a245e5c745 3135 #define LCD_WF8B_BPCLCD45_MASK 0x4u
mbed_official 363:12a245e5c745 3136 #define LCD_WF8B_BPCLCD45_SHIFT 2
mbed_official 363:12a245e5c745 3137 #define LCD_WF8B_BPCLCD57_MASK 0x4u
mbed_official 363:12a245e5c745 3138 #define LCD_WF8B_BPCLCD57_SHIFT 2
mbed_official 363:12a245e5c745 3139 #define LCD_WF8B_BPCLCD42_MASK 0x4u
mbed_official 363:12a245e5c745 3140 #define LCD_WF8B_BPCLCD42_SHIFT 2
mbed_official 363:12a245e5c745 3141 #define LCD_WF8B_BPCLCD35_MASK 0x4u
mbed_official 363:12a245e5c745 3142 #define LCD_WF8B_BPCLCD35_SHIFT 2
mbed_official 363:12a245e5c745 3143 #define LCD_WF8B_BPCLCD13_MASK 0x4u
mbed_official 363:12a245e5c745 3144 #define LCD_WF8B_BPCLCD13_SHIFT 2
mbed_official 363:12a245e5c745 3145 #define LCD_WF8B_BPCLCD36_MASK 0x4u
mbed_official 363:12a245e5c745 3146 #define LCD_WF8B_BPCLCD36_SHIFT 2
mbed_official 363:12a245e5c745 3147 #define LCD_WF8B_BPCLCD30_MASK 0x4u
mbed_official 363:12a245e5c745 3148 #define LCD_WF8B_BPCLCD30_SHIFT 2
mbed_official 363:12a245e5c745 3149 #define LCD_WF8B_BPCLCD52_MASK 0x4u
mbed_official 363:12a245e5c745 3150 #define LCD_WF8B_BPCLCD52_SHIFT 2
mbed_official 363:12a245e5c745 3151 #define LCD_WF8B_BPCLCD58_MASK 0x4u
mbed_official 363:12a245e5c745 3152 #define LCD_WF8B_BPCLCD58_SHIFT 2
mbed_official 363:12a245e5c745 3153 #define LCD_WF8B_BPCLCD41_MASK 0x4u
mbed_official 363:12a245e5c745 3154 #define LCD_WF8B_BPCLCD41_SHIFT 2
mbed_official 363:12a245e5c745 3155 #define LCD_WF8B_BPCLCD37_MASK 0x4u
mbed_official 363:12a245e5c745 3156 #define LCD_WF8B_BPCLCD37_SHIFT 2
mbed_official 363:12a245e5c745 3157 #define LCD_WF8B_BPCLCD3_MASK 0x4u
mbed_official 363:12a245e5c745 3158 #define LCD_WF8B_BPCLCD3_SHIFT 2
mbed_official 363:12a245e5c745 3159 #define LCD_WF8B_BPCLCD12_MASK 0x4u
mbed_official 363:12a245e5c745 3160 #define LCD_WF8B_BPCLCD12_SHIFT 2
mbed_official 363:12a245e5c745 3161 #define LCD_WF8B_BPCLCD11_MASK 0x4u
mbed_official 363:12a245e5c745 3162 #define LCD_WF8B_BPCLCD11_SHIFT 2
mbed_official 363:12a245e5c745 3163 #define LCD_WF8B_BPCLCD38_MASK 0x4u
mbed_official 363:12a245e5c745 3164 #define LCD_WF8B_BPCLCD38_SHIFT 2
mbed_official 363:12a245e5c745 3165 #define LCD_WF8B_BPCLCD44_MASK 0x4u
mbed_official 363:12a245e5c745 3166 #define LCD_WF8B_BPCLCD44_SHIFT 2
mbed_official 363:12a245e5c745 3167 #define LCD_WF8B_BPCLCD31_MASK 0x4u
mbed_official 363:12a245e5c745 3168 #define LCD_WF8B_BPCLCD31_SHIFT 2
mbed_official 363:12a245e5c745 3169 #define LCD_WF8B_BPCLCD40_MASK 0x4u
mbed_official 363:12a245e5c745 3170 #define LCD_WF8B_BPCLCD40_SHIFT 2
mbed_official 363:12a245e5c745 3171 #define LCD_WF8B_BPCLCD62_MASK 0x4u
mbed_official 363:12a245e5c745 3172 #define LCD_WF8B_BPCLCD62_SHIFT 2
mbed_official 363:12a245e5c745 3173 #define LCD_WF8B_BPCLCD56_MASK 0x4u
mbed_official 363:12a245e5c745 3174 #define LCD_WF8B_BPCLCD56_SHIFT 2
mbed_official 363:12a245e5c745 3175 #define LCD_WF8B_BPCLCD39_MASK 0x4u
mbed_official 363:12a245e5c745 3176 #define LCD_WF8B_BPCLCD39_SHIFT 2
mbed_official 363:12a245e5c745 3177 #define LCD_WF8B_BPCLCD6_MASK 0x4u
mbed_official 363:12a245e5c745 3178 #define LCD_WF8B_BPCLCD6_SHIFT 2
mbed_official 363:12a245e5c745 3179 #define LCD_WF8B_BPDLCD47_MASK 0x8u
mbed_official 363:12a245e5c745 3180 #define LCD_WF8B_BPDLCD47_SHIFT 3
mbed_official 363:12a245e5c745 3181 #define LCD_WF8B_BPDLCD23_MASK 0x8u
mbed_official 363:12a245e5c745 3182 #define LCD_WF8B_BPDLCD23_SHIFT 3
mbed_official 363:12a245e5c745 3183 #define LCD_WF8B_BPDLCD48_MASK 0x8u
mbed_official 363:12a245e5c745 3184 #define LCD_WF8B_BPDLCD48_SHIFT 3
mbed_official 363:12a245e5c745 3185 #define LCD_WF8B_BPDLCD24_MASK 0x8u
mbed_official 363:12a245e5c745 3186 #define LCD_WF8B_BPDLCD24_SHIFT 3
mbed_official 363:12a245e5c745 3187 #define LCD_WF8B_BPDLCD15_MASK 0x8u
mbed_official 363:12a245e5c745 3188 #define LCD_WF8B_BPDLCD15_SHIFT 3
mbed_official 363:12a245e5c745 3189 #define LCD_WF8B_BPDLCD22_MASK 0x8u
mbed_official 363:12a245e5c745 3190 #define LCD_WF8B_BPDLCD22_SHIFT 3
mbed_official 363:12a245e5c745 3191 #define LCD_WF8B_BPDLCD60_MASK 0x8u
mbed_official 363:12a245e5c745 3192 #define LCD_WF8B_BPDLCD60_SHIFT 3
mbed_official 363:12a245e5c745 3193 #define LCD_WF8B_BPDLCD10_MASK 0x8u
mbed_official 363:12a245e5c745 3194 #define LCD_WF8B_BPDLCD10_SHIFT 3
mbed_official 363:12a245e5c745 3195 #define LCD_WF8B_BPDLCD21_MASK 0x8u
mbed_official 363:12a245e5c745 3196 #define LCD_WF8B_BPDLCD21_SHIFT 3
mbed_official 363:12a245e5c745 3197 #define LCD_WF8B_BPDLCD49_MASK 0x8u
mbed_official 363:12a245e5c745 3198 #define LCD_WF8B_BPDLCD49_SHIFT 3
mbed_official 363:12a245e5c745 3199 #define LCD_WF8B_BPDLCD1_MASK 0x8u
mbed_official 363:12a245e5c745 3200 #define LCD_WF8B_BPDLCD1_SHIFT 3
mbed_official 363:12a245e5c745 3201 #define LCD_WF8B_BPDLCD25_MASK 0x8u
mbed_official 363:12a245e5c745 3202 #define LCD_WF8B_BPDLCD25_SHIFT 3
mbed_official 363:12a245e5c745 3203 #define LCD_WF8B_BPDLCD20_MASK 0x8u
mbed_official 363:12a245e5c745 3204 #define LCD_WF8B_BPDLCD20_SHIFT 3
mbed_official 363:12a245e5c745 3205 #define LCD_WF8B_BPDLCD2_MASK 0x8u
mbed_official 363:12a245e5c745 3206 #define LCD_WF8B_BPDLCD2_SHIFT 3
mbed_official 363:12a245e5c745 3207 #define LCD_WF8B_BPDLCD55_MASK 0x8u
mbed_official 363:12a245e5c745 3208 #define LCD_WF8B_BPDLCD55_SHIFT 3
mbed_official 363:12a245e5c745 3209 #define LCD_WF8B_BPDLCD59_MASK 0x8u
mbed_official 363:12a245e5c745 3210 #define LCD_WF8B_BPDLCD59_SHIFT 3
mbed_official 363:12a245e5c745 3211 #define LCD_WF8B_BPDLCD5_MASK 0x8u
mbed_official 363:12a245e5c745 3212 #define LCD_WF8B_BPDLCD5_SHIFT 3
mbed_official 363:12a245e5c745 3213 #define LCD_WF8B_BPDLCD19_MASK 0x8u
mbed_official 363:12a245e5c745 3214 #define LCD_WF8B_BPDLCD19_SHIFT 3
mbed_official 363:12a245e5c745 3215 #define LCD_WF8B_BPDLCD6_MASK 0x8u
mbed_official 363:12a245e5c745 3216 #define LCD_WF8B_BPDLCD6_SHIFT 3
mbed_official 363:12a245e5c745 3217 #define LCD_WF8B_BPDLCD26_MASK 0x8u
mbed_official 363:12a245e5c745 3218 #define LCD_WF8B_BPDLCD26_SHIFT 3
mbed_official 363:12a245e5c745 3219 #define LCD_WF8B_BPDLCD0_MASK 0x8u
mbed_official 363:12a245e5c745 3220 #define LCD_WF8B_BPDLCD0_SHIFT 3
mbed_official 363:12a245e5c745 3221 #define LCD_WF8B_BPDLCD50_MASK 0x8u
mbed_official 363:12a245e5c745 3222 #define LCD_WF8B_BPDLCD50_SHIFT 3
mbed_official 363:12a245e5c745 3223 #define LCD_WF8B_BPDLCD46_MASK 0x8u
mbed_official 363:12a245e5c745 3224 #define LCD_WF8B_BPDLCD46_SHIFT 3
mbed_official 363:12a245e5c745 3225 #define LCD_WF8B_BPDLCD18_MASK 0x8u
mbed_official 363:12a245e5c745 3226 #define LCD_WF8B_BPDLCD18_SHIFT 3
mbed_official 363:12a245e5c745 3227 #define LCD_WF8B_BPDLCD61_MASK 0x8u
mbed_official 363:12a245e5c745 3228 #define LCD_WF8B_BPDLCD61_SHIFT 3
mbed_official 363:12a245e5c745 3229 #define LCD_WF8B_BPDLCD9_MASK 0x8u
mbed_official 363:12a245e5c745 3230 #define LCD_WF8B_BPDLCD9_SHIFT 3
mbed_official 363:12a245e5c745 3231 #define LCD_WF8B_BPDLCD17_MASK 0x8u
mbed_official 363:12a245e5c745 3232 #define LCD_WF8B_BPDLCD17_SHIFT 3
mbed_official 363:12a245e5c745 3233 #define LCD_WF8B_BPDLCD27_MASK 0x8u
mbed_official 363:12a245e5c745 3234 #define LCD_WF8B_BPDLCD27_SHIFT 3
mbed_official 363:12a245e5c745 3235 #define LCD_WF8B_BPDLCD53_MASK 0x8u
mbed_official 363:12a245e5c745 3236 #define LCD_WF8B_BPDLCD53_SHIFT 3
mbed_official 363:12a245e5c745 3237 #define LCD_WF8B_BPDLCD51_MASK 0x8u
mbed_official 363:12a245e5c745 3238 #define LCD_WF8B_BPDLCD51_SHIFT 3
mbed_official 363:12a245e5c745 3239 #define LCD_WF8B_BPDLCD54_MASK 0x8u
mbed_official 363:12a245e5c745 3240 #define LCD_WF8B_BPDLCD54_SHIFT 3
mbed_official 363:12a245e5c745 3241 #define LCD_WF8B_BPDLCD13_MASK 0x8u
mbed_official 363:12a245e5c745 3242 #define LCD_WF8B_BPDLCD13_SHIFT 3
mbed_official 363:12a245e5c745 3243 #define LCD_WF8B_BPDLCD16_MASK 0x8u
mbed_official 363:12a245e5c745 3244 #define LCD_WF8B_BPDLCD16_SHIFT 3
mbed_official 363:12a245e5c745 3245 #define LCD_WF8B_BPDLCD32_MASK 0x8u
mbed_official 363:12a245e5c745 3246 #define LCD_WF8B_BPDLCD32_SHIFT 3
mbed_official 363:12a245e5c745 3247 #define LCD_WF8B_BPDLCD14_MASK 0x8u
mbed_official 363:12a245e5c745 3248 #define LCD_WF8B_BPDLCD14_SHIFT 3
mbed_official 363:12a245e5c745 3249 #define LCD_WF8B_BPDLCD28_MASK 0x8u
mbed_official 363:12a245e5c745 3250 #define LCD_WF8B_BPDLCD28_SHIFT 3
mbed_official 363:12a245e5c745 3251 #define LCD_WF8B_BPDLCD43_MASK 0x8u
mbed_official 363:12a245e5c745 3252 #define LCD_WF8B_BPDLCD43_SHIFT 3
mbed_official 363:12a245e5c745 3253 #define LCD_WF8B_BPDLCD4_MASK 0x8u
mbed_official 363:12a245e5c745 3254 #define LCD_WF8B_BPDLCD4_SHIFT 3
mbed_official 363:12a245e5c745 3255 #define LCD_WF8B_BPDLCD45_MASK 0x8u
mbed_official 363:12a245e5c745 3256 #define LCD_WF8B_BPDLCD45_SHIFT 3
mbed_official 363:12a245e5c745 3257 #define LCD_WF8B_BPDLCD8_MASK 0x8u
mbed_official 363:12a245e5c745 3258 #define LCD_WF8B_BPDLCD8_SHIFT 3
mbed_official 363:12a245e5c745 3259 #define LCD_WF8B_BPDLCD62_MASK 0x8u
mbed_official 363:12a245e5c745 3260 #define LCD_WF8B_BPDLCD62_SHIFT 3
mbed_official 363:12a245e5c745 3261 #define LCD_WF8B_BPDLCD33_MASK 0x8u
mbed_official 363:12a245e5c745 3262 #define LCD_WF8B_BPDLCD33_SHIFT 3
mbed_official 363:12a245e5c745 3263 #define LCD_WF8B_BPDLCD34_MASK 0x8u
mbed_official 363:12a245e5c745 3264 #define LCD_WF8B_BPDLCD34_SHIFT 3
mbed_official 363:12a245e5c745 3265 #define LCD_WF8B_BPDLCD29_MASK 0x8u
mbed_official 363:12a245e5c745 3266 #define LCD_WF8B_BPDLCD29_SHIFT 3
mbed_official 363:12a245e5c745 3267 #define LCD_WF8B_BPDLCD58_MASK 0x8u
mbed_official 363:12a245e5c745 3268 #define LCD_WF8B_BPDLCD58_SHIFT 3
mbed_official 363:12a245e5c745 3269 #define LCD_WF8B_BPDLCD57_MASK 0x8u
mbed_official 363:12a245e5c745 3270 #define LCD_WF8B_BPDLCD57_SHIFT 3
mbed_official 363:12a245e5c745 3271 #define LCD_WF8B_BPDLCD42_MASK 0x8u
mbed_official 363:12a245e5c745 3272 #define LCD_WF8B_BPDLCD42_SHIFT 3
mbed_official 363:12a245e5c745 3273 #define LCD_WF8B_BPDLCD35_MASK 0x8u
mbed_official 363:12a245e5c745 3274 #define LCD_WF8B_BPDLCD35_SHIFT 3
mbed_official 363:12a245e5c745 3275 #define LCD_WF8B_BPDLCD52_MASK 0x8u
mbed_official 363:12a245e5c745 3276 #define LCD_WF8B_BPDLCD52_SHIFT 3
mbed_official 363:12a245e5c745 3277 #define LCD_WF8B_BPDLCD7_MASK 0x8u
mbed_official 363:12a245e5c745 3278 #define LCD_WF8B_BPDLCD7_SHIFT 3
mbed_official 363:12a245e5c745 3279 #define LCD_WF8B_BPDLCD36_MASK 0x8u
mbed_official 363:12a245e5c745 3280 #define LCD_WF8B_BPDLCD36_SHIFT 3
mbed_official 363:12a245e5c745 3281 #define LCD_WF8B_BPDLCD30_MASK 0x8u
mbed_official 363:12a245e5c745 3282 #define LCD_WF8B_BPDLCD30_SHIFT 3
mbed_official 363:12a245e5c745 3283 #define LCD_WF8B_BPDLCD41_MASK 0x8u
mbed_official 363:12a245e5c745 3284 #define LCD_WF8B_BPDLCD41_SHIFT 3
mbed_official 363:12a245e5c745 3285 #define LCD_WF8B_BPDLCD37_MASK 0x8u
mbed_official 363:12a245e5c745 3286 #define LCD_WF8B_BPDLCD37_SHIFT 3
mbed_official 363:12a245e5c745 3287 #define LCD_WF8B_BPDLCD44_MASK 0x8u
mbed_official 363:12a245e5c745 3288 #define LCD_WF8B_BPDLCD44_SHIFT 3
mbed_official 363:12a245e5c745 3289 #define LCD_WF8B_BPDLCD63_MASK 0x8u
mbed_official 363:12a245e5c745 3290 #define LCD_WF8B_BPDLCD63_SHIFT 3
mbed_official 363:12a245e5c745 3291 #define LCD_WF8B_BPDLCD38_MASK 0x8u
mbed_official 363:12a245e5c745 3292 #define LCD_WF8B_BPDLCD38_SHIFT 3
mbed_official 363:12a245e5c745 3293 #define LCD_WF8B_BPDLCD56_MASK 0x8u
mbed_official 363:12a245e5c745 3294 #define LCD_WF8B_BPDLCD56_SHIFT 3
mbed_official 363:12a245e5c745 3295 #define LCD_WF8B_BPDLCD40_MASK 0x8u
mbed_official 363:12a245e5c745 3296 #define LCD_WF8B_BPDLCD40_SHIFT 3
mbed_official 363:12a245e5c745 3297 #define LCD_WF8B_BPDLCD31_MASK 0x8u
mbed_official 363:12a245e5c745 3298 #define LCD_WF8B_BPDLCD31_SHIFT 3
mbed_official 363:12a245e5c745 3299 #define LCD_WF8B_BPDLCD12_MASK 0x8u
mbed_official 363:12a245e5c745 3300 #define LCD_WF8B_BPDLCD12_SHIFT 3
mbed_official 363:12a245e5c745 3301 #define LCD_WF8B_BPDLCD39_MASK 0x8u
mbed_official 363:12a245e5c745 3302 #define LCD_WF8B_BPDLCD39_SHIFT 3
mbed_official 363:12a245e5c745 3303 #define LCD_WF8B_BPDLCD3_MASK 0x8u
mbed_official 363:12a245e5c745 3304 #define LCD_WF8B_BPDLCD3_SHIFT 3
mbed_official 363:12a245e5c745 3305 #define LCD_WF8B_BPDLCD11_MASK 0x8u
mbed_official 363:12a245e5c745 3306 #define LCD_WF8B_BPDLCD11_SHIFT 3
mbed_official 363:12a245e5c745 3307 #define LCD_WF8B_BPELCD12_MASK 0x10u
mbed_official 363:12a245e5c745 3308 #define LCD_WF8B_BPELCD12_SHIFT 4
mbed_official 363:12a245e5c745 3309 #define LCD_WF8B_BPELCD39_MASK 0x10u
mbed_official 363:12a245e5c745 3310 #define LCD_WF8B_BPELCD39_SHIFT 4
mbed_official 363:12a245e5c745 3311 #define LCD_WF8B_BPELCD3_MASK 0x10u
mbed_official 363:12a245e5c745 3312 #define LCD_WF8B_BPELCD3_SHIFT 4
mbed_official 363:12a245e5c745 3313 #define LCD_WF8B_BPELCD38_MASK 0x10u
mbed_official 363:12a245e5c745 3314 #define LCD_WF8B_BPELCD38_SHIFT 4
mbed_official 363:12a245e5c745 3315 #define LCD_WF8B_BPELCD40_MASK 0x10u
mbed_official 363:12a245e5c745 3316 #define LCD_WF8B_BPELCD40_SHIFT 4
mbed_official 363:12a245e5c745 3317 #define LCD_WF8B_BPELCD37_MASK 0x10u
mbed_official 363:12a245e5c745 3318 #define LCD_WF8B_BPELCD37_SHIFT 4
mbed_official 363:12a245e5c745 3319 #define LCD_WF8B_BPELCD41_MASK 0x10u
mbed_official 363:12a245e5c745 3320 #define LCD_WF8B_BPELCD41_SHIFT 4
mbed_official 363:12a245e5c745 3321 #define LCD_WF8B_BPELCD36_MASK 0x10u
mbed_official 363:12a245e5c745 3322 #define LCD_WF8B_BPELCD36_SHIFT 4
mbed_official 363:12a245e5c745 3323 #define LCD_WF8B_BPELCD8_MASK 0x10u
mbed_official 363:12a245e5c745 3324 #define LCD_WF8B_BPELCD8_SHIFT 4
mbed_official 363:12a245e5c745 3325 #define LCD_WF8B_BPELCD35_MASK 0x10u
mbed_official 363:12a245e5c745 3326 #define LCD_WF8B_BPELCD35_SHIFT 4
mbed_official 363:12a245e5c745 3327 #define LCD_WF8B_BPELCD42_MASK 0x10u
mbed_official 363:12a245e5c745 3328 #define LCD_WF8B_BPELCD42_SHIFT 4
mbed_official 363:12a245e5c745 3329 #define LCD_WF8B_BPELCD34_MASK 0x10u
mbed_official 363:12a245e5c745 3330 #define LCD_WF8B_BPELCD34_SHIFT 4
mbed_official 363:12a245e5c745 3331 #define LCD_WF8B_BPELCD33_MASK 0x10u
mbed_official 363:12a245e5c745 3332 #define LCD_WF8B_BPELCD33_SHIFT 4
mbed_official 363:12a245e5c745 3333 #define LCD_WF8B_BPELCD11_MASK 0x10u
mbed_official 363:12a245e5c745 3334 #define LCD_WF8B_BPELCD11_SHIFT 4
mbed_official 363:12a245e5c745 3335 #define LCD_WF8B_BPELCD43_MASK 0x10u
mbed_official 363:12a245e5c745 3336 #define LCD_WF8B_BPELCD43_SHIFT 4
mbed_official 363:12a245e5c745 3337 #define LCD_WF8B_BPELCD32_MASK 0x10u
mbed_official 363:12a245e5c745 3338 #define LCD_WF8B_BPELCD32_SHIFT 4
mbed_official 363:12a245e5c745 3339 #define LCD_WF8B_BPELCD31_MASK 0x10u
mbed_official 363:12a245e5c745 3340 #define LCD_WF8B_BPELCD31_SHIFT 4
mbed_official 363:12a245e5c745 3341 #define LCD_WF8B_BPELCD44_MASK 0x10u
mbed_official 363:12a245e5c745 3342 #define LCD_WF8B_BPELCD44_SHIFT 4
mbed_official 363:12a245e5c745 3343 #define LCD_WF8B_BPELCD30_MASK 0x10u
mbed_official 363:12a245e5c745 3344 #define LCD_WF8B_BPELCD30_SHIFT 4
mbed_official 363:12a245e5c745 3345 #define LCD_WF8B_BPELCD29_MASK 0x10u
mbed_official 363:12a245e5c745 3346 #define LCD_WF8B_BPELCD29_SHIFT 4
mbed_official 363:12a245e5c745 3347 #define LCD_WF8B_BPELCD7_MASK 0x10u
mbed_official 363:12a245e5c745 3348 #define LCD_WF8B_BPELCD7_SHIFT 4
mbed_official 363:12a245e5c745 3349 #define LCD_WF8B_BPELCD45_MASK 0x10u
mbed_official 363:12a245e5c745 3350 #define LCD_WF8B_BPELCD45_SHIFT 4
mbed_official 363:12a245e5c745 3351 #define LCD_WF8B_BPELCD28_MASK 0x10u
mbed_official 363:12a245e5c745 3352 #define LCD_WF8B_BPELCD28_SHIFT 4
mbed_official 363:12a245e5c745 3353 #define LCD_WF8B_BPELCD2_MASK 0x10u
mbed_official 363:12a245e5c745 3354 #define LCD_WF8B_BPELCD2_SHIFT 4
mbed_official 363:12a245e5c745 3355 #define LCD_WF8B_BPELCD27_MASK 0x10u
mbed_official 363:12a245e5c745 3356 #define LCD_WF8B_BPELCD27_SHIFT 4
mbed_official 363:12a245e5c745 3357 #define LCD_WF8B_BPELCD46_MASK 0x10u
mbed_official 363:12a245e5c745 3358 #define LCD_WF8B_BPELCD46_SHIFT 4
mbed_official 363:12a245e5c745 3359 #define LCD_WF8B_BPELCD26_MASK 0x10u
mbed_official 363:12a245e5c745 3360 #define LCD_WF8B_BPELCD26_SHIFT 4
mbed_official 363:12a245e5c745 3361 #define LCD_WF8B_BPELCD10_MASK 0x10u
mbed_official 363:12a245e5c745 3362 #define LCD_WF8B_BPELCD10_SHIFT 4
mbed_official 363:12a245e5c745 3363 #define LCD_WF8B_BPELCD13_MASK 0x10u
mbed_official 363:12a245e5c745 3364 #define LCD_WF8B_BPELCD13_SHIFT 4
mbed_official 363:12a245e5c745 3365 #define LCD_WF8B_BPELCD25_MASK 0x10u
mbed_official 363:12a245e5c745 3366 #define LCD_WF8B_BPELCD25_SHIFT 4
mbed_official 363:12a245e5c745 3367 #define LCD_WF8B_BPELCD5_MASK 0x10u
mbed_official 363:12a245e5c745 3368 #define LCD_WF8B_BPELCD5_SHIFT 4
mbed_official 363:12a245e5c745 3369 #define LCD_WF8B_BPELCD24_MASK 0x10u
mbed_official 363:12a245e5c745 3370 #define LCD_WF8B_BPELCD24_SHIFT 4
mbed_official 363:12a245e5c745 3371 #define LCD_WF8B_BPELCD47_MASK 0x10u
mbed_official 363:12a245e5c745 3372 #define LCD_WF8B_BPELCD47_SHIFT 4
mbed_official 363:12a245e5c745 3373 #define LCD_WF8B_BPELCD23_MASK 0x10u
mbed_official 363:12a245e5c745 3374 #define LCD_WF8B_BPELCD23_SHIFT 4
mbed_official 363:12a245e5c745 3375 #define LCD_WF8B_BPELCD22_MASK 0x10u
mbed_official 363:12a245e5c745 3376 #define LCD_WF8B_BPELCD22_SHIFT 4
mbed_official 363:12a245e5c745 3377 #define LCD_WF8B_BPELCD48_MASK 0x10u
mbed_official 363:12a245e5c745 3378 #define LCD_WF8B_BPELCD48_SHIFT 4
mbed_official 363:12a245e5c745 3379 #define LCD_WF8B_BPELCD21_MASK 0x10u
mbed_official 363:12a245e5c745 3380 #define LCD_WF8B_BPELCD21_SHIFT 4
mbed_official 363:12a245e5c745 3381 #define LCD_WF8B_BPELCD49_MASK 0x10u
mbed_official 363:12a245e5c745 3382 #define LCD_WF8B_BPELCD49_SHIFT 4
mbed_official 363:12a245e5c745 3383 #define LCD_WF8B_BPELCD20_MASK 0x10u
mbed_official 363:12a245e5c745 3384 #define LCD_WF8B_BPELCD20_SHIFT 4
mbed_official 363:12a245e5c745 3385 #define LCD_WF8B_BPELCD19_MASK 0x10u
mbed_official 363:12a245e5c745 3386 #define LCD_WF8B_BPELCD19_SHIFT 4
mbed_official 363:12a245e5c745 3387 #define LCD_WF8B_BPELCD9_MASK 0x10u
mbed_official 363:12a245e5c745 3388 #define LCD_WF8B_BPELCD9_SHIFT 4
mbed_official 363:12a245e5c745 3389 #define LCD_WF8B_BPELCD50_MASK 0x10u
mbed_official 363:12a245e5c745 3390 #define LCD_WF8B_BPELCD50_SHIFT 4
mbed_official 363:12a245e5c745 3391 #define LCD_WF8B_BPELCD18_MASK 0x10u
mbed_official 363:12a245e5c745 3392 #define LCD_WF8B_BPELCD18_SHIFT 4
mbed_official 363:12a245e5c745 3393 #define LCD_WF8B_BPELCD6_MASK 0x10u
mbed_official 363:12a245e5c745 3394 #define LCD_WF8B_BPELCD6_SHIFT 4
mbed_official 363:12a245e5c745 3395 #define LCD_WF8B_BPELCD17_MASK 0x10u
mbed_official 363:12a245e5c745 3396 #define LCD_WF8B_BPELCD17_SHIFT 4
mbed_official 363:12a245e5c745 3397 #define LCD_WF8B_BPELCD51_MASK 0x10u
mbed_official 363:12a245e5c745 3398 #define LCD_WF8B_BPELCD51_SHIFT 4
mbed_official 363:12a245e5c745 3399 #define LCD_WF8B_BPELCD16_MASK 0x10u
mbed_official 363:12a245e5c745 3400 #define LCD_WF8B_BPELCD16_SHIFT 4
mbed_official 363:12a245e5c745 3401 #define LCD_WF8B_BPELCD56_MASK 0x10u
mbed_official 363:12a245e5c745 3402 #define LCD_WF8B_BPELCD56_SHIFT 4
mbed_official 363:12a245e5c745 3403 #define LCD_WF8B_BPELCD57_MASK 0x10u
mbed_official 363:12a245e5c745 3404 #define LCD_WF8B_BPELCD57_SHIFT 4
mbed_official 363:12a245e5c745 3405 #define LCD_WF8B_BPELCD52_MASK 0x10u
mbed_official 363:12a245e5c745 3406 #define LCD_WF8B_BPELCD52_SHIFT 4
mbed_official 363:12a245e5c745 3407 #define LCD_WF8B_BPELCD1_MASK 0x10u
mbed_official 363:12a245e5c745 3408 #define LCD_WF8B_BPELCD1_SHIFT 4
mbed_official 363:12a245e5c745 3409 #define LCD_WF8B_BPELCD58_MASK 0x10u
mbed_official 363:12a245e5c745 3410 #define LCD_WF8B_BPELCD58_SHIFT 4
mbed_official 363:12a245e5c745 3411 #define LCD_WF8B_BPELCD59_MASK 0x10u
mbed_official 363:12a245e5c745 3412 #define LCD_WF8B_BPELCD59_SHIFT 4
mbed_official 363:12a245e5c745 3413 #define LCD_WF8B_BPELCD53_MASK 0x10u
mbed_official 363:12a245e5c745 3414 #define LCD_WF8B_BPELCD53_SHIFT 4
mbed_official 363:12a245e5c745 3415 #define LCD_WF8B_BPELCD14_MASK 0x10u
mbed_official 363:12a245e5c745 3416 #define LCD_WF8B_BPELCD14_SHIFT 4
mbed_official 363:12a245e5c745 3417 #define LCD_WF8B_BPELCD0_MASK 0x10u
mbed_official 363:12a245e5c745 3418 #define LCD_WF8B_BPELCD0_SHIFT 4
mbed_official 363:12a245e5c745 3419 #define LCD_WF8B_BPELCD60_MASK 0x10u
mbed_official 363:12a245e5c745 3420 #define LCD_WF8B_BPELCD60_SHIFT 4
mbed_official 363:12a245e5c745 3421 #define LCD_WF8B_BPELCD15_MASK 0x10u
mbed_official 363:12a245e5c745 3422 #define LCD_WF8B_BPELCD15_SHIFT 4
mbed_official 363:12a245e5c745 3423 #define LCD_WF8B_BPELCD61_MASK 0x10u
mbed_official 363:12a245e5c745 3424 #define LCD_WF8B_BPELCD61_SHIFT 4
mbed_official 363:12a245e5c745 3425 #define LCD_WF8B_BPELCD54_MASK 0x10u
mbed_official 363:12a245e5c745 3426 #define LCD_WF8B_BPELCD54_SHIFT 4
mbed_official 363:12a245e5c745 3427 #define LCD_WF8B_BPELCD62_MASK 0x10u
mbed_official 363:12a245e5c745 3428 #define LCD_WF8B_BPELCD62_SHIFT 4
mbed_official 363:12a245e5c745 3429 #define LCD_WF8B_BPELCD63_MASK 0x10u
mbed_official 363:12a245e5c745 3430 #define LCD_WF8B_BPELCD63_SHIFT 4
mbed_official 363:12a245e5c745 3431 #define LCD_WF8B_BPELCD55_MASK 0x10u
mbed_official 363:12a245e5c745 3432 #define LCD_WF8B_BPELCD55_SHIFT 4
mbed_official 363:12a245e5c745 3433 #define LCD_WF8B_BPELCD4_MASK 0x10u
mbed_official 363:12a245e5c745 3434 #define LCD_WF8B_BPELCD4_SHIFT 4
mbed_official 363:12a245e5c745 3435 #define LCD_WF8B_BPFLCD13_MASK 0x20u
mbed_official 363:12a245e5c745 3436 #define LCD_WF8B_BPFLCD13_SHIFT 5
mbed_official 363:12a245e5c745 3437 #define LCD_WF8B_BPFLCD39_MASK 0x20u
mbed_official 363:12a245e5c745 3438 #define LCD_WF8B_BPFLCD39_SHIFT 5
mbed_official 363:12a245e5c745 3439 #define LCD_WF8B_BPFLCD55_MASK 0x20u
mbed_official 363:12a245e5c745 3440 #define LCD_WF8B_BPFLCD55_SHIFT 5
mbed_official 363:12a245e5c745 3441 #define LCD_WF8B_BPFLCD47_MASK 0x20u
mbed_official 363:12a245e5c745 3442 #define LCD_WF8B_BPFLCD47_SHIFT 5
mbed_official 363:12a245e5c745 3443 #define LCD_WF8B_BPFLCD63_MASK 0x20u
mbed_official 363:12a245e5c745 3444 #define LCD_WF8B_BPFLCD63_SHIFT 5
mbed_official 363:12a245e5c745 3445 #define LCD_WF8B_BPFLCD43_MASK 0x20u
mbed_official 363:12a245e5c745 3446 #define LCD_WF8B_BPFLCD43_SHIFT 5
mbed_official 363:12a245e5c745 3447 #define LCD_WF8B_BPFLCD5_MASK 0x20u
mbed_official 363:12a245e5c745 3448 #define LCD_WF8B_BPFLCD5_SHIFT 5
mbed_official 363:12a245e5c745 3449 #define LCD_WF8B_BPFLCD62_MASK 0x20u
mbed_official 363:12a245e5c745 3450 #define LCD_WF8B_BPFLCD62_SHIFT 5
mbed_official 363:12a245e5c745 3451 #define LCD_WF8B_BPFLCD14_MASK 0x20u
mbed_official 363:12a245e5c745 3452 #define LCD_WF8B_BPFLCD14_SHIFT 5
mbed_official 363:12a245e5c745 3453 #define LCD_WF8B_BPFLCD24_MASK 0x20u
mbed_official 363:12a245e5c745 3454 #define LCD_WF8B_BPFLCD24_SHIFT 5
mbed_official 363:12a245e5c745 3455 #define LCD_WF8B_BPFLCD54_MASK 0x20u
mbed_official 363:12a245e5c745 3456 #define LCD_WF8B_BPFLCD54_SHIFT 5
mbed_official 363:12a245e5c745 3457 #define LCD_WF8B_BPFLCD15_MASK 0x20u
mbed_official 363:12a245e5c745 3458 #define LCD_WF8B_BPFLCD15_SHIFT 5
mbed_official 363:12a245e5c745 3459 #define LCD_WF8B_BPFLCD32_MASK 0x20u
mbed_official 363:12a245e5c745 3460 #define LCD_WF8B_BPFLCD32_SHIFT 5
mbed_official 363:12a245e5c745 3461 #define LCD_WF8B_BPFLCD61_MASK 0x20u
mbed_official 363:12a245e5c745 3462 #define LCD_WF8B_BPFLCD61_SHIFT 5
mbed_official 363:12a245e5c745 3463 #define LCD_WF8B_BPFLCD25_MASK 0x20u
mbed_official 363:12a245e5c745 3464 #define LCD_WF8B_BPFLCD25_SHIFT 5
mbed_official 363:12a245e5c745 3465 #define LCD_WF8B_BPFLCD60_MASK 0x20u
mbed_official 363:12a245e5c745 3466 #define LCD_WF8B_BPFLCD60_SHIFT 5
mbed_official 363:12a245e5c745 3467 #define LCD_WF8B_BPFLCD41_MASK 0x20u
mbed_official 363:12a245e5c745 3468 #define LCD_WF8B_BPFLCD41_SHIFT 5
mbed_official 363:12a245e5c745 3469 #define LCD_WF8B_BPFLCD33_MASK 0x20u
mbed_official 363:12a245e5c745 3470 #define LCD_WF8B_BPFLCD33_SHIFT 5
mbed_official 363:12a245e5c745 3471 #define LCD_WF8B_BPFLCD53_MASK 0x20u
mbed_official 363:12a245e5c745 3472 #define LCD_WF8B_BPFLCD53_SHIFT 5
mbed_official 363:12a245e5c745 3473 #define LCD_WF8B_BPFLCD59_MASK 0x20u
mbed_official 363:12a245e5c745 3474 #define LCD_WF8B_BPFLCD59_SHIFT 5
mbed_official 363:12a245e5c745 3475 #define LCD_WF8B_BPFLCD0_MASK 0x20u
mbed_official 363:12a245e5c745 3476 #define LCD_WF8B_BPFLCD0_SHIFT 5
mbed_official 363:12a245e5c745 3477 #define LCD_WF8B_BPFLCD46_MASK 0x20u
mbed_official 363:12a245e5c745 3478 #define LCD_WF8B_BPFLCD46_SHIFT 5
mbed_official 363:12a245e5c745 3479 #define LCD_WF8B_BPFLCD58_MASK 0x20u
mbed_official 363:12a245e5c745 3480 #define LCD_WF8B_BPFLCD58_SHIFT 5
mbed_official 363:12a245e5c745 3481 #define LCD_WF8B_BPFLCD26_MASK 0x20u
mbed_official 363:12a245e5c745 3482 #define LCD_WF8B_BPFLCD26_SHIFT 5
mbed_official 363:12a245e5c745 3483 #define LCD_WF8B_BPFLCD36_MASK 0x20u
mbed_official 363:12a245e5c745 3484 #define LCD_WF8B_BPFLCD36_SHIFT 5
mbed_official 363:12a245e5c745 3485 #define LCD_WF8B_BPFLCD10_MASK 0x20u
mbed_official 363:12a245e5c745 3486 #define LCD_WF8B_BPFLCD10_SHIFT 5
mbed_official 363:12a245e5c745 3487 #define LCD_WF8B_BPFLCD52_MASK 0x20u
mbed_official 363:12a245e5c745 3488 #define LCD_WF8B_BPFLCD52_SHIFT 5
mbed_official 363:12a245e5c745 3489 #define LCD_WF8B_BPFLCD57_MASK 0x20u
mbed_official 363:12a245e5c745 3490 #define LCD_WF8B_BPFLCD57_SHIFT 5
mbed_official 363:12a245e5c745 3491 #define LCD_WF8B_BPFLCD27_MASK 0x20u
mbed_official 363:12a245e5c745 3492 #define LCD_WF8B_BPFLCD27_SHIFT 5
mbed_official 363:12a245e5c745 3493 #define LCD_WF8B_BPFLCD11_MASK 0x20u
mbed_official 363:12a245e5c745 3494 #define LCD_WF8B_BPFLCD11_SHIFT 5
mbed_official 363:12a245e5c745 3495 #define LCD_WF8B_BPFLCD56_MASK 0x20u
mbed_official 363:12a245e5c745 3496 #define LCD_WF8B_BPFLCD56_SHIFT 5
mbed_official 363:12a245e5c745 3497 #define LCD_WF8B_BPFLCD1_MASK 0x20u
mbed_official 363:12a245e5c745 3498 #define LCD_WF8B_BPFLCD1_SHIFT 5
mbed_official 363:12a245e5c745 3499 #define LCD_WF8B_BPFLCD8_MASK 0x20u
mbed_official 363:12a245e5c745 3500 #define LCD_WF8B_BPFLCD8_SHIFT 5
mbed_official 363:12a245e5c745 3501 #define LCD_WF8B_BPFLCD40_MASK 0x20u
mbed_official 363:12a245e5c745 3502 #define LCD_WF8B_BPFLCD40_SHIFT 5
mbed_official 363:12a245e5c745 3503 #define LCD_WF8B_BPFLCD51_MASK 0x20u
mbed_official 363:12a245e5c745 3504 #define LCD_WF8B_BPFLCD51_SHIFT 5
mbed_official 363:12a245e5c745 3505 #define LCD_WF8B_BPFLCD16_MASK 0x20u
mbed_official 363:12a245e5c745 3506 #define LCD_WF8B_BPFLCD16_SHIFT 5
mbed_official 363:12a245e5c745 3507 #define LCD_WF8B_BPFLCD45_MASK 0x20u
mbed_official 363:12a245e5c745 3508 #define LCD_WF8B_BPFLCD45_SHIFT 5
mbed_official 363:12a245e5c745 3509 #define LCD_WF8B_BPFLCD6_MASK 0x20u
mbed_official 363:12a245e5c745 3510 #define LCD_WF8B_BPFLCD6_SHIFT 5
mbed_official 363:12a245e5c745 3511 #define LCD_WF8B_BPFLCD17_MASK 0x20u
mbed_official 363:12a245e5c745 3512 #define LCD_WF8B_BPFLCD17_SHIFT 5
mbed_official 363:12a245e5c745 3513 #define LCD_WF8B_BPFLCD28_MASK 0x20u
mbed_official 363:12a245e5c745 3514 #define LCD_WF8B_BPFLCD28_SHIFT 5
mbed_official 363:12a245e5c745 3515 #define LCD_WF8B_BPFLCD42_MASK 0x20u
mbed_official 363:12a245e5c745 3516 #define LCD_WF8B_BPFLCD42_SHIFT 5
mbed_official 363:12a245e5c745 3517 #define LCD_WF8B_BPFLCD29_MASK 0x20u
mbed_official 363:12a245e5c745 3518 #define LCD_WF8B_BPFLCD29_SHIFT 5
mbed_official 363:12a245e5c745 3519 #define LCD_WF8B_BPFLCD50_MASK 0x20u
mbed_official 363:12a245e5c745 3520 #define LCD_WF8B_BPFLCD50_SHIFT 5
mbed_official 363:12a245e5c745 3521 #define LCD_WF8B_BPFLCD18_MASK 0x20u
mbed_official 363:12a245e5c745 3522 #define LCD_WF8B_BPFLCD18_SHIFT 5
mbed_official 363:12a245e5c745 3523 #define LCD_WF8B_BPFLCD34_MASK 0x20u
mbed_official 363:12a245e5c745 3524 #define LCD_WF8B_BPFLCD34_SHIFT 5
mbed_official 363:12a245e5c745 3525 #define LCD_WF8B_BPFLCD19_MASK 0x20u
mbed_official 363:12a245e5c745 3526 #define LCD_WF8B_BPFLCD19_SHIFT 5
mbed_official 363:12a245e5c745 3527 #define LCD_WF8B_BPFLCD2_MASK 0x20u
mbed_official 363:12a245e5c745 3528 #define LCD_WF8B_BPFLCD2_SHIFT 5
mbed_official 363:12a245e5c745 3529 #define LCD_WF8B_BPFLCD9_MASK 0x20u
mbed_official 363:12a245e5c745 3530 #define LCD_WF8B_BPFLCD9_SHIFT 5
mbed_official 363:12a245e5c745 3531 #define LCD_WF8B_BPFLCD3_MASK 0x20u
mbed_official 363:12a245e5c745 3532 #define LCD_WF8B_BPFLCD3_SHIFT 5
mbed_official 363:12a245e5c745 3533 #define LCD_WF8B_BPFLCD37_MASK 0x20u
mbed_official 363:12a245e5c745 3534 #define LCD_WF8B_BPFLCD37_SHIFT 5
mbed_official 363:12a245e5c745 3535 #define LCD_WF8B_BPFLCD49_MASK 0x20u
mbed_official 363:12a245e5c745 3536 #define LCD_WF8B_BPFLCD49_SHIFT 5
mbed_official 363:12a245e5c745 3537 #define LCD_WF8B_BPFLCD20_MASK 0x20u
mbed_official 363:12a245e5c745 3538 #define LCD_WF8B_BPFLCD20_SHIFT 5
mbed_official 363:12a245e5c745 3539 #define LCD_WF8B_BPFLCD44_MASK 0x20u
mbed_official 363:12a245e5c745 3540 #define LCD_WF8B_BPFLCD44_SHIFT 5
mbed_official 363:12a245e5c745 3541 #define LCD_WF8B_BPFLCD30_MASK 0x20u
mbed_official 363:12a245e5c745 3542 #define LCD_WF8B_BPFLCD30_SHIFT 5
mbed_official 363:12a245e5c745 3543 #define LCD_WF8B_BPFLCD21_MASK 0x20u
mbed_official 363:12a245e5c745 3544 #define LCD_WF8B_BPFLCD21_SHIFT 5
mbed_official 363:12a245e5c745 3545 #define LCD_WF8B_BPFLCD35_MASK 0x20u
mbed_official 363:12a245e5c745 3546 #define LCD_WF8B_BPFLCD35_SHIFT 5
mbed_official 363:12a245e5c745 3547 #define LCD_WF8B_BPFLCD4_MASK 0x20u
mbed_official 363:12a245e5c745 3548 #define LCD_WF8B_BPFLCD4_SHIFT 5
mbed_official 363:12a245e5c745 3549 #define LCD_WF8B_BPFLCD31_MASK 0x20u
mbed_official 363:12a245e5c745 3550 #define LCD_WF8B_BPFLCD31_SHIFT 5
mbed_official 363:12a245e5c745 3551 #define LCD_WF8B_BPFLCD48_MASK 0x20u
mbed_official 363:12a245e5c745 3552 #define LCD_WF8B_BPFLCD48_SHIFT 5
mbed_official 363:12a245e5c745 3553 #define LCD_WF8B_BPFLCD7_MASK 0x20u
mbed_official 363:12a245e5c745 3554 #define LCD_WF8B_BPFLCD7_SHIFT 5
mbed_official 363:12a245e5c745 3555 #define LCD_WF8B_BPFLCD22_MASK 0x20u
mbed_official 363:12a245e5c745 3556 #define LCD_WF8B_BPFLCD22_SHIFT 5
mbed_official 363:12a245e5c745 3557 #define LCD_WF8B_BPFLCD38_MASK 0x20u
mbed_official 363:12a245e5c745 3558 #define LCD_WF8B_BPFLCD38_SHIFT 5
mbed_official 363:12a245e5c745 3559 #define LCD_WF8B_BPFLCD12_MASK 0x20u
mbed_official 363:12a245e5c745 3560 #define LCD_WF8B_BPFLCD12_SHIFT 5
mbed_official 363:12a245e5c745 3561 #define LCD_WF8B_BPFLCD23_MASK 0x20u
mbed_official 363:12a245e5c745 3562 #define LCD_WF8B_BPFLCD23_SHIFT 5
mbed_official 363:12a245e5c745 3563 #define LCD_WF8B_BPGLCD14_MASK 0x40u
mbed_official 363:12a245e5c745 3564 #define LCD_WF8B_BPGLCD14_SHIFT 6
mbed_official 363:12a245e5c745 3565 #define LCD_WF8B_BPGLCD55_MASK 0x40u
mbed_official 363:12a245e5c745 3566 #define LCD_WF8B_BPGLCD55_SHIFT 6
mbed_official 363:12a245e5c745 3567 #define LCD_WF8B_BPGLCD63_MASK 0x40u
mbed_official 363:12a245e5c745 3568 #define LCD_WF8B_BPGLCD63_SHIFT 6
mbed_official 363:12a245e5c745 3569 #define LCD_WF8B_BPGLCD15_MASK 0x40u
mbed_official 363:12a245e5c745 3570 #define LCD_WF8B_BPGLCD15_SHIFT 6
mbed_official 363:12a245e5c745 3571 #define LCD_WF8B_BPGLCD62_MASK 0x40u
mbed_official 363:12a245e5c745 3572 #define LCD_WF8B_BPGLCD62_SHIFT 6
mbed_official 363:12a245e5c745 3573 #define LCD_WF8B_BPGLCD54_MASK 0x40u
mbed_official 363:12a245e5c745 3574 #define LCD_WF8B_BPGLCD54_SHIFT 6
mbed_official 363:12a245e5c745 3575 #define LCD_WF8B_BPGLCD61_MASK 0x40u
mbed_official 363:12a245e5c745 3576 #define LCD_WF8B_BPGLCD61_SHIFT 6
mbed_official 363:12a245e5c745 3577 #define LCD_WF8B_BPGLCD60_MASK 0x40u
mbed_official 363:12a245e5c745 3578 #define LCD_WF8B_BPGLCD60_SHIFT 6
mbed_official 363:12a245e5c745 3579 #define LCD_WF8B_BPGLCD59_MASK 0x40u
mbed_official 363:12a245e5c745 3580 #define LCD_WF8B_BPGLCD59_SHIFT 6
mbed_official 363:12a245e5c745 3581 #define LCD_WF8B_BPGLCD53_MASK 0x40u
mbed_official 363:12a245e5c745 3582 #define LCD_WF8B_BPGLCD53_SHIFT 6
mbed_official 363:12a245e5c745 3583 #define LCD_WF8B_BPGLCD58_MASK 0x40u
mbed_official 363:12a245e5c745 3584 #define LCD_WF8B_BPGLCD58_SHIFT 6
mbed_official 363:12a245e5c745 3585 #define LCD_WF8B_BPGLCD0_MASK 0x40u
mbed_official 363:12a245e5c745 3586 #define LCD_WF8B_BPGLCD0_SHIFT 6
mbed_official 363:12a245e5c745 3587 #define LCD_WF8B_BPGLCD57_MASK 0x40u
mbed_official 363:12a245e5c745 3588 #define LCD_WF8B_BPGLCD57_SHIFT 6
mbed_official 363:12a245e5c745 3589 #define LCD_WF8B_BPGLCD52_MASK 0x40u
mbed_official 363:12a245e5c745 3590 #define LCD_WF8B_BPGLCD52_SHIFT 6
mbed_official 363:12a245e5c745 3591 #define LCD_WF8B_BPGLCD7_MASK 0x40u
mbed_official 363:12a245e5c745 3592 #define LCD_WF8B_BPGLCD7_SHIFT 6
mbed_official 363:12a245e5c745 3593 #define LCD_WF8B_BPGLCD56_MASK 0x40u
mbed_official 363:12a245e5c745 3594 #define LCD_WF8B_BPGLCD56_SHIFT 6
mbed_official 363:12a245e5c745 3595 #define LCD_WF8B_BPGLCD6_MASK 0x40u
mbed_official 363:12a245e5c745 3596 #define LCD_WF8B_BPGLCD6_SHIFT 6
mbed_official 363:12a245e5c745 3597 #define LCD_WF8B_BPGLCD51_MASK 0x40u
mbed_official 363:12a245e5c745 3598 #define LCD_WF8B_BPGLCD51_SHIFT 6
mbed_official 363:12a245e5c745 3599 #define LCD_WF8B_BPGLCD16_MASK 0x40u
mbed_official 363:12a245e5c745 3600 #define LCD_WF8B_BPGLCD16_SHIFT 6
mbed_official 363:12a245e5c745 3601 #define LCD_WF8B_BPGLCD1_MASK 0x40u
mbed_official 363:12a245e5c745 3602 #define LCD_WF8B_BPGLCD1_SHIFT 6
mbed_official 363:12a245e5c745 3603 #define LCD_WF8B_BPGLCD17_MASK 0x40u
mbed_official 363:12a245e5c745 3604 #define LCD_WF8B_BPGLCD17_SHIFT 6
mbed_official 363:12a245e5c745 3605 #define LCD_WF8B_BPGLCD50_MASK 0x40u
mbed_official 363:12a245e5c745 3606 #define LCD_WF8B_BPGLCD50_SHIFT 6
mbed_official 363:12a245e5c745 3607 #define LCD_WF8B_BPGLCD18_MASK 0x40u
mbed_official 363:12a245e5c745 3608 #define LCD_WF8B_BPGLCD18_SHIFT 6
mbed_official 363:12a245e5c745 3609 #define LCD_WF8B_BPGLCD19_MASK 0x40u
mbed_official 363:12a245e5c745 3610 #define LCD_WF8B_BPGLCD19_SHIFT 6
mbed_official 363:12a245e5c745 3611 #define LCD_WF8B_BPGLCD8_MASK 0x40u
mbed_official 363:12a245e5c745 3612 #define LCD_WF8B_BPGLCD8_SHIFT 6
mbed_official 363:12a245e5c745 3613 #define LCD_WF8B_BPGLCD49_MASK 0x40u
mbed_official 363:12a245e5c745 3614 #define LCD_WF8B_BPGLCD49_SHIFT 6
mbed_official 363:12a245e5c745 3615 #define LCD_WF8B_BPGLCD20_MASK 0x40u
mbed_official 363:12a245e5c745 3616 #define LCD_WF8B_BPGLCD20_SHIFT 6
mbed_official 363:12a245e5c745 3617 #define LCD_WF8B_BPGLCD9_MASK 0x40u
mbed_official 363:12a245e5c745 3618 #define LCD_WF8B_BPGLCD9_SHIFT 6
mbed_official 363:12a245e5c745 3619 #define LCD_WF8B_BPGLCD21_MASK 0x40u
mbed_official 363:12a245e5c745 3620 #define LCD_WF8B_BPGLCD21_SHIFT 6
mbed_official 363:12a245e5c745 3621 #define LCD_WF8B_BPGLCD13_MASK 0x40u
mbed_official 363:12a245e5c745 3622 #define LCD_WF8B_BPGLCD13_SHIFT 6
mbed_official 363:12a245e5c745 3623 #define LCD_WF8B_BPGLCD48_MASK 0x40u
mbed_official 363:12a245e5c745 3624 #define LCD_WF8B_BPGLCD48_SHIFT 6
mbed_official 363:12a245e5c745 3625 #define LCD_WF8B_BPGLCD22_MASK 0x40u
mbed_official 363:12a245e5c745 3626 #define LCD_WF8B_BPGLCD22_SHIFT 6
mbed_official 363:12a245e5c745 3627 #define LCD_WF8B_BPGLCD5_MASK 0x40u
mbed_official 363:12a245e5c745 3628 #define LCD_WF8B_BPGLCD5_SHIFT 6
mbed_official 363:12a245e5c745 3629 #define LCD_WF8B_BPGLCD47_MASK 0x40u
mbed_official 363:12a245e5c745 3630 #define LCD_WF8B_BPGLCD47_SHIFT 6
mbed_official 363:12a245e5c745 3631 #define LCD_WF8B_BPGLCD23_MASK 0x40u
mbed_official 363:12a245e5c745 3632 #define LCD_WF8B_BPGLCD23_SHIFT 6
mbed_official 363:12a245e5c745 3633 #define LCD_WF8B_BPGLCD24_MASK 0x40u
mbed_official 363:12a245e5c745 3634 #define LCD_WF8B_BPGLCD24_SHIFT 6
mbed_official 363:12a245e5c745 3635 #define LCD_WF8B_BPGLCD25_MASK 0x40u
mbed_official 363:12a245e5c745 3636 #define LCD_WF8B_BPGLCD25_SHIFT 6
mbed_official 363:12a245e5c745 3637 #define LCD_WF8B_BPGLCD46_MASK 0x40u
mbed_official 363:12a245e5c745 3638 #define LCD_WF8B_BPGLCD46_SHIFT 6
mbed_official 363:12a245e5c745 3639 #define LCD_WF8B_BPGLCD26_MASK 0x40u
mbed_official 363:12a245e5c745 3640 #define LCD_WF8B_BPGLCD26_SHIFT 6
mbed_official 363:12a245e5c745 3641 #define LCD_WF8B_BPGLCD27_MASK 0x40u
mbed_official 363:12a245e5c745 3642 #define LCD_WF8B_BPGLCD27_SHIFT 6
mbed_official 363:12a245e5c745 3643 #define LCD_WF8B_BPGLCD10_MASK 0x40u
mbed_official 363:12a245e5c745 3644 #define LCD_WF8B_BPGLCD10_SHIFT 6
mbed_official 363:12a245e5c745 3645 #define LCD_WF8B_BPGLCD45_MASK 0x40u
mbed_official 363:12a245e5c745 3646 #define LCD_WF8B_BPGLCD45_SHIFT 6
mbed_official 363:12a245e5c745 3647 #define LCD_WF8B_BPGLCD28_MASK 0x40u
mbed_official 363:12a245e5c745 3648 #define LCD_WF8B_BPGLCD28_SHIFT 6
mbed_official 363:12a245e5c745 3649 #define LCD_WF8B_BPGLCD29_MASK 0x40u
mbed_official 363:12a245e5c745 3650 #define LCD_WF8B_BPGLCD29_SHIFT 6
mbed_official 363:12a245e5c745 3651 #define LCD_WF8B_BPGLCD4_MASK 0x40u
mbed_official 363:12a245e5c745 3652 #define LCD_WF8B_BPGLCD4_SHIFT 6
mbed_official 363:12a245e5c745 3653 #define LCD_WF8B_BPGLCD44_MASK 0x40u
mbed_official 363:12a245e5c745 3654 #define LCD_WF8B_BPGLCD44_SHIFT 6
mbed_official 363:12a245e5c745 3655 #define LCD_WF8B_BPGLCD30_MASK 0x40u
mbed_official 363:12a245e5c745 3656 #define LCD_WF8B_BPGLCD30_SHIFT 6
mbed_official 363:12a245e5c745 3657 #define LCD_WF8B_BPGLCD2_MASK 0x40u
mbed_official 363:12a245e5c745 3658 #define LCD_WF8B_BPGLCD2_SHIFT 6
mbed_official 363:12a245e5c745 3659 #define LCD_WF8B_BPGLCD31_MASK 0x40u
mbed_official 363:12a245e5c745 3660 #define LCD_WF8B_BPGLCD31_SHIFT 6
mbed_official 363:12a245e5c745 3661 #define LCD_WF8B_BPGLCD43_MASK 0x40u
mbed_official 363:12a245e5c745 3662 #define LCD_WF8B_BPGLCD43_SHIFT 6
mbed_official 363:12a245e5c745 3663 #define LCD_WF8B_BPGLCD32_MASK 0x40u
mbed_official 363:12a245e5c745 3664 #define LCD_WF8B_BPGLCD32_SHIFT 6
mbed_official 363:12a245e5c745 3665 #define LCD_WF8B_BPGLCD33_MASK 0x40u
mbed_official 363:12a245e5c745 3666 #define LCD_WF8B_BPGLCD33_SHIFT 6
mbed_official 363:12a245e5c745 3667 #define LCD_WF8B_BPGLCD42_MASK 0x40u
mbed_official 363:12a245e5c745 3668 #define LCD_WF8B_BPGLCD42_SHIFT 6
mbed_official 363:12a245e5c745 3669 #define LCD_WF8B_BPGLCD34_MASK 0x40u
mbed_official 363:12a245e5c745 3670 #define LCD_WF8B_BPGLCD34_SHIFT 6
mbed_official 363:12a245e5c745 3671 #define LCD_WF8B_BPGLCD11_MASK 0x40u
mbed_official 363:12a245e5c745 3672 #define LCD_WF8B_BPGLCD11_SHIFT 6
mbed_official 363:12a245e5c745 3673 #define LCD_WF8B_BPGLCD35_MASK 0x40u
mbed_official 363:12a245e5c745 3674 #define LCD_WF8B_BPGLCD35_SHIFT 6
mbed_official 363:12a245e5c745 3675 #define LCD_WF8B_BPGLCD12_MASK 0x40u
mbed_official 363:12a245e5c745 3676 #define LCD_WF8B_BPGLCD12_SHIFT 6
mbed_official 363:12a245e5c745 3677 #define LCD_WF8B_BPGLCD41_MASK 0x40u
mbed_official 363:12a245e5c745 3678 #define LCD_WF8B_BPGLCD41_SHIFT 6
mbed_official 363:12a245e5c745 3679 #define LCD_WF8B_BPGLCD36_MASK 0x40u
mbed_official 363:12a245e5c745 3680 #define LCD_WF8B_BPGLCD36_SHIFT 6
mbed_official 363:12a245e5c745 3681 #define LCD_WF8B_BPGLCD3_MASK 0x40u
mbed_official 363:12a245e5c745 3682 #define LCD_WF8B_BPGLCD3_SHIFT 6
mbed_official 363:12a245e5c745 3683 #define LCD_WF8B_BPGLCD37_MASK 0x40u
mbed_official 363:12a245e5c745 3684 #define LCD_WF8B_BPGLCD37_SHIFT 6
mbed_official 363:12a245e5c745 3685 #define LCD_WF8B_BPGLCD40_MASK 0x40u
mbed_official 363:12a245e5c745 3686 #define LCD_WF8B_BPGLCD40_SHIFT 6
mbed_official 363:12a245e5c745 3687 #define LCD_WF8B_BPGLCD38_MASK 0x40u
mbed_official 363:12a245e5c745 3688 #define LCD_WF8B_BPGLCD38_SHIFT 6
mbed_official 363:12a245e5c745 3689 #define LCD_WF8B_BPGLCD39_MASK 0x40u
mbed_official 363:12a245e5c745 3690 #define LCD_WF8B_BPGLCD39_SHIFT 6
mbed_official 363:12a245e5c745 3691 #define LCD_WF8B_BPHLCD63_MASK 0x80u
mbed_official 363:12a245e5c745 3692 #define LCD_WF8B_BPHLCD63_SHIFT 7
mbed_official 363:12a245e5c745 3693 #define LCD_WF8B_BPHLCD62_MASK 0x80u
mbed_official 363:12a245e5c745 3694 #define LCD_WF8B_BPHLCD62_SHIFT 7
mbed_official 363:12a245e5c745 3695 #define LCD_WF8B_BPHLCD61_MASK 0x80u
mbed_official 363:12a245e5c745 3696 #define LCD_WF8B_BPHLCD61_SHIFT 7
mbed_official 363:12a245e5c745 3697 #define LCD_WF8B_BPHLCD60_MASK 0x80u
mbed_official 363:12a245e5c745 3698 #define LCD_WF8B_BPHLCD60_SHIFT 7
mbed_official 363:12a245e5c745 3699 #define LCD_WF8B_BPHLCD59_MASK 0x80u
mbed_official 363:12a245e5c745 3700 #define LCD_WF8B_BPHLCD59_SHIFT 7
mbed_official 363:12a245e5c745 3701 #define LCD_WF8B_BPHLCD58_MASK 0x80u
mbed_official 363:12a245e5c745 3702 #define LCD_WF8B_BPHLCD58_SHIFT 7
mbed_official 363:12a245e5c745 3703 #define LCD_WF8B_BPHLCD57_MASK 0x80u
mbed_official 363:12a245e5c745 3704 #define LCD_WF8B_BPHLCD57_SHIFT 7
mbed_official 363:12a245e5c745 3705 #define LCD_WF8B_BPHLCD0_MASK 0x80u
mbed_official 363:12a245e5c745 3706 #define LCD_WF8B_BPHLCD0_SHIFT 7
mbed_official 363:12a245e5c745 3707 #define LCD_WF8B_BPHLCD56_MASK 0x80u
mbed_official 363:12a245e5c745 3708 #define LCD_WF8B_BPHLCD56_SHIFT 7
mbed_official 363:12a245e5c745 3709 #define LCD_WF8B_BPHLCD55_MASK 0x80u
mbed_official 363:12a245e5c745 3710 #define LCD_WF8B_BPHLCD55_SHIFT 7
mbed_official 363:12a245e5c745 3711 #define LCD_WF8B_BPHLCD54_MASK 0x80u
mbed_official 363:12a245e5c745 3712 #define LCD_WF8B_BPHLCD54_SHIFT 7
mbed_official 363:12a245e5c745 3713 #define LCD_WF8B_BPHLCD53_MASK 0x80u
mbed_official 363:12a245e5c745 3714 #define LCD_WF8B_BPHLCD53_SHIFT 7
mbed_official 363:12a245e5c745 3715 #define LCD_WF8B_BPHLCD52_MASK 0x80u
mbed_official 363:12a245e5c745 3716 #define LCD_WF8B_BPHLCD52_SHIFT 7
mbed_official 363:12a245e5c745 3717 #define LCD_WF8B_BPHLCD51_MASK 0x80u
mbed_official 363:12a245e5c745 3718 #define LCD_WF8B_BPHLCD51_SHIFT 7
mbed_official 363:12a245e5c745 3719 #define LCD_WF8B_BPHLCD50_MASK 0x80u
mbed_official 363:12a245e5c745 3720 #define LCD_WF8B_BPHLCD50_SHIFT 7
mbed_official 363:12a245e5c745 3721 #define LCD_WF8B_BPHLCD1_MASK 0x80u
mbed_official 363:12a245e5c745 3722 #define LCD_WF8B_BPHLCD1_SHIFT 7
mbed_official 363:12a245e5c745 3723 #define LCD_WF8B_BPHLCD49_MASK 0x80u
mbed_official 363:12a245e5c745 3724 #define LCD_WF8B_BPHLCD49_SHIFT 7
mbed_official 363:12a245e5c745 3725 #define LCD_WF8B_BPHLCD48_MASK 0x80u
mbed_official 363:12a245e5c745 3726 #define LCD_WF8B_BPHLCD48_SHIFT 7
mbed_official 363:12a245e5c745 3727 #define LCD_WF8B_BPHLCD47_MASK 0x80u
mbed_official 363:12a245e5c745 3728 #define LCD_WF8B_BPHLCD47_SHIFT 7
mbed_official 363:12a245e5c745 3729 #define LCD_WF8B_BPHLCD46_MASK 0x80u
mbed_official 363:12a245e5c745 3730 #define LCD_WF8B_BPHLCD46_SHIFT 7
mbed_official 363:12a245e5c745 3731 #define LCD_WF8B_BPHLCD45_MASK 0x80u
mbed_official 363:12a245e5c745 3732 #define LCD_WF8B_BPHLCD45_SHIFT 7
mbed_official 363:12a245e5c745 3733 #define LCD_WF8B_BPHLCD44_MASK 0x80u
mbed_official 363:12a245e5c745 3734 #define LCD_WF8B_BPHLCD44_SHIFT 7
mbed_official 363:12a245e5c745 3735 #define LCD_WF8B_BPHLCD43_MASK 0x80u
mbed_official 363:12a245e5c745 3736 #define LCD_WF8B_BPHLCD43_SHIFT 7
mbed_official 363:12a245e5c745 3737 #define LCD_WF8B_BPHLCD2_MASK 0x80u
mbed_official 363:12a245e5c745 3738 #define LCD_WF8B_BPHLCD2_SHIFT 7
mbed_official 363:12a245e5c745 3739 #define LCD_WF8B_BPHLCD42_MASK 0x80u
mbed_official 363:12a245e5c745 3740 #define LCD_WF8B_BPHLCD42_SHIFT 7
mbed_official 363:12a245e5c745 3741 #define LCD_WF8B_BPHLCD41_MASK 0x80u
mbed_official 363:12a245e5c745 3742 #define LCD_WF8B_BPHLCD41_SHIFT 7
mbed_official 363:12a245e5c745 3743 #define LCD_WF8B_BPHLCD40_MASK 0x80u
mbed_official 363:12a245e5c745 3744 #define LCD_WF8B_BPHLCD40_SHIFT 7
mbed_official 363:12a245e5c745 3745 #define LCD_WF8B_BPHLCD39_MASK 0x80u
mbed_official 363:12a245e5c745 3746 #define LCD_WF8B_BPHLCD39_SHIFT 7
mbed_official 363:12a245e5c745 3747 #define LCD_WF8B_BPHLCD38_MASK 0x80u
mbed_official 363:12a245e5c745 3748 #define LCD_WF8B_BPHLCD38_SHIFT 7
mbed_official 363:12a245e5c745 3749 #define LCD_WF8B_BPHLCD37_MASK 0x80u
mbed_official 363:12a245e5c745 3750 #define LCD_WF8B_BPHLCD37_SHIFT 7
mbed_official 363:12a245e5c745 3751 #define LCD_WF8B_BPHLCD36_MASK 0x80u
mbed_official 363:12a245e5c745 3752 #define LCD_WF8B_BPHLCD36_SHIFT 7
mbed_official 363:12a245e5c745 3753 #define LCD_WF8B_BPHLCD3_MASK 0x80u
mbed_official 363:12a245e5c745 3754 #define LCD_WF8B_BPHLCD3_SHIFT 7
mbed_official 363:12a245e5c745 3755 #define LCD_WF8B_BPHLCD35_MASK 0x80u
mbed_official 363:12a245e5c745 3756 #define LCD_WF8B_BPHLCD35_SHIFT 7
mbed_official 363:12a245e5c745 3757 #define LCD_WF8B_BPHLCD34_MASK 0x80u
mbed_official 363:12a245e5c745 3758 #define LCD_WF8B_BPHLCD34_SHIFT 7
mbed_official 363:12a245e5c745 3759 #define LCD_WF8B_BPHLCD33_MASK 0x80u
mbed_official 363:12a245e5c745 3760 #define LCD_WF8B_BPHLCD33_SHIFT 7
mbed_official 363:12a245e5c745 3761 #define LCD_WF8B_BPHLCD32_MASK 0x80u
mbed_official 363:12a245e5c745 3762 #define LCD_WF8B_BPHLCD32_SHIFT 7
mbed_official 363:12a245e5c745 3763 #define LCD_WF8B_BPHLCD31_MASK 0x80u
mbed_official 363:12a245e5c745 3764 #define LCD_WF8B_BPHLCD31_SHIFT 7
mbed_official 363:12a245e5c745 3765 #define LCD_WF8B_BPHLCD30_MASK 0x80u
mbed_official 363:12a245e5c745 3766 #define LCD_WF8B_BPHLCD30_SHIFT 7
mbed_official 363:12a245e5c745 3767 #define LCD_WF8B_BPHLCD29_MASK 0x80u
mbed_official 363:12a245e5c745 3768 #define LCD_WF8B_BPHLCD29_SHIFT 7
mbed_official 363:12a245e5c745 3769 #define LCD_WF8B_BPHLCD4_MASK 0x80u
mbed_official 363:12a245e5c745 3770 #define LCD_WF8B_BPHLCD4_SHIFT 7
mbed_official 363:12a245e5c745 3771 #define LCD_WF8B_BPHLCD28_MASK 0x80u
mbed_official 363:12a245e5c745 3772 #define LCD_WF8B_BPHLCD28_SHIFT 7
mbed_official 363:12a245e5c745 3773 #define LCD_WF8B_BPHLCD27_MASK 0x80u
mbed_official 363:12a245e5c745 3774 #define LCD_WF8B_BPHLCD27_SHIFT 7
mbed_official 363:12a245e5c745 3775 #define LCD_WF8B_BPHLCD26_MASK 0x80u
mbed_official 363:12a245e5c745 3776 #define LCD_WF8B_BPHLCD26_SHIFT 7
mbed_official 363:12a245e5c745 3777 #define LCD_WF8B_BPHLCD25_MASK 0x80u
mbed_official 363:12a245e5c745 3778 #define LCD_WF8B_BPHLCD25_SHIFT 7
mbed_official 363:12a245e5c745 3779 #define LCD_WF8B_BPHLCD24_MASK 0x80u
mbed_official 363:12a245e5c745 3780 #define LCD_WF8B_BPHLCD24_SHIFT 7
mbed_official 363:12a245e5c745 3781 #define LCD_WF8B_BPHLCD23_MASK 0x80u
mbed_official 363:12a245e5c745 3782 #define LCD_WF8B_BPHLCD23_SHIFT 7
mbed_official 363:12a245e5c745 3783 #define LCD_WF8B_BPHLCD22_MASK 0x80u
mbed_official 363:12a245e5c745 3784 #define LCD_WF8B_BPHLCD22_SHIFT 7
mbed_official 363:12a245e5c745 3785 #define LCD_WF8B_BPHLCD5_MASK 0x80u
mbed_official 363:12a245e5c745 3786 #define LCD_WF8B_BPHLCD5_SHIFT 7
mbed_official 363:12a245e5c745 3787 #define LCD_WF8B_BPHLCD21_MASK 0x80u
mbed_official 363:12a245e5c745 3788 #define LCD_WF8B_BPHLCD21_SHIFT 7
mbed_official 363:12a245e5c745 3789 #define LCD_WF8B_BPHLCD20_MASK 0x80u
mbed_official 363:12a245e5c745 3790 #define LCD_WF8B_BPHLCD20_SHIFT 7
mbed_official 363:12a245e5c745 3791 #define LCD_WF8B_BPHLCD19_MASK 0x80u
mbed_official 363:12a245e5c745 3792 #define LCD_WF8B_BPHLCD19_SHIFT 7
mbed_official 363:12a245e5c745 3793 #define LCD_WF8B_BPHLCD18_MASK 0x80u
mbed_official 363:12a245e5c745 3794 #define LCD_WF8B_BPHLCD18_SHIFT 7
mbed_official 363:12a245e5c745 3795 #define LCD_WF8B_BPHLCD17_MASK 0x80u
mbed_official 363:12a245e5c745 3796 #define LCD_WF8B_BPHLCD17_SHIFT 7
mbed_official 363:12a245e5c745 3797 #define LCD_WF8B_BPHLCD16_MASK 0x80u
mbed_official 363:12a245e5c745 3798 #define LCD_WF8B_BPHLCD16_SHIFT 7
mbed_official 363:12a245e5c745 3799 #define LCD_WF8B_BPHLCD15_MASK 0x80u
mbed_official 363:12a245e5c745 3800 #define LCD_WF8B_BPHLCD15_SHIFT 7
mbed_official 363:12a245e5c745 3801 #define LCD_WF8B_BPHLCD6_MASK 0x80u
mbed_official 363:12a245e5c745 3802 #define LCD_WF8B_BPHLCD6_SHIFT 7
mbed_official 363:12a245e5c745 3803 #define LCD_WF8B_BPHLCD14_MASK 0x80u
mbed_official 363:12a245e5c745 3804 #define LCD_WF8B_BPHLCD14_SHIFT 7
mbed_official 363:12a245e5c745 3805 #define LCD_WF8B_BPHLCD13_MASK 0x80u
mbed_official 363:12a245e5c745 3806 #define LCD_WF8B_BPHLCD13_SHIFT 7
mbed_official 363:12a245e5c745 3807 #define LCD_WF8B_BPHLCD12_MASK 0x80u
mbed_official 363:12a245e5c745 3808 #define LCD_WF8B_BPHLCD12_SHIFT 7
mbed_official 363:12a245e5c745 3809 #define LCD_WF8B_BPHLCD11_MASK 0x80u
mbed_official 363:12a245e5c745 3810 #define LCD_WF8B_BPHLCD11_SHIFT 7
mbed_official 363:12a245e5c745 3811 #define LCD_WF8B_BPHLCD10_MASK 0x80u
mbed_official 363:12a245e5c745 3812 #define LCD_WF8B_BPHLCD10_SHIFT 7
mbed_official 363:12a245e5c745 3813 #define LCD_WF8B_BPHLCD9_MASK 0x80u
mbed_official 363:12a245e5c745 3814 #define LCD_WF8B_BPHLCD9_SHIFT 7
mbed_official 363:12a245e5c745 3815 #define LCD_WF8B_BPHLCD8_MASK 0x80u
mbed_official 363:12a245e5c745 3816 #define LCD_WF8B_BPHLCD8_SHIFT 7
mbed_official 363:12a245e5c745 3817 #define LCD_WF8B_BPHLCD7_MASK 0x80u
mbed_official 363:12a245e5c745 3818 #define LCD_WF8B_BPHLCD7_SHIFT 7
mbed_official 363:12a245e5c745 3819
mbed_official 363:12a245e5c745 3820 /*!
mbed_official 363:12a245e5c745 3821 * @}
mbed_official 363:12a245e5c745 3822 */ /* end of group LCD_Register_Masks */
mbed_official 363:12a245e5c745 3823
mbed_official 363:12a245e5c745 3824
mbed_official 363:12a245e5c745 3825 /* LCD - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 3826 /** Peripheral LCD base address */
mbed_official 363:12a245e5c745 3827 #define LCD_BASE (0x40053000u)
mbed_official 363:12a245e5c745 3828 /** Peripheral LCD base pointer */
mbed_official 363:12a245e5c745 3829 #define LCD ((LCD_Type *)LCD_BASE)
mbed_official 363:12a245e5c745 3830 #define LCD_BASE_PTR (LCD)
mbed_official 363:12a245e5c745 3831 /** Array initializer of LCD peripheral base addresses */
mbed_official 363:12a245e5c745 3832 #define LCD_BASE_ADDRS { LCD_BASE }
mbed_official 363:12a245e5c745 3833 /** Array initializer of LCD peripheral base pointers */
mbed_official 363:12a245e5c745 3834 #define LCD_BASE_PTRS { LCD }
mbed_official 363:12a245e5c745 3835 /** Interrupt vectors for the LCD peripheral type */
mbed_official 363:12a245e5c745 3836 #define LCD_LCD_IRQS { LCD_IRQn }
mbed_official 363:12a245e5c745 3837
mbed_official 363:12a245e5c745 3838 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 3839 -- LCD - Register accessor macros
mbed_official 363:12a245e5c745 3840 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 3841
mbed_official 363:12a245e5c745 3842 /*!
mbed_official 363:12a245e5c745 3843 * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
mbed_official 363:12a245e5c745 3844 * @{
mbed_official 363:12a245e5c745 3845 */
mbed_official 363:12a245e5c745 3846
mbed_official 363:12a245e5c745 3847
mbed_official 363:12a245e5c745 3848 /* LCD - Register instance definitions */
mbed_official 363:12a245e5c745 3849 /* LCD */
mbed_official 363:12a245e5c745 3850 #define LCD_GCR LCD_GCR_REG(LCD)
mbed_official 363:12a245e5c745 3851 #define LCD_AR LCD_AR_REG(LCD)
mbed_official 363:12a245e5c745 3852 #define LCD_FDCR LCD_FDCR_REG(LCD)
mbed_official 363:12a245e5c745 3853 #define LCD_FDSR LCD_FDSR_REG(LCD)
mbed_official 363:12a245e5c745 3854 #define LCD_PENL LCD_PEN_REG(LCD,0)
mbed_official 363:12a245e5c745 3855 #define LCD_PENH LCD_PEN_REG(LCD,1)
mbed_official 363:12a245e5c745 3856 #define LCD_BPENL LCD_BPEN_REG(LCD,0)
mbed_official 363:12a245e5c745 3857 #define LCD_BPENH LCD_BPEN_REG(LCD,1)
mbed_official 363:12a245e5c745 3858 #define LCD_WF0 LCD_WF8B_REG(LCD,0)
mbed_official 363:12a245e5c745 3859 #define LCD_WF3TO0 LCD_WF_REG(LCD,0)
mbed_official 363:12a245e5c745 3860 #define LCD_WF1 LCD_WF8B_REG(LCD,1)
mbed_official 363:12a245e5c745 3861 #define LCD_WF2 LCD_WF8B_REG(LCD,2)
mbed_official 363:12a245e5c745 3862 #define LCD_WF3 LCD_WF8B_REG(LCD,3)
mbed_official 363:12a245e5c745 3863 #define LCD_WF4 LCD_WF8B_REG(LCD,4)
mbed_official 363:12a245e5c745 3864 #define LCD_WF7TO4 LCD_WF_REG(LCD,1)
mbed_official 363:12a245e5c745 3865 #define LCD_WF5 LCD_WF8B_REG(LCD,5)
mbed_official 363:12a245e5c745 3866 #define LCD_WF6 LCD_WF8B_REG(LCD,6)
mbed_official 363:12a245e5c745 3867 #define LCD_WF7 LCD_WF8B_REG(LCD,7)
mbed_official 363:12a245e5c745 3868 #define LCD_WF11TO8 LCD_WF_REG(LCD,2)
mbed_official 363:12a245e5c745 3869 #define LCD_WF8 LCD_WF8B_REG(LCD,8)
mbed_official 363:12a245e5c745 3870 #define LCD_WF9 LCD_WF8B_REG(LCD,9)
mbed_official 363:12a245e5c745 3871 #define LCD_WF10 LCD_WF8B_REG(LCD,10)
mbed_official 363:12a245e5c745 3872 #define LCD_WF11 LCD_WF8B_REG(LCD,11)
mbed_official 363:12a245e5c745 3873 #define LCD_WF12 LCD_WF8B_REG(LCD,12)
mbed_official 363:12a245e5c745 3874 #define LCD_WF15TO12 LCD_WF_REG(LCD,3)
mbed_official 363:12a245e5c745 3875 #define LCD_WF13 LCD_WF8B_REG(LCD,13)
mbed_official 363:12a245e5c745 3876 #define LCD_WF14 LCD_WF8B_REG(LCD,14)
mbed_official 363:12a245e5c745 3877 #define LCD_WF15 LCD_WF8B_REG(LCD,15)
mbed_official 363:12a245e5c745 3878 #define LCD_WF16 LCD_WF8B_REG(LCD,16)
mbed_official 363:12a245e5c745 3879 #define LCD_WF19TO16 LCD_WF_REG(LCD,4)
mbed_official 363:12a245e5c745 3880 #define LCD_WF17 LCD_WF8B_REG(LCD,17)
mbed_official 363:12a245e5c745 3881 #define LCD_WF18 LCD_WF8B_REG(LCD,18)
mbed_official 363:12a245e5c745 3882 #define LCD_WF19 LCD_WF8B_REG(LCD,19)
mbed_official 363:12a245e5c745 3883 #define LCD_WF20 LCD_WF8B_REG(LCD,20)
mbed_official 363:12a245e5c745 3884 #define LCD_WF23TO20 LCD_WF_REG(LCD,5)
mbed_official 363:12a245e5c745 3885 #define LCD_WF21 LCD_WF8B_REG(LCD,21)
mbed_official 363:12a245e5c745 3886 #define LCD_WF22 LCD_WF8B_REG(LCD,22)
mbed_official 363:12a245e5c745 3887 #define LCD_WF23 LCD_WF8B_REG(LCD,23)
mbed_official 363:12a245e5c745 3888 #define LCD_WF24 LCD_WF8B_REG(LCD,24)
mbed_official 363:12a245e5c745 3889 #define LCD_WF27TO24 LCD_WF_REG(LCD,6)
mbed_official 363:12a245e5c745 3890 #define LCD_WF25 LCD_WF8B_REG(LCD,25)
mbed_official 363:12a245e5c745 3891 #define LCD_WF26 LCD_WF8B_REG(LCD,26)
mbed_official 363:12a245e5c745 3892 #define LCD_WF27 LCD_WF8B_REG(LCD,27)
mbed_official 363:12a245e5c745 3893 #define LCD_WF28 LCD_WF8B_REG(LCD,28)
mbed_official 363:12a245e5c745 3894 #define LCD_WF31TO28 LCD_WF_REG(LCD,7)
mbed_official 363:12a245e5c745 3895 #define LCD_WF29 LCD_WF8B_REG(LCD,29)
mbed_official 363:12a245e5c745 3896 #define LCD_WF30 LCD_WF8B_REG(LCD,30)
mbed_official 363:12a245e5c745 3897 #define LCD_WF31 LCD_WF8B_REG(LCD,31)
mbed_official 363:12a245e5c745 3898 #define LCD_WF32 LCD_WF8B_REG(LCD,32)
mbed_official 363:12a245e5c745 3899 #define LCD_WF35TO32 LCD_WF_REG(LCD,8)
mbed_official 363:12a245e5c745 3900 #define LCD_WF33 LCD_WF8B_REG(LCD,33)
mbed_official 363:12a245e5c745 3901 #define LCD_WF34 LCD_WF8B_REG(LCD,34)
mbed_official 363:12a245e5c745 3902 #define LCD_WF35 LCD_WF8B_REG(LCD,35)
mbed_official 363:12a245e5c745 3903 #define LCD_WF36 LCD_WF8B_REG(LCD,36)
mbed_official 363:12a245e5c745 3904 #define LCD_WF39TO36 LCD_WF_REG(LCD,9)
mbed_official 363:12a245e5c745 3905 #define LCD_WF37 LCD_WF8B_REG(LCD,37)
mbed_official 363:12a245e5c745 3906 #define LCD_WF38 LCD_WF8B_REG(LCD,38)
mbed_official 363:12a245e5c745 3907 #define LCD_WF39 LCD_WF8B_REG(LCD,39)
mbed_official 363:12a245e5c745 3908 #define LCD_WF40 LCD_WF8B_REG(LCD,40)
mbed_official 363:12a245e5c745 3909 #define LCD_WF43TO40 LCD_WF_REG(LCD,10)
mbed_official 363:12a245e5c745 3910 #define LCD_WF41 LCD_WF8B_REG(LCD,41)
mbed_official 363:12a245e5c745 3911 #define LCD_WF42 LCD_WF8B_REG(LCD,42)
mbed_official 363:12a245e5c745 3912 #define LCD_WF43 LCD_WF8B_REG(LCD,43)
mbed_official 363:12a245e5c745 3913 #define LCD_WF44 LCD_WF8B_REG(LCD,44)
mbed_official 363:12a245e5c745 3914 #define LCD_WF47TO44 LCD_WF_REG(LCD,11)
mbed_official 363:12a245e5c745 3915 #define LCD_WF45 LCD_WF8B_REG(LCD,45)
mbed_official 363:12a245e5c745 3916 #define LCD_WF46 LCD_WF8B_REG(LCD,46)
mbed_official 363:12a245e5c745 3917 #define LCD_WF47 LCD_WF8B_REG(LCD,47)
mbed_official 363:12a245e5c745 3918 #define LCD_WF48 LCD_WF8B_REG(LCD,48)
mbed_official 363:12a245e5c745 3919 #define LCD_WF51TO48 LCD_WF_REG(LCD,12)
mbed_official 363:12a245e5c745 3920 #define LCD_WF49 LCD_WF8B_REG(LCD,49)
mbed_official 363:12a245e5c745 3921 #define LCD_WF50 LCD_WF8B_REG(LCD,50)
mbed_official 363:12a245e5c745 3922 #define LCD_WF51 LCD_WF8B_REG(LCD,51)
mbed_official 363:12a245e5c745 3923 #define LCD_WF52 LCD_WF8B_REG(LCD,52)
mbed_official 363:12a245e5c745 3924 #define LCD_WF55TO52 LCD_WF_REG(LCD,13)
mbed_official 363:12a245e5c745 3925 #define LCD_WF53 LCD_WF8B_REG(LCD,53)
mbed_official 363:12a245e5c745 3926 #define LCD_WF54 LCD_WF8B_REG(LCD,54)
mbed_official 363:12a245e5c745 3927 #define LCD_WF55 LCD_WF8B_REG(LCD,55)
mbed_official 363:12a245e5c745 3928 #define LCD_WF56 LCD_WF8B_REG(LCD,56)
mbed_official 363:12a245e5c745 3929 #define LCD_WF59TO56 LCD_WF_REG(LCD,14)
mbed_official 363:12a245e5c745 3930 #define LCD_WF57 LCD_WF8B_REG(LCD,57)
mbed_official 363:12a245e5c745 3931 #define LCD_WF58 LCD_WF8B_REG(LCD,58)
mbed_official 363:12a245e5c745 3932 #define LCD_WF59 LCD_WF8B_REG(LCD,59)
mbed_official 363:12a245e5c745 3933 #define LCD_WF60 LCD_WF8B_REG(LCD,60)
mbed_official 363:12a245e5c745 3934 #define LCD_WF63TO60 LCD_WF_REG(LCD,15)
mbed_official 363:12a245e5c745 3935 #define LCD_WF61 LCD_WF8B_REG(LCD,61)
mbed_official 363:12a245e5c745 3936 #define LCD_WF62 LCD_WF8B_REG(LCD,62)
mbed_official 363:12a245e5c745 3937 #define LCD_WF63 LCD_WF8B_REG(LCD,63)
mbed_official 363:12a245e5c745 3938
mbed_official 363:12a245e5c745 3939 /* LCD - Register array accessors */
mbed_official 363:12a245e5c745 3940 #define LCD_PEN(index) LCD_PEN_REG(LCD,index)
mbed_official 363:12a245e5c745 3941 #define LCD_BPEN(index) LCD_BPEN_REG(LCD,index)
mbed_official 363:12a245e5c745 3942 #define LCD_WF(index2) LCD_WF_REG(LCD,index2)
mbed_official 363:12a245e5c745 3943 #define LCD_WF8B(index2) LCD_WF8B_REG(LCD,index2)
mbed_official 363:12a245e5c745 3944
mbed_official 363:12a245e5c745 3945 /*!
mbed_official 363:12a245e5c745 3946 * @}
mbed_official 363:12a245e5c745 3947 */ /* end of group LCD_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 3948
mbed_official 363:12a245e5c745 3949
mbed_official 363:12a245e5c745 3950 /*!
mbed_official 363:12a245e5c745 3951 * @}
mbed_official 363:12a245e5c745 3952 */ /* end of group LCD_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 3953
mbed_official 363:12a245e5c745 3954
mbed_official 363:12a245e5c745 3955 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 3956 -- LLWU Peripheral Access Layer
mbed_official 363:12a245e5c745 3957 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 3958
mbed_official 363:12a245e5c745 3959 /*!
mbed_official 363:12a245e5c745 3960 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
mbed_official 363:12a245e5c745 3961 * @{
mbed_official 363:12a245e5c745 3962 */
mbed_official 363:12a245e5c745 3963
mbed_official 363:12a245e5c745 3964 /** LLWU - Register Layout Typedef */
mbed_official 363:12a245e5c745 3965 typedef struct {
mbed_official 363:12a245e5c745 3966 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
mbed_official 363:12a245e5c745 3967 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
mbed_official 363:12a245e5c745 3968 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
mbed_official 363:12a245e5c745 3969 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
mbed_official 363:12a245e5c745 3970 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
mbed_official 363:12a245e5c745 3971 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
mbed_official 363:12a245e5c745 3972 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
mbed_official 363:12a245e5c745 3973 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
mbed_official 363:12a245e5c745 3974 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
mbed_official 363:12a245e5c745 3975 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
mbed_official 363:12a245e5c745 3976 } LLWU_Type, *LLWU_MemMapPtr;
mbed_official 363:12a245e5c745 3977
mbed_official 363:12a245e5c745 3978 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 3979 -- LLWU - Register accessor macros
mbed_official 363:12a245e5c745 3980 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 3981
mbed_official 363:12a245e5c745 3982 /*!
mbed_official 363:12a245e5c745 3983 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
mbed_official 363:12a245e5c745 3984 * @{
mbed_official 363:12a245e5c745 3985 */
mbed_official 363:12a245e5c745 3986
mbed_official 363:12a245e5c745 3987
mbed_official 363:12a245e5c745 3988 /* LLWU - Register accessors */
mbed_official 363:12a245e5c745 3989 #define LLWU_PE1_REG(base) ((base)->PE1)
mbed_official 363:12a245e5c745 3990 #define LLWU_PE2_REG(base) ((base)->PE2)
mbed_official 363:12a245e5c745 3991 #define LLWU_PE3_REG(base) ((base)->PE3)
mbed_official 363:12a245e5c745 3992 #define LLWU_PE4_REG(base) ((base)->PE4)
mbed_official 363:12a245e5c745 3993 #define LLWU_ME_REG(base) ((base)->ME)
mbed_official 363:12a245e5c745 3994 #define LLWU_F1_REG(base) ((base)->F1)
mbed_official 363:12a245e5c745 3995 #define LLWU_F2_REG(base) ((base)->F2)
mbed_official 363:12a245e5c745 3996 #define LLWU_F3_REG(base) ((base)->F3)
mbed_official 363:12a245e5c745 3997 #define LLWU_FILT1_REG(base) ((base)->FILT1)
mbed_official 363:12a245e5c745 3998 #define LLWU_FILT2_REG(base) ((base)->FILT2)
mbed_official 363:12a245e5c745 3999
mbed_official 363:12a245e5c745 4000 /*!
mbed_official 363:12a245e5c745 4001 * @}
mbed_official 363:12a245e5c745 4002 */ /* end of group LLWU_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4003
mbed_official 363:12a245e5c745 4004
mbed_official 363:12a245e5c745 4005 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4006 -- LLWU Register Masks
mbed_official 363:12a245e5c745 4007 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4008
mbed_official 363:12a245e5c745 4009 /*!
mbed_official 363:12a245e5c745 4010 * @addtogroup LLWU_Register_Masks LLWU Register Masks
mbed_official 363:12a245e5c745 4011 * @{
mbed_official 363:12a245e5c745 4012 */
mbed_official 363:12a245e5c745 4013
mbed_official 363:12a245e5c745 4014 /* PE1 Bit Fields */
mbed_official 363:12a245e5c745 4015 #define LLWU_PE1_WUPE0_MASK 0x3u
mbed_official 363:12a245e5c745 4016 #define LLWU_PE1_WUPE0_SHIFT 0
mbed_official 363:12a245e5c745 4017 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
mbed_official 363:12a245e5c745 4018 #define LLWU_PE1_WUPE1_MASK 0xCu
mbed_official 363:12a245e5c745 4019 #define LLWU_PE1_WUPE1_SHIFT 2
mbed_official 363:12a245e5c745 4020 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
mbed_official 363:12a245e5c745 4021 #define LLWU_PE1_WUPE2_MASK 0x30u
mbed_official 363:12a245e5c745 4022 #define LLWU_PE1_WUPE2_SHIFT 4
mbed_official 363:12a245e5c745 4023 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
mbed_official 363:12a245e5c745 4024 #define LLWU_PE1_WUPE3_MASK 0xC0u
mbed_official 363:12a245e5c745 4025 #define LLWU_PE1_WUPE3_SHIFT 6
mbed_official 363:12a245e5c745 4026 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
mbed_official 363:12a245e5c745 4027 /* PE2 Bit Fields */
mbed_official 363:12a245e5c745 4028 #define LLWU_PE2_WUPE4_MASK 0x3u
mbed_official 363:12a245e5c745 4029 #define LLWU_PE2_WUPE4_SHIFT 0
mbed_official 363:12a245e5c745 4030 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
mbed_official 363:12a245e5c745 4031 #define LLWU_PE2_WUPE5_MASK 0xCu
mbed_official 363:12a245e5c745 4032 #define LLWU_PE2_WUPE5_SHIFT 2
mbed_official 363:12a245e5c745 4033 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
mbed_official 363:12a245e5c745 4034 #define LLWU_PE2_WUPE6_MASK 0x30u
mbed_official 363:12a245e5c745 4035 #define LLWU_PE2_WUPE6_SHIFT 4
mbed_official 363:12a245e5c745 4036 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
mbed_official 363:12a245e5c745 4037 #define LLWU_PE2_WUPE7_MASK 0xC0u
mbed_official 363:12a245e5c745 4038 #define LLWU_PE2_WUPE7_SHIFT 6
mbed_official 363:12a245e5c745 4039 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
mbed_official 363:12a245e5c745 4040 /* PE3 Bit Fields */
mbed_official 363:12a245e5c745 4041 #define LLWU_PE3_WUPE8_MASK 0x3u
mbed_official 363:12a245e5c745 4042 #define LLWU_PE3_WUPE8_SHIFT 0
mbed_official 363:12a245e5c745 4043 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
mbed_official 363:12a245e5c745 4044 #define LLWU_PE3_WUPE9_MASK 0xCu
mbed_official 363:12a245e5c745 4045 #define LLWU_PE3_WUPE9_SHIFT 2
mbed_official 363:12a245e5c745 4046 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
mbed_official 363:12a245e5c745 4047 #define LLWU_PE3_WUPE10_MASK 0x30u
mbed_official 363:12a245e5c745 4048 #define LLWU_PE3_WUPE10_SHIFT 4
mbed_official 363:12a245e5c745 4049 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
mbed_official 363:12a245e5c745 4050 #define LLWU_PE3_WUPE11_MASK 0xC0u
mbed_official 363:12a245e5c745 4051 #define LLWU_PE3_WUPE11_SHIFT 6
mbed_official 363:12a245e5c745 4052 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
mbed_official 363:12a245e5c745 4053 /* PE4 Bit Fields */
mbed_official 363:12a245e5c745 4054 #define LLWU_PE4_WUPE12_MASK 0x3u
mbed_official 363:12a245e5c745 4055 #define LLWU_PE4_WUPE12_SHIFT 0
mbed_official 363:12a245e5c745 4056 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
mbed_official 363:12a245e5c745 4057 #define LLWU_PE4_WUPE13_MASK 0xCu
mbed_official 363:12a245e5c745 4058 #define LLWU_PE4_WUPE13_SHIFT 2
mbed_official 363:12a245e5c745 4059 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
mbed_official 363:12a245e5c745 4060 #define LLWU_PE4_WUPE14_MASK 0x30u
mbed_official 363:12a245e5c745 4061 #define LLWU_PE4_WUPE14_SHIFT 4
mbed_official 363:12a245e5c745 4062 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
mbed_official 363:12a245e5c745 4063 #define LLWU_PE4_WUPE15_MASK 0xC0u
mbed_official 363:12a245e5c745 4064 #define LLWU_PE4_WUPE15_SHIFT 6
mbed_official 363:12a245e5c745 4065 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
mbed_official 363:12a245e5c745 4066 /* ME Bit Fields */
mbed_official 363:12a245e5c745 4067 #define LLWU_ME_WUME0_MASK 0x1u
mbed_official 363:12a245e5c745 4068 #define LLWU_ME_WUME0_SHIFT 0
mbed_official 363:12a245e5c745 4069 #define LLWU_ME_WUME1_MASK 0x2u
mbed_official 363:12a245e5c745 4070 #define LLWU_ME_WUME1_SHIFT 1
mbed_official 363:12a245e5c745 4071 #define LLWU_ME_WUME2_MASK 0x4u
mbed_official 363:12a245e5c745 4072 #define LLWU_ME_WUME2_SHIFT 2
mbed_official 363:12a245e5c745 4073 #define LLWU_ME_WUME3_MASK 0x8u
mbed_official 363:12a245e5c745 4074 #define LLWU_ME_WUME3_SHIFT 3
mbed_official 363:12a245e5c745 4075 #define LLWU_ME_WUME4_MASK 0x10u
mbed_official 363:12a245e5c745 4076 #define LLWU_ME_WUME4_SHIFT 4
mbed_official 363:12a245e5c745 4077 #define LLWU_ME_WUME5_MASK 0x20u
mbed_official 363:12a245e5c745 4078 #define LLWU_ME_WUME5_SHIFT 5
mbed_official 363:12a245e5c745 4079 #define LLWU_ME_WUME6_MASK 0x40u
mbed_official 363:12a245e5c745 4080 #define LLWU_ME_WUME6_SHIFT 6
mbed_official 363:12a245e5c745 4081 #define LLWU_ME_WUME7_MASK 0x80u
mbed_official 363:12a245e5c745 4082 #define LLWU_ME_WUME7_SHIFT 7
mbed_official 363:12a245e5c745 4083 /* F1 Bit Fields */
mbed_official 363:12a245e5c745 4084 #define LLWU_F1_WUF0_MASK 0x1u
mbed_official 363:12a245e5c745 4085 #define LLWU_F1_WUF0_SHIFT 0
mbed_official 363:12a245e5c745 4086 #define LLWU_F1_WUF1_MASK 0x2u
mbed_official 363:12a245e5c745 4087 #define LLWU_F1_WUF1_SHIFT 1
mbed_official 363:12a245e5c745 4088 #define LLWU_F1_WUF2_MASK 0x4u
mbed_official 363:12a245e5c745 4089 #define LLWU_F1_WUF2_SHIFT 2
mbed_official 363:12a245e5c745 4090 #define LLWU_F1_WUF3_MASK 0x8u
mbed_official 363:12a245e5c745 4091 #define LLWU_F1_WUF3_SHIFT 3
mbed_official 363:12a245e5c745 4092 #define LLWU_F1_WUF4_MASK 0x10u
mbed_official 363:12a245e5c745 4093 #define LLWU_F1_WUF4_SHIFT 4
mbed_official 363:12a245e5c745 4094 #define LLWU_F1_WUF5_MASK 0x20u
mbed_official 363:12a245e5c745 4095 #define LLWU_F1_WUF5_SHIFT 5
mbed_official 363:12a245e5c745 4096 #define LLWU_F1_WUF6_MASK 0x40u
mbed_official 363:12a245e5c745 4097 #define LLWU_F1_WUF6_SHIFT 6
mbed_official 363:12a245e5c745 4098 #define LLWU_F1_WUF7_MASK 0x80u
mbed_official 363:12a245e5c745 4099 #define LLWU_F1_WUF7_SHIFT 7
mbed_official 363:12a245e5c745 4100 /* F2 Bit Fields */
mbed_official 363:12a245e5c745 4101 #define LLWU_F2_WUF8_MASK 0x1u
mbed_official 363:12a245e5c745 4102 #define LLWU_F2_WUF8_SHIFT 0
mbed_official 363:12a245e5c745 4103 #define LLWU_F2_WUF9_MASK 0x2u
mbed_official 363:12a245e5c745 4104 #define LLWU_F2_WUF9_SHIFT 1
mbed_official 363:12a245e5c745 4105 #define LLWU_F2_WUF10_MASK 0x4u
mbed_official 363:12a245e5c745 4106 #define LLWU_F2_WUF10_SHIFT 2
mbed_official 363:12a245e5c745 4107 #define LLWU_F2_WUF11_MASK 0x8u
mbed_official 363:12a245e5c745 4108 #define LLWU_F2_WUF11_SHIFT 3
mbed_official 363:12a245e5c745 4109 #define LLWU_F2_WUF12_MASK 0x10u
mbed_official 363:12a245e5c745 4110 #define LLWU_F2_WUF12_SHIFT 4
mbed_official 363:12a245e5c745 4111 #define LLWU_F2_WUF13_MASK 0x20u
mbed_official 363:12a245e5c745 4112 #define LLWU_F2_WUF13_SHIFT 5
mbed_official 363:12a245e5c745 4113 #define LLWU_F2_WUF14_MASK 0x40u
mbed_official 363:12a245e5c745 4114 #define LLWU_F2_WUF14_SHIFT 6
mbed_official 363:12a245e5c745 4115 #define LLWU_F2_WUF15_MASK 0x80u
mbed_official 363:12a245e5c745 4116 #define LLWU_F2_WUF15_SHIFT 7
mbed_official 363:12a245e5c745 4117 /* F3 Bit Fields */
mbed_official 363:12a245e5c745 4118 #define LLWU_F3_MWUF0_MASK 0x1u
mbed_official 363:12a245e5c745 4119 #define LLWU_F3_MWUF0_SHIFT 0
mbed_official 363:12a245e5c745 4120 #define LLWU_F3_MWUF1_MASK 0x2u
mbed_official 363:12a245e5c745 4121 #define LLWU_F3_MWUF1_SHIFT 1
mbed_official 363:12a245e5c745 4122 #define LLWU_F3_MWUF2_MASK 0x4u
mbed_official 363:12a245e5c745 4123 #define LLWU_F3_MWUF2_SHIFT 2
mbed_official 363:12a245e5c745 4124 #define LLWU_F3_MWUF3_MASK 0x8u
mbed_official 363:12a245e5c745 4125 #define LLWU_F3_MWUF3_SHIFT 3
mbed_official 363:12a245e5c745 4126 #define LLWU_F3_MWUF4_MASK 0x10u
mbed_official 363:12a245e5c745 4127 #define LLWU_F3_MWUF4_SHIFT 4
mbed_official 363:12a245e5c745 4128 #define LLWU_F3_MWUF5_MASK 0x20u
mbed_official 363:12a245e5c745 4129 #define LLWU_F3_MWUF5_SHIFT 5
mbed_official 363:12a245e5c745 4130 #define LLWU_F3_MWUF6_MASK 0x40u
mbed_official 363:12a245e5c745 4131 #define LLWU_F3_MWUF6_SHIFT 6
mbed_official 363:12a245e5c745 4132 #define LLWU_F3_MWUF7_MASK 0x80u
mbed_official 363:12a245e5c745 4133 #define LLWU_F3_MWUF7_SHIFT 7
mbed_official 363:12a245e5c745 4134 /* FILT1 Bit Fields */
mbed_official 363:12a245e5c745 4135 #define LLWU_FILT1_FILTSEL_MASK 0xFu
mbed_official 363:12a245e5c745 4136 #define LLWU_FILT1_FILTSEL_SHIFT 0
mbed_official 363:12a245e5c745 4137 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
mbed_official 363:12a245e5c745 4138 #define LLWU_FILT1_FILTE_MASK 0x60u
mbed_official 363:12a245e5c745 4139 #define LLWU_FILT1_FILTE_SHIFT 5
mbed_official 363:12a245e5c745 4140 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
mbed_official 363:12a245e5c745 4141 #define LLWU_FILT1_FILTF_MASK 0x80u
mbed_official 363:12a245e5c745 4142 #define LLWU_FILT1_FILTF_SHIFT 7
mbed_official 363:12a245e5c745 4143 /* FILT2 Bit Fields */
mbed_official 363:12a245e5c745 4144 #define LLWU_FILT2_FILTSEL_MASK 0xFu
mbed_official 363:12a245e5c745 4145 #define LLWU_FILT2_FILTSEL_SHIFT 0
mbed_official 363:12a245e5c745 4146 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
mbed_official 363:12a245e5c745 4147 #define LLWU_FILT2_FILTE_MASK 0x60u
mbed_official 363:12a245e5c745 4148 #define LLWU_FILT2_FILTE_SHIFT 5
mbed_official 363:12a245e5c745 4149 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
mbed_official 363:12a245e5c745 4150 #define LLWU_FILT2_FILTF_MASK 0x80u
mbed_official 363:12a245e5c745 4151 #define LLWU_FILT2_FILTF_SHIFT 7
mbed_official 363:12a245e5c745 4152
mbed_official 363:12a245e5c745 4153 /*!
mbed_official 363:12a245e5c745 4154 * @}
mbed_official 363:12a245e5c745 4155 */ /* end of group LLWU_Register_Masks */
mbed_official 363:12a245e5c745 4156
mbed_official 363:12a245e5c745 4157
mbed_official 363:12a245e5c745 4158 /* LLWU - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 4159 /** Peripheral LLWU base address */
mbed_official 363:12a245e5c745 4160 #define LLWU_BASE (0x4007C000u)
mbed_official 363:12a245e5c745 4161 /** Peripheral LLWU base pointer */
mbed_official 363:12a245e5c745 4162 #define LLWU ((LLWU_Type *)LLWU_BASE)
mbed_official 363:12a245e5c745 4163 #define LLWU_BASE_PTR (LLWU)
mbed_official 363:12a245e5c745 4164 /** Array initializer of LLWU peripheral base addresses */
mbed_official 363:12a245e5c745 4165 #define LLWU_BASE_ADDRS { LLWU_BASE }
mbed_official 363:12a245e5c745 4166 /** Array initializer of LLWU peripheral base pointers */
mbed_official 363:12a245e5c745 4167 #define LLWU_BASE_PTRS { LLWU }
mbed_official 363:12a245e5c745 4168 /** Interrupt vectors for the LLWU peripheral type */
mbed_official 363:12a245e5c745 4169 #define LLWU_IRQS { LLWU_IRQn }
mbed_official 363:12a245e5c745 4170
mbed_official 363:12a245e5c745 4171 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4172 -- LLWU - Register accessor macros
mbed_official 363:12a245e5c745 4173 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4174
mbed_official 363:12a245e5c745 4175 /*!
mbed_official 363:12a245e5c745 4176 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
mbed_official 363:12a245e5c745 4177 * @{
mbed_official 363:12a245e5c745 4178 */
mbed_official 363:12a245e5c745 4179
mbed_official 363:12a245e5c745 4180
mbed_official 363:12a245e5c745 4181 /* LLWU - Register instance definitions */
mbed_official 363:12a245e5c745 4182 /* LLWU */
mbed_official 363:12a245e5c745 4183 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
mbed_official 363:12a245e5c745 4184 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
mbed_official 363:12a245e5c745 4185 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
mbed_official 363:12a245e5c745 4186 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
mbed_official 363:12a245e5c745 4187 #define LLWU_ME LLWU_ME_REG(LLWU)
mbed_official 363:12a245e5c745 4188 #define LLWU_F1 LLWU_F1_REG(LLWU)
mbed_official 363:12a245e5c745 4189 #define LLWU_F2 LLWU_F2_REG(LLWU)
mbed_official 363:12a245e5c745 4190 #define LLWU_F3 LLWU_F3_REG(LLWU)
mbed_official 363:12a245e5c745 4191 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
mbed_official 363:12a245e5c745 4192 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
mbed_official 363:12a245e5c745 4193
mbed_official 363:12a245e5c745 4194 /*!
mbed_official 363:12a245e5c745 4195 * @}
mbed_official 363:12a245e5c745 4196 */ /* end of group LLWU_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4197
mbed_official 363:12a245e5c745 4198
mbed_official 363:12a245e5c745 4199 /*!
mbed_official 363:12a245e5c745 4200 * @}
mbed_official 363:12a245e5c745 4201 */ /* end of group LLWU_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 4202
mbed_official 363:12a245e5c745 4203
mbed_official 363:12a245e5c745 4204 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4205 -- LPTMR Peripheral Access Layer
mbed_official 363:12a245e5c745 4206 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4207
mbed_official 363:12a245e5c745 4208 /*!
mbed_official 363:12a245e5c745 4209 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
mbed_official 363:12a245e5c745 4210 * @{
mbed_official 363:12a245e5c745 4211 */
mbed_official 363:12a245e5c745 4212
mbed_official 363:12a245e5c745 4213 /** LPTMR - Register Layout Typedef */
mbed_official 363:12a245e5c745 4214 typedef struct {
mbed_official 363:12a245e5c745 4215 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
mbed_official 363:12a245e5c745 4216 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
mbed_official 363:12a245e5c745 4217 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
mbed_official 363:12a245e5c745 4218 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
mbed_official 363:12a245e5c745 4219 } LPTMR_Type, *LPTMR_MemMapPtr;
mbed_official 363:12a245e5c745 4220
mbed_official 363:12a245e5c745 4221 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4222 -- LPTMR - Register accessor macros
mbed_official 363:12a245e5c745 4223 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4224
mbed_official 363:12a245e5c745 4225 /*!
mbed_official 363:12a245e5c745 4226 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
mbed_official 363:12a245e5c745 4227 * @{
mbed_official 363:12a245e5c745 4228 */
mbed_official 363:12a245e5c745 4229
mbed_official 363:12a245e5c745 4230
mbed_official 363:12a245e5c745 4231 /* LPTMR - Register accessors */
mbed_official 363:12a245e5c745 4232 #define LPTMR_CSR_REG(base) ((base)->CSR)
mbed_official 363:12a245e5c745 4233 #define LPTMR_PSR_REG(base) ((base)->PSR)
mbed_official 363:12a245e5c745 4234 #define LPTMR_CMR_REG(base) ((base)->CMR)
mbed_official 363:12a245e5c745 4235 #define LPTMR_CNR_REG(base) ((base)->CNR)
mbed_official 363:12a245e5c745 4236
mbed_official 363:12a245e5c745 4237 /*!
mbed_official 363:12a245e5c745 4238 * @}
mbed_official 363:12a245e5c745 4239 */ /* end of group LPTMR_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4240
mbed_official 363:12a245e5c745 4241
mbed_official 363:12a245e5c745 4242 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4243 -- LPTMR Register Masks
mbed_official 363:12a245e5c745 4244 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4245
mbed_official 363:12a245e5c745 4246 /*!
mbed_official 363:12a245e5c745 4247 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
mbed_official 363:12a245e5c745 4248 * @{
mbed_official 363:12a245e5c745 4249 */
mbed_official 363:12a245e5c745 4250
mbed_official 363:12a245e5c745 4251 /* CSR Bit Fields */
mbed_official 363:12a245e5c745 4252 #define LPTMR_CSR_TEN_MASK 0x1u
mbed_official 363:12a245e5c745 4253 #define LPTMR_CSR_TEN_SHIFT 0
mbed_official 363:12a245e5c745 4254 #define LPTMR_CSR_TMS_MASK 0x2u
mbed_official 363:12a245e5c745 4255 #define LPTMR_CSR_TMS_SHIFT 1
mbed_official 363:12a245e5c745 4256 #define LPTMR_CSR_TFC_MASK 0x4u
mbed_official 363:12a245e5c745 4257 #define LPTMR_CSR_TFC_SHIFT 2
mbed_official 363:12a245e5c745 4258 #define LPTMR_CSR_TPP_MASK 0x8u
mbed_official 363:12a245e5c745 4259 #define LPTMR_CSR_TPP_SHIFT 3
mbed_official 363:12a245e5c745 4260 #define LPTMR_CSR_TPS_MASK 0x30u
mbed_official 363:12a245e5c745 4261 #define LPTMR_CSR_TPS_SHIFT 4
mbed_official 363:12a245e5c745 4262 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
mbed_official 363:12a245e5c745 4263 #define LPTMR_CSR_TIE_MASK 0x40u
mbed_official 363:12a245e5c745 4264 #define LPTMR_CSR_TIE_SHIFT 6
mbed_official 363:12a245e5c745 4265 #define LPTMR_CSR_TCF_MASK 0x80u
mbed_official 363:12a245e5c745 4266 #define LPTMR_CSR_TCF_SHIFT 7
mbed_official 363:12a245e5c745 4267 /* PSR Bit Fields */
mbed_official 363:12a245e5c745 4268 #define LPTMR_PSR_PCS_MASK 0x3u
mbed_official 363:12a245e5c745 4269 #define LPTMR_PSR_PCS_SHIFT 0
mbed_official 363:12a245e5c745 4270 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
mbed_official 363:12a245e5c745 4271 #define LPTMR_PSR_PBYP_MASK 0x4u
mbed_official 363:12a245e5c745 4272 #define LPTMR_PSR_PBYP_SHIFT 2
mbed_official 363:12a245e5c745 4273 #define LPTMR_PSR_PRESCALE_MASK 0x78u
mbed_official 363:12a245e5c745 4274 #define LPTMR_PSR_PRESCALE_SHIFT 3
mbed_official 363:12a245e5c745 4275 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
mbed_official 363:12a245e5c745 4276 /* CMR Bit Fields */
mbed_official 363:12a245e5c745 4277 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
mbed_official 363:12a245e5c745 4278 #define LPTMR_CMR_COMPARE_SHIFT 0
mbed_official 363:12a245e5c745 4279 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
mbed_official 363:12a245e5c745 4280 /* CNR Bit Fields */
mbed_official 363:12a245e5c745 4281 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
mbed_official 363:12a245e5c745 4282 #define LPTMR_CNR_COUNTER_SHIFT 0
mbed_official 363:12a245e5c745 4283 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
mbed_official 363:12a245e5c745 4284
mbed_official 363:12a245e5c745 4285 /*!
mbed_official 363:12a245e5c745 4286 * @}
mbed_official 363:12a245e5c745 4287 */ /* end of group LPTMR_Register_Masks */
mbed_official 363:12a245e5c745 4288
mbed_official 363:12a245e5c745 4289
mbed_official 363:12a245e5c745 4290 /* LPTMR - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 4291 /** Peripheral LPTMR0 base address */
mbed_official 363:12a245e5c745 4292 #define LPTMR0_BASE (0x40040000u)
mbed_official 363:12a245e5c745 4293 /** Peripheral LPTMR0 base pointer */
mbed_official 363:12a245e5c745 4294 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
mbed_official 363:12a245e5c745 4295 #define LPTMR0_BASE_PTR (LPTMR0)
mbed_official 363:12a245e5c745 4296 /** Array initializer of LPTMR peripheral base addresses */
mbed_official 363:12a245e5c745 4297 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
mbed_official 363:12a245e5c745 4298 /** Array initializer of LPTMR peripheral base pointers */
mbed_official 363:12a245e5c745 4299 #define LPTMR_BASE_PTRS { LPTMR0 }
mbed_official 363:12a245e5c745 4300 /** Interrupt vectors for the LPTMR peripheral type */
mbed_official 363:12a245e5c745 4301 #define LPTMR_IRQS { LPTMR0_IRQn }
mbed_official 363:12a245e5c745 4302
mbed_official 363:12a245e5c745 4303 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4304 -- LPTMR - Register accessor macros
mbed_official 363:12a245e5c745 4305 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4306
mbed_official 363:12a245e5c745 4307 /*!
mbed_official 363:12a245e5c745 4308 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
mbed_official 363:12a245e5c745 4309 * @{
mbed_official 363:12a245e5c745 4310 */
mbed_official 363:12a245e5c745 4311
mbed_official 363:12a245e5c745 4312
mbed_official 363:12a245e5c745 4313 /* LPTMR - Register instance definitions */
mbed_official 363:12a245e5c745 4314 /* LPTMR0 */
mbed_official 363:12a245e5c745 4315 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
mbed_official 363:12a245e5c745 4316 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
mbed_official 363:12a245e5c745 4317 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
mbed_official 363:12a245e5c745 4318 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
mbed_official 363:12a245e5c745 4319
mbed_official 363:12a245e5c745 4320 /*!
mbed_official 363:12a245e5c745 4321 * @}
mbed_official 363:12a245e5c745 4322 */ /* end of group LPTMR_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4323
mbed_official 363:12a245e5c745 4324
mbed_official 363:12a245e5c745 4325 /*!
mbed_official 363:12a245e5c745 4326 * @}
mbed_official 363:12a245e5c745 4327 */ /* end of group LPTMR_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 4328
mbed_official 363:12a245e5c745 4329
mbed_official 363:12a245e5c745 4330 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4331 -- LPUART Peripheral Access Layer
mbed_official 363:12a245e5c745 4332 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4333
mbed_official 363:12a245e5c745 4334 /*!
mbed_official 363:12a245e5c745 4335 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
mbed_official 363:12a245e5c745 4336 * @{
mbed_official 363:12a245e5c745 4337 */
mbed_official 363:12a245e5c745 4338
mbed_official 363:12a245e5c745 4339 /** LPUART - Register Layout Typedef */
mbed_official 363:12a245e5c745 4340 typedef struct {
mbed_official 363:12a245e5c745 4341 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
mbed_official 363:12a245e5c745 4342 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
mbed_official 363:12a245e5c745 4343 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
mbed_official 363:12a245e5c745 4344 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
mbed_official 363:12a245e5c745 4345 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
mbed_official 363:12a245e5c745 4346 } LPUART_Type, *LPUART_MemMapPtr;
mbed_official 363:12a245e5c745 4347
mbed_official 363:12a245e5c745 4348 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4349 -- LPUART - Register accessor macros
mbed_official 363:12a245e5c745 4350 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4351
mbed_official 363:12a245e5c745 4352 /*!
mbed_official 363:12a245e5c745 4353 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
mbed_official 363:12a245e5c745 4354 * @{
mbed_official 363:12a245e5c745 4355 */
mbed_official 363:12a245e5c745 4356
mbed_official 363:12a245e5c745 4357
mbed_official 363:12a245e5c745 4358 /* LPUART - Register accessors */
mbed_official 363:12a245e5c745 4359 #define LPUART_BAUD_REG(base) ((base)->BAUD)
mbed_official 363:12a245e5c745 4360 #define LPUART_STAT_REG(base) ((base)->STAT)
mbed_official 363:12a245e5c745 4361 #define LPUART_CTRL_REG(base) ((base)->CTRL)
mbed_official 363:12a245e5c745 4362 #define LPUART_DATA_REG(base) ((base)->DATA)
mbed_official 363:12a245e5c745 4363 #define LPUART_MATCH_REG(base) ((base)->MATCH)
mbed_official 363:12a245e5c745 4364
mbed_official 363:12a245e5c745 4365 /*!
mbed_official 363:12a245e5c745 4366 * @}
mbed_official 363:12a245e5c745 4367 */ /* end of group LPUART_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4368
mbed_official 363:12a245e5c745 4369
mbed_official 363:12a245e5c745 4370 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4371 -- LPUART Register Masks
mbed_official 363:12a245e5c745 4372 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4373
mbed_official 363:12a245e5c745 4374 /*!
mbed_official 363:12a245e5c745 4375 * @addtogroup LPUART_Register_Masks LPUART Register Masks
mbed_official 363:12a245e5c745 4376 * @{
mbed_official 363:12a245e5c745 4377 */
mbed_official 363:12a245e5c745 4378
mbed_official 363:12a245e5c745 4379 /* BAUD Bit Fields */
mbed_official 363:12a245e5c745 4380 #define LPUART_BAUD_SBR_MASK 0x1FFFu
mbed_official 363:12a245e5c745 4381 #define LPUART_BAUD_SBR_SHIFT 0
mbed_official 363:12a245e5c745 4382 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
mbed_official 363:12a245e5c745 4383 #define LPUART_BAUD_SBNS_MASK 0x2000u
mbed_official 363:12a245e5c745 4384 #define LPUART_BAUD_SBNS_SHIFT 13
mbed_official 363:12a245e5c745 4385 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u
mbed_official 363:12a245e5c745 4386 #define LPUART_BAUD_RXEDGIE_SHIFT 14
mbed_official 363:12a245e5c745 4387 #define LPUART_BAUD_LBKDIE_MASK 0x8000u
mbed_official 363:12a245e5c745 4388 #define LPUART_BAUD_LBKDIE_SHIFT 15
mbed_official 363:12a245e5c745 4389 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
mbed_official 363:12a245e5c745 4390 #define LPUART_BAUD_RESYNCDIS_SHIFT 16
mbed_official 363:12a245e5c745 4391 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
mbed_official 363:12a245e5c745 4392 #define LPUART_BAUD_BOTHEDGE_SHIFT 17
mbed_official 363:12a245e5c745 4393 #define LPUART_BAUD_MATCFG_MASK 0xC0000u
mbed_official 363:12a245e5c745 4394 #define LPUART_BAUD_MATCFG_SHIFT 18
mbed_official 363:12a245e5c745 4395 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
mbed_official 363:12a245e5c745 4396 #define LPUART_BAUD_RDMAE_MASK 0x200000u
mbed_official 363:12a245e5c745 4397 #define LPUART_BAUD_RDMAE_SHIFT 21
mbed_official 363:12a245e5c745 4398 #define LPUART_BAUD_TDMAE_MASK 0x800000u
mbed_official 363:12a245e5c745 4399 #define LPUART_BAUD_TDMAE_SHIFT 23
mbed_official 363:12a245e5c745 4400 #define LPUART_BAUD_OSR_MASK 0x1F000000u
mbed_official 363:12a245e5c745 4401 #define LPUART_BAUD_OSR_SHIFT 24
mbed_official 363:12a245e5c745 4402 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
mbed_official 363:12a245e5c745 4403 #define LPUART_BAUD_M10_MASK 0x20000000u
mbed_official 363:12a245e5c745 4404 #define LPUART_BAUD_M10_SHIFT 29
mbed_official 363:12a245e5c745 4405 #define LPUART_BAUD_MAEN2_MASK 0x40000000u
mbed_official 363:12a245e5c745 4406 #define LPUART_BAUD_MAEN2_SHIFT 30
mbed_official 363:12a245e5c745 4407 #define LPUART_BAUD_MAEN1_MASK 0x80000000u
mbed_official 363:12a245e5c745 4408 #define LPUART_BAUD_MAEN1_SHIFT 31
mbed_official 363:12a245e5c745 4409 /* STAT Bit Fields */
mbed_official 363:12a245e5c745 4410 #define LPUART_STAT_MA2F_MASK 0x4000u
mbed_official 363:12a245e5c745 4411 #define LPUART_STAT_MA2F_SHIFT 14
mbed_official 363:12a245e5c745 4412 #define LPUART_STAT_MA1F_MASK 0x8000u
mbed_official 363:12a245e5c745 4413 #define LPUART_STAT_MA1F_SHIFT 15
mbed_official 363:12a245e5c745 4414 #define LPUART_STAT_PF_MASK 0x10000u
mbed_official 363:12a245e5c745 4415 #define LPUART_STAT_PF_SHIFT 16
mbed_official 363:12a245e5c745 4416 #define LPUART_STAT_FE_MASK 0x20000u
mbed_official 363:12a245e5c745 4417 #define LPUART_STAT_FE_SHIFT 17
mbed_official 363:12a245e5c745 4418 #define LPUART_STAT_NF_MASK 0x40000u
mbed_official 363:12a245e5c745 4419 #define LPUART_STAT_NF_SHIFT 18
mbed_official 363:12a245e5c745 4420 #define LPUART_STAT_OR_MASK 0x80000u
mbed_official 363:12a245e5c745 4421 #define LPUART_STAT_OR_SHIFT 19
mbed_official 363:12a245e5c745 4422 #define LPUART_STAT_IDLE_MASK 0x100000u
mbed_official 363:12a245e5c745 4423 #define LPUART_STAT_IDLE_SHIFT 20
mbed_official 363:12a245e5c745 4424 #define LPUART_STAT_RDRF_MASK 0x200000u
mbed_official 363:12a245e5c745 4425 #define LPUART_STAT_RDRF_SHIFT 21
mbed_official 363:12a245e5c745 4426 #define LPUART_STAT_TC_MASK 0x400000u
mbed_official 363:12a245e5c745 4427 #define LPUART_STAT_TC_SHIFT 22
mbed_official 363:12a245e5c745 4428 #define LPUART_STAT_TDRE_MASK 0x800000u
mbed_official 363:12a245e5c745 4429 #define LPUART_STAT_TDRE_SHIFT 23
mbed_official 363:12a245e5c745 4430 #define LPUART_STAT_RAF_MASK 0x1000000u
mbed_official 363:12a245e5c745 4431 #define LPUART_STAT_RAF_SHIFT 24
mbed_official 363:12a245e5c745 4432 #define LPUART_STAT_LBKDE_MASK 0x2000000u
mbed_official 363:12a245e5c745 4433 #define LPUART_STAT_LBKDE_SHIFT 25
mbed_official 363:12a245e5c745 4434 #define LPUART_STAT_BRK13_MASK 0x4000000u
mbed_official 363:12a245e5c745 4435 #define LPUART_STAT_BRK13_SHIFT 26
mbed_official 363:12a245e5c745 4436 #define LPUART_STAT_RWUID_MASK 0x8000000u
mbed_official 363:12a245e5c745 4437 #define LPUART_STAT_RWUID_SHIFT 27
mbed_official 363:12a245e5c745 4438 #define LPUART_STAT_RXINV_MASK 0x10000000u
mbed_official 363:12a245e5c745 4439 #define LPUART_STAT_RXINV_SHIFT 28
mbed_official 363:12a245e5c745 4440 #define LPUART_STAT_MSBF_MASK 0x20000000u
mbed_official 363:12a245e5c745 4441 #define LPUART_STAT_MSBF_SHIFT 29
mbed_official 363:12a245e5c745 4442 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u
mbed_official 363:12a245e5c745 4443 #define LPUART_STAT_RXEDGIF_SHIFT 30
mbed_official 363:12a245e5c745 4444 #define LPUART_STAT_LBKDIF_MASK 0x80000000u
mbed_official 363:12a245e5c745 4445 #define LPUART_STAT_LBKDIF_SHIFT 31
mbed_official 363:12a245e5c745 4446 /* CTRL Bit Fields */
mbed_official 363:12a245e5c745 4447 #define LPUART_CTRL_PT_MASK 0x1u
mbed_official 363:12a245e5c745 4448 #define LPUART_CTRL_PT_SHIFT 0
mbed_official 363:12a245e5c745 4449 #define LPUART_CTRL_PE_MASK 0x2u
mbed_official 363:12a245e5c745 4450 #define LPUART_CTRL_PE_SHIFT 1
mbed_official 363:12a245e5c745 4451 #define LPUART_CTRL_ILT_MASK 0x4u
mbed_official 363:12a245e5c745 4452 #define LPUART_CTRL_ILT_SHIFT 2
mbed_official 363:12a245e5c745 4453 #define LPUART_CTRL_WAKE_MASK 0x8u
mbed_official 363:12a245e5c745 4454 #define LPUART_CTRL_WAKE_SHIFT 3
mbed_official 363:12a245e5c745 4455 #define LPUART_CTRL_M_MASK 0x10u
mbed_official 363:12a245e5c745 4456 #define LPUART_CTRL_M_SHIFT 4
mbed_official 363:12a245e5c745 4457 #define LPUART_CTRL_RSRC_MASK 0x20u
mbed_official 363:12a245e5c745 4458 #define LPUART_CTRL_RSRC_SHIFT 5
mbed_official 363:12a245e5c745 4459 #define LPUART_CTRL_DOZEEN_MASK 0x40u
mbed_official 363:12a245e5c745 4460 #define LPUART_CTRL_DOZEEN_SHIFT 6
mbed_official 363:12a245e5c745 4461 #define LPUART_CTRL_LOOPS_MASK 0x80u
mbed_official 363:12a245e5c745 4462 #define LPUART_CTRL_LOOPS_SHIFT 7
mbed_official 363:12a245e5c745 4463 #define LPUART_CTRL_IDLECFG_MASK 0x700u
mbed_official 363:12a245e5c745 4464 #define LPUART_CTRL_IDLECFG_SHIFT 8
mbed_official 363:12a245e5c745 4465 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
mbed_official 363:12a245e5c745 4466 #define LPUART_CTRL_MA2IE_MASK 0x4000u
mbed_official 363:12a245e5c745 4467 #define LPUART_CTRL_MA2IE_SHIFT 14
mbed_official 363:12a245e5c745 4468 #define LPUART_CTRL_MA1IE_MASK 0x8000u
mbed_official 363:12a245e5c745 4469 #define LPUART_CTRL_MA1IE_SHIFT 15
mbed_official 363:12a245e5c745 4470 #define LPUART_CTRL_SBK_MASK 0x10000u
mbed_official 363:12a245e5c745 4471 #define LPUART_CTRL_SBK_SHIFT 16
mbed_official 363:12a245e5c745 4472 #define LPUART_CTRL_RWU_MASK 0x20000u
mbed_official 363:12a245e5c745 4473 #define LPUART_CTRL_RWU_SHIFT 17
mbed_official 363:12a245e5c745 4474 #define LPUART_CTRL_RE_MASK 0x40000u
mbed_official 363:12a245e5c745 4475 #define LPUART_CTRL_RE_SHIFT 18
mbed_official 363:12a245e5c745 4476 #define LPUART_CTRL_TE_MASK 0x80000u
mbed_official 363:12a245e5c745 4477 #define LPUART_CTRL_TE_SHIFT 19
mbed_official 363:12a245e5c745 4478 #define LPUART_CTRL_ILIE_MASK 0x100000u
mbed_official 363:12a245e5c745 4479 #define LPUART_CTRL_ILIE_SHIFT 20
mbed_official 363:12a245e5c745 4480 #define LPUART_CTRL_RIE_MASK 0x200000u
mbed_official 363:12a245e5c745 4481 #define LPUART_CTRL_RIE_SHIFT 21
mbed_official 363:12a245e5c745 4482 #define LPUART_CTRL_TCIE_MASK 0x400000u
mbed_official 363:12a245e5c745 4483 #define LPUART_CTRL_TCIE_SHIFT 22
mbed_official 363:12a245e5c745 4484 #define LPUART_CTRL_TIE_MASK 0x800000u
mbed_official 363:12a245e5c745 4485 #define LPUART_CTRL_TIE_SHIFT 23
mbed_official 363:12a245e5c745 4486 #define LPUART_CTRL_PEIE_MASK 0x1000000u
mbed_official 363:12a245e5c745 4487 #define LPUART_CTRL_PEIE_SHIFT 24
mbed_official 363:12a245e5c745 4488 #define LPUART_CTRL_FEIE_MASK 0x2000000u
mbed_official 363:12a245e5c745 4489 #define LPUART_CTRL_FEIE_SHIFT 25
mbed_official 363:12a245e5c745 4490 #define LPUART_CTRL_NEIE_MASK 0x4000000u
mbed_official 363:12a245e5c745 4491 #define LPUART_CTRL_NEIE_SHIFT 26
mbed_official 363:12a245e5c745 4492 #define LPUART_CTRL_ORIE_MASK 0x8000000u
mbed_official 363:12a245e5c745 4493 #define LPUART_CTRL_ORIE_SHIFT 27
mbed_official 363:12a245e5c745 4494 #define LPUART_CTRL_TXINV_MASK 0x10000000u
mbed_official 363:12a245e5c745 4495 #define LPUART_CTRL_TXINV_SHIFT 28
mbed_official 363:12a245e5c745 4496 #define LPUART_CTRL_TXDIR_MASK 0x20000000u
mbed_official 363:12a245e5c745 4497 #define LPUART_CTRL_TXDIR_SHIFT 29
mbed_official 363:12a245e5c745 4498 #define LPUART_CTRL_R9T8_MASK 0x40000000u
mbed_official 363:12a245e5c745 4499 #define LPUART_CTRL_R9T8_SHIFT 30
mbed_official 363:12a245e5c745 4500 #define LPUART_CTRL_R8T9_MASK 0x80000000u
mbed_official 363:12a245e5c745 4501 #define LPUART_CTRL_R8T9_SHIFT 31
mbed_official 363:12a245e5c745 4502 /* DATA Bit Fields */
mbed_official 363:12a245e5c745 4503 #define LPUART_DATA_R0T0_MASK 0x1u
mbed_official 363:12a245e5c745 4504 #define LPUART_DATA_R0T0_SHIFT 0
mbed_official 363:12a245e5c745 4505 #define LPUART_DATA_R1T1_MASK 0x2u
mbed_official 363:12a245e5c745 4506 #define LPUART_DATA_R1T1_SHIFT 1
mbed_official 363:12a245e5c745 4507 #define LPUART_DATA_R2T2_MASK 0x4u
mbed_official 363:12a245e5c745 4508 #define LPUART_DATA_R2T2_SHIFT 2
mbed_official 363:12a245e5c745 4509 #define LPUART_DATA_R3T3_MASK 0x8u
mbed_official 363:12a245e5c745 4510 #define LPUART_DATA_R3T3_SHIFT 3
mbed_official 363:12a245e5c745 4511 #define LPUART_DATA_R4T4_MASK 0x10u
mbed_official 363:12a245e5c745 4512 #define LPUART_DATA_R4T4_SHIFT 4
mbed_official 363:12a245e5c745 4513 #define LPUART_DATA_R5T5_MASK 0x20u
mbed_official 363:12a245e5c745 4514 #define LPUART_DATA_R5T5_SHIFT 5
mbed_official 363:12a245e5c745 4515 #define LPUART_DATA_R6T6_MASK 0x40u
mbed_official 363:12a245e5c745 4516 #define LPUART_DATA_R6T6_SHIFT 6
mbed_official 363:12a245e5c745 4517 #define LPUART_DATA_R7T7_MASK 0x80u
mbed_official 363:12a245e5c745 4518 #define LPUART_DATA_R7T7_SHIFT 7
mbed_official 363:12a245e5c745 4519 #define LPUART_DATA_R8T8_MASK 0x100u
mbed_official 363:12a245e5c745 4520 #define LPUART_DATA_R8T8_SHIFT 8
mbed_official 363:12a245e5c745 4521 #define LPUART_DATA_R9T9_MASK 0x200u
mbed_official 363:12a245e5c745 4522 #define LPUART_DATA_R9T9_SHIFT 9
mbed_official 363:12a245e5c745 4523 #define LPUART_DATA_IDLINE_MASK 0x800u
mbed_official 363:12a245e5c745 4524 #define LPUART_DATA_IDLINE_SHIFT 11
mbed_official 363:12a245e5c745 4525 #define LPUART_DATA_RXEMPT_MASK 0x1000u
mbed_official 363:12a245e5c745 4526 #define LPUART_DATA_RXEMPT_SHIFT 12
mbed_official 363:12a245e5c745 4527 #define LPUART_DATA_FRETSC_MASK 0x2000u
mbed_official 363:12a245e5c745 4528 #define LPUART_DATA_FRETSC_SHIFT 13
mbed_official 363:12a245e5c745 4529 #define LPUART_DATA_PARITYE_MASK 0x4000u
mbed_official 363:12a245e5c745 4530 #define LPUART_DATA_PARITYE_SHIFT 14
mbed_official 363:12a245e5c745 4531 #define LPUART_DATA_NOISY_MASK 0x8000u
mbed_official 363:12a245e5c745 4532 #define LPUART_DATA_NOISY_SHIFT 15
mbed_official 363:12a245e5c745 4533 /* MATCH Bit Fields */
mbed_official 363:12a245e5c745 4534 #define LPUART_MATCH_MA1_MASK 0x3FFu
mbed_official 363:12a245e5c745 4535 #define LPUART_MATCH_MA1_SHIFT 0
mbed_official 363:12a245e5c745 4536 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
mbed_official 363:12a245e5c745 4537 #define LPUART_MATCH_MA2_MASK 0x3FF0000u
mbed_official 363:12a245e5c745 4538 #define LPUART_MATCH_MA2_SHIFT 16
mbed_official 363:12a245e5c745 4539 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
mbed_official 363:12a245e5c745 4540
mbed_official 363:12a245e5c745 4541 /*!
mbed_official 363:12a245e5c745 4542 * @}
mbed_official 363:12a245e5c745 4543 */ /* end of group LPUART_Register_Masks */
mbed_official 363:12a245e5c745 4544
mbed_official 363:12a245e5c745 4545
mbed_official 363:12a245e5c745 4546 /* LPUART - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 4547 /** Peripheral LPUART0 base address */
mbed_official 363:12a245e5c745 4548 #define LPUART0_BASE (0x40054000u)
mbed_official 363:12a245e5c745 4549 /** Peripheral LPUART0 base pointer */
mbed_official 363:12a245e5c745 4550 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
mbed_official 363:12a245e5c745 4551 #define LPUART0_BASE_PTR (LPUART0)
mbed_official 363:12a245e5c745 4552 /** Peripheral LPUART1 base address */
mbed_official 363:12a245e5c745 4553 #define LPUART1_BASE (0x40055000u)
mbed_official 363:12a245e5c745 4554 /** Peripheral LPUART1 base pointer */
mbed_official 363:12a245e5c745 4555 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
mbed_official 363:12a245e5c745 4556 #define LPUART1_BASE_PTR (LPUART1)
mbed_official 363:12a245e5c745 4557 /** Array initializer of LPUART peripheral base addresses */
mbed_official 363:12a245e5c745 4558 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE }
mbed_official 363:12a245e5c745 4559 /** Array initializer of LPUART peripheral base pointers */
mbed_official 363:12a245e5c745 4560 #define LPUART_BASE_PTRS { LPUART0, LPUART1 }
mbed_official 363:12a245e5c745 4561 /** Interrupt vectors for the LPUART peripheral type */
mbed_official 363:12a245e5c745 4562 #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn }
mbed_official 363:12a245e5c745 4563 #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn }
mbed_official 363:12a245e5c745 4564
mbed_official 363:12a245e5c745 4565 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4566 -- LPUART - Register accessor macros
mbed_official 363:12a245e5c745 4567 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4568
mbed_official 363:12a245e5c745 4569 /*!
mbed_official 363:12a245e5c745 4570 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
mbed_official 363:12a245e5c745 4571 * @{
mbed_official 363:12a245e5c745 4572 */
mbed_official 363:12a245e5c745 4573
mbed_official 363:12a245e5c745 4574
mbed_official 363:12a245e5c745 4575 /* LPUART - Register instance definitions */
mbed_official 363:12a245e5c745 4576 /* LPUART0 */
mbed_official 363:12a245e5c745 4577 #define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
mbed_official 363:12a245e5c745 4578 #define LPUART0_STAT LPUART_STAT_REG(LPUART0)
mbed_official 363:12a245e5c745 4579 #define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
mbed_official 363:12a245e5c745 4580 #define LPUART0_DATA LPUART_DATA_REG(LPUART0)
mbed_official 363:12a245e5c745 4581 #define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
mbed_official 363:12a245e5c745 4582 /* LPUART1 */
mbed_official 363:12a245e5c745 4583 #define LPUART1_BAUD LPUART_BAUD_REG(LPUART1)
mbed_official 363:12a245e5c745 4584 #define LPUART1_STAT LPUART_STAT_REG(LPUART1)
mbed_official 363:12a245e5c745 4585 #define LPUART1_CTRL LPUART_CTRL_REG(LPUART1)
mbed_official 363:12a245e5c745 4586 #define LPUART1_DATA LPUART_DATA_REG(LPUART1)
mbed_official 363:12a245e5c745 4587 #define LPUART1_MATCH LPUART_MATCH_REG(LPUART1)
mbed_official 363:12a245e5c745 4588
mbed_official 363:12a245e5c745 4589 /*!
mbed_official 363:12a245e5c745 4590 * @}
mbed_official 363:12a245e5c745 4591 */ /* end of group LPUART_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4592
mbed_official 363:12a245e5c745 4593
mbed_official 363:12a245e5c745 4594 /*!
mbed_official 363:12a245e5c745 4595 * @}
mbed_official 363:12a245e5c745 4596 */ /* end of group LPUART_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 4597
mbed_official 363:12a245e5c745 4598
mbed_official 363:12a245e5c745 4599 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4600 -- MCG Peripheral Access Layer
mbed_official 363:12a245e5c745 4601 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4602
mbed_official 363:12a245e5c745 4603 /*!
mbed_official 363:12a245e5c745 4604 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
mbed_official 363:12a245e5c745 4605 * @{
mbed_official 363:12a245e5c745 4606 */
mbed_official 363:12a245e5c745 4607
mbed_official 363:12a245e5c745 4608 /** MCG - Register Layout Typedef */
mbed_official 363:12a245e5c745 4609 typedef struct {
mbed_official 363:12a245e5c745 4610 __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */
mbed_official 363:12a245e5c745 4611 __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */
mbed_official 363:12a245e5c745 4612 uint8_t RESERVED_0[4];
mbed_official 363:12a245e5c745 4613 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
mbed_official 363:12a245e5c745 4614 uint8_t RESERVED_1[1];
mbed_official 363:12a245e5c745 4615 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
mbed_official 363:12a245e5c745 4616 uint8_t RESERVED_2[11];
mbed_official 363:12a245e5c745 4617 __I uint8_t HCTRIM; /**< MCG High-frequency IRC Coarse Trim Register, offset: 0x14 */
mbed_official 363:12a245e5c745 4618 __I uint8_t HTTRIM; /**< MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register, offset: 0x15 */
mbed_official 363:12a245e5c745 4619 __I uint8_t HFTRIM; /**< MCG High-frequency IRC Fine Trim Register, offset: 0x16 */
mbed_official 363:12a245e5c745 4620 uint8_t RESERVED_3[1];
mbed_official 363:12a245e5c745 4621 __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */
mbed_official 363:12a245e5c745 4622 __I uint8_t LTRIMRNG; /**< MCG Low-frequency IRC Trim Range Register, offset: 0x19 */
mbed_official 363:12a245e5c745 4623 __I uint8_t LFTRIM; /**< MCG Low-frequency IRC8M Trim Register, offset: 0x1A */
mbed_official 363:12a245e5c745 4624 __I uint8_t LSTRIM; /**< MCG Low-frequency IRC2M Trim Register, offset: 0x1B */
mbed_official 363:12a245e5c745 4625 } MCG_Type, *MCG_MemMapPtr;
mbed_official 363:12a245e5c745 4626
mbed_official 363:12a245e5c745 4627 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4628 -- MCG - Register accessor macros
mbed_official 363:12a245e5c745 4629 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4630
mbed_official 363:12a245e5c745 4631 /*!
mbed_official 363:12a245e5c745 4632 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
mbed_official 363:12a245e5c745 4633 * @{
mbed_official 363:12a245e5c745 4634 */
mbed_official 363:12a245e5c745 4635
mbed_official 363:12a245e5c745 4636
mbed_official 363:12a245e5c745 4637 /* MCG - Register accessors */
mbed_official 363:12a245e5c745 4638 #define MCG_C1_REG(base) ((base)->C1)
mbed_official 363:12a245e5c745 4639 #define MCG_C2_REG(base) ((base)->C2)
mbed_official 363:12a245e5c745 4640 #define MCG_S_REG(base) ((base)->S)
mbed_official 363:12a245e5c745 4641 #define MCG_SC_REG(base) ((base)->SC)
mbed_official 363:12a245e5c745 4642 #define MCG_HCTRIM_REG(base) ((base)->HCTRIM)
mbed_official 363:12a245e5c745 4643 #define MCG_HTTRIM_REG(base) ((base)->HTTRIM)
mbed_official 363:12a245e5c745 4644 #define MCG_HFTRIM_REG(base) ((base)->HFTRIM)
mbed_official 363:12a245e5c745 4645 #define MCG_MC_REG(base) ((base)->MC)
mbed_official 363:12a245e5c745 4646 #define MCG_LTRIMRNG_REG(base) ((base)->LTRIMRNG)
mbed_official 363:12a245e5c745 4647 #define MCG_LFTRIM_REG(base) ((base)->LFTRIM)
mbed_official 363:12a245e5c745 4648 #define MCG_LSTRIM_REG(base) ((base)->LSTRIM)
mbed_official 363:12a245e5c745 4649
mbed_official 363:12a245e5c745 4650 /*!
mbed_official 363:12a245e5c745 4651 * @}
mbed_official 363:12a245e5c745 4652 */ /* end of group MCG_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4653
mbed_official 363:12a245e5c745 4654
mbed_official 363:12a245e5c745 4655 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4656 -- MCG Register Masks
mbed_official 363:12a245e5c745 4657 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4658
mbed_official 363:12a245e5c745 4659 /*!
mbed_official 363:12a245e5c745 4660 * @addtogroup MCG_Register_Masks MCG Register Masks
mbed_official 363:12a245e5c745 4661 * @{
mbed_official 363:12a245e5c745 4662 */
mbed_official 363:12a245e5c745 4663
mbed_official 363:12a245e5c745 4664 /* C1 Bit Fields */
mbed_official 363:12a245e5c745 4665 #define MCG_C1_IREFSTEN_MASK 0x1u
mbed_official 363:12a245e5c745 4666 #define MCG_C1_IREFSTEN_SHIFT 0
mbed_official 363:12a245e5c745 4667 #define MCG_C1_IRCLKEN_MASK 0x2u
mbed_official 363:12a245e5c745 4668 #define MCG_C1_IRCLKEN_SHIFT 1
mbed_official 363:12a245e5c745 4669 #define MCG_C1_CLKS_MASK 0xC0u
mbed_official 363:12a245e5c745 4670 #define MCG_C1_CLKS_SHIFT 6
mbed_official 363:12a245e5c745 4671 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
mbed_official 363:12a245e5c745 4672 /* C2 Bit Fields */
mbed_official 363:12a245e5c745 4673 #define MCG_C2_IRCS_MASK 0x1u
mbed_official 363:12a245e5c745 4674 #define MCG_C2_IRCS_SHIFT 0
mbed_official 363:12a245e5c745 4675 #define MCG_C2_EREFS0_MASK 0x4u
mbed_official 363:12a245e5c745 4676 #define MCG_C2_EREFS0_SHIFT 2
mbed_official 363:12a245e5c745 4677 #define MCG_C2_HGO0_MASK 0x8u
mbed_official 363:12a245e5c745 4678 #define MCG_C2_HGO0_SHIFT 3
mbed_official 363:12a245e5c745 4679 #define MCG_C2_RANGE0_MASK 0x30u
mbed_official 363:12a245e5c745 4680 #define MCG_C2_RANGE0_SHIFT 4
mbed_official 363:12a245e5c745 4681 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
mbed_official 363:12a245e5c745 4682 /* S Bit Fields */
mbed_official 363:12a245e5c745 4683 #define MCG_S_OSCINIT0_MASK 0x2u
mbed_official 363:12a245e5c745 4684 #define MCG_S_OSCINIT0_SHIFT 1
mbed_official 363:12a245e5c745 4685 #define MCG_S_CLKST_MASK 0xCu
mbed_official 363:12a245e5c745 4686 #define MCG_S_CLKST_SHIFT 2
mbed_official 363:12a245e5c745 4687 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
mbed_official 363:12a245e5c745 4688 /* SC Bit Fields */
mbed_official 363:12a245e5c745 4689 #define MCG_SC_FCRDIV_MASK 0xEu
mbed_official 363:12a245e5c745 4690 #define MCG_SC_FCRDIV_SHIFT 1
mbed_official 363:12a245e5c745 4691 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
mbed_official 363:12a245e5c745 4692 /* HCTRIM Bit Fields */
mbed_official 363:12a245e5c745 4693 #define MCG_HCTRIM_COARSE_TRIM_MASK 0x3Fu
mbed_official 363:12a245e5c745 4694 #define MCG_HCTRIM_COARSE_TRIM_SHIFT 0
mbed_official 363:12a245e5c745 4695 #define MCG_HCTRIM_COARSE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HCTRIM_COARSE_TRIM_SHIFT))&MCG_HCTRIM_COARSE_TRIM_MASK)
mbed_official 363:12a245e5c745 4696 /* HTTRIM Bit Fields */
mbed_official 363:12a245e5c745 4697 #define MCG_HTTRIM_TEMPCO_TRIM_MASK 0x1Fu
mbed_official 363:12a245e5c745 4698 #define MCG_HTTRIM_TEMPCO_TRIM_SHIFT 0
mbed_official 363:12a245e5c745 4699 #define MCG_HTTRIM_TEMPCO_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HTTRIM_TEMPCO_TRIM_SHIFT))&MCG_HTTRIM_TEMPCO_TRIM_MASK)
mbed_official 363:12a245e5c745 4700 /* HFTRIM Bit Fields */
mbed_official 363:12a245e5c745 4701 #define MCG_HFTRIM_FINE_TRIM_MASK 0x7Fu
mbed_official 363:12a245e5c745 4702 #define MCG_HFTRIM_FINE_TRIM_SHIFT 0
mbed_official 363:12a245e5c745 4703 #define MCG_HFTRIM_FINE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HFTRIM_FINE_TRIM_SHIFT))&MCG_HFTRIM_FINE_TRIM_MASK)
mbed_official 363:12a245e5c745 4704 /* MC Bit Fields */
mbed_official 363:12a245e5c745 4705 #define MCG_MC_LIRC_DIV2_MASK 0x7u
mbed_official 363:12a245e5c745 4706 #define MCG_MC_LIRC_DIV2_SHIFT 0
mbed_official 363:12a245e5c745 4707 #define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x))<<MCG_MC_LIRC_DIV2_SHIFT))&MCG_MC_LIRC_DIV2_MASK)
mbed_official 363:12a245e5c745 4708 #define MCG_MC_HIRCEN_MASK 0x80u
mbed_official 363:12a245e5c745 4709 #define MCG_MC_HIRCEN_SHIFT 7
mbed_official 363:12a245e5c745 4710 /* LTRIMRNG Bit Fields */
mbed_official 363:12a245e5c745 4711 #define MCG_LTRIMRNG_STRIMRNG_MASK 0x3u
mbed_official 363:12a245e5c745 4712 #define MCG_LTRIMRNG_STRIMRNG_SHIFT 0
mbed_official 363:12a245e5c745 4713 #define MCG_LTRIMRNG_STRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_STRIMRNG_SHIFT))&MCG_LTRIMRNG_STRIMRNG_MASK)
mbed_official 363:12a245e5c745 4714 #define MCG_LTRIMRNG_FTRIMRNG_MASK 0xCu
mbed_official 363:12a245e5c745 4715 #define MCG_LTRIMRNG_FTRIMRNG_SHIFT 2
mbed_official 363:12a245e5c745 4716 #define MCG_LTRIMRNG_FTRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_FTRIMRNG_SHIFT))&MCG_LTRIMRNG_FTRIMRNG_MASK)
mbed_official 363:12a245e5c745 4717 /* LFTRIM Bit Fields */
mbed_official 363:12a245e5c745 4718 #define MCG_LFTRIM_LIRC_FTRIM_MASK 0x7Fu
mbed_official 363:12a245e5c745 4719 #define MCG_LFTRIM_LIRC_FTRIM_SHIFT 0
mbed_official 363:12a245e5c745 4720 #define MCG_LFTRIM_LIRC_FTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LFTRIM_LIRC_FTRIM_SHIFT))&MCG_LFTRIM_LIRC_FTRIM_MASK)
mbed_official 363:12a245e5c745 4721 /* LSTRIM Bit Fields */
mbed_official 363:12a245e5c745 4722 #define MCG_LSTRIM_LIRC_STRIM_MASK 0x7Fu
mbed_official 363:12a245e5c745 4723 #define MCG_LSTRIM_LIRC_STRIM_SHIFT 0
mbed_official 363:12a245e5c745 4724 #define MCG_LSTRIM_LIRC_STRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LSTRIM_LIRC_STRIM_SHIFT))&MCG_LSTRIM_LIRC_STRIM_MASK)
mbed_official 363:12a245e5c745 4725
mbed_official 363:12a245e5c745 4726 /*!
mbed_official 363:12a245e5c745 4727 * @}
mbed_official 363:12a245e5c745 4728 */ /* end of group MCG_Register_Masks */
mbed_official 363:12a245e5c745 4729
mbed_official 363:12a245e5c745 4730
mbed_official 363:12a245e5c745 4731 /* MCG - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 4732 /** Peripheral MCG base address */
mbed_official 363:12a245e5c745 4733 #define MCG_BASE (0x40064000u)
mbed_official 363:12a245e5c745 4734 /** Peripheral MCG base pointer */
mbed_official 363:12a245e5c745 4735 #define MCG ((MCG_Type *)MCG_BASE)
mbed_official 363:12a245e5c745 4736 #define MCG_BASE_PTR (MCG)
mbed_official 363:12a245e5c745 4737 /** Array initializer of MCG peripheral base addresses */
mbed_official 363:12a245e5c745 4738 #define MCG_BASE_ADDRS { MCG_BASE }
mbed_official 363:12a245e5c745 4739 /** Array initializer of MCG peripheral base pointers */
mbed_official 363:12a245e5c745 4740 #define MCG_BASE_PTRS { MCG }
mbed_official 363:12a245e5c745 4741
mbed_official 363:12a245e5c745 4742 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4743 -- MCG - Register accessor macros
mbed_official 363:12a245e5c745 4744 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4745
mbed_official 363:12a245e5c745 4746 /*!
mbed_official 363:12a245e5c745 4747 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
mbed_official 363:12a245e5c745 4748 * @{
mbed_official 363:12a245e5c745 4749 */
mbed_official 363:12a245e5c745 4750
mbed_official 363:12a245e5c745 4751
mbed_official 363:12a245e5c745 4752 /* MCG - Register instance definitions */
mbed_official 363:12a245e5c745 4753 /* MCG */
mbed_official 363:12a245e5c745 4754 #define MCG_C1 MCG_C1_REG(MCG)
mbed_official 363:12a245e5c745 4755 #define MCG_C2 MCG_C2_REG(MCG)
mbed_official 363:12a245e5c745 4756 #define MCG_S MCG_S_REG(MCG)
mbed_official 363:12a245e5c745 4757 #define MCG_SC MCG_SC_REG(MCG)
mbed_official 363:12a245e5c745 4758 #define MCG_HCTRIM MCG_HCTRIM_REG(MCG)
mbed_official 363:12a245e5c745 4759 #define MCG_HTTRIM MCG_HTTRIM_REG(MCG)
mbed_official 363:12a245e5c745 4760 #define MCG_HFTRIM MCG_HFTRIM_REG(MCG)
mbed_official 363:12a245e5c745 4761 #define MCG_MC MCG_MC_REG(MCG)
mbed_official 363:12a245e5c745 4762 #define MCG_LTRIMRNG MCG_LTRIMRNG_REG(MCG)
mbed_official 363:12a245e5c745 4763 #define MCG_LFTRIM MCG_LFTRIM_REG(MCG)
mbed_official 363:12a245e5c745 4764 #define MCG_LSTRIM MCG_LSTRIM_REG(MCG)
mbed_official 363:12a245e5c745 4765
mbed_official 363:12a245e5c745 4766 /*!
mbed_official 363:12a245e5c745 4767 * @}
mbed_official 363:12a245e5c745 4768 */ /* end of group MCG_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4769
mbed_official 363:12a245e5c745 4770
mbed_official 363:12a245e5c745 4771 /*!
mbed_official 363:12a245e5c745 4772 * @}
mbed_official 363:12a245e5c745 4773 */ /* end of group MCG_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 4774
mbed_official 363:12a245e5c745 4775
mbed_official 363:12a245e5c745 4776 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4777 -- MCM Peripheral Access Layer
mbed_official 363:12a245e5c745 4778 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4779
mbed_official 363:12a245e5c745 4780 /*!
mbed_official 363:12a245e5c745 4781 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
mbed_official 363:12a245e5c745 4782 * @{
mbed_official 363:12a245e5c745 4783 */
mbed_official 363:12a245e5c745 4784
mbed_official 363:12a245e5c745 4785 /** MCM - Register Layout Typedef */
mbed_official 363:12a245e5c745 4786 typedef struct {
mbed_official 363:12a245e5c745 4787 uint8_t RESERVED_0[8];
mbed_official 363:12a245e5c745 4788 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
mbed_official 363:12a245e5c745 4789 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
mbed_official 363:12a245e5c745 4790 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
mbed_official 363:12a245e5c745 4791 uint8_t RESERVED_1[48];
mbed_official 363:12a245e5c745 4792 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
mbed_official 363:12a245e5c745 4793 } MCM_Type, *MCM_MemMapPtr;
mbed_official 363:12a245e5c745 4794
mbed_official 363:12a245e5c745 4795 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4796 -- MCM - Register accessor macros
mbed_official 363:12a245e5c745 4797 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4798
mbed_official 363:12a245e5c745 4799 /*!
mbed_official 363:12a245e5c745 4800 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
mbed_official 363:12a245e5c745 4801 * @{
mbed_official 363:12a245e5c745 4802 */
mbed_official 363:12a245e5c745 4803
mbed_official 363:12a245e5c745 4804
mbed_official 363:12a245e5c745 4805 /* MCM - Register accessors */
mbed_official 363:12a245e5c745 4806 #define MCM_PLASC_REG(base) ((base)->PLASC)
mbed_official 363:12a245e5c745 4807 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
mbed_official 363:12a245e5c745 4808 #define MCM_PLACR_REG(base) ((base)->PLACR)
mbed_official 363:12a245e5c745 4809 #define MCM_CPO_REG(base) ((base)->CPO)
mbed_official 363:12a245e5c745 4810
mbed_official 363:12a245e5c745 4811 /*!
mbed_official 363:12a245e5c745 4812 * @}
mbed_official 363:12a245e5c745 4813 */ /* end of group MCM_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4814
mbed_official 363:12a245e5c745 4815
mbed_official 363:12a245e5c745 4816 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4817 -- MCM Register Masks
mbed_official 363:12a245e5c745 4818 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4819
mbed_official 363:12a245e5c745 4820 /*!
mbed_official 363:12a245e5c745 4821 * @addtogroup MCM_Register_Masks MCM Register Masks
mbed_official 363:12a245e5c745 4822 * @{
mbed_official 363:12a245e5c745 4823 */
mbed_official 363:12a245e5c745 4824
mbed_official 363:12a245e5c745 4825 /* PLASC Bit Fields */
mbed_official 363:12a245e5c745 4826 #define MCM_PLASC_ASC_MASK 0xFFu
mbed_official 363:12a245e5c745 4827 #define MCM_PLASC_ASC_SHIFT 0
mbed_official 363:12a245e5c745 4828 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
mbed_official 363:12a245e5c745 4829 /* PLAMC Bit Fields */
mbed_official 363:12a245e5c745 4830 #define MCM_PLAMC_AMC_MASK 0xFFu
mbed_official 363:12a245e5c745 4831 #define MCM_PLAMC_AMC_SHIFT 0
mbed_official 363:12a245e5c745 4832 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
mbed_official 363:12a245e5c745 4833 /* PLACR Bit Fields */
mbed_official 363:12a245e5c745 4834 #define MCM_PLACR_ARB_MASK 0x200u
mbed_official 363:12a245e5c745 4835 #define MCM_PLACR_ARB_SHIFT 9
mbed_official 363:12a245e5c745 4836 #define MCM_PLACR_CFCC_MASK 0x400u
mbed_official 363:12a245e5c745 4837 #define MCM_PLACR_CFCC_SHIFT 10
mbed_official 363:12a245e5c745 4838 #define MCM_PLACR_DFCDA_MASK 0x800u
mbed_official 363:12a245e5c745 4839 #define MCM_PLACR_DFCDA_SHIFT 11
mbed_official 363:12a245e5c745 4840 #define MCM_PLACR_DFCIC_MASK 0x1000u
mbed_official 363:12a245e5c745 4841 #define MCM_PLACR_DFCIC_SHIFT 12
mbed_official 363:12a245e5c745 4842 #define MCM_PLACR_DFCC_MASK 0x2000u
mbed_official 363:12a245e5c745 4843 #define MCM_PLACR_DFCC_SHIFT 13
mbed_official 363:12a245e5c745 4844 #define MCM_PLACR_EFDS_MASK 0x4000u
mbed_official 363:12a245e5c745 4845 #define MCM_PLACR_EFDS_SHIFT 14
mbed_official 363:12a245e5c745 4846 #define MCM_PLACR_DFCS_MASK 0x8000u
mbed_official 363:12a245e5c745 4847 #define MCM_PLACR_DFCS_SHIFT 15
mbed_official 363:12a245e5c745 4848 #define MCM_PLACR_ESFC_MASK 0x10000u
mbed_official 363:12a245e5c745 4849 #define MCM_PLACR_ESFC_SHIFT 16
mbed_official 363:12a245e5c745 4850 /* CPO Bit Fields */
mbed_official 363:12a245e5c745 4851 #define MCM_CPO_CPOREQ_MASK 0x1u
mbed_official 363:12a245e5c745 4852 #define MCM_CPO_CPOREQ_SHIFT 0
mbed_official 363:12a245e5c745 4853 #define MCM_CPO_CPOACK_MASK 0x2u
mbed_official 363:12a245e5c745 4854 #define MCM_CPO_CPOACK_SHIFT 1
mbed_official 363:12a245e5c745 4855 #define MCM_CPO_CPOWOI_MASK 0x4u
mbed_official 363:12a245e5c745 4856 #define MCM_CPO_CPOWOI_SHIFT 2
mbed_official 363:12a245e5c745 4857
mbed_official 363:12a245e5c745 4858 /*!
mbed_official 363:12a245e5c745 4859 * @}
mbed_official 363:12a245e5c745 4860 */ /* end of group MCM_Register_Masks */
mbed_official 363:12a245e5c745 4861
mbed_official 363:12a245e5c745 4862
mbed_official 363:12a245e5c745 4863 /* MCM - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 4864 /** Peripheral MCM base address */
mbed_official 363:12a245e5c745 4865 #define MCM_BASE (0xF0003000u)
mbed_official 363:12a245e5c745 4866 /** Peripheral MCM base pointer */
mbed_official 363:12a245e5c745 4867 #define MCM ((MCM_Type *)MCM_BASE)
mbed_official 363:12a245e5c745 4868 #define MCM_BASE_PTR (MCM)
mbed_official 363:12a245e5c745 4869 /** Array initializer of MCM peripheral base addresses */
mbed_official 363:12a245e5c745 4870 #define MCM_BASE_ADDRS { MCM_BASE }
mbed_official 363:12a245e5c745 4871 /** Array initializer of MCM peripheral base pointers */
mbed_official 363:12a245e5c745 4872 #define MCM_BASE_PTRS { MCM }
mbed_official 363:12a245e5c745 4873
mbed_official 363:12a245e5c745 4874 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4875 -- MCM - Register accessor macros
mbed_official 363:12a245e5c745 4876 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4877
mbed_official 363:12a245e5c745 4878 /*!
mbed_official 363:12a245e5c745 4879 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
mbed_official 363:12a245e5c745 4880 * @{
mbed_official 363:12a245e5c745 4881 */
mbed_official 363:12a245e5c745 4882
mbed_official 363:12a245e5c745 4883
mbed_official 363:12a245e5c745 4884 /* MCM - Register instance definitions */
mbed_official 363:12a245e5c745 4885 /* MCM */
mbed_official 363:12a245e5c745 4886 #define MCM_PLASC MCM_PLASC_REG(MCM)
mbed_official 363:12a245e5c745 4887 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
mbed_official 363:12a245e5c745 4888 #define MCM_PLACR MCM_PLACR_REG(MCM)
mbed_official 363:12a245e5c745 4889 #define MCM_CPO MCM_CPO_REG(MCM)
mbed_official 363:12a245e5c745 4890
mbed_official 363:12a245e5c745 4891 /*!
mbed_official 363:12a245e5c745 4892 * @}
mbed_official 363:12a245e5c745 4893 */ /* end of group MCM_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4894
mbed_official 363:12a245e5c745 4895
mbed_official 363:12a245e5c745 4896 /*!
mbed_official 363:12a245e5c745 4897 * @}
mbed_official 363:12a245e5c745 4898 */ /* end of group MCM_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 4899
mbed_official 363:12a245e5c745 4900
mbed_official 363:12a245e5c745 4901 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4902 -- MTB Peripheral Access Layer
mbed_official 363:12a245e5c745 4903 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4904
mbed_official 363:12a245e5c745 4905 /*!
mbed_official 363:12a245e5c745 4906 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
mbed_official 363:12a245e5c745 4907 * @{
mbed_official 363:12a245e5c745 4908 */
mbed_official 363:12a245e5c745 4909
mbed_official 363:12a245e5c745 4910 /** MTB - Register Layout Typedef */
mbed_official 363:12a245e5c745 4911 typedef struct {
mbed_official 363:12a245e5c745 4912 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
mbed_official 363:12a245e5c745 4913 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
mbed_official 363:12a245e5c745 4914 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
mbed_official 363:12a245e5c745 4915 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
mbed_official 363:12a245e5c745 4916 uint8_t RESERVED_0[3824];
mbed_official 363:12a245e5c745 4917 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
mbed_official 363:12a245e5c745 4918 uint8_t RESERVED_1[156];
mbed_official 363:12a245e5c745 4919 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
mbed_official 363:12a245e5c745 4920 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
mbed_official 363:12a245e5c745 4921 uint8_t RESERVED_2[8];
mbed_official 363:12a245e5c745 4922 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
mbed_official 363:12a245e5c745 4923 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
mbed_official 363:12a245e5c745 4924 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
mbed_official 363:12a245e5c745 4925 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
mbed_official 363:12a245e5c745 4926 uint8_t RESERVED_3[8];
mbed_official 363:12a245e5c745 4927 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
mbed_official 363:12a245e5c745 4928 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
mbed_official 363:12a245e5c745 4929 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
mbed_official 363:12a245e5c745 4930 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 363:12a245e5c745 4931 } MTB_Type, *MTB_MemMapPtr;
mbed_official 363:12a245e5c745 4932
mbed_official 363:12a245e5c745 4933 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4934 -- MTB - Register accessor macros
mbed_official 363:12a245e5c745 4935 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4936
mbed_official 363:12a245e5c745 4937 /*!
mbed_official 363:12a245e5c745 4938 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
mbed_official 363:12a245e5c745 4939 * @{
mbed_official 363:12a245e5c745 4940 */
mbed_official 363:12a245e5c745 4941
mbed_official 363:12a245e5c745 4942
mbed_official 363:12a245e5c745 4943 /* MTB - Register accessors */
mbed_official 363:12a245e5c745 4944 #define MTB_POSITION_REG(base) ((base)->POSITION)
mbed_official 363:12a245e5c745 4945 #define MTB_MASTER_REG(base) ((base)->MASTER)
mbed_official 363:12a245e5c745 4946 #define MTB_FLOW_REG(base) ((base)->FLOW)
mbed_official 363:12a245e5c745 4947 #define MTB_BASE_REG(base) ((base)->BASE)
mbed_official 363:12a245e5c745 4948 #define MTB_MODECTRL_REG(base) ((base)->MODECTRL)
mbed_official 363:12a245e5c745 4949 #define MTB_TAGSET_REG(base) ((base)->TAGSET)
mbed_official 363:12a245e5c745 4950 #define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR)
mbed_official 363:12a245e5c745 4951 #define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS)
mbed_official 363:12a245e5c745 4952 #define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT)
mbed_official 363:12a245e5c745 4953 #define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT)
mbed_official 363:12a245e5c745 4954 #define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH)
mbed_official 363:12a245e5c745 4955 #define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG)
mbed_official 363:12a245e5c745 4956 #define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
mbed_official 363:12a245e5c745 4957 #define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
mbed_official 363:12a245e5c745 4958 #define MTB_COMPID_REG(base,index) ((base)->COMPID[index])
mbed_official 363:12a245e5c745 4959
mbed_official 363:12a245e5c745 4960 /*!
mbed_official 363:12a245e5c745 4961 * @}
mbed_official 363:12a245e5c745 4962 */ /* end of group MTB_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 4963
mbed_official 363:12a245e5c745 4964
mbed_official 363:12a245e5c745 4965 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 4966 -- MTB Register Masks
mbed_official 363:12a245e5c745 4967 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 4968
mbed_official 363:12a245e5c745 4969 /*!
mbed_official 363:12a245e5c745 4970 * @addtogroup MTB_Register_Masks MTB Register Masks
mbed_official 363:12a245e5c745 4971 * @{
mbed_official 363:12a245e5c745 4972 */
mbed_official 363:12a245e5c745 4973
mbed_official 363:12a245e5c745 4974 /* POSITION Bit Fields */
mbed_official 363:12a245e5c745 4975 #define MTB_POSITION_WRAP_MASK 0x4u
mbed_official 363:12a245e5c745 4976 #define MTB_POSITION_WRAP_SHIFT 2
mbed_official 363:12a245e5c745 4977 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
mbed_official 363:12a245e5c745 4978 #define MTB_POSITION_POINTER_SHIFT 3
mbed_official 363:12a245e5c745 4979 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
mbed_official 363:12a245e5c745 4980 /* MASTER Bit Fields */
mbed_official 363:12a245e5c745 4981 #define MTB_MASTER_MASK_MASK 0x1Fu
mbed_official 363:12a245e5c745 4982 #define MTB_MASTER_MASK_SHIFT 0
mbed_official 363:12a245e5c745 4983 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
mbed_official 363:12a245e5c745 4984 #define MTB_MASTER_TSTARTEN_MASK 0x20u
mbed_official 363:12a245e5c745 4985 #define MTB_MASTER_TSTARTEN_SHIFT 5
mbed_official 363:12a245e5c745 4986 #define MTB_MASTER_TSTOPEN_MASK 0x40u
mbed_official 363:12a245e5c745 4987 #define MTB_MASTER_TSTOPEN_SHIFT 6
mbed_official 363:12a245e5c745 4988 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
mbed_official 363:12a245e5c745 4989 #define MTB_MASTER_SFRWPRIV_SHIFT 7
mbed_official 363:12a245e5c745 4990 #define MTB_MASTER_RAMPRIV_MASK 0x100u
mbed_official 363:12a245e5c745 4991 #define MTB_MASTER_RAMPRIV_SHIFT 8
mbed_official 363:12a245e5c745 4992 #define MTB_MASTER_HALTREQ_MASK 0x200u
mbed_official 363:12a245e5c745 4993 #define MTB_MASTER_HALTREQ_SHIFT 9
mbed_official 363:12a245e5c745 4994 #define MTB_MASTER_EN_MASK 0x80000000u
mbed_official 363:12a245e5c745 4995 #define MTB_MASTER_EN_SHIFT 31
mbed_official 363:12a245e5c745 4996 /* FLOW Bit Fields */
mbed_official 363:12a245e5c745 4997 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
mbed_official 363:12a245e5c745 4998 #define MTB_FLOW_AUTOSTOP_SHIFT 0
mbed_official 363:12a245e5c745 4999 #define MTB_FLOW_AUTOHALT_MASK 0x2u
mbed_official 363:12a245e5c745 5000 #define MTB_FLOW_AUTOHALT_SHIFT 1
mbed_official 363:12a245e5c745 5001 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
mbed_official 363:12a245e5c745 5002 #define MTB_FLOW_WATERMARK_SHIFT 3
mbed_official 363:12a245e5c745 5003 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
mbed_official 363:12a245e5c745 5004 /* BASE Bit Fields */
mbed_official 363:12a245e5c745 5005 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5006 #define MTB_BASE_BASEADDR_SHIFT 0
mbed_official 363:12a245e5c745 5007 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
mbed_official 363:12a245e5c745 5008 /* MODECTRL Bit Fields */
mbed_official 363:12a245e5c745 5009 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5010 #define MTB_MODECTRL_MODECTRL_SHIFT 0
mbed_official 363:12a245e5c745 5011 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
mbed_official 363:12a245e5c745 5012 /* TAGSET Bit Fields */
mbed_official 363:12a245e5c745 5013 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5014 #define MTB_TAGSET_TAGSET_SHIFT 0
mbed_official 363:12a245e5c745 5015 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
mbed_official 363:12a245e5c745 5016 /* TAGCLEAR Bit Fields */
mbed_official 363:12a245e5c745 5017 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5018 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
mbed_official 363:12a245e5c745 5019 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
mbed_official 363:12a245e5c745 5020 /* LOCKACCESS Bit Fields */
mbed_official 363:12a245e5c745 5021 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5022 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
mbed_official 363:12a245e5c745 5023 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
mbed_official 363:12a245e5c745 5024 /* LOCKSTAT Bit Fields */
mbed_official 363:12a245e5c745 5025 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5026 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
mbed_official 363:12a245e5c745 5027 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
mbed_official 363:12a245e5c745 5028 /* AUTHSTAT Bit Fields */
mbed_official 363:12a245e5c745 5029 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
mbed_official 363:12a245e5c745 5030 #define MTB_AUTHSTAT_BIT0_SHIFT 0
mbed_official 363:12a245e5c745 5031 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
mbed_official 363:12a245e5c745 5032 #define MTB_AUTHSTAT_BIT1_SHIFT 1
mbed_official 363:12a245e5c745 5033 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
mbed_official 363:12a245e5c745 5034 #define MTB_AUTHSTAT_BIT2_SHIFT 2
mbed_official 363:12a245e5c745 5035 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
mbed_official 363:12a245e5c745 5036 #define MTB_AUTHSTAT_BIT3_SHIFT 3
mbed_official 363:12a245e5c745 5037 /* DEVICEARCH Bit Fields */
mbed_official 363:12a245e5c745 5038 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5039 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
mbed_official 363:12a245e5c745 5040 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
mbed_official 363:12a245e5c745 5041 /* DEVICECFG Bit Fields */
mbed_official 363:12a245e5c745 5042 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5043 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
mbed_official 363:12a245e5c745 5044 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
mbed_official 363:12a245e5c745 5045 /* DEVICETYPID Bit Fields */
mbed_official 363:12a245e5c745 5046 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5047 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
mbed_official 363:12a245e5c745 5048 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
mbed_official 363:12a245e5c745 5049 /* PERIPHID Bit Fields */
mbed_official 363:12a245e5c745 5050 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5051 #define MTB_PERIPHID_PERIPHID_SHIFT 0
mbed_official 363:12a245e5c745 5052 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
mbed_official 363:12a245e5c745 5053 /* COMPID Bit Fields */
mbed_official 363:12a245e5c745 5054 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5055 #define MTB_COMPID_COMPID_SHIFT 0
mbed_official 363:12a245e5c745 5056 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
mbed_official 363:12a245e5c745 5057
mbed_official 363:12a245e5c745 5058 /*!
mbed_official 363:12a245e5c745 5059 * @}
mbed_official 363:12a245e5c745 5060 */ /* end of group MTB_Register_Masks */
mbed_official 363:12a245e5c745 5061
mbed_official 363:12a245e5c745 5062
mbed_official 363:12a245e5c745 5063 /* MTB - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 5064 /** Peripheral MTB base address */
mbed_official 363:12a245e5c745 5065 #define MTB_BASE (0xF0000000u)
mbed_official 363:12a245e5c745 5066 /** Peripheral MTB base pointer */
mbed_official 363:12a245e5c745 5067 #define MTB ((MTB_Type *)MTB_BASE)
mbed_official 363:12a245e5c745 5068 #define MTB_BASE_PTR (MTB)
mbed_official 363:12a245e5c745 5069 /** Array initializer of MTB peripheral base addresses */
mbed_official 363:12a245e5c745 5070 #define MTB_BASE_ADDRS { MTB_BASE }
mbed_official 363:12a245e5c745 5071 /** Array initializer of MTB peripheral base pointers */
mbed_official 363:12a245e5c745 5072 #define MTB_BASE_PTRS { MTB }
mbed_official 363:12a245e5c745 5073
mbed_official 363:12a245e5c745 5074 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5075 -- MTB - Register accessor macros
mbed_official 363:12a245e5c745 5076 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5077
mbed_official 363:12a245e5c745 5078 /*!
mbed_official 363:12a245e5c745 5079 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
mbed_official 363:12a245e5c745 5080 * @{
mbed_official 363:12a245e5c745 5081 */
mbed_official 363:12a245e5c745 5082
mbed_official 363:12a245e5c745 5083
mbed_official 363:12a245e5c745 5084 /* MTB - Register instance definitions */
mbed_official 363:12a245e5c745 5085 /* MTB */
mbed_official 363:12a245e5c745 5086 #define MTB_POSITION MTB_POSITION_REG(MTB)
mbed_official 363:12a245e5c745 5087 #define MTB_MASTER MTB_MASTER_REG(MTB)
mbed_official 363:12a245e5c745 5088 #define MTB_FLOW MTB_FLOW_REG(MTB)
mbed_official 363:12a245e5c745 5089 #define MTB_BASEr MTB_BASE_REG(MTB)
mbed_official 363:12a245e5c745 5090 #define MTB_MODECTRL MTB_MODECTRL_REG(MTB)
mbed_official 363:12a245e5c745 5091 #define MTB_TAGSET MTB_TAGSET_REG(MTB)
mbed_official 363:12a245e5c745 5092 #define MTB_TAGCLEAR MTB_TAGCLEAR_REG(MTB)
mbed_official 363:12a245e5c745 5093 #define MTB_LOCKACCESS MTB_LOCKACCESS_REG(MTB)
mbed_official 363:12a245e5c745 5094 #define MTB_LOCKSTAT MTB_LOCKSTAT_REG(MTB)
mbed_official 363:12a245e5c745 5095 #define MTB_AUTHSTAT MTB_AUTHSTAT_REG(MTB)
mbed_official 363:12a245e5c745 5096 #define MTB_DEVICEARCH MTB_DEVICEARCH_REG(MTB)
mbed_official 363:12a245e5c745 5097 #define MTB_DEVICECFG MTB_DEVICECFG_REG(MTB)
mbed_official 363:12a245e5c745 5098 #define MTB_DEVICETYPID MTB_DEVICETYPID_REG(MTB)
mbed_official 363:12a245e5c745 5099 #define MTB_PERIPHID4 MTB_PERIPHID_REG(MTB,0)
mbed_official 363:12a245e5c745 5100 #define MTB_PERIPHID5 MTB_PERIPHID_REG(MTB,1)
mbed_official 363:12a245e5c745 5101 #define MTB_PERIPHID6 MTB_PERIPHID_REG(MTB,2)
mbed_official 363:12a245e5c745 5102 #define MTB_PERIPHID7 MTB_PERIPHID_REG(MTB,3)
mbed_official 363:12a245e5c745 5103 #define MTB_PERIPHID0 MTB_PERIPHID_REG(MTB,4)
mbed_official 363:12a245e5c745 5104 #define MTB_PERIPHID1 MTB_PERIPHID_REG(MTB,5)
mbed_official 363:12a245e5c745 5105 #define MTB_PERIPHID2 MTB_PERIPHID_REG(MTB,6)
mbed_official 363:12a245e5c745 5106 #define MTB_PERIPHID3 MTB_PERIPHID_REG(MTB,7)
mbed_official 363:12a245e5c745 5107 #define MTB_COMPID0 MTB_COMPID_REG(MTB,0)
mbed_official 363:12a245e5c745 5108 #define MTB_COMPID1 MTB_COMPID_REG(MTB,1)
mbed_official 363:12a245e5c745 5109 #define MTB_COMPID2 MTB_COMPID_REG(MTB,2)
mbed_official 363:12a245e5c745 5110 #define MTB_COMPID3 MTB_COMPID_REG(MTB,3)
mbed_official 363:12a245e5c745 5111
mbed_official 363:12a245e5c745 5112 /* MTB - Register array accessors */
mbed_official 363:12a245e5c745 5113 #define MTB_PERIPHID(index) MTB_PERIPHID_REG(MTB,index)
mbed_official 363:12a245e5c745 5114 #define MTB_COMPID(index) MTB_COMPID_REG(MTB,index)
mbed_official 363:12a245e5c745 5115
mbed_official 363:12a245e5c745 5116 /*!
mbed_official 363:12a245e5c745 5117 * @}
mbed_official 363:12a245e5c745 5118 */ /* end of group MTB_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5119
mbed_official 363:12a245e5c745 5120
mbed_official 363:12a245e5c745 5121 /*!
mbed_official 363:12a245e5c745 5122 * @}
mbed_official 363:12a245e5c745 5123 */ /* end of group MTB_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 5124
mbed_official 363:12a245e5c745 5125
mbed_official 363:12a245e5c745 5126 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5127 -- MTBDWT Peripheral Access Layer
mbed_official 363:12a245e5c745 5128 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5129
mbed_official 363:12a245e5c745 5130 /*!
mbed_official 363:12a245e5c745 5131 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
mbed_official 363:12a245e5c745 5132 * @{
mbed_official 363:12a245e5c745 5133 */
mbed_official 363:12a245e5c745 5134
mbed_official 363:12a245e5c745 5135 /** MTBDWT - Register Layout Typedef */
mbed_official 363:12a245e5c745 5136 typedef struct {
mbed_official 363:12a245e5c745 5137 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
mbed_official 363:12a245e5c745 5138 uint8_t RESERVED_0[28];
mbed_official 363:12a245e5c745 5139 struct { /* offset: 0x20, array step: 0x10 */
mbed_official 363:12a245e5c745 5140 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
mbed_official 363:12a245e5c745 5141 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
mbed_official 363:12a245e5c745 5142 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
mbed_official 363:12a245e5c745 5143 uint8_t RESERVED_0[4];
mbed_official 363:12a245e5c745 5144 } COMPARATOR[2];
mbed_official 363:12a245e5c745 5145 uint8_t RESERVED_1[448];
mbed_official 363:12a245e5c745 5146 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
mbed_official 363:12a245e5c745 5147 uint8_t RESERVED_2[3524];
mbed_official 363:12a245e5c745 5148 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
mbed_official 363:12a245e5c745 5149 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
mbed_official 363:12a245e5c745 5150 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
mbed_official 363:12a245e5c745 5151 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 363:12a245e5c745 5152 } MTBDWT_Type, *MTBDWT_MemMapPtr;
mbed_official 363:12a245e5c745 5153
mbed_official 363:12a245e5c745 5154 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5155 -- MTBDWT - Register accessor macros
mbed_official 363:12a245e5c745 5156 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5157
mbed_official 363:12a245e5c745 5158 /*!
mbed_official 363:12a245e5c745 5159 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
mbed_official 363:12a245e5c745 5160 * @{
mbed_official 363:12a245e5c745 5161 */
mbed_official 363:12a245e5c745 5162
mbed_official 363:12a245e5c745 5163
mbed_official 363:12a245e5c745 5164 /* MTBDWT - Register accessors */
mbed_official 363:12a245e5c745 5165 #define MTBDWT_CTRL_REG(base) ((base)->CTRL)
mbed_official 363:12a245e5c745 5166 #define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
mbed_official 363:12a245e5c745 5167 #define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
mbed_official 363:12a245e5c745 5168 #define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT)
mbed_official 363:12a245e5c745 5169 #define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL)
mbed_official 363:12a245e5c745 5170 #define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG)
mbed_official 363:12a245e5c745 5171 #define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
mbed_official 363:12a245e5c745 5172 #define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
mbed_official 363:12a245e5c745 5173 #define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index])
mbed_official 363:12a245e5c745 5174
mbed_official 363:12a245e5c745 5175 /*!
mbed_official 363:12a245e5c745 5176 * @}
mbed_official 363:12a245e5c745 5177 */ /* end of group MTBDWT_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5178
mbed_official 363:12a245e5c745 5179
mbed_official 363:12a245e5c745 5180 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5181 -- MTBDWT Register Masks
mbed_official 363:12a245e5c745 5182 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5183
mbed_official 363:12a245e5c745 5184 /*!
mbed_official 363:12a245e5c745 5185 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
mbed_official 363:12a245e5c745 5186 * @{
mbed_official 363:12a245e5c745 5187 */
mbed_official 363:12a245e5c745 5188
mbed_official 363:12a245e5c745 5189 /* CTRL Bit Fields */
mbed_official 363:12a245e5c745 5190 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
mbed_official 363:12a245e5c745 5191 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
mbed_official 363:12a245e5c745 5192 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
mbed_official 363:12a245e5c745 5193 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
mbed_official 363:12a245e5c745 5194 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
mbed_official 363:12a245e5c745 5195 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
mbed_official 363:12a245e5c745 5196 /* COMP Bit Fields */
mbed_official 363:12a245e5c745 5197 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5198 #define MTBDWT_COMP_COMP_SHIFT 0
mbed_official 363:12a245e5c745 5199 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
mbed_official 363:12a245e5c745 5200 /* MASK Bit Fields */
mbed_official 363:12a245e5c745 5201 #define MTBDWT_MASK_MASK_MASK 0x1Fu
mbed_official 363:12a245e5c745 5202 #define MTBDWT_MASK_MASK_SHIFT 0
mbed_official 363:12a245e5c745 5203 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
mbed_official 363:12a245e5c745 5204 /* FCT Bit Fields */
mbed_official 363:12a245e5c745 5205 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
mbed_official 363:12a245e5c745 5206 #define MTBDWT_FCT_FUNCTION_SHIFT 0
mbed_official 363:12a245e5c745 5207 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
mbed_official 363:12a245e5c745 5208 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
mbed_official 363:12a245e5c745 5209 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
mbed_official 363:12a245e5c745 5210 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
mbed_official 363:12a245e5c745 5211 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
mbed_official 363:12a245e5c745 5212 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
mbed_official 363:12a245e5c745 5213 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
mbed_official 363:12a245e5c745 5214 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
mbed_official 363:12a245e5c745 5215 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
mbed_official 363:12a245e5c745 5216 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
mbed_official 363:12a245e5c745 5217 #define MTBDWT_FCT_MATCHED_SHIFT 24
mbed_official 363:12a245e5c745 5218 /* TBCTRL Bit Fields */
mbed_official 363:12a245e5c745 5219 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
mbed_official 363:12a245e5c745 5220 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
mbed_official 363:12a245e5c745 5221 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
mbed_official 363:12a245e5c745 5222 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
mbed_official 363:12a245e5c745 5223 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
mbed_official 363:12a245e5c745 5224 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
mbed_official 363:12a245e5c745 5225 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
mbed_official 363:12a245e5c745 5226 /* DEVICECFG Bit Fields */
mbed_official 363:12a245e5c745 5227 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5228 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
mbed_official 363:12a245e5c745 5229 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
mbed_official 363:12a245e5c745 5230 /* DEVICETYPID Bit Fields */
mbed_official 363:12a245e5c745 5231 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5232 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
mbed_official 363:12a245e5c745 5233 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
mbed_official 363:12a245e5c745 5234 /* PERIPHID Bit Fields */
mbed_official 363:12a245e5c745 5235 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5236 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
mbed_official 363:12a245e5c745 5237 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
mbed_official 363:12a245e5c745 5238 /* COMPID Bit Fields */
mbed_official 363:12a245e5c745 5239 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5240 #define MTBDWT_COMPID_COMPID_SHIFT 0
mbed_official 363:12a245e5c745 5241 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
mbed_official 363:12a245e5c745 5242
mbed_official 363:12a245e5c745 5243 /*!
mbed_official 363:12a245e5c745 5244 * @}
mbed_official 363:12a245e5c745 5245 */ /* end of group MTBDWT_Register_Masks */
mbed_official 363:12a245e5c745 5246
mbed_official 363:12a245e5c745 5247
mbed_official 363:12a245e5c745 5248 /* MTBDWT - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 5249 /** Peripheral MTBDWT base address */
mbed_official 363:12a245e5c745 5250 #define MTBDWT_BASE (0xF0001000u)
mbed_official 363:12a245e5c745 5251 /** Peripheral MTBDWT base pointer */
mbed_official 363:12a245e5c745 5252 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
mbed_official 363:12a245e5c745 5253 #define MTBDWT_BASE_PTR (MTBDWT)
mbed_official 363:12a245e5c745 5254 /** Array initializer of MTBDWT peripheral base addresses */
mbed_official 363:12a245e5c745 5255 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
mbed_official 363:12a245e5c745 5256 /** Array initializer of MTBDWT peripheral base pointers */
mbed_official 363:12a245e5c745 5257 #define MTBDWT_BASE_PTRS { MTBDWT }
mbed_official 363:12a245e5c745 5258
mbed_official 363:12a245e5c745 5259 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5260 -- MTBDWT - Register accessor macros
mbed_official 363:12a245e5c745 5261 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5262
mbed_official 363:12a245e5c745 5263 /*!
mbed_official 363:12a245e5c745 5264 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
mbed_official 363:12a245e5c745 5265 * @{
mbed_official 363:12a245e5c745 5266 */
mbed_official 363:12a245e5c745 5267
mbed_official 363:12a245e5c745 5268
mbed_official 363:12a245e5c745 5269 /* MTBDWT - Register instance definitions */
mbed_official 363:12a245e5c745 5270 /* MTBDWT */
mbed_official 363:12a245e5c745 5271 #define MTBDWT_CTRL MTBDWT_CTRL_REG(MTBDWT)
mbed_official 363:12a245e5c745 5272 #define MTBDWT_COMP0 MTBDWT_COMP_REG(MTBDWT,0)
mbed_official 363:12a245e5c745 5273 #define MTBDWT_MASK0 MTBDWT_MASK_REG(MTBDWT,0)
mbed_official 363:12a245e5c745 5274 #define MTBDWT_FCT0 MTBDWT_FCT_REG(MTBDWT,0)
mbed_official 363:12a245e5c745 5275 #define MTBDWT_COMP1 MTBDWT_COMP_REG(MTBDWT,1)
mbed_official 363:12a245e5c745 5276 #define MTBDWT_MASK1 MTBDWT_MASK_REG(MTBDWT,1)
mbed_official 363:12a245e5c745 5277 #define MTBDWT_FCT1 MTBDWT_FCT_REG(MTBDWT,1)
mbed_official 363:12a245e5c745 5278 #define MTBDWT_TBCTRL MTBDWT_TBCTRL_REG(MTBDWT)
mbed_official 363:12a245e5c745 5279 #define MTBDWT_DEVICECFG MTBDWT_DEVICECFG_REG(MTBDWT)
mbed_official 363:12a245e5c745 5280 #define MTBDWT_DEVICETYPID MTBDWT_DEVICETYPID_REG(MTBDWT)
mbed_official 363:12a245e5c745 5281 #define MTBDWT_PERIPHID4 MTBDWT_PERIPHID_REG(MTBDWT,0)
mbed_official 363:12a245e5c745 5282 #define MTBDWT_PERIPHID5 MTBDWT_PERIPHID_REG(MTBDWT,1)
mbed_official 363:12a245e5c745 5283 #define MTBDWT_PERIPHID6 MTBDWT_PERIPHID_REG(MTBDWT,2)
mbed_official 363:12a245e5c745 5284 #define MTBDWT_PERIPHID7 MTBDWT_PERIPHID_REG(MTBDWT,3)
mbed_official 363:12a245e5c745 5285 #define MTBDWT_PERIPHID0 MTBDWT_PERIPHID_REG(MTBDWT,4)
mbed_official 363:12a245e5c745 5286 #define MTBDWT_PERIPHID1 MTBDWT_PERIPHID_REG(MTBDWT,5)
mbed_official 363:12a245e5c745 5287 #define MTBDWT_PERIPHID2 MTBDWT_PERIPHID_REG(MTBDWT,6)
mbed_official 363:12a245e5c745 5288 #define MTBDWT_PERIPHID3 MTBDWT_PERIPHID_REG(MTBDWT,7)
mbed_official 363:12a245e5c745 5289 #define MTBDWT_COMPID0 MTBDWT_COMPID_REG(MTBDWT,0)
mbed_official 363:12a245e5c745 5290 #define MTBDWT_COMPID1 MTBDWT_COMPID_REG(MTBDWT,1)
mbed_official 363:12a245e5c745 5291 #define MTBDWT_COMPID2 MTBDWT_COMPID_REG(MTBDWT,2)
mbed_official 363:12a245e5c745 5292 #define MTBDWT_COMPID3 MTBDWT_COMPID_REG(MTBDWT,3)
mbed_official 363:12a245e5c745 5293
mbed_official 363:12a245e5c745 5294 /* MTBDWT - Register array accessors */
mbed_official 363:12a245e5c745 5295 #define MTBDWT_COMP(index) MTBDWT_COMP_REG(MTBDWT,index)
mbed_official 363:12a245e5c745 5296 #define MTBDWT_MASK(index) MTBDWT_MASK_REG(MTBDWT,index)
mbed_official 363:12a245e5c745 5297 #define MTBDWT_FCT(index) MTBDWT_FCT_REG(MTBDWT,index)
mbed_official 363:12a245e5c745 5298 #define MTBDWT_PERIPHID(index) MTBDWT_PERIPHID_REG(MTBDWT,index)
mbed_official 363:12a245e5c745 5299 #define MTBDWT_COMPID(index) MTBDWT_COMPID_REG(MTBDWT,index)
mbed_official 363:12a245e5c745 5300
mbed_official 363:12a245e5c745 5301 /*!
mbed_official 363:12a245e5c745 5302 * @}
mbed_official 363:12a245e5c745 5303 */ /* end of group MTBDWT_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5304
mbed_official 363:12a245e5c745 5305
mbed_official 363:12a245e5c745 5306 /*!
mbed_official 363:12a245e5c745 5307 * @}
mbed_official 363:12a245e5c745 5308 */ /* end of group MTBDWT_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 5309
mbed_official 363:12a245e5c745 5310
mbed_official 363:12a245e5c745 5311 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5312 -- NV Peripheral Access Layer
mbed_official 363:12a245e5c745 5313 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5314
mbed_official 363:12a245e5c745 5315 /*!
mbed_official 363:12a245e5c745 5316 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
mbed_official 363:12a245e5c745 5317 * @{
mbed_official 363:12a245e5c745 5318 */
mbed_official 363:12a245e5c745 5319
mbed_official 363:12a245e5c745 5320 /** NV - Register Layout Typedef */
mbed_official 363:12a245e5c745 5321 typedef struct {
mbed_official 363:12a245e5c745 5322 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
mbed_official 363:12a245e5c745 5323 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
mbed_official 363:12a245e5c745 5324 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
mbed_official 363:12a245e5c745 5325 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
mbed_official 363:12a245e5c745 5326 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
mbed_official 363:12a245e5c745 5327 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
mbed_official 363:12a245e5c745 5328 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
mbed_official 363:12a245e5c745 5329 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
mbed_official 363:12a245e5c745 5330 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
mbed_official 363:12a245e5c745 5331 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
mbed_official 363:12a245e5c745 5332 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
mbed_official 363:12a245e5c745 5333 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
mbed_official 363:12a245e5c745 5334 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
mbed_official 363:12a245e5c745 5335 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
mbed_official 363:12a245e5c745 5336 } NV_Type, *NV_MemMapPtr;
mbed_official 363:12a245e5c745 5337
mbed_official 363:12a245e5c745 5338 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5339 -- NV - Register accessor macros
mbed_official 363:12a245e5c745 5340 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5341
mbed_official 363:12a245e5c745 5342 /*!
mbed_official 363:12a245e5c745 5343 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
mbed_official 363:12a245e5c745 5344 * @{
mbed_official 363:12a245e5c745 5345 */
mbed_official 363:12a245e5c745 5346
mbed_official 363:12a245e5c745 5347
mbed_official 363:12a245e5c745 5348 /* NV - Register accessors */
mbed_official 363:12a245e5c745 5349 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
mbed_official 363:12a245e5c745 5350 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
mbed_official 363:12a245e5c745 5351 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
mbed_official 363:12a245e5c745 5352 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
mbed_official 363:12a245e5c745 5353 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
mbed_official 363:12a245e5c745 5354 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
mbed_official 363:12a245e5c745 5355 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
mbed_official 363:12a245e5c745 5356 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
mbed_official 363:12a245e5c745 5357 #define NV_FPROT3_REG(base) ((base)->FPROT3)
mbed_official 363:12a245e5c745 5358 #define NV_FPROT2_REG(base) ((base)->FPROT2)
mbed_official 363:12a245e5c745 5359 #define NV_FPROT1_REG(base) ((base)->FPROT1)
mbed_official 363:12a245e5c745 5360 #define NV_FPROT0_REG(base) ((base)->FPROT0)
mbed_official 363:12a245e5c745 5361 #define NV_FSEC_REG(base) ((base)->FSEC)
mbed_official 363:12a245e5c745 5362 #define NV_FOPT_REG(base) ((base)->FOPT)
mbed_official 363:12a245e5c745 5363
mbed_official 363:12a245e5c745 5364 /*!
mbed_official 363:12a245e5c745 5365 * @}
mbed_official 363:12a245e5c745 5366 */ /* end of group NV_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5367
mbed_official 363:12a245e5c745 5368
mbed_official 363:12a245e5c745 5369 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5370 -- NV Register Masks
mbed_official 363:12a245e5c745 5371 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5372
mbed_official 363:12a245e5c745 5373 /*!
mbed_official 363:12a245e5c745 5374 * @addtogroup NV_Register_Masks NV Register Masks
mbed_official 363:12a245e5c745 5375 * @{
mbed_official 363:12a245e5c745 5376 */
mbed_official 363:12a245e5c745 5377
mbed_official 363:12a245e5c745 5378 /* BACKKEY3 Bit Fields */
mbed_official 363:12a245e5c745 5379 #define NV_BACKKEY3_KEY_MASK 0xFFu
mbed_official 363:12a245e5c745 5380 #define NV_BACKKEY3_KEY_SHIFT 0
mbed_official 363:12a245e5c745 5381 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
mbed_official 363:12a245e5c745 5382 /* BACKKEY2 Bit Fields */
mbed_official 363:12a245e5c745 5383 #define NV_BACKKEY2_KEY_MASK 0xFFu
mbed_official 363:12a245e5c745 5384 #define NV_BACKKEY2_KEY_SHIFT 0
mbed_official 363:12a245e5c745 5385 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
mbed_official 363:12a245e5c745 5386 /* BACKKEY1 Bit Fields */
mbed_official 363:12a245e5c745 5387 #define NV_BACKKEY1_KEY_MASK 0xFFu
mbed_official 363:12a245e5c745 5388 #define NV_BACKKEY1_KEY_SHIFT 0
mbed_official 363:12a245e5c745 5389 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
mbed_official 363:12a245e5c745 5390 /* BACKKEY0 Bit Fields */
mbed_official 363:12a245e5c745 5391 #define NV_BACKKEY0_KEY_MASK 0xFFu
mbed_official 363:12a245e5c745 5392 #define NV_BACKKEY0_KEY_SHIFT 0
mbed_official 363:12a245e5c745 5393 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
mbed_official 363:12a245e5c745 5394 /* BACKKEY7 Bit Fields */
mbed_official 363:12a245e5c745 5395 #define NV_BACKKEY7_KEY_MASK 0xFFu
mbed_official 363:12a245e5c745 5396 #define NV_BACKKEY7_KEY_SHIFT 0
mbed_official 363:12a245e5c745 5397 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
mbed_official 363:12a245e5c745 5398 /* BACKKEY6 Bit Fields */
mbed_official 363:12a245e5c745 5399 #define NV_BACKKEY6_KEY_MASK 0xFFu
mbed_official 363:12a245e5c745 5400 #define NV_BACKKEY6_KEY_SHIFT 0
mbed_official 363:12a245e5c745 5401 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
mbed_official 363:12a245e5c745 5402 /* BACKKEY5 Bit Fields */
mbed_official 363:12a245e5c745 5403 #define NV_BACKKEY5_KEY_MASK 0xFFu
mbed_official 363:12a245e5c745 5404 #define NV_BACKKEY5_KEY_SHIFT 0
mbed_official 363:12a245e5c745 5405 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
mbed_official 363:12a245e5c745 5406 /* BACKKEY4 Bit Fields */
mbed_official 363:12a245e5c745 5407 #define NV_BACKKEY4_KEY_MASK 0xFFu
mbed_official 363:12a245e5c745 5408 #define NV_BACKKEY4_KEY_SHIFT 0
mbed_official 363:12a245e5c745 5409 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
mbed_official 363:12a245e5c745 5410 /* FPROT3 Bit Fields */
mbed_official 363:12a245e5c745 5411 #define NV_FPROT3_PROT_MASK 0xFFu
mbed_official 363:12a245e5c745 5412 #define NV_FPROT3_PROT_SHIFT 0
mbed_official 363:12a245e5c745 5413 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
mbed_official 363:12a245e5c745 5414 /* FPROT2 Bit Fields */
mbed_official 363:12a245e5c745 5415 #define NV_FPROT2_PROT_MASK 0xFFu
mbed_official 363:12a245e5c745 5416 #define NV_FPROT2_PROT_SHIFT 0
mbed_official 363:12a245e5c745 5417 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
mbed_official 363:12a245e5c745 5418 /* FPROT1 Bit Fields */
mbed_official 363:12a245e5c745 5419 #define NV_FPROT1_PROT_MASK 0xFFu
mbed_official 363:12a245e5c745 5420 #define NV_FPROT1_PROT_SHIFT 0
mbed_official 363:12a245e5c745 5421 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
mbed_official 363:12a245e5c745 5422 /* FPROT0 Bit Fields */
mbed_official 363:12a245e5c745 5423 #define NV_FPROT0_PROT_MASK 0xFFu
mbed_official 363:12a245e5c745 5424 #define NV_FPROT0_PROT_SHIFT 0
mbed_official 363:12a245e5c745 5425 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
mbed_official 363:12a245e5c745 5426 /* FSEC Bit Fields */
mbed_official 363:12a245e5c745 5427 #define NV_FSEC_SEC_MASK 0x3u
mbed_official 363:12a245e5c745 5428 #define NV_FSEC_SEC_SHIFT 0
mbed_official 363:12a245e5c745 5429 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
mbed_official 363:12a245e5c745 5430 #define NV_FSEC_FSLACC_MASK 0xCu
mbed_official 363:12a245e5c745 5431 #define NV_FSEC_FSLACC_SHIFT 2
mbed_official 363:12a245e5c745 5432 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
mbed_official 363:12a245e5c745 5433 #define NV_FSEC_MEEN_MASK 0x30u
mbed_official 363:12a245e5c745 5434 #define NV_FSEC_MEEN_SHIFT 4
mbed_official 363:12a245e5c745 5435 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
mbed_official 363:12a245e5c745 5436 #define NV_FSEC_KEYEN_MASK 0xC0u
mbed_official 363:12a245e5c745 5437 #define NV_FSEC_KEYEN_SHIFT 6
mbed_official 363:12a245e5c745 5438 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
mbed_official 363:12a245e5c745 5439 /* FOPT Bit Fields */
mbed_official 363:12a245e5c745 5440 #define NV_FOPT_LPBOOT0_MASK 0x1u
mbed_official 363:12a245e5c745 5441 #define NV_FOPT_LPBOOT0_SHIFT 0
mbed_official 363:12a245e5c745 5442 #define NV_FOPT_BOOTPIN_OPT_MASK 0x2u
mbed_official 363:12a245e5c745 5443 #define NV_FOPT_BOOTPIN_OPT_SHIFT 1
mbed_official 363:12a245e5c745 5444 #define NV_FOPT_NMI_DIS_MASK 0x4u
mbed_official 363:12a245e5c745 5445 #define NV_FOPT_NMI_DIS_SHIFT 2
mbed_official 363:12a245e5c745 5446 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
mbed_official 363:12a245e5c745 5447 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
mbed_official 363:12a245e5c745 5448 #define NV_FOPT_LPBOOT1_MASK 0x10u
mbed_official 363:12a245e5c745 5449 #define NV_FOPT_LPBOOT1_SHIFT 4
mbed_official 363:12a245e5c745 5450 #define NV_FOPT_FAST_INIT_MASK 0x20u
mbed_official 363:12a245e5c745 5451 #define NV_FOPT_FAST_INIT_SHIFT 5
mbed_official 363:12a245e5c745 5452 #define NV_FOPT_BOOTSRC_SEL_MASK 0xC0u
mbed_official 363:12a245e5c745 5453 #define NV_FOPT_BOOTSRC_SEL_SHIFT 6
mbed_official 363:12a245e5c745 5454 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTSRC_SEL_SHIFT))&NV_FOPT_BOOTSRC_SEL_MASK)
mbed_official 363:12a245e5c745 5455
mbed_official 363:12a245e5c745 5456 /*!
mbed_official 363:12a245e5c745 5457 * @}
mbed_official 363:12a245e5c745 5458 */ /* end of group NV_Register_Masks */
mbed_official 363:12a245e5c745 5459
mbed_official 363:12a245e5c745 5460
mbed_official 363:12a245e5c745 5461 /* NV - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 5462 /** Peripheral FTFA_FlashConfig base address */
mbed_official 363:12a245e5c745 5463 #define FTFA_FlashConfig_BASE (0x400u)
mbed_official 363:12a245e5c745 5464 /** Peripheral FTFA_FlashConfig base pointer */
mbed_official 363:12a245e5c745 5465 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
mbed_official 363:12a245e5c745 5466 #define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5467 /** Array initializer of NV peripheral base addresses */
mbed_official 363:12a245e5c745 5468 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
mbed_official 363:12a245e5c745 5469 /** Array initializer of NV peripheral base pointers */
mbed_official 363:12a245e5c745 5470 #define NV_BASE_PTRS { FTFA_FlashConfig }
mbed_official 363:12a245e5c745 5471
mbed_official 363:12a245e5c745 5472 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5473 -- NV - Register accessor macros
mbed_official 363:12a245e5c745 5474 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5475
mbed_official 363:12a245e5c745 5476 /*!
mbed_official 363:12a245e5c745 5477 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
mbed_official 363:12a245e5c745 5478 * @{
mbed_official 363:12a245e5c745 5479 */
mbed_official 363:12a245e5c745 5480
mbed_official 363:12a245e5c745 5481
mbed_official 363:12a245e5c745 5482 /* NV - Register instance definitions */
mbed_official 363:12a245e5c745 5483 /* FTFA_FlashConfig */
mbed_official 363:12a245e5c745 5484 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5485 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5486 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5487 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5488 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5489 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5490 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5491 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5492 #define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5493 #define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5494 #define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5495 #define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5496 #define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5497 #define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
mbed_official 363:12a245e5c745 5498
mbed_official 363:12a245e5c745 5499 /*!
mbed_official 363:12a245e5c745 5500 * @}
mbed_official 363:12a245e5c745 5501 */ /* end of group NV_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5502
mbed_official 363:12a245e5c745 5503
mbed_official 363:12a245e5c745 5504 /*!
mbed_official 363:12a245e5c745 5505 * @}
mbed_official 363:12a245e5c745 5506 */ /* end of group NV_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 5507
mbed_official 363:12a245e5c745 5508
mbed_official 363:12a245e5c745 5509 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5510 -- OSC Peripheral Access Layer
mbed_official 363:12a245e5c745 5511 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5512
mbed_official 363:12a245e5c745 5513 /*!
mbed_official 363:12a245e5c745 5514 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
mbed_official 363:12a245e5c745 5515 * @{
mbed_official 363:12a245e5c745 5516 */
mbed_official 363:12a245e5c745 5517
mbed_official 363:12a245e5c745 5518 /** OSC - Register Layout Typedef */
mbed_official 363:12a245e5c745 5519 typedef struct {
mbed_official 363:12a245e5c745 5520 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
mbed_official 363:12a245e5c745 5521 } OSC_Type, *OSC_MemMapPtr;
mbed_official 363:12a245e5c745 5522
mbed_official 363:12a245e5c745 5523 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5524 -- OSC - Register accessor macros
mbed_official 363:12a245e5c745 5525 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5526
mbed_official 363:12a245e5c745 5527 /*!
mbed_official 363:12a245e5c745 5528 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
mbed_official 363:12a245e5c745 5529 * @{
mbed_official 363:12a245e5c745 5530 */
mbed_official 363:12a245e5c745 5531
mbed_official 363:12a245e5c745 5532
mbed_official 363:12a245e5c745 5533 /* OSC - Register accessors */
mbed_official 363:12a245e5c745 5534 #define OSC_CR_REG(base) ((base)->CR)
mbed_official 363:12a245e5c745 5535
mbed_official 363:12a245e5c745 5536 /*!
mbed_official 363:12a245e5c745 5537 * @}
mbed_official 363:12a245e5c745 5538 */ /* end of group OSC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5539
mbed_official 363:12a245e5c745 5540
mbed_official 363:12a245e5c745 5541 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5542 -- OSC Register Masks
mbed_official 363:12a245e5c745 5543 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5544
mbed_official 363:12a245e5c745 5545 /*!
mbed_official 363:12a245e5c745 5546 * @addtogroup OSC_Register_Masks OSC Register Masks
mbed_official 363:12a245e5c745 5547 * @{
mbed_official 363:12a245e5c745 5548 */
mbed_official 363:12a245e5c745 5549
mbed_official 363:12a245e5c745 5550 /* CR Bit Fields */
mbed_official 363:12a245e5c745 5551 #define OSC_CR_SC16P_MASK 0x1u
mbed_official 363:12a245e5c745 5552 #define OSC_CR_SC16P_SHIFT 0
mbed_official 363:12a245e5c745 5553 #define OSC_CR_SC8P_MASK 0x2u
mbed_official 363:12a245e5c745 5554 #define OSC_CR_SC8P_SHIFT 1
mbed_official 363:12a245e5c745 5555 #define OSC_CR_SC4P_MASK 0x4u
mbed_official 363:12a245e5c745 5556 #define OSC_CR_SC4P_SHIFT 2
mbed_official 363:12a245e5c745 5557 #define OSC_CR_SC2P_MASK 0x8u
mbed_official 363:12a245e5c745 5558 #define OSC_CR_SC2P_SHIFT 3
mbed_official 363:12a245e5c745 5559 #define OSC_CR_EREFSTEN_MASK 0x20u
mbed_official 363:12a245e5c745 5560 #define OSC_CR_EREFSTEN_SHIFT 5
mbed_official 363:12a245e5c745 5561 #define OSC_CR_ERCLKEN_MASK 0x80u
mbed_official 363:12a245e5c745 5562 #define OSC_CR_ERCLKEN_SHIFT 7
mbed_official 363:12a245e5c745 5563
mbed_official 363:12a245e5c745 5564 /*!
mbed_official 363:12a245e5c745 5565 * @}
mbed_official 363:12a245e5c745 5566 */ /* end of group OSC_Register_Masks */
mbed_official 363:12a245e5c745 5567
mbed_official 363:12a245e5c745 5568
mbed_official 363:12a245e5c745 5569 /* OSC - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 5570 /** Peripheral OSC0 base address */
mbed_official 363:12a245e5c745 5571 #define OSC0_BASE (0x40065000u)
mbed_official 363:12a245e5c745 5572 /** Peripheral OSC0 base pointer */
mbed_official 363:12a245e5c745 5573 #define OSC0 ((OSC_Type *)OSC0_BASE)
mbed_official 363:12a245e5c745 5574 #define OSC0_BASE_PTR (OSC0)
mbed_official 363:12a245e5c745 5575 /** Array initializer of OSC peripheral base addresses */
mbed_official 363:12a245e5c745 5576 #define OSC_BASE_ADDRS { OSC0_BASE }
mbed_official 363:12a245e5c745 5577 /** Array initializer of OSC peripheral base pointers */
mbed_official 363:12a245e5c745 5578 #define OSC_BASE_PTRS { OSC0 }
mbed_official 363:12a245e5c745 5579
mbed_official 363:12a245e5c745 5580 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5581 -- OSC - Register accessor macros
mbed_official 363:12a245e5c745 5582 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5583
mbed_official 363:12a245e5c745 5584 /*!
mbed_official 363:12a245e5c745 5585 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
mbed_official 363:12a245e5c745 5586 * @{
mbed_official 363:12a245e5c745 5587 */
mbed_official 363:12a245e5c745 5588
mbed_official 363:12a245e5c745 5589
mbed_official 363:12a245e5c745 5590 /* OSC - Register instance definitions */
mbed_official 363:12a245e5c745 5591 /* OSC0 */
mbed_official 363:12a245e5c745 5592 #define OSC0_CR OSC_CR_REG(OSC0)
mbed_official 363:12a245e5c745 5593
mbed_official 363:12a245e5c745 5594 /*!
mbed_official 363:12a245e5c745 5595 * @}
mbed_official 363:12a245e5c745 5596 */ /* end of group OSC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5597
mbed_official 363:12a245e5c745 5598
mbed_official 363:12a245e5c745 5599 /*!
mbed_official 363:12a245e5c745 5600 * @}
mbed_official 363:12a245e5c745 5601 */ /* end of group OSC_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 5602
mbed_official 363:12a245e5c745 5603
mbed_official 363:12a245e5c745 5604 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5605 -- PIT Peripheral Access Layer
mbed_official 363:12a245e5c745 5606 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5607
mbed_official 363:12a245e5c745 5608 /*!
mbed_official 363:12a245e5c745 5609 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
mbed_official 363:12a245e5c745 5610 * @{
mbed_official 363:12a245e5c745 5611 */
mbed_official 363:12a245e5c745 5612
mbed_official 363:12a245e5c745 5613 /** PIT - Register Layout Typedef */
mbed_official 363:12a245e5c745 5614 typedef struct {
mbed_official 363:12a245e5c745 5615 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
mbed_official 363:12a245e5c745 5616 uint8_t RESERVED_0[220];
mbed_official 363:12a245e5c745 5617 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
mbed_official 363:12a245e5c745 5618 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
mbed_official 363:12a245e5c745 5619 uint8_t RESERVED_1[24];
mbed_official 363:12a245e5c745 5620 struct { /* offset: 0x100, array step: 0x10 */
mbed_official 363:12a245e5c745 5621 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
mbed_official 363:12a245e5c745 5622 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
mbed_official 363:12a245e5c745 5623 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
mbed_official 363:12a245e5c745 5624 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
mbed_official 363:12a245e5c745 5625 } CHANNEL[2];
mbed_official 363:12a245e5c745 5626 } PIT_Type, *PIT_MemMapPtr;
mbed_official 363:12a245e5c745 5627
mbed_official 363:12a245e5c745 5628 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5629 -- PIT - Register accessor macros
mbed_official 363:12a245e5c745 5630 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5631
mbed_official 363:12a245e5c745 5632 /*!
mbed_official 363:12a245e5c745 5633 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
mbed_official 363:12a245e5c745 5634 * @{
mbed_official 363:12a245e5c745 5635 */
mbed_official 363:12a245e5c745 5636
mbed_official 363:12a245e5c745 5637
mbed_official 363:12a245e5c745 5638 /* PIT - Register accessors */
mbed_official 363:12a245e5c745 5639 #define PIT_MCR_REG(base) ((base)->MCR)
mbed_official 363:12a245e5c745 5640 #define PIT_LTMR64H_REG(base) ((base)->LTMR64H)
mbed_official 363:12a245e5c745 5641 #define PIT_LTMR64L_REG(base) ((base)->LTMR64L)
mbed_official 363:12a245e5c745 5642 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
mbed_official 363:12a245e5c745 5643 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
mbed_official 363:12a245e5c745 5644 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
mbed_official 363:12a245e5c745 5645 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
mbed_official 363:12a245e5c745 5646
mbed_official 363:12a245e5c745 5647 /*!
mbed_official 363:12a245e5c745 5648 * @}
mbed_official 363:12a245e5c745 5649 */ /* end of group PIT_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5650
mbed_official 363:12a245e5c745 5651
mbed_official 363:12a245e5c745 5652 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5653 -- PIT Register Masks
mbed_official 363:12a245e5c745 5654 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5655
mbed_official 363:12a245e5c745 5656 /*!
mbed_official 363:12a245e5c745 5657 * @addtogroup PIT_Register_Masks PIT Register Masks
mbed_official 363:12a245e5c745 5658 * @{
mbed_official 363:12a245e5c745 5659 */
mbed_official 363:12a245e5c745 5660
mbed_official 363:12a245e5c745 5661 /* MCR Bit Fields */
mbed_official 363:12a245e5c745 5662 #define PIT_MCR_FRZ_MASK 0x1u
mbed_official 363:12a245e5c745 5663 #define PIT_MCR_FRZ_SHIFT 0
mbed_official 363:12a245e5c745 5664 #define PIT_MCR_MDIS_MASK 0x2u
mbed_official 363:12a245e5c745 5665 #define PIT_MCR_MDIS_SHIFT 1
mbed_official 363:12a245e5c745 5666 /* LTMR64H Bit Fields */
mbed_official 363:12a245e5c745 5667 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5668 #define PIT_LTMR64H_LTH_SHIFT 0
mbed_official 363:12a245e5c745 5669 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
mbed_official 363:12a245e5c745 5670 /* LTMR64L Bit Fields */
mbed_official 363:12a245e5c745 5671 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5672 #define PIT_LTMR64L_LTL_SHIFT 0
mbed_official 363:12a245e5c745 5673 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
mbed_official 363:12a245e5c745 5674 /* LDVAL Bit Fields */
mbed_official 363:12a245e5c745 5675 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5676 #define PIT_LDVAL_TSV_SHIFT 0
mbed_official 363:12a245e5c745 5677 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
mbed_official 363:12a245e5c745 5678 /* CVAL Bit Fields */
mbed_official 363:12a245e5c745 5679 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5680 #define PIT_CVAL_TVL_SHIFT 0
mbed_official 363:12a245e5c745 5681 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
mbed_official 363:12a245e5c745 5682 /* TCTRL Bit Fields */
mbed_official 363:12a245e5c745 5683 #define PIT_TCTRL_TEN_MASK 0x1u
mbed_official 363:12a245e5c745 5684 #define PIT_TCTRL_TEN_SHIFT 0
mbed_official 363:12a245e5c745 5685 #define PIT_TCTRL_TIE_MASK 0x2u
mbed_official 363:12a245e5c745 5686 #define PIT_TCTRL_TIE_SHIFT 1
mbed_official 363:12a245e5c745 5687 #define PIT_TCTRL_CHN_MASK 0x4u
mbed_official 363:12a245e5c745 5688 #define PIT_TCTRL_CHN_SHIFT 2
mbed_official 363:12a245e5c745 5689 /* TFLG Bit Fields */
mbed_official 363:12a245e5c745 5690 #define PIT_TFLG_TIF_MASK 0x1u
mbed_official 363:12a245e5c745 5691 #define PIT_TFLG_TIF_SHIFT 0
mbed_official 363:12a245e5c745 5692
mbed_official 363:12a245e5c745 5693 /*!
mbed_official 363:12a245e5c745 5694 * @}
mbed_official 363:12a245e5c745 5695 */ /* end of group PIT_Register_Masks */
mbed_official 363:12a245e5c745 5696
mbed_official 363:12a245e5c745 5697
mbed_official 363:12a245e5c745 5698 /* PIT - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 5699 /** Peripheral PIT base address */
mbed_official 363:12a245e5c745 5700 #define PIT_BASE (0x40037000u)
mbed_official 363:12a245e5c745 5701 /** Peripheral PIT base pointer */
mbed_official 363:12a245e5c745 5702 #define PIT ((PIT_Type *)PIT_BASE)
mbed_official 363:12a245e5c745 5703 #define PIT_BASE_PTR (PIT)
mbed_official 363:12a245e5c745 5704 /** Array initializer of PIT peripheral base addresses */
mbed_official 363:12a245e5c745 5705 #define PIT_BASE_ADDRS { PIT_BASE }
mbed_official 363:12a245e5c745 5706 /** Array initializer of PIT peripheral base pointers */
mbed_official 363:12a245e5c745 5707 #define PIT_BASE_PTRS { PIT }
mbed_official 363:12a245e5c745 5708 /** Interrupt vectors for the PIT peripheral type */
mbed_official 363:12a245e5c745 5709 #define PIT_IRQS { PIT_IRQn, PIT_IRQn }
mbed_official 363:12a245e5c745 5710
mbed_official 363:12a245e5c745 5711 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5712 -- PIT - Register accessor macros
mbed_official 363:12a245e5c745 5713 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5714
mbed_official 363:12a245e5c745 5715 /*!
mbed_official 363:12a245e5c745 5716 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
mbed_official 363:12a245e5c745 5717 * @{
mbed_official 363:12a245e5c745 5718 */
mbed_official 363:12a245e5c745 5719
mbed_official 363:12a245e5c745 5720
mbed_official 363:12a245e5c745 5721 /* PIT - Register instance definitions */
mbed_official 363:12a245e5c745 5722 /* PIT */
mbed_official 363:12a245e5c745 5723 #define PIT_MCR PIT_MCR_REG(PIT)
mbed_official 363:12a245e5c745 5724 #define PIT_LTMR64H PIT_LTMR64H_REG(PIT)
mbed_official 363:12a245e5c745 5725 #define PIT_LTMR64L PIT_LTMR64L_REG(PIT)
mbed_official 363:12a245e5c745 5726 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
mbed_official 363:12a245e5c745 5727 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
mbed_official 363:12a245e5c745 5728 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
mbed_official 363:12a245e5c745 5729 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
mbed_official 363:12a245e5c745 5730 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
mbed_official 363:12a245e5c745 5731 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
mbed_official 363:12a245e5c745 5732 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
mbed_official 363:12a245e5c745 5733 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
mbed_official 363:12a245e5c745 5734
mbed_official 363:12a245e5c745 5735 /* PIT - Register array accessors */
mbed_official 363:12a245e5c745 5736 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
mbed_official 363:12a245e5c745 5737 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
mbed_official 363:12a245e5c745 5738 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
mbed_official 363:12a245e5c745 5739 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
mbed_official 363:12a245e5c745 5740
mbed_official 363:12a245e5c745 5741 /*!
mbed_official 363:12a245e5c745 5742 * @}
mbed_official 363:12a245e5c745 5743 */ /* end of group PIT_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5744
mbed_official 363:12a245e5c745 5745
mbed_official 363:12a245e5c745 5746 /*!
mbed_official 363:12a245e5c745 5747 * @}
mbed_official 363:12a245e5c745 5748 */ /* end of group PIT_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 5749
mbed_official 363:12a245e5c745 5750
mbed_official 363:12a245e5c745 5751 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5752 -- PMC Peripheral Access Layer
mbed_official 363:12a245e5c745 5753 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5754
mbed_official 363:12a245e5c745 5755 /*!
mbed_official 363:12a245e5c745 5756 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
mbed_official 363:12a245e5c745 5757 * @{
mbed_official 363:12a245e5c745 5758 */
mbed_official 363:12a245e5c745 5759
mbed_official 363:12a245e5c745 5760 /** PMC - Register Layout Typedef */
mbed_official 363:12a245e5c745 5761 typedef struct {
mbed_official 363:12a245e5c745 5762 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
mbed_official 363:12a245e5c745 5763 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
mbed_official 363:12a245e5c745 5764 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
mbed_official 363:12a245e5c745 5765 } PMC_Type, *PMC_MemMapPtr;
mbed_official 363:12a245e5c745 5766
mbed_official 363:12a245e5c745 5767 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5768 -- PMC - Register accessor macros
mbed_official 363:12a245e5c745 5769 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5770
mbed_official 363:12a245e5c745 5771 /*!
mbed_official 363:12a245e5c745 5772 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
mbed_official 363:12a245e5c745 5773 * @{
mbed_official 363:12a245e5c745 5774 */
mbed_official 363:12a245e5c745 5775
mbed_official 363:12a245e5c745 5776
mbed_official 363:12a245e5c745 5777 /* PMC - Register accessors */
mbed_official 363:12a245e5c745 5778 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
mbed_official 363:12a245e5c745 5779 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
mbed_official 363:12a245e5c745 5780 #define PMC_REGSC_REG(base) ((base)->REGSC)
mbed_official 363:12a245e5c745 5781
mbed_official 363:12a245e5c745 5782 /*!
mbed_official 363:12a245e5c745 5783 * @}
mbed_official 363:12a245e5c745 5784 */ /* end of group PMC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5785
mbed_official 363:12a245e5c745 5786
mbed_official 363:12a245e5c745 5787 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5788 -- PMC Register Masks
mbed_official 363:12a245e5c745 5789 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5790
mbed_official 363:12a245e5c745 5791 /*!
mbed_official 363:12a245e5c745 5792 * @addtogroup PMC_Register_Masks PMC Register Masks
mbed_official 363:12a245e5c745 5793 * @{
mbed_official 363:12a245e5c745 5794 */
mbed_official 363:12a245e5c745 5795
mbed_official 363:12a245e5c745 5796 /* LVDSC1 Bit Fields */
mbed_official 363:12a245e5c745 5797 #define PMC_LVDSC1_LVDV_MASK 0x3u
mbed_official 363:12a245e5c745 5798 #define PMC_LVDSC1_LVDV_SHIFT 0
mbed_official 363:12a245e5c745 5799 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
mbed_official 363:12a245e5c745 5800 #define PMC_LVDSC1_LVDRE_MASK 0x10u
mbed_official 363:12a245e5c745 5801 #define PMC_LVDSC1_LVDRE_SHIFT 4
mbed_official 363:12a245e5c745 5802 #define PMC_LVDSC1_LVDIE_MASK 0x20u
mbed_official 363:12a245e5c745 5803 #define PMC_LVDSC1_LVDIE_SHIFT 5
mbed_official 363:12a245e5c745 5804 #define PMC_LVDSC1_LVDACK_MASK 0x40u
mbed_official 363:12a245e5c745 5805 #define PMC_LVDSC1_LVDACK_SHIFT 6
mbed_official 363:12a245e5c745 5806 #define PMC_LVDSC1_LVDF_MASK 0x80u
mbed_official 363:12a245e5c745 5807 #define PMC_LVDSC1_LVDF_SHIFT 7
mbed_official 363:12a245e5c745 5808 /* LVDSC2 Bit Fields */
mbed_official 363:12a245e5c745 5809 #define PMC_LVDSC2_LVWV_MASK 0x3u
mbed_official 363:12a245e5c745 5810 #define PMC_LVDSC2_LVWV_SHIFT 0
mbed_official 363:12a245e5c745 5811 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
mbed_official 363:12a245e5c745 5812 #define PMC_LVDSC2_LVWIE_MASK 0x20u
mbed_official 363:12a245e5c745 5813 #define PMC_LVDSC2_LVWIE_SHIFT 5
mbed_official 363:12a245e5c745 5814 #define PMC_LVDSC2_LVWACK_MASK 0x40u
mbed_official 363:12a245e5c745 5815 #define PMC_LVDSC2_LVWACK_SHIFT 6
mbed_official 363:12a245e5c745 5816 #define PMC_LVDSC2_LVWF_MASK 0x80u
mbed_official 363:12a245e5c745 5817 #define PMC_LVDSC2_LVWF_SHIFT 7
mbed_official 363:12a245e5c745 5818 /* REGSC Bit Fields */
mbed_official 363:12a245e5c745 5819 #define PMC_REGSC_BGBE_MASK 0x1u
mbed_official 363:12a245e5c745 5820 #define PMC_REGSC_BGBE_SHIFT 0
mbed_official 363:12a245e5c745 5821 #define PMC_REGSC_REGONS_MASK 0x4u
mbed_official 363:12a245e5c745 5822 #define PMC_REGSC_REGONS_SHIFT 2
mbed_official 363:12a245e5c745 5823 #define PMC_REGSC_ACKISO_MASK 0x8u
mbed_official 363:12a245e5c745 5824 #define PMC_REGSC_ACKISO_SHIFT 3
mbed_official 363:12a245e5c745 5825 #define PMC_REGSC_BGEN_MASK 0x10u
mbed_official 363:12a245e5c745 5826 #define PMC_REGSC_BGEN_SHIFT 4
mbed_official 363:12a245e5c745 5827
mbed_official 363:12a245e5c745 5828 /*!
mbed_official 363:12a245e5c745 5829 * @}
mbed_official 363:12a245e5c745 5830 */ /* end of group PMC_Register_Masks */
mbed_official 363:12a245e5c745 5831
mbed_official 363:12a245e5c745 5832
mbed_official 363:12a245e5c745 5833 /* PMC - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 5834 /** Peripheral PMC base address */
mbed_official 363:12a245e5c745 5835 #define PMC_BASE (0x4007D000u)
mbed_official 363:12a245e5c745 5836 /** Peripheral PMC base pointer */
mbed_official 363:12a245e5c745 5837 #define PMC ((PMC_Type *)PMC_BASE)
mbed_official 363:12a245e5c745 5838 #define PMC_BASE_PTR (PMC)
mbed_official 363:12a245e5c745 5839 /** Array initializer of PMC peripheral base addresses */
mbed_official 363:12a245e5c745 5840 #define PMC_BASE_ADDRS { PMC_BASE }
mbed_official 363:12a245e5c745 5841 /** Array initializer of PMC peripheral base pointers */
mbed_official 363:12a245e5c745 5842 #define PMC_BASE_PTRS { PMC }
mbed_official 363:12a245e5c745 5843 /** Interrupt vectors for the PMC peripheral type */
mbed_official 363:12a245e5c745 5844 #define PMC_IRQS { PMC_IRQn }
mbed_official 363:12a245e5c745 5845
mbed_official 363:12a245e5c745 5846 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5847 -- PMC - Register accessor macros
mbed_official 363:12a245e5c745 5848 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5849
mbed_official 363:12a245e5c745 5850 /*!
mbed_official 363:12a245e5c745 5851 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
mbed_official 363:12a245e5c745 5852 * @{
mbed_official 363:12a245e5c745 5853 */
mbed_official 363:12a245e5c745 5854
mbed_official 363:12a245e5c745 5855
mbed_official 363:12a245e5c745 5856 /* PMC - Register instance definitions */
mbed_official 363:12a245e5c745 5857 /* PMC */
mbed_official 363:12a245e5c745 5858 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
mbed_official 363:12a245e5c745 5859 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
mbed_official 363:12a245e5c745 5860 #define PMC_REGSC PMC_REGSC_REG(PMC)
mbed_official 363:12a245e5c745 5861
mbed_official 363:12a245e5c745 5862 /*!
mbed_official 363:12a245e5c745 5863 * @}
mbed_official 363:12a245e5c745 5864 */ /* end of group PMC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5865
mbed_official 363:12a245e5c745 5866
mbed_official 363:12a245e5c745 5867 /*!
mbed_official 363:12a245e5c745 5868 * @}
mbed_official 363:12a245e5c745 5869 */ /* end of group PMC_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 5870
mbed_official 363:12a245e5c745 5871
mbed_official 363:12a245e5c745 5872 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5873 -- PORT Peripheral Access Layer
mbed_official 363:12a245e5c745 5874 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5875
mbed_official 363:12a245e5c745 5876 /*!
mbed_official 363:12a245e5c745 5877 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
mbed_official 363:12a245e5c745 5878 * @{
mbed_official 363:12a245e5c745 5879 */
mbed_official 363:12a245e5c745 5880
mbed_official 363:12a245e5c745 5881 /** PORT - Register Layout Typedef */
mbed_official 363:12a245e5c745 5882 typedef struct {
mbed_official 363:12a245e5c745 5883 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
mbed_official 363:12a245e5c745 5884 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
mbed_official 363:12a245e5c745 5885 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
mbed_official 363:12a245e5c745 5886 uint8_t RESERVED_0[24];
mbed_official 363:12a245e5c745 5887 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
mbed_official 363:12a245e5c745 5888 } PORT_Type, *PORT_MemMapPtr;
mbed_official 363:12a245e5c745 5889
mbed_official 363:12a245e5c745 5890 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5891 -- PORT - Register accessor macros
mbed_official 363:12a245e5c745 5892 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5893
mbed_official 363:12a245e5c745 5894 /*!
mbed_official 363:12a245e5c745 5895 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
mbed_official 363:12a245e5c745 5896 * @{
mbed_official 363:12a245e5c745 5897 */
mbed_official 363:12a245e5c745 5898
mbed_official 363:12a245e5c745 5899
mbed_official 363:12a245e5c745 5900 /* PORT - Register accessors */
mbed_official 363:12a245e5c745 5901 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
mbed_official 363:12a245e5c745 5902 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
mbed_official 363:12a245e5c745 5903 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
mbed_official 363:12a245e5c745 5904 #define PORT_ISFR_REG(base) ((base)->ISFR)
mbed_official 363:12a245e5c745 5905
mbed_official 363:12a245e5c745 5906 /*!
mbed_official 363:12a245e5c745 5907 * @}
mbed_official 363:12a245e5c745 5908 */ /* end of group PORT_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 5909
mbed_official 363:12a245e5c745 5910
mbed_official 363:12a245e5c745 5911 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5912 -- PORT Register Masks
mbed_official 363:12a245e5c745 5913 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5914
mbed_official 363:12a245e5c745 5915 /*!
mbed_official 363:12a245e5c745 5916 * @addtogroup PORT_Register_Masks PORT Register Masks
mbed_official 363:12a245e5c745 5917 * @{
mbed_official 363:12a245e5c745 5918 */
mbed_official 363:12a245e5c745 5919
mbed_official 363:12a245e5c745 5920 /* PCR Bit Fields */
mbed_official 363:12a245e5c745 5921 #define PORT_PCR_PS_MASK 0x1u
mbed_official 363:12a245e5c745 5922 #define PORT_PCR_PS_SHIFT 0
mbed_official 363:12a245e5c745 5923 #define PORT_PCR_PE_MASK 0x2u
mbed_official 363:12a245e5c745 5924 #define PORT_PCR_PE_SHIFT 1
mbed_official 363:12a245e5c745 5925 #define PORT_PCR_SRE_MASK 0x4u
mbed_official 363:12a245e5c745 5926 #define PORT_PCR_SRE_SHIFT 2
mbed_official 363:12a245e5c745 5927 #define PORT_PCR_PFE_MASK 0x10u
mbed_official 363:12a245e5c745 5928 #define PORT_PCR_PFE_SHIFT 4
mbed_official 363:12a245e5c745 5929 #define PORT_PCR_DSE_MASK 0x40u
mbed_official 363:12a245e5c745 5930 #define PORT_PCR_DSE_SHIFT 6
mbed_official 363:12a245e5c745 5931 #define PORT_PCR_MUX_MASK 0x700u
mbed_official 363:12a245e5c745 5932 #define PORT_PCR_MUX_SHIFT 8
mbed_official 363:12a245e5c745 5933 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
mbed_official 363:12a245e5c745 5934 #define PORT_PCR_IRQC_MASK 0xF0000u
mbed_official 363:12a245e5c745 5935 #define PORT_PCR_IRQC_SHIFT 16
mbed_official 363:12a245e5c745 5936 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
mbed_official 363:12a245e5c745 5937 #define PORT_PCR_ISF_MASK 0x1000000u
mbed_official 363:12a245e5c745 5938 #define PORT_PCR_ISF_SHIFT 24
mbed_official 363:12a245e5c745 5939 /* GPCLR Bit Fields */
mbed_official 363:12a245e5c745 5940 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
mbed_official 363:12a245e5c745 5941 #define PORT_GPCLR_GPWD_SHIFT 0
mbed_official 363:12a245e5c745 5942 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
mbed_official 363:12a245e5c745 5943 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
mbed_official 363:12a245e5c745 5944 #define PORT_GPCLR_GPWE_SHIFT 16
mbed_official 363:12a245e5c745 5945 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
mbed_official 363:12a245e5c745 5946 /* GPCHR Bit Fields */
mbed_official 363:12a245e5c745 5947 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
mbed_official 363:12a245e5c745 5948 #define PORT_GPCHR_GPWD_SHIFT 0
mbed_official 363:12a245e5c745 5949 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
mbed_official 363:12a245e5c745 5950 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
mbed_official 363:12a245e5c745 5951 #define PORT_GPCHR_GPWE_SHIFT 16
mbed_official 363:12a245e5c745 5952 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
mbed_official 363:12a245e5c745 5953 /* ISFR Bit Fields */
mbed_official 363:12a245e5c745 5954 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 5955 #define PORT_ISFR_ISF_SHIFT 0
mbed_official 363:12a245e5c745 5956 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
mbed_official 363:12a245e5c745 5957
mbed_official 363:12a245e5c745 5958 /*!
mbed_official 363:12a245e5c745 5959 * @}
mbed_official 363:12a245e5c745 5960 */ /* end of group PORT_Register_Masks */
mbed_official 363:12a245e5c745 5961
mbed_official 363:12a245e5c745 5962
mbed_official 363:12a245e5c745 5963 /* PORT - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 5964 /** Peripheral PORTA base address */
mbed_official 363:12a245e5c745 5965 #define PORTA_BASE (0x40049000u)
mbed_official 363:12a245e5c745 5966 /** Peripheral PORTA base pointer */
mbed_official 363:12a245e5c745 5967 #define PORTA ((PORT_Type *)PORTA_BASE)
mbed_official 363:12a245e5c745 5968 #define PORTA_BASE_PTR (PORTA)
mbed_official 363:12a245e5c745 5969 /** Peripheral PORTB base address */
mbed_official 363:12a245e5c745 5970 #define PORTB_BASE (0x4004A000u)
mbed_official 363:12a245e5c745 5971 /** Peripheral PORTB base pointer */
mbed_official 363:12a245e5c745 5972 #define PORTB ((PORT_Type *)PORTB_BASE)
mbed_official 363:12a245e5c745 5973 #define PORTB_BASE_PTR (PORTB)
mbed_official 363:12a245e5c745 5974 /** Peripheral PORTC base address */
mbed_official 363:12a245e5c745 5975 #define PORTC_BASE (0x4004B000u)
mbed_official 363:12a245e5c745 5976 /** Peripheral PORTC base pointer */
mbed_official 363:12a245e5c745 5977 #define PORTC ((PORT_Type *)PORTC_BASE)
mbed_official 363:12a245e5c745 5978 #define PORTC_BASE_PTR (PORTC)
mbed_official 363:12a245e5c745 5979 /** Peripheral PORTD base address */
mbed_official 363:12a245e5c745 5980 #define PORTD_BASE (0x4004C000u)
mbed_official 363:12a245e5c745 5981 /** Peripheral PORTD base pointer */
mbed_official 363:12a245e5c745 5982 #define PORTD ((PORT_Type *)PORTD_BASE)
mbed_official 363:12a245e5c745 5983 #define PORTD_BASE_PTR (PORTD)
mbed_official 363:12a245e5c745 5984 /** Peripheral PORTE base address */
mbed_official 363:12a245e5c745 5985 #define PORTE_BASE (0x4004D000u)
mbed_official 363:12a245e5c745 5986 /** Peripheral PORTE base pointer */
mbed_official 363:12a245e5c745 5987 #define PORTE ((PORT_Type *)PORTE_BASE)
mbed_official 363:12a245e5c745 5988 #define PORTE_BASE_PTR (PORTE)
mbed_official 363:12a245e5c745 5989 /** Array initializer of PORT peripheral base addresses */
mbed_official 363:12a245e5c745 5990 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
mbed_official 363:12a245e5c745 5991 /** Array initializer of PORT peripheral base pointers */
mbed_official 363:12a245e5c745 5992 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
mbed_official 363:12a245e5c745 5993 /** Interrupt vectors for the PORT peripheral type */
mbed_official 363:12a245e5c745 5994 #define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTCD_IRQn, PORTCD_IRQn, NotAvail_IRQn }
mbed_official 363:12a245e5c745 5995
mbed_official 363:12a245e5c745 5996 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 5997 -- PORT - Register accessor macros
mbed_official 363:12a245e5c745 5998 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 5999
mbed_official 363:12a245e5c745 6000 /*!
mbed_official 363:12a245e5c745 6001 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
mbed_official 363:12a245e5c745 6002 * @{
mbed_official 363:12a245e5c745 6003 */
mbed_official 363:12a245e5c745 6004
mbed_official 363:12a245e5c745 6005
mbed_official 363:12a245e5c745 6006 /* PORT - Register instance definitions */
mbed_official 363:12a245e5c745 6007 /* PORTA */
mbed_official 363:12a245e5c745 6008 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
mbed_official 363:12a245e5c745 6009 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
mbed_official 363:12a245e5c745 6010 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
mbed_official 363:12a245e5c745 6011 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
mbed_official 363:12a245e5c745 6012 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
mbed_official 363:12a245e5c745 6013 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
mbed_official 363:12a245e5c745 6014 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
mbed_official 363:12a245e5c745 6015 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
mbed_official 363:12a245e5c745 6016 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
mbed_official 363:12a245e5c745 6017 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
mbed_official 363:12a245e5c745 6018 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
mbed_official 363:12a245e5c745 6019 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
mbed_official 363:12a245e5c745 6020 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
mbed_official 363:12a245e5c745 6021 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
mbed_official 363:12a245e5c745 6022 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
mbed_official 363:12a245e5c745 6023 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
mbed_official 363:12a245e5c745 6024 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
mbed_official 363:12a245e5c745 6025 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
mbed_official 363:12a245e5c745 6026 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
mbed_official 363:12a245e5c745 6027 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
mbed_official 363:12a245e5c745 6028 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
mbed_official 363:12a245e5c745 6029 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
mbed_official 363:12a245e5c745 6030 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
mbed_official 363:12a245e5c745 6031 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
mbed_official 363:12a245e5c745 6032 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
mbed_official 363:12a245e5c745 6033 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
mbed_official 363:12a245e5c745 6034 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
mbed_official 363:12a245e5c745 6035 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
mbed_official 363:12a245e5c745 6036 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
mbed_official 363:12a245e5c745 6037 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
mbed_official 363:12a245e5c745 6038 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
mbed_official 363:12a245e5c745 6039 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
mbed_official 363:12a245e5c745 6040 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
mbed_official 363:12a245e5c745 6041 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
mbed_official 363:12a245e5c745 6042 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
mbed_official 363:12a245e5c745 6043 /* PORTB */
mbed_official 363:12a245e5c745 6044 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
mbed_official 363:12a245e5c745 6045 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
mbed_official 363:12a245e5c745 6046 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
mbed_official 363:12a245e5c745 6047 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
mbed_official 363:12a245e5c745 6048 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
mbed_official 363:12a245e5c745 6049 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
mbed_official 363:12a245e5c745 6050 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
mbed_official 363:12a245e5c745 6051 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
mbed_official 363:12a245e5c745 6052 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
mbed_official 363:12a245e5c745 6053 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
mbed_official 363:12a245e5c745 6054 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
mbed_official 363:12a245e5c745 6055 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
mbed_official 363:12a245e5c745 6056 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
mbed_official 363:12a245e5c745 6057 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
mbed_official 363:12a245e5c745 6058 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
mbed_official 363:12a245e5c745 6059 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
mbed_official 363:12a245e5c745 6060 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
mbed_official 363:12a245e5c745 6061 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
mbed_official 363:12a245e5c745 6062 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
mbed_official 363:12a245e5c745 6063 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
mbed_official 363:12a245e5c745 6064 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
mbed_official 363:12a245e5c745 6065 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
mbed_official 363:12a245e5c745 6066 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
mbed_official 363:12a245e5c745 6067 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
mbed_official 363:12a245e5c745 6068 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
mbed_official 363:12a245e5c745 6069 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
mbed_official 363:12a245e5c745 6070 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
mbed_official 363:12a245e5c745 6071 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
mbed_official 363:12a245e5c745 6072 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
mbed_official 363:12a245e5c745 6073 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
mbed_official 363:12a245e5c745 6074 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
mbed_official 363:12a245e5c745 6075 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
mbed_official 363:12a245e5c745 6076 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
mbed_official 363:12a245e5c745 6077 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
mbed_official 363:12a245e5c745 6078 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
mbed_official 363:12a245e5c745 6079 /* PORTC */
mbed_official 363:12a245e5c745 6080 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
mbed_official 363:12a245e5c745 6081 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
mbed_official 363:12a245e5c745 6082 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
mbed_official 363:12a245e5c745 6083 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
mbed_official 363:12a245e5c745 6084 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
mbed_official 363:12a245e5c745 6085 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
mbed_official 363:12a245e5c745 6086 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
mbed_official 363:12a245e5c745 6087 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
mbed_official 363:12a245e5c745 6088 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
mbed_official 363:12a245e5c745 6089 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
mbed_official 363:12a245e5c745 6090 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
mbed_official 363:12a245e5c745 6091 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
mbed_official 363:12a245e5c745 6092 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
mbed_official 363:12a245e5c745 6093 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
mbed_official 363:12a245e5c745 6094 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
mbed_official 363:12a245e5c745 6095 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
mbed_official 363:12a245e5c745 6096 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
mbed_official 363:12a245e5c745 6097 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
mbed_official 363:12a245e5c745 6098 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
mbed_official 363:12a245e5c745 6099 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
mbed_official 363:12a245e5c745 6100 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
mbed_official 363:12a245e5c745 6101 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
mbed_official 363:12a245e5c745 6102 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
mbed_official 363:12a245e5c745 6103 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
mbed_official 363:12a245e5c745 6104 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
mbed_official 363:12a245e5c745 6105 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
mbed_official 363:12a245e5c745 6106 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
mbed_official 363:12a245e5c745 6107 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
mbed_official 363:12a245e5c745 6108 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
mbed_official 363:12a245e5c745 6109 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
mbed_official 363:12a245e5c745 6110 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
mbed_official 363:12a245e5c745 6111 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
mbed_official 363:12a245e5c745 6112 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
mbed_official 363:12a245e5c745 6113 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
mbed_official 363:12a245e5c745 6114 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
mbed_official 363:12a245e5c745 6115 /* PORTD */
mbed_official 363:12a245e5c745 6116 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
mbed_official 363:12a245e5c745 6117 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
mbed_official 363:12a245e5c745 6118 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
mbed_official 363:12a245e5c745 6119 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
mbed_official 363:12a245e5c745 6120 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
mbed_official 363:12a245e5c745 6121 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
mbed_official 363:12a245e5c745 6122 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
mbed_official 363:12a245e5c745 6123 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
mbed_official 363:12a245e5c745 6124 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
mbed_official 363:12a245e5c745 6125 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
mbed_official 363:12a245e5c745 6126 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
mbed_official 363:12a245e5c745 6127 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
mbed_official 363:12a245e5c745 6128 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
mbed_official 363:12a245e5c745 6129 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
mbed_official 363:12a245e5c745 6130 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
mbed_official 363:12a245e5c745 6131 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
mbed_official 363:12a245e5c745 6132 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
mbed_official 363:12a245e5c745 6133 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
mbed_official 363:12a245e5c745 6134 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
mbed_official 363:12a245e5c745 6135 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
mbed_official 363:12a245e5c745 6136 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
mbed_official 363:12a245e5c745 6137 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
mbed_official 363:12a245e5c745 6138 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
mbed_official 363:12a245e5c745 6139 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
mbed_official 363:12a245e5c745 6140 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
mbed_official 363:12a245e5c745 6141 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
mbed_official 363:12a245e5c745 6142 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
mbed_official 363:12a245e5c745 6143 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
mbed_official 363:12a245e5c745 6144 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
mbed_official 363:12a245e5c745 6145 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
mbed_official 363:12a245e5c745 6146 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
mbed_official 363:12a245e5c745 6147 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
mbed_official 363:12a245e5c745 6148 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
mbed_official 363:12a245e5c745 6149 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
mbed_official 363:12a245e5c745 6150 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
mbed_official 363:12a245e5c745 6151 /* PORTE */
mbed_official 363:12a245e5c745 6152 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
mbed_official 363:12a245e5c745 6153 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
mbed_official 363:12a245e5c745 6154 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
mbed_official 363:12a245e5c745 6155 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
mbed_official 363:12a245e5c745 6156 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
mbed_official 363:12a245e5c745 6157 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
mbed_official 363:12a245e5c745 6158 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
mbed_official 363:12a245e5c745 6159 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
mbed_official 363:12a245e5c745 6160 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
mbed_official 363:12a245e5c745 6161 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
mbed_official 363:12a245e5c745 6162 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
mbed_official 363:12a245e5c745 6163 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
mbed_official 363:12a245e5c745 6164 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
mbed_official 363:12a245e5c745 6165 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
mbed_official 363:12a245e5c745 6166 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
mbed_official 363:12a245e5c745 6167 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
mbed_official 363:12a245e5c745 6168 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
mbed_official 363:12a245e5c745 6169 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
mbed_official 363:12a245e5c745 6170 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
mbed_official 363:12a245e5c745 6171 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
mbed_official 363:12a245e5c745 6172 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
mbed_official 363:12a245e5c745 6173 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
mbed_official 363:12a245e5c745 6174 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
mbed_official 363:12a245e5c745 6175 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
mbed_official 363:12a245e5c745 6176 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
mbed_official 363:12a245e5c745 6177 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
mbed_official 363:12a245e5c745 6178 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
mbed_official 363:12a245e5c745 6179 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
mbed_official 363:12a245e5c745 6180 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
mbed_official 363:12a245e5c745 6181 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
mbed_official 363:12a245e5c745 6182 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
mbed_official 363:12a245e5c745 6183 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
mbed_official 363:12a245e5c745 6184 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
mbed_official 363:12a245e5c745 6185 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
mbed_official 363:12a245e5c745 6186 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
mbed_official 363:12a245e5c745 6187
mbed_official 363:12a245e5c745 6188 /* PORT - Register array accessors */
mbed_official 363:12a245e5c745 6189 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
mbed_official 363:12a245e5c745 6190 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
mbed_official 363:12a245e5c745 6191 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
mbed_official 363:12a245e5c745 6192 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
mbed_official 363:12a245e5c745 6193 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
mbed_official 363:12a245e5c745 6194
mbed_official 363:12a245e5c745 6195 /*!
mbed_official 363:12a245e5c745 6196 * @}
mbed_official 363:12a245e5c745 6197 */ /* end of group PORT_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 6198
mbed_official 363:12a245e5c745 6199
mbed_official 363:12a245e5c745 6200 /*!
mbed_official 363:12a245e5c745 6201 * @}
mbed_official 363:12a245e5c745 6202 */ /* end of group PORT_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 6203
mbed_official 363:12a245e5c745 6204
mbed_official 363:12a245e5c745 6205 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6206 -- RCM Peripheral Access Layer
mbed_official 363:12a245e5c745 6207 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6208
mbed_official 363:12a245e5c745 6209 /*!
mbed_official 363:12a245e5c745 6210 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
mbed_official 363:12a245e5c745 6211 * @{
mbed_official 363:12a245e5c745 6212 */
mbed_official 363:12a245e5c745 6213
mbed_official 363:12a245e5c745 6214 /** RCM - Register Layout Typedef */
mbed_official 363:12a245e5c745 6215 typedef struct {
mbed_official 363:12a245e5c745 6216 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
mbed_official 363:12a245e5c745 6217 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
mbed_official 363:12a245e5c745 6218 uint8_t RESERVED_0[2];
mbed_official 363:12a245e5c745 6219 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
mbed_official 363:12a245e5c745 6220 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
mbed_official 363:12a245e5c745 6221 __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
mbed_official 363:12a245e5c745 6222 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */
mbed_official 363:12a245e5c745 6223 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
mbed_official 363:12a245e5c745 6224 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
mbed_official 363:12a245e5c745 6225 } RCM_Type, *RCM_MemMapPtr;
mbed_official 363:12a245e5c745 6226
mbed_official 363:12a245e5c745 6227 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6228 -- RCM - Register accessor macros
mbed_official 363:12a245e5c745 6229 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6230
mbed_official 363:12a245e5c745 6231 /*!
mbed_official 363:12a245e5c745 6232 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
mbed_official 363:12a245e5c745 6233 * @{
mbed_official 363:12a245e5c745 6234 */
mbed_official 363:12a245e5c745 6235
mbed_official 363:12a245e5c745 6236
mbed_official 363:12a245e5c745 6237 /* RCM - Register accessors */
mbed_official 363:12a245e5c745 6238 #define RCM_SRS0_REG(base) ((base)->SRS0)
mbed_official 363:12a245e5c745 6239 #define RCM_SRS1_REG(base) ((base)->SRS1)
mbed_official 363:12a245e5c745 6240 #define RCM_RPFC_REG(base) ((base)->RPFC)
mbed_official 363:12a245e5c745 6241 #define RCM_RPFW_REG(base) ((base)->RPFW)
mbed_official 363:12a245e5c745 6242 #define RCM_FM_REG(base) ((base)->FM)
mbed_official 363:12a245e5c745 6243 #define RCM_MR_REG(base) ((base)->MR)
mbed_official 363:12a245e5c745 6244 #define RCM_SSRS0_REG(base) ((base)->SSRS0)
mbed_official 363:12a245e5c745 6245 #define RCM_SSRS1_REG(base) ((base)->SSRS1)
mbed_official 363:12a245e5c745 6246
mbed_official 363:12a245e5c745 6247 /*!
mbed_official 363:12a245e5c745 6248 * @}
mbed_official 363:12a245e5c745 6249 */ /* end of group RCM_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 6250
mbed_official 363:12a245e5c745 6251
mbed_official 363:12a245e5c745 6252 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6253 -- RCM Register Masks
mbed_official 363:12a245e5c745 6254 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6255
mbed_official 363:12a245e5c745 6256 /*!
mbed_official 363:12a245e5c745 6257 * @addtogroup RCM_Register_Masks RCM Register Masks
mbed_official 363:12a245e5c745 6258 * @{
mbed_official 363:12a245e5c745 6259 */
mbed_official 363:12a245e5c745 6260
mbed_official 363:12a245e5c745 6261 /* SRS0 Bit Fields */
mbed_official 363:12a245e5c745 6262 #define RCM_SRS0_WAKEUP_MASK 0x1u
mbed_official 363:12a245e5c745 6263 #define RCM_SRS0_WAKEUP_SHIFT 0
mbed_official 363:12a245e5c745 6264 #define RCM_SRS0_LVD_MASK 0x2u
mbed_official 363:12a245e5c745 6265 #define RCM_SRS0_LVD_SHIFT 1
mbed_official 363:12a245e5c745 6266 #define RCM_SRS0_WDOG_MASK 0x20u
mbed_official 363:12a245e5c745 6267 #define RCM_SRS0_WDOG_SHIFT 5
mbed_official 363:12a245e5c745 6268 #define RCM_SRS0_PIN_MASK 0x40u
mbed_official 363:12a245e5c745 6269 #define RCM_SRS0_PIN_SHIFT 6
mbed_official 363:12a245e5c745 6270 #define RCM_SRS0_POR_MASK 0x80u
mbed_official 363:12a245e5c745 6271 #define RCM_SRS0_POR_SHIFT 7
mbed_official 363:12a245e5c745 6272 /* SRS1 Bit Fields */
mbed_official 363:12a245e5c745 6273 #define RCM_SRS1_LOCKUP_MASK 0x2u
mbed_official 363:12a245e5c745 6274 #define RCM_SRS1_LOCKUP_SHIFT 1
mbed_official 363:12a245e5c745 6275 #define RCM_SRS1_SW_MASK 0x4u
mbed_official 363:12a245e5c745 6276 #define RCM_SRS1_SW_SHIFT 2
mbed_official 363:12a245e5c745 6277 #define RCM_SRS1_MDM_AP_MASK 0x8u
mbed_official 363:12a245e5c745 6278 #define RCM_SRS1_MDM_AP_SHIFT 3
mbed_official 363:12a245e5c745 6279 #define RCM_SRS1_SACKERR_MASK 0x20u
mbed_official 363:12a245e5c745 6280 #define RCM_SRS1_SACKERR_SHIFT 5
mbed_official 363:12a245e5c745 6281 /* RPFC Bit Fields */
mbed_official 363:12a245e5c745 6282 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
mbed_official 363:12a245e5c745 6283 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
mbed_official 363:12a245e5c745 6284 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
mbed_official 363:12a245e5c745 6285 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
mbed_official 363:12a245e5c745 6286 #define RCM_RPFC_RSTFLTSS_SHIFT 2
mbed_official 363:12a245e5c745 6287 /* RPFW Bit Fields */
mbed_official 363:12a245e5c745 6288 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
mbed_official 363:12a245e5c745 6289 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
mbed_official 363:12a245e5c745 6290 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
mbed_official 363:12a245e5c745 6291 /* FM Bit Fields */
mbed_official 363:12a245e5c745 6292 #define RCM_FM_FORCEROM_MASK 0x6u
mbed_official 363:12a245e5c745 6293 #define RCM_FM_FORCEROM_SHIFT 1
mbed_official 363:12a245e5c745 6294 #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_FM_FORCEROM_SHIFT))&RCM_FM_FORCEROM_MASK)
mbed_official 363:12a245e5c745 6295 /* MR Bit Fields */
mbed_official 363:12a245e5c745 6296 #define RCM_MR_BOOTROM_MASK 0x6u
mbed_official 363:12a245e5c745 6297 #define RCM_MR_BOOTROM_SHIFT 1
mbed_official 363:12a245e5c745 6298 #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_MR_BOOTROM_SHIFT))&RCM_MR_BOOTROM_MASK)
mbed_official 363:12a245e5c745 6299 /* SSRS0 Bit Fields */
mbed_official 363:12a245e5c745 6300 #define RCM_SSRS0_SWAKEUP_MASK 0x1u
mbed_official 363:12a245e5c745 6301 #define RCM_SSRS0_SWAKEUP_SHIFT 0
mbed_official 363:12a245e5c745 6302 #define RCM_SSRS0_SLVD_MASK 0x2u
mbed_official 363:12a245e5c745 6303 #define RCM_SSRS0_SLVD_SHIFT 1
mbed_official 363:12a245e5c745 6304 #define RCM_SSRS0_SWDOG_MASK 0x20u
mbed_official 363:12a245e5c745 6305 #define RCM_SSRS0_SWDOG_SHIFT 5
mbed_official 363:12a245e5c745 6306 #define RCM_SSRS0_SPIN_MASK 0x40u
mbed_official 363:12a245e5c745 6307 #define RCM_SSRS0_SPIN_SHIFT 6
mbed_official 363:12a245e5c745 6308 #define RCM_SSRS0_SPOR_MASK 0x80u
mbed_official 363:12a245e5c745 6309 #define RCM_SSRS0_SPOR_SHIFT 7
mbed_official 363:12a245e5c745 6310 /* SSRS1 Bit Fields */
mbed_official 363:12a245e5c745 6311 #define RCM_SSRS1_SLOCKUP_MASK 0x2u
mbed_official 363:12a245e5c745 6312 #define RCM_SSRS1_SLOCKUP_SHIFT 1
mbed_official 363:12a245e5c745 6313 #define RCM_SSRS1_SSW_MASK 0x4u
mbed_official 363:12a245e5c745 6314 #define RCM_SSRS1_SSW_SHIFT 2
mbed_official 363:12a245e5c745 6315 #define RCM_SSRS1_SMDM_AP_MASK 0x8u
mbed_official 363:12a245e5c745 6316 #define RCM_SSRS1_SMDM_AP_SHIFT 3
mbed_official 363:12a245e5c745 6317 #define RCM_SSRS1_SSACKERR_MASK 0x20u
mbed_official 363:12a245e5c745 6318 #define RCM_SSRS1_SSACKERR_SHIFT 5
mbed_official 363:12a245e5c745 6319
mbed_official 363:12a245e5c745 6320 /*!
mbed_official 363:12a245e5c745 6321 * @}
mbed_official 363:12a245e5c745 6322 */ /* end of group RCM_Register_Masks */
mbed_official 363:12a245e5c745 6323
mbed_official 363:12a245e5c745 6324
mbed_official 363:12a245e5c745 6325 /* RCM - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 6326 /** Peripheral RCM base address */
mbed_official 363:12a245e5c745 6327 #define RCM_BASE (0x4007F000u)
mbed_official 363:12a245e5c745 6328 /** Peripheral RCM base pointer */
mbed_official 363:12a245e5c745 6329 #define RCM ((RCM_Type *)RCM_BASE)
mbed_official 363:12a245e5c745 6330 #define RCM_BASE_PTR (RCM)
mbed_official 363:12a245e5c745 6331 /** Array initializer of RCM peripheral base addresses */
mbed_official 363:12a245e5c745 6332 #define RCM_BASE_ADDRS { RCM_BASE }
mbed_official 363:12a245e5c745 6333 /** Array initializer of RCM peripheral base pointers */
mbed_official 363:12a245e5c745 6334 #define RCM_BASE_PTRS { RCM }
mbed_official 363:12a245e5c745 6335
mbed_official 363:12a245e5c745 6336 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6337 -- RCM - Register accessor macros
mbed_official 363:12a245e5c745 6338 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6339
mbed_official 363:12a245e5c745 6340 /*!
mbed_official 363:12a245e5c745 6341 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
mbed_official 363:12a245e5c745 6342 * @{
mbed_official 363:12a245e5c745 6343 */
mbed_official 363:12a245e5c745 6344
mbed_official 363:12a245e5c745 6345
mbed_official 363:12a245e5c745 6346 /* RCM - Register instance definitions */
mbed_official 363:12a245e5c745 6347 /* RCM */
mbed_official 363:12a245e5c745 6348 #define RCM_SRS0 RCM_SRS0_REG(RCM)
mbed_official 363:12a245e5c745 6349 #define RCM_SRS1 RCM_SRS1_REG(RCM)
mbed_official 363:12a245e5c745 6350 #define RCM_RPFC RCM_RPFC_REG(RCM)
mbed_official 363:12a245e5c745 6351 #define RCM_RPFW RCM_RPFW_REG(RCM)
mbed_official 363:12a245e5c745 6352 #define RCM_FM RCM_FM_REG(RCM)
mbed_official 363:12a245e5c745 6353 #define RCM_MR RCM_MR_REG(RCM)
mbed_official 363:12a245e5c745 6354 #define RCM_SSRS0 RCM_SSRS0_REG(RCM)
mbed_official 363:12a245e5c745 6355 #define RCM_SSRS1 RCM_SSRS1_REG(RCM)
mbed_official 363:12a245e5c745 6356
mbed_official 363:12a245e5c745 6357 /*!
mbed_official 363:12a245e5c745 6358 * @}
mbed_official 363:12a245e5c745 6359 */ /* end of group RCM_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 6360
mbed_official 363:12a245e5c745 6361
mbed_official 363:12a245e5c745 6362 /*!
mbed_official 363:12a245e5c745 6363 * @}
mbed_official 363:12a245e5c745 6364 */ /* end of group RCM_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 6365
mbed_official 363:12a245e5c745 6366
mbed_official 363:12a245e5c745 6367 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6368 -- RFSYS Peripheral Access Layer
mbed_official 363:12a245e5c745 6369 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6370
mbed_official 363:12a245e5c745 6371 /*!
mbed_official 363:12a245e5c745 6372 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
mbed_official 363:12a245e5c745 6373 * @{
mbed_official 363:12a245e5c745 6374 */
mbed_official 363:12a245e5c745 6375
mbed_official 363:12a245e5c745 6376 /** RFSYS - Register Layout Typedef */
mbed_official 363:12a245e5c745 6377 typedef struct {
mbed_official 363:12a245e5c745 6378 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
mbed_official 363:12a245e5c745 6379 } RFSYS_Type, *RFSYS_MemMapPtr;
mbed_official 363:12a245e5c745 6380
mbed_official 363:12a245e5c745 6381 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6382 -- RFSYS - Register accessor macros
mbed_official 363:12a245e5c745 6383 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6384
mbed_official 363:12a245e5c745 6385 /*!
mbed_official 363:12a245e5c745 6386 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
mbed_official 363:12a245e5c745 6387 * @{
mbed_official 363:12a245e5c745 6388 */
mbed_official 363:12a245e5c745 6389
mbed_official 363:12a245e5c745 6390
mbed_official 363:12a245e5c745 6391 /* RFSYS - Register accessors */
mbed_official 363:12a245e5c745 6392 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
mbed_official 363:12a245e5c745 6393
mbed_official 363:12a245e5c745 6394 /*!
mbed_official 363:12a245e5c745 6395 * @}
mbed_official 363:12a245e5c745 6396 */ /* end of group RFSYS_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 6397
mbed_official 363:12a245e5c745 6398
mbed_official 363:12a245e5c745 6399 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6400 -- RFSYS Register Masks
mbed_official 363:12a245e5c745 6401 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6402
mbed_official 363:12a245e5c745 6403 /*!
mbed_official 363:12a245e5c745 6404 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
mbed_official 363:12a245e5c745 6405 * @{
mbed_official 363:12a245e5c745 6406 */
mbed_official 363:12a245e5c745 6407
mbed_official 363:12a245e5c745 6408 /* REG Bit Fields */
mbed_official 363:12a245e5c745 6409 #define RFSYS_REG_LL_MASK 0xFFu
mbed_official 363:12a245e5c745 6410 #define RFSYS_REG_LL_SHIFT 0
mbed_official 363:12a245e5c745 6411 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
mbed_official 363:12a245e5c745 6412 #define RFSYS_REG_LH_MASK 0xFF00u
mbed_official 363:12a245e5c745 6413 #define RFSYS_REG_LH_SHIFT 8
mbed_official 363:12a245e5c745 6414 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
mbed_official 363:12a245e5c745 6415 #define RFSYS_REG_HL_MASK 0xFF0000u
mbed_official 363:12a245e5c745 6416 #define RFSYS_REG_HL_SHIFT 16
mbed_official 363:12a245e5c745 6417 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
mbed_official 363:12a245e5c745 6418 #define RFSYS_REG_HH_MASK 0xFF000000u
mbed_official 363:12a245e5c745 6419 #define RFSYS_REG_HH_SHIFT 24
mbed_official 363:12a245e5c745 6420 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
mbed_official 363:12a245e5c745 6421
mbed_official 363:12a245e5c745 6422 /*!
mbed_official 363:12a245e5c745 6423 * @}
mbed_official 363:12a245e5c745 6424 */ /* end of group RFSYS_Register_Masks */
mbed_official 363:12a245e5c745 6425
mbed_official 363:12a245e5c745 6426
mbed_official 363:12a245e5c745 6427 /* RFSYS - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 6428 /** Peripheral RFSYS base address */
mbed_official 363:12a245e5c745 6429 #define RFSYS_BASE (0x40041000u)
mbed_official 363:12a245e5c745 6430 /** Peripheral RFSYS base pointer */
mbed_official 363:12a245e5c745 6431 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
mbed_official 363:12a245e5c745 6432 #define RFSYS_BASE_PTR (RFSYS)
mbed_official 363:12a245e5c745 6433 /** Array initializer of RFSYS peripheral base addresses */
mbed_official 363:12a245e5c745 6434 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
mbed_official 363:12a245e5c745 6435 /** Array initializer of RFSYS peripheral base pointers */
mbed_official 363:12a245e5c745 6436 #define RFSYS_BASE_PTRS { RFSYS }
mbed_official 363:12a245e5c745 6437
mbed_official 363:12a245e5c745 6438 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6439 -- RFSYS - Register accessor macros
mbed_official 363:12a245e5c745 6440 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6441
mbed_official 363:12a245e5c745 6442 /*!
mbed_official 363:12a245e5c745 6443 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
mbed_official 363:12a245e5c745 6444 * @{
mbed_official 363:12a245e5c745 6445 */
mbed_official 363:12a245e5c745 6446
mbed_official 363:12a245e5c745 6447
mbed_official 363:12a245e5c745 6448 /* RFSYS - Register instance definitions */
mbed_official 363:12a245e5c745 6449 /* RFSYS */
mbed_official 363:12a245e5c745 6450 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
mbed_official 363:12a245e5c745 6451 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
mbed_official 363:12a245e5c745 6452 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
mbed_official 363:12a245e5c745 6453 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
mbed_official 363:12a245e5c745 6454 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
mbed_official 363:12a245e5c745 6455 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
mbed_official 363:12a245e5c745 6456 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
mbed_official 363:12a245e5c745 6457 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
mbed_official 363:12a245e5c745 6458
mbed_official 363:12a245e5c745 6459 /* RFSYS - Register array accessors */
mbed_official 363:12a245e5c745 6460 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
mbed_official 363:12a245e5c745 6461
mbed_official 363:12a245e5c745 6462 /*!
mbed_official 363:12a245e5c745 6463 * @}
mbed_official 363:12a245e5c745 6464 */ /* end of group RFSYS_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 6465
mbed_official 363:12a245e5c745 6466
mbed_official 363:12a245e5c745 6467 /*!
mbed_official 363:12a245e5c745 6468 * @}
mbed_official 363:12a245e5c745 6469 */ /* end of group RFSYS_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 6470
mbed_official 363:12a245e5c745 6471
mbed_official 363:12a245e5c745 6472 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6473 -- ROM Peripheral Access Layer
mbed_official 363:12a245e5c745 6474 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6475
mbed_official 363:12a245e5c745 6476 /*!
mbed_official 363:12a245e5c745 6477 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
mbed_official 363:12a245e5c745 6478 * @{
mbed_official 363:12a245e5c745 6479 */
mbed_official 363:12a245e5c745 6480
mbed_official 363:12a245e5c745 6481 /** ROM - Register Layout Typedef */
mbed_official 363:12a245e5c745 6482 typedef struct {
mbed_official 363:12a245e5c745 6483 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
mbed_official 363:12a245e5c745 6484 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
mbed_official 363:12a245e5c745 6485 uint8_t RESERVED_0[4028];
mbed_official 363:12a245e5c745 6486 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
mbed_official 363:12a245e5c745 6487 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
mbed_official 363:12a245e5c745 6488 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
mbed_official 363:12a245e5c745 6489 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
mbed_official 363:12a245e5c745 6490 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
mbed_official 363:12a245e5c745 6491 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
mbed_official 363:12a245e5c745 6492 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
mbed_official 363:12a245e5c745 6493 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
mbed_official 363:12a245e5c745 6494 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
mbed_official 363:12a245e5c745 6495 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
mbed_official 363:12a245e5c745 6496 } ROM_Type, *ROM_MemMapPtr;
mbed_official 363:12a245e5c745 6497
mbed_official 363:12a245e5c745 6498 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6499 -- ROM - Register accessor macros
mbed_official 363:12a245e5c745 6500 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6501
mbed_official 363:12a245e5c745 6502 /*!
mbed_official 363:12a245e5c745 6503 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
mbed_official 363:12a245e5c745 6504 * @{
mbed_official 363:12a245e5c745 6505 */
mbed_official 363:12a245e5c745 6506
mbed_official 363:12a245e5c745 6507
mbed_official 363:12a245e5c745 6508 /* ROM - Register accessors */
mbed_official 363:12a245e5c745 6509 #define ROM_ENTRY_REG(base,index) ((base)->ENTRY[index])
mbed_official 363:12a245e5c745 6510 #define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK)
mbed_official 363:12a245e5c745 6511 #define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS)
mbed_official 363:12a245e5c745 6512 #define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4)
mbed_official 363:12a245e5c745 6513 #define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5)
mbed_official 363:12a245e5c745 6514 #define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6)
mbed_official 363:12a245e5c745 6515 #define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7)
mbed_official 363:12a245e5c745 6516 #define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0)
mbed_official 363:12a245e5c745 6517 #define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1)
mbed_official 363:12a245e5c745 6518 #define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2)
mbed_official 363:12a245e5c745 6519 #define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3)
mbed_official 363:12a245e5c745 6520 #define ROM_COMPID_REG(base,index) ((base)->COMPID[index])
mbed_official 363:12a245e5c745 6521
mbed_official 363:12a245e5c745 6522 /*!
mbed_official 363:12a245e5c745 6523 * @}
mbed_official 363:12a245e5c745 6524 */ /* end of group ROM_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 6525
mbed_official 363:12a245e5c745 6526
mbed_official 363:12a245e5c745 6527 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6528 -- ROM Register Masks
mbed_official 363:12a245e5c745 6529 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6530
mbed_official 363:12a245e5c745 6531 /*!
mbed_official 363:12a245e5c745 6532 * @addtogroup ROM_Register_Masks ROM Register Masks
mbed_official 363:12a245e5c745 6533 * @{
mbed_official 363:12a245e5c745 6534 */
mbed_official 363:12a245e5c745 6535
mbed_official 363:12a245e5c745 6536 /* ENTRY Bit Fields */
mbed_official 363:12a245e5c745 6537 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6538 #define ROM_ENTRY_ENTRY_SHIFT 0
mbed_official 363:12a245e5c745 6539 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
mbed_official 363:12a245e5c745 6540 /* TABLEMARK Bit Fields */
mbed_official 363:12a245e5c745 6541 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6542 #define ROM_TABLEMARK_MARK_SHIFT 0
mbed_official 363:12a245e5c745 6543 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
mbed_official 363:12a245e5c745 6544 /* SYSACCESS Bit Fields */
mbed_official 363:12a245e5c745 6545 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6546 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
mbed_official 363:12a245e5c745 6547 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
mbed_official 363:12a245e5c745 6548 /* PERIPHID4 Bit Fields */
mbed_official 363:12a245e5c745 6549 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6550 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
mbed_official 363:12a245e5c745 6551 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
mbed_official 363:12a245e5c745 6552 /* PERIPHID5 Bit Fields */
mbed_official 363:12a245e5c745 6553 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6554 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
mbed_official 363:12a245e5c745 6555 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
mbed_official 363:12a245e5c745 6556 /* PERIPHID6 Bit Fields */
mbed_official 363:12a245e5c745 6557 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6558 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
mbed_official 363:12a245e5c745 6559 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
mbed_official 363:12a245e5c745 6560 /* PERIPHID7 Bit Fields */
mbed_official 363:12a245e5c745 6561 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6562 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
mbed_official 363:12a245e5c745 6563 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
mbed_official 363:12a245e5c745 6564 /* PERIPHID0 Bit Fields */
mbed_official 363:12a245e5c745 6565 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6566 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
mbed_official 363:12a245e5c745 6567 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
mbed_official 363:12a245e5c745 6568 /* PERIPHID1 Bit Fields */
mbed_official 363:12a245e5c745 6569 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6570 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
mbed_official 363:12a245e5c745 6571 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
mbed_official 363:12a245e5c745 6572 /* PERIPHID2 Bit Fields */
mbed_official 363:12a245e5c745 6573 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6574 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
mbed_official 363:12a245e5c745 6575 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
mbed_official 363:12a245e5c745 6576 /* PERIPHID3 Bit Fields */
mbed_official 363:12a245e5c745 6577 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6578 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
mbed_official 363:12a245e5c745 6579 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
mbed_official 363:12a245e5c745 6580 /* COMPID Bit Fields */
mbed_official 363:12a245e5c745 6581 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6582 #define ROM_COMPID_COMPID_SHIFT 0
mbed_official 363:12a245e5c745 6583 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
mbed_official 363:12a245e5c745 6584
mbed_official 363:12a245e5c745 6585 /*!
mbed_official 363:12a245e5c745 6586 * @}
mbed_official 363:12a245e5c745 6587 */ /* end of group ROM_Register_Masks */
mbed_official 363:12a245e5c745 6588
mbed_official 363:12a245e5c745 6589
mbed_official 363:12a245e5c745 6590 /* ROM - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 6591 /** Peripheral ROM base address */
mbed_official 363:12a245e5c745 6592 #define ROM_BASE (0xF0002000u)
mbed_official 363:12a245e5c745 6593 /** Peripheral ROM base pointer */
mbed_official 363:12a245e5c745 6594 #define ROM ((ROM_Type *)ROM_BASE)
mbed_official 363:12a245e5c745 6595 #define ROM_BASE_PTR (ROM)
mbed_official 363:12a245e5c745 6596 /** Array initializer of ROM peripheral base addresses */
mbed_official 363:12a245e5c745 6597 #define ROM_BASE_ADDRS { ROM_BASE }
mbed_official 363:12a245e5c745 6598 /** Array initializer of ROM peripheral base pointers */
mbed_official 363:12a245e5c745 6599 #define ROM_BASE_PTRS { ROM }
mbed_official 363:12a245e5c745 6600
mbed_official 363:12a245e5c745 6601 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6602 -- ROM - Register accessor macros
mbed_official 363:12a245e5c745 6603 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6604
mbed_official 363:12a245e5c745 6605 /*!
mbed_official 363:12a245e5c745 6606 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
mbed_official 363:12a245e5c745 6607 * @{
mbed_official 363:12a245e5c745 6608 */
mbed_official 363:12a245e5c745 6609
mbed_official 363:12a245e5c745 6610
mbed_official 363:12a245e5c745 6611 /* ROM - Register instance definitions */
mbed_official 363:12a245e5c745 6612 /* ROM */
mbed_official 363:12a245e5c745 6613 #define ROM_ENTRY0 ROM_ENTRY_REG(ROM,0)
mbed_official 363:12a245e5c745 6614 #define ROM_ENTRY1 ROM_ENTRY_REG(ROM,1)
mbed_official 363:12a245e5c745 6615 #define ROM_ENTRY2 ROM_ENTRY_REG(ROM,2)
mbed_official 363:12a245e5c745 6616 #define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM)
mbed_official 363:12a245e5c745 6617 #define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM)
mbed_official 363:12a245e5c745 6618 #define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM)
mbed_official 363:12a245e5c745 6619 #define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM)
mbed_official 363:12a245e5c745 6620 #define ROM_PERIPHID6 ROM_PERIPHID6_REG(ROM)
mbed_official 363:12a245e5c745 6621 #define ROM_PERIPHID7 ROM_PERIPHID7_REG(ROM)
mbed_official 363:12a245e5c745 6622 #define ROM_PERIPHID0 ROM_PERIPHID0_REG(ROM)
mbed_official 363:12a245e5c745 6623 #define ROM_PERIPHID1 ROM_PERIPHID1_REG(ROM)
mbed_official 363:12a245e5c745 6624 #define ROM_PERIPHID2 ROM_PERIPHID2_REG(ROM)
mbed_official 363:12a245e5c745 6625 #define ROM_PERIPHID3 ROM_PERIPHID3_REG(ROM)
mbed_official 363:12a245e5c745 6626 #define ROM_COMPID0 ROM_COMPID_REG(ROM,0)
mbed_official 363:12a245e5c745 6627 #define ROM_COMPID1 ROM_COMPID_REG(ROM,1)
mbed_official 363:12a245e5c745 6628 #define ROM_COMPID2 ROM_COMPID_REG(ROM,2)
mbed_official 363:12a245e5c745 6629 #define ROM_COMPID3 ROM_COMPID_REG(ROM,3)
mbed_official 363:12a245e5c745 6630
mbed_official 363:12a245e5c745 6631 /* ROM - Register array accessors */
mbed_official 363:12a245e5c745 6632 #define ROM_ENTRY(index) ROM_ENTRY_REG(ROM,index)
mbed_official 363:12a245e5c745 6633 #define ROM_COMPID(index) ROM_COMPID_REG(ROM,index)
mbed_official 363:12a245e5c745 6634
mbed_official 363:12a245e5c745 6635 /*!
mbed_official 363:12a245e5c745 6636 * @}
mbed_official 363:12a245e5c745 6637 */ /* end of group ROM_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 6638
mbed_official 363:12a245e5c745 6639
mbed_official 363:12a245e5c745 6640 /*!
mbed_official 363:12a245e5c745 6641 * @}
mbed_official 363:12a245e5c745 6642 */ /* end of group ROM_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 6643
mbed_official 363:12a245e5c745 6644
mbed_official 363:12a245e5c745 6645 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6646 -- RTC Peripheral Access Layer
mbed_official 363:12a245e5c745 6647 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6648
mbed_official 363:12a245e5c745 6649 /*!
mbed_official 363:12a245e5c745 6650 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
mbed_official 363:12a245e5c745 6651 * @{
mbed_official 363:12a245e5c745 6652 */
mbed_official 363:12a245e5c745 6653
mbed_official 363:12a245e5c745 6654 /** RTC - Register Layout Typedef */
mbed_official 363:12a245e5c745 6655 typedef struct {
mbed_official 363:12a245e5c745 6656 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
mbed_official 363:12a245e5c745 6657 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
mbed_official 363:12a245e5c745 6658 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
mbed_official 363:12a245e5c745 6659 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
mbed_official 363:12a245e5c745 6660 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
mbed_official 363:12a245e5c745 6661 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
mbed_official 363:12a245e5c745 6662 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
mbed_official 363:12a245e5c745 6663 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
mbed_official 363:12a245e5c745 6664 } RTC_Type, *RTC_MemMapPtr;
mbed_official 363:12a245e5c745 6665
mbed_official 363:12a245e5c745 6666 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6667 -- RTC - Register accessor macros
mbed_official 363:12a245e5c745 6668 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6669
mbed_official 363:12a245e5c745 6670 /*!
mbed_official 363:12a245e5c745 6671 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
mbed_official 363:12a245e5c745 6672 * @{
mbed_official 363:12a245e5c745 6673 */
mbed_official 363:12a245e5c745 6674
mbed_official 363:12a245e5c745 6675
mbed_official 363:12a245e5c745 6676 /* RTC - Register accessors */
mbed_official 363:12a245e5c745 6677 #define RTC_TSR_REG(base) ((base)->TSR)
mbed_official 363:12a245e5c745 6678 #define RTC_TPR_REG(base) ((base)->TPR)
mbed_official 363:12a245e5c745 6679 #define RTC_TAR_REG(base) ((base)->TAR)
mbed_official 363:12a245e5c745 6680 #define RTC_TCR_REG(base) ((base)->TCR)
mbed_official 363:12a245e5c745 6681 #define RTC_CR_REG(base) ((base)->CR)
mbed_official 363:12a245e5c745 6682 #define RTC_SR_REG(base) ((base)->SR)
mbed_official 363:12a245e5c745 6683 #define RTC_LR_REG(base) ((base)->LR)
mbed_official 363:12a245e5c745 6684 #define RTC_IER_REG(base) ((base)->IER)
mbed_official 363:12a245e5c745 6685
mbed_official 363:12a245e5c745 6686 /*!
mbed_official 363:12a245e5c745 6687 * @}
mbed_official 363:12a245e5c745 6688 */ /* end of group RTC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 6689
mbed_official 363:12a245e5c745 6690
mbed_official 363:12a245e5c745 6691 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6692 -- RTC Register Masks
mbed_official 363:12a245e5c745 6693 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6694
mbed_official 363:12a245e5c745 6695 /*!
mbed_official 363:12a245e5c745 6696 * @addtogroup RTC_Register_Masks RTC Register Masks
mbed_official 363:12a245e5c745 6697 * @{
mbed_official 363:12a245e5c745 6698 */
mbed_official 363:12a245e5c745 6699
mbed_official 363:12a245e5c745 6700 /* TSR Bit Fields */
mbed_official 363:12a245e5c745 6701 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6702 #define RTC_TSR_TSR_SHIFT 0
mbed_official 363:12a245e5c745 6703 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
mbed_official 363:12a245e5c745 6704 /* TPR Bit Fields */
mbed_official 363:12a245e5c745 6705 #define RTC_TPR_TPR_MASK 0xFFFFu
mbed_official 363:12a245e5c745 6706 #define RTC_TPR_TPR_SHIFT 0
mbed_official 363:12a245e5c745 6707 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
mbed_official 363:12a245e5c745 6708 /* TAR Bit Fields */
mbed_official 363:12a245e5c745 6709 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 6710 #define RTC_TAR_TAR_SHIFT 0
mbed_official 363:12a245e5c745 6711 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
mbed_official 363:12a245e5c745 6712 /* TCR Bit Fields */
mbed_official 363:12a245e5c745 6713 #define RTC_TCR_TCR_MASK 0xFFu
mbed_official 363:12a245e5c745 6714 #define RTC_TCR_TCR_SHIFT 0
mbed_official 363:12a245e5c745 6715 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
mbed_official 363:12a245e5c745 6716 #define RTC_TCR_CIR_MASK 0xFF00u
mbed_official 363:12a245e5c745 6717 #define RTC_TCR_CIR_SHIFT 8
mbed_official 363:12a245e5c745 6718 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
mbed_official 363:12a245e5c745 6719 #define RTC_TCR_TCV_MASK 0xFF0000u
mbed_official 363:12a245e5c745 6720 #define RTC_TCR_TCV_SHIFT 16
mbed_official 363:12a245e5c745 6721 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
mbed_official 363:12a245e5c745 6722 #define RTC_TCR_CIC_MASK 0xFF000000u
mbed_official 363:12a245e5c745 6723 #define RTC_TCR_CIC_SHIFT 24
mbed_official 363:12a245e5c745 6724 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
mbed_official 363:12a245e5c745 6725 /* CR Bit Fields */
mbed_official 363:12a245e5c745 6726 #define RTC_CR_SWR_MASK 0x1u
mbed_official 363:12a245e5c745 6727 #define RTC_CR_SWR_SHIFT 0
mbed_official 363:12a245e5c745 6728 #define RTC_CR_WPE_MASK 0x2u
mbed_official 363:12a245e5c745 6729 #define RTC_CR_WPE_SHIFT 1
mbed_official 363:12a245e5c745 6730 #define RTC_CR_SUP_MASK 0x4u
mbed_official 363:12a245e5c745 6731 #define RTC_CR_SUP_SHIFT 2
mbed_official 363:12a245e5c745 6732 #define RTC_CR_UM_MASK 0x8u
mbed_official 363:12a245e5c745 6733 #define RTC_CR_UM_SHIFT 3
mbed_official 363:12a245e5c745 6734 #define RTC_CR_WPS_MASK 0x10u
mbed_official 363:12a245e5c745 6735 #define RTC_CR_WPS_SHIFT 4
mbed_official 363:12a245e5c745 6736 #define RTC_CR_OSCE_MASK 0x100u
mbed_official 363:12a245e5c745 6737 #define RTC_CR_OSCE_SHIFT 8
mbed_official 363:12a245e5c745 6738 #define RTC_CR_CLKO_MASK 0x200u
mbed_official 363:12a245e5c745 6739 #define RTC_CR_CLKO_SHIFT 9
mbed_official 363:12a245e5c745 6740 #define RTC_CR_SC16P_MASK 0x400u
mbed_official 363:12a245e5c745 6741 #define RTC_CR_SC16P_SHIFT 10
mbed_official 363:12a245e5c745 6742 #define RTC_CR_SC8P_MASK 0x800u
mbed_official 363:12a245e5c745 6743 #define RTC_CR_SC8P_SHIFT 11
mbed_official 363:12a245e5c745 6744 #define RTC_CR_SC4P_MASK 0x1000u
mbed_official 363:12a245e5c745 6745 #define RTC_CR_SC4P_SHIFT 12
mbed_official 363:12a245e5c745 6746 #define RTC_CR_SC2P_MASK 0x2000u
mbed_official 363:12a245e5c745 6747 #define RTC_CR_SC2P_SHIFT 13
mbed_official 363:12a245e5c745 6748 /* SR Bit Fields */
mbed_official 363:12a245e5c745 6749 #define RTC_SR_TIF_MASK 0x1u
mbed_official 363:12a245e5c745 6750 #define RTC_SR_TIF_SHIFT 0
mbed_official 363:12a245e5c745 6751 #define RTC_SR_TOF_MASK 0x2u
mbed_official 363:12a245e5c745 6752 #define RTC_SR_TOF_SHIFT 1
mbed_official 363:12a245e5c745 6753 #define RTC_SR_TAF_MASK 0x4u
mbed_official 363:12a245e5c745 6754 #define RTC_SR_TAF_SHIFT 2
mbed_official 363:12a245e5c745 6755 #define RTC_SR_TCE_MASK 0x10u
mbed_official 363:12a245e5c745 6756 #define RTC_SR_TCE_SHIFT 4
mbed_official 363:12a245e5c745 6757 /* LR Bit Fields */
mbed_official 363:12a245e5c745 6758 #define RTC_LR_TCL_MASK 0x8u
mbed_official 363:12a245e5c745 6759 #define RTC_LR_TCL_SHIFT 3
mbed_official 363:12a245e5c745 6760 #define RTC_LR_CRL_MASK 0x10u
mbed_official 363:12a245e5c745 6761 #define RTC_LR_CRL_SHIFT 4
mbed_official 363:12a245e5c745 6762 #define RTC_LR_SRL_MASK 0x20u
mbed_official 363:12a245e5c745 6763 #define RTC_LR_SRL_SHIFT 5
mbed_official 363:12a245e5c745 6764 #define RTC_LR_LRL_MASK 0x40u
mbed_official 363:12a245e5c745 6765 #define RTC_LR_LRL_SHIFT 6
mbed_official 363:12a245e5c745 6766 /* IER Bit Fields */
mbed_official 363:12a245e5c745 6767 #define RTC_IER_TIIE_MASK 0x1u
mbed_official 363:12a245e5c745 6768 #define RTC_IER_TIIE_SHIFT 0
mbed_official 363:12a245e5c745 6769 #define RTC_IER_TOIE_MASK 0x2u
mbed_official 363:12a245e5c745 6770 #define RTC_IER_TOIE_SHIFT 1
mbed_official 363:12a245e5c745 6771 #define RTC_IER_TAIE_MASK 0x4u
mbed_official 363:12a245e5c745 6772 #define RTC_IER_TAIE_SHIFT 2
mbed_official 363:12a245e5c745 6773 #define RTC_IER_TSIE_MASK 0x10u
mbed_official 363:12a245e5c745 6774 #define RTC_IER_TSIE_SHIFT 4
mbed_official 363:12a245e5c745 6775 #define RTC_IER_WPON_MASK 0x80u
mbed_official 363:12a245e5c745 6776 #define RTC_IER_WPON_SHIFT 7
mbed_official 363:12a245e5c745 6777
mbed_official 363:12a245e5c745 6778 /*!
mbed_official 363:12a245e5c745 6779 * @}
mbed_official 363:12a245e5c745 6780 */ /* end of group RTC_Register_Masks */
mbed_official 363:12a245e5c745 6781
mbed_official 363:12a245e5c745 6782
mbed_official 363:12a245e5c745 6783 /* RTC - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 6784 /** Peripheral RTC base address */
mbed_official 363:12a245e5c745 6785 #define RTC_BASE (0x4003D000u)
mbed_official 363:12a245e5c745 6786 /** Peripheral RTC base pointer */
mbed_official 363:12a245e5c745 6787 #define RTC ((RTC_Type *)RTC_BASE)
mbed_official 363:12a245e5c745 6788 #define RTC_BASE_PTR (RTC)
mbed_official 363:12a245e5c745 6789 /** Array initializer of RTC peripheral base addresses */
mbed_official 363:12a245e5c745 6790 #define RTC_BASE_ADDRS { RTC_BASE }
mbed_official 363:12a245e5c745 6791 /** Array initializer of RTC peripheral base pointers */
mbed_official 363:12a245e5c745 6792 #define RTC_BASE_PTRS { RTC }
mbed_official 363:12a245e5c745 6793 /** Interrupt vectors for the RTC peripheral type */
mbed_official 363:12a245e5c745 6794 #define RTC_IRQS { RTC_IRQn }
mbed_official 363:12a245e5c745 6795 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
mbed_official 363:12a245e5c745 6796
mbed_official 363:12a245e5c745 6797 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6798 -- RTC - Register accessor macros
mbed_official 363:12a245e5c745 6799 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6800
mbed_official 363:12a245e5c745 6801 /*!
mbed_official 363:12a245e5c745 6802 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
mbed_official 363:12a245e5c745 6803 * @{
mbed_official 363:12a245e5c745 6804 */
mbed_official 363:12a245e5c745 6805
mbed_official 363:12a245e5c745 6806
mbed_official 363:12a245e5c745 6807 /* RTC - Register instance definitions */
mbed_official 363:12a245e5c745 6808 /* RTC */
mbed_official 363:12a245e5c745 6809 #define RTC_TSR RTC_TSR_REG(RTC)
mbed_official 363:12a245e5c745 6810 #define RTC_TPR RTC_TPR_REG(RTC)
mbed_official 363:12a245e5c745 6811 #define RTC_TAR RTC_TAR_REG(RTC)
mbed_official 363:12a245e5c745 6812 #define RTC_TCR RTC_TCR_REG(RTC)
mbed_official 363:12a245e5c745 6813 #define RTC_CR RTC_CR_REG(RTC)
mbed_official 363:12a245e5c745 6814 #define RTC_SR RTC_SR_REG(RTC)
mbed_official 363:12a245e5c745 6815 #define RTC_LR RTC_LR_REG(RTC)
mbed_official 363:12a245e5c745 6816 #define RTC_IER RTC_IER_REG(RTC)
mbed_official 363:12a245e5c745 6817
mbed_official 363:12a245e5c745 6818 /*!
mbed_official 363:12a245e5c745 6819 * @}
mbed_official 363:12a245e5c745 6820 */ /* end of group RTC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 6821
mbed_official 363:12a245e5c745 6822
mbed_official 363:12a245e5c745 6823 /*!
mbed_official 363:12a245e5c745 6824 * @}
mbed_official 363:12a245e5c745 6825 */ /* end of group RTC_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 6826
mbed_official 363:12a245e5c745 6827
mbed_official 363:12a245e5c745 6828 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6829 -- SIM Peripheral Access Layer
mbed_official 363:12a245e5c745 6830 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6831
mbed_official 363:12a245e5c745 6832 /*!
mbed_official 363:12a245e5c745 6833 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
mbed_official 363:12a245e5c745 6834 * @{
mbed_official 363:12a245e5c745 6835 */
mbed_official 363:12a245e5c745 6836
mbed_official 363:12a245e5c745 6837 /** SIM - Register Layout Typedef */
mbed_official 363:12a245e5c745 6838 typedef struct {
mbed_official 363:12a245e5c745 6839 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
mbed_official 363:12a245e5c745 6840 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
mbed_official 363:12a245e5c745 6841 uint8_t RESERVED_0[4092];
mbed_official 363:12a245e5c745 6842 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
mbed_official 363:12a245e5c745 6843 uint8_t RESERVED_1[4];
mbed_official 363:12a245e5c745 6844 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
mbed_official 363:12a245e5c745 6845 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
mbed_official 363:12a245e5c745 6846 uint8_t RESERVED_2[4];
mbed_official 363:12a245e5c745 6847 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
mbed_official 363:12a245e5c745 6848 uint8_t RESERVED_3[8];
mbed_official 363:12a245e5c745 6849 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
mbed_official 363:12a245e5c745 6850 uint8_t RESERVED_4[12];
mbed_official 363:12a245e5c745 6851 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
mbed_official 363:12a245e5c745 6852 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
mbed_official 363:12a245e5c745 6853 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
mbed_official 363:12a245e5c745 6854 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
mbed_official 363:12a245e5c745 6855 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
mbed_official 363:12a245e5c745 6856 uint8_t RESERVED_5[4];
mbed_official 363:12a245e5c745 6857 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
mbed_official 363:12a245e5c745 6858 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
mbed_official 363:12a245e5c745 6859 uint8_t RESERVED_6[4];
mbed_official 363:12a245e5c745 6860 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
mbed_official 363:12a245e5c745 6861 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
mbed_official 363:12a245e5c745 6862 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
mbed_official 363:12a245e5c745 6863 uint8_t RESERVED_7[156];
mbed_official 363:12a245e5c745 6864 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
mbed_official 363:12a245e5c745 6865 __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
mbed_official 363:12a245e5c745 6866 } SIM_Type, *SIM_MemMapPtr;
mbed_official 363:12a245e5c745 6867
mbed_official 363:12a245e5c745 6868 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6869 -- SIM - Register accessor macros
mbed_official 363:12a245e5c745 6870 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6871
mbed_official 363:12a245e5c745 6872 /*!
mbed_official 363:12a245e5c745 6873 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
mbed_official 363:12a245e5c745 6874 * @{
mbed_official 363:12a245e5c745 6875 */
mbed_official 363:12a245e5c745 6876
mbed_official 363:12a245e5c745 6877
mbed_official 363:12a245e5c745 6878 /* SIM - Register accessors */
mbed_official 363:12a245e5c745 6879 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
mbed_official 363:12a245e5c745 6880 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
mbed_official 363:12a245e5c745 6881 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
mbed_official 363:12a245e5c745 6882 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
mbed_official 363:12a245e5c745 6883 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
mbed_official 363:12a245e5c745 6884 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
mbed_official 363:12a245e5c745 6885 #define SIM_SDID_REG(base) ((base)->SDID)
mbed_official 363:12a245e5c745 6886 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
mbed_official 363:12a245e5c745 6887 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
mbed_official 363:12a245e5c745 6888 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
mbed_official 363:12a245e5c745 6889 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
mbed_official 363:12a245e5c745 6890 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
mbed_official 363:12a245e5c745 6891 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
mbed_official 363:12a245e5c745 6892 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
mbed_official 363:12a245e5c745 6893 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
mbed_official 363:12a245e5c745 6894 #define SIM_UIDML_REG(base) ((base)->UIDML)
mbed_official 363:12a245e5c745 6895 #define SIM_UIDL_REG(base) ((base)->UIDL)
mbed_official 363:12a245e5c745 6896 #define SIM_COPC_REG(base) ((base)->COPC)
mbed_official 363:12a245e5c745 6897 #define SIM_SRVCOP_REG(base) ((base)->SRVCOP)
mbed_official 363:12a245e5c745 6898
mbed_official 363:12a245e5c745 6899 /*!
mbed_official 363:12a245e5c745 6900 * @}
mbed_official 363:12a245e5c745 6901 */ /* end of group SIM_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 6902
mbed_official 363:12a245e5c745 6903
mbed_official 363:12a245e5c745 6904 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 6905 -- SIM Register Masks
mbed_official 363:12a245e5c745 6906 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 6907
mbed_official 363:12a245e5c745 6908 /*!
mbed_official 363:12a245e5c745 6909 * @addtogroup SIM_Register_Masks SIM Register Masks
mbed_official 363:12a245e5c745 6910 * @{
mbed_official 363:12a245e5c745 6911 */
mbed_official 363:12a245e5c745 6912
mbed_official 363:12a245e5c745 6913 /* SOPT1 Bit Fields */
mbed_official 363:12a245e5c745 6914 #define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
mbed_official 363:12a245e5c745 6915 #define SIM_SOPT1_OSC32KOUT_SHIFT 16
mbed_official 363:12a245e5c745 6916 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
mbed_official 363:12a245e5c745 6917 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
mbed_official 363:12a245e5c745 6918 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
mbed_official 363:12a245e5c745 6919 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
mbed_official 363:12a245e5c745 6920 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
mbed_official 363:12a245e5c745 6921 #define SIM_SOPT1_USBVSTBY_SHIFT 29
mbed_official 363:12a245e5c745 6922 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
mbed_official 363:12a245e5c745 6923 #define SIM_SOPT1_USBSSTBY_SHIFT 30
mbed_official 363:12a245e5c745 6924 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
mbed_official 363:12a245e5c745 6925 #define SIM_SOPT1_USBREGEN_SHIFT 31
mbed_official 363:12a245e5c745 6926 /* SOPT1CFG Bit Fields */
mbed_official 363:12a245e5c745 6927 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
mbed_official 363:12a245e5c745 6928 #define SIM_SOPT1CFG_URWE_SHIFT 24
mbed_official 363:12a245e5c745 6929 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
mbed_official 363:12a245e5c745 6930 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
mbed_official 363:12a245e5c745 6931 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
mbed_official 363:12a245e5c745 6932 #define SIM_SOPT1CFG_USSWE_SHIFT 26
mbed_official 363:12a245e5c745 6933 /* SOPT2 Bit Fields */
mbed_official 363:12a245e5c745 6934 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
mbed_official 363:12a245e5c745 6935 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
mbed_official 363:12a245e5c745 6936 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
mbed_official 363:12a245e5c745 6937 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
mbed_official 363:12a245e5c745 6938 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
mbed_official 363:12a245e5c745 6939 #define SIM_SOPT2_USBSRC_MASK 0x40000u
mbed_official 363:12a245e5c745 6940 #define SIM_SOPT2_USBSRC_SHIFT 18
mbed_official 363:12a245e5c745 6941 #define SIM_SOPT2_FLEXIOSRC_MASK 0xC00000u
mbed_official 363:12a245e5c745 6942 #define SIM_SOPT2_FLEXIOSRC_SHIFT 22
mbed_official 363:12a245e5c745 6943 #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FLEXIOSRC_SHIFT))&SIM_SOPT2_FLEXIOSRC_MASK)
mbed_official 363:12a245e5c745 6944 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
mbed_official 363:12a245e5c745 6945 #define SIM_SOPT2_TPMSRC_SHIFT 24
mbed_official 363:12a245e5c745 6946 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
mbed_official 363:12a245e5c745 6947 #define SIM_SOPT2_LPUART0SRC_MASK 0xC000000u
mbed_official 363:12a245e5c745 6948 #define SIM_SOPT2_LPUART0SRC_SHIFT 26
mbed_official 363:12a245e5c745 6949 #define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART0SRC_SHIFT))&SIM_SOPT2_LPUART0SRC_MASK)
mbed_official 363:12a245e5c745 6950 #define SIM_SOPT2_LPUART1SRC_MASK 0x30000000u
mbed_official 363:12a245e5c745 6951 #define SIM_SOPT2_LPUART1SRC_SHIFT 28
mbed_official 363:12a245e5c745 6952 #define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART1SRC_SHIFT))&SIM_SOPT2_LPUART1SRC_MASK)
mbed_official 363:12a245e5c745 6953 /* SOPT4 Bit Fields */
mbed_official 363:12a245e5c745 6954 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
mbed_official 363:12a245e5c745 6955 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
mbed_official 363:12a245e5c745 6956 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
mbed_official 363:12a245e5c745 6957 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
mbed_official 363:12a245e5c745 6958 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
mbed_official 363:12a245e5c745 6959 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
mbed_official 363:12a245e5c745 6960 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
mbed_official 363:12a245e5c745 6961 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
mbed_official 363:12a245e5c745 6962 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
mbed_official 363:12a245e5c745 6963 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
mbed_official 363:12a245e5c745 6964 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
mbed_official 363:12a245e5c745 6965 /* SOPT5 Bit Fields */
mbed_official 363:12a245e5c745 6966 #define SIM_SOPT5_LPUART0TXSRC_MASK 0x3u
mbed_official 363:12a245e5c745 6967 #define SIM_SOPT5_LPUART0TXSRC_SHIFT 0
mbed_official 363:12a245e5c745 6968 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0TXSRC_SHIFT))&SIM_SOPT5_LPUART0TXSRC_MASK)
mbed_official 363:12a245e5c745 6969 #define SIM_SOPT5_LPUART0RXSRC_MASK 0x4u
mbed_official 363:12a245e5c745 6970 #define SIM_SOPT5_LPUART0RXSRC_SHIFT 2
mbed_official 363:12a245e5c745 6971 #define SIM_SOPT5_LPUART1TXSRC_MASK 0x30u
mbed_official 363:12a245e5c745 6972 #define SIM_SOPT5_LPUART1TXSRC_SHIFT 4
mbed_official 363:12a245e5c745 6973 #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART1TXSRC_SHIFT))&SIM_SOPT5_LPUART1TXSRC_MASK)
mbed_official 363:12a245e5c745 6974 #define SIM_SOPT5_LPUART1RXSRC_MASK 0x40u
mbed_official 363:12a245e5c745 6975 #define SIM_SOPT5_LPUART1RXSRC_SHIFT 6
mbed_official 363:12a245e5c745 6976 #define SIM_SOPT5_LPUART0ODE_MASK 0x10000u
mbed_official 363:12a245e5c745 6977 #define SIM_SOPT5_LPUART0ODE_SHIFT 16
mbed_official 363:12a245e5c745 6978 #define SIM_SOPT5_LPUART1ODE_MASK 0x20000u
mbed_official 363:12a245e5c745 6979 #define SIM_SOPT5_LPUART1ODE_SHIFT 17
mbed_official 363:12a245e5c745 6980 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
mbed_official 363:12a245e5c745 6981 #define SIM_SOPT5_UART2ODE_SHIFT 18
mbed_official 363:12a245e5c745 6982 /* SOPT7 Bit Fields */
mbed_official 363:12a245e5c745 6983 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
mbed_official 363:12a245e5c745 6984 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
mbed_official 363:12a245e5c745 6985 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
mbed_official 363:12a245e5c745 6986 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
mbed_official 363:12a245e5c745 6987 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
mbed_official 363:12a245e5c745 6988 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
mbed_official 363:12a245e5c745 6989 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
mbed_official 363:12a245e5c745 6990 /* SDID Bit Fields */
mbed_official 363:12a245e5c745 6991 #define SIM_SDID_PINID_MASK 0xFu
mbed_official 363:12a245e5c745 6992 #define SIM_SDID_PINID_SHIFT 0
mbed_official 363:12a245e5c745 6993 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
mbed_official 363:12a245e5c745 6994 #define SIM_SDID_REVID_MASK 0xF000u
mbed_official 363:12a245e5c745 6995 #define SIM_SDID_REVID_SHIFT 12
mbed_official 363:12a245e5c745 6996 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
mbed_official 363:12a245e5c745 6997 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
mbed_official 363:12a245e5c745 6998 #define SIM_SDID_SRAMSIZE_SHIFT 16
mbed_official 363:12a245e5c745 6999 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
mbed_official 363:12a245e5c745 7000 #define SIM_SDID_SERIESID_MASK 0xF00000u
mbed_official 363:12a245e5c745 7001 #define SIM_SDID_SERIESID_SHIFT 20
mbed_official 363:12a245e5c745 7002 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
mbed_official 363:12a245e5c745 7003 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
mbed_official 363:12a245e5c745 7004 #define SIM_SDID_SUBFAMID_SHIFT 24
mbed_official 363:12a245e5c745 7005 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
mbed_official 363:12a245e5c745 7006 #define SIM_SDID_FAMID_MASK 0xF0000000u
mbed_official 363:12a245e5c745 7007 #define SIM_SDID_FAMID_SHIFT 28
mbed_official 363:12a245e5c745 7008 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
mbed_official 363:12a245e5c745 7009 /* SCGC4 Bit Fields */
mbed_official 363:12a245e5c745 7010 #define SIM_SCGC4_I2C0_MASK 0x40u
mbed_official 363:12a245e5c745 7011 #define SIM_SCGC4_I2C0_SHIFT 6
mbed_official 363:12a245e5c745 7012 #define SIM_SCGC4_I2C1_MASK 0x80u
mbed_official 363:12a245e5c745 7013 #define SIM_SCGC4_I2C1_SHIFT 7
mbed_official 363:12a245e5c745 7014 #define SIM_SCGC4_UART2_MASK 0x1000u
mbed_official 363:12a245e5c745 7015 #define SIM_SCGC4_UART2_SHIFT 12
mbed_official 363:12a245e5c745 7016 #define SIM_SCGC4_USBFS_MASK 0x40000u
mbed_official 363:12a245e5c745 7017 #define SIM_SCGC4_USBFS_SHIFT 18
mbed_official 363:12a245e5c745 7018 #define SIM_SCGC4_CMP0_MASK 0x80000u
mbed_official 363:12a245e5c745 7019 #define SIM_SCGC4_CMP0_SHIFT 19
mbed_official 363:12a245e5c745 7020 #define SIM_SCGC4_VREF_MASK 0x100000u
mbed_official 363:12a245e5c745 7021 #define SIM_SCGC4_VREF_SHIFT 20
mbed_official 363:12a245e5c745 7022 #define SIM_SCGC4_SPI0_MASK 0x400000u
mbed_official 363:12a245e5c745 7023 #define SIM_SCGC4_SPI0_SHIFT 22
mbed_official 363:12a245e5c745 7024 #define SIM_SCGC4_SPI1_MASK 0x800000u
mbed_official 363:12a245e5c745 7025 #define SIM_SCGC4_SPI1_SHIFT 23
mbed_official 363:12a245e5c745 7026 /* SCGC5 Bit Fields */
mbed_official 363:12a245e5c745 7027 #define SIM_SCGC5_LPTMR_MASK 0x1u
mbed_official 363:12a245e5c745 7028 #define SIM_SCGC5_LPTMR_SHIFT 0
mbed_official 363:12a245e5c745 7029 #define SIM_SCGC5_PORTA_MASK 0x200u
mbed_official 363:12a245e5c745 7030 #define SIM_SCGC5_PORTA_SHIFT 9
mbed_official 363:12a245e5c745 7031 #define SIM_SCGC5_PORTB_MASK 0x400u
mbed_official 363:12a245e5c745 7032 #define SIM_SCGC5_PORTB_SHIFT 10
mbed_official 363:12a245e5c745 7033 #define SIM_SCGC5_PORTC_MASK 0x800u
mbed_official 363:12a245e5c745 7034 #define SIM_SCGC5_PORTC_SHIFT 11
mbed_official 363:12a245e5c745 7035 #define SIM_SCGC5_PORTD_MASK 0x1000u
mbed_official 363:12a245e5c745 7036 #define SIM_SCGC5_PORTD_SHIFT 12
mbed_official 363:12a245e5c745 7037 #define SIM_SCGC5_PORTE_MASK 0x2000u
mbed_official 363:12a245e5c745 7038 #define SIM_SCGC5_PORTE_SHIFT 13
mbed_official 363:12a245e5c745 7039 #define SIM_SCGC5_SLCD_MASK 0x80000u
mbed_official 363:12a245e5c745 7040 #define SIM_SCGC5_SLCD_SHIFT 19
mbed_official 363:12a245e5c745 7041 #define SIM_SCGC5_LPUART0_MASK 0x100000u
mbed_official 363:12a245e5c745 7042 #define SIM_SCGC5_LPUART0_SHIFT 20
mbed_official 363:12a245e5c745 7043 #define SIM_SCGC5_LPUART1_MASK 0x200000u
mbed_official 363:12a245e5c745 7044 #define SIM_SCGC5_LPUART1_SHIFT 21
mbed_official 363:12a245e5c745 7045 #define SIM_SCGC5_FLEXIO_MASK 0x80000000u
mbed_official 363:12a245e5c745 7046 #define SIM_SCGC5_FLEXIO_SHIFT 31
mbed_official 363:12a245e5c745 7047 /* SCGC6 Bit Fields */
mbed_official 363:12a245e5c745 7048 #define SIM_SCGC6_FTF_MASK 0x1u
mbed_official 363:12a245e5c745 7049 #define SIM_SCGC6_FTF_SHIFT 0
mbed_official 363:12a245e5c745 7050 #define SIM_SCGC6_DMAMUX_MASK 0x2u
mbed_official 363:12a245e5c745 7051 #define SIM_SCGC6_DMAMUX_SHIFT 1
mbed_official 363:12a245e5c745 7052 #define SIM_SCGC6_I2S_MASK 0x8000u
mbed_official 363:12a245e5c745 7053 #define SIM_SCGC6_I2S_SHIFT 15
mbed_official 363:12a245e5c745 7054 #define SIM_SCGC6_PIT_MASK 0x800000u
mbed_official 363:12a245e5c745 7055 #define SIM_SCGC6_PIT_SHIFT 23
mbed_official 363:12a245e5c745 7056 #define SIM_SCGC6_TPM0_MASK 0x1000000u
mbed_official 363:12a245e5c745 7057 #define SIM_SCGC6_TPM0_SHIFT 24
mbed_official 363:12a245e5c745 7058 #define SIM_SCGC6_TPM1_MASK 0x2000000u
mbed_official 363:12a245e5c745 7059 #define SIM_SCGC6_TPM1_SHIFT 25
mbed_official 363:12a245e5c745 7060 #define SIM_SCGC6_TPM2_MASK 0x4000000u
mbed_official 363:12a245e5c745 7061 #define SIM_SCGC6_TPM2_SHIFT 26
mbed_official 363:12a245e5c745 7062 #define SIM_SCGC6_ADC0_MASK 0x8000000u
mbed_official 363:12a245e5c745 7063 #define SIM_SCGC6_ADC0_SHIFT 27
mbed_official 363:12a245e5c745 7064 #define SIM_SCGC6_RTC_MASK 0x20000000u
mbed_official 363:12a245e5c745 7065 #define SIM_SCGC6_RTC_SHIFT 29
mbed_official 363:12a245e5c745 7066 #define SIM_SCGC6_DAC0_MASK 0x80000000u
mbed_official 363:12a245e5c745 7067 #define SIM_SCGC6_DAC0_SHIFT 31
mbed_official 363:12a245e5c745 7068 /* SCGC7 Bit Fields */
mbed_official 363:12a245e5c745 7069 #define SIM_SCGC7_DMA_MASK 0x100u
mbed_official 363:12a245e5c745 7070 #define SIM_SCGC7_DMA_SHIFT 8
mbed_official 363:12a245e5c745 7071 /* CLKDIV1 Bit Fields */
mbed_official 363:12a245e5c745 7072 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
mbed_official 363:12a245e5c745 7073 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
mbed_official 363:12a245e5c745 7074 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
mbed_official 363:12a245e5c745 7075 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
mbed_official 363:12a245e5c745 7076 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
mbed_official 363:12a245e5c745 7077 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
mbed_official 363:12a245e5c745 7078 /* FCFG1 Bit Fields */
mbed_official 363:12a245e5c745 7079 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
mbed_official 363:12a245e5c745 7080 #define SIM_FCFG1_FLASHDIS_SHIFT 0
mbed_official 363:12a245e5c745 7081 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
mbed_official 363:12a245e5c745 7082 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
mbed_official 363:12a245e5c745 7083 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
mbed_official 363:12a245e5c745 7084 #define SIM_FCFG1_PFSIZE_SHIFT 24
mbed_official 363:12a245e5c745 7085 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
mbed_official 363:12a245e5c745 7086 /* FCFG2 Bit Fields */
mbed_official 363:12a245e5c745 7087 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
mbed_official 363:12a245e5c745 7088 #define SIM_FCFG2_MAXADDR1_SHIFT 16
mbed_official 363:12a245e5c745 7089 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
mbed_official 363:12a245e5c745 7090 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
mbed_official 363:12a245e5c745 7091 #define SIM_FCFG2_MAXADDR0_SHIFT 24
mbed_official 363:12a245e5c745 7092 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
mbed_official 363:12a245e5c745 7093 /* UIDMH Bit Fields */
mbed_official 363:12a245e5c745 7094 #define SIM_UIDMH_UID_MASK 0xFFFFu
mbed_official 363:12a245e5c745 7095 #define SIM_UIDMH_UID_SHIFT 0
mbed_official 363:12a245e5c745 7096 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
mbed_official 363:12a245e5c745 7097 /* UIDML Bit Fields */
mbed_official 363:12a245e5c745 7098 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 7099 #define SIM_UIDML_UID_SHIFT 0
mbed_official 363:12a245e5c745 7100 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
mbed_official 363:12a245e5c745 7101 /* UIDL Bit Fields */
mbed_official 363:12a245e5c745 7102 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
mbed_official 363:12a245e5c745 7103 #define SIM_UIDL_UID_SHIFT 0
mbed_official 363:12a245e5c745 7104 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
mbed_official 363:12a245e5c745 7105 /* COPC Bit Fields */
mbed_official 363:12a245e5c745 7106 #define SIM_COPC_COPW_MASK 0x1u
mbed_official 363:12a245e5c745 7107 #define SIM_COPC_COPW_SHIFT 0
mbed_official 363:12a245e5c745 7108 #define SIM_COPC_COPCLKS_MASK 0x2u
mbed_official 363:12a245e5c745 7109 #define SIM_COPC_COPCLKS_SHIFT 1
mbed_official 363:12a245e5c745 7110 #define SIM_COPC_COPT_MASK 0xCu
mbed_official 363:12a245e5c745 7111 #define SIM_COPC_COPT_SHIFT 2
mbed_official 363:12a245e5c745 7112 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
mbed_official 363:12a245e5c745 7113 #define SIM_COPC_COPSTPEN_MASK 0x10u
mbed_official 363:12a245e5c745 7114 #define SIM_COPC_COPSTPEN_SHIFT 4
mbed_official 363:12a245e5c745 7115 #define SIM_COPC_COPDBGEN_MASK 0x20u
mbed_official 363:12a245e5c745 7116 #define SIM_COPC_COPDBGEN_SHIFT 5
mbed_official 363:12a245e5c745 7117 #define SIM_COPC_COPCLKSEL_MASK 0xC0u
mbed_official 363:12a245e5c745 7118 #define SIM_COPC_COPCLKSEL_SHIFT 6
mbed_official 363:12a245e5c745 7119 #define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPCLKSEL_SHIFT))&SIM_COPC_COPCLKSEL_MASK)
mbed_official 363:12a245e5c745 7120 /* SRVCOP Bit Fields */
mbed_official 363:12a245e5c745 7121 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
mbed_official 363:12a245e5c745 7122 #define SIM_SRVCOP_SRVCOP_SHIFT 0
mbed_official 363:12a245e5c745 7123 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
mbed_official 363:12a245e5c745 7124
mbed_official 363:12a245e5c745 7125 /*!
mbed_official 363:12a245e5c745 7126 * @}
mbed_official 363:12a245e5c745 7127 */ /* end of group SIM_Register_Masks */
mbed_official 363:12a245e5c745 7128
mbed_official 363:12a245e5c745 7129
mbed_official 363:12a245e5c745 7130 /* SIM - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 7131 /** Peripheral SIM base address */
mbed_official 363:12a245e5c745 7132 #define SIM_BASE (0x40047000u)
mbed_official 363:12a245e5c745 7133 /** Peripheral SIM base pointer */
mbed_official 363:12a245e5c745 7134 #define SIM ((SIM_Type *)SIM_BASE)
mbed_official 363:12a245e5c745 7135 #define SIM_BASE_PTR (SIM)
mbed_official 363:12a245e5c745 7136 /** Array initializer of SIM peripheral base addresses */
mbed_official 363:12a245e5c745 7137 #define SIM_BASE_ADDRS { SIM_BASE }
mbed_official 363:12a245e5c745 7138 /** Array initializer of SIM peripheral base pointers */
mbed_official 363:12a245e5c745 7139 #define SIM_BASE_PTRS { SIM }
mbed_official 363:12a245e5c745 7140
mbed_official 363:12a245e5c745 7141 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7142 -- SIM - Register accessor macros
mbed_official 363:12a245e5c745 7143 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7144
mbed_official 363:12a245e5c745 7145 /*!
mbed_official 363:12a245e5c745 7146 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
mbed_official 363:12a245e5c745 7147 * @{
mbed_official 363:12a245e5c745 7148 */
mbed_official 363:12a245e5c745 7149
mbed_official 363:12a245e5c745 7150
mbed_official 363:12a245e5c745 7151 /* SIM - Register instance definitions */
mbed_official 363:12a245e5c745 7152 /* SIM */
mbed_official 363:12a245e5c745 7153 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
mbed_official 363:12a245e5c745 7154 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
mbed_official 363:12a245e5c745 7155 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
mbed_official 363:12a245e5c745 7156 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
mbed_official 363:12a245e5c745 7157 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
mbed_official 363:12a245e5c745 7158 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
mbed_official 363:12a245e5c745 7159 #define SIM_SDID SIM_SDID_REG(SIM)
mbed_official 363:12a245e5c745 7160 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
mbed_official 363:12a245e5c745 7161 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
mbed_official 363:12a245e5c745 7162 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
mbed_official 363:12a245e5c745 7163 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
mbed_official 363:12a245e5c745 7164 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
mbed_official 363:12a245e5c745 7165 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
mbed_official 363:12a245e5c745 7166 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
mbed_official 363:12a245e5c745 7167 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
mbed_official 363:12a245e5c745 7168 #define SIM_UIDML SIM_UIDML_REG(SIM)
mbed_official 363:12a245e5c745 7169 #define SIM_UIDL SIM_UIDL_REG(SIM)
mbed_official 363:12a245e5c745 7170 #define SIM_COPC SIM_COPC_REG(SIM)
mbed_official 363:12a245e5c745 7171 #define SIM_SRVCOP SIM_SRVCOP_REG(SIM)
mbed_official 363:12a245e5c745 7172
mbed_official 363:12a245e5c745 7173 /*!
mbed_official 363:12a245e5c745 7174 * @}
mbed_official 363:12a245e5c745 7175 */ /* end of group SIM_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 7176
mbed_official 363:12a245e5c745 7177
mbed_official 363:12a245e5c745 7178 /*!
mbed_official 363:12a245e5c745 7179 * @}
mbed_official 363:12a245e5c745 7180 */ /* end of group SIM_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 7181
mbed_official 363:12a245e5c745 7182
mbed_official 363:12a245e5c745 7183 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7184 -- SMC Peripheral Access Layer
mbed_official 363:12a245e5c745 7185 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7186
mbed_official 363:12a245e5c745 7187 /*!
mbed_official 363:12a245e5c745 7188 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
mbed_official 363:12a245e5c745 7189 * @{
mbed_official 363:12a245e5c745 7190 */
mbed_official 363:12a245e5c745 7191
mbed_official 363:12a245e5c745 7192 /** SMC - Register Layout Typedef */
mbed_official 363:12a245e5c745 7193 typedef struct {
mbed_official 363:12a245e5c745 7194 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
mbed_official 363:12a245e5c745 7195 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
mbed_official 363:12a245e5c745 7196 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
mbed_official 363:12a245e5c745 7197 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
mbed_official 363:12a245e5c745 7198 } SMC_Type, *SMC_MemMapPtr;
mbed_official 363:12a245e5c745 7199
mbed_official 363:12a245e5c745 7200 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7201 -- SMC - Register accessor macros
mbed_official 363:12a245e5c745 7202 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7203
mbed_official 363:12a245e5c745 7204 /*!
mbed_official 363:12a245e5c745 7205 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
mbed_official 363:12a245e5c745 7206 * @{
mbed_official 363:12a245e5c745 7207 */
mbed_official 363:12a245e5c745 7208
mbed_official 363:12a245e5c745 7209
mbed_official 363:12a245e5c745 7210 /* SMC - Register accessors */
mbed_official 363:12a245e5c745 7211 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
mbed_official 363:12a245e5c745 7212 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
mbed_official 363:12a245e5c745 7213 #define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
mbed_official 363:12a245e5c745 7214 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
mbed_official 363:12a245e5c745 7215
mbed_official 363:12a245e5c745 7216 /*!
mbed_official 363:12a245e5c745 7217 * @}
mbed_official 363:12a245e5c745 7218 */ /* end of group SMC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 7219
mbed_official 363:12a245e5c745 7220
mbed_official 363:12a245e5c745 7221 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7222 -- SMC Register Masks
mbed_official 363:12a245e5c745 7223 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7224
mbed_official 363:12a245e5c745 7225 /*!
mbed_official 363:12a245e5c745 7226 * @addtogroup SMC_Register_Masks SMC Register Masks
mbed_official 363:12a245e5c745 7227 * @{
mbed_official 363:12a245e5c745 7228 */
mbed_official 363:12a245e5c745 7229
mbed_official 363:12a245e5c745 7230 /* PMPROT Bit Fields */
mbed_official 363:12a245e5c745 7231 #define SMC_PMPROT_AVLLS_MASK 0x2u
mbed_official 363:12a245e5c745 7232 #define SMC_PMPROT_AVLLS_SHIFT 1
mbed_official 363:12a245e5c745 7233 #define SMC_PMPROT_ALLS_MASK 0x8u
mbed_official 363:12a245e5c745 7234 #define SMC_PMPROT_ALLS_SHIFT 3
mbed_official 363:12a245e5c745 7235 #define SMC_PMPROT_AVLP_MASK 0x20u
mbed_official 363:12a245e5c745 7236 #define SMC_PMPROT_AVLP_SHIFT 5
mbed_official 363:12a245e5c745 7237 /* PMCTRL Bit Fields */
mbed_official 363:12a245e5c745 7238 #define SMC_PMCTRL_STOPM_MASK 0x7u
mbed_official 363:12a245e5c745 7239 #define SMC_PMCTRL_STOPM_SHIFT 0
mbed_official 363:12a245e5c745 7240 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
mbed_official 363:12a245e5c745 7241 #define SMC_PMCTRL_STOPA_MASK 0x8u
mbed_official 363:12a245e5c745 7242 #define SMC_PMCTRL_STOPA_SHIFT 3
mbed_official 363:12a245e5c745 7243 #define SMC_PMCTRL_RUNM_MASK 0x60u
mbed_official 363:12a245e5c745 7244 #define SMC_PMCTRL_RUNM_SHIFT 5
mbed_official 363:12a245e5c745 7245 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
mbed_official 363:12a245e5c745 7246 /* STOPCTRL Bit Fields */
mbed_official 363:12a245e5c745 7247 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
mbed_official 363:12a245e5c745 7248 #define SMC_STOPCTRL_VLLSM_SHIFT 0
mbed_official 363:12a245e5c745 7249 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
mbed_official 363:12a245e5c745 7250 #define SMC_STOPCTRL_PORPO_MASK 0x20u
mbed_official 363:12a245e5c745 7251 #define SMC_STOPCTRL_PORPO_SHIFT 5
mbed_official 363:12a245e5c745 7252 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
mbed_official 363:12a245e5c745 7253 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
mbed_official 363:12a245e5c745 7254 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
mbed_official 363:12a245e5c745 7255 /* PMSTAT Bit Fields */
mbed_official 363:12a245e5c745 7256 #define SMC_PMSTAT_PMSTAT_MASK 0xFFu
mbed_official 363:12a245e5c745 7257 #define SMC_PMSTAT_PMSTAT_SHIFT 0
mbed_official 363:12a245e5c745 7258 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
mbed_official 363:12a245e5c745 7259
mbed_official 363:12a245e5c745 7260 /*!
mbed_official 363:12a245e5c745 7261 * @}
mbed_official 363:12a245e5c745 7262 */ /* end of group SMC_Register_Masks */
mbed_official 363:12a245e5c745 7263
mbed_official 363:12a245e5c745 7264
mbed_official 363:12a245e5c745 7265 /* SMC - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 7266 /** Peripheral SMC base address */
mbed_official 363:12a245e5c745 7267 #define SMC_BASE (0x4007E000u)
mbed_official 363:12a245e5c745 7268 /** Peripheral SMC base pointer */
mbed_official 363:12a245e5c745 7269 #define SMC ((SMC_Type *)SMC_BASE)
mbed_official 363:12a245e5c745 7270 #define SMC_BASE_PTR (SMC)
mbed_official 363:12a245e5c745 7271 /** Array initializer of SMC peripheral base addresses */
mbed_official 363:12a245e5c745 7272 #define SMC_BASE_ADDRS { SMC_BASE }
mbed_official 363:12a245e5c745 7273 /** Array initializer of SMC peripheral base pointers */
mbed_official 363:12a245e5c745 7274 #define SMC_BASE_PTRS { SMC }
mbed_official 363:12a245e5c745 7275
mbed_official 363:12a245e5c745 7276 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7277 -- SMC - Register accessor macros
mbed_official 363:12a245e5c745 7278 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7279
mbed_official 363:12a245e5c745 7280 /*!
mbed_official 363:12a245e5c745 7281 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
mbed_official 363:12a245e5c745 7282 * @{
mbed_official 363:12a245e5c745 7283 */
mbed_official 363:12a245e5c745 7284
mbed_official 363:12a245e5c745 7285
mbed_official 363:12a245e5c745 7286 /* SMC - Register instance definitions */
mbed_official 363:12a245e5c745 7287 /* SMC */
mbed_official 363:12a245e5c745 7288 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
mbed_official 363:12a245e5c745 7289 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
mbed_official 363:12a245e5c745 7290 #define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
mbed_official 363:12a245e5c745 7291 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
mbed_official 363:12a245e5c745 7292
mbed_official 363:12a245e5c745 7293 /*!
mbed_official 363:12a245e5c745 7294 * @}
mbed_official 363:12a245e5c745 7295 */ /* end of group SMC_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 7296
mbed_official 363:12a245e5c745 7297
mbed_official 363:12a245e5c745 7298 /*!
mbed_official 363:12a245e5c745 7299 * @}
mbed_official 363:12a245e5c745 7300 */ /* end of group SMC_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 7301
mbed_official 363:12a245e5c745 7302
mbed_official 363:12a245e5c745 7303 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7304 -- SPI Peripheral Access Layer
mbed_official 363:12a245e5c745 7305 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7306
mbed_official 363:12a245e5c745 7307 /*!
mbed_official 363:12a245e5c745 7308 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
mbed_official 363:12a245e5c745 7309 * @{
mbed_official 363:12a245e5c745 7310 */
mbed_official 363:12a245e5c745 7311
mbed_official 363:12a245e5c745 7312 /** SPI - Register Layout Typedef */
mbed_official 363:12a245e5c745 7313 typedef struct {
mbed_official 363:12a245e5c745 7314 __I uint8_t S; /**< SPI Status Register, offset: 0x0 */
mbed_official 363:12a245e5c745 7315 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
mbed_official 363:12a245e5c745 7316 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
mbed_official 363:12a245e5c745 7317 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
mbed_official 363:12a245e5c745 7318 __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
mbed_official 363:12a245e5c745 7319 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
mbed_official 363:12a245e5c745 7320 __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
mbed_official 363:12a245e5c745 7321 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
mbed_official 363:12a245e5c745 7322 uint8_t RESERVED_0[2];
mbed_official 363:12a245e5c745 7323 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
mbed_official 363:12a245e5c745 7324 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
mbed_official 363:12a245e5c745 7325 } SPI_Type, *SPI_MemMapPtr;
mbed_official 363:12a245e5c745 7326
mbed_official 363:12a245e5c745 7327 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7328 -- SPI - Register accessor macros
mbed_official 363:12a245e5c745 7329 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7330
mbed_official 363:12a245e5c745 7331 /*!
mbed_official 363:12a245e5c745 7332 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
mbed_official 363:12a245e5c745 7333 * @{
mbed_official 363:12a245e5c745 7334 */
mbed_official 363:12a245e5c745 7335
mbed_official 363:12a245e5c745 7336
mbed_official 363:12a245e5c745 7337 /* SPI - Register accessors */
mbed_official 363:12a245e5c745 7338 #define SPI_S_REG(base) ((base)->S)
mbed_official 363:12a245e5c745 7339 #define SPI_BR_REG(base) ((base)->BR)
mbed_official 363:12a245e5c745 7340 #define SPI_C2_REG(base) ((base)->C2)
mbed_official 363:12a245e5c745 7341 #define SPI_C1_REG(base) ((base)->C1)
mbed_official 363:12a245e5c745 7342 #define SPI_ML_REG(base) ((base)->ML)
mbed_official 363:12a245e5c745 7343 #define SPI_MH_REG(base) ((base)->MH)
mbed_official 363:12a245e5c745 7344 #define SPI_DL_REG(base) ((base)->DL)
mbed_official 363:12a245e5c745 7345 #define SPI_DH_REG(base) ((base)->DH)
mbed_official 363:12a245e5c745 7346 #define SPI_CI_REG(base) ((base)->CI)
mbed_official 363:12a245e5c745 7347 #define SPI_C3_REG(base) ((base)->C3)
mbed_official 363:12a245e5c745 7348
mbed_official 363:12a245e5c745 7349 /*!
mbed_official 363:12a245e5c745 7350 * @}
mbed_official 363:12a245e5c745 7351 */ /* end of group SPI_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 7352
mbed_official 363:12a245e5c745 7353
mbed_official 363:12a245e5c745 7354 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7355 -- SPI Register Masks
mbed_official 363:12a245e5c745 7356 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7357
mbed_official 363:12a245e5c745 7358 /*!
mbed_official 363:12a245e5c745 7359 * @addtogroup SPI_Register_Masks SPI Register Masks
mbed_official 363:12a245e5c745 7360 * @{
mbed_official 363:12a245e5c745 7361 */
mbed_official 363:12a245e5c745 7362
mbed_official 363:12a245e5c745 7363 /* S Bit Fields */
mbed_official 363:12a245e5c745 7364 #define SPI_S_RFIFOEF_MASK 0x1u
mbed_official 363:12a245e5c745 7365 #define SPI_S_RFIFOEF_SHIFT 0
mbed_official 363:12a245e5c745 7366 #define SPI_S_TXFULLF_MASK 0x2u
mbed_official 363:12a245e5c745 7367 #define SPI_S_TXFULLF_SHIFT 1
mbed_official 363:12a245e5c745 7368 #define SPI_S_TNEAREF_MASK 0x4u
mbed_official 363:12a245e5c745 7369 #define SPI_S_TNEAREF_SHIFT 2
mbed_official 363:12a245e5c745 7370 #define SPI_S_RNFULLF_MASK 0x8u
mbed_official 363:12a245e5c745 7371 #define SPI_S_RNFULLF_SHIFT 3
mbed_official 363:12a245e5c745 7372 #define SPI_S_MODF_MASK 0x10u
mbed_official 363:12a245e5c745 7373 #define SPI_S_MODF_SHIFT 4
mbed_official 363:12a245e5c745 7374 #define SPI_S_SPTEF_MASK 0x20u
mbed_official 363:12a245e5c745 7375 #define SPI_S_SPTEF_SHIFT 5
mbed_official 363:12a245e5c745 7376 #define SPI_S_SPMF_MASK 0x40u
mbed_official 363:12a245e5c745 7377 #define SPI_S_SPMF_SHIFT 6
mbed_official 363:12a245e5c745 7378 #define SPI_S_SPRF_MASK 0x80u
mbed_official 363:12a245e5c745 7379 #define SPI_S_SPRF_SHIFT 7
mbed_official 363:12a245e5c745 7380 /* BR Bit Fields */
mbed_official 363:12a245e5c745 7381 #define SPI_BR_SPR_MASK 0xFu
mbed_official 363:12a245e5c745 7382 #define SPI_BR_SPR_SHIFT 0
mbed_official 363:12a245e5c745 7383 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
mbed_official 363:12a245e5c745 7384 #define SPI_BR_SPPR_MASK 0x70u
mbed_official 363:12a245e5c745 7385 #define SPI_BR_SPPR_SHIFT 4
mbed_official 363:12a245e5c745 7386 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
mbed_official 363:12a245e5c745 7387 /* C2 Bit Fields */
mbed_official 363:12a245e5c745 7388 #define SPI_C2_SPC0_MASK 0x1u
mbed_official 363:12a245e5c745 7389 #define SPI_C2_SPC0_SHIFT 0
mbed_official 363:12a245e5c745 7390 #define SPI_C2_SPISWAI_MASK 0x2u
mbed_official 363:12a245e5c745 7391 #define SPI_C2_SPISWAI_SHIFT 1
mbed_official 363:12a245e5c745 7392 #define SPI_C2_RXDMAE_MASK 0x4u
mbed_official 363:12a245e5c745 7393 #define SPI_C2_RXDMAE_SHIFT 2
mbed_official 363:12a245e5c745 7394 #define SPI_C2_BIDIROE_MASK 0x8u
mbed_official 363:12a245e5c745 7395 #define SPI_C2_BIDIROE_SHIFT 3
mbed_official 363:12a245e5c745 7396 #define SPI_C2_MODFEN_MASK 0x10u
mbed_official 363:12a245e5c745 7397 #define SPI_C2_MODFEN_SHIFT 4
mbed_official 363:12a245e5c745 7398 #define SPI_C2_TXDMAE_MASK 0x20u
mbed_official 363:12a245e5c745 7399 #define SPI_C2_TXDMAE_SHIFT 5
mbed_official 363:12a245e5c745 7400 #define SPI_C2_SPIMODE_MASK 0x40u
mbed_official 363:12a245e5c745 7401 #define SPI_C2_SPIMODE_SHIFT 6
mbed_official 363:12a245e5c745 7402 #define SPI_C2_SPMIE_MASK 0x80u
mbed_official 363:12a245e5c745 7403 #define SPI_C2_SPMIE_SHIFT 7
mbed_official 363:12a245e5c745 7404 /* C1 Bit Fields */
mbed_official 363:12a245e5c745 7405 #define SPI_C1_LSBFE_MASK 0x1u
mbed_official 363:12a245e5c745 7406 #define SPI_C1_LSBFE_SHIFT 0
mbed_official 363:12a245e5c745 7407 #define SPI_C1_SSOE_MASK 0x2u
mbed_official 363:12a245e5c745 7408 #define SPI_C1_SSOE_SHIFT 1
mbed_official 363:12a245e5c745 7409 #define SPI_C1_CPHA_MASK 0x4u
mbed_official 363:12a245e5c745 7410 #define SPI_C1_CPHA_SHIFT 2
mbed_official 363:12a245e5c745 7411 #define SPI_C1_CPOL_MASK 0x8u
mbed_official 363:12a245e5c745 7412 #define SPI_C1_CPOL_SHIFT 3
mbed_official 363:12a245e5c745 7413 #define SPI_C1_MSTR_MASK 0x10u
mbed_official 363:12a245e5c745 7414 #define SPI_C1_MSTR_SHIFT 4
mbed_official 363:12a245e5c745 7415 #define SPI_C1_SPTIE_MASK 0x20u
mbed_official 363:12a245e5c745 7416 #define SPI_C1_SPTIE_SHIFT 5
mbed_official 363:12a245e5c745 7417 #define SPI_C1_SPE_MASK 0x40u
mbed_official 363:12a245e5c745 7418 #define SPI_C1_SPE_SHIFT 6
mbed_official 363:12a245e5c745 7419 #define SPI_C1_SPIE_MASK 0x80u
mbed_official 363:12a245e5c745 7420 #define SPI_C1_SPIE_SHIFT 7
mbed_official 363:12a245e5c745 7421 /* ML Bit Fields */
mbed_official 363:12a245e5c745 7422 #define SPI_ML_Bits_MASK 0xFFu
mbed_official 363:12a245e5c745 7423 #define SPI_ML_Bits_SHIFT 0
mbed_official 363:12a245e5c745 7424 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
mbed_official 363:12a245e5c745 7425 /* MH Bit Fields */
mbed_official 363:12a245e5c745 7426 #define SPI_MH_Bits_MASK 0xFFu
mbed_official 363:12a245e5c745 7427 #define SPI_MH_Bits_SHIFT 0
mbed_official 363:12a245e5c745 7428 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
mbed_official 363:12a245e5c745 7429 /* DL Bit Fields */
mbed_official 363:12a245e5c745 7430 #define SPI_DL_Bits_MASK 0xFFu
mbed_official 363:12a245e5c745 7431 #define SPI_DL_Bits_SHIFT 0
mbed_official 363:12a245e5c745 7432 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
mbed_official 363:12a245e5c745 7433 /* DH Bit Fields */
mbed_official 363:12a245e5c745 7434 #define SPI_DH_Bits_MASK 0xFFu
mbed_official 363:12a245e5c745 7435 #define SPI_DH_Bits_SHIFT 0
mbed_official 363:12a245e5c745 7436 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
mbed_official 363:12a245e5c745 7437 /* CI Bit Fields */
mbed_official 363:12a245e5c745 7438 #define SPI_CI_SPRFCI_MASK 0x1u
mbed_official 363:12a245e5c745 7439 #define SPI_CI_SPRFCI_SHIFT 0
mbed_official 363:12a245e5c745 7440 #define SPI_CI_SPTEFCI_MASK 0x2u
mbed_official 363:12a245e5c745 7441 #define SPI_CI_SPTEFCI_SHIFT 1
mbed_official 363:12a245e5c745 7442 #define SPI_CI_RNFULLFCI_MASK 0x4u
mbed_official 363:12a245e5c745 7443 #define SPI_CI_RNFULLFCI_SHIFT 2
mbed_official 363:12a245e5c745 7444 #define SPI_CI_TNEAREFCI_MASK 0x8u
mbed_official 363:12a245e5c745 7445 #define SPI_CI_TNEAREFCI_SHIFT 3
mbed_official 363:12a245e5c745 7446 #define SPI_CI_RXFOF_MASK 0x10u
mbed_official 363:12a245e5c745 7447 #define SPI_CI_RXFOF_SHIFT 4
mbed_official 363:12a245e5c745 7448 #define SPI_CI_TXFOF_MASK 0x20u
mbed_official 363:12a245e5c745 7449 #define SPI_CI_TXFOF_SHIFT 5
mbed_official 363:12a245e5c745 7450 #define SPI_CI_RXFERR_MASK 0x40u
mbed_official 363:12a245e5c745 7451 #define SPI_CI_RXFERR_SHIFT 6
mbed_official 363:12a245e5c745 7452 #define SPI_CI_TXFERR_MASK 0x80u
mbed_official 363:12a245e5c745 7453 #define SPI_CI_TXFERR_SHIFT 7
mbed_official 363:12a245e5c745 7454 /* C3 Bit Fields */
mbed_official 363:12a245e5c745 7455 #define SPI_C3_FIFOMODE_MASK 0x1u
mbed_official 363:12a245e5c745 7456 #define SPI_C3_FIFOMODE_SHIFT 0
mbed_official 363:12a245e5c745 7457 #define SPI_C3_RNFULLIEN_MASK 0x2u
mbed_official 363:12a245e5c745 7458 #define SPI_C3_RNFULLIEN_SHIFT 1
mbed_official 363:12a245e5c745 7459 #define SPI_C3_TNEARIEN_MASK 0x4u
mbed_official 363:12a245e5c745 7460 #define SPI_C3_TNEARIEN_SHIFT 2
mbed_official 363:12a245e5c745 7461 #define SPI_C3_INTCLR_MASK 0x8u
mbed_official 363:12a245e5c745 7462 #define SPI_C3_INTCLR_SHIFT 3
mbed_official 363:12a245e5c745 7463 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
mbed_official 363:12a245e5c745 7464 #define SPI_C3_RNFULLF_MARK_SHIFT 4
mbed_official 363:12a245e5c745 7465 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
mbed_official 363:12a245e5c745 7466 #define SPI_C3_TNEAREF_MARK_SHIFT 5
mbed_official 363:12a245e5c745 7467
mbed_official 363:12a245e5c745 7468 /*!
mbed_official 363:12a245e5c745 7469 * @}
mbed_official 363:12a245e5c745 7470 */ /* end of group SPI_Register_Masks */
mbed_official 363:12a245e5c745 7471
mbed_official 363:12a245e5c745 7472
mbed_official 363:12a245e5c745 7473 /* SPI - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 7474 /** Peripheral SPI0 base address */
mbed_official 363:12a245e5c745 7475 #define SPI0_BASE (0x40076000u)
mbed_official 363:12a245e5c745 7476 /** Peripheral SPI0 base pointer */
mbed_official 363:12a245e5c745 7477 #define SPI0 ((SPI_Type *)SPI0_BASE)
mbed_official 363:12a245e5c745 7478 #define SPI0_BASE_PTR (SPI0)
mbed_official 363:12a245e5c745 7479 /** Peripheral SPI1 base address */
mbed_official 363:12a245e5c745 7480 #define SPI1_BASE (0x40077000u)
mbed_official 363:12a245e5c745 7481 /** Peripheral SPI1 base pointer */
mbed_official 363:12a245e5c745 7482 #define SPI1 ((SPI_Type *)SPI1_BASE)
mbed_official 363:12a245e5c745 7483 #define SPI1_BASE_PTR (SPI1)
mbed_official 363:12a245e5c745 7484 /** Array initializer of SPI peripheral base addresses */
mbed_official 363:12a245e5c745 7485 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
mbed_official 363:12a245e5c745 7486 /** Array initializer of SPI peripheral base pointers */
mbed_official 363:12a245e5c745 7487 #define SPI_BASE_PTRS { SPI0, SPI1 }
mbed_official 363:12a245e5c745 7488 /** Interrupt vectors for the SPI peripheral type */
mbed_official 363:12a245e5c745 7489 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
mbed_official 363:12a245e5c745 7490
mbed_official 363:12a245e5c745 7491 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7492 -- SPI - Register accessor macros
mbed_official 363:12a245e5c745 7493 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7494
mbed_official 363:12a245e5c745 7495 /*!
mbed_official 363:12a245e5c745 7496 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
mbed_official 363:12a245e5c745 7497 * @{
mbed_official 363:12a245e5c745 7498 */
mbed_official 363:12a245e5c745 7499
mbed_official 363:12a245e5c745 7500
mbed_official 363:12a245e5c745 7501 /* SPI - Register instance definitions */
mbed_official 363:12a245e5c745 7502 /* SPI0 */
mbed_official 363:12a245e5c745 7503 #define SPI0_S SPI_S_REG(SPI0)
mbed_official 363:12a245e5c745 7504 #define SPI0_BR SPI_BR_REG(SPI0)
mbed_official 363:12a245e5c745 7505 #define SPI0_C2 SPI_C2_REG(SPI0)
mbed_official 363:12a245e5c745 7506 #define SPI0_C1 SPI_C1_REG(SPI0)
mbed_official 363:12a245e5c745 7507 #define SPI0_ML SPI_ML_REG(SPI0)
mbed_official 363:12a245e5c745 7508 #define SPI0_MH SPI_MH_REG(SPI0)
mbed_official 363:12a245e5c745 7509 #define SPI0_DL SPI_DL_REG(SPI0)
mbed_official 363:12a245e5c745 7510 #define SPI0_DH SPI_DH_REG(SPI0)
mbed_official 363:12a245e5c745 7511 /* SPI1 */
mbed_official 363:12a245e5c745 7512 #define SPI1_S SPI_S_REG(SPI1)
mbed_official 363:12a245e5c745 7513 #define SPI1_BR SPI_BR_REG(SPI1)
mbed_official 363:12a245e5c745 7514 #define SPI1_C2 SPI_C2_REG(SPI1)
mbed_official 363:12a245e5c745 7515 #define SPI1_C1 SPI_C1_REG(SPI1)
mbed_official 363:12a245e5c745 7516 #define SPI1_ML SPI_ML_REG(SPI1)
mbed_official 363:12a245e5c745 7517 #define SPI1_MH SPI_MH_REG(SPI1)
mbed_official 363:12a245e5c745 7518 #define SPI1_DL SPI_DL_REG(SPI1)
mbed_official 363:12a245e5c745 7519 #define SPI1_DH SPI_DH_REG(SPI1)
mbed_official 363:12a245e5c745 7520 #define SPI1_CI SPI_CI_REG(SPI1)
mbed_official 363:12a245e5c745 7521 #define SPI1_C3 SPI_C3_REG(SPI1)
mbed_official 363:12a245e5c745 7522
mbed_official 363:12a245e5c745 7523 /*!
mbed_official 363:12a245e5c745 7524 * @}
mbed_official 363:12a245e5c745 7525 */ /* end of group SPI_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 7526
mbed_official 363:12a245e5c745 7527
mbed_official 363:12a245e5c745 7528 /*!
mbed_official 363:12a245e5c745 7529 * @}
mbed_official 363:12a245e5c745 7530 */ /* end of group SPI_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 7531
mbed_official 363:12a245e5c745 7532
mbed_official 363:12a245e5c745 7533 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7534 -- TPM Peripheral Access Layer
mbed_official 363:12a245e5c745 7535 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7536
mbed_official 363:12a245e5c745 7537 /*!
mbed_official 363:12a245e5c745 7538 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
mbed_official 363:12a245e5c745 7539 * @{
mbed_official 363:12a245e5c745 7540 */
mbed_official 363:12a245e5c745 7541
mbed_official 363:12a245e5c745 7542 /** TPM - Register Layout Typedef */
mbed_official 363:12a245e5c745 7543 typedef struct {
mbed_official 363:12a245e5c745 7544 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
mbed_official 363:12a245e5c745 7545 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
mbed_official 363:12a245e5c745 7546 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
mbed_official 363:12a245e5c745 7547 struct { /* offset: 0xC, array step: 0x8 */
mbed_official 363:12a245e5c745 7548 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
mbed_official 363:12a245e5c745 7549 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
mbed_official 363:12a245e5c745 7550 } CONTROLS[6];
mbed_official 363:12a245e5c745 7551 uint8_t RESERVED_0[20];
mbed_official 363:12a245e5c745 7552 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
mbed_official 363:12a245e5c745 7553 uint8_t RESERVED_1[28];
mbed_official 363:12a245e5c745 7554 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
mbed_official 363:12a245e5c745 7555 uint8_t RESERVED_2[16];
mbed_official 363:12a245e5c745 7556 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
mbed_official 363:12a245e5c745 7557 } TPM_Type, *TPM_MemMapPtr;
mbed_official 363:12a245e5c745 7558
mbed_official 363:12a245e5c745 7559 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7560 -- TPM - Register accessor macros
mbed_official 363:12a245e5c745 7561 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7562
mbed_official 363:12a245e5c745 7563 /*!
mbed_official 363:12a245e5c745 7564 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
mbed_official 363:12a245e5c745 7565 * @{
mbed_official 363:12a245e5c745 7566 */
mbed_official 363:12a245e5c745 7567
mbed_official 363:12a245e5c745 7568
mbed_official 363:12a245e5c745 7569 /* TPM - Register accessors */
mbed_official 363:12a245e5c745 7570 #define TPM_SC_REG(base) ((base)->SC)
mbed_official 363:12a245e5c745 7571 #define TPM_CNT_REG(base) ((base)->CNT)
mbed_official 363:12a245e5c745 7572 #define TPM_MOD_REG(base) ((base)->MOD)
mbed_official 363:12a245e5c745 7573 #define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
mbed_official 363:12a245e5c745 7574 #define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
mbed_official 363:12a245e5c745 7575 #define TPM_STATUS_REG(base) ((base)->STATUS)
mbed_official 363:12a245e5c745 7576 #define TPM_POL_REG(base) ((base)->POL)
mbed_official 363:12a245e5c745 7577 #define TPM_CONF_REG(base) ((base)->CONF)
mbed_official 363:12a245e5c745 7578
mbed_official 363:12a245e5c745 7579 /*!
mbed_official 363:12a245e5c745 7580 * @}
mbed_official 363:12a245e5c745 7581 */ /* end of group TPM_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 7582
mbed_official 363:12a245e5c745 7583
mbed_official 363:12a245e5c745 7584 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7585 -- TPM Register Masks
mbed_official 363:12a245e5c745 7586 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7587
mbed_official 363:12a245e5c745 7588 /*!
mbed_official 363:12a245e5c745 7589 * @addtogroup TPM_Register_Masks TPM Register Masks
mbed_official 363:12a245e5c745 7590 * @{
mbed_official 363:12a245e5c745 7591 */
mbed_official 363:12a245e5c745 7592
mbed_official 363:12a245e5c745 7593 /* SC Bit Fields */
mbed_official 363:12a245e5c745 7594 #define TPM_SC_PS_MASK 0x7u
mbed_official 363:12a245e5c745 7595 #define TPM_SC_PS_SHIFT 0
mbed_official 363:12a245e5c745 7596 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
mbed_official 363:12a245e5c745 7597 #define TPM_SC_CMOD_MASK 0x18u
mbed_official 363:12a245e5c745 7598 #define TPM_SC_CMOD_SHIFT 3
mbed_official 363:12a245e5c745 7599 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
mbed_official 363:12a245e5c745 7600 #define TPM_SC_CPWMS_MASK 0x20u
mbed_official 363:12a245e5c745 7601 #define TPM_SC_CPWMS_SHIFT 5
mbed_official 363:12a245e5c745 7602 #define TPM_SC_TOIE_MASK 0x40u
mbed_official 363:12a245e5c745 7603 #define TPM_SC_TOIE_SHIFT 6
mbed_official 363:12a245e5c745 7604 #define TPM_SC_TOF_MASK 0x80u
mbed_official 363:12a245e5c745 7605 #define TPM_SC_TOF_SHIFT 7
mbed_official 363:12a245e5c745 7606 #define TPM_SC_DMA_MASK 0x100u
mbed_official 363:12a245e5c745 7607 #define TPM_SC_DMA_SHIFT 8
mbed_official 363:12a245e5c745 7608 /* CNT Bit Fields */
mbed_official 363:12a245e5c745 7609 #define TPM_CNT_COUNT_MASK 0xFFFFu
mbed_official 363:12a245e5c745 7610 #define TPM_CNT_COUNT_SHIFT 0
mbed_official 363:12a245e5c745 7611 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
mbed_official 363:12a245e5c745 7612 /* MOD Bit Fields */
mbed_official 363:12a245e5c745 7613 #define TPM_MOD_MOD_MASK 0xFFFFu
mbed_official 363:12a245e5c745 7614 #define TPM_MOD_MOD_SHIFT 0
mbed_official 363:12a245e5c745 7615 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
mbed_official 363:12a245e5c745 7616 /* CnSC Bit Fields */
mbed_official 363:12a245e5c745 7617 #define TPM_CnSC_DMA_MASK 0x1u
mbed_official 363:12a245e5c745 7618 #define TPM_CnSC_DMA_SHIFT 0
mbed_official 363:12a245e5c745 7619 #define TPM_CnSC_ELSA_MASK 0x4u
mbed_official 363:12a245e5c745 7620 #define TPM_CnSC_ELSA_SHIFT 2
mbed_official 363:12a245e5c745 7621 #define TPM_CnSC_ELSB_MASK 0x8u
mbed_official 363:12a245e5c745 7622 #define TPM_CnSC_ELSB_SHIFT 3
mbed_official 363:12a245e5c745 7623 #define TPM_CnSC_MSA_MASK 0x10u
mbed_official 363:12a245e5c745 7624 #define TPM_CnSC_MSA_SHIFT 4
mbed_official 363:12a245e5c745 7625 #define TPM_CnSC_MSB_MASK 0x20u
mbed_official 363:12a245e5c745 7626 #define TPM_CnSC_MSB_SHIFT 5
mbed_official 363:12a245e5c745 7627 #define TPM_CnSC_CHIE_MASK 0x40u
mbed_official 363:12a245e5c745 7628 #define TPM_CnSC_CHIE_SHIFT 6
mbed_official 363:12a245e5c745 7629 #define TPM_CnSC_CHF_MASK 0x80u
mbed_official 363:12a245e5c745 7630 #define TPM_CnSC_CHF_SHIFT 7
mbed_official 363:12a245e5c745 7631 /* CnV Bit Fields */
mbed_official 363:12a245e5c745 7632 #define TPM_CnV_VAL_MASK 0xFFFFu
mbed_official 363:12a245e5c745 7633 #define TPM_CnV_VAL_SHIFT 0
mbed_official 363:12a245e5c745 7634 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
mbed_official 363:12a245e5c745 7635 /* STATUS Bit Fields */
mbed_official 363:12a245e5c745 7636 #define TPM_STATUS_CH0F_MASK 0x1u
mbed_official 363:12a245e5c745 7637 #define TPM_STATUS_CH0F_SHIFT 0
mbed_official 363:12a245e5c745 7638 #define TPM_STATUS_CH1F_MASK 0x2u
mbed_official 363:12a245e5c745 7639 #define TPM_STATUS_CH1F_SHIFT 1
mbed_official 363:12a245e5c745 7640 #define TPM_STATUS_CH2F_MASK 0x4u
mbed_official 363:12a245e5c745 7641 #define TPM_STATUS_CH2F_SHIFT 2
mbed_official 363:12a245e5c745 7642 #define TPM_STATUS_CH3F_MASK 0x8u
mbed_official 363:12a245e5c745 7643 #define TPM_STATUS_CH3F_SHIFT 3
mbed_official 363:12a245e5c745 7644 #define TPM_STATUS_CH4F_MASK 0x10u
mbed_official 363:12a245e5c745 7645 #define TPM_STATUS_CH4F_SHIFT 4
mbed_official 363:12a245e5c745 7646 #define TPM_STATUS_CH5F_MASK 0x20u
mbed_official 363:12a245e5c745 7647 #define TPM_STATUS_CH5F_SHIFT 5
mbed_official 363:12a245e5c745 7648 #define TPM_STATUS_TOF_MASK 0x100u
mbed_official 363:12a245e5c745 7649 #define TPM_STATUS_TOF_SHIFT 8
mbed_official 363:12a245e5c745 7650 /* POL Bit Fields */
mbed_official 363:12a245e5c745 7651 #define TPM_POL_POL0_MASK 0x1u
mbed_official 363:12a245e5c745 7652 #define TPM_POL_POL0_SHIFT 0
mbed_official 363:12a245e5c745 7653 #define TPM_POL_POL1_MASK 0x2u
mbed_official 363:12a245e5c745 7654 #define TPM_POL_POL1_SHIFT 1
mbed_official 363:12a245e5c745 7655 #define TPM_POL_POL2_MASK 0x4u
mbed_official 363:12a245e5c745 7656 #define TPM_POL_POL2_SHIFT 2
mbed_official 363:12a245e5c745 7657 #define TPM_POL_POL3_MASK 0x8u
mbed_official 363:12a245e5c745 7658 #define TPM_POL_POL3_SHIFT 3
mbed_official 363:12a245e5c745 7659 #define TPM_POL_POL4_MASK 0x10u
mbed_official 363:12a245e5c745 7660 #define TPM_POL_POL4_SHIFT 4
mbed_official 363:12a245e5c745 7661 #define TPM_POL_POL5_MASK 0x20u
mbed_official 363:12a245e5c745 7662 #define TPM_POL_POL5_SHIFT 5
mbed_official 363:12a245e5c745 7663 /* CONF Bit Fields */
mbed_official 363:12a245e5c745 7664 #define TPM_CONF_DOZEEN_MASK 0x20u
mbed_official 363:12a245e5c745 7665 #define TPM_CONF_DOZEEN_SHIFT 5
mbed_official 363:12a245e5c745 7666 #define TPM_CONF_DBGMODE_MASK 0xC0u
mbed_official 363:12a245e5c745 7667 #define TPM_CONF_DBGMODE_SHIFT 6
mbed_official 363:12a245e5c745 7668 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
mbed_official 363:12a245e5c745 7669 #define TPM_CONF_GTBSYNC_MASK 0x100u
mbed_official 363:12a245e5c745 7670 #define TPM_CONF_GTBSYNC_SHIFT 8
mbed_official 363:12a245e5c745 7671 #define TPM_CONF_GTBEEN_MASK 0x200u
mbed_official 363:12a245e5c745 7672 #define TPM_CONF_GTBEEN_SHIFT 9
mbed_official 363:12a245e5c745 7673 #define TPM_CONF_CSOT_MASK 0x10000u
mbed_official 363:12a245e5c745 7674 #define TPM_CONF_CSOT_SHIFT 16
mbed_official 363:12a245e5c745 7675 #define TPM_CONF_CSOO_MASK 0x20000u
mbed_official 363:12a245e5c745 7676 #define TPM_CONF_CSOO_SHIFT 17
mbed_official 363:12a245e5c745 7677 #define TPM_CONF_CROT_MASK 0x40000u
mbed_official 363:12a245e5c745 7678 #define TPM_CONF_CROT_SHIFT 18
mbed_official 363:12a245e5c745 7679 #define TPM_CONF_CPOT_MASK 0x80000u
mbed_official 363:12a245e5c745 7680 #define TPM_CONF_CPOT_SHIFT 19
mbed_official 363:12a245e5c745 7681 #define TPM_CONF_TRGPOL_MASK 0x400000u
mbed_official 363:12a245e5c745 7682 #define TPM_CONF_TRGPOL_SHIFT 22
mbed_official 363:12a245e5c745 7683 #define TPM_CONF_TRGSRC_MASK 0x800000u
mbed_official 363:12a245e5c745 7684 #define TPM_CONF_TRGSRC_SHIFT 23
mbed_official 363:12a245e5c745 7685 #define TPM_CONF_TRGSEL_MASK 0xF000000u
mbed_official 363:12a245e5c745 7686 #define TPM_CONF_TRGSEL_SHIFT 24
mbed_official 363:12a245e5c745 7687 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
mbed_official 363:12a245e5c745 7688
mbed_official 363:12a245e5c745 7689 /*!
mbed_official 363:12a245e5c745 7690 * @}
mbed_official 363:12a245e5c745 7691 */ /* end of group TPM_Register_Masks */
mbed_official 363:12a245e5c745 7692
mbed_official 363:12a245e5c745 7693
mbed_official 363:12a245e5c745 7694 /* TPM - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 7695 /** Peripheral TPM0 base address */
mbed_official 363:12a245e5c745 7696 #define TPM0_BASE (0x40038000u)
mbed_official 363:12a245e5c745 7697 /** Peripheral TPM0 base pointer */
mbed_official 363:12a245e5c745 7698 #define TPM0 ((TPM_Type *)TPM0_BASE)
mbed_official 363:12a245e5c745 7699 #define TPM0_BASE_PTR (TPM0)
mbed_official 363:12a245e5c745 7700 /** Peripheral TPM1 base address */
mbed_official 363:12a245e5c745 7701 #define TPM1_BASE (0x40039000u)
mbed_official 363:12a245e5c745 7702 /** Peripheral TPM1 base pointer */
mbed_official 363:12a245e5c745 7703 #define TPM1 ((TPM_Type *)TPM1_BASE)
mbed_official 363:12a245e5c745 7704 #define TPM1_BASE_PTR (TPM1)
mbed_official 363:12a245e5c745 7705 /** Peripheral TPM2 base address */
mbed_official 363:12a245e5c745 7706 #define TPM2_BASE (0x4003A000u)
mbed_official 363:12a245e5c745 7707 /** Peripheral TPM2 base pointer */
mbed_official 363:12a245e5c745 7708 #define TPM2 ((TPM_Type *)TPM2_BASE)
mbed_official 363:12a245e5c745 7709 #define TPM2_BASE_PTR (TPM2)
mbed_official 363:12a245e5c745 7710 /** Array initializer of TPM peripheral base addresses */
mbed_official 363:12a245e5c745 7711 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
mbed_official 363:12a245e5c745 7712 /** Array initializer of TPM peripheral base pointers */
mbed_official 363:12a245e5c745 7713 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
mbed_official 363:12a245e5c745 7714 /** Interrupt vectors for the TPM peripheral type */
mbed_official 363:12a245e5c745 7715 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
mbed_official 363:12a245e5c745 7716
mbed_official 363:12a245e5c745 7717 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7718 -- TPM - Register accessor macros
mbed_official 363:12a245e5c745 7719 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7720
mbed_official 363:12a245e5c745 7721 /*!
mbed_official 363:12a245e5c745 7722 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
mbed_official 363:12a245e5c745 7723 * @{
mbed_official 363:12a245e5c745 7724 */
mbed_official 363:12a245e5c745 7725
mbed_official 363:12a245e5c745 7726
mbed_official 363:12a245e5c745 7727 /* TPM - Register instance definitions */
mbed_official 363:12a245e5c745 7728 /* TPM0 */
mbed_official 363:12a245e5c745 7729 #define TPM0_SC TPM_SC_REG(TPM0)
mbed_official 363:12a245e5c745 7730 #define TPM0_CNT TPM_CNT_REG(TPM0)
mbed_official 363:12a245e5c745 7731 #define TPM0_MOD TPM_MOD_REG(TPM0)
mbed_official 363:12a245e5c745 7732 #define TPM0_C0SC TPM_CnSC_REG(TPM0,0)
mbed_official 363:12a245e5c745 7733 #define TPM0_C0V TPM_CnV_REG(TPM0,0)
mbed_official 363:12a245e5c745 7734 #define TPM0_C1SC TPM_CnSC_REG(TPM0,1)
mbed_official 363:12a245e5c745 7735 #define TPM0_C1V TPM_CnV_REG(TPM0,1)
mbed_official 363:12a245e5c745 7736 #define TPM0_C2SC TPM_CnSC_REG(TPM0,2)
mbed_official 363:12a245e5c745 7737 #define TPM0_C2V TPM_CnV_REG(TPM0,2)
mbed_official 363:12a245e5c745 7738 #define TPM0_C3SC TPM_CnSC_REG(TPM0,3)
mbed_official 363:12a245e5c745 7739 #define TPM0_C3V TPM_CnV_REG(TPM0,3)
mbed_official 363:12a245e5c745 7740 #define TPM0_C4SC TPM_CnSC_REG(TPM0,4)
mbed_official 363:12a245e5c745 7741 #define TPM0_C4V TPM_CnV_REG(TPM0,4)
mbed_official 363:12a245e5c745 7742 #define TPM0_C5SC TPM_CnSC_REG(TPM0,5)
mbed_official 363:12a245e5c745 7743 #define TPM0_C5V TPM_CnV_REG(TPM0,5)
mbed_official 363:12a245e5c745 7744 #define TPM0_STATUS TPM_STATUS_REG(TPM0)
mbed_official 363:12a245e5c745 7745 #define TPM0_POL TPM_POL_REG(TPM0)
mbed_official 363:12a245e5c745 7746 #define TPM0_CONF TPM_CONF_REG(TPM0)
mbed_official 363:12a245e5c745 7747 /* TPM1 */
mbed_official 363:12a245e5c745 7748 #define TPM1_SC TPM_SC_REG(TPM1)
mbed_official 363:12a245e5c745 7749 #define TPM1_CNT TPM_CNT_REG(TPM1)
mbed_official 363:12a245e5c745 7750 #define TPM1_MOD TPM_MOD_REG(TPM1)
mbed_official 363:12a245e5c745 7751 #define TPM1_C0SC TPM_CnSC_REG(TPM1,0)
mbed_official 363:12a245e5c745 7752 #define TPM1_C0V TPM_CnV_REG(TPM1,0)
mbed_official 363:12a245e5c745 7753 #define TPM1_C1SC TPM_CnSC_REG(TPM1,1)
mbed_official 363:12a245e5c745 7754 #define TPM1_C1V TPM_CnV_REG(TPM1,1)
mbed_official 363:12a245e5c745 7755 #define TPM1_STATUS TPM_STATUS_REG(TPM1)
mbed_official 363:12a245e5c745 7756 #define TPM1_POL TPM_POL_REG(TPM1)
mbed_official 363:12a245e5c745 7757 #define TPM1_CONF TPM_CONF_REG(TPM1)
mbed_official 363:12a245e5c745 7758 /* TPM2 */
mbed_official 363:12a245e5c745 7759 #define TPM2_SC TPM_SC_REG(TPM2)
mbed_official 363:12a245e5c745 7760 #define TPM2_CNT TPM_CNT_REG(TPM2)
mbed_official 363:12a245e5c745 7761 #define TPM2_MOD TPM_MOD_REG(TPM2)
mbed_official 363:12a245e5c745 7762 #define TPM2_C0SC TPM_CnSC_REG(TPM2,0)
mbed_official 363:12a245e5c745 7763 #define TPM2_C0V TPM_CnV_REG(TPM2,0)
mbed_official 363:12a245e5c745 7764 #define TPM2_C1SC TPM_CnSC_REG(TPM2,1)
mbed_official 363:12a245e5c745 7765 #define TPM2_C1V TPM_CnV_REG(TPM2,1)
mbed_official 363:12a245e5c745 7766 #define TPM2_STATUS TPM_STATUS_REG(TPM2)
mbed_official 363:12a245e5c745 7767 #define TPM2_POL TPM_POL_REG(TPM2)
mbed_official 363:12a245e5c745 7768 #define TPM2_CONF TPM_CONF_REG(TPM2)
mbed_official 363:12a245e5c745 7769
mbed_official 363:12a245e5c745 7770 /* TPM - Register array accessors */
mbed_official 363:12a245e5c745 7771 #define TPM0_CnSC(index) TPM_CnSC_REG(TPM0,index)
mbed_official 363:12a245e5c745 7772 #define TPM1_CnSC(index) TPM_CnSC_REG(TPM1,index)
mbed_official 363:12a245e5c745 7773 #define TPM2_CnSC(index) TPM_CnSC_REG(TPM2,index)
mbed_official 363:12a245e5c745 7774 #define TPM0_CnV(index) TPM_CnV_REG(TPM0,index)
mbed_official 363:12a245e5c745 7775 #define TPM1_CnV(index) TPM_CnV_REG(TPM1,index)
mbed_official 363:12a245e5c745 7776 #define TPM2_CnV(index) TPM_CnV_REG(TPM2,index)
mbed_official 363:12a245e5c745 7777
mbed_official 363:12a245e5c745 7778 /*!
mbed_official 363:12a245e5c745 7779 * @}
mbed_official 363:12a245e5c745 7780 */ /* end of group TPM_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 7781
mbed_official 363:12a245e5c745 7782
mbed_official 363:12a245e5c745 7783 /*!
mbed_official 363:12a245e5c745 7784 * @}
mbed_official 363:12a245e5c745 7785 */ /* end of group TPM_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 7786
mbed_official 363:12a245e5c745 7787
mbed_official 363:12a245e5c745 7788 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7789 -- UART Peripheral Access Layer
mbed_official 363:12a245e5c745 7790 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7791
mbed_official 363:12a245e5c745 7792 /*!
mbed_official 363:12a245e5c745 7793 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
mbed_official 363:12a245e5c745 7794 * @{
mbed_official 363:12a245e5c745 7795 */
mbed_official 363:12a245e5c745 7796
mbed_official 363:12a245e5c745 7797 /** UART - Register Layout Typedef */
mbed_official 363:12a245e5c745 7798 typedef struct {
mbed_official 363:12a245e5c745 7799 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
mbed_official 363:12a245e5c745 7800 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
mbed_official 363:12a245e5c745 7801 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
mbed_official 363:12a245e5c745 7802 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
mbed_official 363:12a245e5c745 7803 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
mbed_official 363:12a245e5c745 7804 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
mbed_official 363:12a245e5c745 7805 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
mbed_official 363:12a245e5c745 7806 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
mbed_official 363:12a245e5c745 7807 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
mbed_official 363:12a245e5c745 7808 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
mbed_official 363:12a245e5c745 7809 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
mbed_official 363:12a245e5c745 7810 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
mbed_official 363:12a245e5c745 7811 uint8_t RESERVED_0[12];
mbed_official 363:12a245e5c745 7812 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
mbed_official 363:12a245e5c745 7813 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
mbed_official 363:12a245e5c745 7814 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
mbed_official 363:12a245e5c745 7815 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
mbed_official 363:12a245e5c745 7816 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
mbed_official 363:12a245e5c745 7817 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
mbed_official 363:12a245e5c745 7818 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
mbed_official 363:12a245e5c745 7819 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
mbed_official 363:12a245e5c745 7820 uint8_t RESERVED_1[26];
mbed_official 363:12a245e5c745 7821 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
mbed_official 363:12a245e5c745 7822 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
mbed_official 363:12a245e5c745 7823 union { /* offset: 0x3C */
mbed_official 363:12a245e5c745 7824 struct { /* offset: 0x3C */
mbed_official 363:12a245e5c745 7825 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
mbed_official 363:12a245e5c745 7826 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
mbed_official 363:12a245e5c745 7827 } TYPE0;
mbed_official 363:12a245e5c745 7828 struct { /* offset: 0x3C */
mbed_official 363:12a245e5c745 7829 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
mbed_official 363:12a245e5c745 7830 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
mbed_official 363:12a245e5c745 7831 } TYPE1;
mbed_official 363:12a245e5c745 7832 };
mbed_official 363:12a245e5c745 7833 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
mbed_official 363:12a245e5c745 7834 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
mbed_official 363:12a245e5c745 7835 } UART_Type, *UART_MemMapPtr;
mbed_official 363:12a245e5c745 7836
mbed_official 363:12a245e5c745 7837 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7838 -- UART - Register accessor macros
mbed_official 363:12a245e5c745 7839 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7840
mbed_official 363:12a245e5c745 7841 /*!
mbed_official 363:12a245e5c745 7842 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
mbed_official 363:12a245e5c745 7843 * @{
mbed_official 363:12a245e5c745 7844 */
mbed_official 363:12a245e5c745 7845
mbed_official 363:12a245e5c745 7846
mbed_official 363:12a245e5c745 7847 /* UART - Register accessors */
mbed_official 363:12a245e5c745 7848 #define UART_BDH_REG(base) ((base)->BDH)
mbed_official 363:12a245e5c745 7849 #define UART_BDL_REG(base) ((base)->BDL)
mbed_official 363:12a245e5c745 7850 #define UART_C1_REG(base) ((base)->C1)
mbed_official 363:12a245e5c745 7851 #define UART_C2_REG(base) ((base)->C2)
mbed_official 363:12a245e5c745 7852 #define UART_S1_REG(base) ((base)->S1)
mbed_official 363:12a245e5c745 7853 #define UART_S2_REG(base) ((base)->S2)
mbed_official 363:12a245e5c745 7854 #define UART_C3_REG(base) ((base)->C3)
mbed_official 363:12a245e5c745 7855 #define UART_D_REG(base) ((base)->D)
mbed_official 363:12a245e5c745 7856 #define UART_MA1_REG(base) ((base)->MA1)
mbed_official 363:12a245e5c745 7857 #define UART_MA2_REG(base) ((base)->MA2)
mbed_official 363:12a245e5c745 7858 #define UART_C4_REG(base) ((base)->C4)
mbed_official 363:12a245e5c745 7859 #define UART_C5_REG(base) ((base)->C5)
mbed_official 363:12a245e5c745 7860 #define UART_C7816_REG(base) ((base)->C7816)
mbed_official 363:12a245e5c745 7861 #define UART_IE7816_REG(base) ((base)->IE7816)
mbed_official 363:12a245e5c745 7862 #define UART_IS7816_REG(base) ((base)->IS7816)
mbed_official 363:12a245e5c745 7863 #define UART_WP7816_REG(base) ((base)->WP7816)
mbed_official 363:12a245e5c745 7864 #define UART_WN7816_REG(base) ((base)->WN7816)
mbed_official 363:12a245e5c745 7865 #define UART_WF7816_REG(base) ((base)->WF7816)
mbed_official 363:12a245e5c745 7866 #define UART_ET7816_REG(base) ((base)->ET7816)
mbed_official 363:12a245e5c745 7867 #define UART_TL7816_REG(base) ((base)->TL7816)
mbed_official 363:12a245e5c745 7868 #define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
mbed_official 363:12a245e5c745 7869 #define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
mbed_official 363:12a245e5c745 7870 #define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
mbed_official 363:12a245e5c745 7871 #define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
mbed_official 363:12a245e5c745 7872 #define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
mbed_official 363:12a245e5c745 7873 #define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
mbed_official 363:12a245e5c745 7874 #define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
mbed_official 363:12a245e5c745 7875 #define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
mbed_official 363:12a245e5c745 7876
mbed_official 363:12a245e5c745 7877 /*!
mbed_official 363:12a245e5c745 7878 * @}
mbed_official 363:12a245e5c745 7879 */ /* end of group UART_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 7880
mbed_official 363:12a245e5c745 7881
mbed_official 363:12a245e5c745 7882 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 7883 -- UART Register Masks
mbed_official 363:12a245e5c745 7884 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 7885
mbed_official 363:12a245e5c745 7886 /*!
mbed_official 363:12a245e5c745 7887 * @addtogroup UART_Register_Masks UART Register Masks
mbed_official 363:12a245e5c745 7888 * @{
mbed_official 363:12a245e5c745 7889 */
mbed_official 363:12a245e5c745 7890
mbed_official 363:12a245e5c745 7891 /* BDH Bit Fields */
mbed_official 363:12a245e5c745 7892 #define UART_BDH_SBR_MASK 0x1Fu
mbed_official 363:12a245e5c745 7893 #define UART_BDH_SBR_SHIFT 0
mbed_official 363:12a245e5c745 7894 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
mbed_official 363:12a245e5c745 7895 #define UART_BDH_RXEDGIE_MASK 0x40u
mbed_official 363:12a245e5c745 7896 #define UART_BDH_RXEDGIE_SHIFT 6
mbed_official 363:12a245e5c745 7897 /* BDL Bit Fields */
mbed_official 363:12a245e5c745 7898 #define UART_BDL_SBR_MASK 0xFFu
mbed_official 363:12a245e5c745 7899 #define UART_BDL_SBR_SHIFT 0
mbed_official 363:12a245e5c745 7900 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
mbed_official 363:12a245e5c745 7901 /* C1 Bit Fields */
mbed_official 363:12a245e5c745 7902 #define UART_C1_PT_MASK 0x1u
mbed_official 363:12a245e5c745 7903 #define UART_C1_PT_SHIFT 0
mbed_official 363:12a245e5c745 7904 #define UART_C1_PE_MASK 0x2u
mbed_official 363:12a245e5c745 7905 #define UART_C1_PE_SHIFT 1
mbed_official 363:12a245e5c745 7906 #define UART_C1_ILT_MASK 0x4u
mbed_official 363:12a245e5c745 7907 #define UART_C1_ILT_SHIFT 2
mbed_official 363:12a245e5c745 7908 #define UART_C1_WAKE_MASK 0x8u
mbed_official 363:12a245e5c745 7909 #define UART_C1_WAKE_SHIFT 3
mbed_official 363:12a245e5c745 7910 #define UART_C1_M_MASK 0x10u
mbed_official 363:12a245e5c745 7911 #define UART_C1_M_SHIFT 4
mbed_official 363:12a245e5c745 7912 #define UART_C1_RSRC_MASK 0x20u
mbed_official 363:12a245e5c745 7913 #define UART_C1_RSRC_SHIFT 5
mbed_official 363:12a245e5c745 7914 #define UART_C1_LOOPS_MASK 0x80u
mbed_official 363:12a245e5c745 7915 #define UART_C1_LOOPS_SHIFT 7
mbed_official 363:12a245e5c745 7916 /* C2 Bit Fields */
mbed_official 363:12a245e5c745 7917 #define UART_C2_SBK_MASK 0x1u
mbed_official 363:12a245e5c745 7918 #define UART_C2_SBK_SHIFT 0
mbed_official 363:12a245e5c745 7919 #define UART_C2_RWU_MASK 0x2u
mbed_official 363:12a245e5c745 7920 #define UART_C2_RWU_SHIFT 1
mbed_official 363:12a245e5c745 7921 #define UART_C2_RE_MASK 0x4u
mbed_official 363:12a245e5c745 7922 #define UART_C2_RE_SHIFT 2
mbed_official 363:12a245e5c745 7923 #define UART_C2_TE_MASK 0x8u
mbed_official 363:12a245e5c745 7924 #define UART_C2_TE_SHIFT 3
mbed_official 363:12a245e5c745 7925 #define UART_C2_ILIE_MASK 0x10u
mbed_official 363:12a245e5c745 7926 #define UART_C2_ILIE_SHIFT 4
mbed_official 363:12a245e5c745 7927 #define UART_C2_RIE_MASK 0x20u
mbed_official 363:12a245e5c745 7928 #define UART_C2_RIE_SHIFT 5
mbed_official 363:12a245e5c745 7929 #define UART_C2_TCIE_MASK 0x40u
mbed_official 363:12a245e5c745 7930 #define UART_C2_TCIE_SHIFT 6
mbed_official 363:12a245e5c745 7931 #define UART_C2_TIE_MASK 0x80u
mbed_official 363:12a245e5c745 7932 #define UART_C2_TIE_SHIFT 7
mbed_official 363:12a245e5c745 7933 /* S1 Bit Fields */
mbed_official 363:12a245e5c745 7934 #define UART_S1_PF_MASK 0x1u
mbed_official 363:12a245e5c745 7935 #define UART_S1_PF_SHIFT 0
mbed_official 363:12a245e5c745 7936 #define UART_S1_FE_MASK 0x2u
mbed_official 363:12a245e5c745 7937 #define UART_S1_FE_SHIFT 1
mbed_official 363:12a245e5c745 7938 #define UART_S1_NF_MASK 0x4u
mbed_official 363:12a245e5c745 7939 #define UART_S1_NF_SHIFT 2
mbed_official 363:12a245e5c745 7940 #define UART_S1_OR_MASK 0x8u
mbed_official 363:12a245e5c745 7941 #define UART_S1_OR_SHIFT 3
mbed_official 363:12a245e5c745 7942 #define UART_S1_IDLE_MASK 0x10u
mbed_official 363:12a245e5c745 7943 #define UART_S1_IDLE_SHIFT 4
mbed_official 363:12a245e5c745 7944 #define UART_S1_RDRF_MASK 0x20u
mbed_official 363:12a245e5c745 7945 #define UART_S1_RDRF_SHIFT 5
mbed_official 363:12a245e5c745 7946 #define UART_S1_TC_MASK 0x40u
mbed_official 363:12a245e5c745 7947 #define UART_S1_TC_SHIFT 6
mbed_official 363:12a245e5c745 7948 #define UART_S1_TDRE_MASK 0x80u
mbed_official 363:12a245e5c745 7949 #define UART_S1_TDRE_SHIFT 7
mbed_official 363:12a245e5c745 7950 /* S2 Bit Fields */
mbed_official 363:12a245e5c745 7951 #define UART_S2_RAF_MASK 0x1u
mbed_official 363:12a245e5c745 7952 #define UART_S2_RAF_SHIFT 0
mbed_official 363:12a245e5c745 7953 #define UART_S2_BRK13_MASK 0x4u
mbed_official 363:12a245e5c745 7954 #define UART_S2_BRK13_SHIFT 2
mbed_official 363:12a245e5c745 7955 #define UART_S2_RWUID_MASK 0x8u
mbed_official 363:12a245e5c745 7956 #define UART_S2_RWUID_SHIFT 3
mbed_official 363:12a245e5c745 7957 #define UART_S2_RXINV_MASK 0x10u
mbed_official 363:12a245e5c745 7958 #define UART_S2_RXINV_SHIFT 4
mbed_official 363:12a245e5c745 7959 #define UART_S2_MSBF_MASK 0x20u
mbed_official 363:12a245e5c745 7960 #define UART_S2_MSBF_SHIFT 5
mbed_official 363:12a245e5c745 7961 #define UART_S2_RXEDGIF_MASK 0x40u
mbed_official 363:12a245e5c745 7962 #define UART_S2_RXEDGIF_SHIFT 6
mbed_official 363:12a245e5c745 7963 /* C3 Bit Fields */
mbed_official 363:12a245e5c745 7964 #define UART_C3_PEIE_MASK 0x1u
mbed_official 363:12a245e5c745 7965 #define UART_C3_PEIE_SHIFT 0
mbed_official 363:12a245e5c745 7966 #define UART_C3_FEIE_MASK 0x2u
mbed_official 363:12a245e5c745 7967 #define UART_C3_FEIE_SHIFT 1
mbed_official 363:12a245e5c745 7968 #define UART_C3_NEIE_MASK 0x4u
mbed_official 363:12a245e5c745 7969 #define UART_C3_NEIE_SHIFT 2
mbed_official 363:12a245e5c745 7970 #define UART_C3_ORIE_MASK 0x8u
mbed_official 363:12a245e5c745 7971 #define UART_C3_ORIE_SHIFT 3
mbed_official 363:12a245e5c745 7972 #define UART_C3_TXINV_MASK 0x10u
mbed_official 363:12a245e5c745 7973 #define UART_C3_TXINV_SHIFT 4
mbed_official 363:12a245e5c745 7974 #define UART_C3_TXDIR_MASK 0x20u
mbed_official 363:12a245e5c745 7975 #define UART_C3_TXDIR_SHIFT 5
mbed_official 363:12a245e5c745 7976 #define UART_C3_T8_MASK 0x40u
mbed_official 363:12a245e5c745 7977 #define UART_C3_T8_SHIFT 6
mbed_official 363:12a245e5c745 7978 #define UART_C3_R8_MASK 0x80u
mbed_official 363:12a245e5c745 7979 #define UART_C3_R8_SHIFT 7
mbed_official 363:12a245e5c745 7980 /* D Bit Fields */
mbed_official 363:12a245e5c745 7981 #define UART_D_RT_MASK 0xFFu
mbed_official 363:12a245e5c745 7982 #define UART_D_RT_SHIFT 0
mbed_official 363:12a245e5c745 7983 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
mbed_official 363:12a245e5c745 7984 /* MA1 Bit Fields */
mbed_official 363:12a245e5c745 7985 #define UART_MA1_MA_MASK 0xFFu
mbed_official 363:12a245e5c745 7986 #define UART_MA1_MA_SHIFT 0
mbed_official 363:12a245e5c745 7987 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
mbed_official 363:12a245e5c745 7988 /* MA2 Bit Fields */
mbed_official 363:12a245e5c745 7989 #define UART_MA2_MA_MASK 0xFFu
mbed_official 363:12a245e5c745 7990 #define UART_MA2_MA_SHIFT 0
mbed_official 363:12a245e5c745 7991 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
mbed_official 363:12a245e5c745 7992 /* C4 Bit Fields */
mbed_official 363:12a245e5c745 7993 #define UART_C4_BRFA_MASK 0x1Fu
mbed_official 363:12a245e5c745 7994 #define UART_C4_BRFA_SHIFT 0
mbed_official 363:12a245e5c745 7995 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
mbed_official 363:12a245e5c745 7996 #define UART_C4_M10_MASK 0x20u
mbed_official 363:12a245e5c745 7997 #define UART_C4_M10_SHIFT 5
mbed_official 363:12a245e5c745 7998 #define UART_C4_MAEN2_MASK 0x40u
mbed_official 363:12a245e5c745 7999 #define UART_C4_MAEN2_SHIFT 6
mbed_official 363:12a245e5c745 8000 #define UART_C4_MAEN1_MASK 0x80u
mbed_official 363:12a245e5c745 8001 #define UART_C4_MAEN1_SHIFT 7
mbed_official 363:12a245e5c745 8002 /* C5 Bit Fields */
mbed_official 363:12a245e5c745 8003 #define UART_C5_RDMAS_MASK 0x20u
mbed_official 363:12a245e5c745 8004 #define UART_C5_RDMAS_SHIFT 5
mbed_official 363:12a245e5c745 8005 #define UART_C5_TDMAS_MASK 0x80u
mbed_official 363:12a245e5c745 8006 #define UART_C5_TDMAS_SHIFT 7
mbed_official 363:12a245e5c745 8007 /* C7816 Bit Fields */
mbed_official 363:12a245e5c745 8008 #define UART_C7816_ISO_7816E_MASK 0x1u
mbed_official 363:12a245e5c745 8009 #define UART_C7816_ISO_7816E_SHIFT 0
mbed_official 363:12a245e5c745 8010 #define UART_C7816_TTYPE_MASK 0x2u
mbed_official 363:12a245e5c745 8011 #define UART_C7816_TTYPE_SHIFT 1
mbed_official 363:12a245e5c745 8012 #define UART_C7816_INIT_MASK 0x4u
mbed_official 363:12a245e5c745 8013 #define UART_C7816_INIT_SHIFT 2
mbed_official 363:12a245e5c745 8014 #define UART_C7816_ANACK_MASK 0x8u
mbed_official 363:12a245e5c745 8015 #define UART_C7816_ANACK_SHIFT 3
mbed_official 363:12a245e5c745 8016 #define UART_C7816_ONACK_MASK 0x10u
mbed_official 363:12a245e5c745 8017 #define UART_C7816_ONACK_SHIFT 4
mbed_official 363:12a245e5c745 8018 /* IE7816 Bit Fields */
mbed_official 363:12a245e5c745 8019 #define UART_IE7816_RXTE_MASK 0x1u
mbed_official 363:12a245e5c745 8020 #define UART_IE7816_RXTE_SHIFT 0
mbed_official 363:12a245e5c745 8021 #define UART_IE7816_TXTE_MASK 0x2u
mbed_official 363:12a245e5c745 8022 #define UART_IE7816_TXTE_SHIFT 1
mbed_official 363:12a245e5c745 8023 #define UART_IE7816_GTVE_MASK 0x4u
mbed_official 363:12a245e5c745 8024 #define UART_IE7816_GTVE_SHIFT 2
mbed_official 363:12a245e5c745 8025 #define UART_IE7816_ADTE_MASK 0x8u
mbed_official 363:12a245e5c745 8026 #define UART_IE7816_ADTE_SHIFT 3
mbed_official 363:12a245e5c745 8027 #define UART_IE7816_INITDE_MASK 0x10u
mbed_official 363:12a245e5c745 8028 #define UART_IE7816_INITDE_SHIFT 4
mbed_official 363:12a245e5c745 8029 #define UART_IE7816_BWTE_MASK 0x20u
mbed_official 363:12a245e5c745 8030 #define UART_IE7816_BWTE_SHIFT 5
mbed_official 363:12a245e5c745 8031 #define UART_IE7816_CWTE_MASK 0x40u
mbed_official 363:12a245e5c745 8032 #define UART_IE7816_CWTE_SHIFT 6
mbed_official 363:12a245e5c745 8033 #define UART_IE7816_WTE_MASK 0x80u
mbed_official 363:12a245e5c745 8034 #define UART_IE7816_WTE_SHIFT 7
mbed_official 363:12a245e5c745 8035 /* IS7816 Bit Fields */
mbed_official 363:12a245e5c745 8036 #define UART_IS7816_RXT_MASK 0x1u
mbed_official 363:12a245e5c745 8037 #define UART_IS7816_RXT_SHIFT 0
mbed_official 363:12a245e5c745 8038 #define UART_IS7816_TXT_MASK 0x2u
mbed_official 363:12a245e5c745 8039 #define UART_IS7816_TXT_SHIFT 1
mbed_official 363:12a245e5c745 8040 #define UART_IS7816_GTV_MASK 0x4u
mbed_official 363:12a245e5c745 8041 #define UART_IS7816_GTV_SHIFT 2
mbed_official 363:12a245e5c745 8042 #define UART_IS7816_ADT_MASK 0x8u
mbed_official 363:12a245e5c745 8043 #define UART_IS7816_ADT_SHIFT 3
mbed_official 363:12a245e5c745 8044 #define UART_IS7816_INITD_MASK 0x10u
mbed_official 363:12a245e5c745 8045 #define UART_IS7816_INITD_SHIFT 4
mbed_official 363:12a245e5c745 8046 #define UART_IS7816_BWT_MASK 0x20u
mbed_official 363:12a245e5c745 8047 #define UART_IS7816_BWT_SHIFT 5
mbed_official 363:12a245e5c745 8048 #define UART_IS7816_CWT_MASK 0x40u
mbed_official 363:12a245e5c745 8049 #define UART_IS7816_CWT_SHIFT 6
mbed_official 363:12a245e5c745 8050 #define UART_IS7816_WT_MASK 0x80u
mbed_official 363:12a245e5c745 8051 #define UART_IS7816_WT_SHIFT 7
mbed_official 363:12a245e5c745 8052 /* WP7816 Bit Fields */
mbed_official 363:12a245e5c745 8053 #define UART_WP7816_WTX_MASK 0xFFu
mbed_official 363:12a245e5c745 8054 #define UART_WP7816_WTX_SHIFT 0
mbed_official 363:12a245e5c745 8055 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
mbed_official 363:12a245e5c745 8056 /* WN7816 Bit Fields */
mbed_official 363:12a245e5c745 8057 #define UART_WN7816_GTN_MASK 0xFFu
mbed_official 363:12a245e5c745 8058 #define UART_WN7816_GTN_SHIFT 0
mbed_official 363:12a245e5c745 8059 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
mbed_official 363:12a245e5c745 8060 /* WF7816 Bit Fields */
mbed_official 363:12a245e5c745 8061 #define UART_WF7816_GTFD_MASK 0xFFu
mbed_official 363:12a245e5c745 8062 #define UART_WF7816_GTFD_SHIFT 0
mbed_official 363:12a245e5c745 8063 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
mbed_official 363:12a245e5c745 8064 /* ET7816 Bit Fields */
mbed_official 363:12a245e5c745 8065 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
mbed_official 363:12a245e5c745 8066 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
mbed_official 363:12a245e5c745 8067 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
mbed_official 363:12a245e5c745 8068 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
mbed_official 363:12a245e5c745 8069 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
mbed_official 363:12a245e5c745 8070 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
mbed_official 363:12a245e5c745 8071 /* TL7816 Bit Fields */
mbed_official 363:12a245e5c745 8072 #define UART_TL7816_TLEN_MASK 0xFFu
mbed_official 363:12a245e5c745 8073 #define UART_TL7816_TLEN_SHIFT 0
mbed_official 363:12a245e5c745 8074 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
mbed_official 363:12a245e5c745 8075 /* AP7816A_T0 Bit Fields */
mbed_official 363:12a245e5c745 8076 #define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
mbed_official 363:12a245e5c745 8077 #define UART_AP7816A_T0_ADTI_H_SHIFT 0
mbed_official 363:12a245e5c745 8078 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
mbed_official 363:12a245e5c745 8079 /* AP7816B_T0 Bit Fields */
mbed_official 363:12a245e5c745 8080 #define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
mbed_official 363:12a245e5c745 8081 #define UART_AP7816B_T0_ADTI_L_SHIFT 0
mbed_official 363:12a245e5c745 8082 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
mbed_official 363:12a245e5c745 8083 /* WP7816A_T0 Bit Fields */
mbed_official 363:12a245e5c745 8084 #define UART_WP7816A_T0_WI_H_MASK 0xFFu
mbed_official 363:12a245e5c745 8085 #define UART_WP7816A_T0_WI_H_SHIFT 0
mbed_official 363:12a245e5c745 8086 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
mbed_official 363:12a245e5c745 8087 /* WP7816B_T0 Bit Fields */
mbed_official 363:12a245e5c745 8088 #define UART_WP7816B_T0_WI_L_MASK 0xFFu
mbed_official 363:12a245e5c745 8089 #define UART_WP7816B_T0_WI_L_SHIFT 0
mbed_official 363:12a245e5c745 8090 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
mbed_official 363:12a245e5c745 8091 /* WP7816A_T1 Bit Fields */
mbed_official 363:12a245e5c745 8092 #define UART_WP7816A_T1_BWI_H_MASK 0xFFu
mbed_official 363:12a245e5c745 8093 #define UART_WP7816A_T1_BWI_H_SHIFT 0
mbed_official 363:12a245e5c745 8094 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
mbed_official 363:12a245e5c745 8095 /* WP7816B_T1 Bit Fields */
mbed_official 363:12a245e5c745 8096 #define UART_WP7816B_T1_BWI_L_MASK 0xFFu
mbed_official 363:12a245e5c745 8097 #define UART_WP7816B_T1_BWI_L_SHIFT 0
mbed_official 363:12a245e5c745 8098 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
mbed_official 363:12a245e5c745 8099 /* WGP7816_T1 Bit Fields */
mbed_official 363:12a245e5c745 8100 #define UART_WGP7816_T1_BGI_MASK 0xFu
mbed_official 363:12a245e5c745 8101 #define UART_WGP7816_T1_BGI_SHIFT 0
mbed_official 363:12a245e5c745 8102 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
mbed_official 363:12a245e5c745 8103 #define UART_WGP7816_T1_CWI1_MASK 0xF0u
mbed_official 363:12a245e5c745 8104 #define UART_WGP7816_T1_CWI1_SHIFT 4
mbed_official 363:12a245e5c745 8105 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
mbed_official 363:12a245e5c745 8106 /* WP7816C_T1 Bit Fields */
mbed_official 363:12a245e5c745 8107 #define UART_WP7816C_T1_CWI2_MASK 0x1Fu
mbed_official 363:12a245e5c745 8108 #define UART_WP7816C_T1_CWI2_SHIFT 0
mbed_official 363:12a245e5c745 8109 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
mbed_official 363:12a245e5c745 8110
mbed_official 363:12a245e5c745 8111 /*!
mbed_official 363:12a245e5c745 8112 * @}
mbed_official 363:12a245e5c745 8113 */ /* end of group UART_Register_Masks */
mbed_official 363:12a245e5c745 8114
mbed_official 363:12a245e5c745 8115
mbed_official 363:12a245e5c745 8116 /* UART - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 8117 /** Peripheral UART2 base address */
mbed_official 363:12a245e5c745 8118 #define UART2_BASE (0x4006C000u)
mbed_official 363:12a245e5c745 8119 /** Peripheral UART2 base pointer */
mbed_official 363:12a245e5c745 8120 #define UART2 ((UART_Type *)UART2_BASE)
mbed_official 363:12a245e5c745 8121 #define UART2_BASE_PTR (UART2)
mbed_official 363:12a245e5c745 8122 /** Array initializer of UART peripheral base addresses */
mbed_official 363:12a245e5c745 8123 #define UART_BASE_ADDRS { UART2_BASE }
mbed_official 363:12a245e5c745 8124 /** Array initializer of UART peripheral base pointers */
mbed_official 363:12a245e5c745 8125 #define UART_BASE_PTRS { UART2 }
mbed_official 363:12a245e5c745 8126 /** Interrupt vectors for the UART peripheral type */
mbed_official 363:12a245e5c745 8127 #define UART_RX_TX_IRQS { UART2_FLEXIO_IRQn }
mbed_official 363:12a245e5c745 8128 #define UART_ERR_IRQS { UART2_FLEXIO_IRQn }
mbed_official 363:12a245e5c745 8129
mbed_official 363:12a245e5c745 8130 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 8131 -- UART - Register accessor macros
mbed_official 363:12a245e5c745 8132 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 8133
mbed_official 363:12a245e5c745 8134 /*!
mbed_official 363:12a245e5c745 8135 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
mbed_official 363:12a245e5c745 8136 * @{
mbed_official 363:12a245e5c745 8137 */
mbed_official 363:12a245e5c745 8138
mbed_official 363:12a245e5c745 8139
mbed_official 363:12a245e5c745 8140 /* UART - Register instance definitions */
mbed_official 363:12a245e5c745 8141 /* UART2 */
mbed_official 363:12a245e5c745 8142 #define UART2_BDH UART_BDH_REG(UART2)
mbed_official 363:12a245e5c745 8143 #define UART2_BDL UART_BDL_REG(UART2)
mbed_official 363:12a245e5c745 8144 #define UART2_C1 UART_C1_REG(UART2)
mbed_official 363:12a245e5c745 8145 #define UART2_C2 UART_C2_REG(UART2)
mbed_official 363:12a245e5c745 8146 #define UART2_S1 UART_S1_REG(UART2)
mbed_official 363:12a245e5c745 8147 #define UART2_S2 UART_S2_REG(UART2)
mbed_official 363:12a245e5c745 8148 #define UART2_C3 UART_C3_REG(UART2)
mbed_official 363:12a245e5c745 8149 #define UART2_D UART_D_REG(UART2)
mbed_official 363:12a245e5c745 8150 #define UART2_MA1 UART_MA1_REG(UART2)
mbed_official 363:12a245e5c745 8151 #define UART2_MA2 UART_MA2_REG(UART2)
mbed_official 363:12a245e5c745 8152 #define UART2_C4 UART_C4_REG(UART2)
mbed_official 363:12a245e5c745 8153 #define UART2_C5 UART_C5_REG(UART2)
mbed_official 363:12a245e5c745 8154 #define UART2_C7816 UART_C7816_REG(UART2)
mbed_official 363:12a245e5c745 8155 #define UART2_IE7816 UART_IE7816_REG(UART2)
mbed_official 363:12a245e5c745 8156 #define UART2_IS7816 UART_IS7816_REG(UART2)
mbed_official 363:12a245e5c745 8157 #define UART2_WP7816 UART_WP7816_REG(UART2)
mbed_official 363:12a245e5c745 8158 #define UART2_WN7816 UART_WN7816_REG(UART2)
mbed_official 363:12a245e5c745 8159 #define UART2_WF7816 UART_WF7816_REG(UART2)
mbed_official 363:12a245e5c745 8160 #define UART2_ET7816 UART_ET7816_REG(UART2)
mbed_official 363:12a245e5c745 8161 #define UART2_TL7816 UART_TL7816_REG(UART2)
mbed_official 363:12a245e5c745 8162 #define UART2_AP7816A_T0 UART_AP7816A_T0_REG(UART2)
mbed_official 363:12a245e5c745 8163 #define UART2_AP7816B_T0 UART_AP7816B_T0_REG(UART2)
mbed_official 363:12a245e5c745 8164 #define UART2_WP7816A_T0 UART_WP7816A_T0_REG(UART2)
mbed_official 363:12a245e5c745 8165 #define UART2_WP7816A_T1 UART_WP7816A_T1_REG(UART2)
mbed_official 363:12a245e5c745 8166 #define UART2_WP7816B_T0 UART_WP7816B_T0_REG(UART2)
mbed_official 363:12a245e5c745 8167 #define UART2_WP7816B_T1 UART_WP7816B_T1_REG(UART2)
mbed_official 363:12a245e5c745 8168 #define UART2_WGP7816_T1 UART_WGP7816_T1_REG(UART2)
mbed_official 363:12a245e5c745 8169 #define UART2_WP7816C_T1 UART_WP7816C_T1_REG(UART2)
mbed_official 363:12a245e5c745 8170
mbed_official 363:12a245e5c745 8171 /*!
mbed_official 363:12a245e5c745 8172 * @}
mbed_official 363:12a245e5c745 8173 */ /* end of group UART_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 8174
mbed_official 363:12a245e5c745 8175
mbed_official 363:12a245e5c745 8176 /*!
mbed_official 363:12a245e5c745 8177 * @}
mbed_official 363:12a245e5c745 8178 */ /* end of group UART_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 8179
mbed_official 363:12a245e5c745 8180
mbed_official 363:12a245e5c745 8181 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 8182 -- USB Peripheral Access Layer
mbed_official 363:12a245e5c745 8183 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 8184
mbed_official 363:12a245e5c745 8185 /*!
mbed_official 363:12a245e5c745 8186 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
mbed_official 363:12a245e5c745 8187 * @{
mbed_official 363:12a245e5c745 8188 */
mbed_official 363:12a245e5c745 8189
mbed_official 363:12a245e5c745 8190 /** USB - Register Layout Typedef */
mbed_official 363:12a245e5c745 8191 typedef struct {
mbed_official 363:12a245e5c745 8192 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
mbed_official 363:12a245e5c745 8193 uint8_t RESERVED_0[3];
mbed_official 363:12a245e5c745 8194 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
mbed_official 363:12a245e5c745 8195 uint8_t RESERVED_1[3];
mbed_official 363:12a245e5c745 8196 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
mbed_official 363:12a245e5c745 8197 uint8_t RESERVED_2[3];
mbed_official 363:12a245e5c745 8198 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
mbed_official 363:12a245e5c745 8199 uint8_t RESERVED_3[15];
mbed_official 363:12a245e5c745 8200 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
mbed_official 363:12a245e5c745 8201 uint8_t RESERVED_4[99];
mbed_official 363:12a245e5c745 8202 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
mbed_official 363:12a245e5c745 8203 uint8_t RESERVED_5[3];
mbed_official 363:12a245e5c745 8204 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
mbed_official 363:12a245e5c745 8205 uint8_t RESERVED_6[3];
mbed_official 363:12a245e5c745 8206 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
mbed_official 363:12a245e5c745 8207 uint8_t RESERVED_7[3];
mbed_official 363:12a245e5c745 8208 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
mbed_official 363:12a245e5c745 8209 uint8_t RESERVED_8[3];
mbed_official 363:12a245e5c745 8210 __I uint8_t STAT; /**< Status register, offset: 0x90 */
mbed_official 363:12a245e5c745 8211 uint8_t RESERVED_9[3];
mbed_official 363:12a245e5c745 8212 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
mbed_official 363:12a245e5c745 8213 uint8_t RESERVED_10[3];
mbed_official 363:12a245e5c745 8214 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
mbed_official 363:12a245e5c745 8215 uint8_t RESERVED_11[3];
mbed_official 363:12a245e5c745 8216 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
mbed_official 363:12a245e5c745 8217 uint8_t RESERVED_12[3];
mbed_official 363:12a245e5c745 8218 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
mbed_official 363:12a245e5c745 8219 uint8_t RESERVED_13[3];
mbed_official 363:12a245e5c745 8220 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
mbed_official 363:12a245e5c745 8221 uint8_t RESERVED_14[11];
mbed_official 363:12a245e5c745 8222 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
mbed_official 363:12a245e5c745 8223 uint8_t RESERVED_15[3];
mbed_official 363:12a245e5c745 8224 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
mbed_official 363:12a245e5c745 8225 uint8_t RESERVED_16[11];
mbed_official 363:12a245e5c745 8226 struct { /* offset: 0xC0, array step: 0x4 */
mbed_official 363:12a245e5c745 8227 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
mbed_official 363:12a245e5c745 8228 uint8_t RESERVED_0[3];
mbed_official 363:12a245e5c745 8229 } ENDPOINT[16];
mbed_official 363:12a245e5c745 8230 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
mbed_official 363:12a245e5c745 8231 uint8_t RESERVED_17[3];
mbed_official 363:12a245e5c745 8232 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
mbed_official 363:12a245e5c745 8233 uint8_t RESERVED_18[3];
mbed_official 363:12a245e5c745 8234 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
mbed_official 363:12a245e5c745 8235 uint8_t RESERVED_19[3];
mbed_official 363:12a245e5c745 8236 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
mbed_official 363:12a245e5c745 8237 uint8_t RESERVED_20[7];
mbed_official 363:12a245e5c745 8238 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
mbed_official 363:12a245e5c745 8239 uint8_t RESERVED_21[43];
mbed_official 363:12a245e5c745 8240 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
mbed_official 363:12a245e5c745 8241 uint8_t RESERVED_22[3];
mbed_official 363:12a245e5c745 8242 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
mbed_official 363:12a245e5c745 8243 uint8_t RESERVED_23[15];
mbed_official 363:12a245e5c745 8244 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
mbed_official 363:12a245e5c745 8245 uint8_t RESERVED_24[7];
mbed_official 363:12a245e5c745 8246 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
mbed_official 363:12a245e5c745 8247 } USB_Type, *USB_MemMapPtr;
mbed_official 363:12a245e5c745 8248
mbed_official 363:12a245e5c745 8249 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 8250 -- USB - Register accessor macros
mbed_official 363:12a245e5c745 8251 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 8252
mbed_official 363:12a245e5c745 8253 /*!
mbed_official 363:12a245e5c745 8254 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
mbed_official 363:12a245e5c745 8255 * @{
mbed_official 363:12a245e5c745 8256 */
mbed_official 363:12a245e5c745 8257
mbed_official 363:12a245e5c745 8258
mbed_official 363:12a245e5c745 8259 /* USB - Register accessors */
mbed_official 363:12a245e5c745 8260 #define USB_PERID_REG(base) ((base)->PERID)
mbed_official 363:12a245e5c745 8261 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
mbed_official 363:12a245e5c745 8262 #define USB_REV_REG(base) ((base)->REV)
mbed_official 363:12a245e5c745 8263 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
mbed_official 363:12a245e5c745 8264 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
mbed_official 363:12a245e5c745 8265 #define USB_ISTAT_REG(base) ((base)->ISTAT)
mbed_official 363:12a245e5c745 8266 #define USB_INTEN_REG(base) ((base)->INTEN)
mbed_official 363:12a245e5c745 8267 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
mbed_official 363:12a245e5c745 8268 #define USB_ERREN_REG(base) ((base)->ERREN)
mbed_official 363:12a245e5c745 8269 #define USB_STAT_REG(base) ((base)->STAT)
mbed_official 363:12a245e5c745 8270 #define USB_CTL_REG(base) ((base)->CTL)
mbed_official 363:12a245e5c745 8271 #define USB_ADDR_REG(base) ((base)->ADDR)
mbed_official 363:12a245e5c745 8272 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
mbed_official 363:12a245e5c745 8273 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
mbed_official 363:12a245e5c745 8274 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
mbed_official 363:12a245e5c745 8275 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
mbed_official 363:12a245e5c745 8276 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
mbed_official 363:12a245e5c745 8277 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
mbed_official 363:12a245e5c745 8278 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
mbed_official 363:12a245e5c745 8279 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
mbed_official 363:12a245e5c745 8280 #define USB_CONTROL_REG(base) ((base)->CONTROL)
mbed_official 363:12a245e5c745 8281 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
mbed_official 363:12a245e5c745 8282 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
mbed_official 363:12a245e5c745 8283 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
mbed_official 363:12a245e5c745 8284 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
mbed_official 363:12a245e5c745 8285 #define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN)
mbed_official 363:12a245e5c745 8286 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
mbed_official 363:12a245e5c745 8287
mbed_official 363:12a245e5c745 8288 /*!
mbed_official 363:12a245e5c745 8289 * @}
mbed_official 363:12a245e5c745 8290 */ /* end of group USB_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 8291
mbed_official 363:12a245e5c745 8292
mbed_official 363:12a245e5c745 8293 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 8294 -- USB Register Masks
mbed_official 363:12a245e5c745 8295 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 8296
mbed_official 363:12a245e5c745 8297 /*!
mbed_official 363:12a245e5c745 8298 * @addtogroup USB_Register_Masks USB Register Masks
mbed_official 363:12a245e5c745 8299 * @{
mbed_official 363:12a245e5c745 8300 */
mbed_official 363:12a245e5c745 8301
mbed_official 363:12a245e5c745 8302 /* PERID Bit Fields */
mbed_official 363:12a245e5c745 8303 #define USB_PERID_ID_MASK 0x3Fu
mbed_official 363:12a245e5c745 8304 #define USB_PERID_ID_SHIFT 0
mbed_official 363:12a245e5c745 8305 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
mbed_official 363:12a245e5c745 8306 /* IDCOMP Bit Fields */
mbed_official 363:12a245e5c745 8307 #define USB_IDCOMP_NID_MASK 0x3Fu
mbed_official 363:12a245e5c745 8308 #define USB_IDCOMP_NID_SHIFT 0
mbed_official 363:12a245e5c745 8309 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
mbed_official 363:12a245e5c745 8310 /* REV Bit Fields */
mbed_official 363:12a245e5c745 8311 #define USB_REV_REV_MASK 0xFFu
mbed_official 363:12a245e5c745 8312 #define USB_REV_REV_SHIFT 0
mbed_official 363:12a245e5c745 8313 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
mbed_official 363:12a245e5c745 8314 /* ADDINFO Bit Fields */
mbed_official 363:12a245e5c745 8315 #define USB_ADDINFO_IEHOST_MASK 0x1u
mbed_official 363:12a245e5c745 8316 #define USB_ADDINFO_IEHOST_SHIFT 0
mbed_official 363:12a245e5c745 8317 /* OTGCTL Bit Fields */
mbed_official 363:12a245e5c745 8318 #define USB_OTGCTL_DPHIGH_MASK 0x80u
mbed_official 363:12a245e5c745 8319 #define USB_OTGCTL_DPHIGH_SHIFT 7
mbed_official 363:12a245e5c745 8320 /* ISTAT Bit Fields */
mbed_official 363:12a245e5c745 8321 #define USB_ISTAT_USBRST_MASK 0x1u
mbed_official 363:12a245e5c745 8322 #define USB_ISTAT_USBRST_SHIFT 0
mbed_official 363:12a245e5c745 8323 #define USB_ISTAT_ERROR_MASK 0x2u
mbed_official 363:12a245e5c745 8324 #define USB_ISTAT_ERROR_SHIFT 1
mbed_official 363:12a245e5c745 8325 #define USB_ISTAT_SOFTOK_MASK 0x4u
mbed_official 363:12a245e5c745 8326 #define USB_ISTAT_SOFTOK_SHIFT 2
mbed_official 363:12a245e5c745 8327 #define USB_ISTAT_TOKDNE_MASK 0x8u
mbed_official 363:12a245e5c745 8328 #define USB_ISTAT_TOKDNE_SHIFT 3
mbed_official 363:12a245e5c745 8329 #define USB_ISTAT_SLEEP_MASK 0x10u
mbed_official 363:12a245e5c745 8330 #define USB_ISTAT_SLEEP_SHIFT 4
mbed_official 363:12a245e5c745 8331 #define USB_ISTAT_RESUME_MASK 0x20u
mbed_official 363:12a245e5c745 8332 #define USB_ISTAT_RESUME_SHIFT 5
mbed_official 363:12a245e5c745 8333 #define USB_ISTAT_STALL_MASK 0x80u
mbed_official 363:12a245e5c745 8334 #define USB_ISTAT_STALL_SHIFT 7
mbed_official 363:12a245e5c745 8335 /* INTEN Bit Fields */
mbed_official 363:12a245e5c745 8336 #define USB_INTEN_USBRSTEN_MASK 0x1u
mbed_official 363:12a245e5c745 8337 #define USB_INTEN_USBRSTEN_SHIFT 0
mbed_official 363:12a245e5c745 8338 #define USB_INTEN_ERROREN_MASK 0x2u
mbed_official 363:12a245e5c745 8339 #define USB_INTEN_ERROREN_SHIFT 1
mbed_official 363:12a245e5c745 8340 #define USB_INTEN_SOFTOKEN_MASK 0x4u
mbed_official 363:12a245e5c745 8341 #define USB_INTEN_SOFTOKEN_SHIFT 2
mbed_official 363:12a245e5c745 8342 #define USB_INTEN_TOKDNEEN_MASK 0x8u
mbed_official 363:12a245e5c745 8343 #define USB_INTEN_TOKDNEEN_SHIFT 3
mbed_official 363:12a245e5c745 8344 #define USB_INTEN_SLEEPEN_MASK 0x10u
mbed_official 363:12a245e5c745 8345 #define USB_INTEN_SLEEPEN_SHIFT 4
mbed_official 363:12a245e5c745 8346 #define USB_INTEN_RESUMEEN_MASK 0x20u
mbed_official 363:12a245e5c745 8347 #define USB_INTEN_RESUMEEN_SHIFT 5
mbed_official 363:12a245e5c745 8348 #define USB_INTEN_STALLEN_MASK 0x80u
mbed_official 363:12a245e5c745 8349 #define USB_INTEN_STALLEN_SHIFT 7
mbed_official 363:12a245e5c745 8350 /* ERRSTAT Bit Fields */
mbed_official 363:12a245e5c745 8351 #define USB_ERRSTAT_PIDERR_MASK 0x1u
mbed_official 363:12a245e5c745 8352 #define USB_ERRSTAT_PIDERR_SHIFT 0
mbed_official 363:12a245e5c745 8353 #define USB_ERRSTAT_CRC5_MASK 0x2u
mbed_official 363:12a245e5c745 8354 #define USB_ERRSTAT_CRC5_SHIFT 1
mbed_official 363:12a245e5c745 8355 #define USB_ERRSTAT_CRC16_MASK 0x4u
mbed_official 363:12a245e5c745 8356 #define USB_ERRSTAT_CRC16_SHIFT 2
mbed_official 363:12a245e5c745 8357 #define USB_ERRSTAT_DFN8_MASK 0x8u
mbed_official 363:12a245e5c745 8358 #define USB_ERRSTAT_DFN8_SHIFT 3
mbed_official 363:12a245e5c745 8359 #define USB_ERRSTAT_BTOERR_MASK 0x10u
mbed_official 363:12a245e5c745 8360 #define USB_ERRSTAT_BTOERR_SHIFT 4
mbed_official 363:12a245e5c745 8361 #define USB_ERRSTAT_DMAERR_MASK 0x20u
mbed_official 363:12a245e5c745 8362 #define USB_ERRSTAT_DMAERR_SHIFT 5
mbed_official 363:12a245e5c745 8363 #define USB_ERRSTAT_BTSERR_MASK 0x80u
mbed_official 363:12a245e5c745 8364 #define USB_ERRSTAT_BTSERR_SHIFT 7
mbed_official 363:12a245e5c745 8365 /* ERREN Bit Fields */
mbed_official 363:12a245e5c745 8366 #define USB_ERREN_PIDERREN_MASK 0x1u
mbed_official 363:12a245e5c745 8367 #define USB_ERREN_PIDERREN_SHIFT 0
mbed_official 363:12a245e5c745 8368 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
mbed_official 363:12a245e5c745 8369 #define USB_ERREN_CRC5EOFEN_SHIFT 1
mbed_official 363:12a245e5c745 8370 #define USB_ERREN_CRC16EN_MASK 0x4u
mbed_official 363:12a245e5c745 8371 #define USB_ERREN_CRC16EN_SHIFT 2
mbed_official 363:12a245e5c745 8372 #define USB_ERREN_DFN8EN_MASK 0x8u
mbed_official 363:12a245e5c745 8373 #define USB_ERREN_DFN8EN_SHIFT 3
mbed_official 363:12a245e5c745 8374 #define USB_ERREN_BTOERREN_MASK 0x10u
mbed_official 363:12a245e5c745 8375 #define USB_ERREN_BTOERREN_SHIFT 4
mbed_official 363:12a245e5c745 8376 #define USB_ERREN_DMAERREN_MASK 0x20u
mbed_official 363:12a245e5c745 8377 #define USB_ERREN_DMAERREN_SHIFT 5
mbed_official 363:12a245e5c745 8378 #define USB_ERREN_BTSERREN_MASK 0x80u
mbed_official 363:12a245e5c745 8379 #define USB_ERREN_BTSERREN_SHIFT 7
mbed_official 363:12a245e5c745 8380 /* STAT Bit Fields */
mbed_official 363:12a245e5c745 8381 #define USB_STAT_ODD_MASK 0x4u
mbed_official 363:12a245e5c745 8382 #define USB_STAT_ODD_SHIFT 2
mbed_official 363:12a245e5c745 8383 #define USB_STAT_TX_MASK 0x8u
mbed_official 363:12a245e5c745 8384 #define USB_STAT_TX_SHIFT 3
mbed_official 363:12a245e5c745 8385 #define USB_STAT_ENDP_MASK 0xF0u
mbed_official 363:12a245e5c745 8386 #define USB_STAT_ENDP_SHIFT 4
mbed_official 363:12a245e5c745 8387 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
mbed_official 363:12a245e5c745 8388 /* CTL Bit Fields */
mbed_official 363:12a245e5c745 8389 #define USB_CTL_USBENSOFEN_MASK 0x1u
mbed_official 363:12a245e5c745 8390 #define USB_CTL_USBENSOFEN_SHIFT 0
mbed_official 363:12a245e5c745 8391 #define USB_CTL_ODDRST_MASK 0x2u
mbed_official 363:12a245e5c745 8392 #define USB_CTL_ODDRST_SHIFT 1
mbed_official 363:12a245e5c745 8393 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
mbed_official 363:12a245e5c745 8394 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
mbed_official 363:12a245e5c745 8395 #define USB_CTL_SE0_MASK 0x40u
mbed_official 363:12a245e5c745 8396 #define USB_CTL_SE0_SHIFT 6
mbed_official 363:12a245e5c745 8397 #define USB_CTL_JSTATE_MASK 0x80u
mbed_official 363:12a245e5c745 8398 #define USB_CTL_JSTATE_SHIFT 7
mbed_official 363:12a245e5c745 8399 /* ADDR Bit Fields */
mbed_official 363:12a245e5c745 8400 #define USB_ADDR_ADDR_MASK 0x7Fu
mbed_official 363:12a245e5c745 8401 #define USB_ADDR_ADDR_SHIFT 0
mbed_official 363:12a245e5c745 8402 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
mbed_official 363:12a245e5c745 8403 /* BDTPAGE1 Bit Fields */
mbed_official 363:12a245e5c745 8404 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
mbed_official 363:12a245e5c745 8405 #define USB_BDTPAGE1_BDTBA_SHIFT 1
mbed_official 363:12a245e5c745 8406 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
mbed_official 363:12a245e5c745 8407 /* FRMNUML Bit Fields */
mbed_official 363:12a245e5c745 8408 #define USB_FRMNUML_FRM_MASK 0xFFu
mbed_official 363:12a245e5c745 8409 #define USB_FRMNUML_FRM_SHIFT 0
mbed_official 363:12a245e5c745 8410 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
mbed_official 363:12a245e5c745 8411 /* FRMNUMH Bit Fields */
mbed_official 363:12a245e5c745 8412 #define USB_FRMNUMH_FRM_MASK 0x7u
mbed_official 363:12a245e5c745 8413 #define USB_FRMNUMH_FRM_SHIFT 0
mbed_official 363:12a245e5c745 8414 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
mbed_official 363:12a245e5c745 8415 /* BDTPAGE2 Bit Fields */
mbed_official 363:12a245e5c745 8416 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
mbed_official 363:12a245e5c745 8417 #define USB_BDTPAGE2_BDTBA_SHIFT 0
mbed_official 363:12a245e5c745 8418 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
mbed_official 363:12a245e5c745 8419 /* BDTPAGE3 Bit Fields */
mbed_official 363:12a245e5c745 8420 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
mbed_official 363:12a245e5c745 8421 #define USB_BDTPAGE3_BDTBA_SHIFT 0
mbed_official 363:12a245e5c745 8422 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
mbed_official 363:12a245e5c745 8423 /* ENDPT Bit Fields */
mbed_official 363:12a245e5c745 8424 #define USB_ENDPT_EPHSHK_MASK 0x1u
mbed_official 363:12a245e5c745 8425 #define USB_ENDPT_EPHSHK_SHIFT 0
mbed_official 363:12a245e5c745 8426 #define USB_ENDPT_EPSTALL_MASK 0x2u
mbed_official 363:12a245e5c745 8427 #define USB_ENDPT_EPSTALL_SHIFT 1
mbed_official 363:12a245e5c745 8428 #define USB_ENDPT_EPTXEN_MASK 0x4u
mbed_official 363:12a245e5c745 8429 #define USB_ENDPT_EPTXEN_SHIFT 2
mbed_official 363:12a245e5c745 8430 #define USB_ENDPT_EPRXEN_MASK 0x8u
mbed_official 363:12a245e5c745 8431 #define USB_ENDPT_EPRXEN_SHIFT 3
mbed_official 363:12a245e5c745 8432 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
mbed_official 363:12a245e5c745 8433 #define USB_ENDPT_EPCTLDIS_SHIFT 4
mbed_official 363:12a245e5c745 8434 /* USBCTRL Bit Fields */
mbed_official 363:12a245e5c745 8435 #define USB_USBCTRL_PDE_MASK 0x40u
mbed_official 363:12a245e5c745 8436 #define USB_USBCTRL_PDE_SHIFT 6
mbed_official 363:12a245e5c745 8437 #define USB_USBCTRL_SUSP_MASK 0x80u
mbed_official 363:12a245e5c745 8438 #define USB_USBCTRL_SUSP_SHIFT 7
mbed_official 363:12a245e5c745 8439 /* OBSERVE Bit Fields */
mbed_official 363:12a245e5c745 8440 #define USB_OBSERVE_DMPD_MASK 0x10u
mbed_official 363:12a245e5c745 8441 #define USB_OBSERVE_DMPD_SHIFT 4
mbed_official 363:12a245e5c745 8442 #define USB_OBSERVE_DPPD_MASK 0x40u
mbed_official 363:12a245e5c745 8443 #define USB_OBSERVE_DPPD_SHIFT 6
mbed_official 363:12a245e5c745 8444 #define USB_OBSERVE_DPPU_MASK 0x80u
mbed_official 363:12a245e5c745 8445 #define USB_OBSERVE_DPPU_SHIFT 7
mbed_official 363:12a245e5c745 8446 /* CONTROL Bit Fields */
mbed_official 363:12a245e5c745 8447 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
mbed_official 363:12a245e5c745 8448 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
mbed_official 363:12a245e5c745 8449 /* USBTRC0 Bit Fields */
mbed_official 363:12a245e5c745 8450 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
mbed_official 363:12a245e5c745 8451 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
mbed_official 363:12a245e5c745 8452 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
mbed_official 363:12a245e5c745 8453 #define USB_USBTRC0_SYNC_DET_SHIFT 1
mbed_official 363:12a245e5c745 8454 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
mbed_official 363:12a245e5c745 8455 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
mbed_official 363:12a245e5c745 8456 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
mbed_official 363:12a245e5c745 8457 #define USB_USBTRC0_USBRESMEN_SHIFT 5
mbed_official 363:12a245e5c745 8458 #define USB_USBTRC0_USBRESET_MASK 0x80u
mbed_official 363:12a245e5c745 8459 #define USB_USBTRC0_USBRESET_SHIFT 7
mbed_official 363:12a245e5c745 8460 /* USBFRMADJUST Bit Fields */
mbed_official 363:12a245e5c745 8461 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
mbed_official 363:12a245e5c745 8462 #define USB_USBFRMADJUST_ADJ_SHIFT 0
mbed_official 363:12a245e5c745 8463 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
mbed_official 363:12a245e5c745 8464 /* CLK_RECOVER_CTRL Bit Fields */
mbed_official 363:12a245e5c745 8465 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
mbed_official 363:12a245e5c745 8466 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
mbed_official 363:12a245e5c745 8467 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
mbed_official 363:12a245e5c745 8468 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
mbed_official 363:12a245e5c745 8469 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
mbed_official 363:12a245e5c745 8470 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
mbed_official 363:12a245e5c745 8471 /* CLK_RECOVER_IRC_EN Bit Fields */
mbed_official 363:12a245e5c745 8472 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
mbed_official 363:12a245e5c745 8473 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
mbed_official 363:12a245e5c745 8474 /* CLK_RECOVER_INT_EN Bit Fields */
mbed_official 363:12a245e5c745 8475 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
mbed_official 363:12a245e5c745 8476 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
mbed_official 363:12a245e5c745 8477 /* CLK_RECOVER_INT_STATUS Bit Fields */
mbed_official 363:12a245e5c745 8478 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
mbed_official 363:12a245e5c745 8479 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
mbed_official 363:12a245e5c745 8480
mbed_official 363:12a245e5c745 8481 /*!
mbed_official 363:12a245e5c745 8482 * @}
mbed_official 363:12a245e5c745 8483 */ /* end of group USB_Register_Masks */
mbed_official 363:12a245e5c745 8484
mbed_official 363:12a245e5c745 8485
mbed_official 363:12a245e5c745 8486 /* USB - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 8487 /** Peripheral USB0 base address */
mbed_official 363:12a245e5c745 8488 #define USB0_BASE (0x40072000u)
mbed_official 363:12a245e5c745 8489 /** Peripheral USB0 base pointer */
mbed_official 363:12a245e5c745 8490 #define USB0 ((USB_Type *)USB0_BASE)
mbed_official 363:12a245e5c745 8491 #define USB0_BASE_PTR (USB0)
mbed_official 363:12a245e5c745 8492 /** Array initializer of USB peripheral base addresses */
mbed_official 363:12a245e5c745 8493 #define USB_BASE_ADDRS { USB0_BASE }
mbed_official 363:12a245e5c745 8494 /** Array initializer of USB peripheral base pointers */
mbed_official 363:12a245e5c745 8495 #define USB_BASE_PTRS { USB0 }
mbed_official 363:12a245e5c745 8496 /** Interrupt vectors for the USB peripheral type */
mbed_official 363:12a245e5c745 8497 #define USB_IRQS { USB0_IRQn }
mbed_official 363:12a245e5c745 8498
mbed_official 363:12a245e5c745 8499 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 8500 -- USB - Register accessor macros
mbed_official 363:12a245e5c745 8501 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 8502
mbed_official 363:12a245e5c745 8503 /*!
mbed_official 363:12a245e5c745 8504 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
mbed_official 363:12a245e5c745 8505 * @{
mbed_official 363:12a245e5c745 8506 */
mbed_official 363:12a245e5c745 8507
mbed_official 363:12a245e5c745 8508
mbed_official 363:12a245e5c745 8509 /* USB - Register instance definitions */
mbed_official 363:12a245e5c745 8510 /* USB0 */
mbed_official 363:12a245e5c745 8511 #define USB0_PERID USB_PERID_REG(USB0)
mbed_official 363:12a245e5c745 8512 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
mbed_official 363:12a245e5c745 8513 #define USB0_REV USB_REV_REG(USB0)
mbed_official 363:12a245e5c745 8514 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
mbed_official 363:12a245e5c745 8515 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
mbed_official 363:12a245e5c745 8516 #define USB0_ISTAT USB_ISTAT_REG(USB0)
mbed_official 363:12a245e5c745 8517 #define USB0_INTEN USB_INTEN_REG(USB0)
mbed_official 363:12a245e5c745 8518 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
mbed_official 363:12a245e5c745 8519 #define USB0_ERREN USB_ERREN_REG(USB0)
mbed_official 363:12a245e5c745 8520 #define USB0_STAT USB_STAT_REG(USB0)
mbed_official 363:12a245e5c745 8521 #define USB0_CTL USB_CTL_REG(USB0)
mbed_official 363:12a245e5c745 8522 #define USB0_ADDR USB_ADDR_REG(USB0)
mbed_official 363:12a245e5c745 8523 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
mbed_official 363:12a245e5c745 8524 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
mbed_official 363:12a245e5c745 8525 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
mbed_official 363:12a245e5c745 8526 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
mbed_official 363:12a245e5c745 8527 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
mbed_official 363:12a245e5c745 8528 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
mbed_official 363:12a245e5c745 8529 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
mbed_official 363:12a245e5c745 8530 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
mbed_official 363:12a245e5c745 8531 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
mbed_official 363:12a245e5c745 8532 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
mbed_official 363:12a245e5c745 8533 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
mbed_official 363:12a245e5c745 8534 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
mbed_official 363:12a245e5c745 8535 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
mbed_official 363:12a245e5c745 8536 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
mbed_official 363:12a245e5c745 8537 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
mbed_official 363:12a245e5c745 8538 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
mbed_official 363:12a245e5c745 8539 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
mbed_official 363:12a245e5c745 8540 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
mbed_official 363:12a245e5c745 8541 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
mbed_official 363:12a245e5c745 8542 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
mbed_official 363:12a245e5c745 8543 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
mbed_official 363:12a245e5c745 8544 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
mbed_official 363:12a245e5c745 8545 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
mbed_official 363:12a245e5c745 8546 #define USB0_CONTROL USB_CONTROL_REG(USB0)
mbed_official 363:12a245e5c745 8547 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
mbed_official 363:12a245e5c745 8548 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
mbed_official 363:12a245e5c745 8549 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
mbed_official 363:12a245e5c745 8550 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
mbed_official 363:12a245e5c745 8551 #define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0)
mbed_official 363:12a245e5c745 8552 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
mbed_official 363:12a245e5c745 8553
mbed_official 363:12a245e5c745 8554 /* USB - Register array accessors */
mbed_official 363:12a245e5c745 8555 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
mbed_official 363:12a245e5c745 8556
mbed_official 363:12a245e5c745 8557 /*!
mbed_official 363:12a245e5c745 8558 * @}
mbed_official 363:12a245e5c745 8559 */ /* end of group USB_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 8560
mbed_official 363:12a245e5c745 8561
mbed_official 363:12a245e5c745 8562 /*!
mbed_official 363:12a245e5c745 8563 * @}
mbed_official 363:12a245e5c745 8564 */ /* end of group USB_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 8565
mbed_official 363:12a245e5c745 8566
mbed_official 363:12a245e5c745 8567 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 8568 -- VREF Peripheral Access Layer
mbed_official 363:12a245e5c745 8569 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 8570
mbed_official 363:12a245e5c745 8571 /*!
mbed_official 363:12a245e5c745 8572 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
mbed_official 363:12a245e5c745 8573 * @{
mbed_official 363:12a245e5c745 8574 */
mbed_official 363:12a245e5c745 8575
mbed_official 363:12a245e5c745 8576 /** VREF - Register Layout Typedef */
mbed_official 363:12a245e5c745 8577 typedef struct {
mbed_official 363:12a245e5c745 8578 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
mbed_official 363:12a245e5c745 8579 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
mbed_official 363:12a245e5c745 8580 } VREF_Type, *VREF_MemMapPtr;
mbed_official 363:12a245e5c745 8581
mbed_official 363:12a245e5c745 8582 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 8583 -- VREF - Register accessor macros
mbed_official 363:12a245e5c745 8584 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 8585
mbed_official 363:12a245e5c745 8586 /*!
mbed_official 363:12a245e5c745 8587 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
mbed_official 363:12a245e5c745 8588 * @{
mbed_official 363:12a245e5c745 8589 */
mbed_official 363:12a245e5c745 8590
mbed_official 363:12a245e5c745 8591
mbed_official 363:12a245e5c745 8592 /* VREF - Register accessors */
mbed_official 363:12a245e5c745 8593 #define VREF_TRM_REG(base) ((base)->TRM)
mbed_official 363:12a245e5c745 8594 #define VREF_SC_REG(base) ((base)->SC)
mbed_official 363:12a245e5c745 8595
mbed_official 363:12a245e5c745 8596 /*!
mbed_official 363:12a245e5c745 8597 * @}
mbed_official 363:12a245e5c745 8598 */ /* end of group VREF_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 8599
mbed_official 363:12a245e5c745 8600
mbed_official 363:12a245e5c745 8601 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 8602 -- VREF Register Masks
mbed_official 363:12a245e5c745 8603 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 8604
mbed_official 363:12a245e5c745 8605 /*!
mbed_official 363:12a245e5c745 8606 * @addtogroup VREF_Register_Masks VREF Register Masks
mbed_official 363:12a245e5c745 8607 * @{
mbed_official 363:12a245e5c745 8608 */
mbed_official 363:12a245e5c745 8609
mbed_official 363:12a245e5c745 8610 /* TRM Bit Fields */
mbed_official 363:12a245e5c745 8611 #define VREF_TRM_TRIM_MASK 0x3Fu
mbed_official 363:12a245e5c745 8612 #define VREF_TRM_TRIM_SHIFT 0
mbed_official 363:12a245e5c745 8613 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
mbed_official 363:12a245e5c745 8614 #define VREF_TRM_CHOPEN_MASK 0x40u
mbed_official 363:12a245e5c745 8615 #define VREF_TRM_CHOPEN_SHIFT 6
mbed_official 363:12a245e5c745 8616 /* SC Bit Fields */
mbed_official 363:12a245e5c745 8617 #define VREF_SC_MODE_LV_MASK 0x3u
mbed_official 363:12a245e5c745 8618 #define VREF_SC_MODE_LV_SHIFT 0
mbed_official 363:12a245e5c745 8619 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
mbed_official 363:12a245e5c745 8620 #define VREF_SC_VREFST_MASK 0x4u
mbed_official 363:12a245e5c745 8621 #define VREF_SC_VREFST_SHIFT 2
mbed_official 363:12a245e5c745 8622 #define VREF_SC_ICOMPEN_MASK 0x20u
mbed_official 363:12a245e5c745 8623 #define VREF_SC_ICOMPEN_SHIFT 5
mbed_official 363:12a245e5c745 8624 #define VREF_SC_REGEN_MASK 0x40u
mbed_official 363:12a245e5c745 8625 #define VREF_SC_REGEN_SHIFT 6
mbed_official 363:12a245e5c745 8626 #define VREF_SC_VREFEN_MASK 0x80u
mbed_official 363:12a245e5c745 8627 #define VREF_SC_VREFEN_SHIFT 7
mbed_official 363:12a245e5c745 8628
mbed_official 363:12a245e5c745 8629 /*!
mbed_official 363:12a245e5c745 8630 * @}
mbed_official 363:12a245e5c745 8631 */ /* end of group VREF_Register_Masks */
mbed_official 363:12a245e5c745 8632
mbed_official 363:12a245e5c745 8633
mbed_official 363:12a245e5c745 8634 /* VREF - Peripheral instance base addresses */
mbed_official 363:12a245e5c745 8635 /** Peripheral VREF base address */
mbed_official 363:12a245e5c745 8636 #define VREF_BASE (0x40074000u)
mbed_official 363:12a245e5c745 8637 /** Peripheral VREF base pointer */
mbed_official 363:12a245e5c745 8638 #define VREF ((VREF_Type *)VREF_BASE)
mbed_official 363:12a245e5c745 8639 #define VREF_BASE_PTR (VREF)
mbed_official 363:12a245e5c745 8640 /** Array initializer of VREF peripheral base addresses */
mbed_official 363:12a245e5c745 8641 #define VREF_BASE_ADDRS { VREF_BASE }
mbed_official 363:12a245e5c745 8642 /** Array initializer of VREF peripheral base pointers */
mbed_official 363:12a245e5c745 8643 #define VREF_BASE_PTRS { VREF }
mbed_official 363:12a245e5c745 8644
mbed_official 363:12a245e5c745 8645 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 8646 -- VREF - Register accessor macros
mbed_official 363:12a245e5c745 8647 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 8648
mbed_official 363:12a245e5c745 8649 /*!
mbed_official 363:12a245e5c745 8650 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
mbed_official 363:12a245e5c745 8651 * @{
mbed_official 363:12a245e5c745 8652 */
mbed_official 363:12a245e5c745 8653
mbed_official 363:12a245e5c745 8654
mbed_official 363:12a245e5c745 8655 /* VREF - Register instance definitions */
mbed_official 363:12a245e5c745 8656 /* VREF */
mbed_official 363:12a245e5c745 8657 #define VREF_TRM VREF_TRM_REG(VREF)
mbed_official 363:12a245e5c745 8658 #define VREF_SC VREF_SC_REG(VREF)
mbed_official 363:12a245e5c745 8659
mbed_official 363:12a245e5c745 8660 /*!
mbed_official 363:12a245e5c745 8661 * @}
mbed_official 363:12a245e5c745 8662 */ /* end of group VREF_Register_Accessor_Macros */
mbed_official 363:12a245e5c745 8663
mbed_official 363:12a245e5c745 8664
mbed_official 363:12a245e5c745 8665 /*!
mbed_official 363:12a245e5c745 8666 * @}
mbed_official 363:12a245e5c745 8667 */ /* end of group VREF_Peripheral_Access_Layer */
mbed_official 363:12a245e5c745 8668
mbed_official 363:12a245e5c745 8669
mbed_official 363:12a245e5c745 8670 /*
mbed_official 363:12a245e5c745 8671 ** End of section using anonymous unions
mbed_official 363:12a245e5c745 8672 */
mbed_official 363:12a245e5c745 8673
mbed_official 363:12a245e5c745 8674 #if defined(__ARMCC_VERSION)
mbed_official 363:12a245e5c745 8675 #pragma pop
mbed_official 363:12a245e5c745 8676 #elif defined(__CWCC__)
mbed_official 363:12a245e5c745 8677 #pragma pop
mbed_official 363:12a245e5c745 8678 #elif defined(__GNUC__)
mbed_official 363:12a245e5c745 8679 /* leave anonymous unions enabled */
mbed_official 363:12a245e5c745 8680 #elif defined(__IAR_SYSTEMS_ICC__)
mbed_official 363:12a245e5c745 8681 #pragma language=default
mbed_official 363:12a245e5c745 8682 #else
mbed_official 363:12a245e5c745 8683 #error Not supported compiler type
mbed_official 363:12a245e5c745 8684 #endif
mbed_official 363:12a245e5c745 8685
mbed_official 363:12a245e5c745 8686 /*!
mbed_official 363:12a245e5c745 8687 * @}
mbed_official 363:12a245e5c745 8688 */ /* end of group Peripheral_access_layer */
mbed_official 363:12a245e5c745 8689
mbed_official 363:12a245e5c745 8690
mbed_official 363:12a245e5c745 8691 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 8692 -- Backward Compatibility
mbed_official 363:12a245e5c745 8693 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 8694
mbed_official 363:12a245e5c745 8695 /*!
mbed_official 363:12a245e5c745 8696 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
mbed_official 363:12a245e5c745 8697 * @{
mbed_official 363:12a245e5c745 8698 */
mbed_official 363:12a245e5c745 8699
mbed_official 363:12a245e5c745 8700 #define I2C_S1_RXAK_MASK I2C_S_RXAK_MASK
mbed_official 363:12a245e5c745 8701 #define I2C_S1_RXAK_SHIFT I2C_S_RXAK_SHIFT
mbed_official 363:12a245e5c745 8702 #define I2C_S1_IICIF_MASK I2C_S_IICIF_MASK
mbed_official 363:12a245e5c745 8703 #define I2C_S1_IICIF_SHIFT I2C_S_IICIF_SHIFTFT
mbed_official 363:12a245e5c745 8704 #define I2C_S1_SRW_MASK I2C_S_SRW_MASK
mbed_official 363:12a245e5c745 8705 #define I2C_S1_SRW_SHIFT I2C_S_SRW_SHIFT
mbed_official 363:12a245e5c745 8706 #define I2C_S1_RAM_MASK I2C_S_RAM_MASK
mbed_official 363:12a245e5c745 8707 #define I2C_S1_RAM_SHIFT I2C_S_RAM_SHIFT
mbed_official 363:12a245e5c745 8708 #define I2C_S1_ARBL_MASK I2C_S_ARBL_MASK
mbed_official 363:12a245e5c745 8709 #define I2C_S1_ARBL_SHIFT I2C_S_ARBL_SHIFT
mbed_official 363:12a245e5c745 8710 #define I2C_S1_BUSY_MASK I2C_S_BUSY_MASK
mbed_official 363:12a245e5c745 8711 #define I2C_S1_BUSY_SHIFT I2C_S_BUSY_SHIFT
mbed_official 363:12a245e5c745 8712 #define I2C_S1_IAAS_MASK I2C_S_IAAS_MASK
mbed_official 363:12a245e5c745 8713 #define I2C_S1_IAAS_SHIFT I2C_S_IAAS_SHIFT
mbed_official 363:12a245e5c745 8714 #define I2C_S1_TCF_MASK I2C_S_TCF_MASK
mbed_official 363:12a245e5c745 8715 #define I2C_S1_TCF_SHIFT I2C_S_TCF_SHIFT
mbed_official 363:12a245e5c745 8716 #define I2C_S1_REG(base) I2C_S_REG(base)
mbed_official 363:12a245e5c745 8717 #define I2C0_S1 I2C0_S
mbed_official 363:12a245e5c745 8718 #define I2C1_S1 I2C1_S
mbed_official 363:12a245e5c745 8719 #define ADC_BASES ADC_BASE_PTRS
mbed_official 363:12a245e5c745 8720 #define CMP_BASES CMP_BASE_PTRS
mbed_official 363:12a245e5c745 8721 #define DAC_BASES DAC_BASE_PTRS
mbed_official 363:12a245e5c745 8722 #define DMA_BASES DMA_BASE_PTRS
mbed_official 363:12a245e5c745 8723 #define DMAMUX_BASES DMAMUX_BASE_PTRS
mbed_official 363:12a245e5c745 8724 #define FLEXIO_BASES FLEXIO_BASE_PTRS
mbed_official 363:12a245e5c745 8725 #define FTFA_BASES FTFA_BASE_PTRS
mbed_official 363:12a245e5c745 8726 #define GPIO_BASES GPIO_BASE_PTRS
mbed_official 363:12a245e5c745 8727 #define I2C_BASES I2C_BASE_PTRS
mbed_official 363:12a245e5c745 8728 #define I2S_BASES I2S_BASE_PTRS
mbed_official 363:12a245e5c745 8729 #define LCD_BASES LCD_BASE_PTRS
mbed_official 363:12a245e5c745 8730 #define LLWU_BASES LLWU_BASE_PTRS
mbed_official 363:12a245e5c745 8731 #define LPTMR_BASES LPTMR_BASE_PTRS
mbed_official 363:12a245e5c745 8732 #define LPUART_BASES LPUART_BASE_PTRS
mbed_official 363:12a245e5c745 8733 #define MCG_BASES MCG_BASE_PTRS
mbed_official 363:12a245e5c745 8734 #define MCM_BASES MCM_BASE_PTRS
mbed_official 363:12a245e5c745 8735 #define MTB_BASES MTB_BASE_PTRS
mbed_official 363:12a245e5c745 8736 #define MTBDWT_BASES MTBDWT_BASE_PTRS
mbed_official 363:12a245e5c745 8737 #define NV_BASES NV_BASE_PTRS
mbed_official 363:12a245e5c745 8738 #define OSC_BASES OSC_BASE_PTRS
mbed_official 363:12a245e5c745 8739 #define PIT_BASES PIT_BASE_PTRS
mbed_official 363:12a245e5c745 8740 #define PMC_BASES PMC_BASE_PTRS
mbed_official 363:12a245e5c745 8741 #define PORT_BASES PORT_BASE_PTRS
mbed_official 363:12a245e5c745 8742 #define RCM_BASES RCM_BASE_PTRS
mbed_official 363:12a245e5c745 8743 #define ROM_BASES ROM_BASE_PTRS
mbed_official 363:12a245e5c745 8744 #define RTC_BASES RTC_BASE_PTRS
mbed_official 363:12a245e5c745 8745 #define SIM_BASES SIM_BASE_PTRS
mbed_official 363:12a245e5c745 8746 #define SMC_BASES SMC_BASE_PTRS
mbed_official 363:12a245e5c745 8747 #define SPI_BASES SPI_BASE_PTRS
mbed_official 363:12a245e5c745 8748 #define TPM_BASES TPM_BASE_PTRS
mbed_official 363:12a245e5c745 8749 #define UART_BASES UART_BASE_PTRS
mbed_official 363:12a245e5c745 8750 #define USB_BASES USB_BASE_PTRS
mbed_official 363:12a245e5c745 8751 #define VREF_BASES VREF_BASE_PTRS
mbed_official 363:12a245e5c745 8752 #define PTA_BASE_PTR GPIOA_BASE_PTR
mbed_official 363:12a245e5c745 8753 #define PTB_BASE_PTR GPIOB_BASE_PTR
mbed_official 363:12a245e5c745 8754 #define PTC_BASE_PTR GPIOC_BASE_PTR
mbed_official 363:12a245e5c745 8755 #define PTD_BASE_PTR GPIOD_BASE_PTR
mbed_official 363:12a245e5c745 8756 #define PTE_BASE_PTR GPIOE_BASE_PTR
mbed_official 363:12a245e5c745 8757 #define PTA_BASE GPIOA_BASE
mbed_official 363:12a245e5c745 8758 #define PTB_BASE GPIOB_BASE
mbed_official 363:12a245e5c745 8759 #define PTC_BASE GPIOC_BASE
mbed_official 363:12a245e5c745 8760 #define PTD_BASE GPIOD_BASE
mbed_official 363:12a245e5c745 8761 #define PTE_BASE GPIOE_BASE
mbed_official 363:12a245e5c745 8762 #define PTA GPIOA
mbed_official 363:12a245e5c745 8763 #define PTB GPIOB
mbed_official 363:12a245e5c745 8764 #define PTC GPIOC
mbed_official 363:12a245e5c745 8765 #define PTD GPIOD
mbed_official 363:12a245e5c745 8766 #define PTE GPIOE
mbed_official 363:12a245e5c745 8767 #define UART0_FLEXIO_IRQn UART2_FLEXIO_IRQn
mbed_official 363:12a245e5c745 8768 #define SIM_SOPT5_UART0ODE_MASK SIM_SOPT5_UART2ODE_MASK
mbed_official 363:12a245e5c745 8769 #define SIM_SOPT5_UART0ODE_SHIFT SIM_SOPT5_UART2ODE_SHIFT
mbed_official 363:12a245e5c745 8770 #define SIM_SCGC4_UART0_MASK SIM_SCGC4_UART2_MASK
mbed_official 363:12a245e5c745 8771 #define SIM_SCGC4_UART0_SHIFT SIM_SCGC4_UART2_SHIFT
mbed_official 363:12a245e5c745 8772 #define UART0_BASE UART2_BASE
mbed_official 363:12a245e5c745 8773 #define UART0 UART2
mbed_official 363:12a245e5c745 8774 #define UART0_BASE_PTR UART2_BASE_PTR
mbed_official 363:12a245e5c745 8775 #define UART0_BDH UART2_BDH
mbed_official 363:12a245e5c745 8776 #define UART0_BDL UART2_BDL
mbed_official 363:12a245e5c745 8777 #define UART0_C1 UART2_C1
mbed_official 363:12a245e5c745 8778 #define UART0_C2 UART2_C2
mbed_official 363:12a245e5c745 8779 #define UART0_S1 UART2_S1
mbed_official 363:12a245e5c745 8780 #define UART0_S2 UART2_S2
mbed_official 363:12a245e5c745 8781 #define UART0_C3 UART2_C3
mbed_official 363:12a245e5c745 8782 #define UART0_D UART2_D
mbed_official 363:12a245e5c745 8783 #define UART0_MA1 UART2_MA1
mbed_official 363:12a245e5c745 8784 #define UART0_MA2 UART2_MA2
mbed_official 363:12a245e5c745 8785 #define UART0_C4 UART2_C4
mbed_official 363:12a245e5c745 8786 #define UART0_C5 UART2_C5
mbed_official 363:12a245e5c745 8787 #define UART0_ED UART2_ED
mbed_official 363:12a245e5c745 8788 #define UART0_MODEM UART2_MODEM
mbed_official 363:12a245e5c745 8789 #define UART0_IR UART2_IR
mbed_official 363:12a245e5c745 8790 #define UART0_PFIFO UART2_PFIFO
mbed_official 363:12a245e5c745 8791 #define UART0_CFIFO UART2_CFIFO
mbed_official 363:12a245e5c745 8792 #define UART0_SFIFO UART2_SFIFO
mbed_official 363:12a245e5c745 8793 #define UART0_TWFIFO UART2_TWFIFO
mbed_official 363:12a245e5c745 8794 #define UART0_TCFIFO UART2_TCFIFO
mbed_official 363:12a245e5c745 8795 #define UART0_RWFIFO UART2_RWFIFO
mbed_official 363:12a245e5c745 8796 #define UART0_RCFIFO UART2_RCFIFO
mbed_official 363:12a245e5c745 8797 #define UART0_C7816 UART2_C7816
mbed_official 363:12a245e5c745 8798 #define UART0_IE7816 UART2_IE7816
mbed_official 363:12a245e5c745 8799 #define UART0_IS7816 UART2_IS7816
mbed_official 363:12a245e5c745 8800 #define UART0_WP7816 UART2_WP7816
mbed_official 363:12a245e5c745 8801 #define UART0_WN7816 UART2_WN7816
mbed_official 363:12a245e5c745 8802 #define UART0_WF7816 UART2_WF7816
mbed_official 363:12a245e5c745 8803 #define UART0_ET7816 UART2_ET7816
mbed_official 363:12a245e5c745 8804 #define UART0_TL7816 UART2_TL7816
mbed_official 363:12a245e5c745 8805 #define UART0_AP7816A_T0 UART2_AP7816A_T0
mbed_official 363:12a245e5c745 8806 #define UART0_AP7816B_T0 UART2_AP7816B_T0
mbed_official 363:12a245e5c745 8807 #define UART0_WP7816A_T0 UART2_WP7816A_T0
mbed_official 363:12a245e5c745 8808 #define UART0_WP7816A_T1 UART2_WP7816A_T1
mbed_official 363:12a245e5c745 8809 #define UART0_WP7816B_T0 UART2_WP7816B_T0
mbed_official 363:12a245e5c745 8810 #define UART0_WP7816B_T1 UART2_WP7816B_T1
mbed_official 363:12a245e5c745 8811 #define UART0_WGP7816_T1 UART2_WGP7816_T1
mbed_official 363:12a245e5c745 8812 #define UART0_WP7816C_T1 UART2_WP7816C_T1
mbed_official 363:12a245e5c745 8813 #define I2S0_MDR This_symb_has_been_deprecated
mbed_official 363:12a245e5c745 8814 #define I2S_MDR_DIVIDE_MASK This_symb_has_been_deprecated
mbed_official 363:12a245e5c745 8815 #define I2S_MDR_DIVIDE_SHIFT This_symb_has_been_deprecated
mbed_official 363:12a245e5c745 8816 #define I2S_MDR_DIVIDE(x) This_symb_has_been_deprecated
mbed_official 363:12a245e5c745 8817 #define I2S_MDR_FRACT_MASK This_symb_has_been_deprecated
mbed_official 363:12a245e5c745 8818 #define I2S_MDR_FRACT_SHIFT This_symb_has_been_deprecated
mbed_official 363:12a245e5c745 8819 #define I2S_MDR_FRACT(x) This_symb_has_been_deprecated
mbed_official 363:12a245e5c745 8820 #define I2S_MDR_REG(base) This_symb_has_been_deprecated
mbed_official 363:12a245e5c745 8821 #define CTL0 OTGCTL
mbed_official 363:12a245e5c745 8822 #define USB0_CTL0 USB0_OTGCTL
mbed_official 363:12a245e5c745 8823 #define USB_CTL0_REG(base) USB_OTGCTL_REG(base)
mbed_official 363:12a245e5c745 8824 #define USB_CTL0_DPHIGH_MASK USB_OTGCTL_DPHIGH_MASK
mbed_official 363:12a245e5c745 8825 #define USB_CTL0_DPHIGH_SHIFT USB_OTGCTL_DPHIGH_SHIFT
mbed_official 363:12a245e5c745 8826 #define CTL1 CTL
mbed_official 363:12a245e5c745 8827 #define USB0_CTL1 USB0_CTL
mbed_official 363:12a245e5c745 8828 #define USB_CTL1_REG(base) USB_CTL_REG(base)
mbed_official 363:12a245e5c745 8829 #define USB_CTL1_USBEN_MASK USB_CTL_USBEN_MASK
mbed_official 363:12a245e5c745 8830 #define USB_CTL1_USBEN_SHIFT USB_CTL_USBEN_SHIFT
mbed_official 363:12a245e5c745 8831 #define USB_CTL1_ODDRST_MASK USB_CTL_ODDRST_MASK
mbed_official 363:12a245e5c745 8832 #define USB_CTL1_ODDRST_SHIFT USB_CTL_ODDRST_SHIFT
mbed_official 363:12a245e5c745 8833 #define USB_CTL1_TXSUSPENDTOKENBUSY_MASK USB_CTL_TXSUSPENDTOKENBUSY_MASK
mbed_official 363:12a245e5c745 8834 #define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT USB_CTL_TXSUSPENDTOKENBUSY_SHIFT
mbed_official 363:12a245e5c745 8835 #define USB_CTL1_SE0_MASK USB_CTL_SE0_MASK
mbed_official 363:12a245e5c745 8836 #define USB_CTL1_SE0_SHIFT USB_CTL_SE0_SHIFT
mbed_official 363:12a245e5c745 8837 #define USB_CTL1_JSTATE_MASK USB_CTL_JSTATE_MASK
mbed_official 363:12a245e5c745 8838 #define USB_CTL1_JSTATE_SHIFT USB_CTL_JSTATE_SHIFT
mbed_official 363:12a245e5c745 8839 #define USB_CTL_USBEN_MASK USB_CTL_USBENSOFEN_MASK
mbed_official 363:12a245e5c745 8840 #define USB_CTL_USBEN_SHIFT USB_CTL_USBENSOFEN_SHIFT
mbed_official 363:12a245e5c745 8841
mbed_official 363:12a245e5c745 8842 /*!
mbed_official 363:12a245e5c745 8843 * @}
mbed_official 363:12a245e5c745 8844 */ /* end of group Backward_Compatibility_Symbols */
mbed_official 363:12a245e5c745 8845
mbed_official 363:12a245e5c745 8846
mbed_official 363:12a245e5c745 8847 #else /* #if !defined(MKL43Z4_H_) */
mbed_official 363:12a245e5c745 8848 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
mbed_official 363:12a245e5c745 8849 #if (MCU_MEM_MAP_VERSION != 0x0100u)
mbed_official 363:12a245e5c745 8850 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
mbed_official 363:12a245e5c745 8851 #warning There are included two not compatible versions of memory maps. Please check possible differences.
mbed_official 363:12a245e5c745 8852 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
mbed_official 363:12a245e5c745 8853 #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
mbed_official 363:12a245e5c745 8854 #endif /* #if !defined(MKL43Z4_H_) */
mbed_official 363:12a245e5c745 8855
mbed_official 363:12a245e5c745 8856 /* MKL43Z4.h, eof. */