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targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c@482:d9a48e768ce0, 2015-02-27 (annotated)
- Committer:
- mbed_official
- Date:
- Fri Feb 27 10:00:08 2015 +0000
- Revision:
- 482:d9a48e768ce0
- Parent:
- 460:3bcf9be0332c
Synchronized with git revision 43d7f387ec8e6fef8c03cb5e3a74f7b1596c8f8c
Full URL: https://github.com/mbedmicro/mbed/commit/43d7f387ec8e6fef8c03cb5e3a74f7b1596c8f8c/
RZ/A1H - Modify to support GCC and Fix some bugs of driver.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 390:35c2c1cf29cd | 1 | /* mbed Microcontroller Library |
mbed_official | 390:35c2c1cf29cd | 2 | * Copyright (c) 2006-2013 ARM Limited |
mbed_official | 390:35c2c1cf29cd | 3 | * |
mbed_official | 390:35c2c1cf29cd | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mbed_official | 390:35c2c1cf29cd | 5 | * you may not use this file except in compliance with the License. |
mbed_official | 390:35c2c1cf29cd | 6 | * You may obtain a copy of the License at |
mbed_official | 390:35c2c1cf29cd | 7 | * |
mbed_official | 390:35c2c1cf29cd | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mbed_official | 390:35c2c1cf29cd | 9 | * |
mbed_official | 390:35c2c1cf29cd | 10 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 390:35c2c1cf29cd | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 390:35c2c1cf29cd | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 390:35c2c1cf29cd | 13 | * See the License for the specific language governing permissions and |
mbed_official | 390:35c2c1cf29cd | 14 | * limitations under the License. |
mbed_official | 390:35c2c1cf29cd | 15 | */ |
mbed_official | 390:35c2c1cf29cd | 16 | #include <stddef.h> |
mbed_official | 390:35c2c1cf29cd | 17 | #include "us_ticker_api.h" |
mbed_official | 390:35c2c1cf29cd | 18 | #include "PeripheralNames.h" |
mbed_official | 430:d406b7919023 | 19 | #include "ostm_iodefine.h" |
mbed_official | 430:d406b7919023 | 20 | |
mbed_official | 430:d406b7919023 | 21 | #include "RZ_A1_Init.h" |
mbed_official | 430:d406b7919023 | 22 | #include "MBRZA1H.h" |
mbed_official | 390:35c2c1cf29cd | 23 | |
mbed_official | 430:d406b7919023 | 24 | #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn) |
mbed_official | 430:d406b7919023 | 25 | #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ |
mbed_official | 430:d406b7919023 | 26 | |
mbed_official | 430:d406b7919023 | 27 | #define US_TICKER_CLOCK_US_DEV (1000000) |
mbed_official | 390:35c2c1cf29cd | 28 | |
mbed_official | 390:35c2c1cf29cd | 29 | int us_ticker_inited = 0; |
mbed_official | 430:d406b7919023 | 30 | static double count_clock = 0; |
mbed_official | 437:0b72c0f86db6 | 31 | static uint32_t last_read = 0; |
mbed_official | 437:0b72c0f86db6 | 32 | static uint32_t wrap_arround = 0; |
mbed_official | 482:d9a48e768ce0 | 33 | static uint64_t ticker_us_last64 = 0; |
mbed_official | 390:35c2c1cf29cd | 34 | |
mbed_official | 390:35c2c1cf29cd | 35 | void us_ticker_interrupt(void) { |
mbed_official | 390:35c2c1cf29cd | 36 | us_ticker_irq_handler(); |
mbed_official | 390:35c2c1cf29cd | 37 | } |
mbed_official | 390:35c2c1cf29cd | 38 | |
mbed_official | 390:35c2c1cf29cd | 39 | void us_ticker_init(void) { |
mbed_official | 390:35c2c1cf29cd | 40 | if (us_ticker_inited) return; |
mbed_official | 390:35c2c1cf29cd | 41 | us_ticker_inited = 1; |
mbed_official | 437:0b72c0f86db6 | 42 | |
mbed_official | 430:d406b7919023 | 43 | /* set Counter Clock(us) */ |
mbed_official | 430:d406b7919023 | 44 | if (false == RZ_A1_IsClockMode0()) { |
mbed_official | 437:0b72c0f86db6 | 45 | count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); |
mbed_official | 430:d406b7919023 | 46 | } else { |
mbed_official | 437:0b72c0f86db6 | 47 | count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); |
mbed_official | 430:d406b7919023 | 48 | } |
mbed_official | 430:d406b7919023 | 49 | |
mbed_official | 390:35c2c1cf29cd | 50 | /* Power Control for Peripherals */ |
mbed_official | 430:d406b7919023 | 51 | CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */ |
mbed_official | 390:35c2c1cf29cd | 52 | |
mbed_official | 390:35c2c1cf29cd | 53 | // timer settings |
mbed_official | 430:d406b7919023 | 54 | OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */ |
mbed_official | 430:d406b7919023 | 55 | OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */ |
mbed_official | 390:35c2c1cf29cd | 56 | |
mbed_official | 430:d406b7919023 | 57 | OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */ |
mbed_official | 390:35c2c1cf29cd | 58 | |
mbed_official | 390:35c2c1cf29cd | 59 | // INTC settings |
mbed_official | 430:d406b7919023 | 60 | InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt); |
mbed_official | 430:d406b7919023 | 61 | GIC_SetPriority(US_TICKER_TIMER_IRQn, 5); |
mbed_official | 430:d406b7919023 | 62 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
mbed_official | 390:35c2c1cf29cd | 63 | } |
mbed_official | 390:35c2c1cf29cd | 64 | |
mbed_official | 482:d9a48e768ce0 | 65 | static uint64_t ticker_read_counter64(void) { |
mbed_official | 482:d9a48e768ce0 | 66 | uint32_t cnt_val; |
mbed_official | 482:d9a48e768ce0 | 67 | uint64_t cnt_val64; |
mbed_official | 437:0b72c0f86db6 | 68 | |
mbed_official | 390:35c2c1cf29cd | 69 | if (!us_ticker_inited) |
mbed_official | 390:35c2c1cf29cd | 70 | us_ticker_init(); |
mbed_official | 437:0b72c0f86db6 | 71 | |
mbed_official | 430:d406b7919023 | 72 | /* read counter */ |
mbed_official | 482:d9a48e768ce0 | 73 | cnt_val = OSTM1CNT; |
mbed_official | 482:d9a48e768ce0 | 74 | if (last_read > cnt_val) { |
mbed_official | 437:0b72c0f86db6 | 75 | wrap_arround++; |
mbed_official | 437:0b72c0f86db6 | 76 | } |
mbed_official | 482:d9a48e768ce0 | 77 | last_read = cnt_val; |
mbed_official | 482:d9a48e768ce0 | 78 | cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val; |
mbed_official | 482:d9a48e768ce0 | 79 | |
mbed_official | 482:d9a48e768ce0 | 80 | return cnt_val64; |
mbed_official | 482:d9a48e768ce0 | 81 | } |
mbed_official | 437:0b72c0f86db6 | 82 | |
mbed_official | 482:d9a48e768ce0 | 83 | uint32_t us_ticker_read() { |
mbed_official | 482:d9a48e768ce0 | 84 | uint64_t cnt_val64; |
mbed_official | 482:d9a48e768ce0 | 85 | uint64_t us_val64; |
mbed_official | 482:d9a48e768ce0 | 86 | int check_irq_masked; |
mbed_official | 482:d9a48e768ce0 | 87 | |
mbed_official | 482:d9a48e768ce0 | 88 | check_irq_masked = __disable_irq(); |
mbed_official | 482:d9a48e768ce0 | 89 | |
mbed_official | 482:d9a48e768ce0 | 90 | cnt_val64 = ticker_read_counter64(); |
mbed_official | 482:d9a48e768ce0 | 91 | us_val64 = (cnt_val64 / count_clock); |
mbed_official | 482:d9a48e768ce0 | 92 | ticker_us_last64 = us_val64; |
mbed_official | 460:3bcf9be0332c | 93 | |
mbed_official | 460:3bcf9be0332c | 94 | if (!check_irq_masked) { |
mbed_official | 460:3bcf9be0332c | 95 | __enable_irq(); |
mbed_official | 460:3bcf9be0332c | 96 | } |
mbed_official | 460:3bcf9be0332c | 97 | |
mbed_official | 482:d9a48e768ce0 | 98 | /* clock to us */ |
mbed_official | 482:d9a48e768ce0 | 99 | return (uint32_t)us_val64; |
mbed_official | 390:35c2c1cf29cd | 100 | } |
mbed_official | 390:35c2c1cf29cd | 101 | |
mbed_official | 390:35c2c1cf29cd | 102 | void us_ticker_set_interrupt(timestamp_t timestamp) { |
mbed_official | 390:35c2c1cf29cd | 103 | // set match value |
mbed_official | 482:d9a48e768ce0 | 104 | uint64_t timestamp64; |
mbed_official | 482:d9a48e768ce0 | 105 | uint64_t set_cmp_val64; |
mbed_official | 482:d9a48e768ce0 | 106 | volatile uint32_t set_cmp_val; |
mbed_official | 482:d9a48e768ce0 | 107 | uint64_t count_val_64; |
mbed_official | 482:d9a48e768ce0 | 108 | |
mbed_official | 460:3bcf9be0332c | 109 | /* calc compare mach timestamp */ |
mbed_official | 482:d9a48e768ce0 | 110 | timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp; |
mbed_official | 482:d9a48e768ce0 | 111 | if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) { |
mbed_official | 482:d9a48e768ce0 | 112 | /* This event is wrap arround */ |
mbed_official | 482:d9a48e768ce0 | 113 | timestamp64 += 0x100000000; |
mbed_official | 460:3bcf9be0332c | 114 | } |
mbed_official | 482:d9a48e768ce0 | 115 | |
mbed_official | 460:3bcf9be0332c | 116 | /* calc compare mach timestamp */ |
mbed_official | 482:d9a48e768ce0 | 117 | set_cmp_val64 = timestamp64 * count_clock; |
mbed_official | 482:d9a48e768ce0 | 118 | set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF); |
mbed_official | 482:d9a48e768ce0 | 119 | count_val_64 = ticker_read_counter64(); |
mbed_official | 482:d9a48e768ce0 | 120 | if (set_cmp_val64 <= (count_val_64 + 500)) { |
mbed_official | 482:d9a48e768ce0 | 121 | GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); |
mbed_official | 482:d9a48e768ce0 | 122 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
mbed_official | 482:d9a48e768ce0 | 123 | return; |
mbed_official | 482:d9a48e768ce0 | 124 | } |
mbed_official | 482:d9a48e768ce0 | 125 | OSTM1CMP = set_cmp_val; |
mbed_official | 430:d406b7919023 | 126 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
mbed_official | 390:35c2c1cf29cd | 127 | } |
mbed_official | 390:35c2c1cf29cd | 128 | |
mbed_official | 390:35c2c1cf29cd | 129 | void us_ticker_disable_interrupt(void) { |
mbed_official | 430:d406b7919023 | 130 | GIC_DisableIRQ(US_TICKER_TIMER_IRQn); |
mbed_official | 390:35c2c1cf29cd | 131 | } |
mbed_official | 390:35c2c1cf29cd | 132 | |
mbed_official | 390:35c2c1cf29cd | 133 | void us_ticker_clear_interrupt(void) { |
mbed_official | 482:d9a48e768ce0 | 134 | GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn); |
mbed_official | 390:35c2c1cf29cd | 135 | } |