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targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/us_ticker.c@460:3bcf9be0332c, 2015-02-02 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Feb 02 11:30:07 2015 +0000
- Revision:
- 460:3bcf9be0332c
- Parent:
- 437:0b72c0f86db6
- Child:
- 482:d9a48e768ce0
Synchronized with git revision c53fab9e3c2bcc48a6431a4222a43197c18a8c7b
Full URL: https://github.com/mbedmicro/mbed/commit/c53fab9e3c2bcc48a6431a4222a43197c18a8c7b/
RZ_A1H - Add some function and fix some bugs.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 390:35c2c1cf29cd | 1 | /* mbed Microcontroller Library |
mbed_official | 390:35c2c1cf29cd | 2 | * Copyright (c) 2006-2013 ARM Limited |
mbed_official | 390:35c2c1cf29cd | 3 | * |
mbed_official | 390:35c2c1cf29cd | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
mbed_official | 390:35c2c1cf29cd | 5 | * you may not use this file except in compliance with the License. |
mbed_official | 390:35c2c1cf29cd | 6 | * You may obtain a copy of the License at |
mbed_official | 390:35c2c1cf29cd | 7 | * |
mbed_official | 390:35c2c1cf29cd | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
mbed_official | 390:35c2c1cf29cd | 9 | * |
mbed_official | 390:35c2c1cf29cd | 10 | * Unless required by applicable law or agreed to in writing, software |
mbed_official | 390:35c2c1cf29cd | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
mbed_official | 390:35c2c1cf29cd | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
mbed_official | 390:35c2c1cf29cd | 13 | * See the License for the specific language governing permissions and |
mbed_official | 390:35c2c1cf29cd | 14 | * limitations under the License. |
mbed_official | 390:35c2c1cf29cd | 15 | */ |
mbed_official | 390:35c2c1cf29cd | 16 | #include <stddef.h> |
mbed_official | 390:35c2c1cf29cd | 17 | #include "us_ticker_api.h" |
mbed_official | 390:35c2c1cf29cd | 18 | #include "PeripheralNames.h" |
mbed_official | 430:d406b7919023 | 19 | #include "ostm_iodefine.h" |
mbed_official | 430:d406b7919023 | 20 | |
mbed_official | 430:d406b7919023 | 21 | #include "RZ_A1_Init.h" |
mbed_official | 430:d406b7919023 | 22 | #include "MBRZA1H.h" |
mbed_official | 390:35c2c1cf29cd | 23 | |
mbed_official | 430:d406b7919023 | 24 | #define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn) |
mbed_official | 430:d406b7919023 | 25 | #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */ |
mbed_official | 430:d406b7919023 | 26 | |
mbed_official | 430:d406b7919023 | 27 | #define US_TICKER_CLOCK_US_DEV (1000000) |
mbed_official | 390:35c2c1cf29cd | 28 | |
mbed_official | 390:35c2c1cf29cd | 29 | int us_ticker_inited = 0; |
mbed_official | 430:d406b7919023 | 30 | static double count_clock = 0; |
mbed_official | 437:0b72c0f86db6 | 31 | static uint32_t last_read = 0; |
mbed_official | 437:0b72c0f86db6 | 32 | static uint32_t wrap_arround = 0; |
mbed_official | 390:35c2c1cf29cd | 33 | |
mbed_official | 390:35c2c1cf29cd | 34 | void us_ticker_interrupt(void) { |
mbed_official | 390:35c2c1cf29cd | 35 | us_ticker_irq_handler(); |
mbed_official | 390:35c2c1cf29cd | 36 | } |
mbed_official | 390:35c2c1cf29cd | 37 | |
mbed_official | 390:35c2c1cf29cd | 38 | void us_ticker_init(void) { |
mbed_official | 390:35c2c1cf29cd | 39 | if (us_ticker_inited) return; |
mbed_official | 390:35c2c1cf29cd | 40 | us_ticker_inited = 1; |
mbed_official | 437:0b72c0f86db6 | 41 | |
mbed_official | 430:d406b7919023 | 42 | /* set Counter Clock(us) */ |
mbed_official | 430:d406b7919023 | 43 | if (false == RZ_A1_IsClockMode0()) { |
mbed_official | 437:0b72c0f86db6 | 44 | count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); |
mbed_official | 430:d406b7919023 | 45 | } else { |
mbed_official | 437:0b72c0f86db6 | 46 | count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV); |
mbed_official | 430:d406b7919023 | 47 | } |
mbed_official | 430:d406b7919023 | 48 | |
mbed_official | 390:35c2c1cf29cd | 49 | /* Power Control for Peripherals */ |
mbed_official | 430:d406b7919023 | 50 | CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */ |
mbed_official | 390:35c2c1cf29cd | 51 | |
mbed_official | 390:35c2c1cf29cd | 52 | // timer settings |
mbed_official | 430:d406b7919023 | 53 | OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */ |
mbed_official | 430:d406b7919023 | 54 | OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */ |
mbed_official | 390:35c2c1cf29cd | 55 | |
mbed_official | 430:d406b7919023 | 56 | OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */ |
mbed_official | 390:35c2c1cf29cd | 57 | |
mbed_official | 390:35c2c1cf29cd | 58 | // INTC settings |
mbed_official | 430:d406b7919023 | 59 | InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt); |
mbed_official | 430:d406b7919023 | 60 | GIC_SetPriority(US_TICKER_TIMER_IRQn, 5); |
mbed_official | 430:d406b7919023 | 61 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
mbed_official | 390:35c2c1cf29cd | 62 | } |
mbed_official | 390:35c2c1cf29cd | 63 | |
mbed_official | 460:3bcf9be0332c | 64 | uint64_t us_ticker_read64() { |
mbed_official | 390:35c2c1cf29cd | 65 | uint32_t val; |
mbed_official | 460:3bcf9be0332c | 66 | volatile uint64_t val64; |
mbed_official | 460:3bcf9be0332c | 67 | int check_irq_masked; |
mbed_official | 460:3bcf9be0332c | 68 | |
mbed_official | 460:3bcf9be0332c | 69 | check_irq_masked = __disable_irq(); |
mbed_official | 437:0b72c0f86db6 | 70 | |
mbed_official | 390:35c2c1cf29cd | 71 | if (!us_ticker_inited) |
mbed_official | 390:35c2c1cf29cd | 72 | us_ticker_init(); |
mbed_official | 437:0b72c0f86db6 | 73 | |
mbed_official | 430:d406b7919023 | 74 | /* read counter */ |
mbed_official | 430:d406b7919023 | 75 | val = OSTM1CNT; |
mbed_official | 437:0b72c0f86db6 | 76 | if ( last_read > val ) { |
mbed_official | 437:0b72c0f86db6 | 77 | wrap_arround++; |
mbed_official | 437:0b72c0f86db6 | 78 | } |
mbed_official | 437:0b72c0f86db6 | 79 | last_read = val; |
mbed_official | 437:0b72c0f86db6 | 80 | val64 = ((uint64_t)wrap_arround << 32) + val; |
mbed_official | 437:0b72c0f86db6 | 81 | |
mbed_official | 430:d406b7919023 | 82 | /* clock to us */ |
mbed_official | 460:3bcf9be0332c | 83 | val64 = val64 / count_clock; |
mbed_official | 460:3bcf9be0332c | 84 | |
mbed_official | 460:3bcf9be0332c | 85 | if (!check_irq_masked) { |
mbed_official | 460:3bcf9be0332c | 86 | __enable_irq(); |
mbed_official | 460:3bcf9be0332c | 87 | } |
mbed_official | 460:3bcf9be0332c | 88 | |
mbed_official | 460:3bcf9be0332c | 89 | return val64; |
mbed_official | 460:3bcf9be0332c | 90 | } |
mbed_official | 460:3bcf9be0332c | 91 | |
mbed_official | 460:3bcf9be0332c | 92 | uint32_t us_ticker_read() { |
mbed_official | 460:3bcf9be0332c | 93 | return (uint32_t)us_ticker_read64(); |
mbed_official | 390:35c2c1cf29cd | 94 | } |
mbed_official | 390:35c2c1cf29cd | 95 | |
mbed_official | 390:35c2c1cf29cd | 96 | void us_ticker_set_interrupt(timestamp_t timestamp) { |
mbed_official | 390:35c2c1cf29cd | 97 | // set match value |
mbed_official | 460:3bcf9be0332c | 98 | volatile uint64_t set_cmp_val = 0; |
mbed_official | 460:3bcf9be0332c | 99 | uint64_t timestamp_tmp; |
mbed_official | 460:3bcf9be0332c | 100 | int64_t timestamp_req; |
mbed_official | 460:3bcf9be0332c | 101 | int64_t timestamp_comp; |
mbed_official | 460:3bcf9be0332c | 102 | uint64_t timestamp_now = us_ticker_read64(); |
mbed_official | 460:3bcf9be0332c | 103 | |
mbed_official | 460:3bcf9be0332c | 104 | /* calc compare mach timestamp */ |
mbed_official | 460:3bcf9be0332c | 105 | set_cmp_val = (timestamp_now & 0xFFFFFFFF00000000) + timestamp; |
mbed_official | 460:3bcf9be0332c | 106 | |
mbed_official | 460:3bcf9be0332c | 107 | timestamp_tmp = (uint64_t)timestamp; |
mbed_official | 460:3bcf9be0332c | 108 | timestamp_req = (int64_t)timestamp_tmp; |
mbed_official | 460:3bcf9be0332c | 109 | |
mbed_official | 460:3bcf9be0332c | 110 | timestamp_tmp = (uint64_t)(timestamp_now & 0x00000000FFFFFFFF); |
mbed_official | 460:3bcf9be0332c | 111 | timestamp_comp = (int64_t)timestamp_tmp; |
mbed_official | 460:3bcf9be0332c | 112 | |
mbed_official | 460:3bcf9be0332c | 113 | if (timestamp_req <= timestamp_comp + 1) { |
mbed_official | 460:3bcf9be0332c | 114 | if (((timestamp_req - timestamp_comp) <= 1) && ((timestamp_req - timestamp_comp) >= -10)) { |
mbed_official | 460:3bcf9be0332c | 115 | /* This event was in the past */ |
mbed_official | 460:3bcf9be0332c | 116 | us_ticker_irq_handler(); |
mbed_official | 460:3bcf9be0332c | 117 | return; |
mbed_official | 460:3bcf9be0332c | 118 | } else { |
mbed_official | 460:3bcf9be0332c | 119 | /* This event is wrap arround */ |
mbed_official | 460:3bcf9be0332c | 120 | set_cmp_val += 0x100000000; |
mbed_official | 460:3bcf9be0332c | 121 | } |
mbed_official | 460:3bcf9be0332c | 122 | } |
mbed_official | 460:3bcf9be0332c | 123 | |
mbed_official | 460:3bcf9be0332c | 124 | /* calc compare mach timestamp */ |
mbed_official | 460:3bcf9be0332c | 125 | set_cmp_val = set_cmp_val * count_clock; |
mbed_official | 460:3bcf9be0332c | 126 | OSTM1CMP = (uint32_t)(set_cmp_val & 0xffffffff); |
mbed_official | 430:d406b7919023 | 127 | GIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
mbed_official | 390:35c2c1cf29cd | 128 | } |
mbed_official | 390:35c2c1cf29cd | 129 | |
mbed_official | 390:35c2c1cf29cd | 130 | void us_ticker_disable_interrupt(void) { |
mbed_official | 430:d406b7919023 | 131 | GIC_DisableIRQ(US_TICKER_TIMER_IRQn); |
mbed_official | 390:35c2c1cf29cd | 132 | } |
mbed_official | 390:35c2c1cf29cd | 133 | |
mbed_official | 390:35c2c1cf29cd | 134 | void us_ticker_clear_interrupt(void) { |
mbed_official | 430:d406b7919023 | 135 | /* There are no Flags of OSTM1 to clear here */ |
mbed_official | 430:d406b7919023 | 136 | /* Do Nothing */ |
mbed_official | 390:35c2c1cf29cd | 137 | } |