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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/TOOLCHAIN_GCC_ARM/startup_RZ1AH.s@482:d9a48e768ce0, 2015-02-27 (annotated)

Committer:
mbed_official
Date:
Fri Feb 27 10:00:08 2015 +0000
Revision:
482:d9a48e768ce0
Parent:
390:35c2c1cf29cd
Child:
500:04797f1feae2
Synchronized with git revision 43d7f387ec8e6fef8c03cb5e3a74f7b1596c8f8c



Full URL: https://github.com/mbedmicro/mbed/commit/43d7f387ec8e6fef8c03cb5e3a74f7b1596c8f8c/



RZ/A1H - Modify to support GCC and Fix some bugs of driver.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* File: startup_ARMCM3.s
mbed_official 390:35c2c1cf29cd 2 * Purpose: startup file for Cortex-M3/M4 devices. Should use with
mbed_official 390:35c2c1cf29cd 3 * GNU Tools for ARM Embedded Processors
mbed_official 390:35c2c1cf29cd 4 * Version: V1.1
mbed_official 390:35c2c1cf29cd 5 * Date: 17 June 2011
mbed_official 390:35c2c1cf29cd 6 *
mbed_official 390:35c2c1cf29cd 7 * Copyright (C) 2011 ARM Limited. All rights reserved.
mbed_official 390:35c2c1cf29cd 8 * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
mbed_official 390:35c2c1cf29cd 9 * processor based microcontrollers. This file can be freely distributed
mbed_official 390:35c2c1cf29cd 10 * within development tools that are supporting such ARM based processors.
mbed_official 390:35c2c1cf29cd 11 *
mbed_official 390:35c2c1cf29cd 12 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
mbed_official 390:35c2c1cf29cd 13 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
mbed_official 390:35c2c1cf29cd 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
mbed_official 390:35c2c1cf29cd 15 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
mbed_official 390:35c2c1cf29cd 16 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
mbed_official 390:35c2c1cf29cd 17 */
mbed_official 390:35c2c1cf29cd 18 .syntax unified
mbed_official 482:d9a48e768ce0 19 .extern _start
mbed_official 482:d9a48e768ce0 20
mbed_official 390:35c2c1cf29cd 21 @ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
mbed_official 482:d9a48e768ce0 22 .equ USR_MODE , 0x10
mbed_official 482:d9a48e768ce0 23 .equ FIQ_MODE , 0x11
mbed_official 482:d9a48e768ce0 24 .equ IRQ_MODE , 0x12
mbed_official 482:d9a48e768ce0 25 .equ SVC_MODE , 0x13
mbed_official 482:d9a48e768ce0 26 .equ ABT_MODE , 0x17
mbed_official 482:d9a48e768ce0 27 .equ UND_MODE , 0x1b
mbed_official 482:d9a48e768ce0 28 .equ SYS_MODE , 0x1f
mbed_official 482:d9a48e768ce0 29 .equ Thum_bit , 0x20 @ CPSR/SPSR Thumb bit
mbed_official 482:d9a48e768ce0 30
mbed_official 482:d9a48e768ce0 31 .equ GICI_BASE , 0xe8202000
mbed_official 482:d9a48e768ce0 32 .equ ICCIAR_OFFSET , 0x0000000C
mbed_official 482:d9a48e768ce0 33 .equ ICCEOIR_OFFSET , 0x00000010
mbed_official 482:d9a48e768ce0 34 .equ ICCHPIR_OFFSET , 0x00000018
mbed_official 482:d9a48e768ce0 35 .equ GICD_BASE , 0xe8201000
mbed_official 482:d9a48e768ce0 36 .equ ICDISER0_OFFSET , 0x00000100
mbed_official 482:d9a48e768ce0 37 .equ ICDICER0_OFFSET , 0x00000180
mbed_official 482:d9a48e768ce0 38 .equ ICDISPR0_OFFSET , 0x00000200
mbed_official 482:d9a48e768ce0 39 .equ ICDABR0_OFFSET , 0x00000300
mbed_official 482:d9a48e768ce0 40 .equ ICDIPR0_OFFSET , 0x00000400
mbed_official 482:d9a48e768ce0 41
mbed_official 482:d9a48e768ce0 42 .equ Mode_USR , 0x10
mbed_official 482:d9a48e768ce0 43 .equ Mode_FIQ , 0x11
mbed_official 482:d9a48e768ce0 44 .equ Mode_IRQ , 0x12
mbed_official 482:d9a48e768ce0 45 .equ Mode_SVC , 0x13
mbed_official 482:d9a48e768ce0 46 .equ Mode_ABT , 0x17
mbed_official 482:d9a48e768ce0 47 .equ Mode_UND , 0x1B
mbed_official 482:d9a48e768ce0 48 .equ Mode_SYS , 0x1F
mbed_official 390:35c2c1cf29cd 49
mbed_official 482:d9a48e768ce0 50 .equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled
mbed_official 482:d9a48e768ce0 51 .equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
mbed_official 482:d9a48e768ce0 52 .equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
mbed_official 482:d9a48e768ce0 53
mbed_official 482:d9a48e768ce0 54 .equ GIC_ERRATA_CHECK_1, 0x000003FE
mbed_official 482:d9a48e768ce0 55 .equ GIC_ERRATA_CHECK_2, 0x000003FF
mbed_official 482:d9a48e768ce0 56
mbed_official 482:d9a48e768ce0 57 .equ Sect_Normal , 0x00005c06 @ outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
mbed_official 482:d9a48e768ce0 58 .equ Sect_Normal_Cod , 0x0000dc06 @ outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
mbed_official 482:d9a48e768ce0 59 .equ Sect_Normal_RO , 0x0000dc16 @ as Sect_Normal_Cod, but not executable
mbed_official 482:d9a48e768ce0 60 .equ Sect_Normal_RW , 0x00005c16 @ as Sect_Normal_Cod, but writeable and not executable
mbed_official 482:d9a48e768ce0 61 .equ Sect_SO , 0x00000c12 @ strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
mbed_official 482:d9a48e768ce0 62 .equ Sect_Device_RO , 0x00008c12 @ device, non-shareable, non-executable, ro, domain 0, base addr 0
mbed_official 482:d9a48e768ce0 63 .equ Sect_Device_RW , 0x00000c12 @ as Sect_Device_RO, but writeable
mbed_official 482:d9a48e768ce0 64 .equ Sect_Fault , 0x00000000 @ this translation will fault (the bottom 2 bits are important, the rest are ignored)
mbed_official 482:d9a48e768ce0 65
mbed_official 482:d9a48e768ce0 66 .equ RAM_BASE , 0x80000000
mbed_official 482:d9a48e768ce0 67 .equ VRAM_BASE , 0x18000000
mbed_official 482:d9a48e768ce0 68 .equ SRAM_BASE , 0x2e000000
mbed_official 482:d9a48e768ce0 69 .equ ETHERNET , 0x1a000000
mbed_official 482:d9a48e768ce0 70 .equ CS3_PERIPHERAL_BASE, 0x1c000000
mbed_official 482:d9a48e768ce0 71
mbed_official 482:d9a48e768ce0 72
mbed_official 482:d9a48e768ce0 73 @ Stack Configuration
mbed_official 482:d9a48e768ce0 74
mbed_official 482:d9a48e768ce0 75 .EQU UND_Stack_Size , 0x00000100
mbed_official 482:d9a48e768ce0 76 .EQU SVC_Stack_Size , 0x00008000
mbed_official 482:d9a48e768ce0 77 .EQU ABT_Stack_Size , 0x00000100
mbed_official 482:d9a48e768ce0 78 .EQU FIQ_Stack_Size , 0x00000100
mbed_official 482:d9a48e768ce0 79 .EQU IRQ_Stack_Size , 0x00008000
mbed_official 482:d9a48e768ce0 80 .EQU USR_Stack_Size , 0x00004000
mbed_official 482:d9a48e768ce0 81
mbed_official 482:d9a48e768ce0 82 .EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
mbed_official 390:35c2c1cf29cd 83
mbed_official 390:35c2c1cf29cd 84 .section .stack
mbed_official 390:35c2c1cf29cd 85 .align 3
mbed_official 390:35c2c1cf29cd 86 .globl __StackTop
mbed_official 390:35c2c1cf29cd 87 .globl __StackLimit
mbed_official 390:35c2c1cf29cd 88 __StackLimit:
mbed_official 482:d9a48e768ce0 89 .space ISR_Stack_Size
mbed_official 482:d9a48e768ce0 90 __initial_sp:
mbed_official 482:d9a48e768ce0 91 .space USR_Stack_Size
mbed_official 390:35c2c1cf29cd 92 .size __StackLimit, . - __StackLimit
mbed_official 390:35c2c1cf29cd 93 __StackTop:
mbed_official 390:35c2c1cf29cd 94 .size __StackTop, . - __StackTop
mbed_official 482:d9a48e768ce0 95
mbed_official 482:d9a48e768ce0 96
mbed_official 482:d9a48e768ce0 97 @ Heap Configuration
mbed_official 482:d9a48e768ce0 98
mbed_official 482:d9a48e768ce0 99 .EQU Heap_Size , 0x00080000
mbed_official 390:35c2c1cf29cd 100
mbed_official 390:35c2c1cf29cd 101 .section .heap
mbed_official 390:35c2c1cf29cd 102 .align 3
mbed_official 390:35c2c1cf29cd 103 .globl __HeapBase
mbed_official 390:35c2c1cf29cd 104 .globl __HeapLimit
mbed_official 390:35c2c1cf29cd 105 __HeapBase:
mbed_official 390:35c2c1cf29cd 106 .space Heap_Size
mbed_official 390:35c2c1cf29cd 107 .size __HeapBase, . - __HeapBase
mbed_official 390:35c2c1cf29cd 108 __HeapLimit:
mbed_official 390:35c2c1cf29cd 109 .size __HeapLimit, . - __HeapLimit
mbed_official 482:d9a48e768ce0 110
mbed_official 482:d9a48e768ce0 111
mbed_official 390:35c2c1cf29cd 112 .section .isr_vector
mbed_official 390:35c2c1cf29cd 113 .align 2
mbed_official 390:35c2c1cf29cd 114 .globl __isr_vector
mbed_official 390:35c2c1cf29cd 115 __isr_vector:
mbed_official 482:d9a48e768ce0 116 .long 0xe59ff018 // 0x00
mbed_official 482:d9a48e768ce0 117 .long 0xe59ff018 // 0x04
mbed_official 482:d9a48e768ce0 118 .long 0xe59ff018 // 0x08
mbed_official 482:d9a48e768ce0 119 .long 0xe59ff018 // 0x0c
mbed_official 482:d9a48e768ce0 120 .long 0xe59ff018 // 0x10
mbed_official 482:d9a48e768ce0 121 .long 0xe59ff018 // 0x14
mbed_official 482:d9a48e768ce0 122 .long 0xe59ff018 // 0x18
mbed_official 482:d9a48e768ce0 123 .long 0xe59ff018 // 0x1c
mbed_official 390:35c2c1cf29cd 124
mbed_official 482:d9a48e768ce0 125 .long Reset_Handler /* 0x20 */
mbed_official 482:d9a48e768ce0 126 .long Undef_Handler /* 0x24 */
mbed_official 482:d9a48e768ce0 127 .long SVC_Handler /* 0x28 */
mbed_official 482:d9a48e768ce0 128 .long PAbt_Handler /* 0x2c */
mbed_official 482:d9a48e768ce0 129 .long DAbt_Handler /* 0x30 */
mbed_official 482:d9a48e768ce0 130 .long 0 /* Reserved */
mbed_official 482:d9a48e768ce0 131 .long IRQ_Handler /* IRQ */
mbed_official 482:d9a48e768ce0 132 .long FIQ_Handler /* FIQ */
mbed_official 390:35c2c1cf29cd 133
mbed_official 390:35c2c1cf29cd 134
mbed_official 390:35c2c1cf29cd 135 .size __isr_vector, . - __isr_vector
mbed_official 390:35c2c1cf29cd 136
mbed_official 390:35c2c1cf29cd 137 .text
mbed_official 390:35c2c1cf29cd 138 .align 2
mbed_official 482:d9a48e768ce0 139 .globl Reset_Handler
mbed_official 482:d9a48e768ce0 140 .type Reset_Handler, %function
mbed_official 390:35c2c1cf29cd 141 Reset_Handler:
mbed_official 482:d9a48e768ce0 142 @ Put any cores other than 0 to sleep
mbed_official 482:d9a48e768ce0 143 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
mbed_official 482:d9a48e768ce0 144 ands r0, r0, #3
mbed_official 482:d9a48e768ce0 145
mbed_official 482:d9a48e768ce0 146 goToSleep:
mbed_official 482:d9a48e768ce0 147 wfine
mbed_official 482:d9a48e768ce0 148 bne goToSleep
mbed_official 482:d9a48e768ce0 149
mbed_official 482:d9a48e768ce0 150 @ Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
mbed_official 482:d9a48e768ce0 151 @ Enables Full Access i.e. in both privileged and non privileged modes
mbed_official 482:d9a48e768ce0 152 mrc p15, 0, r0, c1, c0, 2 @ Read Coprocessor Access Control Register (CPACR)
mbed_official 482:d9a48e768ce0 153 orr r0, r0, #(0xF << 20) @ Enable access to CP 10 & 11
mbed_official 482:d9a48e768ce0 154 mcr p15, 0, r0, c1, c0, 2 @ Write Coprocessor Access Control Register (CPACR)
mbed_official 482:d9a48e768ce0 155 isb
mbed_official 482:d9a48e768ce0 156
mbed_official 482:d9a48e768ce0 157 @ Switch on the VFP and NEON hardware
mbed_official 482:d9a48e768ce0 158 mov r0, #0x40000000
mbed_official 482:d9a48e768ce0 159 vmsr fpexc, r0 @ Write FPEXC register, EN bit set
mbed_official 482:d9a48e768ce0 160
mbed_official 482:d9a48e768ce0 161 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
mbed_official 482:d9a48e768ce0 162 bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
mbed_official 482:d9a48e768ce0 163 bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
mbed_official 482:d9a48e768ce0 164 bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU
mbed_official 482:d9a48e768ce0 165 bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction
mbed_official 482:d9a48e768ce0 166 bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs
mbed_official 482:d9a48e768ce0 167 mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
mbed_official 482:d9a48e768ce0 168 isb
mbed_official 390:35c2c1cf29cd 169
mbed_official 482:d9a48e768ce0 170 @ Set Vector Base Address Register (VBAR) to point to this application's vector table
mbed_official 482:d9a48e768ce0 171 ldr r0, =__isr_vector
mbed_official 482:d9a48e768ce0 172 mcr p15, 0, r0, c12, c0, 0
mbed_official 482:d9a48e768ce0 173
mbed_official 482:d9a48e768ce0 174 @ Setup Stack for each exceptional mode
mbed_official 482:d9a48e768ce0 175 /* ldr r0, =__StackTop */
mbed_official 482:d9a48e768ce0 176 ldr r0, =__initial_sp
mbed_official 390:35c2c1cf29cd 177
mbed_official 482:d9a48e768ce0 178 @ Enter Undefined Instruction Mode and set its Stack Pointer
mbed_official 482:d9a48e768ce0 179 msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
mbed_official 482:d9a48e768ce0 180 mov sp, r0
mbed_official 482:d9a48e768ce0 181 sub r0, r0, #UND_Stack_Size
mbed_official 482:d9a48e768ce0 182
mbed_official 482:d9a48e768ce0 183 @ Enter Abort Mode and set its Stack Pointer
mbed_official 482:d9a48e768ce0 184 msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
mbed_official 482:d9a48e768ce0 185 mov sp, r0
mbed_official 482:d9a48e768ce0 186 sub r0, r0, #ABT_Stack_Size
mbed_official 390:35c2c1cf29cd 187
mbed_official 482:d9a48e768ce0 188 @ Enter FIQ Mode and set its Stack Pointer
mbed_official 482:d9a48e768ce0 189 msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
mbed_official 482:d9a48e768ce0 190 mov sp, r0
mbed_official 482:d9a48e768ce0 191 sub r0, r0, #FIQ_Stack_Size
mbed_official 390:35c2c1cf29cd 192
mbed_official 482:d9a48e768ce0 193 @ Enter IRQ Mode and set its Stack Pointer
mbed_official 482:d9a48e768ce0 194 msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
mbed_official 482:d9a48e768ce0 195 mov sp, r0
mbed_official 482:d9a48e768ce0 196 sub r0, r0, #IRQ_Stack_Size
mbed_official 390:35c2c1cf29cd 197
mbed_official 482:d9a48e768ce0 198 @ Enter Supervisor Mode and set its Stack Pointer
mbed_official 482:d9a48e768ce0 199 msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
mbed_official 482:d9a48e768ce0 200 mov sp, r0
mbed_official 390:35c2c1cf29cd 201
mbed_official 482:d9a48e768ce0 202 @ Enter System Mode to complete initialization and enter kernel
mbed_official 482:d9a48e768ce0 203 msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
mbed_official 482:d9a48e768ce0 204 mov sp, r0
mbed_official 390:35c2c1cf29cd 205
mbed_official 482:d9a48e768ce0 206 isb
mbed_official 482:d9a48e768ce0 207 ldr r0, =RZ_A1_SetSramWriteEnable
mbed_official 482:d9a48e768ce0 208 blx r0
mbed_official 482:d9a48e768ce0 209
mbed_official 482:d9a48e768ce0 210 .extern create_translation_table
mbed_official 482:d9a48e768ce0 211 bl create_translation_table
mbed_official 482:d9a48e768ce0 212
mbed_official 482:d9a48e768ce0 213 @ USR/SYS stack pointer will be set during kernel init
mbed_official 482:d9a48e768ce0 214 ldr r0, =SystemInit
mbed_official 482:d9a48e768ce0 215 blx r0
mbed_official 482:d9a48e768ce0 216 ldr r0, =InitMemorySubsystem
mbed_official 482:d9a48e768ce0 217 blx r0
mbed_official 482:d9a48e768ce0 218
mbed_official 482:d9a48e768ce0 219 @ fp_init
mbed_official 482:d9a48e768ce0 220 mov r0, #0x3000000
mbed_official 482:d9a48e768ce0 221 vmsr fpscr, r0
mbed_official 482:d9a48e768ce0 222
mbed_official 390:35c2c1cf29cd 223
mbed_official 482:d9a48e768ce0 224 @ data sections copy
mbed_official 482:d9a48e768ce0 225 ldr r4, =__copy_table_start__
mbed_official 482:d9a48e768ce0 226 ldr r5, =__copy_table_end__
mbed_official 390:35c2c1cf29cd 227
mbed_official 482:d9a48e768ce0 228 .L_loop0:
mbed_official 482:d9a48e768ce0 229 cmp r4, r5
mbed_official 482:d9a48e768ce0 230 bge .L_loop0_done
mbed_official 482:d9a48e768ce0 231 ldr r1, [r4]
mbed_official 482:d9a48e768ce0 232 ldr r2, [r4, #4]
mbed_official 482:d9a48e768ce0 233 ldr r3, [r4, #8]
mbed_official 482:d9a48e768ce0 234
mbed_official 482:d9a48e768ce0 235 .L_loop0_0:
mbed_official 482:d9a48e768ce0 236 subs r3, #4
mbed_official 482:d9a48e768ce0 237 ittt ge
mbed_official 482:d9a48e768ce0 238 ldrge r0, [r1, r3]
mbed_official 482:d9a48e768ce0 239 strge r0, [r2, r3]
mbed_official 482:d9a48e768ce0 240 bge .L_loop0_0
mbed_official 390:35c2c1cf29cd 241
mbed_official 482:d9a48e768ce0 242 adds r4, #12
mbed_official 482:d9a48e768ce0 243 b .L_loop0
mbed_official 482:d9a48e768ce0 244
mbed_official 482:d9a48e768ce0 245 .L_loop0_done:
mbed_official 390:35c2c1cf29cd 246
mbed_official 482:d9a48e768ce0 247 @ bss sections clear
mbed_official 482:d9a48e768ce0 248 ldr r3, =__zero_table_start__
mbed_official 482:d9a48e768ce0 249 ldr r4, =__zero_table_end__
mbed_official 482:d9a48e768ce0 250
mbed_official 482:d9a48e768ce0 251 .L_loop2:
mbed_official 482:d9a48e768ce0 252 cmp r3, r4
mbed_official 482:d9a48e768ce0 253 bge .L_loop2_done
mbed_official 482:d9a48e768ce0 254 ldr r1, [r3]
mbed_official 482:d9a48e768ce0 255 ldr r2, [r3, #4]
mbed_official 482:d9a48e768ce0 256 movs r0, 0
mbed_official 390:35c2c1cf29cd 257
mbed_official 482:d9a48e768ce0 258 .L_loop2_0:
mbed_official 482:d9a48e768ce0 259 subs r2, #4
mbed_official 482:d9a48e768ce0 260 itt ge
mbed_official 482:d9a48e768ce0 261 strge r0, [r1, r2]
mbed_official 482:d9a48e768ce0 262 bge .L_loop2_0
mbed_official 482:d9a48e768ce0 263
mbed_official 482:d9a48e768ce0 264 adds r3, #8
mbed_official 482:d9a48e768ce0 265 b .L_loop2
mbed_official 482:d9a48e768ce0 266 .L_loop2_done:
mbed_official 482:d9a48e768ce0 267
mbed_official 482:d9a48e768ce0 268
mbed_official 482:d9a48e768ce0 269 ldr r0, =_start
mbed_official 482:d9a48e768ce0 270 bx r0
mbed_official 482:d9a48e768ce0 271
mbed_official 482:d9a48e768ce0 272 ldr r0, sf_boot @ dummy to keep boot loader area
mbed_official 482:d9a48e768ce0 273 loop_here:
mbed_official 482:d9a48e768ce0 274 b loop_here
mbed_official 482:d9a48e768ce0 275
mbed_official 482:d9a48e768ce0 276 sf_boot:
mbed_official 482:d9a48e768ce0 277 .word boot_loader
mbed_official 482:d9a48e768ce0 278
mbed_official 390:35c2c1cf29cd 279 .pool
mbed_official 390:35c2c1cf29cd 280 .size Reset_Handler, . - Reset_Handler
mbed_official 390:35c2c1cf29cd 281
mbed_official 482:d9a48e768ce0 282
mbed_official 390:35c2c1cf29cd 283 .text
mbed_official 482:d9a48e768ce0 284
mbed_official 482:d9a48e768ce0 285 Undef_Handler:
mbed_official 482:d9a48e768ce0 286 .global Undef_Handler
mbed_official 482:d9a48e768ce0 287 .func Undef_Handler
mbed_official 482:d9a48e768ce0 288 .extern CUndefHandler
mbed_official 482:d9a48e768ce0 289 SRSDB SP!, #Mode_UND
mbed_official 482:d9a48e768ce0 290 PUSH {R0-R4, R12} /* Save APCS corruptible registers to UND mode stack */
mbed_official 482:d9a48e768ce0 291
mbed_official 482:d9a48e768ce0 292 MRS R0, SPSR
mbed_official 482:d9a48e768ce0 293 TST R0, #T_Bit /* Check mode */
mbed_official 482:d9a48e768ce0 294 MOVEQ R1, #4 /* R1 = 4 ARM mode */
mbed_official 482:d9a48e768ce0 295 MOVNE R1, #2 /* R1 = 2 Thumb mode */
mbed_official 482:d9a48e768ce0 296 SUB R0, LR, R1
mbed_official 482:d9a48e768ce0 297 LDREQ R0, [R0] /* ARM mode - R0 points to offending instruction */
mbed_official 482:d9a48e768ce0 298 BEQ undef_cont
mbed_official 482:d9a48e768ce0 299
mbed_official 482:d9a48e768ce0 300 /* Thumb instruction */
mbed_official 482:d9a48e768ce0 301 /* Determine if it is a 32-bit Thumb instruction */
mbed_official 482:d9a48e768ce0 302 LDRH R0, [R0]
mbed_official 482:d9a48e768ce0 303 MOV R2, #0x1c
mbed_official 482:d9a48e768ce0 304 CMP R2, R0, LSR #11
mbed_official 482:d9a48e768ce0 305 BHS undef_cont /* 16-bit Thumb instruction */
mbed_official 482:d9a48e768ce0 306
mbed_official 482:d9a48e768ce0 307 /* 32-bit Thumb instruction. Unaligned - we need to reconstruct the offending instruction. */
mbed_official 482:d9a48e768ce0 308 LDRH R2, [LR]
mbed_official 482:d9a48e768ce0 309 ORR R0, R2, R0, LSL #16
mbed_official 482:d9a48e768ce0 310 undef_cont:
mbed_official 482:d9a48e768ce0 311 MOV R2, LR /* Set LR to third argument */
mbed_official 482:d9a48e768ce0 312
mbed_official 482:d9a48e768ce0 313 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
mbed_official 482:d9a48e768ce0 314 MOV R3, SP /* Ensure stack is 8-byte aligned */
mbed_official 482:d9a48e768ce0 315 AND R12, R3, #4
mbed_official 482:d9a48e768ce0 316 SUB SP, SP, R12 /* Adjust stack */
mbed_official 482:d9a48e768ce0 317 PUSH {R12, LR} /* Store stack adjustment and dummy LR */
mbed_official 482:d9a48e768ce0 318
mbed_official 482:d9a48e768ce0 319 /* R0 Offending instruction */
mbed_official 482:d9a48e768ce0 320 /* R1 =2 (Thumb) or =4 (ARM) */
mbed_official 482:d9a48e768ce0 321 BL CUndefHandler
mbed_official 482:d9a48e768ce0 322
mbed_official 482:d9a48e768ce0 323 POP {R12, LR} /* Get stack adjustment & discard dummy LR */
mbed_official 482:d9a48e768ce0 324 ADD SP, SP, R12 /* Unadjust stack */
mbed_official 482:d9a48e768ce0 325
mbed_official 482:d9a48e768ce0 326 LDR LR, [SP, #24] /* Restore stacked LR and possibly adjust for retry */
mbed_official 482:d9a48e768ce0 327 SUB LR, LR, R0
mbed_official 482:d9a48e768ce0 328 LDR R0, [SP, #28] /* Restore stacked SPSR */
mbed_official 482:d9a48e768ce0 329 MSR SPSR_cxsf, R0
mbed_official 482:d9a48e768ce0 330 POP {R0-R4, R12} /* Restore stacked APCS registers */
mbed_official 482:d9a48e768ce0 331 ADD SP, SP, #8 /* Adjust SP for already-restored banked registers */
mbed_official 482:d9a48e768ce0 332 MOVS PC, LR
mbed_official 482:d9a48e768ce0 333 .endfunc
mbed_official 482:d9a48e768ce0 334
mbed_official 482:d9a48e768ce0 335 PAbt_Handler:
mbed_official 482:d9a48e768ce0 336 .global PAbt_Handler
mbed_official 482:d9a48e768ce0 337 .func PAbt_Handler
mbed_official 482:d9a48e768ce0 338 .extern CPAbtHandler
mbed_official 482:d9a48e768ce0 339 SUB LR, LR, #4 /* Pre-adjust LR */
mbed_official 482:d9a48e768ce0 340 SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
mbed_official 482:d9a48e768ce0 341 PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
mbed_official 482:d9a48e768ce0 342 MRC p15, 0, R0, c5, c0, 1 /* IFSR */
mbed_official 482:d9a48e768ce0 343 MRC p15, 0, R1, c6, c0, 2 /* IFAR */
mbed_official 482:d9a48e768ce0 344
mbed_official 482:d9a48e768ce0 345 MOV R2, LR /* Set LR to third argument */
mbed_official 482:d9a48e768ce0 346
mbed_official 482:d9a48e768ce0 347 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
mbed_official 482:d9a48e768ce0 348 MOV R3, SP /* Ensure stack is 8-byte aligned */
mbed_official 482:d9a48e768ce0 349 AND R12, R3, #4
mbed_official 482:d9a48e768ce0 350 SUB SP, SP, R12 /* Adjust stack */
mbed_official 482:d9a48e768ce0 351 PUSH {R12, LR} /* Store stack adjustment and dummy LR */
mbed_official 482:d9a48e768ce0 352
mbed_official 482:d9a48e768ce0 353 BL CPAbtHandler
mbed_official 482:d9a48e768ce0 354
mbed_official 482:d9a48e768ce0 355 POP {R12, LR} /* Get stack adjustment & discard dummy LR */
mbed_official 482:d9a48e768ce0 356 ADD SP, SP, R12 /* Unadjust stack */
mbed_official 482:d9a48e768ce0 357
mbed_official 482:d9a48e768ce0 358 POP {R0-R4, R12} /* Restore stack APCS registers */
mbed_official 482:d9a48e768ce0 359 RFEFD SP! /* Return from exception */
mbed_official 482:d9a48e768ce0 360 .endfunc
mbed_official 482:d9a48e768ce0 361
mbed_official 482:d9a48e768ce0 362 DAbt_Handler:
mbed_official 482:d9a48e768ce0 363 .global DAbt_Handler
mbed_official 482:d9a48e768ce0 364 .func DAbt_Handler
mbed_official 482:d9a48e768ce0 365 .extern CDAbtHandler
mbed_official 482:d9a48e768ce0 366 SUB LR, LR, #8 /* Pre-adjust LR */
mbed_official 482:d9a48e768ce0 367 SRSDB SP!, #Mode_ABT /* Save LR and SPRS to ABT mode stack */
mbed_official 482:d9a48e768ce0 368 PUSH {R0-R4, R12} /* Save APCS corruptible registers to ABT mode stack */
mbed_official 482:d9a48e768ce0 369 CLREX /* State of exclusive monitors unknown after taken data abort */
mbed_official 482:d9a48e768ce0 370 MRC p15, 0, R0, c5, c0, 0 /* DFSR */
mbed_official 482:d9a48e768ce0 371 MRC p15, 0, R1, c6, c0, 0 /* DFAR */
mbed_official 482:d9a48e768ce0 372
mbed_official 482:d9a48e768ce0 373 MOV R2, LR /* Set LR to third argument */
mbed_official 482:d9a48e768ce0 374
mbed_official 482:d9a48e768ce0 375 /* AND R12, SP, #4 */ /* Ensure stack is 8-byte aligned */
mbed_official 482:d9a48e768ce0 376 MOV R3, SP /* Ensure stack is 8-byte aligned */
mbed_official 482:d9a48e768ce0 377 AND R12, R3, #4
mbed_official 482:d9a48e768ce0 378 SUB SP, SP, R12 /* Adjust stack */
mbed_official 482:d9a48e768ce0 379 PUSH {R12, LR} /* Store stack adjustment and dummy LR */
mbed_official 482:d9a48e768ce0 380
mbed_official 482:d9a48e768ce0 381 BL CDAbtHandler
mbed_official 482:d9a48e768ce0 382
mbed_official 482:d9a48e768ce0 383 POP {R12, LR} /* Get stack adjustment & discard dummy LR */
mbed_official 482:d9a48e768ce0 384 ADD SP, SP, R12 /* Unadjust stack */
mbed_official 482:d9a48e768ce0 385
mbed_official 482:d9a48e768ce0 386 POP {R0-R4, R12} /* Restore stacked APCS registers */
mbed_official 482:d9a48e768ce0 387 RFEFD SP! /* Return from exception */
mbed_official 482:d9a48e768ce0 388 .endfunc
mbed_official 482:d9a48e768ce0 389
mbed_official 482:d9a48e768ce0 390 FIQ_Handler:
mbed_official 482:d9a48e768ce0 391 .global FIQ_Handler
mbed_official 482:d9a48e768ce0 392 .func FIQ_Handler
mbed_official 482:d9a48e768ce0 393 /* An FIQ might occur between the dummy read and the real read of the GIC in IRQ_Handler,
mbed_official 482:d9a48e768ce0 394 * so if a real FIQ Handler is implemented, this will be needed before returning:
mbed_official 482:d9a48e768ce0 395 */
mbed_official 482:d9a48e768ce0 396 /* LDR R1, =GICI_BASE
mbed_official 482:d9a48e768ce0 397 LDR R0, [R1, #ICCHPIR_OFFSET] ; Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120
mbed_official 482:d9a48e768ce0 398 */
mbed_official 482:d9a48e768ce0 399 B .
mbed_official 482:d9a48e768ce0 400 .endfunc
mbed_official 482:d9a48e768ce0 401
mbed_official 482:d9a48e768ce0 402 .extern SVC_Handler /* refer RTX function */
mbed_official 482:d9a48e768ce0 403
mbed_official 482:d9a48e768ce0 404 IRQ_Handler:
mbed_official 482:d9a48e768ce0 405 .global IRQ_Handler
mbed_official 482:d9a48e768ce0 406 .func IRQ_Handler
mbed_official 482:d9a48e768ce0 407 .extern IRQCount
mbed_official 482:d9a48e768ce0 408 .extern IRQTable
mbed_official 482:d9a48e768ce0 409 .extern IRQNestLevel
mbed_official 482:d9a48e768ce0 410
mbed_official 482:d9a48e768ce0 411 /* prologue */
mbed_official 482:d9a48e768ce0 412 SUB LR, LR, #4 /* Pre-adjust LR */
mbed_official 482:d9a48e768ce0 413 SRSDB SP!, #Mode_SVC /* Save LR_IRQ and SPRS_IRQ to SVC mode stack */
mbed_official 482:d9a48e768ce0 414 CPS #Mode_SVC /* Switch to SVC mode, to avoid a nested interrupt corrupting LR on a BL */
mbed_official 482:d9a48e768ce0 415 PUSH {R0-R3, R12} /* Save remaining APCS corruptible registers to SVC stack */
mbed_official 482:d9a48e768ce0 416
mbed_official 482:d9a48e768ce0 417 /* AND R1, SP, #4 */ /* Ensure stack is 8-byte aligned */
mbed_official 482:d9a48e768ce0 418 MOV R3, SP /* Ensure stack is 8-byte aligned */
mbed_official 482:d9a48e768ce0 419 AND R1, R3, #4
mbed_official 482:d9a48e768ce0 420 SUB SP, SP, R1 /* Adjust stack */
mbed_official 482:d9a48e768ce0 421 PUSH {R1, LR} /* Store stack adjustment and LR_SVC to SVC stack */
mbed_official 482:d9a48e768ce0 422
mbed_official 482:d9a48e768ce0 423 LDR R0, =IRQNestLevel /* Get address of nesting counter */
mbed_official 482:d9a48e768ce0 424 LDR R1, [R0]
mbed_official 482:d9a48e768ce0 425 ADD R1, R1, #1 /* Increment nesting counter */
mbed_official 482:d9a48e768ce0 426 STR R1, [R0]
mbed_official 482:d9a48e768ce0 427
mbed_official 482:d9a48e768ce0 428 /* identify and acknowledge interrupt */
mbed_official 482:d9a48e768ce0 429 LDR R1, =GICI_BASE
mbed_official 482:d9a48e768ce0 430 LDR R0, [R1, #ICCHPIR_OFFSET] /* Dummy Read ICCHPIR (GIC CPU Interface register) to avoid GIC 390 errata 801120 */
mbed_official 482:d9a48e768ce0 431 LDR R0, [R1, #ICCIAR_OFFSET] /* Read ICCIAR (GIC CPU Interface register) */
mbed_official 482:d9a48e768ce0 432 DSB /* Ensure that interrupt acknowledge completes before re-enabling interrupts */
mbed_official 482:d9a48e768ce0 433
mbed_official 482:d9a48e768ce0 434 /* Workaround GIC 390 errata 733075
mbed_official 482:d9a48e768ce0 435 * If the ID is not 0, then service the interrupt as normal.
mbed_official 482:d9a48e768ce0 436 * If the ID is 0 and active, then service interrupt ID 0 as normal.
mbed_official 482:d9a48e768ce0 437 * If the ID is 0 but not active, then the GIC CPU interface may be locked-up, so unlock it
mbed_official 482:d9a48e768ce0 438 * with a dummy write to ICDIPR0. This interrupt should be treated as spurious and not serviced.
mbed_official 482:d9a48e768ce0 439 */
mbed_official 482:d9a48e768ce0 440 LDR R2, =GICD_BASE
mbed_official 482:d9a48e768ce0 441 LDR R3, =GIC_ERRATA_CHECK_1
mbed_official 482:d9a48e768ce0 442 CMP R0, R3
mbed_official 482:d9a48e768ce0 443 BEQ unlock_cpu
mbed_official 482:d9a48e768ce0 444 LDR R3, =GIC_ERRATA_CHECK_2
mbed_official 482:d9a48e768ce0 445 CMP R0, R3
mbed_official 482:d9a48e768ce0 446 BEQ unlock_cpu
mbed_official 482:d9a48e768ce0 447 CMP R0, #0
mbed_official 482:d9a48e768ce0 448 BNE int_active /* If the ID is not 0, then service the interrupt */
mbed_official 482:d9a48e768ce0 449 LDR R3, [R2, #ICDABR0_OFFSET] /* Get the interrupt state */
mbed_official 482:d9a48e768ce0 450 TST R3, #1
mbed_official 482:d9a48e768ce0 451 BNE int_active /* If active, then service the interrupt */
mbed_official 482:d9a48e768ce0 452 unlock_cpu:
mbed_official 482:d9a48e768ce0 453 LDR R3, [R2, #ICDIPR0_OFFSET] /* Not active, so unlock the CPU interface */
mbed_official 482:d9a48e768ce0 454 STR R3, [R2, #ICDIPR0_OFFSET] /* with a dummy write */
mbed_official 482:d9a48e768ce0 455 DSB /* Ensure the write completes before continuing */
mbed_official 482:d9a48e768ce0 456 B ret_irq /* Do not service the spurious interrupt */
mbed_official 482:d9a48e768ce0 457 /* End workaround */
mbed_official 482:d9a48e768ce0 458
mbed_official 482:d9a48e768ce0 459 int_active:
mbed_official 482:d9a48e768ce0 460 LDR R2, =IRQCount /* Read number of IRQs */
mbed_official 482:d9a48e768ce0 461 LDR R2, [R2]
mbed_official 482:d9a48e768ce0 462 CMP R0, R2 /* Clean up and return if no handler */
mbed_official 482:d9a48e768ce0 463 BHS ret_irq /* In a single-processor system, spurious interrupt ID 1023 does not need any special handling */
mbed_official 482:d9a48e768ce0 464 LDR R2, =IRQTable /* Get address of handler */
mbed_official 482:d9a48e768ce0 465 LDR R2, [R2, R0, LSL #2]
mbed_official 482:d9a48e768ce0 466 CMP R2, #0 /* Clean up and return if handler address is 0 */
mbed_official 482:d9a48e768ce0 467 BEQ ret_irq
mbed_official 482:d9a48e768ce0 468 PUSH {R0,R1}
mbed_official 482:d9a48e768ce0 469
mbed_official 482:d9a48e768ce0 470 CPSIE i /* Now safe to re-enable interrupts */
mbed_official 482:d9a48e768ce0 471 BLX R2 /* Call handler. R0 will be IRQ number */
mbed_official 482:d9a48e768ce0 472 CPSID i /* Disable interrupts again */
mbed_official 482:d9a48e768ce0 473
mbed_official 482:d9a48e768ce0 474 /* write EOIR (GIC CPU Interface register) */
mbed_official 482:d9a48e768ce0 475 POP {R0,R1}
mbed_official 482:d9a48e768ce0 476 DSB /* Ensure that interrupt source is cleared before we write the EOIR */
mbed_official 482:d9a48e768ce0 477 ret_irq:
mbed_official 482:d9a48e768ce0 478 /* epilogue */
mbed_official 482:d9a48e768ce0 479 STR R0, [R1, #ICCEOIR_OFFSET]
mbed_official 482:d9a48e768ce0 480
mbed_official 482:d9a48e768ce0 481 LDR R0, =IRQNestLevel /* Get address of nesting counter */
mbed_official 482:d9a48e768ce0 482 LDR R1, [R0]
mbed_official 482:d9a48e768ce0 483 SUB R1, R1, #1 /* Decrement nesting counter */
mbed_official 482:d9a48e768ce0 484 STR R1, [R0]
mbed_official 482:d9a48e768ce0 485
mbed_official 482:d9a48e768ce0 486 POP {R1, LR} /* Get stack adjustment and restore LR_SVC */
mbed_official 482:d9a48e768ce0 487 ADD SP, SP, R1 /* Unadjust stack */
mbed_official 482:d9a48e768ce0 488
mbed_official 482:d9a48e768ce0 489 POP {R0-R3,R12} /* Restore stacked APCS registers */
mbed_official 482:d9a48e768ce0 490 RFEFD SP! /* Return from exception */
mbed_official 482:d9a48e768ce0 491 .endfunc
mbed_official 482:d9a48e768ce0 492
mbed_official 390:35c2c1cf29cd 493 /* Macro to define default handlers. Default handler
mbed_official 390:35c2c1cf29cd 494 * will be weak symbol and just dead loops. They can be
mbed_official 390:35c2c1cf29cd 495 * overwritten by other handlers */
mbed_official 482:d9a48e768ce0 496 .macro def_default_handler handler_name
mbed_official 482:d9a48e768ce0 497 .align 1
mbed_official 482:d9a48e768ce0 498 .thumb_func
mbed_official 482:d9a48e768ce0 499 .weak \handler_name
mbed_official 482:d9a48e768ce0 500 .type \handler_name, %function
mbed_official 390:35c2c1cf29cd 501 \handler_name :
mbed_official 482:d9a48e768ce0 502 b .
mbed_official 482:d9a48e768ce0 503 .size \handler_name, . - \handler_name
mbed_official 482:d9a48e768ce0 504 .endm
mbed_official 390:35c2c1cf29cd 505
mbed_official 482:d9a48e768ce0 506 def_default_handler SVC_Handler
mbed_official 390:35c2c1cf29cd 507
mbed_official 390:35c2c1cf29cd 508
mbed_official 482:d9a48e768ce0 509 /* User Initial Stack & Heap */
mbed_official 482:d9a48e768ce0 510
mbed_official 482:d9a48e768ce0 511 .ifdef __MICROLIB
mbed_official 482:d9a48e768ce0 512
mbed_official 482:d9a48e768ce0 513 .global __initial_sp
mbed_official 482:d9a48e768ce0 514 .global __heap_base
mbed_official 482:d9a48e768ce0 515 .global __heap_limit
mbed_official 482:d9a48e768ce0 516
mbed_official 482:d9a48e768ce0 517 .else
mbed_official 390:35c2c1cf29cd 518
mbed_official 482:d9a48e768ce0 519 .extern __use_two_region_memory
mbed_official 482:d9a48e768ce0 520 .global __user_initial_stackheap
mbed_official 482:d9a48e768ce0 521 __user_initial_stackheap:
mbed_official 482:d9a48e768ce0 522
mbed_official 482:d9a48e768ce0 523 LDR R0, = __HeapBase
mbed_official 482:d9a48e768ce0 524 LDR R1, =(__StackLimit + USR_Stack_Size)
mbed_official 482:d9a48e768ce0 525 LDR R2, = (__HeapBase + Heap_Size)
mbed_official 482:d9a48e768ce0 526 LDR R3, = __StackLimit
mbed_official 482:d9a48e768ce0 527 BX LR
mbed_official 482:d9a48e768ce0 528
mbed_official 482:d9a48e768ce0 529 .endif
mbed_official 390:35c2c1cf29cd 530
mbed_official 390:35c2c1cf29cd 531
mbed_official 482:d9a48e768ce0 532 .END