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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c@626:ba773d547214, 2015-09-25 (annotated)

Committer:
mbed_official
Date:
Fri Sep 25 13:30:09 2015 +0100
Revision:
626:ba773d547214
Parent:
482:d9a48e768ce0 
Synchronized with git revision e8c24ba90dd5507bdb7c1b46dd3aba8cfabb762b



Full URL: https://github.com/mbedmicro/mbed/commit/e8c24ba90dd5507bdb7c1b46dd3aba8cfabb762b/



RZ_A1H - Modify to support NEON for RTOS.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 2 * @file system_MBRZA1H.c
mbed_official 390:35c2c1cf29cd 3 * @brief CMSIS Device System Source File for
mbed_official 626:ba773d547214 4 * ARM Cortex-A9 Device Series
mbed_official 390:35c2c1cf29cd 5 * @version V1.00
mbed_official 626:ba773d547214 6 * @date 09 January 2015
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * @note
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 ******************************************************************************/
mbed_official 626:ba773d547214 11 /* Copyright (c) 2011 - 2015 ARM LIMITED
mbed_official 390:35c2c1cf29cd 12
mbed_official 390:35c2c1cf29cd 13 All rights reserved.
mbed_official 390:35c2c1cf29cd 14 Redistribution and use in source and binary forms, with or without
mbed_official 390:35c2c1cf29cd 15 modification, are permitted provided that the following conditions are met:
mbed_official 390:35c2c1cf29cd 16 - Redistributions of source code must retain the above copyright
mbed_official 390:35c2c1cf29cd 17 notice, this list of conditions and the following disclaimer.
mbed_official 390:35c2c1cf29cd 18 - Redistributions in binary form must reproduce the above copyright
mbed_official 390:35c2c1cf29cd 19 notice, this list of conditions and the following disclaimer in the
mbed_official 390:35c2c1cf29cd 20 documentation and/or other materials provided with the distribution.
mbed_official 390:35c2c1cf29cd 21 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 390:35c2c1cf29cd 22 to endorse or promote products derived from this software without
mbed_official 390:35c2c1cf29cd 23 specific prior written permission.
mbed_official 390:35c2c1cf29cd 24 *
mbed_official 390:35c2c1cf29cd 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 390:35c2c1cf29cd 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 390:35c2c1cf29cd 27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 390:35c2c1cf29cd 29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 390:35c2c1cf29cd 30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 390:35c2c1cf29cd 31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 390:35c2c1cf29cd 32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 390:35c2c1cf29cd 33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 390:35c2c1cf29cd 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 390:35c2c1cf29cd 35 POSSIBILITY OF SUCH DAMAGE.
mbed_official 390:35c2c1cf29cd 36 ---------------------------------------------------------------------------*/
mbed_official 390:35c2c1cf29cd 37
mbed_official 390:35c2c1cf29cd 38
mbed_official 390:35c2c1cf29cd 39 #include <stdint.h>
mbed_official 390:35c2c1cf29cd 40 #include "MBRZA1H.h"
mbed_official 390:35c2c1cf29cd 41 #include "RZ_A1_Init.h"
mbed_official 390:35c2c1cf29cd 42
mbed_official 390:35c2c1cf29cd 43
mbed_official 482:d9a48e768ce0 44 #if defined(__ARMCC_VERSION)
mbed_official 390:35c2c1cf29cd 45 extern void $Super$$main(void);
mbed_official 390:35c2c1cf29cd 46 __asm void FPUEnable(void);
mbed_official 482:d9a48e768ce0 47 #else
mbed_official 482:d9a48e768ce0 48 void FPUEnable(void);
mbed_official 482:d9a48e768ce0 49
mbed_official 482:d9a48e768ce0 50 #endif
mbed_official 390:35c2c1cf29cd 51
mbed_official 390:35c2c1cf29cd 52 uint32_t IRQNestLevel;
mbed_official 626:ba773d547214 53 unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
mbed_official 390:35c2c1cf29cd 54
mbed_official 390:35c2c1cf29cd 55
mbed_official 390:35c2c1cf29cd 56 /**
mbed_official 390:35c2c1cf29cd 57 * Initialize the cache.
mbed_official 390:35c2c1cf29cd 58 *
mbed_official 390:35c2c1cf29cd 59 * @param none
mbed_official 390:35c2c1cf29cd 60 * @return none
mbed_official 390:35c2c1cf29cd 61 *
mbed_official 390:35c2c1cf29cd 62 * @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
mbed_official 390:35c2c1cf29cd 63 */
mbed_official 626:ba773d547214 64 #if defined(__ARMCC_VERSION)
mbed_official 390:35c2c1cf29cd 65 #pragma push
mbed_official 390:35c2c1cf29cd 66 #pragma arm
mbed_official 390:35c2c1cf29cd 67
mbed_official 390:35c2c1cf29cd 68 void InitMemorySubsystem(void) {
mbed_official 390:35c2c1cf29cd 69
mbed_official 390:35c2c1cf29cd 70 /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
mbed_official 390:35c2c1cf29cd 71 * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
mbed_official 390:35c2c1cf29cd 72 * You are not required to invalidate the main TLB, even though it is recommended for safety
mbed_official 390:35c2c1cf29cd 73 * reasons. This ensures compatibility with future revisions of the processor. */
mbed_official 390:35c2c1cf29cd 74
mbed_official 390:35c2c1cf29cd 75 unsigned int l2_id;
mbed_official 390:35c2c1cf29cd 76
mbed_official 390:35c2c1cf29cd 77 /* Invalidate undefined data */
mbed_official 390:35c2c1cf29cd 78 __ca9u_inv_tlb_all();
mbed_official 390:35c2c1cf29cd 79 __v7_inv_icache_all();
mbed_official 390:35c2c1cf29cd 80 __v7_inv_dcache_all();
mbed_official 390:35c2c1cf29cd 81 __v7_inv_btac();
mbed_official 390:35c2c1cf29cd 82
mbed_official 390:35c2c1cf29cd 83 /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
mbed_official 390:35c2c1cf29cd 84 * invalidate in order to flush the valid data to the next level cache.
mbed_official 390:35c2c1cf29cd 85 */
mbed_official 390:35c2c1cf29cd 86 __enable_mmu();
mbed_official 390:35c2c1cf29cd 87
mbed_official 390:35c2c1cf29cd 88 /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
mbed_official 390:35c2c1cf29cd 89 __enable_caches();
mbed_official 390:35c2c1cf29cd 90 __enable_btac();
mbed_official 390:35c2c1cf29cd 91
mbed_official 390:35c2c1cf29cd 92 /* If present, you may also need to Invalidate and Enable L2 cache here */
mbed_official 390:35c2c1cf29cd 93 l2_id = PL310_GetID();
mbed_official 390:35c2c1cf29cd 94 if (l2_id)
mbed_official 390:35c2c1cf29cd 95 {
mbed_official 390:35c2c1cf29cd 96 PL310_InvAllByWay();
mbed_official 390:35c2c1cf29cd 97 PL310_Enable();
mbed_official 390:35c2c1cf29cd 98 }
mbed_official 390:35c2c1cf29cd 99 }
mbed_official 390:35c2c1cf29cd 100 #pragma pop
mbed_official 390:35c2c1cf29cd 101
mbed_official 482:d9a48e768ce0 102 #elif defined(__GNUC__)
mbed_official 482:d9a48e768ce0 103
mbed_official 482:d9a48e768ce0 104 void InitMemorySubsystem(void) {
mbed_official 482:d9a48e768ce0 105
mbed_official 482:d9a48e768ce0 106 /* This SVC is specific for reset where data / tlb / btac may contain undefined data, therefore before
mbed_official 482:d9a48e768ce0 107 * enabling the cache you must invalidate the instruction cache, the data cache, TLB, and BTAC.
mbed_official 482:d9a48e768ce0 108 * You are not required to invalidate the main TLB, even though it is recommended for safety
mbed_official 482:d9a48e768ce0 109 * reasons. This ensures compatibility with future revisions of the processor. */
mbed_official 482:d9a48e768ce0 110
mbed_official 482:d9a48e768ce0 111 unsigned int l2_id;
mbed_official 482:d9a48e768ce0 112
mbed_official 482:d9a48e768ce0 113 /* Invalidate undefined data */
mbed_official 482:d9a48e768ce0 114 __ca9u_inv_tlb_all();
mbed_official 482:d9a48e768ce0 115 __v7_inv_icache_all();
mbed_official 482:d9a48e768ce0 116 __v7_inv_dcache_all();
mbed_official 482:d9a48e768ce0 117 __v7_inv_btac();
mbed_official 482:d9a48e768ce0 118
mbed_official 482:d9a48e768ce0 119 /* Don't use this function during runtime since caches may contain valid data. For a correct cache maintenance you may need to execute a clean and
mbed_official 482:d9a48e768ce0 120 * invalidate in order to flush the valid data to the next level cache.
mbed_official 482:d9a48e768ce0 121 */
mbed_official 482:d9a48e768ce0 122 __enable_mmu();
mbed_official 482:d9a48e768ce0 123
mbed_official 482:d9a48e768ce0 124 /* After MMU is enabled and data has been invalidated, enable caches and BTAC */
mbed_official 482:d9a48e768ce0 125 __enable_caches();
mbed_official 482:d9a48e768ce0 126 __enable_btac();
mbed_official 482:d9a48e768ce0 127
mbed_official 482:d9a48e768ce0 128 /* If present, you may also need to Invalidate and Enable L2 cache here */
mbed_official 482:d9a48e768ce0 129 l2_id = PL310_GetID();
mbed_official 482:d9a48e768ce0 130 if (l2_id)
mbed_official 482:d9a48e768ce0 131 {
mbed_official 482:d9a48e768ce0 132 PL310_InvAllByWay();
mbed_official 482:d9a48e768ce0 133 PL310_Enable();
mbed_official 482:d9a48e768ce0 134 }
mbed_official 482:d9a48e768ce0 135 }
mbed_official 482:d9a48e768ce0 136 #else
mbed_official 482:d9a48e768ce0 137
mbed_official 482:d9a48e768ce0 138 #endif
mbed_official 482:d9a48e768ce0 139
mbed_official 482:d9a48e768ce0 140
mbed_official 390:35c2c1cf29cd 141 IRQHandler IRQTable[Renesas_RZ_A1_IRQ_MAX+1];
mbed_official 390:35c2c1cf29cd 142
mbed_official 390:35c2c1cf29cd 143 uint32_t IRQCount = sizeof IRQTable / 4;
mbed_official 390:35c2c1cf29cd 144
mbed_official 390:35c2c1cf29cd 145 uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
mbed_official 390:35c2c1cf29cd 146 {
mbed_official 390:35c2c1cf29cd 147 if (irq < IRQCount) {
mbed_official 390:35c2c1cf29cd 148 IRQTable[irq] = handler;
mbed_official 390:35c2c1cf29cd 149 return 0;
mbed_official 390:35c2c1cf29cd 150 }
mbed_official 390:35c2c1cf29cd 151 else {
mbed_official 390:35c2c1cf29cd 152 return 1;
mbed_official 390:35c2c1cf29cd 153 }
mbed_official 390:35c2c1cf29cd 154 }
mbed_official 390:35c2c1cf29cd 155
mbed_official 390:35c2c1cf29cd 156 uint32_t InterruptHandlerUnregister (IRQn_Type irq)
mbed_official 390:35c2c1cf29cd 157 {
mbed_official 390:35c2c1cf29cd 158 if (irq < IRQCount) {
mbed_official 390:35c2c1cf29cd 159 IRQTable[irq] = 0;
mbed_official 390:35c2c1cf29cd 160 return 0;
mbed_official 390:35c2c1cf29cd 161 }
mbed_official 390:35c2c1cf29cd 162 else {
mbed_official 390:35c2c1cf29cd 163 return 1;
mbed_official 390:35c2c1cf29cd 164 }
mbed_official 390:35c2c1cf29cd 165 }
mbed_official 390:35c2c1cf29cd 166
mbed_official 390:35c2c1cf29cd 167 /**
mbed_official 390:35c2c1cf29cd 168 * Initialize the system
mbed_official 390:35c2c1cf29cd 169 *
mbed_official 390:35c2c1cf29cd 170 * @param none
mbed_official 390:35c2c1cf29cd 171 * @return none
mbed_official 390:35c2c1cf29cd 172 *
mbed_official 390:35c2c1cf29cd 173 * @brief Setup the microcontroller system.
mbed_official 390:35c2c1cf29cd 174 * Initialize the System.
mbed_official 390:35c2c1cf29cd 175 */
mbed_official 390:35c2c1cf29cd 176 void SystemInit (void)
mbed_official 390:35c2c1cf29cd 177 {
mbed_official 390:35c2c1cf29cd 178 IRQNestLevel = 0;
mbed_official 390:35c2c1cf29cd 179 /* do not use global variables because this function is called before
mbed_official 390:35c2c1cf29cd 180 reaching pre-main. RW section maybe overwritten afterwards. */
mbed_official 390:35c2c1cf29cd 181 RZ_A1_InitClock();
mbed_official 390:35c2c1cf29cd 182 RZ_A1_InitBus();
mbed_official 390:35c2c1cf29cd 183
mbed_official 390:35c2c1cf29cd 184 //Configure GIC ICDICFR GIC_SetICDICFR()
mbed_official 390:35c2c1cf29cd 185 GIC_Enable();
mbed_official 390:35c2c1cf29cd 186 __enable_irq();
mbed_official 390:35c2c1cf29cd 187
mbed_official 390:35c2c1cf29cd 188 }
mbed_official 390:35c2c1cf29cd 189
mbed_official 390:35c2c1cf29cd 190
mbed_official 390:35c2c1cf29cd 191 //Fault Status Register (IFSR/DFSR) definitions
mbed_official 390:35c2c1cf29cd 192 #define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
mbed_official 626:ba773d547214 193 #define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
mbed_official 390:35c2c1cf29cd 194 #define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
mbed_official 390:35c2c1cf29cd 195 #define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
mbed_official 390:35c2c1cf29cd 196 #define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
mbed_official 390:35c2c1cf29cd 197 #define FSR_SYNC_PARITY_TTB_WALK_SECOND 0x1e //sync/external
mbed_official 390:35c2c1cf29cd 198 #define FSR_TRANSLATION_FAULT_FIRST 0x05 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 199 #define FSR_TRANSLATION_FAULT_SECOND 0x07 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 200 #define FSR_ACCESS_FLAG_FAULT_FIRST 0x03 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 201 #define FSR_ACCESS_FLAG_FAULT_SECOND 0x06 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 202 #define FSR_DOMAIN_FAULT_FIRST 0x09 //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 203 #define FSR_DOMAIN_FAULT_SECOND 0x0b //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 204 #define FSR_PERMISION_FAULT_FIRST 0x0f //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 205 #define FSR_PERMISION_FAULT_SECOND 0x0d //MMU Fault - internal
mbed_official 390:35c2c1cf29cd 206 #define FSR_DEBUG_EVENT 0x02 //internal
mbed_official 390:35c2c1cf29cd 207 #define FSR_SYNC_EXT_ABORT 0x08 //sync/external
mbed_official 390:35c2c1cf29cd 208 #define FSR_TLB_CONFLICT_ABORT 0x10 //sync/external
mbed_official 390:35c2c1cf29cd 209 #define FSR_LOCKDOWN 0x14 //internal
mbed_official 390:35c2c1cf29cd 210 #define FSR_COPROCESSOR_ABORT 0x1a //internal
mbed_official 390:35c2c1cf29cd 211 #define FSR_SYNC_PARITY_ERROR 0x19 //sync/external
mbed_official 390:35c2c1cf29cd 212 #define FSR_ASYNC_EXTERNAL_ABORT 0x16 //DFSR only - async/external
mbed_official 390:35c2c1cf29cd 213 #define FSR_ASYNC_PARITY_ERROR 0x18 //DFSR only - async/external
mbed_official 390:35c2c1cf29cd 214
mbed_official 390:35c2c1cf29cd 215 void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
mbed_official 390:35c2c1cf29cd 216 uint32_t FS = (DFSR & (1 << 10)) >> 6 | (DFSR & 0x0f); //Store Fault Status
mbed_official 390:35c2c1cf29cd 217
mbed_official 390:35c2c1cf29cd 218 switch(FS) {
mbed_official 390:35c2c1cf29cd 219 //Synchronous parity errors - retry
mbed_official 390:35c2c1cf29cd 220 case FSR_SYNC_PARITY_ERROR:
mbed_official 390:35c2c1cf29cd 221 case FSR_SYNC_PARITY_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 222 case FSR_SYNC_PARITY_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 223 return;
mbed_official 390:35c2c1cf29cd 224
mbed_official 390:35c2c1cf29cd 225 //Your code here. Value in DFAR is invalid for some fault statuses.
mbed_official 390:35c2c1cf29cd 226 case FSR_ALIGNMENT_FAULT:
mbed_official 626:ba773d547214 227 case FSR_INSTRUCTION_CACHE_MAINTENANCE:
mbed_official 390:35c2c1cf29cd 228 case FSR_SYNC_EXT_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 229 case FSR_SYNC_EXT_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 230 case FSR_TRANSLATION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 231 case FSR_TRANSLATION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 232 case FSR_ACCESS_FLAG_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 233 case FSR_ACCESS_FLAG_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 234 case FSR_DOMAIN_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 235 case FSR_DOMAIN_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 236 case FSR_PERMISION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 237 case FSR_PERMISION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 238 case FSR_DEBUG_EVENT:
mbed_official 390:35c2c1cf29cd 239 case FSR_SYNC_EXT_ABORT:
mbed_official 390:35c2c1cf29cd 240 case FSR_TLB_CONFLICT_ABORT:
mbed_official 390:35c2c1cf29cd 241 case FSR_LOCKDOWN:
mbed_official 390:35c2c1cf29cd 242 case FSR_COPROCESSOR_ABORT:
mbed_official 390:35c2c1cf29cd 243 case FSR_ASYNC_EXTERNAL_ABORT: //DFAR invalid
mbed_official 390:35c2c1cf29cd 244 case FSR_ASYNC_PARITY_ERROR: //DFAR invalid
mbed_official 390:35c2c1cf29cd 245 default:
mbed_official 390:35c2c1cf29cd 246 while(1);
mbed_official 390:35c2c1cf29cd 247 }
mbed_official 390:35c2c1cf29cd 248 }
mbed_official 390:35c2c1cf29cd 249
mbed_official 390:35c2c1cf29cd 250 void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
mbed_official 390:35c2c1cf29cd 251 uint32_t FS = (IFSR & (1 << 10)) >> 6 | (IFSR & 0x0f); //Store Fault Status
mbed_official 390:35c2c1cf29cd 252
mbed_official 390:35c2c1cf29cd 253 switch(FS) {
mbed_official 390:35c2c1cf29cd 254 //Synchronous parity errors - retry
mbed_official 390:35c2c1cf29cd 255 case FSR_SYNC_PARITY_ERROR:
mbed_official 390:35c2c1cf29cd 256 case FSR_SYNC_PARITY_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 257 case FSR_SYNC_PARITY_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 258 return;
mbed_official 390:35c2c1cf29cd 259
mbed_official 390:35c2c1cf29cd 260 //Your code here. Value in IFAR is invalid for some fault statuses.
mbed_official 390:35c2c1cf29cd 261 case FSR_SYNC_EXT_TTB_WALK_FIRST:
mbed_official 390:35c2c1cf29cd 262 case FSR_SYNC_EXT_TTB_WALK_SECOND:
mbed_official 390:35c2c1cf29cd 263 case FSR_TRANSLATION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 264 case FSR_TRANSLATION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 265 case FSR_ACCESS_FLAG_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 266 case FSR_ACCESS_FLAG_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 267 case FSR_DOMAIN_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 268 case FSR_DOMAIN_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 269 case FSR_PERMISION_FAULT_FIRST:
mbed_official 390:35c2c1cf29cd 270 case FSR_PERMISION_FAULT_SECOND:
mbed_official 390:35c2c1cf29cd 271 case FSR_DEBUG_EVENT: //IFAR invalid
mbed_official 390:35c2c1cf29cd 272 case FSR_SYNC_EXT_ABORT:
mbed_official 390:35c2c1cf29cd 273 case FSR_TLB_CONFLICT_ABORT:
mbed_official 390:35c2c1cf29cd 274 case FSR_LOCKDOWN:
mbed_official 390:35c2c1cf29cd 275 case FSR_COPROCESSOR_ABORT:
mbed_official 390:35c2c1cf29cd 276 default:
mbed_official 390:35c2c1cf29cd 277 while(1);
mbed_official 390:35c2c1cf29cd 278 }
mbed_official 390:35c2c1cf29cd 279 }
mbed_official 390:35c2c1cf29cd 280
mbed_official 390:35c2c1cf29cd 281 //returns amount to decrement lr by
mbed_official 626:ba773d547214 282 //this will be 0 when we have emulated the instruction and want to execute the next instruction
mbed_official 626:ba773d547214 283 //this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
mbed_official 626:ba773d547214 284 //this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
mbed_official 390:35c2c1cf29cd 285 uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
mbed_official 482:d9a48e768ce0 286 const unsigned int THUMB = 2;
mbed_official 482:d9a48e768ce0 287 const unsigned int ARM = 4;
mbed_official 390:35c2c1cf29cd 288 //Lazy VFP/NEON initialisation and switching
mbed_official 626:ba773d547214 289
mbed_official 626:ba773d547214 290 // (ARM ARM section A7.5) VFP data processing instruction?
mbed_official 626:ba773d547214 291 // (ARM ARM section A7.6) VFP/NEON register load/store instruction?
mbed_official 626:ba773d547214 292 // (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
mbed_official 626:ba773d547214 293 // (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
mbed_official 626:ba773d547214 294 if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
mbed_official 626:ba773d547214 295 (state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
mbed_official 626:ba773d547214 296 if (((opcode & 0x00000E00) >> 9) == 5) {
mbed_official 390:35c2c1cf29cd 297 FPUEnable();
mbed_official 390:35c2c1cf29cd 298 return state;
mbed_official 390:35c2c1cf29cd 299 }
mbed_official 390:35c2c1cf29cd 300 }
mbed_official 390:35c2c1cf29cd 301
mbed_official 626:ba773d547214 302 // (ARM ARM section A7.4) NEON data processing instruction?
mbed_official 626:ba773d547214 303 if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
mbed_official 626:ba773d547214 304 (state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
mbed_official 626:ba773d547214 305 // (ARM ARM section A7.7) NEON load/store instruction?
mbed_official 626:ba773d547214 306 (state == ARM && ((opcode >> 24) == 0xF4)) ||
mbed_official 626:ba773d547214 307 (state == THUMB && ((opcode >> 24) == 0xF9))) {
mbed_official 626:ba773d547214 308 FPUEnable();
mbed_official 626:ba773d547214 309 return state;
mbed_official 626:ba773d547214 310 }
mbed_official 626:ba773d547214 311
mbed_official 390:35c2c1cf29cd 312 //Add code here for other Undef cases
mbed_official 390:35c2c1cf29cd 313 while(1);
mbed_official 390:35c2c1cf29cd 314 }
mbed_official 390:35c2c1cf29cd 315
mbed_official 482:d9a48e768ce0 316 #if defined(__ARMCC_VERSION)
mbed_official 390:35c2c1cf29cd 317 #pragma push
mbed_official 390:35c2c1cf29cd 318 #pragma arm
mbed_official 390:35c2c1cf29cd 319 //Critical section, called from undef handler, so systick is disabled
mbed_official 390:35c2c1cf29cd 320 __asm void FPUEnable(void) {
mbed_official 390:35c2c1cf29cd 321 ARM
mbed_official 390:35c2c1cf29cd 322
mbed_official 626:ba773d547214 323 //Permit access to VFP/NEON, registers by modifying CPACR
mbed_official 390:35c2c1cf29cd 324 MRC p15,0,R1,c1,c0,2
mbed_official 390:35c2c1cf29cd 325 ORR R1,R1,#0x00F00000
mbed_official 390:35c2c1cf29cd 326 MCR p15,0,R1,c1,c0,2
mbed_official 390:35c2c1cf29cd 327
mbed_official 626:ba773d547214 328 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
mbed_official 626:ba773d547214 329 ISB
mbed_official 626:ba773d547214 330
mbed_official 626:ba773d547214 331 //Enable VFP/NEON
mbed_official 390:35c2c1cf29cd 332 VMRS R1,FPEXC
mbed_official 390:35c2c1cf29cd 333 ORR R1,R1,#0x40000000
mbed_official 390:35c2c1cf29cd 334 VMSR FPEXC,R1
mbed_official 390:35c2c1cf29cd 335
mbed_official 626:ba773d547214 336 //Initialise VFP/NEON registers to 0
mbed_official 390:35c2c1cf29cd 337 MOV R2,#0
mbed_official 626:ba773d547214 338 //Initialise D16 registers to 0
mbed_official 390:35c2c1cf29cd 339 VMOV D0, R2,R2
mbed_official 390:35c2c1cf29cd 340 VMOV D1, R2,R2
mbed_official 390:35c2c1cf29cd 341 VMOV D2, R2,R2
mbed_official 390:35c2c1cf29cd 342 VMOV D3, R2,R2
mbed_official 390:35c2c1cf29cd 343 VMOV D4, R2,R2
mbed_official 390:35c2c1cf29cd 344 VMOV D5, R2,R2
mbed_official 390:35c2c1cf29cd 345 VMOV D6, R2,R2
mbed_official 390:35c2c1cf29cd 346 VMOV D7, R2,R2
mbed_official 390:35c2c1cf29cd 347 VMOV D8, R2,R2
mbed_official 390:35c2c1cf29cd 348 VMOV D9, R2,R2
mbed_official 390:35c2c1cf29cd 349 VMOV D10,R2,R2
mbed_official 390:35c2c1cf29cd 350 VMOV D11,R2,R2
mbed_official 390:35c2c1cf29cd 351 VMOV D12,R2,R2
mbed_official 390:35c2c1cf29cd 352 VMOV D13,R2,R2
mbed_official 390:35c2c1cf29cd 353 VMOV D14,R2,R2
mbed_official 390:35c2c1cf29cd 354 VMOV D15,R2,R2
mbed_official 626:ba773d547214 355 //Initialise D32 registers to 0
mbed_official 626:ba773d547214 356 VMOV D16,R2,R2
mbed_official 626:ba773d547214 357 VMOV D17,R2,R2
mbed_official 626:ba773d547214 358 VMOV D18,R2,R2
mbed_official 626:ba773d547214 359 VMOV D19,R2,R2
mbed_official 626:ba773d547214 360 VMOV D20,R2,R2
mbed_official 626:ba773d547214 361 VMOV D21,R2,R2
mbed_official 626:ba773d547214 362 VMOV D22,R2,R2
mbed_official 626:ba773d547214 363 VMOV D23,R2,R2
mbed_official 626:ba773d547214 364 VMOV D24,R2,R2
mbed_official 626:ba773d547214 365 VMOV D25,R2,R2
mbed_official 626:ba773d547214 366 VMOV D26,R2,R2
mbed_official 626:ba773d547214 367 VMOV D27,R2,R2
mbed_official 626:ba773d547214 368 VMOV D28,R2,R2
mbed_official 626:ba773d547214 369 VMOV D29,R2,R2
mbed_official 626:ba773d547214 370 VMOV D30,R2,R2
mbed_official 626:ba773d547214 371 VMOV D31,R2,R2
mbed_official 390:35c2c1cf29cd 372 //Initialise FPSCR to a known state
mbed_official 390:35c2c1cf29cd 373 VMRS R2,FPSCR
mbed_official 390:35c2c1cf29cd 374 LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
mbed_official 390:35c2c1cf29cd 375 AND R2,R2,R3
mbed_official 390:35c2c1cf29cd 376 VMSR FPSCR,R2
mbed_official 390:35c2c1cf29cd 377
mbed_official 390:35c2c1cf29cd 378 BX LR
mbed_official 390:35c2c1cf29cd 379 }
mbed_official 390:35c2c1cf29cd 380 #pragma pop
mbed_official 482:d9a48e768ce0 381
mbed_official 482:d9a48e768ce0 382 #elif defined(__GNUC__)
mbed_official 626:ba773d547214 383 void FPUEnable(void) {
mbed_official 626:ba773d547214 384 __asm__ (
mbed_official 626:ba773d547214 385 ".ARM;"
mbed_official 626:ba773d547214 386
mbed_official 626:ba773d547214 387 //Permit access to VFP/NEON, registers by modifying CPACR
mbed_official 626:ba773d547214 388 "MRC p15,0,R1,c1,c0,2;"
mbed_official 626:ba773d547214 389 "ORR R1,R1,#0x00F00000;"
mbed_official 626:ba773d547214 390 "MCR p15,0,R1,c1,c0,2;"
mbed_official 626:ba773d547214 391
mbed_official 626:ba773d547214 392 //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
mbed_official 626:ba773d547214 393 "ISB;"
mbed_official 626:ba773d547214 394
mbed_official 626:ba773d547214 395 //Enable VFP/NEON
mbed_official 626:ba773d547214 396 "VMRS R1,FPEXC;"
mbed_official 626:ba773d547214 397 "ORR R1,R1,#0x40000000;"
mbed_official 626:ba773d547214 398 "VMSR FPEXC,R1;"
mbed_official 626:ba773d547214 399
mbed_official 626:ba773d547214 400 //Initialise VFP/NEON registers to 0
mbed_official 626:ba773d547214 401 "MOV R2,#0;"
mbed_official 626:ba773d547214 402 //Initialise D16 registers to 0
mbed_official 626:ba773d547214 403 "VMOV D0, R2,R2;"
mbed_official 626:ba773d547214 404 "VMOV D1, R2,R2;"
mbed_official 626:ba773d547214 405 "VMOV D2, R2,R2;"
mbed_official 626:ba773d547214 406 "VMOV D3, R2,R2;"
mbed_official 626:ba773d547214 407 "VMOV D4, R2,R2;"
mbed_official 626:ba773d547214 408 "VMOV D5, R2,R2;"
mbed_official 626:ba773d547214 409 "VMOV D6, R2,R2;"
mbed_official 626:ba773d547214 410 "VMOV D7, R2,R2;"
mbed_official 626:ba773d547214 411 "VMOV D8, R2,R2;"
mbed_official 626:ba773d547214 412 "VMOV D9, R2,R2;"
mbed_official 626:ba773d547214 413 "VMOV D10,R2,R2;"
mbed_official 626:ba773d547214 414 "VMOV D11,R2,R2;"
mbed_official 626:ba773d547214 415 "VMOV D12,R2,R2;"
mbed_official 626:ba773d547214 416 "VMOV D13,R2,R2;"
mbed_official 626:ba773d547214 417 "VMOV D14,R2,R2;"
mbed_official 626:ba773d547214 418 "VMOV D15,R2,R2;"
mbed_official 626:ba773d547214 419 //Initialise D32 registers to 0
mbed_official 626:ba773d547214 420 "VMOV D16,R2,R2;"
mbed_official 626:ba773d547214 421 "VMOV D17,R2,R2;"
mbed_official 626:ba773d547214 422 "VMOV D18,R2,R2;"
mbed_official 626:ba773d547214 423 "VMOV D19,R2,R2;"
mbed_official 626:ba773d547214 424 "VMOV D20,R2,R2;"
mbed_official 626:ba773d547214 425 "VMOV D21,R2,R2;"
mbed_official 626:ba773d547214 426 "VMOV D22,R2,R2;"
mbed_official 626:ba773d547214 427 "VMOV D23,R2,R2;"
mbed_official 626:ba773d547214 428 "VMOV D24,R2,R2;"
mbed_official 626:ba773d547214 429 "VMOV D25,R2,R2;"
mbed_official 626:ba773d547214 430 "VMOV D26,R2,R2;"
mbed_official 626:ba773d547214 431 "VMOV D27,R2,R2;"
mbed_official 626:ba773d547214 432 "VMOV D28,R2,R2;"
mbed_official 626:ba773d547214 433 "VMOV D29,R2,R2;"
mbed_official 626:ba773d547214 434 "VMOV D30,R2,R2;"
mbed_official 626:ba773d547214 435 "VMOV D31,R2,R2;"
mbed_official 626:ba773d547214 436
mbed_official 626:ba773d547214 437 //Initialise FPSCR to a known state
mbed_official 626:ba773d547214 438 "VMRS R2,FPSCR;"
mbed_official 626:ba773d547214 439 "LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
mbed_official 626:ba773d547214 440 "AND R2,R2,R3;"
mbed_official 626:ba773d547214 441 "VMSR FPSCR,R2;"
mbed_official 626:ba773d547214 442
mbed_official 626:ba773d547214 443 //"BX LR;"
mbed_official 626:ba773d547214 444 :
mbed_official 626:ba773d547214 445 :
mbed_official 626:ba773d547214 446 :"r1", "r2", "r3");
mbed_official 626:ba773d547214 447 return;
mbed_official 482:d9a48e768ce0 448 }
mbed_official 482:d9a48e768ce0 449 #else
mbed_official 482:d9a48e768ce0 450 #endif
mbed_official 482:d9a48e768ce0 451