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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h@573:ad23fe03a082, 2015-06-19 (annotated)

Committer:
mbed_official
Date:
Fri Jun 19 09:15:11 2015 +0100
Revision:
573:ad23fe03a082
Child:
610:813dcc80987e
Synchronized with git revision d47834cd4d729e5b36b4c1ad4650f8b8f6a9ab86



Full URL: https://github.com/mbedmicro/mbed/commit/d47834cd4d729e5b36b4c1ad4650f8b8f6a9ab86/



DISCO_F746NG - Add new target

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 573:ad23fe03a082 1 /**
mbed_official 573:ad23fe03a082 2 ******************************************************************************
mbed_official 573:ad23fe03a082 3 * @file stm32f7xx_hal_eth.h
mbed_official 573:ad23fe03a082 4 * @author MCD Application Team
mbed_official 573:ad23fe03a082 5 * @version V1.0.0
mbed_official 573:ad23fe03a082 6 * @date 12-May-2015
mbed_official 573:ad23fe03a082 7 * @brief Header file of ETH HAL module.
mbed_official 573:ad23fe03a082 8 ******************************************************************************
mbed_official 573:ad23fe03a082 9 * @attention
mbed_official 573:ad23fe03a082 10 *
mbed_official 573:ad23fe03a082 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 573:ad23fe03a082 12 *
mbed_official 573:ad23fe03a082 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 573:ad23fe03a082 14 * are permitted provided that the following conditions are met:
mbed_official 573:ad23fe03a082 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 573:ad23fe03a082 16 * this list of conditions and the following disclaimer.
mbed_official 573:ad23fe03a082 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 573:ad23fe03a082 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 573:ad23fe03a082 19 * and/or other materials provided with the distribution.
mbed_official 573:ad23fe03a082 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 573:ad23fe03a082 21 * may be used to endorse or promote products derived from this software
mbed_official 573:ad23fe03a082 22 * without specific prior written permission.
mbed_official 573:ad23fe03a082 23 *
mbed_official 573:ad23fe03a082 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 573:ad23fe03a082 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 573:ad23fe03a082 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 573:ad23fe03a082 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 573:ad23fe03a082 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 573:ad23fe03a082 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 573:ad23fe03a082 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 573:ad23fe03a082 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 573:ad23fe03a082 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 573:ad23fe03a082 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 573:ad23fe03a082 34 *
mbed_official 573:ad23fe03a082 35 ******************************************************************************
mbed_official 573:ad23fe03a082 36 */
mbed_official 573:ad23fe03a082 37
mbed_official 573:ad23fe03a082 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 573:ad23fe03a082 39 #ifndef __STM32F7xx_HAL_ETH_H
mbed_official 573:ad23fe03a082 40 #define __STM32F7xx_HAL_ETH_H
mbed_official 573:ad23fe03a082 41
mbed_official 573:ad23fe03a082 42 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 43 extern "C" {
mbed_official 573:ad23fe03a082 44 #endif
mbed_official 573:ad23fe03a082 45
mbed_official 573:ad23fe03a082 46 /* Includes ------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 47 #include "stm32f7xx_hal_def.h"
mbed_official 573:ad23fe03a082 48
mbed_official 573:ad23fe03a082 49 /** @addtogroup STM32F7xx_HAL_Driver
mbed_official 573:ad23fe03a082 50 * @{
mbed_official 573:ad23fe03a082 51 */
mbed_official 573:ad23fe03a082 52
mbed_official 573:ad23fe03a082 53 /** @addtogroup ETH
mbed_official 573:ad23fe03a082 54 * @{
mbed_official 573:ad23fe03a082 55 */
mbed_official 573:ad23fe03a082 56
mbed_official 573:ad23fe03a082 57 /** @addtogroup ETH_Private_Macros
mbed_official 573:ad23fe03a082 58 * @{
mbed_official 573:ad23fe03a082 59 */
mbed_official 573:ad23fe03a082 60 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
mbed_official 573:ad23fe03a082 61 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
mbed_official 573:ad23fe03a082 62 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
mbed_official 573:ad23fe03a082 63 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
mbed_official 573:ad23fe03a082 64 ((SPEED) == ETH_SPEED_100M))
mbed_official 573:ad23fe03a082 65 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
mbed_official 573:ad23fe03a082 66 ((MODE) == ETH_MODE_HALFDUPLEX))
mbed_official 573:ad23fe03a082 67 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
mbed_official 573:ad23fe03a082 68 ((MODE) == ETH_MODE_HALFDUPLEX))
mbed_official 573:ad23fe03a082 69 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
mbed_official 573:ad23fe03a082 70 ((MODE) == ETH_RXINTERRUPT_MODE))
mbed_official 573:ad23fe03a082 71 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
mbed_official 573:ad23fe03a082 72 ((MODE) == ETH_RXINTERRUPT_MODE))
mbed_official 573:ad23fe03a082 73 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
mbed_official 573:ad23fe03a082 74 ((MODE) == ETH_RXINTERRUPT_MODE))
mbed_official 573:ad23fe03a082 75 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
mbed_official 573:ad23fe03a082 76 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
mbed_official 573:ad23fe03a082 77 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
mbed_official 573:ad23fe03a082 78 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
mbed_official 573:ad23fe03a082 79 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
mbed_official 573:ad23fe03a082 80 ((CMD) == ETH_WATCHDOG_DISABLE))
mbed_official 573:ad23fe03a082 81 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
mbed_official 573:ad23fe03a082 82 ((CMD) == ETH_JABBER_DISABLE))
mbed_official 573:ad23fe03a082 83 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
mbed_official 573:ad23fe03a082 84 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
mbed_official 573:ad23fe03a082 85 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
mbed_official 573:ad23fe03a082 86 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
mbed_official 573:ad23fe03a082 87 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
mbed_official 573:ad23fe03a082 88 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
mbed_official 573:ad23fe03a082 89 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
mbed_official 573:ad23fe03a082 90 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
mbed_official 573:ad23fe03a082 91 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
mbed_official 573:ad23fe03a082 92 ((CMD) == ETH_CARRIERSENCE_DISABLE))
mbed_official 573:ad23fe03a082 93 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
mbed_official 573:ad23fe03a082 94 ((CMD) == ETH_RECEIVEOWN_DISABLE))
mbed_official 573:ad23fe03a082 95 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
mbed_official 573:ad23fe03a082 96 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
mbed_official 573:ad23fe03a082 97 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
mbed_official 573:ad23fe03a082 98 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
mbed_official 573:ad23fe03a082 99 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
mbed_official 573:ad23fe03a082 100 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
mbed_official 573:ad23fe03a082 101 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
mbed_official 573:ad23fe03a082 102 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
mbed_official 573:ad23fe03a082 103 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
mbed_official 573:ad23fe03a082 104 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
mbed_official 573:ad23fe03a082 105 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
mbed_official 573:ad23fe03a082 106 ((LIMIT) == ETH_BACKOFFLIMIT_1))
mbed_official 573:ad23fe03a082 107 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
mbed_official 573:ad23fe03a082 108 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
mbed_official 573:ad23fe03a082 109 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
mbed_official 573:ad23fe03a082 110 ((CMD) == ETH_RECEIVEAll_DISABLE))
mbed_official 573:ad23fe03a082 111 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
mbed_official 573:ad23fe03a082 112 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
mbed_official 573:ad23fe03a082 113 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
mbed_official 573:ad23fe03a082 114 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
mbed_official 573:ad23fe03a082 115 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
mbed_official 573:ad23fe03a082 116 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
mbed_official 573:ad23fe03a082 117 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
mbed_official 573:ad23fe03a082 118 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
mbed_official 573:ad23fe03a082 119 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
mbed_official 573:ad23fe03a082 120 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
mbed_official 573:ad23fe03a082 121 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
mbed_official 573:ad23fe03a082 122 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
mbed_official 573:ad23fe03a082 123 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
mbed_official 573:ad23fe03a082 124 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
mbed_official 573:ad23fe03a082 125 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
mbed_official 573:ad23fe03a082 126 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
mbed_official 573:ad23fe03a082 127 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
mbed_official 573:ad23fe03a082 128 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
mbed_official 573:ad23fe03a082 129 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
mbed_official 573:ad23fe03a082 130 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
mbed_official 573:ad23fe03a082 131 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
mbed_official 573:ad23fe03a082 132 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
mbed_official 573:ad23fe03a082 133 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
mbed_official 573:ad23fe03a082 134 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
mbed_official 573:ad23fe03a082 135 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
mbed_official 573:ad23fe03a082 136 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
mbed_official 573:ad23fe03a082 137 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
mbed_official 573:ad23fe03a082 138 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
mbed_official 573:ad23fe03a082 139 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
mbed_official 573:ad23fe03a082 140 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
mbed_official 573:ad23fe03a082 141 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
mbed_official 573:ad23fe03a082 142 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
mbed_official 573:ad23fe03a082 143 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
mbed_official 573:ad23fe03a082 144 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
mbed_official 573:ad23fe03a082 145 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
mbed_official 573:ad23fe03a082 146 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
mbed_official 573:ad23fe03a082 147 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
mbed_official 573:ad23fe03a082 148 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
mbed_official 573:ad23fe03a082 149 ((ADDRESS) == ETH_MAC_ADDRESS3))
mbed_official 573:ad23fe03a082 150 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
mbed_official 573:ad23fe03a082 151 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
mbed_official 573:ad23fe03a082 152 ((ADDRESS) == ETH_MAC_ADDRESS3))
mbed_official 573:ad23fe03a082 153 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
mbed_official 573:ad23fe03a082 154 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
mbed_official 573:ad23fe03a082 155 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
mbed_official 573:ad23fe03a082 156 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
mbed_official 573:ad23fe03a082 157 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
mbed_official 573:ad23fe03a082 158 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
mbed_official 573:ad23fe03a082 159 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
mbed_official 573:ad23fe03a082 160 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
mbed_official 573:ad23fe03a082 161 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
mbed_official 573:ad23fe03a082 162 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
mbed_official 573:ad23fe03a082 163 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
mbed_official 573:ad23fe03a082 164 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
mbed_official 573:ad23fe03a082 165 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
mbed_official 573:ad23fe03a082 166 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
mbed_official 573:ad23fe03a082 167 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
mbed_official 573:ad23fe03a082 168 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
mbed_official 573:ad23fe03a082 169 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
mbed_official 573:ad23fe03a082 170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
mbed_official 573:ad23fe03a082 171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
mbed_official 573:ad23fe03a082 172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
mbed_official 573:ad23fe03a082 173 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
mbed_official 573:ad23fe03a082 174 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
mbed_official 573:ad23fe03a082 175 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
mbed_official 573:ad23fe03a082 176 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
mbed_official 573:ad23fe03a082 177 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
mbed_official 573:ad23fe03a082 178 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
mbed_official 573:ad23fe03a082 179 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
mbed_official 573:ad23fe03a082 180 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
mbed_official 573:ad23fe03a082 181 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
mbed_official 573:ad23fe03a082 182 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
mbed_official 573:ad23fe03a082 183 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
mbed_official 573:ad23fe03a082 184 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
mbed_official 573:ad23fe03a082 185 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
mbed_official 573:ad23fe03a082 186 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
mbed_official 573:ad23fe03a082 187 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
mbed_official 573:ad23fe03a082 188 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
mbed_official 573:ad23fe03a082 189 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
mbed_official 573:ad23fe03a082 190 ((CMD) == ETH_FIXEDBURST_DISABLE))
mbed_official 573:ad23fe03a082 191 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
mbed_official 573:ad23fe03a082 192 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
mbed_official 573:ad23fe03a082 193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
mbed_official 573:ad23fe03a082 194 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
mbed_official 573:ad23fe03a082 195 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
mbed_official 573:ad23fe03a082 196 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
mbed_official 573:ad23fe03a082 197 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
mbed_official 573:ad23fe03a082 198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
mbed_official 573:ad23fe03a082 199 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
mbed_official 573:ad23fe03a082 200 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
mbed_official 573:ad23fe03a082 201 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
mbed_official 573:ad23fe03a082 202 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
mbed_official 573:ad23fe03a082 203 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
mbed_official 573:ad23fe03a082 204 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
mbed_official 573:ad23fe03a082 205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
mbed_official 573:ad23fe03a082 206 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
mbed_official 573:ad23fe03a082 207 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
mbed_official 573:ad23fe03a082 208 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
mbed_official 573:ad23fe03a082 209 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
mbed_official 573:ad23fe03a082 210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
mbed_official 573:ad23fe03a082 211 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
mbed_official 573:ad23fe03a082 212 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
mbed_official 573:ad23fe03a082 213 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
mbed_official 573:ad23fe03a082 214 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
mbed_official 573:ad23fe03a082 215 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
mbed_official 573:ad23fe03a082 216 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
mbed_official 573:ad23fe03a082 217 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
mbed_official 573:ad23fe03a082 218 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
mbed_official 573:ad23fe03a082 219 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
mbed_official 573:ad23fe03a082 220 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
mbed_official 573:ad23fe03a082 221 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
mbed_official 573:ad23fe03a082 222 ((FLAG) == ETH_DMATXDESC_IC) || \
mbed_official 573:ad23fe03a082 223 ((FLAG) == ETH_DMATXDESC_LS) || \
mbed_official 573:ad23fe03a082 224 ((FLAG) == ETH_DMATXDESC_FS) || \
mbed_official 573:ad23fe03a082 225 ((FLAG) == ETH_DMATXDESC_DC) || \
mbed_official 573:ad23fe03a082 226 ((FLAG) == ETH_DMATXDESC_DP) || \
mbed_official 573:ad23fe03a082 227 ((FLAG) == ETH_DMATXDESC_TTSE) || \
mbed_official 573:ad23fe03a082 228 ((FLAG) == ETH_DMATXDESC_TER) || \
mbed_official 573:ad23fe03a082 229 ((FLAG) == ETH_DMATXDESC_TCH) || \
mbed_official 573:ad23fe03a082 230 ((FLAG) == ETH_DMATXDESC_TTSS) || \
mbed_official 573:ad23fe03a082 231 ((FLAG) == ETH_DMATXDESC_IHE) || \
mbed_official 573:ad23fe03a082 232 ((FLAG) == ETH_DMATXDESC_ES) || \
mbed_official 573:ad23fe03a082 233 ((FLAG) == ETH_DMATXDESC_JT) || \
mbed_official 573:ad23fe03a082 234 ((FLAG) == ETH_DMATXDESC_FF) || \
mbed_official 573:ad23fe03a082 235 ((FLAG) == ETH_DMATXDESC_PCE) || \
mbed_official 573:ad23fe03a082 236 ((FLAG) == ETH_DMATXDESC_LCA) || \
mbed_official 573:ad23fe03a082 237 ((FLAG) == ETH_DMATXDESC_NC) || \
mbed_official 573:ad23fe03a082 238 ((FLAG) == ETH_DMATXDESC_LCO) || \
mbed_official 573:ad23fe03a082 239 ((FLAG) == ETH_DMATXDESC_EC) || \
mbed_official 573:ad23fe03a082 240 ((FLAG) == ETH_DMATXDESC_VF) || \
mbed_official 573:ad23fe03a082 241 ((FLAG) == ETH_DMATXDESC_CC) || \
mbed_official 573:ad23fe03a082 242 ((FLAG) == ETH_DMATXDESC_ED) || \
mbed_official 573:ad23fe03a082 243 ((FLAG) == ETH_DMATXDESC_UF) || \
mbed_official 573:ad23fe03a082 244 ((FLAG) == ETH_DMATXDESC_DB))
mbed_official 573:ad23fe03a082 245 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
mbed_official 573:ad23fe03a082 246 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
mbed_official 573:ad23fe03a082 247 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
mbed_official 573:ad23fe03a082 248 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
mbed_official 573:ad23fe03a082 249 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
mbed_official 573:ad23fe03a082 250 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
mbed_official 573:ad23fe03a082 251 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
mbed_official 573:ad23fe03a082 252 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
mbed_official 573:ad23fe03a082 253 ((FLAG) == ETH_DMARXDESC_AFM) || \
mbed_official 573:ad23fe03a082 254 ((FLAG) == ETH_DMARXDESC_ES) || \
mbed_official 573:ad23fe03a082 255 ((FLAG) == ETH_DMARXDESC_DE) || \
mbed_official 573:ad23fe03a082 256 ((FLAG) == ETH_DMARXDESC_SAF) || \
mbed_official 573:ad23fe03a082 257 ((FLAG) == ETH_DMARXDESC_LE) || \
mbed_official 573:ad23fe03a082 258 ((FLAG) == ETH_DMARXDESC_OE) || \
mbed_official 573:ad23fe03a082 259 ((FLAG) == ETH_DMARXDESC_VLAN) || \
mbed_official 573:ad23fe03a082 260 ((FLAG) == ETH_DMARXDESC_FS) || \
mbed_official 573:ad23fe03a082 261 ((FLAG) == ETH_DMARXDESC_LS) || \
mbed_official 573:ad23fe03a082 262 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
mbed_official 573:ad23fe03a082 263 ((FLAG) == ETH_DMARXDESC_LC) || \
mbed_official 573:ad23fe03a082 264 ((FLAG) == ETH_DMARXDESC_FT) || \
mbed_official 573:ad23fe03a082 265 ((FLAG) == ETH_DMARXDESC_RWT) || \
mbed_official 573:ad23fe03a082 266 ((FLAG) == ETH_DMARXDESC_RE) || \
mbed_official 573:ad23fe03a082 267 ((FLAG) == ETH_DMARXDESC_DBE) || \
mbed_official 573:ad23fe03a082 268 ((FLAG) == ETH_DMARXDESC_CE) || \
mbed_official 573:ad23fe03a082 269 ((FLAG) == ETH_DMARXDESC_MAMPCE))
mbed_official 573:ad23fe03a082 270 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
mbed_official 573:ad23fe03a082 271 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
mbed_official 573:ad23fe03a082 272 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
mbed_official 573:ad23fe03a082 273 ((FLAG) == ETH_PMT_FLAG_MPR))
mbed_official 573:ad23fe03a082 274 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
mbed_official 573:ad23fe03a082 275 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
mbed_official 573:ad23fe03a082 276 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
mbed_official 573:ad23fe03a082 277 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
mbed_official 573:ad23fe03a082 278 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
mbed_official 573:ad23fe03a082 279 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
mbed_official 573:ad23fe03a082 280 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
mbed_official 573:ad23fe03a082 281 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
mbed_official 573:ad23fe03a082 282 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
mbed_official 573:ad23fe03a082 283 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
mbed_official 573:ad23fe03a082 284 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
mbed_official 573:ad23fe03a082 285 ((FLAG) == ETH_DMA_FLAG_T))
mbed_official 573:ad23fe03a082 286 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
mbed_official 573:ad23fe03a082 287 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
mbed_official 573:ad23fe03a082 288 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
mbed_official 573:ad23fe03a082 289 ((IT) == ETH_MAC_IT_PMT))
mbed_official 573:ad23fe03a082 290 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
mbed_official 573:ad23fe03a082 291 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
mbed_official 573:ad23fe03a082 292 ((FLAG) == ETH_MAC_FLAG_PMT))
mbed_official 573:ad23fe03a082 293 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
mbed_official 573:ad23fe03a082 294 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
mbed_official 573:ad23fe03a082 295 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
mbed_official 573:ad23fe03a082 296 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
mbed_official 573:ad23fe03a082 297 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
mbed_official 573:ad23fe03a082 298 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
mbed_official 573:ad23fe03a082 299 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
mbed_official 573:ad23fe03a082 300 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
mbed_official 573:ad23fe03a082 301 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
mbed_official 573:ad23fe03a082 302 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
mbed_official 573:ad23fe03a082 303 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
mbed_official 573:ad23fe03a082 304 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
mbed_official 573:ad23fe03a082 305 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
mbed_official 573:ad23fe03a082 306 ((IT) != 0x00))
mbed_official 573:ad23fe03a082 307 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
mbed_official 573:ad23fe03a082 308 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
mbed_official 573:ad23fe03a082 309 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
mbed_official 573:ad23fe03a082 310 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
mbed_official 573:ad23fe03a082 311 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
mbed_official 573:ad23fe03a082 312
mbed_official 573:ad23fe03a082 313
mbed_official 573:ad23fe03a082 314 /**
mbed_official 573:ad23fe03a082 315 * @}
mbed_official 573:ad23fe03a082 316 */
mbed_official 573:ad23fe03a082 317
mbed_official 573:ad23fe03a082 318 /** @addtogroup ETH_Private_Defines
mbed_official 573:ad23fe03a082 319 * @{
mbed_official 573:ad23fe03a082 320 */
mbed_official 573:ad23fe03a082 321 /* Delay to wait when writing to some Ethernet registers */
mbed_official 573:ad23fe03a082 322 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 323
mbed_official 573:ad23fe03a082 324 /* ETHERNET Errors */
mbed_official 573:ad23fe03a082 325 #define ETH_SUCCESS ((uint32_t)0)
mbed_official 573:ad23fe03a082 326 #define ETH_ERROR ((uint32_t)1)
mbed_official 573:ad23fe03a082 327
mbed_official 573:ad23fe03a082 328 /* ETHERNET DMA Tx descriptors Collision Count Shift */
mbed_official 573:ad23fe03a082 329 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
mbed_official 573:ad23fe03a082 330
mbed_official 573:ad23fe03a082 331 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
mbed_official 573:ad23fe03a082 332 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
mbed_official 573:ad23fe03a082 333
mbed_official 573:ad23fe03a082 334 /* ETHERNET DMA Rx descriptors Frame Length Shift */
mbed_official 573:ad23fe03a082 335 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
mbed_official 573:ad23fe03a082 336
mbed_official 573:ad23fe03a082 337 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
mbed_official 573:ad23fe03a082 338 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
mbed_official 573:ad23fe03a082 339
mbed_official 573:ad23fe03a082 340 /* ETHERNET DMA Rx descriptors Frame length Shift */
mbed_official 573:ad23fe03a082 341 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
mbed_official 573:ad23fe03a082 342
mbed_official 573:ad23fe03a082 343 /* ETHERNET MAC address offsets */
mbed_official 573:ad23fe03a082 344 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
mbed_official 573:ad23fe03a082 345 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
mbed_official 573:ad23fe03a082 346
mbed_official 573:ad23fe03a082 347 /* ETHERNET MACMIIAR register Mask */
mbed_official 573:ad23fe03a082 348 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
mbed_official 573:ad23fe03a082 349
mbed_official 573:ad23fe03a082 350 /* ETHERNET MACCR register Mask */
mbed_official 573:ad23fe03a082 351 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
mbed_official 573:ad23fe03a082 352
mbed_official 573:ad23fe03a082 353 /* ETHERNET MACFCR register Mask */
mbed_official 573:ad23fe03a082 354 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
mbed_official 573:ad23fe03a082 355
mbed_official 573:ad23fe03a082 356 /* ETHERNET DMAOMR register Mask */
mbed_official 573:ad23fe03a082 357 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
mbed_official 573:ad23fe03a082 358
mbed_official 573:ad23fe03a082 359 /* ETHERNET Remote Wake-up frame register length */
mbed_official 573:ad23fe03a082 360 #define ETH_WAKEUP_REGISTER_LENGTH 8
mbed_official 573:ad23fe03a082 361
mbed_official 573:ad23fe03a082 362 /* ETHERNET Missed frames counter Shift */
mbed_official 573:ad23fe03a082 363 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
mbed_official 573:ad23fe03a082 364 /**
mbed_official 573:ad23fe03a082 365 * @}
mbed_official 573:ad23fe03a082 366 */
mbed_official 573:ad23fe03a082 367
mbed_official 573:ad23fe03a082 368 /* Exported types ------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 369 /** @defgroup ETH_Exported_Types ETH Exported Types
mbed_official 573:ad23fe03a082 370 * @{
mbed_official 573:ad23fe03a082 371 */
mbed_official 573:ad23fe03a082 372
mbed_official 573:ad23fe03a082 373 /**
mbed_official 573:ad23fe03a082 374 * @brief HAL State structures definition
mbed_official 573:ad23fe03a082 375 */
mbed_official 573:ad23fe03a082 376 typedef enum
mbed_official 573:ad23fe03a082 377 {
mbed_official 573:ad23fe03a082 378 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
mbed_official 573:ad23fe03a082 379 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
mbed_official 573:ad23fe03a082 380 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
mbed_official 573:ad23fe03a082 381 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
mbed_official 573:ad23fe03a082 382 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
mbed_official 573:ad23fe03a082 383 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
mbed_official 573:ad23fe03a082 384 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
mbed_official 573:ad23fe03a082 385 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
mbed_official 573:ad23fe03a082 386 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
mbed_official 573:ad23fe03a082 387 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
mbed_official 573:ad23fe03a082 388 }HAL_ETH_StateTypeDef;
mbed_official 573:ad23fe03a082 389
mbed_official 573:ad23fe03a082 390 /**
mbed_official 573:ad23fe03a082 391 * @brief ETH Init Structure definition
mbed_official 573:ad23fe03a082 392 */
mbed_official 573:ad23fe03a082 393
mbed_official 573:ad23fe03a082 394 typedef struct
mbed_official 573:ad23fe03a082 395 {
mbed_official 573:ad23fe03a082 396 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
mbed_official 573:ad23fe03a082 397 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
mbed_official 573:ad23fe03a082 398 and the mode (half/full-duplex).
mbed_official 573:ad23fe03a082 399 This parameter can be a value of @ref ETH_AutoNegotiation */
mbed_official 573:ad23fe03a082 400
mbed_official 573:ad23fe03a082 401 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
mbed_official 573:ad23fe03a082 402 This parameter can be a value of @ref ETH_Speed */
mbed_official 573:ad23fe03a082 403
mbed_official 573:ad23fe03a082 404 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
mbed_official 573:ad23fe03a082 405 This parameter can be a value of @ref ETH_Duplex_Mode */
mbed_official 573:ad23fe03a082 406
mbed_official 573:ad23fe03a082 407 uint16_t PhyAddress; /*!< Ethernet PHY address.
mbed_official 573:ad23fe03a082 408 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
mbed_official 573:ad23fe03a082 409
mbed_official 573:ad23fe03a082 410 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
mbed_official 573:ad23fe03a082 411
mbed_official 573:ad23fe03a082 412 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
mbed_official 573:ad23fe03a082 413 This parameter can be a value of @ref ETH_Rx_Mode */
mbed_official 573:ad23fe03a082 414
mbed_official 573:ad23fe03a082 415 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
mbed_official 573:ad23fe03a082 416 This parameter can be a value of @ref ETH_Checksum_Mode */
mbed_official 573:ad23fe03a082 417
mbed_official 573:ad23fe03a082 418 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
mbed_official 573:ad23fe03a082 419 This parameter can be a value of @ref ETH_Media_Interface */
mbed_official 573:ad23fe03a082 420
mbed_official 573:ad23fe03a082 421 } ETH_InitTypeDef;
mbed_official 573:ad23fe03a082 422
mbed_official 573:ad23fe03a082 423
mbed_official 573:ad23fe03a082 424 /**
mbed_official 573:ad23fe03a082 425 * @brief ETH MAC Configuration Structure definition
mbed_official 573:ad23fe03a082 426 */
mbed_official 573:ad23fe03a082 427
mbed_official 573:ad23fe03a082 428 typedef struct
mbed_official 573:ad23fe03a082 429 {
mbed_official 573:ad23fe03a082 430 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
mbed_official 573:ad23fe03a082 431 When enabled, the MAC allows no more then 2048 bytes to be received.
mbed_official 573:ad23fe03a082 432 When disabled, the MAC can receive up to 16384 bytes.
mbed_official 573:ad23fe03a082 433 This parameter can be a value of @ref ETH_Watchdog */
mbed_official 573:ad23fe03a082 434
mbed_official 573:ad23fe03a082 435 uint32_t Jabber; /*!< Selects or not Jabber timer
mbed_official 573:ad23fe03a082 436 When enabled, the MAC allows no more then 2048 bytes to be sent.
mbed_official 573:ad23fe03a082 437 When disabled, the MAC can send up to 16384 bytes.
mbed_official 573:ad23fe03a082 438 This parameter can be a value of @ref ETH_Jabber */
mbed_official 573:ad23fe03a082 439
mbed_official 573:ad23fe03a082 440 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
mbed_official 573:ad23fe03a082 441 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
mbed_official 573:ad23fe03a082 442
mbed_official 573:ad23fe03a082 443 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
mbed_official 573:ad23fe03a082 444 This parameter can be a value of @ref ETH_Carrier_Sense */
mbed_official 573:ad23fe03a082 445
mbed_official 573:ad23fe03a082 446 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
mbed_official 573:ad23fe03a082 447 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
mbed_official 573:ad23fe03a082 448 in Half-Duplex mode.
mbed_official 573:ad23fe03a082 449 This parameter can be a value of @ref ETH_Receive_Own */
mbed_official 573:ad23fe03a082 450
mbed_official 573:ad23fe03a082 451 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
mbed_official 573:ad23fe03a082 452 This parameter can be a value of @ref ETH_Loop_Back_Mode */
mbed_official 573:ad23fe03a082 453
mbed_official 573:ad23fe03a082 454 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
mbed_official 573:ad23fe03a082 455 This parameter can be a value of @ref ETH_Checksum_Offload */
mbed_official 573:ad23fe03a082 456
mbed_official 573:ad23fe03a082 457 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
mbed_official 573:ad23fe03a082 458 when a collision occurs (Half-Duplex mode).
mbed_official 573:ad23fe03a082 459 This parameter can be a value of @ref ETH_Retry_Transmission */
mbed_official 573:ad23fe03a082 460
mbed_official 573:ad23fe03a082 461 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
mbed_official 573:ad23fe03a082 462 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
mbed_official 573:ad23fe03a082 463
mbed_official 573:ad23fe03a082 464 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
mbed_official 573:ad23fe03a082 465 This parameter can be a value of @ref ETH_Back_Off_Limit */
mbed_official 573:ad23fe03a082 466
mbed_official 573:ad23fe03a082 467 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
mbed_official 573:ad23fe03a082 468 This parameter can be a value of @ref ETH_Deferral_Check */
mbed_official 573:ad23fe03a082 469
mbed_official 573:ad23fe03a082 470 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
mbed_official 573:ad23fe03a082 471 This parameter can be a value of @ref ETH_Receive_All */
mbed_official 573:ad23fe03a082 472
mbed_official 573:ad23fe03a082 473 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
mbed_official 573:ad23fe03a082 474 This parameter can be a value of @ref ETH_Source_Addr_Filter */
mbed_official 573:ad23fe03a082 475
mbed_official 573:ad23fe03a082 476 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
mbed_official 573:ad23fe03a082 477 This parameter can be a value of @ref ETH_Pass_Control_Frames */
mbed_official 573:ad23fe03a082 478
mbed_official 573:ad23fe03a082 479 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
mbed_official 573:ad23fe03a082 480 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
mbed_official 573:ad23fe03a082 481
mbed_official 573:ad23fe03a082 482 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
mbed_official 573:ad23fe03a082 483 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
mbed_official 573:ad23fe03a082 484
mbed_official 573:ad23fe03a082 485 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
mbed_official 573:ad23fe03a082 486 This parameter can be a value of @ref ETH_Promiscuous_Mode */
mbed_official 573:ad23fe03a082 487
mbed_official 573:ad23fe03a082 488 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
mbed_official 573:ad23fe03a082 489 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
mbed_official 573:ad23fe03a082 490
mbed_official 573:ad23fe03a082 491 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
mbed_official 573:ad23fe03a082 492 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
mbed_official 573:ad23fe03a082 493
mbed_official 573:ad23fe03a082 494 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
mbed_official 573:ad23fe03a082 495 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
mbed_official 573:ad23fe03a082 496
mbed_official 573:ad23fe03a082 497 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
mbed_official 573:ad23fe03a082 498 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
mbed_official 573:ad23fe03a082 499
mbed_official 573:ad23fe03a082 500 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
mbed_official 573:ad23fe03a082 501 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
mbed_official 573:ad23fe03a082 502
mbed_official 573:ad23fe03a082 503 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
mbed_official 573:ad23fe03a082 504 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
mbed_official 573:ad23fe03a082 505
mbed_official 573:ad23fe03a082 506 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
mbed_official 573:ad23fe03a082 507 automatic retransmission of PAUSE Frame.
mbed_official 573:ad23fe03a082 508 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
mbed_official 573:ad23fe03a082 509
mbed_official 573:ad23fe03a082 510 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
mbed_official 573:ad23fe03a082 511 unicast address and unique multicast address).
mbed_official 573:ad23fe03a082 512 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
mbed_official 573:ad23fe03a082 513
mbed_official 573:ad23fe03a082 514 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
mbed_official 573:ad23fe03a082 515 disable its transmitter for a specified time (Pause Time)
mbed_official 573:ad23fe03a082 516 This parameter can be a value of @ref ETH_Receive_Flow_Control */
mbed_official 573:ad23fe03a082 517
mbed_official 573:ad23fe03a082 518 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
mbed_official 573:ad23fe03a082 519 or the MAC back-pressure operation (Half-Duplex mode)
mbed_official 573:ad23fe03a082 520 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
mbed_official 573:ad23fe03a082 521
mbed_official 573:ad23fe03a082 522 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
mbed_official 573:ad23fe03a082 523 comparison and filtering.
mbed_official 573:ad23fe03a082 524 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
mbed_official 573:ad23fe03a082 525
mbed_official 573:ad23fe03a082 526 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
mbed_official 573:ad23fe03a082 527
mbed_official 573:ad23fe03a082 528 } ETH_MACInitTypeDef;
mbed_official 573:ad23fe03a082 529
mbed_official 573:ad23fe03a082 530
mbed_official 573:ad23fe03a082 531 /**
mbed_official 573:ad23fe03a082 532 * @brief ETH DMA Configuration Structure definition
mbed_official 573:ad23fe03a082 533 */
mbed_official 573:ad23fe03a082 534
mbed_official 573:ad23fe03a082 535 typedef struct
mbed_official 573:ad23fe03a082 536 {
mbed_official 573:ad23fe03a082 537 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
mbed_official 573:ad23fe03a082 538 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
mbed_official 573:ad23fe03a082 539
mbed_official 573:ad23fe03a082 540 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
mbed_official 573:ad23fe03a082 541 This parameter can be a value of @ref ETH_Receive_Store_Forward */
mbed_official 573:ad23fe03a082 542
mbed_official 573:ad23fe03a082 543 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
mbed_official 573:ad23fe03a082 544 This parameter can be a value of @ref ETH_Flush_Received_Frame */
mbed_official 573:ad23fe03a082 545
mbed_official 573:ad23fe03a082 546 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
mbed_official 573:ad23fe03a082 547 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
mbed_official 573:ad23fe03a082 548
mbed_official 573:ad23fe03a082 549 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
mbed_official 573:ad23fe03a082 550 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
mbed_official 573:ad23fe03a082 551
mbed_official 573:ad23fe03a082 552 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
mbed_official 573:ad23fe03a082 553 This parameter can be a value of @ref ETH_Forward_Error_Frames */
mbed_official 573:ad23fe03a082 554
mbed_official 573:ad23fe03a082 555 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
mbed_official 573:ad23fe03a082 556 and length less than 64 bytes) including pad-bytes and CRC)
mbed_official 573:ad23fe03a082 557 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
mbed_official 573:ad23fe03a082 558
mbed_official 573:ad23fe03a082 559 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
mbed_official 573:ad23fe03a082 560 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
mbed_official 573:ad23fe03a082 561
mbed_official 573:ad23fe03a082 562 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
mbed_official 573:ad23fe03a082 563 frame of Transmit data even before obtaining the status for the first frame.
mbed_official 573:ad23fe03a082 564 This parameter can be a value of @ref ETH_Second_Frame_Operate */
mbed_official 573:ad23fe03a082 565
mbed_official 573:ad23fe03a082 566 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
mbed_official 573:ad23fe03a082 567 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
mbed_official 573:ad23fe03a082 568
mbed_official 573:ad23fe03a082 569 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
mbed_official 573:ad23fe03a082 570 This parameter can be a value of @ref ETH_Fixed_Burst */
mbed_official 573:ad23fe03a082 571
mbed_official 573:ad23fe03a082 572 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
mbed_official 573:ad23fe03a082 573 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
mbed_official 573:ad23fe03a082 574
mbed_official 573:ad23fe03a082 575 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
mbed_official 573:ad23fe03a082 576 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
mbed_official 573:ad23fe03a082 577
mbed_official 573:ad23fe03a082 578 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
mbed_official 573:ad23fe03a082 579 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
mbed_official 573:ad23fe03a082 580
mbed_official 573:ad23fe03a082 581 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
mbed_official 573:ad23fe03a082 582 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
mbed_official 573:ad23fe03a082 583
mbed_official 573:ad23fe03a082 584 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
mbed_official 573:ad23fe03a082 585 This parameter can be a value of @ref ETH_DMA_Arbitration */
mbed_official 573:ad23fe03a082 586 } ETH_DMAInitTypeDef;
mbed_official 573:ad23fe03a082 587
mbed_official 573:ad23fe03a082 588
mbed_official 573:ad23fe03a082 589 /**
mbed_official 573:ad23fe03a082 590 * @brief ETH DMA Descriptors data structure definition
mbed_official 573:ad23fe03a082 591 */
mbed_official 573:ad23fe03a082 592
mbed_official 573:ad23fe03a082 593 typedef struct
mbed_official 573:ad23fe03a082 594 {
mbed_official 573:ad23fe03a082 595 __IO uint32_t Status; /*!< Status */
mbed_official 573:ad23fe03a082 596
mbed_official 573:ad23fe03a082 597 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
mbed_official 573:ad23fe03a082 598
mbed_official 573:ad23fe03a082 599 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
mbed_official 573:ad23fe03a082 600
mbed_official 573:ad23fe03a082 601 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
mbed_official 573:ad23fe03a082 602
mbed_official 573:ad23fe03a082 603 /*!< Enhanced ETHERNET DMA PTP Descriptors */
mbed_official 573:ad23fe03a082 604 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
mbed_official 573:ad23fe03a082 605
mbed_official 573:ad23fe03a082 606 uint32_t Reserved1; /*!< Reserved */
mbed_official 573:ad23fe03a082 607
mbed_official 573:ad23fe03a082 608 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
mbed_official 573:ad23fe03a082 609
mbed_official 573:ad23fe03a082 610 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
mbed_official 573:ad23fe03a082 611
mbed_official 573:ad23fe03a082 612 } ETH_DMADescTypeDef;
mbed_official 573:ad23fe03a082 613
mbed_official 573:ad23fe03a082 614
mbed_official 573:ad23fe03a082 615 /**
mbed_official 573:ad23fe03a082 616 * @brief Received Frame Informations structure definition
mbed_official 573:ad23fe03a082 617 */
mbed_official 573:ad23fe03a082 618 typedef struct
mbed_official 573:ad23fe03a082 619 {
mbed_official 573:ad23fe03a082 620 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
mbed_official 573:ad23fe03a082 621
mbed_official 573:ad23fe03a082 622 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
mbed_official 573:ad23fe03a082 623
mbed_official 573:ad23fe03a082 624 uint32_t SegCount; /*!< Segment count */
mbed_official 573:ad23fe03a082 625
mbed_official 573:ad23fe03a082 626 uint32_t length; /*!< Frame length */
mbed_official 573:ad23fe03a082 627
mbed_official 573:ad23fe03a082 628 uint32_t buffer; /*!< Frame buffer */
mbed_official 573:ad23fe03a082 629
mbed_official 573:ad23fe03a082 630 } ETH_DMARxFrameInfos;
mbed_official 573:ad23fe03a082 631
mbed_official 573:ad23fe03a082 632
mbed_official 573:ad23fe03a082 633 /**
mbed_official 573:ad23fe03a082 634 * @brief ETH Handle Structure definition
mbed_official 573:ad23fe03a082 635 */
mbed_official 573:ad23fe03a082 636
mbed_official 573:ad23fe03a082 637 typedef struct
mbed_official 573:ad23fe03a082 638 {
mbed_official 573:ad23fe03a082 639 ETH_TypeDef *Instance; /*!< Register base address */
mbed_official 573:ad23fe03a082 640
mbed_official 573:ad23fe03a082 641 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
mbed_official 573:ad23fe03a082 642
mbed_official 573:ad23fe03a082 643 uint32_t LinkStatus; /*!< Ethernet link status */
mbed_official 573:ad23fe03a082 644
mbed_official 573:ad23fe03a082 645 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
mbed_official 573:ad23fe03a082 646
mbed_official 573:ad23fe03a082 647 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
mbed_official 573:ad23fe03a082 648
mbed_official 573:ad23fe03a082 649 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
mbed_official 573:ad23fe03a082 650
mbed_official 573:ad23fe03a082 651 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
mbed_official 573:ad23fe03a082 652
mbed_official 573:ad23fe03a082 653 HAL_LockTypeDef Lock; /*!< ETH Lock */
mbed_official 573:ad23fe03a082 654
mbed_official 573:ad23fe03a082 655 } ETH_HandleTypeDef;
mbed_official 573:ad23fe03a082 656
mbed_official 573:ad23fe03a082 657 /**
mbed_official 573:ad23fe03a082 658 * @}
mbed_official 573:ad23fe03a082 659 */
mbed_official 573:ad23fe03a082 660
mbed_official 573:ad23fe03a082 661 /* Exported constants --------------------------------------------------------*/
mbed_official 573:ad23fe03a082 662 /** @defgroup ETH_Exported_Constants ETH Exported Constants
mbed_official 573:ad23fe03a082 663 * @{
mbed_official 573:ad23fe03a082 664 */
mbed_official 573:ad23fe03a082 665
mbed_official 573:ad23fe03a082 666 /** @defgroup ETH_Buffers_setting ETH Buffers setting
mbed_official 573:ad23fe03a082 667 * @{
mbed_official 573:ad23fe03a082 668 */
mbed_official 573:ad23fe03a082 669 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
mbed_official 573:ad23fe03a082 670 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
mbed_official 573:ad23fe03a082 671 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
mbed_official 573:ad23fe03a082 672 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
mbed_official 573:ad23fe03a082 673 #define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
mbed_official 573:ad23fe03a082 674 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
mbed_official 573:ad23fe03a082 675 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
mbed_official 573:ad23fe03a082 676 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
mbed_official 573:ad23fe03a082 677
mbed_official 573:ad23fe03a082 678 /* Ethernet driver receive buffers are organized in a chained linked-list, when
mbed_official 573:ad23fe03a082 679 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
mbed_official 573:ad23fe03a082 680 to the driver receive buffers memory.
mbed_official 573:ad23fe03a082 681
mbed_official 573:ad23fe03a082 682 Depending on the size of the received ethernet packet and the size of
mbed_official 573:ad23fe03a082 683 each ethernet driver receive buffer, the received packet can take one or more
mbed_official 573:ad23fe03a082 684 ethernet driver receive buffer.
mbed_official 573:ad23fe03a082 685
mbed_official 573:ad23fe03a082 686 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
mbed_official 573:ad23fe03a082 687 and the total count of the driver receive buffers ETH_RXBUFNB.
mbed_official 573:ad23fe03a082 688
mbed_official 573:ad23fe03a082 689 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
mbed_official 573:ad23fe03a082 690 example, they can be reconfigured in the application layer to fit the application
mbed_official 573:ad23fe03a082 691 needs */
mbed_official 573:ad23fe03a082 692
mbed_official 573:ad23fe03a082 693 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
mbed_official 573:ad23fe03a082 694 packet */
mbed_official 573:ad23fe03a082 695 #ifndef ETH_RX_BUF_SIZE
mbed_official 573:ad23fe03a082 696 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
mbed_official 573:ad23fe03a082 697 #endif
mbed_official 573:ad23fe03a082 698
mbed_official 573:ad23fe03a082 699 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
mbed_official 573:ad23fe03a082 700 #ifndef ETH_RXBUFNB
mbed_official 573:ad23fe03a082 701 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
mbed_official 573:ad23fe03a082 702 #endif
mbed_official 573:ad23fe03a082 703
mbed_official 573:ad23fe03a082 704
mbed_official 573:ad23fe03a082 705 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
mbed_official 573:ad23fe03a082 706 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
mbed_official 573:ad23fe03a082 707 driver transmit buffers memory to the TxFIFO.
mbed_official 573:ad23fe03a082 708
mbed_official 573:ad23fe03a082 709 Depending on the size of the Ethernet packet to be transmitted and the size of
mbed_official 573:ad23fe03a082 710 each ethernet driver transmit buffer, the packet to be transmitted can take
mbed_official 573:ad23fe03a082 711 one or more ethernet driver transmit buffer.
mbed_official 573:ad23fe03a082 712
mbed_official 573:ad23fe03a082 713 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
mbed_official 573:ad23fe03a082 714 and the total count of the driver transmit buffers ETH_TXBUFNB.
mbed_official 573:ad23fe03a082 715
mbed_official 573:ad23fe03a082 716 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
mbed_official 573:ad23fe03a082 717 example, they can be reconfigured in the application layer to fit the application
mbed_official 573:ad23fe03a082 718 needs */
mbed_official 573:ad23fe03a082 719
mbed_official 573:ad23fe03a082 720 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
mbed_official 573:ad23fe03a082 721 packet */
mbed_official 573:ad23fe03a082 722 #ifndef ETH_TX_BUF_SIZE
mbed_official 573:ad23fe03a082 723 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
mbed_official 573:ad23fe03a082 724 #endif
mbed_official 573:ad23fe03a082 725
mbed_official 573:ad23fe03a082 726 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
mbed_official 573:ad23fe03a082 727 #ifndef ETH_TXBUFNB
mbed_official 573:ad23fe03a082 728 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
mbed_official 573:ad23fe03a082 729 #endif
mbed_official 573:ad23fe03a082 730
mbed_official 573:ad23fe03a082 731 /**
mbed_official 573:ad23fe03a082 732 * @}
mbed_official 573:ad23fe03a082 733 */
mbed_official 573:ad23fe03a082 734
mbed_official 573:ad23fe03a082 735 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
mbed_official 573:ad23fe03a082 736 * @{
mbed_official 573:ad23fe03a082 737 */
mbed_official 573:ad23fe03a082 738
mbed_official 573:ad23fe03a082 739 /*
mbed_official 573:ad23fe03a082 740 DMA Tx Descriptor
mbed_official 573:ad23fe03a082 741 -----------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 742 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
mbed_official 573:ad23fe03a082 743 -----------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 744 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
mbed_official 573:ad23fe03a082 745 -----------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 746 TDES2 | Buffer1 Address [31:0] |
mbed_official 573:ad23fe03a082 747 -----------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 748 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
mbed_official 573:ad23fe03a082 749 -----------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 750 */
mbed_official 573:ad23fe03a082 751
mbed_official 573:ad23fe03a082 752 /**
mbed_official 573:ad23fe03a082 753 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
mbed_official 573:ad23fe03a082 754 */
mbed_official 573:ad23fe03a082 755 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
mbed_official 573:ad23fe03a082 756 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
mbed_official 573:ad23fe03a082 757 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
mbed_official 573:ad23fe03a082 758 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
mbed_official 573:ad23fe03a082 759 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
mbed_official 573:ad23fe03a082 760 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
mbed_official 573:ad23fe03a082 761 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
mbed_official 573:ad23fe03a082 762 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
mbed_official 573:ad23fe03a082 763 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
mbed_official 573:ad23fe03a082 764 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
mbed_official 573:ad23fe03a082 765 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
mbed_official 573:ad23fe03a082 766 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
mbed_official 573:ad23fe03a082 767 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
mbed_official 573:ad23fe03a082 768 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
mbed_official 573:ad23fe03a082 769 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
mbed_official 573:ad23fe03a082 770 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
mbed_official 573:ad23fe03a082 771 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
mbed_official 573:ad23fe03a082 772 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
mbed_official 573:ad23fe03a082 773 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
mbed_official 573:ad23fe03a082 774 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
mbed_official 573:ad23fe03a082 775 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
mbed_official 573:ad23fe03a082 776 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
mbed_official 573:ad23fe03a082 777 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
mbed_official 573:ad23fe03a082 778 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
mbed_official 573:ad23fe03a082 779 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
mbed_official 573:ad23fe03a082 780 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
mbed_official 573:ad23fe03a082 781 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
mbed_official 573:ad23fe03a082 782 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
mbed_official 573:ad23fe03a082 783 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
mbed_official 573:ad23fe03a082 784
mbed_official 573:ad23fe03a082 785 /**
mbed_official 573:ad23fe03a082 786 * @brief Bit definition of TDES1 register
mbed_official 573:ad23fe03a082 787 */
mbed_official 573:ad23fe03a082 788 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
mbed_official 573:ad23fe03a082 789 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
mbed_official 573:ad23fe03a082 790
mbed_official 573:ad23fe03a082 791 /**
mbed_official 573:ad23fe03a082 792 * @brief Bit definition of TDES2 register
mbed_official 573:ad23fe03a082 793 */
mbed_official 573:ad23fe03a082 794 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
mbed_official 573:ad23fe03a082 795
mbed_official 573:ad23fe03a082 796 /**
mbed_official 573:ad23fe03a082 797 * @brief Bit definition of TDES3 register
mbed_official 573:ad23fe03a082 798 */
mbed_official 573:ad23fe03a082 799 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
mbed_official 573:ad23fe03a082 800
mbed_official 573:ad23fe03a082 801 /*---------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 802 TDES6 | Transmit Time Stamp Low [31:0] |
mbed_official 573:ad23fe03a082 803 -----------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 804 TDES7 | Transmit Time Stamp High [31:0] |
mbed_official 573:ad23fe03a082 805 ----------------------------------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 806
mbed_official 573:ad23fe03a082 807 /* Bit definition of TDES6 register */
mbed_official 573:ad23fe03a082 808 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
mbed_official 573:ad23fe03a082 809
mbed_official 573:ad23fe03a082 810 /* Bit definition of TDES7 register */
mbed_official 573:ad23fe03a082 811 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
mbed_official 573:ad23fe03a082 812
mbed_official 573:ad23fe03a082 813 /**
mbed_official 573:ad23fe03a082 814 * @}
mbed_official 573:ad23fe03a082 815 */
mbed_official 573:ad23fe03a082 816 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
mbed_official 573:ad23fe03a082 817 * @{
mbed_official 573:ad23fe03a082 818 */
mbed_official 573:ad23fe03a082 819
mbed_official 573:ad23fe03a082 820 /*
mbed_official 573:ad23fe03a082 821 DMA Rx Descriptor
mbed_official 573:ad23fe03a082 822 --------------------------------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 823 RDES0 | OWN(31) | Status [30:0] |
mbed_official 573:ad23fe03a082 824 ---------------------------------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 825 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
mbed_official 573:ad23fe03a082 826 ---------------------------------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 827 RDES2 | Buffer1 Address [31:0] |
mbed_official 573:ad23fe03a082 828 ---------------------------------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 829 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
mbed_official 573:ad23fe03a082 830 ---------------------------------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 831 */
mbed_official 573:ad23fe03a082 832
mbed_official 573:ad23fe03a082 833 /**
mbed_official 573:ad23fe03a082 834 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
mbed_official 573:ad23fe03a082 835 */
mbed_official 573:ad23fe03a082 836 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
mbed_official 573:ad23fe03a082 837 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
mbed_official 573:ad23fe03a082 838 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
mbed_official 573:ad23fe03a082 839 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
mbed_official 573:ad23fe03a082 840 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
mbed_official 573:ad23fe03a082 841 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
mbed_official 573:ad23fe03a082 842 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
mbed_official 573:ad23fe03a082 843 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
mbed_official 573:ad23fe03a082 844 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
mbed_official 573:ad23fe03a082 845 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
mbed_official 573:ad23fe03a082 846 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
mbed_official 573:ad23fe03a082 847 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
mbed_official 573:ad23fe03a082 848 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
mbed_official 573:ad23fe03a082 849 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
mbed_official 573:ad23fe03a082 850 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
mbed_official 573:ad23fe03a082 851 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
mbed_official 573:ad23fe03a082 852 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
mbed_official 573:ad23fe03a082 853 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
mbed_official 573:ad23fe03a082 854 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
mbed_official 573:ad23fe03a082 855
mbed_official 573:ad23fe03a082 856 /**
mbed_official 573:ad23fe03a082 857 * @brief Bit definition of RDES1 register
mbed_official 573:ad23fe03a082 858 */
mbed_official 573:ad23fe03a082 859 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
mbed_official 573:ad23fe03a082 860 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
mbed_official 573:ad23fe03a082 861 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
mbed_official 573:ad23fe03a082 862 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
mbed_official 573:ad23fe03a082 863 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
mbed_official 573:ad23fe03a082 864
mbed_official 573:ad23fe03a082 865 /**
mbed_official 573:ad23fe03a082 866 * @brief Bit definition of RDES2 register
mbed_official 573:ad23fe03a082 867 */
mbed_official 573:ad23fe03a082 868 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
mbed_official 573:ad23fe03a082 869
mbed_official 573:ad23fe03a082 870 /**
mbed_official 573:ad23fe03a082 871 * @brief Bit definition of RDES3 register
mbed_official 573:ad23fe03a082 872 */
mbed_official 573:ad23fe03a082 873 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
mbed_official 573:ad23fe03a082 874
mbed_official 573:ad23fe03a082 875 /*---------------------------------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 876 RDES4 | Reserved[31:15] | Extended Status [14:0] |
mbed_official 573:ad23fe03a082 877 ---------------------------------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 878 RDES5 | Reserved[31:0] |
mbed_official 573:ad23fe03a082 879 ---------------------------------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 880 RDES6 | Receive Time Stamp Low [31:0] |
mbed_official 573:ad23fe03a082 881 ---------------------------------------------------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 882 RDES7 | Receive Time Stamp High [31:0] |
mbed_official 573:ad23fe03a082 883 --------------------------------------------------------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 884
mbed_official 573:ad23fe03a082 885 /* Bit definition of RDES4 register */
mbed_official 573:ad23fe03a082 886 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
mbed_official 573:ad23fe03a082 887 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
mbed_official 573:ad23fe03a082 888 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
mbed_official 573:ad23fe03a082 889 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
mbed_official 573:ad23fe03a082 890 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
mbed_official 573:ad23fe03a082 891 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
mbed_official 573:ad23fe03a082 892 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
mbed_official 573:ad23fe03a082 893 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
mbed_official 573:ad23fe03a082 894 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
mbed_official 573:ad23fe03a082 895 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
mbed_official 573:ad23fe03a082 896 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
mbed_official 573:ad23fe03a082 897 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
mbed_official 573:ad23fe03a082 898 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
mbed_official 573:ad23fe03a082 899 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
mbed_official 573:ad23fe03a082 900 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
mbed_official 573:ad23fe03a082 901 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
mbed_official 573:ad23fe03a082 902 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
mbed_official 573:ad23fe03a082 903 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
mbed_official 573:ad23fe03a082 904 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
mbed_official 573:ad23fe03a082 905
mbed_official 573:ad23fe03a082 906 /* Bit definition of RDES6 register */
mbed_official 573:ad23fe03a082 907 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
mbed_official 573:ad23fe03a082 908
mbed_official 573:ad23fe03a082 909 /* Bit definition of RDES7 register */
mbed_official 573:ad23fe03a082 910 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
mbed_official 573:ad23fe03a082 911 /**
mbed_official 573:ad23fe03a082 912 * @}
mbed_official 573:ad23fe03a082 913 */
mbed_official 573:ad23fe03a082 914 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
mbed_official 573:ad23fe03a082 915 * @{
mbed_official 573:ad23fe03a082 916 */
mbed_official 573:ad23fe03a082 917 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 918 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 919
mbed_official 573:ad23fe03a082 920 /**
mbed_official 573:ad23fe03a082 921 * @}
mbed_official 573:ad23fe03a082 922 */
mbed_official 573:ad23fe03a082 923 /** @defgroup ETH_Speed ETH Speed
mbed_official 573:ad23fe03a082 924 * @{
mbed_official 573:ad23fe03a082 925 */
mbed_official 573:ad23fe03a082 926 #define ETH_SPEED_10M ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 927 #define ETH_SPEED_100M ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 928
mbed_official 573:ad23fe03a082 929 /**
mbed_official 573:ad23fe03a082 930 * @}
mbed_official 573:ad23fe03a082 931 */
mbed_official 573:ad23fe03a082 932 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
mbed_official 573:ad23fe03a082 933 * @{
mbed_official 573:ad23fe03a082 934 */
mbed_official 573:ad23fe03a082 935 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
mbed_official 573:ad23fe03a082 936 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 937 /**
mbed_official 573:ad23fe03a082 938 * @}
mbed_official 573:ad23fe03a082 939 */
mbed_official 573:ad23fe03a082 940 /** @defgroup ETH_Rx_Mode ETH Rx Mode
mbed_official 573:ad23fe03a082 941 * @{
mbed_official 573:ad23fe03a082 942 */
mbed_official 573:ad23fe03a082 943 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 944 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 945 /**
mbed_official 573:ad23fe03a082 946 * @}
mbed_official 573:ad23fe03a082 947 */
mbed_official 573:ad23fe03a082 948
mbed_official 573:ad23fe03a082 949 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
mbed_official 573:ad23fe03a082 950 * @{
mbed_official 573:ad23fe03a082 951 */
mbed_official 573:ad23fe03a082 952 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 953 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 954 /**
mbed_official 573:ad23fe03a082 955 * @}
mbed_official 573:ad23fe03a082 956 */
mbed_official 573:ad23fe03a082 957
mbed_official 573:ad23fe03a082 958 /** @defgroup ETH_Media_Interface ETH Media Interface
mbed_official 573:ad23fe03a082 959 * @{
mbed_official 573:ad23fe03a082 960 */
mbed_official 573:ad23fe03a082 961 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 962 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
mbed_official 573:ad23fe03a082 963 /**
mbed_official 573:ad23fe03a082 964 * @}
mbed_official 573:ad23fe03a082 965 */
mbed_official 573:ad23fe03a082 966
mbed_official 573:ad23fe03a082 967 /** @defgroup ETH_Watchdog ETH Watchdog
mbed_official 573:ad23fe03a082 968 * @{
mbed_official 573:ad23fe03a082 969 */
mbed_official 573:ad23fe03a082 970 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 971 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
mbed_official 573:ad23fe03a082 972 /**
mbed_official 573:ad23fe03a082 973 * @}
mbed_official 573:ad23fe03a082 974 */
mbed_official 573:ad23fe03a082 975
mbed_official 573:ad23fe03a082 976 /** @defgroup ETH_Jabber ETH Jabber
mbed_official 573:ad23fe03a082 977 * @{
mbed_official 573:ad23fe03a082 978 */
mbed_official 573:ad23fe03a082 979 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 980 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
mbed_official 573:ad23fe03a082 981 /**
mbed_official 573:ad23fe03a082 982 * @}
mbed_official 573:ad23fe03a082 983 */
mbed_official 573:ad23fe03a082 984
mbed_official 573:ad23fe03a082 985 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
mbed_official 573:ad23fe03a082 986 * @{
mbed_official 573:ad23fe03a082 987 */
mbed_official 573:ad23fe03a082 988 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
mbed_official 573:ad23fe03a082 989 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
mbed_official 573:ad23fe03a082 990 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
mbed_official 573:ad23fe03a082 991 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
mbed_official 573:ad23fe03a082 992 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
mbed_official 573:ad23fe03a082 993 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
mbed_official 573:ad23fe03a082 994 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
mbed_official 573:ad23fe03a082 995 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
mbed_official 573:ad23fe03a082 996 /**
mbed_official 573:ad23fe03a082 997 * @}
mbed_official 573:ad23fe03a082 998 */
mbed_official 573:ad23fe03a082 999
mbed_official 573:ad23fe03a082 1000 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
mbed_official 573:ad23fe03a082 1001 * @{
mbed_official 573:ad23fe03a082 1002 */
mbed_official 573:ad23fe03a082 1003 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1004 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 1005 /**
mbed_official 573:ad23fe03a082 1006 * @}
mbed_official 573:ad23fe03a082 1007 */
mbed_official 573:ad23fe03a082 1008
mbed_official 573:ad23fe03a082 1009 /** @defgroup ETH_Receive_Own ETH Receive Own
mbed_official 573:ad23fe03a082 1010 * @{
mbed_official 573:ad23fe03a082 1011 */
mbed_official 573:ad23fe03a082 1012 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1013 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
mbed_official 573:ad23fe03a082 1014 /**
mbed_official 573:ad23fe03a082 1015 * @}
mbed_official 573:ad23fe03a082 1016 */
mbed_official 573:ad23fe03a082 1017
mbed_official 573:ad23fe03a082 1018 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
mbed_official 573:ad23fe03a082 1019 * @{
mbed_official 573:ad23fe03a082 1020 */
mbed_official 573:ad23fe03a082 1021 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
mbed_official 573:ad23fe03a082 1022 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1023 /**
mbed_official 573:ad23fe03a082 1024 * @}
mbed_official 573:ad23fe03a082 1025 */
mbed_official 573:ad23fe03a082 1026
mbed_official 573:ad23fe03a082 1027 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
mbed_official 573:ad23fe03a082 1028 * @{
mbed_official 573:ad23fe03a082 1029 */
mbed_official 573:ad23fe03a082 1030 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
mbed_official 573:ad23fe03a082 1031 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1032 /**
mbed_official 573:ad23fe03a082 1033 * @}
mbed_official 573:ad23fe03a082 1034 */
mbed_official 573:ad23fe03a082 1035
mbed_official 573:ad23fe03a082 1036 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
mbed_official 573:ad23fe03a082 1037 * @{
mbed_official 573:ad23fe03a082 1038 */
mbed_official 573:ad23fe03a082 1039 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1040 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 1041 /**
mbed_official 573:ad23fe03a082 1042 * @}
mbed_official 573:ad23fe03a082 1043 */
mbed_official 573:ad23fe03a082 1044
mbed_official 573:ad23fe03a082 1045 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
mbed_official 573:ad23fe03a082 1046 * @{
mbed_official 573:ad23fe03a082 1047 */
mbed_official 573:ad23fe03a082 1048 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 1049 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1050 /**
mbed_official 573:ad23fe03a082 1051 * @}
mbed_official 573:ad23fe03a082 1052 */
mbed_official 573:ad23fe03a082 1053
mbed_official 573:ad23fe03a082 1054 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
mbed_official 573:ad23fe03a082 1055 * @{
mbed_official 573:ad23fe03a082 1056 */
mbed_official 573:ad23fe03a082 1057 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1058 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 1059 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 1060 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
mbed_official 573:ad23fe03a082 1061 /**
mbed_official 573:ad23fe03a082 1062 * @}
mbed_official 573:ad23fe03a082 1063 */
mbed_official 573:ad23fe03a082 1064
mbed_official 573:ad23fe03a082 1065 /** @defgroup ETH_Deferral_Check ETH Deferral Check
mbed_official 573:ad23fe03a082 1066 * @{
mbed_official 573:ad23fe03a082 1067 */
mbed_official 573:ad23fe03a082 1068 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 1069 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1070 /**
mbed_official 573:ad23fe03a082 1071 * @}
mbed_official 573:ad23fe03a082 1072 */
mbed_official 573:ad23fe03a082 1073
mbed_official 573:ad23fe03a082 1074 /** @defgroup ETH_Receive_All ETH Receive All
mbed_official 573:ad23fe03a082 1075 * @{
mbed_official 573:ad23fe03a082 1076 */
mbed_official 573:ad23fe03a082 1077 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
mbed_official 573:ad23fe03a082 1078 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1079 /**
mbed_official 573:ad23fe03a082 1080 * @}
mbed_official 573:ad23fe03a082 1081 */
mbed_official 573:ad23fe03a082 1082
mbed_official 573:ad23fe03a082 1083 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
mbed_official 573:ad23fe03a082 1084 * @{
mbed_official 573:ad23fe03a082 1085 */
mbed_official 573:ad23fe03a082 1086 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
mbed_official 573:ad23fe03a082 1087 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
mbed_official 573:ad23fe03a082 1088 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1089 /**
mbed_official 573:ad23fe03a082 1090 * @}
mbed_official 573:ad23fe03a082 1091 */
mbed_official 573:ad23fe03a082 1092
mbed_official 573:ad23fe03a082 1093 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
mbed_official 573:ad23fe03a082 1094 * @{
mbed_official 573:ad23fe03a082 1095 */
mbed_official 573:ad23fe03a082 1096 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
mbed_official 573:ad23fe03a082 1097 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
mbed_official 573:ad23fe03a082 1098 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
mbed_official 573:ad23fe03a082 1099 /**
mbed_official 573:ad23fe03a082 1100 * @}
mbed_official 573:ad23fe03a082 1101 */
mbed_official 573:ad23fe03a082 1102
mbed_official 573:ad23fe03a082 1103 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
mbed_official 573:ad23fe03a082 1104 * @{
mbed_official 573:ad23fe03a082 1105 */
mbed_official 573:ad23fe03a082 1106 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1107 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
mbed_official 573:ad23fe03a082 1108 /**
mbed_official 573:ad23fe03a082 1109 * @}
mbed_official 573:ad23fe03a082 1110 */
mbed_official 573:ad23fe03a082 1111
mbed_official 573:ad23fe03a082 1112 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
mbed_official 573:ad23fe03a082 1113 * @{
mbed_official 573:ad23fe03a082 1114 */
mbed_official 573:ad23fe03a082 1115 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1116 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 1117 /**
mbed_official 573:ad23fe03a082 1118 * @}
mbed_official 573:ad23fe03a082 1119 */
mbed_official 573:ad23fe03a082 1120
mbed_official 573:ad23fe03a082 1121 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
mbed_official 573:ad23fe03a082 1122 * @{
mbed_official 573:ad23fe03a082 1123 */
mbed_official 573:ad23fe03a082 1124 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
mbed_official 573:ad23fe03a082 1125 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1126 /**
mbed_official 573:ad23fe03a082 1127 * @}
mbed_official 573:ad23fe03a082 1128 */
mbed_official 573:ad23fe03a082 1129
mbed_official 573:ad23fe03a082 1130 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
mbed_official 573:ad23fe03a082 1131 * @{
mbed_official 573:ad23fe03a082 1132 */
mbed_official 573:ad23fe03a082 1133 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
mbed_official 573:ad23fe03a082 1134 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 1135 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1136 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 1137 /**
mbed_official 573:ad23fe03a082 1138 * @}
mbed_official 573:ad23fe03a082 1139 */
mbed_official 573:ad23fe03a082 1140
mbed_official 573:ad23fe03a082 1141 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
mbed_official 573:ad23fe03a082 1142 * @{
mbed_official 573:ad23fe03a082 1143 */
mbed_official 573:ad23fe03a082 1144 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
mbed_official 573:ad23fe03a082 1145 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 1146 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1147 /**
mbed_official 573:ad23fe03a082 1148 * @}
mbed_official 573:ad23fe03a082 1149 */
mbed_official 573:ad23fe03a082 1150
mbed_official 573:ad23fe03a082 1151 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
mbed_official 573:ad23fe03a082 1152 * @{
mbed_official 573:ad23fe03a082 1153 */
mbed_official 573:ad23fe03a082 1154 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1155 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 1156 /**
mbed_official 573:ad23fe03a082 1157 * @}
mbed_official 573:ad23fe03a082 1158 */
mbed_official 573:ad23fe03a082 1159
mbed_official 573:ad23fe03a082 1160 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
mbed_official 573:ad23fe03a082 1161 * @{
mbed_official 573:ad23fe03a082 1162 */
mbed_official 573:ad23fe03a082 1163 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
mbed_official 573:ad23fe03a082 1164 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
mbed_official 573:ad23fe03a082 1165 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
mbed_official 573:ad23fe03a082 1166 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
mbed_official 573:ad23fe03a082 1167 /**
mbed_official 573:ad23fe03a082 1168 * @}
mbed_official 573:ad23fe03a082 1169 */
mbed_official 573:ad23fe03a082 1170
mbed_official 573:ad23fe03a082 1171 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
mbed_official 573:ad23fe03a082 1172 * @{
mbed_official 573:ad23fe03a082 1173 */
mbed_official 573:ad23fe03a082 1174 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 1175 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1176 /**
mbed_official 573:ad23fe03a082 1177 * @}
mbed_official 573:ad23fe03a082 1178 */
mbed_official 573:ad23fe03a082 1179
mbed_official 573:ad23fe03a082 1180 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
mbed_official 573:ad23fe03a082 1181 * @{
mbed_official 573:ad23fe03a082 1182 */
mbed_official 573:ad23fe03a082 1183 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 1184 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1185 /**
mbed_official 573:ad23fe03a082 1186 * @}
mbed_official 573:ad23fe03a082 1187 */
mbed_official 573:ad23fe03a082 1188
mbed_official 573:ad23fe03a082 1189 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
mbed_official 573:ad23fe03a082 1190 * @{
mbed_official 573:ad23fe03a082 1191 */
mbed_official 573:ad23fe03a082 1192 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 1193 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1194 /**
mbed_official 573:ad23fe03a082 1195 * @}
mbed_official 573:ad23fe03a082 1196 */
mbed_official 573:ad23fe03a082 1197
mbed_official 573:ad23fe03a082 1198 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
mbed_official 573:ad23fe03a082 1199 * @{
mbed_official 573:ad23fe03a082 1200 */
mbed_official 573:ad23fe03a082 1201 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 1202 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1203 /**
mbed_official 573:ad23fe03a082 1204 * @}
mbed_official 573:ad23fe03a082 1205 */
mbed_official 573:ad23fe03a082 1206
mbed_official 573:ad23fe03a082 1207 /** @defgroup ETH_MAC_addresses ETH MAC addresses
mbed_official 573:ad23fe03a082 1208 * @{
mbed_official 573:ad23fe03a082 1209 */
mbed_official 573:ad23fe03a082 1210 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1211 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 1212 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
mbed_official 573:ad23fe03a082 1213 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
mbed_official 573:ad23fe03a082 1214 /**
mbed_official 573:ad23fe03a082 1215 * @}
mbed_official 573:ad23fe03a082 1216 */
mbed_official 573:ad23fe03a082 1217
mbed_official 573:ad23fe03a082 1218 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
mbed_official 573:ad23fe03a082 1219 * @{
mbed_official 573:ad23fe03a082 1220 */
mbed_official 573:ad23fe03a082 1221 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1222 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
mbed_official 573:ad23fe03a082 1223 /**
mbed_official 573:ad23fe03a082 1224 * @}
mbed_official 573:ad23fe03a082 1225 */
mbed_official 573:ad23fe03a082 1226
mbed_official 573:ad23fe03a082 1227 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
mbed_official 573:ad23fe03a082 1228 * @{
mbed_official 573:ad23fe03a082 1229 */
mbed_official 573:ad23fe03a082 1230 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
mbed_official 573:ad23fe03a082 1231 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
mbed_official 573:ad23fe03a082 1232 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
mbed_official 573:ad23fe03a082 1233 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
mbed_official 573:ad23fe03a082 1234 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
mbed_official 573:ad23fe03a082 1235 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
mbed_official 573:ad23fe03a082 1236 /**
mbed_official 573:ad23fe03a082 1237 * @}
mbed_official 573:ad23fe03a082 1238 */
mbed_official 573:ad23fe03a082 1239
mbed_official 573:ad23fe03a082 1240 /** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
mbed_official 573:ad23fe03a082 1241 * @{
mbed_official 573:ad23fe03a082 1242 */
mbed_official 573:ad23fe03a082 1243 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
mbed_official 573:ad23fe03a082 1244 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
mbed_official 573:ad23fe03a082 1245 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
mbed_official 573:ad23fe03a082 1246 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
mbed_official 573:ad23fe03a082 1247 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
mbed_official 573:ad23fe03a082 1248 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
mbed_official 573:ad23fe03a082 1249 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
mbed_official 573:ad23fe03a082 1250 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
mbed_official 573:ad23fe03a082 1251 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
mbed_official 573:ad23fe03a082 1252 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
mbed_official 573:ad23fe03a082 1253 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
mbed_official 573:ad23fe03a082 1254 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
mbed_official 573:ad23fe03a082 1255 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
mbed_official 573:ad23fe03a082 1256 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
mbed_official 573:ad23fe03a082 1257 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
mbed_official 573:ad23fe03a082 1258 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
mbed_official 573:ad23fe03a082 1259 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
mbed_official 573:ad23fe03a082 1260 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
mbed_official 573:ad23fe03a082 1261 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
mbed_official 573:ad23fe03a082 1262 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
mbed_official 573:ad23fe03a082 1263 #define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
mbed_official 573:ad23fe03a082 1264 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
mbed_official 573:ad23fe03a082 1265 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
mbed_official 573:ad23fe03a082 1266 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
mbed_official 573:ad23fe03a082 1267 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
mbed_official 573:ad23fe03a082 1268 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
mbed_official 573:ad23fe03a082 1269 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
mbed_official 573:ad23fe03a082 1270 /**
mbed_official 573:ad23fe03a082 1271 * @}
mbed_official 573:ad23fe03a082 1272 */
mbed_official 573:ad23fe03a082 1273
mbed_official 573:ad23fe03a082 1274 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
mbed_official 573:ad23fe03a082 1275 * @{
mbed_official 573:ad23fe03a082 1276 */
mbed_official 573:ad23fe03a082 1277 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1278 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
mbed_official 573:ad23fe03a082 1279 /**
mbed_official 573:ad23fe03a082 1280 * @}
mbed_official 573:ad23fe03a082 1281 */
mbed_official 573:ad23fe03a082 1282
mbed_official 573:ad23fe03a082 1283 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
mbed_official 573:ad23fe03a082 1284 * @{
mbed_official 573:ad23fe03a082 1285 */
mbed_official 573:ad23fe03a082 1286 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 1287 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1288 /**
mbed_official 573:ad23fe03a082 1289 * @}
mbed_official 573:ad23fe03a082 1290 */
mbed_official 573:ad23fe03a082 1291
mbed_official 573:ad23fe03a082 1292 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
mbed_official 573:ad23fe03a082 1293 * @{
mbed_official 573:ad23fe03a082 1294 */
mbed_official 573:ad23fe03a082 1295 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1296 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
mbed_official 573:ad23fe03a082 1297 /**
mbed_official 573:ad23fe03a082 1298 * @}
mbed_official 573:ad23fe03a082 1299 */
mbed_official 573:ad23fe03a082 1300
mbed_official 573:ad23fe03a082 1301 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
mbed_official 573:ad23fe03a082 1302 * @{
mbed_official 573:ad23fe03a082 1303 */
mbed_official 573:ad23fe03a082 1304 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
mbed_official 573:ad23fe03a082 1305 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1306 /**
mbed_official 573:ad23fe03a082 1307 * @}
mbed_official 573:ad23fe03a082 1308 */
mbed_official 573:ad23fe03a082 1309
mbed_official 573:ad23fe03a082 1310 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
mbed_official 573:ad23fe03a082 1311 * @{
mbed_official 573:ad23fe03a082 1312 */
mbed_official 573:ad23fe03a082 1313 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
mbed_official 573:ad23fe03a082 1314 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
mbed_official 573:ad23fe03a082 1315 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
mbed_official 573:ad23fe03a082 1316 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
mbed_official 573:ad23fe03a082 1317 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
mbed_official 573:ad23fe03a082 1318 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
mbed_official 573:ad23fe03a082 1319 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
mbed_official 573:ad23fe03a082 1320 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
mbed_official 573:ad23fe03a082 1321 /**
mbed_official 573:ad23fe03a082 1322 * @}
mbed_official 573:ad23fe03a082 1323 */
mbed_official 573:ad23fe03a082 1324
mbed_official 573:ad23fe03a082 1325 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
mbed_official 573:ad23fe03a082 1326 * @{
mbed_official 573:ad23fe03a082 1327 */
mbed_official 573:ad23fe03a082 1328 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 1329 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1330 /**
mbed_official 573:ad23fe03a082 1331 * @}
mbed_official 573:ad23fe03a082 1332 */
mbed_official 573:ad23fe03a082 1333
mbed_official 573:ad23fe03a082 1334 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
mbed_official 573:ad23fe03a082 1335 * @{
mbed_official 573:ad23fe03a082 1336 */
mbed_official 573:ad23fe03a082 1337 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
mbed_official 573:ad23fe03a082 1338 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1339 /**
mbed_official 573:ad23fe03a082 1340 * @}
mbed_official 573:ad23fe03a082 1341 */
mbed_official 573:ad23fe03a082 1342
mbed_official 573:ad23fe03a082 1343 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
mbed_official 573:ad23fe03a082 1344 * @{
mbed_official 573:ad23fe03a082 1345 */
mbed_official 573:ad23fe03a082 1346 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
mbed_official 573:ad23fe03a082 1347 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
mbed_official 573:ad23fe03a082 1348 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
mbed_official 573:ad23fe03a082 1349 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
mbed_official 573:ad23fe03a082 1350 /**
mbed_official 573:ad23fe03a082 1351 * @}
mbed_official 573:ad23fe03a082 1352 */
mbed_official 573:ad23fe03a082 1353
mbed_official 573:ad23fe03a082 1354 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
mbed_official 573:ad23fe03a082 1355 * @{
mbed_official 573:ad23fe03a082 1356 */
mbed_official 573:ad23fe03a082 1357 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
mbed_official 573:ad23fe03a082 1358 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1359 /**
mbed_official 573:ad23fe03a082 1360 * @}
mbed_official 573:ad23fe03a082 1361 */
mbed_official 573:ad23fe03a082 1362
mbed_official 573:ad23fe03a082 1363 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
mbed_official 573:ad23fe03a082 1364 * @{
mbed_official 573:ad23fe03a082 1365 */
mbed_official 573:ad23fe03a082 1366 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
mbed_official 573:ad23fe03a082 1367 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1368 /**
mbed_official 573:ad23fe03a082 1369 * @}
mbed_official 573:ad23fe03a082 1370 */
mbed_official 573:ad23fe03a082 1371
mbed_official 573:ad23fe03a082 1372 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
mbed_official 573:ad23fe03a082 1373 * @{
mbed_official 573:ad23fe03a082 1374 */
mbed_official 573:ad23fe03a082 1375 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
mbed_official 573:ad23fe03a082 1376 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1377 /**
mbed_official 573:ad23fe03a082 1378 * @}
mbed_official 573:ad23fe03a082 1379 */
mbed_official 573:ad23fe03a082 1380
mbed_official 573:ad23fe03a082 1381 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
mbed_official 573:ad23fe03a082 1382 * @{
mbed_official 573:ad23fe03a082 1383 */
mbed_official 573:ad23fe03a082 1384 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
mbed_official 573:ad23fe03a082 1385 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
mbed_official 573:ad23fe03a082 1386 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 573:ad23fe03a082 1387 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 573:ad23fe03a082 1388 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 573:ad23fe03a082 1389 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 573:ad23fe03a082 1390 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 573:ad23fe03a082 1391 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 573:ad23fe03a082 1392 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 573:ad23fe03a082 1393 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 573:ad23fe03a082 1394 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
mbed_official 573:ad23fe03a082 1395 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
mbed_official 573:ad23fe03a082 1396 /**
mbed_official 573:ad23fe03a082 1397 * @}
mbed_official 573:ad23fe03a082 1398 */
mbed_official 573:ad23fe03a082 1399
mbed_official 573:ad23fe03a082 1400 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
mbed_official 573:ad23fe03a082 1401 * @{
mbed_official 573:ad23fe03a082 1402 */
mbed_official 573:ad23fe03a082 1403 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
mbed_official 573:ad23fe03a082 1404 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
mbed_official 573:ad23fe03a082 1405 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 573:ad23fe03a082 1406 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 573:ad23fe03a082 1407 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 573:ad23fe03a082 1408 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 573:ad23fe03a082 1409 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 573:ad23fe03a082 1410 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 573:ad23fe03a082 1411 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 573:ad23fe03a082 1412 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 573:ad23fe03a082 1413 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
mbed_official 573:ad23fe03a082 1414 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
mbed_official 573:ad23fe03a082 1415 /**
mbed_official 573:ad23fe03a082 1416 * @}
mbed_official 573:ad23fe03a082 1417 */
mbed_official 573:ad23fe03a082 1418
mbed_official 573:ad23fe03a082 1419 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
mbed_official 573:ad23fe03a082 1420 * @{
mbed_official 573:ad23fe03a082 1421 */
mbed_official 573:ad23fe03a082 1422 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
mbed_official 573:ad23fe03a082 1423 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1424 /**
mbed_official 573:ad23fe03a082 1425 * @}
mbed_official 573:ad23fe03a082 1426 */
mbed_official 573:ad23fe03a082 1427
mbed_official 573:ad23fe03a082 1428 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
mbed_official 573:ad23fe03a082 1429 * @{
mbed_official 573:ad23fe03a082 1430 */
mbed_official 573:ad23fe03a082 1431 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
mbed_official 573:ad23fe03a082 1432 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
mbed_official 573:ad23fe03a082 1433 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
mbed_official 573:ad23fe03a082 1434 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
mbed_official 573:ad23fe03a082 1435 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
mbed_official 573:ad23fe03a082 1436 /**
mbed_official 573:ad23fe03a082 1437 * @}
mbed_official 573:ad23fe03a082 1438 */
mbed_official 573:ad23fe03a082 1439
mbed_official 573:ad23fe03a082 1440 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
mbed_official 573:ad23fe03a082 1441 * @{
mbed_official 573:ad23fe03a082 1442 */
mbed_official 573:ad23fe03a082 1443 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
mbed_official 573:ad23fe03a082 1444 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
mbed_official 573:ad23fe03a082 1445 /**
mbed_official 573:ad23fe03a082 1446 * @}
mbed_official 573:ad23fe03a082 1447 */
mbed_official 573:ad23fe03a082 1448
mbed_official 573:ad23fe03a082 1449 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
mbed_official 573:ad23fe03a082 1450 * @{
mbed_official 573:ad23fe03a082 1451 */
mbed_official 573:ad23fe03a082 1452 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
mbed_official 573:ad23fe03a082 1453 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
mbed_official 573:ad23fe03a082 1454 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
mbed_official 573:ad23fe03a082 1455 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
mbed_official 573:ad23fe03a082 1456 /**
mbed_official 573:ad23fe03a082 1457 * @}
mbed_official 573:ad23fe03a082 1458 */
mbed_official 573:ad23fe03a082 1459
mbed_official 573:ad23fe03a082 1460 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
mbed_official 573:ad23fe03a082 1461 * @{
mbed_official 573:ad23fe03a082 1462 */
mbed_official 573:ad23fe03a082 1463 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
mbed_official 573:ad23fe03a082 1464 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
mbed_official 573:ad23fe03a082 1465 /**
mbed_official 573:ad23fe03a082 1466 * @}
mbed_official 573:ad23fe03a082 1467 */
mbed_official 573:ad23fe03a082 1468
mbed_official 573:ad23fe03a082 1469 /** @defgroup ETH_PMT_Flags ETH PMT Flags
mbed_official 573:ad23fe03a082 1470 * @{
mbed_official 573:ad23fe03a082 1471 */
mbed_official 573:ad23fe03a082 1472 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
mbed_official 573:ad23fe03a082 1473 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
mbed_official 573:ad23fe03a082 1474 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
mbed_official 573:ad23fe03a082 1475 /**
mbed_official 573:ad23fe03a082 1476 * @}
mbed_official 573:ad23fe03a082 1477 */
mbed_official 573:ad23fe03a082 1478
mbed_official 573:ad23fe03a082 1479 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
mbed_official 573:ad23fe03a082 1480 * @{
mbed_official 573:ad23fe03a082 1481 */
mbed_official 573:ad23fe03a082 1482 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 1483 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 1484 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 1485 /**
mbed_official 573:ad23fe03a082 1486 * @}
mbed_official 573:ad23fe03a082 1487 */
mbed_official 573:ad23fe03a082 1488
mbed_official 573:ad23fe03a082 1489 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
mbed_official 573:ad23fe03a082 1490 * @{
mbed_official 573:ad23fe03a082 1491 */
mbed_official 573:ad23fe03a082 1492 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 1493 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 1494 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
mbed_official 573:ad23fe03a082 1495 /**
mbed_official 573:ad23fe03a082 1496 * @}
mbed_official 573:ad23fe03a082 1497 */
mbed_official 573:ad23fe03a082 1498
mbed_official 573:ad23fe03a082 1499 /** @defgroup ETH_MAC_Flags ETH MAC Flags
mbed_official 573:ad23fe03a082 1500 * @{
mbed_official 573:ad23fe03a082 1501 */
mbed_official 573:ad23fe03a082 1502 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
mbed_official 573:ad23fe03a082 1503 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
mbed_official 573:ad23fe03a082 1504 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
mbed_official 573:ad23fe03a082 1505 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
mbed_official 573:ad23fe03a082 1506 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
mbed_official 573:ad23fe03a082 1507 /**
mbed_official 573:ad23fe03a082 1508 * @}
mbed_official 573:ad23fe03a082 1509 */
mbed_official 573:ad23fe03a082 1510
mbed_official 573:ad23fe03a082 1511 /** @defgroup ETH_DMA_Flags ETH DMA Flags
mbed_official 573:ad23fe03a082 1512 * @{
mbed_official 573:ad23fe03a082 1513 */
mbed_official 573:ad23fe03a082 1514 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
mbed_official 573:ad23fe03a082 1515 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
mbed_official 573:ad23fe03a082 1516 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
mbed_official 573:ad23fe03a082 1517 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
mbed_official 573:ad23fe03a082 1518 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */
mbed_official 573:ad23fe03a082 1519 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
mbed_official 573:ad23fe03a082 1520 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
mbed_official 573:ad23fe03a082 1521 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
mbed_official 573:ad23fe03a082 1522 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
mbed_official 573:ad23fe03a082 1523 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
mbed_official 573:ad23fe03a082 1524 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
mbed_official 573:ad23fe03a082 1525 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
mbed_official 573:ad23fe03a082 1526 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
mbed_official 573:ad23fe03a082 1527 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
mbed_official 573:ad23fe03a082 1528 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
mbed_official 573:ad23fe03a082 1529 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
mbed_official 573:ad23fe03a082 1530 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
mbed_official 573:ad23fe03a082 1531 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
mbed_official 573:ad23fe03a082 1532 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
mbed_official 573:ad23fe03a082 1533 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
mbed_official 573:ad23fe03a082 1534 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
mbed_official 573:ad23fe03a082 1535 /**
mbed_official 573:ad23fe03a082 1536 * @}
mbed_official 573:ad23fe03a082 1537 */
mbed_official 573:ad23fe03a082 1538
mbed_official 573:ad23fe03a082 1539 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
mbed_official 573:ad23fe03a082 1540 * @{
mbed_official 573:ad23fe03a082 1541 */
mbed_official 573:ad23fe03a082 1542 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
mbed_official 573:ad23fe03a082 1543 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
mbed_official 573:ad23fe03a082 1544 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
mbed_official 573:ad23fe03a082 1545 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
mbed_official 573:ad23fe03a082 1546 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
mbed_official 573:ad23fe03a082 1547 /**
mbed_official 573:ad23fe03a082 1548 * @}
mbed_official 573:ad23fe03a082 1549 */
mbed_official 573:ad23fe03a082 1550
mbed_official 573:ad23fe03a082 1551 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
mbed_official 573:ad23fe03a082 1552 * @{
mbed_official 573:ad23fe03a082 1553 */
mbed_official 573:ad23fe03a082 1554 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
mbed_official 573:ad23fe03a082 1555 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
mbed_official 573:ad23fe03a082 1556 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
mbed_official 573:ad23fe03a082 1557 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
mbed_official 573:ad23fe03a082 1558 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
mbed_official 573:ad23fe03a082 1559 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
mbed_official 573:ad23fe03a082 1560 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
mbed_official 573:ad23fe03a082 1561 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
mbed_official 573:ad23fe03a082 1562 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
mbed_official 573:ad23fe03a082 1563 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
mbed_official 573:ad23fe03a082 1564 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
mbed_official 573:ad23fe03a082 1565 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
mbed_official 573:ad23fe03a082 1566 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
mbed_official 573:ad23fe03a082 1567 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
mbed_official 573:ad23fe03a082 1568 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
mbed_official 573:ad23fe03a082 1569 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
mbed_official 573:ad23fe03a082 1570 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
mbed_official 573:ad23fe03a082 1571 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
mbed_official 573:ad23fe03a082 1572 /**
mbed_official 573:ad23fe03a082 1573 * @}
mbed_official 573:ad23fe03a082 1574 */
mbed_official 573:ad23fe03a082 1575
mbed_official 573:ad23fe03a082 1576 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
mbed_official 573:ad23fe03a082 1577 * @{
mbed_official 573:ad23fe03a082 1578 */
mbed_official 573:ad23fe03a082 1579 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
mbed_official 573:ad23fe03a082 1580 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
mbed_official 573:ad23fe03a082 1581 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
mbed_official 573:ad23fe03a082 1582 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
mbed_official 573:ad23fe03a082 1583 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
mbed_official 573:ad23fe03a082 1584 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
mbed_official 573:ad23fe03a082 1585
mbed_official 573:ad23fe03a082 1586 /**
mbed_official 573:ad23fe03a082 1587 * @}
mbed_official 573:ad23fe03a082 1588 */
mbed_official 573:ad23fe03a082 1589
mbed_official 573:ad23fe03a082 1590
mbed_official 573:ad23fe03a082 1591 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
mbed_official 573:ad23fe03a082 1592 * @{
mbed_official 573:ad23fe03a082 1593 */
mbed_official 573:ad23fe03a082 1594 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
mbed_official 573:ad23fe03a082 1595 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
mbed_official 573:ad23fe03a082 1596 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
mbed_official 573:ad23fe03a082 1597 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
mbed_official 573:ad23fe03a082 1598 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
mbed_official 573:ad23fe03a082 1599 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
mbed_official 573:ad23fe03a082 1600
mbed_official 573:ad23fe03a082 1601 /**
mbed_official 573:ad23fe03a082 1602 * @}
mbed_official 573:ad23fe03a082 1603 */
mbed_official 573:ad23fe03a082 1604
mbed_official 573:ad23fe03a082 1605 /** @defgroup ETH_DMA_overflow ETH DMA overflow
mbed_official 573:ad23fe03a082 1606 * @{
mbed_official 573:ad23fe03a082 1607 */
mbed_official 573:ad23fe03a082 1608 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
mbed_official 573:ad23fe03a082 1609 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
mbed_official 573:ad23fe03a082 1610 /**
mbed_official 573:ad23fe03a082 1611 * @}
mbed_official 573:ad23fe03a082 1612 */
mbed_official 573:ad23fe03a082 1613
mbed_official 573:ad23fe03a082 1614 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
mbed_official 573:ad23fe03a082 1615 * @{
mbed_official 573:ad23fe03a082 1616 */
mbed_official 573:ad23fe03a082 1617 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
mbed_official 573:ad23fe03a082 1618
mbed_official 573:ad23fe03a082 1619 /**
mbed_official 573:ad23fe03a082 1620 * @}
mbed_official 573:ad23fe03a082 1621 */
mbed_official 573:ad23fe03a082 1622
mbed_official 573:ad23fe03a082 1623 /**
mbed_official 573:ad23fe03a082 1624 * @}
mbed_official 573:ad23fe03a082 1625 */
mbed_official 573:ad23fe03a082 1626
mbed_official 573:ad23fe03a082 1627 /* Exported macro ------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 1628 /** @defgroup ETH_Exported_Macros ETH Exported Macros
mbed_official 573:ad23fe03a082 1629 * @brief macros to handle interrupts and specific clock configurations
mbed_official 573:ad23fe03a082 1630 * @{
mbed_official 573:ad23fe03a082 1631 */
mbed_official 573:ad23fe03a082 1632
mbed_official 573:ad23fe03a082 1633 /** @brief Reset ETH handle state
mbed_official 573:ad23fe03a082 1634 * @param __HANDLE__: specifies the ETH handle.
mbed_official 573:ad23fe03a082 1635 * @retval None
mbed_official 573:ad23fe03a082 1636 */
mbed_official 573:ad23fe03a082 1637 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
mbed_official 573:ad23fe03a082 1638
mbed_official 573:ad23fe03a082 1639 /**
mbed_official 573:ad23fe03a082 1640 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
mbed_official 573:ad23fe03a082 1641 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1642 * @param __FLAG__: specifies the flag of TDES0 to check.
mbed_official 573:ad23fe03a082 1643 * @retval the ETH_DMATxDescFlag (SET or RESET).
mbed_official 573:ad23fe03a082 1644 */
mbed_official 573:ad23fe03a082 1645 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
mbed_official 573:ad23fe03a082 1646
mbed_official 573:ad23fe03a082 1647 /**
mbed_official 573:ad23fe03a082 1648 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
mbed_official 573:ad23fe03a082 1649 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1650 * @param __FLAG__: specifies the flag of RDES0 to check.
mbed_official 573:ad23fe03a082 1651 * @retval the ETH_DMATxDescFlag (SET or RESET).
mbed_official 573:ad23fe03a082 1652 */
mbed_official 573:ad23fe03a082 1653 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
mbed_official 573:ad23fe03a082 1654
mbed_official 573:ad23fe03a082 1655 /**
mbed_official 573:ad23fe03a082 1656 * @brief Enables the specified DMA Rx Desc receive interrupt.
mbed_official 573:ad23fe03a082 1657 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1658 * @retval None
mbed_official 573:ad23fe03a082 1659 */
mbed_official 573:ad23fe03a082 1660 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
mbed_official 573:ad23fe03a082 1661
mbed_official 573:ad23fe03a082 1662 /**
mbed_official 573:ad23fe03a082 1663 * @brief Disables the specified DMA Rx Desc receive interrupt.
mbed_official 573:ad23fe03a082 1664 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1665 * @retval None
mbed_official 573:ad23fe03a082 1666 */
mbed_official 573:ad23fe03a082 1667 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
mbed_official 573:ad23fe03a082 1668
mbed_official 573:ad23fe03a082 1669 /**
mbed_official 573:ad23fe03a082 1670 * @brief Set the specified DMA Rx Desc Own bit.
mbed_official 573:ad23fe03a082 1671 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1672 * @retval None
mbed_official 573:ad23fe03a082 1673 */
mbed_official 573:ad23fe03a082 1674 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
mbed_official 573:ad23fe03a082 1675
mbed_official 573:ad23fe03a082 1676 /**
mbed_official 573:ad23fe03a082 1677 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
mbed_official 573:ad23fe03a082 1678 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1679 * @retval The Transmit descriptor collision counter value.
mbed_official 573:ad23fe03a082 1680 */
mbed_official 573:ad23fe03a082 1681 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
mbed_official 573:ad23fe03a082 1682
mbed_official 573:ad23fe03a082 1683 /**
mbed_official 573:ad23fe03a082 1684 * @brief Set the specified DMA Tx Desc Own bit.
mbed_official 573:ad23fe03a082 1685 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1686 * @retval None
mbed_official 573:ad23fe03a082 1687 */
mbed_official 573:ad23fe03a082 1688 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
mbed_official 573:ad23fe03a082 1689
mbed_official 573:ad23fe03a082 1690 /**
mbed_official 573:ad23fe03a082 1691 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
mbed_official 573:ad23fe03a082 1692 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1693 * @retval None
mbed_official 573:ad23fe03a082 1694 */
mbed_official 573:ad23fe03a082 1695 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
mbed_official 573:ad23fe03a082 1696
mbed_official 573:ad23fe03a082 1697 /**
mbed_official 573:ad23fe03a082 1698 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
mbed_official 573:ad23fe03a082 1699 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1700 * @retval None
mbed_official 573:ad23fe03a082 1701 */
mbed_official 573:ad23fe03a082 1702 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
mbed_official 573:ad23fe03a082 1703
mbed_official 573:ad23fe03a082 1704 /**
mbed_official 573:ad23fe03a082 1705 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
mbed_official 573:ad23fe03a082 1706 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1707 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
mbed_official 573:ad23fe03a082 1708 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 1709 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
mbed_official 573:ad23fe03a082 1710 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
mbed_official 573:ad23fe03a082 1711 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
mbed_official 573:ad23fe03a082 1712 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
mbed_official 573:ad23fe03a082 1713 * @retval None
mbed_official 573:ad23fe03a082 1714 */
mbed_official 573:ad23fe03a082 1715 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
mbed_official 573:ad23fe03a082 1716
mbed_official 573:ad23fe03a082 1717 /**
mbed_official 573:ad23fe03a082 1718 * @brief Enables the DMA Tx Desc CRC.
mbed_official 573:ad23fe03a082 1719 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1720 * @retval None
mbed_official 573:ad23fe03a082 1721 */
mbed_official 573:ad23fe03a082 1722 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
mbed_official 573:ad23fe03a082 1723
mbed_official 573:ad23fe03a082 1724 /**
mbed_official 573:ad23fe03a082 1725 * @brief Disables the DMA Tx Desc CRC.
mbed_official 573:ad23fe03a082 1726 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1727 * @retval None
mbed_official 573:ad23fe03a082 1728 */
mbed_official 573:ad23fe03a082 1729 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
mbed_official 573:ad23fe03a082 1730
mbed_official 573:ad23fe03a082 1731 /**
mbed_official 573:ad23fe03a082 1732 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
mbed_official 573:ad23fe03a082 1733 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1734 * @retval None
mbed_official 573:ad23fe03a082 1735 */
mbed_official 573:ad23fe03a082 1736 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
mbed_official 573:ad23fe03a082 1737
mbed_official 573:ad23fe03a082 1738 /**
mbed_official 573:ad23fe03a082 1739 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
mbed_official 573:ad23fe03a082 1740 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1741 * @retval None
mbed_official 573:ad23fe03a082 1742 */
mbed_official 573:ad23fe03a082 1743 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
mbed_official 573:ad23fe03a082 1744
mbed_official 573:ad23fe03a082 1745 /**
mbed_official 573:ad23fe03a082 1746 * @brief Enables the specified ETHERNET MAC interrupts.
mbed_official 573:ad23fe03a082 1747 * @param __HANDLE__ : ETH Handle
mbed_official 573:ad23fe03a082 1748 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
mbed_official 573:ad23fe03a082 1749 * enabled or disabled.
mbed_official 573:ad23fe03a082 1750 * This parameter can be any combination of the following values:
mbed_official 573:ad23fe03a082 1751 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
mbed_official 573:ad23fe03a082 1752 * @arg ETH_MAC_IT_PMT : PMT interrupt
mbed_official 573:ad23fe03a082 1753 * @retval None
mbed_official 573:ad23fe03a082 1754 */
mbed_official 573:ad23fe03a082 1755 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
mbed_official 573:ad23fe03a082 1756
mbed_official 573:ad23fe03a082 1757 /**
mbed_official 573:ad23fe03a082 1758 * @brief Disables the specified ETHERNET MAC interrupts.
mbed_official 573:ad23fe03a082 1759 * @param __HANDLE__ : ETH Handle
mbed_official 573:ad23fe03a082 1760 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
mbed_official 573:ad23fe03a082 1761 * enabled or disabled.
mbed_official 573:ad23fe03a082 1762 * This parameter can be any combination of the following values:
mbed_official 573:ad23fe03a082 1763 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
mbed_official 573:ad23fe03a082 1764 * @arg ETH_MAC_IT_PMT : PMT interrupt
mbed_official 573:ad23fe03a082 1765 * @retval None
mbed_official 573:ad23fe03a082 1766 */
mbed_official 573:ad23fe03a082 1767 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
mbed_official 573:ad23fe03a082 1768
mbed_official 573:ad23fe03a082 1769 /**
mbed_official 573:ad23fe03a082 1770 * @brief Initiate a Pause Control Frame (Full-duplex only).
mbed_official 573:ad23fe03a082 1771 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1772 * @retval None
mbed_official 573:ad23fe03a082 1773 */
mbed_official 573:ad23fe03a082 1774 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
mbed_official 573:ad23fe03a082 1775
mbed_official 573:ad23fe03a082 1776 /**
mbed_official 573:ad23fe03a082 1777 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
mbed_official 573:ad23fe03a082 1778 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1779 * @retval The new state of flow control busy status bit (SET or RESET).
mbed_official 573:ad23fe03a082 1780 */
mbed_official 573:ad23fe03a082 1781 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
mbed_official 573:ad23fe03a082 1782
mbed_official 573:ad23fe03a082 1783 /**
mbed_official 573:ad23fe03a082 1784 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
mbed_official 573:ad23fe03a082 1785 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1786 * @retval None
mbed_official 573:ad23fe03a082 1787 */
mbed_official 573:ad23fe03a082 1788 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
mbed_official 573:ad23fe03a082 1789
mbed_official 573:ad23fe03a082 1790 /**
mbed_official 573:ad23fe03a082 1791 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
mbed_official 573:ad23fe03a082 1792 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1793 * @retval None
mbed_official 573:ad23fe03a082 1794 */
mbed_official 573:ad23fe03a082 1795 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
mbed_official 573:ad23fe03a082 1796
mbed_official 573:ad23fe03a082 1797 /**
mbed_official 573:ad23fe03a082 1798 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
mbed_official 573:ad23fe03a082 1799 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1800 * @param __FLAG__: specifies the flag to check.
mbed_official 573:ad23fe03a082 1801 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 1802 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
mbed_official 573:ad23fe03a082 1803 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
mbed_official 573:ad23fe03a082 1804 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
mbed_official 573:ad23fe03a082 1805 * @arg ETH_MAC_FLAG_MMC : MMC flag
mbed_official 573:ad23fe03a082 1806 * @arg ETH_MAC_FLAG_PMT : PMT flag
mbed_official 573:ad23fe03a082 1807 * @retval The state of ETHERNET MAC flag.
mbed_official 573:ad23fe03a082 1808 */
mbed_official 573:ad23fe03a082 1809 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
mbed_official 573:ad23fe03a082 1810
mbed_official 573:ad23fe03a082 1811 /**
mbed_official 573:ad23fe03a082 1812 * @brief Enables the specified ETHERNET DMA interrupts.
mbed_official 573:ad23fe03a082 1813 * @param __HANDLE__ : ETH Handle
mbed_official 573:ad23fe03a082 1814 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
mbed_official 573:ad23fe03a082 1815 * enabled @ref ETH_DMA_Interrupts
mbed_official 573:ad23fe03a082 1816 * @retval None
mbed_official 573:ad23fe03a082 1817 */
mbed_official 573:ad23fe03a082 1818 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
mbed_official 573:ad23fe03a082 1819
mbed_official 573:ad23fe03a082 1820 /**
mbed_official 573:ad23fe03a082 1821 * @brief Disables the specified ETHERNET DMA interrupts.
mbed_official 573:ad23fe03a082 1822 * @param __HANDLE__ : ETH Handle
mbed_official 573:ad23fe03a082 1823 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
mbed_official 573:ad23fe03a082 1824 * disabled. @ref ETH_DMA_Interrupts
mbed_official 573:ad23fe03a082 1825 * @retval None
mbed_official 573:ad23fe03a082 1826 */
mbed_official 573:ad23fe03a082 1827 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
mbed_official 573:ad23fe03a082 1828
mbed_official 573:ad23fe03a082 1829 /**
mbed_official 573:ad23fe03a082 1830 * @brief Clears the ETHERNET DMA IT pending bit.
mbed_official 573:ad23fe03a082 1831 * @param __HANDLE__ : ETH Handle
mbed_official 573:ad23fe03a082 1832 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
mbed_official 573:ad23fe03a082 1833 * @retval None
mbed_official 573:ad23fe03a082 1834 */
mbed_official 573:ad23fe03a082 1835 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
mbed_official 573:ad23fe03a082 1836
mbed_official 573:ad23fe03a082 1837 /**
mbed_official 573:ad23fe03a082 1838 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
mbed_official 573:ad23fe03a082 1839 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1840 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
mbed_official 573:ad23fe03a082 1841 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
mbed_official 573:ad23fe03a082 1842 */
mbed_official 573:ad23fe03a082 1843 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
mbed_official 573:ad23fe03a082 1844
mbed_official 573:ad23fe03a082 1845 /**
mbed_official 573:ad23fe03a082 1846 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
mbed_official 573:ad23fe03a082 1847 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1848 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
mbed_official 573:ad23fe03a082 1849 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
mbed_official 573:ad23fe03a082 1850 */
mbed_official 573:ad23fe03a082 1851 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
mbed_official 573:ad23fe03a082 1852
mbed_official 573:ad23fe03a082 1853 /**
mbed_official 573:ad23fe03a082 1854 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
mbed_official 573:ad23fe03a082 1855 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1856 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
mbed_official 573:ad23fe03a082 1857 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 1858 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
mbed_official 573:ad23fe03a082 1859 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
mbed_official 573:ad23fe03a082 1860 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
mbed_official 573:ad23fe03a082 1861 */
mbed_official 573:ad23fe03a082 1862 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
mbed_official 573:ad23fe03a082 1863
mbed_official 573:ad23fe03a082 1864 /**
mbed_official 573:ad23fe03a082 1865 * @brief Set the DMA Receive status watchdog timer register value
mbed_official 573:ad23fe03a082 1866 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1867 * @param __VALUE__: DMA Receive status watchdog timer register value
mbed_official 573:ad23fe03a082 1868 * @retval None
mbed_official 573:ad23fe03a082 1869 */
mbed_official 573:ad23fe03a082 1870 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
mbed_official 573:ad23fe03a082 1871
mbed_official 573:ad23fe03a082 1872 /**
mbed_official 573:ad23fe03a082 1873 * @brief Enables any unicast packet filtered by the MAC address
mbed_official 573:ad23fe03a082 1874 * recognition to be a wake-up frame.
mbed_official 573:ad23fe03a082 1875 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1876 * @retval None
mbed_official 573:ad23fe03a082 1877 */
mbed_official 573:ad23fe03a082 1878 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
mbed_official 573:ad23fe03a082 1879
mbed_official 573:ad23fe03a082 1880 /**
mbed_official 573:ad23fe03a082 1881 * @brief Disables any unicast packet filtered by the MAC address
mbed_official 573:ad23fe03a082 1882 * recognition to be a wake-up frame.
mbed_official 573:ad23fe03a082 1883 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1884 * @retval None
mbed_official 573:ad23fe03a082 1885 */
mbed_official 573:ad23fe03a082 1886 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
mbed_official 573:ad23fe03a082 1887
mbed_official 573:ad23fe03a082 1888 /**
mbed_official 573:ad23fe03a082 1889 * @brief Enables the MAC Wake-Up Frame Detection.
mbed_official 573:ad23fe03a082 1890 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1891 * @retval None
mbed_official 573:ad23fe03a082 1892 */
mbed_official 573:ad23fe03a082 1893 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
mbed_official 573:ad23fe03a082 1894
mbed_official 573:ad23fe03a082 1895 /**
mbed_official 573:ad23fe03a082 1896 * @brief Disables the MAC Wake-Up Frame Detection.
mbed_official 573:ad23fe03a082 1897 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1898 * @retval None
mbed_official 573:ad23fe03a082 1899 */
mbed_official 573:ad23fe03a082 1900 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
mbed_official 573:ad23fe03a082 1901
mbed_official 573:ad23fe03a082 1902 /**
mbed_official 573:ad23fe03a082 1903 * @brief Enables the MAC Magic Packet Detection.
mbed_official 573:ad23fe03a082 1904 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1905 * @retval None
mbed_official 573:ad23fe03a082 1906 */
mbed_official 573:ad23fe03a082 1907 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
mbed_official 573:ad23fe03a082 1908
mbed_official 573:ad23fe03a082 1909 /**
mbed_official 573:ad23fe03a082 1910 * @brief Disables the MAC Magic Packet Detection.
mbed_official 573:ad23fe03a082 1911 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1912 * @retval None
mbed_official 573:ad23fe03a082 1913 */
mbed_official 573:ad23fe03a082 1914 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
mbed_official 573:ad23fe03a082 1915
mbed_official 573:ad23fe03a082 1916 /**
mbed_official 573:ad23fe03a082 1917 * @brief Enables the MAC Power Down.
mbed_official 573:ad23fe03a082 1918 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1919 * @retval None
mbed_official 573:ad23fe03a082 1920 */
mbed_official 573:ad23fe03a082 1921 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
mbed_official 573:ad23fe03a082 1922
mbed_official 573:ad23fe03a082 1923 /**
mbed_official 573:ad23fe03a082 1924 * @brief Disables the MAC Power Down.
mbed_official 573:ad23fe03a082 1925 * @param __HANDLE__: ETH Handle
mbed_official 573:ad23fe03a082 1926 * @retval None
mbed_official 573:ad23fe03a082 1927 */
mbed_official 573:ad23fe03a082 1928 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
mbed_official 573:ad23fe03a082 1929
mbed_official 573:ad23fe03a082 1930 /**
mbed_official 573:ad23fe03a082 1931 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
mbed_official 573:ad23fe03a082 1932 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1933 * @param __FLAG__: specifies the flag to check.
mbed_official 573:ad23fe03a082 1934 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 1935 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
mbed_official 573:ad23fe03a082 1936 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
mbed_official 573:ad23fe03a082 1937 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
mbed_official 573:ad23fe03a082 1938 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
mbed_official 573:ad23fe03a082 1939 */
mbed_official 573:ad23fe03a082 1940 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
mbed_official 573:ad23fe03a082 1941
mbed_official 573:ad23fe03a082 1942 /**
mbed_official 573:ad23fe03a082 1943 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
mbed_official 573:ad23fe03a082 1944 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1945 * @retval None
mbed_official 573:ad23fe03a082 1946 */
mbed_official 573:ad23fe03a082 1947 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
mbed_official 573:ad23fe03a082 1948
mbed_official 573:ad23fe03a082 1949 /**
mbed_official 573:ad23fe03a082 1950 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
mbed_official 573:ad23fe03a082 1951 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1952 * @retval None
mbed_official 573:ad23fe03a082 1953 */
mbed_official 573:ad23fe03a082 1954 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
mbed_official 573:ad23fe03a082 1955 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
mbed_official 573:ad23fe03a082 1956
mbed_official 573:ad23fe03a082 1957 /**
mbed_official 573:ad23fe03a082 1958 * @brief Enables the MMC Counter Freeze.
mbed_official 573:ad23fe03a082 1959 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1960 * @retval None
mbed_official 573:ad23fe03a082 1961 */
mbed_official 573:ad23fe03a082 1962 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
mbed_official 573:ad23fe03a082 1963
mbed_official 573:ad23fe03a082 1964 /**
mbed_official 573:ad23fe03a082 1965 * @brief Disables the MMC Counter Freeze.
mbed_official 573:ad23fe03a082 1966 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1967 * @retval None
mbed_official 573:ad23fe03a082 1968 */
mbed_official 573:ad23fe03a082 1969 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
mbed_official 573:ad23fe03a082 1970
mbed_official 573:ad23fe03a082 1971 /**
mbed_official 573:ad23fe03a082 1972 * @brief Enables the MMC Reset On Read.
mbed_official 573:ad23fe03a082 1973 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1974 * @retval None
mbed_official 573:ad23fe03a082 1975 */
mbed_official 573:ad23fe03a082 1976 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
mbed_official 573:ad23fe03a082 1977
mbed_official 573:ad23fe03a082 1978 /**
mbed_official 573:ad23fe03a082 1979 * @brief Disables the MMC Reset On Read.
mbed_official 573:ad23fe03a082 1980 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1981 * @retval None
mbed_official 573:ad23fe03a082 1982 */
mbed_official 573:ad23fe03a082 1983 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
mbed_official 573:ad23fe03a082 1984
mbed_official 573:ad23fe03a082 1985 /**
mbed_official 573:ad23fe03a082 1986 * @brief Enables the MMC Counter Stop Rollover.
mbed_official 573:ad23fe03a082 1987 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1988 * @retval None
mbed_official 573:ad23fe03a082 1989 */
mbed_official 573:ad23fe03a082 1990 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
mbed_official 573:ad23fe03a082 1991
mbed_official 573:ad23fe03a082 1992 /**
mbed_official 573:ad23fe03a082 1993 * @brief Disables the MMC Counter Stop Rollover.
mbed_official 573:ad23fe03a082 1994 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 1995 * @retval None
mbed_official 573:ad23fe03a082 1996 */
mbed_official 573:ad23fe03a082 1997 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
mbed_official 573:ad23fe03a082 1998
mbed_official 573:ad23fe03a082 1999 /**
mbed_official 573:ad23fe03a082 2000 * @brief Resets the MMC Counters.
mbed_official 573:ad23fe03a082 2001 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 2002 * @retval None
mbed_official 573:ad23fe03a082 2003 */
mbed_official 573:ad23fe03a082 2004 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
mbed_official 573:ad23fe03a082 2005
mbed_official 573:ad23fe03a082 2006 /**
mbed_official 573:ad23fe03a082 2007 * @brief Enables the specified ETHERNET MMC Rx interrupts.
mbed_official 573:ad23fe03a082 2008 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 2009 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 573:ad23fe03a082 2010 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2011 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2012 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2013 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2014 * @retval None
mbed_official 573:ad23fe03a082 2015 */
mbed_official 573:ad23fe03a082 2016 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
mbed_official 573:ad23fe03a082 2017 /**
mbed_official 573:ad23fe03a082 2018 * @brief Disables the specified ETHERNET MMC Rx interrupts.
mbed_official 573:ad23fe03a082 2019 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 2020 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 573:ad23fe03a082 2021 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2022 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2023 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2024 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2025 * @retval None
mbed_official 573:ad23fe03a082 2026 */
mbed_official 573:ad23fe03a082 2027 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
mbed_official 573:ad23fe03a082 2028 /**
mbed_official 573:ad23fe03a082 2029 * @brief Enables the specified ETHERNET MMC Tx interrupts.
mbed_official 573:ad23fe03a082 2030 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 2031 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 573:ad23fe03a082 2032 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2033 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2034 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2035 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2036 * @retval None
mbed_official 573:ad23fe03a082 2037 */
mbed_official 573:ad23fe03a082 2038 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
mbed_official 573:ad23fe03a082 2039
mbed_official 573:ad23fe03a082 2040 /**
mbed_official 573:ad23fe03a082 2041 * @brief Disables the specified ETHERNET MMC Tx interrupts.
mbed_official 573:ad23fe03a082 2042 * @param __HANDLE__: ETH Handle.
mbed_official 573:ad23fe03a082 2043 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 573:ad23fe03a082 2044 * This parameter can be one of the following values:
mbed_official 573:ad23fe03a082 2045 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2046 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2047 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
mbed_official 573:ad23fe03a082 2048 * @retval None
mbed_official 573:ad23fe03a082 2049 */
mbed_official 573:ad23fe03a082 2050 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
mbed_official 573:ad23fe03a082 2051
mbed_official 573:ad23fe03a082 2052 /**
mbed_official 573:ad23fe03a082 2053 * @brief Enables the ETH External interrupt line.
mbed_official 573:ad23fe03a082 2054 * @retval None
mbed_official 573:ad23fe03a082 2055 */
mbed_official 573:ad23fe03a082 2056 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
mbed_official 573:ad23fe03a082 2057
mbed_official 573:ad23fe03a082 2058 /**
mbed_official 573:ad23fe03a082 2059 * @brief Disables the ETH External interrupt line.
mbed_official 573:ad23fe03a082 2060 * @retval None
mbed_official 573:ad23fe03a082 2061 */
mbed_official 573:ad23fe03a082 2062 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 573:ad23fe03a082 2063
mbed_official 573:ad23fe03a082 2064 /**
mbed_official 573:ad23fe03a082 2065 * @brief Enable event on ETH External event line.
mbed_official 573:ad23fe03a082 2066 * @retval None.
mbed_official 573:ad23fe03a082 2067 */
mbed_official 573:ad23fe03a082 2068 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
mbed_official 573:ad23fe03a082 2069
mbed_official 573:ad23fe03a082 2070 /**
mbed_official 573:ad23fe03a082 2071 * @brief Disable event on ETH External event line
mbed_official 573:ad23fe03a082 2072 * @retval None.
mbed_official 573:ad23fe03a082 2073 */
mbed_official 573:ad23fe03a082 2074 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 573:ad23fe03a082 2075
mbed_official 573:ad23fe03a082 2076 /**
mbed_official 573:ad23fe03a082 2077 * @brief Get flag of the ETH External interrupt line.
mbed_official 573:ad23fe03a082 2078 * @retval None
mbed_official 573:ad23fe03a082 2079 */
mbed_official 573:ad23fe03a082 2080 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
mbed_official 573:ad23fe03a082 2081
mbed_official 573:ad23fe03a082 2082 /**
mbed_official 573:ad23fe03a082 2083 * @brief Clear flag of the ETH External interrupt line.
mbed_official 573:ad23fe03a082 2084 * @retval None
mbed_official 573:ad23fe03a082 2085 */
mbed_official 573:ad23fe03a082 2086 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
mbed_official 573:ad23fe03a082 2087
mbed_official 573:ad23fe03a082 2088 /**
mbed_official 573:ad23fe03a082 2089 * @brief Enables rising edge trigger to the ETH External interrupt line.
mbed_official 573:ad23fe03a082 2090 * @retval None
mbed_official 573:ad23fe03a082 2091 */
mbed_official 573:ad23fe03a082 2092 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
mbed_official 573:ad23fe03a082 2093
mbed_official 573:ad23fe03a082 2094 /**
mbed_official 573:ad23fe03a082 2095 * @brief Disables the rising edge trigger to the ETH External interrupt line.
mbed_official 573:ad23fe03a082 2096 * @retval None
mbed_official 573:ad23fe03a082 2097 */
mbed_official 573:ad23fe03a082 2098 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 573:ad23fe03a082 2099
mbed_official 573:ad23fe03a082 2100 /**
mbed_official 573:ad23fe03a082 2101 * @brief Enables falling edge trigger to the ETH External interrupt line.
mbed_official 573:ad23fe03a082 2102 * @retval None
mbed_official 573:ad23fe03a082 2103 */
mbed_official 573:ad23fe03a082 2104 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
mbed_official 573:ad23fe03a082 2105
mbed_official 573:ad23fe03a082 2106 /**
mbed_official 573:ad23fe03a082 2107 * @brief Disables falling edge trigger to the ETH External interrupt line.
mbed_official 573:ad23fe03a082 2108 * @retval None
mbed_official 573:ad23fe03a082 2109 */
mbed_official 573:ad23fe03a082 2110 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 573:ad23fe03a082 2111
mbed_official 573:ad23fe03a082 2112 /**
mbed_official 573:ad23fe03a082 2113 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
mbed_official 573:ad23fe03a082 2114 * @retval None
mbed_official 573:ad23fe03a082 2115 */
mbed_official 573:ad23fe03a082 2116 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
mbed_official 573:ad23fe03a082 2117 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
mbed_official 573:ad23fe03a082 2118
mbed_official 573:ad23fe03a082 2119 /**
mbed_official 573:ad23fe03a082 2120 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
mbed_official 573:ad23fe03a082 2121 * @retval None
mbed_official 573:ad23fe03a082 2122 */
mbed_official 573:ad23fe03a082 2123 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
mbed_official 573:ad23fe03a082 2124 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 573:ad23fe03a082 2125
mbed_official 573:ad23fe03a082 2126 /**
mbed_official 573:ad23fe03a082 2127 * @brief Generate a Software interrupt on selected EXTI line.
mbed_official 573:ad23fe03a082 2128 * @retval None.
mbed_official 573:ad23fe03a082 2129 */
mbed_official 573:ad23fe03a082 2130 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
mbed_official 573:ad23fe03a082 2131
mbed_official 573:ad23fe03a082 2132 /**
mbed_official 573:ad23fe03a082 2133 * @}
mbed_official 573:ad23fe03a082 2134 */
mbed_official 573:ad23fe03a082 2135 /* Exported functions --------------------------------------------------------*/
mbed_official 573:ad23fe03a082 2136
mbed_official 573:ad23fe03a082 2137 /** @addtogroup ETH_Exported_Functions
mbed_official 573:ad23fe03a082 2138 * @{
mbed_official 573:ad23fe03a082 2139 */
mbed_official 573:ad23fe03a082 2140
mbed_official 573:ad23fe03a082 2141 /* Initialization and de-initialization functions ****************************/
mbed_official 573:ad23fe03a082 2142
mbed_official 573:ad23fe03a082 2143 /** @addtogroup ETH_Exported_Functions_Group1
mbed_official 573:ad23fe03a082 2144 * @{
mbed_official 573:ad23fe03a082 2145 */
mbed_official 573:ad23fe03a082 2146 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2147 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2148 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2149 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2150 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
mbed_official 573:ad23fe03a082 2151 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
mbed_official 573:ad23fe03a082 2152
mbed_official 573:ad23fe03a082 2153 /**
mbed_official 573:ad23fe03a082 2154 * @}
mbed_official 573:ad23fe03a082 2155 */
mbed_official 573:ad23fe03a082 2156 /* IO operation functions ****************************************************/
mbed_official 573:ad23fe03a082 2157
mbed_official 573:ad23fe03a082 2158 /** @addtogroup ETH_Exported_Functions_Group2
mbed_official 573:ad23fe03a082 2159 * @{
mbed_official 573:ad23fe03a082 2160 */
mbed_official 573:ad23fe03a082 2161 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
mbed_official 573:ad23fe03a082 2162 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2163 /* Communication with PHY functions*/
mbed_official 573:ad23fe03a082 2164 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
mbed_official 573:ad23fe03a082 2165 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
mbed_official 573:ad23fe03a082 2166 /* Non-Blocking mode: Interrupt */
mbed_official 573:ad23fe03a082 2167 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2168 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2169 /* Callback in non blocking modes (Interrupt) */
mbed_official 573:ad23fe03a082 2170 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2171 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2172 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2173 /**
mbed_official 573:ad23fe03a082 2174 * @}
mbed_official 573:ad23fe03a082 2175 */
mbed_official 573:ad23fe03a082 2176
mbed_official 573:ad23fe03a082 2177 /* Peripheral Control functions **********************************************/
mbed_official 573:ad23fe03a082 2178
mbed_official 573:ad23fe03a082 2179 /** @addtogroup ETH_Exported_Functions_Group3
mbed_official 573:ad23fe03a082 2180 * @{
mbed_official 573:ad23fe03a082 2181 */
mbed_official 573:ad23fe03a082 2182
mbed_official 573:ad23fe03a082 2183 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2184 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2185 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
mbed_official 573:ad23fe03a082 2186 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
mbed_official 573:ad23fe03a082 2187 /**
mbed_official 573:ad23fe03a082 2188 * @}
mbed_official 573:ad23fe03a082 2189 */
mbed_official 573:ad23fe03a082 2190
mbed_official 573:ad23fe03a082 2191 /* Peripheral State functions ************************************************/
mbed_official 573:ad23fe03a082 2192
mbed_official 573:ad23fe03a082 2193 /** @addtogroup ETH_Exported_Functions_Group4
mbed_official 573:ad23fe03a082 2194 * @{
mbed_official 573:ad23fe03a082 2195 */
mbed_official 573:ad23fe03a082 2196 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
mbed_official 573:ad23fe03a082 2197 /**
mbed_official 573:ad23fe03a082 2198 * @}
mbed_official 573:ad23fe03a082 2199 */
mbed_official 573:ad23fe03a082 2200
mbed_official 573:ad23fe03a082 2201 /**
mbed_official 573:ad23fe03a082 2202 * @}
mbed_official 573:ad23fe03a082 2203 */
mbed_official 573:ad23fe03a082 2204
mbed_official 573:ad23fe03a082 2205 /**
mbed_official 573:ad23fe03a082 2206 * @}
mbed_official 573:ad23fe03a082 2207 */
mbed_official 573:ad23fe03a082 2208
mbed_official 573:ad23fe03a082 2209 /**
mbed_official 573:ad23fe03a082 2210 * @}
mbed_official 573:ad23fe03a082 2211 */
mbed_official 573:ad23fe03a082 2212 #ifdef __cplusplus
mbed_official 573:ad23fe03a082 2213 }
mbed_official 573:ad23fe03a082 2214 #endif
mbed_official 573:ad23fe03a082 2215
mbed_official 573:ad23fe03a082 2216 #endif /* __STM32F7xx_HAL_ETH_H */
mbed_official 573:ad23fe03a082 2217
mbed_official 573:ad23fe03a082 2218
mbed_official 573:ad23fe03a082 2219
mbed_official 573:ad23fe03a082 2220 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/